Re: FYI: Merge in progress...

Richard Smith  writes:
> I've been reading this new v2 stuff with some interest.  I may be able to finde
>
> time to move the 440bx stuff over into v2.  We've hired a big gun PCI guru to
> help find our problems that have been keeping me from getting video to work.
>
> While he's working on that and I'm playing gopher boy, I may be able to scratch
> in some v2 conversion work.  What v2 boards have a working SPD implementation?

I think everything except the epia. I wish I could point you at a simple port.
> Whats all this new stuff mean for those of us without these fancy new wizbang
> chipsets and only 1 pci bus?

Possibly an extra nesting level in Config.lb.  If you have a PCI slot
you can still have multiple busses.

Hmm. I suspect your configuration would look something like:

Except that some of the unused parts don't compile out it really
should be fairly simple.

chip northbridge/intel/440bx 
        device pci_domain 0 on 
                device pci 0.0 on end  # memory controller
                device pci 0.1 on end  # PCI-PCI bridge?
                chip southbridge/intel/piix4e
                        device pci 12.0 on end # ISA bridge
                        device pci 12.1 on end # IDE controller
                        device pci 12.2 on end # USB host controller
                        device pci 12.3 on end # Power management registers
                end
        end
        device apic_cluster 0 on
                chip cpu/intel/slot_2
                     device apic 0 on end
                end
        end
end

Eric