Stefan Reinauer (stefan.reinauer@coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2757
-gerrit
commit ac80aacaeced2eaa0fac2077facb091600508840 Author: Aaron Durbin adurbin@chromium.org Date: Fri Feb 8 22:18:04 2013 -0600
haswell: add romstage_after_car() function
There are changes coming to perform more complex tasks after cache-as-ram has been torn down but before ramstage is loaded. Therefore, add the romstage_after_car() function to call after cache-as-ram is torn down. Its responsibility is for loading the ramstage and any other complex tasks. For example, the saving of OS-controlled memory in the resume path has now been moved into C instead of assembly.
Change-Id: Ie0c229cf83a9271c8995b31c534c8e5a696b164e Signed-off-by: Aaron Durbin adurbin@chromium.org --- src/cpu/intel/haswell/cache_as_ram.inc | 30 +----------------------------- src/cpu/intel/haswell/haswell.h | 3 +++ src/cpu/intel/haswell/romstage.c | 21 +++++++++++++++++++++ 3 files changed, 25 insertions(+), 29 deletions(-)
diff --git a/src/cpu/intel/haswell/cache_as_ram.inc b/src/cpu/intel/haswell/cache_as_ram.inc index 5fb5712..8601f46 100644 --- a/src/cpu/intel/haswell/cache_as_ram.inc +++ b/src/cpu/intel/haswell/cache_as_ram.inc @@ -305,38 +305,10 @@ before_romstage:
post_code(0x3c)
-#if CONFIG_HAVE_ACPI_RESUME - movl CBMEM_BOOT_MODE, %eax - cmpl $0x2, %eax // Resume? - jne __acpi_resume_backup_done - - /* copy 1MB - 64K to high tables ram_base to prevent memory corruption - * through stage 2. We could keep stuff like stack and heap in high - * tables memory completely, but that's a wonderful clean up task for - * another day. - */ - cld - movl $CONFIG_RAMBASE, %esi - movl CBMEM_RESUME_BACKUP, %edi - movl $HIGH_MEMORY_SAVE / 4, %ecx - rep movsl - -__acpi_resume_backup_done: -#endif - - post_code(0x3d) - - /* Clear boot_complete flag. */ - xorl %ebp, %ebp __main: post_code(POST_PREPARE_RAMSTAGE) cld /* Clear direction flag. */ - - movl %ebp, %esi - - movl %esp, %ebp - pushl %esi - call copy_and_run + call romstage_after_car
.Lhlt: post_code(POST_DEAD_CODE) diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 7a55ef7..733ddd3 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -129,6 +129,9 @@ void romstage_common(const struct romstage_params *params); * ... */ void * __attribute__((regparm(0))) romstage_main(unsigned long bist); +/* romstage_after_car() is the C function called after cache-as-ram has + * been torn down. It is responsible for loading the ramstage. */ +void romstage_after_car(void); #endif
#ifdef __SMM__ diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 3ce04e2..d62377e 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -18,6 +18,7 @@ */
#include <stdint.h> +#include <string.h> #include <cbmem.h> #include <console/console.h> #include <arch/cpu.h> @@ -28,6 +29,7 @@ #include <lib.h> #include <timestamp.h> #include <arch/io.h> +#include <arch/stages.h> #include <arch/romcc_io.h> #include <device/pci_def.h> #include <cpu/x86/lapic.h> @@ -272,3 +274,22 @@ void romstage_common(const struct romstage_params *params) timestamp_add_now(TS_END_ROMSTAGE); #endif } + +static inline void prepare_for_resume(void) +{ +#if CONFIG_HAVE_ACPI_RESUME + /* Back up the OS-controlled memory where ramstage will be loaded. */ + if (*(u32 *)CBMEM_BOOT_MODE == 2) { + void *src = (void *)CONFIG_RAMBASE; + void *dest = *(void **)CBMEM_RESUME_BACKUP; + memcpy(dest, src, HIGH_MEMORY_SAVE); + } +#endif +} + +void romstage_after_car(void) +{ + prepare_for_resume(); + /* Load the ramstage. */ + copy_and_run(0); +}