Idwer Vollering (vidwer@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/413
-gerrit
commit e544fdc1961b886af95a06a8d17396057671df4b Author: Idwer Vollering vidwer@gmail.com Date: Sat Nov 5 19:34:11 2011 +0100
Refactor src/southbridge/intel/i82801ex/smbus.h
Change-Id: I72f6bf68f1577f41565c96cb4c389609cde55b01 Signed-off-by: Idwer Vollering vidwer@gmail.com --- src/southbridge/intel/i82801ex/early_smbus.c | 4 +--- src/southbridge/intel/i82801ex/smbus.h | 4 ++++ 2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/src/southbridge/intel/i82801ex/early_smbus.c b/src/southbridge/intel/i82801ex/early_smbus.c index cdf1f62..618bec7 100644 --- a/src/southbridge/intel/i82801ex/early_smbus.c +++ b/src/southbridge/intel/i82801ex/early_smbus.c @@ -1,7 +1,5 @@ #include "smbus.h"
-#define SMBUS_IO_BASE 0x0f00 - static void enable_smbus(void) { device_t dev = PCI_DEV(0x0, 0x1f, 0x3); @@ -9,7 +7,7 @@ static void enable_smbus(void) print_spew("SMBus controller enabled\n");
pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1); - print_debug_hex32(pci_read_config32(dev, 0x20)); + printk(BIOS_DEBUG, "SMB_BASE = 0x%x\n", pci_read_config32(dev, SMB_BASE)); /* Set smbus enable */ pci_write_config8(dev, 0x40, 1); /* Set smbus iospace enable */ diff --git a/src/southbridge/intel/i82801ex/smbus.h b/src/southbridge/intel/i82801ex/smbus.h index f330c0a..e257e25 100644 --- a/src/southbridge/intel/i82801ex/smbus.h +++ b/src/southbridge/intel/i82801ex/smbus.h @@ -1,5 +1,9 @@ #include <device/smbus_def.h>
+//#define SMBUS_IO_BASE 0x0f00 +#define SMBUS_IO_BASE 0x400 +#define SMB_BASE 0x20 + #define SMBHSTSTAT 0x0 #define SMBHSTCTL 0x2 #define SMBHSTCMD 0x3