On Tue, 2011-11-08 at 09:33 +0100, Rudolf Marek wrote:
Hi,
Just a quick notes. There a peformance MSRs which have L2 fills counters. I did want to know on AMD how the fills/misses/etc works so I used that counters to see what is actually going on.
http://oprofile.sourceforge.net/docs
Has a list of events.
Good tip! I should be able to use events BSQ_cache_reference and BSQ_allocation to count cache hits and misses.
The CR.NW mode differs accross Intel CPUs just check documentation what is it doing in your case (The architecture manuals). To get CAR working I would simply follow the BIOS with serialICE.
Well, for Xeon CR0.NW is a don't care bit and it's always in no-fill mode.
A part of my Problem 2 was that also inb()/outb() flushes modified cache-lines from L1 to (disabled?) L2 and system bus. I think with SerialICE I could not store a single valid cache-line in L1, as this would involve serial-io between any two store dword instructions.
I just realised that attempts to use compressed ramstage on this mainboard have always halted on un-LZMA, while for payload un-LZMA is OK. Until now I thought it was a compiler issue with ROMCC and GCC creating slighty different machine code, but maybe I should push microcode update before any cache use. While there are quite a few errata for these CPUs, I did not identify any of those with the symptoms I saw.
Thanks, Kyösti