Author: rminnich Date: 2008-06-03 17:22:16 +0200 (Tue, 03 Jun 2008) New Revision: 688
Modified: coreboot-v3/mainboard/artecgroup/dbe62/dts coreboot-v3/southbridge/amd/cs5536/cs5536.c coreboot-v3/southbridge/amd/cs5536/dts Log: This patch gets usb port 3 on dbe62 working and sets up a dts-based way to map USB EHCI power control registers to power enables pins 1 and 2.
Why doesn't port 4 work? Who knows. That's a problem for another day.
Signed-off-by: Ronald G. Minnich rminnich@gmail.com
Acked-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net
Modified: coreboot-v3/mainboard/artecgroup/dbe62/dts =================================================================== --- coreboot-v3/mainboard/artecgroup/dbe62/dts 2008-05-28 01:00:36 UTC (rev 687) +++ coreboot-v3/mainboard/artecgroup/dbe62/dts 2008-06-03 15:22:16 UTC (rev 688) @@ -52,6 +52,8 @@ com2_address = "0x3f8"; /* Set com2 IRQ to be what is usually COM1 */ com2_irq = "4"; + /* USB Port Power Handling setting. */ + pph = "0xf5"; }; pci@15,2 { /config/("southbridge/amd/cs5536/ide");
Modified: coreboot-v3/southbridge/amd/cs5536/cs5536.c =================================================================== --- coreboot-v3/southbridge/amd/cs5536/cs5536.c 2008-05-28 01:00:36 UTC (rev 687) +++ coreboot-v3/southbridge/amd/cs5536/cs5536.c 2008-06-03 15:22:16 UTC (rev 688) @@ -454,8 +454,16 @@ *(bar + UOCMUX) |= PMUX_HOST;
/* Overcurrent configuration */ + printk(BIOS_DEBUG, "UOCCAP is %x\n", *(bar + UOCCAP)); if (sb->enable_USBP4_overcurrent) *(bar + UOCCAP) |= sb->enable_USBP4_overcurrent; + /* power control. see comment in the dts for these bits */ + if (sb->pph) { + *(bar + UOCCAP) &= ~0xff; + *(bar + UOCCAP) |= sb->pph; + } + printk(BIOS_DEBUG, "UOCCAP is %x\n", *(bar + UOCCAP)); + }
/* PBz#6466: If the UOC(OTG) device, port 4, is configured as a @@ -481,7 +489,17 @@ } }
- /* Disable virtual PCI UDC and OTG headers. */ + /* Disable virtual PCI UDC and OTG headers. The kernel never + * sees a header for this device. It used to provide an OS + * visible device, but that was defeatured. There are still + * some registers in the block that are useful for the firmware + * to setup, but nothing that a kernel level driver would need + * to consume. + * + * As you can see above, VSA does provide the header under + * device ID PCI_DEVICE_ID_AMD_CS5536_OTG, but it is hidden + * when 0xDEADBEEF is written to config space register 0x7C. + */ dev = dev_find_pci_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_UDC, 0); if (dev)
Modified: coreboot-v3/southbridge/amd/cs5536/dts =================================================================== --- coreboot-v3/southbridge/amd/cs5536/dts 2008-05-28 01:00:36 UTC (rev 687) +++ coreboot-v3/southbridge/amd/cs5536/dts 2008-06-03 15:22:16 UTC (rev 688) @@ -36,9 +36,34 @@ /* 0:IDE 1:FLASH, if you are using NAND flash instead of IDE drive. */ enable_ide_nand_flash = "0";
- /* Enable USB Port 4 (0:host 1:device). */ + /* Enable USB Port 4 (0:host 1:device). + * This means that the board or whatever would be a "gadget", i.e. + * you connect it to a computer and it looks like a storage or camera + * or printer. + */ enable_USBP4_device = "0";
+ /* This is a tad confusing, but it's hard to make it easy. + * These are the PPH bits (port power handling) in the + * USB Option Capability register. They are 4 2-bit fields + * that correspond to the four ports. This chip has two PWR ENABLE + * pins, and what you can do is, for each of the four fields, + * map which port controls which pin. It is common to map + * ports 1&2 to PWR_EN_1, and ports 3&4 to PWR_EN_2. + * The two bit fields are as follows: + * 00 -- no power ever + * 01 -- power control in EHCI will turn on both. + * 10 -- power control will turn on EN1 + * 11 -- power control will turn on EN2 + * This is all very wiring dependent, + * and there is a default hardware value (0xea), + * meaning port 4 is EN2 and the rest are EN1. + * So we let this default to 0, which to the driver means "do nothing", + * but if the mainboard sets it, then it will be set into the UOCCAP. + * for reference, DBE62 seems to want xx111010 -- xx because we + * can get port 3 to work, but not port 4. + */ + pph = "0"; /* 0:off, xxxx:overcurrent setting, e.g. 0x3FEA. * See CS5536 - Data Book (pages 380-381). */