Author: hailfinger Date: 2007-12-17 15:33:32 +0100 (Mon, 17 Dec 2007) New Revision: 3009
Modified: trunk/util/flashrom/flash.h trunk/util/flashrom/flashchips.c trunk/util/flashrom/spi.c Log: To make it easier to add new SPI chips to flashchips.c, rename functions with multiple possible opcodes from linear numbering at the end (_1, _2) to include the opcode at the end (_60, _c7). That way, you only have to take a short look at the data sheet and choose the right function by appending the opcode listed in the data sheet. No functional changes.
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net Acked-by: Ward Vandewege ward@gnu.org
Modified: trunk/util/flashrom/flash.h =================================================================== --- trunk/util/flashrom/flash.h 2007-12-16 21:15:27 UTC (rev 3008) +++ trunk/util/flashrom/flash.h 2007-12-17 14:33:32 UTC (rev 3009) @@ -257,7 +257,7 @@ int generic_spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); void generic_spi_write_enable(); void generic_spi_write_disable(); -int generic_spi_chip_erase(struct flashchip *flash); +int generic_spi_chip_erase_c7(struct flashchip *flash); int generic_spi_chip_write(struct flashchip *flash, uint8_t *buf);
/* 82802ab.c */
Modified: trunk/util/flashrom/flashchips.c =================================================================== --- trunk/util/flashrom/flashchips.c 2007-12-16 21:15:27 UTC (rev 3008) +++ trunk/util/flashrom/flashchips.c 2007-12-17 14:33:32 UTC (rev 3009) @@ -47,7 +47,7 @@ {"MX29F002", MX_ID, MX_29F002, 256, 64 * 1024, probe_29f002, erase_29f002, write_29f002}, {"MX25L4005", MX_ID, MX_25L4005, 512, 4 * 1024, - probe_spi, generic_spi_chip_erase, generic_spi_chip_write}, + probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write}, {"SST29EE020A", SST_ID, SST_29EE020A, 256, 128, probe_jedec, erase_chip_jedec, write_jedec}, {"SST28SF040A", SST_ID, SST_28SF040, 512, 256, @@ -141,7 +141,7 @@ {"M29F040B", ST_ID, ST_M29F040B, 512, 64 * 1024, probe_29f040b, erase_29f040b, write_29f040b}, {"M25P80", ST_ID, ST_M25P80, 1024, 64 * 1024, - probe_spi, generic_spi_chip_erase, generic_spi_chip_write}, + probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write}, {"82802ab", 137, 173, 512, 64 * 1024, probe_82802ab, erase_82802ab, write_82802ab}, {"82802ac", 137, 172, 1024, 64 * 1024,
Modified: trunk/util/flashrom/spi.c =================================================================== --- trunk/util/flashrom/spi.c 2007-12-16 21:15:27 UTC (rev 3008) +++ trunk/util/flashrom/spi.c 2007-12-17 14:33:32 UTC (rev 3009) @@ -46,24 +46,24 @@ #define JEDEC_WRDI_INSIZE 0x00
/* Chip Erase 0x60 is supported by Macronix/SST chips. */ -#define JEDEC_CE_1 {0x60}; -#define JEDEC_CE_1_OUTSIZE 0x01 -#define JEDEC_CE_1_INSIZE 0x00 +#define JEDEC_CE_60 {0x60}; +#define JEDEC_CE_60_OUTSIZE 0x01 +#define JEDEC_CE_60_INSIZE 0x00
-/* Chip Erase 0xc7 is supported by EON/Macronix chips. */ -#define JEDEC_CE_2 {0xc7}; -#define JEDEC_CE_2_OUTSIZE 0x01 -#define JEDEC_CE_2_INSIZE 0x00 +/* Chip Erase 0xc7 is supported by ST/EON/Macronix chips. */ +#define JEDEC_CE_C7 {0xc7}; +#define JEDEC_CE_C7_OUTSIZE 0x01 +#define JEDEC_CE_C7_INSIZE 0x00
/* Block Erase 0x52 is supported by SST chips. */ -#define JEDEC_BE_1 {0x52}; -#define JEDEC_BE_1_OUTSIZE 0x04 -#define JEDEC_BE_1_INSIZE 0x00 +#define JEDEC_BE_52 {0x52}; +#define JEDEC_BE_52_OUTSIZE 0x04 +#define JEDEC_BE_52_INSIZE 0x00
/* Block Erase 0xd8 is supported by EON/Macronix chips. */ -#define JEDEC_BE_2 {0xd8}; -#define JEDEC_BE_2_OUTSIZE 0x04 -#define JEDEC_BE_2_INSIZE 0x00 +#define JEDEC_BE_D8 {0xd8}; +#define JEDEC_BE_D8_OUTSIZE 0x04 +#define JEDEC_BE_D8_INSIZE 0x00
/* Sector Erase 0x20 is supported by Macronix/SST chips. */ #define JEDEC_SE {0x20}; @@ -277,9 +277,9 @@ return readarr[0]; }
-int generic_spi_chip_erase(struct flashchip *flash) +int generic_spi_chip_erase_c7(struct flashchip *flash) { - const unsigned char cmd[] = JEDEC_CE_2; + const unsigned char cmd[] = JEDEC_CE_C7; uint8_t statusreg;
statusreg = generic_spi_read_status_register(); @@ -287,7 +287,7 @@ generic_spi_write_enable(); /* Send CE (Chip Erase) */ - generic_spi_command(JEDEC_CE_2_OUTSIZE, JEDEC_CE_2_INSIZE, cmd, NULL); + generic_spi_command(JEDEC_CE_C7_OUTSIZE, JEDEC_CE_C7_INSIZE, cmd, NULL); /* Wait until the Write-In-Progress bit is cleared. * This usually takes 1-85 s, so wait in 1 s steps. */ @@ -301,16 +301,16 @@ * 32k for SST * 4-32k non-uniform for EON */ -int generic_spi_block_erase(const struct flashchip *flash, unsigned long addr) +int generic_spi_block_erase_d8(const struct flashchip *flash, unsigned long addr) { - unsigned char cmd[JEDEC_BE_2_OUTSIZE] = JEDEC_BE_2; + unsigned char cmd[JEDEC_BE_D8_OUTSIZE] = JEDEC_BE_D8;
cmd[1] = (addr & 0x00ff0000) >> 16; cmd[2] = (addr & 0x0000ff00) >> 8; cmd[3] = (addr & 0x000000ff); generic_spi_write_enable(); /* Send BE (Block Erase) */ - generic_spi_command(JEDEC_BE_2_OUTSIZE, JEDEC_BE_2_INSIZE, cmd, NULL); + generic_spi_command(JEDEC_BE_D8_OUTSIZE, JEDEC_BE_D8_INSIZE, cmd, NULL); /* Wait until the Write-In-Progress bit is cleared. * This usually takes 100-4000 ms, so wait in 100 ms steps. */