Re: [coreboot] SPD sanity check

[Carl-Daniel Hailfinger]

On 02.10.2009 13:29, Joseph Smith wrote:
> On Thu, 1 Oct 2009 20:39:40 -0700, ron minnich  wrote:
> > On Thu, Oct 1, 2009 at 6:21 PM, Joseph Smith  wrote:
> > > That doesn't look right at all! Shouldn't your dimms be at smbus 0x50
> > > and 0x51? What SuperIO is this?
> >
> > not at all, DIMMS can run from 50-57
>
> Ok but I have never seen one that didn't start at 0x50. Unless you have
> dimms in sockets 5(0x54) and 8(0x57)???

I think I once saw DIMMS at 0x50-0x53 and 0x58-0x5b on a dualprocessor
board with 8 DIMM slots per processor (4 of them populated per
processor), but I could be mistaken.

Regards,
Carl-Daniel