Stefan Reinauer (stefan.reinauer@coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2802
-gerrit
commit c4136759d3c84b99ca2329fab34ee944b3db1709 Author: Duncan Laurie dlaurie@chromium.org Date: Fri Feb 15 13:52:28 2013 -0800
LynxPoint: Move RCBA helper function to its own file
So it can get used in both romstage and ramstage.
Change-Id: Ief9eaafdd91df2a7b668de1a9b83aea3af3ff894 Signed-off-by: Duncan Laurie dlaurie@chromium.org --- src/southbridge/intel/lynxpoint/Makefile.inc | 3 +- src/southbridge/intel/lynxpoint/early_pch.c | 43 ---------------- src/southbridge/intel/lynxpoint/pch.h | 49 +++++++++--------- src/southbridge/intel/lynxpoint/rcba.c | 74 ++++++++++++++++++++++++++++ 4 files changed, 101 insertions(+), 68 deletions(-)
diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index 51bb428..fd5b4df 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -33,6 +33,7 @@ ramstage-y += usb_ehci.c ramstage-y += me_9.x.c ramstage-y += smbus.c
+ramstage-y += rcba.c ramstage-y += me_status.c ramstage-y += reset.c ramstage-y += watchdog.c @@ -48,7 +49,7 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me_9.x.c finalize.c
romstage-y += early_usb.c early_smbus.c early_me.c me_status.c early_pch.c romstage-$(CONFIG_USBDEBUG) += usb_debug.c -romstage-y += reset.c early_spi.c +romstage-y += reset.c early_spi.c rcba.c
ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y) romstage-y += lp_gpio.c diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 848eb56..e7b62b4 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -95,49 +95,6 @@ static void pch_enable_lpc(void) pci_write_config16(dev, LPC_EN, lpc_config); }
-static void pch_config_rcba(const struct rcba_config_instruction *rcba_config) -{ - const struct rcba_config_instruction *rc; - u32 value; - - rc = rcba_config; - while (rc->command != RCBA_COMMAND_END) - { - if ((rc->command & RCBA_REG_SIZE_MASK) == RCBA_REG_SIZE_16) { - switch (rc->command & RCBA_COMMAND_MASK) { - case RCBA_COMMAND_SET: - RCBA16(rc->reg) = (u16)rc->or_value; - break; - case RCBA_COMMAND_READ: - (void)RCBA16(rc->reg); - break; - case RCBA_COMMAND_RMW: - value = RCBA16(rc->reg); - value &= rc->mask; - value |= rc->or_value; - RCBA16(rc->reg) = (u16)value; - break; - } - } else { - switch (rc->command & RCBA_COMMAND_MASK) { - case RCBA_COMMAND_SET: - RCBA32(rc->reg) = rc->or_value; - break; - case RCBA_COMMAND_READ: - (void)RCBA32(rc->reg); - break; - case RCBA_COMMAND_RMW: - value = RCBA32(rc->reg); - value &= rc->mask; - value |= rc->or_value; - RCBA32(rc->reg) = value; - break; - } - } - rc++; - } -} - int early_pch_init(const void *gpio_map, const struct rcba_config_instruction *rcba_config) { diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 6f17d38..563730e 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -83,30 +83,6 @@ void intel_pch_finalize_smm(void); #endif
-#if !defined(__ASSEMBLER__) && !defined(__ROMCC__) -#if !defined(__PRE_RAM__) && !defined(__SMM__) -#include <device/device.h> -#include <arch/acpi.h> -#include "chip.h" -int pch_silicon_revision(void); -int pch_silicon_type(void); -int pch_silicon_supported(int type, int rev); -void pch_enable(device_t dev); -void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); -#if CONFIG_ELOG -void pch_log_state(void); -#endif -void acpi_create_intel_hpet(acpi_hpet_t * hpet); - -/* These helpers are for performing SMM relocation. */ -void southbridge_smm_init(void); -void southbridge_trigger_smi(void); -void southbridge_clear_smi_status(void); -#else -void enable_smbus(void); -void enable_usb_bar(void); -int smbus_read_byte(unsigned device, unsigned address); -int early_spi_read(u32 offset, u32 size, u8 *buffer);
/* State Machine configuration. */ #define RCBA_REG_SIZE_MASK 0x8000 @@ -147,6 +123,31 @@ struct rcba_config_instruction u32 or_value; };
+#if !defined(__ASSEMBLER__) && !defined(__ROMCC__) +void pch_config_rcba(const struct rcba_config_instruction *rcba_config); +#if !defined(__PRE_RAM__) && !defined(__SMM__) +#include <device/device.h> +#include <arch/acpi.h> +#include "chip.h" +int pch_silicon_revision(void); +int pch_silicon_type(void); +int pch_silicon_supported(int type, int rev); +void pch_enable(device_t dev); +void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); +#if CONFIG_ELOG +void pch_log_state(void); +#endif +void acpi_create_intel_hpet(acpi_hpet_t * hpet); + +/* These helpers are for performing SMM relocation. */ +void southbridge_smm_init(void); +void southbridge_trigger_smi(void); +void southbridge_clear_smi_status(void); +#else +void enable_smbus(void); +void enable_usb_bar(void); +int smbus_read_byte(unsigned device, unsigned address); +int early_spi_read(u32 offset, u32 size, u8 *buffer); int early_pch_init(const void *gpio_map, const struct rcba_config_instruction *rcba_config); #endif diff --git a/src/southbridge/intel/lynxpoint/rcba.c b/src/southbridge/intel/lynxpoint/rcba.c new file mode 100644 index 0000000..d41aa86 --- /dev/null +++ b/src/southbridge/intel/lynxpoint/rcba.c @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include <console/console.h> +#include <device/pci_def.h> +#ifdef __PRE_RAM__ +#include <arch/io.h> +#include <arch/romcc_io.h> +#else +#include <device/device.h> +#include <device/pci.h> +#endif +#include "pch.h" + +void pch_config_rcba(const struct rcba_config_instruction *rcba_config) +{ + const struct rcba_config_instruction *rc; + u32 value; + + rc = rcba_config; + while (rc->command != RCBA_COMMAND_END) + { + if ((rc->command & RCBA_REG_SIZE_MASK) == RCBA_REG_SIZE_16) { + switch (rc->command & RCBA_COMMAND_MASK) { + case RCBA_COMMAND_SET: + RCBA16(rc->reg) = (u16)rc->or_value; + break; + case RCBA_COMMAND_READ: + (void)RCBA16(rc->reg); + break; + case RCBA_COMMAND_RMW: + value = RCBA16(rc->reg); + value &= rc->mask; + value |= rc->or_value; + RCBA16(rc->reg) = (u16)value; + break; + } + } else { + switch (rc->command & RCBA_COMMAND_MASK) { + case RCBA_COMMAND_SET: + RCBA32(rc->reg) = rc->or_value; + break; + case RCBA_COMMAND_READ: + (void)RCBA32(rc->reg); + break; + case RCBA_COMMAND_RMW: + value = RCBA32(rc->reg); + value &= rc->mask; + value |= rc->or_value; + RCBA32(rc->reg) = value; + break; + } + } + rc++; + } +} +