Stefan Reinauer (stefan.reinauer@coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1618
-gerrit
commit a1f1a2f9f651102b56717c9507bef0a3ca1e7459 Author: Patrick Georgi patrick.georgi@secunet.com Date: Tue Nov 20 11:53:47 2012 +0100
Remove AMD special case for LAPIC based udelay()
- Optionally override FSB clock detection in generic LAPIC code with constant value. - Override on AMD Model fxx, 10xxx, agesa CPUs with 200MHz - compile LAPIC code for romstage, too - Remove #include ".../apic_timer.c" in AMD based mainboards - Remove custom udelay implementation from intel northbridges' romstages
Future work: - remove the compile time special case (requires some cpuid based switching) - drop northbridge udelay implementations (i945, i5000) if not required anymore (eg. can SMM use the LAPIC timer?)
Change-Id: I25bacaa2163f5e96ab7f3eaf1994ab6899eff054 Signed-off-by: Patrick Georgi patrick.georgi@secunet.com --- src/arch/x86/include/arch/cpu.h | 5 ++ src/cpu/amd/agesa/Kconfig | 5 ++ src/cpu/amd/agesa/Makefile.inc | 1 - src/cpu/amd/agesa/apic_timer.c | 59 ----------------------- src/cpu/amd/model_10xxx/Kconfig | 5 ++ src/cpu/amd/model_10xxx/Makefile.inc | 1 - src/cpu/amd/model_10xxx/apic_timer.c | 55 --------------------- src/cpu/amd/model_fxx/Kconfig | 5 ++ src/cpu/amd/model_fxx/Makefile.inc | 1 - src/cpu/amd/model_fxx/apic_timer.c | 29 ----------- src/cpu/x86/Kconfig | 3 ++ src/cpu/x86/lapic/Makefile.inc | 1 + src/cpu/x86/lapic/apic_timer.c | 13 ++++- src/mainboard/amd/dbm690t/romstage.c | 1 - src/mainboard/amd/mahogany/romstage.c | 1 - src/mainboard/amd/pistachio/romstage.c | 1 - src/mainboard/amd/serengeti_cheetah/ap_romstage.c | 1 - src/mainboard/amd/serengeti_cheetah/romstage.c | 1 - src/mainboard/arima/hdama/romstage.c | 1 - src/mainboard/asrock/939a785gmh/romstage.c | 1 - src/mainboard/asus/a8n_e/romstage.c | 1 - src/mainboard/asus/a8v-e_deluxe/romstage.c | 1 - src/mainboard/asus/a8v-e_se/romstage.c | 1 - src/mainboard/asus/k8v-x/romstage.c | 1 - src/mainboard/asus/m2n-e/romstage.c | 1 - src/mainboard/asus/m2v-mx_se/romstage.c | 1 - src/mainboard/asus/m2v/romstage.c | 1 - src/mainboard/broadcom/blast/romstage.c | 1 - src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c | 1 - src/mainboard/gigabyte/ga_2761gxdk/romstage.c | 1 - src/mainboard/gigabyte/m57sli/ap_romstage.c | 1 - src/mainboard/gigabyte/m57sli/romstage.c | 1 - src/mainboard/hp/dl145_g1/romstage.c | 2 +- src/mainboard/hp/dl145_g3/romstage.c | 1 - src/mainboard/hp/dl165_g6_fam10/romstage.c | 1 - src/mainboard/ibm/e325/romstage.c | 1 - src/mainboard/ibm/e326/romstage.c | 1 - src/mainboard/iwill/dk8_htx/romstage.c | 1 - src/mainboard/iwill/dk8s2/romstage.c | 1 - src/mainboard/iwill/dk8x/romstage.c | 1 - src/mainboard/kontron/kt690/romstage.c | 1 - src/mainboard/msi/ms7135/romstage.c | 1 - src/mainboard/msi/ms7260/ap_romstage.c | 1 - src/mainboard/msi/ms7260/romstage.c | 1 - src/mainboard/msi/ms9185/romstage.c | 1 - src/mainboard/msi/ms9282/romstage.c | 1 - src/mainboard/msi/ms9652_fam10/romstage.c | 1 - src/mainboard/newisys/khepri/romstage.c | 1 - src/mainboard/nvidia/l1_2pvv/ap_romstage.c | 1 - src/mainboard/nvidia/l1_2pvv/romstage.c | 1 - src/mainboard/siemens/sitemp_g1p1/romstage.c | 1 - src/mainboard/sunw/ultra40/romstage.c | 1 - src/mainboard/supermicro/h8dme/ap_romstage.c | 1 - src/mainboard/supermicro/h8dme/romstage.c | 1 - src/mainboard/supermicro/h8dmr/ap_romstage.c | 1 - src/mainboard/supermicro/h8dmr/romstage.c | 1 - src/mainboard/supermicro/h8dmr_fam10/romstage.c | 1 - src/mainboard/supermicro/h8qme_fam10/romstage.c | 1 - src/mainboard/technexion/tim5690/romstage.c | 1 - src/mainboard/technexion/tim8690/romstage.c | 1 - src/mainboard/tyan/s2850/romstage.c | 1 - src/mainboard/tyan/s2875/romstage.c | 1 - src/mainboard/tyan/s2880/romstage.c | 1 - src/mainboard/tyan/s2881/romstage.c | 1 - src/mainboard/tyan/s2882/romstage.c | 1 - src/mainboard/tyan/s2885/romstage.c | 1 - src/mainboard/tyan/s2891/romstage.c | 1 - src/mainboard/tyan/s2892/romstage.c | 1 - src/mainboard/tyan/s2895/romstage.c | 1 - src/mainboard/tyan/s2912/ap_romstage.c | 1 - src/mainboard/tyan/s2912/romstage.c | 1 - src/mainboard/tyan/s2912_fam10/romstage.c | 1 - src/mainboard/tyan/s4880/romstage.c | 1 - src/mainboard/tyan/s4882/romstage.c | 1 - src/northbridge/intel/i5000/Makefile.inc | 2 +- src/northbridge/intel/i945/Makefile.inc | 1 - src/northbridge/intel/sandybridge/Makefile.inc | 1 - 77 files changed, 38 insertions(+), 211 deletions(-)
diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index aa0412f..abe3f7f 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -138,6 +138,7 @@ static inline unsigned int cpuid_edx(unsigned int op) #define X86_VENDOR_SIS 10 #define X86_VENDOR_UNKNOWN 0xff
+#if !defined(__ROMCC__) #if !defined(__PRE_RAM__) #include <device/device.h>
@@ -157,6 +158,10 @@ struct cpu_driver {
struct device; struct cpu_driver *find_cpu_driver(struct device *cpu); +#else +#include <arch/io.h> +#include <arch/romcc_io.h> +#endif
struct cpu_info { device_t cpu; diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 39175fc..d57bded 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -26,6 +26,7 @@ config CPU_AMD_AGESA default y if CPU_AMD_AGESA_FAMILY15_TN default n select TSC_SYNC_LFENCE + select UDELAY_LAPIC
if CPU_AMD_AGESA
@@ -44,6 +45,10 @@ config XIP_ROM_SIZE In order to execute romstage in place on the flash rom, more space is required to be set as write through caching.
+config UDELAY_LAPIC_FIXED_FSB + int + default 200 + source src/cpu/amd/agesa/family10/Kconfig source src/cpu/amd/agesa/family12/Kconfig source src/cpu/amd/agesa/family14/Kconfig diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc index 6c6cb89..401be3e 100644 --- a/src/cpu/amd/agesa/Makefile.inc +++ b/src/cpu/amd/agesa/Makefile.inc @@ -24,5 +24,4 @@ subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) += family15tn
romstage-$(CONFIG_HAVE_ACPI_RESUME) += s3_resume.c ramstage-$(CONFIG_HAVE_ACPI_RESUME) += s3_resume.c -ramstage-y += apic_timer.c cpu_incs += $(src)/cpu/amd/agesa/cache_as_ram.inc diff --git a/src/cpu/amd/agesa/apic_timer.c b/src/cpu/amd/agesa/apic_timer.c deleted file mode 100644 index ec6ddd5..0000000 --- a/src/cpu/amd/agesa/apic_timer.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - ***************************************************************************** - * - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * *************************************************************************** - * - */ - -#include <stdint.h> -#include <delay.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/lapic.h> - -/* NOTE: We use the APIC TIMER register is to hold flags for AP init during - * pre-memory init (__PRE_RAM__). Don't use init_timer() and udelay is - * redirected to udelay_tsc(). - */ - - -void init_timer(void) -{ - /* Set the apic timer to no interrupts and periodic mode */ - lapic_write(LAPIC_LVTT, (1 << 17)|(1<< 16)|(0 << 12)|(0 << 0)); - - /* Set the divider to 1, no divider */ - lapic_write(LAPIC_TDCR, LAPIC_TDR_DIV_1); - - /* Set the initial counter to 0xffffffff */ - lapic_write(LAPIC_TMICT, 0xffffffff); - -} - - -void udelay(u32 usecs) -{ - u32 start, value, ticks; - /* Calculate the number of ticks to run, our FSB runs a 200Mhz */ - ticks = usecs * 200; - start = lapic_read(LAPIC_TMCCT); - do { - value = lapic_read(LAPIC_TMCCT); - } while((start - value) < ticks); - -} diff --git a/src/cpu/amd/model_10xxx/Kconfig b/src/cpu/amd/model_10xxx/Kconfig index 0254cf2..c5bdb4a 100644 --- a/src/cpu/amd/model_10xxx/Kconfig +++ b/src/cpu/amd/model_10xxx/Kconfig @@ -4,6 +4,7 @@ config CPU_AMD_MODEL_10XXX select SSE2 select MMCONF_SUPPORT_DEFAULT select TSC_SYNC_LFENCE + select UDELAY_LAPIC
if CPU_AMD_MODEL_10XXX config CPU_ADDR_BITS @@ -56,6 +57,10 @@ config SET_FIDVID_CORE_RANGE
endif # SET_FIDVID
+config UDELAY_LAPIC_FIXED_FSB + int + default 200 + config UPDATE_CPU_MICROCODE bool default y diff --git a/src/cpu/amd/model_10xxx/Makefile.inc b/src/cpu/amd/model_10xxx/Makefile.inc index c9becbd..81c565b 100644 --- a/src/cpu/amd/model_10xxx/Makefile.inc +++ b/src/cpu/amd/model_10xxx/Makefile.inc @@ -1,4 +1,3 @@ ramstage-y += model_10xxx_init.c ramstage-$(CONFIG_UPDATE_CPU_MICROCODE) += update_microcode.c -ramstage-y += apic_timer.c ramstage-y += processor_name.c diff --git a/src/cpu/amd/model_10xxx/apic_timer.c b/src/cpu/amd/model_10xxx/apic_timer.c deleted file mode 100644 index d961da7..0000000 --- a/src/cpu/amd/model_10xxx/apic_timer.c +++ /dev/null @@ -1,55 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <stdint.h> -#include <delay.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/lapic.h> - -/* NOTE: We use the APIC TIMER register is to hold flags for AP init during - * pre-memory init (__PRE_RAM__). Don't use init_timer() and udelay is - * redirected to udelay_tsc(). - */ - - -void init_timer(void) -{ - /* Set the apic timer to no interrupts and periodic mode */ - lapic_write(LAPIC_LVTT, (1 << 17)|(1<< 16)|(0 << 12)|(0 << 0)); - - /* Set the divider to 1, no divider */ - lapic_write(LAPIC_TDCR, LAPIC_TDR_DIV_1); - - /* Set the initial counter to 0xffffffff */ - lapic_write(LAPIC_TMICT, 0xffffffff); - -} - - -void udelay(u32 usecs) -{ - u32 start, value, ticks; - /* Calculate the number of ticks to run, our FSB runs a 200Mhz */ - ticks = usecs * 200; - start = lapic_read(LAPIC_TMCCT); - do { - value = lapic_read(LAPIC_TMCCT); - } while((start - value) < ticks); - -} diff --git a/src/cpu/amd/model_fxx/Kconfig b/src/cpu/amd/model_fxx/Kconfig index 28beacf..fb094b1 100644 --- a/src/cpu/amd/model_fxx/Kconfig +++ b/src/cpu/amd/model_fxx/Kconfig @@ -4,6 +4,7 @@ config CPU_AMD_MODEL_FXX select SSE select SSE2 select TSC_SYNC_LFENCE + select UDELAY_LAPIC
if CPU_AMD_MODEL_FXX config UDELAY_IO @@ -23,6 +24,10 @@ config HW_SCRUBBER bool default n
+config UDELAY_LAPIC_FIXED_FSB + int + default 200 + if SET_FIDVID config SET_FIDVID_DEBUG bool diff --git a/src/cpu/amd/model_fxx/Makefile.inc b/src/cpu/amd/model_fxx/Makefile.inc index 99c09c8..e016235 100644 --- a/src/cpu/amd/model_fxx/Makefile.inc +++ b/src/cpu/amd/model_fxx/Makefile.inc @@ -1,6 +1,5 @@ # no conditionals here. If you include this file from a socket, then you get all the binaries. ramstage-y += model_fxx_init.c -ramstage-y += apic_timer.c ramstage-y += model_fxx_update_microcode.c ramstage-y += processor_name.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += powernow_acpi.c diff --git a/src/cpu/amd/model_fxx/apic_timer.c b/src/cpu/amd/model_fxx/apic_timer.c deleted file mode 100644 index 6eb99a4..0000000 --- a/src/cpu/amd/model_fxx/apic_timer.c +++ /dev/null @@ -1,29 +0,0 @@ -#include <stdint.h> -#include <delay.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/lapic.h> - -void init_timer(void) -{ - /* Set the apic timer to no interrupts and periodic mode */ - lapic_write(LAPIC_LVTT, (1 << 17)|(1<< 16)|(0 << 12)|(0 << 0)); - - /* Set the divider to 1, no divider */ - lapic_write(LAPIC_TDCR, LAPIC_TDR_DIV_1); - - /* Set the initial counter to 0xffffffff */ - lapic_write(LAPIC_TMICT, 0xffffffff); - -} - -void udelay(unsigned usecs) -{ - uint32_t start, value, ticks; - /* Calculate the number of ticks to run, our FSB runs a 200Mhz */ - ticks = usecs * 200; - start = lapic_read(LAPIC_TMCCT); - do { - value = lapic_read(LAPIC_TMCCT); - } while((start - value) < ticks); - -} diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 4300c3d..ae3241e 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -11,6 +11,9 @@ config UDELAY_LAPIC bool default n
+config UDELAY_LAPIC_FIXED_FSB + int + config UDELAY_TSC bool default n diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc index f3fcadc..6663c12 100644 --- a/src/cpu/x86/lapic/Makefile.inc +++ b/src/cpu/x86/lapic/Makefile.inc @@ -1,5 +1,6 @@ ramstage-y += lapic.c ramstage-y += lapic_cpu_init.c ramstage-y += secondary.S +romstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c ramstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c ramstage-y += boot_cpu.c diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c index 562c79c..53209fb 100644 --- a/src/cpu/x86/lapic/apic_timer.c +++ b/src/cpu/x86/lapic/apic_timer.c @@ -20,7 +20,9 @@
#include <stdint.h> #include <delay.h> +#include <arch/io.h> #include <arch/cpu.h> +#include <cpu/x86/car.h> #include <cpu/x86/msr.h> #include <cpu/x86/lapic.h>
@@ -28,7 +30,15 @@ * memory init. */
-static u32 timer_fsb = 0; +#if CONFIG_UDELAY_LAPIC_FIXED_FSB +static const u32 timer_fsb = CONFIG_UDELAY_LAPIC_FIXED_FSB; + +static int set_timer_fsb(void) +{ + return 0; +} +#else +static u32 timer_fsb CAR_GLOBAL = 0;
static int set_timer_fsb(void) { @@ -60,6 +70,7 @@ static int set_timer_fsb(void)
return 0; } +#endif
void init_timer(void) { diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c index 459aa47..84b08e6 100644 --- a/src/mainboard/amd/dbm690t/romstage.c +++ b/src/mainboard/amd/dbm690t/romstage.c @@ -33,7 +33,6 @@ #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/raminit.h" -#include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c index 9d913e9..39070ea 100644 --- a/src/mainboard/amd/mahogany/romstage.c +++ b/src/mainboard/amd/mahogany/romstage.c @@ -34,7 +34,6 @@ #include <spd.h> #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/raminit.h" -#include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c index 45c94c8..fe37842 100644 --- a/src/mainboard/amd/pistachio/romstage.c +++ b/src/mainboard/amd/pistachio/romstage.c @@ -28,7 +28,6 @@ #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/raminit.h" -#include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" diff --git a/src/mainboard/amd/serengeti_cheetah/ap_romstage.c b/src/mainboard/amd/serengeti_cheetah/ap_romstage.c index 65ac2e6..84561d6 100644 --- a/src/mainboard/amd/serengeti_cheetah/ap_romstage.c +++ b/src/mainboard/amd/serengeti_cheetah/ap_romstage.c @@ -14,7 +14,6 @@
#include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/raminit.h" -#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c index 2524e52..a70baaa 100644 --- a/src/mainboard/amd/serengeti_cheetah/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah/romstage.c @@ -15,7 +15,6 @@ #include "southbridge/amd/amd8111/early_smbus.c" #include <reset.h> #include "northbridge/amd/amdk8/raminit.h" -#include "cpu/amd/model_fxx/apic_timer.c" #include "northbridge/amd/amdk8/reset_test.c" #include "cpu/x86/bist.h" #include "lib/delay.c" diff --git a/src/mainboard/arima/hdama/romstage.c b/src/mainboard/arima/hdama/romstage.c index cd08389..84dc7a3 100644 --- a/src/mainboard/arima/hdama/romstage.c +++ b/src/mainboard/arima/hdama/romstage.c @@ -10,7 +10,6 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" -#include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c index 51b7519..d3717f1 100644 --- a/src/mainboard/asrock/939a785gmh/romstage.c +++ b/src/mainboard/asrock/939a785gmh/romstage.c @@ -34,7 +34,6 @@ #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/raminit.h" -#include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" #include <spd.h> #include "cpu/x86/lapic/boot_cpu.c" diff --git a/src/mainboard/asus/a8n_e/romstage.c b/src/mainboard/asus/a8n_e/romstage.c index fcbe86d..bdfd124 100644 --- a/src/mainboard/asus/a8n_e/romstage.c +++ b/src/mainboard/asus/a8n_e/romstage.c @@ -40,7 +40,6 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/nvidia/ck804/early_smbus.h" #include "northbridge/amd/amdk8/raminit.h" -#include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" #include "northbridge/amd/amdk8/debug.c" #include "cpu/x86/mtrr/earlymtrr.c" diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c index 53a1fbc..3c4f640 100644 --- a/src/mainboard/asus/a8v-e_deluxe/romstage.c +++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c @@ -35,7 +35,6 @@ unsigned int get_sbdn(unsigned bus); #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/raminit.h" -#include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c index 7539a80..014c5b0 100644 --- a/src/mainboard/asus/a8v-e_se/romstage.c +++ b/src/mainboard/asus/a8v-e_se/romstage.c @@ -35,7 +35,6 @@ unsigned int get_sbdn(unsigned bus); #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/raminit.h" -#include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c index 82b0636..a0963da 100644 --- a/src/mainboard/asus/k8v-x/romstage.c +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -35,7 +35,6 @@ unsigned int get_sbdn(unsigned bus); #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/raminit.h" -#include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" diff --git a/src/mainboard/asus/m2n-e/romstage.c b/src/mainboard/asus/m2n-e/romstage.c index 21ca89e..aedd5cd 100644 --- a/src/mainboard/asus/m2n-e/romstage.c +++ b/src/mainboard/asus/m2n-e/romstage.c @@ -37,7 +37,6 @@ #include <cpu/amd/model_fxx_rev.h> #include "southbridge/nvidia/mcp55/early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" -#include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" #include <lib.h> #include <spd.h> diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c index ac88f6a..681ffcb 100644 --- a/src/mainboard/asus/m2v-mx_se/romstage.c +++ b/src/mainboard/asus/m2v-mx_se/romstage.c @@ -40,7 +40,6 @@ unsigned int get_sbdn(unsigned bus); #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/raminit.h" -#include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c index 367ef3b..db6d2c8 100644 --- a/src/mainboard/asus/m2v/romstage.c +++ b/src/mainboard/asus/m2v/romstage.c @@ -40,7 +40,6 @@ unsigned int get_sbdn(unsigned bus); #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/raminit.h" -#include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" diff --git a/src/mainboard/broadcom/blast/romstage.c b/src/mainboard/broadcom/blast/romstage.c index df7b615..4bf421c 100644 --- a/src/mainboard/broadcom/blast/romstage.c +++ b/src/mainboard/broadcom/blast/romstage.c @@ -11,7 +11,6 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/broadcom/bcm5785/early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" -#include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" diff --git a/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c index b157454..28be373 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c @@ -39,7 +39,6 @@
#include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/raminit.h" -#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c index 5a36ac6..d9a133b 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c @@ -40,7 +40,6 @@ #include "southbridge/sis/sis966/sis966.h" #include "southbridge/sis/sis966/early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" -#include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" diff --git a/src/mainboard/gigabyte/m57sli/ap_romstage.c b/src/mainboard/gigabyte/m57sli/ap_romstage.c index 2b4be30..670f63b 100644 --- a/src/mainboard/gigabyte/m57sli/ap_romstage.c +++ b/src/mainboard/gigabyte/m57sli/ap_romstage.c @@ -37,7 +37,6 @@
#include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/raminit.h" -#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c index 7bf7406..2622b62 100644 --- a/src/mainboard/gigabyte/m57sli/romstage.c +++ b/src/mainboard/gigabyte/m57sli/romstage.c @@ -37,7 +37,6 @@ #include <cpu/amd/model_fxx_rev.h> #include "southbridge/nvidia/mcp55/early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" -#include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c index a75d5e1..97e1e30 100644 --- a/src/mainboard/hp/dl145_g1/romstage.c +++ b/src/mainboard/hp/dl145_g1/romstage.c @@ -8,10 +8,10 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> +#include <delay.h> #include "northbridge/amd/amdk8/amdk8.h" #include "southbridge/amd/amd8111/early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" -#include "cpu/amd/model_fxx/apic_timer.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include "superio/winbond/w83627hf/early_serial.c" diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c index 872a337..7decb72 100644 --- a/src/mainboard/hp/dl145_g3/romstage.c +++ b/src/mainboard/hp/dl145_g3/romstage.c @@ -42,7 +42,6 @@ #include <cpu/amd/model_fxx_rev.h> #include "southbridge/broadcom/bcm5785/early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" -#include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index 8235f9c..443fa4e 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -44,7 +44,6 @@ #include "northbridge/amd/amdfam10/amdfam10.h" #include <lib.h> #include <spd.h> -#include "cpu/amd/model_10xxx/apic_timer.c" #include "lib/delay.c" #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdfam10/reset_test.c" diff --git a/src/mainboard/ibm/e325/romstage.c b/src/mainboard/ibm/e325/romstage.c index b10f693..e5b315a 100644 --- a/src/mainboard/ibm/e325/romstage.c +++ b/src/mainboard/ibm/e325/romstage.c @@ -11,7 +11,6 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" -#include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" diff --git a/src/mainboard/ibm/e326/romstage.c b/src/mainboard/ibm/e326/romstage.c index 93afa39..b4dddd5 100644 --- a/src/mainboard/ibm/e326/romstage.c +++ b/src/mainboard/ibm/e326/romstage.c @@ -11,7 +11,6 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" -#include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c index 906105e..3146817 100644 --- a/src/mainboard/iwill/dk8_htx/romstage.c +++ b/src/mainboard/iwill/dk8_htx/romstage.c @@ -14,7 +14,6 @@ #include <cpu/amd/model_fxx_rev.h> #include "southbridge/amd/amd8111/early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" -#include "cpu/amd/model_fxx/apic_timer.c" #include "northbridge/amd/amdk8/reset_test.c" #include "cpu/x86/bist.h" #include "lib/delay.c" diff --git a/src/mainboard/iwill/dk8s2/romstage.c b/src/mainboard/iwill/dk8s2/romstage.c index 4600fa6..f2de54a 100644 --- a/src/mainboard/iwill/dk8s2/romstage.c +++ b/src/mainboard/iwill/dk8s2/romstage.c @@ -14,7 +14,6 @@ #include <cpu/amd/model_fxx_rev.h> #include "southbridge/amd/amd8111/early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" -#include "cpu/amd/model_fxx/apic_timer.c" #include "northbridge/amd/amdk8/reset_test.c" #include "cpu/x86/bist.h" #include "lib/delay.c" diff --git a/src/mainboard/iwill/dk8x/romstage.c b/src/mainboard/iwill/dk8x/romstage.c index 89a652a..eae16d3 100644 --- a/src/mainboard/iwill/dk8x/romstage.c +++ b/src/mainboard/iwill/dk8x/romstage.c @@ -14,7 +14,6 @@ #include <cpu/amd/model_fxx_rev.h> #include "southbridge/amd/amd8111/early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" -#include "cpu/amd/model_fxx/apic_timer.c" #include "northbridge/amd/amdk8/reset_test.c" #include "cpu/x86/bist.h" #include "lib/delay.c" diff --git a/src/mainboard/kontron/kt690/romstage.c b/src/mainboard/kontron/kt690/romstage.c index ee17208..f738666 100644 --- a/src/mainboard/kontron/kt690/romstage.c +++ b/src/mainboard/kontron/kt690/romstage.c @@ -34,7 +34,6 @@ #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/raminit.h" -#include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" #include <spd.h> #include "cpu/x86/lapic/boot_cpu.c" diff --git a/src/mainboard/msi/ms7135/romstage.c b/src/mainboard/msi/ms7135/romstage.c index 515f7d7..42db9cc 100644 --- a/src/mainboard/msi/ms7135/romstage.c +++ b/src/mainboard/msi/ms7135/romstage.c @@ -38,7 +38,6 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/nvidia/ck804/early_smbus.h" #include "northbridge/amd/amdk8/raminit.h" -#include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" #include "northbridge/amd/amdk8/debug.c" #include "cpu/x86/mtrr/earlymtrr.c" diff --git a/src/mainboard/msi/ms7260/ap_romstage.c b/src/mainboard/msi/ms7260/ap_romstage.c index 7a93e8b..e05f74e 100644 --- a/src/mainboard/msi/ms7260/ap_romstage.c +++ b/src/mainboard/msi/ms7260/ap_romstage.c @@ -34,7 +34,6 @@ #include "console/console.c" #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/raminit.h" -#include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" /* #include "cpu/x86/lapic/boot_cpu.c" */ #include "northbridge/amd/amdk8/reset_test.c" diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c index 5ec26a9..0a97960 100644 --- a/src/mainboard/msi/ms7260/romstage.c +++ b/src/mainboard/msi/ms7260/romstage.c @@ -37,7 +37,6 @@ #include <cpu/amd/model_fxx_rev.h> #include "southbridge/nvidia/mcp55/early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" -#include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" #include <lib.h> #include <spd.h> diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c index 1a72ae0..f532465 100644 --- a/src/mainboard/msi/ms9185/romstage.c +++ b/src/mainboard/msi/ms9185/romstage.c @@ -36,7 +36,6 @@ #include <cpu/amd/model_fxx_rev.h> #include "southbridge/broadcom/bcm5785/early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" -#include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" #include <reset.h> #include "cpu/x86/lapic/boot_cpu.c" diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c index 46492a2..7cccc89 100644 --- a/src/mainboard/msi/ms9282/romstage.c +++ b/src/mainboard/msi/ms9282/romstage.c @@ -34,7 +34,6 @@ #include <cpu/amd/model_fxx_rev.h> #include "southbridge/nvidia/mcp55/early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" -#include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index 3bb436a..0431e97 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -37,7 +37,6 @@ #include "southbridge/nvidia/mcp55/early_smbus.c" #include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/amdfam10.h" -#include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdfam10/reset_test.c" diff --git a/src/mainboard/newisys/khepri/romstage.c b/src/mainboard/newisys/khepri/romstage.c index 1098275..ae522d2 100644 --- a/src/mainboard/newisys/khepri/romstage.c +++ b/src/mainboard/newisys/khepri/romstage.c @@ -18,7 +18,6 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" -#include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" diff --git a/src/mainboard/nvidia/l1_2pvv/ap_romstage.c b/src/mainboard/nvidia/l1_2pvv/ap_romstage.c index c1c49cc..5d0fa6b 100644 --- a/src/mainboard/nvidia/l1_2pvv/ap_romstage.c +++ b/src/mainboard/nvidia/l1_2pvv/ap_romstage.c @@ -36,7 +36,6 @@
#include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/raminit.h" -#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c index 454bcac..18a1ff0 100644 --- a/src/mainboard/nvidia/l1_2pvv/romstage.c +++ b/src/mainboard/nvidia/l1_2pvv/romstage.c @@ -38,7 +38,6 @@ #include <cpu/amd/model_fxx_rev.h> #include "southbridge/nvidia/mcp55/early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" -#include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" diff --git a/src/mainboard/siemens/sitemp_g1p1/romstage.c b/src/mainboard/siemens/sitemp_g1p1/romstage.c index b87f19f..3ea9419 100644 --- a/src/mainboard/siemens/sitemp_g1p1/romstage.c +++ b/src/mainboard/siemens/sitemp_g1p1/romstage.c @@ -40,7 +40,6 @@
#include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/raminit.h" -#include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c"
#include "cpu/x86/lapic/boot_cpu.c" diff --git a/src/mainboard/sunw/ultra40/romstage.c b/src/mainboard/sunw/ultra40/romstage.c index 1f0a395..d927396 100644 --- a/src/mainboard/sunw/ultra40/romstage.c +++ b/src/mainboard/sunw/ultra40/romstage.c @@ -13,7 +13,6 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/nvidia/ck804/early_smbus.h" #include "northbridge/amd/amdk8/raminit.h" -#include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" diff --git a/src/mainboard/supermicro/h8dme/ap_romstage.c b/src/mainboard/supermicro/h8dme/ap_romstage.c index ebd0305..2e9c5a9 100644 --- a/src/mainboard/supermicro/h8dme/ap_romstage.c +++ b/src/mainboard/supermicro/h8dme/ap_romstage.c @@ -37,7 +37,6 @@
#include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/raminit.h" -#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c index 989f2d8..6f156bc 100644 --- a/src/mainboard/supermicro/h8dme/romstage.c +++ b/src/mainboard/supermicro/h8dme/romstage.c @@ -35,7 +35,6 @@ #include <cpu/amd/model_fxx_rev.h> #include "southbridge/nvidia/mcp55/early_smbus.c" // for enable the FAN #include "northbridge/amd/amdk8/raminit.h" -#include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" diff --git a/src/mainboard/supermicro/h8dmr/ap_romstage.c b/src/mainboard/supermicro/h8dmr/ap_romstage.c index 62d796a..d04775b 100644 --- a/src/mainboard/supermicro/h8dmr/ap_romstage.c +++ b/src/mainboard/supermicro/h8dmr/ap_romstage.c @@ -37,7 +37,6 @@
#include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/raminit.h" -#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c index cdef306..e3113d8 100644 --- a/src/mainboard/supermicro/h8dmr/romstage.c +++ b/src/mainboard/supermicro/h8dmr/romstage.c @@ -38,7 +38,6 @@ #include <cpu/amd/model_fxx_rev.h> #include "southbridge/nvidia/mcp55/early_smbus.c" // for enable the FAN #include "northbridge/amd/amdk8/raminit.h" -#include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index ddd0920..be5a8e1 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -37,7 +37,6 @@ #include "southbridge/nvidia/mcp55/early_smbus.c" // for enable the FAN #include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/amdfam10.h" -#include "cpu/amd/model_10xxx/apic_timer.c" #include "lib/delay.c" #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdfam10/reset_test.c" diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index 2f5be99..28efb1c 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -37,7 +37,6 @@ #include "southbridge/nvidia/mcp55/early_smbus.c" // for enable the FAN #include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/amdfam10.h" -#include "cpu/amd/model_10xxx/apic_timer.c" #include "lib/delay.c" #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdfam10/reset_test.c" diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c index c24e891..57cb3f2 100644 --- a/src/mainboard/technexion/tim5690/romstage.c +++ b/src/mainboard/technexion/tim5690/romstage.c @@ -33,7 +33,6 @@ #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/raminit.h" -#include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" #include <spd.h> #include "cpu/x86/lapic/boot_cpu.c" diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c index 875321e..ed133da 100644 --- a/src/mainboard/technexion/tim8690/romstage.c +++ b/src/mainboard/technexion/tim8690/romstage.c @@ -33,7 +33,6 @@ #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/raminit.h" -#include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" #include <spd.h> #include "cpu/x86/lapic/boot_cpu.c" diff --git a/src/mainboard/tyan/s2850/romstage.c b/src/mainboard/tyan/s2850/romstage.c index 567b4f1..4f14eab 100644 --- a/src/mainboard/tyan/s2850/romstage.c +++ b/src/mainboard/tyan/s2850/romstage.c @@ -13,7 +13,6 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" -#include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" diff --git a/src/mainboard/tyan/s2875/romstage.c b/src/mainboard/tyan/s2875/romstage.c index 4b52cd3..68422f3 100644 --- a/src/mainboard/tyan/s2875/romstage.c +++ b/src/mainboard/tyan/s2875/romstage.c @@ -13,7 +13,6 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" -#include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" diff --git a/src/mainboard/tyan/s2880/romstage.c b/src/mainboard/tyan/s2880/romstage.c index 6dc62af..20d829c 100644 --- a/src/mainboard/tyan/s2880/romstage.c +++ b/src/mainboard/tyan/s2880/romstage.c @@ -13,7 +13,6 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" -#include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" diff --git a/src/mainboard/tyan/s2881/romstage.c b/src/mainboard/tyan/s2881/romstage.c index 07ac12b..b75e387 100644 --- a/src/mainboard/tyan/s2881/romstage.c +++ b/src/mainboard/tyan/s2881/romstage.c @@ -12,7 +12,6 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" -#include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" diff --git a/src/mainboard/tyan/s2882/romstage.c b/src/mainboard/tyan/s2882/romstage.c index 6dc62af..20d829c 100644 --- a/src/mainboard/tyan/s2882/romstage.c +++ b/src/mainboard/tyan/s2882/romstage.c @@ -13,7 +13,6 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" -#include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" diff --git a/src/mainboard/tyan/s2885/romstage.c b/src/mainboard/tyan/s2885/romstage.c index 5aede1c..1e41d74 100644 --- a/src/mainboard/tyan/s2885/romstage.c +++ b/src/mainboard/tyan/s2885/romstage.c @@ -12,7 +12,6 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" -#include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" diff --git a/src/mainboard/tyan/s2891/romstage.c b/src/mainboard/tyan/s2891/romstage.c index 0936481..c57948f 100644 --- a/src/mainboard/tyan/s2891/romstage.c +++ b/src/mainboard/tyan/s2891/romstage.c @@ -13,7 +13,6 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/nvidia/ck804/early_smbus.h" #include "northbridge/amd/amdk8/raminit.h" -#include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" diff --git a/src/mainboard/tyan/s2892/romstage.c b/src/mainboard/tyan/s2892/romstage.c index 9124b99..443ded0 100644 --- a/src/mainboard/tyan/s2892/romstage.c +++ b/src/mainboard/tyan/s2892/romstage.c @@ -13,7 +13,6 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/nvidia/ck804/early_smbus.h" #include "northbridge/amd/amdk8/raminit.h" -#include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" diff --git a/src/mainboard/tyan/s2895/romstage.c b/src/mainboard/tyan/s2895/romstage.c index db777be..1b5d21d 100644 --- a/src/mainboard/tyan/s2895/romstage.c +++ b/src/mainboard/tyan/s2895/romstage.c @@ -13,7 +13,6 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/nvidia/ck804/early_smbus.h" #include "northbridge/amd/amdk8/raminit.h" -#include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" diff --git a/src/mainboard/tyan/s2912/ap_romstage.c b/src/mainboard/tyan/s2912/ap_romstage.c index 6310759..fc7df82 100644 --- a/src/mainboard/tyan/s2912/ap_romstage.c +++ b/src/mainboard/tyan/s2912/ap_romstage.c @@ -33,7 +33,6 @@
#include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/raminit.h" -#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c index b798068..fc5d659 100644 --- a/src/mainboard/tyan/s2912/romstage.c +++ b/src/mainboard/tyan/s2912/romstage.c @@ -38,7 +38,6 @@ #include <cpu/amd/model_fxx_rev.h> #include "southbridge/nvidia/mcp55/early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" -#include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c index c3017e5..16d3c47 100644 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ b/src/mainboard/tyan/s2912_fam10/romstage.c @@ -37,7 +37,6 @@ #include "southbridge/nvidia/mcp55/early_smbus.c" #include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/amdfam10.h" -#include "cpu/amd/model_10xxx/apic_timer.c" #include "lib/delay.c" #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdfam10/reset_test.c" diff --git a/src/mainboard/tyan/s4880/romstage.c b/src/mainboard/tyan/s4880/romstage.c index c697670..bd9c747 100644 --- a/src/mainboard/tyan/s4880/romstage.c +++ b/src/mainboard/tyan/s4880/romstage.c @@ -12,7 +12,6 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" -#include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" diff --git a/src/mainboard/tyan/s4882/romstage.c b/src/mainboard/tyan/s4882/romstage.c index 56b6325..363f3bb 100644 --- a/src/mainboard/tyan/s4882/romstage.c +++ b/src/mainboard/tyan/s4882/romstage.c @@ -11,7 +11,6 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" -#include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" diff --git a/src/northbridge/intel/i5000/Makefile.inc b/src/northbridge/intel/i5000/Makefile.inc index e3ab0bb..03d8691 100644 --- a/src/northbridge/intel/i5000/Makefile.inc +++ b/src/northbridge/intel/i5000/Makefile.inc @@ -18,5 +18,5 @@ #
ramstage-y += northbridge.c -romstage-y += raminit.c udelay.c +romstage-y += raminit.c cpu_incs += src/northbridge/intel/i5000/halt_second_bsp.S diff --git a/src/northbridge/intel/i945/Makefile.inc b/src/northbridge/intel/i945/Makefile.inc index 89b0308..491225e 100644 --- a/src/northbridge/intel/i945/Makefile.inc +++ b/src/northbridge/intel/i945/Makefile.inc @@ -21,7 +21,6 @@ ramstage-y += northbridge.c ramstage-y += gma.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
-romstage-y += udelay.c romstage-y += raminit.c romstage-y += early_init.c romstage-y += errata.c diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index bef3da5..95d66ce 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -23,7 +23,6 @@ ramstage-y += gma.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c ramstage-y += mrccache.c
-romstage-y += udelay.c romstage-y += raminit.c romstage-y += mrccache.c romstage-y += early_init.c