coreboot

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coreboot 4.17 release planned for May 30th
by Martin Roth 16 May '22

16 May '22

The next quarterly release, 4.17 is targeted for May 30, 2022. Additionally, at that time, we plan to update the release packages and version numbers any of the coreboot branches which have been modified since they were released. Going forward, this should happen anytime there's a new release. Please test any boards that you have available. Current stats since the 4.16 release, 3 months ago (As of early Monday, May 16): Added 10 mainboards: ------------------- * Clevo L140MU / L141MU / L142MU * Dell Inc. Dell Precision T1650 * Google -> Craask * Google -> Gelarshie * Google -> Mithrax * Google -> Osiris * HP Z220 CMT Workstation * Star Labs Star Labs LabTop Mk IV (i3-10110U and i7-10710U) * Star Labs Star Labs Lite Mk III (N5000) * Star Labs Star Labs Lite Mk IV (N5030) Removed 2 mainboards: ------------------- * Google -> Deltan * Google -> Deltaur repo statistics ------------------- - Total Commits: 998 - Average Commits per day: 12.58 - Total lines added: 34473 - Average lines added per commit: 34.54 - Number of patches adding more than 100 lines: 40 - Average lines added per small commit: 22.35 - Total lines removed: 57663 - Average lines removed per commit: 57.78 - Total difference between added and removed: -23190 - Total authors: 131 - New authors: 17 Martin

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New Defects reported by Coverity Scan for coreboot
by scan-admin＠coverity.com 13 May '22

13 May '22

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 2 new defect(s) introduced to coreboot found with Coverity Scan. 1 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 2 of 2 defect(s) ** CID 1488815: Resource leaks (RESOURCE_LEAK) /src/drivers/usb/hub/acpi.c: 48 in usb_hub_add_ports() ________________________________________________________________________________________________________ *** CID 1488815: Resource leaks (RESOURCE_LEAK) /src/drivers/usb/hub/acpi.c: 48 in usb_hub_add_ports() 42 while ((port = dev_bus_each_child(dev->link_list, port)) != NULL) { 43 if (child_count++ >= config->port_count) { 44 printk(BIOS_WARNING, "%s cannot be added. Port Count limit reached.\n", 45 dev_name(port)); 46 continue; 47 } >>> CID 1488815: Resource leaks (RESOURCE_LEAK) >>> Failing to save or free storage allocated by "usb_hub_acpi_name(port)" leaks it. 48 acpigen_write_device(usb_hub_acpi_name(port)); 49 acpigen_write_name_byte("_ADR", port->path.usb.port_id + 1); 50 acpigen_write_device_end(); 51 } 52 } 53 ** CID 1488814: Uninitialized variables (UNINIT) ________________________________________________________________________________________________________ *** CID 1488814: Uninitialized variables (UNINIT) /src/soc/intel/alderlake/acpi.c: 307 in soc_lpi_get_constraints() 301 snprintf(path, sizeof(path), 302 CONFIG_ACPI_CPU_STRING, i); 303 break; 304 } 305 } 306 >>> CID 1488814: Uninitialized variables (UNINIT) >>> Using uninitialized value "*path" when calling "acpigen_emit_namestring". 307 acpigen_emit_namestring(path); 308 break; 309 310 default: 311 /* Unhandled */ 312 printk(BIOS_WARNING, ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u15810271.ct.sendgrid.net/ls/click?upn=HRESupC-2F2Czv4BOaCWWCy7my0P…

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Running coreboot on M1 Mac or Arm64 platforms
by Branden Waldner 13 May '22

13 May '22

> Dear coreboot community, > I just started coreboot and getting the hang of it. I am considering getting a M1 MacBook for my > development work. > May I will will coreboot work well on M1 MacBook? I am doing the coreboot work for x86 > platforms. > I understand that coreboot is using i386 cross GC Compiler, does it works on M1? There is > another option that I could run a Linux OS virtual box on M1 but it will still run on arm64 arc. > Thanks for the help. > Best Regards, > Cory I've built crossgcc-i386 on armv6 (raspberry pi B) and it produced a working rom for my asus/p2b. I don't know about how well it would work with any other targets though. Branden

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Will coreboot work on my machine? DELL XPS m1330
by Mateusz Kolbusz 12 May '22

12 May '22

1. a) Vendor: Dell b) Motherboard product: 0N6705 vendor: Dell Inc. c) Processor: Intel(R) Core(TM)2 Duo CPU T5800 @ 2.00GHz d) Bridge: Mobile PM965/GM965/GL960 Memory Controller Hub e) GPU: Mobile GM965/GL960 Integrated Graphics Controller (primary) 2. lspci -tvnn -[0000:00]-+-00.0 Intel Corporation Mobile PM965/GM965/GL960 Memory Controller Hub [8086:2a00] +-02.0 Intel Corporation Mobile GM965/GL960 Integrated Graphics Controller (primary) [8086:2a02] +-02.1 Intel Corporation Mobile GM965/GL960 Integrated Graphics Controller (secondary) [8086:2a03] +-1a.0 Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #4 [8086:2834] +-1a.1 Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #5 [8086:2835] +-1a.7 Intel Corporation 82801H (ICH8 Family) USB2 EHCI Controller #2 [8086:283a] +-1b.0 Intel Corporation 82801H (ICH8 Family) HD Audio Controller [8086:284b] +-1c.0-[0b]-- +-1c.1-[0c]----00.0 Qualcomm Atheros AR928X Wireless Network Adapter (PCI-Express) [168c:002a] +-1c.3-[0d-0e]-- +-1c.5-[09]----00.0 Broadcom Inc. and subsidiaries NetLink BCM5906M Fast Ethernet PCI Express [14e4:1713] +-1d.0 Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #1 [8086:2830] +-1d.1 Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #2 [8086:2831] +-1d.2 Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #3 [8086:2832] +-1d.7 Intel Corporation 82801H (ICH8 Family) USB2 EHCI Controller #1 [8086:2836] +-1e.0-[03]--+-01.0 Ricoh Co Ltd R5C832 IEEE 1394 Controller [1180:0832] | +-01.1 Ricoh Co Ltd R5C822 SD/SDIO/MMC/MS/MSPro Host Adapter [1180:0822] | +-01.2 Ricoh Co Ltd R5C592 Memory Stick Bus Host Adapter [1180:0592] | \-01.3 Ricoh Co Ltd xD-Picture Card Controller [1180:0852] +-1f.0 Intel Corporation 82801HM (ICH8M) LPC Interface Controller [8086:2815] +-1f.1 Intel Corporation 82801HM/HEM (ICH8M/ICH8M-E) IDE Controller [8086:2850] +-1f.2 Intel Corporation 82801HM/HEM (ICH8M/ICH8M-E) SATA Controller [AHCI mode] [8086:2829] \-1f.3 Intel Corporation 82801H (ICH8 Family) SMBus Controller [8086:283e] 3. Superiotool -dV : [mateusz@mateusz superiotool]$ sudo superiotool -dV superiotool r4.16-884-gd4cdf5d581 Probing for ALi Super I/O at 0x3f0... Failed. Returned data: id=0xffff, rev=0xff Probing for ALi Super I/O at 0x370... Failed. Returned data: id=0xffff, rev=0xff Probing for Aspeed Super I/O at 0x2e... Failed. Returned data: scratch registers all read as 0xff Probing for Aspeed Super I/O at 0x4e... Failed. Returned data: scratch registers all read as 0xff Probing for Exar Super I/O at 0x2e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Exar Super I/O at 0x4e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0xffff, id=0xffff Probing for ITE Super I/O (init=standard) at 0x20e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8502e) at 0x20e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x20e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x20e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8987e) at 0x20e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x20e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=standard) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8502e) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8987e) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=standard) at 0x2e... Failed. Returned data: id=0x3201, rev=0x0 Probing for ITE Super I/O (init=it8502e) at 0x2e... Failed. Returned data: id=0x3201, rev=0x0 Probing for ITE Super I/O (init=it8761e) at 0x2e... Failed. Returned data: id=0x3201, rev=0x0 Probing for ITE Super I/O (init=it8228e) at 0x2e... Failed. Returned data: id=0x3201, rev=0x0 Probing for ITE Super I/O (init=it8987e) at 0x2e... Failed. Returned data: id=0x3201, rev=0x0 Probing for ITE Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id=0x3201, rev=0x0 Probing for ITE Super I/O (init=standard) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8502e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8987e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8661f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8671f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=standard) at 0x6e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8502e) at 0x6e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x6e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x6e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8987e) at 0x6e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x6e... Failed. Returned data: id=0xffff, rev=0xf Probing for NSC Super I/O at 0x2e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x4e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x15c... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x164e... Failed. Returned data: port=0xff, port+1=0xff Probing for Nuvoton Super I/O at 0x164e... Failed. Returned data: chip_id=0xffff Probing for Nuvoton Super I/O (sid=0xfc) at 0x164e... Failed. Returned data: sid=0xff, id=0xffff, rev=0x00 Probing for Nuvoton Super I/O at 0x2e... Failed. Returned data: chip_id=0xffff Probing for Nuvoton Super I/O (sid=0xfc) at 0x2e... Failed. Returned data: sid=0xff, id=0xffff, rev=0x00 Probing for Nuvoton Super I/O at 0x4e... Failed. Returned data: chip_id=0xffff Probing for Nuvoton Super I/O (sid=0xfc) at 0x4e... Failed. Returned data: sid=0xff, id=0xffff, rev=0x00 Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e... Failed. Returned data: id=0x32, rev=0x01 Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e... Failed. Returned data: id=0x00, rev=0x00 Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for VIA Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for VIA Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for VIA Super I/O (init=vt82c686) at 0x3f0... PCI device 1106:0686 not found. Probing for AMD EC Super I/O at 0xaa... Probing for Server Engines Super I/O at 0x2e... Failed. Returned data: id=0xffff, rev=0xff Probing for Infineon Super I/O at 0x2e... Failed. Returned data: id=0x32, rev=0x01 Probing for Infineon Super I/O at 0x4e... Failed. Returned data: id=0xff, rev=0xff No Super I/O found 4. flashrom -p internal -V flashrom v1.2 on Linux 5.17.5-arch1-1 (x86_64) flashrom is free software, get the source code at https://flashrom.org flashrom was built with libpci 3.7.0, GCC 11.2.0, little endian Command line (3 args): flashrom -p internal -V Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). Initializing internal programmer /sys/class/mtd/mtd0 does not exist No coreboot table found. Using Internal DMI decoder. DMI string chassis-type: "Portable" Laptop detected via DMI. DMI string system-manufacturer: "Dell Inc." DMI string system-product-name: "XPS M1330 " DMI string system-version: "Not Specified" DMI string baseboard-manufacturer: "Dell Inc." DMI string baseboard-product-name: "0N6705" DMI string baseboard-version: " " Found chipset "Intel ICH8M" with PCI ID 8086:2815. Enabling flash write... Root Complex Register Block address = 0xfed18000 Error accessing ICH RCRB, 0x4000 bytes at 0x00000000fed18000 /dev/mem mmap failed: Operation not permitted FAILED! FATAL ERROR! Error: Programmer initialization failed. It's has supported chipsed but not motherboard will it work anyway?

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[coreboot - Bug #343] Fails to load GRUB payload: CPU Index 0 - APIC 0 Unexpected Exception:6 @ 10:00009016 - Halting
by Arthur Heymans 10 May '22

10 May '22

Issue #343 has been updated by Arthur Heymans. Bisected. 4ea7bae51f97e49c84dc67ea30b466ca8633b9f6 is the culprit in grub. ---------------------------------------- Bug #343: Fails to load GRUB payload: CPU Index 0 - APIC 0 Unexpected Exception:6 @ 10:00009016 - Halting https://ticket.coreboot.org/issues/343#change-923 * Author: Paul Menzel * Status: New * Priority: Normal * Start date: 2022-03-30 ---------------------------------------- coreboot emulation/qemu-i440fx is unable to load GRUB payload. It works with SeaBIOS. ``` FMAP REGION: COREBOOT Name Offset Type Size Comp cbfs master header 0x0 cbfs header 32 none fallback/romstage 0x80 stage 21944 none fallback/ramstage 0x56c0 stage 62048 LZMA (139536 decompressed) config 0x14980 raw 428 none revision 0x14b80 raw 716 none build_info 0x14e80 raw 112 none fallback/dsdt.aml 0x14f40 raw 4044 none cmos_layout.bin 0x15f40 cmos_layout 640 none fallback/postcar 0x16200 stage 23328 none fallback/payload 0x1bd80 simple elf 460906 none (empty) 0x8c640 null 3603556 none bootblock 0x3fc2c0 bootblock 15104 none ``` ``` […] [NOTE ] coreboot-4.16-415-ga84c00c9ce Wed Mar 30 01:18:14 UTC 2022 ramstage starting (log level: 7)... […] [INFO ] Timestamp - selfboot jump: 965162845 [EMERG] CPU Index 0 - APIC 0 Unexpected Exception:6 @ 10:00009016 - Halting [EMERG] Code: 0 eflags: 00010002 cr2: 00000000 [EMERG] eax: 00000000 ebx: 3ffbdc18 ecx: 0001ac27 edx: 000000ff [EMERG] edi: 3ffbdc00 esi: 3ffbdbf0 ebp: 000001e4 esp: 3ffc3fbc [EMERG] 0x00008fd0: 00 00 00 00 00 00 00 00 [EMERG] 0x00008fd8: 00 00 00 00 00 00 00 00 [EMERG] 0x00008fe0: 00 00 00 00 00 00 00 00 [EMERG] 0x00008fe8: 00 00 00 00 00 00 00 00 [EMERG] 0x00008ff0: 00 00 00 00 00 00 00 00 [EMERG] 0x00008ff8: 00 00 00 00 00 00 00 00 [EMERG] 0x00009000: 52 52 68 27 ac 01 00 6a [EMERG] 0x00009008: 0b e8 5e cd 00 00 83 c4 [EMERG] 0x00009010: 10 a0 00 00 00 00 0f 0b [EMERG] 0x00009018: 51 51 68 6a a2 01 00 6a [EMERG] 0x00009020: 0b e8 46 cd 00 00 83 c4 [EMERG] 0x00009028: 10 eb e6 90 bc f0 ff 07 [EMERG] 0x00009030: 00 e9 c7 d7 00 00 66 90 [EMERG] 0x00009038: 02 b0 ad 1b 02 00 00 00 [EMERG] 0x00009040: fc 4f 52 e4 55 57 56 53 [EMERG] 0x00009048: 83 ec 1c 8b 5c 24 30 8b [EMERG] 0x3ffc4038: 0x00000002 [EMERG] 0x3ffc4034: 0x00000003 [EMERG] 0x3ffc4030: 0x00000000 [EMERG] 0x3ffc402c: 0x00000000 [EMERG] 0x3ffc4028: 0x00000000 [EMERG] 0x3ffc4024: 0x00000000 [EMERG] 0x3ffc4020: 0x00000000 [EMERG] 0x3ffc401c: 0x00000000 [EMERG] 0x3ffc4018: 0x00000000 [EMERG] 0x3ffc4014: 0x00000000 [EMERG] 0x3ffc4010: 0x00000000 [EMERG] 0x3ffc400c: 0x00000000 [EMERG] 0x3ffc4008: 0x00000000 [EMERG] 0x3ffc4004: 0x00000000 [EMERG] 0x3ffc4000: 0x00000000 [EMERG] 0x3ffc3ffc: 0x00000000 [EMERG] 0x3ffc3ff8: 0x3ffbd4e8 [EMERG] 0x3ffc3ff4: 0xdeadbeef [EMERG] 0x3ffc3ff0: 0xdeadbeef [EMERG] 0x3ffc3fec: 0x3ff9e061 [EMERG] 0x3ffc3fe8: 0x3ffa1f19 [EMERG] 0x3ffc3fe4: 0x00018f20 [EMERG] 0x3ffc3fe0: 0x3ffdcfd4 [EMERG] 0x3ffc3fdc: 0x3ffc4000 [EMERG] 0x3ffc3fd8: 0x3ffd63ac [EMERG] 0x3ffc3fd4: 0x00000000 [EMERG] 0x3ffc3fd0: 0x3ffa1fe5 [EMERG] 0x3ffc3fcc: 0x3ffa2139 [EMERG] 0x3ffc3fc8: 0x3ffbdc24 [EMERG] 0x3ffc3fc4: 0x3ffa4303 [EMERG] 0x3ffc3fc0: 0x3ff95000 [EMERG] 0x3ffc3fbc: 0x3ffac8e4 <-esp ``` ---Files-------------------------------- coreboot.log (17.2 KB) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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[coreboot - Bug #322] (Resolved) Image fails to boot on Thinkpad X201 if built with GCC 11
by Arthur Heymans 10 May '22

10 May '22

Issue #322 has been updated by Arthur Heymans. Status changed from New to Resolved Fixed by https://review.coreboot.org/c/coreboot/+/61938 ---------------------------------------- Bug #322: Image fails to boot on Thinkpad X201 if built with GCC 11 https://ticket.coreboot.org/issues/322#change-922 * Author: Stefan Ott * Status: Resolved * Priority: Normal * Start date: 2021-11-17 ---------------------------------------- I can't seem to build a bootable image for the Thinkpad X201 with the new GCC-11-based toolchain. Rather than booting up, the machine just flashes a bunch of LEDs and then resets itself. If I use the old toolchain with GCC 8, the image works just fine. Unfortunately I don't have a console on this machine so I don't have any logs. I don't know whether is is relevant or not, but cbfstool reports different layouts for the images: $ util/cbfstool/cbfstool coreboot-gcc-8.rom print FMAP REGION: COREBOOT Name Offset Type Size Comp cbfs master header 0x0 cbfs header 32 none fallback/romstage 0x80 stage 65328 none cpu_microcode_blob.bin 0x10040 microcode 13312 none fallback/ramstage 0x13480 stage 106502 LZMA (227804 decompressed) vgaroms/seavgabios.bin 0x2d500 raw 28160 none config 0x34340 raw 643 none revision 0x34600 raw 716 none build_info 0x34900 raw 101 none fallback/dsdt.aml 0x349c0 raw 14119 none cmos_layout.bin 0x38140 cmos_layout 1612 none fallback/postcar 0x387c0 stage 20024 none fallback/payload 0x3d640 simple elf 69197 none payload_config 0x4e4c0 raw 1728 none payload_revision 0x4ebc0 raw 237 none etc/ps2-keyboard-spinup 0x4ed00 raw 8 none (empty) 0x4ed40 null 641380 none bootblock 0xeb6c0 bootblock 18176 none $ util/cbfstool/cbfstool coreboot-gcc-11.rom print FMAP REGION: COREBOOT Name Offset Type Size Comp cbfs master header 0x0 cbfs header 32 fallback/romstage 0x80 stage 63664 none cpu_microcode_blob.bin 0xf9c0 microcode 13312 none fallback/ramstage 0x12e00 stage 106836 LZMA (228284 decompressed) vgaroms/seavgabios.bin 0x2cfc0 raw 28160 none config 0x33e00 raw 643 none revision 0x340c0 raw 716 none build_info 0x343c0 raw 101 none fallback/dsdt.aml 0x34480 raw 14119 none cmos_layout.bin 0x37c00 cmos_layout 1612 none fallback/postcar 0x38280 stage 19976 none fallback/payload 0x3d100 simple elf 69050 none payload_config 0x4df00 raw 1728 none payload_revision 0x4e600 raw 236 none etc/ps2-keyboard-spinup 0x4e740 raw 8 none (empty) 0x4e780 null 642916 none bootblock 0xeb700 bootblock 18112 none -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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Open letter to Intel regarding the PSE on Elkhart Lake
by Zeh, Werner 10 May '22

10 May '22

Dear coreboot community. I guess the most of you have seen the tension that was introduced to the community once Intel started to enable the Programmable Service Engine on the new IOTG SoC called Elkhart Lake (for reference, please see [1]). One of the outcome of this difficulties was to ask Intel for open sourcing the PSE code in order to avoid a new blob being introduced to coreboot. I took this action item and reached out to Intel in this regard. As a result I have had two meetings with the responsible people at Intel and they started to look into this request. So as of now Intel is analyzing the code to understand what needs to be done to open source it. What has been mentioned by Intel to me is that up to now nobody else have ever requested this for the PSE. Furthermore Intel let me know that it would be easier to convince the management layer to spend work on open sourcing the code if there would be more people from different companies requesting the same. My first guess was: we can do this! Therefore I have drafted up an open letter which I would like share with all of you: https://openletter.earth/request-for-opening-the-source-code-for-the-pse-on- elkhart-lake-26bad82a The wording have now been reviewed for two days between different parties and I would like to keep it as it is in order to get it done in time. This is now the moment where you can raise your voice! Please have a look at the open letter and sign it if you agree with the terms and if you support this approach. The more people we get the higher are our chances to be visible as an open source community. And it would be really helpful if we could get this letter signed by companies, this will for sure increase the traction of this request. I will keep this letter in "signing" state until 2021-12-09 07:00 am German time. Once we are there I will hand it over to Intel. Thank you for your support in advance Werner [1] <https://review.coreboot.org/c/coreboot/+/55367> https://review.coreboot.org/c/coreboot/+/55367

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New Defects reported by Coverity Scan for coreboot
by scan-admin＠coverity.com 06 May '22

06 May '22

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 1 new defect(s) introduced to coreboot found with Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 1 of 1 defect(s) ** CID 1488487: Integer handling issues (CONSTANT_EXPRESSION_RESULT) /src/soc/amd/common/block/psp/psp_gen2.c: 57 in wr_mbox_buffer_ptr() ________________________________________________________________________________________________________ *** CID 1488487: Integer handling issues (CONSTANT_EXPRESSION_RESULT) /src/soc/amd/common/block/psp/psp_gen2.c: 57 in wr_mbox_buffer_ptr() 51 tmp.val = smn_read32(SMN_PSP_PUBLIC_BASE + PSP_MAILBOX_COMMAND_OFFSET); 52 return !!tmp.fields.recovery; 53 } 54 55 static void wr_mbox_buffer_ptr(void *buffer) 56 { >>> CID 1488487: Integer handling issues (CONSTANT_EXPRESSION_RESULT) >>> "(uint64_t)(uintptr_t)buffer >> 32" is 0 regardless of the values of its operands. This occurs as an initializer. 57 const uint32_t buf_addr_h = (uint64_t)(uintptr_t)buffer >> 32; 58 const uint32_t buf_addr_l = (uint64_t)(uintptr_t)buffer & 0xffffffff; 59 smn_write32(SMN_PSP_PUBLIC_BASE + PSP_MAILBOX_BUFFER_H_OFFSET, buf_addr_h); 60 smn_write32(SMN_PSP_PUBLIC_BASE + PSP_MAILBOX_BUFFER_L_OFFSET, buf_addr_l); 61 } 62 ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u15810271.ct.sendgrid.net/ls/click?upn=HRESupC-2F2Czv4BOaCWWCy7my0P…

1 0

Running coreboot on M1 Mac or Arm64 platforms
by uplift.06several＠icloud.com 06 May '22

06 May '22

Dear coreboot community, I just started coreboot and getting the hang of it. I am considering getting a M1 MacBook for my development work. May I will will coreboot work well on M1 MacBook? I am doing the coreboot work for x86 platforms. I understand that coreboot is using i386 cross GC Compiler, does it works on M1? There is another option that I could run a Linux OS virtual box on M1 but it will still run on arm64 arc. Thanks for the help. Best Regards, Cory

1 0

Systems that use coreboot
by Valerii Gugnin 06 May '22

06 May '22

Hello! I have some questions about coreboot: What are the most popular systems on which coreboot is typically used? What mainboards, southbridges, SoCs etc do these systems use? What is the most used part of code (for which system) in coreboot?

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