coreboot

coreboot@coreboot.org

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39654 discussions

Press ESC for boot menu
by Mahmut Olger 27 Dec '22

27 Dec '22

Hello, We are using intel atom C3558 denverton_NS platform. This platform is booting with coreboot4.16. Payload of coreboot is Seabios. Openbsd running in our board. Coreboot is booting successfully. I press ESC key when I see "Press ESC for boot menu" print but I can not select boot device. It is booting automatically. I think the keyboard could not be enabled. How can i solve this problem. You can find seabios config file above and coreboot config file. Mahmut ÖLGER Embedded Software Engineer.

2 1

LinuxBIOS
by The Original Linux Fan 27 Dec '22

27 Dec '22

Hi all, Many years ago I was tracking the LinuxBIOS project and was very keenly interested in it. Now, it seems that systems have gotten ten times slower to boot. I have an HP Z840 workstation. It is a 56 processor machine and is very slow to boot. I don't have a lot of money and wouldn't want to brick it, but I am interested in attempting to get one machine working with coreboot. Anyway, if anybody has any time for a newbie, I would appreciate any comments. 73, Linuxfan

1 0

Cisco Meraki use coreboot in some MX products and will not provide the source code
by Hal Martin 22 Dec '22

22 Dec '22

Hello, Several Cisco Meraki products (MX84, MX250) are using the coreboot bootloader. Meraki are also distributing coreboot builds for these products via their update mechanism. In October 2021, I requested the corresponding coreboot source code for the MX84 from open-source(a)meraki.com. Another individual requested the coreboot source code for the MX250 around the same time. We own the devices in quesiton. To date, Meraki have not provided the source code or provided an explanation as to the delay in providing the source code. The last reply I received was in January, and they have not replied to any of my follow up requests. As coreboot is GPL licensed software, I wanted to inform the coreboot community that I believe Cisco Meraki are not acting in good faith and are, in my opinion, violating the GPL by not providing the coreboot source code upon request. Kind regards, Hal Martin

4 4

New Defects reported by Coverity Scan for coreboot
by scan-admin＠coverity.com 20 Dec '22

20 Dec '22

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 4 new defect(s) introduced to coreboot found with Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 4 of 4 defect(s) ** CID 1501609: Control flow issues (NO_EFFECT) /src/northbridge/intel/haswell/native_raminit/raminit_main.c: 65 in try_raminit() ________________________________________________________________________________________________________ *** CID 1501609: Control flow issues (NO_EFFECT) /src/northbridge/intel/haswell/native_raminit/raminit_main.c: 65 in try_raminit() 59 { 60 const struct task_entry *const schedule = cold_boot; 61 const size_t length = ARRAY_SIZE(cold_boot); 62 63 enum raminit_status status = RAMINIT_STATUS_UNSPECIFIED_ERROR; 64 >>> CID 1501609: Control flow issues (NO_EFFECT) >>> This less-than-zero comparison of an unsigned value is never true. "i < 0UL". 65 for (size_t i = 0; i < length; i++) { 66 const struct task_entry *const entry = &schedule[i]; 67 assert(entry); 68 assert(entry->name); 69 if (!entry->is_enabled) 70 continue; ** CID 1501608: Control flow issues (DEADCODE) /src/northbridge/intel/haswell/native_raminit/raminit_main.c: 66 in try_raminit() ________________________________________________________________________________________________________ *** CID 1501608: Control flow issues (DEADCODE) /src/northbridge/intel/haswell/native_raminit/raminit_main.c: 66 in try_raminit() 60 const struct task_entry *const schedule = cold_boot; 61 const size_t length = ARRAY_SIZE(cold_boot); 62 63 enum raminit_status status = RAMINIT_STATUS_UNSPECIFIED_ERROR; 64 65 for (size_t i = 0; i < length; i++) { >>> CID 1501608: Control flow issues (DEADCODE) >>> Execution cannot reach this statement: "entry = &schedule[i];". 66 const struct task_entry *const entry = &schedule[i]; 67 assert(entry); 68 assert(entry->name); 69 if (!entry->is_enabled) 70 continue; 71 ** CID 1501607: Code maintainability issues (UNUSED_VALUE) /src/northbridge/intel/haswell/native_raminit/raminit_native.c: 200 in perform_raminit() ________________________________________________________________________________________________________ *** CID 1501607: Code maintainability issues (UNUSED_VALUE) /src/northbridge/intel/haswell/native_raminit/raminit_native.c: 200 in perform_raminit() 194 /* 195 * The 'other' success value is to report loss of memory 196 * consistency to ME if warm boot was downgraded to cold. 197 */ 198 uint8_t me_status; 199 if (BOOTMODE_WARM == orig_bootmode && BOOTMODE_COLD == bootmode) >>> CID 1501607: Code maintainability issues (UNUSED_VALUE) >>> Assigning value "3" to "me_status" here, but that stored value is overwritten before it can be used. 200 me_status = ME_INIT_STATUS_SUCCESS_OTHER; 201 else 202 me_status = ME_INIT_STATUS_SUCCESS; 203 204 /** TODO: Remove this once raminit is implemented **/ 205 me_status = ME_INIT_STATUS_ERROR; ** CID 1501606: Integer handling issues (BAD_SHIFT) /src/lib/fw_config.c: 69 in fw_config_get_field() ________________________________________________________________________________________________________ *** CID 1501606: Integer handling issues (BAD_SHIFT) /src/lib/fw_config.c: 69 in fw_config_get_field() 63 { 64 /* If fw_config is not provisioned, then there is nothing to get. */ 65 if (!fw_config_is_provisioned()) 66 return UNDEFINED_FW_CONFIG; 67 68 int shift = __ffs64(field->mask); >>> CID 1501606: Integer handling issues (BAD_SHIFT) >>> In expression "(fw_config_get() & field->mask) >> shift", shifting by a negative amount has undefined behavior. The shift amount, "shift", is -1. 69 const uint64_t value = (fw_config_get() & field->mask) >> shift; 70 71 printk(BIOS_INFO, "fw_config get field name=%s, mask=0x%" PRIx64 ", shift=%d, value=0x%" 72 PRIx64 "\n", field->field_name, field->mask, shift, value); 73 74 return value; ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u15810271.ct.sendgrid.net/ls/click?upn=HRESupC-2F2Czv4BOaCWWCy7my0P…

1 0

There was always microcode
by Peter Stuge 20 Dec '22

20 Dec '22

Recommend these great posts with technical detail and history: https://www.righto.com/2020/06/a-look-at-die-of-8086-processor.html https://www.reenigne.org/blog/8086-microcode-disassembled/ https://www.righto.com/2022/11/how-8086-processors-microcode-engine.html If ever there was a textbook example of a temporary solution becoming permanent then 8086 must be it: "Because the iAPX 432 was behind schedule, Intel decided in 1976 that they needed a simple, stop-gap processor to sell until the iAPX 432 was ready. Intel rapidly designed the 8086 as a 16-bit processor somewhat compatible with the 8-bit 8080, released in 1978." 45 years later, https://justine.lol/ape.html says: "Outside phones routers mainframes and cars, the consensus surrounding x86 is so strong, that I'd compare it to the Tower of Babel." Kind regards and happy holidays //Peter

1 0

[coreboot - Bug #444] (New) Flaky gitconfig tests are breaking builds
by Martin Roth 20 Dec '22

20 Dec '22

Issue #444 has been reported by Martin Roth. ---------------------------------------- Bug #444: Flaky gitconfig tests are breaking builds https://ticket.coreboot.org/issues/444 * Author: Martin Roth * Status: New * Priority: Normal * Target version: none * Start date: 2022-12-20 ---------------------------------------- The gitconfig tests are failing when they can't delete a directory they created in /tmp, and this is causing builds to fail randomly. Because it's not a part of the test itself, but part of the cleanup, the failure doesn't get captured, and jenkins appears to be failing for no good reason. Someone should figure out what's causing the rm -rf to fail and fix it so that the builders stop failing. -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

1 0

[coreboot - Bug #297] T440P card reader is broken.
by Martin Kepplinger 19 Dec '22

19 Dec '22

Issue #297 has been updated by Martin Kepplinger. just for the record, `watch -n 1 "cat /proc/interrupts | grep -i pci"` shows that rtsx_pci interrupts are being generated on card insert and removal. And this is them (debug output enabled using `echo -n 'file drivers/mmc/* +p' > /sys/kernel/debug/dynamic_debug/control` ) Card inserted: `[31506.595029] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: sdmmc_get_cd: RTSX_BIPR = 0x00000000` Card removed: `[31652.179942] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: sdmmc_get_cd: RTSX_BIPR = 0x00010000 [31652.179945] mmc0: mmc_rescan_try_freq: trying to init card at 400000 Hz [31652.179947] mmc0: clock 0Hz busmode 2 powermode 1 cs 0 Vdd 21 width 1 timing 0 [31652.317025] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: sdmmc_switch_voltage: signal_voltage = 0 [31652.317279] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: Initial signal voltage of 3.3v [31652.323574] mmc0: clock 400000Hz busmode 2 powermode 2 cs 0 Vdd 21 width 1 timing 0 [31652.330058] mmc0: starting CMD52 arg 00000c00 flags 00000195 [31652.330130] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: sd_send_cmd_get_rsp: SD/MMC CMD 52, arg = 0x00000c00 [31652.431890] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: rtsx_pci_send_cmd error (err = -110) [31652.431895] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: CMD 52 0x00000c00 error(-110) [31652.431900] mmc0: req done (CMD52): -110: 00000000 00000000 00000000 00000000 [31652.431911] mmc0: starting CMD52 arg 80000c08 flags 00000195 [31652.431943] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: sd_send_cmd_get_rsp: SD/MMC CMD 52, arg = 0x80000c08 [31652.535914] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: rtsx_pci_send_cmd error (err = -110) [31652.535917] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: CMD 52 0x80000c08 error(-110) [31652.535920] mmc0: req done (CMD52): -110: 00000000 00000000 00000000 00000000 [31652.535925] mmc0: clock 400000Hz busmode 2 powermode 2 cs 1 Vdd 21 width 1 timing 0 [31652.537271] mmc0: starting CMD0 arg 00000000 flags 000000c0 [31652.537301] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: sd_send_cmd_get_rsp: SD/MMC CMD 0, arg = 0x00000000 [31652.537629] mmc0: req done (CMD0): 0: 00000000 00000000 00000000 00000000 [31652.538956] mmc0: clock 400000Hz busmode 2 powermode 2 cs 0 Vdd 21 width 1 timing 0 [31652.540314] mmc0: starting CMD8 arg 000001aa flags 000002f5 [31652.540343] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: sd_send_cmd_get_rsp: SD/MMC CMD 8, arg = 0x000001aa [31652.643922] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: rtsx_pci_send_cmd error (err = -110) [31652.643928] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: CMD 8 0x000001aa error(-110) [31652.643934] mmc0: req done (CMD8): -110: 00000000 00000000 00000000 00000000 [31652.643949] mmc0: starting CMD5 arg 00000000 flags 000002e1 [31652.643987] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: sd_send_cmd_get_rsp: SD/MMC CMD 5, arg = 0x00000000 [31652.747912] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: rtsx_pci_send_cmd error (err = -110) [31652.747916] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: CMD 5 0x00000000 error(-110) [31652.747927] mmc0: req failed (CMD5): -110, retrying... [31652.747960] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: sd_send_cmd_get_rsp: SD/MMC CMD 5, arg = 0x00000000 [31652.851913] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: rtsx_pci_send_cmd error (err = -110) [31652.851917] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: CMD 5 0x00000000 error(-110) [31652.851925] mmc0: req failed (CMD5): -110, retrying... [31652.851958] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: sd_send_cmd_get_rsp: SD/MMC CMD 5, arg = 0x00000000 [31652.955952] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: rtsx_pci_send_cmd error (err = -110) [31652.955960] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: CMD 5 0x00000000 error(-110) [31652.955977] mmc0: req failed (CMD5): -110, retrying... [31652.956047] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: sd_send_cmd_get_rsp: SD/MMC CMD 5, arg = 0x00000000 [31653.059989] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: rtsx_pci_send_cmd error (err = -110) [31653.059996] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: CMD 5 0x00000000 error(-110) [31653.060002] mmc0: req done (CMD5): -110: 00000000 00000000 00000000 00000000 [31653.060050] mmc0: starting CMD55 arg 00000000 flags 000000f5 [31653.060098] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: sd_send_cmd_get_rsp: SD/MMC CMD 55, arg = 0x00000000 [31653.163934] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: rtsx_pci_send_cmd error (err = -110) [31653.163938] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: CMD 55 0x00000000 error(-110) [31653.163940] mmc0: req done (CMD55): -110: 00000000 00000000 00000000 00000000 [31653.163948] mmc0: starting CMD55 arg 00000000 flags 000000f5 [31653.163980] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: sd_send_cmd_get_rsp: SD/MMC CMD 55, arg = 0x00000000 [31653.267888] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: rtsx_pci_send_cmd error (err = -110) [31653.267893] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: CMD 55 0x00000000 error(-110) [31653.267898] mmc0: req done (CMD55): -110: 00000000 00000000 00000000 00000000 [31653.267909] mmc0: starting CMD55 arg 00000000 flags 000000f5 [31653.267951] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: sd_send_cmd_get_rsp: SD/MMC CMD 55, arg = 0x00000000 [31653.371899] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: rtsx_pci_send_cmd error (err = -110) [31653.371902] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: CMD 55 0x00000000 error(-110) [31653.371905] mmc0: req done (CMD55): -110: 00000000 00000000 00000000 00000000 [31653.371932] mmc0: starting CMD55 arg 00000000 flags 000000f5 [31653.371991] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: sd_send_cmd_get_rsp: SD/MMC CMD 55, arg = 0x00000000 [31653.475940] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: rtsx_pci_send_cmd error (err = -110) [31653.475944] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: CMD 55 0x00000000 error(-110) [31653.475946] mmc0: req done (CMD55): -110: 00000000 00000000 00000000 00000000 [31653.475955] mmc0: clock 400000Hz busmode 1 powermode 2 cs 0 Vdd 21 width 1 timing 0 [31653.476044] mmc0: starting CMD1 arg 00000000 flags 000000e1 [31653.476070] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: sd_send_cmd_get_rsp: SD/MMC CMD 1, arg = 0x00000000 [31653.579880] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: rtsx_pci_send_cmd error (err = -110) [31653.579884] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: CMD 1 0x00000000 error(-110) [31653.579886] mmc0: req done (CMD1): -110: 00000000 00000000 00000000 00000000 [31653.579893] mmc0: clock 0Hz busmode 2 powermode 0 cs 0 Vdd 0 width 1 timing 0 [31653.581258] mmc0: mmc_rescan_try_freq: trying to init card at 300000 Hz [31653.581260] mmc0: clock 0Hz busmode 2 powermode 1 cs 0 Vdd 21 width 1 timing 0 [31653.716976] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: sdmmc_switch_voltage: signal_voltage = 0 [31653.717214] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: Initial signal voltage of 3.3v [31653.723505] mmc0: clock 300000Hz busmode 2 powermode 2 cs 0 Vdd 21 width 1 timing 0 [31653.729900] mmc0: starting CMD52 arg 00000c00 flags 00000195 [31653.729938] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: sd_send_cmd_get_rsp: SD/MMC CMD 52, arg = 0x00000c00 [31653.831906] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: rtsx_pci_send_cmd error (err = -110) [31653.831913] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: CMD 52 0x00000c00 error(-110) [31653.831919] mmc0: req done (CMD52): -110: 00000000 00000000 00000000 00000000 [31653.831933] mmc0: starting CMD52 arg 80000c08 flags 00000195 [31653.831989] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: sd_send_cmd_get_rsp: SD/MMC CMD 52, arg = 0x80000c08 [31653.935944] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: rtsx_pci_send_cmd error (err = -110) [31653.935955] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: CMD 52 0x80000c08 error(-110) [31653.935964] mmc0: req done (CMD52): -110: 00000000 00000000 00000000 00000000 [31653.935983] mmc0: clock 300000Hz busmode 2 powermode 2 cs 1 Vdd 21 width 1 timing 0 [31653.937344] mmc0: starting CMD0 arg 00000000 flags 000000c0 [31653.937429] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: sd_send_cmd_get_rsp: SD/MMC CMD 0, arg = 0x00000000 [31653.937750] mmc0: req done (CMD0): 0: 00000000 00000000 00000000 00000000 [31653.939044] mmc0: clock 300000Hz busmode 2 powermode 2 cs 0 Vdd 21 width 1 timing 0 [31653.940377] mmc0: starting CMD8 arg 000001aa flags 000002f5 [31653.940445] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: sd_send_cmd_get_rsp: SD/MMC CMD 8, arg = 0x000001aa [31654.043966] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: rtsx_pci_send_cmd error (err = -110) [31654.043972] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: CMD 8 0x000001aa error(-110) [31654.043977] mmc0: req done (CMD8): -110: 00000000 00000000 00000000 00000000 [31654.043989] mmc0: starting CMD5 arg 00000000 flags 000002e1 [31654.044062] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: sd_send_cmd_get_rsp: SD/MMC CMD 5, arg = 0x00000000 [31654.147947] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: rtsx_pci_send_cmd error (err = -110) [31654.147951] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: CMD 5 0x00000000 error(-110) [31654.147959] mmc0: req failed (CMD5): -110, retrying... [31654.147991] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: sd_send_cmd_get_rsp: SD/MMC CMD 5, arg = 0x00000000 [31654.251943] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: rtsx_pci_send_cmd error (err = -110) [31654.251946] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: CMD 5 0x00000000 error(-110) [31654.251953] mmc0: req failed (CMD5): -110, retrying... [31654.251984] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: sd_send_cmd_get_rsp: SD/MMC CMD 5, arg = 0x00000000 [31654.355903] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: rtsx_pci_send_cmd error (err = -110) [31654.355909] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: CMD 5 0x00000000 error(-110) [31654.355920] mmc0: req failed (CMD5): -110, retrying... [31654.355954] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: sd_send_cmd_get_rsp: SD/MMC CMD 5, arg = 0x00000000 [31654.459942] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: rtsx_pci_send_cmd error (err = -110) [31654.459945] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: CMD 5 0x00000000 error(-110) [31654.459948] mmc0: req done (CMD5): -110: 00000000 00000000 00000000 00000000 [31654.459957] mmc0: starting CMD55 arg 00000000 flags 000000f5 [31654.459988] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: sd_send_cmd_get_rsp: SD/MMC CMD 55, arg = 0x00000000 [31654.563904] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: rtsx_pci_send_cmd error (err = -110) [31654.563911] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: CMD 55 0x00000000 error(-110) [31654.563915] mmc0: req done (CMD55): -110: 00000000 00000000 00000000 00000000 [31654.563929] mmc0: starting CMD55 arg 00000000 flags 000000f5 [31654.563970] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: sd_send_cmd_get_rsp: SD/MMC CMD 55, arg = 0x00000000 [31654.667932] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: rtsx_pci_send_cmd error (err = -110) [31654.667939] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: CMD 55 0x00000000 error(-110) [31654.667946] mmc0: req done (CMD55): -110: 00000000 00000000 00000000 00000000 [31654.667961] mmc0: starting CMD55 arg 00000000 flags 000000f5 [31654.668048] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: sd_send_cmd_get_rsp: SD/MMC CMD 55, arg = 0x00000000 [31654.771948] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: rtsx_pci_send_cmd error (err = -110) [31654.771951] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: CMD 55 0x00000000 error(-110) [31654.771954] mmc0: req done (CMD55): -110: 00000000 00000000 00000000 00000000 [31654.771962] mmc0: starting CMD55 arg 00000000 flags 000000f5 [31654.771994] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: sd_send_cmd_get_rsp: SD/MMC CMD 55, arg = 0x00000000 [31654.875946] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: rtsx_pci_send_cmd error (err = -110) [31654.875950] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: CMD 55 0x00000000 error(-110) [31654.875952] mmc0: req done (CMD55): -110: 00000000 00000000 00000000 00000000 [31654.875962] mmc0: clock 300000Hz busmode 1 powermode 2 cs 0 Vdd 21 width 1 timing 0 [31654.876042] mmc0: starting CMD1 arg 00000000 flags 000000e1 [31654.876067] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: sd_send_cmd_get_rsp: SD/MMC CMD 1, arg = 0x00000000 [31654.979945] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: rtsx_pci_send_cmd error (err = -110) [31654.979948] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: CMD 1 0x00000000 error(-110) [31654.979951] mmc0: req done (CMD1): -110: 00000000 00000000 00000000 00000000 [31654.979958] mmc0: clock 0Hz busmode 2 powermode 0 cs 0 Vdd 0 width 1 timing 0 [31654.981407] mmc0: mmc_rescan_try_freq: trying to init card at 250000 Hz [31654.981409] mmc0: clock 0Hz busmode 2 powermode 1 cs 0 Vdd 21 width 1 timing 0 [31655.117058] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: sdmmc_switch_voltage: signal_voltage = 0 [31655.117288] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: Initial signal voltage of 3.3v [31655.123558] mmc0: clock 250000Hz busmode 2 powermode 2 cs 0 Vdd 21 width 1 timing 0 [31655.129933] mmc0: starting CMD52 arg 00000c00 flags 00000195 [31655.129972] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: sd_send_cmd_get_rsp: SD/MMC CMD 52, arg = 0x00000c00 [31655.231906] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: rtsx_pci_send_cmd error (err = -110) [31655.231909] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: CMD 52 0x00000c00 error(-110) [31655.231912] mmc0: req done (CMD52): -110: 00000000 00000000 00000000 00000000 [31655.231918] mmc0: starting CMD52 arg 80000c08 flags 00000195 [31655.231944] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: sd_send_cmd_get_rsp: SD/MMC CMD 52, arg = 0x80000c08 [31655.335931] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: rtsx_pci_send_cmd error (err = -110) [31655.335943] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: CMD 52 0x80000c08 error(-110) [31655.335953] mmc0: req done (CMD52): -110: 00000000 00000000 00000000 00000000 [31655.335980] mmc0: clock 250000Hz busmode 2 powermode 2 cs 1 Vdd 21 width 1 timing 0 [31655.337377] mmc0: starting CMD0 arg 00000000 flags 000000c0 [31655.337443] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: sd_send_cmd_get_rsp: SD/MMC CMD 0, arg = 0x00000000 [31655.337806] mmc0: req done (CMD0): 0: 00000000 00000000 00000000 00000000 [31655.339094] mmc0: clock 250000Hz busmode 2 powermode 2 cs 0 Vdd 21 width 1 timing 0 [31655.340432] mmc0: starting CMD8 arg 000001aa flags 000002f5 [31655.340492] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: sd_send_cmd_get_rsp: SD/MMC CMD 8, arg = 0x000001aa [31655.443958] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: rtsx_pci_send_cmd error (err = -110) [31655.443962] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: CMD 8 0x000001aa error(-110) [31655.443965] mmc0: req done (CMD8): -110: 00000000 00000000 00000000 00000000 [31655.443974] mmc0: starting CMD5 arg 00000000 flags 000002e1 [31655.444028] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: sd_send_cmd_get_rsp: SD/MMC CMD 5, arg = 0x00000000 [31655.547917] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: rtsx_pci_send_cmd error (err = -110) [31655.547920] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: CMD 5 0x00000000 error(-110) [31655.547927] mmc0: req failed (CMD5): -110, retrying... [31655.547958] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: sd_send_cmd_get_rsp: SD/MMC CMD 5, arg = 0x00000000 [31655.651956] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: rtsx_pci_send_cmd error (err = -110) [31655.651962] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: CMD 5 0x00000000 error(-110) [31655.651977] mmc0: req failed (CMD5): -110, retrying... [31655.652034] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: sd_send_cmd_get_rsp: SD/MMC CMD 5, arg = 0x00000000 [31655.759929] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: rtsx_pci_send_cmd error (err = -110) [31655.759933] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: CMD 5 0x00000000 error(-110) [31655.759970] mmc0: req failed (CMD5): -110, retrying... [31655.760003] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: sd_send_cmd_get_rsp: SD/MMC CMD 5, arg = 0x00000000 [31655.863967] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: rtsx_pci_send_cmd error (err = -110) [31655.863973] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: CMD 5 0x00000000 error(-110) [31655.863977] mmc0: req done (CMD5): -110: 00000000 00000000 00000000 00000000 [31655.863990] mmc0: starting CMD55 arg 00000000 flags 000000f5 [31655.864063] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: sd_send_cmd_get_rsp: SD/MMC CMD 55, arg = 0x00000000 [31655.967948] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: rtsx_pci_send_cmd error (err = -110) [31655.967952] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: CMD 55 0x00000000 error(-110) [31655.967954] mmc0: req done (CMD55): -110: 00000000 00000000 00000000 00000000 [31655.967962] mmc0: starting CMD55 arg 00000000 flags 000000f5 [31655.967992] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: sd_send_cmd_get_rsp: SD/MMC CMD 55, arg = 0x00000000 [31656.071960] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: rtsx_pci_send_cmd error (err = -110) [31656.071965] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: CMD 55 0x00000000 error(-110) [31656.071969] mmc0: req done (CMD55): -110: 00000000 00000000 00000000 00000000 [31656.071979] mmc0: starting CMD55 arg 00000000 flags 000000f5 [31656.072047] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: sd_send_cmd_get_rsp: SD/MMC CMD 55, arg = 0x00000000 [31656.175989] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: rtsx_pci_send_cmd error (err = -110) [31656.175996] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: CMD 55 0x00000000 error(-110) [31656.176003] mmc0: req done (CMD55): -110: 00000000 00000000 00000000 00000000 [31656.176049] mmc0: starting CMD55 arg 00000000 flags 000000f5 [31656.176108] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: sd_send_cmd_get_rsp: SD/MMC CMD 55, arg = 0x00000000 [31656.279934] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: rtsx_pci_send_cmd error (err = -110) [31656.279941] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: CMD 55 0x00000000 error(-110) [31656.279946] mmc0: req done (CMD55): -110: 00000000 00000000 00000000 00000000 [31656.279958] mmc0: clock 250000Hz busmode 1 powermode 2 cs 0 Vdd 21 width 1 timing 0 [31656.280034] mmc0: starting CMD1 arg 00000000 flags 000000e1 [31656.280072] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: sd_send_cmd_get_rsp: SD/MMC CMD 1, arg = 0x00000000 [31656.383957] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: rtsx_pci_send_cmd error (err = -110) [31656.383960] rtsx_pci_sdmmc rtsx_pci_sdmmc.0: CMD 1 0x00000000 error(-110) [31656.383963] mmc0: req done (CMD1): -110: 00000000 00000000 00000000 00000000 [31656.383975] mmc0: clock 0Hz busmode 2 powermode 0 cs 0 Vdd 0 width 1 timing 0` ---------------------------------------- Bug #297: T440P card reader is broken. https://ticket.coreboot.org/issues/297#change-1332 * Author: Jamal Wright * Status: New * Priority: Normal * Start date: 2021-03-03 ---------------------------------------- I've been trying to figure out the reason why the card reader detects but doesn't work and crashes windows. Wanted to track this bug outside of the mailing list since that will probably get lost. I've even cross compared to the X250 and everything looks normal. Am I missing a GPIO? Is there something wrong with the PCIE detection? Perhaps a conflict with the wifi which is on the same PCIE root? Building off master as of 3/3/21 I get this in kernel: kernel: pci 0000:00:1c.1: [8086:8c12] type 01 class 0x060400 kernel: pci 0000:00:1c.1: PME# supported from D0 D3hot D3cold kernel: pci 0000:00:1c.1: PCI bridge to [bus 03] kernel: pci 0000:00:1c.1: bridge window [mem 0x82300000-0x823fffff] kernel: pci 0000:00:1c.1: PCI bridge to [bus 03] kernel: pci 0000:00:1c.1: bridge window [mem 0x82300000-0x823fffff] kernel: pcieport 0000:00:1c.1: PME: Signaling with IRQ 27 kernel: pcieport 0000:00:1c.1: AER: enabled with IRQ 27 This is my PCIE tree: -[0000:00]-+-00.0 Intel Corporation Xeon E3-1200 v3/4th Gen Core Processor DRAM Controller +-02.0 Intel Corporation 4th Gen Core Processor Integrated Graphics Controller +-03.0 Intel Corporation Xeon E3-1200 v3/4th Gen Core Processor HD Audio Controller +-04.0 Intel Corporation Device 0c03 +-14.0 Intel Corporation 8 Series/C220 Series Chipset Family USB xHCI +-16.0 Intel Corporation 8 Series/C220 Series Chipset Family MEI Controller #1 +-19.0 Intel Corporation Ethernet Connection I217-LM +-1a.0 Intel Corporation 8 Series/C220 Series Chipset Family USB EHCI #2 +-1b.0 Intel Corporation 8 Series/C220 Series Chipset High Definition Audio Controller +-1c.0-[02]----00.0 Realtek Semiconductor Co., Ltd. RTS5227 PCI Express Card Reader +-1c.1-[03]----00.0 Intel Corporation Wireless 7265 +-1d.0 Intel Corporation 8 Series/C220 Series Chipset Family USB EHCI #1 +-1f.0 Intel Corporation QM87 Express LPC Controller +-1f.2 Intel Corporation 8 Series/C220 Series Chipset Family 6-port SATA Controller 1 [AHCI mode] \-1f.3 Intel Corporation 8 Series/C220 Series Chipset Family SMBus Controller LSPCI -vv : https://pastebin.com/0hbb0vZg I've attached CBMEM logs as well. A bit out of ideas, just sitting with fingers crossed hoping a haswell or lynxpoint commit fixes it :) ---Files-------------------------------- onbtpci.txt (26.2 KB) pcidevs.txt (26.2 KB) x250pci.txt (21.9 KB) pcidevs.txt (26.2 KB) dsdt.pre (568 KB) pcitreeven.txt (1.09 KB) T440P-vendor.txt (22.9 KB) thinkpad_t440p.7z (4.72 KB) logs.7z (118 KB) arch-dmesg.txt (66.1 KB) cinamon-dmesg.txt (57.2 KB) dmesg-buntu.txt (62.2 KB) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

1 0

New Defects reported by Coverity Scan for coreboot
by scan-admin＠coverity.com 16 Dec '22

16 Dec '22

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 1 new defect(s) introduced to coreboot found with Coverity Scan. 1 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 1 of 1 defect(s) ** CID 1501549: Control flow issues (DEADCODE) /src/soc/amd/morgana/fch.c: 154 in gpp_clk_setup() ________________________________________________________________________________________________________ *** CID 1501549: Control flow issues (DEADCODE) /src/soc/amd/morgana/fch.c: 154 in gpp_clk_setup() 148 * devicetree settings is the clock being enabled, so that a missing devicetree 149 * configuration for this will result in an always active clock and not an 150 * inactive PCIe clock output. Only the configuration for the clock outputs 151 * available on the package is provided via the devicetree; the rest is 152 * switched off unconditionally. 153 */ >>> CID 1501549: Control flow issues (DEADCODE) >>> Execution cannot reach the expression "GPP_CLK_OFF" inside this statement: "switch ((i < 7) ? cfg->gpp_...". 154 switch (i < GPP_CLK_OUTPUT_AVAILABLE ? cfg->gpp_clk_config[i] : GPP_CLK_OFF) { 155 case GPP_CLK_REQ: 156 gpp_clk_ctl |= GPP_CLK_REQ_EXT(gpp_clk_shift_lut[i]); 157 break; 158 case GPP_CLK_OFF: 159 gpp_clk_ctl |= GPP_CLK_REQ_OFF(gpp_clk_shift_lut[i]); ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u15810271.ct.sendgrid.net/ls/click?upn=HRESupC-2F2Czv4BOaCWWCy7my0P…

1 0

Re: Guidelines for using die()
by Martin Roth 15 Dec '22

15 Dec '22

From the leadership meeting: There was general agreement about creating a guideline to only die when coreboot cannot continue. This is strictly a guideline, and is up to the developers to do what makes sense. This means that if it's possible to continue booting, we should do our best. When possible, print a warning and try to continue. Notes: [Angel] We agree with the reasoning, especially because what CB:55690 fixed was quite embarrassing: it broke booting on the T440p until CB;55687 fixed it by adding one line... However, we’d like to ask everyone to be careful when considering removing die()’s in RAM init. Memory init is arcane magic, and it can fail in the most subtle of ways (see CB:48550 for a rather embarrassing example, and CB:47680 for the fix to a long-standing Sandy/Ivy NRI bug that could cause instability). The two errors shown here are about the installed memory modules: if a computer worked before, these errors can only occur if the installed memory modules are changed (or if the SPD data got corrupted somehow, which is even worse). In our honest opinion, it’s best for the user to immediately let them know that their newly-installed memory isn’t going to work properly rather than to risk memory-related instability for the sake of booting. We’d prefer to keep the “controller minimum freq” die() because it stops the RAM from being overclocked (we could add a Kconfig option to continue anyway, though), but we agree with reworking the “SPD mismatch” code as described, and we even volunteer to do so if we can test it. On a somewhat related note, it’s a good idea to avoid using die() within memory init code, but to propagate errors to the caller. This allows retrying memory init with different parameters or disabling failing channels, which increases the chances of booting. [Angel] TL;DR the 2nd example is fine, the rest are OK. Consider using WARN_ON and BUG_ON macros (assert, but allow handling the result in regular C code). For instance: if (BUG_ON(did_error_happen())) handle_error(); [Angel] TO DO: Add the aforementioned macros to coreboot. [Angel] TO DO: Figure out how to enable FATAL_ASSERTS for 9elements QA. [David] "Boots, not bricks" - Need a recovery path if at all possible. Use asserts - so fatal asserts will halt the system and if fatal-asserts are not set, the system will continue. * coreboot needs better document on asserts and error handling. * Julius will try to work on this. Angel can help. * Martin to add documentation to the header files so that information about assert() and die() for IDEs that support this feature. * We need a way to report failures for security issues to later in the boot process when that information can be given to the user or to reboot to whatever recovery mode is implemented. This needs to be designed and discussed separately.

2 1

Porting a board, how to get the overcurrent pin mapping for QM370?
by Jose Trujillo 15 Dec '22

15 Dec '22

Hello Ladies and Gentlemen: I am trying to do the porting of a computer module based on Intel CoffeeLake/QM370. I don't have the schematics. I was trying to find out how to extract/dump the overcurrent pin mapping from the system, but I was unable to find this information. I need this configuration to correctly set the USB configuration in the devicetree.cb. In older systems previous to Skylake this information was in the RCBA (dumped by inteltool), but there is no RCBA in newer chipsets. Anyone can help me in providing the steps? Thank you, Jose Trujillo.

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