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flash_rom support for amd 8111 and pm49fl004
by ron minnich 10 Feb '04

10 Feb '04

I just committed YhLu's updates to flash_from for the amd 8111 and pm49fl004 parts. This is in freebios2 only for now, since freebios 1 does not support this chipset anyway. ron

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Re: Re: LinuxBIOS....on desktop PCs?
by Hendricks David W. 10 Feb '04

10 Feb '04

That's a KT266 mainboard, which might be familiar with the Chaintech mainboard recently added. You might want to check out the details and see how similar they are. On Mon, 9 Feb 2004 bjm_(a)bellsouth.net wrote: > Well...I'm running on an Athlon, yes...2GHz infact. Mainboard is a Shuttle Ak32a, not sure how big the ROM is, how big does it have to be to have LinuxBIOS? > > Oh I just wanted to try out LinuxBIOS because I heard it has fast boot times...and it's linux so it has to work ;) > > -Brad > > > > > From: "Hendricks David W." <dwh(a)lanl.gov> > > Date: 2004/02/09 Mon PM 05:05:46 EST > > To: bjm_(a)bellsouth.net > > CC: linuxbios(a)clustermatic.org > > Subject: Re: LinuxBIOS....on desktop PCs? > > > > Yes, depending on which mainboard you're running. And with the recent > > revelations in VGA support (It works :)), I think LinuxBIOS is well > > underway for use in the desktop market. > > > > Did you have anything specific in mind? If you're looking for a mainboard, > > check out the Epia or perhaps the Chaintech 7KJD if you're looking for an > > Athlon platform. > > > > On Sat, 7 Feb 2004 bjm_(a)bellsouth.net wrote: > > > > > Is it possible to have LinuxBIOS on desktop PCs? Was wondering...if so, I'd like to use it :) > > > > > > _______________________________________________ > > > Linuxbios mailing list > > > Linuxbios(a)clustermatic.org > > > http://www.clustermatic.org/mailman/listinfo/linuxbios > > > > > > > >

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答复: What is this good for?
by YhLu 10 Feb '04

10 Feb '04

Eric, Can you commit the patch that can reduce the time of memory clearing? If the MB is configured with 8G, it will take around 2 minutes to get it finished. Regards YH. -----邮件原件----- 发件人: ebiederman(a)lnxi.com [mailto:ebiederman@lnxi.com] 发送时间: 2004年2月10日 7:21 收件人: Stefan Reinauer 抄送: linuxbios(a)clustermatic.org 主题: Re: What is this good for? Stefan Reinauer <stepan(a)suse.de> writes: > Hi, > > I appreciate that we only have to do one reset when optimizing HT links: > > http://cvs.sourceforge.net/viewcvs.py/freebios/freebios2/src/northbridge/amd /amdk8/misc_control.c?r1=1.4&r2=1.5 > > > What I don't like about the whole situation is the fact that this code > does not honour the actually available links but does hardcodes. > This will break Athlon64 systems _ONCE AGAIN_ > > Please, instead of removing my comments, do read them - They explain > pretty well why certain code is only enabled for CONFIG_MAX_CPUS > 1 Ugh yes that change looks nasty. Here is the version I am running, and it does work on AMD64 systems. It relies on the fact that the unused HT links return 0, instead of doing the prettier thing of walking the capabilities, but it does work. I don't have time at the moment to get this merged, but at least this will give you something to work with. Eric /* Turn off machine check triggers when reading * pci space where there are no devices. * This is necessary when scaning the bus for * devices which is done by the kernel */ #include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> #include <part/hard_reset.h> #include "./cpu_rev.c" #include "amdk8.h" #define IOMMU_APETURE_SIZE (64*1024*1024) /* 64M */ static void mcf3_read_resources(device_t dev) { struct resource *resource; /* Read the generic PCI resources */ pci_dev_read_resources(dev); /* If we are not the first processor don't allocate the gart apeture */ if (dev->path.u.pci.devfn != PCI_DEVFN(24, 3)) { return; } /* Add a 64M Gart apeture resource */ if (dev->resources < MAX_RESOURCES) { resource = &dev->resource[dev->resources]; dev->resources++; resource->base = 0; resource->size = IOMMU_APETURE_SIZE; resource->align = log2(resource->size); resource->gran = log2(resource->size); resource->limit = 0xffffffff; /* 4G */ resource->flags = IORESOURCE_MEM; resource->index = 0x94; } else { printk_err("%s Unexpeted resource shortage\n", dev_path(dev)); } } static void mcf3_set_resources(device_t dev) { struct resource *resource, *last; last = &dev->resource[dev->resources]; for(resource = &dev->resource[0]; resource < last; resource++) { if (resource->index == 0x94) { device_t pdev; uint32_t base; uint32_t size; size = (0<<6)|(0<<5)|(0<<4)|((log2(resource->size) - 25) << 1)|(0<<0); base = ((resource->base) >> 25) & 0x00007fff; pdev = 0; while(pdev = dev_find_device(PCI_VENDOR_ID_AMD, 0x1103, pdev)) { /* I want a 64M GART apeture */ pci_write_config32(pdev, 0x90, (0<<6)|(0<<5)|(0<<4)|(1<<1)|(0<<0)); /* Store the GART base address */ pci_write_config32(pdev, 0x94, base); /* Don't set the GART Table base address */ pci_write_config32(pdev, 0x98, 0); printk_debug( "%s %02x <- [0x%08lx - 0x%08lx] mem <gart>\n", dev_path(pdev), resource->index, resource->base, resource->base + resource->size - 1); } /* Remember this resource has been stored */ resource->flags |= IORESOURCE_STORED; } } /* Set the generic PCI resources */ pci_dev_set_resources(dev); } static void misc_control_init(struct device *dev) { uint32_t cmd, cmd_ref; int needs_reset; struct device *f0_dev, *f2_dev; printk_debug("NB: Function 3 Misc Control.. "); needs_reset = 0; /* Disable Machine checks from Invalid Locations. * This is needed for PC backwards compatibility. */ cmd = pci_read_config32(dev, 0x44); cmd |= (1<<6) | (1<<25); pci_write_config32(dev, 0x44, cmd ); if (is_cpu_pre_c0()) { /* Errata 58 * Disable CPU low power states C2, C1 and throttling */ cmd = pci_read_config32(dev, 0x80); cmd &= ~(1<<0); pci_write_config32(dev, 0x80, cmd ); cmd = pci_read_config32(dev, 0x84); cmd &= ~(1<<24); cmd &= ~(1<<8); pci_write_config32(dev, 0x84, cmd ); /* Errata 66 * Limit the number of downstream posted requests to 1 */ cmd = pci_read_config32(dev, 0x70); if ((cmd & (3 << 0)) != 2) { cmd &= ~(3<<0); cmd |= (2<<0); pci_write_config32(dev, 0x70, cmd ); needs_reset = 1; } cmd = pci_read_config32(dev, 0x7c); if ((cmd & (3 << 4)) != 0) { cmd &= ~(3<<4); cmd |= (0<<4); pci_write_config32(dev, 0x7c, cmd ); needs_reset = 1; } /* Clock Power/Timing Low */ cmd = pci_read_config32(dev, 0xd4); if (cmd != 0x000D0001) { cmd = 0x000D0001; pci_write_config32(dev, 0xd4, cmd); needs_reset = 1; /* Needed? */ } } else { uint32_t dcl; f2_dev = dev_find_slot(0, dev->path.u.pci.devfn - 3 + 2); /* Errata 98 * Set Clk Ramp Hystersis to 7 * Clock Power/Timing Low */ cmd_ref = 0x04e20707; /* Registered */ dcl = pci_read_config32(f2_dev, DRAM_CONFIG_LOW); if (dcl & DCL_UnBufDimm) { cmd_ref = 0x000D0701; /* Unbuffered */ } cmd = pci_read_config32(dev, 0xd4); if(cmd != cmd_ref) { pci_write_config32(dev, 0xd4, cmd_ref ); needs_reset = 1; /* Needed? */ } } /* Optimize the Link read pointers */ f0_dev = dev_find_slot(0, dev->path.u.pci.devfn - 3); if (f0_dev) { int link; cmd_ref = cmd = pci_read_config32(dev, 0xdc); for(link = 0; link < 3; link++) { uint32_t link_type; unsigned reg; reg = 0x98 + (link * 0x20); link_type = pci_read_config32(f0_dev, reg); if (link_type & LinkConnected) { cmd &= 0xff << (link *8); /* FIXME this assumes the device on the other side is an AMD device */ cmd |= 0x25 << (link *8); } } if (cmd != cmd_ref) { pci_write_config32(dev, 0xdc, cmd); needs_reset = 1; } } else { printk_err("Missing f0 device!\n"); } if (needs_reset) { printk_debug("resetting cpu\n"); hard_reset(); } printk_debug("done.\n"); } static struct device_operations mcf3_ops = { .read_resources = mcf3_read_resources, .set_resources = mcf3_set_resources, .enable_resources = pci_dev_enable_resources, .init = misc_control_init, .scan_bus = 0, }; static struct pci_driver mcf3_driver __pci_driver = { .ops = &mcf3_ops, .vendor = PCI_VENDOR_ID_AMD, .device = 0x1103, }; _______________________________________________ Linuxbios mailing list Linuxbios(a)clustermatic.org http://www.clustermatic.org/mailman/listinfo/linuxbios

2 1

vga emulator new version
by ron minnich 10 Feb '04

10 Feb '04

I've got the newest working version of the emulator for anyone who wants to try it. This won't work on K8 systems minus some hacks, due to K8 differences, contact me if interested. ron

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答复: /dev/bios for 2.6
by YhLu 10 Feb '04

10 Feb '04

Why not use flash_rom in freebios2/util? YH -----邮件原件----- 发件人: ebiederman(a)lnxi.com [mailto:ebiederman@lnxi.com] 发送时间: 2004年2月10日 9:10 收件人: RSmith(a)bitworks.com 抄送: stepan(a)suse.de; linuxbios(a)clustermatic.org 主题: Re: /dev/bios for 2.6 Richard Smith <rsmith(a)bitworks.com> writes: > Eric W. Biederman wrote: > > > If you look in jedec_probe.c AM29F040, and AM29LV040B are supported so if > > it is not it should be just a tiny tweak to jedec probe to get the chip > > recognized. > > Ah.. jdec_probe ok well that gives me a place to start. I'll go see if I can > tweak that to find a AM29F040B. I would have though that the AM29F040 id would > have matched. It might I don't know how you have things configured. > >> The MTD webpage dosen't have any info and I build and inserted lots of > >> different mtd > >>modules but nothing indicated they did anything. > > Do you have a proper map driver? > > Er... I don't know. How do I check? MTD has 3 levels of drivers. - The map driver (i.e. ich2rom and amd76xrom ) which knows how to find the ROM chip on a specific board, or chipset. - The probe driver (cfi_probe or jedec_probe) which knows how to detect which ROM chip you have. - The chip driver (cfi_cmdset_0001 cfi_cmdset_002..) which knows how to use a specific command set regardless of which device you have. > I've not found any documentation explaining anything about useing the MTD with > BIOS type flash chips. Its all Msystems or CF stuff so I've just been guessing. > > > My chip is hanging out just like a normal BIOS chip would at physical address > 0xfff80000 - 0xffffffff. The 1Meg extended BIOS space area should be enabled in > my chipset. So BIOS chipselects should be generated for 0xfff0ffff up. > There was an option in the kernel building that asked for a start address and a > size to which I entered 0xfff80000 and 0x80000. > > Hmmm... come to think about it now I may have entered 0x80000 rather than > 0xfff80000 as the start address.. > > In any case.. given my setup what and where do I config this? Basically it depends on the map driver you are using. Some of them can look at your chipset and figure these things out. Some are really generic and you have to hard code things. I don't know if those work at all. Eric _______________________________________________ Linuxbios mailing list Linuxbios(a)clustermatic.org http://www.clustermatic.org/mailman/listinfo/linuxbios

2 1

What is this good for?
by Stefan Reinauer 10 Feb '04

10 Feb '04

Hi, I appreciate that we only have to do one reset when optimizing HT links: http://cvs.sourceforge.net/viewcvs.py/freebios/freebios2/src/northbridge/am… What I don't like about the whole situation is the fact that this code does not honour the actually available links but does hardcodes. This will break Athlon64 systems _ONCE AGAIN_ Please, instead of removing my comments, do read them - They explain pretty well why certain code is only enabled for CONFIG_MAX_CPUS > 1 Best regards, Stefan Reinauer -- Stefan Reinauer, SUSE LINUX AG Teamleader Architecture Development

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Re: IDE on s2885 and LinuxBIOS -- FILO
by YhLu 10 Feb '04

10 Feb '04

Ron, I have checked pci.c in fifo. It need to be changes as follow. It seems otherwise it can not scan the peer root bus. Maybe someone need to make it can handle peer root bus refer to the code in Linux kernel or Etherboot. Regards YH. void pci_init(void) { /* Count devices */ dev_list = 0; debug("Scanning PCI: "); pci_scan_bus(0); pci_scan_bus(1); // For Tyan s2880,s2881,s2882,s2885,s4880 // pci_scan_bus(3); //For Tyan s2885 debug("found %d devices\n", n_devs); /* Make the list */ dev_list = malloc(n_devs * sizeof(struct pci_dev)); n_devs = 0; pci_scan_bus(0); pci_scan_bus(1); // For Tyan s2880,s2881,s2882,s2885,s4880 // pci_scan_bus(3); //For Tyan s2885 #if DEBUG { int i; for (i = 0; i < n_devs; i++) { debug("%02x:%02x.%x %04x:%04x %04x %02x\n", PCI_BUS(dev_list[i].addr), PCI_DEV(dev_list[i].addr), PCI_FN(dev_list[i].addr), dev_list[i].vendor, dev_list[i].device, dev_list[i].devclass, dev_list[i].prog_if); } } #endif } -----邮件原件----- 发件人: YhLu 发送时间: 2003年12月10日 9:27 收件人: 'ron minnich' 抄送: Hendricks David W. 主题: Re: IDE on s2885 and LinuxBIOS Is it working with On current tree or using old source tree to make sure all 8111/8131 on bus 0? Yinghai Lu -----邮件原件----- 发件人: ron minnich [mailto:rminnich@lanl.gov] 发送时间: 2003年12月10日 7:25 收件人: YhLu 抄送: Hendricks David W. 主题: Re: IDE on s2885 and LinuxBIOS I wonder what differes from HDAMA to s2885? filo works fine on HDAMA ron

5 8

where is a step-by-step tutorial ?
by spidermantm＠freenet.de 10 Feb '04

10 Feb '04

1 0

Re: ATI gets a clue.
by Hendricks David W. 09 Feb '04

09 Feb '04

We don't need to with nVidia, we can run their VGA BIOS using testbios. Though in the perfect world, they'd be more forthcoming with specs so that someone can make an LB port for their nForce boards. On Mon, 9 Feb 2004, Carlos Silva wrote: > Really nice news... i'll keep dreaming that nvidia will do the same. > > > > Wonderfull news... I got this back today from ATI. Looks like someone > > with some clout there finally gets it. > > > > So I'm about to start porting some biosless init code I received over to > > Linux. Then work it into linux bios. > > > > I take back everything I said bad about ATI. *grin* > > > > Tell all your OEM buddies that ATI Mobility M1 video chips are about to > > become LinuxBIOS friendly in the near future. > > > > ------- > > Sorry for the lengthy delay. There is a lot of detail here. Basically, > > you can develop code with our documentation, and then release it under > > GPL - no issues there. > > > > If you want to produce a biosless chip init procedure, you can use the > > documentation I pointed you to. If you have any questions, feel free to > > email me about those documents. > > --------- > > > > -- > > Richard A. Smith > > rsmith(a)bitworks.com > > > > > > _______________________________________________ > > Linuxbios mailing list > > Linuxbios(a)clustermatic.org > > http://www.clustermatic.org/mailman/listinfo/linuxbios > > > > _______________________________________________ > Linuxbios mailing list > Linuxbios(a)clustermatic.org > http://www.clustermatic.org/mailman/listinfo/linuxbios >

5 7

Re: LinuxBIOS....on desktop PCs?
by Hendricks David W. 09 Feb '04

09 Feb '04

Yes, depending on which mainboard you're running. And with the recent revelations in VGA support (It works :)), I think LinuxBIOS is well underway for use in the desktop market. Did you have anything specific in mind? If you're looking for a mainboard, check out the Epia or perhaps the Chaintech 7KJD if you're looking for an Athlon platform. On Sat, 7 Feb 2004 bjm_(a)bellsouth.net wrote: > Is it possible to have LinuxBIOS on desktop PCs? Was wondering...if so, I'd like to use it :) > > _______________________________________________ > Linuxbios mailing list > Linuxbios(a)clustermatic.org > http://www.clustermatic.org/mailman/listinfo/linuxbios >

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