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RE: Freebios2 recovery progress...
by YhLu 22 Oct '04

22 Oct '04

You can not test that in arima board. Because all device on 8131 is using ioapic in amd8111. YH -----Original Message----- From: ebiederman(a)lnxi.com [mailto:ebiederman@lnxi.com] Sent: Thursday, October 21, 2004 11:13 AM To: YhLu Cc: LinuxBIOS Subject: Re: Freebios2 recovery progress... YhLu <YhLu(a)tyan.com> writes: > Eric, > > You overwrite some lines in amd8131.... > > /* We have to enable MEM and Bus Master for IOAPIC */ > value = pci_read_config32(dev, 0x4); > value |= 6; > pci_write_config32(dev, 0x4, value); Yep. But in src/devices/pci_device.c:pci_scan_bus I added: /* Architectural/System devices always need to * be bus masters. */ if ((dev->class >> 16) == PCI_BASE_CLASS_SYSTEM) { dev->command |= PCI_COMMAND_MASTER; } Which achieves the same thing in a generally less fragile way. We still might have one or two devices that we need to hard code the master command status for but this catches the general case. Basically system devices have well known interfaces so they are likely to have a generic driver instead of a device specific driver. So enabling them as bus masters looks safe and will fix all of the cases I know about where this is needed. And I checked and the bus master bit is still getting set on the IOAPICs on the HDAMA. But thanks good catch, this needed an explanation. Did I mention I was just a little behind on merging my code? :) Eric

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RE: Freebios2 recovery progress... moving enable_childrens_resour ces
by YhLu 22 Oct '04

22 Oct '04

Mis spelling diff -r freebios2/src/southbridge/amd/amd8111/amd8111_lpc.c ../freebios2/src/southbridge/amd/amd8111/amd8111_lpc.c 173c173 < static void amd8111_lpc_enable_resoruces(device_t dev) --- > static void amd8111_lpc_enable_resources(device_t dev) -----Original Message----- From: ebiederman(a)lnxi.com [mailto:ebiederman@lnxi.com] Sent: Thursday, October 21, 2004 7:43 PM To: YhLu Cc: LinuxBIOS Subject: Re: Freebios2 recovery progress... moving enable_childrens_resour ces YhLu <YhLu(a)tyan.com> writes: > add one call to amd8111 lpc ? Exactly. And committed for the amd8111 and the i82801??? chips. The rest of the southbridges did not appear to an lpc or an isa bus that I could identify code wise so it appears they have more that needs to be done to get them into shape. Eric

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RE: Freebios2 recovery progress... pci64 mem optimization
by YhLu 21 Oct '04

21 Oct '04

You are right 4G installed: PCI-DMA: Disabling IOMMU. ----> 8G installed: PCI-DMA: Disabling AGP. PCI-DMA: aperture base @ 8000000 size 65536 KB PCI-DMA: Reserving 64MB of IOMMU area in the AGP aperture -----Original Message----- From: ebiederman(a)lnxi.com [mailto:ebiederman@lnxi.com] Sent: Thursday, October 21, 2004 7:40 PM To: YhLu Cc: 'LinuxBIOS' Subject: Re: Freebios2 recovery progress... pci64 mem optimization YhLu <YhLu(a)tyan.com> writes: > Iommu is only needed when system installed memory > 4G? IOMMU's have 2 uses. 1) let devices with small DMA ranges reach all of memory (pci devices that don't implement DAC can only talk to the first 4G) 2) Isolation. Allowing the OS to controll which memory may be touched by I/O devices. The current Opteron IOMMU does not appear to be general enough to perform isolation so it is only needed when you have more than 4GB of memory. So there may be some point in disabling it on systems with 4GB. Plus the linux kernel seems to be able to properly allocate the iommu if it needs it. Eric

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RE: Freebios2 recovery progress... pci64 mem optimization
by YhLu 21 Oct '04

21 Oct '04

Clear. Thanks. -----Original Message----- From: ebiederman(a)lnxi.com [mailto:ebiederman@lnxi.com] Sent: Thursday, October 21, 2004 7:40 PM To: YhLu Cc: 'LinuxBIOS' Subject: Re: Freebios2 recovery progress... pci64 mem optimization YhLu <YhLu(a)tyan.com> writes: > Iommu is only needed when system installed memory > 4G? IOMMU's have 2 uses. 1) let devices with small DMA ranges reach all of memory (pci devices that don't implement DAC can only talk to the first 4G) 2) Isolation. Allowing the OS to controll which memory may be touched by I/O devices. The current Opteron IOMMU does not appear to be general enough to perform isolation so it is only needed when you have more than 4GB of memory. So there may be some point in disabling it on systems with 4GB. Plus the linux kernel seems to be able to properly allocate the iommu if it needs it. Eric

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RE: Freebios2 recovery progress... moving enable_childrens_resour ces
by YhLu 21 Oct '04

21 Oct '04

add one call to amd8111 lpc ? static struct device_operations lpc_ops = { .read_resources = amd8111_lpc_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = lpc_init, .scan_bus = scan_static_bus, .enable = amd8111_enable, .ops_pci = &lops_pci, }; ----> static void amd8111_lpc_enable_resources(device_t dev) { pci_dev_enable_resources(dev); enable_childrens_resources(dev); } static struct device_operations lpc_ops = { .read_resources = amd8111_lpc_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = amd8111_lpc_enable_resources, .init = lpc_init, .scan_bus = scan_static_bus, .enable = amd8111_enable, .ops_pci = &lops_pci, };

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RE: Freebios2 recovery progress... pci64 mem optimization
by YhLu 21 Oct '04

21 Oct '04

Iommu is only needed when system installed memory > 4G? YH -----Original Message----- From: ebiederman(a)lnxi.com [mailto:ebiederman@lnxi.com] Sent: Thursday, October 21, 2004 7:08 PM To: YhLu Cc: 'LinuxBIOS' Subject: Re: Freebios2 recovery progress... pci64 mem optimization YhLu <YhLu(a)tyan.com> writes: > If no agp, > Still need gart? > > YH > > PCI: 00:18.3 94 <- [0x00f8000000 - 0x00fbffffff] mem <gart> > PCI: 00:19.3 94 <- [0x00f8000000 - 0x00fbffffff] mem <gart> With more than 4GB of memory it is used as an IOMMU so you don't need bounce buffers. Eric

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RE: Freebios2 recovery progress... moving enable_childrens_resour ces
by YhLu 21 Oct '04

21 Oct '04

Eric, Why moving enable_childrens_resources(dev); from void pci_dev_enable_resources(struct device *dev) to void pci_bus_enable_resources(struct device *dev) the superio under the PCI device will not be enabled with resources. Regards YH -----Original Message----- From: YhLu Sent: Thursday, October 21, 2004 2:03 PM To: ebiederman(a)lnxi.com Cc: LinuxBIOS Subject: RE: Freebios2 recovery progress... It's OK. PCI: 04:01.0 bridge ctrl <- 0003 PCI: 04:01.0 cmd <- 146 PCI: 05:04.0 cmd <- 142 PCI: 04:01.1 subsystem <- 10f1/2895 PCI: 04:01.1 cmd <- 146 PCI: 04:02.0 bridge ctrl <- 0003 PCI: 04:02.0 cmd <- 147 PCI: 06:06.0 cmd <- 143 PCI: 06:06.1 cmd <- 143 -----Original Message----- From: YhLu Sent: Thursday, October 21, 2004 12:11 PM To: 'ebiederman(a)lnxi.com' Cc: LinuxBIOS Subject: RE: Freebios2 recovery progress... I will test that on s2885. I suspect that will need MEM enable too. YH -----Original Message----- From: ebiederman(a)lnxi.com [mailto:ebiederman@lnxi.com] Sent: Thursday, October 21, 2004 11:39 AM To: YhLu Cc: LinuxBIOS Subject: Re: Freebios2 recovery progress... YhLu <YhLu(a)tyan.com> writes: > You can not test that in arima board. Because all device on 8131 is using > ioapic in amd8111. I can't test that it works but I can test that the bits are getting set by running lspci. And that is how I tested. The bus master bit is still getting set. I just move the location. Eric _______________________________________________ Linuxbios mailing list Linuxbios(a)clustermatic.org http://www.clustermatic.org/mailman/listinfo/linuxbios

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RE: Freebios2 recovery progress... pci64 mem optimization
by YhLu 21 Oct '04

21 Oct '04

Eric, In northbridge.c Another typo error /* If so place the one with the most stringent alignment first */ if (mem2->align > mem1->align) { struct resource *tmp; tmp = mem1; mem1 = mem2; mem2 = mem1; } /* Now place the memory as high up as it will go */ mem2->base = resource_max(mem2); mem1->limit = mem2->base - 1; mem1->base = resource_max(mem1); ----> /* If so place the one with the most stringent alignment first */ if (mem2->align > mem1->align) { struct resource *tmp; tmp = mem1; mem1 = mem2; mem2 = tmp; } /* Now place the memory as high up as it will go */ mem2->base = resource_max(mem2); mem1->limit = mem2->base - 1; mem1->base = resource_max(mem1); Another question is Should do align big allocation at first or align small first. It seems you should do align big allocation. Align big first base1: 0xd0000000 limit1: 0xfebfffff size: 0x18800000 align: 28 base2: 0xec000000 limit2: 0xfebfffff size: 0x06b00000 align: 26 base1: 0xd8000000 limit1: 0xdfffffff size: 0x06b00000 align: 26 base2: 0xe0000000 limit2: 0xfebfffff size: 0x18800000 align: 28 PCI_DOMAIN: 0000 00 <- [0x0000001000 - 0x0000005fff] io PCI_DOMAIN: 0000 01 <- [0x00e0000000 - 0x00f87fffff] prefmem PCI_DOMAIN: 0000 02 <- [0x00d8000000 - 0x00deafffff] mem Align small first base1: 0xd0000000 limit1: 0xfebfffff size: 0x18800000 align: 28 base2: 0xec000000 limit2: 0xfebfffff size: 0x06b00000 align: 26 base1: 0xd0000000 limit1: 0xf7ffffff size: 0x18800000 align: 28 base2: 0xf8000000 limit2: 0xfebfffff size: 0x06b00000 align: 26 PCI_DOMAIN: 0000 00 <- [0x0000001000 - 0x0000005fff] io PCI_DOMAIN: 0000 01 <- [0x00d0000000 - 0x00e87fffff] prefmem PCI_DOMAIN: 0000 02 <- [0x00f8000000 - 0x00feafffff] mem

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RE: Freebios2 recovery progress... pci64 mem optimization
by YhLu 21 Oct '04

21 Oct '04

Cool, with prefmem 64 bit, and mem opt. Get back 512M RAM. Mellanox IB PCI-E card support real pci mem64. base1: 0xd8000000 limit1: 0xfcffffffff size: 0x18800000 align: 27 base2: 0xf4000000 limit2: 0xfe8fffff size: 0x04c00000 align: 26 base1: 0xfce0000000 limit1: 0xfcffffffff size: 0x18800000 align: 27 base2: 0xf8000000 limit2: 0xfe8fffff size: 0x04c00000 align: 26 PCI_DOMAIN: 0000 00 <- [0x0000001000 - 0x0000005fff] io PCI_DOMAIN: 0000 01 <- [0xfce0000000 - 0xfcf87fffff] prefmem PCI_DOMAIN: 0000 02 <- [0x00f8000000 - 0x00fcbfffff] mem Setting variable MTRR 0, base: 0MB, range: 2048MB, type WB Setting variable MTRR 1, base: 2048MB, range: 1024MB, type WB Setting variable MTRR 2, base: 3072MB, range: 512MB, type WB Setting variable MTRR 3, base: 3584MB, range: 256MB, type WB Setting variable MTRR 4, base: 3840MB, range: 128MB, type WB LBsuse91AMD64:~ # lspci -vvxxx -s 3:0.0 0000:03:00.0 InfiniBand: Mellanox Technology MT25208 InfiniHost III Ex HCA (rev a0) Subsystem: Mellanox Technology MT25208 InfiniHost III Ex HCA Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Interrupt: pin A routed to IRQ 18 Region 0: Memory at fc800000 (64-bit, non-prefetchable) Region 2: Memory at fce8000000 (64-bit, prefetchable) [size=8M] Region 4: Memory at fce0000000 (64-bit, prefetchable) [size=128M] Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [48] Vital Product Data Capabilities: [90] Message Signalled Interrupts: 64bit+ Queue=0/5 Enable- Address: 0000000000000000 Data: 0000 Capabilities: [60] #10 [0001] 00: b3 15 78 62 42 01 10 00 a0 00 06 0c 10 00 00 00 10: 04 00 80 fc 00 00 00 00 0c 00 00 e8 fc 00 00 00 20: 0c 00 00 e0 fc 00 00 00 00 00 00 00 b3 15 78 62 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 01 00 00 40: 01 48 02 00 00 00 00 00 03 90 ff 7f 11 11 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 10 00 01 00 c0 0f 00 00 00 20 01 00 81 f4 03 08 70: 00 00 81 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 11 00 1f 00 00 20 08 00 00 22 08 00 90: 05 60 8a 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 LBsuse91AMD64:~ # lspci -vvxxx -s 8:0.0 0000:08:00.0 InfiniBand: Mellanox Technology MT25208 InfiniHost III Ex HCA (rev a0) Subsystem: Mellanox Technology MT25208 InfiniHost III Ex HCA Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Interrupt: pin A routed to IRQ 50 Region 0: Memory at fca00000 (64-bit, non-prefetchable) Region 2: Memory at fcf8000000 (64-bit, prefetchable) [size=8M] Region 4: Memory at fcf0000000 (64-bit, prefetchable) [size=128M] Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [48] Vital Product Data Capabilities: [90] Message Signalled Interrupts: 64bit+ Queue=0/5 Enable- Address: 0000000000000000 Data: 0000 Capabilities: [60] #10 [0001] 00: b3 15 78 62 42 01 10 00 a0 00 06 0c 10 00 00 00 10: 04 00 a0 fc 00 00 00 00 0c 00 00 f8 fc 00 00 00 20: 0c 00 00 f0 fc 00 00 00 00 00 00 00 b3 15 78 62 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 01 00 00 40: 01 48 02 00 00 00 00 00 03 90 ff 7f 11 11 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 10 00 01 00 c0 0f 00 00 00 20 01 00 81 f4 03 08 70: 00 00 81 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 11 00 1f 00 00 20 08 00 00 22 08 00 90: 05 60 8a 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

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RE: Freebios2 recovery progress... pci64 mem optimization
by YhLu 21 Oct '04

21 Oct '04

Another case Align big allocation at first base1: 0xe0000000 limit1: 0xfebfffff size: 0x10000000 align: 28 base2: 0xf0000000 limit2: 0xfebfffff size: 0x06a00000 align: 26 base1: 0xd8000000 limit1: 0xdfffffff size: 0x06a00000 align: 26 base2: 0xe0000000 limit2: 0xfebfffff size: 0x10000000 align: 28 PCI_DOMAIN: 0000 00 <- [0x0000001000 - 0x0000005fff] io PCI_DOMAIN: 0000 01 <- [0x00e0000000 - 0x00efffffff] prefmem PCI_DOMAIN: 0000 02 <- [0x00d8000000 - 0x00de9fffff] mem Align small allocation at first base1: 0xe0000000 limit1: 0xfebfffff size: 0x10000000 align: 28 base2: 0xf0000000 limit2: 0xfebfffff size: 0x06a00000 align: 26 base1: 0xe0000000 limit1: 0xf7ffffff size: 0x10000000 align: 28 base2: 0xf8000000 limit2: 0xfebfffff size: 0x06a00000 align: 26 PCI_DOMAIN: 0000 00 <- [0x0000001000 - 0x0000005fff] io PCI_DOMAIN: 0000 01 <- [0x00e0000000 - 0x00efffffff] prefmem PCI_DOMAIN: 0000 02 <- [0x00f8000000 - 0x00fe9fffff] mem Maybe need to compare the base to find out which one first. -----Original Message----- From: YhLu Sent: Thursday, October 21, 2004 3:57 PM To: ebiederman(a)lnxi.com Cc: LinuxBIOS Subject: RE: Freebios2 recovery progress... pci64 mem optimization Eric, In northbridge.c Another typo error /* If so place the one with the most stringent alignment first */ if (mem2->align > mem1->align) { struct resource *tmp; tmp = mem1; mem1 = mem2; mem2 = mem1; } /* Now place the memory as high up as it will go */ mem2->base = resource_max(mem2); mem1->limit = mem2->base - 1; mem1->base = resource_max(mem1); ----> /* If so place the one with the most stringent alignment first */ if (mem2->align > mem1->align) { struct resource *tmp; tmp = mem1; mem1 = mem2; mem2 = tmp; } /* Now place the memory as high up as it will go */ mem2->base = resource_max(mem2); mem1->limit = mem2->base - 1; mem1->base = resource_max(mem1); Another question is Should do align big allocation at first or align small first. It seems you should do align big allocation. Align big first base1: 0xd0000000 limit1: 0xfebfffff size: 0x18800000 align: 28 base2: 0xec000000 limit2: 0xfebfffff size: 0x06b00000 align: 26 base1: 0xd8000000 limit1: 0xdfffffff size: 0x06b00000 align: 26 base2: 0xe0000000 limit2: 0xfebfffff size: 0x18800000 align: 28 PCI_DOMAIN: 0000 00 <- [0x0000001000 - 0x0000005fff] io PCI_DOMAIN: 0000 01 <- [0x00e0000000 - 0x00f87fffff] prefmem PCI_DOMAIN: 0000 02 <- [0x00d8000000 - 0x00deafffff] mem Align small first base1: 0xd0000000 limit1: 0xfebfffff size: 0x18800000 align: 28 base2: 0xec000000 limit2: 0xfebfffff size: 0x06b00000 align: 26 base1: 0xd0000000 limit1: 0xf7ffffff size: 0x18800000 align: 28 base2: 0xf8000000 limit2: 0xfebfffff size: 0x06b00000 align: 26 PCI_DOMAIN: 0000 00 <- [0x0000001000 - 0x0000005fff] io PCI_DOMAIN: 0000 01 <- [0x00d0000000 - 0x00e87fffff] prefmem PCI_DOMAIN: 0000 02 <- [0x00f8000000 - 0x00feafffff] mem

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