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[LinuxBIOS] Athlon64 939
by YhLu 31 Mar '05

31 Mar '05

The Athlon 64 939 support dual channel. but in the test in s2865 with d0 Athlon64 939 in LinuxBIOS, it only work with one DIMM in socket 1. weird.... the same code with Opteron d0 .... YH > -----Original Message----- > From: YhLu > Sent: Wednesday, March 30, 2005 3:09 PM > To: ebiederman(a)lnxi.com; Kevin O'Connor > Cc: linuxbios(a)openbios.org > Subject: RE: [LinuxBIOS] Re: Error in compiling STPC Consumer > > Eric, > > the code in raminit.c is_opteron will treat my athlon 64 > (939) as Opteron too. > > YH > > static int is_opteron(const struct mem_controller *ctrl) { > /* Test to see if I am an Opteron. > * FIXME Testing dual channel capability is correct for now > * but a beter test is probably required. > */ > #warning "FIXME implement a better test for opterons" > uint32_t nbcap; > nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP); > return !!(nbcap & NBCAP_128Bit); } > > > _______________________________________________ > LinuxBIOS mailing list > LinuxBIOS(a)openbios.org > http://www.openbios.org/mailman/listinfo/linuxbios >

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[LinuxBIOS] Simulator to test BIOS
by Ramesh Chhaba 31 Mar '05

31 Mar '05

Hi all , I want any simulator that i can use as virtual machine to test my romimage without burning it in to actual chip. I there is any such software or alternative . Thank you Ramesh Chander Yahoo! India Matrimony: Find your life partneronline.

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[LinuxBIOS] Simulator to test BIOS
by Ramesh Chhaba 31 Mar '05

31 Mar '05

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Re: [LinuxBIOS] RTC on geode gx1
by ramesh bios 30 Mar '05

30 Mar '05

I noticed that, unlike, some of the other northbridge/southbridge code, the cs5530 code doesn't do an rtc_init(0). I added that and that now allows me to set the date. But... I still have weirdness going on: RTC Init RTC: Checksum invalid zeroing cmos Invalid CMOS LB checksum So now I'm in the process of reading the rtc_init code, looking at the board (I know now that my w83977AF is connected to a 32.768kHz oscillator) and then figuring out what all the settings mean. That is, stuff like below. I'm not sure whether the defaults are good for any board or if they need to be customized. I guess I'll be finding this out iteratively. /* control registers - Moto names */ #define RTC_REG_A 10 #define RTC_REG_B 11 #define RTC_REG_C 12 #define RTC_REG_D 13 #define RTC_FREQ_SELECT RTC_REG_A #define RTC_CONTROL RTC_REG_B #define RTC_CONTROL_DEFAULT (RTC_24H) #define RTC_FREQ_SELECT_DEFAULT (RTC_REF_CLCK_32KHZ | RTC_RATE_1024HZ) --- Peter Stuge <stuge-linuxbios(a)cdy.org> wrote: > On Tue, Mar 29, 2005 at 07:28:00PM -0800, ramesh > bios wrote: > > I'm using the freebios v1 tree on a geode > > gx1/cs5530a/w83977 with 2.6.11. I noticed that > there > > appears to be problem with writing to the RTC > using > > hwclock. I seem to be able to use hwclock to set > the > > time but not the date. That is: > > There are a few bits in the 5530 at page 107 in the > data sheet > regarding the RTC, but I doubt the RTC would be > reachable at all if > they weren't ok. > > I just went over the RTC part of the W83977F data > sheet too and it > seems to have a couple of control bits that may have > to be tweaked > to get proper operation. I don't remember if anyone > else has had > similar problems with that superio. > > Besides timing, the only other explanation I can > think of is that > since time is stored in RTC registers 00h, 02h and > 04h, date of month > in 07h and month/year in 08h-09h, if address bit 3 > wasn't connected > properly then the date registers would be > unreachable, but then you > should see some connection between time and date, so > lack of proper > initialization or possibly a timing issue is my > guess.. > > > //Peter > > _______________________________________________ > LinuxBIOS mailing list > LinuxBIOS(a)openbios.org > http://www.openbios.org/mailman/listinfo/linuxbios > __________________________________ Do you Yahoo!? Yahoo! Mail - now with 250MB free storage. Learn more. http://info.mail.yahoo.com/mail_250

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RE: [LinuxBIOS] Re: Error in compiling STPC Consumer
by YhLu 30 Mar '05

30 Mar '05

Eric, the code in raminit.c is_opteron will treat my athlon 64 (939) as Opteron too. YH static int is_opteron(const struct mem_controller *ctrl) { /* Test to see if I am an Opteron. * FIXME Testing dual channel capability is correct for now * but a beter test is probably required. */ #warning "FIXME implement a better test for opterons" uint32_t nbcap; nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP); return !!(nbcap & NBCAP_128Bit); }

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[LinuxBIOS] RTC on geode gx1
by ramesh bios 30 Mar '05

30 Mar '05

I'm using the freebios v1 tree on a geode gx1/cs5530a/w83977 with 2.6.11. I noticed that there appears to be problem with writing to the RTC using hwclock. I seem to be able to use hwclock to set the time but not the date. That is: # date Wed Mar 30 09:16:11 IST 2005 # hwclock Mon Jan 10 08:56:16 2005 0.000000 seconds # hwclock -w # hwclock Tue Jan 11 09:16:21 2005 0.000000 seconds I noticed that the date went to Jan 11 while the time was updated correctly. When I switch back to the vendor BIOS, this issue goes away. I'm not yet sure what to suspect. I'll go look at the kernel's rtc code for writing to the CMOS since it would appear that it can set the time but not the date for some reason. If anyone has any suggestions, please let me know. Thanks. __________________________________________________ Do You Yahoo!? Tired of spam? Yahoo! Mail has the best spam protection around http://mail.yahoo.com

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[LinuxBIOS] logic error in rom image geomatry
by Ramesh Chhaba 30 Mar '05

30 Mar '05

Hi All , I am trying to understand the boot sequence of PC BIOS I have got an rough idea it is as follows 1. system power up and fetch up first from ffffff0 addr. 2. there is a near jump to code to get system in to flat or protected mode 3. then we can jump to further secod stage bootloader after neccessary HW init. Plz Somebody correct it and explain it in detail . Second thing My BIOS image is ok abt 10 KB (suppose) and i have chip of 256KB So my image is like this ------------------------- lower most address(00000) Second stage bootloader : Protected mode init code : Basic HW init Code : ..ffff0 jmp instruction to Basic HW init code( at bottom ) --------------------------- uppermost address(ffff...) (Fig is reversed as per normal figures in books for memory ) And I want to know where to place this small code in BIG chip ---------------------Chip start addr where to place my code in it ??? ----------------------chip end addr I think start and end of both will be in same direction so it may be like this --------------------------lowest address for chip (free space with ff ff) ------------------------- lower most address(00000) Second stage bootloader : Protected mode init code : Basic HW init Code : ..ffff0 jmp instruction to Basic HW init code( at bottom ) --------------------------- uppermost address(ffff...) both for chip and code Plz comment and correct above information . Thank you Ramesh Chander Yahoo! India Matrimony: Find your life partneronline.

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[LinuxBIOS] Re: Amlcode structure generation
by Stefan Reinauer 29 Mar '05

29 Mar '05

* Peter.VanEchaute(a)bench.com <Peter.VanEchaute(a)bench.com> [050329 23:20]: > I am not a guru on the topic of ACIP or APIC. I am attempting to make a stab > at it and had a question about the file > > src/mainboard/island/aruma/dsdt.c > > My question is how was it created? Using iasl, intel's aml compiler. Stefan

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[LinuxBIOS] Bios "Bible"?
by Justin Walsh 29 Mar '05

29 Mar '05

Or what is the definitive Blue Book on: 1. Bios in General? 3. Bios in particular? 3. How does one switch a 686 or 786 from native into real mode? i.e. 286 emulation? Thanks JW http://en.wikipedia.org/wiki/BIOS Google Search on Bios: http://www.google.com.au/search?hl=en&q=Bios&btnG=Google+Search&meta=

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[LinuxBIOS] Re: NSC sc1100 port
by Peter Stuge 29 Mar '05

29 Mar '05

On Tue, Mar 29, 2005 at 10:40:28AM -0600, Bari Ari wrote: > http://www.amd.com/us-en/ConnectivitySolutions/ProductInformation/0,,50_233… Looks like a smaller sibling of the SCx200s. Might work with little to no modification of the nano code in v1. //Peter

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