Hi list,
I reported about a week ago that I could not get a DigitalLogic
smartcore-p5 PC/104 card to run neither FILO nor Etherboot using
LinuxBIOS v1. Since then, I have kept trying to get it to work, but
still no luck - I'm stuck exactly at the same point as a week ago:
LinuxBIOS seems to startup fine, bit no message ever comes out from
FILO :-(
So here's another try to get some hints from the list.
- Has anybody reported the smartcore-p5 support in v1 to actually work?
- I have attached the config files for LinuxBIOS and FILO below, as
well as the LinuxBIOS serial console output with extensive debugging
output enabled. Can anyone experienced in reading these see anything
unusual here?
- Any suggestions how I should proceed?
I'd really appreciate some help here, since without it I'll probably
have to give up using the LinuxBIOS at this point.
Cheers, /Kjell
LinuxBIOS config:
----------------
# Sample config file for Intel 430TX chipset on the Smartcore P5
# This will make a target directory of ./smartcore-p5
target smartcore-p5
# ASUS CUA main board
mainboard digitallogic/smartcore-p5
# option HAVE_PIRQ_TABLE=1
# Enable Serial Console for debugging
option SERIAL_CONSOLE=1
option SERIAL_POST=1
option NO_KEYBOARD=1
#option INBUF_COPY=1
option DEBUG=1
option DEFAULT_CONSOLE_LOGLEVEL=9
option MAXIMUM_CONSOLE_LOGLEVEL=10
# MEMORY TESTING USING MEMTEST
# option RAMTEST=1
option USE_GENERIC_ROM=1
# option ROM_SIZE=131072
# option ROM_SIZE=524288
option ROM_SIZE=262144
# option STD_FLASH=1
# option PAYLOAD_SIZE=65536
# option PAYLOAD_SIZE=458752
option PAYLOAD_SIZE=196608
option CONFIG_COMPRESS=1
option USE_ELF_BOOT=1
payload ../filo.elf
# payload ../eepro100.elf
FILO Config:
------------
# !!! NOTE !!!
# Do NOT add spaces or comments at the end of option lines.
# It confuses some versions of make.
# Image filename for automatic boot and optional command line parameter
AUTOBOOT_FILE = "hdc1:/bzImage root=/dev/hdc2 rw console=tty0
console=ttyS0,115200"
# Time in second before booting AUTOBOOT_FILE
AUTOBOOT_DELAY = 5
# Driver for hard disk, CompactFlash, and CD-ROM on IDE bus
IDE_DISK = 1
# VGA text console
#VGA_CONSOLE = 0
#PC_KEYBOARD = 0
# Serial console
SERIAL_CONSOLE = 1
SERIAL_IOBASE = 0x3f8
SERIAL_SPEED = 115200
# Filesystems
FSYS_EXT2FS = 1
#FSYS_FAT = 0
#FSYS_JFS = 0
#FSYS_MINIX = 0
#FSYS_REISERFS = 0
#FSYS_XFS = 0
#FSYS_ISO9660 = 0
# Support for boot disk image in bootable CD-ROM (El Torito)
#ELTORITO = 0
# PCI support
SUPPORT_PCI = 1
# Enable this if not all PCI buses are scanned (you can see it with
DEBUG_PCI)
# K8-based boards may need it
#PCI_BRUTE_SCAN = 1
# Sound support (needs SUPPORT_PCI)
#SUPPORT_SOUND = 1
# Sound drivers
#VIA_SOUND = 1
# Debugging
DEBUG_ALL = 1
#DEBUG_ELFBOOT = 1
#DEBUG_ELFNOTE = 1
#DEBUG_LINUXBIOS = 1
#DEBUG_MALLOC = 1
#DEBUG_MULTIBOOT = 1
#DEBUG_SEGMENT = 1
#DEBUG_SYS_INFO = 1
#DEBUG_TIMER = 1
#DEBUG_BLOCKDEV = 1
#DEBUG_PCI = 1
#DEBUG_VIA_SOUND = 1
#DEBUG_LINUXLOAD = 1
#DEBUG_IDE = 1
#DEBUG_ELTORITO = 1
# i386 options
# Loader for standard Linux kernel image, a.k.a. /vmlinuz
LINUX_LOADER = 1
# Boot FILO from Multiboot loader (eg. GRUB)
MULTIBOOT_IMAGE = 1
# Use PCI Configuration Mechanism #1 (most boards)
PCI_CONFIG_1 = 1
LinuxBIOS serial console output (extensive debugging enabled):
---------------------------------------------------------------
LinuxBIOS-1.0.0 Mon May 16 14:25:45 CEST 2005 starting...
Ram1
After 0x0000000 nop...
Before 0x4000000 nop...
After 0x4000000 nop...
After 0x54...
After 0x00...
Before 0x4000000 nop...
After 0x4000000 nop...
After 0x4000000 nop...
Before 0x4000000 nop...
After 0x4000000 nop...
After 0x0000000 nop...
Before 0x4000000 nop...
After 0x4000000 nop...
After 0x54...
After 0x00...
Before 0x4000000 nop...
After 0x4000000 nop...
After 0x4000000 nop...
First DRAM setup done
Ram2
Ram3
Ram Enable 1
Ram Enable 2
Ram Enable 3
Ram Enable 4
Ram Enable 5
Ram4
Ram5
Ram6
Copying LinuxBIOS to ram.
Jumping to LinuxBIOS.
POST: 0x39
LinuxBIOS-1.0.0 Mon May 16 14:25:45 CEST 2005 booting...
POST: 0x40
Finding PCI configuration type.
PCI: Using configuration type 1
POST: 0x5f
Scanning PCI bus...PCI: pci_scan_bus for bus 0
POST: 0x24
Read config dword bus 0,devfn 0x0,reg 0x0,val 0x71008086,res 0x0
Read config byte bus 0,devfn 0x0,reg 0xe,val 0x0,res 0x0
Read config dword bus 0,devfn 0x0,reg 0x8,val 0x6000001,res 0x0
malloc Enter, size 204, free_mem_ptr 0001100c
malloc 0x0001100c
Read config byte bus 0,devfn 0x0,reg 0x4,val 0x6,res 0x0
Write config byte bus 0, devfn 0x0, reg 0x4, val 0x6
Read config byte bus 0,devfn 0x0,reg 0x4,val 0x6,res 0x0
Write config byte bus 0, devfn 0x0, reg 0x4, val 0x6
PCI: 00:00.0 [8086/7100]
Read config dword bus 0,devfn 0x8,reg 0x0,val 0xffffffff,res 0x0
PCI: devfn 0x8, bad id 0xffffffff
Read config dword bus 0,devfn 0x10,reg 0x0,val 0xffffffff,res 0x0
PCI: devfn 0x10, bad id 0xffffffff
Read config dword bus 0,devfn 0x18,reg 0x0,val 0xffffffff,res 0x0
PCI: devfn 0x18, bad id 0xffffffff
Read config dword bus 0,devfn 0x20,reg 0x0,val 0xffffffff,res 0x0
PCI: devfn 0x20, bad id 0xffffffff
Read config dword bus 0,devfn 0x28,reg 0x0,val 0xffffffff,res 0x0
PCI: devfn 0x28, bad id 0xffffffff
Read config dword bus 0,devfn 0x30,reg 0x0,val 0xffffffff,res 0x0
PCI: devfn 0x30, bad id 0xffffffff
Read config dword bus 0,devfn 0x38,reg 0x0,val 0x71108086,res 0x0
Read config byte bus 0,devfn 0x38,reg 0xe,val 0x80,res 0x0
Read config dword bus 0,devfn 0x38,reg 0x8,val 0x6010002,res 0x0
malloc Enter, size 204, free_mem_ptr 000110d8
malloc 0x000110d8
Read config byte bus 0,devfn 0x38,reg 0x4,val 0x7,res 0x0
Write config byte bus 0, devfn 0x38, reg 0x4, val 0x7
Read config byte bus 0,devfn 0x38,reg 0x4,val 0x7,res 0x0
Write config byte bus 0, devfn 0x38, reg 0x4, val 0x7
PCI: 00:07.0 [8086/7110]
Read config dword bus 0,devfn 0x39,reg 0x0,val 0x71118086,res 0x0
Read config byte bus 0,devfn 0x39,reg 0xe,val 0x0,res 0x0
Read config dword bus 0,devfn 0x39,reg 0x8,val 0x1018001,res 0x0
malloc Enter, size 204, free_mem_ptr 000111a4
malloc 0x000111a4
Read config byte bus 0,devfn 0x39,reg 0x4,val 0x0,res 0x0
Write config byte bus 0, devfn 0x39, reg 0x4, val 0x4
Read config byte bus 0,devfn 0x39,reg 0x4,val 0x4,res 0x0
Write config byte bus 0, devfn 0x39, reg 0x4, val 0x0
PCI: 00:07.1 [8086/7111]
Read config dword bus 0,devfn 0x3a,reg 0x0,val 0x71128086,res 0x0
Read config byte bus 0,devfn 0x3a,reg 0xe,val 0x0,res 0x0
Read config dword bus 0,devfn 0x3a,reg 0x8,val 0xc030001,res 0x0
malloc Enter, size 204, free_mem_ptr 00011270
malloc 0x00011270
Read config byte bus 0,devfn 0x3a,reg 0x4,val 0x0,res 0x0
Write config byte bus 0, devfn 0x3a, reg 0x4, val 0x4
Read config byte bus 0,devfn 0x3a,reg 0x4,val 0x4,res 0x0
Write config byte bus 0, devfn 0x3a, reg 0x4, val 0x0
PCI: 00:07.2 [8086/7112]
Read config dword bus 0,devfn 0x3b,reg 0x0,val 0x71138086,res 0x0
Read config byte bus 0,devfn 0x3b,reg 0xe,val 0x0,res 0x0
Read config dword bus 0,devfn 0x3b,reg 0x8,val 0x6800002,res 0x0
malloc Enter, size 204, free_mem_ptr 0001133c
malloc 0x0001133c
Read config byte bus 0,devfn 0x3b,reg 0x4,val 0x0,res 0x0
Write config byte bus 0, devfn 0x3b, reg 0x4, val 0x4
Read config byte bus 0,devfn 0x3b,reg 0x4,val 0x0,res 0x0
Write config byte bus 0, devfn 0x3b, reg 0x4, val 0x0
PCI: 00:07.3 [8086/7113]
Read config dword bus 0,devfn 0x3c,reg 0x0,val 0xffffffff,res 0x0
PCI: devfn 0x3c, bad id 0xffffffff
Read config dword bus 0,devfn 0x3d,reg 0x0,val 0xffffffff,res 0x0
PCI: devfn 0x3d, bad id 0xffffffff
Read config dword bus 0,devfn 0x3e,reg 0x0,val 0xffffffff,res 0x0
PCI: devfn 0x3e, bad id 0xffffffff
Read config dword bus 0,devfn 0x3f,reg 0x0,val 0xffffffff,res 0x0
PCI: devfn 0x3f, bad id 0xffffffff
Read config dword bus 0,devfn 0x40,reg 0x0,val 0xffffffff,res 0x0
PCI: devfn 0x40, bad id 0xffffffff
Read config dword bus 0,devfn 0x48,reg 0x0,val 0xffffffff,res 0x0
PCI: devfn 0x48, bad id 0xffffffff
Read config dword bus 0,devfn 0x50,reg 0x0,val 0xffffffff,res 0x0
PCI: devfn 0x50, bad id 0xffffffff
Read config dword bus 0,devfn 0x58,reg 0x0,val 0xffffffff,res 0x0
PCI: devfn 0x58, bad id 0xffffffff
Read config dword bus 0,devfn 0x60,reg 0x0,val 0xffffffff,res 0x0
PCI: devfn 0x60, bad id 0xffffffff
Read config dword bus 0,devfn 0x68,reg 0x0,val 0xffffffff,res 0x0
PCI: devfn 0x68, bad id 0xffffffff
Read config dword bus 0,devfn 0x70,reg 0x0,val 0xffffffff,res 0x0
PCI: devfn 0x70, bad id 0xffffffff
Read config dword bus 0,devfn 0x78,reg 0x0,val 0xffffffff,res 0x0
PCI: devfn 0x78, bad id 0xffffffff
Read config dword bus 0,devfn 0x80,reg 0x0,val 0xffffffff,res 0x0
PCI: devfn 0x80, bad id 0xffffffff
Read config dword bus 0,devfn 0x88,reg 0x0,val 0xffffffff,res 0x0
PCI: devfn 0x88, bad id 0xffffffff
Read config dword bus 0,devfn 0x90,reg 0x0,val 0x12098086,res 0x0
Read config byte bus 0,devfn 0x90,reg 0xe,val 0x0,res 0x0
Read config dword bus 0,devfn 0x90,reg 0x8,val 0x2000010,res 0x0
malloc Enter, size 204, free_mem_ptr 00011408
malloc 0x00011408
Read config byte bus 0,devfn 0x90,reg 0x4,val 0x0,res 0x0
Write config byte bus 0, devfn 0x90, reg 0x4, val 0x4
Read config byte bus 0,devfn 0x90,reg 0x4,val 0x4,res 0x0
Write config byte bus 0, devfn 0x90, reg 0x4, val 0x0
PCI: 00:12.0 [8086/1209]
Read config dword bus 0,devfn 0x98,reg 0x0,val 0xffffffff,res 0x0
PCI: devfn 0x98, bad id 0xffffffff
Read config dword bus 0,devfn 0xa0,reg 0x0,val 0xffffffff,res 0x0
PCI: devfn 0xa0, bad id 0xffffffff
Read config dword bus 0,devfn 0xa8,reg 0x0,val 0xffffffff,res 0x0
PCI: devfn 0xa8, bad id 0xffffffff
Read config dword bus 0,devfn 0xb0,reg 0x0,val 0xffffffff,res 0x0
PCI: devfn 0xb0, bad id 0xffffffff
Read config dword bus 0,devfn 0xb8,reg 0x0,val 0xffffffff,res 0x0
PCI: devfn 0xb8, bad id 0xffffffff
Read config dword bus 0,devfn 0xc0,reg 0x0,val 0xffffffff,res 0x0
PCI: devfn 0xc0, bad id 0xffffffff
Read config dword bus 0,devfn 0xc8,reg 0x0,val 0xffffffff,res 0x0
PCI: devfn 0xc8, bad id 0xffffffff
Read config dword bus 0,devfn 0xd0,reg 0x0,val 0xffffffff,res 0x0
PCI: devfn 0xd0, bad id 0xffffffff
Read config dword bus 0,devfn 0xd8,reg 0x0,val 0xffffffff,res 0x0
PCI: devfn 0xd8, bad id 0xffffffff
Read config dword bus 0,devfn 0xe0,reg 0x0,val 0xffffffff,res 0x0
PCI: devfn 0xe0, bad id 0xffffffff
Read config dword bus 0,devfn 0xe8,reg 0x0,val 0xffffffff,res 0x0
PCI: devfn 0xe8, bad id 0xffffffff
Read config dword bus 0,devfn 0xf0,reg 0x0,val 0xffffffff,res 0x0
PCI: devfn 0xf0, bad id 0xffffffff
Read config dword bus 0,devfn 0xf8,reg 0x0,val 0xffffffff,res 0x0
PCI: devfn 0xf8, bad id 0xffffffff
POST: 0x25
PCI: pci_scan_bus returning with max=00
POST: 0x55
done
POST: 0x66
Allocating PCI resources...
PCI: 00:00.0 compute_allocate_io: base: 00000400 size: 00000000 align:
0 gran: 0
Read config dword bus 0,devfn 0x0,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x10, val 0xffffffff
Read config dword bus 0,devfn 0x0,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x10, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x10, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x14, val 0xffffffff
Read config dword bus 0,devfn 0x0,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x14, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x14, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x18, val 0xffffffff
Read config dword bus 0,devfn 0x0,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x18, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x18, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x1c, val 0xffffffff
Read config dword bus 0,devfn 0x0,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x1c, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x1c, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x20, val 0xffffffff
Read config dword bus 0,devfn 0x0,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x20, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x20, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x24, val 0xffffffff
Read config dword bus 0,devfn 0x0,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x24, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x24, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x30,val 0x0,res 0x0
Read config dword bus 0,devfn 0x38,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x10, val 0xffffffff
Read config dword bus 0,devfn 0x38,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x10, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x10, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x14, val 0xffffffff
Read config dword bus 0,devfn 0x38,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x14, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x14, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x18, val 0xffffffff
Read config dword bus 0,devfn 0x38,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x18, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x18, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x1c, val 0xffffffff
Read config dword bus 0,devfn 0x38,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x1c, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x1c, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x20, val 0xffffffff
Read config dword bus 0,devfn 0x38,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x20, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x20, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x24, val 0xffffffff
Read config dword bus 0,devfn 0x38,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x24, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x24, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x30,val 0x0,res 0x0
Read config dword bus 0,devfn 0x39,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x39, reg 0x10, val 0xffffffff
Read config dword bus 0,devfn 0x39,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x39, reg 0x10, val 0x0
Read config dword bus 0,devfn 0x39,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x39, reg 0x10, val 0x0
Read config dword bus 0,devfn 0x39,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x39, reg 0x14, val 0xffffffff
Read config dword bus 0,devfn 0x39,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x39, reg 0x14, val 0x0
Read config dword bus 0,devfn 0x39,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x39, reg 0x14, val 0x0
Read config dword bus 0,devfn 0x39,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x39, reg 0x18, val 0xffffffff
Read config dword bus 0,devfn 0x39,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x39, reg 0x18, val 0x0
Read config dword bus 0,devfn 0x39,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x39, reg 0x18, val 0x0
Read config dword bus 0,devfn 0x39,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x39, reg 0x1c, val 0xffffffff
Read config dword bus 0,devfn 0x39,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x39, reg 0x1c, val 0x0
Read config dword bus 0,devfn 0x39,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x39, reg 0x1c, val 0x0
Read config dword bus 0,devfn 0x39,reg 0x20,val 0x1,res 0x0
Write config dword bus 0, devfn 0x39, reg 0x20, val 0xffffffff
Read config dword bus 0,devfn 0x39,reg 0x20,val 0xfff1,res 0x0
Write config dword bus 0, devfn 0x39, reg 0x20, val 0x0
Read config dword bus 0,devfn 0x39,reg 0x20,val 0x1,res 0x0
Write config dword bus 0, devfn 0x39, reg 0x20, val 0x1
Read config dword bus 0,devfn 0x39,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x39, reg 0x24, val 0xffffffff
Read config dword bus 0,devfn 0x39,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x39, reg 0x24, val 0x0
Read config dword bus 0,devfn 0x39,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x39, reg 0x24, val 0x0
Read config dword bus 0,devfn 0x39,reg 0x30,val 0x0,res 0x0
Read config dword bus 0,devfn 0x3a,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3a, reg 0x10, val 0xffffffff
Read config dword bus 0,devfn 0x3a,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3a, reg 0x10, val 0x0
Read config dword bus 0,devfn 0x3a,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3a, reg 0x10, val 0x0
Read config dword bus 0,devfn 0x3a,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3a, reg 0x14, val 0xffffffff
Read config dword bus 0,devfn 0x3a,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3a, reg 0x14, val 0x0
Read config dword bus 0,devfn 0x3a,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3a, reg 0x14, val 0x0
Read config dword bus 0,devfn 0x3a,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3a, reg 0x18, val 0xffffffff
Read config dword bus 0,devfn 0x3a,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3a, reg 0x18, val 0x0
Read config dword bus 0,devfn 0x3a,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3a, reg 0x18, val 0x0
Read config dword bus 0,devfn 0x3a,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3a, reg 0x1c, val 0xffffffff
Read config dword bus 0,devfn 0x3a,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3a, reg 0x1c, val 0x0
Read config dword bus 0,devfn 0x3a,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3a, reg 0x1c, val 0x0
Read config dword bus 0,devfn 0x3a,reg 0x20,val 0x1,res 0x0
Write config dword bus 0, devfn 0x3a, reg 0x20, val 0xffffffff
Read config dword bus 0,devfn 0x3a,reg 0x20,val 0xffe1,res 0x0
Write config dword bus 0, devfn 0x3a, reg 0x20, val 0x0
Read config dword bus 0,devfn 0x3a,reg 0x20,val 0x1,res 0x0
Write config dword bus 0, devfn 0x3a, reg 0x20, val 0x1
Read config dword bus 0,devfn 0x3a,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3a, reg 0x24, val 0xffffffff
Read config dword bus 0,devfn 0x3a,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3a, reg 0x24, val 0x0
Read config dword bus 0,devfn 0x3a,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3a, reg 0x24, val 0x0
Read config dword bus 0,devfn 0x3a,reg 0x30,val 0x0,res 0x0
Read config dword bus 0,devfn 0x3b,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x10, val 0xffffffff
Read config dword bus 0,devfn 0x3b,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x10, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x10, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x14, val 0xffffffff
Read config dword bus 0,devfn 0x3b,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x14, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x14, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x18, val 0xffffffff
Read config dword bus 0,devfn 0x3b,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x18, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x18, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x1c, val 0xffffffff
Read config dword bus 0,devfn 0x3b,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x1c, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x1c, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x20, val 0xffffffff
Read config dword bus 0,devfn 0x3b,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x20, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x20, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x24, val 0xffffffff
Read config dword bus 0,devfn 0x3b,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x24, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x24, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x30,val 0x0,res 0x0
Read config dword bus 0,devfn 0x90,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x90, reg 0x10, val 0xffffffff
Read config dword bus 0,devfn 0x90,reg 0x10,val 0xfffff000,res 0x0
Write config dword bus 0, devfn 0x90, reg 0x10, val 0x0
Read config dword bus 0,devfn 0x90,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x90, reg 0x10, val 0x0
Read config dword bus 0,devfn 0x90,reg 0x14,val 0x1,res 0x0
Write config dword bus 0, devfn 0x90, reg 0x14, val 0xffffffff
Read config dword bus 0,devfn 0x90,reg 0x14,val 0xffffffc1,res 0x0
Write config dword bus 0, devfn 0x90, reg 0x14, val 0x0
Read config dword bus 0,devfn 0x90,reg 0x14,val 0x1,res 0x0
Write config dword bus 0, devfn 0x90, reg 0x14, val 0x1
Read config dword bus 0,devfn 0x90,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x90, reg 0x18, val 0xffffffff
Read config dword bus 0,devfn 0x90,reg 0x18,val 0xfffe0000,res 0x0
Write config dword bus 0, devfn 0x90, reg 0x18, val 0x0
Read config dword bus 0,devfn 0x90,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x90, reg 0x18, val 0x0
Read config dword bus 0,devfn 0x90,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x90, reg 0x1c, val 0xffffffff
Read config dword bus 0,devfn 0x90,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x90, reg 0x1c, val 0x0
Read config dword bus 0,devfn 0x90,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x90, reg 0x1c, val 0x0
Read config dword bus 0,devfn 0x90,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x90, reg 0x20, val 0xffffffff
Read config dword bus 0,devfn 0x90,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x90, reg 0x20, val 0x0
Read config dword bus 0,devfn 0x90,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x90, reg 0x20, val 0x0
Read config dword bus 0,devfn 0x90,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x90, reg 0x24, val 0xffffffff
Read config dword bus 0,devfn 0x90,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x90, reg 0x24, val 0x0
Read config dword bus 0,devfn 0x90,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x90, reg 0x24, val 0x0
Read config dword bus 0,devfn 0x90,reg 0x30,val 0x0,res 0x0
PCI: 00:12.0 14 * [0x00000400 - 0x0000043f] io
PCI: 00:07.2 20 * [0x00000440 - 0x0000045f] io
PCI: 00:07.1 20 * [0x00000460 - 0x0000046f] io
PCI: 00:00.0 compute_allocate_io: base: 00000470 size: 00000070 align:
6 gran: 0 done
PCI: 00:00.0 compute_allocate_mem: base: 00000000 size: 00000000 align:
0 gran: 0
Read config dword bus 0,devfn 0x0,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x10, val 0xffffffff
Read config dword bus 0,devfn 0x0,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x10, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x10, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x14, val 0xffffffff
Read config dword bus 0,devfn 0x0,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x14, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x14, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x18, val 0xffffffff
Read config dword bus 0,devfn 0x0,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x18, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x18, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x1c, val 0xffffffff
Read config dword bus 0,devfn 0x0,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x1c, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x1c, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x20, val 0xffffffff
Read config dword bus 0,devfn 0x0,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x20, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x20, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x24, val 0xffffffff
Read config dword bus 0,devfn 0x0,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x24, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x24, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x30,val 0x0,res 0x0
Read config dword bus 0,devfn 0x38,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x10, val 0xffffffff
Read config dword bus 0,devfn 0x38,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x10, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x10, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x14, val 0xffffffff
Read config dword bus 0,devfn 0x38,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x14, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x14, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x18, val 0xffffffff
Read config dword bus 0,devfn 0x38,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x18, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x18, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x1c, val 0xffffffff
Read config dword bus 0,devfn 0x38,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x1c, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x1c, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x20, val 0xffffffff
Read config dword bus 0,devfn 0x38,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x20, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x20, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x24, val 0xffffffff
Read config dword bus 0,devfn 0x38,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x24, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x24, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x30,val 0x0,res 0x0
Read config dword bus 0,devfn 0x3b,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x10, val 0xffffffff
Read config dword bus 0,devfn 0x3b,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x10, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x10, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x14, val 0xffffffff
Read config dword bus 0,devfn 0x3b,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x14, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x14, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x18, val 0xffffffff
Read config dword bus 0,devfn 0x3b,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x18, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x18, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x1c, val 0xffffffff
Read config dword bus 0,devfn 0x3b,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x1c, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x1c, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x20, val 0xffffffff
Read config dword bus 0,devfn 0x3b,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x20, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x20, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x24, val 0xffffffff
Read config dword bus 0,devfn 0x3b,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x24, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x24, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x30,val 0x0,res 0x0
PCI: 00:12.0 18 * [0x00000000 - 0x0001ffff] mem
PCI: 00:12.0 10 * [0x00020000 - 0x00020fff] mem
PCI: 00:00.0 compute_allocate_mem: base: 00021000 size: 00021000 align:
17 gran: 0 done
PCI: 00:00.0 compute_allocate_io: base: 00001000 size: 00000070 align:
6 gran: 0
Read config dword bus 0,devfn 0x0,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x10, val 0xffffffff
Read config dword bus 0,devfn 0x0,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x10, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x10, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x14, val 0xffffffff
Read config dword bus 0,devfn 0x0,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x14, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x14, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x18, val 0xffffffff
Read config dword bus 0,devfn 0x0,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x18, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x18, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x1c, val 0xffffffff
Read config dword bus 0,devfn 0x0,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x1c, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x1c, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x20, val 0xffffffff
Read config dword bus 0,devfn 0x0,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x20, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x20, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x24, val 0xffffffff
Read config dword bus 0,devfn 0x0,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x24, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x24, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x30,val 0x0,res 0x0
Read config dword bus 0,devfn 0x38,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x10, val 0xffffffff
Read config dword bus 0,devfn 0x38,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x10, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x10, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x14, val 0xffffffff
Read config dword bus 0,devfn 0x38,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x14, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x14, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x18, val 0xffffffff
Read config dword bus 0,devfn 0x38,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x18, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x18, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x1c, val 0xffffffff
Read config dword bus 0,devfn 0x38,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x1c, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x1c, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x20, val 0xffffffff
Read config dword bus 0,devfn 0x38,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x20, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x20, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x24, val 0xffffffff
Read config dword bus 0,devfn 0x38,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x24, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x24, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x30,val 0x0,res 0x0
Read config dword bus 0,devfn 0x3b,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x10, val 0xffffffff
Read config dword bus 0,devfn 0x3b,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x10, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x10, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x14, val 0xffffffff
Read config dword bus 0,devfn 0x3b,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x14, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x14, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x18, val 0xffffffff
Read config dword bus 0,devfn 0x3b,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x18, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x18, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x1c, val 0xffffffff
Read config dword bus 0,devfn 0x3b,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x1c, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x1c, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x20, val 0xffffffff
Read config dword bus 0,devfn 0x3b,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x20, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x20, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x24, val 0xffffffff
Read config dword bus 0,devfn 0x3b,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x24, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x24, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x30,val 0x0,res 0x0
PCI: 00:12.0 14 * [0x00001000 - 0x0000103f] io
PCI: 00:07.2 20 * [0x00001040 - 0x0000105f] io
PCI: 00:07.1 20 * [0x00001060 - 0x0000106f] io
PCI: 00:00.0 compute_allocate_io: base: 00001070 size: 00000070 align:
6 gran: 0 done
PCI: 00:00.0 compute_allocate_mem: base: febc0000 size: 00021000 align:
17 gran: 0
Read config dword bus 0,devfn 0x0,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x10, val 0xffffffff
Read config dword bus 0,devfn 0x0,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x10, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x10, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x14, val 0xffffffff
Read config dword bus 0,devfn 0x0,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x14, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x14, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x18, val 0xffffffff
Read config dword bus 0,devfn 0x0,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x18, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x18, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x1c, val 0xffffffff
Read config dword bus 0,devfn 0x0,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x1c, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x1c, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x20, val 0xffffffff
Read config dword bus 0,devfn 0x0,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x20, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x20, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x24, val 0xffffffff
Read config dword bus 0,devfn 0x0,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x24, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x0, reg 0x24, val 0x0
Read config dword bus 0,devfn 0x0,reg 0x30,val 0x0,res 0x0
Read config dword bus 0,devfn 0x38,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x10, val 0xffffffff
Read config dword bus 0,devfn 0x38,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x10, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x10, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x14, val 0xffffffff
Read config dword bus 0,devfn 0x38,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x14, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x14, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x18, val 0xffffffff
Read config dword bus 0,devfn 0x38,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x18, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x18, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x1c, val 0xffffffff
Read config dword bus 0,devfn 0x38,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x1c, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x1c, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x20, val 0xffffffff
Read config dword bus 0,devfn 0x38,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x20, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x20, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x24, val 0xffffffff
Read config dword bus 0,devfn 0x38,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x24, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x38, reg 0x24, val 0x0
Read config dword bus 0,devfn 0x38,reg 0x30,val 0x0,res 0x0
Read config dword bus 0,devfn 0x3b,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x10, val 0xffffffff
Read config dword bus 0,devfn 0x3b,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x10, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x10,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x10, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x14, val 0xffffffff
Read config dword bus 0,devfn 0x3b,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x14, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x14,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x14, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x18, val 0xffffffff
Read config dword bus 0,devfn 0x3b,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x18, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x18,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x18, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x1c, val 0xffffffff
Read config dword bus 0,devfn 0x3b,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x1c, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x1c,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x1c, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x20, val 0xffffffff
Read config dword bus 0,devfn 0x3b,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x20, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x20,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x20, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x24, val 0xffffffff
Read config dword bus 0,devfn 0x3b,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x24, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x24,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x24, val 0x0
Read config dword bus 0,devfn 0x3b,reg 0x30,val 0x0,res 0x0
PCI: 00:12.0 18 * [0xfebc0000 - 0xfebdffff] mem
PCI: 00:12.0 10 * [0xfebe0000 - 0xfebe0fff] mem
PCI: 00:00.0 compute_allocate_mem: base: febe1000 size: 00021000 align:
17 gran: 0 done
ASSIGN RESOURCES, bus 0
Write config byte bus 0, devfn 0x0, reg 0xd, val 0x40
Read config byte bus 0,devfn 0x0,reg 0x3d,val 0x0,res 0x0
Write config byte bus 0, devfn 0x0, reg 0xc, val 0x10
Write config byte bus 0, devfn 0x38, reg 0xd, val 0x40
Read config byte bus 0,devfn 0x38,reg 0x3d,val 0x0,res 0x0
Write config byte bus 0, devfn 0x38, reg 0xc, val 0x10
Write config dword bus 0, devfn 0x39, reg 0x20, val 0x1061
PCI: 00:07.1 20 <- [0x00001060 - 0x0000106f] io
Write config byte bus 0, devfn 0x39, reg 0xd, val 0x40
Read config byte bus 0,devfn 0x39,reg 0x3d,val 0x0,res 0x0
Write config byte bus 0, devfn 0x39, reg 0xc, val 0x10
Write config dword bus 0, devfn 0x3a, reg 0x20, val 0x1041
PCI: 00:07.2 20 <- [0x00001040 - 0x0000105f] io
Write config byte bus 0, devfn 0x3a, reg 0xd, val 0x40
Read config byte bus 0,devfn 0x3a,reg 0x3d,val 0x4,res 0x0
Write config byte bus 0, devfn 0x3a, reg 0x3c, val 0x0
Write config byte bus 0, devfn 0x3a, reg 0xc, val 0x10
Write config byte bus 0, devfn 0x3b, reg 0xd, val 0x40
Read config byte bus 0,devfn 0x3b,reg 0x3d,val 0x0,res 0x0
Write config byte bus 0, devfn 0x3b, reg 0xc, val 0x10
Write config dword bus 0, devfn 0x90, reg 0x10, val 0xfebe0000
PCI: 00:12.0 10 <- [0xfebe0000 - 0xfebe0fff] mem
Write config dword bus 0, devfn 0x90, reg 0x14, val 0x1001
PCI: 00:12.0 14 <- [0x00001000 - 0x0000103f] io
Write config dword bus 0, devfn 0x90, reg 0x18, val 0xfebc0000
PCI: 00:12.0 18 <- [0xfebc0000 - 0xfebdffff] mem
Write config byte bus 0, devfn 0x90, reg 0xd, val 0x40
Read config byte bus 0,devfn 0x90,reg 0x3d,val 0x1,res 0x0
Write config byte bus 0, devfn 0x90, reg 0x3c, val 0x0
Write config byte bus 0, devfn 0x90, reg 0xc, val 0x10
ASSIGNED RESOURCES, bus 0
Read config dword bus 0,devfn 0x0,reg 0x8,val 0x6000001,res 0x0
Read config dword bus 0,devfn 0x38,reg 0x8,val 0x6010002,res 0x0
Read config dword bus 0,devfn 0x39,reg 0x8,val 0x1018001,res 0x0
Read config dword bus 0,devfn 0x3a,reg 0x8,val 0xc030001,res 0x0
Read config dword bus 0,devfn 0x3b,reg 0x8,val 0x6800002,res 0x0
Read config dword bus 0,devfn 0x90,reg 0x8,val 0x2000010,res 0x0
done.
POST: 0x88
Enabling PCI resourcess...Read config word bus 0,devfn 0x0,reg 0x4,val
0x6,res 0x0
PCI: 00:00.0 cmd <- 06
Write config word bus 0, devfn 0x0, reg 0x4, val 0x6
Read config word bus 0,devfn 0x38,reg 0x4,val 0x7,res 0x0
PCI: 00:07.0 cmd <- 07
Write config word bus 0, devfn 0x38, reg 0x4, val 0x7
Read config word bus 0,devfn 0x39,reg 0x4,val 0x0,res 0x0
PCI: 00:07.1 cmd <- 01
Write config word bus 0, devfn 0x39, reg 0x4, val 0x1
Read config word bus 0,devfn 0x3a,reg 0x4,val 0x0,res 0x0
PCI: 00:07.2 cmd <- 01
Write config word bus 0, devfn 0x3a, reg 0x4, val 0x1
Read config word bus 0,devfn 0x3b,reg 0x4,val 0x0,res 0x0
PCI: 00:07.3 cmd <- 00
Write config word bus 0, devfn 0x3b, reg 0x4, val 0x0
Read config word bus 0,devfn 0x90,reg 0x4,val 0x0,res 0x0
PCI: 00:12.0 cmd <- 03
Write config word bus 0, devfn 0x90, reg 0x4, val 0x3
done.
Initializing PCI devices...
PCI devices initialized
POST: 0x89
Read config byte bus 0,devfn 0x0,reg 0x65,val 0x20,res 0x0
POST: 0x70
totalram: 128M
Initializing CPU #0
POST: 0x60
Enabling cache...POST: 0x6a
done.
Max cpuid index : 1
Vendor ID : GenuineIntel
Processor Type : 0x00
Processor Family : 0x05
Processor Model : 0x08
Processor Mask : 0x00
Processor Stepping : 0x01
Feature flags : 0x008001bf
POST: 0x92
done.
POST: 0x9b
CPU #0 Initialized
BOOT CPU is 0
intel_mainboard_fixup()
Write config byte bus 0, devfn 0x0, reg 0x3c, val 0x15
Testing SMI
Read config dword bus 0,devfn 0x3b,reg 0x58,val 0x0,res 0x0
Write config dword bus 0, devfn 0x3b, reg 0x58, val 0x2000000
SMI disabled
POST: 0x75
POST: 0x77
POST: 0x91
POST: 0x92
Enabling extended BIOS access
Enabling Full ISA Mode
Read config byte bus 0,devfn 0x38,reg 0xb0,val 0x0,res 0x0
Write config byte bus 0, devfn 0x38, reg 0xb0, val 0x1
Enabling IRQ8
Read config byte bus 0,devfn 0x38,reg 0xb1,val 0x0,res 0x0
Write config byte bus 0, devfn 0x38, reg 0xb1, val 0x40
Enabling Mouse IRQ12 on piix4e
Write config word bus 0, devfn 0x38, reg 0x4e, val 0x3f1
done.
POST: 0x91
POST: 0x95
POST: 0xec
POST: 0x9a
Checking IRQ routing tables...
/home/ks/proj/p513_Tiburtius/fastboot/freebios-1.0/src/arch/i386/lib/
pirq_routing.c: 30:check_pirq_routing_table() - irq_routing_table
located at: 0x000087c0
done.
Copying IRQ routing tables to 0xf0000...done.
Verifing priq routing tables copy at 0xf0000...failed
POST: 0x96
Wrote linuxbios table at: 00000500 - 00000684 checksum 2e6b
Welcome to elfboot, the open sourced starter.
January 2002, Eric Biederman.
Version 1.2
POST: 0xf8
37:init_bytes() - zkernel_start:0xfffc0000 zkernel_mask:0x0000007f
Found ELF candiate at offset 0
header_offset is 0
Try to load at offset 0x0
malloc Enter, size 32, free_mem_ptr 000114d4
malloc 0x000114d4
New segment addr 0x100000 size 0x22300 offset 0xa0 filesize 0x8368
(cleaned up) New segment addr 0x100000 size 0x22300 offset 0xa0
filesize 0x8368
lb: [0x0000000000004000, 0x000000000005100c)
malloc Enter, size 32, free_mem_ptr 000114f4
malloc 0x000114f4
New segment addr 0x122300 size 0x48 offset 0x8420 filesize 0x48
(cleaned up) New segment addr 0x122300 size 0x48 offset 0x8420 filesize
0x48
lb: [0x0000000000004000, 0x000000000005100c)
Dropping non PT_LOAD segment
Loading Segment: addr: 0x0000000000100000 memsz: 0x0000000000022300
filesz: 0x0000000000008368
[ 0x0000000000100000, 0000000000108368, 0x0000000000122300) <-
00000000000000a0
Clearing Segment: addr: 0x0000000000108368 memsz: 0x0000000000019f98
Loading Segment: addr: 0x0000000000122300 memsz: 0x0000000000000048
filesz: 0x0000000000000048
[ 0x0000000000122300, 0000000000122348, 0x0000000000122348) <-
0000000000008420
Loaded segments
verified segments
closed down stream
Jumping to boot code at 0x104e24
POST: 0xfe
entry = 0x00104e24
lb_start = 0x00004000
lb_size = 0x0004d00c
adjust = 0x07faeff4
buffer = 0x07f65fe8
elf_boot_notes = 0x0000ae80
adjusted_boot_notes = 0x07fb9e74
