Hi All,
Does Tianocore payload supports Variable services for storing variables in
SPI Flash
The default has
*In CorebootPayloadPkgIa32X64.dsc *
* MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf*
Ideally it should have below drivers for Variable services to work
CorebootPayloadPkg/PchSpi/RuntimeDxe/PchSpiRuntime.inf
CorebootPayloadPkg/FvbRuntimeDxe/FvbRuntimeDxe.inf {
<LibraryClasses>
FlashDeviceLib|CorebootPayloadPkg/Library/FlashDeviceLib/FlashDeviceLib.inf
NULL|CorebootPayloadPkg/Library/SpiFlashChipLib/SpiFlashChipWINBOND/SpiFlashChipWINBOND.inf
NULL|CorebootPayloadPkg/Library/SpiFlashChipLib/SpiFlashChipNUMONYX/SpiFlashChipNUMONYX.inf
}
!endif
MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
Can any one comment on this for newer platforms like Skylake and KabyLake
Regards
Ranga
Applicable to:
SP5100 AMD C32/G34 systems such as the KCMA-D8 and KGPE-D16.
Situation: If you don't have OpenBMC installed you need to run
pwmconfig/fancontrol to manage fan speeds.
Problem:
Normally the hwmon paths will change almost every boot resulting in the
need to run pwmconfig repeatedly or fix them manually in /etc/fancontrol
- this was driving me nuts so I searched for and found a solution.
Solution:
Create a .conf file in /etc/modprobe.d/ to set sensor module load order
with these contents then reboot and fix the hwmon paths in your
/etc/fancontrol, reboot again and all should be well :D
softdep fam15h_power pre: k10temp
softdep k10temp pre: jc42
softdep jc42 pre: w83795g
softdep w83795g pre: radeon
In Debians non-free repo there is already a newer version of Intels
microcode, patching spectre ng attacks.
why is it not up-to-date in the coreboot blob folder?
kinky greetings
I've uploaded a patch to gerrit, but the build was unstable.
This caused by another patch in gerrit, without any relation to my patch.
This issue in now solved in gerrit, so my patch should build without any problems now.
What is the best/easiest way to trigger gerrit to rebuild ?
Hi,
My platform is Intel Denverton with Coreboot 4.8.1 and SSC(Spread Spectrum Clocking) setting is default enabled by FSP even I set it disabled in soft strap pin. Is there any way that I can change it back in Coreboot or how to send command through HECI to configure it? The “Intelmetool” seems only can read.
Thanks.
-Hilbert
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When you have a series of patches uploaded to Gerrit, there is an
implied dependency between them, and most tools respect that (i.e.
when Jenkins build tests them, it tests the current patch together
with all its ancestors). However, I can still submit any patch from
the middle of a patch train and it will cherry-pick just that one,
meaning that the state the tree ends up in will be different than the
one Jenkins tested (which can lead to breakages like I caused
accidentally with https://review.coreboot.org/29299).
Can we please configure Gerrit so that it just doesn't allow you to
submit patches with unsubmitted dependencies? I'm pretty sure the
Chromium Gerrit enforces that, so I assume there is an option
somewhere. It's just unsafe and pretty much never the right thing (if
you wanted to submit patches in a different order than they were
uploaded, you can just reupload them instead).
Hello everyone,
9elements is going to build up an Open Source Firmware Assembly at the
Chaos Communication Congress in Leipzig from 27th to 30th Dec. 2018 [1]
We reserved some tables as done in the last years.
You can get in touch with solutions like coreboot, Linuxboot, Tianocore
and U-Root.
We will bring some equipment so that you will be able to flash your own
devices to get rid of your BIOS.
So feel free to visit our assembly in the Chaos-West hall [2] at 35C3.
[1]:
https://events.ccc.de/2018/09/11/35c3-call-for-participation-and-submission…
[2]: https://chaos-west.de/wiki/index.php?title=35C3
Kind Regards,
Patrick
My issue is that my dual slot graphics card obstructs one of the PCI-e
slots as it is too long to place in the first slot without colliding
with one of the RAM slot retention tabs and I was wondering if there is
a way to easily and without damaging anything remove the RAM lever tab
and thus make it possible to fit the card in the first slot.
I do not need RAM in those slots as I only have one CPU but at the same
time I don't want to damage them.