coreboot December 2018

coreboot@coreboot.org

52 participants
62 discussions

Variable services in Tianocore payload
by galla rao 14 Dec '18

14 Dec '18

Hi All, Does Tianocore payload supports Variable services for storing variables in SPI Flash The default has *In CorebootPayloadPkgIa32X64.dsc * * MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf* Ideally it should have below drivers for Variable services to work CorebootPayloadPkg/PchSpi/RuntimeDxe/PchSpiRuntime.inf CorebootPayloadPkg/FvbRuntimeDxe/FvbRuntimeDxe.inf { <LibraryClasses> FlashDeviceLib|CorebootPayloadPkg/Library/FlashDeviceLib/FlashDeviceLib.inf NULL|CorebootPayloadPkg/Library/SpiFlashChipLib/SpiFlashChipWINBOND/SpiFlashChipWINBOND.inf NULL|CorebootPayloadPkg/Library/SpiFlashChipLib/SpiFlashChipNUMONYX/SpiFlashChipNUMONYX.inf } !endif MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf Can any one comment on this for newer platforms like Skylake and KabyLake Regards Ranga

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KGPE-D16/KCMA-D8 Tip: Force sensor module load order to avoid the improper changing of hwmon paths which breaks fancontrol
by Taiidan＠gmx.com 14 Dec '18

14 Dec '18

Applicable to: SP5100 AMD C32/G34 systems such as the KCMA-D8 and KGPE-D16. Situation: If you don't have OpenBMC installed you need to run pwmconfig/fancontrol to manage fan speeds. Problem: Normally the hwmon paths will change almost every boot resulting in the need to run pwmconfig repeatedly or fix them manually in /etc/fancontrol - this was driving me nuts so I searched for and found a solution. Solution: Create a .conf file in /etc/modprobe.d/ to set sensor module load order with these contents then reboot and fix the hwmon paths in your /etc/fancontrol, reboot again and all should be well :D softdep fam15h_power pre: k10temp softdep k10temp pre: jc42 softdep jc42 pre: w83795g softdep w83795g pre: radeon

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Update Intel microcode
by kinky_nekoboi 13 Dec '18

13 Dec '18

In Debians non-free repo there is already a newer version of Intels microcode, patching spectre ng attacks. why is it not up-to-date in the coreboot blob folder? kinky greetings

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Retrigger gerrit to build
by Frans Hendriks 13 Dec '18

13 Dec '18

I've uploaded a patch to gerrit, but the build was unstable. This caused by another patch in gerrit, without any relation to my patch. This issue in now solved in gerrit, so my patch should build without any problems now. What is the best/easiest way to trigger gerrit to rebuild ?

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SSC setting in FSP
by Hilbert Tu(杜睿哲_Pegatron) 12 Dec '18

12 Dec '18

Hi, My platform is Intel Denverton with Coreboot 4.8.1 and SSC(Spread Spectrum Clocking) setting is default enabled by FSP even I set it disabled in soft strap pin. Is there any way that I can change it back in Coreboot or how to send command through HECI to configure it? The “Intelmetool” seems only can read. Thanks. -Hilbert This e-mail and its attachment may contain information that is confidential or privileged, and are solely for the use of the individual to whom this e-mail is addressed. If you are not the intended recipient or have received it accidentally, please immediately notify the sender by reply e-mail and destroy all copies of this email and its attachment. Please be advised that any unauthorized use, disclosure, distribution or copying of this email or its attachment is strictly prohibited. 本電子郵件及其附件可能含有機密或依法受特殊管制之資訊，僅供本電子郵件之受文者使用。台端如非本電子郵件之受文者或誤收本電子郵件，請立即回覆郵件通知寄件人，並銷毀本電子郵件之所有複本及附件。任何未經授權而使用、揭露、散佈或複製本電子郵件或其附件之行為，皆嚴格禁止。

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Prevent out-of-order submissions on Gerrit
by Julius Werner 12 Dec '18

12 Dec '18

When you have a series of patches uploaded to Gerrit, there is an implied dependency between them, and most tools respect that (i.e. when Jenkins build tests them, it tests the current patch together with all its ancestors). However, I can still submit any patch from the middle of a patch train and it will cherry-pick just that one, meaning that the state the tree ends up in will be different than the one Jenkins tested (which can lead to breakages like I caused accidentally with https://review.coreboot.org/29299). Can we please configure Gerrit so that it just doesn't allow you to submit patches with unsubmitted dependencies? I'm pretty sure the Chromium Gerrit enforces that, so I assume there is an option somewhere. It's just unsafe and pretty much never the right thing (if you wanted to submit patches in a different order than they were uploaded, you can just reupload them instead).

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Open Source Firmware Assembly @ Chaos Communication Congress (35C3) in Leipzig, Germany
by Patrick Rudolph 12 Dec '18

12 Dec '18

Hello everyone, 9elements is going to build up an Open Source Firmware Assembly at the Chaos Communication Congress in Leipzig from 27th to 30th Dec. 2018 [1] We reserved some tables as done in the last years. You can get in touch with solutions like coreboot, Linuxboot, Tianocore and U-Root. We will bring some equipment so that you will be able to flash your own devices to get rid of your BIOS. So feel free to visit our assembly in the Chaos-West hall [2] at 35C3. [1]: https://events.ccc.de/2018/09/11/35c3-call-for-participation-and-submission… [2]: https://chaos-west.de/wiki/index.php?title=35C3 Kind Regards, Patrick

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(no subject)
by claudio T 11 Dec '18

11 Dec '18

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The problem of coreboot porting to fu540
by 王翔 10 Dec '18

10 Dec '18

I use bbl as the coreboot's payload, bbl can start and running into the enter_supervisor_mode function, but can't continue. I added some code to print register state before mret and print memory on target address. I debugged it for a long time and didn't know where the problem was. hoping to get your help. Below is my output: ``` mhartid : 2 mstatus : 8000000a00006800 mie : 0000000000000008 mtvec : 0000000080080004 mscratch : 000000008008cec0 mepc : 0000000080280000 mcause : 0000000000000002 mip : 0000000000000200 sstatus : 8000000200006000 sie : 0000000000000000 stvec : 0000000080280100 sscratch : 0000000000000000 sepc : ffffffe000927ff8 scause : 8000000000000005 sip : 0000000000000200 satp : 0000000000000000 mhartid : 1 mstatus : 8000000a00006800 mie : 0000000000000008 mtvec : 0000000080080004 mscratch : 000000008008bec0 mepc : 0000000080280000 mcause : 0000000000000002 mip : 0000000000000200 sstatus : 8000000200006000 sie : 0000000000000000 stvec : 0000000080280100 sscratch : 0000000000000000 sepc : ffffffe000927ff8 scause : 8000000000000005 sip : 0000000000000200 satp : 0000000000000000 mhartid : 3 mstatus : 8000000a00006800 mie : 0000000000000008 mtvec : 0000000080080004 mscratch : 000000008008dec0 mepc : 0000000080280000 mcause : 0000000000000002 mip : 0000000000000200 sstatus : 8000000200006000 sie : 0000000000000000 stvec : 0000000080280100 sscratch : 0000000000000000 sepc : ffffffe000927ff8 scause : 8000000000000005 sip : 0000000000000200 satp : 0000000000000000 mhartid : 4 mstatus : 8000000a00006800 mie : 0000000000000008 mtvec : 0000000080080004 mscratch : 000000008008eec0 mepc : 0000000080280000 mcause : 0000000000000001 mip : 0000000000000200 sstatus : 8000000200006000 sie : 0000000000000000 stvec : ffffffe000927c74 sscratch : 0000000000000000 sepc : 0000000080282240 scause : 0000000000000003 sip : 0000000000000200 satp : 0000000000000000 0000000080280000: 73 10 40 10 97 31 d3 00 0000000080280008: 93 81 c1 8d 99 62 73 b0 0000000080280010: 02 10 93 86 01 16 05 46 0000000080280018: af a6 c6 00 d9 ee 2a 84 0000000080280020: ae 84 17 01 d0 00 13 01 0000000080280028: e1 fd ef 20 00 1f ef 00 0000000080280030: 80 02 17 62 d0 00 13 02 0000000080280038: e2 a8 23 24 82 02 17 e1 0000000080280040: cf 00 13 01 21 fc 09 65 0000000080280048: 2a 91 22 85 a6 85 ef 20 0000000080280050: 80 27 6f 00 40 68 9b 05 0000000080280058: f0 ff 93 95 55 02 17 05 0000000080280060: 00 00 13 05 25 fa 89 8d 0000000080280068: ae 90 17 05 00 00 13 05 0000000080280070: 65 03 2e 95 73 10 55 10 0000000080280078: 17 56 db 00 13 06 86 f8 ``` ------------------ 王翔安全研究员广州市腾御安信息科技有限公司广州市天河区珠江新城华穗路406号保利克洛维二期中景A座1020-1024

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Removing a RAM slot retention lever on my KGPE-D16
by Taiidan＠gmx.com 10 Dec '18

10 Dec '18

My issue is that my dual slot graphics card obstructs one of the PCI-e slots as it is too long to place in the first slot without colliding with one of the RAM slot retention tabs and I was wondering if there is a way to easily and without damaging anything remove the RAM lever tab and thus make it possible to fit the card in the first slot. I do not need RAM in those slots as I only have one CPU but at the same time I don't want to damage them.

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coreboot December 2018