coreboot May 2014

coreboot@coreboot.org

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89 discussions

Re: [coreboot] Compling error in ubuntu 14.04
by Furquan Shaikh 08 May '14

08 May '14

Hello Wang Fei, This CL has been submitted which fixes the issue: http://review.coreboot.org/#/c/5701/ Thanks, Furquan On Thu, May 8, 2014 at 4:36 PM, WANG FEI <wangfei.jimei(a)gmail.com> wrote: > Hi, all > > I noticed coreboot compiles failed on my ubuntu 14.04 since the following > change committed. > > > > > *Author: Furquan Shaikh <furquan(a)google.com <furquan(a)google.com>> > 2014-04-23 18:18:48 Committer: Furquan Shaikh <furquan(a)google.com > <furquan(a)google.com>> 2014-05-06 19:23:31Parent: > fb494d68ff92d036adf10fb7eacf97ed9f1a4391 (baytrail: gpio: Add support for > direct / dedicated IRQs) Child: 9547f8d799829ddab9196c4e0cad644a06db49e9 > (rambi: Add DIRQs for trackpad and touchscreen)* > > The compiling log as below, > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > *ubuntu@ubuntu:~/work/coreboot$ make /bin/sh: 1: Syntax error: redirection > unexpected/bin/sh: 1: -print-libgcc-file-name: not found/bin/sh: 1: > -print-libgcc-file-name: not found/bin/sh: 1: Syntax error: redirection > unexpected/bin/sh: 1: -print-libgcc-file-name: not found /bin/sh: 1: > -print-libgcc-file-name: not found/bin/sh: 1: Syntax error: redirection > unexpected/bin/sh: 1: -print-libgcc-file-name: not found/bin/sh: 1: > -print-libgcc-file-name: not foundwarning: (BOARD_SPECIFIC_OPTIONS && > NORTHBRIDGE_INTEL_NEHALEM && SOUTHBRIDGE_VIA_K8M890_VGA_EN && > DRIVERS_EMULATION_QEMU_BOCHS) selects VGA which has unmet direct > dependencies (VENDOR_INTEL && BOARD_INTEL_COUGAR_CANYON2) ## configuration > written to .config#warning: (BOARD_SPECIFIC_OPTIONS && > NORTHBRIDGE_INTEL_NEHALEM && SOUTHBRIDGE_VIA_K8M890_VGA_EN && > DRIVERS_EMULATION_QEMU_BOCHS) selects VGA which has unmet direct > dependencies (VENDOR_INTEL && BOARD_INTEL_COUGAR_CANYON2) warning: > (BOARD_SPECIFIC_OPTIONS && NORTHBRIDGE_INTEL_NEHALEM && > SOUTHBRIDGE_VIA_K8M890_VGA_EN && DRIVERS_EMULATION_QEMU_BOCHS) selects VGA > which has unmet direct dependencies (VENDOR_INTEL && > BOARD_INTEL_COUGAR_CANYON2) HOSTCC nvramtool/cli/nvramtool.o > HOSTCC nvramtool/cli/opts.o HOSTCC nvramtool/cmos_lowlevel.o > HOSTCC nvramtool/cmos_ops.o HOSTCC nvramtool/common.o > HOSTCC nvramtool/compute_ip_checksum.o HOSTCC > nvramtool/hexdump.o HOSTCC nvramtool/input_file.o HOSTCC > nvramtool/layout.o HOSTCC nvramtool/accessors/layout-common.o > HOSTCC nvramtool/accessors/layout-text.o HOSTCC > nvramtool/accessors/layout-bin.o HOSTCC nvramtool/lbtable.o > HOSTCC nvramtool/reg_expr.o HOSTCC nvramtool/cbfs.o > HOSTCC nvramtool/accessors/cmos-mem.o HOSTCC nvramtool/nvramtool > (link) OPTION option_table.h GEN build.h CC > romstage.incmake: MMD: Command not found POST romstage.incsed: > can't read build/mainboard/emulation/qemu-i440fx/romstage.pre.inc: No such > file or directory make: *** > [build/mainboard/emulation/qemu-i440fx/romstage.inc] Error 2* > > It looks the bash on my system does not compatible with the new committed > makefile, does anyone get the same failure? How to solve it? > > The bash I'm using is, > > > > > > > > > > *ubuntu@ubuntu:~/work/coreboot$ /bin/bash --versionGNU bash, version > 4.3.11(1)-release (i686-pc-linux-gnu)Copyright (C) 2013 Free Software > Foundation, Inc.License GPLv3+: GNU GPL version 3 or later > <http://gnu.org/licenses/gpl.html <http://gnu.org/licenses/gpl.html>> This > is free software; you are free to change and redistribute it.There is NO > WARRANTY, to the extent permitted by law.* > > *-Fei * > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot >

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Compling error in ubuntu 14.04
by WANG FEI 08 May '14

08 May '14

Hi, all I noticed coreboot compiles failed on my ubuntu 14.04 since the following change committed. *Author: Furquan Shaikh <furquan(a)google.com <furquan(a)google.com>> 2014-04-23 18:18:48 Committer: Furquan Shaikh <furquan(a)google.com <furquan(a)google.com>> 2014-05-06 19:23:31Parent: fb494d68ff92d036adf10fb7eacf97ed9f1a4391 (baytrail: gpio: Add support for direct / dedicated IRQs) Child: 9547f8d799829ddab9196c4e0cad644a06db49e9 (rambi: Add DIRQs for trackpad and touchscreen)* The compiling log as below, *ubuntu@ubuntu:~/work/coreboot$ make /bin/sh: 1: Syntax error: redirection unexpected/bin/sh: 1: -print-libgcc-file-name: not found/bin/sh: 1: -print-libgcc-file-name: not found/bin/sh: 1: Syntax error: redirection unexpected/bin/sh: 1: -print-libgcc-file-name: not found /bin/sh: 1: -print-libgcc-file-name: not found/bin/sh: 1: Syntax error: redirection unexpected/bin/sh: 1: -print-libgcc-file-name: not found/bin/sh: 1: -print-libgcc-file-name: not foundwarning: (BOARD_SPECIFIC_OPTIONS && NORTHBRIDGE_INTEL_NEHALEM && SOUTHBRIDGE_VIA_K8M890_VGA_EN && DRIVERS_EMULATION_QEMU_BOCHS) selects VGA which has unmet direct dependencies (VENDOR_INTEL && BOARD_INTEL_COUGAR_CANYON2) ## configuration written to .config#warning: (BOARD_SPECIFIC_OPTIONS && NORTHBRIDGE_INTEL_NEHALEM && SOUTHBRIDGE_VIA_K8M890_VGA_EN && DRIVERS_EMULATION_QEMU_BOCHS) selects VGA which has unmet direct dependencies (VENDOR_INTEL && BOARD_INTEL_COUGAR_CANYON2) warning: (BOARD_SPECIFIC_OPTIONS && NORTHBRIDGE_INTEL_NEHALEM && SOUTHBRIDGE_VIA_K8M890_VGA_EN && DRIVERS_EMULATION_QEMU_BOCHS) selects VGA which has unmet direct dependencies (VENDOR_INTEL && BOARD_INTEL_COUGAR_CANYON2) HOSTCC nvramtool/cli/nvramtool.o HOSTCC nvramtool/cli/opts.o HOSTCC nvramtool/cmos_lowlevel.o HOSTCC nvramtool/cmos_ops.o HOSTCC nvramtool/common.o HOSTCC nvramtool/compute_ip_checksum.o HOSTCC nvramtool/hexdump.o HOSTCC nvramtool/input_file.o HOSTCC nvramtool/layout.o HOSTCC nvramtool/accessors/layout-common.o HOSTCC nvramtool/accessors/layout-text.o HOSTCC nvramtool/accessors/layout-bin.o HOSTCC nvramtool/lbtable.o HOSTCC nvramtool/reg_expr.o HOSTCC nvramtool/cbfs.o HOSTCC nvramtool/accessors/cmos-mem.o HOSTCC nvramtool/nvramtool (link) OPTION option_table.h GEN build.h CC romstage.incmake: MMD: Command not found POST romstage.incsed: can't read build/mainboard/emulation/qemu-i440fx/romstage.pre.inc: No such file or directory make: *** [build/mainboard/emulation/qemu-i440fx/romstage.inc] Error 2* It looks the bash on my system does not compatible with the new committed makefile, does anyone get the same failure? How to solve it? The bash I'm using is, *ubuntu@ubuntu:~/work/coreboot$ /bin/bash --versionGNU bash, version 4.3.11(1)-release (i686-pc-linux-gnu)Copyright (C) 2013 Free Software Foundation, Inc.License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html <http://gnu.org/licenses/gpl.html>> This is free software; you are free to change and redistribute it.There is NO WARRANTY, to the extent permitted by law.* *-Fei*

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The Novena Open Laptop + Coreboot?
by devel＠roosoft.ltd.uk 08 May '14

08 May '14

Hey all, Now that Novena Laptop has finally been crowd funded above and beyond it's target, does anyone know if any of their team has approached coreboot to make sure it is a open laptop from the moment you turn it on. It would be so nice to have a real free as in libre laptop. Their page: http://www.crowdsupply.com/kosagi/novena-open-laptop -- == D Alexander Dogsbody RooSoft Ltd

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Latest coreboot compiling failure on ubuntu 14.04
by WANG FEI 08 May '14

08 May '14

Hi, all I noticed coreboot compiles failed on my system since the following change committed. *Author: Furquan Shaikh <furquan(a)google.com <furquan(a)google.com>> 2014-04-23 18:18:48Committer: Furquan Shaikh <furquan(a)google.com <furquan(a)google.com>> 2014-05-06 19:23:31Parent: fb494d68ff92d036adf10fb7eacf97ed9f1a4391 (baytrail: gpio: Add support for direct / dedicated IRQs)Child: 9547f8d799829ddab9196c4e0cad644a06db49e9 (rambi: Add DIRQs for trackpad and touchscreen)* The compiling log as below, *ubuntu@ubuntu:~/work/coreboot$ make/bin/sh: 1: Syntax error: redirection unexpected/bin/sh: 1: -print-libgcc-file-name: not found/bin/sh: 1: -print-libgcc-file-name: not found/bin/sh: 1: Syntax error: redirection unexpected/bin/sh: 1: -print-libgcc-file-name: not found/bin/sh: 1: -print-libgcc-file-name: not found/bin/sh: 1: Syntax error: redirection unexpected/bin/sh: 1: -print-libgcc-file-name: not found/bin/sh: 1: -print-libgcc-file-name: not foundwarning: (BOARD_SPECIFIC_OPTIONS && NORTHBRIDGE_INTEL_NEHALEM && SOUTHBRIDGE_VIA_K8M890_VGA_EN && DRIVERS_EMULATION_QEMU_BOCHS) selects VGA which has unmet direct dependencies (VENDOR_INTEL && BOARD_INTEL_COUGAR_CANYON2)## configuration written to .config#warning: (BOARD_SPECIFIC_OPTIONS && NORTHBRIDGE_INTEL_NEHALEM && SOUTHBRIDGE_VIA_K8M890_VGA_EN && DRIVERS_EMULATION_QEMU_BOCHS) selects VGA which has unmet direct dependencies (VENDOR_INTEL && BOARD_INTEL_COUGAR_CANYON2)warning: (BOARD_SPECIFIC_OPTIONS && NORTHBRIDGE_INTEL_NEHALEM && SOUTHBRIDGE_VIA_K8M890_VGA_EN && DRIVERS_EMULATION_QEMU_BOCHS) selects VGA which has unmet direct dependencies (VENDOR_INTEL && BOARD_INTEL_COUGAR_CANYON2) HOSTCC nvramtool/cli/nvramtool.o HOSTCC nvramtool/cli/opts.o HOSTCC nvramtool/cmos_lowlevel.o HOSTCC nvramtool/cmos_ops.o HOSTCC nvramtool/common.o HOSTCC nvramtool/compute_ip_checksum.o HOSTCC nvramtool/hexdump.o HOSTCC nvramtool/input_file.o HOSTCC nvramtool/layout.o HOSTCC nvramtool/accessors/layout-common.o HOSTCC nvramtool/accessors/layout-text.o HOSTCC nvramtool/accessors/layout-bin.o HOSTCC nvramtool/lbtable.o HOSTCC nvramtool/reg_expr.o HOSTCC nvramtool/cbfs.o HOSTCC nvramtool/accessors/cmos-mem.o HOSTCC nvramtool/nvramtool (link) OPTION option_table.h GEN build.h CC romstage.incmake: MMD: Command not found POST romstage.incsed: can't read build/mainboard/emulation/qemu-i440fx/romstage.pre.inc: No such file or directorymake: *** [build/mainboard/emulation/qemu-i440fx/romstage.inc] Error 2* It looks the bash on my system does not compatible with the new committed makefile, does anyone get the failure? The bash I'm using is, *ubuntu@ubuntu:~/work/coreboot$ /bin/bash --versionGNU bash, version 4.3.11(1)-release (i686-pc-linux-gnu)Copyright (C) 2013 Free Software Foundation, Inc.License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html <http://gnu.org/licenses/gpl.html>>This is free software; you are free to change and redistribute it.There is NO WARRANTY, to the extent permitted by law.* -Fei

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eventlong & backtrace support
by Rudolf Marek 08 May '14

08 May '14

Hi all, I'm still suffering with following errors ONLY when using 4 core Trinity CPU on the F2A85-M: EventLog: EventClass = 2, EventInfo = 8040100. Param1 = a00a, Param2 = 0. Param3 = 0, Param4 = 0. EventLog: EventClass = 2, EventInfo = 8040100. Param1 = a00a, Param2 = 0. Param3 = 0, Param4 = 0. ... EventLog: EventClass = 2, EventInfo = 8040100. Param1 = a00a, Param2 = 0. Param3 = 0, Param4 = 0. EventLog: EventClass = 2, EventInfo = 8040100. Param1 = a00a, Param2 = 0. Param3 = 0, Param4 = 0. agesawrapper_amdinitpost failed: 4 Got past agesawrapper_amdinitpost There is about 10? of them. System seems to boot fine. I still dont know what those are but I decided to attack the problem via a backtrace. I implemented a simple backtracer which I placed in the AGESA PutEventLog() function. Once the function is visited I print: agesawrapper_amdinitreset Fch OEM config in INIT RESET Done EVENT BACKTRACE: 0xff82cfa7 0xff82f333 0xff82f377 0xff834e5a 0xff8349b2 0xff838bf3 0xff83663d 0xff837495 0xff861999 0xff8346f1 0xff82d661 0xff81db3c 0xff81a355 EVENT BACKTRACE: ... Then with simple(stupid) script: cat - | while read line ; do unset A if echo $line | grep ^0x > /dev/null ; then A=`addr2line -e build/cbfs/fallback/romstage_xip.elf "$line" | tr -d "\n"` fi echo $line $A done It turns to: agesawrapper_amdinitreset Fch OEM config in INIT RESET Done EVENT BACKTRACE: 0xff82cfa7 /home/ruik/coreboot/src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c:662 0xff82f333 /home/ruik/coreboot/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3SaveState.c:217 0xff82f377 /home/ruik/coreboot/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3SaveState.c:256 0xff834e5a /home/ruik/coreboot/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c:96 0xff8349b2 /home/ruik/coreboot/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.c:161 0xff838bf3 /home/ruik/coreboot/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c:1241 0xff83663d /home/ruik/coreboot/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxLibTN.c:330 0xff837495 /home/ruik/coreboot/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbEarlyInitTN.c:840 0xff861999 /home/ruik/coreboot/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbLibFeatures.c:99 0xff8346f1 /home/ruik/coreboot/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtEarly.c:122 0xff82d661 /home/ruik/coreboot/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitEarly.c:270 0xff81db3c /home/ruik/coreboot/src/mainboard/asus/f2a85-m/agesawrapper.c:234 0xff81a355 /home/ruik/coreboot/src/mainboard/asus/f2a85-m/romstage.c:135 EVENT BACKTRACE: It makes me wonder why we dont have such backtrace function available? Or did I miss something? Anyway I'm attaching a diff how this was hacked in. I wont have time for this for couple of days. It could be handy for someone else, or even better make it a real feature :) Thanks Rudolf

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Re: [coreboot] New addendums to INTEL FSP family (ron minnich)
by Jiming Sun 07 May '14

07 May '14

Hi, Ron, I am hesitant to respond because I am afraid that this is a philosophical discussion that will stir a lot of strong opinions and debates. :-) If open source community is meant for collaboration and innovation, do you think there can be silicon specific code that only a few people can understand, therefore whether it is open or not really does not matter? Besides, if the code is meant to be part of SOC someday, does it matter whether or not it is completely open? For example, ARM has a Boot ROM inside their SOC, should the code inside the Boot ROM be open? or does it matter? I think it is a balancing act that every silicon vendor needs to decide on. Some are more careful than the others. I know some hard-core open source advocates would like to see every software open including microcode, but from practicality perspective, if the code cannot be modified by the community without causing adverse effects, then it is not something that needs to be "collaborated" on; thus open or not really does not matter. I think you and some Google people have provided this view in this forum sometimes in the past, Ron. I know this view point is not going to be popular, but Intel is trying hard to open as much code as possible (tianocore.org, Linux drivers, and Quark firmware are a few examples; I am sure more will come in the future). This conversation is meant for dialog, and it is my own opinions. Just a disclaimer: this is not Intel's official position, and I don't speak for Intel. :-) After that being said, any comments about Intel's FSP are still welcome. We believe encapsulating basic silicon code is a good idea regardless if it is completely open. Thanks, Jiming On Mon, May 5, 2014 at 8:51 AM, ron minnich <rminnich(a)gmail.com> wrote: > Jiming, why doesn't intel just put that more open stuff up on github > and be done with it? > > ron > -- Blessings, Jiming Sun

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Re: [coreboot] PIC instead of APIC mode for KolibriOS - mouse fix
by Scott Duplichan 07 May '14

07 May '14

ron minnich [mailto:rminnich@gmail.com] wrote: ]So, how would these changes affect other payloads? ] ]ron The patch adds programming and one reporting mechanism for PIC mode PCI interrupt routing for the ASRock E350M1 board only. Without the patch, PIC mode PCI interrupt routing is not programmed and not reported. There are several ways an OS can find PIC mode interrupt routing for PCI devices: 1) $PIR table 2) ACPI 3) PCI config space interrupt line registers This change adds reporting method 3. Reporting methods 1 and 2 are incomplete or unimplemented for this board. This patch programs PIC mode PCI interrupt routing to match the OEM BIOS. Without the patch, PIC mode PCI interrupt routing is unprogrammed. The changes affect an OS or other code that uses PCI interrupts in PIC mode. APIC mode is unaffected. >From what I can remember, older mainstream operating systems normally use the ACPI method to find PIC mode interrupt routing. They might fall back to $PIR or even the config space line register method I suppose. I see some coreboot boards support the ACPI method of reporting (and modifying) PIC mode PCI interrupts. However I don't see this this code in E350M1 project. As a result, an OS such as Windows 2000 may or may not see improvement with this patch. I didn't try it. Linux still supports PIC mode PCI interrupt routing through grub options. I did not test that either. It seems interest in PIC mode interrupts has waned since multicore processors have become popular. A limitation of PIC mode interrupts is that all PCI interrupts are handled by the BSP core and cannot be routed to AP cores. I know of one application that uses PIC mode PCI interrupts and finds them from the config space line register. It is the interrupt test portion of the Broadcom b57diag utility. For operating systems, Windows dropped PIC mode starting with XP x64 edition if I remember correctly. XP 32-bit defaults to APIC mode, but can be switched to PIC mode during installation. After XP, all PIC mode is gone. For linux, PIC mode is still supported, but the default was switched to APIC mode several years ago. I believe there was a time with 32-bit Linux used PIC mode but 64-bit used APIC mode. This is from memory so I could be a little off. Thanks, Scott

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Re: [coreboot] coreboot Digest, Vol 111, Issue 6
by Mark C. Mason 07 May '14

07 May '14

I'm planning to build this for an ASROCK IMB-180 this week or next. I previously had trouble booting until Wim Vervoon <wvervoorn(a)eltan.com> suggested that it might be dual-ranked dimms. Replacing the dual-rank dimm with a single rank did the trick. I'll test both configurations with the new code and post the results. Mark Mason Engineering Design Team > Send coreboot mailing list submissions to > coreboot(a)coreboot.org > > To subscribe or unsubscribe via the World Wide Web, visit > http://www.coreboot.org/mailman/listinfo/coreboot > or, via email, send a message with subject or body 'help' to > coreboot-request(a)coreboot.org > > You can reach the person managing the list at > coreboot-owner(a)coreboot.org > > When replying, please edit your Subject line so it is more specific > than "Re: Contents of coreboot digest..." > > > Today's Topics: > > 1. Re: Flash access on ASUS F2A85 variants (Rudolf Marek) > 2. Re: Flash access on ASUS F2A85 variants (Rudolf Marek) > 3. Is there a payload to test SeaBIOS? BIOS mouse interface? > (Paul Menzel) > 4. [RFH] Please test latest cleanups on AGESA boards (Paul Menzel) > > > ---------------------------------------------------------------------- > > Message: 1 > Date: Sun, 04 May 2014 13:56:03 +0200 > From: Rudolf Marek <r.marek(a)assembler.cz> > To: coreboot(a)coreboot.org > Cc: flashrom(a)flashrom.org > Subject: Re: [coreboot] Flash access on ASUS F2A85 variants > Message-ID: <53662AD3.3030304(a)assembler.cz> > Content-Type: text/plain; charset=UTF-8; format=flowed > > Hi Stefan, > > I could not find any details but the error message one receives: >> "ERROR: State of SpiAccessMacRomEn or SpiHostAccessRomEn prohibits full >> access." > Found ITE Super I/O, ID 0x8603 on port 0x2e > Found chipset "AMD FCH" with PCI ID 1022:780e. Enabling flash write... SPI base > address is at 0xfec10000 > Hudson-2/3/4 detected. > SpiRomEnable=1, PrefetchEnSPIFromIMC=0, PrefetchEnSPIFromHost=1 > (0x6f4c2105) SpiArbEnable=1, SpiAccessMacRomEn=1, SpiHostAccessRomEn=0, > ArbWaitCount=7, SpiBridgeDisable=1, SpiBusy=0 > ERROR: State of SpiAccessMacRomEn or SpiHostAccessRomEn prohibits full access. > >> If I read the documentation of SpiHostAccessRomEn correctly then it >> should not bother us at all. It indicates it the ethernet firmware can >> access the host partition of the flash chip. If however the other bit >> (SpiAccessMacRomEn) is reset to 0 then we indeed have a problem. > Yes I tried to disable the check and got following (I was testing BIOS version 6502) > > Found Winbond flash chip "W25Q64.V" (8192 kB, SPI). > This chip may contain one-time programmable memory. flashrom cannot read > and may never be able to write it, hence it may not be able to completely > clone the contents of this chip (see man page for details). > coreboot last image size (not ROM size) is 8388608 bytes. > Manufacturer: ASUS > Mainboard ID: F2A85-M > Reading old flash chip contents... FIFO pointer corruption! Pointer is 0, wanted 3 > Something else is accessing the flash chip and causes random corruption. > Please stop all applications and drivers and IPMI which access the flash chip. > FAILED. >> Can someone please send me the verbose output of flashrom to confirm >> which one it is? And I am also looking for testers with these boards, >> because I think the abort on SpiHostAccessRomEn is a bug in flashrom. > Hm looks like something will happen, becuase it does not work. This board has > external ethernet chip. So the only master accessing the chip could be USB 3.0 > firmware. But, this works fine with coreboot and also removing the XHCI drivers > did not help. > > Maybe some protection bits are set elsewhere. > > This is dump of MMIO space: > > hexdump -C a.bin > 00000000 05 21 4c 6f 00 00 00 00 00 06 00 00 00 70 00 02 |.!Lo.........p..| > 00000010 06 20 04 04 06 04 9f 05 03 0b 0a 02 ff 88 00 3b |. .............;| > 00000020 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |................| > * > > It looks like (look to 48751 Rev 3.00 - May 30, 2013 BKDG for AMD Family 16h > Models 00h-0Fh Processors) > > SPIx1D Alt_SPI_CS 0x88 > > SpiProtectEn0. IF (SPIx1D[SpiProtectLock]==1) THEN Read-only. ELSE Read-write. > ENDIF. > > Reset: 0. 1=Enable SPI read/write protection ranges specified by > D14F3x[5C,58,54,50]. > > Funny is that the SPiProtectLock is not set to 1 > > 00:14.3 ISA bridge: Advanced Micro Devices [AMD] Hudson LPC Bridge (rev 11) > 00: 22 10 0e 78 0f 00 20 02 11 00 01 06 00 00 80 00 > 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 27 85 > 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 40: 04 00 00 00 d5 ff 03 ff 07 ff 00 00 00 00 00 00 > 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > > And all protection ranges are 0 anyway... > > 60: 00 00 00 00 30 02 00 00 00 00 0f 00 00 ff ff ff > 70: 67 45 23 00 00 00 00 00 9c 00 00 00 05 0b 00 00 > 80: 08 00 03 a8 00 00 00 00 00 00 00 00 00 00 00 00 > 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > a0: 02 00 c1 fe 2f 01 00 00 00 00 00 00 00 00 00 00 > b0: 00 00 00 00 00 00 00 00 00 00 e9 45 00 00 00 00 > c0: 00 00 00 00 00 00 00 00 00 00 00 00 17 00 82 ff > d0: 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > > And clearing the bit 4 of 1d also did not help. So it must be something else > elsewhere. > > I hope this is enough information for the start ;) > > Thanks > Rudolf > > > > > ------------------------------ > > Message: 2 > Date: Sun, 04 May 2014 21:38:58 +0200 > From: Rudolf Marek <r.marek(a)assembler.cz> > To: coreboot(a)coreboot.org > Cc: flashrom(a)flashrom.org > Subject: Re: [coreboot] Flash access on ASUS F2A85 variants > Message-ID: <53669752.8060200(a)assembler.cz> > Content-Type: text/plain; charset=ISO-8859-1; format=flowed > > Hi Stefan, > > I just tried with v6402 which is open: > > 00:14.3 ISA bridge: Advanced Micro Devices [AMD] Hudson LPC Bridge (rev 11) > 00: 22 10 0e 78 0f 00 20 02 11 00 01 06 00 00 80 00 > 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 27 85 > 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 40: 04 00 00 00 d5 ff 03 ff 07 ff 00 00 00 00 00 00 > 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 60: 00 00 00 00 30 02 00 00 00 00 0f 00 00 ff ff ff > 70: 67 45 23 00 00 00 00 00 9c 00 00 00 05 0a 00 00 > 80: 08 00 03 a8 00 00 00 00 00 00 00 00 00 00 00 00 > 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > a0: 02 00 c1 fe 2f 01 00 00 00 00 00 00 00 00 00 00 > b0: 00 00 00 00 00 00 00 00 00 00 e9 45 00 00 00 00 > c0: 00 00 00 00 00 00 00 00 00 00 00 00 17 00 82 ff > d0: 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > > ruiktest ~ # hexdump -C a.bin > 00000000 05 21 cc 6f 00 00 00 00 00 00 00 00 00 70 00 02 |.!.o.........p..| > 00000010 06 20 04 04 06 04 9f 05 03 0b 0a 02 ff 88 00 3b |. .............;| > 00000020 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |................| > > The newer (locked) version from last email: > > hexdump -C a.bin > 00000000 05 21 4c 6f 00 00 00 00 00 06 00 00 00 70 00 02 |.!Lo.........p..| > 00000010 06 20 04 04 06 04 9f 05 03 0b 0a 02 ff 88 00 3b |. .............;| > 00000020 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |................| > * > > It looks that the the SPI CMD 06 is now restricted CMD for MAC and > SPIhostaccesRomEn is clear. > > I tried to boot with open version v6402 and then just clear the > SpiHostAccessRomEn without setting any other bits and I receive failure even for > read: > > ./flashrom/flashrom -V -p internal -r bios_open.bin > > Found Winbond flash chip "W25Q64.V" (8192 kB, SPI). > This chip may contain one-time programmable memory. flashrom cannot read > and may never be able to write it, hence it may not be able to completely > clone the contents of this chip (see man page for details). > Reading flash... FIFO pointer corruption! Pointer is 0, wanted 3 > Something else is accessing the flash chip and causes random corruption. > Please stop all applications and drivers and IPMI which access the flash chip. > Read operation failed! > FAILED. > > Yes it looks like something is happening with flashrom / controller if > SpiHostAccessRomEn is cleared. > > Thanks > Rudolf > > > > ------------------------------ > > Message: 3 > Date: Mon, 05 May 2014 00:54:55 +0200 > From: Paul Menzel <paulepanter(a)users.sourceforge.net> > To: coreboot(a)coreboot.org > Subject: [coreboot] Is there a payload to test SeaBIOS? BIOS mouse > interface? > Message-ID: <1399244095.7732.188.camel@mattotaupa> > Content-Type: text/plain; charset="utf-8" > > Dear coreboot folks, > > > on the ASRock E350M1 [1] with coreboot and SeaBIOS payload, starting > KolibriOS from GRUB 2 on the hard drive, it loads fine but neither > keyboard nor mouse work. This is true for USB and PS/2 [2]. > > Do you know of a payload I can use to test SeaBIOS? BIOS mouse > interface? > > > Thanks, > > Paul > > > [1] http://www.coreboot.org/Board:asrock/e350m1 > [2] http://bugs.kolibrios.org/view.php?id=84 >

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Re: [coreboot] pcengines/apu status
by Pascal Dornier 07 May '14

07 May '14

GPL source is available on request, just ask support(a)pcengines.ch and brace for impact. Able and willing developers, inquire within. Best regards, Pascal Dornier

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#201: Error building coreboot for Samsung Exynos5 Google Snow
by coreboot 07 May '14

07 May '14

#201: Error building coreboot for Samsung Exynos5 Google Snow -------------------------------------------+------------------------------- Reporter: Pete <bluestore.logmein@…> | Owner: stepan@… Type: defect | Status: new Priority: major | Milestone: Component: coreboot | Keywords: Dependencies: | Patch Status: there is no | patch -------------------------------------------+------------------------------- Hi, I am trying to compile a coreboot rom for the Samsung chromebook Series 3 - Exynos5, i followed the instructions at http://www.coreboot.org/Exynos5 to compile the armv7a-eabi toolchain and evertyhing went ok. At the menuconfig i selected Google MainBoard, model Snow, exit and save. It starts to compile until it returns this error: GEN generated/romstage.ld LINK cbfs/fallback/romstage.debug build/ec/google/chromeec/ec.romstage.o: In function `google_chromeec_early_init': /home/suporte/coreboot/src/ec/google/chromeec/ec.c:117: undefined reference to `recovery_mode_enabled' collect2: error: ld returned 1 exit status make: *** [build/cbfs/fallback/romstage.debug] Error 1 Am i missing something? Also tried make clean and make crossgcc, and even the built went fine, when i run make always returns this error. Thank you, Pete -- Ticket URL: <https://tracker.coreboot.org/trac/coreboot/ticket/201> coreboot <http://www.coreboot.org/>

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coreboot May 2014