coreboot November 2012

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895 discussions

Re: [coreboot] ROM option compile problem
by Idwer Vollering 01 Nov '12

01 Nov '12

2012/11/1 <jeroenkrabbendam(a)fastmail.fm>: > > Thx for replying. > > I switch to this email address, trying not to pollute the mailing list. Please keep coreboot@ in the To: or CC field, others can't help you when you don't use reply-to-all. > > I think is not a hardware problem, as the error occurs on the same plae everytime. It is fully reproducable. Rebooted, heavy workload, no workload, it is > always the same. > > Then the software: Weekly updated Gentoo distro, so that could not be the problem either. Can you tell more about the hardware it runs on: 32 or 64 bit, does it happen with a debian install as well? > > Nor 'dmesg', nor any syslog file logs anything different from usual. > > The link you've sent, is about a random error, this error is absolutely not random. > > Regards, Jeroen Krabbendam > > >> That.. sounds like something is 'wrong' with your machine, either in a >> software or a hardware way (or both): ancient OS/userland, bad memory. >> Is there anything useful in dmesg output? >> http://stackoverflow.com/questions/3789089/bus-error-in-cron-job

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ROM option compile problem
by jeroenkrabbendam＠fastmail.fm 01 Nov '12

01 Nov '12

Hi, I am not very familiar with C programming, and therefore cannot repair the following problem. In the last branch of coreboot, selecting one of the 'Run (non-)VGA Option ROMs' results in an error: CC devices/dummy_chip_ops.ramstage.o CC devices/oprom/x86.ramstage.o src/devices/oprom/x86.c: In function ■interrupt_handler■: src/devices/oprom/x86.c:408:3: error: unknown field ■eax■ specified in initializer cc1: warnings being treated as errors src/devices/oprom/x86.c:408:3: error: missing braces around initializer src/devices/oprom/x86.c:408:3: error: (near initialization for ■(anonymous).<anonymous>■) src/devices/oprom/x86.c:409:3: error: unknown field ■ecx■ specified in initializer src/devices/oprom/x86.c:410:3: error: unknown field ■edx■ specified in initializer src/devices/oprom/x86.c:411:3: error: unknown field ■ebx■ specified in initializer src/devices/oprom/x86.c:412:3: error: unknown field ■esp■ specified in initializer src/devices/oprom/x86.c:413:3: error: unknown field ■ebp■ specified in initializer src/devices/oprom/x86.c:414:3: error: unknown field ■esi■ specified in initializer src/devices/oprom/x86.c:415:3: error: unknown field ■edi■ specified in initializer make: *** [build/devices/oprom/x86.ramstage.o] Error 1 Very easy to reproduce, just select one of the aforementioned options. Any ideas?? Thx, Jeroen Krabbendam

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New patch to review for coreboot: 93f0f4d add .gitreview
by David Hendricks 01 Nov '12

01 Nov '12

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1665 -gerrit commit 93f0f4d5a238b7434c06f812b1a54b43abe351ff Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Nov 1 10:46:29 2012 -0700 add .gitreview This adds a .gitreview file for use with the git-review tool. More information is available at the URL below: https://labsconsole.wikimedia.org/wiki/Git-review Change-Id: I723d78bf7dd81c5756e684d5b166210246fe2daf Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- .gitreview | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/.gitreview b/.gitreview new file mode 100644 index 0000000..20191c7 --- /dev/null +++ b/.gitreview @@ -0,0 +1,5 @@ +[gerrit] +host=review.coreboot.org +port=29418 +project=coreboot +defaultbranch=master

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Patch set updated for coreboot: 1b394ab cpu/intel/model_1067x: Add proper c-state/p-state/thermal support
by Patrick Georgi 01 Nov '12

01 Nov '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1663 -gerrit commit 1b394ab14021ec0ac20db1319bbd67887734d47c Author: Nico Huber <nico.huber(a)secunet.com> Date: Tue Oct 2 11:46:11 2012 +0200 cpu/intel/model_1067x: Add proper c-state/p-state/thermal support Change-Id: I853454e8f5617fb7af5dddd7288bdeeacc7b1b8e Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- src/cpu/intel/model_1067x/chip.h | 24 +++ src/cpu/intel/model_1067x/model_1067x_init.c | 232 +++++++++++++++++++++++---- src/cpu/intel/speedstep/Makefile.inc | 1 + 3 files changed, 226 insertions(+), 31 deletions(-) diff --git a/src/cpu/intel/model_1067x/chip.h b/src/cpu/intel/model_1067x/chip.h new file mode 100644 index 0000000..1731c50 --- /dev/null +++ b/src/cpu/intel/model_1067x/chip.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +struct cpu_intel_model_1067x_config { + int c5 : 1; + int c6 : 1; + int slfm : 1; +}; diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index c6d716d9..2b7839b 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007-2009 coresystems GmbH + * 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -33,6 +34,8 @@ #include <cpu/x86/cache.h> #include <cpu/x86/name.h> +#include "chip.h" + static const uint32_t microcode_updates[] = { #include "microcode-2618-m441067AA07.h" #include "microcode-2626-m1010677705.h" @@ -98,20 +101,45 @@ static void enable_vmx(void) #define PMG_CST_CONFIG_CONTROL 0xe2 #define PMG_IO_BASE_ADDR 0xe3 #define PMG_IO_CAPTURE_ADDR 0xe4 +#define MSR_BBL_CR_CTL3 0x11e +#define MSR_FSB_FREQ 0xcd -#define CST_RANGE 2 -static void configure_c_states(void) +static void configure_c_states(const int quad) { msr_t msr; - msr = rdmsr(PMG_CST_CONFIG_CONTROL); + /* Find pointer to CPU configuration. */ + const device_t lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); + const struct cpu_intel_model_1067x_config *const conf = + (lapic && lapic->chip_info) ? lapic->chip_info : NULL; - msr.lo |= (1 << 15); // config lock until next reset - msr.lo |= (1 << 14); // Deeper Sleep - msr.lo |= (1 << 10); // Enable IO MWAIT redirection - msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk - msr.lo |= (1 << 3); // Dynamic L2 + /* Is C5 requested and supported? */ + const int c5 = conf && conf->c5 && + (rdmsr(MSR_BBL_CR_CTL3).lo & (3 << 30)) && + !(rdmsr(MSR_FSB_FREQ).lo & (1 << 31)); + /* Is C6 requested and supported? */ + const int c6 = conf && conf->c6 && + ((cpuid_edx(5) >> (6 * 4)) & 0xf) && c5; + const int cst_range = (c6 ? 6 : (c5 ? 5 : 4)) - 2; /* zero means lvl2 */ + + msr = rdmsr(PMG_CST_CONFIG_CONTROL); + msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk + msr.lo |= (1 << 8); + if (quad) { + msr.lo = (msr.lo & ~(7 << 0)) | (4 << 0); + } + if (c5) { + msr.lo &= ~(1 << 13); + msr.lo &= ~(7 << 0); + msr.lo |= (1 << 3); /* Enable dynamic L2. */ + msr.lo |= (1 << 14); /* Enable deeper sleep */ + } + /* Next two fields seem to be mutually exclusive: */ + msr.lo &= ~(7 << 4); + msr.lo |= (1 << 10); /* Enable IO MWAIT redirection. */ + if (c6) + msr.lo |= (1 << 25); wrmsr(PMG_CST_CONFIG_CONTROL, msr); /* Set Processor MWAIT IO BASE */ @@ -121,52 +149,160 @@ static void configure_c_states(void) /* Set IO Capture Address */ msr.hi = 0; - msr.lo = ((PMB0_BASE + 4) & 0xffff) | (( CST_RANGE & 0xffff) << 16); + msr.lo = ((PMB0_BASE + 4) & 0xffff) | ((cst_range & 0xffff) << 16); wrmsr(PMG_IO_CAPTURE_ADDR, msr); + + if (c5) { + msr = rdmsr(MSR_BBL_CR_CTL3); + msr.lo &= ~(7 << 25); + msr.lo |= (2 << 25); + msr.lo &= ~(3 << 30); + msr.lo |= (1 << 30); + wrmsr(MSR_BBL_CR_CTL3, msr); + } +} + +static void configure_p_states(const char stepping, const char cores) +{ + msr_t msr; + + /* Find pointer to CPU configuration. */ + const device_t lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); + struct cpu_intel_model_1067x_config *const conf = + (lapic && lapic->chip_info) ? lapic->chip_info : NULL; + + msr = rdmsr(MSR_EXTENDED_CONFIG); + if (conf->slfm && (msr.lo & (1 << 27))) /* Super LFM supported? */ + msr.lo |= (1 << 28); /* Enable Super LFM. */ + wrmsr(MSR_EXTENDED_CONFIG, msr); + + if (rdmsr(MSR_FSB_CLOCK_VCC).hi & (1 << (63 - 32))) { + /* Turbo supported? */ + if ((stepping == 0xa) && (cores < 4)) { + msr = rdmsr(MSR_FSB_FREQ); + msr.lo |= (1 << 3); /* Enable hysteresis. */ + wrmsr(MSR_FSB_FREQ, msr); + } + msr = rdmsr(IA32_PERF_CTL); + msr.hi &= ~(1 << (32 - 32)); /* Clear turbo disable. */ + wrmsr(IA32_PERF_CTL, msr); + } + + msr = rdmsr(PMG_CST_CONFIG_CONTROL); + msr.lo &= ~(1 << 11); /* Enable hw coordination. */ + msr.lo |= (1 << 15); /* Lock config until next reset. */ + wrmsr(PMG_CST_CONFIG_CONTROL, msr); +} + +#define MSR_EMTTM_CR_TABLE(x) (0xa8 + (x)) +#define MSR_EMTTM_TABLE_NUM 6 +static void configure_emttm_tables(void) +{ + int i; + int num_states, pstate_idx; + msr_t msr; + sst_table_t pstates; + + /* Gather p-state information. */ + speedstep_gen_pstates(&pstates); + + /* Never turbo mode or Super LFM. */ + num_states = pstates.num_states; + if (pstates.states[0].is_turbo) + --num_states; + if (pstates.states[pstates.num_states - 1].is_slfm) + --num_states; + /* Repeat lowest p-state if we haven't enough states. */ + const int num_lowest_pstate = + (num_states < MSR_EMTTM_TABLE_NUM) + ? (MSR_EMTTM_TABLE_NUM - num_states) + 1 + : 1; + /* Start from the lowest entry but skip Super LFM. */ + if (pstates.states[pstates.num_states - 1].is_slfm) + pstate_idx = pstates.num_states - 2; + else + pstate_idx = pstates.num_states - 1; + for (i = 0; i < MSR_EMTTM_TABLE_NUM; ++i) { + if (i >= num_lowest_pstate) + --pstate_idx; + const sst_state_t *const pstate = &pstates.states[pstate_idx]; + printk(BIOS_DEBUG, "writing P-State %d: %d, %d, " + "%2d, 0x%02x, %d; encoded: 0x%04x\n", + pstate_idx, pstate->dynfsb, pstate->nonint, + pstate->ratio, pstate->vid, pstate->power, + SPEEDSTEP_ENCODE_STATE(*pstate)); + msr.hi = 0; + msr.lo = SPEEDSTEP_ENCODE_STATE(pstates.states[pstate_idx]) & + /* Don't set half ratios. */ + ~SPEEDSTEP_RATIO_NONINT; + wrmsr(MSR_EMTTM_CR_TABLE(i), msr); + } + + msr = rdmsr(MSR_EMTTM_CR_TABLE(5)); + msr.lo |= (1 << 31); /* lock tables */ + wrmsr(MSR_EMTTM_CR_TABLE(5), msr); } -#define IA32_MISC_ENABLE 0x1a0 -static void configure_misc(void) +static void configure_misc(const int eist, const int tm2, const int emttm) { msr_t msr; - msr = rdmsr(IA32_MISC_ENABLE); - msr.lo |= (1 << 3); /* TM1 enable */ - msr.lo |= (1 << 13); /* TM2 enable */ + const u32 sub_cstates = cpuid_edx(5); + + msr = rdmsr(IA32_MISC_ENABLES); + msr.lo |= (1 << 3); /* TM1 enable */ + if (tm2) + msr.lo |= (1 << 13); /* TM2 enable */ msr.lo |= (1 << 17); /* Bidirectional PROCHOT# */ + msr.lo |= (1 << 18); /* MONITOR/MWAIT enable */ msr.lo |= (1 << 10); /* FERR# multiplexing */ - // TODO: Only if IA32_PLATFORM_ID[17] = 0 and IA32_PLATFORM_ID[50] = 1 - msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ + if (eist) + msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ /* Enable C2E */ - msr.lo |= (1 << 26); + if (((sub_cstates >> (2 * 4)) & 0xf) >= 2) { + msr.lo |= (1 << 26); + } /* Enable C4E */ - /* TODO This should only be done on mobile CPUs, see cpuid 5 */ - msr.hi |= (1 << (32 - 32)); // C4E - msr.hi |= (1 << (33 - 32)); // Hard C4E + if (((sub_cstates >> (4 * 4)) & 0xf) >= 2) { + msr.hi |= (1 << (32 - 32)); // C4E + msr.hi |= (1 << (33 - 32)); // Hard C4E + } - /* Enable EMTTM. */ - /* NOTE: We leave the EMTTM_CR_TABLE0-5 at their default values */ - msr.hi |= (1 << (36 - 32)); + /* Enable EMTTM */ + if (emttm) + msr.hi |= (1 << (36 - 32)); - wrmsr(IA32_MISC_ENABLE, msr); + /* Enable turbo mode */ + if (rdmsr(MSR_FSB_CLOCK_VCC).hi & (1 << (63 - 32))) + msr.hi &= ~(1 << (38 - 32)); - msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */ - wrmsr(IA32_MISC_ENABLE, msr); + wrmsr(IA32_MISC_ENABLES, msr); + + if (eist) { + msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */ + wrmsr(IA32_MISC_ENABLES, msr); + } } #define PIC_SENS_CFG 0x1aa -static void configure_pic_thermal_sensors(void) +static void configure_pic_thermal_sensors(const int tm2, const int quad) { msr_t msr; msr = rdmsr(PIC_SENS_CFG); + if (quad) + msr.lo |= (1 << 31); + else + msr.lo &= ~(1 << 31); + if (tm2) + msr.lo |= (1 << 20); /* Enable TM1 if TM2 fails. */ msr.lo |= (1 << 21); // inter-core lock TM1 - msr.lo |= (1 << 4); // Enable bypass filter + msr.lo |= (1 << 4); // Enable bypass filter /* What does it do? */ wrmsr(PIC_SENS_CFG, msr); } @@ -179,6 +315,30 @@ static void model_1067x_init(device_t cpu) { char processor_name[49]; + + /* Gather some information: */ + + const struct cpuid_result cpuid1 = cpuid(1); + + /* Read stepping. */ + const char stepping = cpuid1.eax & 0xf; + /* Read number of cores. */ + const char cores = (cpuid1.ebx >> 16) & 0xf; + /* Is this a quad core? */ + const char quad = cores > 2; + /* Is this even a multiprocessor? */ + const char mp = cores > 1; + + /* Enable EMTTM on uni- and on multi-processors if it's not disabled. */ + const char emttm = !mp || !(rdmsr(MSR_EXTENDED_CONFIG).lo & 4); + + /* Is enhanced speedstep supported? */ + const char eist = (cpuid1.ecx & (1 << 7)) && + !(rdmsr(IA32_PLATFORM_ID).lo & (1 << 17)); + /* Test for TM2 only if EIST is available. */ + const char tm2 = eist && (cpuid1.ecx & (1 << 8)); + + /* Turn on caching if we haven't already */ x86_enable_cache(); @@ -214,13 +374,20 @@ static void model_1067x_init(device_t cpu) enable_vmx(); /* Configure C States */ - configure_c_states(); + configure_c_states(quad); + + /* Configure P States */ + configure_p_states(stepping, cores); + + /* EMTTM */ + if (emttm) + configure_emttm_tables(); /* Configure Enhanced SpeedStep and Thermal Sensors */ - configure_misc(); + configure_misc(eist, tm2, emttm); /* PIC thermal sensor control */ - configure_pic_thermal_sensors(); + configure_pic_thermal_sensors(tm2, quad); /* Start up my cpu siblings */ intel_sibling_init(cpu); @@ -242,3 +409,6 @@ static const struct cpu_driver driver __cpu_driver = { .id_table = cpu_table, }; +struct chip_operations cpu_intel_model_1067x_ops = { + CHIP_NAME("Intel Penryn CPU") +}; diff --git a/src/cpu/intel/speedstep/Makefile.inc b/src/cpu/intel/speedstep/Makefile.inc index 753dbcd..130eb0c 100644 --- a/src/cpu/intel/speedstep/Makefile.inc +++ b/src/cpu/intel/speedstep/Makefile.inc @@ -1 +1,2 @@ ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c speedstep.c +ramstage-$(CONFIG_CPU_INTEL_MODEL_1067X) += speedstep.c

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New patch to review for coreboot: c8a16c9 intel/socket_BGA956: enable more features
by Patrick Georgi 01 Nov '12

01 Nov '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1664 -gerrit commit c8a16c9a9f3cf7eba3ba8392275334f079d364c6 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Thu Nov 1 15:32:32 2012 +0100 intel/socket_BGA956: enable more features MMX, SSE, Speedstep are a given there. Change-Id: I54f34e48e34bb6ab5b9954ab7ece8c2c3a1a8e67 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- src/cpu/intel/socket_BGA956/Kconfig | 15 +++++++++++++++ src/cpu/intel/socket_BGA956/Makefile.inc | 1 + 2 files changed, 16 insertions(+) diff --git a/src/cpu/intel/socket_BGA956/Kconfig b/src/cpu/intel/socket_BGA956/Kconfig index a764348..40f82af 100644 --- a/src/cpu/intel/socket_BGA956/Kconfig +++ b/src/cpu/intel/socket_BGA956/Kconfig @@ -1,3 +1,18 @@ config CPU_INTEL_SOCKET_BGA956 bool select CPU_INTEL_MODEL_1067X + select CACHE_AS_RAM + select MMX + select SSE + +if CPU_INTEL_SOCKET_BGA956 + +config DCACHE_RAM_BASE + hex + default 0xffaf8000 + +config DCACHE_RAM_SIZE + hex + default 0x8000 + +endif diff --git a/src/cpu/intel/socket_BGA956/Makefile.inc b/src/cpu/intel/socket_BGA956/Makefile.inc index a290e69..f93fa00 100644 --- a/src/cpu/intel/socket_BGA956/Makefile.inc +++ b/src/cpu/intel/socket_BGA956/Makefile.inc @@ -7,6 +7,7 @@ subdirs-y += ../../x86/cache subdirs-y += ../../x86/smm subdirs-y += ../microcode subdirs-y += ../hyperthreading +subdirs-y += ../speedstep # Use Intel Core (not Core 2) code for CAR init, any CPU might be used. cpu_incs += $(src)/cpu/intel/model_6ex/cache_as_ram.inc

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New patch to review for coreboot: 59dc837 cpu/intel/model_1067x: Add proper c-state/p-state/thermal support
by Patrick Georgi 01 Nov '12

01 Nov '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1663 -gerrit commit 59dc837b4afcf799ff7307e30540c03413ba3f9f Author: Nico Huber <nico.huber(a)secunet.com> Date: Tue Oct 2 11:46:11 2012 +0200 cpu/intel/model_1067x: Add proper c-state/p-state/thermal support Change-Id: I853454e8f5617fb7af5dddd7288bdeeacc7b1b8e Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- src/cpu/intel/model_1067x/chip.h | 24 +++ src/cpu/intel/model_1067x/model_1067x_init.c | 232 +++++++++++++++++++++++---- src/cpu/intel/speedstep/Makefile.inc | 1 + 3 files changed, 226 insertions(+), 31 deletions(-) diff --git a/src/cpu/intel/model_1067x/chip.h b/src/cpu/intel/model_1067x/chip.h new file mode 100644 index 0000000..1731c50 --- /dev/null +++ b/src/cpu/intel/model_1067x/chip.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +struct cpu_intel_model_1067x_config { + int c5 : 1; + int c6 : 1; + int slfm : 1; +}; diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index c6d716d9..2b7839b 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007-2009 coresystems GmbH + * 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -33,6 +34,8 @@ #include <cpu/x86/cache.h> #include <cpu/x86/name.h> +#include "chip.h" + static const uint32_t microcode_updates[] = { #include "microcode-2618-m441067AA07.h" #include "microcode-2626-m1010677705.h" @@ -98,20 +101,45 @@ static void enable_vmx(void) #define PMG_CST_CONFIG_CONTROL 0xe2 #define PMG_IO_BASE_ADDR 0xe3 #define PMG_IO_CAPTURE_ADDR 0xe4 +#define MSR_BBL_CR_CTL3 0x11e +#define MSR_FSB_FREQ 0xcd -#define CST_RANGE 2 -static void configure_c_states(void) +static void configure_c_states(const int quad) { msr_t msr; - msr = rdmsr(PMG_CST_CONFIG_CONTROL); + /* Find pointer to CPU configuration. */ + const device_t lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); + const struct cpu_intel_model_1067x_config *const conf = + (lapic && lapic->chip_info) ? lapic->chip_info : NULL; - msr.lo |= (1 << 15); // config lock until next reset - msr.lo |= (1 << 14); // Deeper Sleep - msr.lo |= (1 << 10); // Enable IO MWAIT redirection - msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk - msr.lo |= (1 << 3); // Dynamic L2 + /* Is C5 requested and supported? */ + const int c5 = conf && conf->c5 && + (rdmsr(MSR_BBL_CR_CTL3).lo & (3 << 30)) && + !(rdmsr(MSR_FSB_FREQ).lo & (1 << 31)); + /* Is C6 requested and supported? */ + const int c6 = conf && conf->c6 && + ((cpuid_edx(5) >> (6 * 4)) & 0xf) && c5; + const int cst_range = (c6 ? 6 : (c5 ? 5 : 4)) - 2; /* zero means lvl2 */ + + msr = rdmsr(PMG_CST_CONFIG_CONTROL); + msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk + msr.lo |= (1 << 8); + if (quad) { + msr.lo = (msr.lo & ~(7 << 0)) | (4 << 0); + } + if (c5) { + msr.lo &= ~(1 << 13); + msr.lo &= ~(7 << 0); + msr.lo |= (1 << 3); /* Enable dynamic L2. */ + msr.lo |= (1 << 14); /* Enable deeper sleep */ + } + /* Next two fields seem to be mutually exclusive: */ + msr.lo &= ~(7 << 4); + msr.lo |= (1 << 10); /* Enable IO MWAIT redirection. */ + if (c6) + msr.lo |= (1 << 25); wrmsr(PMG_CST_CONFIG_CONTROL, msr); /* Set Processor MWAIT IO BASE */ @@ -121,52 +149,160 @@ static void configure_c_states(void) /* Set IO Capture Address */ msr.hi = 0; - msr.lo = ((PMB0_BASE + 4) & 0xffff) | (( CST_RANGE & 0xffff) << 16); + msr.lo = ((PMB0_BASE + 4) & 0xffff) | ((cst_range & 0xffff) << 16); wrmsr(PMG_IO_CAPTURE_ADDR, msr); + + if (c5) { + msr = rdmsr(MSR_BBL_CR_CTL3); + msr.lo &= ~(7 << 25); + msr.lo |= (2 << 25); + msr.lo &= ~(3 << 30); + msr.lo |= (1 << 30); + wrmsr(MSR_BBL_CR_CTL3, msr); + } +} + +static void configure_p_states(const char stepping, const char cores) +{ + msr_t msr; + + /* Find pointer to CPU configuration. */ + const device_t lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); + struct cpu_intel_model_1067x_config *const conf = + (lapic && lapic->chip_info) ? lapic->chip_info : NULL; + + msr = rdmsr(MSR_EXTENDED_CONFIG); + if (conf->slfm && (msr.lo & (1 << 27))) /* Super LFM supported? */ + msr.lo |= (1 << 28); /* Enable Super LFM. */ + wrmsr(MSR_EXTENDED_CONFIG, msr); + + if (rdmsr(MSR_FSB_CLOCK_VCC).hi & (1 << (63 - 32))) { + /* Turbo supported? */ + if ((stepping == 0xa) && (cores < 4)) { + msr = rdmsr(MSR_FSB_FREQ); + msr.lo |= (1 << 3); /* Enable hysteresis. */ + wrmsr(MSR_FSB_FREQ, msr); + } + msr = rdmsr(IA32_PERF_CTL); + msr.hi &= ~(1 << (32 - 32)); /* Clear turbo disable. */ + wrmsr(IA32_PERF_CTL, msr); + } + + msr = rdmsr(PMG_CST_CONFIG_CONTROL); + msr.lo &= ~(1 << 11); /* Enable hw coordination. */ + msr.lo |= (1 << 15); /* Lock config until next reset. */ + wrmsr(PMG_CST_CONFIG_CONTROL, msr); +} + +#define MSR_EMTTM_CR_TABLE(x) (0xa8 + (x)) +#define MSR_EMTTM_TABLE_NUM 6 +static void configure_emttm_tables(void) +{ + int i; + int num_states, pstate_idx; + msr_t msr; + sst_table_t pstates; + + /* Gather p-state information. */ + speedstep_gen_pstates(&pstates); + + /* Never turbo mode or Super LFM. */ + num_states = pstates.num_states; + if (pstates.states[0].is_turbo) + --num_states; + if (pstates.states[pstates.num_states - 1].is_slfm) + --num_states; + /* Repeat lowest p-state if we haven't enough states. */ + const int num_lowest_pstate = + (num_states < MSR_EMTTM_TABLE_NUM) + ? (MSR_EMTTM_TABLE_NUM - num_states) + 1 + : 1; + /* Start from the lowest entry but skip Super LFM. */ + if (pstates.states[pstates.num_states - 1].is_slfm) + pstate_idx = pstates.num_states - 2; + else + pstate_idx = pstates.num_states - 1; + for (i = 0; i < MSR_EMTTM_TABLE_NUM; ++i) { + if (i >= num_lowest_pstate) + --pstate_idx; + const sst_state_t *const pstate = &pstates.states[pstate_idx]; + printk(BIOS_DEBUG, "writing P-State %d: %d, %d, " + "%2d, 0x%02x, %d; encoded: 0x%04x\n", + pstate_idx, pstate->dynfsb, pstate->nonint, + pstate->ratio, pstate->vid, pstate->power, + SPEEDSTEP_ENCODE_STATE(*pstate)); + msr.hi = 0; + msr.lo = SPEEDSTEP_ENCODE_STATE(pstates.states[pstate_idx]) & + /* Don't set half ratios. */ + ~SPEEDSTEP_RATIO_NONINT; + wrmsr(MSR_EMTTM_CR_TABLE(i), msr); + } + + msr = rdmsr(MSR_EMTTM_CR_TABLE(5)); + msr.lo |= (1 << 31); /* lock tables */ + wrmsr(MSR_EMTTM_CR_TABLE(5), msr); } -#define IA32_MISC_ENABLE 0x1a0 -static void configure_misc(void) +static void configure_misc(const int eist, const int tm2, const int emttm) { msr_t msr; - msr = rdmsr(IA32_MISC_ENABLE); - msr.lo |= (1 << 3); /* TM1 enable */ - msr.lo |= (1 << 13); /* TM2 enable */ + const u32 sub_cstates = cpuid_edx(5); + + msr = rdmsr(IA32_MISC_ENABLES); + msr.lo |= (1 << 3); /* TM1 enable */ + if (tm2) + msr.lo |= (1 << 13); /* TM2 enable */ msr.lo |= (1 << 17); /* Bidirectional PROCHOT# */ + msr.lo |= (1 << 18); /* MONITOR/MWAIT enable */ msr.lo |= (1 << 10); /* FERR# multiplexing */ - // TODO: Only if IA32_PLATFORM_ID[17] = 0 and IA32_PLATFORM_ID[50] = 1 - msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ + if (eist) + msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ /* Enable C2E */ - msr.lo |= (1 << 26); + if (((sub_cstates >> (2 * 4)) & 0xf) >= 2) { + msr.lo |= (1 << 26); + } /* Enable C4E */ - /* TODO This should only be done on mobile CPUs, see cpuid 5 */ - msr.hi |= (1 << (32 - 32)); // C4E - msr.hi |= (1 << (33 - 32)); // Hard C4E + if (((sub_cstates >> (4 * 4)) & 0xf) >= 2) { + msr.hi |= (1 << (32 - 32)); // C4E + msr.hi |= (1 << (33 - 32)); // Hard C4E + } - /* Enable EMTTM. */ - /* NOTE: We leave the EMTTM_CR_TABLE0-5 at their default values */ - msr.hi |= (1 << (36 - 32)); + /* Enable EMTTM */ + if (emttm) + msr.hi |= (1 << (36 - 32)); - wrmsr(IA32_MISC_ENABLE, msr); + /* Enable turbo mode */ + if (rdmsr(MSR_FSB_CLOCK_VCC).hi & (1 << (63 - 32))) + msr.hi &= ~(1 << (38 - 32)); - msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */ - wrmsr(IA32_MISC_ENABLE, msr); + wrmsr(IA32_MISC_ENABLES, msr); + + if (eist) { + msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */ + wrmsr(IA32_MISC_ENABLES, msr); + } } #define PIC_SENS_CFG 0x1aa -static void configure_pic_thermal_sensors(void) +static void configure_pic_thermal_sensors(const int tm2, const int quad) { msr_t msr; msr = rdmsr(PIC_SENS_CFG); + if (quad) + msr.lo |= (1 << 31); + else + msr.lo &= ~(1 << 31); + if (tm2) + msr.lo |= (1 << 20); /* Enable TM1 if TM2 fails. */ msr.lo |= (1 << 21); // inter-core lock TM1 - msr.lo |= (1 << 4); // Enable bypass filter + msr.lo |= (1 << 4); // Enable bypass filter /* What does it do? */ wrmsr(PIC_SENS_CFG, msr); } @@ -179,6 +315,30 @@ static void model_1067x_init(device_t cpu) { char processor_name[49]; + + /* Gather some information: */ + + const struct cpuid_result cpuid1 = cpuid(1); + + /* Read stepping. */ + const char stepping = cpuid1.eax & 0xf; + /* Read number of cores. */ + const char cores = (cpuid1.ebx >> 16) & 0xf; + /* Is this a quad core? */ + const char quad = cores > 2; + /* Is this even a multiprocessor? */ + const char mp = cores > 1; + + /* Enable EMTTM on uni- and on multi-processors if it's not disabled. */ + const char emttm = !mp || !(rdmsr(MSR_EXTENDED_CONFIG).lo & 4); + + /* Is enhanced speedstep supported? */ + const char eist = (cpuid1.ecx & (1 << 7)) && + !(rdmsr(IA32_PLATFORM_ID).lo & (1 << 17)); + /* Test for TM2 only if EIST is available. */ + const char tm2 = eist && (cpuid1.ecx & (1 << 8)); + + /* Turn on caching if we haven't already */ x86_enable_cache(); @@ -214,13 +374,20 @@ static void model_1067x_init(device_t cpu) enable_vmx(); /* Configure C States */ - configure_c_states(); + configure_c_states(quad); + + /* Configure P States */ + configure_p_states(stepping, cores); + + /* EMTTM */ + if (emttm) + configure_emttm_tables(); /* Configure Enhanced SpeedStep and Thermal Sensors */ - configure_misc(); + configure_misc(eist, tm2, emttm); /* PIC thermal sensor control */ - configure_pic_thermal_sensors(); + configure_pic_thermal_sensors(tm2, quad); /* Start up my cpu siblings */ intel_sibling_init(cpu); @@ -242,3 +409,6 @@ static const struct cpu_driver driver __cpu_driver = { .id_table = cpu_table, }; +struct chip_operations cpu_intel_model_1067x_ops = { + CHIP_NAME("Intel Penryn CPU") +}; diff --git a/src/cpu/intel/speedstep/Makefile.inc b/src/cpu/intel/speedstep/Makefile.inc index 753dbcd..130eb0c 100644 --- a/src/cpu/intel/speedstep/Makefile.inc +++ b/src/cpu/intel/speedstep/Makefile.inc @@ -1 +1,2 @@ ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c speedstep.c +ramstage-$(CONFIG_CPU_INTEL_MODEL_1067X) += speedstep.c

1 0

Re: [coreboot] Installing uboot/qemu to Chromebook
by ron minnich 01 Nov '12

01 Nov '12

welcome! On Wed, Oct 31, 2012 at 10:46 AM, Reese Chappuis <c0dege3k(a)gmail.com> wrote: > Ron Minnich requested that we move this > conversation<https://plus.google.com/u/0/102325349472273329333/posts/Ly6n56R7Ltd> > to > here. I'm looking to install qemu on my Chromebook to run Arch Linux in a > vm. OK, I think we'lll assume seabios, rather than u-boot, for now. Sven does have an image you can use. Sven, any comments for Reese that would be helpful to other chromebook users? ron

1 0

Patch set updated for coreboot: 889a637 Overhaul speedstep code
by Nico Huber 01 Nov '12

01 Nov '12

Nico Huber (nico.huber(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1658 -gerrit commit 889a637020494e173f66c21a8ee84b7fb043ac9a Author: Nico Huber <nico.huber(a)secunet.com> Date: Tue Oct 2 11:11:42 2012 +0200 Overhaul speedstep code This adds proper support for turbo and super-low-frequency modes. Calculation of the p-states has been rewritten and moved into an extra file speedstep.c so it can be used for non-acpi stuff like EMTTM table generation. It has been tested with a Core2Duo T9400 (Penryn) and a Core Duo T2300 (Yonah) processor. Change-Id: I5f7104fc921ba67d85794254f11d486b6688ecec Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- src/cpu/intel/speedstep/Makefile.inc | 2 +- src/cpu/intel/speedstep/acpi.c | 195 +++++++++++++++++++++-------------- src/cpu/intel/speedstep/speedstep.c | 189 +++++++++++++++++++++++++++++++++ src/include/cpu/intel/speedstep.h | 74 +++++++++++++ 4 files changed, 379 insertions(+), 81 deletions(-) diff --git a/src/cpu/intel/speedstep/Makefile.inc b/src/cpu/intel/speedstep/Makefile.inc index c717a33..753dbcd 100644 --- a/src/cpu/intel/speedstep/Makefile.inc +++ b/src/cpu/intel/speedstep/Makefile.inc @@ -1 +1 @@ -ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c +ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c speedstep.c diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c index 070f8d5..910055d 100644 --- a/src/cpu/intel/speedstep/acpi.c +++ b/src/cpu/intel/speedstep/acpi.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2009 coresystems GmbH + * 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -28,7 +29,18 @@ #include <cpu/intel/speedstep.h> #include <device/device.h> -// XXX: PSS table values for power consumption are for Merom only +/** + * @brief Returns c-state entries for this system + * + * This function is usually overwritten in mainboard code. + * + * @return Number of c-states *entries will point to. + */ +int __attribute__((weak)) get_cst_entries(acpi_cstate_t **entries + __attribute__((unused))) +{ + return 0; +} static int determine_total_number_of_cores(void) { @@ -47,110 +59,133 @@ static int determine_total_number_of_cores(void) return count; } +/** + * @brief Returns three times the FSB clock in MHz + * + * The result of calculations with the returned value shall be divided by 3. + * This helps to avoid rounding errors. + */ static int get_fsb(void) { const u32 fsbcode = rdmsr(0xcd).lo & 7; switch (fsbcode) { - case 0: return 266; - case 1: return 133; - case 2: return 200; - case 3: return 166; - case 4: return 333; - case 5: return 100; - case 6: return 400; + case 0: return 800; /* / 3 == 266 */ + case 1: return 400; /* / 3 == 133 */ + case 2: return 600; /* / 3 == 200 */ + case 3: return 500; /* / 3 == 166 */ + case 4: return 1000; /* / 3 == 333 */ + case 5: return 300; /* / 3 == 100 */ + case 6: return 1200; /* / 3 == 400 */ } - printk(BIOS_DEBUG, "Warning: No supported FSB frequency. Assuming 200MHz\n"); - return 200; + printk(BIOS_WARNING, + "Warning: No supported FSB frequency. Assuming 200MHz\n"); + return 600; } -int __attribute__((weak)) get_cst_entries(acpi_cstate_t **entries __attribute__((unused))) +static int gen_pstate_entries(const sst_table_t *const pstates, + const int cpuID, const int cores_per_package, + const uint8_t coordination) { - return 0; + int i; + int len, len_ps; + int frequency; + + len = acpigen_write_empty_PCT(); + len += acpigen_write_PSD_package( + cpuID, cores_per_package, coordination); + len += acpigen_write_name("_PSS"); + + const int fsb3 = get_fsb(); + const int min_ratio2 = SPEEDSTEP_DOUBLE_RATIO( + pstates->states[pstates->num_states - 1]); + const int max_ratio2 = SPEEDSTEP_DOUBLE_RATIO(pstates->states[0]); + printk(BIOS_DEBUG, "clocks between %d and %d MHz.\n", + (min_ratio2 * fsb3) + / (pstates->states[pstates->num_states - 1].is_slfm ? 12 : 6), + (max_ratio2 * fsb3) / 6); + + printk(BIOS_DEBUG, "adding %x P-States between " + "busratio %x and %x, ""incl. P0\n", + pstates->num_states, min_ratio2 / 2, max_ratio2 / 2); + len_ps = acpigen_write_package(pstates->num_states); + for (i = 0; i < pstates->num_states; ++i) { + const sst_state_t *const pstate = &pstates->states[i]; + /* Report frequency of turbo mode as that of HFM + 1. */ + if (pstate->is_turbo) + frequency = (SPEEDSTEP_DOUBLE_RATIO( + pstates->states[i + 1]) * fsb3) / 6 + 1; + /* Super-LFM runs at half frequency. */ + else if (pstate->is_slfm) + frequency = (SPEEDSTEP_DOUBLE_RATIO(*pstate)*fsb3)/12; + else + frequency = (SPEEDSTEP_DOUBLE_RATIO(*pstate)*fsb3)/6; + len_ps += acpigen_write_PSS_package( + frequency, pstate->power, 0, 0, + SPEEDSTEP_ENCODE_STATE(*pstate), + SPEEDSTEP_ENCODE_STATE(*pstate)); + } + len_ps--; + acpigen_patch_len(len_ps); + + len += acpigen_write_PPC(0); + + len += len_ps; + + return len; } +/** + * @brief Generate ACPI entries for Speedstep for each cpu + */ void generate_cpu_entries(void) { - int len_pr, len_ps; + int len_pr; int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6; - msr_t msr; int totalcores = determine_total_number_of_cores(); int cores_per_package = (cpuid_ebx(1)>>16) & 0xff; - int numcpus = totalcores/cores_per_package; // this assumes that all CPUs share the same layout - int count; - acpi_cstate_t *cst_entries; + int numcpus = totalcores/cores_per_package; /* This assumes that all + CPUs share the same + layout. */ + int num_cstates; + acpi_cstate_t *cstates; + sst_table_t pstates; + uint8_t coordination; + + printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", + numcpus, cores_per_package); - printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", numcpus, cores_per_package); + num_cstates = get_cst_entries(&cstates); + speedstep_gen_pstates(&pstates); + if (((cpuid_eax(1) >> 4) & 0xffff) == 0x1067) + /* For Penryn use HW_ALL. */ + coordination = HW_ALL; + else + /* Use SW_ANY as that was the default. */ + coordination = SW_ANY; - for (cpuID=1; cpuID <=numcpus; cpuID++) { + for (cpuID = 0; cpuID < numcpus; ++cpuID) { for (coreID=1; coreID<=cores_per_package; coreID++) { if (coreID>1) { pcontrol_blk = 0; plen = 0; } + + /* Generate processor \_PR.CPUx. */ len_pr = acpigen_write_processor( - (cpuID - 1) * cores_per_package + coreID - 1, pcontrol_blk, plen); - len_pr += acpigen_write_empty_PCT(); - len_pr += acpigen_write_PSD_package(cpuID-1,cores_per_package,SW_ANY); - if ((count = get_cst_entries(&cst_entries)) > 0) - len_pr += acpigen_write_CST_package(cst_entries, count); - len_pr += acpigen_write_name("_PSS"); - - int max_states=8; - int busratio_step=2; - msr = rdmsr(IA32_PERF_STS); - int busratio_min=(msr.lo >> 24) & 0x1f; - int busratio_max=(msr.hi >> (40-32)) & 0x1f; - int vid_min=msr.lo & 0x3f; - msr = rdmsr(IA32_PLATFORM_ID); - int vid_max=msr.lo & 0x3f; - int clock_max=get_fsb()*busratio_max; - int clock_min=get_fsb()*busratio_min; - printk(BIOS_DEBUG, "clocks between %d and %d MHz.\n", clock_min, clock_max); -#define MEROM_MIN_POWER 16000 -#define MEROM_MAX_POWER 35000 - int power_max=MEROM_MAX_POWER; - int power_min=MEROM_MIN_POWER; - - int num_states=(busratio_max-busratio_min)/busratio_step; - while (num_states > max_states-1) { - busratio_step <<= 1; - num_states >>= 1; - } - printk(BIOS_DEBUG, "adding %x P-States between busratio %x and %x, incl. P0\n", - num_states+1, busratio_min, busratio_max); - int vid_step=(vid_max-vid_min)/num_states; - int power_step=(power_max-power_min)/num_states; - int clock_step=(clock_max-clock_min)/num_states; - len_ps = acpigen_write_package(num_states + 1); /* For Super LFM, this must - be increases by another one. */ - len_ps += acpigen_write_PSS_package( - clock_max /*mhz*/, power_max /*mW*/, 0 /*lat1*/, 0 /*lat2*/, - (busratio_max << 8) | vid_max /*control*/, - (busratio_max << 8) | vid_max /*status*/); - - int current_busratio=busratio_min+((num_states-1)*busratio_step); - int current_vid=vid_min+((num_states-1)*vid_step); - int current_power=power_min+((num_states-1)*power_step); - int current_clock=clock_min+((num_states-1)*clock_step); - int i; - for (i=0;i<num_states; i++) { - len_ps += acpigen_write_PSS_package( - current_clock /*mhz*/, current_power /*mW*/, - 0 /*lat1*/, 0 /*lat2*/, - (current_busratio << 8) | current_vid /*control*/, - (current_busratio << 8) | current_vid /*status*/); - current_busratio -= busratio_step; - current_vid -= vid_step; - current_power -= power_step; - current_clock -= clock_step; - } - len_ps--; - acpigen_patch_len(len_ps); - len_pr += acpigen_write_PPC(0); - len_pr += len_ps; + cpuID * cores_per_package + coreID - 1, + pcontrol_blk, plen); + + /* Generate p-state entries. */ + len_pr += gen_pstate_entries(&pstates, cpuID, + cores_per_package, coordination); + + /* Generate c-state entries. */ + if (num_cstates > 0) + len_pr += acpigen_write_CST_package( + cstates, num_cstates); + len_pr--; acpigen_patch_len(len_pr); } } } - diff --git a/src/cpu/intel/speedstep/speedstep.c b/src/cpu/intel/speedstep/speedstep.c new file mode 100644 index 0000000..f2cff04 --- /dev/null +++ b/src/cpu/intel/speedstep/speedstep.c @@ -0,0 +1,189 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <arch/cpu.h> +#include <cpu/x86/msr.h> +#include <console/console.h> +#include <cpu/intel/speedstep.h> + +/** + * @brief Gather speedstep limits for current processor + * + * At least power limits are processor type specific. Penryn introduced half + * steps in bus ratios. Don't know about Atom processors. + */ +static void speedstep_get_limits(sst_params_t *const params) +{ + msr_t msr; + + const uint16_t cpu_id = (cpuid_eax(1) >> 4) & 0xffff; + const uint32_t state_mask = + /* Penryn supports non integer (i.e. half) ratios. */ + ((cpu_id == 0x1067) ? SPEEDSTEP_RATIO_NONINT : 0) + | SPEEDSTEP_RATIO_VALUE_MASK | SPEEDSTEP_VID_MASK; + + /* Initialize params to zero. */ + memset(params, '\0', sizeof(*params)); + + /* Read Super-LFM parameters. */ + if (((rdmsr(MSR_EXTENDED_CONFIG).lo >> 27) & 3) == 3) {/*supported and + enabled bits */ + msr = rdmsr(MSR_FSB_CLOCK_VCC); + params->slfm = SPEEDSTEP_STATE_FROM_MSR(msr.lo, state_mask); + params->slfm.dynfsb = 1; + params->slfm.is_slfm = 1; + } + + /* Read normal minimum parameters. */ + msr = rdmsr(MSR_THERM2_CTL); + params->min = SPEEDSTEP_STATE_FROM_MSR(msr.lo, state_mask); + + /* Read normal maximum parameters. */ + /* Newer CPUs provide the normal maximum settings in + IA32_PLATFORM_ID. The values in IA32_PERF_STS change + when using turbo mode. */ + msr = rdmsr(IA32_PLATFORM_ID); + params->max = SPEEDSTEP_STATE_FROM_MSR(msr.lo, state_mask); + if (cpu_id == 0x006e) { + /* Looks like Yonah CPUs don't have the frequency ratio in + IA32_PLATFORM_ID. Use IA32_PERF_STS instead, the reading + should be reliable as those CPUs don't have turbo mode. */ + msr = rdmsr(IA32_PERF_STS); + params->max.ratio = (msr.hi & SPEEDSTEP_RATIO_VALUE_MASK) + >> SPEEDSTEP_RATIO_SHIFT; + } + + /* Read turbo parameters. */ + msr = rdmsr(MSR_FSB_CLOCK_VCC); + if ((msr.hi & (1 << (63 - 32))) && + /* supported and */ + !(rdmsr(IA32_MISC_ENABLES).hi & (1 << (38 - 32)))) { + /* not disabled */ + params->turbo = SPEEDSTEP_STATE_FROM_MSR(msr.hi, state_mask); + params->turbo.is_turbo = 1; + } + + /* Set power limits by processor type. */ + /* Defined values match the normal voltage versions only. But + they are only a hint for OSPM, so this should not hurt much. */ + switch (cpu_id) { + case 0x006e: + /* Yonah */ + params->min.power = SPEEDSTEP_MIN_POWER_YONAH; + params->max.power = SPEEDSTEP_MAX_POWER_YONAH; + break; + case 0x1067: + /* Penryn */ + params->slfm.power = SPEEDSTEP_SLFM_POWER_PENRYN; + params->min.power = SPEEDSTEP_MIN_POWER_PENRYN; + params->max.power = SPEEDSTEP_MAX_POWER_PENRYN; + params->turbo.power = SPEEDSTEP_MAX_POWER_PENRYN; + break; + case 0x006f: + /* Merom */ + default: + /* Use Merom values by default (as before). */ + params->slfm.power = SPEEDSTEP_SLFM_POWER_MEROM; + params->min.power = SPEEDSTEP_MIN_POWER_MEROM; + params->max.power = SPEEDSTEP_MAX_POWER_MEROM; + params->turbo.power = SPEEDSTEP_MAX_POWER_MEROM; + break; + } +} + +/** + * @brief Generate full p-states table from processor parameters + * + * This is generic code and should work at least for Merom and Penryn + * processors. It is used to generate acpi tables and configure EMTTM. + */ +void speedstep_gen_pstates(sst_table_t *const table) +{ + sst_params_t params; + /* Gather speedstep limits. */ + speedstep_get_limits(&params); + + + /*\ First, find the number of normal states: \*/ + + /* Calculate with doubled values to work + around non-integer (.5) bus ratios. */ + const int power_diff2 = (params.max.power - params.min.power) * 2; + const int vid_diff2 = (params.max.vid - params.min.vid) * 2; + const int max_ratio2 = SPEEDSTEP_DOUBLE_RATIO(params.max); + const int min_ratio2 = SPEEDSTEP_DOUBLE_RATIO(params.min); + const int ratio_diff2 = max_ratio2 - min_ratio2; + /* Calculate number of normal states (LFM to HFM, min to max). */ + /* Increase step size, until all states fit into the table. + (Note: First try should always work, if + SPEEDSTEP_MAX_NORMAL_STATES is set correctly.) */ + int states, step2 = 0; + do { + step2 += 2 * 2; /* Must be a multiple of 2 (doubled). */ + states = ratio_diff2 / step2 + 1; + } while (states > SPEEDSTEP_MAX_NORMAL_STATES); + if (step2 > 4) + printk(BIOS_INFO, "Enhanced Speedstep processor with " + "more than %d possible p-states.\n", + SPEEDSTEP_MAX_NORMAL_STATES); + if (states < 2) /* Report at least two normal states. */ + states = 2; + + + /*\ Now, fill the table: \*/ + + table->num_states = 0; + + /* Add turbo state if supported. */ + if (params.turbo.is_turbo) + table->states[table->num_states++] = params.turbo; + + /* Add HFM first. */ + table->states[table->num_states] = params.max; + /* Work around HFM and LFM having the same bus ratio. */ + if ((params.max.dynfsb == params.min.dynfsb) && + (params.max.nonint == params.min.nonint) && + (params.max.ratio == params.min.ratio)) + table->states[table->num_states].vid = params.min.vid; + ++table->num_states; + --states; + + /* Now, add all other normal states based on LFM (min). */ + const int power_step = (power_diff2 / states) / 2; + const int vid_step = (vid_diff2 / states) / 2; + const int ratio_step = step2 / 2; + int power = params.min.power + (states - 1) * power_step; + int vid = params.min.vid + (states - 1) * vid_step; + int ratio = params.min.ratio + (states - 1) * ratio_step; + for (; states > 0; --states) { + table->states[table->num_states++] = + (sst_state_t){ 0, 0, ratio, vid, 0, 0, power }; + power -= power_step; + vid -= vid_step; + ratio -= ratio_step; + } + + /* At last, add Super-LFM state if supported. */ + if (params.slfm.is_slfm) + table->states[table->num_states++] = params.slfm; +} diff --git a/src/include/cpu/intel/speedstep.h b/src/include/cpu/intel/speedstep.h index c3cd2d2..b5d1d68 100644 --- a/src/include/cpu/intel/speedstep.h +++ b/src/include/cpu/intel/speedstep.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007-2009 coresystems GmbH + * 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -19,6 +20,11 @@ * MA 02110-1301 USA */ +#ifndef CPU_INTEL_SPEEDSTEP_H +#define CPU_INTEL_SPEEDSTEP_H + +#include <stdint.h> + /* Magic value used to locate speedstep configuration in the device tree */ #define SPEEDSTEP_APIC_MAGIC 0xACAC @@ -39,3 +45,71 @@ #define IA32_PERF_CTL 0x199 #define MSR_THERM2_CTL 0x19D #define IA32_MISC_ENABLES 0x1A0 +#define MSR_FSB_CLOCK_VCC 0xce +#define MSR_EXTENDED_CONFIG 0xee + + +typedef struct { + uint8_t dynfsb : 1; /* whether this is SLFM */ + uint8_t nonint : 1; /* add .5 to ratio */ + uint8_t ratio : 6; + uint8_t vid; + uint8_t is_turbo; + uint8_t is_slfm; + uint32_t power; +} sst_state_t; +#define SPEEDSTEP_RATIO_SHIFT 8 +#define SPEEDSTEP_RATIO_DYNFSB_SHIFT (7 + SPEEDSTEP_RATIO_SHIFT) +#define SPEEDSTEP_RATIO_DYNFSB (1 << SPEEDSTEP_RATIO_DYNFSB_SHIFT) +#define SPEEDSTEP_RATIO_NONINT_SHIFT (6 + SPEEDSTEP_RATIO_SHIFT) +#define SPEEDSTEP_RATIO_NONINT (1 << SPEEDSTEP_RATIO_NONINT_SHIFT) +#define SPEEDSTEP_RATIO_VALUE_MASK (0x1f << SPEEDSTEP_RATIO_SHIFT) +#define SPEEDSTEP_VID_MASK 0x3f +#define SPEEDSTEP_STATE_FROM_MSR(val, mask) ((sst_state_t){ \ + 0, /* dynfsb won't be read. */ \ + ((val & mask) & SPEEDSTEP_RATIO_NONINT) ? 1 : 0, \ + (((val & mask) & SPEEDSTEP_RATIO_VALUE_MASK) \ + >> SPEEDSTEP_RATIO_SHIFT), \ + (val & mask) & SPEEDSTEP_VID_MASK, \ + 0, /* not turbo by default */ \ + 0, /* not slfm by default */ \ + 0 /* power is hardcoded in software. */ \ + }) +#define SPEEDSTEP_ENCODE_STATE(state) ( \ + ((uint16_t)(state).dynfsb << SPEEDSTEP_RATIO_DYNFSB_SHIFT) | \ + ((uint16_t)(state).nonint << SPEEDSTEP_RATIO_NONINT_SHIFT) | \ + ((uint16_t)(state).ratio << SPEEDSTEP_RATIO_SHIFT) | \ + ((uint16_t)(state).vid & SPEEDSTEP_VID_MASK)) +#define SPEEDSTEP_DOUBLE_RATIO(state) ( \ + ((uint8_t)(state).ratio * 2) + (state).nonint) + +typedef struct { + sst_state_t slfm; + sst_state_t min; + sst_state_t max; + sst_state_t turbo; +} sst_params_t; + +/* Looking at core2's spec, the highest normal bus ratio for an eist enabled + processor is 14, the lowest is always 6. This makes 5 states with the + minimal step width of 2. With turbo mode and super LFM we have at most 7. */ +#define SPEEDSTEP_MAX_NORMAL_STATES 5 +#define SPEEDSTEP_MAX_STATES (SPEEDSTEP_MAX_NORMAL_STATES + 2) +typedef struct { + /* Table of p-states for EMTTM and ACPI by decreasing performance. */ + sst_state_t states[SPEEDSTEP_MAX_STATES]; + int num_states; +} sst_table_t; + +void speedstep_gen_pstates(sst_table_t *); + +#define SPEEDSTEP_MAX_POWER_YONAH 31000 +#define SPEEDSTEP_MIN_POWER_YONAH 13100 +#define SPEEDSTEP_MAX_POWER_MEROM 35000 +#define SPEEDSTEP_MIN_POWER_MEROM 25000 +#define SPEEDSTEP_SLFM_POWER_MEROM 12000 +#define SPEEDSTEP_MAX_POWER_PENRYN 35000 +#define SPEEDSTEP_MIN_POWER_PENRYN 15000 +#define SPEEDSTEP_SLFM_POWER_PENRYN 12000 + +#endif /* CPU_INTEL_SPEEDSTEP_H */

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G31M-S2C Bios
by Louis Kruger 01 Nov '12

01 Nov '12

Hi, I am total newbie. I am interested to build a coreboot for my machine: G31M-S2C I still use XP SP3 for some of my clients and it has certain limitations ito disks larger than 2TB. I can load the SeaGate drivers, but then I have to do something else when I boot in Linux. So I thought that if I make the bios UEFI I could maybe overcome that boundary. Secondly I would like to make it possible to move the IDE drives after the SATA in stread of only before. (I am waiting for my museam permit to poses IDE drives.) So what do you seasoned bios developers think? Am I too ambitious or would it be easy. I downloaded everything and plan to test the set-up over the weekend. I already have all the data sheets of the parts that are not currently part of the main stream. How would you seasoned developers suggest I take it further. Regards, Louis.

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Patch set updated for coreboot: c541ad0 acpi: Add support for DMAR tables (Intel IOMMU support)
by Patrick Georgi 01 Nov '12

01 Nov '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1654 -gerrit commit c541ad0295f451874771a79073fd34a66bdfafe3 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Tue Sep 11 15:21:01 2012 +0200 acpi: Add support for DMAR tables (Intel IOMMU support) Adds lowlevel handling of DMAR tables for use by mainboards' ACPI code. Not much automagic (yet). Change-Id: Ia86e950dfcc5b9994202ec0e2f6d9a2912c74ad8 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- src/arch/x86/boot/acpi.c | 65 ++++++++++++++++++++++++++++++++++++++++ src/arch/x86/include/arch/acpi.h | 57 +++++++++++++++++++++++++++++++++++ 2 files changed, 122 insertions(+) diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index 9881ffe..72b6d96 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -334,6 +334,71 @@ void acpi_create_srat(acpi_srat_t *srat) header->checksum = acpi_checksum((void *)srat, header->length); } +unsigned long __attribute__((weak)) acpi_fill_dmar(unsigned long current) +{ + return current; +} + +void acpi_create_dmar(acpi_dmar_t *dmar) +{ + acpi_header_t *header = &(dmar->header); + unsigned long current = (unsigned long)dmar + sizeof(acpi_dmar_t); + + memset((void *)dmar, 0, sizeof(acpi_dmar_t)); + + /* Fill out header fields. */ + memcpy(header->signature, "DMAR", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + + header->length = sizeof(acpi_dmar_t); + header->revision = 1; + + dmar->host_address_width = 40 - 1; /* FIXME: == MTRR size? */ + dmar->flags = 0; + + current = acpi_fill_dmar(current); + + /* (Re)calculate length and checksum. */ + header->length = current - (unsigned long)dmar; + header->checksum = acpi_checksum((void *)dmar, header->length); +} + +unsigned long acpi_create_dmar_drhd(unsigned long current, u8 flags, + u16 segment, u32 bar) +{ + dmar_entry_t *drhd = (dmar_entry_t *)current; + memset(drhd, 0, sizeof(*drhd)); + drhd->type = DMAR_DRHD; + drhd->length = sizeof(*drhd); /* will be fixed up later */ + drhd->flags = flags; + drhd->segment = segment; + drhd->bar = bar; + + return drhd->length; +} + +void acpi_dmar_drhd_fixup(unsigned long base, unsigned long current) +{ + dmar_entry_t *drhd = (dmar_entry_t *)base; + drhd->length = current - base; +} + +unsigned long acpi_create_dmar_drhd_ds_pci(unsigned long current, u8 segment, + u8 dev, u8 fn) +{ + dev_scope_t *ds = (dev_scope_t *)current; + memset(ds, 0, sizeof(*ds)); + ds->type = SCOPE_PCI_ENDPOINT; + ds->length = sizeof(*ds) + 2; /* we don't support longer paths yet */ + ds->start_bus = segment; + ds->path[0].dev = dev; + ds->path[0].fn = fn; + + return ds->length; +} + /* http://h21007.www2.hp.com/portal/download/files/unprot/Itanium/slit.pdf */ void acpi_create_slit(acpi_slit_t *slit) { diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 0b2cbf4..b39e8c0 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -187,6 +187,54 @@ typedef struct acpi_madt { u32 flags; /* Multiple APIC flags */ } __attribute__ ((packed)) acpi_madt_t; +enum dev_scope_type { + SCOPE_PCI_ENDPOINT = 1, + SCOPE_PCI_SUB = 2, + SCOPE_IOAPIC = 3, + SCOPE_MSI_HPET = 4 +}; + +typedef struct dev_scope { + u8 type; + u8 length; + u8 reserved[2]; + u8 enumeration; + u8 start_bus; + struct { + u8 dev; + u8 fn; + } __attribute__((packed)) path[0]; +} __attribute__ ((packed)) dev_scope_t; + +enum dmar_type { + DMAR_DRHD = 0, + DMAR_RMRR = 1, + DMAR_ATSR = 2, + DMAR_RHSA = 3 +}; + +enum { + DRHD_INCLUDE_PCI_ALL = 1 +}; + +typedef struct dmar_entry { + u16 type; + u16 length; + u8 flags; + u8 reserved; + u16 segment; + u64 bar; +} __attribute__ ((packed)) dmar_entry_t; + +/* DMAR (DMA Remapping Reporting Structure) */ +typedef struct acpi_dmar { + struct acpi_table_header header; + u8 host_address_width; + u8 flags; + u8 reserved[10]; + dmar_entry_t structure[0]; +} __attribute__ ((packed)) acpi_dmar_t; + /* MADT: APIC Structure Types */ /* TODO: Convert to ALLCAPS. */ enum acpi_apic_types { @@ -483,6 +531,15 @@ void acpi_create_mcfg(acpi_mcfg_t *mcfg); void acpi_create_facs(acpi_facs_t *facs); +void acpi_create_dmar(acpi_dmar_t *dmar); +unsigned long acpi_create_dmar_drhd(unsigned long current, u8 flags, + u16 segment, u32 bar); +void acpi_dmar_drhd_fixup(unsigned long base, unsigned long current); +unsigned long acpi_create_dmar_drhd_ds_pci(unsigned long current, u8 segment, + u8 dev, u8 fn); + +unsigned long acpi_fill_dmar(unsigned long); + #if CONFIG_HAVE_ACPI_SLIC unsigned long acpi_create_slic(unsigned long current); #endif

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coreboot November 2012