coreboot November 2011

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Patch merged into coreboot/master: 1e93c67 Avoid false detection of SMSC FDC37N972 when Infineon TPM is present
by gerrit＠coreboot.org 07 Nov '11

07 Nov '11

the following patch was just integrated into master: commit 1e93c672d9a0464eb3b0b860e82d9c5f7f672872 Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Mon Nov 7 10:43:05 2011 -0600 Avoid false detection of SMSC FDC37N972 when Infineon TPM is present Change-Id: Ibfb3af4c5d7675a5d4e27021cbb988c2ce00fd9f Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Build-Tested: build bot (Jenkins) at Mon Nov 7 18:11:21 2011, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Mon Nov 7 18:13:14 2011, giving +2 See http://review.coreboot.org/420 for details. -gerrit

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New patch to review for coreboot: 2af661a superiotool: add detection and dump of Infineon SLB9635 TPM
by Jonathan A. Kollasch 07 Nov '11

07 Nov '11

Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/421 -gerrit commit 2af661acd3e793e6acd5448e34c85da3660eee5b Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Mon Nov 7 10:56:42 2011 -0600 superiotool: add detection and dump of Infineon SLB9635 TPM Change-Id: If94ea5f45135a4b65bdd37532851fa0ba864bb73 Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- util/superiotool/Makefile | 2 +- util/superiotool/infineon.c | 79 ++++++++++++++++++++++++++++++++++++++++ util/superiotool/superiotool.h | 6 +++ 3 files changed, 86 insertions(+), 1 deletions(-) diff --git a/util/superiotool/Makefile b/util/superiotool/Makefile index 5cc7650..e7d2f63 100644 --- a/util/superiotool/Makefile +++ b/util/superiotool/Makefile @@ -34,7 +34,7 @@ CFLAGS += -O2 -Wall -Wstrict-prototypes -Wundef -Wstrict-aliasing \ LDFLAGS += -lz OBJS = superiotool.o serverengines.o ali.o fintek.o ite.o nsc.o nuvoton.o \ - smsc.o winbond.o + smsc.o winbond.o infineon.o OS_ARCH = $(shell uname) ifeq ($(OS_ARCH), Darwin) diff --git a/util/superiotool/infineon.c b/util/superiotool/infineon.c new file mode 100644 index 0000000..da25383 --- /dev/null +++ b/util/superiotool/infineon.c @@ -0,0 +1,79 @@ +/* + * This file is part of the superiotool project. + * + * Copyright (C) 2011 Jonathan A. Kollasch <jakllsch(a)kollasch.net> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "superiotool.h" + +#define DEVICE_ID_REG 0x20 +#define DEVICE_REV_REG 0x21 + +static const struct superio_registers reg_table[] = { + {0x0b, "SLB9635TT12", { + {NOLDN, NULL, + {0x20,0x21,0x26,0x27,EOT}, + {0x0b,0x00,NANA,NANA,EOT}}, + {0, NULL, + {0x30,0x38,0x60,0x61,0x70,0x71,0xf1,0xf2,0xf3,0xf4,0xf5,EOT}, + {0x00,0x00,NANA,NANA,0x00,0x02,0xd1,0x15,0x0b,0x00,NANA,EOT}}, + {EOT}}}, + {EOT} +}; + +/* same as some SMSC */ +static void enter_conf_mode_infineon(uint16_t port) +{ + OUTB(0x55, port); +} + +static void exit_conf_mode_infineon(uint16_t port) +{ + OUTB(0xaa, port); +} + +void probe_idregs_infineon(uint16_t port) +{ + uint8_t rev, devid; + + probing_for("Infinieon", "", port); + + enter_conf_mode_infineon(port); + + devid = regval(port, DEVICE_ID_REG); + rev = regval(port, DEVICE_REV_REG); + + if (superio_unknown(reg_table, devid)) { + if (verbose) + printf(NOTFOUND "id=0x%02x, rev=0x%02x\n", devid, rev); + exit_conf_mode_infineon(port); + return; + } + + printf("Found Infineon %s (id=0x%02x, rev=0x%02x) at 0x%x\n", + get_superio_name(reg_table, devid), devid, rev, port); + chip_found = 1; + + dump_superio("Infineon", reg_table, port, devid, LDN_SEL); + + exit_conf_mode_infineon(port); +} + +void print_infineon_chips(void) +{ + print_vendor_chips("Infineon", reg_table); +} diff --git a/util/superiotool/superiotool.h b/util/superiotool/superiotool.h index f705a58..5583ec5 100644 --- a/util/superiotool/superiotool.h +++ b/util/superiotool/superiotool.h @@ -195,6 +195,10 @@ void probe_idregs_fintek(uint16_t port); void probe_idregs_fintek_alternative(uint16_t port); void print_fintek_chips(void); +/* infineon.c */ +void probe_idregs_infineon(uint16_t port); +void print_infineon_chips(void); + /* ite.c */ void probe_idregs_ite(uint16_t port); void print_ite_chips(void); @@ -243,6 +247,7 @@ static const struct { {probe_idregs_amd, {0xaa, EOT}}, #endif {probe_idregs_serverengines, {0x2e, EOT}}, + {probe_idregs_infineon, {0x2e, 0x4e}}, }; /** Table of functions to print out supported Super I/O chips. */ @@ -261,6 +266,7 @@ static const struct { {print_amd_chips}, #endif {print_serverengines_chips}, + {print_infineon_chips}, }; #endif

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Patch set updated for coreboot: 0776ce9 Add code to set the clock speed for Winbond W83627THF/THG.
by Idwer Vollering 07 Nov '11

07 Nov '11

Idwer Vollering (vidwer(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/412 -gerrit commit 0776ce9e109aa7decf366022f786d0d8c4699de2 Author: Idwer Vollering <vidwer(a)gmail.com> Date: Mon Nov 7 17:48:33 2011 +0100 Add code to set the clock speed for Winbond W83627THF/THG. Change-Id: I984404dd1df50b3ba423ac610283b9bf8bca5a31 Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- src/superio/winbond/w83627thg/early_serial.c | 9 +++++++++ src/superio/winbond/w83627thg/w83627thg.h | 2 ++ 2 files changed, 11 insertions(+), 0 deletions(-) diff --git a/src/superio/winbond/w83627thg/early_serial.c b/src/superio/winbond/w83627thg/early_serial.c index 559e982..bdb3e07 100644 --- a/src/superio/winbond/w83627thg/early_serial.c +++ b/src/superio/winbond/w83627thg/early_serial.c @@ -45,3 +45,12 @@ static void inline w83627thg_enable_serial(device_t dev, u16 iobase) pnp_set_enable(dev, 1); pnp_exit_ext_func_mode(dev); } + +void w83627thg_set_clksel_48(device_t dev) { + u8 reg8; + pnp_enter_ext_func_mode(dev); + reg8 = pnp_read_config(dev, 0x24); + reg8 |= (1 << 6); /* Set CLKSEL (clock input on pin 1) to 48MHz. */ + pnp_write_config(dev, 0x24, reg8); + pnp_exit_ext_func_mode(dev); +} diff --git a/src/superio/winbond/w83627thg/w83627thg.h b/src/superio/winbond/w83627thg/w83627thg.h index 73be544..99ff565 100644 --- a/src/superio/winbond/w83627thg/w83627thg.h +++ b/src/superio/winbond/w83627thg/w83627thg.h @@ -34,4 +34,6 @@ #define W83627THG_ACPI 10 #define W83627THG_HWM 11 /* Hardware monitor */ +void w83627thg_set_clksel_48(device_t dev); + #endif

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New patch to review for coreboot: 1e93c67 Avoid false detection of SMSC FDC37N972 when Infineon TPM is present
by Jonathan A. Kollasch 07 Nov '11

07 Nov '11

Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/420 -gerrit commit 1e93c672d9a0464eb3b0b860e82d9c5f7f672872 Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Mon Nov 7 10:43:05 2011 -0600 Avoid false detection of SMSC FDC37N972 when Infineon TPM is present Change-Id: Ibfb3af4c5d7675a5d4e27021cbb988c2ce00fd9f Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- util/superiotool/smsc.c | 13 +++++++++++++ 1 files changed, 13 insertions(+), 0 deletions(-) diff --git a/util/superiotool/smsc.c b/util/superiotool/smsc.c index 17925ae..012ffbd 100644 --- a/util/superiotool/smsc.c +++ b/util/superiotool/smsc.c @@ -844,6 +844,19 @@ static void probe_idregs_smsc_helper(uint16_t port, uint8_t idreg, return; } + /* Infineon TPM causes false match of FDC37N972 */ + if (idreg == DEVICE_ID_REG && revreg == DEVICE_REV_REG && + id == 0x0b && rev == 0x00) { + /* Infineon sets config port in 0x27:0x26, but SMSC does not */ + if (((regval(port, 0x27)<<8)|regval(port, 0x26)) == port) { + if (verbose) + printf(NOTFOUND "id=0x%02x, rev=0x%02x\n", + id, rev); + exit_conf_mode_smsc(port); + return; + } + } + printf("Found %s %s (id=0x%02x, rev=0x%02x) at 0x%x\n", (id == 0x77 ? "ASUS" : "SMSC"), get_superio_name(reg_table, id), id, rev, port);

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Trac reminder: list of new ticket(s)
by coreboot tracker 07 Nov '11

07 Nov '11

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Patch merged into coreboot/master: 16f7f24 in vt8237r_enable(), write function enables only to ISA bridge config space
by gerrit＠coreboot.org 07 Nov '11

07 Nov '11

the following patch was just integrated into master: commit 16f7f242b6f4c7d3bdd8d4f41a1f2366a861d06f Author: Florian Zumbiehl <florz(a)florz.de> Date: Tue Nov 1 20:16:16 2011 +0100 in vt8237r_enable(), write function enables only to ISA bridge config space vt8237r_enable() so far wrote the function enable values to the same offset in the config space of every one of the vt8237's functions, even though the register is located in the ISA bridge only. Change-Id: I639586dc238132f5b8d2f320b794948718281b9c Signed-off-by: Florian Zumbiehl <florz(a)florz.de> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Mon Nov 7 13:04:36 2011, giving +2 See http://review.coreboot.org/368 for details. -gerrit

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Patch merged into coreboot/master: c593fc8 Cycle time at CAS Latency (CLX - 2) is at 25 in DDR2 SPD, not at 26
by gerrit＠coreboot.org 07 Nov '11

07 Nov '11

the following patch was just integrated into master: commit c593fc823a5a2bc3de327fea5f1d44cfec8aec15 Author: Florian Zumbiehl <florz(a)florz.de> Date: Tue Nov 1 20:17:12 2011 +0100 Cycle time at CAS Latency (CLX - 2) is at 25 in DDR2 SPD, not at 26 Change-Id: Ic77854130ad43715daa7c0eb462291db48df9f84 Signed-off-by: Florian Zumbiehl <florz(a)florz.de> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Mon Nov 7 11:40:55 2011, giving +2 See http://review.coreboot.org/370 for details. -gerrit

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ASUS P5B-vm mainboard
by Rene 06 Nov '11

06 Nov '11

I want to add this board to coreboot. why? It is probably a case of because its there. I also understand that I'm not going to do this in a couple of days or weeks. ( I wonder if I will be able to get it done at all. There is a lot of low-level stuff which is overwhelming) Of this board The cpu is ????? The socket LGA 775 i haven't seen it yet in the coreboot tree. The super io Winbond W83627DHG (id=0xa0, rev=0x23) at 0x2e is supported. The North-(G965) and Southbridge(i82801H ICH8) not. :-( proc/cpuinfo processor : 1 vendor_id : GenuineIntel cpu family : 6 model : 15 model name : Intel(R) Core(TM)2 CPU 6320 @ 1.86GHz stepping : 6 cpu MHz : 1862.000 it is a LGA775 socket. I thought of adding the mainboard/asus/p5b-vm/devicetree.cb first. I use the mainboard/intel/d945clgf as a starting point. Which brings me to a first question. What is de entry for this socket/cpu in devicetree.cb? device lapic_cluster 0 on chip cpu/intel/socket_441 device lapic 0 on end end end Is there a way to generate devicetree.cb from superio and lspci output and other info ? secondly I'm a bit unsure how the keyboard pci info is derived my lspci looks like 00:00.0 Host bridge: Intel Corporation 82P965/G965 Memory Controller Hub (rev 02) 00:01.0 PCI bridge: Intel Corporation 82P965/G965 PCI Express Root Port (rev 02) 00:02.0 VGA compatible controller: Intel Corporation 82G965 Integrated Graphics Controller (rev 02) 00:1a.0 USB controller: Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #4 (rev 02) 00:1a.1 USB controller: Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #5 (rev 02) 00:1a.7 USB controller: Intel Corporation 82801H (ICH8 Family) USB2 EHCI Controller #2 (rev 02) 00:1b.0 Audio device: Intel Corporation 82801H (ICH8 Family) HD Audio Controller (rev 02) 00:1c.0 PCI bridge: Intel Corporation 82801H (ICH8 Family) PCI Express Port 1 (rev 02) 00:1c.4 PCI bridge: Intel Corporation 82801H (ICH8 Family) PCI Express Port 5 (rev 02) 00:1c.5 PCI bridge: Intel Corporation 82801H (ICH8 Family) PCI Express Port 6 (rev 02) 00:1d.0 USB controller: Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #1 (rev 02) 00:1d.1 USB controller: Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #2 (rev 02) 00:1d.2 USB controller: Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #3 (rev 02) 00:1d.7 USB controller: Intel Corporation 82801H (ICH8 Family) USB2 EHCI Controller #1 (rev 02) 00:1e.0 PCI bridge: Intel Corporation 82801 PCI Bridge (rev f2) 00:1f.0 ISA bridge: Intel Corporation 82801HB/HR (ICH8/R) LPC Interface Controller (rev 02) 00:1f.2 IDE interface: Intel Corporation 82801H (ICH8 Family) 4 port SATA IDE Controller (rev 02) 00:1f.3 SMBus: Intel Corporation 82801H (ICH8 Family) SMBus Controller (rev 02) 00:1f.5 IDE interface: Intel Corporation 82801H (ICH8 Family) 2 port SATA IDE Controller (rev 02) 02:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168B PCI Express Gigabit Ethernet controller (rev 01) 03:00.0 SATA controller: JMicron Technology Corp. JMB362/JMB363 Serial ATA Controller (rev 03) 03:00.1 IDE interface: JMicron Technology Corp. JMB362/JMB363 Serial ATA Controller (rev 03) 05:01.0 FireWire (IEEE 1394): Texas Instruments TSB43AB22A IEEE-1394a-2000 Controller (PHY/Link) [iOHCI-Lynx] the mainboard/intel/d945clgf/devicetree.cb has device pci 1f.0 on # LPC bridge chip superio/winbond/w83627dhg #######should be for my board device pnp 2e.0 off # Floppy end device pnp 2e.3 off # Parport end What I fail to understand is why these devices(floppy, keyboard, mouse, com and Parport) are not on the 1f.[0-9a-f] in d945clgf/devicetree.cb. But that might be specific for that board. How can I find these for my board? -- Rene

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buildgcc broken
by Nils 06 Nov '11

06 Nov '11

Hi Patrick and Stefan, I tried to test Patricks new patch "Change Id9e6b204: buildgcc: Explicitely state CC everywhere" but crossgcc doesn't compile at al. The problem started after commit: "Change I1b7d5b89: buildgcc: Update coreboot reference toolchain to gcc 4.6.2" The messages are: nils@Debian:~/coreboot$ make crossgcc Welcome to the coreboot cross toolchain builder v1.07 (November 1st, 2011) Invalid option Usage: ./buildgcc [-V] [-c] [-p <platform>] [-d <target directory>] [-D <dest dir>] [-G] [-S] ./buildgcc [-V|--version] ./buildgcc [-h|--help] Options: [-V|--version] print version number and exit [-h|--help] print this help and exit [-c|--clean] remove temporary files before build [-t|--savetemps] don't remove temporary files after build [-j|--jobs <num>] run <num> jobs in parallel in make [-p|--platform <platform>] target platform to build cross compiler for (defaults to i386-elf) [-d|--directory <target dir>] target directory to install cross compiler to (defaults to /home/nils/coreboot/util/crossgcc/xgcc) [-D|--destdir <dest dir>] destination directory to install cross compiler to (for RPM builds, default unset) [-G|--gdb] build GNU debugger [-S|--scripting] build scripting support for GDB make[1]: *** [build-without-gdb] Error 1 make: *** [crossgcc] Error 2 nils@Debian:~/coreboot$ Thanks, Nils.

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Patch merged into coreboot/master: fbbbb4a buildgcc: Explicitely state CC everywhere
by gerrit＠coreboot.org 06 Nov '11

06 Nov '11

the following patch was just integrated into master: commit fbbbb4a66ab9b1c2c22f75b673a7aa233de6e5e0 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Fri Nov 4 21:30:49 2011 +0100 buildgcc: Explicitely state CC everywhere This should fix issues with the iasl Makefile on Debian and prepares ccache support for buildgcc. Change-Id: Id9e6b2044b159b19bf013ec5c47b60ca1c2f2991 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Build-Tested: build bot (Jenkins) at Fri Nov 4 22:35:18 2011, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Sun Nov 6 18:44:53 2011, giving +2 See http://review.coreboot.org/399 for details. -gerrit

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coreboot November 2011