coreboot February 2010

coreboot@coreboot.org

61 participants
310 discussions

build service results for r5102
by coreboot information 09 Feb '10

09 Feb '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "oxygene" checked in revision 5102 to the coreboot repository. This caused the following changes: Change Log: Allow building images with different prefixes (ie. normal/romstage, helloWorld/romstage, ...). It defaults to fallback/, so there's no user visible change now. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Peter Stuge <peter(a)stuge.se> Build Log: Compilation of amd:serengeti_cheetah_fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5102&device=serengeti_chee… Compilation of asus:m2v-mx_se has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5102&device=m2v-mx_se&vend… Compilation of emulation:qemu-x86 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5102&device=qemu-x86&vendo… Compilation of kontron:986lcd-m has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5102&device=986lcd-m&vendo… Compilation of supermicro:h8dmr_fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5102&device=h8dmr_fam10&ve… Compilation of supermicro:h8qme_fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5102&device=h8qme_fam10&ve… Compilation of tyan:s2912_fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5102&device=s2912_fam10&ve… If something broke during this checkin please be a pain in oxygene's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

[commit] r5102 - in trunk/src: . arch/i386 arch/i386/init boot cpu/amd/car cpu/amd/model_lx
by repository service 09 Feb '10

09 Feb '10

Author: oxygene Date: Tue Feb 9 20:35:16 2010 New Revision: 5102 URL: http://tracker.coreboot.org/trac/coreboot/changeset/5102 Log: Add image updating support. When selecting it, it expects a coreboot.rom to be available, and adds the files to it. It has no idea how to replace files, it merely adds them. It only works with Tinybootblock and the bootblock is immutable. The "clean" rules allow "make clean-for-update", which removes everything but coreboot.rom Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/src/Kconfig trunk/src/arch/i386/Makefile.inc trunk/src/arch/i386/Makefile.tinybootblock.inc trunk/src/arch/i386/init/crt0.S.lb trunk/src/boot/hardwaremain.c trunk/src/cpu/amd/car/copy_and_run.c trunk/src/cpu/amd/model_lx/cache_as_ram.inc Modified: trunk/src/Kconfig ============================================================================== --- trunk/src/Kconfig Tue Feb 9 16:15:29 2010 (r5101) +++ trunk/src/Kconfig Tue Feb 9 20:35:16 2010 (r5102) @@ -39,6 +39,13 @@ the coreboot version number, so that you can easily distinguish boot logs of different boards from each other. +config CBFS_PREFIX + string "CBFS prefix to use" + default "fallback" + help + Select the prefix to all files put into the image. It's "fallback" + by default, "normal" is a common alternative. + endmenu source src/mainboard/Kconfig Modified: trunk/src/arch/i386/Makefile.inc ============================================================================== --- trunk/src/arch/i386/Makefile.inc Tue Feb 9 16:15:29 2010 (r5101) +++ trunk/src/arch/i386/Makefile.inc Tue Feb 9 20:35:16 2010 (r5102) @@ -15,14 +15,14 @@ cp $(obj)/coreboot.pre $@ if [ -f fallback/coreboot_apc ]; \ then \ - $(CBFSTOOL) $@ add-stage fallback/coreboot_apc fallback/coreboot_apc $(CBFS_COMPRESS_FLAG); \ + $(CBFSTOOL) $@ add-stage fallback/coreboot_apc $(CONFIG_CBFS_PREFIX)/coreboot_apc $(CBFS_COMPRESS_FLAG); \ fi - $(CBFSTOOL) $@ add-stage $(obj)/coreboot_ram fallback/coreboot_ram $(CBFS_COMPRESS_FLAG) + $(CBFSTOOL) $@ add-stage $(obj)/coreboot_ram $(CONFIG_CBFS_PREFIX)/coreboot_ram $(CBFS_COMPRESS_FLAG) ifeq ($(CONFIG_PAYLOAD_NONE),y) @printf " PAYLOAD none (as specified by user)\n" else @printf " PAYLOAD $(CONFIG_FALLBACK_PAYLOAD_FILE) $(CBFS_PAYLOAD_COMPRESS_FLAG)\n" - $(CBFSTOOL) $(obj)/coreboot.rom add-payload $(CONFIG_FALLBACK_PAYLOAD_FILE) fallback/payload $(CBFS_PAYLOAD_COMPRESS_FLAG) + $(CBFSTOOL) $(obj)/coreboot.rom add-payload $(CONFIG_FALLBACK_PAYLOAD_FILE) $(CONFIG_CBFS_PREFIX)/payload $(CBFS_PAYLOAD_COMPRESS_FLAG) endif ifeq ($(CONFIG_VGA_BIOS),y) @printf " VGABIOS $(CONFIG_FALLBACK_VGA_BIOS_FILE) $(CONFIG_FALLBACK_VGA_BIOS_ID)\n" Modified: trunk/src/arch/i386/Makefile.tinybootblock.inc ============================================================================== --- trunk/src/arch/i386/Makefile.tinybootblock.inc Tue Feb 9 16:15:29 2010 (r5101) +++ trunk/src/arch/i386/Makefile.tinybootblock.inc Tue Feb 9 20:35:16 2010 (r5102) @@ -10,7 +10,7 @@ $(obj)/coreboot.pre: $(obj)/coreboot.romstage $(obj)/coreboot.pre1 $(CBFSTOOL) rm -f $@ cp $(obj)/coreboot.pre1 $@ - $(CBFSTOOL) $@ add-stage $(obj)/romstage.elf fallback/romstage x 0x$(shell cat $(obj)/location.txt) + $(CBFSTOOL) $@ add-stage $(obj)/romstage.elf $(CONFIG_CBFS_PREFIX)/romstage x 0x$(shell cat $(obj)/location.txt) #FIXME: location.txt might require an offset of header size ####################################################################### @@ -58,8 +58,8 @@ $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.s: $(obj)/bootblock/bootblock.c $(CC) -x assembler-with-cpp -DASSEMBLY -E -I$(src)/include -I$(src)/arch/i386/include -I$(obj) -I$(obj)/bootblock -include $(obj)/config.h -I. -I$(src) $< > $@.new && mv $@.new $@ -$(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc: $(obj)/romcc $(src)/arch/i386/init/bootblock.c - $(obj)/romcc $(bootblock_romccflags) -O2 $(ROMCCFLAGS) $(INCLUDES) $(src)/arch/i386/init/bootblock.c -o $@ +$(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc: $(src)/arch/i386/init/$(subst ",,$(CONFIG_TINY_BOOTBLOCK_SOURCE)) $(obj)/romcc + $(obj)/romcc $(bootblock_romccflags) -O2 $(ROMCCFLAGS) $(INCLUDES) $< -o $@ $(obj)/bootblock.elf: $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.o $(obj)/bootblock/ldscript.ld @printf " LINK $(subst $(obj)/,,$(@))\n" @@ -74,7 +74,7 @@ $(CC) -nostdlib -nostartfiles -static -o $(obj)/romstage.elf -L$(obj) -T $(obj)/romstage/ldscript.ld $(initobjs) $(OBJCOPY) -O binary $(obj)/romstage.elf $(obj)/romstage.bin printf "CONFIG_ROMBASE = 0x" > $(obj)/location.ld - $(CBFSTOOL) $(obj)/coreboot.pre1 locate $(obj)/romstage.bin fallback/romstage $(CONFIG_XIP_ROM_SIZE) > $(obj)/location.txt + $(CBFSTOOL) $(obj)/coreboot.pre1 locate $(obj)/romstage.bin $(CONFIG_CBFS_PREFIX)/romstage $(CONFIG_XIP_ROM_SIZE) > $(obj)/location.txt cat $(obj)/location.txt >> $(obj)/location.ld printf ';\nAUTO_XIP_ROM_BASE = CONFIG_ROMBASE & ~(CONFIG_XIP_ROM_SIZE - 1);\n' >> $(obj)/location.ld $(CC) -nostdlib -nostartfiles -static -o $(obj)/romstage.elf -L$(obj) -T $(obj)/romstage/ldscript.ld $(initobjs) Modified: trunk/src/arch/i386/init/crt0.S.lb ============================================================================== --- trunk/src/arch/i386/init/crt0.S.lb Tue Feb 9 16:15:29 2010 (r5101) +++ trunk/src/arch/i386/init/crt0.S.lb Tue Feb 9 20:35:16 2010 (r5102) @@ -137,10 +137,7 @@ #endif /* ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG */ -#if CONFIG_USE_FALLBACK_IMAGE == 1 -str_coreboot_ram_name: .string "fallback/coreboot_ram" -#else -str_coreboot_ram_name: .string "normal/coreboot_ram" -#endif +str_coreboot_ram_name: .ascii CONFIG_CBFS_PREFIX + .string "/coreboot_ram" #endif /* CONFIG_USE_DCACHE_RAM */ Modified: trunk/src/boot/hardwaremain.c ============================================================================== --- trunk/src/boot/hardwaremain.c Tue Feb 9 16:15:29 2010 (r5101) +++ trunk/src/boot/hardwaremain.c Tue Feb 9 20:35:16 2010 (r5102) @@ -103,11 +103,7 @@ * write our configuration tables. */ lb_mem = write_tables(); -#if CONFIG_USE_FALLBACK_IMAGE == 1 - cbfs_load_payload(lb_mem, "fallback/payload"); -#else - cbfs_load_payload(lb_mem, "normal/payload"); -#endif + cbfs_load_payload(lb_mem, CONFIG_CBFS_PREFIX "/payload"); printk(BIOS_ERR, "Boot failed.\n"); } Modified: trunk/src/cpu/amd/car/copy_and_run.c ============================================================================== --- trunk/src/cpu/amd/car/copy_and_run.c Tue Feb 9 16:15:29 2010 (r5101) +++ trunk/src/cpu/amd/car/copy_and_run.c Tue Feb 9 20:35:16 2010 (r5102) @@ -7,21 +7,13 @@ static void copy_and_run(void) { -#if CONFIG_USE_FALLBACK_IMAGE == 1 - cbfs_and_run_core("fallback/coreboot_ram", 0); -#else - cbfs_and_run_core("normal/coreboot_ram", 0); -#endif + cbfs_and_run_core(CONFIG_CBFS_PREFIX "/coreboot_ram", 0); } #if CONFIG_AP_CODE_IN_CAR == 1 static void copy_and_run_ap_code_in_car(unsigned ret_addr) { -# if CONFIG_USE_FALLBACK_IMAGE == 1 - cbfs_and_run_core("fallback/coreboot_apc", ret_addr); -# else - cbfs_and_run_core("normal/coreboot_apc", ret_addr); -# endif + cbfs_and_run_core(CONFIG_CBFS_PREFIX "/coreboot_apc", ret_addr); } #endif Modified: trunk/src/cpu/amd/model_lx/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/amd/model_lx/cache_as_ram.inc Tue Feb 9 16:15:29 2010 (r5101) +++ trunk/src/cpu/amd/model_lx/cache_as_ram.inc Tue Feb 9 20:35:16 2010 (r5102) @@ -278,8 +278,5 @@ .previous #endif /* ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG */ -#if CONFIG_USE_FALLBACK_IMAGE == 1 -str_coreboot_ram_name: .string "fallback/coreboot_ram" -#else -str_coreboot_ram_name: .string "normal/coreboot_ram" -#endif +str_coreboot_ram_name: .ascii CONFIG_CBFS_PREFIX + .string "/coreboot_ram"

2 1

[commit] r5103 - in trunk: . src/arch/i386
by repository service 09 Feb '10

09 Feb '10

Author: oxygene Date: Tue Feb 9 20:41:11 2010 New Revision: 5103 URL: http://tracker.coreboot.org/trac/coreboot/changeset/5103 Log: Add image updating support. When selecting it, it expects a coreboot.rom to be available, and adds the files to it. It has no idea how to replace files, it merely adds them. It only works with Tinybootblock and the bootblock is immutable. The "clean" rules allow "make clean-for-update", which removes everything but coreboot.rom Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/Makefile trunk/src/arch/i386/Kconfig trunk/src/arch/i386/Makefile.tinybootblock.inc Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Tue Feb 9 20:35:16 2010 (r5102) +++ trunk/Makefile Tue Feb 9 20:41:11 2010 (r5103) @@ -284,15 +284,19 @@ doxygen-clean: rm -rf $(DOXYGEN_OUTPUT_DIR) -clean: doxygen-clean - rm -f $(allobjs) $(obj)/coreboot* .xcompile +clean-for-update: doxygen-clean + rm -f $(objs) $(initobjs) $(drivers) $(smmobjs) .xcompile + rm -f $(obj)/coreboot_ram* $(obj)/coreboot.romstage $(obj)/coreboot.pre* $(obj)/coreboot.bootblock $(obj)/coreboot.a rm -rf $(obj)/bootblock* $(obj)/romstage* $(obj)/location.* - rm -f $(obj)/option_table.* $(obj)/crt0_includes.h $(obj)/ldscript + rm -f $(obj)/option_table.* $(obj)/crt0_includes.h $(obj)/ldscript $(obj)/config.h rm -f $(obj)/mainboard/$(MAINBOARDDIR)/static.c $(obj)/mainboard/$(MAINBOARDDIR)/config.py $(obj)/mainboard/$(MAINBOARDDIR)/static.dot rm -f $(obj)/mainboard/$(MAINBOARDDIR)/auto.inc $(obj)/mainboard/$(MAINBOARDDIR)/crt0.s $(obj)/mainboard/$(MAINBOARDDIR)/crt0.disasm rmdir -p $(alldirs) 2>/dev/null >/dev/null || true $(MAKE) -C util/sconfig clean +clean: clean-for-update + rm -f $(obj)/coreboot* + distclean: clean rm -rf $(obj) rm -f .config .config.old ..config.tmp .kconfig.d .tmpconfig* Modified: trunk/src/arch/i386/Kconfig ============================================================================== --- trunk/src/arch/i386/Kconfig Tue Feb 9 20:35:16 2010 (r5102) +++ trunk/src/arch/i386/Kconfig Tue Feb 9 20:41:11 2010 (r5103) @@ -49,6 +49,16 @@ default n if TINY_BOOTBLOCK default y +config UPDATE_IMAGE + bool "Update existing coreboot.rom image" + default n + depends on TINY_BOOTBLOCK + help + If this option is activate, no new coreboot.rom file + is created. Instead it is expected that there already + is a suitable file for further processing. + The bootblock will not be modified. + config ROMCC bool default n Modified: trunk/src/arch/i386/Makefile.tinybootblock.inc ============================================================================== --- trunk/src/arch/i386/Makefile.tinybootblock.inc Tue Feb 9 20:35:16 2010 (r5102) +++ trunk/src/arch/i386/Makefile.tinybootblock.inc Tue Feb 9 20:41:11 2010 (r5103) @@ -3,9 +3,14 @@ ####################################################################### # Build the final rom image +ifneq ($(CONFIG_UPDATE_IMAGE),y) $(obj)/coreboot.pre1: $(obj)/coreboot.bootblock $(CBFSTOOL) rm -f $@ $(CBFSTOOL) $@ create $(CONFIG_COREBOOT_ROMSIZE_KB)K $(obj)/coreboot.bootblock +else +$(obj)/coreboot.pre1: $(CBFSTOOL) + mv $(obj)/coreboot.rom $@ +endif $(obj)/coreboot.pre: $(obj)/coreboot.romstage $(obj)/coreboot.pre1 $(CBFSTOOL) rm -f $@

1 0

[PATCH]Flexible filename prefix
by Patrick Georgi 09 Feb '10

09 Feb '10

Hi, attached file is the first part of my quest for a fallback/normal switch in the Kconfig regime. It allows building images with different prefixes (ie. normal/romstage, helloWorld/romstage, ...). It defaults to fallback/, so there's no user visible change now. It's intended to ultimately support switching between images in the Tinybootblock build model, by running the build several times, adding to the same image: First fallback, then normal, ... Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de>

2 1

[PATCH]Add "update image" feature
by Patrick Georgi 09 Feb '10

09 Feb '10

Hi, attached image adds image updating support. When selecting it, it expects a coreboot.rom to be available, and adds the files to it. It has no idea how to replace files, it merely adds them. It only works with Tinybootblock and the bootblock is immutable. The "clean" rules were changed to allow "make clean-for-update", which removes everything but coreboot.rom Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de>

2 1

Re: [coreboot] M2v-mx_se asus : nvram reset on power unplug
by congedete＠voila.fr 09 Feb '10

09 Feb '10

OK. I thought NVRAM was referring to CMOS in coreboot. You learn me a new thing again. Thank you very much Rudolf. Regards. > Message du 08/02/10 à 18h02 > De : "Rudolf Marek" <r.marek(a)assembler.cz> > A : congedete(a)voila.fr > Copie à : "Joseph Smith" <joe(a)settoplinux.org>, coreboot(a)coreboot.org > Objet : Re: [coreboot] M2v-mx_se asus : nvram reset on power unplug > > hi > > This NVRAM is for suspend/resume. So it is only powered if 5VSB is > there. So it is not a real battery backup device. > > The platform has 256 bytes of classic NVRAM (CMOS). I think you can use > ioports 74/75. to get access > to whole 256Bytes. > > (check if PCI 11.0 4e bit 3 is 1) I think it should be. > > Rudolf > > > > > > > > > congedete(a)voila.fr wrote: > > I use those methods in Seabios. > > And as soon as I unplug the power supply, load_state_from_nvram doesn't return the value saved. > > Is something wrong with my methods ? > > > > #define K8T890_NVRAM_IO_BASE 0xf00 > > int save_state_to_nvram(u32 dword) { > > int nvram_pos=64; > > dprintf(1,"Writing %x of size 4 to nvram pos: %d\n", dword, nvram_pos); > > //size=4 > > outl(dword, K8T890_NVRAM_IO_BASE+nvram_pos); > > nvram_pos +=4; > > > > return nvram_pos; > > } > > > > int load_state_from_nvram( u32 *old_dword) { > > int nvram_pos=64; > > //size=4 > > *old_dword = inl(K8T890_NVRAM_IO_BASE+nvram_pos); > > nvram_pos +=4; > > > > dprintf(1,"Loading %x of size 4 from nvram pos:%d\n", * old_dword, nvram_pos-4); > > return nvram_pos; > > } > > > > > > > >> Message du 05/02/10 à 20h38 > >> De : "Joseph Smith" <joe(a)settoplinux.org> > >> A : congedete(a)voila.fr > >> Copie à : coreboot(a)coreboot.org > >> Objet : Re: [coreboot] M2v-mx_se asus : nvram reset on power unplug > >> > >> On 02/05/2010 02:35 PM, congedete(a)voila.fr wrote: > >> > >>> > >>> > >>>> Message du 05/02/10 à 19h52 > >>>> De : "Joseph Smith"<joe(a)settoplinux.org> > >>>> A : congedete(a)voila.fr > >>>> Copie à : coreboot(a)coreboot.org > >>>> Objet : Re: [coreboot] M2v-mx_se asus : nvram reset on power unplug > >>>> > >>>> > >>>> On 02/05/2010 01:22 PM, congedete(a)voila.fr wrote: > >>>> > >>>>> Hello, > >>>>> > >>>>> When I shutdown my computer, my nvram datas are kept alive. But if I unplug/plug the power supply, nvram is reset. > >>>>> The clock is OK, so it is not a battery problem. > >>>>> > >>>>> How can I keep datas in nvram when I unplug the power supply ? > >>>>> > >>>>> > >>>> Either your CMOS battery is dead or you have RTC issue. > >>>> > >>> But the clock is OK, so I don't think my CMOS battery is dead. > >>> Could you tell me more about the RTC issue ? > >>> > >>> > >> Is this with coreboot? > >> > >> > >> -- > >> Thanks, > >> Joseph Smith > >> Set-Top-Linux > >> www.settoplinux.org > >> > >> -- > >> coreboot mailing list: coreboot(a)coreboot.org > >> http://www.coreboot.org/mailman/listinfo/coreboot > >> > > > > ____________________________________________________ > > > > Faites le plein d’amour, de cadeaux coquins et de poèmes romantiques avec Voila sur http://evenementiel.voila.fr/SaintValentin2010/ > > > > > > > > > > > > > > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot ____________________________________________________ A défaut d’un cadeau, envoyez un petit mot ! Retrouvez nos cartes de saint Valentin sur http://carte-de-voeux.voila.fr/

1 0

Request
by Ryan 09 Feb '10

09 Feb '10

Good Day I own the ecs elitegroup 945G-M3 (V1.0a) motherboard and was wondering if there is support for this motherborad.I will be very greatful.Below is the feartures of the board.Thank you CPU LGA775 socket for Intel Pentium 4 / Pentium D processor FSB 1066/800/533 MHz Support Hyper-Threading Technology CHIPSET Intel® 945G & ICH7 North Bridge: Intel® 945G South Bridge: Intel® ICH7 GRAPHICS Integrated Intel® Graphics Media Accelerator 950 ( GMA950 ) MEMORY Dual-channel DDR2 memory architecture 2 x 240-pin DDR2 DIMM socket support up to 2 GB Support DDR2 667/533/400 DDR2 SDRAM EXPANSION SLOT 1 x PCI Express x1 slot 1 x PCI Express x16 slot 2 x PCI slots STORAGE Supported by Intel®ICH7 2 x Ultra DMA100/66 devices 4 x Serial ATAII 3.0Gb/s devices AUDIO Realtek ALC880 8-channel audio CODEC IEEE 1394a VIA® VT6307, support 2x IEEE1394a ports LAN Realtek RTL8110S Gigabit LAN Controller REAR PANEL I/O 1 x PS/2 keyboard & PS/2 mouse connectors 4 x USB ports 1 x Serial port (COM1) 1 x VGA port 1 x Parallel port (LPT1) 1 x 1394a port 1 x RJ45 LAN connector 1 x Audio port (Line-in,4x Line-out, Mic_in) INTERNAL I/O CONNECTORS & HEADERS 1 x 24-pin ATX Power Supply connector 1 x 4-pin ATX 12V connector 1 x FDD connector supports two 360K~2.88MB FDDs 1 x IDE connector 4 x Serial ATA connectors 2 x USB 2.0 headers support additional 4 USB Ports 1 x Front panel switch/LED header 1 x Front panel audio header 1 x IrDA for SIR header 1 x 1394a header AUX-in header CPUFAN/SYSFAN connectors SYSTEM BIOS Award BIOS with 4Mb Flash ROM Supports Plug and Play 1.0A, APM 1.2, Multi Boot, DMI Supports ACPI revision 1.0 specification FORM FACTOR Micro-ATX Size, 244mm*244mm

1 0

[commit] r5101 - trunk/util/optionlist
by repository service 09 Feb '10

09 Feb '10

Author: stepan Date: Tue Feb 9 16:15:29 2010 New Revision: 5101 URL: http://tracker.coreboot.org/trac/coreboot/changeset/5101 Log: I took Rob Landley's nice "menuconfig2html.py" script from http://landley.net/hg/kdocs and modified it to produce MediaWiki output for coreboot's Option List at http://coreboot.org/Coreboot_Options. The attached patch exchanges our old ("newconfig") optionlist script with the new one. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Added: trunk/util/optionlist/kconfig2wiki (contents, props changed) Deleted: trunk/util/optionlist/Options-wiki.xsl trunk/util/optionlist/Options.xsl trunk/util/optionlist/mkOptionList.py Modified: trunk/util/optionlist/Makefile trunk/util/optionlist/README Modified: trunk/util/optionlist/Makefile ============================================================================== --- trunk/util/optionlist/Makefile Tue Feb 9 13:32:55 2010 (r5100) +++ trunk/util/optionlist/Makefile Tue Feb 9 16:15:29 2010 (r5101) @@ -1,10 +1,9 @@ # -# Copyright (C) 2005 Stefan Reinauer <stepan(a)coresystems.de> +# Copyright (C) 2010 coresystems GmbH # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2 of the License, or -# (at your option) any later version. +# the Free Software Foundation; version 2 of the License. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -16,17 +15,12 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # -all: html wiki -html: - ./mkOptionList.py - @#saxon Options.xml Options.xsl > Options.html - xsltproc Options.xsl Options.xml > Options.html - -wiki: - ./mkOptionList.py - xsltproc Options-wiki.xsl Options.xml > Options.wiki +SVNVERSION := $(shell LC_ALL=C svnversion -cn ../.. | sed -e "s/.*://" -e "s/$[0-9]*$.*/\1/" | grep "[0-9]" || LC_ALL=C svn info . | grep ^Revision | sed "s/.*[[:blank:]]\+$[0-9]*$[^0-9]*/\1/" | grep "[0-9]" || echo unknown) + +all: + cd ../..; util/optionlist/kconfig2wiki src/Kconfig $(SVNVERSION) > util/optionlist/Options.wiki clean: - rm -rf Options.xml Options.html Options.wiki + rm -rf Options.wiki Modified: trunk/util/optionlist/README ============================================================================== --- trunk/util/optionlist/README Tue Feb 9 13:32:55 2010 (r5100) +++ trunk/util/optionlist/README Tue Feb 9 16:15:29 2010 (r5101) @@ -1,46 +1 @@ -I would like to contribute the following to the coreboot wiki in case -it's useable: - -1. I have written a rather small Python script to convert the Options.lb - into an XML file which is much more useable for the web in most cases. - -2. I have written a XSLT to convert the XML file to (X)HTML to be able - to present it as a table. - -Florob (Florian Zeitz <florian-zeitz(a)lycos.de>) - - -ChangeLog ---------- - -* 2005-03-19 stepan - - fix xml stylesheet to work with xsltproc and saxon - - add Makefile - - make script a bit more verbose - -* 2005-03-15 florob - - Initial version - - -License -------- - -Copyright (C) 2005 Florian Zeitz <florian-zeitz(a)lycos.de> -Copyright (C) 2005-2006 Stefan Reinauer <stepan(a)coresystems.de> -Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - - +This script creates the page http://www.coreboot.org/Coreboot_Options Added: trunk/util/optionlist/kconfig2wiki ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/util/optionlist/kconfig2wiki Tue Feb 9 16:15:29 2010 (r5101) @@ -0,0 +1,133 @@ +#!/usr/bin/python +# +# kconfig2wiki - Kconfig to MediaWiki converter for +# http://www.coreboot.org/Coreboot_Options +# +# Copyright (C) 2010 coresystems GmbH +# based on http://landley.net/kdocs/make/menuconfig2html.py +# Copyright (C) by Rob Landley +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +helplen = 0 +extra_chapters = 0 + +## +## Remove quotes from Kconfig string options +## +def zapquotes(str): + if str[0]=='"': str = str[1:str.rfind('"')] + return str + +## +## Escape HTML special characters +## +def htmlescape(str): + return str.strip().replace("&","&").replace("<","<").replace(">",">") + +## +## Process Kconfig file +## +def readfile(filename): + import sys + global helplen + + source=filename.replace("src/","").replace("/Kconfig","").replace("Kconfig","toplevel") + + try: + lines = open(filename).read().split("\n") + except IOError: + sys.stderr.write("File %s missing\n" % filename) + return + config = None + description = None + configtype = None + for i in lines: + if helplen: + i = i.expandtabs() + if not len(i) or i[:helplen].isspace(): + sys.stdout.write("%s\n" % htmlescape(i)) + continue + else: + helplen = 0 + sys.stdout.write("||\n") + + words = i.strip().split(None,1) + if not len(words): continue + + if words[0] in ("config", "menuconfig"): + config = words[1] + description = "" + elif words[0] in ("bool", "boolean", "tristate", "string", "hex", "int"): + configtype = htmlescape(zapquotes(words[0])) + if len(words)>1: description = htmlescape(zapquotes(words[1])) + elif words[0]=="prompt": + description = htmlescape(zapquotes(words[1])) + elif words[0] in ("help", "---help---"): + sys.stdout.write("|- bgcolor=\"#eeeeee\"\n") + sys.stdout.write("| %s || %s || %s || %s || \n" % (config,source,configtype,description) ) + helplen = len(i[:i.find(words[0])].expandtabs()) + elif words[0] == "comment": + sys.stdout.write("|- bgcolor=\"#eeeeee\"\n") + sys.stdout.write("| || || (comment) || || %s ||\n" % htmlescape(zapquotes(words[1]))) + elif words[0]=="menu": + if len(words)>1: + temp = htmlescape(zapquotes(words[1])) + if extra_chapters: + sys.stdout.write("== Menu: %s ==\n" % temp) + sys.stdout.write("{| border=\"0\" style=\"font-size: smaller\"\n"); + sys.stdout.write("|- bgcolor=\"#6699dd\"\n") + sys.stdout.write("! align=\"left\" | Option\n") + sys.stdout.write("! align=\"left\" | Source\n") + sys.stdout.write("! align=\"left\" | Format\n") + sys.stdout.write("! align=\"left\" | Short Description\n") + sys.stdout.write("! align=\"left\" | Description\n") + else: + # Don't start an extra chapter for a + # new menu + sys.stdout.write("|- bgcolor=\"#6699dd\"\n") + sys.stdout.write("! align=\"left\" | Menu: %s || || || ||\n" % temp) + elif words[0] == "endmenu": + if extra_chapters: + sys.stdout.write("|}\n") + sys.stdout.write("\n") + elif words[0] == "source": + fn=zapquotes(words[1]) + readfile(fn) + elif words[0] in ("default","depends", "select", "if", "endif", "#"): pass + #else: sys.stderr.write("unknown: %s\n" % i) + if helplen: sys.stdout.write("||\n") + +def main(): + import sys, time + + if len(sys.argv)!=3: + sys.stderr.write("Usage: kconfig2wiki kconfigfile version\n") + sys.exit(1) + + sys.stdout.write("This is an automatically generated list of '''coreboot compile-time options'''.\n") + sys.stdout.write("\nLast update: %s. (r%s)\n" % (time.strftime('%Y/%m/%d %H:%M:%S'),sys.argv[2])) + sys.stdout.write("{| border=\"0\" style=\"font-size: smaller\"\n"); + sys.stdout.write("|- bgcolor=\"#6699dd\"\n") + sys.stdout.write("! align=\"left\" | Option\n") + sys.stdout.write("! align=\"left\" | Source\n") + sys.stdout.write("! align=\"left\" | Format\n") + sys.stdout.write("! align=\"left\" | Short Description\n") + sys.stdout.write("! align=\"left\" | Description\n") + readfile(sys.argv[1]) + sys.stdout.write("|}\n") + +if __name__ == "__main__": + main()

1 0

[PATCH] Option List Generator
by Stefan Reinauer 09 Feb '10

09 Feb '10

Hi, I took Rob Landley's nice "menuconfig2html.py" script from http://landley.net/hg/kdocs and modified it to produce MediaWiki output for coreboot's Option List at http://coreboot.org/Coreboot_Options. The attached patch exchanges our old ("newconfig") optionlist script with the new one. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866

2 1

[commit] r5097 - in trunk/src: mainboard/amd/norwich mainboard/olpc/btest mainboard/olpc/rev_a southbridge/amd/cs5536
by repository service 09 Feb '10

09 Feb '10

Author: oxygene Date: Tue Feb 9 11:22:33 2010 New Revision: 5097 URL: http://tracker.coreboot.org/trac/coreboot/changeset/5097 Log: Port of CS5536 early UART setup from v3. Permit early setup of COM2 Signed-off-by: Edwin Beasant <edwin_beasant(a)virtensys.com> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Modified: trunk/src/mainboard/amd/norwich/romstage.c trunk/src/mainboard/olpc/btest/romstage.c trunk/src/mainboard/olpc/rev_a/romstage.c trunk/src/southbridge/amd/cs5536/cs5536.c trunk/src/southbridge/amd/cs5536/cs5536_early_setup.c Modified: trunk/src/mainboard/amd/norwich/romstage.c ============================================================================== --- trunk/src/mainboard/amd/norwich/romstage.c Mon Feb 8 19:30:41 2010 (r5096) +++ trunk/src/mainboard/amd/norwich/romstage.c Tue Feb 9 11:22:33 2010 (r5097) @@ -115,7 +115,7 @@ * up later... */ /* If debug. real setup done in chipset init via Config.lb. */ - cs5536_setup_onchipuart(); + cs5536_setup_onchipuart(1); mb_gpio_init(); uart_init(); console_init(); Modified: trunk/src/mainboard/olpc/btest/romstage.c ============================================================================== --- trunk/src/mainboard/olpc/btest/romstage.c Mon Feb 8 19:30:41 2010 (r5096) +++ trunk/src/mainboard/olpc/btest/romstage.c Tue Feb 9 11:22:33 2010 (r5097) @@ -177,7 +177,7 @@ * it is counting on some early MSR setup * for cs5536 */ - cs5536_setup_onchipuart(); + cs5536_setup_onchipuart(1); gpio_init(); uart_init(); console_init(); Modified: trunk/src/mainboard/olpc/rev_a/romstage.c ============================================================================== --- trunk/src/mainboard/olpc/rev_a/romstage.c Mon Feb 8 19:30:41 2010 (r5096) +++ trunk/src/mainboard/olpc/rev_a/romstage.c Tue Feb 9 11:22:33 2010 (r5097) @@ -177,7 +177,7 @@ * it is counting on some early MSR setup * for cs5536 */ - cs5536_setup_onchipuart(); + cs5536_setup_onchipuart(1); gpio_init(); uart_init(); console_init(); Modified: trunk/src/southbridge/amd/cs5536/cs5536.c ============================================================================== --- trunk/src/southbridge/amd/cs5536/cs5536.c Mon Feb 8 19:30:41 2010 (r5096) +++ trunk/src/southbridge/amd/cs5536/cs5536.c Tue Feb 9 11:22:33 2010 (r5097) @@ -247,38 +247,45 @@ isa_dma_init(); } + +/** + * Depending on settings in the config struct, enable COM1 or COM2 or both. + * + * If the enable is NOT set, the UARTs are explicitly disabled, which is + * required if (e.g.) there is a Super I/O attached that does COM1 or COM2. + * + * @param sb Southbridge config structure. + */ static void uarts_init(struct southbridge_amd_cs5536_config *sb) { msr_t msr; - uint16_t addr; - uint32_t gpio_addr; + u16 addr = 0; + u32 gpio_addr; device_t dev; - + dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, 0); gpio_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_1); - gpio_addr &= ~1; /* clear IO bit */ - printk_debug("GPIO_ADDR: %08X\n", gpio_addr); + gpio_addr &= ~1; /* Clear I/O bit */ + printk(BIOS_DEBUG, "GPIO_ADDR: %08X\n", gpio_addr); - /* This could be extended to support IR modes */ + /* This could be extended to support IR modes. */ /* COM1 */ if (sb->com1_enable) { - /* Set the address */ + printk(BIOS_SPEW, "uarts_init: enable COM1\n"); + /* Set the address. */ switch (sb->com1_address) { case 0x3F8: addr = 7; break; - case 0x3E8: addr = 6; break; - case 0x2F8: addr = 5; break; - case 0x2E8: addr = 4; break; @@ -287,13 +294,13 @@ msr.lo |= addr << 16; wrmsr(MDD_LEG_IO, msr); - /* Set the IRQ */ + /* Set the IRQ. */ msr = rdmsr(MDD_IRQM_YHIGH); msr.lo |= sb->com1_irq << 24; wrmsr(MDD_IRQM_YHIGH, msr); /* GPIO8 - UART1_TX */ - /* Set: Output Enable (0x4) */ + /* Set: Output Enable (0x4) */ outl(GPIOL_8_SET, gpio_addr + GPIOL_OUTPUT_ENABLE); /* Set: OUTAUX1 Select (0x10) */ outl(GPIOL_8_SET, gpio_addr + GPIOL_OUT_AUX1_SELECT); @@ -301,28 +308,31 @@ /* GPIO9 - UART1_RX */ /* Set: Input Enable (0x20) */ outl(GPIOL_9_SET, gpio_addr + GPIOL_INPUT_ENABLE); - /* Set: INAUX1 Select (0x34) */ + /* Set: INAUX1 Select (0x34) */ outl(GPIOL_9_SET, gpio_addr + GPIOL_IN_AUX1_SELECT); - /* Set: GPIO 8 + 9 Pull Up (0x18) */ + /* Set: GPIO 8 + 9 Pull Up (0x18) */ outl(GPIOL_8_SET | GPIOL_9_SET, gpio_addr + GPIOL_PULLUP_ENABLE); - /* enable COM1 */ - /* Bit 1 = device enable Bit 4 = allow access to the upper banks */ + /* Enable COM1. + * + * Bit 1 = device enable + * Bit 4 = allow access to the upper banks + */ msr.lo = (1 << 4) | (1 << 1); msr.hi = 0; wrmsr(MDD_UART1_CONF, msr); - } else { - /* Reset and disable COM1 */ + /* Reset and disable COM1. */ + printk(BIOS_SPEW, "uarts_init: disable COM1\n"); msr = rdmsr(MDD_UART1_CONF); - msr.lo = 1; // reset + msr.lo = 1; /* Reset */ wrmsr(MDD_UART1_CONF, msr); - msr.lo = 0; // disabled + msr.lo = 0; /* Disabled */ wrmsr(MDD_UART1_CONF, msr); - /* Disable the IRQ */ + /* Disable the IRQ. */ msr = rdmsr(MDD_LEG_IO); msr.lo &= ~(0xF << 16); wrmsr(MDD_LEG_IO, msr); @@ -330,19 +340,17 @@ /* COM2 */ if (sb->com2_enable) { + printk(BIOS_SPEW, "uarts_init: enable COM2\n"); switch (sb->com2_address) { case 0x3F8: addr = 7; break; - case 0x3E8: addr = 6; break; - case 0x2F8: addr = 5; break; - case 0x2E8: addr = 4; break; @@ -350,11 +358,13 @@ msr = rdmsr(MDD_LEG_IO); msr.lo |= addr << 20; wrmsr(MDD_LEG_IO, msr); + printk(BIOS_SPEW, "uarts_init: wrote COM2 address 0x%x\n", sb->com2_address); - /* Set the IRQ */ + /* Set the IRQ. */ msr = rdmsr(MDD_IRQM_YHIGH); msr.lo |= sb->com2_irq << 28; wrmsr(MDD_IRQM_YHIGH, msr); + printk(BIOS_SPEW, "uarts_init: set COM2 irq\n"); /* GPIO3 - UART2_RX */ /* Set: Input Enable (0x20) */ @@ -365,34 +375,42 @@ /* GPIO4 - UART2_TX */ /* Set: Output Enable (0x4) */ outl(GPIOL_4_SET, gpio_addr + GPIOL_OUTPUT_ENABLE); + printk(BIOS_SPEW, "uarts_init: set output enable\n"); /* Set: OUTAUX1 Select (0x10) */ outl(GPIOL_4_SET, gpio_addr + GPIOL_OUT_AUX1_SELECT); + printk(BIOS_SPEW, "uarts_init: set OUTAUX1\n"); - /* Set: GPIO 3 and 4 Pull Up (0x18) */ + /* Set: GPIO 3 + 4 Pull Up (0x18) */ outl(GPIOL_3_SET | GPIOL_4_SET, gpio_addr + GPIOL_PULLUP_ENABLE); + printk(BIOS_SPEW, "uarts_init: set pullup COM2\n"); - /* enable COM2 */ - /* Bit 1 = device enable Bit 4 = allow access to the upper banks */ + /* Enable COM2. + * + * Bit 1 = device enable + * Bit 4 = allow access to the upper banks + */ msr.lo = (1 << 4) | (1 << 1); msr.hi = 0; wrmsr(MDD_UART2_CONF, msr); - + printk(BIOS_SPEW, "uarts_init: COM2 enabled\n"); } else { - /* Reset and disable COM2 */ + printk(BIOS_SPEW, "uarts_init: disable COM2\n"); + /* Reset and disable COM2. */ msr = rdmsr(MDD_UART2_CONF); - msr.lo = 1; // reset + msr.lo = 1; /* Reset */ wrmsr(MDD_UART2_CONF, msr); - msr.lo = 0; // disabled + msr.lo = 0; /* Disabled */ wrmsr(MDD_UART2_CONF, msr); - /* Disable the IRQ */ + /* Disable the IRQ. */ msr = rdmsr(MDD_LEG_IO); msr.lo &= ~(0xF << 20); wrmsr(MDD_LEG_IO, msr); } } + #define HCCPARAMS 0x08 #define IPREG04 0xA0 #define USB_HCCPW_SET (1 << 1) Modified: trunk/src/southbridge/amd/cs5536/cs5536_early_setup.c ============================================================================== --- trunk/src/southbridge/amd/cs5536/cs5536_early_setup.c Mon Feb 8 19:30:41 2010 (r5096) +++ trunk/src/southbridge/amd/cs5536/cs5536_early_setup.c Tue Feb 9 11:22:33 2010 (r5097) @@ -153,47 +153,98 @@ wrmsr(GLPCI_SB_CTRL, msr); } -/* see page 412 of the cs5536 companion book */ -static void cs5536_setup_onchipuart(void) +/** + * Enable the on-chip UART. + * + * See page 412 of the AMD Geode CS5536 Companion Device data book. + */ +void cs5536_setup_onchipuart1(void) { msr_t msr; /* Setup early for polling only mode. - * 1. Eanble GPIO 8 to OUT_AUX1, 9 to IN_AUX1 + * 1. Enable GPIO 8 to OUT_AUX1, 9 to IN_AUX1. * GPIO LBAR + 0x04, LBAR + 0x10, LBAR + 0x20, LBAR + 34 - * 2. Enable UART IO space in MDD + * 2. Enable UART I/O space in MDD. * MSR 0x51400014 bit 18:16 - * 3. Enable UART controller + * 3. Enable UART controller. * MSR 0x5140003A bit 0, 1 */ /* GPIO8 - UART1_TX */ - /* Set: Output Enable (0x4) */ + /* Set: Output Enable (0x4) */ outl(GPIOL_8_SET, GPIO_IO_BASE + GPIOL_OUTPUT_ENABLE); /* Set: OUTAUX1 Select (0x10) */ outl(GPIOL_8_SET, GPIO_IO_BASE + GPIOL_OUT_AUX1_SELECT); /* GPIO9 - UART1_RX */ - /* Set: Input Enable (0x20) */ + /* Set: Input Enable (0x20) */ outl(GPIOL_9_SET, GPIO_IO_BASE + GPIOL_INPUT_ENABLE); - /* Set: INAUX1 Select (0x34) */ + /* Set: INAUX1 Select (0x34) */ outl(GPIOL_9_SET, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT); - /* set address to 3F8 */ + /* Set address to 0x3F8. */ msr = rdmsr(MDD_LEG_IO); msr.lo |= 0x7 << 16; wrmsr(MDD_LEG_IO, msr); - /* Bit 1 = DEVEN (device enable) - * Bit 4 = EN_BANKS (allow access to the upper banks + /* Bit 1 = DEVEN (device enable) + * Bit 4 = EN_BANKS (allow access to the upper banks) */ msr.lo = (1 << 4) | (1 << 1); msr.hi = 0; - /* enable COM1 */ + /* Enable COM1. */ wrmsr(MDD_UART1_CONF, msr); } +void cs5536_setup_onchipuart2(void) +{ + msr_t msr; + + /* GPIO4 - UART2_TX */ + /* Set: Output Enable (0x4) */ + outl(GPIOL_4_SET, GPIO_IO_BASE + GPIOL_OUTPUT_ENABLE); + /* Set: OUTAUX1 Select (0x10) */ + outl(GPIOL_4_SET, GPIO_IO_BASE + GPIOL_OUT_AUX1_SELECT); + /* GPIO4 - UART2_RX */ + /* Set: Input Enable (0x20) */ + outl(GPIOL_3_SET, GPIO_IO_BASE + GPIOL_INPUT_ENABLE); + /* Set: INAUX1 Select (0x34) */ + outl(GPIOL_3_SET, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT); + + /* Set: GPIO 3 + 3 Pull Up (0x18) */ + outl(GPIOL_3_SET | GPIOL_4_SET, + GPIO_IO_BASE + GPIOL_PULLUP_ENABLE); + + /* set address to 2F8 */ + msr = rdmsr(MDD_LEG_IO); + msr.lo |= 0x5 << 20; + wrmsr(MDD_LEG_IO, msr); + + /* Bit 1 = DEVEN (device enable) + * Bit 4 = EN_BANKS (allow access to the upper banks + */ + msr.lo = (1 << 4) | (1 << 1); + msr.hi = 0; + + /* enable COM2 */ + wrmsr(MDD_UART2_CONF, msr); +} + +void cs5536_setup_onchipuart(int uart) +{ + switch (uart) { + case 1: + cs5536_setup_onchipuart1(); + break; + case 2: + cs5536_setup_onchipuart2(); + break; + } +} + + /* note: you can't do prints in here in most cases, * and we don't want to hang on serial, so they are * commented out

5 4

← Newer
1
...
19
20
21
22
23
24
25
...
31
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot February 2010