coreboot August 2008

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[PATCH] v3: per-device PCI subsystem IDs
by Carl-Daniel Hailfinger 29 Aug '08

29 Aug '08

Prepare for per-device subsystem IDs. Fix the bus location for Qemu IDE. This patch only provides the needed infrastructure for per-device subsystem IDs, it does not hook them up to the PCI core yet, so this patch is a no-op. By the way, the on_mainboard property is activating lots of completely untested code paths in v3, so someone might want to audit them. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: corebootv3-subsystem_id_per_device/mainboard/emulation/qemu-x86/dts =================================================================== --- corebootv3-subsystem_id_per_device/mainboard/emulation/qemu-x86/dts (Revision 842) +++ corebootv3-subsystem_id_per_device/mainboard/emulation/qemu-x86/dts (Arbeitskopie) @@ -30,8 +30,11 @@ bus@0 { pci@0,0 { }; - pci@1,0 { + pci@1,1 { /config/("southbridge/intel/i82371eb/ide"); + subsystem_vendor = "0x15ad"; + subsystem_device = "0x1976"; + on_mainboard; }; }; }; Index: corebootv3-subsystem_id_per_device/util/dtc/flattree.c =================================================================== --- corebootv3-subsystem_id_per_device/util/dtc/flattree.c (Revision 842) +++ corebootv3-subsystem_id_per_device/util/dtc/flattree.c (Arbeitskopie) @@ -622,6 +622,12 @@ if (streq(prop->name, "on_mainboard")){ fprintf(f, "\t.on_mainboard = 1,\n"); } + if (streq(prop->name, "subsystem_vendor")){ + fprintf(f, "\t.subsystem_vendor = %s,\n", prop->val.val); + } + if (streq(prop->name, "subsystem_device")){ + fprintf(f, "\t.subsystem_device = %s,\n", prop->val.val); + } if (streq(prop->name, "enabled")){ enabled = 1; } -- http://www.hailfinger.org/

3 3

r844 - in coreboot-v3: mainboard/emulation/qemu-x86 util/dtc
by svn＠coreboot.org 29 Aug '08

29 Aug '08

Author: hailfinger Date: 2008-08-29 10:49:24 +0200 (Fri, 29 Aug 2008) New Revision: 844 Modified: coreboot-v3/mainboard/emulation/qemu-x86/dts coreboot-v3/util/dtc/flattree.c Log: Prepare for per-device subsystem IDs. Fix the bus location for Qemu IDE. This patch only provides the needed infrastructure for per-device subsystem IDs, it does not hook them up to the PCI core yet, so this patch is a no-op. By the way, the on_mainboard property is activating lots of completely untested code paths in v3, so someone might want to audit them. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: coreboot-v3/mainboard/emulation/qemu-x86/dts =================================================================== --- coreboot-v3/mainboard/emulation/qemu-x86/dts 2008-08-29 04:33:56 UTC (rev 843) +++ coreboot-v3/mainboard/emulation/qemu-x86/dts 2008-08-29 08:49:24 UTC (rev 844) @@ -30,8 +30,11 @@ bus@0 { pci@0,0 { }; - pci@1,0 { + pci@1,1 { /config/("southbridge/intel/i82371eb/ide"); + subsystem_vendor = "0x15ad"; + subsystem_device = "0x1976"; + on_mainboard; }; }; }; Modified: coreboot-v3/util/dtc/flattree.c =================================================================== --- coreboot-v3/util/dtc/flattree.c 2008-08-29 04:33:56 UTC (rev 843) +++ coreboot-v3/util/dtc/flattree.c 2008-08-29 08:49:24 UTC (rev 844) @@ -622,6 +622,12 @@ if (streq(prop->name, "on_mainboard")){ fprintf(f, "\t.on_mainboard = 1,\n"); } + if (streq(prop->name, "subsystem_vendor")){ + fprintf(f, "\t.subsystem_vendor = %s,\n", prop->val.val); + } + if (streq(prop->name, "subsystem_device")){ + fprintf(f, "\t.subsystem_device = %s,\n", prop->val.val); + } if (streq(prop->name, "enabled")){ enabled = 1; }

1 0

r843 - in coreboot-v3: arch/x86/amd/model_fxx include/arch/x86 include/arch/x86/amd/k8 mainboard/amd/serengeti northbridge/amd/k8
by svn＠coreboot.org 29 Aug '08

29 Aug '08

Author: rminnich Date: 2008-08-29 06:33:56 +0200 (Fri, 29 Aug 2008) New Revision: 843 Modified: coreboot-v3/arch/x86/amd/model_fxx/dualcore.c coreboot-v3/arch/x86/amd/model_fxx/fidvid.c coreboot-v3/arch/x86/amd/model_fxx/init_cpus.c coreboot-v3/include/arch/x86/amd/k8/k8.h coreboot-v3/include/arch/x86/lapic.h coreboot-v3/mainboard/amd/serengeti/initram.c coreboot-v3/northbridge/amd/k8/coherent_ht.c Log: This is closer! There are < 10 functions to be worked out, so most of what you get are warnings. There is lots of room for improvement as we move to all CAR code, but that will take time. I hope to get this to really compile over the weekend. At the same time, if anybody wants to take a crack at it, your efforts are welcome. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/arch/x86/amd/model_fxx/dualcore.c =================================================================== --- coreboot-v3/arch/x86/amd/model_fxx/dualcore.c 2008-08-28 22:44:49 UTC (rev 842) +++ coreboot-v3/arch/x86/amd/model_fxx/dualcore.c 2008-08-29 04:33:56 UTC (rev 843) @@ -21,10 +21,11 @@ /** * Given a nodeid, return the count of the number of cores in that node. + * Note there are two very similar functions that do almost the same thing. * @param nodeid The nodeid * @returns The number of cores in that node. */ -unsigned int get_core_count(unsigned int nodeid) +unsigned int get_node_core_count(unsigned int nodeid) { u32 dword; dword = pci_conf1_read_config32(PCI_BDF(0, 0x18+nodeid, 3), NORTHBRIDGE_CAP); @@ -59,22 +60,22 @@ void start_cores(unsigned nodeid) { u32 dword; - /* set PCI_DEV(0, 0x18+nodeid, 3), 0x44 bit 27 to redirect all MC4 + /* set PCI_BDF(0, 0x18+nodeid, 3), 0x44 bit 27 to redirect all MC4 * accesses and error logging to core0 */ dword = pci_conf1_read_config32(PCI_BDF(0, 0x18+nodeid, 3), MCA_NB_CONFIG); dword |= MNC_NBMCATOMSTCPUEN; // NbMcaToMstCpuEn bit - pci_conf1_write_config32(PCI_DEV(0, 0x18+nodeid, 3), MCA_NB_CONFIG, dword); - // set PCI_DEV(0, 0x18+nodeid, 0), 0x68 bit 5 to start core1 + pci_conf1_write_config32(PCI_BDF(0, 0x18+nodeid, 3), MCA_NB_CONFIG, dword); + // set PCI_BDF(0, 0x18+nodeid, 0), 0x68 bit 5 to start core1 dword = pci_conf1_read_config32(PCI_BDF(0, 0x18+nodeid, 0), HT_TRANSACTION_CONTROL); dword |= HTTC_CPU1_EN; - pci_conf1_write_config32(PCI_DEV(0, 0x18+nodeid, 0), HT_TRANSACTION_CONTROL, dword); + pci_conf1_write_config32(PCI_BDF(0, 0x18+nodeid, 0), HT_TRANSACTION_CONTROL, dword); } /** * start cores on all nodes including BSP. This is assumed to be running on core 0 of node 0 */ -static inline void start_all_cores(void) +void start_all_cores(void) { unsigned nodes; unsigned nodeid; @@ -88,7 +89,7 @@ nodes = get_nodes(); for(nodeid=0; nodeid<nodes; nodeid++) { - if( get_core_count(nodeid) > 0) { + if( get_node_core_count(nodeid) > 0) { start_cores(nodeid); } } Modified: coreboot-v3/arch/x86/amd/model_fxx/fidvid.c =================================================================== --- coreboot-v3/arch/x86/amd/model_fxx/fidvid.c 2008-08-28 22:44:49 UTC (rev 842) +++ coreboot-v3/arch/x86/amd/model_fxx/fidvid.c 2008-08-29 04:33:56 UTC (rev 843) @@ -12,6 +12,7 @@ #include <amd/k8/k8.h> #include <mc146818rtc.h> #include <spd.h> +#include <lapic.h> #define K8_SET_FIDVID_DEBUG 1 @@ -25,7 +26,7 @@ #define FX_SUPPORT 1 -static void enable_fid_change(void) +void enable_fid_change(void) { u32 dword; unsigned nodes; @@ -35,26 +36,26 @@ #warning document these settings! for (i = 0; i < nodes; i++) { - dword = pci_conf1_read_config32(PCI_DEV(0, 0x18+i, 3), 0xd8); + dword = pci_conf1_read_config32(PCI_BDF(0, 0x18+i, 3), 0xd8); dword &= 0x8ff00000; dword |= (2 << 28) | (0x02710); - pci_conf1_write_config32(PCI_DEV(0, 0x18+i, 3), 0xd8, dword); + pci_conf1_write_config32(PCI_BDF(0, 0x18+i, 3), 0xd8, dword); dword = 0x04e2a707; - pci_conf1_write_config32(PCI_DEV(0, 0x18+i, 3), 0xd4, dword); + pci_conf1_write_config32(PCI_BDF(0, 0x18+i, 3), 0xd4, dword); /* disable the DRAM interface at first, it will be enabled * by raminit again */ - dword = pci_conf1_read_config32(PCI_DEV(0, 0x18+i, 2), 0x94); + dword = pci_conf1_read_config32(PCI_BDF(0, 0x18+i, 2), 0x94); dword |= (1 << 14); - pci_conf1_write_config32(PCI_DEV(0, 0x18+i, 2), 0x94, dword); + pci_conf1_write_config32(PCI_BDF(0, 0x18+i, 2), 0x94, dword); dword = 0x23070700; /* enable FID/VID change */ // dword = 0x00070000; /* enable FID/VID change */ - pci_conf1_write_config32(PCI_DEV(0, 0x18+i, 3), 0x80, dword); + pci_conf1_write_config32(PCI_BDF(0, 0x18+i, 3), 0x80, dword); dword = 0x00132113; - pci_conf1_write_config32(PCI_DEV(0, 0x18+i, 3), 0x84, dword); + pci_conf1_write_config32(PCI_BDF(0, 0x18+i, 3), 0x84, dword); } } @@ -250,7 +251,7 @@ u32 send; u32 readback = 0; unsigned int timeout = 1; - struct msr; + struct msr msr; u32 vid_cur; u32 fid_cur; u32 fid_max; @@ -425,7 +426,7 @@ } #endif -static void init_fidvid_bsp(unsigned bsp_apicid) +void init_fidvid_bsp(unsigned bsp_apicid) { u32 vid_max; u32 fid_max; Modified: coreboot-v3/arch/x86/amd/model_fxx/init_cpus.c =================================================================== --- coreboot-v3/arch/x86/amd/model_fxx/init_cpus.c 2008-08-28 22:44:49 UTC (rev 842) +++ coreboot-v3/arch/x86/amd/model_fxx/init_cpus.c 2008-08-29 04:33:56 UTC (rev 843) @@ -35,7 +35,6 @@ #include <spd.h> #include <lapic.h> -typedef void (*process_ap_t) (unsigned apicid, void *gp); /* See page 330 of Publication # 26094 Revision: 3.30 Issue Date: February 2006 * for APIC id discussion */ @@ -51,7 +50,7 @@ * @param process pointer to the function to run * @param gp general purpose argument to be passed as a parameter to the function */ -static void for_each_ap(unsigned bsp_apicid, unsigned core_range, +void for_each_ap(unsigned bsp_apicid, unsigned core_range, process_ap_t process_ap, void *gp) { /* Assume the OS will not change our APIC ID. Why does this matter? Because some of the setup @@ -74,8 +73,10 @@ get_option(&disable_siblings, "dual_core"); /* There is an interesting problem in different steppings. See page 373. The interpretation of the - * APIC ID bits is different. To determine which order is used, check bit 54 of the - /* here we assume that all nodes are the same stepping. If not, "otherwise we can use use nb_cfg_54 from bsp for all nodes" */ + * APIC ID bits is different. To determine which order is used, check bit 54 of the programmers' guide + * here we assume that all nodes are the same stepping. + * If not, "otherwise we can use use nb_cfg_54 from bsp for all nodes" + */ nb_cfg_54 = read_nb_cfg_54(); @@ -88,7 +89,7 @@ NBCAP_CmpCap_MASK); if (nb_cfg_54) { if (j == 0) // if it is single core, we need to increase siblings for apic calculation - J = 1; + j = 1; } siblings = j; @@ -192,7 +193,7 @@ void print_apicid_nodeid_coreid(unsigned apicid, struct node_core_id id, const char *str) { - printk(BIOS_DEBUG, ""%s --- { APICID = %02x NODEID = %02x COREID = %02x} ---\r\n", + printk(BIOS_DEBUG, "%s --- { APICID = %02x NODEID = %02x COREID = %02x} ---\n", str, apicid, id.nodeid, id.coreid); } @@ -445,8 +446,7 @@ timeout = wait_cpu_state(bsp_apicid, 0x44); } if (timeout) { - print_initcpu8 - ("while waiting for BSP signal to STOP, timeout in ap ", + printk(BIOS_DEBUG, "while waiting for BSP signal to STOP, timeout in ap 0x%08x\n", apicid); } /* indicate that we are in state 44 as well. We are catching up to the BSP. */ Modified: coreboot-v3/include/arch/x86/amd/k8/k8.h =================================================================== --- coreboot-v3/include/arch/x86/amd/k8/k8.h 2008-08-28 22:44:49 UTC (rev 842) +++ coreboot-v3/include/arch/x86/amd/k8/k8.h 2008-08-29 04:33:56 UTC (rev 843) @@ -62,6 +62,28 @@ #define TOP_MEM_MASK 0x007fffff #define TOP_MEM_MASK_KB (TOP_MEM_MASK >> 10) +/* MSRs for the model_fxx */ +/* the comments are confusing. Does "only E0" mean "only E0 or later" or really "Only E0" + */ +#define HWCR_MSR 0xC0010015 +#define NB_CFG_MSR 0xC001001f +#define LS_CFG_MSR 0xC0011020 +#define IC_CFG_MSR 0xC0011021 +#define DC_CFG_MSR 0xC0011022 +#define BU_CFG_MSR 0xC0011023 +#define FIDVID_CTL 0xC0010041 +#define FIDVID_STATUS 0xC0010042 + + +#define CPU_ID_FEATURES_MSR 0xc0011004 + +/* D0 only */ +#define CPU_ID_HYPER_EXT_FEATURES 0xc001100d +/* E0 only */ +#define LOGICAL_CPUS_NUM_MSR 0xc001100d + +#define CPU_ID_EXT_FEATURES_MSR 0xc0011005 + /* Definitions of various K8 registers for REV F*/ /* Function 0 */ #define NODEID 0x60 @@ -102,6 +124,10 @@ #define HTTC_HI_PRI_BYP_CNT_SHIFT 26 #define HTTC_HI_PRI_BYP_CNT_MASK 3 +#define HT_INIT_CONTROL 0x6c +#define HTIC_ColdR_Detect (1<<4) +#define HTIC_BIOSR_Detect (1<<5) +#define HTIC_INIT_Detect (1<<6) /* Function 1 */ #define PCI_IO_BASE0 0xc0 @@ -459,6 +485,7 @@ #define MCA_NB_CONFIG 0x44 #define MNC_ECC_EN (1 << 22) #define MNC_CHIPKILL_EN (1 << 23) +#define MNC_NBMCATOMSTCPUEN (1 << 27) #define SCRUB_CONTROL 0x58 #define SCRUB_NONE 0 @@ -520,6 +547,9 @@ #define NonCoherent (1 << 2) #define ConnectionPending (1 << 4) +/* Special LAPIC define which we only find in the K8 sources. */ +#define LAPIC_MSG_REG 0x380 + #ifndef ASSEMBLY /* Steppings of the K8 cpu */ @@ -614,9 +644,10 @@ unsigned coreid; }; -/* use this to get the nodeid and core it of the current cpu (but not other CPUs) */ -/* the nb_cfg_54 indicates the setting of bit 54 (InitApicIdCpuIdLo) */ -struct node_core_id get_node_core_id(unsigned int nb_cfg_54); +/* use this to get the nodeid and core id of the current cpu + * (but not other CPUs) + */ +struct node_core_id get_node_core_id(void); struct device; unsigned get_apicid_base(unsigned ioapic_num); @@ -628,8 +659,37 @@ int node_id; }; +typedef void (*process_ap_t) (unsigned apicid, void *gp); + struct hw_mem_hole_info get_hw_mem_hole_info(void); +/* General purpose support functions that can run in any stage. */ + +unsigned int get_nodes(void); +unsigned int init_cpus(unsigned cpu_init_detectedx, + struct sys_info *sysinfo); +void setup_coherent_ht_domain(void); +void wait_all_core0_started(void); +void start_all_cores(void); +void wait_all_other_cores_started(unsigned bsp_apicid); +void for_each_ap(unsigned bsp_apicid, unsigned core_range, + process_ap_t process_ap, void *gp); +void ht_setup_chains_x(struct sys_info *sysinfo); +int optimize_link_coherent_ht(void); +int optimize_link_incoherent_ht(struct sys_info *sysinfo); +void allow_all_aps_stop(unsigned bsp_apicid); +unsigned int get_core_count(void); +void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, + const u16 *spd_addr); +int lapic_remote_read(int apicid, int reg, unsigned int *pvalue); +void print_apicid_nodeid_coreid(unsigned apicid, struct node_core_id id, + const char *str); +unsigned int wait_cpu_state(unsigned apicid, unsigned state); +void set_apicid_cpuid_lo(void); +/* fidvid.c */ +void enable_fid_change(void); +void init_fidvid_bsp(unsigned bsp_apicid); + #endif /* ! ASSEMBLY */ #endif /* AMD_K8_H */ Modified: coreboot-v3/include/arch/x86/lapic.h =================================================================== --- coreboot-v3/include/arch/x86/lapic.h 2008-08-28 22:44:49 UTC (rev 842) +++ coreboot-v3/include/arch/x86/lapic.h 2008-08-29 04:33:56 UTC (rev 843) @@ -120,7 +120,8 @@ xchg((volatile unsigned long *)(LAPIC_DEFAULT_BASE+reg), v); } - +/* I think we don't want to do this any more. But there is one defined for k8 explicitly; what to do?*/ +#if 0 #ifdef CONFIG_X86_GOOD_APIC # define FORCE_READ_AROUND_WRITE 0 # define lapic_read_around(x) lapic_read(x) @@ -155,7 +156,7 @@ return result; } - +#endif void setup_lapic(void); Modified: coreboot-v3/mainboard/amd/serengeti/initram.c =================================================================== --- coreboot-v3/mainboard/amd/serengeti/initram.c 2008-08-28 22:44:49 UTC (rev 842) +++ coreboot-v3/mainboard/amd/serengeti/initram.c 2008-08-29 04:33:56 UTC (rev 843) @@ -111,6 +111,7 @@ * That way we can see the definition without grepping the source tree. */ void enable_smbus(void); + void enable_fid_change_on_sb(u16 sbbusn, u16 sbdn); u32 init_detected; static const u16 spd_addr[] = { //first node @@ -195,8 +196,8 @@ // show final fid and vid { - struct msr; - msr=rdmsr(msr_t); + struct msr msr; + msr=rdmsr(FIDVID_STATUS); printk(BIOS_DEBUG, "begin msr fid, vid %08x:%08x\n", msr.hi ,msr.lo); } Modified: coreboot-v3/northbridge/amd/k8/coherent_ht.c =================================================================== --- coreboot-v3/northbridge/amd/k8/coherent_ht.c 2008-08-28 22:44:49 UTC (rev 842) +++ coreboot-v3/northbridge/amd/k8/coherent_ht.c 2008-08-29 04:33:56 UTC (rev 843) @@ -1692,7 +1692,7 @@ /** * get_nodes * see page 46 of the BKDG Publication # 26094 Revision: 3.30 Issue Date: February 2006 - * @returns an int containing the node id. + * @returns an int containing the number of nodes. * The format of the register is 32 bits, and the node count is in bits 4-6 */ unsigned int get_nodes(void)

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v3 phase3/phase5 strangeness
by Carl-Daniel Hailfinger 29 Aug '08

29 Aug '08

Why do we call a phase5 function in the middle of phase3? Boot log excerpt on qemu follows: > Phase 3: Enumerating buses... > dev_phase3_scan: scanning root(Root Device) > scan_static_bus for root (Root Device) > cpus: Unknown device path type: 0 > cpus() enabled > dev_phase5: bus_0(PCI_BUS: 0000) missing ops ^^^^^^^^^^ > domain_0(PCI_DOMAIN: 0000) enabled > domain_0(PCI_DOMAIN: 0000) scanning... > dev_phase3_scan: scanning domain_0(PCI_DOMAIN: 0000) As a side note, I'd like to ask everybody working on v3 to read through a complete boot log of his favourite board and ask for explanations if he/she doesn't understand something or if something looks fishy. Sorting the whole boot log and trying to explain duplicate lines is also very interesting. Regards, Carl-Daniel -- http://www.hailfinger.org/

2 1

r3553 - trunk/payloads/libpayload/libc
by svn＠coreboot.org 29 Aug '08

29 Aug '08

Author: jcrouse Date: 2008-08-29 01:12:34 +0200 (Fri, 29 Aug 2008) New Revision: 3553 Modified: trunk/payloads/libpayload/libc/time.c Log: [PATCH]: libpayload: Document time functions No code changes. Signed-off-by: Jordan Crouse <jordan.crouse(a)amd.com> Acked-by: Jordan Crouse <jordan.crouse(a)amd.com> Modified: trunk/payloads/libpayload/libc/time.c =================================================================== --- trunk/payloads/libpayload/libc/time.c 2008-08-28 23:12:22 UTC (rev 3552) +++ trunk/payloads/libpayload/libc/time.c 2008-08-28 23:12:34 UTC (rev 3553) @@ -27,6 +27,10 @@ * SUCH DAMAGE. */ +/** @file libc/time.c + * @brief General Time Functions + */ + #include <config.h> #include <libpayload.h> #include <arch/rdtsc.h> @@ -110,6 +114,12 @@ } #endif +/** + * Return the current time broken into a timeval structure + * @param tv A pointer to a timeval structure + * @param tz Added for compatability - not used + * @return 0 for success + */ int gettimeofday(struct timeval *tv, void *tz) { /* Call the gtod init when we need it - this keeps

1 0

r3552 - in trunk/payloads/libpayload: i386 include
by svn＠coreboot.org 29 Aug '08

29 Aug '08

Author: jcrouse Date: 2008-08-29 01:12:22 +0200 (Fri, 29 Aug 2008) New Revision: 3552 Modified: trunk/payloads/libpayload/i386/timer.c trunk/payloads/libpayload/include/libpayload.h Log: [PATCH]: libpayload: Document the architecture specific routines No code changes. Signed-off-by: Jordan Crouse <jordan.crouse(a)amd.com> Acked-by: Jordan Crouse <jordan.crouse(a)amd.com> Modified: trunk/payloads/libpayload/i386/timer.c =================================================================== --- trunk/payloads/libpayload/i386/timer.c 2008-08-28 23:12:02 UTC (rev 3551) +++ trunk/payloads/libpayload/i386/timer.c 2008-08-28 23:12:22 UTC (rev 3552) @@ -27,9 +27,17 @@ * SUCH DAMAGE. */ +/** @file i386/timer.c + * @brief i386 specific timer routines + */ + #include <libpayload.h> #include <arch/rdtsc.h> +/** + * @ingroup arch + * Global variable containing the speed of the processor in KHz + */ u32 cpu_khz; /** @@ -72,21 +80,39 @@ while (rdtsc() < timeout) ; } +/** + * Delay for a specified number of nanoseconds + * @param n Number of nanoseconds to delay for + */ void ndelay(unsigned int n) { _delay(n * cpu_khz / 1000000); } +/** + * Delay for a specified number of microseconds + * @param n Number of microseconds to delay for + */ void udelay(unsigned int n) { _delay(n * cpu_khz / 1000); } +/** + * Delay for a specified number of milliseconds + * @param n Number of milliseconds to delay for + */ + void mdelay(unsigned int m) { _delay(m * cpu_khz); } +/** + * Delay for a specified number of seconds + * @param n Number of seconds to delay for + */ + void delay(unsigned int s) { _delay(s * cpu_khz * 1000); Modified: trunk/payloads/libpayload/include/libpayload.h =================================================================== --- trunk/payloads/libpayload/include/libpayload.h 2008-08-28 23:12:02 UTC (rev 3551) +++ trunk/payloads/libpayload/include/libpayload.h 2008-08-28 23:12:22 UTC (rev 3552) @@ -244,6 +244,7 @@ long long int llabs(long long int j); u8 bin2hex(u8 b); u8 hex2bin(u8 h); +void fatal(const char* msg) __attribute__ ((noreturn)); /** @} */ /** @@ -398,6 +399,8 @@ /** * @defgroup arch Architecture Specific Functions + * This modules contains global architecure specific functions. + * All architectures are expected to define these functions. * @{ */ int get_coreboot_info(struct sysinfo_t *info); @@ -411,9 +414,13 @@ void mdelay(unsigned int n); void delay(unsigned int n); -#define abort() halt() +#define abort() halt() /**< Alias for the halt() function */ + +/** + * Stops executions and halts the processor. This function does + * not return. + */ void halt(void) __attribute__ ((noreturn)); -void fatal(const char* msg) __attribute__ ((noreturn)); /** @} */ /**

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r3551 - trunk/payloads/libpayload/i386
by svn＠coreboot.org 29 Aug '08

29 Aug '08

Author: jcrouse Date: 2008-08-29 01:12:02 +0200 (Fri, 29 Aug 2008) New Revision: 3551 Modified: trunk/payloads/libpayload/i386/timer.c Log: [PATCH]: libpayload: change the type of the cpu_khz variable This makes it match the extern declaration in libc/time.c - and doxygen can find make the connection. Trivial. Signed-off-by: Jordan Crouse <jordan.crouse(a)amd.com> Acked-by: Jordan Crouse <jordan.crouse(a)amd.com> Modified: trunk/payloads/libpayload/i386/timer.c =================================================================== --- trunk/payloads/libpayload/i386/timer.c 2008-08-28 23:11:29 UTC (rev 3550) +++ trunk/payloads/libpayload/i386/timer.c 2008-08-28 23:12:02 UTC (rev 3551) @@ -30,7 +30,7 @@ #include <libpayload.h> #include <arch/rdtsc.h> -unsigned int cpu_khz; +u32 cpu_khz; /** * Calculate the speed of the processor for use in delays.

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r3550 - in trunk/payloads/libpayload: include libc
by svn＠coreboot.org 29 Aug '08

29 Aug '08

Author: jcrouse Date: 2008-08-29 01:11:29 +0200 (Fri, 29 Aug 2008) New Revision: 3550 Modified: trunk/payloads/libpayload/include/libpayload.h trunk/payloads/libpayload/libc/readline.c Log: [PATCH]: libpayload: Document readline No code changes. Signed-off-by: Jordan Crouse <jordan.crouse(a)amd.com> Acked-by: Jordan Crouse <jordan.crouse(a)amd.com> Modified: trunk/payloads/libpayload/include/libpayload.h =================================================================== --- trunk/payloads/libpayload/include/libpayload.h 2008-08-28 23:10:55 UTC (rev 3549) +++ trunk/payloads/libpayload/include/libpayload.h 2008-08-28 23:11:29 UTC (rev 3550) @@ -418,6 +418,9 @@ /** * @defgroup readline Readline Functions + * This interface provides a simple implementation of the standard + * readline and getline functions. They are suitable for reading a + * line of input from the console. * @{ */ char * readline(const char * prompt); Modified: trunk/payloads/libpayload/libc/readline.c =================================================================== --- trunk/payloads/libpayload/libc/readline.c 2008-08-28 23:10:55 UTC (rev 3549) +++ trunk/payloads/libpayload/libc/readline.c 2008-08-28 23:11:29 UTC (rev 3550) @@ -27,16 +27,26 @@ * SUCH DAMAGE. */ +/** @file libc/readline.c + * @brief Simple readline implementation + */ + #include <libpayload.h> static char * readline_buffer; static int readline_bufferlen; /** - * This readline implementation is rather simple, but it does more than the - * original readline() because it allows us to have a pre-filled buffer. To - * pre-fill the buffer, use the getline() function. + * @brief Read a line from the terminal and return it + * @param prompt A prompt to display on the line + * @return A pointer to the input string + * + * Read a line from the terminal and return it. This readline implementation + * is rather simple, but it does more than the original readline() because + * it allows us to have a pre-filled buffer. To pre-fill the buffer, use the + * getline() function. */ + char * readline(const char * prompt) { char *buffer; @@ -50,7 +60,7 @@ } buffer = readline_buffer; - + /* print prompt */ if (prompt) { current = 0; @@ -140,6 +150,18 @@ return buffer; } +/** + * @brief Read a line from the input and store it in a buffer + * @param prompt A buffer to store the line in + * @param len Length of the buffer + * @return The final length of the string + * This function allows the user to pass a predefined buffer to + * readline(). The buffer may be filled with a default value + * which will be displayed by readline and can be edited as normal. + * The final input string returned by readline will be returned in + * the buffer and the function will return the length of the string. + */ + int getline(char *buffer, int len) { readline_buffer = buffer;

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r3549 - trunk/payloads/libpayload/include
by svn＠coreboot.org 29 Aug '08

29 Aug '08

Author: jcrouse Date: 2008-08-29 01:10:55 +0200 (Fri, 29 Aug 2008) New Revision: 3549 Modified: trunk/payloads/libpayload/include/libpayload.h Log: [PATCH]: libpayload: Document include/libpayload.h No code changes. Signed-off-by: Jordan Crouse <jordan.crouse(a)amd.com> Acked-by: Jordan Crouse <jordan.crouse(a)amd.com> Modified: trunk/payloads/libpayload/include/libpayload.h =================================================================== --- trunk/payloads/libpayload/include/libpayload.h 2008-08-28 23:10:25 UTC (rev 3548) +++ trunk/payloads/libpayload/include/libpayload.h 2008-08-28 23:10:55 UTC (rev 3549) @@ -76,30 +76,33 @@ __attribute__((__used__)) \ __attribute__((section(".note.pinfo"),unused)) = #key "=" value -/* Some NVRAM byte definitions */ -#define NVRAM_RTC_SECONDS 0 -#define NVRAM_RTC_MINUTES 2 -#define NVRAM_RTC_HOURS 4 -#define NVRAM_RTC_DAY 7 -#define NVRAM_RTC_MONTH 8 -#define NVRAM_RTC_YEAR 9 -#define NVRAM_RTC_FREQ_SELECT 10 -#define NVRAM_RTC_UIP 0x80 - /** * @defgroup nvram NVRAM and RTC functions * @{ */ + +#define NVRAM_RTC_SECONDS 0 /**< RTC Seconds offset in CMOS */ +#define NVRAM_RTC_MINUTES 2 /**< RTC Minutes offset in CMOS */ +#define NVRAM_RTC_HOURS 4 /**< RTC Hours offset in CMOS */ +#define NVRAM_RTC_DAY 7 /**< RTC Days offset in CMOS */ +#define NVRAM_RTC_MONTH 8 /**< RTC Month offset in CMOS */ +#define NVRAM_RTC_YEAR 9 /**< RTC Year offset in CMOS */ +#define NVRAM_RTC_FREQ_SELECT 10 /**< RTC Update Status Register */ +#define NVRAM_RTC_UIP 0x80 + +/** @struct tm + * \brief Broken down time structure + */ struct tm { - int tm_sec; - int tm_min; - int tm_hour; - int tm_mday; - int tm_mon; - int tm_year; - int tm_wday; - int tm_yday; - int tm_isdst; + int tm_sec; /**< Number of seconds after the minute */ + int tm_min; /**< Number of minutes after the hour */ + int tm_hour; /**< Number of hours past midnight */ + int tm_mday; /**< The day of the month */ + int tm_mon; /**< The month of the year */ + int tm_year; /**< The number of years since 1900 */ + int tm_wday; /**< The day of the week */ + int tm_yday; /**< The number of days since January 1 */ + int tm_isdst; /**< A flag indicating daylight savings time */ }; u8 nvram_read(u8 addr); @@ -312,9 +315,14 @@ * @defgroup time Time Functions * @{ */ + +/** @struct timeval + * @brief System time structure + */ + struct timeval { - time_t tv_sec; - suseconds_t tv_usec; + time_t tv_sec; /**< Seconds */ + suseconds_t tv_usec; /**< Microseconds */ }; int gettimeofday(struct timeval *tv, void *tz); @@ -324,36 +332,50 @@ * @defgroup lar LAR Functions * @{ */ + +/** @struct LAR + * @brief LAR File Header + */ struct LAR { - void * start; - int cindex; - int count; - int alloc; - int eof; - void **headers; + void * start; /**< Location of the LAR in memory */ + int cindex; /**< Next file to return in readlar() */ + int count; /**< Number of entries in the header cache */ + int alloc; /**< Number of slots in the header cache */ + int eof; /**< Last entry in the header cache */ + void **headers; /**< Pointer to the header cache */ }; +/** @struct larent + * @brief A structure representing the next LAR entry + */ struct larent { - u8 name[LAR_MAX_PATHLEN]; + u8 name[LAR_MAX_PATHLEN]; /**< The name of the next LAR entry */ }; +/** @struct larstat + * @brief A structure containing information about a LAR file + */ struct larstat { - u32 len; - u32 reallen; - u32 checksum; - u32 compchecksum; - u32 offset; - u32 compression; - u64 entry; - u64 loadaddress; + u32 len; /**< Length of the file in the LAR */ + u32 reallen; /**< Length of the uncompressed file */ + u32 checksum; /**< Checksum of the uncompressed file */ + u32 compchecksum; /**< Checksum of the compressed file in the LAR */ + u32 offset; /**< Offset of the file in the LAR */ + u32 compression; /**< Compression type of the file */ + u64 entry; /**< Entry point of the file for executables */ + u64 loadaddress; /**< Address in memory to put the uncompressed file */ }; +/** @struct LFILE + * @brief A structure representing a LAR file + */ + struct LFILE { - struct LAR *lar; - struct lar_header *header; - u32 size; - void *start; - u32 offset; + struct LAR *lar; /**< Pointer to the LAR struct */ + struct lar_header *header; /**< Pointer to the header struct */ + u32 size; /**< Size of the file */ + void *start; /**< Start of the file in memory */ + u32 offset; /**< Offset of the file in the LAR */ }; struct LAR *openlar(void *addr); @@ -366,9 +388,9 @@ struct LFILE * lfopen(struct LAR *lar, const char *filename); int lfread(void *ptr, size_t size, size_t nmemb, struct LFILE *stream); -#define SEEK_SET 0 -#define SEEK_CUR 1 -#define SEEK_END 2 +#define SEEK_SET 0 /**@def The seek offset is absolute */ +#define SEEK_CUR 1 /**@def The seek offset is against the current position */ +#define SEEK_END 2 /**@def The see offset is against the end of the file */ int lfseek(struct LFILE *stream, long offset, int whence); int lfclose(struct LFILE *file);

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r3548 - trunk/payloads/libpayload
by svn＠coreboot.org 29 Aug '08

29 Aug '08

Author: jcrouse Date: 2008-08-29 01:10:25 +0200 (Fri, 29 Aug 2008) New Revision: 3548 Modified: trunk/payloads/libpayload/Doxyfile Log: [PATCH]: Libpayload: Remove static variables from the doxygen output No code changes. Signed-off-by: Jordan Crouse <jordan.crouse(a)amd.com> Acked-by: Jordan Crouse <jordan.crouse(a)amd.com> Modified: trunk/payloads/libpayload/Doxyfile =================================================================== --- trunk/payloads/libpayload/Doxyfile 2008-08-28 18:23:58 UTC (rev 3547) +++ trunk/payloads/libpayload/Doxyfile 2008-08-28 23:10:25 UTC (rev 3548) @@ -287,7 +287,7 @@ # If the EXTRACT_STATIC tag is set to YES all static members of a file # will be included in the documentation. -EXTRACT_STATIC = YES +EXTRACT_STATIC = NO # If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) # defined locally in source files will be included in the documentation.

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coreboot August 2008