coreboot October 2005

coreboot@coreboot.org

34 participants
58 discussions

[LinuxBIOS] Proposed change to hypertransport.c for better error handling
by San Mehat 24 Oct '05

24 Oct '05

Hey all, It appears that under certain situations / hardware, HT can come up with the LinkFail and CrcError bits set on certain devices, even though the bus isn't *currently* in an error state. This causes 'hypertransport_scan_chain()' to stop traversing down a chain. I've made the following patch which knocks down the error state and re-reads to identify if the error is transient or not (It also reports the error rather than silently aborts the chain scan which caused me about 6 hours of hunting to find): *****BEGIN CUT***** Index: hypertransport.c =================================================================== --- hypertransport.c (revision 2064) +++ hypertransport.c (working copy) @@ -345,12 +345,25 @@ /* Wait until the link initialization is complete */ do { ctrl = pci_read_config16(prev.dev, prev.pos + prev.ctrl_off); - /* Is this the end of the hypertransport chain? - * Has the link failed? - * If so further scanning is pointless. - */ - if (ctrl & ((1 << 6) | (1 << 4))) { - goto end_of_chain; + + if (ctrl & (1 << 6)) + goto end_of_chain; // End of chain + + if (ctrl & ((1 << 4) | (1 << 8))) { + /* + * Either the link has failed, or we have + * a CRC error. + * Sometimes this can happen due to link + * retrain, so lets knock it down and see + * if its transient + */ + ctrl |= ((1 << 6) | (1 <<8)); // Link fail + Crc + pci_write_config16(prev.dev, prev.pos + prev.ctrl_off, ctrl); + ctrl = pci_read_config16(prev.dev, prev.pos + prev.ctrl_off); + if (ctrl & ((1 << 4) | (1 << 8))) { + printk_alert("Detected error on Hypertransport Link\n"); + goto end_of_chain; + } } } while((ctrl & (1 << 5)) == 0); ****END CUT*****

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RE: [LinuxBIOS] Mainboard MSI-6330
by Lu, Yinghai 21 Oct '05

21 Oct '05

Need someone add via SB support.... YH -----Original Message----- From: linuxbios-bounces(a)openbios.org [mailto:linuxbios-bounces@openbios.org] On Behalf Of 2481-287 Sent: Monday, December 26, 2005 3:54 PM To: linuxbios(a)openbios.org Subject: [LinuxBIOS] Mainboard MSI-6330 Hello, My questions are attached Thank You Stephan

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[LinuxBIOS] Re: [linuxbios-checkins] r2065 - trunk/LinuxBIOSv2/src/stream/fs
by ebiederman＠lnxi.com 21 Oct '05

21 Oct '05

svn(a)openbios.org writes: > Author: gwatson > Date: 2005-10-21 02:52:52 +0200 (Fri, 21 Oct 2005) > New Revision: 2065 This commit is broken. We are never going to be able to set ARCH to the character constant 'i386'. The basic sentiment sane but not the implementation. Eric > Modified: > trunk/LinuxBIOSv2/src/stream/fs/ext2fs.c > trunk/LinuxBIOSv2/src/stream/fs/fat.c > Log: > Some compilation issue fix for PPC970 port > > Modified: trunk/LinuxBIOSv2/src/stream/fs/ext2fs.c > =================================================================== > --- trunk/LinuxBIOSv2/src/stream/fs/ext2fs.c 2005-10-20 01:44:21 UTC (rev 2064) > +++ trunk/LinuxBIOSv2/src/stream/fs/ext2fs.c 2005-10-21 00:52:52 UTC (rev 2065) > @@ -239,7 +239,7 @@ > * ffz = Find First Zero in word. Undefined if no zero exists, > * so code should check against ~0UL first.. > */ > -#ifndef PPC > +#if ARCH == 'i386' > static __inline__ unsigned long > ffz (unsigned long word) > { > > Modified: trunk/LinuxBIOSv2/src/stream/fs/fat.c > =================================================================== > --- trunk/LinuxBIOSv2/src/stream/fs/fat.c 2005-10-20 01:44:21 UTC (rev 2064) > +++ trunk/LinuxBIOSv2/src/stream/fs/fat.c 2005-10-21 00:52:52 UTC (rev 2065) > @@ -54,7 +54,7 @@ > > #define FAT_CACHE_SIZE 2048 > > -#ifndef PPC > +#if ARCH == 'i386' > static __inline__ unsigned long > log2 (unsigned long word) > { > > > -- > To unsubscribe send an email to > linuxbios-checkins+unsubscribe(a)openbios.org

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RE: [LinuxBIOS] Tyan S2865 LinuxBIOS
by Lu, Yinghai 20 Oct '05

20 Oct '05

I have ported the s2865 support at Tyan. So you can ask tyan to release that code to public tree. They need to remove some NDA info.... YH -----Original Message----- From: linuxbios-bounces(a)openbios.org [mailto:linuxbios-bounces@openbios.org] On Behalf Of Jeremy Jackson Sent: Thursday, October 20, 2005 7:24 AM To: linuxbios(a)openbios.org Subject: [LinuxBIOS] Tyan S2865 LinuxBIOS Hi, I inquired about this with Charlie at Tyan, but I haven't heard anything and it's been over a month; maybe someone here knows about the status of LinuxBIOS for the S2865? (ck804 based) Regards, Jeremy -- Jeremy Jackson Coplanar Networks W:(519)489-4903 C:(519)897-1516 http://www.coplanar.net -- LinuxBIOS mailing list LinuxBIOS(a)openbios.org http://www.openbios.org/mailman/listinfo/linuxbios

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[LinuxBIOS] Tyan S2865 LinuxBIOS
by Jeremy Jackson 20 Oct '05

20 Oct '05

Hi, I inquired about this with Charlie at Tyan, but I haven't heard anything and it's been over a month; maybe someone here knows about the status of LinuxBIOS for the S2865? (ck804 based) Regards, Jeremy -- Jeremy Jackson Coplanar Networks W:(519)489-4903 C:(519)897-1516 http://www.coplanar.net

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[LinuxBIOS] Via Epia-m and VGA Bios emulation
by Nick Barker 19 Oct '05

19 Oct '05

I now have some more information on running the VGA bios through the emulator on the epia-m I have implemented both real mode and emulated VGA initialisation. The real mode brings up the vga properly, whilst the emulation does not. The emulated version runs to completion and also returns with Carry Flag set which I'm assuming means that it has given up trying. Using TSC, a performance counter set to count instructions, and a simple instruction counter in the main loop of the emulator, I have come up with the following statistics for the vga initialisation sequence: Real Mode --------- CPU Clocks = 691,530,971 (600Mhz processor = 1.1 seconds approx) Instructions executed = 16,481,875 Interestingly this gives a clocks/instruction ratio of about 43, which we can put down to intensive I/O and which must stall the processor by many clock cycles per I/O. Emulation mode -------------- CPU Clocks = 4,618,464,706 (= 7.7 seconds approx) Instructions executed = 1,946,308,181 Emulated instructions = 13,756,300 This gives us 2 ratios of interest: Average clocks per instruction = 2.37 (much less than real mode since the emulation is much more memory intensive) Average instructions per emulated instruction = 141 The emulator is also running nearly 3 million fewer instructions, which could be down to it doing fewer loop iterations whilst waiting for things to come ready, or could also be attributed to the bios giving up early. I am now working on the hypothesis that the emulator has to be faster if it is going to work at all for the epia-m, which means fewer instructions per emulated instruction. I have a few ideas which I intend investigating and trying out: 1) embed/inline the memory read/write and io functions directly where they are used rather than having trivial subroutines accessed via arrays of function pointers. I believe that this processor is easily stalled by jumps to subroutines, and so inlining these should help. 2) hard code the emulator memory base at 0, so that this addition is avoided on every memory access (since linuxbios always sets it at 0 anyway) 3) Implement the primitive operations in assembler - as has been done in prim_asm.h for the Watcom compiler, but this time for gcc 4) Investigate the emulated repeat move string operation to see if this is done efficiently by the emulator etc.... Nick Barker

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RE: [LinuxBIOS] K8 CAR issue
by Lu, Yinghai 19 Oct '05

19 Oct '05

Any reason for you to use HDT? Can you disable the XIP and have a try? YH ________________________________ From: linuxbios-bounces(a)openbios.org [mailto:linuxbios-bounces@openbios.org] On Behalf Of San Mehat Sent: Tuesday, October 18, 2005 4:59 PM To: LinuxBIOS Subject: [LinuxBIOS] K8 CAR issue Greetings, I've been experimenting with getting the Cache as Ram stuff working with my experiments, and have run into a puzzling issue relating to XIP. In amd/cache_as_ram.inc, as soon as the writes to MSR 203 completes, my system crashes. Using my HDT, it looks like the entire memory image gets all buggered up as well. The offending segment of code appears to be: 0008:FFFF7312 B902020000 MOV ECX,00000202 0008:FFFF7317 31D2 XOR EDX,EDX 0008:FFFF7319 B80600FEFF MOV EAX,fffe0006 0008:FFFF731E 0F30 WRMSR 0008:FFFF7320 B903020000 MOV ECX,00000203 0008:FFFF7325 BA0F000000 MOV EDX,0000000f 0008:FFFF732A B80008FEFF MOV EAX,fffe0800 0008:FFFF732F 0F30 WRMSR <--------------- POW... In my Config.lb, XIP options are: default XIP_ROM_SIZE=65536 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) Any ideas YH? ;) thanks -san

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[LinuxBIOS] Mainboard MSI-6330
by 2481-287 19 Oct '05

19 Oct '05

Hello, My questions are attached Thank You Stephan Hello, I want to change my BIOS from AWARD BIOS to LinuxBIOS I have a MSI MS6330 Mainboard with a AthlonXP1800+ CPU and and 3 PC133-3-3-3 SDRAMs (see also x1800ctb, which is a Output from ctbios) Here is my lspci -vvv: 0000:00:00.0 Host bridge: VIA Technologies, Inc. VT8363/8365 [KT133/KM133] (rev 03) Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 8 Region 0: Memory at d0000000 (32-bit, prefetchable) Capabilities: [a0] AGP version 2.0 Status: RQ=32 Iso- ArqSz=0 Cal=0 SBA+ ITACoh- GART64- HTrans- 64bit- FW- AGP3- Rate=x1,x2 Command: RQ=1 ArqSz=0 Cal=0 SBA- AGP- GART64- 64bit- FW- Rate=<none> Capabilities: [c0] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 0000:00:01.0 PCI bridge: VIA Technologies, Inc. VT8363/8365 [KT133/KM133 AGP] (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Bus: primary=00, secondary=01, subordinate=01, sec-latency=0 I/O behind bridge: 0000f000-00000fff Memory behind bridge: d4000000-d6ffffff Prefetchable memory behind bridge: d7000000-d7ffffff BridgeCtl: Parity- SERR- NoISA+ VGA+ MAbort- >Reset- FastB2B- Capabilities: [80] Power Management version 2 Flags: PMEClk- DSI- D1+ D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 0000:00:07.0 ISA bridge: VIA Technologies, Inc. VT82C686 [Apollo Super South] (rev 40) Subsystem: VIA Technologies, Inc. VT82C686/A PCI to ISA Bridge Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping+ SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Capabilities: [c0] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 0000:00:07.1 IDE interface: VIA Technologies, Inc. VT82C586A/B/VT82C686/A/B/VT823x/A/C PIPC Bus Master IDE (rev 06) (prog-if 8a [Master SecP PriP]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 32 Region 4: I/O ports at d000 [size=16] Capabilities: [c0] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 0000:00:07.4 Host bridge: VIA Technologies, Inc. VT82C686 [Apollo Super ACPI] (rev 40) Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Interrupt: pin ? routed to IRQ 9 Capabilities: [68] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 0000:00:07.5 Multimedia audio controller: VIA Technologies, Inc. VT82C686 AC97 Audio Controller (rev 50) Subsystem: Micro-Star International Co., Ltd. MS-6330 Onboard Audio Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Interrupt: pin C routed to IRQ 5 Region 0: I/O ports at dc00 Region 1: I/O ports at e000 [size=4] Region 2: I/O ports at e400 [size=4] Capabilities: [c0] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 0000:00:08.0 Ethernet controller: Intel Corp. 82557/8/9 [Ethernet Pro 100] (rev 0c) Subsystem: Intel Corp. EtherExpress PRO/100 S Desktop Adapter Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 32 (2000ns min, 14000ns max), cache line size 08 Interrupt: pin A routed to IRQ 11 Region 0: Memory at d9020000 (32-bit, non-prefetchable) Region 1: I/O ports at e800 [size=64] Region 2: Memory at d9000000 (32-bit, non-prefetchable) [size=128K] Capabilities: [dc] Power Management version 2 Flags: PMEClk- DSI+ D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=2 PME- 0000:00:0a.0 FireWire (IEEE 1394): VIA Technologies, Inc. IEEE 1394 Host Controller (rev 43) (prog-if 10 [OHCI]) Subsystem: VIA Technologies, Inc. IEEE 1394 Host Controller Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 32 (8000ns max), cache line size 08 Interrupt: pin A routed to IRQ 5 Region 0: Memory at d9021000 (32-bit, non-prefetchable) Region 1: I/O ports at ec00 [size=128] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1- D2+ AuxCurrent=0mA PME(D0-,D1-,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 0000:00:0d.0 USB Controller: ALi Corporation USB 1.1 Controller (rev 03) (prog-if 10 [OHCI]) Subsystem: ALi Corporation USB 1.1 Controller Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 32 (20000ns max), cache line size 08 Interrupt: pin B routed to IRQ 5 Region 0: Memory at d9022000 (32-bit, non-prefetchable) Capabilities: [60] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1+,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME+ 0000:00:0d.1 USB Controller: ALi Corporation USB 1.1 Controller (rev 03) (prog-if 10 [OHCI]) Subsystem: ALi Corporation USB 1.1 Controller Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 32 (20000ns max), cache line size 08 Interrupt: pin C routed to IRQ 10 Region 0: Memory at d9023000 (32-bit, non-prefetchable) Capabilities: [60] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1+,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 0000:00:0d.2 USB Controller: ALi Corporation USB 1.1 Controller (rev 03) (prog-if 10 [OHCI]) Subsystem: ALi Corporation USB 1.1 Controller Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 32 (20000ns max), cache line size 08 Interrupt: pin D routed to IRQ 11 Region 0: Memory at d9024000 (32-bit, non-prefetchable) Capabilities: [60] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1+,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 0000:00:0d.3 USB Controller: ALi Corporation USB 2.0 Controller (rev 01) (prog-if 20 [EHCI]) Subsystem: ALi Corporation: Unknown device 5272 Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 32 (20000ns max), cache line size 10 Interrupt: pin A routed to IRQ 3 Region 0: Memory at d9025000 (32-bit, non-prefetchable) Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [58] #0a [2090] 0000:01:00.0 VGA compatible controller: Matrox Graphics, Inc. MGA G200 AGP (rev 03) (prog-if 00 [VGA]) Subsystem: Matrox Graphics, Inc. Millennium G200 AGP Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 64 (4000ns min, 8000ns max), cache line size 08 Interrupt: pin A routed to IRQ 10 Region 0: Memory at d7000000 (32-bit, prefetchable) Region 1: Memory at d4000000 (32-bit, non-prefetchable) [size=16K] Region 2: Memory at d5000000 (32-bit, non-prefetchable) [size=8M] Capabilities: [dc] Power Management version 1 Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [f0] AGP version 1.0 Status: RQ=32 Iso- ArqSz=0 Cal=0 SBA+ ITACoh- GART64- HTrans- 64bit- FW- AGP3- Rate=x1,x2 Command: RQ=32 ArqSz=0 Cal=0 SBA+ AGP+ GART64- 64bit- FW- Rate=x2 I think my SuperIO Chip is integrated in the Southbridge. My BIOS flash device is a EON EN29F002NT-70J(0112C-B861C) The boards URL is http://www.msi.com.tw/program/products/mainboard/mbd/pro_mbd_detail.php?UID… Could you please tell me, wheter there is any chance to run LinuxBIOS on this board ? Thank you very much ! Stephan

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[LinuxBIOS] Epia-M compilation fails
by Bu Bacoo 19 Oct '05

19 Oct '05

Hello After preparing epia-m build ( ./buildtarget via/epia-m/ ), I move to via/epia-m/epia-m and run 'make'. I get this error during linkage: .... cut..... gcc -m32 -nostdlib -r -o linuxbios_ram.o c_start.o vt8235_lpc.o uart8250_console.o vt8235.o vt8235_ide.o mainboard.o vt8235_usb.o vt8235_nic.o model_centaur_init.o linuxbios.a/usr/lib/gcc-lib/i686-pc-linux-gnu/3.3.6/libgcc.a gcc -m32 -nostdlib -nostartfiles -static -o linuxbios_ram -T /home/bubak/epia/bios/LinuxBIOSv2/src/config/linuxbios_ram.ld linuxbios_ram.o linuxbios_ram.o(.text+0x8bc): In function `vga_fixup': : undefined reference to `setup_realmode_idt' linuxbios_ram.o(.text+0x8cd): In function `vga_fixup': : undefined reference to `do_vgabios' linuxbios_ram.o(.text+0x8e0): In function `vga_fixup': : undefined reference to `vga_enable_console' collect2: ld returned 1 exit status make[1]: *** [linuxbios_ram] Error 1 make[1]: Leaving directory `/home/bubak/epia/bios/LinuxBIOSv2/targets/via/epia-m/epia-m/normal' make: *** [normal/linuxbios.rom] Error 1 Any ideas please? Thanks, Bu

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[LinuxBIOS] K8 CAR issue
by San Mehat 18 Oct '05

18 Oct '05

Greetings, I've been experimenting with getting the Cache as Ram stuff working with my experiments, and have run into a puzzling issue relating to XIP. In amd/cache_as_ram.inc, as soon as the writes to MSR 203 completes, my system crashes. Using my HDT, it looks like the entire memory image gets all buggered up as well. The offending segment of code appears to be: 0008:FFFF7312 B902020000 MOV ECX,00000202 0008:FFFF7317 31D2 XOR EDX,EDX 0008:FFFF7319 B80600FEFF MOV EAX,fffe0006 0008:FFFF731E 0F30 WRMSR 0008:FFFF7320 B903020000 MOV ECX,00000203 0008:FFFF7325 BA0F000000 MOV EDX,0000000f 0008:FFFF732A B80008FEFF MOV EAX,fffe0800 0008:FFFF732F 0F30 WRMSR <--------------- POW... In my Config.lb <http://Config.lb>, XIP options are: default XIP_ROM_SIZE=65536 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) Any ideas YH? ;) thanks -san

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coreboot October 2005