Change in coreboot[master]: Add support for OCP platform TiogaPass

[Jonathan Zhang (Code Review)]

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38549 )

Change subject: Add support for OCP platform TiogaPass
......................................................................

Add support for OCP platform TiogaPass

OCP platform Tiogapass is a 2 socket server platform based on
Intel Skylake-SP SOC. The chipset includes Lewisburg PCH.

Following ACPI tables are added:
DSDT/SSDT, MADT, FACP, FACS, HPET, MCFG, SLIT, SRAT, DMAR

This patchset was tested on a board. It booted with Linux kernel
4.16.0; lscpu command shows all 72 cpus; ifconfig command shows
networking is up from Mellanox ConnectX-4 PCIe NIC card.

Known issues:
1. MP init does not work reliably, this causes reboot stability,
eg. some reboots does not boot up successfully.
2. c6 state is not supported.
3. "lspci -vvv" causes segmentation fault.

Signed-off-by: Jonathan Zhang 
Signed-off-by: Reddy Chagam 
Change-Id: I29868f03037d1887b90dfb19d15aee83c456edce
---
A src/mainboard/ocp/Kconfig
A src/mainboard/ocp/Kconfig.name
A src/mainboard/ocp/tiogapass/Kconfig
A src/mainboard/ocp/tiogapass/Kconfig.name
A src/mainboard/ocp/tiogapass/Makefile.inc
A src/mainboard/ocp/tiogapass/acpi/platform.asl
A src/mainboard/ocp/tiogapass/acpi_tables.c
A src/mainboard/ocp/tiogapass/board_info.txt
A src/mainboard/ocp/tiogapass/boardid.c
A src/mainboard/ocp/tiogapass/devicetree.cb
A src/mainboard/ocp/tiogapass/dsdt.asl
A src/mainboard/ocp/tiogapass/emmc.h
A src/mainboard/ocp/tiogapass/fadt.c
A src/mainboard/ocp/tiogapass/ramstage.c
A src/mainboard/ocp/tiogapass/romstage.c
A src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h
A src/mainboard/ocp/tiogapass/skxsp_tp_iio.h
A src/mainboard/ocp/tiogapass/tiogapass_boardid.h
A src/mainboard/ocp/tiogapass/vboot-ro.fmd
19 files changed, 1,321 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/38549/1

diff --git a/src/mainboard/ocp/Kconfig b/src/mainboard/ocp/Kconfig
new file mode 100644
index 0000000..b748129
--- /dev/null
+++ b/src/mainboard/ocp/Kconfig
@@ -0,0 +1,16 @@
+if VENDOR_OCP
+
+choice
+	prompt "Mainboard model"
+
+source "src/mainboard/ocp/*/Kconfig.name"
+
+endchoice
+
+source "src/mainboard/ocp/*/Kconfig"
+
+config MAINBOARD_VENDOR
+	string
+	default "Open Compute Project"
+
+endif # VENDOR_OCP
diff --git a/src/mainboard/ocp/Kconfig.name b/src/mainboard/ocp/Kconfig.name
new file mode 100644
index 0000000..f5d8d0a
--- /dev/null
+++ b/src/mainboard/ocp/Kconfig.name
@@ -0,0 +1,2 @@
+config VENDOR_OCP
+	bool "Open Compute Project"
diff --git a/src/mainboard/ocp/tiogapass/Kconfig b/src/mainboard/ocp/tiogapass/Kconfig
new file mode 100644
index 0000000..b2517b0
--- /dev/null
+++ b/src/mainboard/ocp/tiogapass/Kconfig
@@ -0,0 +1,53 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2019 - 2020 Intel Corporation.
+## Copyright (C) 2019 - 2020 Facebook Inc
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+if BOARD_OCP_TIOGAPASS
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_32768
+  select HAVE_ACPI_TABLES
+	select SOC_INTEL_SKYLAKE_SP
+	select SKYLAKE_SP_SOC_PCH_H
+	select MAINBOARD_USES_FSP2_0
+	select FSP_CAR
+
+config MAINBOARD_DIR
+    string
+    default "ocp/tiogapass"
+
+config MAINBOARD_PART_NUMBER
+    string
+    default "Tioga Pass"
+
+config MAINBOARD_FAMILY
+    string
+    default "OCP Tioga Pass"
+
+config MAINBOARD_VENDOR
+	string
+	default "OCP"
+
+config MAX_SOCKET
+  int
+  default 2
+
+config FLIGHT_PLAN_TIMEOUT_US
+  int
+  default 10000000
+
+endif # BOARD_OCP_TIOGAPASS
diff --git a/src/mainboard/ocp/tiogapass/Kconfig.name b/src/mainboard/ocp/tiogapass/Kconfig.name
new file mode 100644
index 0000000..0c57fd3
--- /dev/null
+++ b/src/mainboard/ocp/tiogapass/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_OCP_TIOGAPASS
+	bool "Tioga Pass"
diff --git a/src/mainboard/ocp/tiogapass/Makefile.inc b/src/mainboard/ocp/tiogapass/Makefile.inc
new file mode 100644
index 0000000..b09b35e
--- /dev/null
+++ b/src/mainboard/ocp/tiogapass/Makefile.inc
@@ -0,0 +1,26 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2019 - 2020 Intel Corporation.
+## Copyright (C) 2019 - 2020 Facebook Inc
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+romstage-y += boardid.c
+
+ramstage-y += ramstage.c
+ramstage-y += boardid.c
+ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c
+
+CPPFLAGS_common += -Isrc/mainboard/$(MAINBOARDDIR)/
+CPPFLAGS_common += -I$(src)/soc/intel/skylake_sp/include
+CPPFLAGS_common += -I$(CONFIG_FSP_HEADER_PATH)
diff --git a/src/mainboard/ocp/tiogapass/acpi/platform.asl b/src/mainboard/ocp/tiogapass/acpi/platform.asl
new file mode 100644
index 0000000..5bbe4ae
--- /dev/null
+++ b/src/mainboard/ocp/tiogapass/acpi/platform.asl
@@ -0,0 +1,382 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 - 2020 Intel Corporation.
+ * Copyright (C) 2019 - 2020 Facebook Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* Enable ACPI _SWS methods */
+#include <soc/intel/common/acpi/acpi_wake_source.asl>
+
+Name (_S0, Package (0x04) // mandatory system state
+{
+    0x00, 0x00, 0x00, 0x00
+})
+
+Name (_S5, Package (0x04)  // mandatory system state
+{
+    0x07, 0x00, 0x00, 0x00
+})
+
+/* The APM port can be used for generating software SMIs */
+OperationRegion (APMP, SystemIO, 0xb2, 2)
+Field (APMP, ByteAcc, NoLock, Preserve)
+{
+	APMC, 8,	// APM command
+	APMS, 8		// APM status
+}
+
+/* Port 80 POST */
+OperationRegion (DBG0, SystemIO, 0x80, 0x02)
+Field (DBG0, ByteAcc, Lock, Preserve)
+{
+	IO80, 8,
+  IO81, 8
+}
+
+/* IO-Trap at 0x800.
+ * This is the ACPI->SMI communication interface.
+ */
+OperationRegion (IO_T, SystemIO, 0x800, 0x10)
+Field (IO_T, ByteAcc, NoLock, Preserve)
+{
+	Offset (0x8),
+	TRP0, 8		/* IO-Trap at 0x808 */
+}
+
+OperationRegion (PSYS, SystemMemory, 0x6D081000, 0x0400)
+Field (PSYS, ByteAcc, NoLock, Preserve)
+{
+	PLAT,   32,  // Platform ID
+
+	// IOAPIC
+	APC0,   1,   // PCH IOAPIC Enable
+	AP00,   1,   // PC00 IOAPIC Enable
+	AP01,   1,   // PC01 IOAPIC Enable
+	AP02,   1,   // PC02 IOAPIC Enable
+	AP03,   1,   // PC03 IOAPIC Enable
+	AP04,   1,   // PC04 IOAPIC Enable
+	AP05,   1,   // PC05 IOAPIC Enable
+	AP06,   1,   // PC06 IOAPIC Enable
+	AP07,   1,   // PC07 IOAPIC Enable
+	AP08,   1,   // PC08 IOAPIC Enable
+	AP09,   1,   // PC09 IOAPIC Enable
+	AP10,   1,   // PC10 IOAPIC Enable
+	AP11,   1,   // PC11 IOAPIC Enable
+	AP12,   1,   // PC12 IOAPIC Enable
+	AP13,   1,   // PC13 IOAPIC Enable
+	AP14,   1,   // PC14 IOAPIC Enable
+	AP15,   1,   // PC15 IOAPIC Enable
+	AP16,   1,   // PC16 IOAPIC Enable
+	AP17,   1,   // PC17 IOAPIC Enable
+	AP18,   1,   // PC18 IOAPIC Enable
+	AP19,   1,   // PC19 IOAPIC Enable
+	AP20,   1,   // PC20 IOAPIC Enable
+	AP21,   1,   // PC21 IOAPIC Enable
+	AP22,   1,   // PC22 IOAPIC Enable
+	AP23,   1,   // PC23 IOAPIC Enable
+	RESA,   7,
+	SKOV,   1,   // Override Socket APIC Id
+	RES0,   7,
+
+	// Power Management
+	TPME,   1,
+	CSEN,   1,
+	C3EN,   1,
+	C6EN,   1,
+	C7EN,   1,
+	MWOS,   1,
+	PSEN,   1,
+	EMCA,   1,
+	HWAL,   2,
+	KPRS,   1,
+	MPRS,   1,
+	TSEN,   1,
+	FGTS,   1,
+	OSCX,   1,
+	RESX,   1,
+
+	// RAS
+	CPHP,   8,
+	IIOP,   8,
+	IIOH,   64,
+	PRBM,   32,
+	P0ID,   32,
+	P1ID,   32,
+	P2ID,   32,
+	P3ID,   32,
+	P4ID,   32,
+	P5ID,   32,
+	P6ID,   32,
+	P7ID,   32,
+	P0BM,   64,
+	P1BM,   64,
+	P2BM,   64,
+	P3BM,   64,
+	P4BM,   64,
+	P5BM,   64,
+	P6BM,   64,
+	P7BM,   64,
+	MEBM,   16,
+	MEBC,   16,
+	CFMM,   32,
+	TSSY,   32,  // TODO: This is TSSZ in system booted from production FW
+	M0BS,   64,
+	M1BS,   64,
+	M2BS,   64,
+	M3BS,   64,
+	M4BS,   64,
+	M5BS,   64,
+	M6BS,   64,
+	M7BS,   64,
+	M0RN,   64,
+	M1RN,   64,
+	M2RN,   64,
+	M3RN,   64,
+	M4RN,   64,
+	M5RN,   64,
+	M6RN,   64,
+	M7RN,   64,
+	SMI0,   32,
+	SMI1,   32,
+	SMI2,   32,
+	SMI3,   32,
+	SCI0,   32,
+	SCI1,   32,
+	SCI2,   32,
+	SCI3,   32,
+	MADD,   64,
+	CUU0,   128,
+	CUU1,   128,
+	CUU2,   128,
+	CUU3,   128,
+	CUU4,   128,
+	CUU5,   128,
+	CUU6,   128,
+	CUU7,   128,
+	CPSP,   8,
+	ME00,   128,
+	ME01,   128,
+	ME10,   128,
+	ME11,   128,
+	ME20,   128,
+	ME21,   128,
+	ME30,   128,
+	ME31,   128,
+	ME40,   128,
+	ME41,   128,
+	ME50,   128,
+	ME51,   128,
+	ME60,   128,
+	ME61,   128,
+	ME70,   128,
+	ME71,   128,
+	MESP,   16,
+	LDIR,   64,
+	PRID,   32,
+	AHPE,   8,
+
+	// VTD
+	DHRD,   192,
+	ATSR,   192,
+	RHSA,   192,
+
+	// SR-IOV
+	WSIC,   8,
+	WSIS,   16,
+	WSIB,   8,
+	WSID,   8,
+	WSIF,   8,
+	WSTS,   8,
+	WHEA,   8,
+
+	// BIOS Guard
+	BGMA,   64,
+	BGMS,   8,
+	BGIO,   16,
+	BGIL,   8,
+	CNBS,   8,
+
+	// USB3
+	XHMD,   8,
+	SBV1,   8,
+	SBV2,   8,
+
+	// HWPM
+	HWEN,   2,
+	ACEN,   1,
+	HWPI,   1,
+	RES1,   4,
+
+	// IIO
+	BB00,   8,
+	BB01,   8,
+	BB02,   8,
+	BB03,   8,
+	BB04,   8,
+	BB05,   8,
+	BB06,   8,
+	BB07,   8,
+	BB08,   8,
+	BB09,   8,
+	BB10,   8,
+	BB11,   8,
+	BB12,   8,
+	BB13,   8,
+	BB14,   8,
+	BB15,   8,
+	BB16,   8,
+	BB17,   8,
+	BB18,   8,
+	BB19,   8,
+	BB20,   8,
+	BB21,   8,
+	BB22,   8,
+	BB23,   8,
+	BB24,   8,
+	BB25,   8,
+	BB26,   8,
+	BB27,   8,
+	BB28,   8,
+	BB29,   8,
+	BB30,   8,
+	BB31,   8,
+	BB32,   8,
+	BB33,   8,
+	BB34,   8,
+	BB35,   8,
+	BB36,   8,
+	BB37,   8,
+	BB38,   8,
+	BB39,   8,
+	BB40,   8,
+	BB41,   8,
+	BB42,   8,
+	BB43,   8,
+	BB44,   8,
+	BB45,   8,
+	BB46,   8,
+	BB47,   8,
+	SGEN,   8,
+	SG00,   8,
+	SG01,   8,
+	SG02,   8,
+	SG03,   8,
+	SG04,   8,
+	SG05,   8,
+	SG06,   8,
+	SG07,   8,
+
+	// Performance
+	CLOD,   8,
+
+	// XTU
+	XTUB,   32,
+	XTUS,   32,
+	XMBA,   32,
+	DDRF,   8,
+	RT3S,   8,
+	RTP0,   8,
+	RTP3,   8,
+
+	// FPGA
+	FBB0,   8,
+	FBB1,   8,
+	FBB2,   8,
+	FBB3,   8,
+	FBB4,   8,
+	FBB5,   8,
+	FBB6,   8,
+	FBB7,   8,
+	FBL0,   8,
+	FBL1,   8,
+	FBL2,   8,
+	FBL3,   8,
+	FBL4,   8,
+	FBL5,   8,
+	FBL6,   8,
+	FBL7,   8,
+	P0FB,   8,
+	P1FB,   8,
+	P2FB,   8,
+	P3FB,   8,
+	P4FB,   8,
+	P5FB,   8,
+	P6FB,   8,
+	P7FB,   8,
+	FMB0,   32,
+	FMB1,   32,
+	FMB2,   32,
+	FMB3,   32,
+	FMB4,   32,
+	FMB5,   32,
+	FMB6,   32,
+	FMB7,   32,
+	FML0,   32,
+	FML1,   32,
+	FML2,   32,
+	FML3,   32,
+	FML4,   32,
+	FML5,   32,
+	FML6,   32,
+	FML7,   32,
+	FKPB,   32,
+	FKB0,   8,
+	FKB1,   8,
+	FKB2,   8,
+	FKB3,   8,
+	FKB4,   8,
+	FKB5,   8,
+	FKB6,   8,
+	FKB7,   8
+}
+
+/* SMI I/O Trap */
+Method (TRAP, 1, Serialized)
+{
+	Store (Arg0, SMIF)	// SMI Function
+	Store (0, TRP0)		// Generate trap
+	Return (SMIF)		// Return value of SMI handler
+}
+
+/*
+ * The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC.
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local Apic/IOAPIC configuration.
+ */
+
+Method (_PIC, 1)
+{
+	/* Remember the OS' IRQ routing choice. */
+	Store (Arg0, PICM)
+}
+
+/*
+ * The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method (_PTS, 1)
+{
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method (_WAK, 1)
+{
+	Return (Package (){ 0, 0 })
+}
diff --git a/src/mainboard/ocp/tiogapass/acpi_tables.c b/src/mainboard/ocp/tiogapass/acpi_tables.c
new file mode 100644
index 0000000..93f659a
--- /dev/null
+++ b/src/mainboard/ocp/tiogapass/acpi_tables.c
@@ -0,0 +1,44 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ * Copyright (C) 2014 - 2020 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <types.h>
+#include <string.h>
+#include <arch/acpi.h>
+#include <arch/ioapic.h>
+#include <arch/acpigen.h>
+#include <arch/smp/mpspec.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <cpu/x86/msr.h>
+
+#include <intelblocks/acpi.h>
+#include <soc/acpi.h>
+#include <soc/nvs.h>
+
+extern const unsigned char AmlCode[];
+
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+	acpi_init_gnvs(gnvs);
+
+	/* Disable USB ports in S5 */
+	gnvs->s5u0 = 0;
+	gnvs->s5u1 = 0;
+
+	/* TPM Present */
+	gnvs->tpmp = 0;
+}
diff --git a/src/mainboard/ocp/tiogapass/board_info.txt b/src/mainboard/ocp/tiogapass/board_info.txt
new file mode 100644
index 0000000..e86f78f
--- /dev/null
+++ b/src/mainboard/ocp/tiogapass/board_info.txt
@@ -0,0 +1,5 @@
+Board name: TiogaPass
+Category: server
+ROM protocol: SPI
+ROM socketed: yes
+Release year: 2018
diff --git a/src/mainboard/ocp/tiogapass/boardid.c b/src/mainboard/ocp/tiogapass/boardid.c
new file mode 100644
index 0000000..a0454cb
--- /dev/null
+++ b/src/mainboard/ocp/tiogapass/boardid.c
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 - 2020 Intel Corporation.
+ * Copyright (C) 2019 - 2020 Facebook Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <console/console.h>
+
+#include "tiogapass_boardid.h"
+
+uint8_t board_id(void)
+{
+	int id = BoardIdTiogaPass;
+
+	printk(BIOS_SPEW, "Board ID: %#x.\n", id);
+
+	return id;
+}
diff --git a/src/mainboard/ocp/tiogapass/devicetree.cb b/src/mainboard/ocp/tiogapass/devicetree.cb
new file mode 100644
index 0000000..7409f55
--- /dev/null
+++ b/src/mainboard/ocp/tiogapass/devicetree.cb
@@ -0,0 +1,92 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2019 - 2020 Intel Corporation.
+## Copyright (C) 2019 - 2020 Facebook Inc
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+chip soc/intel/skylake_sp
+
+	register "pirqa_routing" = "PCH_IRQ11"
+	register "pirqb_routing" = "PCH_IRQ10"
+	register "pirqc_routing" = "PCH_IRQ11"
+	register "pirqd_routing" = "PCH_IRQ11"
+	register "pirqe_routing" = "PCH_IRQ11"
+	register "pirqf_routing" = "PCH_IRQ11"
+	register "pirqg_routing" = "PCH_IRQ11"
+	register "pirqh_routing" = "PCH_IRQ11"
+
+  # configure device interrupt routing
+  register "ir00_routing" = "0x3210" # IR00, Dev31
+  register "ir01_routing" = "0x3210" # IR01, Dev30
+  register "ir02_routing" = "0x3210" # IR02, Dev29
+  register "ir03_routing" = "0x3210" # IR03, Dev28
+  register "ir04_routing" = "0x3210" # IR04, Dev27
+
+  # configure interrupt polarity control
+  register "ipc0" = "0x00ff4000" # IPC0, PIRQA-H (IRQ16-23) should always be ActiveLow
+  register "ipc1" = "0x00000000" # IPC1
+  register "ipc2" = "0x00000000" # IPC2
+  register "ipc3" = "0x00000000" # IPC3
+
+	# configure MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT_CORES msrs
+	# FB production turbo_ratio_limit is 0x1f1f1f2022222325
+	register "turbo_ratio_limit" = "0x1b1b1b1d20222325"
+	# FB production turbo_ratio_limit_cores is 0x1c1812100c080402
+	register "turbo_ratio_limit_cores" = "0x1c1814100c080402"
+
+	# configure PSTATE_REQ_RATIO for MSR_IA32_PERF_CTRL
+	register "pstate_req_ratio" = "0xa"
+
+	# configure VTD
+  register "vtd_support" = "1"
+  register "coherency_support" = "1"
+  register "ats_support" = "1"
+
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+
+	device domain 0 on
+        device pci 00.0 on end # Host bridge
+				device pci 04.0 on end # Intel Corporation Sky Lake-E CBDMA Registers
+				device pci 04.1 on end # Intel Corporation Sky Lake-E CBDMA Registers
+				device pci 04.2 on end # Intel Corporation Sky Lake-E CBDMA Registers
+				device pci 04.3 on end # Intel Corporation Sky Lake-E CBDMA Registers
+				device pci 04.4 on end # Intel Corporation Sky Lake-E CBDMA Registers
+				device pci 04.5 on end # Intel Corporation Sky Lake-E CBDMA Registers
+				device pci 04.6 on end # Intel Corporation Sky Lake-E CBDMA Registers
+				device pci 04.7 on end # Intel Corporation Sky Lake-E CBDMA Registers
+				device pci 05.0 on end # Intel Corporation Sky Lake-E MM/Vt-d Configuration Registers
+				device pci 05.2 on end # Intel Corporation Device 2025
+				device pci 05.4 on end # Intel Corporation Device 2026
+				device pci 08.0 on end # Intel Corporation Sky Lake-E Ubox Registers
+				device pci 08.1 on end # Intel Corporation Sky Lake-E Ubox Registers
+				device pci 08.2 on end # Intel Corporation Sky Lake-E Ubox Registers
+				device pci 11.0 on end # Intel Corporation C620 Series Chipset Family MROM 0
+				device pci 11.1 on end # Intel Corporation C620 Series Chipset Family MROM 1
+				device pci 11.5 on end # Intel Corporation C620 Series Chipset Family SSATA Controller [AHCI mode]
+				device pci 14.0 on end # Intel Corporation C620 Series Chipset Family USB 3.0 xHCI Controller
+#			device pci 14.2 on end # Intel Corporation C620 Series Chipset Family Thermal Subsystem
+				device pci 16.0 on end # Intel Corporation C620 Series Chipset Family MEI Controller #1
+				device pci 16.1 on end # Intel Corporation C620 Series Chipset Family MEI Controller #2
+				device pci 16.4 on end # Intel Corporation C620 Series Chipset Family MEI Controller #3
+				device pci 17.0 on end # Intel Corporation C620 Series Chipset Family SATA Controller [AHCI mode]
+				device pci 1c.0 on end # PCI bridge: Intel Corporation C620 Series Chipset Family PCI Express Root Port #1
+				device pci 1c.4 on end # PCI bridge: Intel Corporation C620 Series Chipset Family PCI Express Root Port #5
+				device pci 1f.0 on end # Intel Corporation C621 Series Chipset LPC/eSPI Controller
+				device pci 1f.2 on end # Intel Corporation C620 Series Chipset Family Power Management Controller
+				device pci 1f.4 on end # Intel Corporation C620 Series Chipset Family SMBus
+				device pci 1f.5 on end # Intel Corporation C620 Series Chipset Family SPI Controller
+	end
+end
diff --git a/src/mainboard/ocp/tiogapass/dsdt.asl b/src/mainboard/ocp/tiogapass/dsdt.asl
new file mode 100644
index 0000000..bf36ab9
--- /dev/null
+++ b/src/mainboard/ocp/tiogapass/dsdt.asl
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 - 2020 Intel Corporation.
+ * Copyright (C) 2019 - 2020 Facebook Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+
+#include <arch/acpi.h>
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x02,		// DSDT revision: ACPI v2.0 and up
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725	// OEM revision
+)
+{
+	// platform ACPI tables
+	#include "acpi/platform.asl"
+
+	// global NVS and variables
+	#include <soc/intel/skylake_sp/acpi/globalnvs.asl>
+
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	// Xeon Skylake SP ACPI tables
+	Scope (_SB) {
+		#include <soc/intel/skylake_sp/acpi/uncore.asl>
+	}
+}
diff --git a/src/mainboard/ocp/tiogapass/emmc.h b/src/mainboard/ocp/tiogapass/emmc.h
new file mode 100644
index 0000000..5f5816b
--- /dev/null
+++ b/src/mainboard/ocp/tiogapass/emmc.h
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 - 2020 Intel Corporation.
+ * Copyright (C) 2019 - 2020 Facebook Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _MAINBOARD_EMMC_H
+#define _MAINBOARD_EMMC_H
+
+#include <fsp/util.h>
+
+/*
+ * eMMC DLL structure for EMMC DLL registers settings
+ */
+typedef struct {
+		UINT32 TxCmdCntl;
+		UINT32 TxDataCntl1;
+		UINT32 TxDataCntl2;
+		UINT32 RxCmdDataCntl1;
+		UINT32 RxStrobeCntl;
+		UINT32 RxCmdDataCntl2;
+		UINT32 MasterSwCntl;
+} BL_EMMC_DLL_CONFIG;
+
+typedef struct {
+	UINT16 Signature;
+	BL_EMMC_DLL_CONFIG eMMCDLLConfig;
+} BL_EMMC_INFORMATION;
+
+#define DEFAULT_EMMC_DLL_SIGN 0x55aa
+
+#ifndef __ACPI__
+BL_EMMC_INFORMATION tiogapass_emmc_config[] = {
+	/*
+	 *  Default eMMC DLL configuration.
+	 */
+	{DEFAULT_EMMC_DLL_SIGN,
+	 {0x00000508, 0x00000c11, 0x1c2a2a2a, 0x00191e27, 0x00000a0a,
+	  0x00010013, 0x00000001} } };
+#endif
+
+#endif /* _MAINBOARD_EMMC_H */
diff --git a/src/mainboard/ocp/tiogapass/fadt.c b/src/mainboard/ocp/tiogapass/fadt.c
new file mode 100644
index 0000000..664034d
--- /dev/null
+++ b/src/mainboard/ocp/tiogapass/fadt.c
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 - 2020 Intel Corporation.
+ * Copyright (C) 2019 - 2020 Facebook Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <string.h>
+#include <arch/acpi.h>
+
+#include <soc/acpi.h>
+#include <soc/soc_util.h>
+
+void motherboard_fill_fadt(acpi_fadt_t *fadt)
+{
+//	fadt->model = 1;
+	fadt->reserved = 0;
+	fadt->preferred_pm_profile = PM_ENTERPRISE_SERVER;
+}
diff --git a/src/mainboard/ocp/tiogapass/ramstage.c b/src/mainboard/ocp/tiogapass/ramstage.c
new file mode 100644
index 0000000..22a3fb3
--- /dev/null
+++ b/src/mainboard/ocp/tiogapass/ramstage.c
@@ -0,0 +1,57 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 - 2020 Intel Corporation.
+ * Copyright (C) 2019 - 2020 Facebook Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <fsp/api.h>
+#include <soc/ramstage.h>
+#include "emmc.h"
+
+static int get_emmc_dll_info(uint16_t signature, size_t num_of_entry,
+			     BL_EMMC_INFORMATION **config)
+{
+	uint8_t entry;
+
+	if ((signature == 0) || (num_of_entry == 0) || (*config == NULL))
+		return 1;
+
+	for (entry = 0; entry < num_of_entry; entry++) {
+		if ((*config)[entry].Signature == signature) {
+			*config = &(*config)[entry];
+			return 0;
+		}
+	}
+
+	return 1;
+}
+
+void mainboard_silicon_init_params(FSPS_UPD *params)
+{
+	size_t num;
+	uint16_t emmc_dll_sign;
+	BL_EMMC_INFORMATION *emmc_config;
+
+	/* Configure eMMC DLL PCD */
+	emmc_dll_sign = DEFAULT_EMMC_DLL_SIGN;
+	num = ARRAY_SIZE(tiogapass_emmc_config);
+	emmc_config = tiogapass_emmc_config;
+
+	if (get_emmc_dll_info(emmc_dll_sign, num, &emmc_config))
+		die("eMMC DLL Configuration is invalid, please correct it!");
+
+	params->FspsConfig.PcdEMMCDLLConfigPtr =
+		(uint32_t)&emmc_config->eMMCDLLConfig;
+}
diff --git a/src/mainboard/ocp/tiogapass/romstage.c b/src/mainboard/ocp/tiogapass/romstage.c
new file mode 100644
index 0000000..af79de6
--- /dev/null
+++ b/src/mainboard/ocp/tiogapass/romstage.c
@@ -0,0 +1,66 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 - 2020 Intel Corporation.
+ * Copyright (C) 2019 - 2020 Facebook Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "tiogapass_boardid.h"
+#include <console/console.h>
+#include <fsp/api.h>
+#include <fsp/soc_binding.h>
+#include <FspmUpd.h>
+#define PCH_SERVER_BIOS_FLAG 1
+#include "skxsp_tp_gpio.h"
+#include "skxsp_tp_iio.h"
+
+void mainboard_config_gpios(FSPM_UPD * mupd);
+void mainboard_config_iio(FSPM_UPD *mupd);
+void mainboard_memory_init_params(FSPM_UPD *mupd);
+
+/*
+* Configure GPIO depend on platform
+*/
+void mainboard_config_gpios(FSPM_UPD *mupd)
+{
+	mupd->FspmConfig.GpioConfig.GpioTable = (UPD_GPIO_INIT_CONFIG *) tp_gpio_table;
+	mupd->FspmConfig.GpioConfig.NumberOfEntries =
+		sizeof(tp_gpio_table)/sizeof(UPD_GPIO_INIT_CONFIG);
+}
+
+void mainboard_config_iio(FSPM_UPD *mupd)
+{
+	mupd->FspmConfig.IioBifurcationConfig.IIoBifurcationTable =
+		(UPD_IIO_BIFURCATION_DATA_ENTRY *) tp_iio_bifur_table;
+	mupd->FspmConfig.IioBifurcationConfig.NumberOfEntries =
+		sizeof(tp_iio_bifur_table)/sizeof(UPD_IIO_BIFURCATION_DATA_ENTRY);
+
+	mupd->FspmConfig.IioPciConfig.ConfigurationTable =
+		(UPD_PCI_PORT_CONFIG *) tp_iio_pci_port_skt0;
+	mupd->FspmConfig.IioPciConfig.NumberOfEntries =
+		sizeof(tp_iio_pci_port_skt0)/sizeof(UPD_PCI_PORT_CONFIG);
+
+	mupd->FspmConfig.PchPciConfig.PciPortConfig =
+		(UPD_PCH_PCIE_PORT *) tp_pch_pci_port_skt0;
+	mupd->FspmConfig.PchPciConfig.NumberOfEntries =
+		sizeof(tp_pch_pci_port_skt0)/sizeof(UPD_PCH_PCIE_PORT);
+
+	mupd->FspmConfig.PchPciConfig.RootPortFunctionSwapping = 0x00;
+	mupd->FspmConfig.PchPciConfig.PciePllSsc = 0x00;
+}
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	mainboard_config_gpios(mupd);
+	mainboard_config_iio(mupd);
+}
diff --git a/src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h b/src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h
new file mode 100644
index 0000000..c6aa3f4
--- /dev/null
+++ b/src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h
@@ -0,0 +1,301 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 - 2020 Intel Corporation.
+ * Copyright (C) 2019 - 2020 Facebook Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+
+#ifndef _SKXSP_TP_GPIO_H
+#define _SKXSP_TP_GPIO_H
+
+#include <FspmUpd.h>
+#include <soc/gpio_fsp.h>
+#include <soc/gpio_soc_defs.h>
+
+/**
+ *  OCP TiogaPass Gpio Pad Configuration
+**/
+static const UPD_GPIO_INIT_CONFIG tp_gpio_table[] = {
+		{GPIO_SKL_H_GPP_A0,  { GpioPadModeGpio,    GpioHostOwnGpio, GpioDirIn,    GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_0_LPC_RCIN_N_ESPI_ALERT1_N
+		{GPIO_SKL_H_GPP_A1,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_1_LAD_0_ESPI_IO_0
+		{GPIO_SKL_H_GPP_A2,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_2_LAD_1_ESPI_IO_1
+		{GPIO_SKL_H_GPP_A3,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_3_LAD_2_ESPI_IO_2
+		{GPIO_SKL_H_GPP_A4,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_4_LAD_3_ESPI_IO_3
+		{GPIO_SKL_H_GPP_A5,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_5_LPC_LFRAME_N_ESPI_CS0_N
+		{GPIO_SKL_H_GPP_A6,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_6_IRQ_LPC_SERIRQ_ESPI_CS1_N
+		{GPIO_SKL_H_GPP_A7,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_7_IRQ_LPC_PIRQA_N_ESPI_ALERT0_N
+		{GPIO_SKL_H_GPP_A8,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_8_FM_LPC_CLKRUN_N
+		{GPIO_SKL_H_GPP_A9,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_9_CLKOUT_LPC0_ESPI_CLK
+		{GPIO_SKL_H_GPP_A10, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_10_CLKOUT_LPC1
+		{GPIO_SKL_H_GPP_A11, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_11_FM_LPC_PME_N
+		{GPIO_SKL_H_GPP_A12, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_A_12_BMBUSY_N_SXEXITHLDOFF_N
+		{GPIO_SKL_H_GPP_A13, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_13_SUSWARN_N_SUSPWRDNACK
+		{GPIO_SKL_H_GPP_A14, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_14_ESPI_RESET_N
+		{GPIO_SKL_H_GPP_A15, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_15_SUSACK_N
+		{GPIO_SKL_H_GPP_A16, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_16_CLKOUT_LPC2
+		{GPIO_SKL_H_GPP_A17, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_17
+		{GPIO_SKL_H_GPP_A18, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_18
+//		{GPIO_SKL_H_GPP_A19, {} }, //GPP_A_19, controlled by ME
+		{GPIO_SKL_H_GPP_A20, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_20
+		{GPIO_SKL_H_GPP_A21, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutLow,		 GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_21
+		{GPIO_SKL_H_GPP_A22, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_22
+		{GPIO_SKL_H_GPP_A23, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_23
+
+		{GPIO_SKL_H_GPP_B0,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_0_CORE_VID_0
+		{GPIO_SKL_H_GPP_B1,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_1_CORE_VID_1
+		{GPIO_SKL_H_GPP_B2,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_2_VRALERT_N
+		{GPIO_SKL_H_GPP_B3,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_3_CPU_GP2
+		{GPIO_SKL_H_GPP_B4,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_4_CPU_GP3
+		{GPIO_SKL_H_GPP_B5,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_5_SRCCLKREQ0_N
+		{GPIO_SKL_H_GPP_B6,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_B_6_SRCCLKREQ1_N
+		{GPIO_SKL_H_GPP_B7,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_B_7_SRCCLKREQ2_N
+		{GPIO_SKL_H_GPP_B8,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_8_SRCCLKREQ3_N
+		{GPIO_SKL_H_GPP_B9,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_9_SRCCLKREQ4_N
+		{GPIO_SKL_H_GPP_B10, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_10_SRCCLKREQ5_N
+		{GPIO_SKL_H_GPP_B11, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutLow,		 GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_11
+		{GPIO_SKL_H_GPP_B12, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_12_GLB_RST_WARN_N
+		{GPIO_SKL_H_GPP_B13, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_13_RST_PLTRST_N
+		{GPIO_SKL_H_GPP_B14, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_14_FM_PCH_BIOS_RCVR_SPKR
+		{GPIO_SKL_H_GPP_B15, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_15
+		{GPIO_SKL_H_GPP_B16, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_16
+		{GPIO_SKL_H_GPP_B17, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_17
+		{GPIO_SKL_H_GPP_B18, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_18
+		{GPIO_SKL_H_GPP_B19, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutLow,		 GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_19
+		{GPIO_SKL_H_GPP_B20, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_20
+		{GPIO_SKL_H_GPP_B21, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_21
+		{GPIO_SKL_H_GPP_B22, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_22
+		{GPIO_SKL_H_GPP_B23, { GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut,   GpioOutLow,		 GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock} }, //GPP_B_23_MEIE_SML1ALRT_N_PHOT_N
+
+//		{GPIO_SKL_H_GPP_C0,  {} }, //GPP_C_0_SMBCLK, controlled by ME
+//		{GPIO_SKL_H_GPP_C1,  {} }, //GPP_C_1_SMBDATA, controlled by ME
+		{GPIO_SKL_H_GPP_C2,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_C_2_SMBALERT_N
+//		{GPIO_SKL_H_GPP_C3,  {} }, //GPP_C_3_SML0CLK_IE, controlled by ME
+//		{GPIO_SKL_H_GPP_C4,  {} }, //GPP_C_4_SML0DATA_IE, controlled by ME
+		{GPIO_SKL_H_GPP_C5,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPP_C_5_SML0ALERT_IE_N
+//		{GPIO_SKL_H_GPP_C6,  {} }, //GPP_C_6_SML1CLK_IE, controlled by ME
+//		{GPIO_SKL_H_GPP_C7,  {} }, //GPP_C_7_SML1DATA_IE, controlled by ME
+		{GPIO_SKL_H_GPP_C8,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_8
+		{GPIO_SKL_H_GPP_C9,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutLow,		 GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_9
+		{GPIO_SKL_H_GPP_C10, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_C_10
+		{GPIO_SKL_H_GPP_C11, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_11
+		{GPIO_SKL_H_GPP_C12, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_C_12
+		{GPIO_SKL_H_GPP_C13, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_C_13
+		{GPIO_SKL_H_GPP_C14, { GpioPadModeGpio,		GpioHostOwnAcpi, GpioDirIn,		GpioOutDefault, GpioIntLevel | GpioIntSci, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_C_14
+		{GPIO_SKL_H_GPP_C15, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_15
+		{GPIO_SKL_H_GPP_C16, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_16
+		{GPIO_SKL_H_GPP_C17, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_17
+		{GPIO_SKL_H_GPP_C18, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_18
+		{GPIO_SKL_H_GPP_C19, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_19
+//		{GPIO_SKL_H_GPP_C20, {} }, //GPP_C_20, controlled by ME
+		{GPIO_SKL_H_GPP_C21, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_21
+		{GPIO_SKL_H_GPP_C22, { GpioPadModeGpio,		GpioHostOwnAcpi, GpioDirIn,		GpioOutDefault, GpioIntLevel | GpioIntSmi, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_C_22
+		{GPIO_SKL_H_GPP_C23, { GpioPadModeGpio,		GpioHostOwnAcpi, GpioDirIn,		GpioOutDefault, GpioIntLevel | GpioIntSmi, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_C_23
+
+		{GPIO_SKL_H_GPP_D0,  { GpioPadModeGpio,		GpioHostOwnAcpi, GpioDirIn,		GpioOutDefault, GpioIntLevel | GpioIntSmi, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_D_0
+		{GPIO_SKL_H_GPP_D1,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_1
+		{GPIO_SKL_H_GPP_D2,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_D_2
+		{GPIO_SKL_H_GPP_D3,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_D_3
+		{GPIO_SKL_H_GPP_D4,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutLow,		 GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_4
+		{GPIO_SKL_H_GPP_D5,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_5
+		{GPIO_SKL_H_GPP_D6,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_6
+		{GPIO_SKL_H_GPP_D7,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_7
+		{GPIO_SKL_H_GPP_D8,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_8
+		{GPIO_SKL_H_GPP_D9,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_9_SSATA_DEVSLP3
+		{GPIO_SKL_H_GPP_D10, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_10_SSATA_DEVSLP4
+		{GPIO_SKL_H_GPP_D11, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_11_SSATA_DEVSLP5
+		{GPIO_SKL_H_GPP_D12, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_12_SSATA_SDATAOUT1
+		{GPIO_SKL_H_GPP_D13, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_13_SML0BLCK_IE
+		{GPIO_SKL_H_GPP_D14, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_14_SML0BDATA_IE
+		{GPIO_SKL_H_GPP_D15, { GpioPadModeNative3, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_15_SSATA_SDATAOUT0
+		{GPIO_SKL_H_GPP_D16, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_16_SML0BALERT_IE_N
+		{GPIO_SKL_H_GPP_D17, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_17
+		{GPIO_SKL_H_GPP_D18, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_18
+		{GPIO_SKL_H_GPP_D19, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutLow,		 GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock | GpioOutputStateLock} }, //GPP_D_19
+		{GPIO_SKL_H_GPP_D20, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_20_TP_PCH_GPP_D_20
+		{GPIO_SKL_H_GPP_D21, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_21_IE_URAT_RX
+		{GPIO_SKL_H_GPP_D22, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_22_IE_URAT_TX
+		{GPIO_SKL_H_GPP_D23, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_23
+
+		{GPIO_SKL_H_GPP_E0,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntLevel | GpioIntSmi, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_0_SATAXPCIE0_SATAGP0
+		{GPIO_SKL_H_GPP_E1,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntLevel | GpioIntSmi, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_1_SATAXPCIE1_SATAGP1
+		{GPIO_SKL_H_GPP_E2,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_2_SATAXPCIE2_SATAGP2
+		{GPIO_SKL_H_GPP_E3,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_3_CPU_GP0
+		{GPIO_SKL_H_GPP_E4,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_4_SATA_DEVSLP0
+		{GPIO_SKL_H_GPP_E5,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_5_SATA_DEVSLP1
+		{GPIO_SKL_H_GPP_E6,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_6_SATA_DEVSLP2
+		{GPIO_SKL_H_GPP_E7,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_7_CPU_GP1
+		{GPIO_SKL_H_GPP_E8,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_8_SATA_LED_N
+		{GPIO_SKL_H_GPP_E9,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_9_USB2_OC0_N
+		{GPIO_SKL_H_GPP_E10, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_10_USB2_OC1_N
+		{GPIO_SKL_H_GPP_E11, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_11_USB2_OC2_N
+		{GPIO_SKL_H_GPP_E12, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_12_USB2_OC3_N
+
+		{GPIO_SKL_H_GPP_F0,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_F_0_SATAXPCIE3_SATAGP3
+		{GPIO_SKL_H_GPP_F1,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_F_1_SATAXPCIE4_SATAGP4
+		{GPIO_SKL_H_GPP_F2,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_F_2_SATAXPCIE5_SATAGP5
+		{GPIO_SKL_H_GPP_F3,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_F_3_SATAXPCIE6_SATAGP6
+		{GPIO_SKL_H_GPP_F4,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_F_4_SATAXPCIE7_SATAGP7
+		{GPIO_SKL_H_GPP_F5,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_F_5_SATA_DEVSLP3
+		{GPIO_SKL_H_GPP_F6,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_F_6_SATA_DEVSLP4
+		{GPIO_SKL_H_GPP_F7,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_F_7_SATA_DEVSLP5
+		{GPIO_SKL_H_GPP_F8,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_F_8_SATA_DEVSLP6
+		{GPIO_SKL_H_GPP_F9,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_F_9_SATA_DEVSLP7
+		{GPIO_SKL_H_GPP_F10, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_10_SATA_SCLOCK
+		{GPIO_SKL_H_GPP_F11, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_11_SATA_SLOAD
+		{GPIO_SKL_H_GPP_F12, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_12_SATA_SDATAOUT1
+		{GPIO_SKL_H_GPP_F13, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_13_SATA_SDATAOUT0
+		{GPIO_SKL_H_GPP_F14, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_14_SSATA_LED_N
+		{GPIO_SKL_H_GPP_F15, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_15_USB2_OC4_N
+		{GPIO_SKL_H_GPP_F16, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_16_USB2_OC5_N
+		{GPIO_SKL_H_GPP_F17, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_17_USB2_OC6_N
+		{GPIO_SKL_H_GPP_F18, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_18_USB2_OC7_N
+		{GPIO_SKL_H_GPP_F19, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_19_LAN_SMBCLK
+		{GPIO_SKL_H_GPP_F20, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_20_LAN_SMBDATA
+		{GPIO_SKL_H_GPP_F21, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_21_LAN_SMBALERT_N
+		{GPIO_SKL_H_GPP_F22, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_22_SSATA_SCLOCK
+		{GPIO_SKL_H_GPP_F23, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_23_SSATA_SLOAD
+
+		{GPIO_SKL_H_GPP_G0,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_0_FANTACH0_FANTACH0IE
+		{GPIO_SKL_H_GPP_G1,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_1_FANTACH1_FANTACH1IE
+		{GPIO_SKL_H_GPP_G2,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_2_FANTACH2_FANTACH2IE
+		{GPIO_SKL_H_GPP_G3,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_3_FANTACH3_FANTACH3IE
+		{GPIO_SKL_H_GPP_G4,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_4_FANTACH4_FANTACH4IE
+		{GPIO_SKL_H_GPP_G5,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_5_FANTACH5_FANTACH5IE
+		{GPIO_SKL_H_GPP_G6,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_6_FANTACH6_FANTACH6IE
+		{GPIO_SKL_H_GPP_G7,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_7_FANTACH7_FANTACH7IE
+		{GPIO_SKL_H_GPP_G8,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_8_FANPWM0_FANPWM0IE
+		{GPIO_SKL_H_GPP_G9,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_9_FANPWM1_FANPWM1IE
+		{GPIO_SKL_H_GPP_G10, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_10_FANPWM2_FANPWM2IE
+		{GPIO_SKL_H_GPP_G11, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_11_FANPWM3_FANPWM3IE
+		{GPIO_SKL_H_GPP_G12, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_12
+		{GPIO_SKL_H_GPP_G13, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_13
+		{GPIO_SKL_H_GPP_G14, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_14
+		{GPIO_SKL_H_GPP_G15, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_15
+		{GPIO_SKL_H_GPP_G16, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_16
+		{GPIO_SKL_H_GPP_G17, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_17_ADR_COMPLETE
+		{GPIO_SKL_H_GPP_G18, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_18_FM_NMI_EVENT_N
+		{GPIO_SKL_H_GPP_G19, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_19_FM_SMI_ACTIVE_N
+//		{GPIO_SKL_H_GPP_G20, {} }, //GPP_G_20_SSATA_DEVSLP0, controlled by ME
+		{GPIO_SKL_H_GPP_G21, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_21_SSATA_DEVSLP1
+		{GPIO_SKL_H_GPP_G22, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_G_22_SSATA_DEVSLP2
+		{GPIO_SKL_H_GPP_G23, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_23_SSATAXPCIE0_SSATAGP0
+
+		{GPIO_SKL_H_GPP_H0,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_H_0_SRCCLKREQ6_N
+		{GPIO_SKL_H_GPP_H1,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_H_1_SRCCLKREQ7_N
+		{GPIO_SKL_H_GPP_H2,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_H_2_SRCCLKREQ8_N
+		{GPIO_SKL_H_GPP_H3,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_H_3_SRCCLKREQ9_N
+		{GPIO_SKL_H_GPP_H4,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_H_4_SRCCLKREQ10_N
+//		{GPIO_SKL_H_GPP_H5,  {} }, //GPP_H_5_SRCCLKREQ11_N
+		{GPIO_SKL_H_GPP_H6,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_H_6_SRCCLKREQ12_N
+		{GPIO_SKL_H_GPP_H7,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_H_7_SRCCLKREQ13_N
+		{GPIO_SKL_H_GPP_H8,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_H_8_SRCCLKREQ14_N
+		{GPIO_SKL_H_GPP_H9,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_H_9_SRCCLKREQ15_N
+//		{GPIO_SKL_H_GPP_H10, {} }, //GPP_H_10_SML2CLK_IE
+//		{GPIO_SKL_H_GPP_H11, {} }, //GPP_H_11_SML2DATA_IE
+		{GPIO_SKL_H_GPP_H12, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_H_12_SML2ALERT_N_IE
+//		{GPIO_SKL_H_GPP_H13, {} }, //GPP_H_13_SML3CLK_IE
+//		{GPIO_SKL_H_GPP_H14, {} }, //GPP_H_14_SML3DATA_IE
+		{GPIO_SKL_H_GPP_H15, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_H_15_SML3ALERT_N_IE
+//		{GPIO_SKL_H_GPP_H16, {} }, //GPP_H_16_SML4CLK_IE
+//		{GPIO_SKL_H_GPP_H17, {} }, //GPP_H_17_SML4DATA_IE
+		{GPIO_SKL_H_GPP_H18, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_H_18_SML4ALERT_N_IE
+		{GPIO_SKL_H_GPP_H19, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_H_19_SSATAXPCIE1_SSATAGP1
+		{GPIO_SKL_H_GPP_H20, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_H_20_SSATAXPCIE2_SSATAGP2
+		{GPIO_SKL_H_GPP_H21, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_H_21_SSATAXPCIE3_SSATAGP3
+		{GPIO_SKL_H_GPP_H22, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_H_22_SSATAXPCIE4_SSATAGP4
+		{GPIO_SKL_H_GPP_H23, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_H_23_SSATAXPCIE5_SSATAGP5
+
+		{GPIO_SKL_H_GPP_I0,  { GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_I_0_GBE_TDO
+		{GPIO_SKL_H_GPP_I1,  { GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_I_1_GBE_TCK
+		{GPIO_SKL_H_GPP_I2,  { GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_I_2_GBE_TMS
+		{GPIO_SKL_H_GPP_I3,  { GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_I_3_GBE_TDI
+		{GPIO_SKL_H_GPP_I4,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_I_4_DO_RESET_IN_N
+		{GPIO_SKL_H_GPP_I5,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_I_5_DO_RESET_OUT_N
+		{GPIO_SKL_H_GPP_I6,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_I_6_RESET_DONE
+		{GPIO_SKL_H_GPP_I7,  { GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_I_7_JTAG_GBE_TRST_N
+		{GPIO_SKL_H_GPP_I8,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_I_8_GBE_PCI_DIS
+		{GPIO_SKL_H_GPP_I9,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_I_9_GBE_LAN_DIS
+		{GPIO_SKL_H_GPP_I10, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_I_10
+
+		{GPIO_SKL_H_GPP_J0,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_0_LAN_LED_P0_0
+		{GPIO_SKL_H_GPP_J1,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_1_LAN_LED_P0_1
+		{GPIO_SKL_H_GPP_J2,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_2_LAN_LED_P1_0
+		{GPIO_SKL_H_GPP_J3,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_3_LAN_LED_P1_1
+		{GPIO_SKL_H_GPP_J4,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_4_LAN_LED_P2_0
+		{GPIO_SKL_H_GPP_J5,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_5_LAN_LED_P2_1
+		{GPIO_SKL_H_GPP_J6,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_6_LAN_LED_P3_0
+		{GPIO_SKL_H_GPP_J7,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_7_LAN_LED_P3_1
+		{GPIO_SKL_H_GPP_J8,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_8_LAN_I2C_SCL_MDC_P0
+		{GPIO_SKL_H_GPP_J9,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_9_LAN_I2C_SDA_MDIO_P0
+		{GPIO_SKL_H_GPP_J10, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_10_LAN_I2C_SCL_MDC_P1
+		{GPIO_SKL_H_GPP_J11, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_11_LAN_I2C_SDA_MDIO_P1
+		{GPIO_SKL_H_GPP_J12, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_12_LAN_I2C_SCL_MDC_P2
+		{GPIO_SKL_H_GPP_J13, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_13_LAN_I2C_SDA_MDIO_P2
+		{GPIO_SKL_H_GPP_J14, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_14_LAN_I2C_SCL_MDC_P3
+		{GPIO_SKL_H_GPP_J15, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_15_LAN_I2C_SDA_MDIO_P3
+		{GPIO_SKL_H_GPP_J16, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_16_LAN_SDP_P0_0
+		{GPIO_SKL_H_GPP_J17, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_17_LAN_SDP_P0_1
+		{GPIO_SKL_H_GPP_J18, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_18_LAN_SDP_P1_0
+		{GPIO_SKL_H_GPP_J19, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_19_LAN_SDP_P1_1
+		{GPIO_SKL_H_GPP_J20, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_20_LAN_SDP_P2_0
+		{GPIO_SKL_H_GPP_J21, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_21_LAN_SDP_P2_1
+		{GPIO_SKL_H_GPP_J22, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_22_LAN_SDP_P3_0
+		{GPIO_SKL_H_GPP_J23, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_23_LAN_SDP_P3_1
+
+		{GPIO_SKL_H_GPP_K0,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_K_0_LAN_NCSI_CLK_IN
+		{GPIO_SKL_H_GPP_K1,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_K_1_LAN_NCSI_TXD0
+		{GPIO_SKL_H_GPP_K2,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_K_2_LAN_NCSI_TXD1
+		{GPIO_SKL_H_GPP_K3,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_K_3_LAN_NCSI_TX_EN
+		{GPIO_SKL_H_GPP_K4,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_K_4_LAN_NCSI_CRS_DV
+		{GPIO_SKL_H_GPP_K5,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_K_5_LAN_NCSI_RXD0
+		{GPIO_SKL_H_GPP_K6,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_K_6_LAN_NCSI_RXD1
+		{GPIO_SKL_H_GPP_K7,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_K_7
+		{GPIO_SKL_H_GPP_K8,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,  GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_K_8_LAN_NCSI_ARB_IN
+		{GPIO_SKL_H_GPP_K9,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_K_9_LAN_NCSI_ARB_OUT
+		{GPIO_SKL_H_GPP_K10, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_K_10_PE_RST_N
+
+		{GPIO_SKL_H_GPP_L2,  { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_2_TESTCH0_D0
+		{GPIO_SKL_H_GPP_L3,  { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_3_TESTCH0_D1
+		{GPIO_SKL_H_GPP_L4,  { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_4_TESTCH0_D2
+		{GPIO_SKL_H_GPP_L5,  { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_5_TESTCH0_D3
+		{GPIO_SKL_H_GPP_L6,  { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_6_TESTCH0_D4
+		{GPIO_SKL_H_GPP_L7,  { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_7_TESTCH0_D5
+		{GPIO_SKL_H_GPP_L8,  { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_8_TESTCH0_D6
+		{GPIO_SKL_H_GPP_L9,  { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_9_TESTCH0_D7
+		{GPIO_SKL_H_GPP_L10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_10_TESTCH0_CLK
+		{GPIO_SKL_H_GPP_L11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_11_TESTCH1_D0
+		{GPIO_SKL_H_GPP_L12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_12_TESTCH1_D1
+		{GPIO_SKL_H_GPP_L13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_13_TESTCH1_D2
+		{GPIO_SKL_H_GPP_L14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_14_TESTCH1_D3
+		{GPIO_SKL_H_GPP_L15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_15_TESTCH1_D4
+		{GPIO_SKL_H_GPP_L16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_16_TESTCH1_D5
+		{GPIO_SKL_H_GPP_L17, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_17_TESTCH1_D6
+		{GPIO_SKL_H_GPP_L18, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_18_TESTCH1_D7
+		{GPIO_SKL_H_GPP_L19, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_19_TESTCH1_CLK
+
+		{GPIO_SKL_H_GPD0,		{} }, //GPD_0, controlled by ME
+		{GPIO_SKL_H_GPD1,		{ GpioPadModeGpio,   GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPD_1_ACPRESENT
+		{GPIO_SKL_H_GPD2,		{ GpioPadModeGpio,   GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPD_2_GBE_WAKE_N
+		{GPIO_SKL_H_GPD3,		{ GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPD_3_PWRBTNB_N
+		{GPIO_SKL_H_GPD4,		{ GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPD_4_SLP_S3B
+		{GPIO_SKL_H_GPD5,		{ GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPD_5_SLP_S4B
+		{GPIO_SKL_H_GPD6,		{ GpioPadModeGpio,   GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPD_6_SLPA_N
+		{GPIO_SKL_H_GPD7,		{ GpioPadModeGpio,   GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPD_7
+		{GPIO_SKL_H_GPD8,		{ GpioPadModeGpio,   GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPD_8_CLK_33K_PCH_SUSCLK_PLD
+		{GPIO_SKL_H_GPD9,		{ GpioPadModeGpio,   GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPD_9
+		{GPIO_SKL_H_GPD10,   { GpioPadModeGpio,   GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPD_10_FM_SLPS5_N
+		{GPIO_SKL_H_GPD11,   { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPD_11_GBEPHY
+};
+
+#endif
diff --git a/src/mainboard/ocp/tiogapass/skxsp_tp_iio.h b/src/mainboard/ocp/tiogapass/skxsp_tp_iio.h
new file mode 100644
index 0000000..ac0fe99
--- /dev/null
+++ b/src/mainboard/ocp/tiogapass/skxsp_tp_iio.h
@@ -0,0 +1,73 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 - 2020 Intel Corporation.
+ * Copyright (C) 2019 - 2020 Facebook Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SKXSP_TP_IIO_H
+#define _SKXSP_TP_IIO_H
+
+#include <FspmUpd.h>
+#include <soc/pci_devs.h>
+
+/**
+ * Standard Tioga Pass Iio Bifurcation Table
+ * This is SS 2x16 config. As documented in OCP TP spec, there are
+ * 3 configs. SS 2x16 is the most common.
+ * TODO: figure out config through board SKU ID and through PCIe
+ * config GPIO setting (SLT_CFG0 / SLT_CFG1).
+**/
+static const UPD_IIO_BIFURCATION_DATA_ENTRY tp_iio_bifur_table[] = {
+	{ Iio_Socket0, Iio_Iou0, IIO_BIFURCATE_xxxxxx16 }, /* 1A x16 */
+	{ Iio_Socket0, Iio_Iou1, IIO_BIFURCATE_xxxxxx16 }, /* 2A x16 */
+	{ Iio_Socket0, Iio_Iou2, IIO_BIFURCATE_xxxxxx16 }, /* 3A x16 */
+	{ Iio_Socket0, Iio_Mcp0, IIO_BIFURCATE_xxxxxxxx }, /* No MCP */
+	{ Iio_Socket0, Iio_Mcp1, IIO_BIFURCATE_xxxxxxxx }, /* No MCP */
+	{ Iio_Socket1, Iio_Iou0, IIO_BIFURCATE_xxxxxxxx }, /* no IOU0 */
+	{ Iio_Socket1, Iio_Iou1, IIO_BIFURCATE_xxxxxxxx }, /* no IOU1 */
+	{ Iio_Socket1, Iio_Iou2, IIO_BIFURCATE_xxx8xxx8 }, /* 3A x8, 3C x8 */
+	{ Iio_Socket1, Iio_Mcp0, IIO_BIFURCATE_xxxxxxxx }, /* No MCP */
+	{ Iio_Socket1, Iio_Mcp1, IIO_BIFURCATE_xxxxxxxx }, /* No MCP */
+};
+
+/**
+ * Standard Tioga Pass Iio PCIe Port Table
+**/
+static const UPD_PCI_PORT_CONFIG tp_iio_pci_port_skt0[] = {
+  // PortIndex |  HidePort  | DeEmphasis | PortLinkSpeed | MaxPayload | DfxDnTxPreset | DfxRxPreset | DfxUpTxPreset | Sris | PcieCommonClock | NtbPpd               | NtbSplitBar | NtbBarSizePBar23 | NtbBarSizePBar4 | NtbBarSizePBar5 | NtbBarSizePBar45 | NtbBarSizeSBar23 | NtbBarSizeSBar4 | NtbBarSizeSbar5 | NtbBarSizeSBar45 | NtbSBar01Prefetch | NtbXlinkCtlOverride
+	{ PORT_1A, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
+	{ PORT_1B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
+	{ PORT_1C, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
+	{ PORT_1D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
+	{ PORT_2A, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
+	{ PORT_2B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
+	{ PORT_2C, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
+	{ PORT_2D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
+	{ PORT_3A, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
+	{ PORT_3B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
+	{ PORT_3C, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
+	{ PORT_3D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
+};
+
+/**
+ * Standard Tioga Pass PCH PCIe Port Table
+**/
+static const UPD_PCH_PCIE_PORT tp_pch_pci_port_skt0[] = {
+	//PortIndex ; ForceEnable ; PortLinkSpeed
+	{ 0x00, 0x01, PcieAuto },
+	{ 0x04, 0x01, PcieAuto },
+	{ 0x05, 0x01, PcieAuto },
+};
+
+#endif // end of _SKXSP_TP_IIO_H
diff --git a/src/mainboard/ocp/tiogapass/tiogapass_boardid.h b/src/mainboard/ocp/tiogapass/tiogapass_boardid.h
new file mode 100644
index 0000000..39dc7b3
--- /dev/null
+++ b/src/mainboard/ocp/tiogapass/tiogapass_boardid.h
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 - 2020 Intel Corporation.
+ * Copyright (C) 2019 - 2020 Facebook Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef TIOGAPASS_MAINBOARD_BOARD_H
+#define TIOGAPASS_MAINBOARD_BOARD_H
+
+#include <stdint.h>
+
+#define BoardIdTiogaPass 0x52
+
+uint8_t board_id(void);
+
+#endif /* MAINBOARD_BOARD_H */
diff --git a/src/mainboard/ocp/tiogapass/vboot-ro.fmd b/src/mainboard/ocp/tiogapass/vboot-ro.fmd
new file mode 100644
index 0000000..30551fe
--- /dev/null
+++ b/src/mainboard/ocp/tiogapass/vboot-ro.fmd
@@ -0,0 +1,23 @@
+FLASH 32M {
+	# ME takes 16MB.
+	SI_ALL@0x0 0x1000000 {
+		SI_DESC@0x0 0x1000
+		SI_ME@0x1000 0xfff000
+	}
+	SI_BIOS@0x1000000 0x1000000 {
+		MISC_RW@0x0 0x20000 {
+			RW_MRC_CACHE@0x0 0x10000
+			RW_VPD(PRESERVE)@0x010000 0x4000
+		}
+		WP_RO@0x020000 0xfe0000 {
+			RO_VPD(PRESERVE)@0x0 0x4000
+			RO_SECTION@0x4000 0xfdc000 {
+				FMAP@0x0 0x800
+				RO_FRID@0x800 0x40
+				RO_FRID_PAD@0x840 0x7c0
+				GBB@0x1000 0x4000
+				COREBOOT(CBFS)@0x5000 0xfd7000
+			}
+		}
+	}
+}

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38549 )

Change subject: Add support for OCP platform TiogaPass
......................................................................

Patch Set 1:

(253 comments)

https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
File src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h:

https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 30: 		{GPIO_SKL_H_GPP_A0,  { GpioPadModeGpio,    GpioHostOwnGpio, GpioDirIn,    GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_0_LPC_RCIN_N_ESPI_ALERT1_N
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 31: 		{GPIO_SKL_H_GPP_A1,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_1_LAD_0_ESPI_IO_0
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 32: 		{GPIO_SKL_H_GPP_A2,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_2_LAD_1_ESPI_IO_1
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 33: 		{GPIO_SKL_H_GPP_A3,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_3_LAD_2_ESPI_IO_2
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 34: 		{GPIO_SKL_H_GPP_A4,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_4_LAD_3_ESPI_IO_3
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 35: 		{GPIO_SKL_H_GPP_A5,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_5_LPC_LFRAME_N_ESPI_CS0_N
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 36: 		{GPIO_SKL_H_GPP_A6,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_6_IRQ_LPC_SERIRQ_ESPI_CS1_N
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 37: 		{GPIO_SKL_H_GPP_A7,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_7_IRQ_LPC_PIRQA_N_ESPI_ALERT0_N
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 38: 		{GPIO_SKL_H_GPP_A8,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_8_FM_LPC_CLKRUN_N
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 39: 		{GPIO_SKL_H_GPP_A9,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_9_CLKOUT_LPC0_ESPI_CLK
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 40: 		{GPIO_SKL_H_GPP_A10, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_10_CLKOUT_LPC1
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 41: 		{GPIO_SKL_H_GPP_A11, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_11_FM_LPC_PME_N
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 42: 		{GPIO_SKL_H_GPP_A12, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_A_12_BMBUSY_N_SXEXITHLDOFF_N
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 43: 		{GPIO_SKL_H_GPP_A13, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_13_SUSWARN_N_SUSPWRDNACK
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 44: 		{GPIO_SKL_H_GPP_A14, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_14_ESPI_RESET_N
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 45: 		{GPIO_SKL_H_GPP_A15, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_15_SUSACK_N
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 46: 		{GPIO_SKL_H_GPP_A16, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_16_CLKOUT_LPC2
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 47: 		{GPIO_SKL_H_GPP_A17, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_17
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 48: 		{GPIO_SKL_H_GPP_A18, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_18
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 50: 		{GPIO_SKL_H_GPP_A20, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_20
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 51: 		{GPIO_SKL_H_GPP_A21, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutLow,		 GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_21
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 52: 		{GPIO_SKL_H_GPP_A22, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_22
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 53: 		{GPIO_SKL_H_GPP_A23, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_23
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 55: 		{GPIO_SKL_H_GPP_B0,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_0_CORE_VID_0
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 56: 		{GPIO_SKL_H_GPP_B1,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_1_CORE_VID_1
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 57: 		{GPIO_SKL_H_GPP_B2,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_2_VRALERT_N
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 58: 		{GPIO_SKL_H_GPP_B3,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_3_CPU_GP2
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 59: 		{GPIO_SKL_H_GPP_B4,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_4_CPU_GP3
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 60: 		{GPIO_SKL_H_GPP_B5,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_5_SRCCLKREQ0_N
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 61: 		{GPIO_SKL_H_GPP_B6,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_B_6_SRCCLKREQ1_N
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 62: 		{GPIO_SKL_H_GPP_B7,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_B_7_SRCCLKREQ2_N
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 63: 		{GPIO_SKL_H_GPP_B8,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_8_SRCCLKREQ3_N
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 64: 		{GPIO_SKL_H_GPP_B9,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_9_SRCCLKREQ4_N
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 65: 		{GPIO_SKL_H_GPP_B10, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_10_SRCCLKREQ5_N
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 66: 		{GPIO_SKL_H_GPP_B11, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutLow,		 GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_11
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 67: 		{GPIO_SKL_H_GPP_B12, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_12_GLB_RST_WARN_N
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 68: 		{GPIO_SKL_H_GPP_B13, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_13_RST_PLTRST_N
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 69: 		{GPIO_SKL_H_GPP_B14, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_14_FM_PCH_BIOS_RCVR_SPKR
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 70: 		{GPIO_SKL_H_GPP_B15, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_15
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 71: 		{GPIO_SKL_H_GPP_B16, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_16
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 72: 		{GPIO_SKL_H_GPP_B17, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_17
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 73: 		{GPIO_SKL_H_GPP_B18, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_18
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 74: 		{GPIO_SKL_H_GPP_B19, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutLow,		 GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_19
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 75: 		{GPIO_SKL_H_GPP_B20, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_20
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 76: 		{GPIO_SKL_H_GPP_B21, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_21
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 77: 		{GPIO_SKL_H_GPP_B22, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_22
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 78: 		{GPIO_SKL_H_GPP_B23, { GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut,   GpioOutLow,		 GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock} }, //GPP_B_23_MEIE_SML1ALRT_N_PHOT_N
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 82: 		{GPIO_SKL_H_GPP_C2,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_C_2_SMBALERT_N
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 85: 		{GPIO_SKL_H_GPP_C5,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPP_C_5_SML0ALERT_IE_N
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 88: 		{GPIO_SKL_H_GPP_C8,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_8
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 89: 		{GPIO_SKL_H_GPP_C9,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutLow,		 GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_9
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 90: 		{GPIO_SKL_H_GPP_C10, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_C_10
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 91: 		{GPIO_SKL_H_GPP_C11, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_11
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 92: 		{GPIO_SKL_H_GPP_C12, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_C_12
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 93: 		{GPIO_SKL_H_GPP_C13, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_C_13
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 94: 		{GPIO_SKL_H_GPP_C14, { GpioPadModeGpio,		GpioHostOwnAcpi, GpioDirIn,		GpioOutDefault, GpioIntLevel | GpioIntSci, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_C_14
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 95: 		{GPIO_SKL_H_GPP_C15, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_15
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 96: 		{GPIO_SKL_H_GPP_C16, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_16
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 97: 		{GPIO_SKL_H_GPP_C17, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_17
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 98: 		{GPIO_SKL_H_GPP_C18, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_18
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 99: 		{GPIO_SKL_H_GPP_C19, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_19
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 101: 		{GPIO_SKL_H_GPP_C21, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_21
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 102: 		{GPIO_SKL_H_GPP_C22, { GpioPadModeGpio,		GpioHostOwnAcpi, GpioDirIn,		GpioOutDefault, GpioIntLevel | GpioIntSmi, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_C_22
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 103: 		{GPIO_SKL_H_GPP_C23, { GpioPadModeGpio,		GpioHostOwnAcpi, GpioDirIn,		GpioOutDefault, GpioIntLevel | GpioIntSmi, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_C_23
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 105: 		{GPIO_SKL_H_GPP_D0,  { GpioPadModeGpio,		GpioHostOwnAcpi, GpioDirIn,		GpioOutDefault, GpioIntLevel | GpioIntSmi, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_D_0
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 106: 		{GPIO_SKL_H_GPP_D1,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_1
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 107: 		{GPIO_SKL_H_GPP_D2,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_D_2
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 108: 		{GPIO_SKL_H_GPP_D3,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_D_3
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 109: 		{GPIO_SKL_H_GPP_D4,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutLow,		 GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_4
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 110: 		{GPIO_SKL_H_GPP_D5,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_5
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 111: 		{GPIO_SKL_H_GPP_D6,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_6
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 112: 		{GPIO_SKL_H_GPP_D7,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_7
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 113: 		{GPIO_SKL_H_GPP_D8,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_8
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 114: 		{GPIO_SKL_H_GPP_D9,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_9_SSATA_DEVSLP3
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 115: 		{GPIO_SKL_H_GPP_D10, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_10_SSATA_DEVSLP4
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 116: 		{GPIO_SKL_H_GPP_D11, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_11_SSATA_DEVSLP5
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 117: 		{GPIO_SKL_H_GPP_D12, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_12_SSATA_SDATAOUT1
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 118: 		{GPIO_SKL_H_GPP_D13, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_13_SML0BLCK_IE
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 119: 		{GPIO_SKL_H_GPP_D14, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_14_SML0BDATA_IE
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 120: 		{GPIO_SKL_H_GPP_D15, { GpioPadModeNative3, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_15_SSATA_SDATAOUT0
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 121: 		{GPIO_SKL_H_GPP_D16, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_16_SML0BALERT_IE_N
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 122: 		{GPIO_SKL_H_GPP_D17, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_17
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 123: 		{GPIO_SKL_H_GPP_D18, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_18
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 124: 		{GPIO_SKL_H_GPP_D19, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutLow,		 GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock | GpioOutputStateLock} }, //GPP_D_19
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 125: 		{GPIO_SKL_H_GPP_D20, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_20_TP_PCH_GPP_D_20
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 126: 		{GPIO_SKL_H_GPP_D21, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_21_IE_URAT_RX
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 127: 		{GPIO_SKL_H_GPP_D22, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_22_IE_URAT_TX
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 128: 		{GPIO_SKL_H_GPP_D23, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_23
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 130: 		{GPIO_SKL_H_GPP_E0,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntLevel | GpioIntSmi, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_0_SATAXPCIE0_SATAGP0
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 131: 		{GPIO_SKL_H_GPP_E1,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntLevel | GpioIntSmi, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_1_SATAXPCIE1_SATAGP1
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 132: 		{GPIO_SKL_H_GPP_E2,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_2_SATAXPCIE2_SATAGP2
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 133: 		{GPIO_SKL_H_GPP_E3,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_3_CPU_GP0
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 134: 		{GPIO_SKL_H_GPP_E4,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_4_SATA_DEVSLP0
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 135: 		{GPIO_SKL_H_GPP_E5,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_5_SATA_DEVSLP1
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 136: 		{GPIO_SKL_H_GPP_E6,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_6_SATA_DEVSLP2
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 137: 		{GPIO_SKL_H_GPP_E7,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_7_CPU_GP1
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 138: 		{GPIO_SKL_H_GPP_E8,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_8_SATA_LED_N
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 139: 		{GPIO_SKL_H_GPP_E9,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_9_USB2_OC0_N
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 140: 		{GPIO_SKL_H_GPP_E10, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_10_USB2_OC1_N
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 141: 		{GPIO_SKL_H_GPP_E11, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_11_USB2_OC2_N
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 142: 		{GPIO_SKL_H_GPP_E12, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_12_USB2_OC3_N
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 144: 		{GPIO_SKL_H_GPP_F0,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_F_0_SATAXPCIE3_SATAGP3
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 145: 		{GPIO_SKL_H_GPP_F1,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_F_1_SATAXPCIE4_SATAGP4
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 146: 		{GPIO_SKL_H_GPP_F2,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_F_2_SATAXPCIE5_SATAGP5
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 147: 		{GPIO_SKL_H_GPP_F3,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_F_3_SATAXPCIE6_SATAGP6
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 148: 		{GPIO_SKL_H_GPP_F4,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_F_4_SATAXPCIE7_SATAGP7
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 149: 		{GPIO_SKL_H_GPP_F5,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_F_5_SATA_DEVSLP3
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 150: 		{GPIO_SKL_H_GPP_F6,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_F_6_SATA_DEVSLP4
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 151: 		{GPIO_SKL_H_GPP_F7,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_F_7_SATA_DEVSLP5
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 152: 		{GPIO_SKL_H_GPP_F8,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_F_8_SATA_DEVSLP6
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 153: 		{GPIO_SKL_H_GPP_F9,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_F_9_SATA_DEVSLP7
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 154: 		{GPIO_SKL_H_GPP_F10, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_10_SATA_SCLOCK
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 155: 		{GPIO_SKL_H_GPP_F11, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_11_SATA_SLOAD
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 156: 		{GPIO_SKL_H_GPP_F12, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_12_SATA_SDATAOUT1
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 157: 		{GPIO_SKL_H_GPP_F13, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_13_SATA_SDATAOUT0
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 158: 		{GPIO_SKL_H_GPP_F14, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_14_SSATA_LED_N
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 159: 		{GPIO_SKL_H_GPP_F15, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_15_USB2_OC4_N
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 160: 		{GPIO_SKL_H_GPP_F16, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_16_USB2_OC5_N
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 161: 		{GPIO_SKL_H_GPP_F17, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_17_USB2_OC6_N
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 162: 		{GPIO_SKL_H_GPP_F18, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_18_USB2_OC7_N
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 163: 		{GPIO_SKL_H_GPP_F19, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_19_LAN_SMBCLK
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 164: 		{GPIO_SKL_H_GPP_F20, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_20_LAN_SMBDATA
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 165: 		{GPIO_SKL_H_GPP_F21, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_21_LAN_SMBALERT_N
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 166: 		{GPIO_SKL_H_GPP_F22, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_22_SSATA_SCLOCK
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 167: 		{GPIO_SKL_H_GPP_F23, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_23_SSATA_SLOAD
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 169: 		{GPIO_SKL_H_GPP_G0,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_0_FANTACH0_FANTACH0IE
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 170: 		{GPIO_SKL_H_GPP_G1,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_1_FANTACH1_FANTACH1IE
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 171: 		{GPIO_SKL_H_GPP_G2,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_2_FANTACH2_FANTACH2IE
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 172: 		{GPIO_SKL_H_GPP_G3,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_3_FANTACH3_FANTACH3IE
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 173: 		{GPIO_SKL_H_GPP_G4,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_4_FANTACH4_FANTACH4IE
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 174: 		{GPIO_SKL_H_GPP_G5,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_5_FANTACH5_FANTACH5IE
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 175: 		{GPIO_SKL_H_GPP_G6,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_6_FANTACH6_FANTACH6IE
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 176: 		{GPIO_SKL_H_GPP_G7,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_7_FANTACH7_FANTACH7IE
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 177: 		{GPIO_SKL_H_GPP_G8,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_8_FANPWM0_FANPWM0IE
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 178: 		{GPIO_SKL_H_GPP_G9,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_9_FANPWM1_FANPWM1IE
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 179: 		{GPIO_SKL_H_GPP_G10, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_10_FANPWM2_FANPWM2IE
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 180: 		{GPIO_SKL_H_GPP_G11, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_11_FANPWM3_FANPWM3IE
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 181: 		{GPIO_SKL_H_GPP_G12, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_12
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 182: 		{GPIO_SKL_H_GPP_G13, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_13
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 183: 		{GPIO_SKL_H_GPP_G14, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_14
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 184: 		{GPIO_SKL_H_GPP_G15, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_15
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 185: 		{GPIO_SKL_H_GPP_G16, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_16
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 186: 		{GPIO_SKL_H_GPP_G17, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_17_ADR_COMPLETE
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 187: 		{GPIO_SKL_H_GPP_G18, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_18_FM_NMI_EVENT_N
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 188: 		{GPIO_SKL_H_GPP_G19, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_19_FM_SMI_ACTIVE_N
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 190: 		{GPIO_SKL_H_GPP_G21, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_21_SSATA_DEVSLP1
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 191: 		{GPIO_SKL_H_GPP_G22, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_G_22_SSATA_DEVSLP2
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 192: 		{GPIO_SKL_H_GPP_G23, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_23_SSATAXPCIE0_SSATAGP0
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 194: 		{GPIO_SKL_H_GPP_H0,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_H_0_SRCCLKREQ6_N
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 195: 		{GPIO_SKL_H_GPP_H1,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_H_1_SRCCLKREQ7_N
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 196: 		{GPIO_SKL_H_GPP_H2,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_H_2_SRCCLKREQ8_N
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 197: 		{GPIO_SKL_H_GPP_H3,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_H_3_SRCCLKREQ9_N
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 198: 		{GPIO_SKL_H_GPP_H4,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_H_4_SRCCLKREQ10_N
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 200: 		{GPIO_SKL_H_GPP_H6,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_H_6_SRCCLKREQ12_N
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 201: 		{GPIO_SKL_H_GPP_H7,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_H_7_SRCCLKREQ13_N
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 202: 		{GPIO_SKL_H_GPP_H8,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_H_8_SRCCLKREQ14_N
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 203: 		{GPIO_SKL_H_GPP_H9,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_H_9_SRCCLKREQ15_N
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 206: 		{GPIO_SKL_H_GPP_H12, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_H_12_SML2ALERT_N_IE
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 209: 		{GPIO_SKL_H_GPP_H15, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_H_15_SML3ALERT_N_IE
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 212: 		{GPIO_SKL_H_GPP_H18, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_H_18_SML4ALERT_N_IE
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 213: 		{GPIO_SKL_H_GPP_H19, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_H_19_SSATAXPCIE1_SSATAGP1
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 214: 		{GPIO_SKL_H_GPP_H20, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_H_20_SSATAXPCIE2_SSATAGP2
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 215: 		{GPIO_SKL_H_GPP_H21, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_H_21_SSATAXPCIE3_SSATAGP3
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 216: 		{GPIO_SKL_H_GPP_H22, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_H_22_SSATAXPCIE4_SSATAGP4
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 217: 		{GPIO_SKL_H_GPP_H23, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_H_23_SSATAXPCIE5_SSATAGP5
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 219: 		{GPIO_SKL_H_GPP_I0,  { GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_I_0_GBE_TDO
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 220: 		{GPIO_SKL_H_GPP_I1,  { GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_I_1_GBE_TCK
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 221: 		{GPIO_SKL_H_GPP_I2,  { GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_I_2_GBE_TMS
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 222: 		{GPIO_SKL_H_GPP_I3,  { GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_I_3_GBE_TDI
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 223: 		{GPIO_SKL_H_GPP_I4,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_I_4_DO_RESET_IN_N
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 224: 		{GPIO_SKL_H_GPP_I5,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_I_5_DO_RESET_OUT_N
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 225: 		{GPIO_SKL_H_GPP_I6,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_I_6_RESET_DONE
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 226: 		{GPIO_SKL_H_GPP_I7,  { GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_I_7_JTAG_GBE_TRST_N
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 227: 		{GPIO_SKL_H_GPP_I8,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_I_8_GBE_PCI_DIS
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 228: 		{GPIO_SKL_H_GPP_I9,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_I_9_GBE_LAN_DIS
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 229: 		{GPIO_SKL_H_GPP_I10, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_I_10
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 231: 		{GPIO_SKL_H_GPP_J0,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_0_LAN_LED_P0_0
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 232: 		{GPIO_SKL_H_GPP_J1,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_1_LAN_LED_P0_1
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 233: 		{GPIO_SKL_H_GPP_J2,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_2_LAN_LED_P1_0
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 234: 		{GPIO_SKL_H_GPP_J3,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_3_LAN_LED_P1_1
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 235: 		{GPIO_SKL_H_GPP_J4,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_4_LAN_LED_P2_0
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 236: 		{GPIO_SKL_H_GPP_J5,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_5_LAN_LED_P2_1
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 237: 		{GPIO_SKL_H_GPP_J6,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_6_LAN_LED_P3_0
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 238: 		{GPIO_SKL_H_GPP_J7,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_7_LAN_LED_P3_1
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 239: 		{GPIO_SKL_H_GPP_J8,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_8_LAN_I2C_SCL_MDC_P0
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 240: 		{GPIO_SKL_H_GPP_J9,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_9_LAN_I2C_SDA_MDIO_P0
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 241: 		{GPIO_SKL_H_GPP_J10, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_10_LAN_I2C_SCL_MDC_P1
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 242: 		{GPIO_SKL_H_GPP_J11, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_11_LAN_I2C_SDA_MDIO_P1
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 243: 		{GPIO_SKL_H_GPP_J12, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_12_LAN_I2C_SCL_MDC_P2
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 244: 		{GPIO_SKL_H_GPP_J13, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_13_LAN_I2C_SDA_MDIO_P2
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 245: 		{GPIO_SKL_H_GPP_J14, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_14_LAN_I2C_SCL_MDC_P3
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 246: 		{GPIO_SKL_H_GPP_J15, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_15_LAN_I2C_SDA_MDIO_P3
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 247: 		{GPIO_SKL_H_GPP_J16, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_16_LAN_SDP_P0_0
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 248: 		{GPIO_SKL_H_GPP_J17, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_17_LAN_SDP_P0_1
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 249: 		{GPIO_SKL_H_GPP_J18, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_18_LAN_SDP_P1_0
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 250: 		{GPIO_SKL_H_GPP_J19, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_19_LAN_SDP_P1_1
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 251: 		{GPIO_SKL_H_GPP_J20, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_20_LAN_SDP_P2_0
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 252: 		{GPIO_SKL_H_GPP_J21, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_21_LAN_SDP_P2_1
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 253: 		{GPIO_SKL_H_GPP_J22, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_22_LAN_SDP_P3_0
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 254: 		{GPIO_SKL_H_GPP_J23, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_23_LAN_SDP_P3_1
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 256: 		{GPIO_SKL_H_GPP_K0,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_K_0_LAN_NCSI_CLK_IN
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 257: 		{GPIO_SKL_H_GPP_K1,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_K_1_LAN_NCSI_TXD0
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 258: 		{GPIO_SKL_H_GPP_K2,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_K_2_LAN_NCSI_TXD1
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 259: 		{GPIO_SKL_H_GPP_K3,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_K_3_LAN_NCSI_TX_EN
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 260: 		{GPIO_SKL_H_GPP_K4,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_K_4_LAN_NCSI_CRS_DV
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 261: 		{GPIO_SKL_H_GPP_K5,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_K_5_LAN_NCSI_RXD0
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 262: 		{GPIO_SKL_H_GPP_K6,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_K_6_LAN_NCSI_RXD1
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 263: 		{GPIO_SKL_H_GPP_K7,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_K_7
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 264: 		{GPIO_SKL_H_GPP_K8,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,  GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_K_8_LAN_NCSI_ARB_IN
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 265: 		{GPIO_SKL_H_GPP_K9,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_K_9_LAN_NCSI_ARB_OUT
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 266: 		{GPIO_SKL_H_GPP_K10, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_K_10_PE_RST_N
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 268: 		{GPIO_SKL_H_GPP_L2,  { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_2_TESTCH0_D0
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 269: 		{GPIO_SKL_H_GPP_L3,  { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_3_TESTCH0_D1
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 270: 		{GPIO_SKL_H_GPP_L4,  { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_4_TESTCH0_D2
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 271: 		{GPIO_SKL_H_GPP_L5,  { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_5_TESTCH0_D3
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 272: 		{GPIO_SKL_H_GPP_L6,  { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_6_TESTCH0_D4
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 273: 		{GPIO_SKL_H_GPP_L7,  { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_7_TESTCH0_D5
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 274: 		{GPIO_SKL_H_GPP_L8,  { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_8_TESTCH0_D6
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 275: 		{GPIO_SKL_H_GPP_L9,  { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_9_TESTCH0_D7
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 276: 		{GPIO_SKL_H_GPP_L10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_10_TESTCH0_CLK
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 277: 		{GPIO_SKL_H_GPP_L11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_11_TESTCH1_D0
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 278: 		{GPIO_SKL_H_GPP_L12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_12_TESTCH1_D1
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 279: 		{GPIO_SKL_H_GPP_L13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_13_TESTCH1_D2
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 280: 		{GPIO_SKL_H_GPP_L14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_14_TESTCH1_D3
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 281: 		{GPIO_SKL_H_GPP_L15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_15_TESTCH1_D4
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 282: 		{GPIO_SKL_H_GPP_L16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_16_TESTCH1_D5
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 283: 		{GPIO_SKL_H_GPP_L17, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_17_TESTCH1_D6
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 284: 		{GPIO_SKL_H_GPP_L18, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_18_TESTCH1_D7
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 285: 		{GPIO_SKL_H_GPP_L19, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_19_TESTCH1_CLK
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 288: 		{GPIO_SKL_H_GPD1,		{ GpioPadModeGpio,   GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPD_1_ACPRESENT
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 289: 		{GPIO_SKL_H_GPD2,		{ GpioPadModeGpio,   GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPD_2_GBE_WAKE_N
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 290: 		{GPIO_SKL_H_GPD3,		{ GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPD_3_PWRBTNB_N
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 291: 		{GPIO_SKL_H_GPD4,		{ GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPD_4_SLP_S3B
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 292: 		{GPIO_SKL_H_GPD5,		{ GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPD_5_SLP_S4B
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 293: 		{GPIO_SKL_H_GPD6,		{ GpioPadModeGpio,   GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPD_6_SLPA_N
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 294: 		{GPIO_SKL_H_GPD7,		{ GpioPadModeGpio,   GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPD_7
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 295: 		{GPIO_SKL_H_GPD8,		{ GpioPadModeGpio,   GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPD_8_CLK_33K_PCH_SUSCLK_PLD
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 296: 		{GPIO_SKL_H_GPD9,		{ GpioPadModeGpio,   GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPD_9
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 297: 		{GPIO_SKL_H_GPD10,   { GpioPadModeGpio,   GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPD_10_FM_SLPS5_N
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 298: 		{GPIO_SKL_H_GPD11,   { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPD_11_GBEPHY
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
File src/mainboard/ocp/tiogapass/skxsp_tp_iio.h:

https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 48:   // PortIndex |  HidePort  | DeEmphasis | PortLinkSpeed | MaxPayload | DfxDnTxPreset | DfxRxPreset | DfxUpTxPreset | Sris | PcieCommonClock | NtbPpd               | NtbSplitBar | NtbBarSizePBar23 | NtbBarSizePBar4 | NtbBarSizePBar5 | NtbBarSizePBar45 | NtbBarSizeSBar23 | NtbBarSizeSBar4 | NtbBarSizeSbar5 | NtbBarSizeSBar45 | NtbSBar01Prefetch | NtbXlinkCtlOverride
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 49: 	{ PORT_1A, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 50: 	{ PORT_1B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 51: 	{ PORT_1C, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 52: 	{ PORT_1D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 53: 	{ PORT_2A, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 54: 	{ PORT_2B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 55: 	{ PORT_2C, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 56: 	{ PORT_2D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 57: 	{ PORT_3A, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 58: 	{ PORT_3B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 59: 	{ PORT_3C, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
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https://review.coreboot.org/c/coreboot/+/38549/1/src/mainboard/ocp/tiogapass... 
PS1, Line 60: 	{ PORT_3D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
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[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38549 )

Change subject: Add support for OCP platform TiogaPass
......................................................................

Patch Set 2:

(253 comments)

https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
File src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h:

https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 30: 		{GPIO_SKL_H_GPP_A0,  { GpioPadModeGpio,    GpioHostOwnGpio, GpioDirIn,    GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_0_LPC_RCIN_N_ESPI_ALERT1_N
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 31: 		{GPIO_SKL_H_GPP_A1,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_1_LAD_0_ESPI_IO_0
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 32: 		{GPIO_SKL_H_GPP_A2,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_2_LAD_1_ESPI_IO_1
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 33: 		{GPIO_SKL_H_GPP_A3,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_3_LAD_2_ESPI_IO_2
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 34: 		{GPIO_SKL_H_GPP_A4,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_4_LAD_3_ESPI_IO_3
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 35: 		{GPIO_SKL_H_GPP_A5,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_5_LPC_LFRAME_N_ESPI_CS0_N
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 36: 		{GPIO_SKL_H_GPP_A6,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_6_IRQ_LPC_SERIRQ_ESPI_CS1_N
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 37: 		{GPIO_SKL_H_GPP_A7,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_7_IRQ_LPC_PIRQA_N_ESPI_ALERT0_N
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 38: 		{GPIO_SKL_H_GPP_A8,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_8_FM_LPC_CLKRUN_N
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 39: 		{GPIO_SKL_H_GPP_A9,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_9_CLKOUT_LPC0_ESPI_CLK
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 40: 		{GPIO_SKL_H_GPP_A10, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_10_CLKOUT_LPC1
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 41: 		{GPIO_SKL_H_GPP_A11, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_11_FM_LPC_PME_N
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 42: 		{GPIO_SKL_H_GPP_A12, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_A_12_BMBUSY_N_SXEXITHLDOFF_N
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 43: 		{GPIO_SKL_H_GPP_A13, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_13_SUSWARN_N_SUSPWRDNACK
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 44: 		{GPIO_SKL_H_GPP_A14, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_14_ESPI_RESET_N
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 45: 		{GPIO_SKL_H_GPP_A15, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_15_SUSACK_N
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 46: 		{GPIO_SKL_H_GPP_A16, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_16_CLKOUT_LPC2
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 47: 		{GPIO_SKL_H_GPP_A17, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_17
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 48: 		{GPIO_SKL_H_GPP_A18, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_18
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 50: 		{GPIO_SKL_H_GPP_A20, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_20
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 51: 		{GPIO_SKL_H_GPP_A21, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutLow,		 GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_21
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 52: 		{GPIO_SKL_H_GPP_A22, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_22
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 53: 		{GPIO_SKL_H_GPP_A23, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_23
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 55: 		{GPIO_SKL_H_GPP_B0,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_0_CORE_VID_0
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 56: 		{GPIO_SKL_H_GPP_B1,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_1_CORE_VID_1
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 57: 		{GPIO_SKL_H_GPP_B2,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_2_VRALERT_N
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 58: 		{GPIO_SKL_H_GPP_B3,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_3_CPU_GP2
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 59: 		{GPIO_SKL_H_GPP_B4,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_4_CPU_GP3
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 60: 		{GPIO_SKL_H_GPP_B5,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_5_SRCCLKREQ0_N
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 61: 		{GPIO_SKL_H_GPP_B6,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_B_6_SRCCLKREQ1_N
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 62: 		{GPIO_SKL_H_GPP_B7,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_B_7_SRCCLKREQ2_N
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 63: 		{GPIO_SKL_H_GPP_B8,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_8_SRCCLKREQ3_N
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 64: 		{GPIO_SKL_H_GPP_B9,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_9_SRCCLKREQ4_N
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 65: 		{GPIO_SKL_H_GPP_B10, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_10_SRCCLKREQ5_N
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 66: 		{GPIO_SKL_H_GPP_B11, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutLow,		 GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_11
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 67: 		{GPIO_SKL_H_GPP_B12, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_12_GLB_RST_WARN_N
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 68: 		{GPIO_SKL_H_GPP_B13, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_13_RST_PLTRST_N
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 69: 		{GPIO_SKL_H_GPP_B14, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_14_FM_PCH_BIOS_RCVR_SPKR
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 70: 		{GPIO_SKL_H_GPP_B15, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_15
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 71: 		{GPIO_SKL_H_GPP_B16, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_16
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 72: 		{GPIO_SKL_H_GPP_B17, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_17
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 73: 		{GPIO_SKL_H_GPP_B18, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_18
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 74: 		{GPIO_SKL_H_GPP_B19, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutLow,		 GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_19
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 75: 		{GPIO_SKL_H_GPP_B20, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_20
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 76: 		{GPIO_SKL_H_GPP_B21, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_21
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 77: 		{GPIO_SKL_H_GPP_B22, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_22
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 78: 		{GPIO_SKL_H_GPP_B23, { GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut,   GpioOutLow,		 GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock} }, //GPP_B_23_MEIE_SML1ALRT_N_PHOT_N
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 82: 		{GPIO_SKL_H_GPP_C2,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_C_2_SMBALERT_N
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 85: 		{GPIO_SKL_H_GPP_C5,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPP_C_5_SML0ALERT_IE_N
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 88: 		{GPIO_SKL_H_GPP_C8,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_8
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 89: 		{GPIO_SKL_H_GPP_C9,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutLow,		 GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_9
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 90: 		{GPIO_SKL_H_GPP_C10, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_C_10
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 91: 		{GPIO_SKL_H_GPP_C11, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_11
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 92: 		{GPIO_SKL_H_GPP_C12, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_C_12
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 93: 		{GPIO_SKL_H_GPP_C13, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_C_13
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 94: 		{GPIO_SKL_H_GPP_C14, { GpioPadModeGpio,		GpioHostOwnAcpi, GpioDirIn,		GpioOutDefault, GpioIntLevel | GpioIntSci, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_C_14
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 95: 		{GPIO_SKL_H_GPP_C15, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_15
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 96: 		{GPIO_SKL_H_GPP_C16, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_16
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 97: 		{GPIO_SKL_H_GPP_C17, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_17
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 98: 		{GPIO_SKL_H_GPP_C18, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_18
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 99: 		{GPIO_SKL_H_GPP_C19, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_19
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 101: 		{GPIO_SKL_H_GPP_C21, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_21
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 102: 		{GPIO_SKL_H_GPP_C22, { GpioPadModeGpio,		GpioHostOwnAcpi, GpioDirIn,		GpioOutDefault, GpioIntLevel | GpioIntSmi, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_C_22
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 103: 		{GPIO_SKL_H_GPP_C23, { GpioPadModeGpio,		GpioHostOwnAcpi, GpioDirIn,		GpioOutDefault, GpioIntLevel | GpioIntSmi, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_C_23
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 105: 		{GPIO_SKL_H_GPP_D0,  { GpioPadModeGpio,		GpioHostOwnAcpi, GpioDirIn,		GpioOutDefault, GpioIntLevel | GpioIntSmi, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_D_0
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 106: 		{GPIO_SKL_H_GPP_D1,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_1
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 107: 		{GPIO_SKL_H_GPP_D2,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_D_2
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 108: 		{GPIO_SKL_H_GPP_D3,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_D_3
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 109: 		{GPIO_SKL_H_GPP_D4,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutLow,		 GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_4
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 110: 		{GPIO_SKL_H_GPP_D5,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_5
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 111: 		{GPIO_SKL_H_GPP_D6,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_6
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 112: 		{GPIO_SKL_H_GPP_D7,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_7
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 113: 		{GPIO_SKL_H_GPP_D8,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_8
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 114: 		{GPIO_SKL_H_GPP_D9,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_9_SSATA_DEVSLP3
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 115: 		{GPIO_SKL_H_GPP_D10, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_10_SSATA_DEVSLP4
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 116: 		{GPIO_SKL_H_GPP_D11, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_11_SSATA_DEVSLP5
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 117: 		{GPIO_SKL_H_GPP_D12, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_12_SSATA_SDATAOUT1
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 118: 		{GPIO_SKL_H_GPP_D13, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_13_SML0BLCK_IE
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 119: 		{GPIO_SKL_H_GPP_D14, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_14_SML0BDATA_IE
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 120: 		{GPIO_SKL_H_GPP_D15, { GpioPadModeNative3, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_15_SSATA_SDATAOUT0
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 121: 		{GPIO_SKL_H_GPP_D16, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_16_SML0BALERT_IE_N
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 122: 		{GPIO_SKL_H_GPP_D17, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_17
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 123: 		{GPIO_SKL_H_GPP_D18, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_18
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 124: 		{GPIO_SKL_H_GPP_D19, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutLow,		 GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock | GpioOutputStateLock} }, //GPP_D_19
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 125: 		{GPIO_SKL_H_GPP_D20, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_20_TP_PCH_GPP_D_20
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 126: 		{GPIO_SKL_H_GPP_D21, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_21_IE_URAT_RX
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 127: 		{GPIO_SKL_H_GPP_D22, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_22_IE_URAT_TX
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 128: 		{GPIO_SKL_H_GPP_D23, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_23
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 130: 		{GPIO_SKL_H_GPP_E0,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntLevel | GpioIntSmi, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_0_SATAXPCIE0_SATAGP0
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 131: 		{GPIO_SKL_H_GPP_E1,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntLevel | GpioIntSmi, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_1_SATAXPCIE1_SATAGP1
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 132: 		{GPIO_SKL_H_GPP_E2,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_2_SATAXPCIE2_SATAGP2
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 133: 		{GPIO_SKL_H_GPP_E3,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_3_CPU_GP0
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 134: 		{GPIO_SKL_H_GPP_E4,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_4_SATA_DEVSLP0
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 135: 		{GPIO_SKL_H_GPP_E5,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_5_SATA_DEVSLP1
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 136: 		{GPIO_SKL_H_GPP_E6,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_6_SATA_DEVSLP2
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 137: 		{GPIO_SKL_H_GPP_E7,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_7_CPU_GP1
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 138: 		{GPIO_SKL_H_GPP_E8,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_8_SATA_LED_N
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 139: 		{GPIO_SKL_H_GPP_E9,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_9_USB2_OC0_N
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 140: 		{GPIO_SKL_H_GPP_E10, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_10_USB2_OC1_N
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 141: 		{GPIO_SKL_H_GPP_E11, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_11_USB2_OC2_N
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 142: 		{GPIO_SKL_H_GPP_E12, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_12_USB2_OC3_N
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 144: 		{GPIO_SKL_H_GPP_F0,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_F_0_SATAXPCIE3_SATAGP3
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 145: 		{GPIO_SKL_H_GPP_F1,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_F_1_SATAXPCIE4_SATAGP4
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 146: 		{GPIO_SKL_H_GPP_F2,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_F_2_SATAXPCIE5_SATAGP5
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 147: 		{GPIO_SKL_H_GPP_F3,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_F_3_SATAXPCIE6_SATAGP6
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 148: 		{GPIO_SKL_H_GPP_F4,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_F_4_SATAXPCIE7_SATAGP7
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 149: 		{GPIO_SKL_H_GPP_F5,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_F_5_SATA_DEVSLP3
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 150: 		{GPIO_SKL_H_GPP_F6,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_F_6_SATA_DEVSLP4
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 151: 		{GPIO_SKL_H_GPP_F7,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_F_7_SATA_DEVSLP5
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 152: 		{GPIO_SKL_H_GPP_F8,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_F_8_SATA_DEVSLP6
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 153: 		{GPIO_SKL_H_GPP_F9,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_F_9_SATA_DEVSLP7
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 154: 		{GPIO_SKL_H_GPP_F10, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_10_SATA_SCLOCK
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 155: 		{GPIO_SKL_H_GPP_F11, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_11_SATA_SLOAD
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 156: 		{GPIO_SKL_H_GPP_F12, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_12_SATA_SDATAOUT1
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 157: 		{GPIO_SKL_H_GPP_F13, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_13_SATA_SDATAOUT0
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 158: 		{GPIO_SKL_H_GPP_F14, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_14_SSATA_LED_N
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 159: 		{GPIO_SKL_H_GPP_F15, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_15_USB2_OC4_N
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 160: 		{GPIO_SKL_H_GPP_F16, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_16_USB2_OC5_N
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 161: 		{GPIO_SKL_H_GPP_F17, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_17_USB2_OC6_N
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 162: 		{GPIO_SKL_H_GPP_F18, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_18_USB2_OC7_N
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 163: 		{GPIO_SKL_H_GPP_F19, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_19_LAN_SMBCLK
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 164: 		{GPIO_SKL_H_GPP_F20, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_20_LAN_SMBDATA
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 165: 		{GPIO_SKL_H_GPP_F21, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_21_LAN_SMBALERT_N
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 166: 		{GPIO_SKL_H_GPP_F22, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_22_SSATA_SCLOCK
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 167: 		{GPIO_SKL_H_GPP_F23, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_23_SSATA_SLOAD
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 169: 		{GPIO_SKL_H_GPP_G0,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_0_FANTACH0_FANTACH0IE
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 170: 		{GPIO_SKL_H_GPP_G1,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_1_FANTACH1_FANTACH1IE
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 171: 		{GPIO_SKL_H_GPP_G2,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_2_FANTACH2_FANTACH2IE
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 172: 		{GPIO_SKL_H_GPP_G3,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_3_FANTACH3_FANTACH3IE
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 173: 		{GPIO_SKL_H_GPP_G4,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_4_FANTACH4_FANTACH4IE
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 174: 		{GPIO_SKL_H_GPP_G5,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_5_FANTACH5_FANTACH5IE
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 175: 		{GPIO_SKL_H_GPP_G6,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_6_FANTACH6_FANTACH6IE
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 176: 		{GPIO_SKL_H_GPP_G7,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_7_FANTACH7_FANTACH7IE
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 177: 		{GPIO_SKL_H_GPP_G8,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_8_FANPWM0_FANPWM0IE
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 178: 		{GPIO_SKL_H_GPP_G9,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_9_FANPWM1_FANPWM1IE
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 179: 		{GPIO_SKL_H_GPP_G10, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_10_FANPWM2_FANPWM2IE
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 180: 		{GPIO_SKL_H_GPP_G11, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_11_FANPWM3_FANPWM3IE
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 181: 		{GPIO_SKL_H_GPP_G12, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_12
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 182: 		{GPIO_SKL_H_GPP_G13, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_13
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 183: 		{GPIO_SKL_H_GPP_G14, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_14
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 184: 		{GPIO_SKL_H_GPP_G15, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_15
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 185: 		{GPIO_SKL_H_GPP_G16, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_16
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 186: 		{GPIO_SKL_H_GPP_G17, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_17_ADR_COMPLETE
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 187: 		{GPIO_SKL_H_GPP_G18, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_18_FM_NMI_EVENT_N
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 188: 		{GPIO_SKL_H_GPP_G19, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_19_FM_SMI_ACTIVE_N
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 190: 		{GPIO_SKL_H_GPP_G21, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_21_SSATA_DEVSLP1
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 191: 		{GPIO_SKL_H_GPP_G22, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_G_22_SSATA_DEVSLP2
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 192: 		{GPIO_SKL_H_GPP_G23, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_23_SSATAXPCIE0_SSATAGP0
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 194: 		{GPIO_SKL_H_GPP_H0,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_H_0_SRCCLKREQ6_N
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 195: 		{GPIO_SKL_H_GPP_H1,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_H_1_SRCCLKREQ7_N
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 196: 		{GPIO_SKL_H_GPP_H2,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_H_2_SRCCLKREQ8_N
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 197: 		{GPIO_SKL_H_GPP_H3,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_H_3_SRCCLKREQ9_N
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 198: 		{GPIO_SKL_H_GPP_H4,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_H_4_SRCCLKREQ10_N
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 200: 		{GPIO_SKL_H_GPP_H6,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_H_6_SRCCLKREQ12_N
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 201: 		{GPIO_SKL_H_GPP_H7,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_H_7_SRCCLKREQ13_N
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 202: 		{GPIO_SKL_H_GPP_H8,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_H_8_SRCCLKREQ14_N
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 203: 		{GPIO_SKL_H_GPP_H9,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_H_9_SRCCLKREQ15_N
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 206: 		{GPIO_SKL_H_GPP_H12, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_H_12_SML2ALERT_N_IE
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 209: 		{GPIO_SKL_H_GPP_H15, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_H_15_SML3ALERT_N_IE
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 212: 		{GPIO_SKL_H_GPP_H18, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_H_18_SML4ALERT_N_IE
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 213: 		{GPIO_SKL_H_GPP_H19, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_H_19_SSATAXPCIE1_SSATAGP1
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 214: 		{GPIO_SKL_H_GPP_H20, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_H_20_SSATAXPCIE2_SSATAGP2
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 215: 		{GPIO_SKL_H_GPP_H21, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_H_21_SSATAXPCIE3_SSATAGP3
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 216: 		{GPIO_SKL_H_GPP_H22, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_H_22_SSATAXPCIE4_SSATAGP4
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 217: 		{GPIO_SKL_H_GPP_H23, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_H_23_SSATAXPCIE5_SSATAGP5
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 219: 		{GPIO_SKL_H_GPP_I0,  { GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_I_0_GBE_TDO
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 220: 		{GPIO_SKL_H_GPP_I1,  { GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_I_1_GBE_TCK
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 221: 		{GPIO_SKL_H_GPP_I2,  { GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_I_2_GBE_TMS
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 222: 		{GPIO_SKL_H_GPP_I3,  { GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_I_3_GBE_TDI
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 223: 		{GPIO_SKL_H_GPP_I4,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_I_4_DO_RESET_IN_N
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 224: 		{GPIO_SKL_H_GPP_I5,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_I_5_DO_RESET_OUT_N
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 225: 		{GPIO_SKL_H_GPP_I6,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_I_6_RESET_DONE
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 226: 		{GPIO_SKL_H_GPP_I7,  { GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_I_7_JTAG_GBE_TRST_N
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 227: 		{GPIO_SKL_H_GPP_I8,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_I_8_GBE_PCI_DIS
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 228: 		{GPIO_SKL_H_GPP_I9,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_I_9_GBE_LAN_DIS
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 229: 		{GPIO_SKL_H_GPP_I10, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_I_10
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 231: 		{GPIO_SKL_H_GPP_J0,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_0_LAN_LED_P0_0
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 232: 		{GPIO_SKL_H_GPP_J1,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_1_LAN_LED_P0_1
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 233: 		{GPIO_SKL_H_GPP_J2,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_2_LAN_LED_P1_0
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 234: 		{GPIO_SKL_H_GPP_J3,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_3_LAN_LED_P1_1
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 235: 		{GPIO_SKL_H_GPP_J4,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_4_LAN_LED_P2_0
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 236: 		{GPIO_SKL_H_GPP_J5,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_5_LAN_LED_P2_1
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 237: 		{GPIO_SKL_H_GPP_J6,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_6_LAN_LED_P3_0
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 238: 		{GPIO_SKL_H_GPP_J7,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_7_LAN_LED_P3_1
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 239: 		{GPIO_SKL_H_GPP_J8,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_8_LAN_I2C_SCL_MDC_P0
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 240: 		{GPIO_SKL_H_GPP_J9,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_9_LAN_I2C_SDA_MDIO_P0
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 241: 		{GPIO_SKL_H_GPP_J10, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_10_LAN_I2C_SCL_MDC_P1
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 242: 		{GPIO_SKL_H_GPP_J11, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_11_LAN_I2C_SDA_MDIO_P1
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 243: 		{GPIO_SKL_H_GPP_J12, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_12_LAN_I2C_SCL_MDC_P2
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 244: 		{GPIO_SKL_H_GPP_J13, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_13_LAN_I2C_SDA_MDIO_P2
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 245: 		{GPIO_SKL_H_GPP_J14, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_14_LAN_I2C_SCL_MDC_P3
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 246: 		{GPIO_SKL_H_GPP_J15, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_15_LAN_I2C_SDA_MDIO_P3
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 247: 		{GPIO_SKL_H_GPP_J16, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_16_LAN_SDP_P0_0
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 248: 		{GPIO_SKL_H_GPP_J17, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_17_LAN_SDP_P0_1
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 249: 		{GPIO_SKL_H_GPP_J18, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_18_LAN_SDP_P1_0
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 250: 		{GPIO_SKL_H_GPP_J19, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_19_LAN_SDP_P1_1
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 251: 		{GPIO_SKL_H_GPP_J20, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_20_LAN_SDP_P2_0
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 252: 		{GPIO_SKL_H_GPP_J21, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_21_LAN_SDP_P2_1
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 253: 		{GPIO_SKL_H_GPP_J22, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_22_LAN_SDP_P3_0
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 254: 		{GPIO_SKL_H_GPP_J23, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_23_LAN_SDP_P3_1
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 256: 		{GPIO_SKL_H_GPP_K0,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_K_0_LAN_NCSI_CLK_IN
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 257: 		{GPIO_SKL_H_GPP_K1,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_K_1_LAN_NCSI_TXD0
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 258: 		{GPIO_SKL_H_GPP_K2,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_K_2_LAN_NCSI_TXD1
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 259: 		{GPIO_SKL_H_GPP_K3,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_K_3_LAN_NCSI_TX_EN
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 260: 		{GPIO_SKL_H_GPP_K4,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_K_4_LAN_NCSI_CRS_DV
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 261: 		{GPIO_SKL_H_GPP_K5,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_K_5_LAN_NCSI_RXD0
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 262: 		{GPIO_SKL_H_GPP_K6,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_K_6_LAN_NCSI_RXD1
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 263: 		{GPIO_SKL_H_GPP_K7,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_K_7
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 264: 		{GPIO_SKL_H_GPP_K8,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,  GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_K_8_LAN_NCSI_ARB_IN
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 265: 		{GPIO_SKL_H_GPP_K9,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_K_9_LAN_NCSI_ARB_OUT
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 266: 		{GPIO_SKL_H_GPP_K10, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_K_10_PE_RST_N
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 268: 		{GPIO_SKL_H_GPP_L2,  { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_2_TESTCH0_D0
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 269: 		{GPIO_SKL_H_GPP_L3,  { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_3_TESTCH0_D1
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 270: 		{GPIO_SKL_H_GPP_L4,  { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_4_TESTCH0_D2
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 271: 		{GPIO_SKL_H_GPP_L5,  { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_5_TESTCH0_D3
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 272: 		{GPIO_SKL_H_GPP_L6,  { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_6_TESTCH0_D4
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 273: 		{GPIO_SKL_H_GPP_L7,  { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_7_TESTCH0_D5
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 274: 		{GPIO_SKL_H_GPP_L8,  { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_8_TESTCH0_D6
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 275: 		{GPIO_SKL_H_GPP_L9,  { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_9_TESTCH0_D7
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 276: 		{GPIO_SKL_H_GPP_L10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_10_TESTCH0_CLK
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 277: 		{GPIO_SKL_H_GPP_L11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_11_TESTCH1_D0
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 278: 		{GPIO_SKL_H_GPP_L12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_12_TESTCH1_D1
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 279: 		{GPIO_SKL_H_GPP_L13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_13_TESTCH1_D2
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 280: 		{GPIO_SKL_H_GPP_L14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_14_TESTCH1_D3
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 281: 		{GPIO_SKL_H_GPP_L15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_15_TESTCH1_D4
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 282: 		{GPIO_SKL_H_GPP_L16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_16_TESTCH1_D5
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 283: 		{GPIO_SKL_H_GPP_L17, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_17_TESTCH1_D6
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 284: 		{GPIO_SKL_H_GPP_L18, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_18_TESTCH1_D7
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 285: 		{GPIO_SKL_H_GPP_L19, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_19_TESTCH1_CLK
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 288: 		{GPIO_SKL_H_GPD1,		{ GpioPadModeGpio,   GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPD_1_ACPRESENT
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 289: 		{GPIO_SKL_H_GPD2,		{ GpioPadModeGpio,   GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPD_2_GBE_WAKE_N
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 290: 		{GPIO_SKL_H_GPD3,		{ GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPD_3_PWRBTNB_N
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 291: 		{GPIO_SKL_H_GPD4,		{ GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPD_4_SLP_S3B
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 292: 		{GPIO_SKL_H_GPD5,		{ GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPD_5_SLP_S4B
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 293: 		{GPIO_SKL_H_GPD6,		{ GpioPadModeGpio,   GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPD_6_SLPA_N
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 294: 		{GPIO_SKL_H_GPD7,		{ GpioPadModeGpio,   GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPD_7
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 295: 		{GPIO_SKL_H_GPD8,		{ GpioPadModeGpio,   GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPD_8_CLK_33K_PCH_SUSCLK_PLD
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 296: 		{GPIO_SKL_H_GPD9,		{ GpioPadModeGpio,   GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPD_9
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 297: 		{GPIO_SKL_H_GPD10,   { GpioPadModeGpio,   GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPD_10_FM_SLPS5_N
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 298: 		{GPIO_SKL_H_GPD11,   { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPD_11_GBEPHY
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
File src/mainboard/ocp/tiogapass/skxsp_tp_iio.h:

https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 48:   // PortIndex |  HidePort  | DeEmphasis | PortLinkSpeed | MaxPayload | DfxDnTxPreset | DfxRxPreset | DfxUpTxPreset | Sris | PcieCommonClock | NtbPpd               | NtbSplitBar | NtbBarSizePBar23 | NtbBarSizePBar4 | NtbBarSizePBar5 | NtbBarSizePBar45 | NtbBarSizeSBar23 | NtbBarSizeSBar4 | NtbBarSizeSbar5 | NtbBarSizeSBar45 | NtbSBar01Prefetch | NtbXlinkCtlOverride
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 49: 	{ PORT_1A, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 50: 	{ PORT_1B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 51: 	{ PORT_1C, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 52: 	{ PORT_1D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 53: 	{ PORT_2A, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 54: 	{ PORT_2B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 55: 	{ PORT_2C, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 56: 	{ PORT_2D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 57: 	{ PORT_3A, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 58: 	{ PORT_3B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 59: 	{ PORT_3C, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
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https://review.coreboot.org/c/coreboot/+/38549/2/src/mainboard/ocp/tiogapass... 
PS2, Line 60: 	{ PORT_3D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
line over 96 characters

[Jonathan Zhang (Code Review)]

Hello build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38549

to look at the new patch set (#3).

Change subject: Add support for OCP platform TiogaPass
......................................................................

Add support for OCP platform TiogaPass

OCP platform Tiogapass is a 2 socket server platform based on
Intel Skylake-SP SOC. The chipset includes Lewisburg PCH.

Following ACPI tables are added:
DSDT/SSDT, MADT, FACP, FACS, HPET, MCFG, SLIT, SRAT, DMAR

This patchset was tested on a Tiogapass board. It booted with
Linux kernel 4.16.0; lscpu command shows all 72 cpus (2 sockets,
18 cores, 2 thread per core); ifconfig command shows
networking is up from Mellanox ConnectX-4 PCIe NIC card.

Known issues:
1. MP init does not work reliably, this causes reboot stability,
eg. some reboots does not boot up successfully.
2. c6 state is not supported.
3. "lspci -vvv" causes segmentation fault.

Signed-off-by: Jonathan Zhang 
Signed-off-by: Reddy Chagam 
Change-Id: I29868f03037d1887b90dfb19d15aee83c456edce
---
A src/mainboard/ocp/Kconfig
A src/mainboard/ocp/Kconfig.name
A src/mainboard/ocp/tiogapass/Kconfig
A src/mainboard/ocp/tiogapass/Kconfig.name
A src/mainboard/ocp/tiogapass/Makefile.inc
A src/mainboard/ocp/tiogapass/acpi/platform.asl
A src/mainboard/ocp/tiogapass/acpi_tables.c
A src/mainboard/ocp/tiogapass/board_info.txt
A src/mainboard/ocp/tiogapass/boardid.c
A src/mainboard/ocp/tiogapass/devicetree.cb
A src/mainboard/ocp/tiogapass/dsdt.asl
A src/mainboard/ocp/tiogapass/emmc.h
A src/mainboard/ocp/tiogapass/fadt.c
A src/mainboard/ocp/tiogapass/ramstage.c
A src/mainboard/ocp/tiogapass/romstage.c
A src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h
A src/mainboard/ocp/tiogapass/skxsp_tp_iio.h
A src/mainboard/ocp/tiogapass/tiogapass_boardid.h
A src/mainboard/ocp/tiogapass/vboot-ro.fmd
19 files changed, 1,321 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/38549/3

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38549 )

Change subject: Add support for OCP platform TiogaPass
......................................................................

Patch Set 3:

(253 comments)

https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
File src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h:

https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 30: 		{GPIO_SKL_H_GPP_A0,  { GpioPadModeGpio,    GpioHostOwnGpio, GpioDirIn,    GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_0_LPC_RCIN_N_ESPI_ALERT1_N
line over 96 characters

https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 31: 		{GPIO_SKL_H_GPP_A1,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_1_LAD_0_ESPI_IO_0
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 32: 		{GPIO_SKL_H_GPP_A2,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_2_LAD_1_ESPI_IO_1
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 33: 		{GPIO_SKL_H_GPP_A3,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_3_LAD_2_ESPI_IO_2
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 34: 		{GPIO_SKL_H_GPP_A4,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_4_LAD_3_ESPI_IO_3
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 35: 		{GPIO_SKL_H_GPP_A5,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_5_LPC_LFRAME_N_ESPI_CS0_N
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 36: 		{GPIO_SKL_H_GPP_A6,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_6_IRQ_LPC_SERIRQ_ESPI_CS1_N
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 37: 		{GPIO_SKL_H_GPP_A7,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_7_IRQ_LPC_PIRQA_N_ESPI_ALERT0_N
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 38: 		{GPIO_SKL_H_GPP_A8,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_8_FM_LPC_CLKRUN_N
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 39: 		{GPIO_SKL_H_GPP_A9,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_9_CLKOUT_LPC0_ESPI_CLK
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 40: 		{GPIO_SKL_H_GPP_A10, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_10_CLKOUT_LPC1
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 41: 		{GPIO_SKL_H_GPP_A11, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_11_FM_LPC_PME_N
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 42: 		{GPIO_SKL_H_GPP_A12, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_A_12_BMBUSY_N_SXEXITHLDOFF_N
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 43: 		{GPIO_SKL_H_GPP_A13, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_13_SUSWARN_N_SUSPWRDNACK
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 44: 		{GPIO_SKL_H_GPP_A14, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_14_ESPI_RESET_N
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 45: 		{GPIO_SKL_H_GPP_A15, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_15_SUSACK_N
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 46: 		{GPIO_SKL_H_GPP_A16, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_16_CLKOUT_LPC2
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 47: 		{GPIO_SKL_H_GPP_A17, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_17
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 48: 		{GPIO_SKL_H_GPP_A18, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_18
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 50: 		{GPIO_SKL_H_GPP_A20, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_20
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 51: 		{GPIO_SKL_H_GPP_A21, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutLow,		 GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_21
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 52: 		{GPIO_SKL_H_GPP_A22, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_22
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 53: 		{GPIO_SKL_H_GPP_A23, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_23
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 55: 		{GPIO_SKL_H_GPP_B0,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_0_CORE_VID_0
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 56: 		{GPIO_SKL_H_GPP_B1,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_1_CORE_VID_1
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 57: 		{GPIO_SKL_H_GPP_B2,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_2_VRALERT_N
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 58: 		{GPIO_SKL_H_GPP_B3,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_3_CPU_GP2
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 59: 		{GPIO_SKL_H_GPP_B4,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_4_CPU_GP3
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 60: 		{GPIO_SKL_H_GPP_B5,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_5_SRCCLKREQ0_N
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 61: 		{GPIO_SKL_H_GPP_B6,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_B_6_SRCCLKREQ1_N
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 62: 		{GPIO_SKL_H_GPP_B7,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_B_7_SRCCLKREQ2_N
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 63: 		{GPIO_SKL_H_GPP_B8,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_8_SRCCLKREQ3_N
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 64: 		{GPIO_SKL_H_GPP_B9,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_9_SRCCLKREQ4_N
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 65: 		{GPIO_SKL_H_GPP_B10, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_10_SRCCLKREQ5_N
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 66: 		{GPIO_SKL_H_GPP_B11, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutLow,		 GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_11
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 67: 		{GPIO_SKL_H_GPP_B12, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_12_GLB_RST_WARN_N
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 68: 		{GPIO_SKL_H_GPP_B13, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_13_RST_PLTRST_N
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 69: 		{GPIO_SKL_H_GPP_B14, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_14_FM_PCH_BIOS_RCVR_SPKR
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 70: 		{GPIO_SKL_H_GPP_B15, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_15
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 71: 		{GPIO_SKL_H_GPP_B16, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_16
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 72: 		{GPIO_SKL_H_GPP_B17, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_17
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 73: 		{GPIO_SKL_H_GPP_B18, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_18
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 74: 		{GPIO_SKL_H_GPP_B19, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutLow,		 GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_19
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 75: 		{GPIO_SKL_H_GPP_B20, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_20
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 76: 		{GPIO_SKL_H_GPP_B21, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_21
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 77: 		{GPIO_SKL_H_GPP_B22, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_22
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 78: 		{GPIO_SKL_H_GPP_B23, { GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut,   GpioOutLow,		 GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock} }, //GPP_B_23_MEIE_SML1ALRT_N_PHOT_N
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 82: 		{GPIO_SKL_H_GPP_C2,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_C_2_SMBALERT_N
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 85: 		{GPIO_SKL_H_GPP_C5,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPP_C_5_SML0ALERT_IE_N
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 88: 		{GPIO_SKL_H_GPP_C8,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_8
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 89: 		{GPIO_SKL_H_GPP_C9,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutLow,		 GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_9
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 90: 		{GPIO_SKL_H_GPP_C10, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_C_10
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 91: 		{GPIO_SKL_H_GPP_C11, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_11
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 92: 		{GPIO_SKL_H_GPP_C12, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_C_12
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 93: 		{GPIO_SKL_H_GPP_C13, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_C_13
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 94: 		{GPIO_SKL_H_GPP_C14, { GpioPadModeGpio,		GpioHostOwnAcpi, GpioDirIn,		GpioOutDefault, GpioIntLevel | GpioIntSci, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_C_14
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 95: 		{GPIO_SKL_H_GPP_C15, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_15
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 96: 		{GPIO_SKL_H_GPP_C16, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_16
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 97: 		{GPIO_SKL_H_GPP_C17, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_17
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 98: 		{GPIO_SKL_H_GPP_C18, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_18
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 99: 		{GPIO_SKL_H_GPP_C19, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_19
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 101: 		{GPIO_SKL_H_GPP_C21, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_21
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 102: 		{GPIO_SKL_H_GPP_C22, { GpioPadModeGpio,		GpioHostOwnAcpi, GpioDirIn,		GpioOutDefault, GpioIntLevel | GpioIntSmi, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_C_22
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 103: 		{GPIO_SKL_H_GPP_C23, { GpioPadModeGpio,		GpioHostOwnAcpi, GpioDirIn,		GpioOutDefault, GpioIntLevel | GpioIntSmi, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_C_23
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 105: 		{GPIO_SKL_H_GPP_D0,  { GpioPadModeGpio,		GpioHostOwnAcpi, GpioDirIn,		GpioOutDefault, GpioIntLevel | GpioIntSmi, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_D_0
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 106: 		{GPIO_SKL_H_GPP_D1,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_1
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 107: 		{GPIO_SKL_H_GPP_D2,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_D_2
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 108: 		{GPIO_SKL_H_GPP_D3,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_D_3
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 109: 		{GPIO_SKL_H_GPP_D4,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutLow,		 GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_4
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 110: 		{GPIO_SKL_H_GPP_D5,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_5
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 111: 		{GPIO_SKL_H_GPP_D6,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_6
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 112: 		{GPIO_SKL_H_GPP_D7,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_7
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 113: 		{GPIO_SKL_H_GPP_D8,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_8
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 114: 		{GPIO_SKL_H_GPP_D9,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_9_SSATA_DEVSLP3
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 115: 		{GPIO_SKL_H_GPP_D10, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_10_SSATA_DEVSLP4
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 116: 		{GPIO_SKL_H_GPP_D11, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_11_SSATA_DEVSLP5
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 117: 		{GPIO_SKL_H_GPP_D12, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_12_SSATA_SDATAOUT1
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 118: 		{GPIO_SKL_H_GPP_D13, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_13_SML0BLCK_IE
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 119: 		{GPIO_SKL_H_GPP_D14, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_14_SML0BDATA_IE
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 120: 		{GPIO_SKL_H_GPP_D15, { GpioPadModeNative3, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_15_SSATA_SDATAOUT0
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 121: 		{GPIO_SKL_H_GPP_D16, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_16_SML0BALERT_IE_N
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 122: 		{GPIO_SKL_H_GPP_D17, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_17
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 123: 		{GPIO_SKL_H_GPP_D18, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_18
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 124: 		{GPIO_SKL_H_GPP_D19, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutLow,		 GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock | GpioOutputStateLock} }, //GPP_D_19
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 125: 		{GPIO_SKL_H_GPP_D20, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_20_TP_PCH_GPP_D_20
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 126: 		{GPIO_SKL_H_GPP_D21, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_21_IE_URAT_RX
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 127: 		{GPIO_SKL_H_GPP_D22, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_22_IE_URAT_TX
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 128: 		{GPIO_SKL_H_GPP_D23, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_23
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 130: 		{GPIO_SKL_H_GPP_E0,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntLevel | GpioIntSmi, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_0_SATAXPCIE0_SATAGP0
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 131: 		{GPIO_SKL_H_GPP_E1,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntLevel | GpioIntSmi, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_1_SATAXPCIE1_SATAGP1
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 132: 		{GPIO_SKL_H_GPP_E2,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_2_SATAXPCIE2_SATAGP2
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 133: 		{GPIO_SKL_H_GPP_E3,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_3_CPU_GP0
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 134: 		{GPIO_SKL_H_GPP_E4,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_4_SATA_DEVSLP0
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 135: 		{GPIO_SKL_H_GPP_E5,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_5_SATA_DEVSLP1
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 136: 		{GPIO_SKL_H_GPP_E6,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_6_SATA_DEVSLP2
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 137: 		{GPIO_SKL_H_GPP_E7,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_7_CPU_GP1
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 138: 		{GPIO_SKL_H_GPP_E8,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_8_SATA_LED_N
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 139: 		{GPIO_SKL_H_GPP_E9,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_9_USB2_OC0_N
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 140: 		{GPIO_SKL_H_GPP_E10, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_10_USB2_OC1_N
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 141: 		{GPIO_SKL_H_GPP_E11, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_11_USB2_OC2_N
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 142: 		{GPIO_SKL_H_GPP_E12, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_12_USB2_OC3_N
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 144: 		{GPIO_SKL_H_GPP_F0,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_F_0_SATAXPCIE3_SATAGP3
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 145: 		{GPIO_SKL_H_GPP_F1,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_F_1_SATAXPCIE4_SATAGP4
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 146: 		{GPIO_SKL_H_GPP_F2,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_F_2_SATAXPCIE5_SATAGP5
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 147: 		{GPIO_SKL_H_GPP_F3,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_F_3_SATAXPCIE6_SATAGP6
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 148: 		{GPIO_SKL_H_GPP_F4,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_F_4_SATAXPCIE7_SATAGP7
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 149: 		{GPIO_SKL_H_GPP_F5,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_F_5_SATA_DEVSLP3
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 150: 		{GPIO_SKL_H_GPP_F6,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_F_6_SATA_DEVSLP4
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 151: 		{GPIO_SKL_H_GPP_F7,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_F_7_SATA_DEVSLP5
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 152: 		{GPIO_SKL_H_GPP_F8,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_F_8_SATA_DEVSLP6
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 153: 		{GPIO_SKL_H_GPP_F9,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_F_9_SATA_DEVSLP7
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 154: 		{GPIO_SKL_H_GPP_F10, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_10_SATA_SCLOCK
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 155: 		{GPIO_SKL_H_GPP_F11, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_11_SATA_SLOAD
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 156: 		{GPIO_SKL_H_GPP_F12, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_12_SATA_SDATAOUT1
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 157: 		{GPIO_SKL_H_GPP_F13, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_13_SATA_SDATAOUT0
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 158: 		{GPIO_SKL_H_GPP_F14, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_14_SSATA_LED_N
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 159: 		{GPIO_SKL_H_GPP_F15, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_15_USB2_OC4_N
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 160: 		{GPIO_SKL_H_GPP_F16, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_16_USB2_OC5_N
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 161: 		{GPIO_SKL_H_GPP_F17, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_17_USB2_OC6_N
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 162: 		{GPIO_SKL_H_GPP_F18, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_18_USB2_OC7_N
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 163: 		{GPIO_SKL_H_GPP_F19, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_19_LAN_SMBCLK
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 164: 		{GPIO_SKL_H_GPP_F20, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_20_LAN_SMBDATA
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 165: 		{GPIO_SKL_H_GPP_F21, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_21_LAN_SMBALERT_N
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 166: 		{GPIO_SKL_H_GPP_F22, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_22_SSATA_SCLOCK
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 167: 		{GPIO_SKL_H_GPP_F23, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_23_SSATA_SLOAD
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 169: 		{GPIO_SKL_H_GPP_G0,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_0_FANTACH0_FANTACH0IE
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 170: 		{GPIO_SKL_H_GPP_G1,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_1_FANTACH1_FANTACH1IE
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 171: 		{GPIO_SKL_H_GPP_G2,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_2_FANTACH2_FANTACH2IE
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 172: 		{GPIO_SKL_H_GPP_G3,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_3_FANTACH3_FANTACH3IE
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 173: 		{GPIO_SKL_H_GPP_G4,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_4_FANTACH4_FANTACH4IE
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 174: 		{GPIO_SKL_H_GPP_G5,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_5_FANTACH5_FANTACH5IE
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 175: 		{GPIO_SKL_H_GPP_G6,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_6_FANTACH6_FANTACH6IE
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 176: 		{GPIO_SKL_H_GPP_G7,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_7_FANTACH7_FANTACH7IE
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 177: 		{GPIO_SKL_H_GPP_G8,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_8_FANPWM0_FANPWM0IE
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 178: 		{GPIO_SKL_H_GPP_G9,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_9_FANPWM1_FANPWM1IE
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 179: 		{GPIO_SKL_H_GPP_G10, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_10_FANPWM2_FANPWM2IE
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 180: 		{GPIO_SKL_H_GPP_G11, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_11_FANPWM3_FANPWM3IE
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 181: 		{GPIO_SKL_H_GPP_G12, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_12
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 182: 		{GPIO_SKL_H_GPP_G13, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_13
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 183: 		{GPIO_SKL_H_GPP_G14, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_14
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 184: 		{GPIO_SKL_H_GPP_G15, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_15
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 185: 		{GPIO_SKL_H_GPP_G16, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_16
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 186: 		{GPIO_SKL_H_GPP_G17, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_17_ADR_COMPLETE
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 187: 		{GPIO_SKL_H_GPP_G18, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_18_FM_NMI_EVENT_N
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 188: 		{GPIO_SKL_H_GPP_G19, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_19_FM_SMI_ACTIVE_N
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 190: 		{GPIO_SKL_H_GPP_G21, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_21_SSATA_DEVSLP1
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 191: 		{GPIO_SKL_H_GPP_G22, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_G_22_SSATA_DEVSLP2
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 192: 		{GPIO_SKL_H_GPP_G23, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_23_SSATAXPCIE0_SSATAGP0
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 194: 		{GPIO_SKL_H_GPP_H0,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_H_0_SRCCLKREQ6_N
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 195: 		{GPIO_SKL_H_GPP_H1,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_H_1_SRCCLKREQ7_N
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 196: 		{GPIO_SKL_H_GPP_H2,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_H_2_SRCCLKREQ8_N
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 197: 		{GPIO_SKL_H_GPP_H3,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_H_3_SRCCLKREQ9_N
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 198: 		{GPIO_SKL_H_GPP_H4,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_H_4_SRCCLKREQ10_N
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 200: 		{GPIO_SKL_H_GPP_H6,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_H_6_SRCCLKREQ12_N
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 201: 		{GPIO_SKL_H_GPP_H7,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_H_7_SRCCLKREQ13_N
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 202: 		{GPIO_SKL_H_GPP_H8,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_H_8_SRCCLKREQ14_N
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 203: 		{GPIO_SKL_H_GPP_H9,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_H_9_SRCCLKREQ15_N
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 206: 		{GPIO_SKL_H_GPP_H12, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_H_12_SML2ALERT_N_IE
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 209: 		{GPIO_SKL_H_GPP_H15, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_H_15_SML3ALERT_N_IE
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 212: 		{GPIO_SKL_H_GPP_H18, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_H_18_SML4ALERT_N_IE
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 213: 		{GPIO_SKL_H_GPP_H19, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_H_19_SSATAXPCIE1_SSATAGP1
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 214: 		{GPIO_SKL_H_GPP_H20, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_H_20_SSATAXPCIE2_SSATAGP2
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 215: 		{GPIO_SKL_H_GPP_H21, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_H_21_SSATAXPCIE3_SSATAGP3
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 216: 		{GPIO_SKL_H_GPP_H22, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_H_22_SSATAXPCIE4_SSATAGP4
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 217: 		{GPIO_SKL_H_GPP_H23, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_H_23_SSATAXPCIE5_SSATAGP5
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 219: 		{GPIO_SKL_H_GPP_I0,  { GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_I_0_GBE_TDO
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 220: 		{GPIO_SKL_H_GPP_I1,  { GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_I_1_GBE_TCK
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 221: 		{GPIO_SKL_H_GPP_I2,  { GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_I_2_GBE_TMS
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 222: 		{GPIO_SKL_H_GPP_I3,  { GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_I_3_GBE_TDI
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 223: 		{GPIO_SKL_H_GPP_I4,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_I_4_DO_RESET_IN_N
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 224: 		{GPIO_SKL_H_GPP_I5,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_I_5_DO_RESET_OUT_N
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 225: 		{GPIO_SKL_H_GPP_I6,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_I_6_RESET_DONE
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 226: 		{GPIO_SKL_H_GPP_I7,  { GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_I_7_JTAG_GBE_TRST_N
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 227: 		{GPIO_SKL_H_GPP_I8,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_I_8_GBE_PCI_DIS
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 228: 		{GPIO_SKL_H_GPP_I9,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_I_9_GBE_LAN_DIS
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 229: 		{GPIO_SKL_H_GPP_I10, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_I_10
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 231: 		{GPIO_SKL_H_GPP_J0,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_0_LAN_LED_P0_0
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 232: 		{GPIO_SKL_H_GPP_J1,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_1_LAN_LED_P0_1
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 233: 		{GPIO_SKL_H_GPP_J2,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_2_LAN_LED_P1_0
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 234: 		{GPIO_SKL_H_GPP_J3,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_3_LAN_LED_P1_1
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 235: 		{GPIO_SKL_H_GPP_J4,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_4_LAN_LED_P2_0
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 236: 		{GPIO_SKL_H_GPP_J5,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_5_LAN_LED_P2_1
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 237: 		{GPIO_SKL_H_GPP_J6,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_6_LAN_LED_P3_0
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 238: 		{GPIO_SKL_H_GPP_J7,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_7_LAN_LED_P3_1
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 239: 		{GPIO_SKL_H_GPP_J8,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_8_LAN_I2C_SCL_MDC_P0
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 240: 		{GPIO_SKL_H_GPP_J9,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_9_LAN_I2C_SDA_MDIO_P0
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 241: 		{GPIO_SKL_H_GPP_J10, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_10_LAN_I2C_SCL_MDC_P1
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 242: 		{GPIO_SKL_H_GPP_J11, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_11_LAN_I2C_SDA_MDIO_P1
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 243: 		{GPIO_SKL_H_GPP_J12, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_12_LAN_I2C_SCL_MDC_P2
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 244: 		{GPIO_SKL_H_GPP_J13, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_13_LAN_I2C_SDA_MDIO_P2
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 245: 		{GPIO_SKL_H_GPP_J14, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_14_LAN_I2C_SCL_MDC_P3
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 246: 		{GPIO_SKL_H_GPP_J15, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_15_LAN_I2C_SDA_MDIO_P3
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 247: 		{GPIO_SKL_H_GPP_J16, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_16_LAN_SDP_P0_0
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 248: 		{GPIO_SKL_H_GPP_J17, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_17_LAN_SDP_P0_1
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 249: 		{GPIO_SKL_H_GPP_J18, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_18_LAN_SDP_P1_0
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 250: 		{GPIO_SKL_H_GPP_J19, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_19_LAN_SDP_P1_1
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 251: 		{GPIO_SKL_H_GPP_J20, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_20_LAN_SDP_P2_0
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 252: 		{GPIO_SKL_H_GPP_J21, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_21_LAN_SDP_P2_1
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 253: 		{GPIO_SKL_H_GPP_J22, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_22_LAN_SDP_P3_0
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 254: 		{GPIO_SKL_H_GPP_J23, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_23_LAN_SDP_P3_1
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 256: 		{GPIO_SKL_H_GPP_K0,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_K_0_LAN_NCSI_CLK_IN
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 257: 		{GPIO_SKL_H_GPP_K1,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_K_1_LAN_NCSI_TXD0
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 258: 		{GPIO_SKL_H_GPP_K2,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_K_2_LAN_NCSI_TXD1
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 259: 		{GPIO_SKL_H_GPP_K3,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_K_3_LAN_NCSI_TX_EN
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 260: 		{GPIO_SKL_H_GPP_K4,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_K_4_LAN_NCSI_CRS_DV
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 261: 		{GPIO_SKL_H_GPP_K5,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_K_5_LAN_NCSI_RXD0
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 262: 		{GPIO_SKL_H_GPP_K6,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_K_6_LAN_NCSI_RXD1
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 263: 		{GPIO_SKL_H_GPP_K7,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_K_7
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 264: 		{GPIO_SKL_H_GPP_K8,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,  GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_K_8_LAN_NCSI_ARB_IN
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 265: 		{GPIO_SKL_H_GPP_K9,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_K_9_LAN_NCSI_ARB_OUT
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 266: 		{GPIO_SKL_H_GPP_K10, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_K_10_PE_RST_N
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 268: 		{GPIO_SKL_H_GPP_L2,  { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_2_TESTCH0_D0
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 269: 		{GPIO_SKL_H_GPP_L3,  { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_3_TESTCH0_D1
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 270: 		{GPIO_SKL_H_GPP_L4,  { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_4_TESTCH0_D2
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 271: 		{GPIO_SKL_H_GPP_L5,  { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_5_TESTCH0_D3
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 272: 		{GPIO_SKL_H_GPP_L6,  { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_6_TESTCH0_D4
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 273: 		{GPIO_SKL_H_GPP_L7,  { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_7_TESTCH0_D5
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 274: 		{GPIO_SKL_H_GPP_L8,  { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_8_TESTCH0_D6
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 275: 		{GPIO_SKL_H_GPP_L9,  { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_9_TESTCH0_D7
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 276: 		{GPIO_SKL_H_GPP_L10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_10_TESTCH0_CLK
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 277: 		{GPIO_SKL_H_GPP_L11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_11_TESTCH1_D0
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 278: 		{GPIO_SKL_H_GPP_L12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_12_TESTCH1_D1
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 279: 		{GPIO_SKL_H_GPP_L13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_13_TESTCH1_D2
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 280: 		{GPIO_SKL_H_GPP_L14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_14_TESTCH1_D3
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 281: 		{GPIO_SKL_H_GPP_L15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_15_TESTCH1_D4
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 282: 		{GPIO_SKL_H_GPP_L16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_16_TESTCH1_D5
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 283: 		{GPIO_SKL_H_GPP_L17, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_17_TESTCH1_D6
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 284: 		{GPIO_SKL_H_GPP_L18, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_18_TESTCH1_D7
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 285: 		{GPIO_SKL_H_GPP_L19, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_19_TESTCH1_CLK
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 288: 		{GPIO_SKL_H_GPD1,		{ GpioPadModeGpio,   GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPD_1_ACPRESENT
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 289: 		{GPIO_SKL_H_GPD2,		{ GpioPadModeGpio,   GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPD_2_GBE_WAKE_N
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 290: 		{GPIO_SKL_H_GPD3,		{ GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPD_3_PWRBTNB_N
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 291: 		{GPIO_SKL_H_GPD4,		{ GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPD_4_SLP_S3B
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 292: 		{GPIO_SKL_H_GPD5,		{ GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPD_5_SLP_S4B
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 293: 		{GPIO_SKL_H_GPD6,		{ GpioPadModeGpio,   GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPD_6_SLPA_N
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 294: 		{GPIO_SKL_H_GPD7,		{ GpioPadModeGpio,   GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPD_7
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 295: 		{GPIO_SKL_H_GPD8,		{ GpioPadModeGpio,   GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPD_8_CLK_33K_PCH_SUSCLK_PLD
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 296: 		{GPIO_SKL_H_GPD9,		{ GpioPadModeGpio,   GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPD_9
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 297: 		{GPIO_SKL_H_GPD10,   { GpioPadModeGpio,   GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPD_10_FM_SLPS5_N
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 298: 		{GPIO_SKL_H_GPD11,   { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPD_11_GBEPHY
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
File src/mainboard/ocp/tiogapass/skxsp_tp_iio.h:

https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 48:   // PortIndex |  HidePort  | DeEmphasis | PortLinkSpeed | MaxPayload | DfxDnTxPreset | DfxRxPreset | DfxUpTxPreset | Sris | PcieCommonClock | NtbPpd               | NtbSplitBar | NtbBarSizePBar23 | NtbBarSizePBar4 | NtbBarSizePBar5 | NtbBarSizePBar45 | NtbBarSizeSBar23 | NtbBarSizeSBar4 | NtbBarSizeSbar5 | NtbBarSizeSBar45 | NtbSBar01Prefetch | NtbXlinkCtlOverride
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 49: 	{ PORT_1A, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 50: 	{ PORT_1B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 51: 	{ PORT_1C, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 52: 	{ PORT_1D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 53: 	{ PORT_2A, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 54: 	{ PORT_2B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 55: 	{ PORT_2C, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 56: 	{ PORT_2D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 57: 	{ PORT_3A, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 58: 	{ PORT_3B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 59: 	{ PORT_3C, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
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https://review.coreboot.org/c/coreboot/+/38549/3/src/mainboard/ocp/tiogapass... 
PS3, Line 60: 	{ PORT_3D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
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[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38549 )

Change subject: Add support for OCP platform TiogaPass
......................................................................

Patch Set 4:

(253 comments)

https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
File src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h:

https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 30: 		{GPIO_SKL_H_GPP_A0,  { GpioPadModeGpio,    GpioHostOwnGpio, GpioDirIn,    GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_0_LPC_RCIN_N_ESPI_ALERT1_N
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 31: 		{GPIO_SKL_H_GPP_A1,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_1_LAD_0_ESPI_IO_0
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 32: 		{GPIO_SKL_H_GPP_A2,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_2_LAD_1_ESPI_IO_1
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 33: 		{GPIO_SKL_H_GPP_A3,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_3_LAD_2_ESPI_IO_2
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 34: 		{GPIO_SKL_H_GPP_A4,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_4_LAD_3_ESPI_IO_3
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 35: 		{GPIO_SKL_H_GPP_A5,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_5_LPC_LFRAME_N_ESPI_CS0_N
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 36: 		{GPIO_SKL_H_GPP_A6,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_6_IRQ_LPC_SERIRQ_ESPI_CS1_N
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 37: 		{GPIO_SKL_H_GPP_A7,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_7_IRQ_LPC_PIRQA_N_ESPI_ALERT0_N
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 38: 		{GPIO_SKL_H_GPP_A8,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_8_FM_LPC_CLKRUN_N
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 39: 		{GPIO_SKL_H_GPP_A9,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_9_CLKOUT_LPC0_ESPI_CLK
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 40: 		{GPIO_SKL_H_GPP_A10, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_10_CLKOUT_LPC1
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 41: 		{GPIO_SKL_H_GPP_A11, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_11_FM_LPC_PME_N
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 42: 		{GPIO_SKL_H_GPP_A12, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_A_12_BMBUSY_N_SXEXITHLDOFF_N
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 43: 		{GPIO_SKL_H_GPP_A13, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_13_SUSWARN_N_SUSPWRDNACK
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 44: 		{GPIO_SKL_H_GPP_A14, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_14_ESPI_RESET_N
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 45: 		{GPIO_SKL_H_GPP_A15, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_15_SUSACK_N
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 46: 		{GPIO_SKL_H_GPP_A16, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_16_CLKOUT_LPC2
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 47: 		{GPIO_SKL_H_GPP_A17, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_17
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 48: 		{GPIO_SKL_H_GPP_A18, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_18
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 50: 		{GPIO_SKL_H_GPP_A20, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_20
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 51: 		{GPIO_SKL_H_GPP_A21, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutLow,		 GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_21
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 52: 		{GPIO_SKL_H_GPP_A22, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_22
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 53: 		{GPIO_SKL_H_GPP_A23, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_23
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 55: 		{GPIO_SKL_H_GPP_B0,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_0_CORE_VID_0
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 56: 		{GPIO_SKL_H_GPP_B1,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_1_CORE_VID_1
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 57: 		{GPIO_SKL_H_GPP_B2,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_2_VRALERT_N
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 58: 		{GPIO_SKL_H_GPP_B3,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_3_CPU_GP2
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 59: 		{GPIO_SKL_H_GPP_B4,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_4_CPU_GP3
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 60: 		{GPIO_SKL_H_GPP_B5,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_5_SRCCLKREQ0_N
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 61: 		{GPIO_SKL_H_GPP_B6,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_B_6_SRCCLKREQ1_N
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 62: 		{GPIO_SKL_H_GPP_B7,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_B_7_SRCCLKREQ2_N
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 63: 		{GPIO_SKL_H_GPP_B8,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_8_SRCCLKREQ3_N
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 64: 		{GPIO_SKL_H_GPP_B9,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_9_SRCCLKREQ4_N
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 65: 		{GPIO_SKL_H_GPP_B10, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_10_SRCCLKREQ5_N
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 66: 		{GPIO_SKL_H_GPP_B11, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutLow,		 GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_11
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 67: 		{GPIO_SKL_H_GPP_B12, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_12_GLB_RST_WARN_N
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 68: 		{GPIO_SKL_H_GPP_B13, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_13_RST_PLTRST_N
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 69: 		{GPIO_SKL_H_GPP_B14, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_14_FM_PCH_BIOS_RCVR_SPKR
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 70: 		{GPIO_SKL_H_GPP_B15, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_15
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 71: 		{GPIO_SKL_H_GPP_B16, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_16
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 72: 		{GPIO_SKL_H_GPP_B17, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_17
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 73: 		{GPIO_SKL_H_GPP_B18, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_18
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 74: 		{GPIO_SKL_H_GPP_B19, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutLow,		 GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_19
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 75: 		{GPIO_SKL_H_GPP_B20, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_20
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 76: 		{GPIO_SKL_H_GPP_B21, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_21
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 77: 		{GPIO_SKL_H_GPP_B22, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_22
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 78: 		{GPIO_SKL_H_GPP_B23, { GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut,   GpioOutLow,		 GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock} }, //GPP_B_23_MEIE_SML1ALRT_N_PHOT_N
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 82: 		{GPIO_SKL_H_GPP_C2,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_C_2_SMBALERT_N
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 85: 		{GPIO_SKL_H_GPP_C5,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPP_C_5_SML0ALERT_IE_N
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 88: 		{GPIO_SKL_H_GPP_C8,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_8
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 89: 		{GPIO_SKL_H_GPP_C9,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutLow,		 GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_9
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 90: 		{GPIO_SKL_H_GPP_C10, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_C_10
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 91: 		{GPIO_SKL_H_GPP_C11, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_11
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 92: 		{GPIO_SKL_H_GPP_C12, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_C_12
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 93: 		{GPIO_SKL_H_GPP_C13, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_C_13
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 94: 		{GPIO_SKL_H_GPP_C14, { GpioPadModeGpio,		GpioHostOwnAcpi, GpioDirIn,		GpioOutDefault, GpioIntLevel | GpioIntSci, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_C_14
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 95: 		{GPIO_SKL_H_GPP_C15, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_15
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 96: 		{GPIO_SKL_H_GPP_C16, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_16
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 97: 		{GPIO_SKL_H_GPP_C17, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_17
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 98: 		{GPIO_SKL_H_GPP_C18, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_18
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 99: 		{GPIO_SKL_H_GPP_C19, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_19
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 101: 		{GPIO_SKL_H_GPP_C21, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_21
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 102: 		{GPIO_SKL_H_GPP_C22, { GpioPadModeGpio,		GpioHostOwnAcpi, GpioDirIn,		GpioOutDefault, GpioIntLevel | GpioIntSmi, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_C_22
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 103: 		{GPIO_SKL_H_GPP_C23, { GpioPadModeGpio,		GpioHostOwnAcpi, GpioDirIn,		GpioOutDefault, GpioIntLevel | GpioIntSmi, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_C_23
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 105: 		{GPIO_SKL_H_GPP_D0,  { GpioPadModeGpio,		GpioHostOwnAcpi, GpioDirIn,		GpioOutDefault, GpioIntLevel | GpioIntSmi, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_D_0
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 106: 		{GPIO_SKL_H_GPP_D1,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_1
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 107: 		{GPIO_SKL_H_GPP_D2,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_D_2
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 108: 		{GPIO_SKL_H_GPP_D3,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_D_3
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 109: 		{GPIO_SKL_H_GPP_D4,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutLow,		 GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_4
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 110: 		{GPIO_SKL_H_GPP_D5,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_5
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 111: 		{GPIO_SKL_H_GPP_D6,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_6
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 112: 		{GPIO_SKL_H_GPP_D7,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_7
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 113: 		{GPIO_SKL_H_GPP_D8,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_8
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 114: 		{GPIO_SKL_H_GPP_D9,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_9_SSATA_DEVSLP3
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 115: 		{GPIO_SKL_H_GPP_D10, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_10_SSATA_DEVSLP4
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 116: 		{GPIO_SKL_H_GPP_D11, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_11_SSATA_DEVSLP5
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 117: 		{GPIO_SKL_H_GPP_D12, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_12_SSATA_SDATAOUT1
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 118: 		{GPIO_SKL_H_GPP_D13, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_13_SML0BLCK_IE
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 119: 		{GPIO_SKL_H_GPP_D14, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_14_SML0BDATA_IE
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 120: 		{GPIO_SKL_H_GPP_D15, { GpioPadModeNative3, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_15_SSATA_SDATAOUT0
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 121: 		{GPIO_SKL_H_GPP_D16, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_16_SML0BALERT_IE_N
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 122: 		{GPIO_SKL_H_GPP_D17, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_17
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 123: 		{GPIO_SKL_H_GPP_D18, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_18
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 124: 		{GPIO_SKL_H_GPP_D19, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutLow,		 GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock | GpioOutputStateLock} }, //GPP_D_19
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 125: 		{GPIO_SKL_H_GPP_D20, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_20_TP_PCH_GPP_D_20
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 126: 		{GPIO_SKL_H_GPP_D21, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_21_IE_URAT_RX
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 127: 		{GPIO_SKL_H_GPP_D22, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_22_IE_URAT_TX
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 128: 		{GPIO_SKL_H_GPP_D23, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_23
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 130: 		{GPIO_SKL_H_GPP_E0,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntLevel | GpioIntSmi, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_0_SATAXPCIE0_SATAGP0
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 131: 		{GPIO_SKL_H_GPP_E1,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntLevel | GpioIntSmi, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_1_SATAXPCIE1_SATAGP1
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 132: 		{GPIO_SKL_H_GPP_E2,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_2_SATAXPCIE2_SATAGP2
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 133: 		{GPIO_SKL_H_GPP_E3,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_3_CPU_GP0
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 134: 		{GPIO_SKL_H_GPP_E4,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_4_SATA_DEVSLP0
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 135: 		{GPIO_SKL_H_GPP_E5,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_5_SATA_DEVSLP1
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 136: 		{GPIO_SKL_H_GPP_E6,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_6_SATA_DEVSLP2
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 137: 		{GPIO_SKL_H_GPP_E7,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_7_CPU_GP1
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 138: 		{GPIO_SKL_H_GPP_E8,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_8_SATA_LED_N
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 139: 		{GPIO_SKL_H_GPP_E9,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_9_USB2_OC0_N
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 140: 		{GPIO_SKL_H_GPP_E10, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_10_USB2_OC1_N
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 141: 		{GPIO_SKL_H_GPP_E11, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_11_USB2_OC2_N
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 142: 		{GPIO_SKL_H_GPP_E12, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_12_USB2_OC3_N
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 144: 		{GPIO_SKL_H_GPP_F0,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_F_0_SATAXPCIE3_SATAGP3
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 145: 		{GPIO_SKL_H_GPP_F1,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_F_1_SATAXPCIE4_SATAGP4
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 146: 		{GPIO_SKL_H_GPP_F2,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_F_2_SATAXPCIE5_SATAGP5
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 147: 		{GPIO_SKL_H_GPP_F3,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_F_3_SATAXPCIE6_SATAGP6
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 148: 		{GPIO_SKL_H_GPP_F4,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_F_4_SATAXPCIE7_SATAGP7
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 149: 		{GPIO_SKL_H_GPP_F5,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_F_5_SATA_DEVSLP3
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 150: 		{GPIO_SKL_H_GPP_F6,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_F_6_SATA_DEVSLP4
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 151: 		{GPIO_SKL_H_GPP_F7,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_F_7_SATA_DEVSLP5
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 152: 		{GPIO_SKL_H_GPP_F8,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_F_8_SATA_DEVSLP6
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 153: 		{GPIO_SKL_H_GPP_F9,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_F_9_SATA_DEVSLP7
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 154: 		{GPIO_SKL_H_GPP_F10, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_10_SATA_SCLOCK
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 155: 		{GPIO_SKL_H_GPP_F11, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_11_SATA_SLOAD
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 156: 		{GPIO_SKL_H_GPP_F12, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_12_SATA_SDATAOUT1
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 157: 		{GPIO_SKL_H_GPP_F13, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_13_SATA_SDATAOUT0
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 158: 		{GPIO_SKL_H_GPP_F14, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_14_SSATA_LED_N
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 159: 		{GPIO_SKL_H_GPP_F15, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_15_USB2_OC4_N
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 160: 		{GPIO_SKL_H_GPP_F16, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_16_USB2_OC5_N
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 161: 		{GPIO_SKL_H_GPP_F17, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_17_USB2_OC6_N
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 162: 		{GPIO_SKL_H_GPP_F18, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_18_USB2_OC7_N
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 163: 		{GPIO_SKL_H_GPP_F19, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_19_LAN_SMBCLK
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 164: 		{GPIO_SKL_H_GPP_F20, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_20_LAN_SMBDATA
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 165: 		{GPIO_SKL_H_GPP_F21, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_21_LAN_SMBALERT_N
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 166: 		{GPIO_SKL_H_GPP_F22, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_22_SSATA_SCLOCK
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 167: 		{GPIO_SKL_H_GPP_F23, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_23_SSATA_SLOAD
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 169: 		{GPIO_SKL_H_GPP_G0,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_0_FANTACH0_FANTACH0IE
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 170: 		{GPIO_SKL_H_GPP_G1,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_1_FANTACH1_FANTACH1IE
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 171: 		{GPIO_SKL_H_GPP_G2,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_2_FANTACH2_FANTACH2IE
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 172: 		{GPIO_SKL_H_GPP_G3,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_3_FANTACH3_FANTACH3IE
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 173: 		{GPIO_SKL_H_GPP_G4,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_4_FANTACH4_FANTACH4IE
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 174: 		{GPIO_SKL_H_GPP_G5,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_5_FANTACH5_FANTACH5IE
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 175: 		{GPIO_SKL_H_GPP_G6,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_6_FANTACH6_FANTACH6IE
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 176: 		{GPIO_SKL_H_GPP_G7,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_7_FANTACH7_FANTACH7IE
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 177: 		{GPIO_SKL_H_GPP_G8,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_8_FANPWM0_FANPWM0IE
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 178: 		{GPIO_SKL_H_GPP_G9,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_9_FANPWM1_FANPWM1IE
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 179: 		{GPIO_SKL_H_GPP_G10, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_10_FANPWM2_FANPWM2IE
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 180: 		{GPIO_SKL_H_GPP_G11, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_11_FANPWM3_FANPWM3IE
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 181: 		{GPIO_SKL_H_GPP_G12, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_12
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 182: 		{GPIO_SKL_H_GPP_G13, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_13
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 183: 		{GPIO_SKL_H_GPP_G14, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_14
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 184: 		{GPIO_SKL_H_GPP_G15, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_15
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 185: 		{GPIO_SKL_H_GPP_G16, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_16
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 186: 		{GPIO_SKL_H_GPP_G17, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_17_ADR_COMPLETE
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 187: 		{GPIO_SKL_H_GPP_G18, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_18_FM_NMI_EVENT_N
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 188: 		{GPIO_SKL_H_GPP_G19, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_19_FM_SMI_ACTIVE_N
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 190: 		{GPIO_SKL_H_GPP_G21, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_21_SSATA_DEVSLP1
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 191: 		{GPIO_SKL_H_GPP_G22, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_G_22_SSATA_DEVSLP2
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 192: 		{GPIO_SKL_H_GPP_G23, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_23_SSATAXPCIE0_SSATAGP0
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 194: 		{GPIO_SKL_H_GPP_H0,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_H_0_SRCCLKREQ6_N
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 195: 		{GPIO_SKL_H_GPP_H1,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_H_1_SRCCLKREQ7_N
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 196: 		{GPIO_SKL_H_GPP_H2,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_H_2_SRCCLKREQ8_N
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 197: 		{GPIO_SKL_H_GPP_H3,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_H_3_SRCCLKREQ9_N
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 198: 		{GPIO_SKL_H_GPP_H4,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_H_4_SRCCLKREQ10_N
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 200: 		{GPIO_SKL_H_GPP_H6,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_H_6_SRCCLKREQ12_N
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 201: 		{GPIO_SKL_H_GPP_H7,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_H_7_SRCCLKREQ13_N
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 202: 		{GPIO_SKL_H_GPP_H8,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_H_8_SRCCLKREQ14_N
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 203: 		{GPIO_SKL_H_GPP_H9,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_H_9_SRCCLKREQ15_N
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 206: 		{GPIO_SKL_H_GPP_H12, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_H_12_SML2ALERT_N_IE
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 209: 		{GPIO_SKL_H_GPP_H15, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_H_15_SML3ALERT_N_IE
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 212: 		{GPIO_SKL_H_GPP_H18, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_H_18_SML4ALERT_N_IE
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 213: 		{GPIO_SKL_H_GPP_H19, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_H_19_SSATAXPCIE1_SSATAGP1
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 214: 		{GPIO_SKL_H_GPP_H20, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_H_20_SSATAXPCIE2_SSATAGP2
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 215: 		{GPIO_SKL_H_GPP_H21, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_H_21_SSATAXPCIE3_SSATAGP3
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 216: 		{GPIO_SKL_H_GPP_H22, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_H_22_SSATAXPCIE4_SSATAGP4
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 217: 		{GPIO_SKL_H_GPP_H23, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_H_23_SSATAXPCIE5_SSATAGP5
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 219: 		{GPIO_SKL_H_GPP_I0,  { GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_I_0_GBE_TDO
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 220: 		{GPIO_SKL_H_GPP_I1,  { GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_I_1_GBE_TCK
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 221: 		{GPIO_SKL_H_GPP_I2,  { GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_I_2_GBE_TMS
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 222: 		{GPIO_SKL_H_GPP_I3,  { GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_I_3_GBE_TDI
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 223: 		{GPIO_SKL_H_GPP_I4,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_I_4_DO_RESET_IN_N
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 224: 		{GPIO_SKL_H_GPP_I5,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_I_5_DO_RESET_OUT_N
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 225: 		{GPIO_SKL_H_GPP_I6,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_I_6_RESET_DONE
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 226: 		{GPIO_SKL_H_GPP_I7,  { GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_I_7_JTAG_GBE_TRST_N
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 227: 		{GPIO_SKL_H_GPP_I8,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_I_8_GBE_PCI_DIS
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 228: 		{GPIO_SKL_H_GPP_I9,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_I_9_GBE_LAN_DIS
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 229: 		{GPIO_SKL_H_GPP_I10, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_I_10
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 231: 		{GPIO_SKL_H_GPP_J0,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_0_LAN_LED_P0_0
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 232: 		{GPIO_SKL_H_GPP_J1,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_1_LAN_LED_P0_1
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 233: 		{GPIO_SKL_H_GPP_J2,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_2_LAN_LED_P1_0
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 234: 		{GPIO_SKL_H_GPP_J3,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_3_LAN_LED_P1_1
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 235: 		{GPIO_SKL_H_GPP_J4,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_4_LAN_LED_P2_0
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 236: 		{GPIO_SKL_H_GPP_J5,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_5_LAN_LED_P2_1
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 237: 		{GPIO_SKL_H_GPP_J6,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_6_LAN_LED_P3_0
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 238: 		{GPIO_SKL_H_GPP_J7,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_7_LAN_LED_P3_1
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 239: 		{GPIO_SKL_H_GPP_J8,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_8_LAN_I2C_SCL_MDC_P0
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 240: 		{GPIO_SKL_H_GPP_J9,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_9_LAN_I2C_SDA_MDIO_P0
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 241: 		{GPIO_SKL_H_GPP_J10, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_10_LAN_I2C_SCL_MDC_P1
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 242: 		{GPIO_SKL_H_GPP_J11, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_11_LAN_I2C_SDA_MDIO_P1
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 243: 		{GPIO_SKL_H_GPP_J12, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_12_LAN_I2C_SCL_MDC_P2
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 244: 		{GPIO_SKL_H_GPP_J13, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_13_LAN_I2C_SDA_MDIO_P2
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 245: 		{GPIO_SKL_H_GPP_J14, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_14_LAN_I2C_SCL_MDC_P3
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 246: 		{GPIO_SKL_H_GPP_J15, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_15_LAN_I2C_SDA_MDIO_P3
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 247: 		{GPIO_SKL_H_GPP_J16, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_16_LAN_SDP_P0_0
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 248: 		{GPIO_SKL_H_GPP_J17, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_17_LAN_SDP_P0_1
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 249: 		{GPIO_SKL_H_GPP_J18, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_18_LAN_SDP_P1_0
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 250: 		{GPIO_SKL_H_GPP_J19, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_19_LAN_SDP_P1_1
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 251: 		{GPIO_SKL_H_GPP_J20, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_20_LAN_SDP_P2_0
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 252: 		{GPIO_SKL_H_GPP_J21, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_21_LAN_SDP_P2_1
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 253: 		{GPIO_SKL_H_GPP_J22, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_22_LAN_SDP_P3_0
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 254: 		{GPIO_SKL_H_GPP_J23, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_23_LAN_SDP_P3_1
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 256: 		{GPIO_SKL_H_GPP_K0,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_K_0_LAN_NCSI_CLK_IN
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 257: 		{GPIO_SKL_H_GPP_K1,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_K_1_LAN_NCSI_TXD0
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 258: 		{GPIO_SKL_H_GPP_K2,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_K_2_LAN_NCSI_TXD1
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 259: 		{GPIO_SKL_H_GPP_K3,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_K_3_LAN_NCSI_TX_EN
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 260: 		{GPIO_SKL_H_GPP_K4,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_K_4_LAN_NCSI_CRS_DV
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 261: 		{GPIO_SKL_H_GPP_K5,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_K_5_LAN_NCSI_RXD0
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 262: 		{GPIO_SKL_H_GPP_K6,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_K_6_LAN_NCSI_RXD1
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 263: 		{GPIO_SKL_H_GPP_K7,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_K_7
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 264: 		{GPIO_SKL_H_GPP_K8,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,  GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_K_8_LAN_NCSI_ARB_IN
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 265: 		{GPIO_SKL_H_GPP_K9,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_K_9_LAN_NCSI_ARB_OUT
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 266: 		{GPIO_SKL_H_GPP_K10, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_K_10_PE_RST_N
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 268: 		{GPIO_SKL_H_GPP_L2,  { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_2_TESTCH0_D0
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 269: 		{GPIO_SKL_H_GPP_L3,  { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_3_TESTCH0_D1
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 270: 		{GPIO_SKL_H_GPP_L4,  { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_4_TESTCH0_D2
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 271: 		{GPIO_SKL_H_GPP_L5,  { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_5_TESTCH0_D3
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 272: 		{GPIO_SKL_H_GPP_L6,  { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_6_TESTCH0_D4
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 273: 		{GPIO_SKL_H_GPP_L7,  { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_7_TESTCH0_D5
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 274: 		{GPIO_SKL_H_GPP_L8,  { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_8_TESTCH0_D6
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 275: 		{GPIO_SKL_H_GPP_L9,  { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_9_TESTCH0_D7
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 276: 		{GPIO_SKL_H_GPP_L10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_10_TESTCH0_CLK
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 277: 		{GPIO_SKL_H_GPP_L11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_11_TESTCH1_D0
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 278: 		{GPIO_SKL_H_GPP_L12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_12_TESTCH1_D1
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 279: 		{GPIO_SKL_H_GPP_L13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_13_TESTCH1_D2
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 280: 		{GPIO_SKL_H_GPP_L14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_14_TESTCH1_D3
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 281: 		{GPIO_SKL_H_GPP_L15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_15_TESTCH1_D4
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 282: 		{GPIO_SKL_H_GPP_L16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_16_TESTCH1_D5
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 283: 		{GPIO_SKL_H_GPP_L17, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_17_TESTCH1_D6
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 284: 		{GPIO_SKL_H_GPP_L18, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_18_TESTCH1_D7
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 285: 		{GPIO_SKL_H_GPP_L19, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_19_TESTCH1_CLK
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 288: 		{GPIO_SKL_H_GPD1,		{ GpioPadModeGpio,   GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPD_1_ACPRESENT
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 289: 		{GPIO_SKL_H_GPD2,		{ GpioPadModeGpio,   GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPD_2_GBE_WAKE_N
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 290: 		{GPIO_SKL_H_GPD3,		{ GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPD_3_PWRBTNB_N
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 291: 		{GPIO_SKL_H_GPD4,		{ GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPD_4_SLP_S3B
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 292: 		{GPIO_SKL_H_GPD5,		{ GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPD_5_SLP_S4B
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 293: 		{GPIO_SKL_H_GPD6,		{ GpioPadModeGpio,   GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPD_6_SLPA_N
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 294: 		{GPIO_SKL_H_GPD7,		{ GpioPadModeGpio,   GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPD_7
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 295: 		{GPIO_SKL_H_GPD8,		{ GpioPadModeGpio,   GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPD_8_CLK_33K_PCH_SUSCLK_PLD
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 296: 		{GPIO_SKL_H_GPD9,		{ GpioPadModeGpio,   GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPD_9
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 297: 		{GPIO_SKL_H_GPD10,   { GpioPadModeGpio,   GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPD_10_FM_SLPS5_N
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 298: 		{GPIO_SKL_H_GPD11,   { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPD_11_GBEPHY
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
File src/mainboard/ocp/tiogapass/skxsp_tp_iio.h:

https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 48:   // PortIndex |  HidePort  | DeEmphasis | PortLinkSpeed | MaxPayload | DfxDnTxPreset | DfxRxPreset | DfxUpTxPreset | Sris | PcieCommonClock | NtbPpd               | NtbSplitBar | NtbBarSizePBar23 | NtbBarSizePBar4 | NtbBarSizePBar5 | NtbBarSizePBar45 | NtbBarSizeSBar23 | NtbBarSizeSBar4 | NtbBarSizeSbar5 | NtbBarSizeSBar45 | NtbSBar01Prefetch | NtbXlinkCtlOverride
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 49: 	{ PORT_1A, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 50: 	{ PORT_1B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 51: 	{ PORT_1C, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 52: 	{ PORT_1D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 53: 	{ PORT_2A, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 54: 	{ PORT_2B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 55: 	{ PORT_2C, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 56: 	{ PORT_2D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 57: 	{ PORT_3A, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 58: 	{ PORT_3B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 59: 	{ PORT_3C, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
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https://review.coreboot.org/c/coreboot/+/38549/4/src/mainboard/ocp/tiogapass... 
PS4, Line 60: 	{ PORT_3D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
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[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38549 )

Change subject: Add support for OCP platform TiogaPass
......................................................................

Patch Set 4:

(2 comments)

https://review.coreboot.org/c/coreboot/+/38549/4//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/38549/4//COMMIT_MSG@9 
PS4, Line 9: 2 socket
this works as an adjective, so it should be hyphenated: 2-socket

https://review.coreboot.org/c/coreboot/+/38549/4//COMMIT_MSG@9 
PS4, Line 9: platform based on
           : Intel Skylake-SP SOC. The chipset includes Lewisburg PCH.
I would rewrite this part a bit:

platform, which combines Skylake-SP processors with the Lewisburg PCH.

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38549 )

Change subject: Add support for OCP platform TiogaPass
......................................................................

Patch Set 4:

(6 comments)

https://review.coreboot.org/c/coreboot/+/38549/4//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/38549/4//COMMIT_MSG@7 
PS4, Line 7: Add support for OCP platform TiogaPass
Please add a prefix.

https://review.coreboot.org/c/coreboot/+/38549/4//COMMIT_MSG@15 
PS4, Line 15: was
is

https://review.coreboot.org/c/coreboot/+/38549/4//COMMIT_MSG@17 
PS4, Line 17: ifconfig
ip is the successor.

https://review.coreboot.org/c/coreboot/+/38549/4//COMMIT_MSG@22 
PS4, Line 22: does
do

https://review.coreboot.org/c/coreboot/+/38549/4//COMMIT_MSG@22 
PS4, Line 22: eg. some reboots does not boot up successfully.
More details? At what point does it stop in coreboot?

https://review.coreboot.org/c/coreboot/+/38549/4//COMMIT_MSG@24 
PS4, Line 24: 3. "lspci -vvv" causes segmentation fault.
Really? Should be documented more elaborately.

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38549 )

Change subject: Add support for OCP platform TiogaPass
......................................................................

Patch Set 5:

(253 comments)

https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
File src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h:

https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 30: 		{GPIO_SKL_H_GPP_A0,  { GpioPadModeGpio,    GpioHostOwnGpio, GpioDirIn,    GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_0_LPC_RCIN_N_ESPI_ALERT1_N
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 31: 		{GPIO_SKL_H_GPP_A1,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_1_LAD_0_ESPI_IO_0
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 32: 		{GPIO_SKL_H_GPP_A2,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_2_LAD_1_ESPI_IO_1
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 33: 		{GPIO_SKL_H_GPP_A3,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_3_LAD_2_ESPI_IO_2
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 34: 		{GPIO_SKL_H_GPP_A4,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_4_LAD_3_ESPI_IO_3
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 35: 		{GPIO_SKL_H_GPP_A5,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_5_LPC_LFRAME_N_ESPI_CS0_N
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 36: 		{GPIO_SKL_H_GPP_A6,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_6_IRQ_LPC_SERIRQ_ESPI_CS1_N
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 37: 		{GPIO_SKL_H_GPP_A7,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_7_IRQ_LPC_PIRQA_N_ESPI_ALERT0_N
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 38: 		{GPIO_SKL_H_GPP_A8,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_8_FM_LPC_CLKRUN_N
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 39: 		{GPIO_SKL_H_GPP_A9,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_9_CLKOUT_LPC0_ESPI_CLK
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 40: 		{GPIO_SKL_H_GPP_A10, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_10_CLKOUT_LPC1
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 41: 		{GPIO_SKL_H_GPP_A11, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_11_FM_LPC_PME_N
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 42: 		{GPIO_SKL_H_GPP_A12, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_A_12_BMBUSY_N_SXEXITHLDOFF_N
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 43: 		{GPIO_SKL_H_GPP_A13, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_13_SUSWARN_N_SUSPWRDNACK
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 44: 		{GPIO_SKL_H_GPP_A14, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_14_ESPI_RESET_N
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 45: 		{GPIO_SKL_H_GPP_A15, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_15_SUSACK_N
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 46: 		{GPIO_SKL_H_GPP_A16, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_16_CLKOUT_LPC2
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 47: 		{GPIO_SKL_H_GPP_A17, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_17
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 48: 		{GPIO_SKL_H_GPP_A18, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_18
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 50: 		{GPIO_SKL_H_GPP_A20, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_20
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 51: 		{GPIO_SKL_H_GPP_A21, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutLow,		 GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_21
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 52: 		{GPIO_SKL_H_GPP_A22, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_22
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 53: 		{GPIO_SKL_H_GPP_A23, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_A_23
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 55: 		{GPIO_SKL_H_GPP_B0,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_0_CORE_VID_0
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 56: 		{GPIO_SKL_H_GPP_B1,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_1_CORE_VID_1
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 57: 		{GPIO_SKL_H_GPP_B2,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_2_VRALERT_N
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 58: 		{GPIO_SKL_H_GPP_B3,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_3_CPU_GP2
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 59: 		{GPIO_SKL_H_GPP_B4,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_4_CPU_GP3
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 60: 		{GPIO_SKL_H_GPP_B5,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_5_SRCCLKREQ0_N
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 61: 		{GPIO_SKL_H_GPP_B6,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_B_6_SRCCLKREQ1_N
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 62: 		{GPIO_SKL_H_GPP_B7,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_B_7_SRCCLKREQ2_N
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 63: 		{GPIO_SKL_H_GPP_B8,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_8_SRCCLKREQ3_N
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 64: 		{GPIO_SKL_H_GPP_B9,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_9_SRCCLKREQ4_N
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 65: 		{GPIO_SKL_H_GPP_B10, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_10_SRCCLKREQ5_N
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 66: 		{GPIO_SKL_H_GPP_B11, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutLow,		 GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_11
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 67: 		{GPIO_SKL_H_GPP_B12, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_12_GLB_RST_WARN_N
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 68: 		{GPIO_SKL_H_GPP_B13, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_13_RST_PLTRST_N
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 69: 		{GPIO_SKL_H_GPP_B14, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_14_FM_PCH_BIOS_RCVR_SPKR
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 70: 		{GPIO_SKL_H_GPP_B15, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_15
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 71: 		{GPIO_SKL_H_GPP_B16, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_16
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 72: 		{GPIO_SKL_H_GPP_B17, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_17
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 73: 		{GPIO_SKL_H_GPP_B18, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_18
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 74: 		{GPIO_SKL_H_GPP_B19, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutLow,		 GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_19
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 75: 		{GPIO_SKL_H_GPP_B20, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_20
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 76: 		{GPIO_SKL_H_GPP_B21, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_21
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 77: 		{GPIO_SKL_H_GPP_B22, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_B_22
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 78: 		{GPIO_SKL_H_GPP_B23, { GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut,   GpioOutLow,		 GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock} }, //GPP_B_23_MEIE_SML1ALRT_N_PHOT_N
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 82: 		{GPIO_SKL_H_GPP_C2,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_C_2_SMBALERT_N
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 85: 		{GPIO_SKL_H_GPP_C5,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPP_C_5_SML0ALERT_IE_N
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 88: 		{GPIO_SKL_H_GPP_C8,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_8
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 89: 		{GPIO_SKL_H_GPP_C9,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutLow,		 GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_9
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 90: 		{GPIO_SKL_H_GPP_C10, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_C_10
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 91: 		{GPIO_SKL_H_GPP_C11, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_11
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 92: 		{GPIO_SKL_H_GPP_C12, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_C_12
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 93: 		{GPIO_SKL_H_GPP_C13, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_C_13
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 94: 		{GPIO_SKL_H_GPP_C14, { GpioPadModeGpio,		GpioHostOwnAcpi, GpioDirIn,		GpioOutDefault, GpioIntLevel | GpioIntSci, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_C_14
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 95: 		{GPIO_SKL_H_GPP_C15, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_15
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 96: 		{GPIO_SKL_H_GPP_C16, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_16
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 97: 		{GPIO_SKL_H_GPP_C17, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_17
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 98: 		{GPIO_SKL_H_GPP_C18, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_18
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 99: 		{GPIO_SKL_H_GPP_C19, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_19
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 101: 		{GPIO_SKL_H_GPP_C21, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_21
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 102: 		{GPIO_SKL_H_GPP_C22, { GpioPadModeGpio,		GpioHostOwnAcpi, GpioDirIn,		GpioOutDefault, GpioIntLevel | GpioIntSmi, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_C_22
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 103: 		{GPIO_SKL_H_GPP_C23, { GpioPadModeGpio,		GpioHostOwnAcpi, GpioDirIn,		GpioOutDefault, GpioIntLevel | GpioIntSmi, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_C_23
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 105: 		{GPIO_SKL_H_GPP_D0,  { GpioPadModeGpio,		GpioHostOwnAcpi, GpioDirIn,		GpioOutDefault, GpioIntLevel | GpioIntSmi, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_D_0
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 106: 		{GPIO_SKL_H_GPP_D1,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_1
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 107: 		{GPIO_SKL_H_GPP_D2,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_D_2
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 108: 		{GPIO_SKL_H_GPP_D3,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_D_3
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 109: 		{GPIO_SKL_H_GPP_D4,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutLow,		 GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_4
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 110: 		{GPIO_SKL_H_GPP_D5,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_5
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 111: 		{GPIO_SKL_H_GPP_D6,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_6
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 112: 		{GPIO_SKL_H_GPP_D7,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_7
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 113: 		{GPIO_SKL_H_GPP_D8,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_8
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 114: 		{GPIO_SKL_H_GPP_D9,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_9_SSATA_DEVSLP3
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 115: 		{GPIO_SKL_H_GPP_D10, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_10_SSATA_DEVSLP4
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 116: 		{GPIO_SKL_H_GPP_D11, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_11_SSATA_DEVSLP5
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 117: 		{GPIO_SKL_H_GPP_D12, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_12_SSATA_SDATAOUT1
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 118: 		{GPIO_SKL_H_GPP_D13, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_13_SML0BLCK_IE
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 119: 		{GPIO_SKL_H_GPP_D14, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_14_SML0BDATA_IE
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 120: 		{GPIO_SKL_H_GPP_D15, { GpioPadModeNative3, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_15_SSATA_SDATAOUT0
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 121: 		{GPIO_SKL_H_GPP_D16, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_16_SML0BALERT_IE_N
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 122: 		{GPIO_SKL_H_GPP_D17, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_17
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 123: 		{GPIO_SKL_H_GPP_D18, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_18
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 124: 		{GPIO_SKL_H_GPP_D19, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutLow,		 GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock | GpioOutputStateLock} }, //GPP_D_19
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 125: 		{GPIO_SKL_H_GPP_D20, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_20_TP_PCH_GPP_D_20
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 126: 		{GPIO_SKL_H_GPP_D21, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_21_IE_URAT_RX
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 127: 		{GPIO_SKL_H_GPP_D22, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_22_IE_URAT_TX
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 128: 		{GPIO_SKL_H_GPP_D23, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_23
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 130: 		{GPIO_SKL_H_GPP_E0,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntLevel | GpioIntSmi, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_0_SATAXPCIE0_SATAGP0
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 131: 		{GPIO_SKL_H_GPP_E1,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntLevel | GpioIntSmi, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_1_SATAXPCIE1_SATAGP1
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 132: 		{GPIO_SKL_H_GPP_E2,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_2_SATAXPCIE2_SATAGP2
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 133: 		{GPIO_SKL_H_GPP_E3,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_3_CPU_GP0
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 134: 		{GPIO_SKL_H_GPP_E4,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_4_SATA_DEVSLP0
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 135: 		{GPIO_SKL_H_GPP_E5,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_5_SATA_DEVSLP1
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 136: 		{GPIO_SKL_H_GPP_E6,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_6_SATA_DEVSLP2
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 137: 		{GPIO_SKL_H_GPP_E7,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_7_CPU_GP1
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 138: 		{GPIO_SKL_H_GPP_E8,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_8_SATA_LED_N
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 139: 		{GPIO_SKL_H_GPP_E9,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_9_USB2_OC0_N
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 140: 		{GPIO_SKL_H_GPP_E10, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_10_USB2_OC1_N
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 141: 		{GPIO_SKL_H_GPP_E11, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_11_USB2_OC2_N
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 142: 		{GPIO_SKL_H_GPP_E12, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_E_12_USB2_OC3_N
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 144: 		{GPIO_SKL_H_GPP_F0,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_F_0_SATAXPCIE3_SATAGP3
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 145: 		{GPIO_SKL_H_GPP_F1,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_F_1_SATAXPCIE4_SATAGP4
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 146: 		{GPIO_SKL_H_GPP_F2,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_F_2_SATAXPCIE5_SATAGP5
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 147: 		{GPIO_SKL_H_GPP_F3,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_F_3_SATAXPCIE6_SATAGP6
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 148: 		{GPIO_SKL_H_GPP_F4,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_F_4_SATAXPCIE7_SATAGP7
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 149: 		{GPIO_SKL_H_GPP_F5,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_F_5_SATA_DEVSLP3
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 150: 		{GPIO_SKL_H_GPP_F6,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_F_6_SATA_DEVSLP4
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 151: 		{GPIO_SKL_H_GPP_F7,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_F_7_SATA_DEVSLP5
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 152: 		{GPIO_SKL_H_GPP_F8,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_F_8_SATA_DEVSLP6
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 153: 		{GPIO_SKL_H_GPP_F9,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_F_9_SATA_DEVSLP7
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 154: 		{GPIO_SKL_H_GPP_F10, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_10_SATA_SCLOCK
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 155: 		{GPIO_SKL_H_GPP_F11, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_11_SATA_SLOAD
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 156: 		{GPIO_SKL_H_GPP_F12, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_12_SATA_SDATAOUT1
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 157: 		{GPIO_SKL_H_GPP_F13, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_13_SATA_SDATAOUT0
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 158: 		{GPIO_SKL_H_GPP_F14, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_14_SSATA_LED_N
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 159: 		{GPIO_SKL_H_GPP_F15, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_15_USB2_OC4_N
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 160: 		{GPIO_SKL_H_GPP_F16, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_16_USB2_OC5_N
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 161: 		{GPIO_SKL_H_GPP_F17, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_17_USB2_OC6_N
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 162: 		{GPIO_SKL_H_GPP_F18, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_18_USB2_OC7_N
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 163: 		{GPIO_SKL_H_GPP_F19, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_19_LAN_SMBCLK
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 164: 		{GPIO_SKL_H_GPP_F20, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_20_LAN_SMBDATA
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 165: 		{GPIO_SKL_H_GPP_F21, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_21_LAN_SMBALERT_N
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 166: 		{GPIO_SKL_H_GPP_F22, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_22_SSATA_SCLOCK
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 167: 		{GPIO_SKL_H_GPP_F23, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_23_SSATA_SLOAD
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 169: 		{GPIO_SKL_H_GPP_G0,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_0_FANTACH0_FANTACH0IE
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 170: 		{GPIO_SKL_H_GPP_G1,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_1_FANTACH1_FANTACH1IE
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 171: 		{GPIO_SKL_H_GPP_G2,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_2_FANTACH2_FANTACH2IE
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 172: 		{GPIO_SKL_H_GPP_G3,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_3_FANTACH3_FANTACH3IE
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 173: 		{GPIO_SKL_H_GPP_G4,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_4_FANTACH4_FANTACH4IE
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 174: 		{GPIO_SKL_H_GPP_G5,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_5_FANTACH5_FANTACH5IE
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 175: 		{GPIO_SKL_H_GPP_G6,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_6_FANTACH6_FANTACH6IE
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 176: 		{GPIO_SKL_H_GPP_G7,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_7_FANTACH7_FANTACH7IE
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 177: 		{GPIO_SKL_H_GPP_G8,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_8_FANPWM0_FANPWM0IE
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 178: 		{GPIO_SKL_H_GPP_G9,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_9_FANPWM1_FANPWM1IE
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 179: 		{GPIO_SKL_H_GPP_G10, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_10_FANPWM2_FANPWM2IE
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 180: 		{GPIO_SKL_H_GPP_G11, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_11_FANPWM3_FANPWM3IE
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 181: 		{GPIO_SKL_H_GPP_G12, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_12
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 182: 		{GPIO_SKL_H_GPP_G13, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_13
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 183: 		{GPIO_SKL_H_GPP_G14, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_14
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 184: 		{GPIO_SKL_H_GPP_G15, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_15
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 185: 		{GPIO_SKL_H_GPP_G16, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_16
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 186: 		{GPIO_SKL_H_GPP_G17, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_17_ADR_COMPLETE
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 187: 		{GPIO_SKL_H_GPP_G18, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_18_FM_NMI_EVENT_N
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 188: 		{GPIO_SKL_H_GPP_G19, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_19_FM_SMI_ACTIVE_N
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 190: 		{GPIO_SKL_H_GPP_G21, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_21_SSATA_DEVSLP1
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 191: 		{GPIO_SKL_H_GPP_G22, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_G_22_SSATA_DEVSLP2
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 192: 		{GPIO_SKL_H_GPP_G23, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_23_SSATAXPCIE0_SSATAGP0
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 194: 		{GPIO_SKL_H_GPP_H0,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_H_0_SRCCLKREQ6_N
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 195: 		{GPIO_SKL_H_GPP_H1,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_H_1_SRCCLKREQ7_N
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 196: 		{GPIO_SKL_H_GPP_H2,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_H_2_SRCCLKREQ8_N
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 197: 		{GPIO_SKL_H_GPP_H3,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_H_3_SRCCLKREQ9_N
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 198: 		{GPIO_SKL_H_GPP_H4,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_H_4_SRCCLKREQ10_N
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 200: 		{GPIO_SKL_H_GPP_H6,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_H_6_SRCCLKREQ12_N
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 201: 		{GPIO_SKL_H_GPP_H7,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_H_7_SRCCLKREQ13_N
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 202: 		{GPIO_SKL_H_GPP_H8,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_H_8_SRCCLKREQ14_N
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 203: 		{GPIO_SKL_H_GPP_H9,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_H_9_SRCCLKREQ15_N
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 206: 		{GPIO_SKL_H_GPP_H12, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_H_12_SML2ALERT_N_IE
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 209: 		{GPIO_SKL_H_GPP_H15, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_H_15_SML3ALERT_N_IE
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 212: 		{GPIO_SKL_H_GPP_H18, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_H_18_SML4ALERT_N_IE
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 213: 		{GPIO_SKL_H_GPP_H19, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_H_19_SSATAXPCIE1_SSATAGP1
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 214: 		{GPIO_SKL_H_GPP_H20, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_H_20_SSATAXPCIE2_SSATAGP2
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 215: 		{GPIO_SKL_H_GPP_H21, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_H_21_SSATAXPCIE3_SSATAGP3
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 216: 		{GPIO_SKL_H_GPP_H22, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_H_22_SSATAXPCIE4_SSATAGP4
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 217: 		{GPIO_SKL_H_GPP_H23, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_H_23_SSATAXPCIE5_SSATAGP5
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 219: 		{GPIO_SKL_H_GPP_I0,  { GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_I_0_GBE_TDO
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 220: 		{GPIO_SKL_H_GPP_I1,  { GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_I_1_GBE_TCK
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 221: 		{GPIO_SKL_H_GPP_I2,  { GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_I_2_GBE_TMS
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 222: 		{GPIO_SKL_H_GPP_I3,  { GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_I_3_GBE_TDI
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 223: 		{GPIO_SKL_H_GPP_I4,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_I_4_DO_RESET_IN_N
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 224: 		{GPIO_SKL_H_GPP_I5,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_I_5_DO_RESET_OUT_N
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 225: 		{GPIO_SKL_H_GPP_I6,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_I_6_RESET_DONE
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 226: 		{GPIO_SKL_H_GPP_I7,  { GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_I_7_JTAG_GBE_TRST_N
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 227: 		{GPIO_SKL_H_GPP_I8,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_I_8_GBE_PCI_DIS
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 228: 		{GPIO_SKL_H_GPP_I9,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_I_9_GBE_LAN_DIS
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 229: 		{GPIO_SKL_H_GPP_I10, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_I_10
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 231: 		{GPIO_SKL_H_GPP_J0,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_0_LAN_LED_P0_0
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 232: 		{GPIO_SKL_H_GPP_J1,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_1_LAN_LED_P0_1
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 233: 		{GPIO_SKL_H_GPP_J2,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_2_LAN_LED_P1_0
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 234: 		{GPIO_SKL_H_GPP_J3,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_3_LAN_LED_P1_1
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 235: 		{GPIO_SKL_H_GPP_J4,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_4_LAN_LED_P2_0
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 236: 		{GPIO_SKL_H_GPP_J5,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_5_LAN_LED_P2_1
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 237: 		{GPIO_SKL_H_GPP_J6,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_6_LAN_LED_P3_0
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 238: 		{GPIO_SKL_H_GPP_J7,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_7_LAN_LED_P3_1
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 239: 		{GPIO_SKL_H_GPP_J8,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_8_LAN_I2C_SCL_MDC_P0
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 240: 		{GPIO_SKL_H_GPP_J9,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_9_LAN_I2C_SDA_MDIO_P0
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 241: 		{GPIO_SKL_H_GPP_J10, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_10_LAN_I2C_SCL_MDC_P1
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 242: 		{GPIO_SKL_H_GPP_J11, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_11_LAN_I2C_SDA_MDIO_P1
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 243: 		{GPIO_SKL_H_GPP_J12, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_12_LAN_I2C_SCL_MDC_P2
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 244: 		{GPIO_SKL_H_GPP_J13, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_13_LAN_I2C_SDA_MDIO_P2
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 245: 		{GPIO_SKL_H_GPP_J14, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_14_LAN_I2C_SCL_MDC_P3
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 246: 		{GPIO_SKL_H_GPP_J15, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_15_LAN_I2C_SDA_MDIO_P3
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 247: 		{GPIO_SKL_H_GPP_J16, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_16_LAN_SDP_P0_0
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 248: 		{GPIO_SKL_H_GPP_J17, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_17_LAN_SDP_P0_1
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 249: 		{GPIO_SKL_H_GPP_J18, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_18_LAN_SDP_P1_0
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 250: 		{GPIO_SKL_H_GPP_J19, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_19_LAN_SDP_P1_1
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 251: 		{GPIO_SKL_H_GPP_J20, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_20_LAN_SDP_P2_0
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 252: 		{GPIO_SKL_H_GPP_J21, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_21_LAN_SDP_P2_1
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 253: 		{GPIO_SKL_H_GPP_J22, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_22_LAN_SDP_P3_0
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 254: 		{GPIO_SKL_H_GPP_J23, { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_J_23_LAN_SDP_P3_1
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 256: 		{GPIO_SKL_H_GPP_K0,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_K_0_LAN_NCSI_CLK_IN
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 257: 		{GPIO_SKL_H_GPP_K1,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_K_1_LAN_NCSI_TXD0
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 258: 		{GPIO_SKL_H_GPP_K2,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_K_2_LAN_NCSI_TXD1
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 259: 		{GPIO_SKL_H_GPP_K3,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_K_3_LAN_NCSI_TX_EN
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 260: 		{GPIO_SKL_H_GPP_K4,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_K_4_LAN_NCSI_CRS_DV
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 261: 		{GPIO_SKL_H_GPP_K5,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_K_5_LAN_NCSI_RXD0
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 262: 		{GPIO_SKL_H_GPP_K6,  { GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_K_6_LAN_NCSI_RXD1
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 263: 		{GPIO_SKL_H_GPP_K7,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_K_7
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 264: 		{GPIO_SKL_H_GPP_K8,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,  GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_K_8_LAN_NCSI_ARB_IN
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 265: 		{GPIO_SKL_H_GPP_K9,  { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_K_9_LAN_NCSI_ARB_OUT
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 266: 		{GPIO_SKL_H_GPP_K10, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_K_10_PE_RST_N
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 268: 		{GPIO_SKL_H_GPP_L2,  { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_2_TESTCH0_D0
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 269: 		{GPIO_SKL_H_GPP_L3,  { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_3_TESTCH0_D1
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 270: 		{GPIO_SKL_H_GPP_L4,  { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_4_TESTCH0_D2
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 271: 		{GPIO_SKL_H_GPP_L5,  { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_5_TESTCH0_D3
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 272: 		{GPIO_SKL_H_GPP_L6,  { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_6_TESTCH0_D4
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 273: 		{GPIO_SKL_H_GPP_L7,  { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_7_TESTCH0_D5
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 274: 		{GPIO_SKL_H_GPP_L8,  { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_8_TESTCH0_D6
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 275: 		{GPIO_SKL_H_GPP_L9,  { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_9_TESTCH0_D7
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 276: 		{GPIO_SKL_H_GPP_L10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_10_TESTCH0_CLK
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 277: 		{GPIO_SKL_H_GPP_L11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_11_TESTCH1_D0
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 278: 		{GPIO_SKL_H_GPP_L12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_12_TESTCH1_D1
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 279: 		{GPIO_SKL_H_GPP_L13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_13_TESTCH1_D2
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 280: 		{GPIO_SKL_H_GPP_L14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_14_TESTCH1_D3
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 281: 		{GPIO_SKL_H_GPP_L15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_15_TESTCH1_D4
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 282: 		{GPIO_SKL_H_GPP_L16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_16_TESTCH1_D5
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 283: 		{GPIO_SKL_H_GPP_L17, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_17_TESTCH1_D6
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 284: 		{GPIO_SKL_H_GPP_L18, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_18_TESTCH1_D7
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 285: 		{GPIO_SKL_H_GPP_L19, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault, GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock} }, //GPP_L_19_TESTCH1_CLK
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 288: 		{GPIO_SKL_H_GPD1,		{ GpioPadModeGpio,   GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPD_1_ACPRESENT
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 289: 		{GPIO_SKL_H_GPD2,		{ GpioPadModeGpio,   GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPD_2_GBE_WAKE_N
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 290: 		{GPIO_SKL_H_GPD3,		{ GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPD_3_PWRBTNB_N
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 291: 		{GPIO_SKL_H_GPD4,		{ GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPD_4_SLP_S3B
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https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 292: 		{GPIO_SKL_H_GPD5,		{ GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault, GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPD_5_SLP_S4B
line over 96 characters

https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 293: 		{GPIO_SKL_H_GPD6,		{ GpioPadModeGpio,   GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPD_6_SLPA_N
line over 96 characters

https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 294: 		{GPIO_SKL_H_GPD7,		{ GpioPadModeGpio,   GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPD_7
line over 96 characters

https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 295: 		{GPIO_SKL_H_GPD8,		{ GpioPadModeGpio,   GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPD_8_CLK_33K_PCH_SUSCLK_PLD
line over 96 characters

https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 296: 		{GPIO_SKL_H_GPD9,		{ GpioPadModeGpio,   GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPD_9
line over 96 characters

https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 297: 		{GPIO_SKL_H_GPD10,   { GpioPadModeGpio,   GpioHostOwnGpio, GpioDirIn,		GpioOutDefault, GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPD_10_FM_SLPS5_N
line over 96 characters

https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 298: 		{GPIO_SKL_H_GPD11,   { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutLow,		 GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock} }, //GPD_11_GBEPHY
line over 96 characters

https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
File src/mainboard/ocp/tiogapass/skxsp_tp_iio.h:

https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 48:   // PortIndex |  HidePort  | DeEmphasis | PortLinkSpeed | MaxPayload | DfxDnTxPreset | DfxRxPreset | DfxUpTxPreset | Sris | PcieCommonClock | NtbPpd               | NtbSplitBar | NtbBarSizePBar23 | NtbBarSizePBar4 | NtbBarSizePBar5 | NtbBarSizePBar45 | NtbBarSizeSBar23 | NtbBarSizeSBar4 | NtbBarSizeSbar5 | NtbBarSizeSBar45 | NtbSBar01Prefetch | NtbXlinkCtlOverride
line over 96 characters

https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 49: 	{ PORT_1A, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
line over 96 characters

https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 50: 	{ PORT_1B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
line over 96 characters

https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 51: 	{ PORT_1C, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
line over 96 characters

https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 52: 	{ PORT_1D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
line over 96 characters

https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 53: 	{ PORT_2A, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
line over 96 characters

https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 54: 	{ PORT_2B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
line over 96 characters

https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 55: 	{ PORT_2C, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
line over 96 characters

https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 56: 	{ PORT_2D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
line over 96 characters

https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 57: 	{ PORT_3A, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
line over 96 characters

https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 58: 	{ PORT_3B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
line over 96 characters

https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 59: 	{ PORT_3C, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
line over 96 characters

https://review.coreboot.org/c/coreboot/+/38549/5/src/mainboard/ocp/tiogapass... 
PS5, Line 60: 	{ PORT_3D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
line over 96 characters

[Jonathan Zhang (Code Review)]

Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38549 )

Change subject: Add support for OCP platform TiogaPass
......................................................................

Patch Set 5:

(7 comments)

Thanks for the review. Will update an updated patch set over the weekend.

https://review.coreboot.org/c/coreboot/+/38549/4//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/38549/4//COMMIT_MSG@7 
PS4, Line 7: Add support for OCP platform TiogaPass
> Please add a prefix.

Done

https://review.coreboot.org/c/coreboot/+/38549/4//COMMIT_MSG@9 
PS4, Line 9: 2 socket
> this works as an adjective, so it should be hyphenated: 2-socket

Done

https://review.coreboot.org/c/coreboot/+/38549/4//COMMIT_MSG@9 
PS4, Line 9: platform based on
           : Intel Skylake-SP SOC. The chipset includes Lewisburg PCH.
> I would rewrite this part a bit: […]

Done

https://review.coreboot.org/c/coreboot/+/38549/4//COMMIT_MSG@15 
PS4, Line 15: was
> is

Done

https://review.coreboot.org/c/coreboot/+/38549/4//COMMIT_MSG@17 
PS4, Line 17: ifconfig
> ip is the successor.

Done

https://review.coreboot.org/c/coreboot/+/38549/4//COMMIT_MSG@22 
PS4, Line 22: does
> do

Done

https://review.coreboot.org/c/coreboot/+/38549/4//COMMIT_MSG@24 
PS4, Line 24: 3. "lspci -vvv" causes segmentation fault.
> Really? Should be documented more elaborately.

Actually after I flashed in traditional UEFI firmware, the same problem happens. This might has something to do with target OS kernel, which is quite old (4.16.0). So I am removing this as a known issue.

Change in coreboot[master]: mainboard/ocp: Add support for OCP platform TiogaPass

[Jonathan Zhang (Code Review)]

Hello David Hendricks, build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38549

to look at the new patch set (#6).

Change subject: mainboard/ocp: Add support for OCP platform TiogaPass
......................................................................

mainboard/ocp: Add support for OCP platform TiogaPass

OCP platform Tiogapass is a 2-socket server platform, which
is based on a chipset including Intel Skylake-SP processors
and a Lewisburg PCH.

Following ACPI tables are added:
DSDT/SSDT, MADT, FACP, FACS, HPET, MCFG, SLIT, SRAT, DMAR

This patchset is tested on a Tiogapass board. It booted with
Linux kernel 4.16.0; lscpu command shows all 72 cpus (2 sockets,
18 cores, 2 thread per core); ssh command shows
networking is up from Mellanox ConnectX-4 PCIe NIC card.

Known issues:
1. MP init does not work reliably, this causes reboot stability,
eg. some reboots do not boot up successfully.
2. c6 state is not supported.

Signed-off-by: Jonathan Zhang 
Signed-off-by: Reddy Chagam 
Change-Id: I29868f03037d1887b90dfb19d15aee83c456edce
---
A src/mainboard/ocp/Kconfig
A src/mainboard/ocp/Kconfig.name
A src/mainboard/ocp/tiogapass/Kconfig
A src/mainboard/ocp/tiogapass/Kconfig.name
A src/mainboard/ocp/tiogapass/Makefile.inc
A src/mainboard/ocp/tiogapass/acpi/platform.asl
A src/mainboard/ocp/tiogapass/acpi_tables.c
A src/mainboard/ocp/tiogapass/board_info.txt
A src/mainboard/ocp/tiogapass/boardid.c
A src/mainboard/ocp/tiogapass/devicetree.cb
A src/mainboard/ocp/tiogapass/dsdt.asl
A src/mainboard/ocp/tiogapass/emmc.h
A src/mainboard/ocp/tiogapass/fadt.c
A src/mainboard/ocp/tiogapass/ramstage.c
A src/mainboard/ocp/tiogapass/romstage.c
A src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h
A src/mainboard/ocp/tiogapass/skxsp_tp_iio.h
A src/mainboard/ocp/tiogapass/tiogapass_boardid.h
A src/mainboard/ocp/tiogapass/vboot-ro.fmd
19 files changed, 2,069 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/38549/6

Change in coreboot[master]: mainboard/ocp: Add support for OCP platform TiogaPass

[Jonathan Zhang (Code Review)]

Hello David Hendricks, build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38549

to look at the new patch set (#7).

Change subject: mainboard/ocp: Add support for OCP platform TiogaPass
......................................................................

mainboard/ocp: Add support for OCP platform TiogaPass

OCP platform Tiogapass is a 2-socket server platform, which
is based on a chipset including Intel Skylake-SP processors
and a Lewisburg PCH.

Following ACPI tables are added:
DSDT/SSDT, MADT, FACP, FACS, HPET, MCFG, SLIT, SRAT, DMAR

This patchset is tested on a Tiogapass board. It booted with
Linux kernel 4.16.0; lscpu command shows all 72 cpus (2 sockets,
18 cores, 2 thread per core); ssh command shows
networking is up from Mellanox ConnectX-4 PCIe NIC card.

Known issues:
1. MP init does not work reliably, this causes reboot stability,
eg. some reboots do not boot up successfully.
2. c6 state is not supported.

Signed-off-by: Jonathan Zhang 
Signed-off-by: Reddy Chagam 
Change-Id: I29868f03037d1887b90dfb19d15aee83c456edce
---
A src/mainboard/ocp/Kconfig
A src/mainboard/ocp/Kconfig.name
A src/mainboard/ocp/tiogapass/Kconfig
A src/mainboard/ocp/tiogapass/Kconfig.name
A src/mainboard/ocp/tiogapass/Makefile.inc
A src/mainboard/ocp/tiogapass/acpi/platform.asl
A src/mainboard/ocp/tiogapass/acpi_tables.c
A src/mainboard/ocp/tiogapass/board_info.txt
A src/mainboard/ocp/tiogapass/boardid.c
A src/mainboard/ocp/tiogapass/devicetree.cb
A src/mainboard/ocp/tiogapass/dsdt.asl
A src/mainboard/ocp/tiogapass/emmc.h
A src/mainboard/ocp/tiogapass/fadt.c
A src/mainboard/ocp/tiogapass/ramstage.c
A src/mainboard/ocp/tiogapass/romstage.c
A src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h
A src/mainboard/ocp/tiogapass/skxsp_tp_iio.h
A src/mainboard/ocp/tiogapass/tiogapass_boardid.h
A src/mainboard/ocp/tiogapass/vboot-ro.fmd
19 files changed, 2,064 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/38549/7

Change in coreboot[master]: mainboard/ocp: Add support for OCP platform TiogaPass

[Jonathan Zhang (Code Review)]

Hello David Hendricks, build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38549

to look at the new patch set (#8).

Change subject: mainboard/ocp: Add support for OCP platform TiogaPass
......................................................................

mainboard/ocp: Add support for OCP platform TiogaPass

OCP platform Tiogapass is a 2-socket server platform, which
is based on a chipset including Intel Skylake-SP processors
and a Lewisburg PCH.

Following ACPI tables are added:
DSDT/SSDT, MADT, FACP, FACS, HPET, MCFG, SLIT, SRAT, DMAR

This patchset is tested on a Tiogapass board. It booted with
Linux kernel 4.16.0; lscpu command shows all 72 cpus (2 sockets,
18 cores, 2 thread per core); ssh command shows
networking is up from Mellanox ConnectX-4 PCIe NIC card.

Known issues:
1. MP init does not work reliably, this causes reboot stability,
eg. some reboots do not boot up successfully.
2. c6 state is not supported.

Signed-off-by: Jonathan Zhang 
Signed-off-by: Reddy Chagam 
Change-Id: I29868f03037d1887b90dfb19d15aee83c456edce
---
A src/mainboard/ocp/Kconfig
A src/mainboard/ocp/Kconfig.name
A src/mainboard/ocp/tiogapass/Kconfig
A src/mainboard/ocp/tiogapass/Kconfig.name
A src/mainboard/ocp/tiogapass/Makefile.inc
A src/mainboard/ocp/tiogapass/acpi/platform.asl
A src/mainboard/ocp/tiogapass/acpi_tables.c
A src/mainboard/ocp/tiogapass/board_info.txt
A src/mainboard/ocp/tiogapass/boardid.c
A src/mainboard/ocp/tiogapass/devicetree.cb
A src/mainboard/ocp/tiogapass/dsdt.asl
A src/mainboard/ocp/tiogapass/emmc.h
A src/mainboard/ocp/tiogapass/fadt.c
A src/mainboard/ocp/tiogapass/ramstage.c
A src/mainboard/ocp/tiogapass/romstage.c
A src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h
A src/mainboard/ocp/tiogapass/skxsp_tp_iio.h
A src/mainboard/ocp/tiogapass/tiogapass_boardid.h
A src/mainboard/ocp/tiogapass/vboot-ro.fmd
19 files changed, 2,064 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/38549/8

Change in coreboot[master]: mainboard/ocp: Add support for OCP platform TiogaPass

[Jonathan Zhang (Code Review)]

Hello David Hendricks, build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38549

to look at the new patch set (#9).

Change subject: mainboard/ocp: Add support for OCP platform TiogaPass
......................................................................

mainboard/ocp: Add support for OCP platform TiogaPass

OCP platform Tiogapass is a 2-socket server platform, which
is based on a chipset including Intel Skylake-SP processors
and a Lewisburg PCH.

Following ACPI tables are added:
DSDT/SSDT, MADT, FACP, FACS, HPET, MCFG, SLIT, SRAT, DMAR

This patchset is tested on a Tiogapass board. It booted with
Linux kernel 4.16.0; lscpu command shows all 72 cpus (2 sockets,
18 cores, 2 thread per core); ssh command shows
networking is up from Mellanox ConnectX-4 PCIe NIC card.

Known issues:
1. MP init does not work reliably, this causes reboot stability,
eg. some reboots do not boot up successfully. When this happens,
coreboot fails with an assert, indicating there is a MP boot
init timeout.
2. c6 state is not supported.

Signed-off-by: Jonathan Zhang 
Signed-off-by: Reddy Chagam 
Change-Id: I29868f03037d1887b90dfb19d15aee83c456edce
---
A src/mainboard/ocp/Kconfig
A src/mainboard/ocp/Kconfig.name
A src/mainboard/ocp/tiogapass/Kconfig
A src/mainboard/ocp/tiogapass/Kconfig.name
A src/mainboard/ocp/tiogapass/Makefile.inc
A src/mainboard/ocp/tiogapass/acpi/platform.asl
A src/mainboard/ocp/tiogapass/acpi_tables.c
A src/mainboard/ocp/tiogapass/board_info.txt
A src/mainboard/ocp/tiogapass/boardid.c
A src/mainboard/ocp/tiogapass/devicetree.cb
A src/mainboard/ocp/tiogapass/dsdt.asl
A src/mainboard/ocp/tiogapass/emmc.h
A src/mainboard/ocp/tiogapass/fadt.c
A src/mainboard/ocp/tiogapass/ramstage.c
A src/mainboard/ocp/tiogapass/romstage.c
A src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h
A src/mainboard/ocp/tiogapass/skxsp_tp_iio.h
A src/mainboard/ocp/tiogapass/tiogapass_boardid.h
A src/mainboard/ocp/tiogapass/vboot-ro.fmd
19 files changed, 2,064 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/38549/9

Change in coreboot[master]: mainboard/ocp: Add support for OCP platform TiogaPass

[HAOUAS Elyes (Code Review)]

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38549 )

Change subject: mainboard/ocp: Add support for OCP platform TiogaPass
......................................................................

Patch Set 9: Code-Review-1

(1 comment)

https://review.coreboot.org/c/coreboot/+/38549/9/src/mainboard/ocp/tiogapass... 
File src/mainboard/ocp/tiogapass/acpi_tables.c:

https://review.coreboot.org/c/coreboot/+/38549/9/src/mainboard/ocp/tiogapass... 
PS9, Line 18: #include <types.h>
            : #include <string.h>
            : #include <arch/acpi.h>
            : #include <arch/ioapic.h>
            : #include <arch/acpigen.h>
            : #include <arch/smp/mpspec.h>
            : #include <device/device.h>
            : #include <device/pci.h>
            : #include <cpu/x86/msr.h>
            : 
            : #include <intelblocks/acpi.h>
            : #include <soc/acpi.h>
            : #include <soc/nvs.h>
Please include only what you use.
Please check the other files.

Change in coreboot[master]: mainboard/ocp: Add support for OCP platform TiogaPass

[Jonathan Zhang (Code Review)]

Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38549 )

Change subject: mainboard/ocp: Add support for OCP platform TiogaPass
......................................................................

Patch Set 9:

(1 comment)

Rebased to upstream tip:
e4d6c033fe (origin/master, origin/HEAD) Doc/mb/lenovo: Shrink picture for x301

Tested on TiogaPass server without regression observed.

https://review.coreboot.org/c/coreboot/+/38549/9/src/mainboard/ocp/tiogapass... 
File src/mainboard/ocp/tiogapass/acpi_tables.c:

https://review.coreboot.org/c/coreboot/+/38549/9/src/mainboard/ocp/tiogapass... 
PS9, Line 18: #include <types.h>
            : #include <string.h>
            : #include <arch/acpi.h>
            : #include <arch/ioapic.h>
            : #include <arch/acpigen.h>
            : #include <arch/smp/mpspec.h>
            : #include <device/device.h>
            : #include <device/pci.h>
            : #include <cpu/x86/msr.h>
            : 
            : #include <intelblocks/acpi.h>
            : #include <soc/acpi.h>
            : #include <soc/nvs.h>
> Please include only what you use. […]

Done

Change in coreboot[master]: mainboard/ocp: Add support for OCP platform TiogaPass

[Jonathan Zhang (Code Review)]

Hello HAOUAS Elyes, David Hendricks, build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38549

to look at the new patch set (#10).

Change subject: mainboard/ocp: Add support for OCP platform TiogaPass
......................................................................

mainboard/ocp: Add support for OCP platform TiogaPass

OCP platform Tiogapass is a 2-socket server platform, which
is based on a chipset including Intel Skylake-SP processors
and a Lewisburg PCH.

Following ACPI tables are added:
DSDT/SSDT, MADT, FACP, FACS, HPET, MCFG, SLIT, SRAT, DMAR

This patchset is tested on a Tiogapass board. It booted with
Linux kernel 4.16.0; lscpu command shows all 72 cpus (2 sockets,
18 cores, 2 thread per core); ssh command shows
networking is up from Mellanox ConnectX-4 PCIe NIC card.

Known issues (Not intend to address in this initial support for
Xeon-SP processors):
1. MP init does not work reliably, this causes reboot stability,
eg. some reboots do not boot up successfully. When this happens,
coreboot fails with an assert, indicating there is a MP boot
init timeout.
2. c6 state is not supported.
3. dsdt table is not fully populated, such as processor/socket
devices, some PCIe devices.
4. SMM handlers are not added.

Signed-off-by: Jonathan Zhang 
Signed-off-by: Reddy Chagam 
Change-Id: I29868f03037d1887b90dfb19d15aee83c456edce
---
A src/mainboard/ocp/Kconfig
A src/mainboard/ocp/Kconfig.name
A src/mainboard/ocp/tiogapass/Kconfig
A src/mainboard/ocp/tiogapass/Kconfig.name
A src/mainboard/ocp/tiogapass/Makefile.inc
A src/mainboard/ocp/tiogapass/acpi/platform.asl
A src/mainboard/ocp/tiogapass/acpi_tables.c
A src/mainboard/ocp/tiogapass/board_info.txt
A src/mainboard/ocp/tiogapass/boardid.c
A src/mainboard/ocp/tiogapass/devicetree.cb
A src/mainboard/ocp/tiogapass/dsdt.asl
A src/mainboard/ocp/tiogapass/emmc.h
A src/mainboard/ocp/tiogapass/fadt.c
A src/mainboard/ocp/tiogapass/ramstage.c
A src/mainboard/ocp/tiogapass/romstage.c
A src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h
A src/mainboard/ocp/tiogapass/skxsp_tp_iio.h
A src/mainboard/ocp/tiogapass/tiogapass_boardid.h
A src/mainboard/ocp/tiogapass/vboot-ro.fmd
19 files changed, 2,053 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/38549/10

Change in coreboot[master]: mainboard/ocp: Add support for OCP platform TiogaPass

[Jonathan Zhang (Code Review)]

Hello HAOUAS Elyes, David Hendricks, build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38549

to look at the new patch set (#11).

Change subject: mainboard/ocp: Add support for OCP platform TiogaPass
......................................................................

mainboard/ocp: Add support for OCP platform TiogaPass

OCP platform Tiogapass is a 2-socket server platform, which
is based on a chipset including Intel Skylake-SP processors
and a Lewisburg PCH.

Following ACPI tables are added:
DSDT/SSDT, MADT, FACP, FACS, HPET, MCFG, SLIT, SRAT, DMAR

This patchset is tested on a Tiogapass board. It booted with
Linux kernel 4.16.0; lscpu command shows all 72 cpus (2 sockets,
18 cores, 2 thread per core); ssh command shows
networking is up from Mellanox ConnectX-4 PCIe NIC card.

Known issues (Not intend to address in this initial support for
Xeon-SP processors):
1. MP init does not work reliably, this causes reboot stability,
eg. some reboots do not boot up successfully. When this happens,
coreboot fails with an assert, indicating there is a MP boot
init timeout.
2. c6 state is not supported.
3. dsdt table is not fully populated, such as processor/socket
devices, some PCIe devices.
4. SMM handlers are not added.

Signed-off-by: Jonathan Zhang 
Signed-off-by: Reddy Chagam 
Change-Id: I29868f03037d1887b90dfb19d15aee83c456edce
---
A src/mainboard/ocp/Kconfig
A src/mainboard/ocp/Kconfig.name
A src/mainboard/ocp/tiogapass/Kconfig
A src/mainboard/ocp/tiogapass/Kconfig.name
A src/mainboard/ocp/tiogapass/Makefile.inc
A src/mainboard/ocp/tiogapass/acpi/platform.asl
A src/mainboard/ocp/tiogapass/acpi_tables.c
A src/mainboard/ocp/tiogapass/board_info.txt
A src/mainboard/ocp/tiogapass/boardid.c
A src/mainboard/ocp/tiogapass/devicetree.cb
A src/mainboard/ocp/tiogapass/dsdt.asl
A src/mainboard/ocp/tiogapass/emmc.h
A src/mainboard/ocp/tiogapass/fadt.c
A src/mainboard/ocp/tiogapass/ramstage.c
A src/mainboard/ocp/tiogapass/romstage.c
A src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h
A src/mainboard/ocp/tiogapass/skxsp_tp_iio.h
A src/mainboard/ocp/tiogapass/tiogapass_boardid.h
A src/mainboard/ocp/tiogapass/vboot-ro.fmd
19 files changed, 2,053 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/38549/11

Change in coreboot[master]: mainboard/ocp: Add support for OCP platform TiogaPass

[Jonathan Zhang (Code Review)]

Hello HAOUAS Elyes, David Hendricks, build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38549

to look at the new patch set (#12).

Change subject: mainboard/ocp: Add support for OCP platform TiogaPass
......................................................................

mainboard/ocp: Add support for OCP platform TiogaPass

OCP platform Tiogapass is a 2-socket server platform, which
is based on a chipset including Intel Skylake-SP processors
and a Lewisburg PCH.

Following ACPI tables are added:
DSDT/SSDT, MADT, FACP, FACS, HPET, MCFG, SLIT, SRAT, DMAR

This patchset is tested on a Tiogapass board. It booted with
Linux kernel 4.16.0; lscpu command shows all 72 cpus (2 sockets,
18 cores, 2 thread per core); ssh command shows
networking is up from Mellanox ConnectX-4 PCIe NIC card.

Known issues (Not intend to address in this initial support for
Xeon-SP processors):
1. MP init does not work reliably, this causes reboot stability,
eg. some reboots do not boot up successfully. When this happens,
coreboot fails with an assert, indicating there is a MP boot
init timeout.
2. c6 state is not supported.
3. dsdt table is not fully populated, such as processor/socket
devices, some PCIe devices.
4. SMM handlers are not added.

Signed-off-by: Jonathan Zhang 
Signed-off-by: Reddy Chagam 
Change-Id: I29868f03037d1887b90dfb19d15aee83c456edce
---
A src/mainboard/ocp/Kconfig
A src/mainboard/ocp/Kconfig.name
A src/mainboard/ocp/tiogapass/Kconfig
A src/mainboard/ocp/tiogapass/Kconfig.name
A src/mainboard/ocp/tiogapass/Makefile.inc
A src/mainboard/ocp/tiogapass/acpi/platform.asl
A src/mainboard/ocp/tiogapass/acpi_tables.c
A src/mainboard/ocp/tiogapass/board_info.txt
A src/mainboard/ocp/tiogapass/boardid.c
A src/mainboard/ocp/tiogapass/devicetree.cb
A src/mainboard/ocp/tiogapass/dsdt.asl
A src/mainboard/ocp/tiogapass/emmc.h
A src/mainboard/ocp/tiogapass/fadt.c
A src/mainboard/ocp/tiogapass/ramstage.c
A src/mainboard/ocp/tiogapass/romstage.c
A src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h
A src/mainboard/ocp/tiogapass/skxsp_tp_iio.h
A src/mainboard/ocp/tiogapass/tiogapass_boardid.h
A src/mainboard/ocp/tiogapass/vboot-ro.fmd
19 files changed, 2,053 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/38549/12

Change in coreboot[master]: mainboard/ocp: Add support for OCP platform TiogaPass

[Jonathan Zhang (Code Review)]

Hello HAOUAS Elyes, David Hendricks, build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38549

to look at the new patch set (#13).

Change subject: mainboard/ocp: Add support for OCP platform TiogaPass
......................................................................

mainboard/ocp: Add support for OCP platform TiogaPass

OCP platform Tiogapass is a 2-socket server platform, which
is based on a chipset including Intel Skylake-SP processors
and a Lewisburg PCH.

Following ACPI tables are added:
DSDT/SSDT, MADT, FACP, FACS, HPET, MCFG, SLIT, SRAT, DMAR

This patchset is tested on a Tiogapass board. It booted with
Linux kernel 4.16.0; lscpu command shows all 72 cpus (2 sockets,
18 cores, 2 thread per core); ssh command shows
networking is up from Mellanox ConnectX-4 PCIe NIC card.

Known issues (Not intend to address in this initial support for
Xeon-SP processors):
* c6 state is not supported.
* dsdt table is not fully populated, such as processor/socket
devices, some PCIe devices.
* SMM handlers are not added.
* MP init may not work reliably (I have not seen this happening
in the last several days). When it happens, coreboot fails with
an assert, indicating there is a MP boot init timeout.

Signed-off-by: Jonathan Zhang 
Signed-off-by: Reddy Chagam 
Change-Id: I29868f03037d1887b90dfb19d15aee83c456edce
---
A src/mainboard/ocp/Kconfig
A src/mainboard/ocp/Kconfig.name
A src/mainboard/ocp/tiogapass/Kconfig
A src/mainboard/ocp/tiogapass/Kconfig.name
A src/mainboard/ocp/tiogapass/Makefile.inc
A src/mainboard/ocp/tiogapass/acpi/platform.asl
A src/mainboard/ocp/tiogapass/acpi_tables.c
A src/mainboard/ocp/tiogapass/board_info.txt
A src/mainboard/ocp/tiogapass/boardid.c
A src/mainboard/ocp/tiogapass/devicetree.cb
A src/mainboard/ocp/tiogapass/dsdt.asl
A src/mainboard/ocp/tiogapass/emmc.h
A src/mainboard/ocp/tiogapass/fadt.c
A src/mainboard/ocp/tiogapass/ramstage.c
A src/mainboard/ocp/tiogapass/romstage.c
A src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h
A src/mainboard/ocp/tiogapass/skxsp_tp_iio.h
A src/mainboard/ocp/tiogapass/tiogapass_boardid.h
A src/mainboard/ocp/tiogapass/vboot-ro.fmd
19 files changed, 2,049 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/38549/13

Change in coreboot[master]: mainboard/ocp: Add support for OCP platform TiogaPass

[HAOUAS Elyes (Code Review)]

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38549 )

Change subject: mainboard/ocp: Add support for OCP platform TiogaPass
......................................................................

Patch Set 13:

(1 comment)

https://review.coreboot.org/c/coreboot/+/38549/13/src/mainboard/ocp/tiogapas... 
File src/mainboard/ocp/tiogapass/romstage.c:

https://review.coreboot.org/c/coreboot/+/38549/13/src/mainboard/ocp/tiogapas... 
PS13, Line 24: PCH_SERVER_BIOS_FLAG
is this used ?

Change in coreboot[master]: mainboard/ocp: Add support for OCP platform TiogaPass

[Jonathan Zhang (Code Review)]

Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38549 )

Change subject: mainboard/ocp: Add support for OCP platform TiogaPass
......................................................................

Patch Set 13:

(1 comment)

https://review.coreboot.org/c/coreboot/+/38549/13/src/mainboard/ocp/tiogapas... 
File src/mainboard/ocp/tiogapass/romstage.c:

https://review.coreboot.org/c/coreboot/+/38549/13/src/mainboard/ocp/tiogapas... 
PS13, Line 24: PCH_SERVER_BIOS_FLAG
> is this used ?

Yes, it is. Check src/soc/intel/skylake_sp/include/soc/gpio_soc_defs.h.

Change in coreboot[master]: mainboard/ocp: Add support for OCP platform TiogaPass

[Jonathan Zhang (Code Review)]

Hello HAOUAS Elyes, David Hendricks, build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38549

to look at the new patch set (#14).

Change subject: mainboard/ocp: Add support for OCP platform TiogaPass
......................................................................

mainboard/ocp: Add support for OCP platform TiogaPass

OCP platform Tiogapass is a 2-socket server platform, which
is based on a chipset including Intel Skylake-SP processors
and a Lewisburg PCH.

Following ACPI tables are added:
DSDT/SSDT, MADT, FACP, FACS, HPET, MCFG, SLIT, SRAT, DMAR

This patchset is tested on a Tiogapass board. It booted with
Linux kernel 4.16.0; lscpu command shows all 72 cpus (2 sockets,
18 cores, 2 thread per core); ssh command shows
networking is up from Mellanox ConnectX-4 PCIe NIC card.

Known issues (Not intend to address in this initial support for
Xeon-SP processors):
* c6 state is not supported.
* dsdt table is not fully populated, such as processor/socket
devices, some PCIe devices.
* SMM handlers are not added.
* MP init may not work reliably (I have not seen this happening
in the last several days with hundreds of manual reflash/reboots).
When it happens, coreboot fails with an assert, indicating there
is a MP boot init timeout.

Following are some command execution with CentOS booted from
local SATA disk:
[root@localhost ~]# lscpu
Architecture:          x86_64
CPU op-mode(s):        32-bit, 64-bit
Byte Order:            Little Endian
CPU(s):                72
On-line CPU(s) list:   0-71
Thread(s) per core:    2
Core(s) per socket:    18
Socket(s):             2
NUMA node(s):          2
Vendor ID:             GenuineIntel
CPU family:            6
Model:                 85
Model name:            Intel(R) Xeon(R) Gold 6139 CPU @ 2.30GHz
Stepping:              4
CPU MHz:               140.415
BogoMIPS:              4626.46
Virtualization:        VT-x
L1d cache:             32K
L1i cache:             32K
L2 cache:              1024K
L3 cache:              25344K
NUMA node0 CPU(s):     0-17,36-53
NUMA node1 CPU(s):     18-35,54-71
[root@localhost ~]# ifconfig
eth0: flags=4163<UP,BROADCAST,RUNNING,MULTICAST>  mtu 1500
        inet 172.23.68.190  netmask 255.255.0.0  broadcast 172.23.255.255
        inet6 2620:10d:c082:9063:268a:7ff:fe57:5af0  prefixlen 64  scopeid 0x0<global>
        inet6 fe80::268a:7ff:fe57:5af0  prefixlen 64  scopeid 0x20<link>
        inet6 2620:10d:c082:9063::5d2  prefixlen 128  scopeid 0x0<global>
        ether 24:8a:07:57:5a:f0  txqueuelen 1000  (Ethernet)
        RX packets 84249  bytes 6371591 (6.0 MiB)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 8418  bytes 748781 (731.2 KiB)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0

lo: flags=73<UP,LOOPBACK,RUNNING>  mtu 65536
        inet 127.0.0.1  netmask 255.0.0.0
        inet6 ::1  prefixlen 128  scopeid 0x10<host>
        loop  txqueuelen 1000  (Local Loopback)
        RX packets 613  bytes 63906 (62.4 KiB)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 613  bytes 63906 (62.4 KiB)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0

Signed-off-by: Jonathan Zhang 
Signed-off-by: Reddy Chagam 
Change-Id: I29868f03037d1887b90dfb19d15aee83c456edce
---
A src/mainboard/ocp/Kconfig
A src/mainboard/ocp/Kconfig.name
A src/mainboard/ocp/tiogapass/Kconfig
A src/mainboard/ocp/tiogapass/Kconfig.name
A src/mainboard/ocp/tiogapass/Makefile.inc
A src/mainboard/ocp/tiogapass/acpi/platform.asl
A src/mainboard/ocp/tiogapass/acpi_tables.c
A src/mainboard/ocp/tiogapass/board.fmd
A src/mainboard/ocp/tiogapass/board_info.txt
A src/mainboard/ocp/tiogapass/boardid.c
A src/mainboard/ocp/tiogapass/devicetree.cb
A src/mainboard/ocp/tiogapass/dsdt.asl
A src/mainboard/ocp/tiogapass/emmc.h
A src/mainboard/ocp/tiogapass/fadt.c
A src/mainboard/ocp/tiogapass/ramstage.c
A src/mainboard/ocp/tiogapass/romstage.c
A src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h
A src/mainboard/ocp/tiogapass/skxsp_tp_iio.h
A src/mainboard/ocp/tiogapass/tiogapass_boardid.h
19 files changed, 2,053 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/38549/14

Change in coreboot[master]: mainboard/ocp: Add support for OCP platform TiogaPass

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38549 )

Change subject: mainboard/ocp: Add support for OCP platform TiogaPass
......................................................................

Patch Set 14:

(7 comments)

https://review.coreboot.org/c/coreboot/+/38549/14/src/mainboard/ocp/tiogapas... 
File src/mainboard/ocp/tiogapass/Kconfig:

https://review.coreboot.org/c/coreboot/+/38549/14/src/mainboard/ocp/tiogapas... 
PS14, Line 34: OCP
Vendor shouldn't be needed here

https://review.coreboot.org/c/coreboot/+/38549/14/src/mainboard/ocp/tiogapas... 
PS14, Line 34: TiogaPass
Is it TiogaPass or Tioga Pass?

https://review.coreboot.org/c/coreboot/+/38549/14/src/mainboard/ocp/tiogapas... 
PS14, Line 39: 
             : config MAINBOARD_VENDOR
             : 	string
             : 	default "OCP"
Set to "Open Compute Project" in src/mb/ocp/Kconfig

https://review.coreboot.org/c/coreboot/+/38549/14/src/mainboard/ocp/tiogapas... 
File src/mainboard/ocp/tiogapass/Makefile.inc:

https://review.coreboot.org/c/coreboot/+/38549/14/src/mainboard/ocp/tiogapas... 
PS14, Line 25: CPPFLAGS_common += -I$(src)/soc/intel/skylake_sp/include
This should not be here

https://review.coreboot.org/c/coreboot/+/38549/14/src/mainboard/ocp/tiogapas... 
File src/mainboard/ocp/tiogapass/acpi_tables.c:

https://review.coreboot.org/c/coreboot/+/38549/14/src/mainboard/ocp/tiogapas... 
PS14, Line 27: 
             : 	/* Disable USB ports in S5 */
             : 	gnvs->s5u0 = 0;
             : 	gnvs->s5u1 = 0;
These can be dropped

https://review.coreboot.org/c/coreboot/+/38549/14/src/mainboard/ocp/tiogapas... 
PS14, Line 32: Present
Really?

https://review.coreboot.org/c/coreboot/+/38549/14/src/mainboard/ocp/tiogapas... 
File src/mainboard/ocp/tiogapass/devicetree.cb:

https://review.coreboot.org/c/coreboot/+/38549/14/src/mainboard/ocp/tiogapas... 
PS14, Line 62: 				device pci 04.0 on end # Intel Corporation Sky Lake-E CBDMA Registers
These comments can be shortened

Change in coreboot[master]: mainboard/ocp: Add support for OCP platform TiogaPass

[Jonathan Zhang (Code Review)]

Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38549 )

Change subject: mainboard/ocp: Add support for OCP platform TiogaPass
......................................................................

Patch Set 14:

(5 comments)

Thanks for the review. I have changes ready but not able to send right now. The current tip is broken for my compiler, the change identified is not committed yet.

https://review.coreboot.org/c/coreboot/+/38549/14/src/mainboard/ocp/tiogapas... 
File src/mainboard/ocp/tiogapass/Kconfig:

https://review.coreboot.org/c/coreboot/+/38549/14/src/mainboard/ocp/tiogapas... 
PS14, Line 34: OCP
> Vendor shouldn't be needed here

Why not?

https://review.coreboot.org/c/coreboot/+/38549/14/src/mainboard/ocp/tiogapas... 
PS14, Line 34: TiogaPass
> Is it TiogaPass or Tioga Pass?

Will use TiogaPass consistently.

https://review.coreboot.org/c/coreboot/+/38549/14/src/mainboard/ocp/tiogapas... 
PS14, Line 39: 
             : config MAINBOARD_VENDOR
             : 	string
             : 	default "OCP"
> Set to "Open Compute Project" in src/mb/ocp/Kconfig

Done

https://review.coreboot.org/c/coreboot/+/38549/14/src/mainboard/ocp/tiogapas... 
File src/mainboard/ocp/tiogapass/Makefile.inc:

https://review.coreboot.org/c/coreboot/+/38549/14/src/mainboard/ocp/tiogapas... 
PS14, Line 25: CPPFLAGS_common += -I$(src)/soc/intel/skylake_sp/include
> This should not be here

Done

https://review.coreboot.org/c/coreboot/+/38549/14/src/mainboard/ocp/tiogapas... 
File src/mainboard/ocp/tiogapass/devicetree.cb:

https://review.coreboot.org/c/coreboot/+/38549/14/src/mainboard/ocp/tiogapas... 
PS14, Line 62: 				device pci 04.0 on end # Intel Corporation Sky Lake-E CBDMA Registers
> These comments can be shortened

Done

Change in coreboot[master]: mainboard/ocp: Add support for OCP platform TiogaPass

[Jonathan Zhang (Code Review)]

Hello HAOUAS Elyes, David Hendricks, build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38549

to look at the new patch set (#15).

Change subject: mainboard/ocp: Add support for OCP platform TiogaPass
......................................................................

mainboard/ocp: Add support for OCP platform TiogaPass

OCP platform Tiogapass is a 2-socket server platform, which
is based on a chipset including Intel Skylake-SP processors
and a Lewisburg PCH.

Following ACPI tables are added:
DSDT/SSDT, MADT, FACP, FACS, HPET, MCFG, SLIT, SRAT, DMAR

This patchset is tested on a Tiogapass board. It booted with
Linux kernel 4.16.0; lscpu command shows all 72 cpus (2 sockets,
18 cores, 2 thread per core); ssh command shows
networking is up from Mellanox ConnectX-4 PCIe NIC card.

Toward successful gerrit buildbot build, note:
* microcode is in coreboot intel-microcode submodule repo.
* We are trying to get IFD/ME binaries into coreboot blobs
submodule repo.
* We are trying to get FSP header files into coreboot fsp
submodule repo.
* For FSP binary, we need to update coreboot make system so
that an image could be built without FSP binary. Such image
will not be functional, but at least all coreboot binaries
can be be proved to build without problem.

Known issues (Not intend to address in this initial support for
Xeon-SP processors):
* c6 state is not supported.
* dsdt table is not fully populated, such as processor/socket
devices, some PCIe devices.
* SMM handlers are not added.

Following are some command execution with CentOS booted from
local SATA disk:
[root@localhost ~]# lscpu
Architecture:          x86_64
CPU op-mode(s):        32-bit, 64-bit
Byte Order:            Little Endian
CPU(s):                72
On-line CPU(s) list:   0-71
Thread(s) per core:    2
Core(s) per socket:    18
Socket(s):             2
NUMA node(s):          2
Vendor ID:             GenuineIntel
CPU family:            6
Model:                 85
Model name:            Intel(R) Xeon(R) Gold 6139 CPU @ 2.30GHz
Stepping:              4
CPU MHz:               140.415
BogoMIPS:              4626.46
Virtualization:        VT-x
L1d cache:             32K
L1i cache:             32K
L2 cache:              1024K
L3 cache:              25344K
NUMA node0 CPU(s):     0-17,36-53
NUMA node1 CPU(s):     18-35,54-71
[root@localhost ~]# ifconfig
eth0: flags=4163<UP,BROADCAST,RUNNING,MULTICAST>  mtu 1500
        inet 172.23.68.190  netmask 255.255.0.0  broadcast 172.23.255.255
        inet6 2620:10d:c082:9063:268a:7ff:fe57:5af0  prefixlen 64 //cut
        inet6 fe80::268a:7ff:fe57:5af0  prefixlen 64  scopeid 0x20<link>
        inet6 2620:10d:c082:9063::5d2  prefixlen 128  scopeid 0x0<global>
        ether 24:8a:07:57:5a:f0  txqueuelen 1000  (Ethernet)
        RX packets 84249  bytes 6371591 (6.0 MiB)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 8418  bytes 748781 (731.2 KiB)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0

lo: flags=73<UP,LOOPBACK,RUNNING>  mtu 65536
        inet 127.0.0.1  netmask 255.0.0.0
        inet6 ::1  prefixlen 128  scopeid 0x10<host>
        loop  txqueuelen 1000  (Local Loopback)
        RX packets 613  bytes 63906 (62.4 KiB)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 613  bytes 63906 (62.4 KiB)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0
[root@localhost ~]# cbmem
36 entries total:

// Lines were cut to avoid checkpatch.pl warnings

Total Time: 96,243,882,140,175,829

Signed-off-by: Jonathan Zhang 
Signed-off-by: Reddy Chagam 
Change-Id: I29868f03037d1887b90dfb19d15aee83c456edce
---
A configs/config.ocp_tiogapass
A src/mainboard/ocp/Kconfig
A src/mainboard/ocp/Kconfig.name
A src/mainboard/ocp/tiogapass/Kconfig
A src/mainboard/ocp/tiogapass/Kconfig.name
A src/mainboard/ocp/tiogapass/Makefile.inc
A src/mainboard/ocp/tiogapass/acpi/platform.asl
A src/mainboard/ocp/tiogapass/acpi_tables.c
A src/mainboard/ocp/tiogapass/board.fmd
A src/mainboard/ocp/tiogapass/board_info.txt
A src/mainboard/ocp/tiogapass/boardid.c
A src/mainboard/ocp/tiogapass/devicetree.cb
A src/mainboard/ocp/tiogapass/dsdt.asl
A src/mainboard/ocp/tiogapass/emmc.h
A src/mainboard/ocp/tiogapass/fadt.c
A src/mainboard/ocp/tiogapass/ramstage.c
A src/mainboard/ocp/tiogapass/romstage.c
A src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h
A src/mainboard/ocp/tiogapass/skxsp_tp_iio.h
A src/mainboard/ocp/tiogapass/tiogapass_boardid.h
20 files changed, 2,055 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/38549/15

Change in coreboot[master]: mainboard/ocp: Add support for OCP platform TiogaPass

[Jonathan Zhang (Code Review)]

Hello HAOUAS Elyes, David Hendricks, build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38549

to look at the new patch set (#16).

Change subject: mainboard/ocp: Add support for OCP platform TiogaPass
......................................................................

mainboard/ocp: Add support for OCP platform TiogaPass

OCP platform Tiogapass is a 2-socket server platform, which
is based on a chipset including Intel Skylake-SP processors
and a Lewisburg PCH.

Following ACPI tables are added:
DSDT/SSDT, MADT, FACP, FACS, HPET, MCFG, SLIT, SRAT, DMAR

This patchset is tested on a Tiogapass board. It booted with
Linux kernel 4.16.0; lscpu command shows all 72 cpus (2 sockets,
18 cores, 2 thread per core); ssh command shows
networking is up from Mellanox ConnectX-4 PCIe NIC card.

Toward successful gerrit buildbot build, note:
* microcode is in coreboot intel-microcode submodule repo.
* We are trying to get IFD/ME binaries into coreboot blobs
submodule repo.
* We are trying to get FSP header files into coreboot fsp
submodule repo.
* For FSP binary, we need to update coreboot make system so
that an image could be built without FSP binary. Such image
will not be functional, but at least all coreboot binaries
can be be proved to build without problem.

Known issues (Not intend to address in this initial support for
Xeon-SP processors):
* c6 state is not supported.
* dsdt table is not fully populated, such as processor/socket
devices, some PCIe devices.
* SMM handlers are not added.

Following are some command execution with CentOS booted from
local SATA disk:
[root@localhost ~]# lscpu
Architecture:          x86_64
CPU op-mode(s):        32-bit, 64-bit
Byte Order:            Little Endian
CPU(s):                72
On-line CPU(s) list:   0-71
Thread(s) per core:    2
Core(s) per socket:    18
Socket(s):             2
NUMA node(s):          2
Vendor ID:             GenuineIntel
CPU family:            6
Model:                 85
Model name:            Intel(R) Xeon(R) Gold 6139 CPU @ 2.30GHz
Stepping:              4
CPU MHz:               140.415
BogoMIPS:              4626.46
Virtualization:        VT-x
L1d cache:             32K
L1i cache:             32K
L2 cache:              1024K
L3 cache:              25344K
NUMA node0 CPU(s):     0-17,36-53
NUMA node1 CPU(s):     18-35,54-71
[root@localhost ~]# ifconfig
eth0: flags=4163<UP,BROADCAST,RUNNING,MULTICAST>  mtu 1500
        inet 172.23.68.190  netmask 255.255.0.0  broadcast 172.23.255.255
        inet6 2620:10d:c082:9063:268a:7ff:fe57:5af0  prefixlen 64 //cut
        inet6 fe80::268a:7ff:fe57:5af0  prefixlen 64  scopeid 0x20<link>
        inet6 2620:10d:c082:9063::5d2  prefixlen 128  scopeid 0x0<global>
        ether 24:8a:07:57:5a:f0  txqueuelen 1000  (Ethernet)
        RX packets 84249  bytes 6371591 (6.0 MiB)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 8418  bytes 748781 (731.2 KiB)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0

lo: flags=73<UP,LOOPBACK,RUNNING>  mtu 65536
        inet 127.0.0.1  netmask 255.0.0.0
        inet6 ::1  prefixlen 128  scopeid 0x10<host>
        loop  txqueuelen 1000  (Local Loopback)
        RX packets 613  bytes 63906 (62.4 KiB)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 613  bytes 63906 (62.4 KiB)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0
[root@localhost ~]# cbmem
36 entries total:

// Lines were cut to avoid checkpatch.pl warnings

Total Time: 96,243,882,140,175,829

Signed-off-by: Jonathan Zhang 
Signed-off-by: Reddy Chagam 
Change-Id: I29868f03037d1887b90dfb19d15aee83c456edce
---
A configs/config.ocp_tiogapass
A src/mainboard/ocp/Kconfig
A src/mainboard/ocp/Kconfig.name
A src/mainboard/ocp/tiogapass/Kconfig
A src/mainboard/ocp/tiogapass/Kconfig.name
A src/mainboard/ocp/tiogapass/Makefile.inc
A src/mainboard/ocp/tiogapass/acpi/platform.asl
A src/mainboard/ocp/tiogapass/acpi_tables.c
A src/mainboard/ocp/tiogapass/board.fmd
A src/mainboard/ocp/tiogapass/board_info.txt
A src/mainboard/ocp/tiogapass/boardid.c
A src/mainboard/ocp/tiogapass/devicetree.cb
A src/mainboard/ocp/tiogapass/dsdt.asl
A src/mainboard/ocp/tiogapass/emmc.h
A src/mainboard/ocp/tiogapass/fadt.c
A src/mainboard/ocp/tiogapass/ramstage.c
A src/mainboard/ocp/tiogapass/romstage.c
A src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h
A src/mainboard/ocp/tiogapass/skxsp_tp_iio.h
A src/mainboard/ocp/tiogapass/tiogapass_boardid.h
20 files changed, 2,052 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/38549/16

Change in coreboot[master]: mainboard/ocp: Add support for OCP platform TiogaPass

[Jonathan Zhang (Code Review)]

Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38549 )

Change subject: mainboard/ocp: Add support for OCP platform TiogaPass
......................................................................

Patch Set 16:

(3 comments)

https://review.coreboot.org/c/coreboot/+/38549/4//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/38549/4//COMMIT_MSG@22 
PS4, Line 22: eg. some reboots does not boot up successfully.
> More details? At what point does it stop in coreboot?

Done

https://review.coreboot.org/c/coreboot/+/38549/14/src/mainboard/ocp/tiogapas... 
File src/mainboard/ocp/tiogapass/acpi_tables.c:

https://review.coreboot.org/c/coreboot/+/38549/14/src/mainboard/ocp/tiogapas... 
PS14, Line 27: 
             : 	/* Disable USB ports in S5 */
             : 	gnvs->s5u0 = 0;
             : 	gnvs->s5u1 = 0;
> These can be dropped

Done

https://review.coreboot.org/c/coreboot/+/38549/14/src/mainboard/ocp/tiogapas... 
PS14, Line 32: Present
> Really?

Done

Change in coreboot[master]: mainboard/ocp: Add support for OCP platform TiogaPass

[Jonathan Zhang (Code Review)]

Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38549 )

Change subject: mainboard/ocp: Add support for OCP platform TiogaPass
......................................................................

Patch Set 16:

(1 comment)

https://review.coreboot.org/c/coreboot/+/38549/4//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/38549/4//COMMIT_MSG@24 
PS4, Line 24: 3. "lspci -vvv" causes segmentation fault.
> Actually after I flashed in traditional UEFI firmware, the same problem happens. […]

Done

Change in coreboot[master]: mainboard/ocp: Add support for OCP platform TiogaPass

[Jonathan Zhang (Code Review)]

Hello HAOUAS Elyes, David Hendricks, build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38549

to look at the new patch set (#18).

Change subject: mainboard/ocp: Add support for OCP platform TiogaPass
......................................................................

mainboard/ocp: Add support for OCP platform TiogaPass

OCP platform Tiogapass is a 2-socket server platform, which
is based on a chipset including Intel Skylake-SP processors
and a Lewisburg PCH.

Following ACPI tables are added:
DSDT/SSDT, MADT, FACP, FACS, HPET, MCFG, SLIT, SRAT, DMAR

This patchset is tested on a Tiogapass board. It booted with
Linux kernel 4.16.0; lscpu command shows all 72 cpus (2 sockets,
18 cores, 2 thread per core); ssh command shows
networking is up from Mellanox ConnectX-4 PCIe NIC card.

Toward successful gerrit buildbot build, note:
* microcode is in coreboot intel-microcode submodule repo.
* We are trying to get IFD/ME binaries into coreboot blobs
submodule repo.
* We are trying to get FSP header files into coreboot fsp
submodule repo.
* For FSP binary, we need to update coreboot make system so
that an image could be built without FSP binary. Such image
will not be functional, but at least all coreboot binaries
can be be proved to build without problem.

Known issues (Not intend to address in this initial support for
Xeon-SP processors):
* c6 state is not supported.
* dsdt table is not fully populated, such as processor/socket
devices, some PCIe devices.
* SMM handlers are not added.

Following are some command execution with CentOS booted from
local SATA disk:
[root@localhost ~]# lscpu
Architecture:          x86_64
CPU op-mode(s):        32-bit, 64-bit
Byte Order:            Little Endian
CPU(s):                72
On-line CPU(s) list:   0-71
Thread(s) per core:    2
Core(s) per socket:    18
Socket(s):             2
NUMA node(s):          2
Vendor ID:             GenuineIntel
CPU family:            6
Model:                 85
Model name:            Intel(R) Xeon(R) Gold 6139 CPU @ 2.30GHz
Stepping:              4
CPU MHz:               140.415
BogoMIPS:              4626.46
Virtualization:        VT-x
L1d cache:             32K
L1i cache:             32K
L2 cache:              1024K
L3 cache:              25344K
NUMA node0 CPU(s):     0-17,36-53
NUMA node1 CPU(s):     18-35,54-71
[root@localhost ~]# ifconfig
eth0: flags=4163<UP,BROADCAST,RUNNING,MULTICAST>  mtu 1500
        inet 172.23.68.190  netmask 255.255.0.0  broadcast 172.23.255.255
        inet6 2620:10d:c082:9063:268a:7ff:fe57:5af0  prefixlen 64 //cut
        inet6 fe80::268a:7ff:fe57:5af0  prefixlen 64  scopeid 0x20<link>
        inet6 2620:10d:c082:9063::5d2  prefixlen 128  scopeid 0x0<global>
        ether 24:8a:07:57:5a:f0  txqueuelen 1000  (Ethernet)
        RX packets 84249  bytes 6371591 (6.0 MiB)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 8418  bytes 748781 (731.2 KiB)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0

lo: flags=73<UP,LOOPBACK,RUNNING>  mtu 65536
        inet 127.0.0.1  netmask 255.0.0.0
        inet6 ::1  prefixlen 128  scopeid 0x10<host>
        loop  txqueuelen 1000  (Local Loopback)
        RX packets 613  bytes 63906 (62.4 KiB)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 613  bytes 63906 (62.4 KiB)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0
[root@localhost ~]# cbmem
36 entries total:

// Lines were cut to avoid checkpatch.pl warnings

Total Time: 96,243,882,140,175,829

Signed-off-by: Jonathan Zhang 
Signed-off-by: Reddy Chagam 
Tested-by: [e-mail]
Change-Id: I29868f03037d1887b90dfb19d15aee83c456edce
---
A configs/config.ocp_tiogapass
A src/mainboard/ocp/Kconfig
A src/mainboard/ocp/Kconfig.name
A src/mainboard/ocp/tiogapass/Kconfig
A src/mainboard/ocp/tiogapass/Kconfig.name
A src/mainboard/ocp/tiogapass/Makefile.inc
A src/mainboard/ocp/tiogapass/acpi/platform.asl
A src/mainboard/ocp/tiogapass/acpi_tables.c
A src/mainboard/ocp/tiogapass/board.fmd
A src/mainboard/ocp/tiogapass/board_info.txt
A src/mainboard/ocp/tiogapass/boardid.c
A src/mainboard/ocp/tiogapass/devicetree.cb
A src/mainboard/ocp/tiogapass/dsdt.asl
A src/mainboard/ocp/tiogapass/emmc.h
A src/mainboard/ocp/tiogapass/fadt.c
A src/mainboard/ocp/tiogapass/ramstage.c
A src/mainboard/ocp/tiogapass/romstage.c
A src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h
A src/mainboard/ocp/tiogapass/skxsp_tp_iio.h
A src/mainboard/ocp/tiogapass/tiogapass_boardid.h
20 files changed, 2,052 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/38549/18

Change in coreboot[master]: mainboard/ocp: Add support for OCP platform TiogaPass

[Jonathan Zhang (Code Review)]

Hello HAOUAS Elyes, David Hendricks, build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38549

to look at the new patch set (#19).

Change subject: mainboard/ocp: Add support for OCP platform TiogaPass
......................................................................

mainboard/ocp: Add support for OCP platform TiogaPass

OCP platform Tiogapass is a 2-socket server platform, which
is based on a chipset including Intel Skylake-SP processors
and a Lewisburg PCH.

Following ACPI tables are added:
DSDT/SSDT, MADT, FACP, FACS, HPET, MCFG, SLIT, SRAT, DMAR

This patchset is tested on a Tiogapass board. It booted with
Linux kernel 4.16.0; lscpu command shows all 72 cpus (2 sockets,
18 cores, 2 thread per core); ssh command shows
networking is up from Mellanox ConnectX-4 PCIe NIC card.

Toward successful gerrit buildbot build, note that:
* microcode is in coreboot intel-microcode submodule repo.
* IFD binary is included in this patch.
* Dummy ME binary is used, as it may take long time for Intel
ME binary to be available in public domain.
* Dummy FSP binary is used, as at this moment the SKX-SP
FSP binary is not going to be available in public domain.

Known issues (Not intend to address in this initial support for
Xeon-SP processors):
* c6 state is not supported.
* dsdt table is not fully populated, such as processor/socket
devices, some PCIe devices.
* SMM handlers are not added.

Following are some command execution with CentOS booted from
local SATA disk:
[root@localhost ~]# lscpu
Architecture:          x86_64
CPU op-mode(s):        32-bit, 64-bit
Byte Order:            Little Endian
CPU(s):                72
On-line CPU(s) list:   0-71
Thread(s) per core:    2
Core(s) per socket:    18
Socket(s):             2
NUMA node(s):          2
Vendor ID:             GenuineIntel
CPU family:            6
Model:                 85
Model name:            Intel(R) Xeon(R) Gold 6139 CPU @ 2.30GHz
Stepping:              4
CPU MHz:               140.415
BogoMIPS:              4626.46
Virtualization:        VT-x
L1d cache:             32K
L1i cache:             32K
L2 cache:              1024K
L3 cache:              25344K
NUMA node0 CPU(s):     0-17,36-53
NUMA node1 CPU(s):     18-35,54-71
[root@localhost ~]# ifconfig
eth0: flags=4163<UP,BROADCAST,RUNNING,MULTICAST>  mtu 1500
        inet 172.23.68.190  netmask 255.255.0.0  broadcast 172.23.255.255
        inet6 2620:10d:c082:9063:268a:7ff:fe57:5af0  prefixlen 64 //cut
        inet6 fe80::268a:7ff:fe57:5af0  prefixlen 64  scopeid 0x20<link>
        inet6 2620:10d:c082:9063::5d2  prefixlen 128  scopeid 0x0<global>
        ether 24:8a:07:57:5a:f0  txqueuelen 1000  (Ethernet)
        RX packets 84249  bytes 6371591 (6.0 MiB)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 8418  bytes 748781 (731.2 KiB)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0

lo: flags=73<UP,LOOPBACK,RUNNING>  mtu 65536
        inet 127.0.0.1  netmask 255.0.0.0
        inet6 ::1  prefixlen 128  scopeid 0x10<host>
        loop  txqueuelen 1000  (Local Loopback)
        RX packets 613  bytes 63906 (62.4 KiB)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 613  bytes 63906 (62.4 KiB)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0
[root@localhost ~]# cbmem
36 entries total:

// Lines were cut to avoid checkpatch.pl warnings

Total Time: 96,243,882,140,175,829

Signed-off-by: Jonathan Zhang 
Signed-off-by: Reddy Chagam 
Tested-by: [e-mail]
Change-Id: I29868f03037d1887b90dfb19d15aee83c456edce
---
A configs/config.ocp_tiogapass
A src/mainboard/ocp/Kconfig
A src/mainboard/ocp/Kconfig.name
A src/mainboard/ocp/tiogapass/Kconfig
A src/mainboard/ocp/tiogapass/Kconfig.name
A src/mainboard/ocp/tiogapass/Makefile.inc
A src/mainboard/ocp/tiogapass/acpi/platform.asl
A src/mainboard/ocp/tiogapass/acpi_tables.c
A src/mainboard/ocp/tiogapass/blobs/Fsp_dummy.fd
A src/mainboard/ocp/tiogapass/blobs/ifd.bin
A src/mainboard/ocp/tiogapass/blobs/me_dummy.bin
A src/mainboard/ocp/tiogapass/board.fmd
A src/mainboard/ocp/tiogapass/board_info.txt
A src/mainboard/ocp/tiogapass/boardid.c
A src/mainboard/ocp/tiogapass/devicetree.cb
A src/mainboard/ocp/tiogapass/dsdt.asl
A src/mainboard/ocp/tiogapass/emmc.h
A src/mainboard/ocp/tiogapass/fadt.c
A src/mainboard/ocp/tiogapass/ramstage.c
A src/mainboard/ocp/tiogapass/romstage.c
A src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h
A src/mainboard/ocp/tiogapass/skxsp_tp_iio.h
A src/mainboard/ocp/tiogapass/tiogapass_boardid.h
23 files changed, 2,055 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/38549/19

Change in coreboot[master]: mainboard/ocp: Add support for OCP platform TiogaPass

[Jonathan Zhang (Code Review)]

Hello HAOUAS Elyes, David Hendricks, build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38549

to look at the new patch set (#22).

Change subject: mainboard/ocp: Add support for OCP platform TiogaPass
......................................................................

mainboard/ocp: Add support for OCP platform TiogaPass

OCP platform Tiogapass is a 2-socket server platform, which
is based on a chipset including Intel Skylake-SP processors
and a Lewisburg PCH.

Following ACPI tables are added:
DSDT/SSDT, MADT, FACP, FACS, HPET, MCFG, SLIT, SRAT, DMAR

This patchset is tested on a Tiogapass board. It booted with
Linux kernel 4.16.0; lscpu command shows all 72 cpus (2 sockets,
18 cores, 2 thread per core); ssh command shows
networking is up from Mellanox ConnectX-4 PCIe NIC card.

Towards successful gerrit buildbot build, note that:
* microcode is in coreboot intel-microcode submodule repo.
* IFD binary is included in this patch.
* Dummy ME binary is used, as it may take long time for Intel
ME binary to be available in public domain.
* Dummy FSP binary is used, as at this moment the SKX-SP
FSP binary is not going to be available in public domain.

Known issues (Not intend to address in this initial support for
Xeon-SP processors):
* c6 state is not supported.
* dsdt table is not fully populated, such as processor/socket
devices, some PCIe devices.
* SMM handlers are not added.

Following are some command execution with CentOS booted from
local SATA disk:
[root@localhost ~]# lscpu
Architecture:          x86_64
CPU op-mode(s):        32-bit, 64-bit
Byte Order:            Little Endian
CPU(s):                72
On-line CPU(s) list:   0-71
Thread(s) per core:    2
Core(s) per socket:    18
Socket(s):             2
NUMA node(s):          2
Vendor ID:             GenuineIntel
CPU family:            6
Model:                 85
Model name:            Intel(R) Xeon(R) Gold 6139 CPU @ 2.30GHz
Stepping:              4
CPU MHz:               140.415
BogoMIPS:              4626.46
Virtualization:        VT-x
L1d cache:             32K
L1i cache:             32K
L2 cache:              1024K
L3 cache:              25344K
NUMA node0 CPU(s):     0-17,36-53
NUMA node1 CPU(s):     18-35,54-71
[root@localhost ~]# ifconfig
eth0: flags=4163<UP,BROADCAST,RUNNING,MULTICAST>  mtu 1500
        inet 172.23.68.190  netmask 255.255.0.0  broadcast 172.23.255.255
        inet6 2620:10d:c082:9063:268a:7ff:fe57:5af0  prefixlen 64 //cut
        inet6 fe80::268a:7ff:fe57:5af0  prefixlen 64  scopeid 0x20<link>
        inet6 2620:10d:c082:9063::5d2  prefixlen 128  scopeid 0x0<global>
        ether 24:8a:07:57:5a:f0  txqueuelen 1000  (Ethernet)
        RX packets 84249  bytes 6371591 (6.0 MiB)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 8418  bytes 748781 (731.2 KiB)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0

lo: flags=73<UP,LOOPBACK,RUNNING>  mtu 65536
        inet 127.0.0.1  netmask 255.0.0.0
        inet6 ::1  prefixlen 128  scopeid 0x10<host>
        loop  txqueuelen 1000  (Local Loopback)
        RX packets 613  bytes 63906 (62.4 KiB)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 613  bytes 63906 (62.4 KiB)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0
[root@localhost ~]# cbmem
36 entries total:

// Lines were cut to avoid checkpatch.pl warnings

Total Time: 96,243,882,140,175,829

Signed-off-by: Jonathan Zhang 
Signed-off-by: Reddy Chagam 
Tested-by: [e-mail]
Change-Id: I29868f03037d1887b90dfb19d15aee83c456edce
---
A configs/config.ocp_tiogapass
A src/mainboard/ocp/Kconfig
A src/mainboard/ocp/Kconfig.name
A src/mainboard/ocp/tiogapass/Kconfig
A src/mainboard/ocp/tiogapass/Kconfig.name
A src/mainboard/ocp/tiogapass/Makefile.inc
A src/mainboard/ocp/tiogapass/acpi/platform.asl
A src/mainboard/ocp/tiogapass/acpi_tables.c
A src/mainboard/ocp/tiogapass/blobs/Fsp_dummy.fd
A src/mainboard/ocp/tiogapass/blobs/ifd.bin
A src/mainboard/ocp/tiogapass/blobs/me_dummy.bin
A src/mainboard/ocp/tiogapass/board.fmd
A src/mainboard/ocp/tiogapass/board_info.txt
A src/mainboard/ocp/tiogapass/boardid.c
A src/mainboard/ocp/tiogapass/devicetree.cb
A src/mainboard/ocp/tiogapass/dsdt.asl
A src/mainboard/ocp/tiogapass/emmc.h
A src/mainboard/ocp/tiogapass/fadt.c
A src/mainboard/ocp/tiogapass/ramstage.c
A src/mainboard/ocp/tiogapass/romstage.c
A src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h
A src/mainboard/ocp/tiogapass/skxsp_tp_iio.h
A src/mainboard/ocp/tiogapass/tiogapass_boardid.h
23 files changed, 2,055 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/38549/22

Change in coreboot[master]: mainboard/ocp: Add support for OCP platform TiogaPass

[Jonathan Zhang (Code Review)]

Hello HAOUAS Elyes, David Hendricks, build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38549

to look at the new patch set (#23).

Change subject: mainboard/ocp: Add support for OCP platform TiogaPass
......................................................................

mainboard/ocp: Add support for OCP platform TiogaPass

OCP platform Tiogapass is a 2-socket server platform, which
is based on a chipset including Intel Skylake-SP processors
and a Lewisburg PCH.

Following ACPI tables are added:
DSDT/SSDT, MADT, FACP, FACS, HPET, MCFG, SLIT, SRAT, DMAR

This patchset is tested on a Tiogapass board. It booted with
Linux kernel 4.16.0; lscpu command shows all 72 cpus (2 sockets,
18 cores, 2 thread per core); ssh command shows
networking is up from Mellanox ConnectX-4 PCIe NIC card.

Towards successful gerrit buildbot build, note that:
* microcode is in coreboot intel-microcode submodule repo.
* IFD binary is included in this patch.
* Dummy ME binary is used, as it may take long time for Intel
ME binary to be available in public domain.
* Fake FSP binary is used, as at this moment the SKX-SP
FSP binary is not going to be available in public domain.

Known issues (Not intend to address in this initial support for
Xeon-SP processors):
* c6 state is not supported.
* dsdt table is not fully populated, such as processor/socket
devices, some PCIe devices.
* SMM handlers are not added.

Following are some command execution with CentOS booted from
local SATA disk:
[root@localhost ~]# lscpu
Architecture:          x86_64
CPU op-mode(s):        32-bit, 64-bit
Byte Order:            Little Endian
CPU(s):                72
On-line CPU(s) list:   0-71
Thread(s) per core:    2
Core(s) per socket:    18
Socket(s):             2
NUMA node(s):          2
Vendor ID:             GenuineIntel
CPU family:            6
Model:                 85
Model name:            Intel(R) Xeon(R) Gold 6139 CPU @ 2.30GHz
Stepping:              4
CPU MHz:               140.415
BogoMIPS:              4626.46
Virtualization:        VT-x
L1d cache:             32K
L1i cache:             32K
L2 cache:              1024K
L3 cache:              25344K
NUMA node0 CPU(s):     0-17,36-53
NUMA node1 CPU(s):     18-35,54-71
[root@localhost ~]# ifconfig
eth0: flags=4163<UP,BROADCAST,RUNNING,MULTICAST>  mtu 1500
        inet 172.23.68.190  netmask 255.255.0.0  broadcast 172.23.255.255
        inet6 2620:10d:c082:9063:268a:7ff:fe57:5af0  prefixlen 64 //cut
        inet6 fe80::268a:7ff:fe57:5af0  prefixlen 64  scopeid 0x20<link>
        inet6 2620:10d:c082:9063::5d2  prefixlen 128  scopeid 0x0<global>
        ether 24:8a:07:57:5a:f0  txqueuelen 1000  (Ethernet)
        RX packets 84249  bytes 6371591 (6.0 MiB)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 8418  bytes 748781 (731.2 KiB)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0

lo: flags=73<UP,LOOPBACK,RUNNING>  mtu 65536
        inet 127.0.0.1  netmask 255.0.0.0
        inet6 ::1  prefixlen 128  scopeid 0x10<host>
        loop  txqueuelen 1000  (Local Loopback)
        RX packets 613  bytes 63906 (62.4 KiB)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 613  bytes 63906 (62.4 KiB)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0
[root@localhost ~]# cbmem
36 entries total:

// Lines were cut to avoid checkpatch.pl warnings

Total Time: 96,243,882,140,175,829

Signed-off-by: Jonathan Zhang 
Signed-off-by: Reddy Chagam 
Tested-by: [e-mail]
Change-Id: I29868f03037d1887b90dfb19d15aee83c456edce
---
A configs/config.ocp_tiogapass
A src/mainboard/ocp/Kconfig
A src/mainboard/ocp/Kconfig.name
A src/mainboard/ocp/tiogapass/Kconfig
A src/mainboard/ocp/tiogapass/Kconfig.name
A src/mainboard/ocp/tiogapass/Makefile.inc
A src/mainboard/ocp/tiogapass/acpi/platform.asl
A src/mainboard/ocp/tiogapass/acpi_tables.c
A src/mainboard/ocp/tiogapass/blobs/ifd.bin
A src/mainboard/ocp/tiogapass/blobs/me_dummy.bin
A src/mainboard/ocp/tiogapass/board.fmd
A src/mainboard/ocp/tiogapass/board_info.txt
A src/mainboard/ocp/tiogapass/boardid.c
A src/mainboard/ocp/tiogapass/devicetree.cb
A src/mainboard/ocp/tiogapass/dsdt.asl
A src/mainboard/ocp/tiogapass/emmc.h
A src/mainboard/ocp/tiogapass/fadt.c
A src/mainboard/ocp/tiogapass/ramstage.c
A src/mainboard/ocp/tiogapass/romstage.c
A src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h
A src/mainboard/ocp/tiogapass/skxsp_tp_iio.h
A src/mainboard/ocp/tiogapass/tiogapass_boardid.h
22 files changed, 2,055 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/38549/23

Change in coreboot[master]: mainboard/ocp: Add support for OCP platform TiogaPass

[Jonathan Zhang (Code Review)]

Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38549 )

Change subject: mainboard/ocp: Add support for OCP platform TiogaPass
......................................................................

Patch Set 24:

(1 comment)

Thanks for the review. All the comments so far are addressed.

We plan to work on this code base (support for Xeon-SP processors and their OCP platforms) in 3 phases:
Phase 1: initial code base. It supports the previous generation of Xeon-SP processor (Skylake-SP), and one OCP platform (TiogaPass). This patch set is verified to boot to target OS on several TiogaPass servers with slightly different configurations (such as CPU core count, PCIe config, socket count, etc.). Pending item of this phase is to merge this patch set into coreboot upstream.
Phase 2. Support for current Xeon-SP processors. We are working on bring-up of current generation of Xeon-SP processor (Note that SKX-SP was in Mass Production as of 2018). The code base will be refactored/improved, it will support both Xeon-SP processors and multiple OCP platform (Most of the OCP platform are yet to be announced). This is the multi-company teams' focus right now.
Phase 3. Nicer integration with coreboot common code. Through lessons learned from Xeon-SP code base, we will see what we could do to improve coreboot common code, if any.

Let us know if you have any further comments, we will address them as soon as we can.

Best,
Jonathan

https://review.coreboot.org/c/coreboot/+/38549/14/src/mainboard/ocp/tiogapas... 
File src/mainboard/ocp/tiogapass/Kconfig:

https://review.coreboot.org/c/coreboot/+/38549/14/src/mainboard/ocp/tiogapas... 
PS14, Line 34: OCP
> Why not?

Done

Change in coreboot[master]: mainboard/ocp: Add support for OCP platform TiogaPass

[Andrey Petrov (Code Review)]

Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38549 )

Change subject: mainboard/ocp: Add support for OCP platform TiogaPass
......................................................................

Patch Set 24:

(3 comments)

nice. One major issue I have is that we can't set up GPIOs at will and have to rely on FSP.

https://review.coreboot.org/c/coreboot/+/38549/24/src/mainboard/ocp/tiogapas... 
File src/mainboard/ocp/tiogapass/board.fmd:

https://review.coreboot.org/c/coreboot/+/38549/24/src/mainboard/ocp/tiogapas... 
PS24, Line 8: MISC_RW
we do not have RO here, everything is RW. Lets collapse these two sections and get rid of unused sections

https://review.coreboot.org/c/coreboot/+/38549/24/src/mainboard/ocp/tiogapas... 
File src/mainboard/ocp/tiogapass/romstage.c:

https://review.coreboot.org/c/coreboot/+/38549/24/src/mainboard/ocp/tiogapas... 
PS24, Line 24: #define PCH_SERVER_BIOS_FLAG 1
again I do not think it make sense to have this flag

https://review.coreboot.org/c/coreboot/+/38549/24/src/mainboard/ocp/tiogapas... 
PS24, Line 37: 	mupd->FspmConfig.GpioConfig.GpioTable = (UPD_GPIO_INIT_CONFIG *) tp_gpio_table;
             : 	mupd->FspmConfig.GpioConfig.NumberOfEntries =
             : 		sizeof(tp_gpio_table)/sizeof(UPD_GPIO_INIT_CONFIG);
So on this board we have C62x PCH. What are the SKL-H macros?
I think we should try to get GPIO on C62x work rather than on relying on FSP to do it for us

Change in coreboot[master]: mainboard/ocp: Add support for OCP platform TiogaPass

[Andrey Petrov (Code Review)]

Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38549 )

Change subject: mainboard/ocp: Add support for OCP platform TiogaPass
......................................................................

Patch Set 24:

(1 comment)

https://review.coreboot.org/c/coreboot/+/38549/24/src/mainboard/ocp/tiogapas... 
File src/mainboard/ocp/tiogapass/emmc.h:

https://review.coreboot.org/c/coreboot/+/38549/24/src/mainboard/ocp/tiogapas... 
PS24, Line 18: #ifndef _MAINBOARD_EMMC_H
             : #define _MAINBOARD_EMMC_H
             : 
             : #include <fsp/util.h>
             : 
             : /*
             :  * eMMC DLL structure for EMMC DLL registers settings
             :  */
             : typedef struct {
             : 		UINT32 TxCmdCntl;
             : 		UINT32 TxDataCntl1;
             : 		UINT32 TxDataCntl2;
             : 		UINT32 RxCmdDataCntl1;
             : 		UINT32 RxStrobeCntl;
             : 		UINT32 RxCmdDataCntl2;
             : 		UINT32 MasterSwCntl;
             : } BL_EMMC_DLL_CONFIG;
             : 
             : typedef struct {
             : 	UINT16 Signature;
             : 	BL_EMMC_DLL_CONFIG eMMCDLLConfig;
             : } BL_EMMC_INFORMATION;
             : 
             : #define DEFAULT_EMMC_DLL_SIGN 0x55aa
             : 
             : #ifndef __ACPI__
             : BL_EMMC_INFORMATION tiogapass_emmc_config[] = {
             : 	/*
             : 	 *  Default eMMC DLL configuration.
             : 	 */
             : 	{DEFAULT_EMMC_DLL_SIGN,
             : 	 {0x00000508, 0x00000c11, 0x1c2a2a2a, 0x00191e27, 0x00000a0a,
             : 	  0x00010013, 0x00000001} } };
             : #endif
             : 
             : #endif /* _MAINBOARD_EMMC_H */
there is no eMMC on Tioga Pass

Change in coreboot[master]: mainboard/ocp: Add support for OCP platform TiogaPass

[Jonathan Zhang (Code Review)]

Hello HAOUAS Elyes, Johnny Lin, David Hendricks, build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38549

to look at the new patch set (#25).

Change subject: mainboard/ocp: Add support for OCP platform TiogaPass
......................................................................

mainboard/ocp: Add support for OCP platform TiogaPass

OCP platform Tiogapass is a 2-socket server platform, which
is based on a chipset including Intel Skylake-SP processors
and a Lewisburg PCH.

Following ACPI tables are added:
DSDT/SSDT, MADT, FACP, FACS, HPET, MCFG, SLIT, SRAT, DMAR

This patchset is tested on a Tiogapass board. It booted with
Linux kernel 4.16.0; lscpu command shows all 72 cpus (2 sockets,
18 cores, 2 thread per core); ssh command shows
networking is up from Mellanox ConnectX-4 PCIe NIC card.

Towards successful gerrit buildbot build, note that:
* microcode is in coreboot intel-microcode submodule repo.
* IFD binary is included in this patch.
* Dummy ME binary is used, as it may take long time for Intel
ME binary to be available in public domain.
* Fake FSP binary is used, as at this moment the SKX-SP
FSP binary is not going to be available in public domain.

Known issues (Not intend to address in this initial support for
Xeon-SP processors):
* c6 state is not supported.
* dsdt table is not fully populated, such as processor/socket
devices, some PCIe devices.
* SMM handlers are not added.

Following are some command execution with CentOS booted from
local SATA disk:
[root@localhost ~]# lscpu
Architecture:          x86_64
CPU op-mode(s):        32-bit, 64-bit
Byte Order:            Little Endian
CPU(s):                72
On-line CPU(s) list:   0-71
Thread(s) per core:    2
Core(s) per socket:    18
Socket(s):             2
NUMA node(s):          2
Vendor ID:             GenuineIntel
CPU family:            6
Model:                 85
Model name:            Intel(R) Xeon(R) Gold 6139 CPU @ 2.30GHz
Stepping:              4
CPU MHz:               140.415
BogoMIPS:              4626.46
Virtualization:        VT-x
L1d cache:             32K
L1i cache:             32K
L2 cache:              1024K
L3 cache:              25344K
NUMA node0 CPU(s):     0-17,36-53
NUMA node1 CPU(s):     18-35,54-71
[root@localhost ~]# ifconfig
eth0: flags=4163<UP,BROADCAST,RUNNING,MULTICAST>  mtu 1500
        inet 172.23.68.190  netmask 255.255.0.0  broadcast 172.23.255.255
        inet6 2620:10d:c082:9063:268a:7ff:fe57:5af0  prefixlen 64 //cut
        inet6 fe80::268a:7ff:fe57:5af0  prefixlen 64  scopeid 0x20<link>
        inet6 2620:10d:c082:9063::5d2  prefixlen 128  scopeid 0x0<global>
        ether 24:8a:07:57:5a:f0  txqueuelen 1000  (Ethernet)
        RX packets 84249  bytes 6371591 (6.0 MiB)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 8418  bytes 748781 (731.2 KiB)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0

lo: flags=73<UP,LOOPBACK,RUNNING>  mtu 65536
        inet 127.0.0.1  netmask 255.0.0.0
        inet6 ::1  prefixlen 128  scopeid 0x10<host>
        loop  txqueuelen 1000  (Local Loopback)
        RX packets 613  bytes 63906 (62.4 KiB)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 613  bytes 63906 (62.4 KiB)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0
[root@localhost ~]# cbmem
36 entries total:

// Lines were cut to avoid checkpatch.pl warnings

Total Time: 96,243,882,140,175,829

Signed-off-by: Jonathan Zhang 
Signed-off-by: Reddy Chagam 
Tested-by: [e-mail]
Change-Id: I29868f03037d1887b90dfb19d15aee83c456edce
---
A configs/config.ocp_tiogapass
A src/mainboard/ocp/Kconfig
A src/mainboard/ocp/Kconfig.name
A src/mainboard/ocp/tiogapass/Kconfig
A src/mainboard/ocp/tiogapass/Kconfig.name
A src/mainboard/ocp/tiogapass/Makefile.inc
A src/mainboard/ocp/tiogapass/acpi/platform.asl
A src/mainboard/ocp/tiogapass/acpi_tables.c
A src/mainboard/ocp/tiogapass/blobs/ifd.bin
A src/mainboard/ocp/tiogapass/blobs/me_dummy.bin
A src/mainboard/ocp/tiogapass/board.fmd
A src/mainboard/ocp/tiogapass/board_info.txt
A src/mainboard/ocp/tiogapass/boardid.c
A src/mainboard/ocp/tiogapass/devicetree.cb
A src/mainboard/ocp/tiogapass/dsdt.asl
A src/mainboard/ocp/tiogapass/fadt.c
A src/mainboard/ocp/tiogapass/ramstage.c
A src/mainboard/ocp/tiogapass/romstage.c
A src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h
A src/mainboard/ocp/tiogapass/skxsp_tp_iio.h
A src/mainboard/ocp/tiogapass/tiogapass_boardid.h
21 files changed, 1,966 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/38549/25

Change in coreboot[master]: mainboard/ocp: Add support for OCP platform TiogaPass

[Jonathan Zhang (Code Review)]

Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38549 )

Change subject: mainboard/ocp: Add support for OCP platform TiogaPass
......................................................................

Patch Set 25:

(4 comments)

Thanks for the review, Andrey,

https://review.coreboot.org/c/coreboot/+/38549/24/src/mainboard/ocp/tiogapas... 
File src/mainboard/ocp/tiogapass/board.fmd:

https://review.coreboot.org/c/coreboot/+/38549/24/src/mainboard/ocp/tiogapas... 
PS24, Line 8: MISC_RW
> we do not have RO here, everything is RW. […]

We will have RO_VPD in future, to store stuffs like default configurations.

https://review.coreboot.org/c/coreboot/+/38549/24/src/mainboard/ocp/tiogapas... 
File src/mainboard/ocp/tiogapass/emmc.h:

https://review.coreboot.org/c/coreboot/+/38549/24/src/mainboard/ocp/tiogapas... 
PS24, Line 18: #ifndef _MAINBOARD_EMMC_H
             : #define _MAINBOARD_EMMC_H
             : 
             : #include <fsp/util.h>
             : 
             : /*
             :  * eMMC DLL structure for EMMC DLL registers settings
             :  */
             : typedef struct {
             : 		UINT32 TxCmdCntl;
             : 		UINT32 TxDataCntl1;
             : 		UINT32 TxDataCntl2;
             : 		UINT32 RxCmdDataCntl1;
             : 		UINT32 RxStrobeCntl;
             : 		UINT32 RxCmdDataCntl2;
             : 		UINT32 MasterSwCntl;
             : } BL_EMMC_DLL_CONFIG;
             : 
             : typedef struct {
             : 	UINT16 Signature;
             : 	BL_EMMC_DLL_CONFIG eMMCDLLConfig;
             : } BL_EMMC_INFORMATION;
             : 
             : #define DEFAULT_EMMC_DLL_SIGN 0x55aa
             : 
             : #ifndef __ACPI__
             : BL_EMMC_INFORMATION tiogapass_emmc_config[] = {
             : 	/*
             : 	 *  Default eMMC DLL configuration.
             : 	 */
             : 	{DEFAULT_EMMC_DLL_SIGN,
             : 	 {0x00000508, 0x00000c11, 0x1c2a2a2a, 0x00191e27, 0x00000a0a,
             : 	  0x00010013, 0x00000001} } };
             : #endif
             : 
             : #endif /* _MAINBOARD_EMMC_H */
> there is no eMMC on Tioga Pass

Done

https://review.coreboot.org/c/coreboot/+/38549/24/src/mainboard/ocp/tiogapas... 
File src/mainboard/ocp/tiogapass/romstage.c:

https://review.coreboot.org/c/coreboot/+/38549/24/src/mainboard/ocp/tiogapas... 
PS24, Line 24: #define PCH_SERVER_BIOS_FLAG 1
> again I do not think it make sense to have this flag

We can take care of this in future work.

https://review.coreboot.org/c/coreboot/+/38549/24/src/mainboard/ocp/tiogapas... 
PS24, Line 37: 	mupd->FspmConfig.GpioConfig.GpioTable = (UPD_GPIO_INIT_CONFIG *) tp_gpio_table;
             : 	mupd->FspmConfig.GpioConfig.NumberOfEntries =
             : 		sizeof(tp_gpio_table)/sizeof(UPD_GPIO_INIT_CONFIG);
> So on this board we have C62x PCH. What are the SKL-H macros? […]

Those are GPIO configurations. We should discuss with Intel so that current generation Xeon-SP FSP does not do it.

Change in coreboot[master]: mainboard/ocp: Add support for OCP platform TiogaPass

[Andrey Petrov (Code Review)]

Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38549 )

Change subject: mainboard/ocp: Add support for OCP platform TiogaPass
......................................................................

Patch Set 25:

(2 comments)

https://review.coreboot.org/c/coreboot/+/38549/24/src/mainboard/ocp/tiogapas... 
File src/mainboard/ocp/tiogapass/board.fmd:

https://review.coreboot.org/c/coreboot/+/38549/24/src/mainboard/ocp/tiogapas... 
PS24, Line 8: MISC_RW
> We will have RO_VPD in future, to store stuffs like default configurations.

yeah we want to use VPD but there is no notion of RO and RW parts of flash. The board does not use WP (write protect pin) of SPI flash chip. We need to keep VPD but we do not need WP_RO section as such. Everything is RW

https://review.coreboot.org/c/coreboot/+/38549/24/src/mainboard/ocp/tiogapas... 
File src/mainboard/ocp/tiogapass/romstage.c:

https://review.coreboot.org/c/coreboot/+/38549/24/src/mainboard/ocp/tiogapas... 
PS24, Line 37: 	mupd->FspmConfig.GpioConfig.GpioTable = (UPD_GPIO_INIT_CONFIG *) tp_gpio_table;
             : 	mupd->FspmConfig.GpioConfig.NumberOfEntries =
             : 		sizeof(tp_gpio_table)/sizeof(UPD_GPIO_INIT_CONFIG);
> Those are GPIO configurations. […]

if we want FSP to leave GPIO alone, we just need to set GpioTable to NULL and NumberOfEntries to 0. But that besides the point. The point is that we need to add gpio driver for C62x PCH. But yeah we do not need to worry about that in this particular patch, I am just thinking aloud.

Change in coreboot[master]: mainboard/ocp: Add support for OCP platform TiogaPass

[Andrey Petrov (Code Review)]

Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38549 )

Change subject: mainboard/ocp: Add support for OCP platform TiogaPass
......................................................................

Patch Set 25:

(1 comment)

https://review.coreboot.org/c/coreboot/+/38549/25/src/mainboard/ocp/tiogapas... 
File src/mainboard/ocp/tiogapass/romstage.c:

https://review.coreboot.org/c/coreboot/+/38549/25/src/mainboard/ocp/tiogapas... 
PS25, Line 24: #define PCH_SERVER_BIOS_FLAG 1
unused; remove

Change in coreboot[master]: mainboard/ocp: Add support for OCP platform TiogaPass

[Jonathan Zhang (Code Review)]

Hello HAOUAS Elyes, Johnny Lin, David Hendricks, build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38549

to look at the new patch set (#26).

Change subject: mainboard/ocp: Add support for OCP platform TiogaPass
......................................................................

mainboard/ocp: Add support for OCP platform TiogaPass

OCP platform Tiogapass is a 2-socket server platform, which
is based on a chipset including Intel Skylake-SP processors
and a Lewisburg PCH. Skylake-SP is a processor in Intel Xeon
Scalable Processor family.

Following ACPI tables are added:
DSDT/SSDT, MADT, FACP, FACS, HPET, MCFG, SLIT, SRAT, DMAR

This patchset is tested on a Tiogapass board. It booted with
Linux kernel 4.16.0; lscpu command shows all 72 cpus (2 sockets,
18 cores, 2 thread per core); ssh command shows
networking is up from Mellanox ConnectX-4 PCIe NIC card.

Towards successful gerrit buildbot build, note that:
* microcode is in coreboot intel-microcode submodule repo.
* IFD binary is included in this patch.
* Dummy ME binary is used, as it may take long time for Intel
ME binary to be available in public domain.
* Fake FSP binary is used, as at this moment the SKX-SP
FSP binary is not going to be available in public domain.

Known issues (Not intend to address in this initial support for
Xeon-SP processors):
* c6 state is not supported.
* dsdt table is not fully populated, such as processor/socket
devices, some PCIe devices.
* SMM handlers are not added.

Following are some command execution with CentOS booted from
local SATA disk:
[root@localhost ~]# lscpu
Architecture:          x86_64
CPU op-mode(s):        32-bit, 64-bit
Byte Order:            Little Endian
CPU(s):                72
On-line CPU(s) list:   0-71
Thread(s) per core:    2
Core(s) per socket:    18
Socket(s):             2
NUMA node(s):          2
Vendor ID:             GenuineIntel
CPU family:            6
Model:                 85
Model name:            Intel(R) Xeon(R) Gold 6139 CPU @ 2.30GHz
Stepping:              4
CPU MHz:               140.415
BogoMIPS:              4626.46
Virtualization:        VT-x
L1d cache:             32K
L1i cache:             32K
L2 cache:              1024K
L3 cache:              25344K
NUMA node0 CPU(s):     0-17,36-53
NUMA node1 CPU(s):     18-35,54-71
[root@localhost ~]# ifconfig
eth0: flags=4163<UP,BROADCAST,RUNNING,MULTICAST>  mtu 1500
        inet 172.23.68.190  netmask 255.255.0.0  broadcast 172.23.255.255
        inet6 2620:10d:c082:9063:268a:7ff:fe57:5af0  prefixlen 64 //cut
        inet6 fe80::268a:7ff:fe57:5af0  prefixlen 64  scopeid 0x20<link>
        inet6 2620:10d:c082:9063::5d2  prefixlen 128  scopeid 0x0<global>
        ether 24:8a:07:57:5a:f0  txqueuelen 1000  (Ethernet)
        RX packets 84249  bytes 6371591 (6.0 MiB)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 8418  bytes 748781 (731.2 KiB)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0

lo: flags=73<UP,LOOPBACK,RUNNING>  mtu 65536
        inet 127.0.0.1  netmask 255.0.0.0
        inet6 ::1  prefixlen 128  scopeid 0x10<host>
        loop  txqueuelen 1000  (Local Loopback)
        RX packets 613  bytes 63906 (62.4 KiB)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 613  bytes 63906 (62.4 KiB)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0
[root@localhost ~]# cbmem
36 entries total:

// Lines were cut to avoid checkpatch.pl warnings

Total Time: 96,243,882,140,175,829

Signed-off-by: Jonathan Zhang 
Signed-off-by: Reddy Chagam 
Tested-by: [e-mail]
Change-Id: I29868f03037d1887b90dfb19d15aee83c456edce
---
A configs/config.ocp_tiogapass
A src/mainboard/ocp/Kconfig
A src/mainboard/ocp/Kconfig.name
A src/mainboard/ocp/tiogapass/Kconfig
A src/mainboard/ocp/tiogapass/Kconfig.name
A src/mainboard/ocp/tiogapass/Makefile.inc
A src/mainboard/ocp/tiogapass/acpi/platform.asl
A src/mainboard/ocp/tiogapass/acpi_tables.c
A src/mainboard/ocp/tiogapass/blobs/ifd.bin
A src/mainboard/ocp/tiogapass/blobs/me_dummy.bin
A src/mainboard/ocp/tiogapass/board.fmd
A src/mainboard/ocp/tiogapass/board_info.txt
A src/mainboard/ocp/tiogapass/boardid.c
A src/mainboard/ocp/tiogapass/devicetree.cb
A src/mainboard/ocp/tiogapass/dsdt.asl
A src/mainboard/ocp/tiogapass/fadt.c
A src/mainboard/ocp/tiogapass/ramstage.c
A src/mainboard/ocp/tiogapass/romstage.c
A src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h
A src/mainboard/ocp/tiogapass/skxsp_tp_iio.h
A src/mainboard/ocp/tiogapass/tiogapass_boardid.h
21 files changed, 1,965 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/38549/26

Change in coreboot[master]: mainboard/ocp: Add support for OCP platform TiogaPass

[Jonathan Zhang (Code Review)]

Hello HAOUAS Elyes, Johnny Lin, David Hendricks, build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38549

to look at the new patch set (#27).

Change subject: mainboard/ocp: Add support for OCP platform TiogaPass
......................................................................

mainboard/ocp: Add support for OCP platform TiogaPass

OCP platform Tiogapass is a 2-socket server platform, which
is based on a chipset including Intel Skylake-SP processors
and a Lewisburg PCH. Skylake-SP is a processor in Intel Xeon
Scalable Processor family.

Following ACPI tables are added:
DSDT/SSDT, MADT, FACP, FACS, HPET, MCFG, SLIT, SRAT, DMAR

This patchset is tested on a Tiogapass board. It booted with
Linux kernel 4.16.0; lscpu command shows all 72 cpus (2 sockets,
18 cores, 2 thread per core); ssh command shows
networking is up from Mellanox ConnectX-4 PCIe NIC card.

Towards successful gerrit buildbot build, note that:
* microcode is in coreboot intel-microcode submodule repo.
* IFD binary is included in this patch.
* Dummy ME binary is used, as it may take long time for Intel
ME binary to be available in public domain.
* Fake FSP binary is used, as at this moment the SKX-SP
FSP binary is not going to be available in public domain.

Known issues (Not intend to address in this initial support for
Xeon-SP processors):
* c6 state is not supported.
* dsdt table is not fully populated, such as processor/socket
devices, some PCIe devices.
* SMM handlers are not added.

Following are some command execution with CentOS booted from
local SATA disk:
[root@localhost ~]# lscpu
Architecture:          x86_64
CPU op-mode(s):        32-bit, 64-bit
Byte Order:            Little Endian
CPU(s):                72
On-line CPU(s) list:   0-71
Thread(s) per core:    2
Core(s) per socket:    18
Socket(s):             2
NUMA node(s):          2
Vendor ID:             GenuineIntel
CPU family:            6
Model:                 85
Model name:            Intel(R) Xeon(R) Gold 6139 CPU @ 2.30GHz
Stepping:              4
CPU MHz:               140.415
BogoMIPS:              4626.46
Virtualization:        VT-x
L1d cache:             32K
L1i cache:             32K
L2 cache:              1024K
L3 cache:              25344K
NUMA node0 CPU(s):     0-17,36-53
NUMA node1 CPU(s):     18-35,54-71
[root@localhost ~]# ifconfig
eth0: flags=4163<UP,BROADCAST,RUNNING,MULTICAST>  mtu 1500
        inet 172.23.68.190  netmask 255.255.0.0  broadcast 172.23.255.255
        inet6 2620:10d:c082:9063:268a:7ff:fe57:5af0  prefixlen 64 //cut
        inet6 fe80::268a:7ff:fe57:5af0  prefixlen 64  scopeid 0x20<link>
        inet6 2620:10d:c082:9063::5d2  prefixlen 128  scopeid 0x0<global>
        ether 24:8a:07:57:5a:f0  txqueuelen 1000  (Ethernet)
        RX packets 84249  bytes 6371591 (6.0 MiB)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 8418  bytes 748781 (731.2 KiB)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0

lo: flags=73<UP,LOOPBACK,RUNNING>  mtu 65536
        inet 127.0.0.1  netmask 255.0.0.0
        inet6 ::1  prefixlen 128  scopeid 0x10<host>
        loop  txqueuelen 1000  (Local Loopback)
        RX packets 613  bytes 63906 (62.4 KiB)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 613  bytes 63906 (62.4 KiB)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0
[root@localhost ~]# cbmem
36 entries total:

// Lines were cut to avoid checkpatch.pl warnings

Total Time: 96,243,882,140,175,829

Signed-off-by: Jonathan Zhang 
Signed-off-by: Reddy Chagam 
Tested-by: [e-mail]
Change-Id: I29868f03037d1887b90dfb19d15aee83c456edce
---
A configs/config.ocp_tiogapass
A src/mainboard/ocp/Kconfig
A src/mainboard/ocp/Kconfig.name
A src/mainboard/ocp/tiogapass/Kconfig
A src/mainboard/ocp/tiogapass/Kconfig.name
A src/mainboard/ocp/tiogapass/Makefile.inc
A src/mainboard/ocp/tiogapass/acpi/platform.asl
A src/mainboard/ocp/tiogapass/acpi_tables.c
A src/mainboard/ocp/tiogapass/blobs/ifd.bin
A src/mainboard/ocp/tiogapass/blobs/me_dummy.bin
A src/mainboard/ocp/tiogapass/board.fmd
A src/mainboard/ocp/tiogapass/board_info.txt
A src/mainboard/ocp/tiogapass/boardid.c
A src/mainboard/ocp/tiogapass/devicetree.cb
A src/mainboard/ocp/tiogapass/dsdt.asl
A src/mainboard/ocp/tiogapass/fadt.c
A src/mainboard/ocp/tiogapass/ramstage.c
A src/mainboard/ocp/tiogapass/romstage.c
A src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h
A src/mainboard/ocp/tiogapass/skxsp_tp_iio.h
A src/mainboard/ocp/tiogapass/tiogapass_boardid.h
21 files changed, 1,965 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/38549/27

Change in coreboot[master]: mainboard/ocp: Add support for OCP platform TiogaPass

[Jonathan Zhang (Code Review)]

Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38549 )

Change subject: mainboard/ocp: Add support for OCP platform TiogaPass
......................................................................

Patch Set 27:

(1 comment)

https://review.coreboot.org/c/coreboot/+/38549/25/src/mainboard/ocp/tiogapas... 
File src/mainboard/ocp/tiogapass/romstage.c:

https://review.coreboot.org/c/coreboot/+/38549/25/src/mainboard/ocp/tiogapas... 
PS25, Line 24: #define PCH_SERVER_BIOS_FLAG 1
> unused; remove

Done

Change in coreboot[master]: mainboard/ocp: Add support for OCP platform TiogaPass

[Jonathan Zhang (Code Review)]

Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38549 )

Change subject: mainboard/ocp: Add support for OCP platform TiogaPass
......................................................................

Patch Set 28:

(1 comment)

https://review.coreboot.org/c/coreboot/+/38549/24/src/mainboard/ocp/tiogapas... 
File src/mainboard/ocp/tiogapass/romstage.c:

https://review.coreboot.org/c/coreboot/+/38549/24/src/mainboard/ocp/tiogapas... 
PS24, Line 24: #define PCH_SERVER_BIOS_FLAG 1
> We can take care of this in future work.

Done

Change in coreboot[master]: mainboard/ocp: Add support for OCP platform TiogaPass

[David Hendricks (Code Review)]

David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38549 )

Change subject: mainboard/ocp: Add support for OCP platform TiogaPass
......................................................................

Patch Set 31: Code-Review-1

(1 comment)

There seems to be something wrong with Kconfig... here's an error I see when I try to `make menuconfig`:
$ make menuconfig
warning: (BOARD_SPECIFIC_OPTIONS && BOARD_SPECIFIC_OPTIONS && CPU_SPECIFIC_OPTIONS) selects FSP_USE_REPO which has unmet direct dependencies (PLATFORM_USES_FSP1_1 && SOC_INTEL_BRASWELL && !USE_GOOGLE_FSP || PLATFORM_USES_FSP2_0 && ADD_FSP_BINARIES && (SOC_INTEL_APOLLOLAKE || SOC_INTEL_SKYLAKE || SOC_INTEL_KABYLAKE || SOC_INTEL_COFFEELAKE || SOC_INTEL_ICELAKE || SOC_INTEL_WHISKEYLAKE || SOC_INTEL_XEON_SP))

*** ERROR: 1 warnings encountered, and warnings are errors.

Your configuration changes were NOT saved.

https://review.coreboot.org/c/coreboot/+/38549/14/src/mainboard/ocp/tiogapas... 
File src/mainboard/ocp/tiogapass/Kconfig:

https://review.coreboot.org/c/coreboot/+/38549/14/src/mainboard/ocp/tiogapas... 
PS14, Line 34: OCP
> Done

Vendor is specified by the MAINBOARD_VENDOR value, adding "OCP" here is redundant.

Change in coreboot[master]: mainboard/ocp: Add support for OCP platform TiogaPass

[David Hendricks (Code Review)]

David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38549 )

Change subject: mainboard/ocp: Add support for OCP platform TiogaPass
......................................................................

Patch Set 31:

(1 comment)
> Patch Set 31: Code-Review-1
>
> (1 comment)
>
> There seems to be something wrong with Kconfig... here's an error I see when I try to `make menuconfig`:
> $ make menuconfig
> warning: (BOARD_SPECIFIC_OPTIONS && BOARD_SPECIFIC_OPTIONS && CPU_SPECIFIC_OPTIONS) selects FSP_USE_REPO which has unmet direct dependencies (PLATFORM_USES_FSP1_1 && SOC_INTEL_BRASWELL && !USE_GOOGLE_FSP || PLATFORM_USES_FSP2_0 && ADD_FSP_BINARIES && (SOC_INTEL_APOLLOLAKE || SOC_INTEL_SKYLAKE || SOC_INTEL_KABYLAKE || SOC_INTEL_COFFEELAKE || SOC_INTEL_ICELAKE || SOC_INTEL_WHISKEYLAKE || SOC_INTEL_XEON_SP))
>
> *** ERROR: 1 warnings encountered, and warnings are errors.
>
> Your configuration changes were NOT saved.

Turns out we just need to select ADD_FSP_BINARIES in the mainboard's Kconfig.

https://review.coreboot.org/c/coreboot/+/38549/31/src/mainboard/ocp/tiogapas... 
File src/mainboard/ocp/tiogapass/Kconfig:

https://review.coreboot.org/c/coreboot/+/38549/31/src/mainboard/ocp/tiogapas... 
PS31, Line 21: 	def_bool y
select ADD_FSP_BINARIES

Change in coreboot[master]: mainboard/ocp: Add support for OCP platform TiogaPass

[Jonathan Zhang (Code Review)]

Hello HAOUAS Elyes, Johnny Lin, David Hendricks, build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38549

to look at the new patch set (#33).

Change subject: mainboard/ocp: Add support for OCP platform TiogaPass
......................................................................

mainboard/ocp: Add support for OCP platform TiogaPass

OCP platform Tiogapass is a 2-socket server platform, which
is based on a chipset including Intel Skylake-SP processors
and a Lewisburg PCH. Skylake-SP is a processor in Intel Xeon
Scalable Processor family.

Following ACPI tables are added:
DSDT/SSDT, MADT, FACP, FACS, HPET, MCFG, SLIT, SRAT, DMAR

This patchset is tested on a Tiogapass board. It booted with
Linux kernel 4.16.0; lscpu command shows all 72 cpus (2 sockets,
18 cores, 2 thread per core); ssh command shows
networking is up from Mellanox ConnectX-4 PCIe NIC card.

Towards successful gerrit buildbot build, note that:
* microcode is in coreboot intel-microcode submodule repo.
* IFD binary is included in this patch.
* Dummy ME binary is used, as it may take long time for Intel
ME binary to be available in public domain.
* Fake FSP binary is used, as at this moment the SKX-SP
FSP binary is not going to be available in public domain.

Known issues (Not intend to address in this initial support for
Xeon-SP processors):
* c6 state is not supported.
* dsdt table is not fully populated, such as processor/socket
devices, some PCIe devices.
* SMM handlers are not added.

Following are some command execution with CentOS booted from
local SATA disk:
[root@localhost ~]# lscpu
Architecture:          x86_64
CPU op-mode(s):        32-bit, 64-bit
Byte Order:            Little Endian
CPU(s):                72
On-line CPU(s) list:   0-71
Thread(s) per core:    2
Core(s) per socket:    18
Socket(s):             2
NUMA node(s):          2
Vendor ID:             GenuineIntel
CPU family:            6
Model:                 85
Model name:            Intel(R) Xeon(R) Gold 6139 CPU @ 2.30GHz
Stepping:              4
CPU MHz:               140.415
BogoMIPS:              4626.46
Virtualization:        VT-x
L1d cache:             32K
L1i cache:             32K
L2 cache:              1024K
L3 cache:              25344K
NUMA node0 CPU(s):     0-17,36-53
NUMA node1 CPU(s):     18-35,54-71
[root@localhost ~]# ifconfig
eth0: flags=4163<UP,BROADCAST,RUNNING,MULTICAST>  mtu 1500
        inet 172.23.68.190  netmask 255.255.0.0  broadcast 172.23.255.255
        inet6 2620:10d:c082:9063:268a:7ff:fe57:5af0  prefixlen 64 //cut
        inet6 fe80::268a:7ff:fe57:5af0  prefixlen 64  scopeid 0x20<link>
        inet6 2620:10d:c082:9063::5d2  prefixlen 128  scopeid 0x0<global>
        ether 24:8a:07:57:5a:f0  txqueuelen 1000  (Ethernet)
        RX packets 84249  bytes 6371591 (6.0 MiB)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 8418  bytes 748781 (731.2 KiB)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0

lo: flags=73<UP,LOOPBACK,RUNNING>  mtu 65536
        inet 127.0.0.1  netmask 255.0.0.0
        inet6 ::1  prefixlen 128  scopeid 0x10<host>
        loop  txqueuelen 1000  (Local Loopback)
        RX packets 613  bytes 63906 (62.4 KiB)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 613  bytes 63906 (62.4 KiB)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0
[root@localhost ~]# cbmem
36 entries total:

// Lines were cut to avoid checkpatch.pl warnings

Total Time: 96,243,882,140,175,829

Signed-off-by: Jonathan Zhang 
Signed-off-by: Reddy Chagam 
Tested-by: [e-mail]
Change-Id: I29868f03037d1887b90dfb19d15aee83c456edce
---
A configs/config.ocp_tiogapass
A src/mainboard/ocp/Kconfig
A src/mainboard/ocp/Kconfig.name
A src/mainboard/ocp/tiogapass/Kconfig
A src/mainboard/ocp/tiogapass/Kconfig.name
A src/mainboard/ocp/tiogapass/Makefile.inc
A src/mainboard/ocp/tiogapass/acpi/platform.asl
A src/mainboard/ocp/tiogapass/acpi_tables.c
A src/mainboard/ocp/tiogapass/blobs/ifd.bin
A src/mainboard/ocp/tiogapass/blobs/me_dummy.bin
A src/mainboard/ocp/tiogapass/board.fmd
A src/mainboard/ocp/tiogapass/board_info.txt
A src/mainboard/ocp/tiogapass/boardid.c
A src/mainboard/ocp/tiogapass/devicetree.cb
A src/mainboard/ocp/tiogapass/dsdt.asl
A src/mainboard/ocp/tiogapass/fadt.c
A src/mainboard/ocp/tiogapass/ramstage.c
A src/mainboard/ocp/tiogapass/romstage.c
A src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h
A src/mainboard/ocp/tiogapass/skxsp_tp_iio.h
A src/mainboard/ocp/tiogapass/tiogapass_boardid.h
21 files changed, 1,961 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/38549/33

Change in coreboot[master]: mainboard/ocp: Add support for OCP platform TiogaPass

[Jonathan Zhang (Code Review)]

Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38549 )

Change subject: mainboard/ocp: Add support for OCP platform TiogaPass
......................................................................

Patch Set 33:

(2 comments)

https://review.coreboot.org/c/coreboot/+/38549/14/src/mainboard/ocp/tiogapas... 
File src/mainboard/ocp/tiogapass/Kconfig:

https://review.coreboot.org/c/coreboot/+/38549/14/src/mainboard/ocp/tiogapas... 
PS14, Line 34: OCP
> Vendor is specified by the MAINBOARD_VENDOR value, adding "OCP" here is redundant.

Done

https://review.coreboot.org/c/coreboot/+/38549/31/src/mainboard/ocp/tiogapas... 
File src/mainboard/ocp/tiogapass/Kconfig:

https://review.coreboot.org/c/coreboot/+/38549/31/src/mainboard/ocp/tiogapas... 
PS31, Line 21: 	def_bool y
> select ADD_FSP_BINARIES

Yes. I did have this in configs/config.ocp_tiogapss. But it makes more sense to select it in tiogapss/Kconfig. I made the change and also remove the line from configs/config.ocp_tiogapass

Change in coreboot[master]: mainboard/ocp: Add support for OCP platform TiogaPass

[HAOUAS Elyes (Code Review)]

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38549 )

Change subject: mainboard/ocp: Add support for OCP platform TiogaPass
......................................................................

Patch Set 33:

(1 comment)

Thx

https://review.coreboot.org/c/coreboot/+/38549/33/src/mainboard/ocp/tiogapas... 
File src/mainboard/ocp/tiogapass/romstage.c:

https://review.coreboot.org/c/coreboot/+/38549/33/src/mainboard/ocp/tiogapas... 
PS33, Line 19: #include <console/console.h>
maybe not use.
would you please include only what you use ?

Change in coreboot[master]: mainboard/ocp: Add support for OCP platform TiogaPass

[Jonathan Zhang (Code Review)]

Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38549 )

Change subject: mainboard/ocp: Add support for OCP platform TiogaPass
......................................................................

Patch Set 33:

(1 comment)

Thanks. Changes made locally. Will upload a version in 24 hours to collect changes for other comments if any.

https://review.coreboot.org/c/coreboot/+/38549/33/src/mainboard/ocp/tiogapas... 
File src/mainboard/ocp/tiogapass/romstage.c:

https://review.coreboot.org/c/coreboot/+/38549/33/src/mainboard/ocp/tiogapas... 
PS33, Line 19: #include <console/console.h>
> maybe not use. […]

Done

Change in coreboot[master]: mainboard/ocp: Add support for OCP platform TiogaPass

[Johnny Lin (Code Review)]

Johnny Lin has uploaded a new patch set (#34) to the change originally created by Jonathan Zhang. ( https://review.coreboot.org/c/coreboot/+/38549 )

Change subject: mainboard/ocp: Add support for OCP platform TiogaPass
......................................................................

mainboard/ocp: Add support for OCP platform TiogaPass

OCP platform Tiogapass is a 2-socket server platform, which
is based on a chipset including Intel Skylake-SP processors
and a Lewisburg PCH. Skylake-SP is a processor in Intel Xeon
Scalable Processor family.

Following ACPI tables are added:
DSDT/SSDT, MADT, FACP, FACS, HPET, MCFG, SLIT, SRAT, DMAR

This patchset is tested on a Tiogapass board. It booted with
Linux kernel 4.16.0; lscpu command shows all 72 cpus (2 sockets,
18 cores, 2 thread per core); ssh command shows
networking is up from Mellanox ConnectX-4 PCIe NIC card.

Towards successful gerrit buildbot build, note that:
* microcode is in coreboot intel-microcode submodule repo.
* IFD binary is included in this patch.
* Dummy ME binary is used, as it may take long time for Intel
ME binary to be available in public domain.
* Fake FSP binary is used, as at this moment the SKX-SP
FSP binary is not going to be available in public domain.

Known issues (Not intend to address in this initial support for
Xeon-SP processors):
* c6 state is not supported.
* dsdt table is not fully populated, such as processor/socket
devices, some PCIe devices.
* SMM handlers are not added.

Following are some command execution with CentOS booted from
local SATA disk:
[root@localhost ~]# lscpu
Architecture:          x86_64
CPU op-mode(s):        32-bit, 64-bit
Byte Order:            Little Endian
CPU(s):                72
On-line CPU(s) list:   0-71
Thread(s) per core:    2
Core(s) per socket:    18
Socket(s):             2
NUMA node(s):          2
Vendor ID:             GenuineIntel
CPU family:            6
Model:                 85
Model name:            Intel(R) Xeon(R) Gold 6139 CPU @ 2.30GHz
Stepping:              4
CPU MHz:               140.415
BogoMIPS:              4626.46
Virtualization:        VT-x
L1d cache:             32K
L1i cache:             32K
L2 cache:              1024K
L3 cache:              25344K
NUMA node0 CPU(s):     0-17,36-53
NUMA node1 CPU(s):     18-35,54-71
[root@localhost ~]# ifconfig
eth0: flags=4163<UP,BROADCAST,RUNNING,MULTICAST>  mtu 1500
        inet 172.23.68.190  netmask 255.255.0.0  broadcast 172.23.255.255
        inet6 2620:10d:c082:9063:268a:7ff:fe57:5af0  prefixlen 64 //cut
        inet6 fe80::268a:7ff:fe57:5af0  prefixlen 64  scopeid 0x20<link>
        inet6 2620:10d:c082:9063::5d2  prefixlen 128  scopeid 0x0<global>
        ether 24:8a:07:57:5a:f0  txqueuelen 1000  (Ethernet)
        RX packets 84249  bytes 6371591 (6.0 MiB)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 8418  bytes 748781 (731.2 KiB)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0

lo: flags=73<UP,LOOPBACK,RUNNING>  mtu 65536
        inet 127.0.0.1  netmask 255.0.0.0
        inet6 ::1  prefixlen 128  scopeid 0x10<host>
        loop  txqueuelen 1000  (Local Loopback)
        RX packets 613  bytes 63906 (62.4 KiB)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 613  bytes 63906 (62.4 KiB)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0
[root@localhost ~]# cbmem
36 entries total:

// Lines were cut to avoid checkpatch.pl warnings

Total Time: 96,243,882,140,175,829

Signed-off-by: Jonathan Zhang 
Signed-off-by: Reddy Chagam 
Tested-by: [e-mail]
Change-Id: I29868f03037d1887b90dfb19d15aee83c456edce
---
A configs/config.ocp_tiogapass
A src/mainboard/ocp/Kconfig
A src/mainboard/ocp/Kconfig.name
A src/mainboard/ocp/tiogapass/Kconfig
A src/mainboard/ocp/tiogapass/Kconfig.name
A src/mainboard/ocp/tiogapass/Makefile.inc
A src/mainboard/ocp/tiogapass/acpi/platform.asl
A src/mainboard/ocp/tiogapass/acpi_tables.c
A src/mainboard/ocp/tiogapass/blobs/ifd.bin
A src/mainboard/ocp/tiogapass/blobs/me_dummy.bin
A src/mainboard/ocp/tiogapass/board.fmd
A src/mainboard/ocp/tiogapass/board_info.txt
A src/mainboard/ocp/tiogapass/boardid.c
A src/mainboard/ocp/tiogapass/devicetree.cb
A src/mainboard/ocp/tiogapass/dsdt.asl
A src/mainboard/ocp/tiogapass/fadt.c
A src/mainboard/ocp/tiogapass/ramstage.c
A src/mainboard/ocp/tiogapass/romstage.c
A src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h
A src/mainboard/ocp/tiogapass/skxsp_tp_iio.h
A src/mainboard/ocp/tiogapass/tiogapass_boardid.h
21 files changed, 1,959 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/38549/34

Change in coreboot[master]: mainboard/ocp: Add support for OCP platform TiogaPass

[Andrey Petrov (Code Review)]

Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38549 )

Change subject: mainboard/ocp: Add support for OCP platform TiogaPass
......................................................................

Patch Set 35:

(1 comment)

https://review.coreboot.org/c/coreboot/+/38549/24/src/mainboard/ocp/tiogapas... 
File src/mainboard/ocp/tiogapass/board.fmd:

https://review.coreboot.org/c/coreboot/+/38549/24/src/mainboard/ocp/tiogapas... 
PS24, Line 8: MISC_RW
> yeah we want to use VPD but there is no notion of RO and RW parts of flash. […]

I believe this item is not resolved.
The FMD file needs cleanup. There are unused sections below.
Also, the naming implies there are RW and RO regions of flash chip.
This is incorrect.

Change in coreboot[master]: mainboard/ocp: Add support for OCP platform TiogaPass

[Jonathan Zhang (Code Review)]

Hello HAOUAS Elyes, Johnny Lin, David Hendricks, build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38549

to look at the new patch set (#36).

Change subject: mainboard/ocp: Add support for OCP platform TiogaPass
......................................................................

mainboard/ocp: Add support for OCP platform TiogaPass

OCP platform Tiogapass is a 2-socket server platform, which
is based on a chipset including Intel Skylake-SP processors
and a Lewisburg PCH. Skylake-SP is a processor in Intel Xeon
Scalable Processor family.

Following ACPI tables are added:
DSDT/SSDT, MADT, FACP, FACS, HPET, MCFG, SLIT, SRAT, DMAR

This patchset is tested on a Tiogapass board. It booted with
Linux kernel 4.16.0; lscpu command shows all 72 cpus (2 sockets,
18 cores, 2 thread per core); ssh command shows
networking is up from Mellanox ConnectX-4 PCIe NIC card.

Towards successful gerrit buildbot build, note that:
* microcode is in coreboot intel-microcode submodule repo.
* IFD binary is included in this patch.
* Dummy ME binary is used, as it may take long time for Intel
ME binary to be available in public domain.
* Fake FSP binary is used, as at this moment the SKX-SP
FSP binary is not going to be available in public domain.

Known issues (Not intend to address in this initial support for
Xeon-SP processors):
* c6 state is not supported.
* dsdt table is not fully populated, such as processor/socket
devices, some PCIe devices.
* SMM handlers are not added.

Following are some command execution with CentOS booted from
local SATA disk:
[root@localhost ~]# lscpu
Architecture:          x86_64
CPU op-mode(s):        32-bit, 64-bit
Byte Order:            Little Endian
CPU(s):                72
On-line CPU(s) list:   0-71
Thread(s) per core:    2
Core(s) per socket:    18
Socket(s):             2
NUMA node(s):          2
Vendor ID:             GenuineIntel
CPU family:            6
Model:                 85
Model name:            Intel(R) Xeon(R) Gold 6139 CPU @ 2.30GHz
Stepping:              4
CPU MHz:               140.415
BogoMIPS:              4626.46
Virtualization:        VT-x
L1d cache:             32K
L1i cache:             32K
L2 cache:              1024K
L3 cache:              25344K
NUMA node0 CPU(s):     0-17,36-53
NUMA node1 CPU(s):     18-35,54-71
[root@localhost ~]# ifconfig
eth0: flags=4163<UP,BROADCAST,RUNNING,MULTICAST>  mtu 1500
        inet 172.23.68.190  netmask 255.255.0.0  broadcast 172.23.255.255
        inet6 2620:10d:c082:9063:268a:7ff:fe57:5af0  prefixlen 64 //cut
        inet6 fe80::268a:7ff:fe57:5af0  prefixlen 64  scopeid 0x20<link>
        inet6 2620:10d:c082:9063::5d2  prefixlen 128  scopeid 0x0<global>
        ether 24:8a:07:57:5a:f0  txqueuelen 1000  (Ethernet)
        RX packets 84249  bytes 6371591 (6.0 MiB)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 8418  bytes 748781 (731.2 KiB)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0

lo: flags=73<UP,LOOPBACK,RUNNING>  mtu 65536
        inet 127.0.0.1  netmask 255.0.0.0
        inet6 ::1  prefixlen 128  scopeid 0x10<host>
        loop  txqueuelen 1000  (Local Loopback)
        RX packets 613  bytes 63906 (62.4 KiB)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 613  bytes 63906 (62.4 KiB)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0
[root@localhost ~]# cbmem
36 entries total:

// Lines were cut to avoid checkpatch.pl warnings

Total Time: 96,243,882,140,175,829

Signed-off-by: Jonathan Zhang 
Signed-off-by: Reddy Chagam 
Tested-by: [e-mail]
Change-Id: I29868f03037d1887b90dfb19d15aee83c456edce
---
A configs/config.ocp_tiogapass
A src/mainboard/ocp/Kconfig
A src/mainboard/ocp/Kconfig.name
A src/mainboard/ocp/tiogapass/Kconfig
A src/mainboard/ocp/tiogapass/Kconfig.name
A src/mainboard/ocp/tiogapass/Makefile.inc
A src/mainboard/ocp/tiogapass/acpi/platform.asl
A src/mainboard/ocp/tiogapass/acpi_tables.c
A src/mainboard/ocp/tiogapass/blobs/ifd.bin
A src/mainboard/ocp/tiogapass/blobs/me_dummy.bin
A src/mainboard/ocp/tiogapass/board.fmd
A src/mainboard/ocp/tiogapass/board_info.txt
A src/mainboard/ocp/tiogapass/boardid.c
A src/mainboard/ocp/tiogapass/devicetree.cb
A src/mainboard/ocp/tiogapass/dsdt.asl
A src/mainboard/ocp/tiogapass/fadt.c
A src/mainboard/ocp/tiogapass/ramstage.c
A src/mainboard/ocp/tiogapass/romstage.c
A src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h
A src/mainboard/ocp/tiogapass/skxsp_tp_iio.h
A src/mainboard/ocp/tiogapass/tiogapass_boardid.h
21 files changed, 1,958 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/38549/36

Change in coreboot[master]: mainboard/ocp: Add support for OCP platform TiogaPass

[Jonathan Zhang (Code Review)]

Hello HAOUAS Elyes, Johnny Lin, David Hendricks, build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38549

to look at the new patch set (#37).

Change subject: mainboard/ocp: Add support for OCP platform TiogaPass
......................................................................

mainboard/ocp: Add support for OCP platform TiogaPass

OCP platform Tiogapass is a 2-socket server platform, which
is based on a chipset including Intel Skylake-SP processors
and a Lewisburg PCH. Skylake-SP is a processor in Intel Xeon
Scalable Processor family.

Following ACPI tables are added:
DSDT/SSDT, MADT, FACP, FACS, HPET, MCFG, SLIT, SRAT, DMAR

This patchset is tested on a Tiogapass board. It booted with
Linux kernel 4.16.0; lscpu command shows all 72 cpus (2 sockets,
18 cores, 2 thread per core); ssh command shows
networking is up from Mellanox ConnectX-4 PCIe NIC card.

Towards successful gerrit buildbot build, note that:
* microcode is in coreboot intel-microcode submodule repo.
* IFD binary is included in this patch.
* Dummy ME binary is used, as it may take long time for Intel
ME binary to be available in public domain.
* Fake FSP binary is used, as at this moment the SKX-SP
FSP binary is not going to be available in public domain.

Known issues (Not intend to address in this initial support for
Xeon-SP processors):
* c6 state is not supported.
* dsdt table is not fully populated, such as processor/socket
devices, some PCIe devices.
* SMM handlers are not added.

Following are some command execution with CentOS booted from
local SATA disk:
[root@localhost ~]# lscpu
Architecture:          x86_64
CPU op-mode(s):        32-bit, 64-bit
Byte Order:            Little Endian
CPU(s):                72
On-line CPU(s) list:   0-71
Thread(s) per core:    2
Core(s) per socket:    18
Socket(s):             2
NUMA node(s):          2
Vendor ID:             GenuineIntel
CPU family:            6
Model:                 85
Model name:            Intel(R) Xeon(R) Gold 6139 CPU @ 2.30GHz
Stepping:              4
CPU MHz:               140.415
BogoMIPS:              4626.46
Virtualization:        VT-x
L1d cache:             32K
L1i cache:             32K
L2 cache:              1024K
L3 cache:              25344K
NUMA node0 CPU(s):     0-17,36-53
NUMA node1 CPU(s):     18-35,54-71
[root@localhost ~]# ifconfig
eth0: flags=4163<UP,BROADCAST,RUNNING,MULTICAST>  mtu 1500
        inet 172.23.68.190  netmask 255.255.0.0  broadcast 172.23.255.255
        inet6 2620:10d:c082:9063:268a:7ff:fe57:5af0  prefixlen 64 //cut
        inet6 fe80::268a:7ff:fe57:5af0  prefixlen 64  scopeid 0x20<link>
        inet6 2620:10d:c082:9063::5d2  prefixlen 128  scopeid 0x0<global>
        ether 24:8a:07:57:5a:f0  txqueuelen 1000  (Ethernet)
        RX packets 84249  bytes 6371591 (6.0 MiB)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 8418  bytes 748781 (731.2 KiB)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0

lo: flags=73<UP,LOOPBACK,RUNNING>  mtu 65536
        inet 127.0.0.1  netmask 255.0.0.0
        inet6 ::1  prefixlen 128  scopeid 0x10<host>
        loop  txqueuelen 1000  (Local Loopback)
        RX packets 613  bytes 63906 (62.4 KiB)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 613  bytes 63906 (62.4 KiB)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0
[root@localhost ~]# cbmem
36 entries total:

// Lines were cut to avoid checkpatch.pl warnings

Total Time: 96,243,882,140,175,829

Signed-off-by: Jonathan Zhang 
Signed-off-by: Reddy Chagam 
Tested-by: [e-mail]
Change-Id: I29868f03037d1887b90dfb19d15aee83c456edce
---
A configs/config.ocp_tiogapass
A src/mainboard/ocp/Kconfig
A src/mainboard/ocp/Kconfig.name
A src/mainboard/ocp/tiogapass/Kconfig
A src/mainboard/ocp/tiogapass/Kconfig.name
A src/mainboard/ocp/tiogapass/Makefile.inc
A src/mainboard/ocp/tiogapass/acpi/platform.asl
A src/mainboard/ocp/tiogapass/acpi_tables.c
A src/mainboard/ocp/tiogapass/blobs/ifd.bin
A src/mainboard/ocp/tiogapass/blobs/me_dummy.bin
A src/mainboard/ocp/tiogapass/board.fmd
A src/mainboard/ocp/tiogapass/board_info.txt
A src/mainboard/ocp/tiogapass/boardid.c
A src/mainboard/ocp/tiogapass/devicetree.cb
A src/mainboard/ocp/tiogapass/dsdt.asl
A src/mainboard/ocp/tiogapass/fadt.c
A src/mainboard/ocp/tiogapass/ramstage.c
A src/mainboard/ocp/tiogapass/romstage.c
A src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h
A src/mainboard/ocp/tiogapass/skxsp_tp_iio.h
A src/mainboard/ocp/tiogapass/tiogapass_boardid.h
21 files changed, 1,956 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/38549/37

Change in coreboot[master]: mainboard/ocp: Add support for OCP platform TiogaPass

[David Hendricks (Code Review)]

David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38549 )

Change subject: mainboard/ocp: Add support for OCP platform TiogaPass
......................................................................

Patch Set 38: Code-Review-1

(28 comments)

Mostly small stuff. The main thing is to drop the dummy IFD and ME files by removing HAVE_IFD_BIN and HAVE_ME_BIN from src/mainboard/ocp/tiogapass/Kconfig.

https://review.coreboot.org/c/coreboot/+/38549/38/configs/config.ocp_tiogapa... 
File configs/config.ocp_tiogapass:

https://review.coreboot.org/c/coreboot/+/38549/38/configs/config.ocp_tiogapa... 
PS38, Line 3: CONFIG_CPU_MICROCODE_CBFS_LOC=0xfff0fdc0
            : CONFIG_CPU_MICROCODE_CBFS_LEN=0x7C00
No need to specify these, they are the defaults as per src/soc/intel/xeon_sp/Kconfig

https://review.coreboot.org/c/coreboot/+/38549/38/src/mainboard/ocp/tiogapas... 
File src/mainboard/ocp/tiogapass/Kconfig:

https://review.coreboot.org/c/coreboot/+/38549/38/src/mainboard/ocp/tiogapas... 
PS38, Line 25: select HAVE_IFD_BIN
             : 	select HAVE_ME_BIN
Remove these and coreboot will not try to add an IFD or ME image. Then we can also remove those fake binary files.

For real builds, the user can either enable these with a pre-made .config file or `make menuconfig and Chipset --> Add Intel descriptor.bin file (which will also allow an ME path to be specified)

https://review.coreboot.org/c/coreboot/+/38549/38/src/mainboard/ocp/tiogapas... 
File src/mainboard/ocp/tiogapass/Makefile.inc:

https://review.coreboot.org/c/coreboot/+/38549/38/src/mainboard/ocp/tiogapas... 
PS38, Line 18: romstage-y += boardid.c
remove (see comment in tiogapass_boardid.h)

https://review.coreboot.org/c/coreboot/+/38549/38/src/mainboard/ocp/tiogapas... 
PS38, Line 21: ramstage-y += boardid.c
same as previous comment

https://review.coreboot.org/c/coreboot/+/38549/38/src/mainboard/ocp/tiogapas... 
File src/mainboard/ocp/tiogapass/acpi/platform.asl:

PS38: 
Please indent this file uniformly using tabs.

https://review.coreboot.org/c/coreboot/+/38549/38/src/mainboard/ocp/tiogapas... 
File src/mainboard/ocp/tiogapass/acpi_tables.c:

https://review.coreboot.org/c/coreboot/+/38549/38/src/mainboard/ocp/tiogapas... 
PS38, Line 20: #include <soc/nvs.h>
nit: this is not needed

https://review.coreboot.org/c/coreboot/+/38549/38/src/mainboard/ocp/tiogapas... 
File src/mainboard/ocp/tiogapass/boardid.c:

PS38: 
This is currently unused, let's get rid of it for now and reintroduce it later if needed.

https://review.coreboot.org/c/coreboot/+/38549/38/src/mainboard/ocp/tiogapas... 
File src/mainboard/ocp/tiogapass/devicetree.cb:

PS38: 
Please indent this file uniformly using tabs.

https://review.coreboot.org/c/coreboot/+/38549/38/src/mainboard/ocp/tiogapas... 
File src/mainboard/ocp/tiogapass/romstage.c:

https://review.coreboot.org/c/coreboot/+/38549/38/src/mainboard/ocp/tiogapas... 
PS38, Line 18: #include "tiogapass_boardid.h"
remove (see comment in tiogapass_boardid.h)

https://review.coreboot.org/c/coreboot/+/38549/38/src/mainboard/ocp/tiogapas... 
PS38, Line 20: #include <fsp/soc_binding.h>
unnecessary #include

https://review.coreboot.org/c/coreboot/+/38549/38/src/mainboard/ocp/tiogapas... 
PS38, Line 21: #include <FspmUpd.h>
#include <soc/romstage.h>

(see comment below about mainboard_* function prototypes)

https://review.coreboot.org/c/coreboot/+/38549/38/src/mainboard/ocp/tiogapas... 
PS38, Line 26: void mainboard_config_gpios(FSPM_UPD * mupd);
             : void mainboard_config_iio(FSPM_UPD *mupd);
             : void mainboard_memory_init_params(FSPM_UPD *mupd);
I'm surprised that the compiler doesn't err out on these... mainboard_config_gpios() and mainboard_memory_init_params() are defined in <soc/romstage.h> (part of the previous patch)

https://review.coreboot.org/c/coreboot/+/38549/38/src/mainboard/ocp/tiogapas... 
PS38, Line 33: void mainboard_config_gpios(FSPM_UPD *mupd)
I think this is only called from mainboard_memory_init_params() in this file, so it can be static.

Also, there is a function declaration in the SoC's romstage.h file (in the previous patch) that should be removed.

https://review.coreboot.org/c/coreboot/+/38549/38/src/mainboard/ocp/tiogapas... 
PS38, Line 40: void mainboard_config_iio(FSPM_UPD *mupd)
this can be static since it's only called from mainboard_memory_init_params()

https://review.coreboot.org/c/coreboot/+/38549/38/src/mainboard/ocp/tiogapas... 
PS38, Line 45: sizeof(tp_iio_bifur_table)/sizeof(UPD_IIO_BIFURCATION_DATA_ENTRY);
ARRAY_SIZE(tp_iio_bifur_table)

https://review.coreboot.org/c/coreboot/+/38549/38/src/mainboard/ocp/tiogapas... 
PS38, Line 50: sizeof(tp_iio_pci_port_skt0)/sizeof(UPD_PCI_PORT_CONFIG);
ARRAY_SIZE(tp_iio_pci_port_skt0);

https://review.coreboot.org/c/coreboot/+/38549/38/src/mainboard/ocp/tiogapas... 
PS38, Line 55: sizeof(tp_pch_pci_port_skt0)/sizeof(UPD_PCH_PCIE_PORT);
ARRAY_SIZE(tp_pch_pci_port_skt0);

https://review.coreboot.org/c/coreboot/+/38549/38/src/mainboard/ocp/tiogapas... 
File src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h:

https://review.coreboot.org/c/coreboot/+/38549/38/src/mainboard/ocp/tiogapas... 
PS38, Line 24: *
nit: extra asterix

https://review.coreboot.org/c/coreboot/+/38549/38/src/mainboard/ocp/tiogapas... 
PS38, Line 26: *
nit: extra asterix

https://review.coreboot.org/c/coreboot/+/38549/38/src/mainboard/ocp/tiogapas... 
PS38, Line 1020: 
Needs an #endif

https://review.coreboot.org/c/coreboot/+/38549/38/src/mainboard/ocp/tiogapas... 
File src/mainboard/ocp/tiogapass/skxsp_tp_iio.h:

https://review.coreboot.org/c/coreboot/+/38549/38/src/mainboard/ocp/tiogapas... 
PS38, Line 24: /**
nit: Use /* (without the extra asterix)

https://review.coreboot.org/c/coreboot/+/38549/38/src/mainboard/ocp/tiogapas... 
PS38, Line 30: **/
Nit: Use */ (without the extra asterix)

https://review.coreboot.org/c/coreboot/+/38549/38/src/mainboard/ocp/tiogapas... 
PS38, Line 44: /**
Nit: extra asterix

https://review.coreboot.org/c/coreboot/+/38549/38/src/mainboard/ocp/tiogapas... 
PS38, Line 46: **/
Nit: extra asterix

https://review.coreboot.org/c/coreboot/+/38549/38/src/mainboard/ocp/tiogapas... 
PS38, Line 48:  
indent

https://review.coreboot.org/c/coreboot/+/38549/38/src/mainboard/ocp/tiogapas... 
PS38, Line 91: /**
Nit: extra asterix

https://review.coreboot.org/c/coreboot/+/38549/38/src/mainboard/ocp/tiogapas... 
PS38, Line 93: **/
Nit: extra asterix

https://review.coreboot.org/c/coreboot/+/38549/38/src/mainboard/ocp/tiogapas... 
File src/mainboard/ocp/tiogapass/tiogapass_boardid.h:

PS38: 
This seems copy+pasted from harcuvar. Let's get rid of it for now, though we may introduce it in a more proper form if we need logic to tell apart board revisions / vendors for whatever reason.

Change in coreboot[master]: mainboard/ocp: Add support for OCP platform TiogaPass

[Jonathan Zhang (Code Review)]

Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38549 )

Change subject: mainboard/ocp: Add support for OCP platform TiogaPass
......................................................................

Patch Set 38:

(29 comments)

Thanks!

https://review.coreboot.org/c/coreboot/+/38549/38/configs/config.ocp_tiogapa... 
File configs/config.ocp_tiogapass:

https://review.coreboot.org/c/coreboot/+/38549/38/configs/config.ocp_tiogapa... 
PS38, Line 3: CONFIG_CPU_MICROCODE_CBFS_LOC=0xfff0fdc0
            : CONFIG_CPU_MICROCODE_CBFS_LEN=0x7C00
> No need to specify these, they are the defaults as per src/soc/intel/xeon_sp/Kconfig

Done

https://review.coreboot.org/c/coreboot/+/38549/38/src/mainboard/ocp/tiogapas... 
File src/mainboard/ocp/tiogapass/Kconfig:

https://review.coreboot.org/c/coreboot/+/38549/38/src/mainboard/ocp/tiogapas... 
PS38, Line 25: select HAVE_IFD_BIN
             : 	select HAVE_ME_BIN
> Remove these and coreboot will not try to add an IFD or ME image. […]

Done

https://review.coreboot.org/c/coreboot/+/38549/38/src/mainboard/ocp/tiogapas... 
File src/mainboard/ocp/tiogapass/Makefile.inc:

https://review.coreboot.org/c/coreboot/+/38549/38/src/mainboard/ocp/tiogapas... 
PS38, Line 18: romstage-y += boardid.c
> remove (see comment in tiogapass_boardid. […]

Done

https://review.coreboot.org/c/coreboot/+/38549/38/src/mainboard/ocp/tiogapas... 
PS38, Line 21: ramstage-y += boardid.c
> same as previous comment

Done

https://review.coreboot.org/c/coreboot/+/38549/38/src/mainboard/ocp/tiogapas... 
File src/mainboard/ocp/tiogapass/acpi/platform.asl:

PS38:
> Please indent this file uniformly using tabs.

Done

PS38:
> Please indent this file uniformly using tabs.

Done

https://review.coreboot.org/c/coreboot/+/38549/38/src/mainboard/ocp/tiogapas... 
File src/mainboard/ocp/tiogapass/acpi_tables.c:

https://review.coreboot.org/c/coreboot/+/38549/38/src/mainboard/ocp/tiogapas... 
PS38, Line 20: #include <soc/nvs.h>
> nit: this is not needed

Done

https://review.coreboot.org/c/coreboot/+/38549/38/src/mainboard/ocp/tiogapas... 
File src/mainboard/ocp/tiogapass/boardid.c:

PS38:
> This is currently unused, let's get rid of it for now and reintroduce it later if needed.

Done

https://review.coreboot.org/c/coreboot/+/38549/38/src/mainboard/ocp/tiogapas... 
File src/mainboard/ocp/tiogapass/devicetree.cb:

PS38:
> Please indent this file uniformly using tabs.

Done

https://review.coreboot.org/c/coreboot/+/38549/38/src/mainboard/ocp/tiogapas... 
File src/mainboard/ocp/tiogapass/romstage.c:

https://review.coreboot.org/c/coreboot/+/38549/38/src/mainboard/ocp/tiogapas... 
PS38, Line 18: #include "tiogapass_boardid.h"
> remove (see comment in tiogapass_boardid. […]

Done

https://review.coreboot.org/c/coreboot/+/38549/38/src/mainboard/ocp/tiogapas... 
PS38, Line 20: #include <fsp/soc_binding.h>
> unnecessary #include

Done

https://review.coreboot.org/c/coreboot/+/38549/38/src/mainboard/ocp/tiogapas... 
PS38, Line 21: #include <FspmUpd.h>
> #include <soc/romstage.h> […]

Done

https://review.coreboot.org/c/coreboot/+/38549/38/src/mainboard/ocp/tiogapas... 
PS38, Line 26: void mainboard_config_gpios(FSPM_UPD * mupd);
             : void mainboard_config_iio(FSPM_UPD *mupd);
             : void mainboard_memory_init_params(FSPM_UPD *mupd);
> I'm surprised that the compiler doesn't err out on these... […]

Done

https://review.coreboot.org/c/coreboot/+/38549/38/src/mainboard/ocp/tiogapas... 
PS38, Line 33: void mainboard_config_gpios(FSPM_UPD *mupd)
> I think this is only called from mainboard_memory_init_params() in this file, so it can be static. […]

Done

https://review.coreboot.org/c/coreboot/+/38549/38/src/mainboard/ocp/tiogapas... 
PS38, Line 40: void mainboard_config_iio(FSPM_UPD *mupd)
> this can be static since it's only called from mainboard_memory_init_params()

Done

https://review.coreboot.org/c/coreboot/+/38549/38/src/mainboard/ocp/tiogapas... 
PS38, Line 45: sizeof(tp_iio_bifur_table)/sizeof(UPD_IIO_BIFURCATION_DATA_ENTRY);
> ARRAY_SIZE(tp_iio_bifur_table)

Done

https://review.coreboot.org/c/coreboot/+/38549/38/src/mainboard/ocp/tiogapas... 
PS38, Line 50: sizeof(tp_iio_pci_port_skt0)/sizeof(UPD_PCI_PORT_CONFIG);
> ARRAY_SIZE(tp_iio_pci_port_skt0);

Done

https://review.coreboot.org/c/coreboot/+/38549/38/src/mainboard/ocp/tiogapas... 
PS38, Line 55: sizeof(tp_pch_pci_port_skt0)/sizeof(UPD_PCH_PCIE_PORT);
> ARRAY_SIZE(tp_pch_pci_port_skt0);

Done

https://review.coreboot.org/c/coreboot/+/38549/38/src/mainboard/ocp/tiogapas... 
File src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h:

https://review.coreboot.org/c/coreboot/+/38549/38/src/mainboard/ocp/tiogapas... 
PS38, Line 24: *
> nit: extra asterix

Done

https://review.coreboot.org/c/coreboot/+/38549/38/src/mainboard/ocp/tiogapas... 
PS38, Line 26: *
> nit: extra asterix

Done

https://review.coreboot.org/c/coreboot/+/38549/38/src/mainboard/ocp/tiogapas... 
PS38, Line 1020:
> Needs an #endif

Done

https://review.coreboot.org/c/coreboot/+/38549/38/src/mainboard/ocp/tiogapas... 
File src/mainboard/ocp/tiogapass/skxsp_tp_iio.h:

https://review.coreboot.org/c/coreboot/+/38549/38/src/mainboard/ocp/tiogapas... 
PS38, Line 24: /**
> nit: Use /* (without the extra asterix)

Done

https://review.coreboot.org/c/coreboot/+/38549/38/src/mainboard/ocp/tiogapas... 
PS38, Line 30: **/
> Nit: Use */ (without the extra asterix)

Done

https://review.coreboot.org/c/coreboot/+/38549/38/src/mainboard/ocp/tiogapas... 
PS38, Line 44: /**
> Nit: extra asterix

Done

https://review.coreboot.org/c/coreboot/+/38549/38/src/mainboard/ocp/tiogapas... 
PS38, Line 46: **/
> Nit: extra asterix

Done

https://review.coreboot.org/c/coreboot/+/38549/38/src/mainboard/ocp/tiogapas... 
PS38, Line 48:
> indent

Done

https://review.coreboot.org/c/coreboot/+/38549/38/src/mainboard/ocp/tiogapas... 
PS38, Line 91: /**
> Nit: extra asterix

Done

https://review.coreboot.org/c/coreboot/+/38549/38/src/mainboard/ocp/tiogapas... 
PS38, Line 93: **/
> Nit: extra asterix

Done

https://review.coreboot.org/c/coreboot/+/38549/38/src/mainboard/ocp/tiogapas... 
File src/mainboard/ocp/tiogapass/tiogapass_boardid.h:

PS38:
> This seems copy+pasted from harcuvar. […]

Done

Change in coreboot[master]: mainboard/ocp: Add support for OCP platform TiogaPass

[Jonathan Zhang (Code Review)]

Hello HAOUAS Elyes, Johnny Lin, David Hendricks, build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38549

to look at the new patch set (#39).

Change subject: mainboard/ocp: Add support for OCP platform TiogaPass
......................................................................

mainboard/ocp: Add support for OCP platform TiogaPass

OCP platform Tiogapass is a 2-socket server platform, which
is based on a chipset including Intel Skylake-SP processors
and a Lewisburg PCH. Skylake-SP is a processor in Intel Xeon
Scalable Processor family.

Following ACPI tables are added:
DSDT/SSDT, MADT, FACP, FACS, HPET, MCFG, SLIT, SRAT, DMAR

This patchset is tested on a Tiogapass board. It booted with
Linux kernel 4.16.0; lscpu command shows all 72 cpus (2 sockets,
18 cores, 2 thread per core); ssh command shows
networking is up from Mellanox ConnectX-4 PCIe NIC card.

Towards successful gerrit buildbot build, note that:
* microcode is in coreboot intel-microcode submodule repo.
* IFD binary is included in this patch.
* Dummy ME binary is used, as it may take long time for Intel
ME binary to be available in public domain.
* Fake FSP binary is used, as at this moment the SKX-SP
FSP binary is not going to be available in public domain.

Known issues (Not intend to address in this initial support for
Xeon-SP processors):
* c6 state is not supported.
* dsdt table is not fully populated, such as processor/socket
devices, some PCIe devices.
* SMM handlers are not added.

Following are some command execution with CentOS booted from
local SATA disk:
[root@localhost ~]# lscpu
Architecture:          x86_64
CPU op-mode(s):        32-bit, 64-bit
Byte Order:            Little Endian
CPU(s):                72
On-line CPU(s) list:   0-71
Thread(s) per core:    2
Core(s) per socket:    18
Socket(s):             2
NUMA node(s):          2
Vendor ID:             GenuineIntel
CPU family:            6
Model:                 85
Model name:            Intel(R) Xeon(R) Gold 6139 CPU @ 2.30GHz
Stepping:              4
CPU MHz:               140.415
BogoMIPS:              4626.46
Virtualization:        VT-x
L1d cache:             32K
L1i cache:             32K
L2 cache:              1024K
L3 cache:              25344K
NUMA node0 CPU(s):     0-17,36-53
NUMA node1 CPU(s):     18-35,54-71
[root@localhost ~]# ifconfig
eth0: flags=4163<UP,BROADCAST,RUNNING,MULTICAST>  mtu 1500
        inet 172.23.68.190  netmask 255.255.0.0  broadcast 172.23.255.255
        inet6 2620:10d:c082:9063:268a:7ff:fe57:5af0  prefixlen 64 //cut
        inet6 fe80::268a:7ff:fe57:5af0  prefixlen 64  scopeid 0x20<link>
        inet6 2620:10d:c082:9063::5d2  prefixlen 128  scopeid 0x0<global>
        ether 24:8a:07:57:5a:f0  txqueuelen 1000  (Ethernet)
        RX packets 84249  bytes 6371591 (6.0 MiB)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 8418  bytes 748781 (731.2 KiB)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0

lo: flags=73<UP,LOOPBACK,RUNNING>  mtu 65536
        inet 127.0.0.1  netmask 255.0.0.0
        inet6 ::1  prefixlen 128  scopeid 0x10<host>
        loop  txqueuelen 1000  (Local Loopback)
        RX packets 613  bytes 63906 (62.4 KiB)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 613  bytes 63906 (62.4 KiB)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0
[root@localhost ~]# cbmem
36 entries total:

// Lines were cut to avoid checkpatch.pl warnings

Total Time: 96,243,882,140,175,829

Signed-off-by: Jonathan Zhang 
Signed-off-by: Reddy Chagam 
Tested-by: [e-mail]
Change-Id: I29868f03037d1887b90dfb19d15aee83c456edce
---
A configs/config.ocp_tiogapass
A src/mainboard/ocp/Kconfig
A src/mainboard/ocp/Kconfig.name
A src/mainboard/ocp/tiogapass/Kconfig
A src/mainboard/ocp/tiogapass/Kconfig.name
A src/mainboard/ocp/tiogapass/Makefile.inc
A src/mainboard/ocp/tiogapass/acpi/platform.asl
A src/mainboard/ocp/tiogapass/acpi_tables.c
A src/mainboard/ocp/tiogapass/blobs/ifd.bin
A src/mainboard/ocp/tiogapass/board.fmd
A src/mainboard/ocp/tiogapass/board_info.txt
A src/mainboard/ocp/tiogapass/boardid.c
A src/mainboard/ocp/tiogapass/devicetree.cb
A src/mainboard/ocp/tiogapass/dsdt.asl
A src/mainboard/ocp/tiogapass/fadt.c
A src/mainboard/ocp/tiogapass/ramstage.c
A src/mainboard/ocp/tiogapass/romstage.c
A src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h
A src/mainboard/ocp/tiogapass/skxsp_tp_iio.h
A src/mainboard/ocp/tiogapass/tiogapass_boardid.h
20 files changed, 1,931 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/38549/39

Change in coreboot[master]: mainboard/ocp: Add support for OCP platform TiogaPass

[Jonathan Zhang (Code Review)]

Hello HAOUAS Elyes, Johnny Lin, David Hendricks, build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38549

to look at the new patch set (#40).

Change subject: mainboard/ocp: Add support for OCP platform TiogaPass
......................................................................

mainboard/ocp: Add support for OCP platform TiogaPass

OCP platform Tiogapass is a 2-socket server platform, which
is based on a chipset including Intel Skylake-SP processors
and a Lewisburg PCH. Skylake-SP is a processor in Intel Xeon
Scalable Processor family.

Following ACPI tables are added:
DSDT/SSDT, MADT, FACP, FACS, HPET, MCFG, SLIT, SRAT, DMAR

This patchset is tested on a Tiogapass board. It booted with
Linux kernel 4.16.0; lscpu command shows all 72 cpus (2 sockets,
18 cores, 2 thread per core); ssh command shows
networking is up from Mellanox ConnectX-4 PCIe NIC card.

Towards successful gerrit buildbot build, note that:
* microcode is in coreboot intel-microcode submodule repo.
* IFD binary is included in this patch.
* Dummy ME binary is used, as it may take long time for Intel
ME binary to be available in public domain.
* Fake FSP binary is used, as at this moment the SKX-SP
FSP binary is not going to be available in public domain.

Known issues (Not intend to address in this initial support for
Xeon-SP processors):
* c6 state is not supported.
* dsdt table is not fully populated, such as processor/socket
devices, some PCIe devices.
* SMM handlers are not added.

Following are some command execution with CentOS booted from
local SATA disk:
[root@localhost ~]# lscpu
Architecture:          x86_64
CPU op-mode(s):        32-bit, 64-bit
Byte Order:            Little Endian
CPU(s):                72
On-line CPU(s) list:   0-71
Thread(s) per core:    2
Core(s) per socket:    18
Socket(s):             2
NUMA node(s):          2
Vendor ID:             GenuineIntel
CPU family:            6
Model:                 85
Model name:            Intel(R) Xeon(R) Gold 6139 CPU @ 2.30GHz
Stepping:              4
CPU MHz:               140.415
BogoMIPS:              4626.46
Virtualization:        VT-x
L1d cache:             32K
L1i cache:             32K
L2 cache:              1024K
L3 cache:              25344K
NUMA node0 CPU(s):     0-17,36-53
NUMA node1 CPU(s):     18-35,54-71
[root@localhost ~]# ifconfig
eth0: flags=4163<UP,BROADCAST,RUNNING,MULTICAST>  mtu 1500
        inet 172.23.68.190  netmask 255.255.0.0  broadcast 172.23.255.255
        inet6 2620:10d:c082:9063:268a:7ff:fe57:5af0  prefixlen 64 //cut
        inet6 fe80::268a:7ff:fe57:5af0  prefixlen 64  scopeid 0x20<link>
        inet6 2620:10d:c082:9063::5d2  prefixlen 128  scopeid 0x0<global>
        ether 24:8a:07:57:5a:f0  txqueuelen 1000  (Ethernet)
        RX packets 84249  bytes 6371591 (6.0 MiB)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 8418  bytes 748781 (731.2 KiB)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0

lo: flags=73<UP,LOOPBACK,RUNNING>  mtu 65536
        inet 127.0.0.1  netmask 255.0.0.0
        inet6 ::1  prefixlen 128  scopeid 0x10<host>
        loop  txqueuelen 1000  (Local Loopback)
        RX packets 613  bytes 63906 (62.4 KiB)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 613  bytes 63906 (62.4 KiB)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0
[root@localhost ~]# cbmem
36 entries total:

// Lines were cut to avoid checkpatch.pl warnings

Total Time: 96,243,882,140,175,829

Signed-off-by: Jonathan Zhang 
Signed-off-by: Reddy Chagam 
Tested-by: [e-mail]
Change-Id: I29868f03037d1887b90dfb19d15aee83c456edce
---
A configs/config.ocp_tiogapass
A src/mainboard/ocp/Kconfig
A src/mainboard/ocp/Kconfig.name
A src/mainboard/ocp/tiogapass/Kconfig
A src/mainboard/ocp/tiogapass/Kconfig.name
A src/mainboard/ocp/tiogapass/Makefile.inc
A src/mainboard/ocp/tiogapass/acpi/platform.asl
A src/mainboard/ocp/tiogapass/acpi_tables.c
A src/mainboard/ocp/tiogapass/blobs/ifd.bin
A src/mainboard/ocp/tiogapass/board.fmd
A src/mainboard/ocp/tiogapass/board_info.txt
A src/mainboard/ocp/tiogapass/boardid.c
A src/mainboard/ocp/tiogapass/devicetree.cb
A src/mainboard/ocp/tiogapass/dsdt.asl
A src/mainboard/ocp/tiogapass/fadt.c
A src/mainboard/ocp/tiogapass/ramstage.c
A src/mainboard/ocp/tiogapass/romstage.c
A src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h
A src/mainboard/ocp/tiogapass/skxsp_tp_iio.h
A src/mainboard/ocp/tiogapass/tiogapass_boardid.h
20 files changed, 1,930 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/38549/40

Change in coreboot[master]: mainboard/ocp: Add support for OCP platform TiogaPass

[Jonathan Zhang (Code Review)]

Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38549 )

Change subject: mainboard/ocp: Add support for OCP platform TiogaPass
......................................................................

Patch Set 40:

(1 comment)

https://review.coreboot.org/c/coreboot/+/38549/24/src/mainboard/ocp/tiogapas... 
File src/mainboard/ocp/tiogapass/board.fmd:

https://review.coreboot.org/c/coreboot/+/38549/24/src/mainboard/ocp/tiogapas... 
PS24, Line 8: MISC_RW
> I believe this item is not resolved. […]

Cleaned up. Will need to add RO_VPD and RW_VPD regions in follow-up patches.

Change in coreboot[master]: mainboard/ocp: Add support for OCP platform TiogaPass

[David Hendricks (Code Review)]

David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38549 )

Change subject: mainboard/ocp: Add support for OCP platform TiogaPass
......................................................................

Patch Set 43: Code-Review-1

(3 comments)

Almost there - Looks like you may have forgotten to `git rm` the unused board ID files.

https://review.coreboot.org/c/coreboot/+/38549/43/src/mainboard/ocp/tiogapas... 
File src/mainboard/ocp/tiogapass/boardid.c:

PS43: 
remove this unused file

https://review.coreboot.org/c/coreboot/+/38549/43/src/mainboard/ocp/tiogapas... 
File src/mainboard/ocp/tiogapass/devicetree.cb:

https://review.coreboot.org/c/coreboot/+/38549/43/src/mainboard/ocp/tiogapas... 
PS43, Line 29:   # configure device interrupt routing
missed one

https://review.coreboot.org/c/coreboot/+/38549/43/src/mainboard/ocp/tiogapas... 
File src/mainboard/ocp/tiogapass/tiogapass_boardid.h:

PS43: 
remove this unused file

Change in coreboot[master]: mainboard/ocp: Add support for OCP platform TiogaPass

[David Hendricks (Code Review)]

David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38549 )

Change subject: mainboard/ocp: Add support for OCP platform TiogaPass
......................................................................

Patch Set 43:

oh, and we should move ifd.bin to the blobs repo

Change in coreboot[master]: mainboard/ocp: Add support for OCP platform TiogaPass

[David Hendricks (Code Review)]

David Hendricks has uploaded a new patch set (#44) to the change originally created by Jonathan Zhang. ( https://review.coreboot.org/c/coreboot/+/38549 )

Change subject: mainboard/ocp: Add support for OCP platform TiogaPass
......................................................................

mainboard/ocp: Add support for OCP platform TiogaPass

OCP platform Tiogapass is a 2-socket server platform, which
is based on a chipset including Intel Skylake-SP processors
and a Lewisburg PCH. Skylake-SP is a processor in Intel Xeon
Scalable Processor family.

Following ACPI tables are added:
DSDT/SSDT, MADT, FACP, FACS, HPET, MCFG, SLIT, SRAT, DMAR

This patchset is tested on a Tiogapass board. It booted with
Linux kernel 4.16.0; lscpu command shows all 72 cpus (2 sockets,
18 cores, 2 thread per core); ssh command shows
networking is up from Mellanox ConnectX-4 PCIe NIC card.

Towards successful gerrit buildbot build, note that:
* microcode is in coreboot intel-microcode submodule repo.
* IFD binary is included in this patch.
* Dummy ME binary is used, as it may take long time for Intel
ME binary to be available in public domain.
* Fake FSP binary is used, as at this moment the SKX-SP
FSP binary is not going to be available in public domain.

Known issues (Not intend to address in this initial support for
Xeon-SP processors):
* c6 state is not supported.
* dsdt table is not fully populated, such as processor/socket
devices, some PCIe devices.
* SMM handlers are not added.

Following are some command execution with CentOS booted from
local SATA disk:
[root@localhost ~]# lscpu
Architecture:          x86_64
CPU op-mode(s):        32-bit, 64-bit
Byte Order:            Little Endian
CPU(s):                72
On-line CPU(s) list:   0-71
Thread(s) per core:    2
Core(s) per socket:    18
Socket(s):             2
NUMA node(s):          2
Vendor ID:             GenuineIntel
CPU family:            6
Model:                 85
Model name:            Intel(R) Xeon(R) Gold 6139 CPU @ 2.30GHz
Stepping:              4
CPU MHz:               140.415
BogoMIPS:              4626.46
Virtualization:        VT-x
L1d cache:             32K
L1i cache:             32K
L2 cache:              1024K
L3 cache:              25344K
NUMA node0 CPU(s):     0-17,36-53
NUMA node1 CPU(s):     18-35,54-71
[root@localhost ~]# ifconfig
eth0: flags=4163<UP,BROADCAST,RUNNING,MULTICAST>  mtu 1500
        inet 172.23.68.190  netmask 255.255.0.0  broadcast 172.23.255.255
        inet6 2620:10d:c082:9063:268a:7ff:fe57:5af0  prefixlen 64 //cut
        inet6 fe80::268a:7ff:fe57:5af0  prefixlen 64  scopeid 0x20<link>
        inet6 2620:10d:c082:9063::5d2  prefixlen 128  scopeid 0x0<global>
        ether 24:8a:07:57:5a:f0  txqueuelen 1000  (Ethernet)
        RX packets 84249  bytes 6371591 (6.0 MiB)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 8418  bytes 748781 (731.2 KiB)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0

lo: flags=73<UP,LOOPBACK,RUNNING>  mtu 65536
        inet 127.0.0.1  netmask 255.0.0.0
        inet6 ::1  prefixlen 128  scopeid 0x10<host>
        loop  txqueuelen 1000  (Local Loopback)
        RX packets 613  bytes 63906 (62.4 KiB)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 613  bytes 63906 (62.4 KiB)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0
[root@localhost ~]# cbmem
36 entries total:

// Lines were cut to avoid checkpatch.pl warnings

Total Time: 96,243,882,140,175,829

Signed-off-by: Jonathan Zhang 
Signed-off-by: Reddy Chagam 
Tested-by: [e-mail]
Change-Id: I29868f03037d1887b90dfb19d15aee83c456edce
---
A configs/config.ocp_tiogapass
A src/mainboard/ocp/Kconfig
A src/mainboard/ocp/Kconfig.name
A src/mainboard/ocp/tiogapass/Kconfig
A src/mainboard/ocp/tiogapass/Kconfig.name
A src/mainboard/ocp/tiogapass/Makefile.inc
A src/mainboard/ocp/tiogapass/acpi/platform.asl
A src/mainboard/ocp/tiogapass/acpi_tables.c
A src/mainboard/ocp/tiogapass/blobs/ifd.bin
A src/mainboard/ocp/tiogapass/board.fmd
A src/mainboard/ocp/tiogapass/board_info.txt
A src/mainboard/ocp/tiogapass/boardid.c
A src/mainboard/ocp/tiogapass/devicetree.cb
A src/mainboard/ocp/tiogapass/dsdt.asl
A src/mainboard/ocp/tiogapass/fadt.c
A src/mainboard/ocp/tiogapass/ramstage.c
A src/mainboard/ocp/tiogapass/romstage.c
A src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h
A src/mainboard/ocp/tiogapass/skxsp_tp_iio.h
A src/mainboard/ocp/tiogapass/tiogapass_boardid.h
20 files changed, 1,930 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/38549/44

Change in coreboot[master]: mainboard/ocp: Add support for OCP platform TiogaPass

[Jonathan Zhang (Code Review)]

Hello build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth, Johnny Lin, David Hendricks,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38549

to look at the new patch set (#45).

Change subject: mainboard/ocp: Add support for OCP platform TiogaPass
......................................................................

mainboard/ocp: Add support for OCP platform TiogaPass

OCP platform Tiogapass is a 2-socket server platform, which
is based on a chipset including Intel Skylake-SP processors
and a Lewisburg PCH. Skylake-SP is a processor in Intel Xeon
Scalable Processor family.

Following ACPI tables are added:
DSDT/SSDT, MADT, FACP, FACS, HPET, MCFG, SLIT, SRAT, DMAR

This patchset is tested on a Tiogapass board. It booted with
Linux kernel 4.16.0; lscpu command shows all 72 cpus (2 sockets,
18 cores, 2 thread per core); ssh command shows
networking is up from Mellanox ConnectX-4 PCIe NIC card.

Towards successful gerrit buildbot build, note that:
* microcode is in coreboot intel-microcode submodule repo.
* IFD binary is included in this patch.
* Dummy ME binary is used, as it may take long time for Intel
ME binary to be available in public domain.
* Fake FSP binary is used, as at this moment the SKX-SP
FSP binary is not going to be available in public domain.

Known issues (Not intend to address in this initial support for
Xeon-SP processors):
* c6 state is not supported.
* dsdt table is not fully populated, such as processor/socket
devices, some PCIe devices.
* SMM handlers are not added.

Following are some command execution with CentOS booted from
local SATA disk:
[root@localhost ~]# lscpu
Architecture:          x86_64
CPU op-mode(s):        32-bit, 64-bit
Byte Order:            Little Endian
CPU(s):                72
On-line CPU(s) list:   0-71
Thread(s) per core:    2
Core(s) per socket:    18
Socket(s):             2
NUMA node(s):          2
Vendor ID:             GenuineIntel
CPU family:            6
Model:                 85
Model name:            Intel(R) Xeon(R) Gold 6139 CPU @ 2.30GHz
Stepping:              4
CPU MHz:               140.415
BogoMIPS:              4626.46
Virtualization:        VT-x
L1d cache:             32K
L1i cache:             32K
L2 cache:              1024K
L3 cache:              25344K
NUMA node0 CPU(s):     0-17,36-53
NUMA node1 CPU(s):     18-35,54-71
[root@localhost ~]# ifconfig
eth0: flags=4163<UP,BROADCAST,RUNNING,MULTICAST>  mtu 1500
        inet 172.23.68.190  netmask 255.255.0.0  broadcast 172.23.255.255
        inet6 2620:10d:c082:9063:268a:7ff:fe57:5af0  prefixlen 64 //cut
        inet6 fe80::268a:7ff:fe57:5af0  prefixlen 64  scopeid 0x20<link>
        inet6 2620:10d:c082:9063::5d2  prefixlen 128  scopeid 0x0<global>
        ether 24:8a:07:57:5a:f0  txqueuelen 1000  (Ethernet)
        RX packets 84249  bytes 6371591 (6.0 MiB)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 8418  bytes 748781 (731.2 KiB)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0

lo: flags=73<UP,LOOPBACK,RUNNING>  mtu 65536
        inet 127.0.0.1  netmask 255.0.0.0
        inet6 ::1  prefixlen 128  scopeid 0x10<host>
        loop  txqueuelen 1000  (Local Loopback)
        RX packets 613  bytes 63906 (62.4 KiB)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 613  bytes 63906 (62.4 KiB)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0
[root@localhost ~]# cbmem
36 entries total:

// Lines were cut to avoid checkpatch.pl warnings

Total Time: 96,243,882,140,175,829

Signed-off-by: Jonathan Zhang 
Signed-off-by: Reddy Chagam 
Tested-by: [e-mail]
Change-Id: I29868f03037d1887b90dfb19d15aee83c456edce
---
A configs/config.ocp_tiogapass
A src/mainboard/ocp/Kconfig
A src/mainboard/ocp/Kconfig.name
A src/mainboard/ocp/tiogapass/Kconfig
A src/mainboard/ocp/tiogapass/Kconfig.name
A src/mainboard/ocp/tiogapass/Makefile.inc
A src/mainboard/ocp/tiogapass/acpi/platform.asl
A src/mainboard/ocp/tiogapass/acpi_tables.c
A src/mainboard/ocp/tiogapass/board.fmd
A src/mainboard/ocp/tiogapass/board_info.txt
A src/mainboard/ocp/tiogapass/devicetree.cb
A src/mainboard/ocp/tiogapass/dsdt.asl
A src/mainboard/ocp/tiogapass/fadt.c
A src/mainboard/ocp/tiogapass/ramstage.c
A src/mainboard/ocp/tiogapass/romstage.c
A src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h
A src/mainboard/ocp/tiogapass/skxsp_tp_iio.h
17 files changed, 1,874 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/38549/45

Change in coreboot[master]: mainboard/ocp: Add support for OCP platform TiogaPass

[Jonathan Zhang (Code Review)]

Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38549 )

Change subject: mainboard/ocp: Add support for OCP platform TiogaPass
......................................................................

Patch Set 45:

(2 comments)

https://review.coreboot.org/c/coreboot/+/38549/43/src/mainboard/ocp/tiogapas... 
File src/mainboard/ocp/tiogapass/boardid.c:

PS43:
> remove this unused file

Done

https://review.coreboot.org/c/coreboot/+/38549/43/src/mainboard/ocp/tiogapas... 
File src/mainboard/ocp/tiogapass/devicetree.cb:

https://review.coreboot.org/c/coreboot/+/38549/43/src/mainboard/ocp/tiogapas... 
PS43, Line 29:   # configure device interrupt routing
> missed one

Done

Change in coreboot[master]: mainboard/ocp: Add support for OCP platform TiogaPass

[Jonathan Zhang (Code Review)]

Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38549 )

Change subject: mainboard/ocp: Add support for OCP platform TiogaPass
......................................................................

Patch Set 45:

(1 comment)

https://review.coreboot.org/c/coreboot/+/38549/43/src/mainboard/ocp/tiogapas... 
File src/mainboard/ocp/tiogapass/tiogapass_boardid.h:

PS43:
> remove this unused file

Done

Change in coreboot[master]: mainboard/ocp: Add support for OCP platform TiogaPass

[David Hendricks (Code Review)]

David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38549 )

Change subject: mainboard/ocp: Add support for OCP platform TiogaPass
......................................................................

Patch Set 45: Code-Review+2

Same as the previous patch

Change in coreboot[master]: mainboard/ocp: Add support for OCP platform TiogaPass

[Jonathan Zhang (Code Review)]

Hello build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth, Johnny Lin, David Hendricks,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38549

to look at the new patch set (#46).

Change subject: mainboard/ocp: Add support for OCP platform TiogaPass
......................................................................

mainboard/ocp: Add support for OCP platform TiogaPass

OCP platform Tiogapass is a 2-socket server platform, which
is based on a chipset including Intel Skylake-SP processors
and a Lewisburg PCH. Skylake-SP is a processor in Intel Xeon
Scalable Processor family.

Following ACPI tables are added:
DSDT/SSDT, MADT, FACP, FACS, HPET, MCFG, SLIT, SRAT, DMAR

This patchset is tested on a Tiogapass board. It booted with
Linux kernel 4.16.0; lscpu command shows all 72 cpus (2 sockets,
18 cores, 2 thread per core); ssh command shows
networking is up from Mellanox ConnectX-4 PCIe NIC card.

Towards successful gerrit buildbot build, note that:
* microcode is in coreboot intel-microcode submodule repo.
* IFD binary is included in this patch.
* Dummy ME binary is used, as it may take long time for Intel
ME binary to be available in public domain.
* Fake FSP binary is used, as at this moment the SKX-SP
FSP binary is not going to be available in public domain.

Known issues (Not intend to address in this initial support for
Xeon-SP processors):
* c6 state is not supported.
* dsdt table is not fully populated, such as processor/socket
devices, some PCIe devices.
* SMM handlers are not added.

Following are some command execution with CentOS booted from
local SATA disk:
[root@localhost ~]# lscpu
Architecture:          x86_64
CPU op-mode(s):        32-bit, 64-bit
Byte Order:            Little Endian
CPU(s):                72
On-line CPU(s) list:   0-71
Thread(s) per core:    2
Core(s) per socket:    18
Socket(s):             2
NUMA node(s):          2
Vendor ID:             GenuineIntel
CPU family:            6
Model:                 85
Model name:            Intel(R) Xeon(R) Gold 6139 CPU @ 2.30GHz
Stepping:              4
CPU MHz:               140.415
BogoMIPS:              4626.46
Virtualization:        VT-x
L1d cache:             32K
L1i cache:             32K
L2 cache:              1024K
L3 cache:              25344K
NUMA node0 CPU(s):     0-17,36-53
NUMA node1 CPU(s):     18-35,54-71
[root@localhost ~]# ifconfig
eth0: flags=4163<UP,BROADCAST,RUNNING,MULTICAST>  mtu 1500
        inet 172.23.68.190  netmask 255.255.0.0  broadcast 172.23.255.255
        inet6 2620:10d:c082:9063:268a:7ff:fe57:5af0  prefixlen 64 //cut
        inet6 fe80::268a:7ff:fe57:5af0  prefixlen 64  scopeid 0x20<link>
        inet6 2620:10d:c082:9063::5d2  prefixlen 128  scopeid 0x0<global>
        ether 24:8a:07:57:5a:f0  txqueuelen 1000  (Ethernet)
        RX packets 84249  bytes 6371591 (6.0 MiB)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 8418  bytes 748781 (731.2 KiB)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0

lo: flags=73<UP,LOOPBACK,RUNNING>  mtu 65536
        inet 127.0.0.1  netmask 255.0.0.0
        inet6 ::1  prefixlen 128  scopeid 0x10<host>
        loop  txqueuelen 1000  (Local Loopback)
        RX packets 613  bytes 63906 (62.4 KiB)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 613  bytes 63906 (62.4 KiB)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0
[root@localhost ~]# cbmem
36 entries total:

// Lines were cut to avoid checkpatch.pl warnings

Total Time: 96,243,882,140,175,829

Signed-off-by: Jonathan Zhang 
Signed-off-by: Reddy Chagam 
Tested-by: [e-mail]
Change-Id: I29868f03037d1887b90dfb19d15aee83c456edce
---
A configs/config.ocp_tiogapass
A src/mainboard/ocp/Kconfig
A src/mainboard/ocp/Kconfig.name
A src/mainboard/ocp/tiogapass/Kconfig
A src/mainboard/ocp/tiogapass/Kconfig.name
A src/mainboard/ocp/tiogapass/Makefile.inc
A src/mainboard/ocp/tiogapass/acpi/platform.asl
A src/mainboard/ocp/tiogapass/acpi_tables.c
A src/mainboard/ocp/tiogapass/board.fmd
A src/mainboard/ocp/tiogapass/board_info.txt
A src/mainboard/ocp/tiogapass/devicetree.cb
A src/mainboard/ocp/tiogapass/dsdt.asl
A src/mainboard/ocp/tiogapass/fadt.c
A src/mainboard/ocp/tiogapass/ramstage.c
A src/mainboard/ocp/tiogapass/romstage.c
A src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h
A src/mainboard/ocp/tiogapass/skxsp_tp_iio.h
17 files changed, 1,874 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/38549/46

Change in coreboot[master]: mainboard/ocp: Add support for OCP platform TiogaPass

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38549 )

Change subject: mainboard/ocp: Add support for OCP platform TiogaPass
......................................................................

mainboard/ocp: Add support for OCP platform TiogaPass

OCP platform Tiogapass is a 2-socket server platform, which
is based on a chipset including Intel Skylake-SP processors
and a Lewisburg PCH. Skylake-SP is a processor in Intel Xeon
Scalable Processor family.

Following ACPI tables are added:
DSDT/SSDT, MADT, FACP, FACS, HPET, MCFG, SLIT, SRAT, DMAR

This patchset is tested on a Tiogapass board. It booted with
Linux kernel 4.16.0; lscpu command shows all 72 cpus (2 sockets,
18 cores, 2 thread per core); ssh command shows
networking is up from Mellanox ConnectX-4 PCIe NIC card.

Towards successful gerrit buildbot build, note that:
* microcode is in coreboot intel-microcode submodule repo.
* IFD binary is included in this patch.
* Dummy ME binary is used, as it may take long time for Intel
ME binary to be available in public domain.
* Fake FSP binary is used, as at this moment the SKX-SP
FSP binary is not going to be available in public domain.

Known issues (Not intend to address in this initial support for
Xeon-SP processors):
* c6 state is not supported.
* dsdt table is not fully populated, such as processor/socket
devices, some PCIe devices.
* SMM handlers are not added.

Following are some command execution with CentOS booted from
local SATA disk:
[root@localhost ~]# lscpu
Architecture:          x86_64
CPU op-mode(s):        32-bit, 64-bit
Byte Order:            Little Endian
CPU(s):                72
On-line CPU(s) list:   0-71
Thread(s) per core:    2
Core(s) per socket:    18
Socket(s):             2
NUMA node(s):          2
Vendor ID:             GenuineIntel
CPU family:            6
Model:                 85
Model name:            Intel(R) Xeon(R) Gold 6139 CPU @ 2.30GHz
Stepping:              4
CPU MHz:               140.415
BogoMIPS:              4626.46
Virtualization:        VT-x
L1d cache:             32K
L1i cache:             32K
L2 cache:              1024K
L3 cache:              25344K
NUMA node0 CPU(s):     0-17,36-53
NUMA node1 CPU(s):     18-35,54-71
[root@localhost ~]# ifconfig
eth0: flags=4163<UP,BROADCAST,RUNNING,MULTICAST>  mtu 1500
        inet 172.23.68.190  netmask 255.255.0.0  broadcast 172.23.255.255
        inet6 2620:10d:c082:9063:268a:7ff:fe57:5af0  prefixlen 64 //cut
        inet6 fe80::268a:7ff:fe57:5af0  prefixlen 64  scopeid 0x20<link>
        inet6 2620:10d:c082:9063::5d2  prefixlen 128  scopeid 0x0<global>
        ether 24:8a:07:57:5a:f0  txqueuelen 1000  (Ethernet)
        RX packets 84249  bytes 6371591 (6.0 MiB)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 8418  bytes 748781 (731.2 KiB)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0

lo: flags=73<UP,LOOPBACK,RUNNING>  mtu 65536
        inet 127.0.0.1  netmask 255.0.0.0
        inet6 ::1  prefixlen 128  scopeid 0x10<host>
        loop  txqueuelen 1000  (Local Loopback)
        RX packets 613  bytes 63906 (62.4 KiB)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 613  bytes 63906 (62.4 KiB)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0
[root@localhost ~]# cbmem
36 entries total:

// Lines were cut to avoid checkpatch.pl warnings

Total Time: 96,243,882,140,175,829

Signed-off-by: Jonathan Zhang 
Signed-off-by: Reddy Chagam 
Tested-by: [e-mail]
Change-Id: I29868f03037d1887b90dfb19d15aee83c456edce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38549
Tested-by: build bot (Jenkins) 
Reviewed-by: David Hendricks 
---
A configs/config.ocp_tiogapass
A src/mainboard/ocp/Kconfig
A src/mainboard/ocp/Kconfig.name
A src/mainboard/ocp/tiogapass/Kconfig
A src/mainboard/ocp/tiogapass/Kconfig.name
A src/mainboard/ocp/tiogapass/Makefile.inc
A src/mainboard/ocp/tiogapass/acpi/platform.asl
A src/mainboard/ocp/tiogapass/acpi_tables.c
A src/mainboard/ocp/tiogapass/board.fmd
A src/mainboard/ocp/tiogapass/board_info.txt
A src/mainboard/ocp/tiogapass/devicetree.cb
A src/mainboard/ocp/tiogapass/dsdt.asl
A src/mainboard/ocp/tiogapass/fadt.c
A src/mainboard/ocp/tiogapass/ramstage.c
A src/mainboard/ocp/tiogapass/romstage.c
A src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h
A src/mainboard/ocp/tiogapass/skxsp_tp_iio.h
17 files changed, 1,874 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  David Hendricks: Looks good to me, approved

diff --git a/configs/config.ocp_tiogapass b/configs/config.ocp_tiogapass
new file mode 100644
index 0000000..ca0a5b7
--- /dev/null
+++ b/configs/config.ocp_tiogapass
@@ -0,0 +1,5 @@
+CONFIG_VENDOR_OCP=y
+CONFIG_BOARD_OCP_TIOGAPASS=y
+CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
+CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y
+CONFIG_CPU_UCODE_BINARIES="3rdparty/intel-microcode/intel-ucode/06-55-04"
diff --git a/src/mainboard/ocp/Kconfig b/src/mainboard/ocp/Kconfig
new file mode 100644
index 0000000..b748129
--- /dev/null
+++ b/src/mainboard/ocp/Kconfig
@@ -0,0 +1,16 @@
+if VENDOR_OCP
+
+choice
+	prompt "Mainboard model"
+
+source "src/mainboard/ocp/*/Kconfig.name"
+
+endchoice
+
+source "src/mainboard/ocp/*/Kconfig"
+
+config MAINBOARD_VENDOR
+	string
+	default "Open Compute Project"
+
+endif # VENDOR_OCP
diff --git a/src/mainboard/ocp/Kconfig.name b/src/mainboard/ocp/Kconfig.name
new file mode 100644
index 0000000..f5d8d0a
--- /dev/null
+++ b/src/mainboard/ocp/Kconfig.name
@@ -0,0 +1,2 @@
+config VENDOR_OCP
+	bool "Open Compute Project"
diff --git a/src/mainboard/ocp/tiogapass/Kconfig b/src/mainboard/ocp/tiogapass/Kconfig
new file mode 100644
index 0000000..dfa8f54
--- /dev/null
+++ b/src/mainboard/ocp/tiogapass/Kconfig
@@ -0,0 +1,45 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2019 - 2020 Intel Corporation.
+## Copyright (C) 2019 - 2020 Facebook Inc
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+if BOARD_OCP_TIOGAPASS
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select ADD_FSP_BINARIES
+	select BOARD_ROMSIZE_KB_32768
+	select HAVE_ACPI_TABLES
+	select SOC_INTEL_XEON_SP
+	select MAINBOARD_USES_FSP2_0
+	select FSP_CAR
+
+config MAINBOARD_DIR
+	string
+	default "ocp/tiogapass"
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "TiogaPass"
+
+config MAINBOARD_FAMILY
+	string
+	default "TiogaPass"
+
+config FMDFILE
+	string
+	default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd"
+
+endif # BOARD_OCP_TIOGAPASS
diff --git a/src/mainboard/ocp/tiogapass/Kconfig.name b/src/mainboard/ocp/tiogapass/Kconfig.name
new file mode 100644
index 0000000..e1bf821
--- /dev/null
+++ b/src/mainboard/ocp/tiogapass/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_OCP_TIOGAPASS
+	bool "TiogaPass"
diff --git a/src/mainboard/ocp/tiogapass/Makefile.inc b/src/mainboard/ocp/tiogapass/Makefile.inc
new file mode 100644
index 0000000..f5ea591
--- /dev/null
+++ b/src/mainboard/ocp/tiogapass/Makefile.inc
@@ -0,0 +1,22 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2019 - 2020 Intel Corporation.
+## Copyright (C) 2019 - 2020 Facebook Inc
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+ramstage-y += ramstage.c
+ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c
+
+CPPFLAGS_common += -Isrc/mainboard/$(MAINBOARDDIR)/
+CPPFLAGS_common += -I$(CONFIG_FSP_HEADER_PATH)
diff --git a/src/mainboard/ocp/tiogapass/acpi/platform.asl b/src/mainboard/ocp/tiogapass/acpi/platform.asl
new file mode 100644
index 0000000..e349cf3
--- /dev/null
+++ b/src/mainboard/ocp/tiogapass/acpi/platform.asl
@@ -0,0 +1,382 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 - 2020 Intel Corporation.
+ * Copyright (C) 2019 - 2020 Facebook Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* Enable ACPI _SWS methods */
+#include <soc/intel/common/acpi/acpi_wake_source.asl>
+
+Name (_S0, Package (0x04) // mandatory system state
+{
+	0x00, 0x00, 0x00, 0x00
+})
+
+Name (_S5, Package (0x04)  // mandatory system state
+{
+	0x07, 0x00, 0x00, 0x00
+})
+
+/* The APM port can be used for generating software SMIs */
+OperationRegion (APMP, SystemIO, 0xb2, 2)
+Field (APMP, ByteAcc, NoLock, Preserve)
+{
+	APMC, 8,	// APM command
+	APMS, 8		// APM status
+}
+
+/* Port 80 POST */
+OperationRegion (DBG0, SystemIO, 0x80, 0x02)
+Field (DBG0, ByteAcc, Lock, Preserve)
+{
+	IO80, 8,
+	IO81, 8
+}
+
+/* IO-Trap at 0x800.
+ * This is the ACPI->SMI communication interface.
+ */
+OperationRegion (IO_T, SystemIO, 0x800, 0x10)
+Field (IO_T, ByteAcc, NoLock, Preserve)
+{
+	Offset (0x8),
+	TRP0, 8		/* IO-Trap at 0x808 */
+}
+
+OperationRegion (PSYS, SystemMemory, 0x6D081000, 0x0400)
+Field (PSYS, ByteAcc, NoLock, Preserve)
+{
+	PLAT,   32,  // Platform ID
+
+	// IOAPIC
+	APC0,   1,   // PCH IOAPIC Enable
+	AP00,   1,   // PC00 IOAPIC Enable
+	AP01,   1,   // PC01 IOAPIC Enable
+	AP02,   1,   // PC02 IOAPIC Enable
+	AP03,   1,   // PC03 IOAPIC Enable
+	AP04,   1,   // PC04 IOAPIC Enable
+	AP05,   1,   // PC05 IOAPIC Enable
+	AP06,   1,   // PC06 IOAPIC Enable
+	AP07,   1,   // PC07 IOAPIC Enable
+	AP08,   1,   // PC08 IOAPIC Enable
+	AP09,   1,   // PC09 IOAPIC Enable
+	AP10,   1,   // PC10 IOAPIC Enable
+	AP11,   1,   // PC11 IOAPIC Enable
+	AP12,   1,   // PC12 IOAPIC Enable
+	AP13,   1,   // PC13 IOAPIC Enable
+	AP14,   1,   // PC14 IOAPIC Enable
+	AP15,   1,   // PC15 IOAPIC Enable
+	AP16,   1,   // PC16 IOAPIC Enable
+	AP17,   1,   // PC17 IOAPIC Enable
+	AP18,   1,   // PC18 IOAPIC Enable
+	AP19,   1,   // PC19 IOAPIC Enable
+	AP20,   1,   // PC20 IOAPIC Enable
+	AP21,   1,   // PC21 IOAPIC Enable
+	AP22,   1,   // PC22 IOAPIC Enable
+	AP23,   1,   // PC23 IOAPIC Enable
+	RESA,   7,
+	SKOV,   1,   // Override Socket APIC Id
+	RES0,   7,
+
+	// Power Management
+	TPME,   1,
+	CSEN,   1,
+	C3EN,   1,
+	C6EN,   1,
+	C7EN,   1,
+	MWOS,   1,
+	PSEN,   1,
+	EMCA,   1,
+	HWAL,   2,
+	KPRS,   1,
+	MPRS,   1,
+	TSEN,   1,
+	FGTS,   1,
+	OSCX,   1,
+	RESX,   1,
+
+	// RAS
+	CPHP,   8,
+	IIOP,   8,
+	IIOH,   64,
+	PRBM,   32,
+	P0ID,   32,
+	P1ID,   32,
+	P2ID,   32,
+	P3ID,   32,
+	P4ID,   32,
+	P5ID,   32,
+	P6ID,   32,
+	P7ID,   32,
+	P0BM,   64,
+	P1BM,   64,
+	P2BM,   64,
+	P3BM,   64,
+	P4BM,   64,
+	P5BM,   64,
+	P6BM,   64,
+	P7BM,   64,
+	MEBM,   16,
+	MEBC,   16,
+	CFMM,   32,
+	TSSY,   32,  // TODO: This is TSSZ in system booted from production FW
+	M0BS,   64,
+	M1BS,   64,
+	M2BS,   64,
+	M3BS,   64,
+	M4BS,   64,
+	M5BS,   64,
+	M6BS,   64,
+	M7BS,   64,
+	M0RN,   64,
+	M1RN,   64,
+	M2RN,   64,
+	M3RN,   64,
+	M4RN,   64,
+	M5RN,   64,
+	M6RN,   64,
+	M7RN,   64,
+	SMI0,   32,
+	SMI1,   32,
+	SMI2,   32,
+	SMI3,   32,
+	SCI0,   32,
+	SCI1,   32,
+	SCI2,   32,
+	SCI3,   32,
+	MADD,   64,
+	CUU0,   128,
+	CUU1,   128,
+	CUU2,   128,
+	CUU3,   128,
+	CUU4,   128,
+	CUU5,   128,
+	CUU6,   128,
+	CUU7,   128,
+	CPSP,   8,
+	ME00,   128,
+	ME01,   128,
+	ME10,   128,
+	ME11,   128,
+	ME20,   128,
+	ME21,   128,
+	ME30,   128,
+	ME31,   128,
+	ME40,   128,
+	ME41,   128,
+	ME50,   128,
+	ME51,   128,
+	ME60,   128,
+	ME61,   128,
+	ME70,   128,
+	ME71,   128,
+	MESP,   16,
+	LDIR,   64,
+	PRID,   32,
+	AHPE,   8,
+
+	// VTD
+	DHRD,   192,
+	ATSR,   192,
+	RHSA,   192,
+
+	// SR-IOV
+	WSIC,   8,
+	WSIS,   16,
+	WSIB,   8,
+	WSID,   8,
+	WSIF,   8,
+	WSTS,   8,
+	WHEA,   8,
+
+	// BIOS Guard
+	BGMA,   64,
+	BGMS,   8,
+	BGIO,   16,
+	BGIL,   8,
+	CNBS,   8,
+
+	// USB3
+	XHMD,   8,
+	SBV1,   8,
+	SBV2,   8,
+
+	// HWPM
+	HWEN,   2,
+	ACEN,   1,
+	HWPI,   1,
+	RES1,   4,
+
+	// IIO
+	BB00,   8,
+	BB01,   8,
+	BB02,   8,
+	BB03,   8,
+	BB04,   8,
+	BB05,   8,
+	BB06,   8,
+	BB07,   8,
+	BB08,   8,
+	BB09,   8,
+	BB10,   8,
+	BB11,   8,
+	BB12,   8,
+	BB13,   8,
+	BB14,   8,
+	BB15,   8,
+	BB16,   8,
+	BB17,   8,
+	BB18,   8,
+	BB19,   8,
+	BB20,   8,
+	BB21,   8,
+	BB22,   8,
+	BB23,   8,
+	BB24,   8,
+	BB25,   8,
+	BB26,   8,
+	BB27,   8,
+	BB28,   8,
+	BB29,   8,
+	BB30,   8,
+	BB31,   8,
+	BB32,   8,
+	BB33,   8,
+	BB34,   8,
+	BB35,   8,
+	BB36,   8,
+	BB37,   8,
+	BB38,   8,
+	BB39,   8,
+	BB40,   8,
+	BB41,   8,
+	BB42,   8,
+	BB43,   8,
+	BB44,   8,
+	BB45,   8,
+	BB46,   8,
+	BB47,   8,
+	SGEN,   8,
+	SG00,   8,
+	SG01,   8,
+	SG02,   8,
+	SG03,   8,
+	SG04,   8,
+	SG05,   8,
+	SG06,   8,
+	SG07,   8,
+
+	// Performance
+	CLOD,   8,
+
+	// XTU
+	XTUB,   32,
+	XTUS,   32,
+	XMBA,   32,
+	DDRF,   8,
+	RT3S,   8,
+	RTP0,   8,
+	RTP3,   8,
+
+	// FPGA
+	FBB0,   8,
+	FBB1,   8,
+	FBB2,   8,
+	FBB3,   8,
+	FBB4,   8,
+	FBB5,   8,
+	FBB6,   8,
+	FBB7,   8,
+	FBL0,   8,
+	FBL1,   8,
+	FBL2,   8,
+	FBL3,   8,
+	FBL4,   8,
+	FBL5,   8,
+	FBL6,   8,
+	FBL7,   8,
+	P0FB,   8,
+	P1FB,   8,
+	P2FB,   8,
+	P3FB,   8,
+	P4FB,   8,
+	P5FB,   8,
+	P6FB,   8,
+	P7FB,   8,
+	FMB0,   32,
+	FMB1,   32,
+	FMB2,   32,
+	FMB3,   32,
+	FMB4,   32,
+	FMB5,   32,
+	FMB6,   32,
+	FMB7,   32,
+	FML0,   32,
+	FML1,   32,
+	FML2,   32,
+	FML3,   32,
+	FML4,   32,
+	FML5,   32,
+	FML6,   32,
+	FML7,   32,
+	FKPB,   32,
+	FKB0,   8,
+	FKB1,   8,
+	FKB2,   8,
+	FKB3,   8,
+	FKB4,   8,
+	FKB5,   8,
+	FKB6,   8,
+	FKB7,   8
+}
+
+/* SMI I/O Trap */
+Method (TRAP, 1, Serialized)
+{
+	Store (Arg0, SMIF)	// SMI Function
+	Store (0, TRP0)		// Generate trap
+	Return (SMIF)		// Return value of SMI handler
+}
+
+/*
+ * The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC.
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local Apic/IOAPIC configuration.
+ */
+
+Method (_PIC, 1)
+{
+	/* Remember the OS' IRQ routing choice. */
+	Store (Arg0, PICM)
+}
+
+/*
+ * The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method (_PTS, 1)
+{
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method (_WAK, 1)
+{
+	Return (Package (){ 0, 0 })
+}
diff --git a/src/mainboard/ocp/tiogapass/acpi_tables.c b/src/mainboard/ocp/tiogapass/acpi_tables.c
new file mode 100644
index 0000000..c4dda3b
--- /dev/null
+++ b/src/mainboard/ocp/tiogapass/acpi_tables.c
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ * Copyright (C) 2014 - 2020 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <intelblocks/acpi.h>
+#include <soc/acpi.h>
+
+extern const unsigned char AmlCode[];
+
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+	acpi_init_gnvs(gnvs);
+}
diff --git a/src/mainboard/ocp/tiogapass/board.fmd b/src/mainboard/ocp/tiogapass/board.fmd
new file mode 100644
index 0000000..1e3fda7
--- /dev/null
+++ b/src/mainboard/ocp/tiogapass/board.fmd
@@ -0,0 +1,11 @@
+FLASH 32M {
+	SI_ALL@0x0 0xa36000 {
+		SI_DESC@0x0 0x1000
+		SI_ME@0x1000 0xa23000
+		PLATFORM_DATA@0xa26000 0x10000
+	}
+	SI_BIOS@0x1000000 0x1000000 {
+		FMAP@0x0 0x800
+		COREBOOT(CBFS)@0x800 0xfff800
+	}
+}
diff --git a/src/mainboard/ocp/tiogapass/board_info.txt b/src/mainboard/ocp/tiogapass/board_info.txt
new file mode 100644
index 0000000..e86f78f
--- /dev/null
+++ b/src/mainboard/ocp/tiogapass/board_info.txt
@@ -0,0 +1,5 @@
+Board name: TiogaPass
+Category: server
+ROM protocol: SPI
+ROM socketed: yes
+Release year: 2018
diff --git a/src/mainboard/ocp/tiogapass/devicetree.cb b/src/mainboard/ocp/tiogapass/devicetree.cb
new file mode 100644
index 0000000..46311d9
--- /dev/null
+++ b/src/mainboard/ocp/tiogapass/devicetree.cb
@@ -0,0 +1,91 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2019 - 2020 Intel Corporation.
+## Copyright (C) 2019 - 2020 Facebook Inc
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+chip soc/intel/xeon_sp
+
+	register "pirqa_routing" = "PCH_IRQ11"
+	register "pirqb_routing" = "PCH_IRQ10"
+	register "pirqc_routing" = "PCH_IRQ11"
+	register "pirqd_routing" = "PCH_IRQ11"
+	register "pirqe_routing" = "PCH_IRQ11"
+	register "pirqf_routing" = "PCH_IRQ11"
+	register "pirqg_routing" = "PCH_IRQ11"
+	register "pirqh_routing" = "PCH_IRQ11"
+
+	# configure device interrupt routing
+	register "ir00_routing" = "0x3210" # IR00, Dev31
+	register "ir01_routing" = "0x3210" # IR01, Dev30
+	register "ir02_routing" = "0x3210" # IR02, Dev29
+	register "ir03_routing" = "0x3210" # IR03, Dev28
+	register "ir04_routing" = "0x3210" # IR04, Dev27
+
+	# configure interrupt polarity control
+	register "ipc0" = "0x00ff4000" # IPC0, PIRQA-H (IRQ16-23) should always be ActiveLow
+	register "ipc1" = "0x00000000" # IPC1
+	register "ipc2" = "0x00000000" # IPC2
+	register "ipc3" = "0x00000000" # IPC3
+
+	# configure MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT_CORES msrs
+	# FB production turbo_ratio_limit is 0x1f1f1f2022222325
+	register "turbo_ratio_limit" = "0x1b1b1b1d20222325"
+	# FB production turbo_ratio_limit_cores is 0x1c1812100c080402
+	register "turbo_ratio_limit_cores" = "0x1c1814100c080402"
+
+	# configure PSTATE_REQ_RATIO for MSR_IA32_PERF_CTRL
+	register "pstate_req_ratio" = "0xa"
+
+	# configure VTD
+	register "vtd_support" = "1"
+	register "coherency_support" = "1"
+	register "ats_support" = "1"
+
+	device cpu_cluster 0 on
+	  device lapic 0 on end
+	end
+
+	device domain 0 on
+		device pci 00.0 on end # Host bridge
+		device pci 04.0 on end # Intel Corporation SkyLake-E CBDMA Registers
+		device pci 04.1 on end # Intel Corporation SkyLake-E CBDMA Registers
+		device pci 04.2 on end # Intel Corporation SkyLake-E CBDMA Registers
+		device pci 04.3 on end # Intel Corporation SkyLake-E CBDMA Registers
+		device pci 04.4 on end # Intel Corporation SkyLake-E CBDMA Registers
+		device pci 04.5 on end # Intel Corporation SkyLake-E CBDMA Registers
+		device pci 04.6 on end # Intel Corporation SkyLake-E CBDMA Registers
+		device pci 04.7 on end # Intel Corporation SkyLake-E CBDMA Registers
+		device pci 05.0 on end # Intel Corporation SkyLake-E MM/Vt-d Configuration Registers
+		device pci 05.2 on end # Intel Corporation Device 2025
+		device pci 05.4 on end # Intel Corporation Device 2026
+		device pci 08.0 on end # Intel Corporation SkyLake-E Ubox Registers
+		device pci 08.1 on end # Intel Corporation SkyLake-E Ubox Registers
+		device pci 08.2 on end # Intel Corporation SkyLake-E Ubox Registers
+		device pci 11.0 on end # Intel Corporation C620 Series Chipset Family MROM 0
+		device pci 11.1 on end # Intel Corporation C620 Series Chipset Family MROM 1
+		device pci 11.5 on end # Intel Corporation C620 Series Chipset Family SSATA Controller [AHCI mode]
+		device pci 14.0 on end # Intel Corporation C620 Series Chipset Family USB 3.0 xHCI Controller
+		device pci 16.0 on end # Intel Corporation C620 Series Chipset Family MEI Controller #1
+		device pci 16.1 on end # Intel Corporation C620 Series Chipset Family MEI Controller #2
+		device pci 16.4 on end # Intel Corporation C620 Series Chipset Family MEI Controller #3
+		device pci 17.0 on end # Intel Corporation C620 Series Chipset Family SATA Controller [AHCI mode]
+		device pci 1c.0 on end # PCI bridge: Intel Corporation C620 Series Chipset Family PCI Express Root Port #1
+		device pci 1c.4 on end # PCI bridge: Intel Corporation C620 Series Chipset Family PCI Express Root Port #5
+		device pci 1f.0 on end # Intel Corporation C621 Series Chipset LPC/eSPI Controller
+		device pci 1f.2 on end # Intel Corporation C620 Series Chipset Family Power Management Controller
+		device pci 1f.4 on end # Intel Corporation C620 Series Chipset Family SMBus
+		device pci 1f.5 on end # Intel Corporation C620 Series Chipset Family SPI Controller
+	end
+end
diff --git a/src/mainboard/ocp/tiogapass/dsdt.asl b/src/mainboard/ocp/tiogapass/dsdt.asl
new file mode 100644
index 0000000..aca6c4d
--- /dev/null
+++ b/src/mainboard/ocp/tiogapass/dsdt.asl
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 - 2020 Intel Corporation.
+ * Copyright (C) 2019 - 2020 Facebook Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+
+#include <arch/acpi.h>
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x02,		// DSDT revision: ACPI v2.0 and up
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725	// OEM revision
+)
+{
+	// platform ACPI tables
+	#include "acpi/platform.asl"
+
+	// global NVS and variables
+	#include <soc/intel/xeon_sp/acpi/globalnvs.asl>
+
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	// Xeon-SP ACPI tables
+	Scope (_SB) {
+		#include <soc/intel/xeon_sp/acpi/uncore.asl>
+	}
+}
diff --git a/src/mainboard/ocp/tiogapass/fadt.c b/src/mainboard/ocp/tiogapass/fadt.c
new file mode 100644
index 0000000..6962455
--- /dev/null
+++ b/src/mainboard/ocp/tiogapass/fadt.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 - 2020 Intel Corporation.
+ * Copyright (C) 2019 - 2020 Facebook Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include <soc/acpi.h>
+
+void motherboard_fill_fadt(acpi_fadt_t *fadt)
+{
+	fadt->reserved = 0;
+	fadt->preferred_pm_profile = PM_ENTERPRISE_SERVER;
+}
diff --git a/src/mainboard/ocp/tiogapass/ramstage.c b/src/mainboard/ocp/tiogapass/ramstage.c
new file mode 100644
index 0000000..35a7faa
--- /dev/null
+++ b/src/mainboard/ocp/tiogapass/ramstage.c
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 - 2020 Intel Corporation.
+ * Copyright (C) 2019 - 2020 Facebook Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <soc/ramstage.h>
+
+void mainboard_silicon_init_params(FSPS_UPD *params)
+{
+}
diff --git a/src/mainboard/ocp/tiogapass/romstage.c b/src/mainboard/ocp/tiogapass/romstage.c
new file mode 100644
index 0000000..c95a696
--- /dev/null
+++ b/src/mainboard/ocp/tiogapass/romstage.c
@@ -0,0 +1,60 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 - 2020 Intel Corporation.
+ * Copyright (C) 2019 - 2020 Facebook Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <fsp/api.h>
+#include <FspmUpd.h>
+#include <soc/romstage.h>
+
+#include "skxsp_tp_gpio.h"
+#include "skxsp_tp_iio.h"
+
+/*
+* Configure GPIO depend on platform
+*/
+static void mainboard_config_gpios(FSPM_UPD *mupd)
+{
+	mupd->FspmConfig.GpioConfig.GpioTable = (UPD_GPIO_INIT_CONFIG *) tp_gpio_table;
+	mupd->FspmConfig.GpioConfig.NumberOfEntries =
+		sizeof(tp_gpio_table)/sizeof(UPD_GPIO_INIT_CONFIG);
+}
+
+static void mainboard_config_iio(FSPM_UPD *mupd)
+{
+	mupd->FspmConfig.IioBifurcationConfig.IIoBifurcationTable =
+		(UPD_IIO_BIFURCATION_DATA_ENTRY *) tp_iio_bifur_table;
+	mupd->FspmConfig.IioBifurcationConfig.NumberOfEntries =
+		ARRAY_SIZE(tp_iio_bifur_table);
+
+	mupd->FspmConfig.IioPciConfig.ConfigurationTable =
+		(UPD_PCI_PORT_CONFIG *) tp_iio_pci_port_skt0;
+	mupd->FspmConfig.IioPciConfig.NumberOfEntries =
+		ARRAY_SIZE(tp_iio_pci_port_skt0);
+
+	mupd->FspmConfig.PchPciConfig.PciPortConfig =
+		(UPD_PCH_PCIE_PORT *) tp_pch_pci_port_skt0;
+	mupd->FspmConfig.PchPciConfig.NumberOfEntries =
+		ARRAY_SIZE(tp_pch_pci_port_skt0);
+
+	mupd->FspmConfig.PchPciConfig.RootPortFunctionSwapping = 0x00;
+	mupd->FspmConfig.PchPciConfig.PciePllSsc = 0x00;
+}
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	mainboard_config_gpios(mupd);
+	mainboard_config_iio(mupd);
+}
diff --git a/src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h b/src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h
new file mode 100644
index 0000000..5987caa
--- /dev/null
+++ b/src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h
@@ -0,0 +1,1019 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 - 2020 Intel Corporation.
+ * Copyright (C) 2019 - 2020 Facebook Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SKXSP_TP_GPIO_H_
+#define _SKXSP_TP_GPIO_H_
+
+#include <gpio_fsp.h>
+#include <soc/gpio_soc_defs.h>
+
+/*
+ *  OCP TiogaPass Gpio Pad Configuration
+ */
+static const UPD_GPIO_INIT_CONFIG tp_gpio_table[] = {
+	{GPIO_SKL_H_GPP_A0, {
+		GpioPadModeGpio,    GpioHostOwnGpio, GpioDirIn,    GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_A_0_LPC_RCIN_N_ESPI_ALERT1_N
+	{GPIO_SKL_H_GPP_A1, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_A_1_LAD_0_ESPI_IO_0
+	{GPIO_SKL_H_GPP_A2, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_A_2_LAD_1_ESPI_IO_1
+	{GPIO_SKL_H_GPP_A3, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_A_3_LAD_2_ESPI_IO_2
+	{GPIO_SKL_H_GPP_A4, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_A_4_LAD_3_ESPI_IO_3
+	{GPIO_SKL_H_GPP_A5, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_A_5_LPC_LFRAME_N_ESPI_CS0_N
+	{GPIO_SKL_H_GPP_A6, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_A_6_IRQ_LPC_SERIRQ_ESPI_CS1_N
+	{GPIO_SKL_H_GPP_A7, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_A_7_IRQ_LPC_PIRQA_N_ESPI_ALERT0_N
+	{GPIO_SKL_H_GPP_A8, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_A_8_FM_LPC_CLKRUN_N
+	{GPIO_SKL_H_GPP_A9, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_A_9_CLKOUT_LPC0_ESPI_CLK
+	{GPIO_SKL_H_GPP_A10, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_A_10_CLKOUT_LPC1
+	{GPIO_SKL_H_GPP_A11, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_A_11_FM_LPC_PME_N
+	{GPIO_SKL_H_GPP_A12, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_A_12_BMBUSY_N_SXEXITHLDOFF_N
+	{GPIO_SKL_H_GPP_A13, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_A_13_SUSWARN_N_SUSPWRDNACK
+	{GPIO_SKL_H_GPP_A14, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_A_14_ESPI_RESET_N
+	{GPIO_SKL_H_GPP_A15, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_A_15_SUSACK_N
+	{GPIO_SKL_H_GPP_A16, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_A_16_CLKOUT_LPC2
+	{GPIO_SKL_H_GPP_A17, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_A_17
+	{GPIO_SKL_H_GPP_A18, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_A_18
+	//		{GPIO_SKL_H_GPP_A19, {} }, //GPP_A_19, controlled by ME
+	{GPIO_SKL_H_GPP_A20, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} },//GPP_A_20
+	{GPIO_SKL_H_GPP_A21, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,   GpioOutLow,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_A_21
+	{GPIO_SKL_H_GPP_A22, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_A_22
+	{GPIO_SKL_H_GPP_A23, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_A_23
+
+	{GPIO_SKL_H_GPP_B0,  {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_B_0_CORE_VID_0
+	{GPIO_SKL_H_GPP_B1,  {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_B_1_CORE_VID_1
+	{GPIO_SKL_H_GPP_B2,  {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_B_2_VRALERT_N
+	{GPIO_SKL_H_GPP_B3,  {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_B_3_CPU_GP2
+	{GPIO_SKL_H_GPP_B4,  {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_B_4_CPU_GP3
+	{GPIO_SKL_H_GPP_B5,  {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_B_5_SRCCLKREQ0_N
+	{GPIO_SKL_H_GPP_B6,  {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_B_6_SRCCLKREQ1_N
+	{GPIO_SKL_H_GPP_B7,  {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_B_7_SRCCLKREQ2_N
+	{GPIO_SKL_H_GPP_B8,  {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_B_8_SRCCLKREQ3_N
+	{GPIO_SKL_H_GPP_B9,  {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_B_9_SRCCLKREQ4_N
+	{GPIO_SKL_H_GPP_B10, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_B_10_SRCCLKREQ5_N
+	{GPIO_SKL_H_GPP_B11, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,   GpioOutLow,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_B_11
+	{GPIO_SKL_H_GPP_B12, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_B_12_GLB_RST_WARN_N
+	{GPIO_SKL_H_GPP_B13, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_B_13_RST_PLTRST_N
+	{GPIO_SKL_H_GPP_B14, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_B_14_FM_PCH_BIOS_RCVR_SPKR
+	{GPIO_SKL_H_GPP_B15, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_B_15
+	{GPIO_SKL_H_GPP_B16, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_B_16
+	{GPIO_SKL_H_GPP_B17, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_B_17
+	{GPIO_SKL_H_GPP_B18, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_B_18
+	{GPIO_SKL_H_GPP_B19, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,   GpioOutLow,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_B_19
+	{GPIO_SKL_H_GPP_B20, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_B_20
+	{GPIO_SKL_H_GPP_B21, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_B_21
+	{GPIO_SKL_H_GPP_B22, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_B_22
+	{GPIO_SKL_H_GPP_B23, {
+		GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut,   GpioOutLow,
+		GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_B_23_MEIE_SML1ALRT_N_PHOT_N
+
+//		{GPIO_SKL_H_GPP_C0,  {} }, //GPP_C_0_SMBCLK, controlled by ME
+//		{GPIO_SKL_H_GPP_C1,  {} }, //GPP_C_1_SMBDATA, controlled by ME
+	{GPIO_SKL_H_GPP_C2,  {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_C_2_SMBALERT_N
+//		{GPIO_SKL_H_GPP_C3,  {} }, //GPP_C_3_SML0CLK_IE, controlled by ME
+//		{GPIO_SKL_H_GPP_C4,  {} }, //GPP_C_4_SML0DATA_IE, controlled by ME
+	{GPIO_SKL_H_GPP_C5,  {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+		GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_C_5_SML0ALERT_IE_N
+//		{GPIO_SKL_H_GPP_C6,  {} }, //GPP_C_6_SML1CLK_IE, controlled by ME
+//		{GPIO_SKL_H_GPP_C7,  {} }, //GPP_C_7_SML1DATA_IE, controlled by ME
+	{GPIO_SKL_H_GPP_C8,  {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_C_8
+	{GPIO_SKL_H_GPP_C9,  {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_C_9
+	{GPIO_SKL_H_GPP_C10, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow,
+		GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_C_10
+	{GPIO_SKL_H_GPP_C11, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,	GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_C_11
+	{GPIO_SKL_H_GPP_C12, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_C_12
+	{GPIO_SKL_H_GPP_C13, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_C_13
+	{GPIO_SKL_H_GPP_C14, {
+		GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, GpioOutDefault,
+		GpioIntLevel | GpioIntSci, GpioResetNormal, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_C_14
+	{GPIO_SKL_H_GPP_C15, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_C_15
+	{GPIO_SKL_H_GPP_C16, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_C_16
+	{GPIO_SKL_H_GPP_C17, {
+		GpioPadModeGpio,		GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_C_17
+	{GPIO_SKL_H_GPP_C18, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_C_18
+	{GPIO_SKL_H_GPP_C19, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_C_19
+//		{GPIO_SKL_H_GPP_C20, {} }, //GPP_C_20, controlled by ME
+	{GPIO_SKL_H_GPP_C21, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_C_21
+	{GPIO_SKL_H_GPP_C22, {
+		GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, GpioOutDefault,
+		GpioIntLevel | GpioIntSmi, GpioResetNormal, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_C_22
+	{GPIO_SKL_H_GPP_C23, {
+		GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, GpioOutDefault,
+		GpioIntLevel | GpioIntSmi, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_C_23
+
+	{GPIO_SKL_H_GPP_D0, {
+		GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn,		GpioOutDefault,
+		GpioIntLevel | GpioIntSmi, GpioResetNormal, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_D_0
+	{GPIO_SKL_H_GPP_D1, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_D_1
+	{GPIO_SKL_H_GPP_D2, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_D_2
+	{GPIO_SKL_H_GPP_D3, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_D_3
+	{GPIO_SKL_H_GPP_D4, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,   GpioOutLow,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_D_4
+	{GPIO_SKL_H_GPP_D5, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_D_5
+	{GPIO_SKL_H_GPP_D6, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_D_6
+	{GPIO_SKL_H_GPP_D7, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_D_7
+	{GPIO_SKL_H_GPP_D8, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_D_8
+	{GPIO_SKL_H_GPP_D9, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_D_9_SSATA_DEVSLP3
+	{GPIO_SKL_H_GPP_D10, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_D_10_SSATA_DEVSLP4
+	{GPIO_SKL_H_GPP_D11, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_D_11_SSATA_DEVSLP5
+	{GPIO_SKL_H_GPP_D12, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_D_12_SSATA_SDATAOUT1
+	{GPIO_SKL_H_GPP_D13, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_D_13_SML0BLCK_IE
+	{GPIO_SKL_H_GPP_D14, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_D_14_SML0BDATA_IE
+	{GPIO_SKL_H_GPP_D15, {
+		GpioPadModeNative3, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_D_15_SSATA_SDATAOUT0
+	{GPIO_SKL_H_GPP_D16, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_D_16_SML0BALERT_IE_N
+	{GPIO_SKL_H_GPP_D17, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_D_17
+	{GPIO_SKL_H_GPP_D18, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_D_18
+	{GPIO_SKL_H_GPP_D19, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,   GpioOutLow,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock | GpioOutputStateLock
+		} }, //GPP_D_19
+	{GPIO_SKL_H_GPP_D20, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_D_20_TP_PCH_GPP_D_20
+	{GPIO_SKL_H_GPP_D21, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_D_21_IE_URAT_RX
+	{GPIO_SKL_H_GPP_D22, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_D_22_IE_URAT_TX
+	{GPIO_SKL_H_GPP_D23, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_D_23
+
+	{GPIO_SKL_H_GPP_E0, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntLevel | GpioIntSmi, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_E_0_SATAXPCIE0_SATAGP0
+	{GPIO_SKL_H_GPP_E1, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntLevel | GpioIntSmi, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_E_1_SATAXPCIE1_SATAGP1
+	{GPIO_SKL_H_GPP_E2, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_E_2_SATAXPCIE2_SATAGP2
+	{GPIO_SKL_H_GPP_E3, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_E_3_CPU_GP0
+	{GPIO_SKL_H_GPP_E4, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_E_4_SATA_DEVSLP0
+	{GPIO_SKL_H_GPP_E5, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_E_5_SATA_DEVSLP1
+	{GPIO_SKL_H_GPP_E6, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_E_6_SATA_DEVSLP2
+	{GPIO_SKL_H_GPP_E7, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_E_7_CPU_GP1
+	{GPIO_SKL_H_GPP_E8, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_E_8_SATA_LED_N
+	{GPIO_SKL_H_GPP_E9, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_E_9_USB2_OC0_N
+	{GPIO_SKL_H_GPP_E10, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_E_10_USB2_OC1_N
+	{GPIO_SKL_H_GPP_E11, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_E_11_USB2_OC2_N
+	{GPIO_SKL_H_GPP_E12, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_E_12_USB2_OC3_N
+
+	{GPIO_SKL_H_GPP_F0, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_F_0_SATAXPCIE3_SATAGP3
+	{GPIO_SKL_H_GPP_F1, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_F_1_SATAXPCIE4_SATAGP4
+	{GPIO_SKL_H_GPP_F2, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_F_2_SATAXPCIE5_SATAGP5
+	{GPIO_SKL_H_GPP_F3, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_F_3_SATAXPCIE6_SATAGP6
+	{GPIO_SKL_H_GPP_F4, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_F_4_SATAXPCIE7_SATAGP7
+	{GPIO_SKL_H_GPP_F5, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutLow,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_F_5_SATA_DEVSLP3
+	{GPIO_SKL_H_GPP_F6, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_F_6_SATA_DEVSLP4
+	{GPIO_SKL_H_GPP_F7, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_F_7_SATA_DEVSLP5
+	{GPIO_SKL_H_GPP_F8, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_F_8_SATA_DEVSLP6
+	{GPIO_SKL_H_GPP_F9, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_F_9_SATA_DEVSLP7
+	{GPIO_SKL_H_GPP_F10, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_F_10_SATA_SCLOCK
+	{GPIO_SKL_H_GPP_F11, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_F_11_SATA_SLOAD
+	{GPIO_SKL_H_GPP_F12, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_F_12_SATA_SDATAOUT1
+	{GPIO_SKL_H_GPP_F13, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_F_13_SATA_SDATAOUT0
+	{GPIO_SKL_H_GPP_F14, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_F_14_SSATA_LED_N
+	{GPIO_SKL_H_GPP_F15, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_F_15_USB2_OC4_N
+	{GPIO_SKL_H_GPP_F16, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_F_16_USB2_OC5_N
+	{GPIO_SKL_H_GPP_F17, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_F_17_USB2_OC6_N
+	{GPIO_SKL_H_GPP_F18, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_F_18_USB2_OC7_N
+	{GPIO_SKL_H_GPP_F19, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_F_19_LAN_SMBCLK
+	{GPIO_SKL_H_GPP_F20, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_F_20_LAN_SMBDATA
+	{GPIO_SKL_H_GPP_F21, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_F_21_LAN_SMBALERT_N
+	{GPIO_SKL_H_GPP_F22, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_F_22_SSATA_SCLOCK
+	{GPIO_SKL_H_GPP_F23, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_F_23_SSATA_SLOAD
+
+	{GPIO_SKL_H_GPP_G0, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_G_0_FANTACH0_FANTACH0IE
+	{GPIO_SKL_H_GPP_G1, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_G_1_FANTACH1_FANTACH1IE
+	{GPIO_SKL_H_GPP_G2, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_G_2_FANTACH2_FANTACH2IE
+	{GPIO_SKL_H_GPP_G3, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_G_3_FANTACH3_FANTACH3IE
+	{GPIO_SKL_H_GPP_G4, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_G_4_FANTACH4_FANTACH4IE
+	{GPIO_SKL_H_GPP_G5, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_G_5_FANTACH5_FANTACH5IE
+	{GPIO_SKL_H_GPP_G6, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_G_6_FANTACH6_FANTACH6IE
+	{GPIO_SKL_H_GPP_G7, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_G_7_FANTACH7_FANTACH7IE
+	{GPIO_SKL_H_GPP_G8, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_G_8_FANPWM0_FANPWM0IE
+	{GPIO_SKL_H_GPP_G9, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_G_9_FANPWM1_FANPWM1IE
+	{GPIO_SKL_H_GPP_G10, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_G_10_FANPWM2_FANPWM2IE
+	{GPIO_SKL_H_GPP_G11, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_G_11_FANPWM3_FANPWM3IE
+	{GPIO_SKL_H_GPP_G12, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutLow,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_G_12
+	{GPIO_SKL_H_GPP_G13, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutLow,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_G_13
+	{GPIO_SKL_H_GPP_G14, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutLow,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_G_14
+	{GPIO_SKL_H_GPP_G15, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutLow,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_G_15
+	{GPIO_SKL_H_GPP_G16, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutLow,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_G_16
+	{GPIO_SKL_H_GPP_G17, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_G_17_ADR_COMPLETE
+	{GPIO_SKL_H_GPP_G18, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_G_18_FM_NMI_EVENT_N
+	{GPIO_SKL_H_GPP_G19, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_G_19_FM_SMI_ACTIVE_N
+//		{GPIO_SKL_H_GPP_G20, {} }, //GPP_G_20_SSATA_DEVSLP0, controlled by ME
+	{GPIO_SKL_H_GPP_G21, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_G_21_SSATA_DEVSLP1
+	{GPIO_SKL_H_GPP_G22, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_G_22_SSATA_DEVSLP2
+	{GPIO_SKL_H_GPP_G23, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_G_23_SSATAXPCIE0_SSATAGP0
+
+	{GPIO_SKL_H_GPP_H0, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_H_0_SRCCLKREQ6_N
+	{GPIO_SKL_H_GPP_H1, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_H_1_SRCCLKREQ7_N
+	{GPIO_SKL_H_GPP_H2, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_H_2_SRCCLKREQ8_N
+	{GPIO_SKL_H_GPP_H3, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_H_3_SRCCLKREQ9_N
+	{GPIO_SKL_H_GPP_H4, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_H_4_SRCCLKREQ10_N
+//		{GPIO_SKL_H_GPP_H5,  {} }, //GPP_H_5_SRCCLKREQ11_N
+	{GPIO_SKL_H_GPP_H6, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_H_6_SRCCLKREQ12_N
+	{GPIO_SKL_H_GPP_H7, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_H_7_SRCCLKREQ13_N
+	{GPIO_SKL_H_GPP_H8, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_H_8_SRCCLKREQ14_N
+	{GPIO_SKL_H_GPP_H9, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_H_9_SRCCLKREQ15_N
+//		{GPIO_SKL_H_GPP_H10, {} }, //GPP_H_10_SML2CLK_IE
+//		{GPIO_SKL_H_GPP_H11, {} }, //GPP_H_11_SML2DATA_IE
+	{GPIO_SKL_H_GPP_H12, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_H_12_SML2ALERT_N_IE
+//		{GPIO_SKL_H_GPP_H13, {} }, //GPP_H_13_SML3CLK_IE
+//		{GPIO_SKL_H_GPP_H14, {} }, //GPP_H_14_SML3DATA_IE
+	{GPIO_SKL_H_GPP_H15, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_H_15_SML3ALERT_N_IE
+//		{GPIO_SKL_H_GPP_H16, {} }, //GPP_H_16_SML4CLK_IE
+//		{GPIO_SKL_H_GPP_H17, {} }, //GPP_H_17_SML4DATA_IE
+	{GPIO_SKL_H_GPP_H18, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_H_18_SML4ALERT_N_IE
+	{GPIO_SKL_H_GPP_H19, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_H_19_SSATAXPCIE1_SSATAGP1
+	{GPIO_SKL_H_GPP_H20, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_H_20_SSATAXPCIE2_SSATAGP2
+	{GPIO_SKL_H_GPP_H21, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_H_21_SSATAXPCIE3_SSATAGP3
+	{GPIO_SKL_H_GPP_H22, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_H_22_SSATAXPCIE4_SSATAGP4
+	{GPIO_SKL_H_GPP_H23, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock
+		} }, //GPP_H_23_SSATAXPCIE5_SSATAGP5
+
+	{GPIO_SKL_H_GPP_I0, {
+		GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_I_0_GBE_TDO
+	{GPIO_SKL_H_GPP_I1, {
+		GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_I_1_GBE_TCK
+	{GPIO_SKL_H_GPP_I2, {
+		GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_I_2_GBE_TMS
+	{GPIO_SKL_H_GPP_I3, {
+		GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_I_3_GBE_TDI
+	{GPIO_SKL_H_GPP_I4, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_I_4_DO_RESET_IN_N
+	{GPIO_SKL_H_GPP_I5, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_I_5_DO_RESET_OUT_N
+	{GPIO_SKL_H_GPP_I6, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_I_6_RESET_DONE
+	{GPIO_SKL_H_GPP_I7, {
+		GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_I_7_JTAG_GBE_TRST_N
+	{GPIO_SKL_H_GPP_I8, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_I_8_GBE_PCI_DIS
+	{GPIO_SKL_H_GPP_I9, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_I_9_GBE_LAN_DIS
+	{GPIO_SKL_H_GPP_I10, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_I_10
+
+	{GPIO_SKL_H_GPP_J0, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_J_0_LAN_LED_P0_0
+	{GPIO_SKL_H_GPP_J1, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_J_1_LAN_LED_P0_1
+	{GPIO_SKL_H_GPP_J2, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_J_2_LAN_LED_P1_0
+	{GPIO_SKL_H_GPP_J3, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_J_3_LAN_LED_P1_1
+	{GPIO_SKL_H_GPP_J4, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_J_4_LAN_LED_P2_0
+	{GPIO_SKL_H_GPP_J5, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_J_5_LAN_LED_P2_1
+	{GPIO_SKL_H_GPP_J6, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_J_6_LAN_LED_P3_0
+	{GPIO_SKL_H_GPP_J7, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_J_7_LAN_LED_P3_1
+	{GPIO_SKL_H_GPP_J8, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_J_8_LAN_I2C_SCL_MDC_P0
+	{GPIO_SKL_H_GPP_J9, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_J_9_LAN_I2C_SDA_MDIO_P0
+	{GPIO_SKL_H_GPP_J10, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_J_10_LAN_I2C_SCL_MDC_P1
+	{GPIO_SKL_H_GPP_J11, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_J_11_LAN_I2C_SDA_MDIO_P1
+	{GPIO_SKL_H_GPP_J12, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_J_12_LAN_I2C_SCL_MDC_P2
+	{GPIO_SKL_H_GPP_J13, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_J_13_LAN_I2C_SDA_MDIO_P2
+	{GPIO_SKL_H_GPP_J14, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_J_14_LAN_I2C_SCL_MDC_P3
+	{GPIO_SKL_H_GPP_J15, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_J_15_LAN_I2C_SDA_MDIO_P3
+	{GPIO_SKL_H_GPP_J16, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_J_16_LAN_SDP_P0_0
+	{GPIO_SKL_H_GPP_J17, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_J_17_LAN_SDP_P0_1
+	{GPIO_SKL_H_GPP_J18, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_J_18_LAN_SDP_P1_0
+	{GPIO_SKL_H_GPP_J19, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_J_19_LAN_SDP_P1_1
+	{GPIO_SKL_H_GPP_J20, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_J_20_LAN_SDP_P2_0
+	{GPIO_SKL_H_GPP_J21, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_J_21_LAN_SDP_P2_1
+	{GPIO_SKL_H_GPP_J22, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_J_22_LAN_SDP_P3_0
+	{GPIO_SKL_H_GPP_J23, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_J_23_LAN_SDP_P3_1
+
+	{GPIO_SKL_H_GPP_K0, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_K_0_LAN_NCSI_CLK_IN
+	{GPIO_SKL_H_GPP_K1, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_K_1_LAN_NCSI_TXD0
+	{GPIO_SKL_H_GPP_K2, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_K_2_LAN_NCSI_TXD1
+	{GPIO_SKL_H_GPP_K3, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_K_3_LAN_NCSI_TX_EN
+	{GPIO_SKL_H_GPP_K4, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_K_4_LAN_NCSI_CRS_DV
+	{GPIO_SKL_H_GPP_K5, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_K_5_LAN_NCSI_RXD0
+	{GPIO_SKL_H_GPP_K6, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_K_6_LAN_NCSI_RXD1
+	{GPIO_SKL_H_GPP_K7, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_K_7
+	{GPIO_SKL_H_GPP_K8, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,  GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_K_8_LAN_NCSI_ARB_IN
+	{GPIO_SKL_H_GPP_K9, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_K_9_LAN_NCSI_ARB_OUT
+	{GPIO_SKL_H_GPP_K10, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_K_10_PE_RST_N
+
+	{GPIO_SKL_H_GPP_L2, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_L_2_TESTCH0_D0
+	{GPIO_SKL_H_GPP_L3, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_L_3_TESTCH0_D1
+	{GPIO_SKL_H_GPP_L4, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_L_4_TESTCH0_D2
+	{GPIO_SKL_H_GPP_L5, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_L_5_TESTCH0_D3
+	{GPIO_SKL_H_GPP_L6, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_L_6_TESTCH0_D4
+	{GPIO_SKL_H_GPP_L7, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_L_7_TESTCH0_D5
+	{GPIO_SKL_H_GPP_L8, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_L_8_TESTCH0_D6
+	{GPIO_SKL_H_GPP_L9, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_L_9_TESTCH0_D7
+	{GPIO_SKL_H_GPP_L10, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_L_10_TESTCH0_CLK
+	{GPIO_SKL_H_GPP_L11, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_L_11_TESTCH1_D0
+	{GPIO_SKL_H_GPP_L12, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_L_12_TESTCH1_D1
+	{GPIO_SKL_H_GPP_L13, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_L_13_TESTCH1_D2
+	{GPIO_SKL_H_GPP_L14, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_L_14_TESTCH1_D3
+	{GPIO_SKL_H_GPP_L15, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_L_15_TESTCH1_D4
+	{GPIO_SKL_H_GPP_L16, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_L_16_TESTCH1_D5
+	{GPIO_SKL_H_GPP_L17, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_L_17_TESTCH1_D6
+	{GPIO_SKL_H_GPP_L18, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_L_18_TESTCH1_D7
+	{GPIO_SKL_H_GPP_L19, {
+		GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,   GpioOutDefault,
+		GpioIntDis, GpioResetDeep,  GpioTermNone, GpioPadConfigLock
+		} }, //GPP_L_19_TESTCH1_CLK
+
+	{GPIO_SKL_H_GPD0,	{} }, //GPD_0, controlled by ME
+	{GPIO_SKL_H_GPD1,	{
+		GpioPadModeGpio,   GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock
+		} }, //GPD_1_ACPRESENT
+	{GPIO_SKL_H_GPD2,	{
+		GpioPadModeGpio,   GpioHostOwnGpio, GpioDirIn,		GpioOutLow,
+		GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock
+		} }, //GPD_2_GBE_WAKE_N
+	{GPIO_SKL_H_GPD3,	{
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock
+		} }, //GPD_3_PWRBTNB_N
+	{GPIO_SKL_H_GPD4,	{
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock
+		} }, //GPD_4_SLP_S3B
+	{GPIO_SKL_H_GPD5,	{
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,   GpioOutDefault,
+		GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock
+		} }, //GPD_5_SLP_S4B
+	{GPIO_SKL_H_GPD6,	{
+		GpioPadModeGpio,   GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock
+		} }, //GPD_6_SLPA_N
+	{GPIO_SKL_H_GPD7,	{
+		GpioPadModeGpio,   GpioHostOwnGpio, GpioDirIn,		GpioOutLow,
+		GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock
+		} }, //GPD_7
+	{GPIO_SKL_H_GPD8,	{
+		GpioPadModeGpio,   GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock
+		} }, //GPD_8_CLK_33K_PCH_SUSCLK_PLD
+	{GPIO_SKL_H_GPD9,	{
+		GpioPadModeGpio,   GpioHostOwnGpio, GpioDirIn,		GpioOutLow,
+		GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock
+		} }, //GPD_9
+	{GPIO_SKL_H_GPD10, {
+		GpioPadModeGpio,   GpioHostOwnGpio, GpioDirIn,		GpioOutDefault,
+		GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock
+		} }, //GPD_10_FM_SLPS5_N
+	{GPIO_SKL_H_GPD11, {
+		GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,		GpioOutLow,
+		GpioIntDis, GpioResetPwrGood,  GpioTermNone, GpioPadConfigLock
+		} }, //GPD_11_GBEPHY
+};
+
+#endif /* _SKXSP_TP_GPIO_H_ */
diff --git a/src/mainboard/ocp/tiogapass/skxsp_tp_iio.h b/src/mainboard/ocp/tiogapass/skxsp_tp_iio.h
new file mode 100644
index 0000000..0ad92f2
--- /dev/null
+++ b/src/mainboard/ocp/tiogapass/skxsp_tp_iio.h
@@ -0,0 +1,101 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 - 2020 Intel Corporation.
+ * Copyright (C) 2019 - 2020 Facebook Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SKXSP_TP_IIO_H_
+#define _SKXSP_TP_IIO_H_
+
+#include <FspmUpd.h>
+#include <soc/pci_devs.h>
+
+/*
+ * Standard Tioga Pass Iio Bifurcation Table
+ * This is SS 2x16 config. As documented in OCP TP spec, there are
+ * 3 configs. SS 2x16 is the most common.
+ * TODO: figure out config through board SKU ID and through PCIe
+ * config GPIO setting (SLT_CFG0 / SLT_CFG1).
+ */
+static const UPD_IIO_BIFURCATION_DATA_ENTRY tp_iio_bifur_table[] = {
+	{ Iio_Socket0, Iio_Iou0, IIO_BIFURCATE_xxxxxx16 }, /* 1A x16 */
+	{ Iio_Socket0, Iio_Iou1, IIO_BIFURCATE_xxxxxx16 }, /* 2A x16 */
+	{ Iio_Socket0, Iio_Iou2, IIO_BIFURCATE_xxxxxx16 }, /* 3A x16 */
+	{ Iio_Socket0, Iio_Mcp0, IIO_BIFURCATE_xxxxxxxx }, /* No MCP */
+	{ Iio_Socket0, Iio_Mcp1, IIO_BIFURCATE_xxxxxxxx }, /* No MCP */
+	{ Iio_Socket1, Iio_Iou0, IIO_BIFURCATE_xxxxxxxx }, /* no IOU0 */
+	{ Iio_Socket1, Iio_Iou1, IIO_BIFURCATE_xxxxxxxx }, /* no IOU1 */
+	{ Iio_Socket1, Iio_Iou2, IIO_BIFURCATE_xxx8xxx8 }, /* 3A x8, 3C x8 */
+	{ Iio_Socket1, Iio_Mcp0, IIO_BIFURCATE_xxxxxxxx }, /* No MCP */
+	{ Iio_Socket1, Iio_Mcp1, IIO_BIFURCATE_xxxxxxxx }, /* No MCP */
+};
+
+/*
+ * Standard Tioga Pass Iio PCIe Port Table
+ */
+static const UPD_PCI_PORT_CONFIG tp_iio_pci_port_skt0[] = {
+	// PortIndex |  HidePort  | DeEmphasis | PortLinkSpeed | MaxPayload |
+	// DfxDnTxPreset | DfxRxPreset | DfxUpTxPreset | Sris | PcieCommonClock | NtbPpd |
+	// NtbSplitBar | NtbBarSizePBar23 | NtbBarSizePBar4 | NtbBarSizePBar5 |
+	// NtbBarSizePBar45 | NtbBarSizeSBar23 | NtbBarSizeSBar4 | NtbBarSizeSbar5 |
+	// NtbBarSizeSBar45 | NtbSBar01Prefetch | NtbXlinkCtlOverride
+	{ PORT_1A, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
+		NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
+		0x16, 0x00, 0x03 },
+	{ PORT_1B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
+		NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
+		0x16, 0x00, 0x03 },
+	{ PORT_1C, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
+		NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
+		0x16, 0x00, 0x03 },
+	{ PORT_1D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
+		NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
+		0x16, 0x00, 0x03 },
+	{ PORT_2A, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
+		NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
+		0x16, 0x00, 0x03 },
+	{ PORT_2B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
+		NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
+		0x16, 0x00, 0x03 },
+	{ PORT_2C, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
+		NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
+		0x16, 0x00, 0x03 },
+	{ PORT_2D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
+		NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
+		0x16, 0x00, 0x03 },
+	{ PORT_3A, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
+		NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
+		0x16, 0x00, 0x03 },
+	{ PORT_3B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
+		NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
+		0x16, 0x00, 0x03 },
+	{ PORT_3C, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
+		NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
+		0x16, 0x00, 0x03 },
+	{ PORT_3D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
+		NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
+		0x16, 0x00, 0x03 },
+};
+
+/*
+ * Standard Tioga Pass PCH PCIe Port Table
+ */
+static const UPD_PCH_PCIE_PORT tp_pch_pci_port_skt0[] = {
+	//PortIndex ; ForceEnable ; PortLinkSpeed
+	{ 0x00, 0x00, PcieAuto },
+	{ 0x04, 0x00, PcieAuto },
+	{ 0x05, 0x00, PcieAuto },
+};
+
+#endif /* _SKXSP_TP_IIO_H_ */

Change in coreboot[master]: mainboard/ocp: Add support for OCP platform TiogaPass

[9elements QA (Code Review)]

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38549 )

Change subject: mainboard/ocp: Add support for OCP platform TiogaPass
......................................................................

Patch Set 47:

Automatic boot test returned (PASS/FAIL/TOTAL): 3/0/3
Emulation targets:
EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/1144
EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1143
EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1142

Please note: This test is under development and might not be accurate at all!