253 comments:
File src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h:
Patch Set #2, Line 30: {GPIO_SKL_H_GPP_A0, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_A_0_LPC_RCIN_N_ESPI_ALERT1_N
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Patch Set #2, Line 31: {GPIO_SKL_H_GPP_A1, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_A_1_LAD_0_ESPI_IO_0
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Patch Set #2, Line 32: {GPIO_SKL_H_GPP_A2, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_A_2_LAD_1_ESPI_IO_1
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Patch Set #2, Line 33: {GPIO_SKL_H_GPP_A3, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_A_3_LAD_2_ESPI_IO_2
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Patch Set #2, Line 34: {GPIO_SKL_H_GPP_A4, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_A_4_LAD_3_ESPI_IO_3
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Patch Set #2, Line 35: {GPIO_SKL_H_GPP_A5, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_A_5_LPC_LFRAME_N_ESPI_CS0_N
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Patch Set #2, Line 36: {GPIO_SKL_H_GPP_A6, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_A_6_IRQ_LPC_SERIRQ_ESPI_CS1_N
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Patch Set #2, Line 37: {GPIO_SKL_H_GPP_A7, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_A_7_IRQ_LPC_PIRQA_N_ESPI_ALERT0_N
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Patch Set #2, Line 38: {GPIO_SKL_H_GPP_A8, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_A_8_FM_LPC_CLKRUN_N
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Patch Set #2, Line 39: {GPIO_SKL_H_GPP_A9, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_A_9_CLKOUT_LPC0_ESPI_CLK
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Patch Set #2, Line 40: {GPIO_SKL_H_GPP_A10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_A_10_CLKOUT_LPC1
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Patch Set #2, Line 41: {GPIO_SKL_H_GPP_A11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_A_11_FM_LPC_PME_N
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Patch Set #2, Line 42: {GPIO_SKL_H_GPP_A12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_A_12_BMBUSY_N_SXEXITHLDOFF_N
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Patch Set #2, Line 43: {GPIO_SKL_H_GPP_A13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_A_13_SUSWARN_N_SUSPWRDNACK
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Patch Set #2, Line 44: {GPIO_SKL_H_GPP_A14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_A_14_ESPI_RESET_N
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Patch Set #2, Line 45: {GPIO_SKL_H_GPP_A15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_A_15_SUSACK_N
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Patch Set #2, Line 46: {GPIO_SKL_H_GPP_A16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_A_16_CLKOUT_LPC2
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Patch Set #2, Line 47: {GPIO_SKL_H_GPP_A17, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_A_17
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Patch Set #2, Line 48: {GPIO_SKL_H_GPP_A18, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_A_18
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Patch Set #2, Line 50: {GPIO_SKL_H_GPP_A20, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_A_20
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Patch Set #2, Line 51: {GPIO_SKL_H_GPP_A21, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_A_21
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Patch Set #2, Line 52: {GPIO_SKL_H_GPP_A22, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_A_22
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Patch Set #2, Line 53: {GPIO_SKL_H_GPP_A23, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_A_23
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Patch Set #2, Line 55: {GPIO_SKL_H_GPP_B0, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_B_0_CORE_VID_0
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Patch Set #2, Line 56: {GPIO_SKL_H_GPP_B1, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_B_1_CORE_VID_1
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Patch Set #2, Line 57: {GPIO_SKL_H_GPP_B2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_B_2_VRALERT_N
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Patch Set #2, Line 58: {GPIO_SKL_H_GPP_B3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_B_3_CPU_GP2
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Patch Set #2, Line 59: {GPIO_SKL_H_GPP_B4, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_B_4_CPU_GP3
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Patch Set #2, Line 60: {GPIO_SKL_H_GPP_B5, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_B_5_SRCCLKREQ0_N
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Patch Set #2, Line 61: {GPIO_SKL_H_GPP_B6, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_B_6_SRCCLKREQ1_N
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Patch Set #2, Line 62: {GPIO_SKL_H_GPP_B7, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_B_7_SRCCLKREQ2_N
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Patch Set #2, Line 63: {GPIO_SKL_H_GPP_B8, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_B_8_SRCCLKREQ3_N
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Patch Set #2, Line 64: {GPIO_SKL_H_GPP_B9, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_B_9_SRCCLKREQ4_N
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Patch Set #2, Line 65: {GPIO_SKL_H_GPP_B10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_B_10_SRCCLKREQ5_N
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Patch Set #2, Line 66: {GPIO_SKL_H_GPP_B11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_B_11
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Patch Set #2, Line 67: {GPIO_SKL_H_GPP_B12, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_B_12_GLB_RST_WARN_N
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Patch Set #2, Line 68: {GPIO_SKL_H_GPP_B13, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_B_13_RST_PLTRST_N
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Patch Set #2, Line 69: {GPIO_SKL_H_GPP_B14, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_B_14_FM_PCH_BIOS_RCVR_SPKR
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Patch Set #2, Line 70: {GPIO_SKL_H_GPP_B15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_B_15
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Patch Set #2, Line 71: {GPIO_SKL_H_GPP_B16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_B_16
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Patch Set #2, Line 72: {GPIO_SKL_H_GPP_B17, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_B_17
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Patch Set #2, Line 73: {GPIO_SKL_H_GPP_B18, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_B_18
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Patch Set #2, Line 74: {GPIO_SKL_H_GPP_B19, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_B_19
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Patch Set #2, Line 75: {GPIO_SKL_H_GPP_B20, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_B_20
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Patch Set #2, Line 76: {GPIO_SKL_H_GPP_B21, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_B_21
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Patch Set #2, Line 77: {GPIO_SKL_H_GPP_B22, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_B_22
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Patch Set #2, Line 78: {GPIO_SKL_H_GPP_B23, { GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock} }, //GPP_B_23_MEIE_SML1ALRT_N_PHOT_N
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Patch Set #2, Line 82: {GPIO_SKL_H_GPP_C2, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_2_SMBALERT_N
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Patch Set #2, Line 85: {GPIO_SKL_H_GPP_C5, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock} }, //GPP_C_5_SML0ALERT_IE_N
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Patch Set #2, Line 88: {GPIO_SKL_H_GPP_C8, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_8
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Patch Set #2, Line 89: {GPIO_SKL_H_GPP_C9, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_9
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Patch Set #2, Line 90: {GPIO_SKL_H_GPP_C10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_C_10
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Patch Set #2, Line 91: {GPIO_SKL_H_GPP_C11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_11
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Patch Set #2, Line 92: {GPIO_SKL_H_GPP_C12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_12
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Patch Set #2, Line 93: {GPIO_SKL_H_GPP_C13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_13
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Patch Set #2, Line 94: {GPIO_SKL_H_GPP_C14, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_C_14
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Patch Set #2, Line 95: {GPIO_SKL_H_GPP_C15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_15
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Patch Set #2, Line 96: {GPIO_SKL_H_GPP_C16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_16
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Patch Set #2, Line 97: {GPIO_SKL_H_GPP_C17, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_17
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Patch Set #2, Line 98: {GPIO_SKL_H_GPP_C18, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_18
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Patch Set #2, Line 99: {GPIO_SKL_H_GPP_C19, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_19
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Patch Set #2, Line 101: {GPIO_SKL_H_GPP_C21, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_21
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Patch Set #2, Line 102: {GPIO_SKL_H_GPP_C22, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntSmi, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_C_22
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Patch Set #2, Line 103: {GPIO_SKL_H_GPP_C23, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntSmi, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_C_23
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Patch Set #2, Line 105: {GPIO_SKL_H_GPP_D0, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntSmi, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_D_0
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Patch Set #2, Line 106: {GPIO_SKL_H_GPP_D1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_1
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Patch Set #2, Line 107: {GPIO_SKL_H_GPP_D2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_D_2
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Patch Set #2, Line 108: {GPIO_SKL_H_GPP_D3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_D_3
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Patch Set #2, Line 109: {GPIO_SKL_H_GPP_D4, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_4
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Patch Set #2, Line 110: {GPIO_SKL_H_GPP_D5, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_5
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Patch Set #2, Line 111: {GPIO_SKL_H_GPP_D6, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_6
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Patch Set #2, Line 112: {GPIO_SKL_H_GPP_D7, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_7
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Patch Set #2, Line 113: {GPIO_SKL_H_GPP_D8, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_8
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Patch Set #2, Line 114: {GPIO_SKL_H_GPP_D9, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_9_SSATA_DEVSLP3
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Patch Set #2, Line 115: {GPIO_SKL_H_GPP_D10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_10_SSATA_DEVSLP4
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Patch Set #2, Line 116: {GPIO_SKL_H_GPP_D11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_11_SSATA_DEVSLP5
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Patch Set #2, Line 117: {GPIO_SKL_H_GPP_D12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_12_SSATA_SDATAOUT1
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Patch Set #2, Line 118: {GPIO_SKL_H_GPP_D13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_13_SML0BLCK_IE
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Patch Set #2, Line 119: {GPIO_SKL_H_GPP_D14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_14_SML0BDATA_IE
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Patch Set #2, Line 120: {GPIO_SKL_H_GPP_D15, { GpioPadModeNative3, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_15_SSATA_SDATAOUT0
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Patch Set #2, Line 121: {GPIO_SKL_H_GPP_D16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_16_SML0BALERT_IE_N
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Patch Set #2, Line 122: {GPIO_SKL_H_GPP_D17, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_17
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Patch Set #2, Line 123: {GPIO_SKL_H_GPP_D18, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_18
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Patch Set #2, Line 124: {GPIO_SKL_H_GPP_D19, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock | GpioOutputStateLock} }, //GPP_D_19
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Patch Set #2, Line 125: {GPIO_SKL_H_GPP_D20, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_20_TP_PCH_GPP_D_20
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Patch Set #2, Line 126: {GPIO_SKL_H_GPP_D21, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_21_IE_URAT_RX
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Patch Set #2, Line 127: {GPIO_SKL_H_GPP_D22, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_22_IE_URAT_TX
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Patch Set #2, Line 128: {GPIO_SKL_H_GPP_D23, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_D_23
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Patch Set #2, Line 130: {GPIO_SKL_H_GPP_E0, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntSmi, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_E_0_SATAXPCIE0_SATAGP0
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Patch Set #2, Line 131: {GPIO_SKL_H_GPP_E1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntSmi, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_E_1_SATAXPCIE1_SATAGP1
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Patch Set #2, Line 132: {GPIO_SKL_H_GPP_E2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_E_2_SATAXPCIE2_SATAGP2
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Patch Set #2, Line 133: {GPIO_SKL_H_GPP_E3, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_E_3_CPU_GP0
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Patch Set #2, Line 134: {GPIO_SKL_H_GPP_E4, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_E_4_SATA_DEVSLP0
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Patch Set #2, Line 135: {GPIO_SKL_H_GPP_E5, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_E_5_SATA_DEVSLP1
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Patch Set #2, Line 136: {GPIO_SKL_H_GPP_E6, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_E_6_SATA_DEVSLP2
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Patch Set #2, Line 137: {GPIO_SKL_H_GPP_E7, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_E_7_CPU_GP1
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Patch Set #2, Line 138: {GPIO_SKL_H_GPP_E8, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_E_8_SATA_LED_N
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Patch Set #2, Line 139: {GPIO_SKL_H_GPP_E9, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_E_9_USB2_OC0_N
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Patch Set #2, Line 140: {GPIO_SKL_H_GPP_E10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_E_10_USB2_OC1_N
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Patch Set #2, Line 141: {GPIO_SKL_H_GPP_E11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_E_11_USB2_OC2_N
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Patch Set #2, Line 142: {GPIO_SKL_H_GPP_E12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_E_12_USB2_OC3_N
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Patch Set #2, Line 144: {GPIO_SKL_H_GPP_F0, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_0_SATAXPCIE3_SATAGP3
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Patch Set #2, Line 145: {GPIO_SKL_H_GPP_F1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_1_SATAXPCIE4_SATAGP4
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Patch Set #2, Line 146: {GPIO_SKL_H_GPP_F2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_2_SATAXPCIE5_SATAGP5
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Patch Set #2, Line 147: {GPIO_SKL_H_GPP_F3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_3_SATAXPCIE6_SATAGP6
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Patch Set #2, Line 148: {GPIO_SKL_H_GPP_F4, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_4_SATAXPCIE7_SATAGP7
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Patch Set #2, Line 149: {GPIO_SKL_H_GPP_F5, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_5_SATA_DEVSLP3
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Patch Set #2, Line 150: {GPIO_SKL_H_GPP_F6, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_F_6_SATA_DEVSLP4
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Patch Set #2, Line 151: {GPIO_SKL_H_GPP_F7, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_F_7_SATA_DEVSLP5
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Patch Set #2, Line 152: {GPIO_SKL_H_GPP_F8, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_F_8_SATA_DEVSLP6
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Patch Set #2, Line 153: {GPIO_SKL_H_GPP_F9, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_F_9_SATA_DEVSLP7
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Patch Set #2, Line 154: {GPIO_SKL_H_GPP_F10, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_10_SATA_SCLOCK
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Patch Set #2, Line 155: {GPIO_SKL_H_GPP_F11, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_11_SATA_SLOAD
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Patch Set #2, Line 156: {GPIO_SKL_H_GPP_F12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_12_SATA_SDATAOUT1
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Patch Set #2, Line 157: {GPIO_SKL_H_GPP_F13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_13_SATA_SDATAOUT0
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Patch Set #2, Line 158: {GPIO_SKL_H_GPP_F14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_14_SSATA_LED_N
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Patch Set #2, Line 159: {GPIO_SKL_H_GPP_F15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_15_USB2_OC4_N
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Patch Set #2, Line 160: {GPIO_SKL_H_GPP_F16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_16_USB2_OC5_N
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Patch Set #2, Line 161: {GPIO_SKL_H_GPP_F17, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_17_USB2_OC6_N
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Patch Set #2, Line 162: {GPIO_SKL_H_GPP_F18, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_18_USB2_OC7_N
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Patch Set #2, Line 163: {GPIO_SKL_H_GPP_F19, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_19_LAN_SMBCLK
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Patch Set #2, Line 164: {GPIO_SKL_H_GPP_F20, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_20_LAN_SMBDATA
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Patch Set #2, Line 165: {GPIO_SKL_H_GPP_F21, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_21_LAN_SMBALERT_N
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Patch Set #2, Line 166: {GPIO_SKL_H_GPP_F22, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_22_SSATA_SCLOCK
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Patch Set #2, Line 167: {GPIO_SKL_H_GPP_F23, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_F_23_SSATA_SLOAD
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Patch Set #2, Line 169: {GPIO_SKL_H_GPP_G0, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_0_FANTACH0_FANTACH0IE
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Patch Set #2, Line 170: {GPIO_SKL_H_GPP_G1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_1_FANTACH1_FANTACH1IE
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Patch Set #2, Line 171: {GPIO_SKL_H_GPP_G2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_2_FANTACH2_FANTACH2IE
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Patch Set #2, Line 172: {GPIO_SKL_H_GPP_G3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_3_FANTACH3_FANTACH3IE
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Patch Set #2, Line 173: {GPIO_SKL_H_GPP_G4, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_4_FANTACH4_FANTACH4IE
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Patch Set #2, Line 174: {GPIO_SKL_H_GPP_G5, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_5_FANTACH5_FANTACH5IE
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Patch Set #2, Line 175: {GPIO_SKL_H_GPP_G6, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_6_FANTACH6_FANTACH6IE
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Patch Set #2, Line 176: {GPIO_SKL_H_GPP_G7, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_7_FANTACH7_FANTACH7IE
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Patch Set #2, Line 177: {GPIO_SKL_H_GPP_G8, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_8_FANPWM0_FANPWM0IE
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Patch Set #2, Line 178: {GPIO_SKL_H_GPP_G9, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_9_FANPWM1_FANPWM1IE
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Patch Set #2, Line 179: {GPIO_SKL_H_GPP_G10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_10_FANPWM2_FANPWM2IE
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Patch Set #2, Line 180: {GPIO_SKL_H_GPP_G11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_11_FANPWM3_FANPWM3IE
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Patch Set #2, Line 181: {GPIO_SKL_H_GPP_G12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_12
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Patch Set #2, Line 182: {GPIO_SKL_H_GPP_G13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_13
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Patch Set #2, Line 183: {GPIO_SKL_H_GPP_G14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_14
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Patch Set #2, Line 184: {GPIO_SKL_H_GPP_G15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_15
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Patch Set #2, Line 185: {GPIO_SKL_H_GPP_G16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_16
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Patch Set #2, Line 186: {GPIO_SKL_H_GPP_G17, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_17_ADR_COMPLETE
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Patch Set #2, Line 187: {GPIO_SKL_H_GPP_G18, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_18_FM_NMI_EVENT_N
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Patch Set #2, Line 188: {GPIO_SKL_H_GPP_G19, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_19_FM_SMI_ACTIVE_N
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Patch Set #2, Line 190: {GPIO_SKL_H_GPP_G21, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_21_SSATA_DEVSLP1
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Patch Set #2, Line 191: {GPIO_SKL_H_GPP_G22, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_22_SSATA_DEVSLP2
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Patch Set #2, Line 192: {GPIO_SKL_H_GPP_G23, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_G_23_SSATAXPCIE0_SSATAGP0
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Patch Set #2, Line 194: {GPIO_SKL_H_GPP_H0, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_H_0_SRCCLKREQ6_N
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Patch Set #2, Line 195: {GPIO_SKL_H_GPP_H1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_H_1_SRCCLKREQ7_N
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Patch Set #2, Line 196: {GPIO_SKL_H_GPP_H2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_H_2_SRCCLKREQ8_N
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Patch Set #2, Line 197: {GPIO_SKL_H_GPP_H3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_H_3_SRCCLKREQ9_N
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Patch Set #2, Line 198: {GPIO_SKL_H_GPP_H4, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_H_4_SRCCLKREQ10_N
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Patch Set #2, Line 200: {GPIO_SKL_H_GPP_H6, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_H_6_SRCCLKREQ12_N
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Patch Set #2, Line 201: {GPIO_SKL_H_GPP_H7, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_H_7_SRCCLKREQ13_N
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Patch Set #2, Line 202: {GPIO_SKL_H_GPP_H8, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_H_8_SRCCLKREQ14_N
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Patch Set #2, Line 203: {GPIO_SKL_H_GPP_H9, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_H_9_SRCCLKREQ15_N
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Patch Set #2, Line 206: {GPIO_SKL_H_GPP_H12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_H_12_SML2ALERT_N_IE
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Patch Set #2, Line 209: {GPIO_SKL_H_GPP_H15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_H_15_SML3ALERT_N_IE
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Patch Set #2, Line 212: {GPIO_SKL_H_GPP_H18, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_H_18_SML4ALERT_N_IE
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Patch Set #2, Line 213: {GPIO_SKL_H_GPP_H19, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone, GpioPadConfigLock} }, //GPP_H_19_SSATAXPCIE1_SSATAGP1
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Patch Set #2, Line 214: {GPIO_SKL_H_GPP_H20, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_H_20_SSATAXPCIE2_SSATAGP2
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Patch Set #2, Line 215: {GPIO_SKL_H_GPP_H21, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_H_21_SSATAXPCIE3_SSATAGP3
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Patch Set #2, Line 216: {GPIO_SKL_H_GPP_H22, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_H_22_SSATAXPCIE4_SSATAGP4
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Patch Set #2, Line 217: {GPIO_SKL_H_GPP_H23, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_H_23_SSATAXPCIE5_SSATAGP5
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Patch Set #2, Line 219: {GPIO_SKL_H_GPP_I0, { GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_I_0_GBE_TDO
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Patch Set #2, Line 220: {GPIO_SKL_H_GPP_I1, { GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_I_1_GBE_TCK
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Patch Set #2, Line 221: {GPIO_SKL_H_GPP_I2, { GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_I_2_GBE_TMS
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Patch Set #2, Line 222: {GPIO_SKL_H_GPP_I3, { GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_I_3_GBE_TDI
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Patch Set #2, Line 223: {GPIO_SKL_H_GPP_I4, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_I_4_DO_RESET_IN_N
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Patch Set #2, Line 224: {GPIO_SKL_H_GPP_I5, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_I_5_DO_RESET_OUT_N
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Patch Set #2, Line 225: {GPIO_SKL_H_GPP_I6, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_I_6_RESET_DONE
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Patch Set #2, Line 226: {GPIO_SKL_H_GPP_I7, { GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_I_7_JTAG_GBE_TRST_N
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Patch Set #2, Line 227: {GPIO_SKL_H_GPP_I8, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_I_8_GBE_PCI_DIS
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Patch Set #2, Line 228: {GPIO_SKL_H_GPP_I9, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_I_9_GBE_LAN_DIS
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Patch Set #2, Line 229: {GPIO_SKL_H_GPP_I10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_I_10
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Patch Set #2, Line 231: {GPIO_SKL_H_GPP_J0, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_J_0_LAN_LED_P0_0
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Patch Set #2, Line 232: {GPIO_SKL_H_GPP_J1, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_J_1_LAN_LED_P0_1
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Patch Set #2, Line 233: {GPIO_SKL_H_GPP_J2, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_J_2_LAN_LED_P1_0
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Patch Set #2, Line 234: {GPIO_SKL_H_GPP_J3, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_J_3_LAN_LED_P1_1
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Patch Set #2, Line 235: {GPIO_SKL_H_GPP_J4, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_J_4_LAN_LED_P2_0
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Patch Set #2, Line 236: {GPIO_SKL_H_GPP_J5, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_J_5_LAN_LED_P2_1
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Patch Set #2, Line 237: {GPIO_SKL_H_GPP_J6, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_J_6_LAN_LED_P3_0
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Patch Set #2, Line 238: {GPIO_SKL_H_GPP_J7, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_J_7_LAN_LED_P3_1
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Patch Set #2, Line 239: {GPIO_SKL_H_GPP_J8, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_J_8_LAN_I2C_SCL_MDC_P0
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Patch Set #2, Line 240: {GPIO_SKL_H_GPP_J9, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_J_9_LAN_I2C_SDA_MDIO_P0
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Patch Set #2, Line 241: {GPIO_SKL_H_GPP_J10, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_J_10_LAN_I2C_SCL_MDC_P1
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Patch Set #2, Line 242: {GPIO_SKL_H_GPP_J11, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_J_11_LAN_I2C_SDA_MDIO_P1
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Patch Set #2, Line 243: {GPIO_SKL_H_GPP_J12, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_J_12_LAN_I2C_SCL_MDC_P2
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Patch Set #2, Line 244: {GPIO_SKL_H_GPP_J13, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_J_13_LAN_I2C_SDA_MDIO_P2
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Patch Set #2, Line 245: {GPIO_SKL_H_GPP_J14, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_J_14_LAN_I2C_SCL_MDC_P3
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Patch Set #2, Line 246: {GPIO_SKL_H_GPP_J15, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_J_15_LAN_I2C_SDA_MDIO_P3
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Patch Set #2, Line 247: {GPIO_SKL_H_GPP_J16, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_J_16_LAN_SDP_P0_0
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Patch Set #2, Line 248: {GPIO_SKL_H_GPP_J17, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_J_17_LAN_SDP_P0_1
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Patch Set #2, Line 249: {GPIO_SKL_H_GPP_J18, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_J_18_LAN_SDP_P1_0
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Patch Set #2, Line 250: {GPIO_SKL_H_GPP_J19, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_J_19_LAN_SDP_P1_1
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Patch Set #2, Line 251: {GPIO_SKL_H_GPP_J20, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_J_20_LAN_SDP_P2_0
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Patch Set #2, Line 252: {GPIO_SKL_H_GPP_J21, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_J_21_LAN_SDP_P2_1
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Patch Set #2, Line 253: {GPIO_SKL_H_GPP_J22, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_J_22_LAN_SDP_P3_0
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Patch Set #2, Line 254: {GPIO_SKL_H_GPP_J23, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_J_23_LAN_SDP_P3_1
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Patch Set #2, Line 256: {GPIO_SKL_H_GPP_K0, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_K_0_LAN_NCSI_CLK_IN
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Patch Set #2, Line 257: {GPIO_SKL_H_GPP_K1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_K_1_LAN_NCSI_TXD0
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Patch Set #2, Line 258: {GPIO_SKL_H_GPP_K2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_K_2_LAN_NCSI_TXD1
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Patch Set #2, Line 259: {GPIO_SKL_H_GPP_K3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_K_3_LAN_NCSI_TX_EN
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Patch Set #2, Line 260: {GPIO_SKL_H_GPP_K4, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_K_4_LAN_NCSI_CRS_DV
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Patch Set #2, Line 261: {GPIO_SKL_H_GPP_K5, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_K_5_LAN_NCSI_RXD0
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Patch Set #2, Line 262: {GPIO_SKL_H_GPP_K6, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_K_6_LAN_NCSI_RXD1
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Patch Set #2, Line 263: {GPIO_SKL_H_GPP_K7, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_K_7
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Patch Set #2, Line 264: {GPIO_SKL_H_GPP_K8, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_K_8_LAN_NCSI_ARB_IN
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Patch Set #2, Line 265: {GPIO_SKL_H_GPP_K9, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_K_9_LAN_NCSI_ARB_OUT
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Patch Set #2, Line 266: {GPIO_SKL_H_GPP_K10, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_K_10_PE_RST_N
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Patch Set #2, Line 268: {GPIO_SKL_H_GPP_L2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_L_2_TESTCH0_D0
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Patch Set #2, Line 269: {GPIO_SKL_H_GPP_L3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_L_3_TESTCH0_D1
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Patch Set #2, Line 270: {GPIO_SKL_H_GPP_L4, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_L_4_TESTCH0_D2
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Patch Set #2, Line 271: {GPIO_SKL_H_GPP_L5, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_L_5_TESTCH0_D3
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Patch Set #2, Line 272: {GPIO_SKL_H_GPP_L6, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_L_6_TESTCH0_D4
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Patch Set #2, Line 273: {GPIO_SKL_H_GPP_L7, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_L_7_TESTCH0_D5
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Patch Set #2, Line 274: {GPIO_SKL_H_GPP_L8, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_L_8_TESTCH0_D6
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Patch Set #2, Line 275: {GPIO_SKL_H_GPP_L9, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_L_9_TESTCH0_D7
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Patch Set #2, Line 276: {GPIO_SKL_H_GPP_L10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_L_10_TESTCH0_CLK
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Patch Set #2, Line 277: {GPIO_SKL_H_GPP_L11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_L_11_TESTCH1_D0
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Patch Set #2, Line 278: {GPIO_SKL_H_GPP_L12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_L_12_TESTCH1_D1
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Patch Set #2, Line 279: {GPIO_SKL_H_GPP_L13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_L_13_TESTCH1_D2
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Patch Set #2, Line 280: {GPIO_SKL_H_GPP_L14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_L_14_TESTCH1_D3
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Patch Set #2, Line 281: {GPIO_SKL_H_GPP_L15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_L_15_TESTCH1_D4
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Patch Set #2, Line 282: {GPIO_SKL_H_GPP_L16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_L_16_TESTCH1_D5
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Patch Set #2, Line 283: {GPIO_SKL_H_GPP_L17, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_L_17_TESTCH1_D6
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Patch Set #2, Line 284: {GPIO_SKL_H_GPP_L18, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_L_18_TESTCH1_D7
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Patch Set #2, Line 285: {GPIO_SKL_H_GPP_L19, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone, GpioPadConfigLock} }, //GPP_L_19_TESTCH1_CLK
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Patch Set #2, Line 288: {GPIO_SKL_H_GPD1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock} }, //GPD_1_ACPRESENT
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Patch Set #2, Line 289: {GPIO_SKL_H_GPD2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock} }, //GPD_2_GBE_WAKE_N
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Patch Set #2, Line 290: {GPIO_SKL_H_GPD3, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock} }, //GPD_3_PWRBTNB_N
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Patch Set #2, Line 291: {GPIO_SKL_H_GPD4, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock} }, //GPD_4_SLP_S3B
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Patch Set #2, Line 292: {GPIO_SKL_H_GPD5, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock} }, //GPD_5_SLP_S4B
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Patch Set #2, Line 293: {GPIO_SKL_H_GPD6, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock} }, //GPD_6_SLPA_N
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Patch Set #2, Line 294: {GPIO_SKL_H_GPD7, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock} }, //GPD_7
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Patch Set #2, Line 295: {GPIO_SKL_H_GPD8, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock} }, //GPD_8_CLK_33K_PCH_SUSCLK_PLD
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Patch Set #2, Line 296: {GPIO_SKL_H_GPD9, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock} }, //GPD_9
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Patch Set #2, Line 297: {GPIO_SKL_H_GPD10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock} }, //GPD_10_FM_SLPS5_N
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Patch Set #2, Line 298: {GPIO_SKL_H_GPD11, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock} }, //GPD_11_GBEPHY
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File src/mainboard/ocp/tiogapass/skxsp_tp_iio.h:
Patch Set #2, Line 48: // PortIndex | HidePort | DeEmphasis | PortLinkSpeed | MaxPayload | DfxDnTxPreset | DfxRxPreset | DfxUpTxPreset | Sris | PcieCommonClock | NtbPpd | NtbSplitBar | NtbBarSizePBar23 | NtbBarSizePBar4 | NtbBarSizePBar5 | NtbBarSizePBar45 | NtbBarSizeSBar23 | NtbBarSizeSBar4 | NtbBarSizeSbar5 | NtbBarSizeSBar45 | NtbSBar01Prefetch | NtbXlinkCtlOverride
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Patch Set #2, Line 49: { PORT_1A, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
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Patch Set #2, Line 50: { PORT_1B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
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Patch Set #2, Line 51: { PORT_1C, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
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Patch Set #2, Line 52: { PORT_1D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
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Patch Set #2, Line 53: { PORT_2A, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
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Patch Set #2, Line 54: { PORT_2B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
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Patch Set #2, Line 55: { PORT_2C, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
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Patch Set #2, Line 56: { PORT_2D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
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Patch Set #2, Line 57: { PORT_3A, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
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Patch Set #2, Line 58: { PORT_3B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
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Patch Set #2, Line 59: { PORT_3C, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
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Patch Set #2, Line 60: { PORT_3D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x00, 0x03 },
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