coreboot-gerrit March 2020

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Change in coreboot[master]: [WIP] util/inteltool: add opt to override cores number

by Maxim Polyakov (Code Review)

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35919 ) Change subject: [WIP] util/inteltool: add opt to override cores number ...................................................................... [WIP] util/inteltool: add opt to override cores number In some cases, it is necessary to increase (if the server contains several processors) or decrease (dump should be more compact) the number of CPU cores for dump MSRs. Change-Id: I3a037cf7ac270d2b51d6e453334c358ff47b4105 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M util/inteltool/cpu.c M util/inteltool/inteltool.c M util/inteltool/inteltool.h 3 files changed, 15 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/35919/1 diff --git a/util/inteltool/cpu.c b/util/inteltool/cpu.c index f100851..9ae46c9 100644 --- a/util/inteltool/cpu.c +++ b/util/inteltool/cpu.c @@ -219,7 +219,7 @@ return error; } -int print_intel_core_msrs(void) +int print_intel_core_msrs(unsigned int cores_num) { unsigned int i, core, id; msr_t msr; @@ -2256,8 +2256,10 @@ close(fd_msr); - unsigned int max_core_limit = cpu->max_core_limit ? 8 : cpu->max_core_limit; - for (core = 0; core < max_core_limit; core++) { + if (!cores_num) + cores_num = cpu->max_core_limit; + + for (core = 0; core < cores_num; core++) { #ifndef __DARWIN__ char msrfilename[64]; memset(msrfilename, 0, 64); diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index db80bd2..bc9af2b 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -476,7 +476,7 @@ static void print_usage(const char *name) { - printf("usage: %s [-vh?gGrpmedPMaAsfSRx]\n", name); + printf("usage: %s [-vh?gGrpmedPMcaAsfSRx]\n", name); printf("\n" " -v | --version: print the version\n" " -h | --help: print this help\n\n" @@ -493,6 +493,7 @@ " -d | --dmibar: dump northbridge DMIBAR registers\n" " -P | --pciexpress: dump northbridge PCIEXBAR registers\n\n" " -M | --msrs: dump CPU MSRs\n" + " -c <num> | --cores <num>: override CPU cores number for MSR dump\n\n" " -A | --ambs: dump AMB registers\n" " -x | --sgx: dump SGX status\n" " -a | --all: dump all known (safe) registers\n" @@ -508,6 +509,7 @@ struct pci_dev *sb = NULL, *nb, *gfx = NULL, *ahci = NULL, *dev; const char *dump_spd_file = NULL; int opt, option_index = 0; + unsigned int cores = 0; unsigned int id, i; char *sbname = "unknown", *nbname = "unknown", *gfxname = "unknown"; @@ -532,6 +534,7 @@ {"dmibar", 0, 0, 'd'}, {"pciexpress", 0, 0, 'P'}, {"msrs", 0, 0, 'M'}, + {"cores", required_argument, 0, 'c'}, {"ambs", 0, 0, 'A'}, {"spi", 0, 0, 's'}, {"spd", 0, 0, 'S'}, @@ -543,7 +546,7 @@ {0, 0, 0, 0} }; - while ((opt = getopt_long(argc, argv, "vh?gGrpmedPMaAsfRS:x", + while ((opt = getopt_long(argc, argv, "vh?gGrpmedPMc:aAsfRS:x", long_options, &option_index)) != EOF) { switch (opt) { case 'v': @@ -587,6 +590,9 @@ case 'M': dump_coremsrs = 1; break; + case 'c': + cores = strtoul(optarg, NULL, 0); + break; case 'a': dump_gpios = 1; show_gpio_diffs = 1; @@ -813,7 +819,7 @@ } if (dump_coremsrs) { - print_intel_core_msrs(); + print_intel_core_msrs(cores); printf("\n\n"); } diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index fc6dc4b..7708d70 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -385,7 +385,7 @@ void unmap_physical(void *virt_addr, size_t len); unsigned int cpuid(unsigned int op); -int print_intel_core_msrs(void); +int print_intel_core_msrs(unsigned int cores_num); int print_mchbar(struct pci_dev *nb, struct pci_access *pacc, const char *dump_spd_file); int print_pmbase(struct pci_dev *sb, struct pci_access *pacc); int print_rcba(struct pci_dev *sb); -- To view, visit https://review.coreboot.org/c/coreboot/+/35919 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a037cf7ac270d2b51d6e453334c358ff47b4105 Gerrit-Change-Number: 35919 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

23 hours, 39 minutes

Change in coreboot[master]: mb/gigabyte: Add Gigabyte Z170X-Gaming 7

by Christoph Pomaska (Code Review)

Christoph Pomaska has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38920 ) Change subject: mb/gigabyte: Add Gigabyte Z170X-Gaming 7 ...................................................................... mb/gigabyte: Add Gigabyte Z170X-Gaming 7 Change-Id: Ib2c69bddd22cbd8f797dbb57370a4d8e5afa63bc --- A src/mainboard/gigabyte/ga-z170x-gaming7/Kconfig A src/mainboard/gigabyte/ga-z170x-gaming7/Kconfig.name A src/mainboard/gigabyte/ga-z170x-gaming7/Makefile.inc A src/mainboard/gigabyte/ga-z170x-gaming7/acpi/dptf.asl A src/mainboard/gigabyte/ga-z170x-gaming7/acpi/ec.asl A src/mainboard/gigabyte/ga-z170x-gaming7/acpi/mainboard.asl A src/mainboard/gigabyte/ga-z170x-gaming7/acpi/superio.asl A src/mainboard/gigabyte/ga-z170x-gaming7/board_info.txt A src/mainboard/gigabyte/ga-z170x-gaming7/cmos.default A src/mainboard/gigabyte/ga-z170x-gaming7/cmos.layout A src/mainboard/gigabyte/ga-z170x-gaming7/devicetree.cb A src/mainboard/gigabyte/ga-z170x-gaming7/dsdt.asl A src/mainboard/gigabyte/ga-z170x-gaming7/gma-mainboard.ads A src/mainboard/gigabyte/ga-z170x-gaming7/gpio.h A src/mainboard/gigabyte/ga-z170x-gaming7/hda_verb.c A src/mainboard/gigabyte/ga-z170x-gaming7/include/gpio.h A src/mainboard/gigabyte/ga-z170x-gaming7/mainboard.c A src/mainboard/gigabyte/ga-z170x-gaming7/ramstage.c A src/mainboard/gigabyte/ga-z170x-gaming7/romstage.c 19 files changed, 1,704 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/38920/1 diff --git a/src/mainboard/gigabyte/ga-z170x-gaming7/Kconfig b/src/mainboard/gigabyte/ga-z170x-gaming7/Kconfig new file mode 100644 index 0000000..3218b39 --- /dev/null +++ b/src/mainboard/gigabyte/ga-z170x-gaming7/Kconfig @@ -0,0 +1,49 @@ +if BOARD_GIGABYTE_GA_Z170X_GAMING_7 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select INTEL_GMA_HAVE_VBT + select INTEL_INT15 + select SOC_INTEL_KABYLAKE + select SKYLAKE_SOC_PCH_H + select SUPERIO_ITE_IT8528E # board has actually IT8628E + +config IRQ_SLOT_COUNT + int + default 18 + +config MAINBOARD_DIR + string + default "gigabyte/ga-z170x-gaming7" + +config MAINBOARD_PART_NUMBER + string + default "Z170X-Gaming 7" + +config MAX_CPUS + int + default 8 + +config DEVICETREE + string + default "devicetree.cb" + +config PRERAM_CBMEM_CONSOLE_SIZE + hex + default 0xd00 + +config DIMM_SPD_SIZE + int + default 512 #DDR4 + +# This is overridden if CMOS is used for configuration values. +config MAINBOARD_POWER_ON_AFTER_POWER_FAIL + bool + default n + +endif diff --git a/src/mainboard/gigabyte/ga-z170x-gaming7/Kconfig.name b/src/mainboard/gigabyte/ga-z170x-gaming7/Kconfig.name new file mode 100644 index 0000000..a0ff2d5 --- /dev/null +++ b/src/mainboard/gigabyte/ga-z170x-gaming7/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_GIGABYTE_Z170X_GAMING_7 + bool "GA-Z170X-Gaming 7" diff --git a/src/mainboard/gigabyte/ga-z170x-gaming7/Makefile.inc b/src/mainboard/gigabyte/ga-z170x-gaming7/Makefile.inc new file mode 100644 index 0000000..223820e --- /dev/null +++ b/src/mainboard/gigabyte/ga-z170x-gaming7/Makefile.inc @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## Copyright (C) 2016 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-y += mainboard.c +ramstage-y += ramstage.c +ramstage-y += hda_verb.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/gigabyte/ga-z170x-gaming7/acpi/dptf.asl b/src/mainboard/gigabyte/ga-z170x-gaming7/acpi/dptf.asl new file mode 100644 index 0000000..4453f3b --- /dev/null +++ b/src/mainboard/gigabyte/ga-z170x-gaming7/acpi/dptf.asl @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * Copyright (C) 2019 Maxim Polyakov <max.senia.poliak(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 98 +#define DPTF_CPU_CRITICAL 125 +#define DPTF_CPU_ACTIVE_AC0 91 +#define DPTF_CPU_ACTIVE_AC1 85 +#define DPTF_CPU_ACTIVE_AC2 83 +#define DPTF_CPU_ACTIVE_AC3 80 +#define DPTF_CPU_ACTIVE_AC4 75 + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 }, + +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 10000, /* PowerLimitMinimum */ + 31000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 28000, /* TimeWindowMaximum */ + 100 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 15000, /* PowerLimitMinimum */ + 65000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 28000, /* TimeWindowMaximum */ + 100 /* StepSize */ + } +}) + +/* Include DPTF */ +#include <soc/intel/skylake/acpi/dptf/dptf.asl> diff --git a/src/mainboard/gigabyte/ga-z170x-gaming7/acpi/ec.asl b/src/mainboard/gigabyte/ga-z170x-gaming7/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/gigabyte/ga-z170x-gaming7/acpi/ec.asl diff --git a/src/mainboard/gigabyte/ga-z170x-gaming7/acpi/mainboard.asl b/src/mainboard/gigabyte/ga-z170x-gaming7/acpi/mainboard.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/gigabyte/ga-z170x-gaming7/acpi/mainboard.asl diff --git a/src/mainboard/gigabyte/ga-z170x-gaming7/acpi/superio.asl b/src/mainboard/gigabyte/ga-z170x-gaming7/acpi/superio.asl new file mode 100644 index 0000000..8b13789 --- /dev/null +++ b/src/mainboard/gigabyte/ga-z170x-gaming7/acpi/superio.asl @@ -0,0 +1 @@ + diff --git a/src/mainboard/gigabyte/ga-z170x-gaming7/board_info.txt b/src/mainboard/gigabyte/ga-z170x-gaming7/board_info.txt new file mode 100644 index 0000000..c6b7655 --- /dev/null +++ b/src/mainboard/gigabyte/ga-z170x-gaming7/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.gigabyte.com/Motherboard/GA-Z170X-Gaming-7-rev-10 +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2015 diff --git a/src/mainboard/gigabyte/ga-z170x-gaming7/cmos.default b/src/mainboard/gigabyte/ga-z170x-gaming7/cmos.default new file mode 100644 index 0000000..3296093 --- /dev/null +++ b/src/mainboard/gigabyte/ga-z170x-gaming7/cmos.default @@ -0,0 +1,4 @@ +boot_option=Fallback +debug_level=Debug +power_on_after_fail=Disable +nmi=Enable diff --git a/src/mainboard/gigabyte/ga-z170x-gaming7/cmos.layout b/src/mainboard/gigabyte/ga-z170x-gaming7/cmos.layout new file mode 100644 index 0000000..916db62 --- /dev/null +++ b/src/mainboard/gigabyte/ga-z170x-gaming7/cmos.layout @@ -0,0 +1,125 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2016 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +#392 3 r 0 unused +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# coreboot config options: bootloader +#Used by ChromeOS: +416 128 r 0 vbnv +#544 440 r 0 unused + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/gigabyte/ga-z170x-gaming7/devicetree.cb b/src/mainboard/gigabyte/ga-z170x-gaming7/devicetree.cb new file mode 100644 index 0000000..29fbd71 --- /dev/null +++ b/src/mainboard/gigabyte/ga-z170x-gaming7/devicetree.cb @@ -0,0 +1,439 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2017 Intel Corporation. +## Copyright (C) 2019 Maxim Polyakov <max.senia.poliak(a)gmail.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip soc/intel/skylake + + register "deep_s3_enable_ac" = "0" + register "deep_s3_enable_dc" = "0" + register "deep_s5_enable_ac" = "0" + register "deep_s5_enable_dc" = "0" + register "deep_sx_config" = "DSX_EN_WAKE_PIN" + + register "eist_enable" = "1" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_B" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + # Set @0x280-0x2ff I/O Range for SuperIO HWM + register "gen1_dec" = "0x00fc0201" + register "gen2_dec" = "0x007c0a01" + register "gen3_dec" = "0x000c0081" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # Enable DPTF + register "dptf_enable" = "1" + + # FSP Configuration + register "SmbusEnable" = "1" + register "ScsEmmcEnabled" = "0" + register "ScsEmmcHs400Enabled" = "0" + register "ScsSdCardEnabled" = "0" + register "HeciEnabled" = "0" + register "SkipExtGfxScan" = "0" + register "PrimaryDisplay" = "Display_PEG" + register "Device4Enable" = "1" + register "SaGv" = "SaGv_Enabled" + register "PmTimerDisabled" = "0" + register "EnableAzalia" = "1" + register "DspEnable" = "0" + register "PchHdaVcType" = "Vc1" + + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + # Set LPC Serial IRQ mode + register "serirq_mode" = "SERIRQ_CONTINUOUS" + + # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch + # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s + register "PmConfigSlpS3MinAssert" = "0x02" + + # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s + register "PmConfigSlpS4MinAssert" = "0x04" + + # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s + register "PmConfigSlpSusMinAssert" = "0x03" + + # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s + register "PmConfigSlpAMinAssert" = "0x03" + + # VR Settings Configuration + #+----------------+-------+-------+-------------+-------+ + #| Domain/Setting | SA | IA | GT Unsliced | GT | + #+----------------+-------+-------+-------------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax* | 0 | 0 | 0 | 0 | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #+----------------+-------+-------+-------------+-------+ + # * - is set automatically in the vr_config.c + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = VR_CFG_AMP(20), \ + .psi2threshold = VR_CFG_AMP(4), \ + .psi3threshold = VR_CFG_AMP(1), \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x0, \ + .voltage_limit = 1520 \ + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = VR_CFG_AMP(20), \ + .psi2threshold = VR_CFG_AMP(5), \ + .psi3threshold = VR_CFG_AMP(1), \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x0, \ + .voltage_limit = 1520 \ + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = VR_CFG_AMP(20), \ + .psi2threshold = VR_CFG_AMP(5), \ + .psi3threshold = VR_CFG_AMP(1), \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x0 ,\ + .voltage_limit = 1520 \ + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = VR_CFG_AMP(20), \ + .psi2threshold = VR_CFG_AMP(5), \ + .psi3threshold = VR_CFG_AMP(1), \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x0, \ + .voltage_limit = 1520 \ + }" + + register "EnableLan" = "1" + register "PmTimerDisabled" = "0" + + # USB + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[2]" = "USB2_PORT_MID(OC4)" + register "usb2_ports[3]" = "USB2_PORT_MID(OC4)" + register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" + register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" + register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[8]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[9]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[10]" = "USB2_PORT_MID(OC1)" + register "usb2_ports[11]" = "USB2_PORT_MID(OC1)" + register "usb2_ports[12]" = "USB2_PORT_MID(OC_SKIP)" + register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)" + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)" + register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC_SKIP)" + + # SATA + register "EnableSata" = "1" + register "SataSalpSupport" = "1" + register "SataPortsEnable" = "{ \ + [0] = 1, \ + [1] = 1, \ + [2] = 1, \ + [3] = 1, \ + [4] = 0, \ + [5] = 0, \ + }" + # SATA4 and SATA5 are located in the lower right corner + # of the board, but there is no connector for this + + # PCH UART, SPI, I2C + register "SerialIoDevMode" = "{ \ + [PchSerialIoIndexI2C0] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \ + [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \ + [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart0] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart2] = PchSerialIoDisabled, \ + }" + + # Set params for PEG 0:1:0 + register "Peg0MaxLinkWidth" = "Peg0_x16" + # Configure PCIe clockgen in PCH + # PEG0 uses SRCCLKREQ0 and CLKSRC0 + register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqNumber[0]" = "0" + register "PcieRpClkSrcNumber[0]" = "0" + + # Enable Root port 6(x1) for LAN. + register "PcieRpEnable[5]" = "1" + # Disable CLKREQ#, since onboard LAN is always present + register "PcieRpClkReqSupport[5]" = "0" + # Enable Advanced Error Reporting + register "PcieRpAdvancedErrorReporting[5]" = "1" + # Enable Latency Tolerance Reporting Mechanism + register "PcieRpLtrEnable[5]" = "1" + # Use CLK SRC 1 + register "PcieRpClkSrcNumber[5]" = "1" + + # Enable Root port 5 (x1) for PCIE slot. + register "PcieRpEnable[4]" = "1" + # Enable CLKREQ# + register "PcieRpClkReqSupport[4]" = "1" + # Use SRCCLKREQ2# + register "PcieRpClkReqNumber[4]" = "2" + # Enable Advanced Error Reporting + register "PcieRpAdvancedErrorReporting[4]" = "1" + # Enable Latency Tolerance Reporting Mechanism + register "PcieRpLtrEnable[4]" = "1" + # Use CLK SRC 2 + register "PcieRpClkSrcNumber[4]" = "2" + # Use Hot Plug subsystem + register "PcieRpHotPlug[4]" = "1" + + # Enable Root port 7(x1) for PCIE slot. + register "PcieRpEnable[6]" = "1" + # Enable CLKREQ# + register "PcieRpClkReqSupport[6]" = "1" + # Use SRCCLKREQ3# + register "PcieRpClkReqNumber[6]" = "3" + # Enable Advanced Error Reporting + register "PcieRpAdvancedErrorReporting[6]" = "1" + # Enable Latency Tolerance Reporting Mechanism + register "PcieRpLtrEnable[6]" = "1" + # Use CLK SRC 3 + register "PcieRpClkSrcNumber[6]" = "3" + # Use Hot Plug subsystem + register "PcieRpHotPlug[6]" = "1" + + # PL2 override 95W + register "tdp_pl2_override" = "95" + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on # Host Bridge + subsystemid 0x1849 0x191f + end + device pci 01.0 on # PEG + subsystemid 0x1849 0x1901 + end + device pci 02.0 on # Integrated Graphics Device + subsystemid 0x1849 0x1912 + end + device pci 14.0 on # USB xHCI + subsystemid 0x1849 0xa131 + end + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 off # Thermal Subsystem + #subsystemid 0x1849 0xa131 + end + device pci 15.0 off end # I2C #0 + device pci 15.1 off end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x1849 0xa131 + end + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 on # SATA + subsystemid 0x1b21 0x0612 + end + device pci 19.0 off end # UART #2 + device pci 19.1 off end # I2C #5 + device pci 19.2 off end # I2C #4 + device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.1 on end # PCI Express Port 2 + device pci 1c.2 on # Qualcomm Atheros Killer E2400 Gigabit Ethernet Controller + subsystemid 0x1969 0xe0a1 + off + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 on end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 off end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1e.0 off end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1e.4 off end # eMMC + device pci 1e.5 off end # SDIO + device pci 1e.6 off end # SDCard + device pci 1f.0 on # LPC bridge + subsystemid 0x1849 0x1a43 + + chip superio/common + device pnp 2e.0 on # passes SIO base addr to SSDT gen + + chip superio/nuvoton/nct6791d + device pnp 2e.1 on + # Global Control Registers + # Device IRQ Polarity + irq 0x13 = 0x00 + irq 0x14 = 0x00 + # Global Option + irq 0x24 = 0xfb + irq 0x27 = 0x10 + # Multi Function + irq 0x1a = 0xb0 + irq 0x1b = 0xe6 + irq 0x2a = 0x04 + irq 0x2c = 0x40 + irq 0x2d = 0x03 + + # Parallel Port + io 0x60 = 0x0378 + irq 0x70 = 7 + drq 0x74 = 4 # No DMA + irq 0xf0 = 0x3c # Printer mode + end + device pnp 2e.2 on # UART A + io 0x60 = 0x03f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # IR + io 0x60 = 0x02f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 KBC + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 # Keyboard + irq 0x72 = 12 # Mouse + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 on # GPIO6 + irq 0xf6 = 0xff + irq 0xf7 = 0xff + irq 0xf8 = 0xff + end + device pnp 2e.107 on # GPIO7 + irq 0xe0 = 0x7f + irq 0xe1 = 0x0d + end + device pnp 2e.207 on # GPIO8 + irq 0xe6 = 0xff + irq 0xe7 = 0xff + irq 0xed = 0xff + end + device pnp 2e.8 off end # WDT + device pnp 2e.108 on end # GPIO0 + device pnp 2e.308 off end # GPIO base + device pnp 2e.408 off end # WDTMEM + device pnp 2e.708 on end # GPIO1 + device pnp 2e.9 on end # GPIO2 + device pnp 2e.109 on # GPIO3 + irq 0xe4 = 0x7b + irq 0xe5 = 0x02 + irq 0xea = 0x04 + end + device pnp 2e.209 on # GPIO4 + irq 0xf0 = 0x7f + irq 0xf1 = 0x80 + end + device pnp 2e.309 on # GPIO5 + irq 0xf4 = 0xdf + irq 0xf5 = 0xd5 + end + device pnp 2e.a on + # Power RAM in S3 and let the PCH + # handle power failure actions + irq 0xe4 = 0x70 + # Set HWM reset source to LRESET# + irq 0xe7 = 0x01 + end # ACPI + device pnp 2e.b on # HWM, LED + io 0x60 = 0x0290 + io 0x62 = 0 + irq 0x70 = 0 + end + device pnp 2e.d off end # BCLK, WDT2, WDT_MEM + device pnp 2e.e off end # CIR wake-up + device pnp 2e.f off end # GPIO PP/OD + device pnp 2e.14 off end # SVID, Port 80 UART + device pnp 2e.16 off end # DS5 + device pnp 2e.116 off end # DS3 + device pnp 2e.316 on end # PCHDSW + device pnp 2e.416 off end # DSWWOPT + device pnp 2e.516 on end # DS3OPT + device pnp 2e.616 on end # DSDSS + device pnp 2e.716 off end # DSPU + end # chip superio/nuvoton/nct6791d + + end # device pnp 2e.0 + end # chip superio/common + + chip drivers/pc80/tpm + device pnp 4e.0 on end # TPM module + end + end # LPC Interface + device pci 1f.1 off end + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 on end # GbE + end +end diff --git a/src/mainboard/gigabyte/ga-z170x-gaming7/dsdt.asl b/src/mainboard/gigabyte/ga-z170x-gaming7/dsdt.asl new file mode 100644 index 0000000..1f3537e --- /dev/null +++ b/src/mainboard/gigabyte/ga-z170x-gaming7/dsdt.asl @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2016 Intel Corporation + * Copyright (C) 2019 Maxim Polyakov <max.senia.poliak(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + #include <soc/intel/skylake/acpi/platform.asl> + + // global NVS and variables + #include <soc/intel/skylake/acpi/globalnvs.asl> + + // CPU + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + /* Image processing unit */ + #include <soc/intel/skylake/acpi/ipu.asl> + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + + // Dynamic Platform Thermal Framework + #include "acpi/dptf.asl" + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> + + // Mainboard specific + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/gigabyte/ga-z170x-gaming7/gma-mainboard.ads b/src/mainboard/gigabyte/ga-z170x-gaming7/gma-mainboard.ads new file mode 100644 index 0000000..86a3a62 --- /dev/null +++ b/src/mainboard/gigabyte/ga-z170x-gaming7/gma-mainboard.ads @@ -0,0 +1,32 @@ +-- +-- This file is part of the coreboot project. +-- +-- Copyright (C) 2018 Tristan Corrick <tristan(a)corrick.kiwi> +-- Copyright (C) 2019 Maxim Polyakov <max.senia.poliak(a)gmail.com> +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, -- mainboard DVI port + HDMI3, -- mainboard HDMI port + Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/gigabyte/ga-z170x-gaming7/gpio.h b/src/mainboard/gigabyte/ga-z170x-gaming7/gpio.h new file mode 100644 index 0000000..8417dee --- /dev/null +++ b/src/mainboard/gigabyte/ga-z170x-gaming7/gpio.h @@ -0,0 +1,235 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Christoph Pomaska + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +#ifndef __ACPI__ + +/* Pad configuration in ramstage. */ +static const struct pad_config gpio_table[] = { + PAD_CFG_NF(GPD0, NONE, PWROK, NF1), + PAD_CFG_TERM_GPO(GPD1, 0, NONE, PWROK), + _PAD_CFG_STRUCT(GPD2, 0x00080500, 0x3c00), + PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), + PAD_CFG_NF(GPD6, NONE, PWROK, NF1), + PAD_CFG_TERM_GPO(GPD7, 1, NONE, PWROK), + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), + PAD_CFG_NF(GPD9, NONE, PWROK, NF1), + PAD_CFG_NF(GPD10, NONE, PWROK, NF1), + PAD_CFG_NF(GPD11, NONE, PWROK, NF1), + PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A8, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPP_A10, DN_20K, PLTRST, NF1), + PAD_CFG_NF(GPP_A11, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF3), + PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), + PAD_NC(GPP_A16, NONE), + PAD_NC(GPP_A17, NONE), + PAD_CFG_NF(GPP_A18, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_A19, NONE, PLTRST, NF1), + PAD_NC(GPP_A20, NONE), + PAD_CFG_TERM_GPO(GPP_A21, 1, NONE, DEEP), + PAD_CFG_TERM_GPO(GPP_A22, 1, NONE, DEEP), + _PAD_CFG_STRUCT(GPP_A23, 0x40100100, 0x0000), + PAD_CFG_TERM_GPO(GPP_B0, 0, NONE, DEEP), + PAD_CFG_TERM_GPO(GPP_B1, 0, NONE, DEEP), + PAD_NC(GPP_B2, NONE), + PAD_NC(GPP_B3, NONE), + PAD_CFG_TERM_GPO(GPP_B4, 0, NONE, PLTRST), + PAD_NC(GPP_B5, NONE), + PAD_NC(GPP_B6, NONE), + PAD_NC(GPP_B7, NONE), + PAD_NC(GPP_B8, NONE), + PAD_NC(GPP_B9, NONE), + PAD_NC(GPP_B10, NONE), + PAD_CFG_TERM_GPO(GPP_B11, 0, NONE, DEEP), + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B14, DN_20K, PLTRST, NF1), + PAD_CFG_TERM_GPO(GPP_B15, 0, NONE, PLTRST), + PAD_NC(GPP_B16, NONE), + PAD_CFG_TERM_GPO(GPP_B17, 1, NONE, DEEP), + PAD_CFG_TERM_GPO(GPP_B18, 0, NONE, DEEP), + PAD_CFG_TERM_GPO(GPP_B19, 0, NONE, PLTRST), + PAD_CFG_NF(GPP_B20, DN_20K, PLTRST, NF1), + PAD_CFG_NF(GPP_B21, DN_20K, PLTRST, NF1), + PAD_CFG_NF(GPP_B22, DN_20K, PLTRST, NF1), + _PAD_CFG_STRUCT(GPP_B23, 0x84000a01, 0x1000), + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + PAD_CFG_TERM_GPO(GPP_C2, 1, NONE, DEEP), + PAD_CFG_NF(GPP_C3, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + PAD_CFG_TERM_GPO(GPP_C5, 0, NONE, DEEP), + _PAD_CFG_STRUCT(GPP_C6, 0xfffffffd, 0xffffff00), + _PAD_CFG_STRUCT(GPP_C7, 0xfffffffd, 0xffffff00), + PAD_NC(GPP_C8, NONE), + PAD_NC(GPP_C9, NONE), + PAD_NC(GPP_C10, NONE), + PAD_NC(GPP_C11, NONE), + PAD_NC(GPP_C12, NONE), + PAD_NC(GPP_C13, NONE), + PAD_NC(GPP_C14, NONE), + PAD_NC(GPP_C15, NONE), + PAD_NC(GPP_C16, NONE), + PAD_NC(GPP_C17, NONE), + PAD_NC(GPP_C18, NONE), + PAD_CFG_TERM_GPO(GPP_C19, 0, NONE, PWROK), + PAD_CFG_TERM_GPO(GPP_C20, 0, NONE, PWROK), + PAD_CFG_TERM_GPO(GPP_C21, 0, NONE, PWROK), + _PAD_CFG_STRUCT(GPP_C22, 0x42840101, 0x0000), + PAD_NC(GPP_C23, NONE), + PAD_CFG_TERM_GPO(GPP_D0, 0, NONE, PWROK), + PAD_CFG_TERM_GPO(GPP_D1, 1, NONE, PWROK), + PAD_CFG_TERM_GPO(GPP_D2, 0, NONE, PWROK), + _PAD_CFG_STRUCT(GPP_D3, 0x82880101, 0x1000), + _PAD_CFG_STRUCT(GPP_D4, 0x42840101, 0x0000), + PAD_CFG_NF(GPP_D5, NONE, PLTRST, NF1), + PAD_CFG_TERM_GPO(GPP_D6, 0, NONE, PLTRST), + PAD_CFG_NF(GPP_D7, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_D8, NONE, PLTRST, NF1), + PAD_CFG_TERM_GPO(GPP_D9, 0, NONE, PWROK), + PAD_NC(GPP_D10, NONE), + PAD_NC(GPP_D11, NONE), + PAD_NC(GPP_D12, NONE), + PAD_NC(GPP_D13, NONE), + PAD_NC(GPP_D14, NONE), + PAD_NC(GPP_D15, NONE), + PAD_NC(GPP_D16, NONE), + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D21, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_D22, NONE, PLTRST, NF1), + PAD_NC(GPP_D23, NONE), + PAD_CFG_NF(GPP_E0, UP_20K, PLTRST, NF1), + PAD_CFG_NF(GPP_E1, UP_20K, PLTRST, NF1), + PAD_CFG_NF(GPP_E2, UP_20K, PLTRST, NF1), + PAD_NC(GPP_E3, NONE), + PAD_NC(GPP_E4, NONE), + _PAD_CFG_STRUCT(GPP_E5, 0x04000601, 0x0000), + PAD_CFG_NF(GPP_E6, NONE, PWROK, NF1), + PAD_NC(GPP_E7, NONE), + PAD_CFG_NF(GPP_E8, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F0, UP_20K, PLTRST, NF1), + PAD_CFG_NF(GPP_F1, UP_20K, PLTRST, NF1), + PAD_CFG_NF(GPP_F2, UP_20K, PLTRST, NF1), + PAD_NC(GPP_F3, NONE), + PAD_NC(GPP_F4, NONE), + PAD_CFG_TERM_GPO(GPP_F5, 1, NONE, PLTRST), + PAD_CFG_NF(GPP_F6, NONE, PWROK, NF1), + PAD_NC(GPP_F7, NONE), + PAD_NC(GPP_F8, NONE), + PAD_NC(GPP_F9, NONE), + PAD_CFG_GPI(GPP_F10, NONE, PLTRST), + PAD_NC(GPP_F11, NONE), + _PAD_CFG_STRUCT(GPP_F12, 0x80900100, 0x0000), + _PAD_CFG_STRUCT(GPP_F13, 0x80100100, 0x0000), + _PAD_CFG_STRUCT(GPP_F14, 0x40900100, 0x0000), + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), + PAD_NC(GPP_F17, NONE), + PAD_CFG_TERM_GPO(GPP_F18, 1, NONE, PLTRST), + PAD_CFG_NF(GPP_F19, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_F20, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_F21, NONE, PLTRST, NF1), + PAD_CFG_TERM_GPO(GPP_F22, 1, NONE, PLTRST), + PAD_CFG_TERM_GPO(GPP_F23, 1, NONE, PLTRST), + _PAD_CFG_STRUCT(GPP_G0, 0x84000101, 0x0000), + _PAD_CFG_STRUCT(GPP_G1, 0x84000101, 0x0000), + PAD_CFG_TERM_GPO(GPP_G2, 1, NONE, PLTRST), + PAD_NC(GPP_G3, NONE), + PAD_NC(GPP_G4, NONE), + PAD_CFG_TERM_GPO(GPP_G5, 1, NONE, PLTRST), + PAD_CFG_TERM_GPO(GPP_G6, 1, NONE, PLTRST), + PAD_CFG_TERM_GPO(GPP_G7, 1, NONE, DEEP), + PAD_CFG_NF(GPP_G8, NONE, DEEP, NF1), + PAD_CFG_GPI(GPP_G9, NONE, PLTRST), + PAD_CFG_GPI(GPP_G10, NONE, PLTRST), + PAD_CFG_NF(GPP_G11, NONE, DEEP, NF1), + PAD_CFG_TERM_GPO(GPP_G12, 1, NONE, PLTRST), + PAD_NC(GPP_G13, NONE), + PAD_CFG_TERM_GPO(GPP_G14, 1, NONE, PLTRST), + PAD_CFG_TERM_GPO(GPP_G15, 1, NONE, PLTRST), + PAD_CFG_TERM_GPO(GPP_G16, 0, DN_20K, PLTRST), + PAD_NC(GPP_G17, NONE), + PAD_CFG_TERM_GPO(GPP_G18, 1, NONE, PLTRST), + PAD_CFG_TERM_GPO(GPP_G19, 1, NONE, PLTRST), + PAD_CFG_TERM_GPO(GPP_G20, 1, NONE, PLTRST), + PAD_CFG_TERM_GPO(GPP_G21, 1, NONE, PLTRST), + PAD_CFG_TERM_GPO(GPP_G22, 1, NONE, PLTRST), + PAD_CFG_TERM_GPO(GPP_G23, 1, NONE, PLTRST), + PAD_NC(GPP_H0, NONE), + PAD_NC(GPP_H1, NONE), + PAD_NC(GPP_H2, NONE), + PAD_NC(GPP_H3, NONE), + PAD_NC(GPP_H4, NONE), + PAD_NC(GPP_H5, NONE), + PAD_NC(GPP_H6, NONE), + PAD_NC(GPP_H7, NONE), + PAD_NC(GPP_H8, NONE), + PAD_NC(GPP_H9, NONE), + PAD_NC(GPP_H10, NONE), + PAD_NC(GPP_H11, NONE), + PAD_CFG_TERM_GPO(GPP_H12, 0, NONE, DEEP), + _PAD_CFG_STRUCT(GPP_H13, 0x80100100, 0x0000), + _PAD_CFG_STRUCT(GPP_H14, 0x80100100, 0x0000), + _PAD_CFG_STRUCT(GPP_H15, 0x80100100, 0x0000), + PAD_CFG_TERM_GPO(GPP_H16, 1, NONE, PLTRST), + PAD_CFG_TERM_GPO(GPP_H17, 1, NONE, PLTRST), + PAD_NC(GPP_H18, NONE), + PAD_CFG_NF(GPP_H19, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_H20, NONE, PLTRST, NF1), + PAD_NC(GPP_H21, NONE), + PAD_NC(GPP_H22, NONE), + PAD_CFG_TERM_GPO(GPP_H23, 0, NONE, DEEP), + PAD_CFG_NF(GPP_I0, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I1, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I2, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I3, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I4, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I5, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I6, DN_20K, PLTRST, NF1), + PAD_CFG_NF(GPP_I7, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I8, DN_20K, PLTRST, NF1), + PAD_CFG_NF(GPP_I9, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I10, DN_20K, PLTRST, NF1), +}; + +#endif + +#endif + diff --git a/src/mainboard/gigabyte/ga-z170x-gaming7/hda_verb.c b/src/mainboard/gigabyte/ga-z170x-gaming7/hda_verb.c new file mode 100644 index 0000000..940c8fb --- /dev/null +++ b/src/mainboard/gigabyte/ga-z170x-gaming7/hda_verb.c @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Christoph Pomaska + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef HDA_VERB_H +#define HDA_VERB_H + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* Creative, Recon3Di */ + 0x11020011, /* Vendor ID */ + 0x1458a036, /* Subsystem ID */ + 11, /* Number of entries */ + AZALIA_SUBVENDOR(0, 0x1458a036), + AZALIA_PIN_CFG(0, 0x0b, 0x01014010), + AZALIA_PIN_CFG(0, 0x0c, 0x014580f0), + AZALIA_PIN_CFG(0, 0x0d, 0x014570f0), + AZALIA_PIN_CFG(0, 0x0e, 0x01c530f0), + AZALIA_PIN_CFG(0, 0x0f, 0x0221401f), + AZALIA_PIN_CFG(0, 0x10, 0x02216011), + AZALIA_PIN_CFG(0, 0x11, 0x02012014), + AZALIA_PIN_CFG(0, 0x12, 0x37a791f0), + AZALIA_PIN_CFG(0, 0x13, 0x908700f0), + AZALIA_PIN_CFG(0, 0x18, 0x500000f0), + /* Intel, SkylakeHDMI */ + 0x80862809, /* Vendor ID */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of entries */ + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_PIN_CFG(2, 0x05, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x07, 0x18560010), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; + +#endif diff --git a/src/mainboard/gigabyte/ga-z170x-gaming7/include/gpio.h b/src/mainboard/gigabyte/ga-z170x-gaming7/include/gpio.h new file mode 100644 index 0000000..0b33078 --- /dev/null +++ b/src/mainboard/gigabyte/ga-z170x-gaming7/include/gpio.h @@ -0,0 +1,508 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Maxim Polyakov <max.senia.poliak(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef _PCH_GPIO_H +#define _PCH_GPIO_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +/* Pad configuration in ramstage */ +static const struct pad_config gpio_table[] = { + /* ------- GPIO Group GPP_A ------- */ + /* GPP_A0 - RCIN# */ + PAD_CFG_NF_BUF_TRIG(GPP_A0, NONE, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_A1 - LAD0 */ + PAD_CFG_NF_BUF_TRIG(GPP_A1, 20K_PU, PLTRST, NF1, NO_DISABLE, OFF), + /* GPP_A2 - LAD1 */ + PAD_CFG_NF_BUF_TRIG(GPP_A2, 20K_PU, PLTRST, NF1, NO_DISABLE, OFF), + /* GPP_A3 - LAD2 */ + PAD_CFG_NF_BUF_TRIG(GPP_A3, 20K_PU, PLTRST, NF1, NO_DISABLE, OFF), + /* GPP_A4 - LAD3 */ + PAD_CFG_NF_BUF_TRIG(GPP_A4, 20K_PU, PLTRST, NF1, NO_DISABLE, OFF), + /* GPP_A5 - LFRAME# */ + PAD_CFG_NF_BUF_TRIG(GPP_A5, NONE, PLTRST, NF1, RX_DISABLE, OFF), + /* GPP_A6 - SERIRQ */ + PAD_CFG_NF_BUF_TRIG(GPP_A6, NONE, PLTRST, NF1, NO_DISABLE, OFF), + /* GPP_A7 - GPIO */ + PAD_CFG_GPI_INT(GPP_A7, NONE, PLTRST, OFF), + /* GPP_A8 - CLKRUN# */ + PAD_CFG_NF_BUF_TRIG(GPP_A8, NONE, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_A9 - CLKOUT_LPC0 */ + PAD_CFG_NF_BUF_TRIG(GPP_A9, 20K_PD, PLTRST, NF1, RX_DISABLE, OFF), + /* GPP_A10 - CLKOUT_LPC1 */ + PAD_CFG_NF_BUF_TRIG(GPP_A10, 20K_PD, PLTRST, NF1, RX_DISABLE, OFF), + /* GPP_A11 - GPIO */ + PAD_CFG_GPI_INT(GPP_A11, NONE, PLTRST, OFF), + /* GPP_A12 - GPIO */ + PAD_CFG_GPI_INT(GPP_A12, NONE, PLTRST, OFF), + /* GPP_A13 - SUSWARN#/SUSPWRDNACK */ + PAD_CFG_NF_BUF_TRIG(GPP_A13, NONE, DEEP, NF1, RX_DISABLE, OFF), + /* GPP_A14 - SUS_STAT# */ + PAD_CFG_NF_BUF_TRIG(GPP_A14, NONE, DEEP, NF1, RX_DISABLE, OFF), + /* GPP_A15 - SUS_ACK# */ + PAD_CFG_NF_BUF_TRIG(GPP_A15, 20K_PU, DEEP, NF1, TX_DISABLE, OFF), + /* GPP_A16 - GPIO */ + PAD_CFG_GPI_INT(GPP_A16, NONE, PLTRST, OFF), + /* GPP_A17 - GPIO */ + PAD_CFG_GPI_INT(GPP_A17, NONE, PLTRST, OFF), + /* GPP_A18 - GPIO */ + PAD_CFG_GPI_INT(GPP_A18, NONE, PLTRST, OFF), + /* GPP_A19 - GPIO */ + PAD_CFG_GPI_INT(GPP_A19, NONE, PLTRST, OFF), + /* GPP_A20 - GPIO */ + PAD_CFG_GPI_INT(GPP_A20, NONE, PLTRST, OFF), + /* GPP_A21 - GPIO */ + PAD_CFG_GPI_INT(GPP_A21, NONE, PLTRST, OFF), + /* GPP_A22 - GPIO */ + PAD_CFG_GPI_INT(GPP_A22, NONE, PLTRST, OFF), + /* GPP_A23 - GPIO */ + PAD_CFG_GPI_INT(GPP_A23, NONE, PLTRST, OFF), + + /* ------- GPIO Group GPP_B ------- */ + /* GPP_B0 - GPIO */ + PAD_CFG_GPI_INT(GPP_B0, NONE, PLTRST, OFF), + /* GPP_B1 - GPIO */ + PAD_CFG_GPI_INT(GPP_B1, NONE, PLTRST, OFF), + /* GPP_B2 - GPIO */ + PAD_CFG_GPI_INT(GPP_B2, NONE, PLTRST, OFF), + /* GPP_B3 - GPIO */ + PAD_CFG_GPO(GPP_B3, 1, DEEP), + /* GPP_B4 - CPU_GP3 */ + PAD_CFG_NF_BUF_TRIG(GPP_B4, NONE, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_B5 - GPIO */ + PAD_CFG_GPI_INT(GPP_B5, NONE, PLTRST, OFF), + /* GPP_B6 - GPIO */ + PAD_CFG_GPI_INT(GPP_B6, NONE, PLTRST, OFF), + /* GPP_B7 - NC */ + PAD_NC(GPP_B7, NONE), + /* GPP_B8 - GPIO */ + PAD_CFG_GPI_INT(GPP_B8, 5K_PU, PLTRST, OFF), + /* GPP_B9 - GPIO */ + PAD_CFG_GPI_INT(GPP_B9, NONE, PLTRST, OFF), + /* GPP_B10 - GPIO */ + PAD_CFG_GPI_INT(GPP_B10, NONE, PLTRST, OFF), + /* GPP_B11 - GPIO */ + _PAD_CFG_STRUCT(GPP_B11, + PAD_FUNC(GPIO) | PAD_RESET(PWROK) | + PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | + PAD_BUF(NO_DISABLE), + PAD_PULL(NONE)), + /* GPP_B12 - SLP_S0# */ + PAD_CFG_NF_BUF_TRIG(GPP_B12, NONE, DEEP, NF1, RX_DISABLE, OFF), + /* GPP_B13 - PLTRST# */ + PAD_CFG_NF_BUF_TRIG(GPP_B13, NONE, DEEP, NF1, RX_DISABLE, OFF), + /* GPP_B14 - SPKR */ + PAD_CFG_NF_BUF_TRIG(GPP_B14, 20K_PD, PLTRST, NF1, RX_DISABLE, OFF), + /* GPP_B15 - GPIO */ + PAD_CFG_GPI_INT(GPP_B15, NONE, PLTRST, OFF), + /* GPP_B16 - GPIO */ + PAD_CFG_GPI_INT(GPP_B16, NONE, PLTRST, OFF), + /* GPP_B17 - GPIO */ + PAD_CFG_GPO(GPP_B17, 1, DEEP), + /* GPP_B18 - GPIO */ + PAD_CFG_GPI_INT(GPP_B18, NONE, PLTRST, OFF), + /* GPP_B19 - GPIO */ + PAD_CFG_GPI_INT(GPP_B19, NONE, PLTRST, OFF), + /* GPP_B20 - GPIO */ + PAD_CFG_GPI_INT(GPP_B20, NONE, PLTRST, OFF), + /* GPP_B21 - GPIO */ + PAD_CFG_GPI_INT(GPP_B21, NONE, PLTRST, OFF), + /* GPP_B22 - GPIO */ + PAD_CFG_GPI_INT(GPP_B22, NONE, PLTRST, OFF), + /* GPP_B23 - PCHHOT# */ + _PAD_CFG_STRUCT(GPP_B23, + PAD_FUNC(NF2) | PAD_RESET(PLTRST) | + PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | + PAD_BUF(RX_DISABLE) | 1, + PAD_PULL(20K_PD)), + + /* ------- GPIO Group GPP_C ------- */ + /* GPP_C0 - SMBCLK */ + PAD_CFG_NF_BUF_TRIG(GPP_C0, NONE, DEEP, NF1, TX_DISABLE, OFF), + /* GPP_C1 - SMBDATA */ + PAD_CFG_NF_BUF_TRIG(GPP_C1, NONE, DEEP, NF1, TX_DISABLE, OFF), + /* GPP_C2 - GPIO */ + PAD_CFG_GPO(GPP_C2, 1, DEEP), + /* GPP_C3 - SML0CLK */ + PAD_CFG_NF_BUF_TRIG(GPP_C3, NONE, DEEP, NF1, TX_DISABLE, OFF), + /* GPP_C4 - SML0DATA */ + PAD_CFG_NF_BUF_TRIG(GPP_C4, NONE, DEEP, NF1, TX_DISABLE, OFF), + /* GPP_C5 - GPIO */ + PAD_CFG_GPI_INT(GPP_C5, NONE, PLTRST, OFF), + /* GPP_C6 - RESERVED */ + /* GPP_C7 - RESERVED */ + /* GPP_C8 - UART0_RXD */ + PAD_CFG_NF_BUF_TRIG(GPP_C8, NONE, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_C9 - UART0_TXD */ + PAD_CFG_NF_BUF_TRIG(GPP_C9, NONE, PLTRST, NF1, RX_DISABLE, OFF), + /* GPP_C10 - UART0_RTS# */ + PAD_CFG_NF_BUF_TRIG(GPP_C10, NONE, PLTRST, NF1, RX_DISABLE, OFF), + /* GPP_C11 - UART0_CTS# */ + PAD_CFG_NF_BUF_TRIG(GPP_C11, NONE, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_C12 - GPIO */ + PAD_CFG_GPI_INT(GPP_C12, NONE, PLTRST, OFF), + /* GPP_C13 - GPIO */ + PAD_CFG_GPI_INT(GPP_C13, NONE, PLTRST, OFF), + /* GPP_C14 - GPIO */ + PAD_CFG_GPI_INT(GPP_C14, NONE, PLTRST, OFF), + /* GPP_C15 - GPIO */ + PAD_CFG_GPI_INT(GPP_C15, NONE, PLTRST, OFF), + /* GPP_C16 - GPIO */ + PAD_CFG_GPI_INT(GPP_C16, NONE, PLTRST, OFF), + /* GPP_C17 - GPIO */ + PAD_CFG_GPI_INT(GPP_C17, NONE, PLTRST, OFF), + /* GPP_C18 - GPIO */ + PAD_CFG_GPI_INT(GPP_C18, NONE, PLTRST, OFF), + /* GPP_C19 - GPIO */ + PAD_CFG_GPI_INT(GPP_C19, NONE, PLTRST, OFF), + /* GPP_C20 - UART2_RXD */ + PAD_CFG_NF_BUF_TRIG(GPP_C20, NONE, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_C21 - UART2_TXD */ + PAD_CFG_NF_BUF_TRIG(GPP_C21, NONE, PLTRST, NF1, RX_DISABLE, OFF), + /* GPP_C22 - UART2_RTS# */ + PAD_CFG_NF_BUF_TRIG(GPP_C22, NONE, PLTRST, NF1, RX_DISABLE, OFF), + /* GPP_C23 - GPIO */ + PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, LEVEL, YES), + + /* ------- GPIO Group GPP_D ------- */ + /* GPP_D0 - GPIO */ + PAD_CFG_GPI_INT(GPP_D0, NONE, PLTRST, OFF), + /* GPP_D1 - GPIO */ + PAD_CFG_GPI_INT(GPP_D1, NONE, PLTRST, OFF), + /* GPP_D2 - GPIO */ + PAD_CFG_GPI_INT(GPP_D2, NONE, PLTRST, OFF), + /* GPP_D3 - GPIO */ + PAD_CFG_GPI_INT(GPP_D3, NONE, PLTRST, OFF), + /* GPP_D4 - GPIO */ + PAD_CFG_GPI_INT(GPP_D4, NONE, PLTRST, OFF), + /* GPP_D5 - I2S_SFRM */ + PAD_CFG_NF_BUF_TRIG(GPP_D5, NONE, PLTRST, NF1, NO_DISABLE, OFF), + /* GPP_D6 - I2S_TXD */ + PAD_CFG_NF_BUF_TRIG(GPP_D6, NONE, PLTRST, NF1, RX_DISABLE, OFF), + /* GPP_D7 - I2S_RXD */ + PAD_CFG_NF_BUF_TRIG(GPP_D7, NONE, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_D8 - I2S_SCLK */ + PAD_CFG_NF_BUF_TRIG(GPP_D8, NONE, PLTRST, NF1, NO_DISABLE, OFF), + /* GPP_D9 - GPIO */ + PAD_CFG_GPI_INT(GPP_D9, NONE, PLTRST, OFF), + /* GPP_D10 - GPIO */ + PAD_CFG_GPI_INT(GPP_D10, NONE, PLTRST, OFF), + /* GPP_D11 - GPIO */ + PAD_CFG_GPI_INT(GPP_D11, NONE, PLTRST, OFF), + /* GPP_D12 - GPIO */ + PAD_CFG_GPI_INT(GPP_D12, NONE, PLTRST, OFF), + /* GPP_D13 - GPIO */ + PAD_CFG_GPI_INT(GPP_D13, NONE, PLTRST, OFF), + /* GPP_D14 - GPIO */ + PAD_CFG_GPI_INT(GPP_D14, NONE, PLTRST, OFF), + /* GPP_D15 - GPIO */ + PAD_CFG_GPI_INT(GPP_D15, NONE, PLTRST, OFF), + /* GPP_D16 - GPIO */ + PAD_CFG_GPI_INT(GPP_D16, NONE, PLTRST, OFF), + /* GPP_D17 - GPIO */ + PAD_CFG_GPI_INT(GPP_D17, NONE, PLTRST, OFF), + /* GPP_D18 - GPIO */ + PAD_CFG_GPI_INT(GPP_D18, NONE, PLTRST, OFF), + /* GPP_D19 - DMIC_CLK0 */ + PAD_CFG_NF_BUF_TRIG(GPP_D19, 20K_PU, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_D20 - DMIC_DATA0 */ + PAD_CFG_NF_BUF_TRIG(GPP_D20, 20K_PU, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_D21 - GPIO */ + PAD_CFG_GPI_INT(GPP_D21, NONE, PLTRST, OFF), + /* GPP_D22 - GPIO */ + PAD_CFG_GPI_INT(GPP_D22, NONE, PLTRST, OFF), + /* GPP_D23 - GPIO */ + PAD_CFG_GPI_INT(GPP_D23, NONE, PLTRST, OFF), + + /* ------- GPIO Group GPP_E ------- */ + /* GPP_E0 - SATAXPCIE0 */ + PAD_CFG_NF_BUF_TRIG(GPP_E0, 20K_PU, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_E1 - SATAXPCIE1 */ + PAD_CFG_NF_BUF_TRIG(GPP_E1, 20K_PU, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_E2 - SATAXPCIE2 */ + PAD_CFG_NF_BUF_TRIG(GPP_E2, 20K_PU, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_E3 - CPU_GP0 */ + PAD_CFG_NF_BUF_TRIG(GPP_E3, NONE, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_E4 - SATA_DEVSLP0 */ + PAD_CFG_NF_BUF_TRIG(GPP_E4, NONE, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_E5 - SATA_DEVSLP1 */ + PAD_CFG_NF_BUF_TRIG(GPP_E5, NONE, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_E6 - SATA_DEVSLP2 */ + PAD_CFG_NF_BUF_TRIG(GPP_E6, NONE, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_E7 - GPIO */ + PAD_CFG_GPI_INT(GPP_E7, NONE, PLTRST, OFF), + /* GPP_E8 - SATA_LED# */ + PAD_CFG_NF_BUF_TRIG(GPP_E8, NONE, PLTRST, NF1, RX_DISABLE, OFF), + /* GPP_E9 - USB_OC0# */ + PAD_CFG_NF_BUF_TRIG(GPP_E9, NONE, DEEP, NF1, TX_DISABLE, OFF), + /* GPP_E10 - USB_OC1# */ + PAD_CFG_NF_BUF_TRIG(GPP_E10, NONE, DEEP, NF1, TX_DISABLE, OFF), + /* GPP_E11 - USB_OC2# */ + PAD_CFG_NF_BUF_TRIG(GPP_E11, NONE, DEEP, NF1, TX_DISABLE, OFF), + /* GPP_E12 - USB_OC3# */ + PAD_CFG_NF_BUF_TRIG(GPP_E12, NONE, DEEP, NF1, TX_DISABLE, OFF), + + /* ------- GPIO Group GPP_F ------- */ + /* GPP_F0 - GPIO */ + PAD_CFG_GPI_INT(GPP_F0, NONE, PLTRST, OFF), + /* GPP_F1 - SATAXPCIE4 */ + PAD_CFG_NF_BUF_TRIG(GPP_F1, 20K_PU, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_F2 - GPIO */ + PAD_NC(GPP_F2, NONE), + /* GPP_F3 - GPIO */ + PAD_CFG_GPI_INT(GPP_F3, NONE, PLTRST, OFF), + /* GPP_F4 - GPIO */ + PAD_CFG_GPI_INT(GPP_F4, NONE, PLTRST, OFF), + /* GPP_F5 - GPIO */ + PAD_CFG_GPI_INT(GPP_F5, NONE, PLTRST, OFF), + /* GPP_F6 - GPIO */ + PAD_CFG_GPI_INT(GPP_F6, NONE, PLTRST, OFF), + /* GPP_F7 - GPIO */ + PAD_CFG_GPI_INT(GPP_F7, NONE, PLTRST, OFF), + /* GPP_F8 - GPIO */ + PAD_CFG_GPI_INT(GPP_F8, NONE, PLTRST, OFF), + /* GPP_F9 - GPIO */ + PAD_CFG_GPI_INT(GPP_F9, NONE, PLTRST, OFF), + /* GPP_F10 - GPIO */ + PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), + /* GPP_F11 - GPIO */ + PAD_CFG_GPI_INT(GPP_F11, NONE, PLTRST, OFF), + /* GPP_F12 - GPIO */ + PAD_CFG_GPI_APIC_INVERT(GPP_F12, NONE, PLTRST), + /* GPP_F13 - GPIO */ + PAD_CFG_GPI_APIC(GPP_F13, NONE, PLTRST), + /* GPP_F14 - GPIO */ + PAD_CFG_GPI_APIC_INVERT(GPP_F14, NONE, DEEP), + /* GPP_F15 - USB_OC4# */ + PAD_CFG_NF_BUF_TRIG(GPP_F15, NONE, DEEP, NF1, TX_DISABLE, OFF), + /* GPP_F16 - USB_OC5# */ + PAD_CFG_NF_BUF_TRIG(GPP_F16, NONE, DEEP, NF1, TX_DISABLE, OFF), + /* GPP_F17 - USB_OC6# */ + PAD_CFG_NF_BUF_TRIG(GPP_F17, NONE, DEEP, NF1, TX_DISABLE, OFF), + /* GPP_F18 - GPIO */ + PAD_CFG_GPO(GPP_F18, 1, PLTRST), + /* GPP_F19 - GPIO */ + PAD_CFG_GPI_INT(GPP_F19, NONE, PLTRST, OFF), + /* GPP_F20 - GPIO */ + PAD_CFG_GPI_INT(GPP_F20, NONE, PLTRST, OFF), + /* GPP_F21 - GPIO */ + PAD_CFG_GPI_INT(GPP_F21, NONE, PLTRST, OFF), + /* GPP_F22 - GPIO */ + PAD_CFG_GPI_INT(GPP_F22, NONE, PLTRST, OFF), + /* GPP_F23 - GPIO */ + PAD_CFG_GPI_INT(GPP_F23, NONE, PLTRST, OFF), + + /* ------- GPIO Group GPP_G ------- */ + /* GPP_G0 - GPIO */ + PAD_CFG_GPI_INT(GPP_G0, NONE, PWROK, OFF), + /* GPP_G1 - GPIO */ + PAD_CFG_GPI_INT(GPP_G1, NONE, PWROK, OFF), + /* GPP_G2 - GPIO */ + PAD_CFG_GPI_INT(GPP_G2, NONE, PWROK, OFF), + /* GPP_G3 - GPIO */ + PAD_CFG_GPI_INT(GPP_G3, NONE, PWROK, OFF), + /* GPP_G4 - GPIO */ + PAD_CFG_GPO(GPP_G4, 0, DEEP), + /* GPP_G5 - GPIO */ + PAD_CFG_GPI_INT(GPP_G5, NONE, PWROK, OFF), + /* GPP_G6 - GPIO */ + _PAD_CFG_STRUCT(GPP_G6, + PAD_FUNC(GPIO) | PAD_RESET(PWROK) | + PAD_CFG0_TRIG_LEVEL | PAD_CFG0_RX_POL_YES | + PAD_BUF(TX_DISABLE), + PAD_PULL(NONE)), + /* GPP_G7 - GPIO */ + PAD_CFG_GPI_INT(GPP_G7, NONE, PWROK, OFF), + /* GPP_G8 - GPIO */ + PAD_CFG_GPI_INT(GPP_G8, NONE, PLTRST, OFF), + /* GPP_G9 - GPIO */ + PAD_CFG_GPI_INT(GPP_G9, NONE, PLTRST, OFF), + /* GPP_G10 - GPIO */ + PAD_CFG_GPI_INT(GPP_G10, NONE, PLTRST, OFF), + /* GPP_G11 - GPIO */ + PAD_CFG_GPI_INT(GPP_G11, NONE, PLTRST, OFF), + /* GPP_G12 - GPIO */ + _PAD_CFG_STRUCT(GPP_G12, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | + PAD_CFG0_TRIG_LEVEL | PAD_CFG0_RX_POL_YES | + PAD_BUF(TX_DISABLE), + PAD_PULL(NONE)), + /* GPP_G13 - GPIO */ + PAD_CFG_GPO(GPP_G13, 1, PLTRST), + /* GPP_G14 - GPIO */ + _PAD_CFG_STRUCT(GPP_G14, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | + PAD_CFG0_TRIG_LEVEL | PAD_CFG0_RX_POL_YES | + PAD_BUF(TX_DISABLE), + PAD_PULL(NONE)), + /* GPP_G15 - GPIO */ + PAD_CFG_GPO(GPP_G15, 0, PLTRST), + /* GPP_G16 - GPIO */ + PAD_CFG_TERM_GPO(GPP_G16, 1, 20K_PD, PLTRST), + /* GPP_G17 - GPIO */ + PAD_CFG_GPI_INT(GPP_G17, NONE, PLTRST, OFF), + /* GPP_G18 - GPIO */ + PAD_CFG_GPI_APIC(GPP_G18, NONE, PLTRST), + /* GPP_G19 - SMI# */ + PAD_CFG_NF_BUF_TRIG(GPP_G19, NONE, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_G20 - GPIO */ + PAD_CFG_GPI_INT(GPP_G20, NONE, PLTRST, OFF), + /* GPP_G21 - GPIO */ + PAD_CFG_GPI_INT(GPP_G21, NONE, PLTRST, OFF), + /* GPP_G22 - GPIO */ + PAD_CFG_GPI_INT(GPP_G22, NONE, PLTRST, OFF), + /* GPP_G23 - GPIO */ + PAD_CFG_GPI_INT(GPP_G23, NONE, PLTRST, OFF), + + /* ------- GPIO Group GPP_H ------- */ + /* GPP_H0 - GPIO */ + PAD_CFG_GPI_INT(GPP_H0, NONE, PLTRST, OFF), + /* GPP_H1 - GPIO */ + PAD_NC(GPP_H1, NONE), + /* GPP_H2 - GPIO */ + PAD_CFG_GPI_INT(GPP_H2, NONE, PLTRST, OFF), + /* GPP_H3 - GPIO */ + PAD_CFG_GPI_INT(GPP_H3, NONE, PLTRST, OFF), + /* GPP_H4 - GPIO */ + PAD_CFG_GPI_INT(GPP_H4, NONE, PLTRST, OFF), + /* GPP_H5 - GPIO */ + PAD_CFG_GPI_INT(GPP_H5, NONE, PLTRST, OFF), + /* GPP_H6 - GPIO */ + PAD_CFG_GPI_INT(GPP_H6, NONE, PLTRST, OFF), + /* GPP_H7 - GPIO */ + PAD_CFG_GPI_INT(GPP_H7, NONE, PLTRST, OFF), + /* GPP_H8 - GPIO */ + PAD_CFG_GPI_INT(GPP_H8, NONE, PLTRST, OFF), + /* GPP_H9 - GPIO */ + PAD_CFG_GPI_INT(GPP_H9, NONE, PLTRST, OFF), + /* GPP_H10 - GPIO */ + PAD_CFG_GPI_INT(GPP_H10, NONE, PLTRST, OFF), + /* GPP_H11 - GPIO */ + PAD_CFG_GPI_INT(GPP_H11, NONE, PLTRST, OFF), + /* GPP_H12 - GPIO */ + PAD_CFG_GPI_INT(GPP_H12, NONE, PLTRST, OFF), + /* GPP_H13 - GPIO */ + PAD_CFG_GPI_APIC(GPP_H13, NONE, PLTRST), + /* GPP_H14 - GPIO */ + PAD_CFG_GPI_APIC(GPP_H14, NONE, PLTRST), + /* GPP_H15 - GPIO */ + PAD_CFG_GPI_APIC(GPP_H15, NONE, PLTRST), + /* GPP_H16 - GPIO */ + PAD_CFG_GPI(GPP_H16, NONE, PLTRST), + /* GPP_H17 - GPIO */ + PAD_CFG_GPO(GPP_H17, 1, PLTRST), + /* GPP_H18 - GPIO */ + PAD_CFG_GPI_INT(GPP_H18, NONE, PLTRST, OFF), + /* GPP_H19 - GPIO */ + PAD_CFG_GPI_INT(GPP_H19, NONE, PLTRST, OFF), + /* GPP_H20 - GPIO */ + PAD_CFG_GPI_INT(GPP_H20, NONE, PLTRST, OFF), + /* GPP_H21 - GPIO */ + PAD_CFG_GPI_INT(GPP_H21, NONE, PLTRST, OFF), + /* GPP_H22 - GPIO */ + PAD_CFG_GPI_INT(GPP_H22, NONE, PLTRST, OFF), + /* GPP_H23 - GPIO */ + PAD_CFG_GPI_INT(GPP_H23, NONE, PWROK, OFF), + + /* -------- GPIO Group GPD -------- */ + /* GPD0 - GPIO */ + PAD_CFG_GPI_INT(GPD0, NONE, PLTRST, OFF), + /* GPD1 - GPIO */ + PAD_CFG_GPO(GPD1, 0, PWROK), + /* GPD2 - LAN_WAKE# */ + PAD_CFG_NF_BUF_TRIG(GPD2, NATIVE, PWROK, NF1, RX_DISABLE, LEVEL), + /* GPD3 - PWRBTN# */ + PAD_CFG_NF_BUF_TRIG(GPD3, 20K_PU, PWROK, NF1, TX_DISABLE, OFF), + /* GPD4 - SLP_S3# */ + PAD_CFG_NF_BUF_TRIG(GPD4, NONE, PWROK, NF1, RX_DISABLE, OFF), + /* GPD5 - SLP_S4# */ + PAD_CFG_NF_BUF_TRIG(GPD5, NONE, PWROK, NF1, RX_DISABLE, OFF), + /* GPD6 - GPIO */ + PAD_CFG_GPI_INT(GPD6, NONE, PLTRST, OFF), + /* GPD7 - GPIO */ + _PAD_CFG_STRUCT(GPD7, + PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | + PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | + PAD_BUF(TX_DISABLE) | 1, + PAD_PULL(NONE)), + /* GPD8 - SUSCLK */ + PAD_CFG_NF_BUF_TRIG(GPD8, NONE, PWROK, NF1, RX_DISABLE, OFF), + /* GPD9 - SLP_WLAN# */ + PAD_CFG_NF_BUF_TRIG(GPD9, NONE, PWROK, NF1, RX_DISABLE, OFF), + /* GPD10 - SLP_S5# */ + PAD_CFG_NF_BUF_TRIG(GPD10, NONE, PWROK, NF1, RX_DISABLE, OFF), + /* GPD11 - GPIO */ + PAD_CFG_GPO(GPD11, 0, PWROK), + + /* ------- GPIO Group GPP_I ------- */ + /* GPP_I0 - DDPB_HPD0 */ + PAD_CFG_NF_BUF_TRIG(GPP_I0, NONE, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_I1 - DDPC_HPD1 */ + PAD_CFG_NF_BUF_TRIG(GPP_I1, NONE, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_I2 - DDPD_HPD2 */ + PAD_CFG_NF_BUF_TRIG(GPP_I2, NONE, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_I3 - DDPE_HPD3 */ + PAD_CFG_NF_BUF_TRIG(GPP_I3, NONE, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_I4 - GPIO */ + PAD_CFG_GPI_INT(GPP_I4, NONE, PLTRST, OFF), + /* GPP_I5 - DDPB_CTRLCLK */ + PAD_CFG_NF_BUF_TRIG(GPP_I5, NONE, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_I6 - DDPB_CTRLDATA */ + PAD_CFG_NF_BUF_TRIG(GPP_I6, 20K_PD, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_I7 - DDPC_CTRLCLK */ + PAD_CFG_NF_BUF_TRIG(GPP_I7, NONE, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_I8 - DDPC_CTRLDATA */ + PAD_CFG_NF_BUF_TRIG(GPP_I8, 20K_PD, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_I9 - DDPD_CTRLCLK */ + PAD_CFG_NF_BUF_TRIG(GPP_I9, NONE, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_I10 - DDPD_CTRLDATA */ + PAD_CFG_NF_BUF_TRIG(GPP_I10, 20K_PD, PLTRST, NF1, TX_DISABLE, OFF), +}; + +/* Early pad configuration in romstage */ +static const struct pad_config early_gpio_table[] = { + /* ------- GPIO Group GPP_A ------- */ + /* GPP_A0 - RCIN# */ + PAD_CFG_NF_BUF_TRIG(GPP_A0, NONE, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_A1 - LAD0 */ + PAD_CFG_NF_BUF_TRIG(GPP_A1, 20K_PU, PLTRST, NF1, NO_DISABLE, OFF), + /* GPP_A2 - LAD1 */ + PAD_CFG_NF_BUF_TRIG(GPP_A2, 20K_PU, PLTRST, NF1, NO_DISABLE, OFF), + /* GPP_A3 - LAD2 */ + PAD_CFG_NF_BUF_TRIG(GPP_A3, 20K_PU, PLTRST, NF1, NO_DISABLE, OFF), + /* GPP_A4 - LAD3 */ + PAD_CFG_NF_BUF_TRIG(GPP_A4, 20K_PU, PLTRST, NF1, NO_DISABLE, OFF), + /* GPP_A5 - LFRAME# */ + PAD_CFG_NF_BUF_TRIG(GPP_A5, NONE, PLTRST, NF1, RX_DISABLE, OFF), + /* GPP_A6 - SERIRQ */ + PAD_CFG_NF_BUF_TRIG(GPP_A6, NONE, PLTRST, NF1, NO_DISABLE, OFF), + + /* GPP_A8 - CLKRUN# */ + PAD_CFG_NF_BUF_TRIG(GPP_A8, NONE, PLTRST, NF1, TX_DISABLE, OFF), + /* GPP_A9 - CLKOUT_LPC0 */ + PAD_CFG_NF_BUF_TRIG(GPP_A9, 20K_PD, PLTRST, NF1, RX_DISABLE, OFF), + /* GPP_A10 - CLKOUT_LPC1 */ + PAD_CFG_NF_BUF_TRIG(GPP_A10, 20K_PD, PLTRST, NF1, RX_DISABLE, OFF), + + /* GPP_A13 - SUSWARN#/SUSPWRDNACK */ + PAD_CFG_NF_BUF_TRIG(GPP_A13, NONE, DEEP, NF1, RX_DISABLE, OFF), + /* GPP_A14 - SUS_STAT# */ + PAD_CFG_NF_BUF_TRIG(GPP_A14, NONE, DEEP, NF1, RX_DISABLE, OFF), + /* GPP_A15 - SUS_ACK# */ + PAD_CFG_NF_BUF_TRIG(GPP_A15, 20K_PU, DEEP, NF1, TX_DISABLE, OFF), +}; + +#endif diff --git a/src/mainboard/gigabyte/ga-z170x-gaming7/mainboard.c b/src/mainboard/gigabyte/ga-z170x-gaming7/mainboard.c new file mode 100644 index 0000000..4c1c6cd --- /dev/null +++ b/src/mainboard/gigabyte/ga-z170x-gaming7/mainboard.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Tristan Corrick <tristan(a)corrick.kiwi> + * Copyright (C) 2019 Maxim Polyakov <max.senia.poliak(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> + +static void mainboard_enable(struct device *dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/gigabyte/ga-z170x-gaming7/ramstage.c b/src/mainboard/gigabyte/ga-z170x-gaming7/ramstage.c new file mode 100644 index 0000000..a247b72 --- /dev/null +++ b/src/mainboard/gigabyte/ga-z170x-gaming7/ramstage.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation + * Copyright (C) 2019 Maxim Polyakov <max.senia.poliak(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/ramstage.h> +#include "include/gpio.h" + +void mainboard_silicon_init_params(FSP_SIL_UPD *params) +{ + /* Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + + params->CdClock = 3; +} diff --git a/src/mainboard/gigabyte/ga-z170x-gaming7/romstage.c b/src/mainboard/gigabyte/ga-z170x-gaming7/romstage.c new file mode 100644 index 0000000..0c0371b --- /dev/null +++ b/src/mainboard/gigabyte/ga-z170x-gaming7/romstage.c @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * Copyright (C) 2019 Maxim Polyakov <max.senia.poliak(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/romstage.h> +#include <string.h> +#include <spd_bin.h> + +static void mainboard_fill_rcomp_res_data(void *rcomp_ptr) +{ + /* Rcomp resistor */ + const u16 RcompResistor[3] = { 200, 81, 162 }; + memcpy(rcomp_ptr, RcompResistor, + sizeof(RcompResistor)); +} + +static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) +{ + /* Rcomp target */ + static const u16 RcompTarget[5] = { + 100, 40, 40, 23, 40 }; + memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); +} + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg; + struct spd_block blk = { + .addr_map = { 0x50, 0x51, 0x52, 0x53, }, + }; + + mem_cfg = &mupd->FspmConfig; + mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0, + &mem_cfg->DqByteMapCh1); + mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0, + &mem_cfg->DqsMapCpu2DramCh1); + mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); + mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); + + mem_cfg->DqPinsInterleaved = 1; + get_spd_smbus(&blk); + mem_cfg->MemorySpdDataLen = blk.len; + mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; + mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[2]; + mem_cfg->MemorySpdPtr01 = (uintptr_t)blk.spd_array[1]; + mem_cfg->MemorySpdPtr11 = (uintptr_t)blk.spd_array[3]; + dump_spd_info(&blk); + + /* use virtual channel 1 for the dmi interface of the PCH */ + mupd->FspmTestConfig.DmiVc1 = 1; + + /* desktop type */ + mem_cfg->UserBd = BOARD_TYPE_DESKTOP; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/38920 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2c69bddd22cbd8f797dbb57370a4d8e5afa63bc Gerrit-Change-Number: 38920 Gerrit-PatchSet: 1 Gerrit-Owner: Christoph Pomaska <github(a)slrie.de> Gerrit-MessageType: newchange

5 days, 8 hours

Change in coreboot[master]: soc/intel/common: Add romstage common stage file

by Bernardo Perez Priego (Code Review)

Bernardo Perez Priego has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37628 ) Change subject: soc/intel/common: Add romstage common stage file ...................................................................... soc/intel/common: Add romstage common stage file This patch will ensures all intel soc is using common stage files to make coreboot design flow align across all socs. CPU, SA, PCH, MCH programming sequence might be different between socs but the function call should route from same location across all soc. Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Change-Id: I06d43ac29f5e87ce731a470e5e145adea07ece4c --- M src/cpu/intel/car/romstage.c A src/soc/intel/common/basecode/include/intelbasecode/romstage.h A src/soc/intel/common/basecode/romstage/Makefile.inc A src/soc/intel/common/basecode/romstage/romstage.c 4 files changed, 162 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/37628/1 diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c index 1f8eb9a..55d3c9d 100644 --- a/src/cpu/intel/car/romstage.c +++ b/src/cpu/intel/car/romstage.c @@ -52,9 +52,6 @@ for (i = 0; i < num_guards; i++) stack_base[i] = stack_guard; - if (CONFIG(VBOOT_EARLY_EC_SYNC)) - vboot_sync_ec(); - mainboard_romstage_entry(); /* Check the stack. */ @@ -64,9 +61,6 @@ printk(BIOS_DEBUG, "Smashed stack detected in romstage!\n"); } - if (CONFIG(SMM_TSEG)) - smm_list_regions(); - prepare_and_run_postcar(&early_mtrrs); /* We do not return here. */ } diff --git a/src/soc/intel/common/basecode/include/intelbasecode/romstage.h b/src/soc/intel/common/basecode/include/intelbasecode/romstage.h new file mode 100644 index 0000000..0cebbbf --- /dev/null +++ b/src/soc/intel/common/basecode/include/intelbasecode/romstage.h @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_INTEL_COMMON_BASECODE_ROMSTAGE_H +#define SOC_INTEL_COMMON_BASECODE_ROMSTAGE_H + +#include <stddef.h> +#include <stdint.h> +#include <fsp/soc_binding.h> + +struct romstage_ops { + void (*soc_early_init)(void); + void (*soc_init)(void); + void (*pch_early_init)(void); + void (*pch_init)(void); + void (*cpu_early_init)(void); + void (*cpu_init)(void); + bool (*is_s3wake)(void); + void (*soc_mem_init_params)(FSP_M_CONFIG *mupd); +}; + +/* SoC Override function */ +struct romstage_ops *soc_get_ops(void); + +#endif diff --git a/src/soc/intel/common/basecode/romstage/Makefile.inc b/src/soc/intel/common/basecode/romstage/Makefile.inc new file mode 100644 index 0000000..29763fb --- /dev/null +++ b/src/soc/intel/common/basecode/romstage/Makefile.inc @@ -0,0 +1 @@ +romstage-y += romstage.c diff --git a/src/soc/intel/common/basecode/romstage/romstage.c b/src/soc/intel/common/basecode/romstage/romstage.c new file mode 100644 index 0000000..55c4ab5 --- /dev/null +++ b/src/soc/intel/common/basecode/romstage/romstage.c @@ -0,0 +1,124 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/early_variables.h> +#include <romstage_common.h> +#include <cpu/x86/pae.h> +#include <intelbasecode/romstage.h> +#include <intelblocks/systemagent.h> +#include <soc/iomap.h> +#include <soc/romstage.h> + +static const struct romstage_ops s_romstage_ops; + +__weak struct romstage_ops *soc_get_ops(void) +{ + return (struct romstage_ops *)&s_romstage_ops; +} + +void romstage_early_init(void) +{ + struct romstage_ops *rs_ops = soc_get_ops(); + + rs_ops->soc_early_init(); + rs_ops->pch_early_init(); + rs_ops->cpu_early_init(); +} + +void romstage_init(void) +{ + struct romstage_ops *rs_ops = soc_get_ops(); + + rs_ops->soc_init(); + rs_ops->pch_init(); + rs_ops->cpu_init(); +} + +void romstage_cmn_soc_early_init(void) +{ + systemagent_early_init(); + heci_init(HECI1_BASE_ADDRESS); +} + +void romstage_cmn_soc_init(void) +{ +} + +void romstage_cmn_pch_early_init(void) +{ +} + +void romstage_cmn_cpu_early_init(void) +{ +} + +void romstage_cmn_pch_init(void) +{ +} + +void romstage_cmn_cpu_init(void) +{ +} + +bool romstage_cmn_is_s3wake(void) +{ + struct chipset_power_state *ps = pmc_get_power_state(); + return pmc_fill_power_state(ps) == ACPI_S3; +} + +void romstage_cmn_soc_mem_init_param(FSP_M_CONFIG *m_cfg) +{ +} + +static const struct romstage_ops s_romstage_ops = { + &romstage_cmn_soc_early_init, + &romstage_cmn_soc_init, + &romstage_cmn_pch_early_init, + &romstage_cmn_pch_init, + &romstage_cmn_cpu_early_init, + &romstage_cmn_cpu_init, + &romstage_cmn_is_s3wake, + &romstage_cmn_mb_mem_init_param, + &romstage_cmn_soc_mem_init_param +}; + +/* + Main romstage function +*/ +asmlinkage void mainboard_romstage_entry(void) +{ + if (CONFIG(VBOOT_EARLY_EC_SYNC)) + vboot_sync_ec(rs_ops->fill_power_state()); + + romstage_early_init(); + romstage_init(); + fsp_memory_init(rs_ops->is_s3wake()); + + if (CONFIG(SMM_TSEG)) + smm_list_regions(); +} + +/* + Callback function for FSP memory initialization +*/ +void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) +{ + struct romstage_ops *rs_ops = soc_get_ops(); + + FSP_M_CONFIG *m_cfg; + rs_ops->soc_mem_init_params(m_cfg); + mainboard_memory_init_params(m_cfg); +} + -- To view, visit https://review.coreboot.org/c/coreboot/+/37628 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06d43ac29f5e87ce731a470e5e145adea07ece4c Gerrit-Change-Number: 37628 Gerrit-PatchSet: 1 Gerrit-Owner: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-MessageType: newchange

5 days, 15 hours

Change in coreboot[master]: soc/intel/{apl,glk}: add options to configure GPU

by Maxim Polyakov (Code Review)

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39374 ) Change subject: soc/intel/{apl,glk}: add options to configure GPU ...................................................................... soc/intel/{apl,glk}: add options to configure GPU Adds options to select the primary GPU device and configure IGD, which allows to override the appropriate FSP options in the SoC code. These changes do not affect the configuration of the boards with the Apollo Lake and Gemini Lake processors, because if these parameters are not defined in the devicetree, they will be set to the default values. Change-Id: Idcd117217cf412ee0722aff52db4b3c8ec2a226c Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/soc/intel/apollolake/chip.h M src/soc/intel/apollolake/romstage.c 2 files changed, 64 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/39374/1 diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index 40cd39b..0375cec 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -44,6 +44,46 @@ /* Common structure containing soc config data required by common code*/ struct soc_intel_common_config common_soc_config; + /* Select DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size */ + enum { + DVMT_64MB = 2, /* Default */ + DVMT_96MB, + DVMT_128MB, + DVMT_160MB, + DVMT_192MB, + DVMT_224MB, + DVMT_256MB, + DVMT_288MB, + DVMT_320MB, + DVMT_352MB, + DVMT_384MB, + DVMT_416MB, + DVMT_448MB, + DVMT_480MB, + DVMT_512MB, + } igd_dvmt_50_pre_alloc_size; + + /* Select the Aperture Size for GPU device */ + enum { + APERTURE_128MB = 1, /* Default */ + APERTURE_256MB, + APERTURE_512MB, + } igd_aperture_size; + + /* Select the GTT Size for GPU device */ + enum { + GTT_2MB = 1, + GTT_4MB, + GTT_8MB, /* Default */ + } igd_gtt_size; + + /* Select primary GPU device */ + enum { + PRIMARY_AUTO = 0, /* Default */ + PRIMARY_IGD = 2, + PRIMARY_PCI = 3, + } primary_gpu; + /* * Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has * four CLKREQ inputs, but six root ports. Root ports without an diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 05cd0db..1576802 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -264,12 +264,34 @@ } } +static void soc_gpu_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + const struct soc_intel_apollolake_config *soc_cfg = config_of_soc(); + const struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD); + + m_cfg->PrimaryVideoAdaptor = soc_cfg->primary_gpu; + if (dev && dev->enabled && (soc_cfg->primary_gpu != PRIMARY_PCI)) { + /* + * Override FSP settings for IGD only if they are set in the devicetree. + * Otherwise, the default values from UPD will be used for them + */ + if (soc_cfg->igd_dvmt_50_pre_alloc_size) + m_cfg->IgdDvmt50PreAlloc = soc_cfg->igd_dvmt_50_pre_alloc_size; + + if (soc_cfg->igd_aperture_size) + m_cfg->IgdApertureSize = soc_cfg->igd_aperture_size; + + if (soc_cfg->igd_gtt_size) + m_cfg->GttSize = soc_cfg->igd_gtt_size; + } +} + static void soc_memory_init_params(FSPM_UPD *mupd) { #if CONFIG(SOC_INTEL_GLK) /* Only for GLK */ FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; - m_cfg->PrmrrSize = get_prmrr_size(); /* @@ -307,6 +329,7 @@ check_full_retrain(mupd); fill_console_params(mupd); + soc_gpu_init_params(mupd); if (CONFIG(SOC_INTEL_GLK)) soc_memory_init_params(mupd); -- To view, visit https://review.coreboot.org/c/coreboot/+/39374 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idcd117217cf412ee0722aff52db4b3c8ec2a226c Gerrit-Change-Number: 39374 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 week, 4 days

Change in coreboot[master]: mb/up/squared: set primary GPU in the devicetree

by Maxim Polyakov (Code Review)

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39375 ) Change subject: mb/up/squared: set primary GPU in the devicetree ...................................................................... mb/up/squared: set primary GPU in the devicetree Change-Id: I368fa5d13615dc4ee37db596cb6a5eef993fc220 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/up/squared/devicetree.cb M src/mainboard/up/squared/romstage.c 2 files changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/39375/1 diff --git a/src/mainboard/up/squared/devicetree.cb b/src/mainboard/up/squared/devicetree.cb index d7281a6..6ba3bf4 100644 --- a/src/mainboard/up/squared/devicetree.cb +++ b/src/mainboard/up/squared/devicetree.cb @@ -1,5 +1,8 @@ chip soc/intel/apollolake + # Set IGD as the primary graphics device + register "primary_gpu" = "PRIMARY_IGD" + # Override USB port configuration register "usb_config_override" = "1" # USB 2.0 diff --git a/src/mainboard/up/squared/romstage.c b/src/mainboard/up/squared/romstage.c index 55235a8..fd06559 100644 --- a/src/mainboard/up/squared/romstage.c +++ b/src/mainboard/up/squared/romstage.c @@ -169,7 +169,6 @@ config->RmtCheckRun = 0x3; // 0x0 config->RmtMarginCheckScaleHighThreshold = 0xC8; // 0x0 config->EnhancePort8xhDecoding = 0x0; // 0x1 - config->PrimaryVideoAdaptor = 0x2; // 0x0 config->Ch0_DeviceWidth = 0x1; // 0x0 config->Ch0_Option = 0x3; // 0x0 -- To view, visit https://review.coreboot.org/c/coreboot/+/39375 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I368fa5d13615dc4ee37db596cb6a5eef993fc220 Gerrit-Change-Number: 39375 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

1 week, 5 days

Change in coreboot[master]: util/kconfig: Uprev to Linux 5.3's kconfig

by Patrick Georgi (Code Review)

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37152 ) Change subject: util/kconfig: Uprev to Linux 5.3's kconfig ...................................................................... util/kconfig: Uprev to Linux 5.3's kconfig This was originally several commits that had to be squashed into one because the intermediate states weren't able to build coreboot: - one to remove everything that wasn't our own code, leaving only regex.[ch], toada.c, description.md and Makefile.inc - one to copy in Linux 5.3's scripts/kconfig and adapt Makefile.inc to make the original Makefile work again. TODO: - more commits that bring back our modifications, both directly in the code and as a diff in a patches/ subdirectory. Change-Id: Ia0e8fe4e9022b278f34ab113a433ef4d45e5c355 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M util/kconfig/Makefile M util/kconfig/Makefile.inc D util/kconfig/POTFILES.in D util/kconfig/check.sh M util/kconfig/conf.c M util/kconfig/confdata.c M util/kconfig/expr.c M util/kconfig/expr.h A util/kconfig/gconf-cfg.sh M util/kconfig/gconf.c M util/kconfig/images.c A util/kconfig/images.h D util/kconfig/kxgettext.c A util/kconfig/lexer.l M util/kconfig/list.h M util/kconfig/lkc.h M util/kconfig/lkc_proto.h D util/kconfig/lxdialog/.gitignore M util/kconfig/lxdialog/BIG.FAT.WARNING D util/kconfig/lxdialog/check-lxdialog.sh M util/kconfig/lxdialog/checklist.c M util/kconfig/lxdialog/dialog.h M util/kconfig/lxdialog/inputbox.c M util/kconfig/lxdialog/menubox.c M util/kconfig/lxdialog/textbox.c M util/kconfig/lxdialog/util.c M util/kconfig/lxdialog/yesno.c A util/kconfig/mconf-cfg.sh M util/kconfig/mconf.c M util/kconfig/menu.c A util/kconfig/merge_config.sh A util/kconfig/nconf-cfg.sh M util/kconfig/nconf.c M util/kconfig/nconf.gui.c M util/kconfig/nconf.h R util/kconfig/parser.y A util/kconfig/preprocess.c A util/kconfig/qconf-cfg.sh M util/kconfig/qconf.cc M util/kconfig/qconf.h A util/kconfig/streamline_config.pl M util/kconfig/symbol.c M util/kconfig/util.c D util/kconfig/zconf.gperf D util/kconfig/zconf.hash.c_shipped D util/kconfig/zconf.l D util/kconfig/zconf.lex.c_shipped D util/kconfig/zconf.tab.c_shipped 48 files changed, 4,250 insertions(+), 8,203 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/37152/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/37152 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia0e8fe4e9022b278f34ab113a433ef4d45e5c355 Gerrit-Change-Number: 37152 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

2 weeks, 6 days

Change in coreboot[master]: [TESTME]x4x/i82801jx/socket_LGA775: Add x86_64 support

by Patrick Rudolph (Code Review)

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36779 ) Change subject: [TESTME]x4x/i82801jx/socket_LGA775: Add x86_64 support ...................................................................... [TESTME]x4x/i82801jx/socket_LGA775: Add x86_64 support Use correct datasize to compile on x86_64. Change-Id: Ib4851932975e99e06ba5650c2359a835b46d702d Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/arch/x86/walkcbfs.S M src/cpu/intel/model_1067x/Kconfig M src/cpu/intel/model_6fx/Kconfig M src/cpu/intel/model_f3x/Kconfig M src/cpu/intel/model_f4x/Kconfig M src/cpu/intel/socket_LGA775/Kconfig M src/cpu/x86/mp_init.c M src/cpu/x86/smm/smm_module_handler.c M src/drivers/net/atl1e.c M src/northbridge/intel/x4x/dq_dqs.c M src/northbridge/intel/x4x/northbridge.c M src/northbridge/intel/x4x/raminit_ddr23.c M src/northbridge/intel/x4x/rcven.c M src/northbridge/intel/x4x/x4x.h M src/southbridge/intel/common/spi.c M src/southbridge/intel/i82801jx/hdaudio.c M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/i82801jx/sata.c 18 files changed, 63 insertions(+), 40 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/36779/1 diff --git a/src/arch/x86/walkcbfs.S b/src/arch/x86/walkcbfs.S index ded6558..01382e4 100644 --- a/src/arch/x86/walkcbfs.S +++ b/src/arch/x86/walkcbfs.S @@ -33,6 +33,7 @@ .section .text .global walkcbfs_asm +.code32 /* * input %esi: filename diff --git a/src/cpu/intel/model_1067x/Kconfig b/src/cpu/intel/model_1067x/Kconfig index 564a428..93604d6 100644 --- a/src/cpu/intel/model_1067x/Kconfig +++ b/src/cpu/intel/model_1067x/Kconfig @@ -1,9 +1,14 @@ config CPU_INTEL_MODEL_1067X bool - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 + select ARCH_BOOTBLOCK_X86_32 if !ARCH_EXP_X86_64 + select ARCH_VERSTAGE_X86_32 if !ARCH_EXP_X86_64 + select ARCH_ROMSTAGE_X86_32 if !ARCH_EXP_X86_64 + select ARCH_RAMSTAGE_X86_32 if !ARCH_EXP_X86_64 + select ARCH_BOOTBLOCK_X86_64 if ARCH_EXP_X86_64 + select ARCH_VERSTAGE_X86_64 if ARCH_EXP_X86_64 + select ARCH_ROMSTAGE_X86_64 if ARCH_EXP_X86_64 + select ARCH_RAMSTAGE_X86_64 if ARCH_EXP_X86_64 + select SMP select SSE2 select UDELAY_TSC diff --git a/src/cpu/intel/model_6fx/Kconfig b/src/cpu/intel/model_6fx/Kconfig index cfd3e7c..8c86226 100644 --- a/src/cpu/intel/model_6fx/Kconfig +++ b/src/cpu/intel/model_6fx/Kconfig @@ -1,9 +1,14 @@ config CPU_INTEL_MODEL_6FX bool - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 + select ARCH_BOOTBLOCK_X86_32 if !ARCH_EXP_X86_64 + select ARCH_VERSTAGE_X86_32 if !ARCH_EXP_X86_64 + select ARCH_ROMSTAGE_X86_32 if !ARCH_EXP_X86_64 + select ARCH_RAMSTAGE_X86_32 if !ARCH_EXP_X86_64 + + select ARCH_BOOTBLOCK_X86_64 if ARCH_EXP_X86_64 + select ARCH_VERSTAGE_X86_64 if ARCH_EXP_X86_64 + select ARCH_ROMSTAGE_X86_64 if ARCH_EXP_X86_64 + select ARCH_RAMSTAGE_X86_64 if ARCH_EXP_X86_64 select SMP select SSE2 select UDELAY_TSC diff --git a/src/cpu/intel/model_f3x/Kconfig b/src/cpu/intel/model_f3x/Kconfig index 9a5e2a1..ae67337 100644 --- a/src/cpu/intel/model_f3x/Kconfig +++ b/src/cpu/intel/model_f3x/Kconfig @@ -1,9 +1,14 @@ config CPU_INTEL_MODEL_F3X bool - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 + select ARCH_BOOTBLOCK_X86_32 if !ARCH_EXP_X86_64 + select ARCH_VERSTAGE_X86_32 if !ARCH_EXP_X86_64 + select ARCH_ROMSTAGE_X86_32 if !ARCH_EXP_X86_64 + select ARCH_RAMSTAGE_X86_32 if !ARCH_EXP_X86_64 + + select ARCH_BOOTBLOCK_X86_64 if ARCH_EXP_X86_64 + select ARCH_VERSTAGE_X86_64 if ARCH_EXP_X86_64 + select ARCH_ROMSTAGE_X86_64 if ARCH_EXP_X86_64 + select ARCH_RAMSTAGE_X86_64 if ARCH_EXP_X86_64 select SMP select SUPPORT_CPU_UCODE_IN_CBFS select CPU_INTEL_COMMON diff --git a/src/cpu/intel/model_f4x/Kconfig b/src/cpu/intel/model_f4x/Kconfig index 4ef60b5..84c6863 100644 --- a/src/cpu/intel/model_f4x/Kconfig +++ b/src/cpu/intel/model_f4x/Kconfig @@ -1,8 +1,12 @@ config CPU_INTEL_MODEL_F4X bool - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 + select ARCH_BOOTBLOCK_X86_32 if !ARCH_EXP_X86_64 + select ARCH_VERSTAGE_X86_32 if !ARCH_EXP_X86_64 + select ARCH_ROMSTAGE_X86_32 if !ARCH_EXP_X86_64 + select ARCH_RAMSTAGE_X86_32 if !ARCH_EXP_X86_64 + select ARCH_BOOTBLOCK_X86_64 if ARCH_EXP_X86_64 + select ARCH_VERSTAGE_X86_64 if ARCH_EXP_X86_64 + select ARCH_ROMSTAGE_X86_64 if ARCH_EXP_X86_64 + select ARCH_RAMSTAGE_X86_64 if ARCH_EXP_X86_64 select SMP select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/socket_LGA775/Kconfig b/src/cpu/intel/socket_LGA775/Kconfig index 8b227bd..8f60d2c 100644 --- a/src/cpu/intel/socket_LGA775/Kconfig +++ b/src/cpu/intel/socket_LGA775/Kconfig @@ -3,6 +3,10 @@ if CPU_INTEL_SOCKET_LGA775 +config ARCH_EXP_X86_64 + bool "Enable experimental 64bit support" + default n + config SOCKET_SPECIFIC_OPTIONS # dummy def_bool y select CPU_INTEL_MODEL_6FX diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 29ae3de..ea70453 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -122,7 +122,7 @@ /* The SIPI vector is loaded at the SMM_DEFAULT_BASE. The reason is at the * memory range is already reserved so the OS cannot use it. That region is * free to use for AP bringup before SMM is initialized. */ -static const uint32_t sipi_vector_location = SMM_DEFAULT_BASE; +static const uintptr_t sipi_vector_location = SMM_DEFAULT_BASE; static const int sipi_vector_location_size = SMM_DEFAULT_SIZE; struct mp_flight_plan { @@ -348,16 +348,16 @@ setup_default_sipi_vector_params(sp); /* Setup MSR table. */ - sp->msr_table_ptr = (uint32_t)&mod_loc[module_size]; + sp->msr_table_ptr = (uintptr_t)&mod_loc[module_size]; sp->msr_count = num_msrs; /* Provide pointer to microcode patch. */ - sp->microcode_ptr = (uint32_t)mp_params->microcode_pointer; + sp->microcode_ptr = (uintptr_t)mp_params->microcode_pointer; /* Pass on abiility to load microcode in parallel. */ if (mp_params->parallel_microcode_load) sp->microcode_lock = 0; else sp->microcode_lock = ~0; - sp->c_handler = (uint32_t)&ap_init; + sp->c_handler = (uintptr_t)&ap_init; ap_count = &sp->ap_count; atomic_set(ap_count, 0); diff --git a/src/cpu/x86/smm/smm_module_handler.c b/src/cpu/x86/smm/smm_module_handler.c index bd4d48c..82ad37d 100644 --- a/src/cpu/x86/smm/smm_module_handler.c +++ b/src/cpu/x86/smm/smm_module_handler.c @@ -107,7 +107,7 @@ /* This function assumes all save states start at top of default * SMRAM size space and are staggered down by save state size. */ - base = (void *)smm_runtime->smbase; + base = (void *)(uintptr_t)smm_runtime->smbase; base += SMM_DEFAULT_SIZE; base -= (cpu + 1) * smm_runtime->save_state_size; diff --git a/src/drivers/net/atl1e.c b/src/drivers/net/atl1e.c index 51470b0..d68ea0d 100644 --- a/src/drivers/net/atl1e.c +++ b/src/drivers/net/atl1e.c @@ -86,7 +86,7 @@ } } -static void program_mac_address(u32 mem_base) +static void program_mac_address(uintptr_t mem_base) { u8 macstrbuf[MACLEN] = { 0 }; /* Default MAC Address of 90:e6:ba:24:f9:d2 */ @@ -110,7 +110,7 @@ printk(BIOS_DEBUG, "done\n"); } -static int atl1e_eeprom_exist(u32 mem_base) +static int atl1e_eeprom_exist(uintptr_t mem_base) { u32 value = read32((void *)mem_base + REG_SPI_FLASH_CTRL); if (value & SPI_FLASH_CTRL_EN_VPD) { diff --git a/src/northbridge/intel/x4x/dq_dqs.c b/src/northbridge/intel/x4x/dq_dqs.c index ed372b5..080262e 100644 --- a/src/northbridge/intel/x4x/dq_dqs.c +++ b/src/northbridge/intel/x4x/dq_dqs.c @@ -178,7 +178,7 @@ static u8 test_dq_aligned(const struct sysinfo *s, const u8 channel) { - u32 address; + uintptr_t address; int rank, lane; u8 count, count1; u8 data[8]; @@ -374,7 +374,7 @@ { int i, rank, lane; volatile u8 data[8]; - u32 address; + uintptr_t address; u8 bytelane_error = 0; FOR_EACH_POPULATED_RANK_IN_CHANNEL(s->dimms, channel, rank) { @@ -453,7 +453,8 @@ int do_read_training(struct sysinfo *s) { int loop, channel, i, lane, rank; - u32 address, content; + uintptr_t address; + u32 content; u8 dqs_lower[TOTAL_BYTELANES]; u8 dqs_upper[TOTAL_BYTELANES]; struct rt_dqs_setting dqs_setting[TOTAL_BYTELANES]; @@ -643,7 +644,7 @@ static void sample_dq(const struct sysinfo *s, u8 channel, u8 rank, u8 high_found[8]) { - u32 address = test_address(channel, rank); + uintptr_t address = test_address(channel, rank); int samples, lane; memset(high_found, 0, TOTAL_BYTELANES * sizeof(high_found[0])); diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index 39f24d3..592a2e0 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -89,7 +89,7 @@ /* cbmem_top can be shifted downwards due to alignment. Mark the region between cbmem_top and tomk as unusable */ - delta_cbmem = tomk - ((uint32_t)cbmem_top() >> 10); + delta_cbmem = tomk - ((uintptr_t)cbmem_top() >> 10); tomk -= delta_cbmem; uma_sizek += delta_cbmem; diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index efdcbb6..31e94f4 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -1316,7 +1316,7 @@ void send_jedec_cmd(const struct sysinfo *s, u8 r, u8 ch, u8 cmd, u32 val) { - u32 addr = test_address(ch, r); + uintptr_t addr = test_address(ch, r); u8 data8 = cmd; u32 data32; @@ -2160,7 +2160,7 @@ if (s->boot_path == BOOT_PATH_NORMAL) { FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { for (bank = 0; bank < 4; bank++) - read32((u32 *)(test_address(ch, r) | 0x800000 | (bank << 12))); + read32((u32 *)((uintptr_t)test_address(ch, r) | 0x800000 | (bank << 12))); } } printk(BIOS_DEBUG, "Done dummy reads\n"); diff --git a/src/northbridge/intel/x4x/rcven.c b/src/northbridge/intel/x4x/rcven.c index 36a6ebd..c41bb07 100644 --- a/src/northbridge/intel/x4x/rcven.c +++ b/src/northbridge/intel/x4x/rcven.c @@ -39,7 +39,7 @@ asm volatile("mfence":::); } -static u8 sampledqs(u32 addr, u8 lane, u8 channel) +static u8 sampledqs(uintptr_t addr, u8 lane, u8 channel) { u32 sample_offset = 0x400 * channel + 0x561 + lane * 4; diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index 76d94c6..4809ee7 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -84,9 +84,9 @@ * MCHBAR */ -#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) +#define MCHBAR8(x) (*((volatile u8 *)((uintptr_t)DEFAULT_MCHBAR + (x)))) +#define MCHBAR16(x) (*((volatile u16 *)((uintptr_t)DEFAULT_MCHBAR + (x)))) +#define MCHBAR32(x) (*((volatile u32 *)((uintptr_t)DEFAULT_MCHBAR + (x)))) #define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) #define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or)) #define MCHBAR8_AND_OR(x, and, or) \ diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index a84a0df..a9c8863 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -275,7 +275,7 @@ { struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); uint8_t *rcrb; /* Root Complex Register Block */ - uint32_t rcba; /* Root Complex Base Address */ + uintptr_t rcba; /* Root Complex Base Address */ uint8_t bios_cntl; struct ich9_spi_regs *ich9_spi; struct ich7_spi_regs *ich7_spi; diff --git a/src/southbridge/intel/i82801jx/hdaudio.c b/src/southbridge/intel/i82801jx/hdaudio.c index 0628c43..2273e6c 100644 --- a/src/southbridge/intel/i82801jx/hdaudio.c +++ b/src/southbridge/intel/i82801jx/hdaudio.c @@ -276,10 +276,8 @@ if (!res) return; - // NOTE this will break as soon as the Azalia get's a bar above - // 4G. Is there anything we can do about it? base = res2mmio(res, 0, 0); - printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base); + printk(BIOS_DEBUG, "Azalia: base = %p\n", base); codec_mask = codec_detect(base); if (codec_mask) { diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index a395069..412e97f 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -669,7 +669,7 @@ /* Add it to SSDT. */ acpigen_write_scope("\\"); - acpigen_write_name_dword("NVSA", (u32) gnvs); + acpigen_write_name_dword("NVSA", (u32)(uintptr_t) gnvs); acpigen_pop_len(); } } diff --git a/src/southbridge/intel/i82801jx/sata.c b/src/southbridge/intel/i82801jx/sata.c index e6e08a3..70c5e69 100644 --- a/src/southbridge/intel/i82801jx/sata.c +++ b/src/southbridge/intel/i82801jx/sata.c @@ -37,7 +37,7 @@ u32 reg32; /* Initialize AHCI memory-mapped space */ - u8 *abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); + u8 *abar = (u8 *)(uintptr_t)pci_read_config32(dev, PCI_BASE_ADDRESS_5); printk(BIOS_DEBUG, "ABAR: %p\n", abar); /* Set AHCI access mode. -- To view, visit https://review.coreboot.org/c/coreboot/+/36779 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4851932975e99e06ba5650c2359a835b46d702d Gerrit-Change-Number: 36779 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 weeks

Change in coreboot[master]: mb/acer/aspire_vn7_572g: Adds support for an Acer laptop Adds initial...

by Benjamin Doron (Code Review)

Benjamin Doron has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35523 ) Change subject: mb/acer/aspire_vn7_572g: Adds support for an Acer laptop Adds initial, rudimentary support for Acer Aspire VN7-572G. May not boot correctly or at all. For testing purposes only. ...................................................................... mb/acer/aspire_vn7_572g: Adds support for an Acer laptop Adds initial, rudimentary support for Acer Aspire VN7-572G. May not boot correctly or at all. For testing purposes only. Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/acpi_tables.c A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/mainboard.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 18 files changed, 1,282 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/1 diff --git a/src/mainboard/acer/Kconfig b/src/mainboard/acer/Kconfig new file mode 100644 index 0000000..f56a2a2 --- /dev/null +++ b/src/mainboard/acer/Kconfig @@ -0,0 +1,16 @@ +if VENDOR_ACER + +choice + prompt "Mainboard model" + +source "src/mainboard/acer/*/Kconfig.name" + +endchoice + +source "src/mainboard/acer/*/Kconfig" + +config MAINBOARD_VENDOR + string "Mainboard Vendor" + default "Acer" + +endif # VENDOR_ACER diff --git a/src/mainboard/acer/Kconfig.name b/src/mainboard/acer/Kconfig.name new file mode 100644 index 0000000..bb177f9 --- /dev/null +++ b/src/mainboard/acer/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_ACER + bool "Acer" diff --git a/src/mainboard/acer/aspire_vn7_572g/Kconfig b/src/mainboard/acer/aspire_vn7_572g/Kconfig new file mode 100644 index 0000000..4b3c127 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/Kconfig @@ -0,0 +1,68 @@ +if BOARD_ACER_VN7_572G + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SYSTEM_TYPE_LAPTOP + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SOC_INTEL_SKYLAKE + select MAINBOARD_USES_FSP2_0 + select SPD_READ_BY_WORD + select MAINBOARD_HAS_LPC_TPM + select NO_POST # This platform has no way to see POST codes so disable them by default. + +config IRQ_SLOT_COUNT + int + default 18 + +config MAINBOARD_VENDOR + string + default "Acer" + +config MAINBOARD_FAMILY + string + default "Aspire V Nitro" + +config MAINBOARD_PART_NUMBER + string + default "Aspire VN7-572G" + +config MAINBOARD_DIR + string + default "acer/aspire_vn7_572g" + +config DEVICETREE + string + default "devicetree.cb" + +config MAX_CPUS + int + default 4 + +config VGA_BIOS_ID + string + default "8086,1916" + +config DIMM_MAX + int + default 2 + +config DIMM_SPD_SIZE + int + default 512 + +config CPU_MICROCODE_CBFS_LEN + hex + default 0x18000 + +config CPU_MICROCODE_CBFS_LOC + hex + default 0xFFE115A0 + +config CBFS_SIZE + hex + default 0x5c0000 + +endif diff --git a/src/mainboard/acer/aspire_vn7_572g/Kconfig.name b/src/mainboard/acer/aspire_vn7_572g/Kconfig.name new file mode 100644 index 0000000..b881680 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ACER_VN7_572G + bool "Aspire VN7-572G" diff --git a/src/mainboard/acer/aspire_vn7_572g/Makefile.inc b/src/mainboard/acer/aspire_vn7_572g/Makefile.inc new file mode 100644 index 0000000..35f0f6c --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/Makefile.inc @@ -0,0 +1,17 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2015 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-y += ramstage.c +ramstage-y += hda_verb.c diff --git a/src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl b/src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl new file mode 100644 index 0000000..2eed489 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl @@ -0,0 +1,328 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Name (EMBA, 0xFE800000) + +Device (EC0) +{ + Name (_HID, EisaId ("PNP0C09")) /* Embedded Controller Device */ // _HID: Hardware ID + + Name (_GPE, 0x50) // _GPE: General Purpose Events + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings + IO (Decode16, 0x62, 0x62, 0, 1) // Range Minimum, Range Maximum, Alignment, Length + IO (Decode16, 0x66, 0x66, 0, 1) // Range Minimum, Range Maximum, Alignment, Length + }) + OperationRegion (ECO1, SystemIO, 0x62, One) + Field (ECO1, ByteAcc, Lock, Preserve) + { + PX62, 8 + } + + OperationRegion (ECO2, SystemIO, 0x66, One) + Field (ECO2, ByteAcc, Lock, Preserve) + { + PX66, 8 + } + + OperationRegion (ECMB, SystemMemory, EMBA, 0x0200) + OperationRegion (RAM, EmbeddedControl, Zero, 0xFF) + Field (RAM, ByteAcc, Lock, Preserve) + { + CMDB, 8, + Offset (0x06), + CMD2, 8, + CMD1, 8, + CMD0, 8, + Offset (0x0A), + , 1, /* Reserved */ + , 1, /* Reserved */ + Offset (0x10), + EQEN, 1, + , 1, /* Reserved */ + Offset (0x4E), + ISEN, 1, /* Sense? (0=Not Exist, 1=Exist) */ + Offset (0x51), + , 3, /* Reserved */ + TPEN, 1, + Offset (0x52), + WLEX, 1, /* Wireless LAN (0=Not Exist, 1=Exist) */ + BTEX, 1, /* Bluetooth? (0=Not Exist, 1=Exist) */ + EX3G, 1, /* 3G (0=Not Exist, 1=Exist) */ + , 3, /* Reserved */ + RFEX, 1, + Offset (0x57), + , 7, /* Reserved */ + AHKB, 1, + AHKE, 8, + Offset (0x5C), + Offset (0x5D), + Offset (0x70), + , 1, /* Reserved */ + KLID, 1, /* LID? */ + , 3, /* Reserved */ + KACS, 1, /* AC power? */ + Offset (0x71), + WLEN, 1, /* Wireless LAN (0=Not Enabled, 1=Enabled) */ + BTEN, 1, /* Bluetooth (0=Not Enabled, 1=Enabled) */ + , 3, /* Reserved */ + ISS3, 1, + ISS4, 1, + ISS5, 1, + Offset (0x74), + , 2, /* Reserved */ + , 1, /* Reserved */ + TPEX, 1, + Offset (0x75), + BLST, 1, + LMIB, 1, + Offset (0x76), + ECSS, 4, + EOSS, 4 + } + + Method (_REG, 2, NotSerialized) // _REG: Region Availability + { + /* Initialize AC power state */ + Store (KACS, \PWRS) + + /* Initialize LID switch state */ + Store (KLID, \LIDS) + } + + /* KEY_BRIGHTNESSUP */ + Method (_Q1C, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Notify (^^^GFX0.DD1F, 0x86) // Device-Specific + } + + /* KEY_BRIGHTNESSDOWN */ + Method (_Q1D, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Notify (^^^GFX0.DD1F, 0x87) // Device-Specific + } + + /* Battery Information Event */ + Method (_Q40, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Notify (BAT0, 0x81) // Information Change + } + + /* AC event */ + Method (_Q50, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Notify (ADP1, 0x80) // Status Change + } + + /* Lid event */ + Method (_Q52, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Notify (LID0, 0x80) // Status Change + } + + /* Battery Information Event */ + Method (_Q41, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Notify (BAT0, 0x81) // Information Change + } + + /* Battery Status Event */ + Method (_Q48, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Notify (BAT0, 0x80) // Status Change + } + + Method (ECWK, 1, NotSerialized) + { + EQEN = One + Notify (BAT0, 0x81) // Information Change + If (((Arg0 == 0x03) || (Arg0 == 0x04))) + { + Notify (SLPB, 0x02) // Device Wake + } + } + + Name (B0ST, Zero) + Field (ECMB, ByteAcc, Lock, Preserve) + { + Offset (0x08), + MB0S, 8 + } + + OperationRegion (MBB0, SystemMemory, (EMBA + 0x80), 0xFF) + Field (MBB0, ByteAcc, Lock, Preserve) + { + MBRC, 16, + MBFC, 16, + MBPE, 16, + MBAC, 16, + MBVO, 16, + , 15, + MBCM, 1, + MBCU, 16, + MBTV, 16 + } + + Method (GBIF, 3, NotSerialized) + { + If (Arg2) + { + Arg1 [One] = 0xFFFFFFFF + Arg1 [0x02] = 0xFFFFFFFF + Arg1 [0x04] = 0xFFFFFFFF + Arg1 [0x05] = Zero + Arg1 [0x06] = Zero + } + + Return (Arg1) + } + + Method (GBST, 4, NotSerialized) + { + Local0 = Zero + + If ((Arg1 & One)) + { + Local1 = MBAC /* \_SB_.PCI0.LPCB.EC0_.MBAC */ + Local2 = MBRC /* \_SB_.PCI0.LPCB.EC0_.MBRC */ + If (ACST) + { + If ((Arg1 & 0x20)) + { + Local2 = MBFC /* \_SB_.PCI0.LPCB.EC0_.MBFC */ + } + } + + Local3 = MBVO /* \_SB_.PCI0.LPCB.EC0_.MBVO */ + If ((Local1 >= 0x8000)) + { + If ((Local0 & One)) + { + Local1 = (0x00010000 - Local1) + } + Else + { + Local1 = Zero + } + } + + If (Arg2) + { + Local1 *= Local3 + Divide (Local1, 0x03E8, Local1) + } + } + Else + { + Local0 = Zero + Local1 = 0xFFFFFFFF + Local2 = 0xFFFFFFFF + Local3 = 0xFFFFFFFF + } + + Arg3 [Zero] = Local0 + Arg3 [One] = Local1 + Arg3 [0x02] = Local2 + Arg3 [0x03] = Local3 + Return (Arg3) + } + + Name (ACST, One) + Device (ADP1) + { + Name (_HID, "ACPI0003") /* Power Source Device */ // _HID: Hardware ID + Name (_PCL, Package () { \_SB }) // _PCL: Power Consumer List + Method (_PSR) // _PSR: Power Source + { + Return (\PWRS) + } + Method (_STA) // _STA: Status + { + Return (0x0F) + } + } + + Device (BAT0) + { + Name (_HID, EisaId ("PNP0C0A")) /* Control Method Battery */ // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Method (_PCL, 0, NotSerialized) // _PCL: Power Consumer List + { + Return (_SB) /* \_SB_ */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + If (B0ST) + { + Return (0x1F) + } + Else + { + Return (0x0F) + } + } + + Name (B0IP, Package (0x0D) + { + 0x00000001, /* 0x00: Power Unit: mAH */ + 0xFFFFFFFF, /* 0x01: Design Capacity */ + 0xFFFFFFFF, /* 0x02: Last Full Charge Capacity */ + 0x00000001, /* 0x03: Battery Technology: Rechargeable */ + 0xFFFFFFFF, /* 0x04: Design Voltage */ + 0x00000000, /* 0x05: Design Capacity of Warning */ + 0x00000000, /* 0x06: Design Capacity of Low */ + 0x00000001, /* 0x07: Capacity Granularity 1 */ + 0x00000001, /* 0x08: Capacity Granularity 2 */ + "", /* 0x09: Model Number */ + "100", /* 0x0a: Serial Number */ + "Lion", /* 0x0b: Battery Type */ + 0x00000000 /* 0x0c: OEM Information */ + }) + + Method (_BIF, 0, NotSerialized) // _BIF: Battery Information + { + Local6 = B0ST /* \_SB_.PCI0.LPCB.EC0_.B0ST */ + While ((Local6)) + { + Local1 = MB0S /* \_SB_.PCI0.LPCB.EC0_.MB0S */ + If ((Local1 & 0x08)) + { + Local6 = Zero + } + } + + Return (GBIF (Zero, B0IP, Local6)) + } + + Name (B0SP, Package (0x04) + { + 0x00000000, /* 0x00: Battery State */ + 0xFFFFFFFF, /* 0x01: Battery Present Rate */ + 0xFFFFFFFF, /* 0x02: Battery Remaining Capacity */ + 0xFFFFFFFF /* 0x03: Battery Present Voltage */ + }) + + Method (_BST, 0, NotSerialized) // _BST: Battery Status + { + Local0 = (DerefOf (B0IP [Zero]) ^ One) + Return (GBST (Zero, MB0S, Local0, B0SP)) + } + } +} diff --git a/src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl b/src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl new file mode 100644 index 0000000..e145a2b --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +OperationRegion (SANV, SystemMemory, 0x7CE5FD98, Zero) +Field (SANV, AnyAcc, Lock, Preserve) +{ + BRTL, 8 +} + +Scope (\_SB.PCI0) +{ + Device (GFX0) + { + Name (_ADR, 0x00020000) // _ADR: Address + + Device (DD1F) + { + Method (_ADR, 0, Serialized) // _ADR: Address + { + Return (0x1F) + } + + Method (_BCL, 0, NotSerialized) // _BCL: Brightness Control Levels + { + Return (Package (0x0C) + { + 0x50, + 0x32, + 0x0A, + 0x14, + 0x1E, + 0x28, + 0x32, + 0x3C, + 0x46, + 0x50, + 0x5A, + 0x64 + }) + } + + Method (_BCM, 1, NotSerialized) // _BCM: Brightness Control Method + { + If (((Arg0 >= Zero) && (Arg0 <= 0x64))) + { + BRTL = Arg0 + } + } + + Method (_BQC, 0, NotSerialized) // _BQC: Brightness Query Current + { + Return (BRTL) /* \BRTL */ + } + } + } +} diff --git a/src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl b/src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl new file mode 100644 index 0000000..90e75f2 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB) +{ + Device (LID0) /* Lid Device */ + { + Name (_HID, EisaId ("PNP0C0D")) + + Method (_STA) // _STA: Status + { + Return (0xF) + } + + Method (_LID) // _LID: Lid Status + { + Return (\LIDS) + } + } + + Device (PWRB) + { + Name (_HID, EisaId ("PNP0C0C")) + + Method (_STA) + { + Return (0xF) + } + + Name (_PRW, Package () { 27, 4 }) + } + + Device (SLPB) /* Sleep Button Device */ // _HID: Hardware ID + { + Name (_HID, EisaId ("PNP0C0E")) + + Method (_STA) // _STA: Status + { + Return (0xF) + } + } +} diff --git a/src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl b/src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl new file mode 100644 index 0000000..92c272e --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/acer/aspire_vn7_572g/acpi_tables.c b/src/mainboard/acer/aspire_vn7_572g/acpi_tables.c new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/acpi_tables.c diff --git a/src/mainboard/acer/aspire_vn7_572g/board_info.txt b/src/mainboard/acer/aspire_vn7_572g/board_info.txt new file mode 100644 index 0000000..f16707e --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/board_info.txt @@ -0,0 +1,8 @@ +Vendor name: Acer +Board name: Aspire VN7-572G +Category: laptop +ROM package: SOIC8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2015 diff --git a/src/mainboard/acer/aspire_vn7_572g/devicetree.cb b/src/mainboard/acer/aspire_vn7_572g/devicetree.cb new file mode 100644 index 0000000..f38b0b8 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/devicetree.cb @@ -0,0 +1,218 @@ +chip soc/intel/skylake + + # Disable deep Sx states + register "deep_s3_enable_ac" = "0" + register "deep_s3_enable_dc" = "0" + register "deep_s5_enable_ac" = "0" + register "deep_s5_enable_dc" = "0" + register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" + + register "eist_enable" = "1" + + # Set the Thermal Control Circuit (TCC) activaction value to 95C + # even though FSP integration guide says to set it to 100C for SKL-U + # (offset at 0), because when the TCC activates at 100C, the CPU + # will have already shut itself down from overheating protection. + register "tcc_offset" = "5" # TCC of 95C + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_C" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + # EC host command ranges are in 0x60-0x66 + register "gen1_dec" = "0x00000061" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # Disable DPTF + register "dptf_enable" = "0" + + # FSP Configuration + register "ProbelessTrace" = "0" + register "EnableLan" = "0" + register "EnableSata" = "1" + register "SataSalpSupport" = "1" + register "SataMode" = "0" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsEnable[2]" = "1" + register "SataPortsDevSlp[0]" = "0" + register "SataPortsDevSlp[1]" = "0" + register "SataPortsDevSlp[2]" = "0" + register "EnableAzalia" = "1" + register "DspEnable" = "1" + register "IoBufferOwnership" = "0" + register "EnableTraceHub" = "0" + register "SsicPortEnable" = "0" + register "SmbusEnable" = "1" + register "Cio2Enable" = "0" + register "ScsEmmcEnabled" = "0" + register "ScsEmmcHs400Enabled" = "0" + register "ScsSdCardEnabled" = "0" + register "PttSwitch" = "0" + register "SkipExtGfxScan" = "0" + register "Device4Enable" = "0" + register "HeciEnabled" = "1" + register "SaGv" = "0" + register "PmConfigSlpS3MinAssert" = "2" # 50ms + register "PmConfigSlpS4MinAssert" = "1" # 1s + register "PmConfigSlpSusMinAssert" = "3" # 500ms + register "PmConfigSlpAMinAssert" = "3" # 2s + register "PmTimerDisabled" = "0" + + # EC/KBC requires continuous mode + register "serirq_mode" = "SERIRQ_CONTINUOUS" + + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + # VR Settings Configuration for 4 Domains + #+----------------+-----------+-----------+-------------+----------+ + #| Domain/Setting | SA | IA | GT Unsliced | GT | + #+----------------+-----------+-----------+-------------+----------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax | 7A | 34A | 35A | 35A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #+----------------+-----------+-----------+-------------+----------+ + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(4), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(7), + .voltage_limit = 1520, + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(34), + .voltage_limit = 1520, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(35), + .voltage_limit = 1520, + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(35), + .voltage_limit = 1520, + }" + + # Enable Root Ports 1, 9 and 10 + register "PcieRpEnable[2]" = "1" + register "PcieRpLtrEnable[2]" = "1" + register "PcieRpEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + register "PcieRpEnable[9]" = "1" + register "PcieRpLtrEnable[9]" = "1" + +# register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port + register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-A Port (right) + register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-A Port (right) + register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" # Type-A Port (left) + register "usb2_ports[4]" = "USB2_PORT_FLEX(OC2)" # Bluetooth + register "usb2_ports[6]" = "USB2_PORT_FLEX(OC2)" # Webcam + register "usb2_ports[7]" = "USB2_PORT_FLEX(OC2)" # SD + + # OC0 should be for Type-C but it seems to not have been wired, according to + # the available schematics, even though it is labeled as USB_OC_TYPEC. +# register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (right) + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (right) + + # PL2 override 25W + register "tdp_pl2_override" = "25" + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + + # Lock Down + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 14.0 on end # USB xHCI + device pci 14.1 on end # USB xDCI (OTG) + device pci 14.2 on end # Thermal Subsystem + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 on end # SATA + device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.1 on end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end # LPC Interface + device pci 1f.1 off end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/acer/aspire_vn7_572g/dsdt.asl b/src/mainboard/acer/aspire_vn7_572g/dsdt.asl new file mode 100644 index 0000000..c9bcb7d --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/dsdt.asl @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2016 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 // OEM revision +) +{ + // Some generic macros + #include <soc/intel/skylake/acpi/platform.asl> + + // global NVS and variables + #include <soc/intel/skylake/acpi/globalnvs.asl> + + // CPU + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + } + + // Chipset specific sleep states + #include <soc/intel/skylake/acpi/sleepstates.asl> + + // Mainboard specific + #include "acpi/mainboard.asl" + + // Graphics display + #include "acpi/graphics.asl" +} diff --git a/src/mainboard/acer/aspire_vn7_572g/gpio.h b/src/mainboard/acer/aspire_vn7_572g/gpio.h new file mode 100644 index 0000000..4d98da1 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/gpio.h @@ -0,0 +1,201 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +#ifndef __ACPI__ + +/* Pad configuration in ramstage. */ +static const struct pad_config gpio_table[] = { +_PAD_CFG_STRUCT(GPP_A0, 0x44000703, 0x0), /* RCIN# */ +_PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x3c00), /* LAD0 */ +_PAD_CFG_STRUCT(GPP_A2, 0x44000702, 0x3c00), /* LAD1 */ +_PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x3c00), /* LAD2 */ +_PAD_CFG_STRUCT(GPP_A4, 0x44000702, 0x3c00), /* LAD3 */ +_PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x0), /* LFRAME# */ +_PAD_CFG_STRUCT(GPP_A6, 0x44000702, 0x0), /* SERIRQ */ +_PAD_CFG_STRUCT(GPP_A7, 0x44000702, 0x0), /* PIRQA# */ +_PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x0), /* CLKRUN# */ +_PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x1000), /* CLKOUT_LPC0 */ +_PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x1000), /* CLKOUT_LPC1 */ +_PAD_CFG_STRUCT(GPP_A11, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_A12, 0x44000100, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_A13, 0x44000700, 0x0), /* SUSWARN#/SUSPWRDNACK */ +_PAD_CFG_STRUCT(GPP_A14, 0x44000700, 0x0), /* SUS_STAT# */ +_PAD_CFG_STRUCT(GPP_A15, 0x44000700, 0x1000), /* SUS_ACK# */ +_PAD_CFG_STRUCT(GPP_A16, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_A17, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_A18, 0x44000102, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_A19, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_A20, 0x44000100, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_A21, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_A22, 0x44000201, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_A23, 0x44000201, 0x1000), /* GPIO */ + +_PAD_CFG_STRUCT(GPP_B0, 0x44000700, 0x0), /* CORE_VID0 */ +_PAD_CFG_STRUCT(GPP_B1, 0x44000700, 0x0), /* CORE_VID1 */ +_PAD_CFG_STRUCT(GPP_B2, 0x44000100, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B3, 0x80100102, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B4, 0x44000200, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B5, 0x44000702, 0x0), /* SRCCLKREQ0# */ +_PAD_CFG_STRUCT(GPP_B6, 0x44000702, 0x0), /* SRCCLKREQ1# */ +_PAD_CFG_STRUCT(GPP_B7, 0x44000700, 0x0), /* SRCCLKREQ2# */ +_PAD_CFG_STRUCT(GPP_B8, 0x44000702, 0x0), /* SRCCLKREQ3# */ +_PAD_CFG_STRUCT(GPP_B9, 0x44000702, 0x0), /* SRCCLKREQ4# */ +_PAD_CFG_STRUCT(GPP_B10, 0x44000702, 0x0), /* SRCCLKREQ5# */ +_PAD_CFG_STRUCT(GPP_B11, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B12, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x0), /* PLTRST# */ +_PAD_CFG_STRUCT(GPP_B14, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B15, 0x44000200, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B16, 0x44000200, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B17, 0x42880100, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B18, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B19, 0x44000100, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B20, 0x44000102, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B21, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B22, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B23, 0x44000201, 0x1000), /* GPIO */ + +_PAD_CFG_STRUCT(GPP_C0, 0x44000702, 0x0), /* SMBCLK */ +_PAD_CFG_STRUCT(GPP_C1, 0x44000702, 0x1000), /* SMBDATA */ +_PAD_CFG_STRUCT(GPP_C2, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_C3, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_C4, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_C5, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_C6, 0x44000702, 0x0), /* SML1CLK */ +_PAD_CFG_STRUCT(GPP_C7, 0x44000702, 0x1000), /* SML1DATA */ +_PAD_CFG_STRUCT(GPP_C8, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_C9, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_C10, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_C11, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_C12, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_C13, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_C14, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_C15, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_C16, 0x44000702, 0x0), /* I2C0_SDA */ +_PAD_CFG_STRUCT(GPP_C17, 0x44000702, 0x0), /* I2C0_SCL */ +_PAD_CFG_STRUCT(GPP_C18, 0x44000702, 0x0), /* I2C1_SDA */ +_PAD_CFG_STRUCT(GPP_C19, 0x44000702, 0x0), /* I2C1_SCL */ +_PAD_CFG_STRUCT(GPP_C20, 0x44000702, 0x0), /* UART2_RXD */ +_PAD_CFG_STRUCT(GPP_C21, 0x44000700, 0x0), /* UART2_TXD */ +_PAD_CFG_STRUCT(GPP_C22, 0x44000700, 0x0), /* UART2_RTS# */ +_PAD_CFG_STRUCT(GPP_C23, 0x44000702, 0x0), /* UART2_CTS# */ + +_PAD_CFG_STRUCT(GPP_D0, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D1, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D2, 0x44000700, 0x0), /* SPI1_MISO */ +_PAD_CFG_STRUCT(GPP_D3, 0x44000700, 0x0), /* SPI1_MOSI */ +_PAD_CFG_STRUCT(GPP_D4, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D5, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D6, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D7, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D8, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D9, 0x40000102, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D10, 0x40000102, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D11, 0x40000102, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D12, 0x40000102, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D13, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D14, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D15, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D16, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D17, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D18, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D19, 0x44000700, 0x0), /* DMIC_CLK0 */ +_PAD_CFG_STRUCT(GPP_D20, 0x44000700, 0x0), /* DMIC_DATA0 */ +_PAD_CFG_STRUCT(GPP_D21, 0x44000700, 0x0), /* SPI1_IO2 */ +_PAD_CFG_STRUCT(GPP_D22, 0x44000700, 0x0), /* SPI1_IO3 */ +_PAD_CFG_STRUCT(GPP_D23, 0x44000201, 0x1000), /* GPIO */ + +_PAD_CFG_STRUCT(GPP_E0, 0x44000700, 0x0), /* SATAXPCIE0 */ +_PAD_CFG_STRUCT(GPP_E1, 0x44000700, 0x0), /* SATAXPCIE1 */ +_PAD_CFG_STRUCT(GPP_E2, 0x44000702, 0x0), /* SATAXPCIE2 */ +_PAD_CFG_STRUCT(GPP_E3, 0x44000201, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_E4, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_E5, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_E6, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_E7, 0x40900100, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_E8, 0xffffffff, 0xffffff00),/* RESERVED */ +_PAD_CFG_STRUCT(GPP_E9, 0x44000702, 0x0), /* USB2_OC0# */ +_PAD_CFG_STRUCT(GPP_E10, 0x44000702, 0x0), /* USB2_OC1# */ +_PAD_CFG_STRUCT(GPP_E11, 0x44000702, 0x0), /* USB2_OC2# */ +_PAD_CFG_STRUCT(GPP_E12, 0x44000702, 0x0), /* USB2_OC3# */ +_PAD_CFG_STRUCT(GPP_E13, 0x44000700, 0x0), /* DDPB_HPD0 */ +_PAD_CFG_STRUCT(GPP_E14, 0x44000700, 0x0), /* DDPC_HPD1 */ +_PAD_CFG_STRUCT(GPP_E15, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_E16, 0x80880102, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_E17, 0x44000702, 0x0), /* EDP_HPD */ +_PAD_CFG_STRUCT(GPP_E18, 0x44000702, 0x0), /* DDPB_CTRLCLK */ +_PAD_CFG_STRUCT(GPP_E19, 0x44000702, 0x1000), /* DDPB_CTRLDATA */ +_PAD_CFG_STRUCT(GPP_E20, 0x44000700, 0x0), /* DDPC_CTRLCLK */ +_PAD_CFG_STRUCT(GPP_E21, 0x44000702, 0x1000), /* DDPC_CTRLDATA */ +_PAD_CFG_STRUCT(GPP_E22, 0x40100000, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_E23, 0x44000201, 0x1000), /* GPIO */ + +_PAD_CFG_STRUCT(GPD0, 0x4000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPD1, 0x4000702, 0x0), /* ACPRESENT */ +_PAD_CFG_STRUCT(GPD2, 0x4000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPD3, 0x4000702, 0x3000), /* PWRBTN# */ +_PAD_CFG_STRUCT(GPD4, 0x4000700, 0x0), /* SLP_S3# */ +_PAD_CFG_STRUCT(GPD5, 0x4000700, 0x0), /* SLP_S4# */ +_PAD_CFG_STRUCT(GPD6, 0x4000601, 0x1000), /* SLP_A# */ +_PAD_CFG_STRUCT(GPD7, 0x4000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPD8, 0x4000700, 0x0), /* SUSCLK */ +_PAD_CFG_STRUCT(GPD9, 0x4000601, 0x1000), /* SLP_WLAN# */ +_PAD_CFG_STRUCT(GPD10, 0x4000601, 0x1000), /* SLP_S5# */ +_PAD_CFG_STRUCT(GPD11, 0x4000201, 0x1000), /* GPIO */ + +_PAD_CFG_STRUCT(GPP_F0, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F1, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F2, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F3, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F4, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F5, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F6, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F7, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F8, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F9, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F10, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F11, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F12, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F13, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F14, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F15, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F16, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F17, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F18, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F19, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F20, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F21, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F22, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F23, 0x40100100, 0x0), /* GPIO */ + +_PAD_CFG_STRUCT(GPP_G0, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_G1, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_G2, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_G3, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_G4, 0x44000200, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_G5, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_G6, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_G7, 0x44000201, 0x1000), /* GPIO */ +}; + +#endif + +#endif diff --git a/src/mainboard/acer/aspire_vn7_572g/hda_verb.c b/src/mainboard/acer/aspire_vn7_572g/hda_verb.c new file mode 100644 index 0000000..8cd5f97 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/hda_verb.c @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Purism SPC. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0255, /* Codec Vendor / Device ID: Realtek ALC255 */ + 0x10251037, /* Subsystem ID */ + 0x0000000c, /* Number of jacks (NID entries) */ + + 0x0017ff00, /* Function Reset */ + 0x0017ff00, /* Double Function Reset */ + 0x0017ff00, + 0x0017ff00, + + /* Bits 31:28 - Codec Address */ + /* Bits 27:20 - NID */ + /* Bits 19:8 - Verb ID */ + /* Bits 7:0 - Payload */ + + /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x10251037 */ + AZALIA_SUBVENDOR(0x0, 0x10251037), + + /* Pin Widget Verb Table */ + + /* Pin Complex (NID 0x12) */ + AZALIA_PIN_CFG(0x0, 0x12, 0x411111c0), + + /* Pin Complex (NID 0x14) */ + AZALIA_PIN_CFG(0x0, 0x14, 0x90172120), + + /* Pin Complex (NID 0x17) */ + AZALIA_PIN_CFG(0x0, 0x17, 0x40000000), + + /* Pin Complex (NID 0x18) */ + AZALIA_PIN_CFG(0x0, 0x18, 0x411111f0), + + /* Pin Complex (NID 0x19) */ + AZALIA_PIN_CFG(0x0, 0x19, 0x411111f0), + + /* Pin Complex (NID 0x1A) */ + AZALIA_PIN_CFG(0x0, 0x1A, 0x411111f0), + + /* Pin Complex (NID 0x1B) */ + AZALIA_PIN_CFG(0x0, 0x1B, 0x411111f0), + + /* Pin Complex (NID 0x1D) */ + AZALIA_PIN_CFG(0x0, 0x1D, 0x40700001), + + /* Pin Complex (NID 0x1E) */ + AZALIA_PIN_CFG(0x0, 0x1E, 0x411111f0), + + /* Pin Complex (NID 0x21) */ + AZALIA_PIN_CFG(0x0, 0x21, 0x02211030), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/acer/aspire_vn7_572g/mainboard.c b/src/mainboard/acer/aspire_vn7_572g/mainboard.c new file mode 100644 index 0000000..462b995 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/mainboard.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Purism SPC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <smbios.h> +#include <string.h> +#include <cbfs.h> + +#define MAX_SERIAL_LENGTH 0x100 + +const char *smbios_mainboard_serial_number(void) +{ + static char serial_number[MAX_SERIAL_LENGTH + 1] = {0}; + struct cbfsf file; + + if (serial_number[0] != 0) + return serial_number; + + if (cbfs_boot_locate(&file, "serial_number", NULL) == 0) { + struct region_device cbfs_region; + size_t serial_len; + + cbfs_file_data(&cbfs_region, &file); + + serial_len = region_device_sz(&cbfs_region); + if (serial_len <= MAX_SERIAL_LENGTH) { + if (rdev_readat(&cbfs_region, serial_number, 0, + serial_len) == serial_len) { + serial_number[serial_len] = 0; + return serial_number; + } + } + } + + strncpy(serial_number, CONFIG_MAINBOARD_SERIAL_NUMBER, + MAX_SERIAL_LENGTH); + + return serial_number; +} diff --git a/src/mainboard/acer/aspire_vn7_572g/ramstage.c b/src/mainboard/acer/aspire_vn7_572g/ramstage.c new file mode 100644 index 0000000..94f8071 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/ramstage.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corporation + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/ramstage.h> +#include "gpio.h" + +void mainboard_silicon_init_params(FSP_SIL_UPD *params) +{ + /* Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/acer/aspire_vn7_572g/romstage.c b/src/mainboard/acer/aspire_vn7_572g/romstage.c new file mode 100644 index 0000000..86ef5af --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/romstage.c @@ -0,0 +1,84 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation + * Copyright (C) 2017 Purism SPC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <assert.h> +#include <soc/romstage.h> +#include <spd_bin.h> +#include <string.h> + +static void mainboard_fill_dq_map_data(void *dq_map_ch0, void *dq_map_ch1) +{ + /* DQ byte map */ + const u8 dq_map[2][12] = { + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, + { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, + 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; + memcpy(dq_map_ch0, dq_map[0], sizeof(dq_map[0])); + memcpy(dq_map_ch1, dq_map[1], sizeof(dq_map[1])); +} + +static void mainboard_fill_dqs_map_data(void *dqs_map_ch0, void *dqs_map_ch1) +{ + /* DQS CPU<>DRAM map */ + const u8 dqs_map[2][8] = { + { 0, 1, 3, 2, 4, 5, 6, 7 }, + { 1, 0, 4, 5, 2, 3, 6, 7 } }; + memcpy(dqs_map_ch0, dqs_map[0], sizeof(dqs_map[0])); + memcpy(dqs_map_ch1, dqs_map[1], sizeof(dqs_map[1])); +} + +static void mainboard_fill_rcomp_res_data(void *rcomp_ptr) +{ + /* Rcomp resistor */ + const u16 RcompResistor[3] = { 121, 81, 100 }; + memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor)); +} + +static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) +{ + /* Rcomp target */ + const u16 RcompTarget[5] = { 100, 40, 20, 20, 26 }; + memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); +} + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg; + struct spd_block blk = { + .addr_map = { 0x50, 0x52 }, + }; + + mem_cfg = &mupd->FspmConfig; + + get_spd_smbus(&blk); + dump_spd_info(&blk); + assert(blk.spd_array[0][0] != 0); + + mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0, + &mem_cfg->DqByteMapCh1); + mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0, + &mem_cfg->DqsMapCpu2DramCh1); + mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); + mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); + + mem_cfg->DqPinsInterleaved = TRUE; + mem_cfg->MemorySpdDataLen = blk.len; + mem_cfg->MemorySpdPtr00 = (uintptr_t) blk.spd_array[0]; + mem_cfg->MemorySpdPtr10 = (uintptr_t) blk.spd_array[1]; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/35523 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Gerrit-Change-Number: 35523 Gerrit-PatchSet: 1 Gerrit-Owner: Benjamin Doron Gerrit-MessageType: newchange

1 month

Change in coreboot[master]: soc/intel/common/block/cpu/car: Enable caching before FSP-T

by Gaggery Tsai (Code Review)

Gaggery Tsai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38252 ) Change subject: soc/intel/common/block/cpu/car: Enable caching before FSP-T ...................................................................... soc/intel/common/block/cpu/car: Enable caching before FSP-T This patch is required for Boot Guard enabled platform. Enable caching before entering FSP-T. TEST=Stitch boot guard ACM with signed KM and BPM && Enable FSP-T and boot all the way to the OS && Read MSR 0x13a and esnure boot guard verified boot and measured boot are enabled. Change-Id: Ie1def754f7b0024725638fcea481fd3273ef3d24 --- M src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/38252/1 diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S index 091fc4a..fd22903 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S @@ -35,6 +35,12 @@ cache_as_ram: post_code(0x21) + /* Enable caching */ + mov %cr0, %eax + and $~(CR0_CD | CR0_NW), %eax + invd + mov %eax, %cr0 + /* find fsp in cbfs */ lea fsp_name, %esi mov $1f, %esp -- To view, visit https://review.coreboot.org/c/coreboot/+/38252 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie1def754f7b0024725638fcea481fd3273ef3d24 Gerrit-Change-Number: 38252 Gerrit-PatchSet: 1 Gerrit-Owner: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-MessageType: newchange

1 month

Change in ...coreboot[master]: mb/apple: Add MacBook Pro 10,1 (A1398) support

by Evgeny Zinoviev (Code Review)

Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32673 Change subject: mb/apple: Add MacBook Pro 10,1 (A1398) support ...................................................................... mb/apple: Add MacBook Pro 10,1 (A1398) support MacBook Pro Retina 15 (Mid 2012) with Ivy Bridge CPU. This is WIP. Not for merging. Change-Id: Ica03aba442493c0d369a3d360ad569ddc16954df Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- M 3rdparty/vboot A src/mainboard/apple/macbookpro10_1/Kconfig A src/mainboard/apple/macbookpro10_1/Kconfig.name A src/mainboard/apple/macbookpro10_1/Makefile.inc A src/mainboard/apple/macbookpro10_1/acpi/ec.asl A src/mainboard/apple/macbookpro10_1/acpi/platform.asl A src/mainboard/apple/macbookpro10_1/acpi/superio.asl A src/mainboard/apple/macbookpro10_1/acpi_tables.c A src/mainboard/apple/macbookpro10_1/board_info.txt A src/mainboard/apple/macbookpro10_1/devicetree.cb A src/mainboard/apple/macbookpro10_1/dsdt.asl A src/mainboard/apple/macbookpro10_1/gma-mainboard.ads A src/mainboard/apple/macbookpro10_1/gpio.c A src/mainboard/apple/macbookpro10_1/hda_verb.c A src/mainboard/apple/macbookpro10_1/mainboard.c A src/mainboard/apple/macbookpro10_1/romstage.c 16 files changed, 758 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/32673/1 diff --git a/3rdparty/vboot b/3rdparty/vboot index e7edff6..304aa42 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit e7edff6653e16ed915c3ad12234d133d1ef4dcc9 +Subproject commit 304aa429c1a04cda3ab2ce37b9e31af84405bfca diff --git a/src/mainboard/apple/macbookpro10_1/Kconfig b/src/mainboard/apple/macbookpro10_1/Kconfig new file mode 100644 index 0000000..603f3ee --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/Kconfig @@ -0,0 +1,46 @@ +if BOARD_APPLE_MACBOOKPRO10_1 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select EC_ACPI + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select NORTHBRIDGE_INTEL_IVYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_C216 + select SYSTEM_TYPE_LAPTOP + select USE_NATIVE_RAMINIT + select MAINBOARD_HAS_LIBGFXINIT + select GFX_GMA_INTERNAL_IS_EDP + select SERIRQ_CONTINUOUS_MODE + +config MAINBOARD_DIR + string + default apple/macbookpro10_1 + +config MAINBOARD_PART_NUMBER + string + default "MacBookPro10,1" + +config VGA_BIOS_FILE + string + default "pci8086,0166.rom" + +config VGA_BIOS_ID + string + default "8086,0166" + +config DRAM_RESET_GATE_GPIO + int + default 28 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX # FIXME: check this + int + default 2 +endif diff --git a/src/mainboard/apple/macbookpro10_1/Kconfig.name b/src/mainboard/apple/macbookpro10_1/Kconfig.name new file mode 100644 index 0000000..c257f7a --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_APPLE_MACBOOKPRO10_1 + bool "MacBookPro10,1" diff --git a/src/mainboard/apple/macbookpro10_1/Makefile.inc b/src/mainboard/apple/macbookpro10_1/Makefile.inc new file mode 100644 index 0000000..fd60338 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/Makefile.inc @@ -0,0 +1,7 @@ +romstage-y += gpio.c + +cbfs-files-y += spd.bin +spd.bin-file := spd.bin +spd.bin-type := spd + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/apple/macbookpro10_1/acpi/ec.asl b/src/mainboard/apple/macbookpro10_1/acpi/ec.asl new file mode 100644 index 0000000..f70cb3d --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/acpi/ec.asl @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device(EC) +{ + Name (_HID, EISAID("PNP0C09")) + Name (_UID, 0) + Name (_GPE, 23) +/* FIXME: EC support */ +} diff --git a/src/mainboard/apple/macbookpro10_1/acpi/platform.asl b/src/mainboard/apple/macbookpro10_1/acpi/platform.asl new file mode 100644 index 0000000..a17c6ea --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/acpi/platform.asl @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_WAK,1) +{ + /* FIXME: EC support */ + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ + /* FIXME: EC support */ +} diff --git a/src/mainboard/apple/macbookpro10_1/acpi/superio.asl b/src/mainboard/apple/macbookpro10_1/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/acpi/superio.asl diff --git a/src/mainboard/apple/macbookpro10_1/acpi_tables.c b/src/mainboard/apple/macbookpro10_1/acpi_tables.c new file mode 100644 index 0000000..c48f0bd --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/acpi_tables.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> + +/* FIXME: check this function. */ +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + // the lid is open by default. + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/apple/macbookpro10_1/board_info.txt b/src/mainboard/apple/macbookpro10_1/board_info.txt new file mode 100644 index 0000000..81a5134 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/board_info.txt @@ -0,0 +1,6 @@ +Category: laptop +ROM protocol: SPI +Flashrom support: n +ROM package: SOIC-8 +ROM socketed: n +Release year: 2012 diff --git a/src/mainboard/apple/macbookpro10_1/devicetree.cb b/src/mainboard/apple/macbookpro10_1/devicetree.cb new file mode 100644 index 0000000..f9e7eb4 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/devicetree.cb @@ -0,0 +1,124 @@ +chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did + #register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" + register "gfx.did" = "{ 0x80000410, 0x80000320, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx.link_frequency_270_mhz" = "0" + register "gfx.ndid" = "3" + register "gfx.use_spread_spectrum_clock" = "1" + register "gpu_cpu_backlight" = "0xffffffff" + register "gpu_dp_b_hotplug" = "7" + register "gpu_dp_c_hotplug" = "7" + register "gpu_dp_d_hotplug" = "7" + register "gpu_panel_port_select" = "3" + register "gpu_panel_power_backlight_off_delay" = "8191" + register "gpu_panel_power_backlight_on_delay" = "8191" + register "gpu_panel_power_cycle_delay" = "255" + register "gpu_panel_power_down_delay" = "8191" + register "gpu_panel_power_up_delay" = "8191" + register "gpu_pch_backlight" = "0xffffffff" + device cpu_cluster 0x0 on + chip cpu/intel/model_206ax # FIXME: check all registers + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on + end + device lapic 0xacac off + end + end + end + device domain 0x0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "0" + register "gen1_dec" = "0x000c0681" + register "gen2_dec" = "0x000c1641" + register "gen3_dec" = "0x001c0301" + register "gen4_dec" = "0x00fc0701" + register "gpi7_routing" = "2" + register "p_cnt_throttling_supported" = "1" + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x1" + register "spi_lvscc" = "0x0" + register "spi_uvscc" = "0x2005" + register "superspeed_capable_ports" = "0x0000000f" + register "xhci_overcurrent_mapping" = "0x08040201" + register "xhci_switchable_ports" = "0x0000000f" + device pci 14.0 on # USB 3.0 Controller + subsystemid 0x8086 0x7270 + end + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x8086 0x7270 + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 off # Management Engine KT + end + device pci 19.0 off # Intel Gigabit Ethernet + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x8086 0x7270 + end + device pci 1b.0 on # High Definition Audio Audio controller + subsystemid 0x8086 0x7270 + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x8086 0x7270 + end + device pci 1c.1 on # PCIe Port #2 + subsystemid 0x8086 0x7270 + end + device pci 1c.2 off # PCIe Port #3 + end + device pci 1c.3 off # PCIe Port #4 + end + device pci 1c.4 off # PCIe Port #5 + end + device pci 1c.5 off # PCIe Port #6 + end + device pci 1c.6 off # PCIe Port #7 + end + device pci 1c.7 off # PCIe Port #8 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x8086 0x7270 + end + device pci 1e.0 off # PCI bridge + end + device pci 1f.0 on # LPC bridge PCI-LPC bridge + subsystemid 0x8086 0x7270 + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x8086 0x7270 + end + device pci 1f.3 on # SMBus + subsystemid 0x8086 0x7270 + end + device pci 1f.5 off # SATA Controller 2 + end + device pci 1f.6 off # Thermal + end + end + device pci 00.0 on # Host bridge Host bridge + subsystemid 0x106b 0x00f7 + end + device pci 01.0 on # PCIe Bridge for discrete graphics + subsystemid 0x106b 0x00f7 + end + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x106b 0x00f7 + end + device pci 01.2 on + subsystemid 0x106b 0x00f7 + end + device pci 01.1 on + subsystemid 0x106b 0x00f7 + end + end +end diff --git a/src/mainboard/apple/macbookpro10_1/dsdt.asl b/src/mainboard/apple/macbookpro10_1/dsdt.asl new file mode 100644 index 0000000..455ac17 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/dsdt.asl @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI 2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 // OEM revision +) +{ + /* Some generic macros */ + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/apple/macbookpro10_1/gma-mainboard.ads b/src/mainboard/apple/macbookpro10_1/gma-mainboard.ads new file mode 100644 index 0000000..d4a5d7d --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/gma-mainboard.ads @@ -0,0 +1,34 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + Internal, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/apple/macbookpro10_1/gpio.c b/src/mainboard/apple/macbookpro10_1/gpio.c new file mode 100644 index 0000000..a445687 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/gpio.c @@ -0,0 +1,243 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_OUTPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_OUTPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio26 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_LOW, + .gpio15 = GPIO_LEVEL_HIGH, + .gpio16 = GPIO_LEVEL_LOW, + .gpio19 = GPIO_LEVEL_HIGH, + .gpio21 = GPIO_LEVEL_LOW, + .gpio22 = GPIO_LEVEL_LOW, + .gpio23 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio11 = GPIO_RESET_RSMRST, + .gpio15 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio2 = GPIO_INVERT, + .gpio4 = GPIO_INVERT, + .gpio5 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_GPIO, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_OUTPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio47 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_OUTPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_OUTPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_OUTPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio34 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, + .gpio36 = GPIO_LEVEL_LOW, + .gpio48 = GPIO_LEVEL_HIGH, + .gpio49 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio52 = GPIO_LEVEL_LOW, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio54 = GPIO_LEVEL_LOW, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_GPIO, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_GPIO, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_NATIVE, + .gpio73 = GPIO_MODE_GPIO, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_OUTPUT, + .gpio65 = GPIO_DIR_OUTPUT, + .gpio66 = GPIO_DIR_OUTPUT, + .gpio67 = GPIO_DIR_OUTPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio73 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio64 = GPIO_LEVEL_LOW, + .gpio65 = GPIO_LEVEL_LOW, + .gpio66 = GPIO_LEVEL_LOW, + .gpio67 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/apple/macbookpro10_1/hda_verb.c b/src/mainboard/apple/macbookpro10_1/hda_verb.c new file mode 100644 index 0000000..b8e4855 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/hda_verb.c @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10134206, /* Codec Vendor / Device ID: Cirrus */ + 0x106b2800, /* Subsystem ID */ + + 0x0000000b, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x0, 0x106b2800), + + /* NID 0x09. */ + AZALIA_PIN_CFG(0x0, 0x09, 0x002b4020), + + /* NID 0x0a. */ + AZALIA_PIN_CFG(0x0, 0x0a, 0x90100112), + + /* NID 0x0b. */ + AZALIA_PIN_CFG(0x0, 0x0b, 0x90100110), + + /* NID 0x0c. */ + AZALIA_PIN_CFG(0x0, 0x0c, 0x400000f0), + + /* NID 0x0d. */ + AZALIA_PIN_CFG(0x0, 0x0d, 0x400000f0), + + /* NID 0x0e. */ + AZALIA_PIN_CFG(0x0, 0x0e, 0x90a60100), + + /* NID 0x0f. */ + AZALIA_PIN_CFG(0x0, 0x0f, 0x400000f0), + + /* NID 0x10. */ + AZALIA_PIN_CFG(0x0, 0x10, 0x004be030), + + /* NID 0x12. */ + AZALIA_PIN_CFG(0x0, 0x12, 0x400000f0), + + /* NID 0x15. */ + AZALIA_PIN_CFG(0x0, 0x15, 0x400000f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/apple/macbookpro10_1/mainboard.c b/src/mainboard/apple/macbookpro10_1/mainboard.c new file mode 100644 index 0000000..3910541 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/mainboard.c @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <ec/acpi/ec.h> +#include <console/console.h> + +static void mainboard_init(struct device *dev) +{ + +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = mainboard_init; + + /* FIXME: fix those values*/ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/apple/macbookpro10_1/romstage.c b/src/mainboard/apple/macbookpro10_1/romstage.c new file mode 100644 index 0000000..c35604b --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/romstage.c @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* FIXME: Check if all includes are needed. */ + +#include <stdint.h> +#include <string.h> +#include <timestamp.h> +#include <arch/byteorder.h> +#include <arch/io.h> +#include <device/mmio.h> +#include <device/pci_ops.h> +#include <device/pnp_ops.h> +#include <console/console.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/gpio.h> +#include <cbfs.h> + +void pch_enable_lpc(void) +{ + pci_write_config16(PCH_LPC_DEV, 0x82, 0x3f0f); + pci_write_config32(PCH_LPC_DEV, 0x84, 0x000c0681); + pci_write_config32(PCH_LPC_DEV, 0x88, 0x000c1641); + pci_write_config32(PCH_LPC_DEV, 0x8c, 0x001c0301); + pci_write_config32(PCH_LPC_DEV, 0x90, 0x00fc0701); + pci_write_config16(PCH_LPC_DEV, 0x80, 0x0070); +} + +void mainboard_rcba_config(void) +{ +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, 0 }, + { 1, 0, 1 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, +}; + +void mainboard_early_init(int s3resume) +{ +} + +void mainboard_config_superio(void) +{ +} + +// FIXME +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + void *spd_file; + size_t spd_file_len = 0; + spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, + &spd_file_len); + if (spd_file && spd_file_len >= 128) { + memcpy(&spd[0], spd_file, 128); + memcpy(&spd[2], spd_file, 128); + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/32673 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica03aba442493c0d369a3d360ad569ddc16954df Gerrit-Change-Number: 32673 Gerrit-PatchSet: 1 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-MessageType: newchange

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