March 2020 - coreboot-gerrit - mail.coreboot.org

Change in coreboot[master]: drivers/i2c/nct7802y: configure local temp sensor [WIP]

by Maxim Polyakov (Code Review)

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39766 ) Change subject: drivers/i2c/nct7802y: configure local temp sensor [WIP] ...................................................................... drivers/i2c/nct7802y: configure local temp sensor [WIP] According to the documentation[1], the Mode Selection Register sets the operation mode of the local temperature sensors. The patch allows to do this from a tree of devices for a board that uses uses this HWM. [1] page 30, section 7.2.32, Nuvoton Hardware Monitoring IC NCT7802Y with PECI 3.0 interface, datasheet, revision 1.2, february 2012 Change-Id: I28cc4e5cae76cf0bcdad26a50ee6cd43a201d31e --- M src/drivers/i2c/nct7802y/chip.h M src/drivers/i2c/nct7802y/nct7802y.h M src/drivers/i2c/nct7802y/nct7802y_fan.c 3 files changed, 33 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/39766/1 diff --git a/src/drivers/i2c/nct7802y/chip.h b/src/drivers/i2c/nct7802y/chip.h index adff0f5..693cc41 100644 --- a/src/drivers/i2c/nct7802y/chip.h +++ b/src/drivers/i2c/nct7802y/chip.h @@ -19,6 +19,13 @@ #define NCT7802Y_PECI_CNT 2 #define NCT7802Y_FAN_CNT 3 +enum nct7802y_sensor_mode_type { + RTD_CLOSED = 0, + RTD_CURRENT_MODE, + RTD_THERMISTOR_MODE, + RTD_VOLTAGE_MODE, +}; + enum nct7802y_peci_mode { PECI_DISABLED = 0, PECI_DOMAIN_0, @@ -64,6 +71,14 @@ TEMP_SOURCE_PROGRAMMABLE_1, }; +/* Local temperature sensor configuration */ +struct nct7802y_sensor_mode_selection { + bool local_temp_sensor_enable; + enum nct7802y_sensor_mode_type rtd3_md; + enum nct7802y_sensor_mode_type rtd2_md; + enum nct7802y_sensor_mode_type rtd1_md; +}; + struct nct7802y_fan_smartconfig { enum nct7802y_fan_smartmode mode; enum nct7802y_fan_speed speed; @@ -85,6 +100,7 @@ /* Implements only those parts currently used by coreboot mainboards. */ struct drivers_i2c_nct7802y_config { + struct nct7802y_sensor_mode_selection sensor_mode; struct nct7802y_peci_config peci[NCT7802Y_PECI_CNT]; struct nct7802y_fan_config fan[NCT7802Y_FAN_CNT]; enum nct7802y_fan_pecierror on_pecierror; diff --git a/src/drivers/i2c/nct7802y/nct7802y.h b/src/drivers/i2c/nct7802y/nct7802y.h index 9f3aaef..a105fea 100644 --- a/src/drivers/i2c/nct7802y/nct7802y.h +++ b/src/drivers/i2c/nct7802y/nct7802y.h @@ -23,6 +23,15 @@ /* Bank 0 */ +#define MODE_SELECTION 0x22 +#define MODE_SELECTION_EN_LTD(x) (x << 6) +#define MODE_SELECTION_RTD3_MD(x) (x << 4) +#define MODE_SELECTION_RTD2_MD(x) (x << 2) +#define MODE_SELECTION_RTD1_MD(x) (x) + +#define PECI_ENABLE 0x23 +#define PECI_ENABLE_AGENTx(x) (1 << (x)) + #define PECI_ENABLE 0x23 #define PECI_ENABLE_AGENTx(x) (1 << (x)) diff --git a/src/drivers/i2c/nct7802y/nct7802y_fan.c b/src/drivers/i2c/nct7802y/nct7802y_fan.c index d7cfb90..1193bb9 100644 --- a/src/drivers/i2c/nct7802y/nct7802y_fan.c +++ b/src/drivers/i2c/nct7802y/nct7802y_fan.c @@ -89,6 +89,14 @@ init_fan(dev, &config->fan[i], i); } + if (config->sensor_mode.local_temp_sensor_enable) { + nct7802y_write(dev, MODE_SELECTION, + MODE_SELECTION_EN_LTD(config->sensor_mode.local_temp_sensor_enable) | + MODE_SELECTION_RTD3_MD(config->sensor_mode.rtd3_md) | + MODE_SELECTION_RTD2_MD(config->sensor_mode.rtd2_md) | + MODE_SELECTION_RTD1_MD(config->sensor_mode.rtd1_md)); + } + switch (config->on_pecierror) { case PECI_ERROR_KEEP: set = CLOSE_LOOP_FAN_PECI_ERR_CURR; -- To view, visit https://review.coreboot.org/c/coreboot/+/39766 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28cc4e5cae76cf0bcdad26a50ee6cd43a201d31e Gerrit-Change-Number: 39766 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

6 hours, 2 minutes

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Change in coreboot[master]: soc/intel/{apl,glk}: add options to configure GPU

by Maxim Polyakov (Code Review)

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39374 ) Change subject: soc/intel/{apl,glk}: add options to configure GPU ...................................................................... soc/intel/{apl,glk}: add options to configure GPU Adds options to select the primary GPU device and configure IGD, which allows to override the appropriate FSP options in the SoC code. These changes do not affect the configuration of the boards with the Apollo Lake and Gemini Lake processors, because if these parameters are not defined in the devicetree, they will be set to the default values. Change-Id: Idcd117217cf412ee0722aff52db4b3c8ec2a226c Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/soc/intel/apollolake/chip.h M src/soc/intel/apollolake/romstage.c 2 files changed, 64 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/39374/1 diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index 40cd39b..0375cec 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -44,6 +44,46 @@ /* Common structure containing soc config data required by common code*/ struct soc_intel_common_config common_soc_config; + /* Select DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size */ + enum { + DVMT_64MB = 2, /* Default */ + DVMT_96MB, + DVMT_128MB, + DVMT_160MB, + DVMT_192MB, + DVMT_224MB, + DVMT_256MB, + DVMT_288MB, + DVMT_320MB, + DVMT_352MB, + DVMT_384MB, + DVMT_416MB, + DVMT_448MB, + DVMT_480MB, + DVMT_512MB, + } igd_dvmt_50_pre_alloc_size; + + /* Select the Aperture Size for GPU device */ + enum { + APERTURE_128MB = 1, /* Default */ + APERTURE_256MB, + APERTURE_512MB, + } igd_aperture_size; + + /* Select the GTT Size for GPU device */ + enum { + GTT_2MB = 1, + GTT_4MB, + GTT_8MB, /* Default */ + } igd_gtt_size; + + /* Select primary GPU device */ + enum { + PRIMARY_AUTO = 0, /* Default */ + PRIMARY_IGD = 2, + PRIMARY_PCI = 3, + } primary_gpu; + /* * Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has * four CLKREQ inputs, but six root ports. Root ports without an diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 05cd0db..1576802 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -264,12 +264,34 @@ } } +static void soc_gpu_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + const struct soc_intel_apollolake_config *soc_cfg = config_of_soc(); + const struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD); + + m_cfg->PrimaryVideoAdaptor = soc_cfg->primary_gpu; + if (dev && dev->enabled && (soc_cfg->primary_gpu != PRIMARY_PCI)) { + /* + * Override FSP settings for IGD only if they are set in the devicetree. + * Otherwise, the default values from UPD will be used for them + */ + if (soc_cfg->igd_dvmt_50_pre_alloc_size) + m_cfg->IgdDvmt50PreAlloc = soc_cfg->igd_dvmt_50_pre_alloc_size; + + if (soc_cfg->igd_aperture_size) + m_cfg->IgdApertureSize = soc_cfg->igd_aperture_size; + + if (soc_cfg->igd_gtt_size) + m_cfg->GttSize = soc_cfg->igd_gtt_size; + } +} + static void soc_memory_init_params(FSPM_UPD *mupd) { #if CONFIG(SOC_INTEL_GLK) /* Only for GLK */ FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; - m_cfg->PrmrrSize = get_prmrr_size(); /* @@ -307,6 +329,7 @@ check_full_retrain(mupd); fill_console_params(mupd); + soc_gpu_init_params(mupd); if (CONFIG(SOC_INTEL_GLK)) soc_memory_init_params(mupd); -- To view, visit https://review.coreboot.org/c/coreboot/+/39374 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idcd117217cf412ee0722aff52db4b3c8ec2a226c Gerrit-Change-Number: 39374 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

12 hours, 36 minutes

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Change in coreboot[master]: soc/intel/xeon_sp: add ACPI to control GPIO [WIP]

by Maxim Polyakov (Code Review)

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39979 ) Change subject: soc/intel/xeon_sp: add ACPI to control GPIO [WIP] ...................................................................... soc/intel/xeon_sp: add ACPI to control GPIO [WIP] Change-Id: I07c882077eb3c035faae81641bc860e69db224b4 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- A src/soc/intel/xeon_sp/acpi/gpio.asl 1 file changed, 177 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/39979/1 diff --git a/src/soc/intel/xeon_sp/acpi/gpio.asl b/src/soc/intel/xeon_sp/acpi/gpio.asl new file mode 100644 index 0000000..4a981b7 --- /dev/null +++ b/src/soc/intel/xeon_sp/acpi/gpio.asl @@ -0,0 +1,177 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ +#include <soc/gpio.h> + +#define GPIOTXSTATE_MASK 0x1 +#define GPIORXSTATE_MASK 0x1 + +Device (GPIO) +{ + Name (_HID, "INT3536") + Name (_UID, 1) + Name (_DDN, "GPIO Controller") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0, COM0) + Memory32Fixed (ReadWrite, 0, 0, COM1) + Memory32Fixed (ReadWrite, 0, 0, COM3) + Memory32Fixed (ReadWrite, 0, 0, COM4) + Memory32Fixed (ReadWrite, 0, 0, COM5) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) + { 0 } + }) + + Method (_CRS, 0, NotSerialized) + { + /* GPIO Community 0 */ + CreateDWordField (^RBUF, ^COM0._BAS, BAS0) + CreateDWordField (^RBUF, ^COM0._LEN, LEN0) + Store (^^PCRB (PID_GPIOCOM0), BAS0) + Store (GPIO_BASE_SIZE, LEN0) + + /* GPIO Community 1 */ + CreateDWordField (^RBUF, ^COM1._BAS, BAS1) + CreateDWordField (^RBUF, ^COM1._LEN, LEN1) + Store (^^PCRB (PID_GPIOCOM1), BAS1) + Store (GPIO_BASE_SIZE, LEN1) + + /* GPIO Community 3 */ + CreateDWordField (^RBUF, ^COM3._BAS, BAS3) + CreateDWordField (^RBUF, ^COM3._LEN, LEN3) + Store (^^PCRB (PID_GPIOCOM3), BAS3) + Store (GPIO_BASE_SIZE, LEN3) + + /* GPIO Community 4 */ + CreateDWordField (^RBUF, ^COM4._BAS, BAS4) + CreateDWordField (^RBUF, ^COM4._LEN, LEN4) + Store (^^PCRB (PID_GPIOCOM4), BAS4) + Store (GPIO_BASE_SIZE, LEN4) + + /* GPIO Community 5 */ + CreateDWordField (^RBUF, ^COM5._BAS, BAS5) + CreateDWordField (^RBUF, ^COM5._LEN, LEN5) + Store (^^PCRB (PID_GPIOCOM5), BAS5) + Store (GPIO_BASE_SIZE, LEN5) + + CreateDWordField (^RBUF, ^GIRQ._INT, IRQN) + And (^^PCRR (PID_GPIOCOM0, GPIO_MISCCFG), + GPIO_DRIVER_IRQ_ROUTE_MASK, Local0) + + /* TODO: Check this! + If (LEqual (Local0, GPIO_DRIVER_IRQ_ROUTE_IRQ14)) { + Store (GPIO_IRQ14, IRQN) + } Else { + Store (GPIO_IRQ15, IRQN) + } + */ + + Return (RBUF) + } + + Method (_STA, 0, NotSerialized) + { + Return (0xF) + } +} + +/* + * Get GPIO DW0 Address + * Arg0 - GPIO Number + */ +Method (GADD, 1, NotSerialized) +{ + /* GPIO Community 0 */ + If (LAnd (LGreaterEqual (Arg0, GPP_A0), LLessEqual (Arg0, GPP_F23))) + { + Store (PID_GPIOCOM0, Local0) + Subtract (Arg0, GPP_A0, Local1) + } + /* GPIO Community 1 */ + If (LAnd (LGreaterEqual (Arg0, GPP_C0), LLessEqual (Arg0, GPP_H23))) + { + Store (PID_GPIOCOM1, Local0) + Subtract (Arg0, GPP_C0, Local1) + } + /* GPIO Community 3 */ + If (LAnd (LGreaterEqual (Arg0, GPP_I0), LLessEqual (Arg0, GPP_I10))) + { + Store (PID_GPIOCOM3, Local0) + Subtract (Arg0, GPP_I0, Local1) + } + /* GPIO Community 4 */ + If (LAnd (LGreaterEqual (Arg0, GPP_J0), LLessEqual (Arg0, GPP_K10))) + { + Store (PID_GPIOCOM4, Local0) + Subtract (Arg0, GPP_J0, Local1) + } + /* GPIO Community 5 */ + If (LAnd (LGreaterEqual (Arg0, GPP_G0), LLessEqual (Arg0, GPP_L19))) + { + Store (PID_GPIOCOM5, Local0) + Subtract (Arg0, GPP_G0, Local1) + } + Store (PCRB (Local0), Local2) + Add (Local2, PAD_CFG_BASE, Local2) + Return (Add (Local2, Multiply (Local1, 8))) +} + +/* + * Get GPIO Rx Value + * Arg0 - GPIO Number + */ +Method (GRXS, 1, Serialized) +{ + OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) + Field (PREG, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + And (GPIORXSTATE_MASK, ShiftRight (VAL0, PAD_CFG0_RX_STATE_BIT), Local0) + + Return (Local0) +} + +/* + * Get GPIO Tx Value + * Arg0 - GPIO Number + */ +Method (GTXS, 1, Serialized) +{ + OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) + Field (PREG, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + And (GPIOTXSTATE_MASK, ShiftRight (VAL0, PAD_CFG0_TX_STATE_BIT), Local0) + + Return (Local0) +} + +/* + * Set GPIO Tx Value + * Arg0 - GPIO Number + */ +Method (STXS, 1, Serialized) +{ + OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) + Field (PREG, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + Or (GPIOTXSTATE_MASK, VAL0, VAL0) +} + +/* + * Clear GPIO Tx Value + * Arg0 - GPIO Number + */ +Method (CTXS, 1, Serialized) +{ + OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) + Field (PREG, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + And (Not (GPIOTXSTATE_MASK), VAL0, VAL0) +} -- To view, visit https://review.coreboot.org/c/coreboot/+/39979 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I07c882077eb3c035faae81641bc860e69db224b4 Gerrit-Change-Number: 39979 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

13 hours, 53 minutes

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Change in coreboot[master]: mb/ocp/tiogapass: use ACPI to control GPIO [WIP]

by Maxim Polyakov (Code Review)

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39987 ) Change subject: mb/ocp/tiogapass: use ACPI to control GPIO [WIP] ...................................................................... mb/ocp/tiogapass: use ACPI to control GPIO [WIP] Change-Id: I0d4526c423b2192f51e515d993a05c03a3eaf58b Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/ocp/tiogapass/dsdt.asl 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/39987/1 diff --git a/src/mainboard/ocp/tiogapass/dsdt.asl b/src/mainboard/ocp/tiogapass/dsdt.asl index 9d33865..59ee7f8 100644 --- a/src/mainboard/ocp/tiogapass/dsdt.asl +++ b/src/mainboard/ocp/tiogapass/dsdt.asl @@ -35,5 +35,7 @@ // Xeon-SP ACPI tables Scope (\_SB) { #include <soc/intel/xeon_sp/skx/acpi/uncore.asl> + #include <soc/intel/common/acpi/pcr.asl> + #include <soc/intel/xeon_sp/acpi/gpio.asl> } } -- To view, visit https://review.coreboot.org/c/coreboot/+/39987 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d4526c423b2192f51e515d993a05c03a3eaf58b Gerrit-Change-Number: 39987 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

13 hours, 53 minutes

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Change in coreboot[master]: [WIP]nehalem: Add x86_64 support

by Patrick Rudolph (Code Review)

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37371 ) Change subject: [WIP]nehalem: Add x86_64 support ...................................................................... [WIP]nehalem: Add x86_64 support Use correct datasize to compile on x86_64. Change-Id: I213b2b1c5de174b5c14b67d1b437d19c656d13fd Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/arch/x86/Makefile.inc M src/arch/x86/include/arch/cbfs.h M src/cpu/intel/car/non-evict/cache_as_ram.S M src/cpu/intel/microcode/microcode_asm.S M src/cpu/intel/model_2065x/Kconfig M src/cpu/x86/early_reset.S M src/drivers/pc80/tpm/tis.c M src/northbridge/intel/nehalem/raminit.c M src/southbridge/intel/bd82x6x/me_8.x.c M src/southbridge/intel/ibexpeak/azalia.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/ibexpeak/me.c M src/southbridge/intel/ibexpeak/sata.c M src/southbridge/intel/ibexpeak/smihandler.c 14 files changed, 39 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/37371/1 diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 45db303..a25d91a 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -126,7 +126,7 @@ $(eval $(call early_x86_stage,bootblock,elf64-x86-64)) endif -bootblock-$(CONFIG_ARCH_BOOTBLOCK_X86_32) += walkcbfs.S +bootblock-y += walkcbfs.S else # ROMCC_BOOTBLOCK diff --git a/src/arch/x86/include/arch/cbfs.h b/src/arch/x86/include/arch/cbfs.h index ec367ed..78bf2ed 100644 --- a/src/arch/x86/include/arch/cbfs.h +++ b/src/arch/x86/include/arch/cbfs.h @@ -33,7 +33,7 @@ static void *walkcbfs(char *target) { struct cbfs_file *head = walkcbfs_head(target); - if ((u32)head != 0) + if ((uintptr_t)head != 0) return CBFS_SUBHEADER(head); /* We should never reach this if 'target' exists */ @@ -51,7 +51,7 @@ static inline unsigned long findstage(char *target) { struct cbfs_stage_restricted *stage = walkcbfs(target); - if ((u32)stage != 0) + if ((uintptr_t)stage != 0) return stage->entry; /* We should never reach this if 'target' exists */ diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index 5a668c4..e458302 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -220,8 +220,20 @@ /* Need to align stack to 16 bytes at call instruction. Account for the pushes below. */ andl $0xfffffff0, %esp - subl $4, %esp + /* entry64.inc preserves ebx. */ +#include <cpu/x86/64bit/entry64.inc> + +#ifdef __x86_64__ + + movd %mm2, %rdi + shld %rdi, 32 + movd %mm1, %rsi + or %rsi, %rdi /* tsc */ + + movd %mm0, %rsi /* BIST */ +#else + subl $4, %esp /* push TSC and BIST to stack */ movd %mm0, %eax pushl %eax /* BIST */ @@ -229,6 +241,7 @@ pushl %eax /* tsc[63:32] */ movd %mm1, %eax pushl %eax /* tsc[31:0] */ +#endif before_c_entry: post_code(0x29) diff --git a/src/cpu/intel/microcode/microcode_asm.S b/src/cpu/intel/microcode/microcode_asm.S index 647f67c..b9c43cc 100644 --- a/src/cpu/intel/microcode/microcode_asm.S +++ b/src/cpu/intel/microcode/microcode_asm.S @@ -56,6 +56,7 @@ .section .text .global update_bsp_microcode +.code32 update_bsp_microcode: /* Keep return address */ diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index a76a95d..d816b4e 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -3,12 +3,20 @@ if CPU_INTEL_MODEL_2065X +config ARCH_EXP_X86_64 + bool "Experimental 64bit support" + default n + config CPU_SPECIFIC_OPTIONS def_bool y - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 + select ARCH_BOOTBLOCK_X86_32 if !ARCH_EXP_X86_64 + select ARCH_VERSTAGE_X86_32 if !ARCH_EXP_X86_64 + select ARCH_ROMSTAGE_X86_32 if !ARCH_EXP_X86_64 + select ARCH_RAMSTAGE_X86_32 if !ARCH_EXP_X86_64 + select ARCH_BOOTBLOCK_X86_64 if ARCH_EXP_X86_64 + select ARCH_VERSTAGE_X86_64 if ARCH_EXP_X86_64 + select ARCH_ROMSTAGE_X86_64 if ARCH_EXP_X86_64 + select ARCH_RAMSTAGE_X86_64 if ARCH_EXP_X86_64 select SMP select SSE2 select UDELAY_TSC diff --git a/src/cpu/x86/early_reset.S b/src/cpu/x86/early_reset.S index ec015abe..998ebda 100644 --- a/src/cpu/x86/early_reset.S +++ b/src/cpu/x86/early_reset.S @@ -21,6 +21,7 @@ .section .text .global check_mtrr +.code32 check_mtrr: /* Use the MTRR default type MSR as a proxy for detecting INIT#. diff --git a/src/drivers/pc80/tpm/tis.c b/src/drivers/pc80/tpm/tis.c index 39fa70d..27e11bd 100644 --- a/src/drivers/pc80/tpm/tis.c +++ b/src/drivers/pc80/tpm/tis.c @@ -55,7 +55,7 @@ /* the macro accepts the locality value, but only locality 0 is operational */ #define TIS_REG(LOCALITY, REG) \ - (void *)(CONFIG_TPM_TIS_BASE_ADDRESS + (LOCALITY << 12) + REG) + (void *)((uintptr_t)CONFIG_TPM_TIS_BASE_ADDRESS + (LOCALITY << 12) + REG) /* hardware registers' offsets */ #define TIS_REG_ACCESS 0x0 diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index a393cb7..673cb5a 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -1999,7 +1999,7 @@ u32 offset; u8 *base; - base = (u8 *)(totalrank << 28); + base = (u8 *)(uintptr_t)(totalrank << 28); for (offset = 0; offset < 9 * 480; offset += 2) { write32(base + offset * 8, get_etalon2(flip, offset)); write32(base + offset * 8 + 4, get_etalon2(flip, offset)); diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index f13ced9..84960ea 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -482,7 +482,7 @@ struct me_hfs hfs; u32 reg32; - mei_base_address = (void *) + mei_base_address = (void *)(uintptr_t) (pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf); /* S3 path will have hidden this device already */ diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c index 5b38ea7..c0d2494 100644 --- a/src/southbridge/intel/ibexpeak/azalia.c +++ b/src/southbridge/intel/ibexpeak/azalia.c @@ -238,7 +238,7 @@ // NOTE this will break as soon as the Azalia get's a bar above // 4G. Is there anything we can do about it? base = res2mmio(res, 0, 0); - printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base); + printk(BIOS_DEBUG, "Azalia: base = %p\n", base); if (RCBA32(0x2030) & (1 << 31)) { reg32 = pci_read_config32(dev, 0x120); diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 2b48eab..6771a7a 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -598,7 +598,7 @@ /* Add it to SSDT. */ acpigen_write_scope("\\"); - acpigen_write_name_dword("NVSA", (u32) gnvs); + acpigen_write_name_dword("NVSA", (uintptr_t) gnvs); acpigen_pop_len(); } } diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c index 63dff6a..62fd08a 100644 --- a/src/southbridge/intel/ibexpeak/me.c +++ b/src/southbridge/intel/ibexpeak/me.c @@ -372,7 +372,7 @@ struct me_hfs hfs; u32 reg32; - mei_base_address = (u32 *) + mei_base_address = (u32 *)(uintptr_t) (pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf); /* S3 path will have hidden this device already */ diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c index 2d9412a..33e717a 100644 --- a/src/southbridge/intel/ibexpeak/sata.c +++ b/src/southbridge/intel/ibexpeak/sata.c @@ -104,7 +104,7 @@ pci_write_config32(dev, 0x98, 0x00590200); /* Initialize AHCI memory-mapped space */ - abar = (u32 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); + abar = (u32 *)(uintptr_t)pci_read_config32(dev, PCI_BASE_ADDRESS_5); printk(BIOS_DEBUG, "ABAR: %p\n", abar); /* CAP (HBA Capabilities) : enable power management */ reg32 = read32(abar + 0x00); diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index 3668842..a68c89a 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -177,7 +177,7 @@ smi_apmc_find_state_save(apm_cnt); if (state) { /* EBX in the state save contains the GNVS pointer */ - gnvs = (global_nvs_t *)((u32)state->rbx); + gnvs = (global_nvs_t *)(uintptr_t)((u32)state->rbx); *smm_done = 1; printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } -- To view, visit https://review.coreboot.org/c/coreboot/+/37371 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I213b2b1c5de174b5c14b67d1b437d19c656d13fd Gerrit-Change-Number: 37371 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 day, 9 hours

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Change in coreboot[master]: [Hack] [TEST] Very Crude way of enabling IMGCLKOUT1

by Varshit B Pandya (Code Review)

Varshit B Pandya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39473 ) Change subject: [Hack] [TEST] Very Crude way of enabling IMGCLKOUT1 ...................................................................... [Hack] [TEST] Very Crude way of enabling IMGCLKOUT1 Signed-off-by: Pandya, Varshit B <varshit.b.pandya(a)intel.com> Change-Id: I5d0c99211b6ba43a1032322214058db688337b67 --- M src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/cam1.asl M src/soc/intel/tigerlake/finalize.c 2 files changed, 8 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/39473/1 diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/cam1.asl b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/cam1.asl index 8df60a8..f8c6ae0 100644 --- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/cam1.asl +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/acpi/cam1.asl @@ -20,7 +20,7 @@ { Method (_ON, 0, Serialized) // _ON_: Power On { - MCCT(1,1,1) // Clock 0, enable, 19.2MHz + //MCCT(1,1,1) // Clock 0, enable, 19.2MHz //Check if another sensor is ON IF(STA0) { @@ -55,7 +55,7 @@ IF(STA0) { //Do nothing since the other sensor is ON - MCCT(1,0,1) // Clock 0, disable, 19.2MHz + //MCCT(1,0,1) // Clock 0, disable, 19.2MHz } ELSE { @@ -63,7 +63,7 @@ CTXS(GPP_D13) //Disable PP2800 lane CTXS(GPP_D14) - MCCT(1,0,1) // Clock 0, disable, 19.2MHz + //MCCT(1,0,1) // Clock 0, disable, 19.2MHz } Store(0,STA1) } diff --git a/src/soc/intel/tigerlake/finalize.c b/src/soc/intel/tigerlake/finalize.c index aed5cc0..fd5655d 100644 --- a/src/soc/intel/tigerlake/finalize.c +++ b/src/soc/intel/tigerlake/finalize.c @@ -108,6 +108,11 @@ pch_finalize(); printk(BIOS_DEBUG, "Finalizing SMM.\n"); + //Hack for enabling CLK + uint32_t test; + write32((void *)0xfdad800c, 0x2); + write32((void *)0xfdad800c, 0x3); + outb(APM_CNT_FINALIZE, APM_CNT); /* Indicate finalize step with post code */ -- To view, visit https://review.coreboot.org/c/coreboot/+/39473 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d0c99211b6ba43a1032322214058db688337b67 Gerrit-Change-Number: 39473 Gerrit-PatchSet: 1 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-MessageType: newchange

2 days, 14 hours

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Change in coreboot[master]: cpu/qemu-x86/car: Move long mode entry right before c entry

by Patrick Rudolph (Code Review)

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37370 ) Change subject: cpu/qemu-x86/car: Move long mode entry right before c entry ...................................................................... cpu/qemu-x86/car: Move long mode entry right before c entry Change-Id: I45e56ed8db9a44c00cd61e962bb82f27926eb23f Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/arch/x86/bootblock_crt0.S M src/cpu/qemu-x86/cache_as_ram_bootblock.S 2 files changed, 3 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/37370/1 diff --git a/src/arch/x86/bootblock_crt0.S b/src/arch/x86/bootblock_crt0.S index 3256731..e167a12 100644 --- a/src/arch/x86/bootblock_crt0.S +++ b/src/arch/x86/bootblock_crt0.S @@ -30,12 +30,6 @@ #include <cpu/x86/16bit/reset16.inc> #include <cpu/x86/32bit/entry32.inc> - /* BIST result in eax */ - mov %eax, %ebx - /* entry64.inc preserves ebx. */ -#include <cpu/x86/64bit/entry64.inc> - mov %ebx, %eax - #if CONFIG(BOOTBLOCK_DEBUG_SPINLOOP) /* Wait for a JTAG debugger to break in and set EBX non-zero */ diff --git a/src/cpu/qemu-x86/cache_as_ram_bootblock.S b/src/cpu/qemu-x86/cache_as_ram_bootblock.S index 1fa0018..f7280bf 100644 --- a/src/cpu/qemu-x86/cache_as_ram_bootblock.S +++ b/src/cpu/qemu-x86/cache_as_ram_bootblock.S @@ -39,6 +39,9 @@ /* Align the stack and keep aligned for call to bootblock_c_entry() */ and $0xfffffff0, %esp + /* entry64.inc preserves ebx. */ +#include <cpu/x86/64bit/entry64.inc> + /* Restore the BIST result and timestamps. */ #if defined(__x86_64__) movd %mm1, %rdi -- To view, visit https://review.coreboot.org/c/coreboot/+/37370 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45e56ed8db9a44c00cd61e962bb82f27926eb23f Gerrit-Change-Number: 37370 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 days, 9 hours

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Change in coreboot[master]: arch/x86/Kconfig: Move pagetables down by 4K

by Patrick Rudolph (Code Review)

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37394 ) Change subject: arch/x86/Kconfig: Move pagetables down by 4K ...................................................................... arch/x86/Kconfig: Move pagetables down by 4K In case of 64K bootblock the pagetables doesn't fit, as the CBFS header also needs a few bytes. Fixes build error on platforms that use 64KiB bootblock. Tested on Lenovo T410 with additional x86_64 patches. Change-Id: I854c5f575e2376827a366cca8d25682c4d90bc8f Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/arch/x86/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/37394/1 diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 0e6f486..1e27970 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -68,7 +68,7 @@ config ARCH_X86_64_PGTBL_LOC hex "x86_64 page table location in CBFS" depends on ARCH_BOOTBLOCK_X86_64 - default 0xfffea000 + default 0xfffe9000 help The position where to place pagetables. Needs to be known at compile time. Must not overlap other files in CBFS. -- To view, visit https://review.coreboot.org/c/coreboot/+/37394 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I854c5f575e2376827a366cca8d25682c4d90bc8f Gerrit-Change-Number: 37394 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

3 days, 10 hours

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Change in coreboot[master]: cbfs: Introduce cbfs_ro_map() and cbfs_ro_load()

by Julius Werner (Code Review)

Hello Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/39306 to review the following change. Change subject: cbfs: Introduce cbfs_ro_map() and cbfs_ro_load() ...................................................................... cbfs: Introduce cbfs_ro_map() and cbfs_ro_load() This patch introduces two new CBFS API functions which are equivalent to cbfs_map() and cbfs_load(), respectively, with the difference that they always operate on the read-only CBFS region ("COREBOOT" FMAP section). Use it to replace some of the simple cases that needed to use cbfs_locate_file_in_region(). Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I9c55b022b6502a333a9805ab0e4891dd7b97ef7f --- M src/drivers/pc80/rtc/option.c M src/include/cbfs.h M src/lib/cbfs.c M src/northbridge/intel/haswell/raminit.c M src/soc/intel/broadwell/romstage/raminit.c M src/soc/intel/quark/romstage/romstage.c 6 files changed, 60 insertions(+), 89 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/39306/1 diff --git a/src/drivers/pc80/rtc/option.c b/src/drivers/pc80/rtc/option.c index 4789b15..1f9abb5 100644 --- a/src/drivers/pc80/rtc/option.c +++ b/src/drivers/pc80/rtc/option.c @@ -60,36 +60,28 @@ return CB_SUCCESS; } -static enum cb_err locate_cmos_layout(struct region_device *rdev) +static struct cmos_option_table *get_cmos_layout(struct region_device *rdev) { - uint32_t cbfs_type = CBFS_COMPONENT_CMOS_LAYOUT; - MAYBE_STATIC_BSS struct cbfsf fh = {}; + MAYBE_STATIC_BSS struct cmos_option_table ct = NULL; /* * In case VBOOT is enabled and this function is called from SMM, * we have multiple CMOS layout files and to locate them we'd need to * include VBOOT into SMM... * - * Support only one CMOS layout in the 'COREBOOT' region for now. + * Support only one CMOS layout in the RO CBFS for now. */ - if (!region_device_sz(&(fh.data))) { - if (cbfs_locate_file_in_region(&fh, "COREBOOT", "cmos_layout.bin", - &cbfs_type)) { - printk(BIOS_ERR, "RTC: cmos_layout.bin could not be found. " - "Options are disabled\n"); - return CB_CMOS_LAYOUT_NOT_FOUND; - } - } - - cbfs_file_data(rdev, &fh); - - return CB_SUCCESS; + if (!ct) + ct = cbfs_ro_map("cmos_layout.bin", NULL); + if (!ct) + printk(BIOS_ERR, "RTC: cmos_layout.bin could not be found. " + "Options are disabled\n"); + return ct; } enum cb_err cmos_get_option(void *dest, const char *name) { struct cmos_option_table *ct; - struct region_device rdev; struct cmos_entries *ce; size_t namelen; int found = 0; @@ -97,16 +89,9 @@ /* Figure out how long name is */ namelen = strnlen(name, CMOS_MAX_NAME_LENGTH); - if (locate_cmos_layout(&rdev) != CB_SUCCESS) { + ct = get_cmos_layout(); + if (!ct) return CB_CMOS_LAYOUT_NOT_FOUND; - } - ct = rdev_mmap_full(&rdev); - if (!ct) { - printk(BIOS_ERR, "RTC: cmos_layout.bin could not be mapped. " - "Options are disabled\n"); - - return CB_CMOS_LAYOUT_NOT_FOUND; - } /* find the requested entry record */ ce = (struct cmos_entries *)((unsigned char *)ct + ct->header_length); @@ -119,19 +104,15 @@ } if (!found) { printk(BIOS_DEBUG, "No CMOS option '%s'.\n", name); - rdev_munmap(&rdev, ct); return CB_CMOS_OPTION_NOT_FOUND; } - if (!cmos_checksum_valid(LB_CKS_RANGE_START, LB_CKS_RANGE_END, LB_CKS_LOC)) { - rdev_munmap(&rdev, ct); + if (!cmos_checksum_valid(LB_CKS_RANGE_START, LB_CKS_RANGE_END, LB_CKS_LOC)) return CB_CMOS_CHECKSUM_INVALID; - } - if (get_cmos_value(ce->bit, ce->length, dest) != CB_SUCCESS) { - rdev_munmap(&rdev, ct); +} + if (get_cmos_value(ce->bit, ce->length, dest) != CB_SUCCESS) return CB_CMOS_ACCESS_ERROR; - } - rdev_munmap(&rdev, ct); +} return CB_SUCCESS; } @@ -179,7 +160,6 @@ enum cb_err cmos_set_option(const char *name, void *value) { struct cmos_option_table *ct; - struct region_device rdev; struct cmos_entries *ce; unsigned long length; size_t namelen; @@ -188,16 +168,9 @@ /* Figure out how long name is */ namelen = strnlen(name, CMOS_MAX_NAME_LENGTH); - if (locate_cmos_layout(&rdev) != CB_SUCCESS) { + ct = get_cmos_layout(); + if (!ct) return CB_CMOS_LAYOUT_NOT_FOUND; - } - ct = rdev_mmap_full(&rdev); - if (!ct) { - printk(BIOS_ERR, "RTC: cmos_layout.bin could not be mapped. " - "Options are disabled\n"); - - return CB_CMOS_LAYOUT_NOT_FOUND; - } /* find the requested entry record */ ce = (struct cmos_entries *)((unsigned char *)ct + ct->header_length); @@ -210,7 +183,6 @@ } if (!found) { printk(BIOS_DEBUG, "WARNING: No CMOS option '%s'.\n", name); - rdev_munmap(&rdev, ct); return CB_CMOS_OPTION_NOT_FOUND; } @@ -219,18 +191,13 @@ length = MAX(strlen((const char *)value) * 8, ce->length - 8); /* make sure the string is null terminated */ if (set_cmos_value(ce->bit + ce->length - 8, 8, &(u8[]){0}) - != CB_SUCCESS) { - rdev_munmap(&rdev, ct); + != CB_SUCCESS) return CB_CMOS_ACCESS_ERROR; - } } - if (set_cmos_value(ce->bit, length, value) != CB_SUCCESS) { - rdev_munmap(&rdev, ct); + if (set_cmos_value(ce->bit, length, value) != CB_SUCCESS) return CB_CMOS_ACCESS_ERROR; - } - rdev_munmap(&rdev, ct); return CB_SUCCESS; } diff --git a/src/include/cbfs.h b/src/include/cbfs.h index cc61b16..8cd5713 100644 --- a/src/include/cbfs.h +++ b/src/include/cbfs.h @@ -36,9 +36,12 @@ NOTE: Since this may return a direct pointer to memory-mapped hardware, compressed files are NOT transparently decompressed (unlike cbfs_load()). */ void *cbfs_map(const char *name, size_t *size); -/* Removes a mapping previously allocated with cbfs_map(). Should try to unmap - mappings in strict LIFO order where possible, since mapping backends often - don't support more complicated cases. */ +/* Like cbfs_map(), except that it will always read from the read-only CBFS + ("COREBOOT" FMAP region), even when CONFIG_VBOOT is enabled. */ +void *cbfs_ro_map(const char *name, size_t *size); +/* Removes a previously allocated CBFS mapping. Should try to unmap mappings in + strict LIFO order where possible, since mapping backends often don't support + more complicated cases. */ int cbfs_unmap(void *mapping); /* Locate file in a specific region of fmap. Return 0 on success. < 0 on error*/ int cbfs_locate_file_in_region(struct cbfsf *fh, const char *region_name, @@ -47,6 +50,9 @@ success or 0 on error. File will get decompressed as necessary. Same decompression requirements as cbfs_load_and_decompress(). */ size_t cbfs_load(const char *name, void *buf, size_t buf_size); +/* Like cbfs_load(), except that it will always read from the read-only CBFS + ("COREBOOT" FMAP region), even when CONFIG_VBOOT is enabled. */ +size_t cbfs_ro_load(const char *name, void *buf, size_t buf_size); /* Load |in_size| bytes from |rdev| at |offset| to the |buffer_size| bytes * large |buffer|, decompressing it according to |compression| in the process. * Returns the decompressed file size, or 0 on error. diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index c3660aa..ba50c34 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -79,9 +79,9 @@ return 0; } -void *cbfs_map(const char *name, size_t *size) +static void *_cbfs_map(const char *name, size_t *size, bool force_ro) { - const struct cbfs_boot_device *cbd = cbfs_get_boot_device(false); + const struct cbfs_boot_device *cbd = cbfs_get_boot_device(force_ro); union cbfs_mdata mdata; size_t data_offset; @@ -96,6 +96,16 @@ return rdev_mmap(&cbd->rdev, data_offset, data_size); } +void *cbfs_map(const char *name, size_t *size) +{ + return _cbfs_map(name, size, false); +} + +void *cbfs_ro_map(const char *name, size_t *size) +{ + return _cbfs_map(name, size, true); +} + int cbfs_unmap(void *mapping) { /* This works because munmap() only works on the root rdev and never @@ -215,7 +225,8 @@ return prog_entry(&stage); } -size_t cbfs_load(const char *name, void *buf, size_t buf_size) +static size_t _cbfs_load(const char *name, void *buf, size_t buf_size, + bool force_ro) { const struct cbfs_boot_device *cbd = cbfs_get_boot_device(false); union cbfs_mdata mdata; @@ -238,6 +249,16 @@ compression); } +size_t cbfs_load(const char *name, void *buf, size_t buf_size) +{ + return _cbfs_load(name, buf, buf_size, false); +} + +size_t cbfs_ro_load(const char *name, void *buf, size_t buf_size) +{ + return _cbfs_load(name, buf, buf_size, true); +} + size_t cbfs_prog_stage_section(struct prog *pstage, uintptr_t *base) { struct cbfs_stage stage; diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 8267833..00211bd 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -118,8 +118,6 @@ void sdram_initialize(struct pei_data *pei_data) { unsigned long entry; - uint32_t type = CBFS_TYPE_MRC; - struct cbfsf f; printk(BIOS_DEBUG, "Starting UEFI PEI System Agent\n"); @@ -144,12 +142,11 @@ /* * Locate and call UEFI System Agent binary. The binary needs to be at * a fixed offset in the flash and can therefore only reside in the - * COREBOOT fmap region + * COREBOOT fmap region. We don't care about leaking the mapping. */ - if (cbfs_locate_file_in_region(&f, "COREBOOT", "mrc.bin", &type) < 0) + entry = (unsigned long)cbfs_ro_map("mrc.bin", NULL); + if (!entry) die("mrc.bin not found!"); - /* We don't care about leaking the mapping */ - entry = (unsigned long)rdev_mmap_full(&f.data); if (entry) { int rv; asm volatile ( diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c index 3759c1f..bcf7148 100644 --- a/src/soc/intel/broadwell/romstage/raminit.c +++ b/src/soc/intel/broadwell/romstage/raminit.c @@ -43,8 +43,6 @@ struct memory_info *mem_info; pei_wrapper_entry_t entry; int ret; - struct cbfsf f; - uint32_t type = CBFS_TYPE_MRC; broadwell_fill_pei_data(pei_data); @@ -76,15 +74,10 @@ pei_data->saved_data_size = 0; } - /* Determine if mrc.bin is in the cbfs. */ - if (cbfs_locate_file_in_region(&f, "COREBOOT", "mrc.bin", &type) < 0) - die("mrc.bin not found!"); /* We don't care about leaking the mapping */ - entry = (pei_wrapper_entry_t)rdev_mmap_full(&f.data); - if (entry == NULL) { - printk(BIOS_DEBUG, "Couldn't find mrc.bin\n"); - return; - } + entry = cbfs_ro_map("mrc.bin", NULL); + if (entry == NULL) + die("mrc.bin not found!"); printk(BIOS_DEBUG, "Starting Memory Reference Code\n"); diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c index 4ac580e..3e08663 100644 --- a/src/soc/intel/quark/romstage/romstage.c +++ b/src/soc/intel/quark/romstage/romstage.c @@ -63,29 +63,16 @@ void *locate_rmu_file(size_t *rmu_file_len) { - struct cbfsf fh; size_t fsize; void *rmu_data; - uint32_t type; /* Locate the rmu.bin file in the read-only region of the flash */ - type = CBFS_TYPE_RAW; - if (cbfs_locate_file_in_region(&fh, "COREBOOT", "rmu.bin", &type)) + rmu_data = cbfs_ro_map("rmu.bin", &fsize); + if (!rmu_data) return NULL; - /* Get the file size */ - fsize = region_device_sz(&fh.data); if (rmu_file_len != NULL) *rmu_file_len = fsize; - /* Get the data address */ - rmu_data = rdev_mmap(&fh.data, 0, fsize); - - /* Since the SPI flash is directly mapped into memory, we do not need - * the mapping provided by the rdev service. Unmap the file to prevent - * a memory leak. Return/leak the SPI flash address for the rmu.bin - * file data which will be directly accessed by FSP MemoryInit. - */ - rdev_munmap(&fh.data, rmu_data); return rmu_data; } -- To view, visit https://review.coreboot.org/c/coreboot/+/39306 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c55b022b6502a333a9805ab0e4891dd7b97ef7f Gerrit-Change-Number: 39306 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: cbfs: Port cbfs_load() and cbfs_map() to new API

by Julius Werner (Code Review)

Hello Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/39305 to review the following change. Change subject: cbfs: Port cbfs_load() and cbfs_map() to new API ...................................................................... cbfs: Port cbfs_load() and cbfs_map() to new API This patch adapts cbfs_load() and cbfs_map() to use the new CBFS API directly, rather than through cbfs_boot_locate(). For cbfs_load() this means that attribute metadata does not need to be read twice. Change-Id: I754cc34b1c1471129e15475aa0f1891e02439a02 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M src/commonlib/bsd/cbfs_private.c M src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h M src/lib/cbfs.c 3 files changed, 43 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/39305/1 diff --git a/src/commonlib/bsd/cbfs_private.c b/src/commonlib/bsd/cbfs_private.c index 85a75ab..7e309ec 100644 --- a/src/commonlib/bsd/cbfs_private.c +++ b/src/commonlib/bsd/cbfs_private.c @@ -155,3 +155,21 @@ }; return cbfs_walk(dev, lookup_walker, &args, master_hash, 0); } + +void *cbfs_find_attr(union cbfs_mdata *mdata, uint32_t attr_tag) +{ + uint32_t offset = be32toh(mdata->h.attributes_offset); + uint32_t end = be32toh(mdata->h.offset); + + if (!offset) + return NULL; + + while (offset < end) { + struct cbfs_file_attribute *attr = (void *)mdata + offset; + if (be32toh(attr->tag) == attr_tag) + return attr; + offset += be32toh(attr->len); + } + + return NULL; +} diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h b/src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h index df97009..4962cef 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h +++ b/src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h @@ -112,4 +112,7 @@ /* Returns the amount of bytes actually used by the CBFS metadata cache in |mcache|. */ size_t cbfs_mcache_real_size(const void *mcache, size_t mcache_size); +/* Finds a CBFS attribute in a metadata block. Attribute returned as-is (still big-endian). */ +void *cbfs_find_attr(union cbfs_mdata *mdata, uint32_t attr_tag); + #endif /* _COMMONLIB_BSD_CBFS_PRIVATE_H_ */ diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index bece4d0..c3660aa 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -81,18 +81,19 @@ void *cbfs_map(const char *name, size_t *size) { - struct cbfsf fh; - size_t fsize; + const struct cbfs_boot_device *cbd = cbfs_get_boot_device(false); + union cbfs_mdata mdata; + size_t data_offset; - if (cbfs_boot_locate(&fh, name, NULL)) + if (cbfs_boot_lookup(cbd, name, &mdata, &data_offset)) return NULL; - fsize = region_device_sz(&fh.data); + size_t data_size = be32toh(mdata.h.len); if (size != NULL) - *size = fsize; + *size = data_size; - return rdev_mmap(&fh.data, 0, fsize); + return rdev_mmap(&cbd->rdev, data_offset, data_size); } int cbfs_unmap(void *mapping) @@ -216,21 +217,25 @@ size_t cbfs_load(const char *name, void *buf, size_t buf_size) { - struct cbfsf fh; - uint32_t compression_algo; - size_t decompressed_size; + const struct cbfs_boot_device *cbd = cbfs_get_boot_device(false); + union cbfs_mdata mdata; + size_t data_offset; - if (cbfs_boot_locate(&fh, name, NULL) < 0) + if (cbfs_boot_lookup(cbd, name, &mdata, &data_offset)) return 0; - if (cbfsf_decompression_info(&fh, &compression_algo, - &decompressed_size) - < 0 - || decompressed_size > buf_size) - return 0; + uint32_t compression = CBFS_COMPRESS_NONE; + struct cbfs_file_attr_compression *attr = + cbfs_find_attr(&mdata, CBFS_FILE_ATTR_TAG_COMPRESSION); + if (attr) { + compression = be32toh(attr->compression); + if (buf_size < be32toh(attr->decompressed_size)) + return 0; + } - return cbfs_load_and_decompress(&fh.data, 0, region_device_sz(&fh.data), - buf, buf_size, compression_algo); + return cbfs_load_and_decompress(&cbd->rdev, data_offset, + be32toh(mdata.h.len), buf, buf_size, + compression); } size_t cbfs_prog_stage_section(struct prog *pstage, uintptr_t *base) -- To view, visit https://review.coreboot.org/c/coreboot/+/39305 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I754cc34b1c1471129e15475aa0f1891e02439a02 Gerrit-Change-Number: 39305 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

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coreboot-gerrit March 2020