Change in ...coreboot[master]: autoport: Add support for Haswell-LynxPoint platform
by Iru Cai (vimacs) (Code Review)
Hello Iru Cai,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/30890
to review the following change.
Change subject: autoport: Add support for Haswell-LynxPoint platform
......................................................................
autoport: Add support for Haswell-LynxPoint platform
It can now generate a buildable source for Clevo W650SZ.
TODO:
- Support Lynx Point LP (GPIO registers differ from non-LP)
- Use PCH HD-Audio in azilia instead of the CPU/Northbridge HD-Audio
Change-Id: I4f6e8c97b5122101de2f36bba8ba9f8ddd5b813a
Signed-off-by: Iru Cai <mytbk920423(a)gmail.com>
---
M util/autoport/azalia.go
A util/autoport/haswell.go
A util/autoport/lynxpoint.go
M util/autoport/main.go
4 files changed, 625 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/30890/1
diff --git a/util/autoport/azalia.go b/util/autoport/azalia.go
index c525189..3090dd0 100644
--- a/util/autoport/azalia.go
+++ b/util/autoport/azalia.go
@@ -62,4 +62,9 @@
RegisterPCI(0x8086, 0x1c20, azalia{})
/* C216/ivybridge */
RegisterPCI(0x8086, 0x1e20, azalia{})
+ /* Haswell */
+ RegisterPCI(0x8086, 0x0c0c, azalia{})
+ /* Lynx Point */
+ RegisterPCI(0x8086, 0x8c20, azalia{})
+ RegisterPCI(0x8086, 0x9c20, azalia{})
}
diff --git a/util/autoport/haswell.go b/util/autoport/haswell.go
new file mode 100644
index 0000000..d3c9d9f
--- /dev/null
+++ b/util/autoport/haswell.go
@@ -0,0 +1,119 @@
+package main
+
+type haswellmc struct {
+ variant string
+}
+
+func (i haswellmc) Scan(ctx Context, addr PCIDevData) {
+ inteltool := ctx.InfoSource.GetInteltool()
+
+ /* FIXME:XX Move this somewhere else. */
+ MainboardIncludes = append(MainboardIncludes, "drivers/intel/gma/int15.h")
+ MainboardEnable += (` /* FIXME: fix those values*/
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+`)
+
+ DevTree = DevTreeNode{
+ Chip: "northbridge/intel/haswell",
+ MissingParent: "northbridge",
+ Comment: "FIXME: check gfx.ndid and gfx.did",
+ Registers: map[string]string{
+ "gpu_dp_b_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 2) & 7),
+ "gpu_dp_c_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 10) & 7),
+ "gpu_dp_d_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 18) & 7),
+ "gpu_panel_port_select": FormatInt32((inteltool.IGD[0xc7208] >> 30) & 3),
+ "gpu_panel_power_up_delay": FormatInt32((inteltool.IGD[0xc7208] >> 16) & 0x1fff),
+ "gpu_panel_power_backlight_on_delay": FormatInt32(inteltool.IGD[0xc7208] & 0x1fff),
+ "gpu_panel_power_down_delay": FormatInt32((inteltool.IGD[0xc720c] >> 16) & 0x1fff),
+ "gpu_panel_power_backlight_off_delay": FormatInt32(inteltool.IGD[0xc720c] & 0x1fff),
+ "gpu_panel_power_cycle_delay": FormatInt32(inteltool.IGD[0xc7210] & 0xff),
+ "gpu_cpu_backlight": FormatHex32(inteltool.IGD[0x48254]),
+ "gpu_pch_backlight": FormatHex32((inteltool.IGD[0xc8254] >> 16) * 0x10001),
+ "gpu_ddi_e_connected": FormatBool(((inteltool.IGD[0x64000] >> 4) & 1) == 0),
+ /* FIXME:XX hardcoded. */
+ "gfx.ndid": "3",
+ "gfx.did": "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }",
+ },
+ Children: []DevTreeNode{
+ {
+ Chip: "cpu_cluster",
+ Dev: 0,
+ Children: []DevTreeNode{
+ {
+ Chip: "cpu/intel/haswell",
+ Children: []DevTreeNode{
+ {
+ Chip: "lapic",
+ Dev: 0,
+ },
+ {
+ Chip: "lapic",
+ Dev: 0xacac,
+ Disabled: true,
+ },
+ },
+ Registers: map[string]string{
+ /* FIXME:XX hardcoded. */
+ "c1_acpower": "1",
+ "c2_acpower": "3",
+ "c3_acpower": "5",
+ "c1_battery": "1",
+ "c2_battery": "3",
+ "c3_battery": "5",
+ },
+ },
+ },
+ },
+
+ {
+ Chip: "domain",
+ Dev: 0,
+ PCIController: true,
+ ChildPCIBus: 0,
+ PCISlots: []PCISlot{
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x0, Func: 0}, writeEmpty: true, additionalComment: "Host bridge"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1, Func: 0}, writeEmpty: true, additionalComment: "PCIe Bridge for discrete graphics"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x2, Func: 0}, writeEmpty: true, additionalComment: "Internal graphics"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x3, Func: 0}, writeEmpty: true, additionalComment: "Mini-HD audio"},
+ },
+ },
+ },
+ }
+
+ PutPCIDev(addr, "Host bridge")
+
+ /* FIXME:XX some configs are unsupported. */
+
+ KconfigBool["CPU_INTEL_HASWELL"] = true
+ KconfigBool["NORTHBRIDGE_INTEL_HASWELL"] = true
+ KconfigBool["INTEL_INT15"] = true
+ KconfigBool["HAVE_ACPI_TABLES"] = true
+ KconfigBool["HAVE_ACPI_RESUME"] = true
+
+ KconfigInt["MAX_CPUS"] = 8
+
+ DSDTIncludes = append(DSDTIncludes, DSDTInclude{
+ File: "cpu/intel/common/acpi/cpu.asl",
+ })
+
+ DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{
+ File: "northbridge/intel/haswell/acpi/haswell.asl",
+ }, DSDTInclude{
+ File: "drivers/intel/gma/acpi/default_brightness_levels.asl",
+ })
+}
+
+func init() {
+ RegisterPCI(0x8086, 0x0c00, haswellmc{variant: "Desktop"})
+ RegisterPCI(0x8086, 0x0c04, haswellmc{variant: "Mobile"})
+ RegisterPCI(0x8086, 0x0a04, haswellmc{variant: "ULT"})
+ RegisterPCI(0x8086, 0x0c08, haswellmc{variant: "Server"})
+ for _, id := range []uint16{
+ 0x0402, 0x0412, 0x0422,
+ 0x0406, 0x0416, 0x0426,
+ 0x0d16, 0x0d26, 0x0d36,
+ 0x0a06, 0x0a16, 0x0a26,
+ } {
+ RegisterPCI(0x8086, id, GenericVGA{GenericPCI{Comment: "VGA controller"}})
+ }
+}
diff --git a/util/autoport/lynxpoint.go b/util/autoport/lynxpoint.go
new file mode 100644
index 0000000..df20c3f
--- /dev/null
+++ b/util/autoport/lynxpoint.go
@@ -0,0 +1,495 @@
+package main
+
+import (
+ "fmt"
+ "os"
+)
+
+type lynxpoint struct {
+ variant string
+ node *DevTreeNode
+}
+
+func (b lynxpoint) writeGPIOSet(ctx Context, sb *os.File,
+ val uint32, set uint, partno int, constraint uint32) {
+
+ max := uint(32)
+ if set == 3 {
+ max = 12
+ }
+
+ bits := [6][2]string{
+ {"GPIO_MODE_NATIVE", "GPIO_MODE_GPIO"},
+ {"GPIO_DIR_OUTPUT", "GPIO_DIR_INPUT"},
+ {"GPIO_LEVEL_LOW", "GPIO_LEVEL_HIGH"},
+ {"GPIO_RESET_PWROK", "GPIO_RESET_RSMRST"},
+ {"GPIO_NO_INVERT", "GPIO_INVERT"},
+ {"GPIO_NO_BLINK", "GPIO_BLINK"},
+ }
+
+ for i := uint(0); i < max; i++ {
+ if ((constraint>>i)&1 == 1) {
+ fmt.Fprintf(sb, " .gpio%d = %s,\n",
+ (set-1)*32+i,
+ bits[partno][(val>>i)&1])
+ }
+ }
+}
+
+func (b lynxpoint) GPIO(ctx Context, inteltool InteltoolData) {
+ var constraint uint32
+ gpio := Create(ctx, "gpio.c")
+ defer gpio.Close()
+
+ AddROMStageFile("gpio.c", "")
+
+ Add_gpl(gpio)
+ gpio.WriteString("#include <southbridge/intel/common/gpio.h>\n\n")
+
+ /* TODO: different in LP PCH */
+ addresses := [3][6]int{
+ {0x00, 0x04, 0x0c, 0x60, 0x2c, 0x18},
+ {0x30, 0x34, 0x38, 0x64, -1, -1},
+ {0x40, 0x44, 0x48, 0x68, -1, -1},
+ }
+
+ for set := 1; set <= 3; set++ {
+ for partno, part := range []string{"mode", "direction", "level", "reset", "invert", "blink"} {
+ addr := addresses[set-1][partno]
+ if addr < 0 {
+ continue
+ }
+ fmt.Fprintf(gpio, "static const struct pch_gpio_set%d pch_gpio_set%d_%s = {\n",
+ set, set, part)
+
+ constraint = 0xffffffff
+ switch part {
+ case "direction":
+ /* Ignored on native mode */
+ constraint = inteltool.GPIO[uint16(addresses[set-1][0])]
+ case "level":
+ /* Level doesn't matter for input */
+ constraint = inteltool.GPIO[uint16(addresses[set-1][0])]
+ constraint &^= inteltool.GPIO[uint16(addresses[set-1][1])]
+ case "reset":
+ /* Only show reset */
+ constraint = inteltool.GPIO[uint16(addresses[set-1][3])]
+ case "invert":
+ /* Only on input and only show inverted GPIO */
+ constraint = inteltool.GPIO[uint16(addresses[set-1][0])]
+ constraint &= inteltool.GPIO[uint16(addresses[set-1][1])]
+ constraint &= inteltool.GPIO[uint16(addresses[set-1][4])]
+ case "blink":
+ /* Only on output and only show blinking GPIO */
+ constraint = inteltool.GPIO[uint16(addresses[set-1][0])]
+ constraint &^= inteltool.GPIO[uint16(addresses[set-1][1])]
+ constraint &= inteltool.GPIO[uint16(addresses[set-1][5])]
+ }
+ b.writeGPIOSet(ctx, gpio, inteltool.GPIO[uint16(addr)], uint(set), partno, constraint)
+ gpio.WriteString("};\n\n")
+ }
+ }
+
+ gpio.WriteString(`const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
+`)
+}
+
+func (b lynxpoint) IsPCIeHotplug(ctx Context, port int) bool {
+ portDev, ok := PCIMap[PCIAddr{Bus: 0, Dev: 0x1c, Func: port}]
+ if !ok {
+ return false
+ }
+ return (portDev.ConfigDump[0xdb] & (1 << 6)) != 0
+}
+
+func (b lynxpoint) GetGPIOHeader() string {
+ return "southbridge/intel/lynxpoint/pch.h"
+}
+
+func (b lynxpoint) EnableGPE(in int) {
+ b.node.Registers[fmt.Sprintf("gpi%d_routing", in)] = "2"
+}
+
+func (b lynxpoint) EncodeGPE(in int) int {
+ return in + 0x10
+}
+
+func (b lynxpoint) DecodeGPE(in int) int {
+ return in - 0x10
+}
+
+func (b lynxpoint) NeedRouteGPIOManually() {
+ b.node.Comment += ", FIXME: set gpiX_routing for EC support"
+}
+
+func (b lynxpoint) Scan(ctx Context, addr PCIDevData) {
+
+ SouthBridge = &b
+
+ inteltool := ctx.InfoSource.GetInteltool()
+ b.GPIO(ctx, inteltool)
+
+ KconfigBool["SOUTHBRIDGE_INTEL_LYNXPOINT"] = true
+ if b.variant == "Lynx Point LP" {
+ KconfigBool["INTEL_LYNXPOINT_LP"] = true
+ }
+ KconfigBool["SERIRQ_CONTINUOUS_MODE"] = true
+ KconfigInt["USBDEBUG_HCD_INDEX"] = 2
+ KconfigComment["USBDEBUG_HCD_INDEX"] = "FIXME: check this"
+ dmi := ctx.InfoSource.GetDMI()
+ if dmi.Vendor == "LENOVO" {
+ KconfigInt["DRAM_RESET_GATE_GPIO"] = 10
+ } else {
+ KconfigInt["DRAM_RESET_GATE_GPIO"] = 60
+ }
+ KconfigComment["DRAM_RESET_GATE_GPIO"] = "FIXME: check this"
+
+ /* Not strictly speaking correct. These subsys/subvendor referer to PCI devices.
+ But most systems don't have any of those. But the config needs to be set
+ nevertheless. So set it to southbridge subsys/subvendor. */
+ KconfigHex["MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID"] = uint32(GetLE16(addr.ConfigDump[0x2c:0x2e]))
+ KconfigHex["MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID"] = uint32(GetLE16(addr.ConfigDump[0x2e:0x30]))
+
+ ich9GetFlashSize(ctx)
+
+ DSDTDefines = append(DSDTDefines,
+ DSDTDefine{
+ Key: "BRIGHTNESS_UP",
+ Value: "\\_SB.PCI0.GFX0.INCB",
+ },
+ DSDTDefine{
+ Key: "BRIGHTNESS_DOWN",
+ Value: "\\_SB.PCI0.GFX0.DECB",
+ },
+ DSDTDefine{
+ Key: "ACPI_VIDEO_DEVICE",
+ Value: "\\_SB.PCI0.GFX0",
+ })
+
+ /* SPI init */
+ MainboardIncludes = append(MainboardIncludes, "southbridge/intel/lynxpoint/pch.h")
+
+ cur := DevTreeNode{
+ Chip: "southbridge/intel/lynxpoint",
+ Comment: "Intel Series 8 Lynx Point PCH",
+
+ Registers: map[string]string{
+ "pirqa_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x60]),
+ "pirqb_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x61]),
+ "pirqc_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x62]),
+ "pirqd_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x63]),
+ "pirqe_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x68]),
+ "pirqf_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x69]),
+ "pirqg_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x6a]),
+ "pirqh_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x6b]),
+ "sata_ahci": "1",
+ "gen1_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x84:0x88]),
+ "gen2_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x88:0x8c]),
+ "gen3_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x8c:0x90]),
+ "gen4_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x90:0x94]),
+ "sata_port_map": fmt.Sprintf("0x%x", PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 2}].ConfigDump[0x92]&0x3f),
+ },
+ PCISlots: []PCISlot{
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x14, Func: 0}, writeEmpty: false, additionalComment: "USB 3.0 Controller"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 0}, writeEmpty: true, additionalComment: "Management Engine Interface 1"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 1}, writeEmpty: true, additionalComment: "Management Engine Interface 2"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 2}, writeEmpty: true, additionalComment: "Management Engine IDE-R"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 3}, writeEmpty: true, additionalComment: "Management Engine KT"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x19, Func: 0}, writeEmpty: true, additionalComment: "Intel Gigabit Ethernet"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1a, Func: 0}, writeEmpty: true, additionalComment: "USB2 EHCI #2"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1b, Func: 0}, writeEmpty: true, additionalComment: "High Definition Audio"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 0}, writeEmpty: true, additionalComment: "PCIe Port #1"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 1}, writeEmpty: true, additionalComment: "PCIe Port #2"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 2}, writeEmpty: true, additionalComment: "PCIe Port #3"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 3}, writeEmpty: true, additionalComment: "PCIe Port #4"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 4}, writeEmpty: true, additionalComment: "PCIe Port #5"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 5}, writeEmpty: true, additionalComment: "PCIe Port #6"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 6}, writeEmpty: true, additionalComment: "PCIe Port #7"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 7}, writeEmpty: true, additionalComment: "PCIe Port #8"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1d, Func: 0}, writeEmpty: true, additionalComment: "USB2 EHCI #1"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1e, Func: 0}, writeEmpty: true, additionalComment: "PCI bridge"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 0}, writeEmpty: true, additionalComment: "LPC bridge"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 2}, writeEmpty: true, additionalComment: "SATA Controller 1"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 3}, writeEmpty: true, additionalComment: "SMBus"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 5}, writeEmpty: true, additionalComment: "SATA Controller 2"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 6}, writeEmpty: true, additionalComment: "Thermal"},
+ },
+ }
+
+ b.node = &cur
+
+ PutPCIChip(addr, cur)
+ PutPCIDevParent(addr, "PCI-LPC bridge", "lpc")
+
+ DSDTIncludes = append(DSDTIncludes, DSDTInclude{
+ File: "southbridge/intel/lynxpoint/acpi/platform.asl",
+ })
+ DSDTIncludes = append(DSDTIncludes, DSDTInclude{
+ File: "southbridge/intel/lynxpoint/acpi/globalnvs.asl",
+ Comment: "global NVS and variables",
+ })
+ DSDTIncludes = append(DSDTIncludes, DSDTInclude{
+ File: "southbridge/intel/lynxpoint/acpi/sleepstates.asl",
+ })
+ DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{
+ File: "southbridge/intel/lynxpoint/acpi/pch.asl",
+ })
+
+ sb := Create(ctx, "romstage.c")
+ defer sb.Close()
+ Add_gpl(sb)
+ sb.WriteString(`#include <stdint.h>
+#include <cpu/intel/romstage.h>
+#include <cpu/intel/haswell/haswell.h>
+#include <northbridge/intel/haswell/haswell.h>
+#include <northbridge/intel/haswell/pei_data.h>
+#include <southbridge/intel/common/gpio.h>
+#include <southbridge/intel/lynxpoint/pch.h>
+
+static const struct rcba_config_instruction rcba_config[] = {
+`)
+ RestoreDIRRoute(sb, "D31IR", uint16(inteltool.RCBA[0x3140]))
+ RestoreDIRRoute(sb, "D29IR", uint16(inteltool.RCBA[0x3144]))
+ RestoreDIRRoute(sb, "D28IR", uint16(inteltool.RCBA[0x3146]))
+ RestoreDIRRoute(sb, "D27IR", uint16(inteltool.RCBA[0x3148]))
+ RestoreDIRRoute(sb, "D26IR", uint16(inteltool.RCBA[0x314c]))
+ RestoreDIRRoute(sb, "D25IR", uint16(inteltool.RCBA[0x3150]))
+ RestoreDIRRoute(sb, "D22IR", uint16(inteltool.RCBA[0x315c]))
+ RestoreDIRRoute(sb, "D20IR", uint16(inteltool.RCBA[0x3160]))
+
+ sb.WriteString(`
+ RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS),
+
+ RCBA_END_CONFIG,
+};`)
+
+ sb.WriteString(`
+
+void mainboard_config_superio(void)
+{
+}
+
+void mainboard_romstage_entry(unsigned long bist)
+{
+ struct pei_data pei_data = {
+ .pei_version = PEI_VERSION,
+ .mchbar = (uintptr_t)DEFAULT_MCHBAR,
+ .dmibar = (uintptr_t)DEFAULT_DMIBAR,
+ .epbar = DEFAULT_EPBAR,
+ .pciexbar = DEFAULT_PCIEXBAR,
+ .smbusbar = SMBUS_IO_BASE,
+ .wdbbar = 0x4000000,
+ .wdbsize = 0x1000,
+ .hpet_address = HPET_ADDR,
+ .rcba = (uintptr_t)DEFAULT_RCBA,
+ .pmbase = DEFAULT_PMBASE,
+ .gpiobase = DEFAULT_GPIOBASE,
+ .temp_mmio_base = 0xfed08000,
+ .system_type = 1, /* desktop/server, FIXME: check this */
+ .tseg_size = CONFIG_SMM_TSEG_SIZE,
+ .spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 }, /* FIXME: check this */
+ .ec_present = 0,
+ .dimm_channel0_disabled = 0, /* FIXME: leave channel 0 enabled */
+ .dimm_channel1_disabled = 0, /* FIXME: leave channel 1 enabled */
+ .max_ddr3_freq = 1600,
+ .usb2_ports = {
+ /* Length, Enable, OCn#, Location */
+`)
+
+ pdo1 := PCIMap[PCIAddr{Bus: 0, Dev: 0x1d, Func: 0}].ConfigDump[0x64]
+ ocmap1 := PCIMap[PCIAddr{Bus: 0, Dev: 0x1d, Func: 0}].ConfigDump[0x74:0x78]
+ pdo2 := PCIMap[PCIAddr{Bus: 0, Dev: 0x1a, Func: 0}].ConfigDump[0x64]
+ ocmap2 := PCIMap[PCIAddr{Bus: 0, Dev: 0x1a, Func: 0}].ConfigDump[0x74:0x78]
+
+ for port := uint(0); port < 14; port++ {
+ var port_oc int = -1
+ var port_pos string
+ var port_disable uint8
+
+ if port < 8 {
+ port_disable = (pdo1 >> port) & 1
+ for oc := 0; oc < 4; oc++ {
+ if ((ocmap1[oc] & (1 << port)) != 0) {
+ port_oc = oc
+ break
+ }
+ }
+ } else {
+ port_disable = (pdo2 >> (port - 8)) & 1
+ for oc := 0; oc < 4; oc++ {
+ if ((ocmap2[oc] & (1 << (port - 8))) != 0) {
+ port_oc = oc + 4
+ break
+ }
+ }
+ }
+ if port_disable == 1 {
+ port_pos = "USB_PORT_SKIP"
+ } else {
+ port_pos = "USB_PORT_BACK_PANEL"
+ }
+ if port_oc == -1 {
+ fmt.Fprintf(sb, " { 0x0040, %d, USB_OC_PIN_SKIP, %s },\n",
+ (port_disable ^ 1), port_pos)
+ } else {
+ fmt.Fprintf(sb, " { 0x0040, %d, %d, %s },\n",
+ (port_disable ^ 1), port_oc, port_pos)
+ }
+ }
+
+ sb.WriteString(` },
+ .usb3_ports = {
+`)
+
+ xpdo := PCIMap[PCIAddr{Bus: 0, Dev: 0x14, Func: 0}].ConfigDump[0xe8]
+ u3ocm := PCIMap[PCIAddr{Bus: 0, Dev: 0x14, Func: 0}].ConfigDump[0xc8:0xd0]
+
+ for port := uint(0); port < 6; port++ {
+ var port_oc int = -1
+ port_disable := (xpdo >> port) & 1
+ for oc := 0; oc < 8; oc++ {
+ if (u3ocm[oc] & (1 << port)) != 0 {
+ port_oc = oc
+ break
+ }
+ }
+ if port_oc == -1 {
+ fmt.Fprintf(sb, " { %d, USB_OC_PIN_SKIP },\n",
+ (port_disable ^ 1))
+ } else {
+ fmt.Fprintf(sb, " { %d, %d },\n",
+ (port_disable ^ 1), port_oc)
+ }
+ }
+
+ sb.WriteString(` },
+ };
+
+ struct romstage_params romstage_params = {
+ .pei_data = &pei_data,
+ .gpio_map = &mainboard_gpio_map,
+ .rcba_config = &rcba_config[0],
+ .bist = bist,
+ };
+
+ romstage_common(&romstage_params);
+}`)
+
+ gnvs := Create(ctx, "acpi_tables.c")
+ defer gnvs.Close()
+
+ Add_gpl(gnvs)
+ gnvs.WriteString(`#include <southbridge/intel/lynxpoint/nvs.h>
+
+/* FIXME: check this function. */
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+ /* Disable USB ports in S3 by default */
+ gnvs->s3u0 = 0;
+ gnvs->s3u1 = 0;
+
+ /* Disable USB ports in S5 by default */
+ gnvs->s5u0 = 0;
+ gnvs->s5u1 = 0;
+
+ // the lid is open by default.
+ gnvs->lids = 1;
+
+ gnvs->tcrt = 100;
+ gnvs->tpsv = 90;
+}
+`)
+
+}
+
+func init() {
+ for _, id := range []uint16 {
+ 0x8c41, 0x8c49, 0x8c4b, 0x8c4f,
+ } {
+ RegisterPCI(0x8086, uint16(id), lynxpoint{variant: "Lynx Point Mobile"})
+ }
+
+ for _, id := range []uint16 {
+ 0x8c42, 0x8c44, 0x8c46, 0x8c4a,
+ 0x8c4c, 0x8c4e, 0x8c50, 0x8c5c,
+ } {
+ RegisterPCI(0x8086, uint16(id), lynxpoint{variant: "Lynx Point Desktop"})
+ }
+
+ for _, id := range []uint16 {
+ 0x8c52, 0x8c54, 0x8c56,
+ } {
+ RegisterPCI(0x8086, uint16(id), lynxpoint{variant: "Lynx Point Server"})
+ }
+
+ for _, id := range []uint16 {
+ 0x9c41, 0x9c43, 0x9c45,
+ } {
+ RegisterPCI(0x8086, uint16(id), lynxpoint{variant: "Lynx Point LP"})
+ }
+
+ /* PCIe bridge */
+ for _, id := range []uint16{
+ 0x8c10, 0x8c12, 0x8c14, 0x8c16, 0x8c18, 0x8c1a, 0x8c1c, 0x8c1e,
+ 0x9c10, 0x9c12, 0x9c14, 0x9c16, 0x9c18, 0x9c1a,
+ } {
+ RegisterPCI(0x8086, id, GenericPCI{})
+ }
+
+ /* SMBus controller */
+ RegisterPCI(0x8086, 0x1c22, GenericPCI{MissingParent: "smbus"})
+ RegisterPCI(0x8086, 0x1e22, GenericPCI{MissingParent: "smbus"})
+ RegisterPCI(0x8086, 0x8c22, GenericPCI{MissingParent: "smbus"})
+ RegisterPCI(0x8086, 0x9c22, GenericPCI{MissingParent: "smbus"})
+
+ /* SATA */
+ for _, id := range []uint16{
+ 0x8c00, 0x8c02, 0x8c04, 0x8c06, 0x8c08, 0x8c0e,
+ 0x8c01, 0x8c03, 0x8c05, 0x8c07, 0x8c09, 0x8c0f,
+ 0x9c03, 0x9c05, 0x9c07, 0x9c0f,
+ } {
+ RegisterPCI(0x8086, id, GenericPCI{})
+ }
+
+ /* EHCI */
+ for _, id := range []uint16{
+ 0x9c26, 0x8c26, 0x8c2d,
+ } {
+ RegisterPCI(0x8086, id, GenericPCI{})
+ }
+
+ /* XHCI */
+ RegisterPCI(0x8086, 0x8c31, GenericPCI{})
+ RegisterPCI(0x8086, 0x9c31, GenericPCI{})
+
+ /* ME and children */
+ for _, id := range []uint16{
+ 0x8c3a, 0x8c3b,
+ } {
+ RegisterPCI(0x8086, id, GenericPCI{})
+ }
+
+ /* Ethernet */
+ RegisterPCI(0x8086, 0x8c33, GenericPCI{})
+}
diff --git a/util/autoport/main.go b/util/autoport/main.go
index 05a829b..c1920a7 100644
--- a/util/autoport/main.go
+++ b/util/autoport/main.go
@@ -236,6 +236,12 @@
pcidev.ConfigDump[addr])
}
+func RestoreDIRRoute(f *os.File, regname string, val uint16) {
+ fmt.Fprintf(f, " RCBA_SET_REG_16(%s, DIR_ROUTE(PIRQ%c, PIRQ%c, PIRQ%c, PIRQ%c)),\n",
+ regname, 'A' + (val & 7), 'A' + ((val >> 4) & 7),
+ 'A' + ((val >> 8) & 7), 'A' + ((val >> 12) & 7))
+}
+
func RestorePCI32Simple(f *os.File, pcidev PCIDevData, addr uint16) {
fmt.Fprintf(f, " pci_write_config32(PCI_DEV(%d, 0x%02x, %d), 0x%02x, 0x%02x%02x%02x%02x);\n",
pcidev.Bus, pcidev.Dev, pcidev.Func, addr,
--
To view, visit https://review.coreboot.org/c/coreboot/+/30890
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I4f6e8c97b5122101de2f36bba8ba9f8ddd5b813a
Gerrit-Change-Number: 30890
Gerrit-PatchSet: 1
Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com>
Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com>
Gerrit-MessageType: newchange
1 day, 1 hour
- 8
- 48
Change in coreboot[master]: [WIP] AGESA,binaryPI boards: Drop invalid MP table files
by Kyösti Mälkki (Code Review)
Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38313 )
Change subject: [WIP] AGESA,binaryPI boards: Drop invalid MP table files
......................................................................
[WIP] AGESA,binaryPI boards: Drop invalid MP table files
If we spot any error in the file, treat it as untested and
broken copy-paste.
Change-Id: Idd13b8b006fce7383f3f73c3c0a5d51a71c0155b
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/mainboard/amd/bettong/Kconfig
D src/mainboard/amd/bettong/mptable.c
M src/mainboard/amd/db-ft3b-lc/Kconfig
D src/mainboard/amd/db-ft3b-lc/mptable.c
M src/mainboard/amd/gardenia/Kconfig
D src/mainboard/amd/gardenia/mptable.c
M src/mainboard/amd/inagua/Kconfig
D src/mainboard/amd/inagua/mptable.c
M src/mainboard/amd/lamar/Kconfig
D src/mainboard/amd/lamar/mptable.c
M src/mainboard/amd/olivehill/Kconfig
D src/mainboard/amd/olivehill/mptable.c
M src/mainboard/amd/olivehillplus/Kconfig
D src/mainboard/amd/olivehillplus/mptable.c
M src/mainboard/amd/parmer/Kconfig
D src/mainboard/amd/parmer/mptable.c
M src/mainboard/amd/persimmon/Kconfig
D src/mainboard/amd/persimmon/mptable.c
M src/mainboard/amd/south_station/Kconfig
D src/mainboard/amd/south_station/mptable.c
M src/mainboard/amd/thatcher/Kconfig
D src/mainboard/amd/thatcher/mptable.c
M src/mainboard/amd/union_station/Kconfig
D src/mainboard/amd/union_station/mptable.c
M src/mainboard/asrock/e350m1/Kconfig
D src/mainboard/asrock/e350m1/mptable.c
M src/mainboard/asrock/imb-a180/Kconfig
D src/mainboard/asrock/imb-a180/mptable.c
M src/mainboard/asus/am1i-a/Kconfig
D src/mainboard/asus/am1i-a/mptable.c
M src/mainboard/asus/f2a85-m/Kconfig
D src/mainboard/asus/f2a85-m/mptable.c
M src/mainboard/bap/ode_e20XX/Kconfig
D src/mainboard/bap/ode_e20XX/mptable.c
M src/mainboard/bap/ode_e21XX/Kconfig
D src/mainboard/bap/ode_e21XX/mptable.c
M src/mainboard/biostar/a68n_5200/Kconfig
D src/mainboard/biostar/a68n_5200/mptable.c
M src/mainboard/biostar/am1ml/Kconfig
D src/mainboard/biostar/am1ml/mptable.c
M src/mainboard/elmex/pcm205400/Kconfig
D src/mainboard/elmex/pcm205400/mptable.c
M src/mainboard/gizmosphere/gizmo/Kconfig
D src/mainboard/gizmosphere/gizmo/mptable.c
M src/mainboard/gizmosphere/gizmo2/Kconfig
D src/mainboard/gizmosphere/gizmo2/mptable.c
D src/mainboard/google/kahlee/mptable.c
M src/mainboard/hp/abm/Kconfig
D src/mainboard/hp/abm/mptable.c
M src/mainboard/hp/pavilion_m6_1035dx/Kconfig
D src/mainboard/hp/pavilion_m6_1035dx/mptable.c
M src/mainboard/jetway/nf81-t56n-lf/Kconfig
D src/mainboard/jetway/nf81-t56n-lf/mptable.c
M src/mainboard/lenovo/g505s/Kconfig
D src/mainboard/lenovo/g505s/mptable.c
M src/mainboard/lippert/frontrunner-af/Kconfig
D src/mainboard/lippert/frontrunner-af/mptable.c
M src/mainboard/lippert/toucan-af/Kconfig
D src/mainboard/lippert/toucan-af/mptable.c
M src/mainboard/msi/ms7721/Kconfig
D src/mainboard/msi/ms7721/mptable.c
M src/mainboard/pcengines/apu1/Kconfig
D src/mainboard/pcengines/apu1/mptable.c
M src/mainboard/pcengines/apu2/Kconfig
D src/mainboard/pcengines/apu2/mptable.c
65 files changed, 0 insertions(+), 4,840 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/38313/1
diff --git a/src/mainboard/amd/bettong/Kconfig b/src/mainboard/amd/bettong/Kconfig
index 4617360..50140f7 100644
--- a/src/mainboard/amd/bettong/Kconfig
+++ b/src/mainboard/amd/bettong/Kconfig
@@ -28,7 +28,6 @@
select DEFAULT_POST_ON_LPC
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_8192
select GFXUMA
diff --git a/src/mainboard/amd/bettong/mptable.c b/src/mainboard/amd/bettong/mptable.c
deleted file mode 100644
index d9632d5..0000000
--- a/src/mainboard/amd/bettong/mptable.c
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/x86/lapic.h>
-#include <southbridge/amd/pi/hudson/hudson.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-
-static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
-{
- mc->mpc_length += length;
- mc->mpc_entry_count++;
-}
-
-static void my_smp_write_bus(struct mp_config_table *mc,
- unsigned char id, const char *bustype)
-{
- struct mpc_config_bus *mpc;
- mpc = smp_next_mpc_entry(mc);
- memset(mpc, '\0', sizeof(*mpc));
- mpc->mpc_type = MP_BUS;
- mpc->mpc_busid = id;
- memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
- smp_add_mpc_entry(mc, sizeof(*mpc));
-}
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
- memcpy(mc->mpc_oem, "AMD ", 8);
-
- smp_write_processors(mc);
-
- my_smp_write_bus(mc, 0, "PCI ");
- my_smp_write_bus(mc, 1, "PCI ");
- bus_isa = 0x02;
- my_smp_write_bus(mc, bus_isa, "ISA ");
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
-
- /* Internal VGA */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
- /* SMBUS */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
-
- /* HD Audio */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
- /* on board NIC & Slot PCIE. */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0. */
- PCI_INT(bus_pci, 0x5, 0x0, 0x14);
- PCI_INT(bus_pci, 0x5, 0x1, 0x15);
- PCI_INT(bus_pci, 0x5, 0x2, 0x16);
- PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_pci, 0x6, 0x0, 0x15);
- PCI_INT(bus_pci, 0x6, 0x1, 0x16);
- PCI_INT(bus_pci, 0x6, 0x2, 0x17);
- PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_pci, 0x7, 0x0, 0x16);
- PCI_INT(bus_pci, 0x7, 0x1, 0x17);
- PCI_INT(bus_pci, 0x7, 0x2, 0x14);
- PCI_INT(bus_pci, 0x7, 0x3, 0x15);
- }
-
- /* PCIe Lan*/
- PCI_INT(0x0, 0x06, 0x0, 0x13);
-
- /* FCH PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, 0x10);
- /* FCH PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, 0x11);
- /* FCH PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, 0x12);
- /* FCH PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, 0x13);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/amd/db-ft3b-lc/Kconfig b/src/mainboard/amd/db-ft3b-lc/Kconfig
index f17d2d3..7f24015 100644
--- a/src/mainboard/amd/db-ft3b-lc/Kconfig
+++ b/src/mainboard/amd/db-ft3b-lc/Kconfig
@@ -29,7 +29,6 @@
select DEFAULT_POST_ON_LPC
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_8192
select GFXUMA
diff --git a/src/mainboard/amd/db-ft3b-lc/mptable.c b/src/mainboard/amd/db-ft3b-lc/mptable.c
deleted file mode 100644
index 40a75ad..0000000
--- a/src/mainboard/amd/db-ft3b-lc/mptable.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- * Copyright (C) 2014 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <stdint.h>
-#include <cpu/x86/lapic.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /* Initialize the MP_Table */
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- /*
- * Type 0: Processor Entries:
- * LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
- * CPU Signature (Stepping, Model, Family),
- * Feature Flags
- */
- smp_write_processors(mc);
-
- /*
- * Type 1: Bus Entries:
- * Bus ID, Bus Type
- */
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /*
- * Type 2: I/O APICs:
- * APIC ID, Version, APIC Flags:EN, Address
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
- /*
- * Type 3: I/O Interrupt Table Entries:
- * Int Type, Int Polarity, Int Level, Source Bus ID,
- * Source Bus IRQ, Dest APIC ID, Dest PIN#
- */
-
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
-
- /* APU Internal Graphic Device */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]);
-
- /* SMBUS / ACPI */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]);
-
- /* Southbridge HD Audio */
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[PIRQ_EHCI1]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[PIRQ_EHCI2]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[PIRQ_EHCI3]);
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_OHCI4]);
-
- /* SATA */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
-
- /* on board NIC & Slot PCIE */
- PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]);
- PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]);
-
- /* PCIe Lan*/
- PCI_INT(0x0, 0x06, 0x0, intr_data_ptr[PIRQ_D]);
-
- /* FCH PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_A]);
- /* FCH PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_B]);
- /* FCH PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_C]);
- /* FCH PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_D]);
-
- IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
-
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/amd/gardenia/Kconfig b/src/mainboard/amd/gardenia/Kconfig
index e97a3ba..424a47d 100644
--- a/src/mainboard/amd/gardenia/Kconfig
+++ b/src/mainboard/amd/gardenia/Kconfig
@@ -21,7 +21,6 @@
select AMD_APU_STONEYRIDGE
select AMD_APU_PKG_FP4
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_8192
select GFXUMA
diff --git a/src/mainboard/amd/gardenia/mptable.c b/src/mainboard/amd/gardenia/mptable.c
deleted file mode 100644
index 5bb70e9..0000000
--- a/src/mainboard/amd/gardenia/mptable.c
+++ /dev/null
@@ -1,162 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/x86/lapic.h>
-#include <soc/southbridge.h>
-#include <amdblocks/amd_pci_util.h>
-
-static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
-{
- mc->mpc_length += length;
- mc->mpc_entry_count++;
-}
-
-static void my_smp_write_bus(struct mp_config_table *mc,
- unsigned char id, const char *bustype)
-{
- struct mpc_config_bus *mpc;
- mpc = smp_next_mpc_entry(mc);
- memset(mpc, '\0', sizeof(*mpc));
- mpc->mpc_type = MP_BUS;
- mpc->mpc_busid = id;
- memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
- smp_add_mpc_entry(mc, sizeof(*mpc));
-}
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
- memcpy(mc->mpc_oem, "AMD ", 8);
-
- smp_write_processors(mc);
-
- //mptable_write_buses(mc, NULL, &bus_isa);
- my_smp_write_bus(mc, 0, "PCI ");
- my_smp_write_bus(mc, 1, "PCI ");
- bus_isa = 0x02;
- my_smp_write_bus(mc, bus_isa, "ISA ");
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), \
- MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, \
- (intr), (apicid), (pin))
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, \
- MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), \
- (((dev)<<2)|(int_sign)), ioapic_id, (pin))
-
- /* Internal VGA */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
- /* SMBUS */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
-
- /* HD Audio */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
- /* on board NIC & Slot PCIE. */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0. */
- PCI_INT(bus_pci, 0x5, 0x0, 0x14);
- PCI_INT(bus_pci, 0x5, 0x1, 0x15);
- PCI_INT(bus_pci, 0x5, 0x2, 0x16);
- PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_pci, 0x6, 0x0, 0x15);
- PCI_INT(bus_pci, 0x6, 0x1, 0x16);
- PCI_INT(bus_pci, 0x6, 0x2, 0x17);
- PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_pci, 0x7, 0x0, 0x16);
- PCI_INT(bus_pci, 0x7, 0x1, 0x17);
- PCI_INT(bus_pci, 0x7, 0x2, 0x14);
- PCI_INT(bus_pci, 0x7, 0x3, 0x15);
- }
-
- /* PCIe Lan*/
- PCI_INT(0x0, 0x06, 0x0, 0x13);
-
- /* FCH PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, 0x10);
- /* FCH PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, 0x11);
- /* FCH PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, 0x12);
- /* FCH PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, 0x13);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/amd/inagua/Kconfig b/src/mainboard/amd/inagua/Kconfig
index a5ba07e..77f6b8a 100644
--- a/src/mainboard/amd/inagua/Kconfig
+++ b/src/mainboard/amd/inagua/Kconfig
@@ -27,7 +27,6 @@
select SUPERIO_SMSC_KBC1100
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_2048
select GFXUMA
diff --git a/src/mainboard/amd/inagua/mptable.c b/src/mainboard/amd/inagua/mptable.c
deleted file mode 100644
index b8bd0b3..0000000
--- a/src/mainboard/amd/inagua/mptable.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <string.h>
-#include <stdint.h>
-#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
- memcpy(mc->mpc_oem, "AMD ", 8);
-
- smp_write_processors(mc);
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
-
- /* APU Internal Graphic Device*/
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
- //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
- /* Southbridge HD Audio: */
- PCI_INT(0x0, 0x14, 0x2, 0x12);
-
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
- /* on board NIC & Slot PCIE. */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0. */
- PCI_INT(bus_pci, 0x5, 0x0, 0x14);
- PCI_INT(bus_pci, 0x5, 0x1, 0x15);
- PCI_INT(bus_pci, 0x5, 0x2, 0x16);
- PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_pci, 0x6, 0x0, 0x15);
- PCI_INT(bus_pci, 0x6, 0x1, 0x16);
- PCI_INT(bus_pci, 0x6, 0x2, 0x17);
- PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_pci, 0x7, 0x0, 0x16);
- PCI_INT(bus_pci, 0x7, 0x1, 0x17);
- PCI_INT(bus_pci, 0x7, 0x2, 0x14);
- PCI_INT(bus_pci, 0x7, 0x3, 0x15);
- }
-
- /* PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, 0x10);
- /* PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, 0x11);
- /* PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, 0x12);
- /* PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, 0x13);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/amd/lamar/Kconfig b/src/mainboard/amd/lamar/Kconfig
index c856534..2e19c3d 100644
--- a/src/mainboard/amd/lamar/Kconfig
+++ b/src/mainboard/amd/lamar/Kconfig
@@ -29,7 +29,6 @@
select SUPERIO_FINTEK_F81216H
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_8192
select GFXUMA
diff --git a/src/mainboard/amd/lamar/mptable.c b/src/mainboard/amd/lamar/mptable.c
deleted file mode 100644
index 1f2093d..0000000
--- a/src/mainboard/amd/lamar/mptable.c
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 - 2014 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <stdint.h>
-#include <cpu/x86/lapic.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <drivers/generic/ioapic/chip.h>
-#include <southbridge/amd/pi/hudson/amd_pci_int_defs.h>
-#include <northbridge/amd/pi/00630F01/pci_devs.h>
-
-#define NB_APIC_ADDR ((u8 *)0xFEC20000)
-
-#define PCI_INT(bus, dev, fn, apic, pin) \
- if (((pin) != 0x00) && ((pin) != 0x1F)) \
- { \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apic, (pin)); \
- }
-
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /* Initialize the MP_Table */
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- /*
- * Type 0: Processor Entries:
- * LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
- * CPU Signature (Stepping, Model, Family),
- * Feature Flags
- */
- smp_write_processors(mc);
-
- /*
- * Type 1: Bus Entries:
- * Bus ID, Bus Type
- */
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /*
- * Type 2: I/O APICs:
- * APIC ID, Version, APIC Flags:EN, Address
- */
-
- u8 apicid_nb = (io_apic_read(NB_APIC_ADDR, 0x00) >> 24); /* Get the GNB IOAPIC ID */
- u8 apicver_nb = (io_apic_read(NB_APIC_ADDR, 0x01) & 0xFF); /* Get the GNB IOAPIC version */
-
- smp_write_ioapic(mc, apicid_nb, apicver_nb, NB_APIC_ADDR);
-
- u8 apicid_sb = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); /* Get the southbridge IOAPIC ID */
- u8 apicver_sb = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); /* Get the southbridge IOAPIC version */
-
- smp_write_ioapic(mc, apicid_sb, apicver_sb, VIO_APIC_VADDR);
-
- /*
- * Type 3: I/O Interrupt Table Entries:
- * Int Type, Int Polarity, Int Level, Source Bus ID,
- * Source Bus IRQ, Dest APIC ID, Dest PIN#
- */
- mptable_add_isa_interrupts(mc, bus_isa, apicid_nb, 0);
- mptable_add_isa_interrupts(mc, bus_isa, apicid_sb, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-
- /* APU Internal Graphic Device */
- PCI_INT(0x0, 0x01, 0x0, apicid_nb, intr_data_ptr[PIRQ_GFX]);
- PCI_INT(0x0, 0x01, 0x1, apicid_nb, intr_data_ptr[PIRQ_ACTL]);
-
- /* SMBUS / ACPI */
- PCI_INT(0x0, 0x14, 0x0, apicid_sb, intr_data_ptr[PIRQ_SMBUS]);
-
- /* Southbridge HD Audio */
- PCI_INT(0x0, 0x14, 0x2, apicid_sb, intr_data_ptr[PIRQ_HDA]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, apicid_sb, intr_data_ptr[PIRQ_OHCI1]);
- PCI_INT(0x0, 0x12, 0x2, apicid_sb, intr_data_ptr[PIRQ_EHCI1]);
- PCI_INT(0x0, 0x13, 0x0, apicid_sb, intr_data_ptr[PIRQ_OHCI2]);
- PCI_INT(0x0, 0x13, 0x2, apicid_sb, intr_data_ptr[PIRQ_EHCI2]);
- PCI_INT(0x0, 0x16, 0x0, apicid_sb, intr_data_ptr[PIRQ_OHCI3]);
- PCI_INT(0x0, 0x16, 0x2, apicid_sb, intr_data_ptr[PIRQ_EHCI3]);
- PCI_INT(0x0, 0x14, 0x5, apicid_sb, intr_data_ptr[PIRQ_OHCI4]);
-
- /* SATA */
- PCI_INT(0x0, 0x11, 0x0, apicid_sb, intr_data_ptr[PIRQ_SATA]);
-
- /* IDE */
- PCI_INT(0x0, 0x14, 0x1, apicid_sb, intr_data_ptr[PIRQ_IDE]);
-
- /* PCI slots */
- /* NB Gfx PCIe Bridges */
- PCI_INT(0, 0x2, 0x1, apicid_nb, intr_data_ptr[PIRQ_A]);
- PCI_INT(0, 0x2, 0x2, apicid_nb, intr_data_ptr[PIRQ_A]);
-
- /* NB GPP PCIe Bridges */
- PCI_INT(0, 0x3, 0x1, apicid_nb, intr_data_ptr[PIRQ_A]);
- PCI_INT(0, 0x3, 0x2, apicid_nb, intr_data_ptr[PIRQ_A]);
- PCI_INT(0, 0x3, 0x3, apicid_nb, intr_data_ptr[PIRQ_A]);
- PCI_INT(0, 0x3, 0x4, apicid_nb, intr_data_ptr[PIRQ_A]);
- PCI_INT(0, 0x3, 0x5, apicid_nb, intr_data_ptr[PIRQ_A]);
-
- /* PCI slots */
- PCI_INT(0, 0x14, 0x4, apicid_sb, intr_data_ptr[PIRQ_A]);
-
- /* FCH GPP PCIe Bridges */
- PCI_INT(0x0, 0x15, 0x0, apicid_sb, intr_data_ptr[PIRQ_A]);
- /* FCH PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, apicid_sb, intr_data_ptr[PIRQ_A]);
- /* FCH PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, apicid_sb, intr_data_ptr[PIRQ_A]);
- /* FCH PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, apicid_sb, intr_data_ptr[PIRQ_A]);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
-
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/amd/olivehill/Kconfig b/src/mainboard/amd/olivehill/Kconfig
index 78f768f..8810c1d 100644
--- a/src/mainboard/amd/olivehill/Kconfig
+++ b/src/mainboard/amd/olivehill/Kconfig
@@ -27,7 +27,6 @@
select DEFAULT_POST_ON_LPC
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_4096
diff --git a/src/mainboard/amd/olivehill/mptable.c b/src/mainboard/amd/olivehill/mptable.c
deleted file mode 100644
index 7082013..0000000
--- a/src/mainboard/amd/olivehill/mptable.c
+++ /dev/null
@@ -1,158 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/x86/lapic.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <southbridge/amd/agesa/hudson/hudson.h>
-
-static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
-{
- mc->mpc_length += length;
- mc->mpc_entry_count++;
-}
-
-static void my_smp_write_bus(struct mp_config_table *mc,
- unsigned char id, const char *bustype)
-{
- struct mpc_config_bus *mpc;
- mpc = smp_next_mpc_entry(mc);
- memset(mpc, '\0', sizeof(*mpc));
- mpc->mpc_type = MP_BUS;
- mpc->mpc_busid = id;
- memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
- smp_add_mpc_entry(mc, sizeof(*mpc));
-}
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
- memcpy(mc->mpc_oem, "AMD ", 8);
-
- smp_write_processors(mc);
-
- //mptable_write_buses(mc, NULL, &bus_isa);
- my_smp_write_bus(mc, 0, "PCI ");
- my_smp_write_bus(mc, 1, "PCI ");
- bus_isa = 0x02;
- my_smp_write_bus(mc, bus_isa, "ISA ");
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
-
- /* Internal VGA */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
- /* SMBUS */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
-
- /* HD Audio */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
- /* on board NIC & Slot PCIE. */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0. */
- PCI_INT(bus_pci, 0x5, 0x0, 0x14);
- PCI_INT(bus_pci, 0x5, 0x1, 0x15);
- PCI_INT(bus_pci, 0x5, 0x2, 0x16);
- PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_pci, 0x6, 0x0, 0x15);
- PCI_INT(bus_pci, 0x6, 0x1, 0x16);
- PCI_INT(bus_pci, 0x6, 0x2, 0x17);
- PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_pci, 0x7, 0x0, 0x16);
- PCI_INT(bus_pci, 0x7, 0x1, 0x17);
- PCI_INT(bus_pci, 0x7, 0x2, 0x14);
- PCI_INT(bus_pci, 0x7, 0x3, 0x15);
- }
-
- /* PCIe Lan*/
- PCI_INT(0x0, 0x06, 0x0, 0x13);
-
- /* FCH PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, 0x10);
- /* FCH PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, 0x11);
- /* FCH PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, 0x12);
- /* FCH PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, 0x13);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/amd/olivehillplus/Kconfig b/src/mainboard/amd/olivehillplus/Kconfig
index 907de3b..1745969 100644
--- a/src/mainboard/amd/olivehillplus/Kconfig
+++ b/src/mainboard/amd/olivehillplus/Kconfig
@@ -28,7 +28,6 @@
select DEFAULT_POST_ON_LPC
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_8192
select GFXUMA
diff --git a/src/mainboard/amd/olivehillplus/mptable.c b/src/mainboard/amd/olivehillplus/mptable.c
deleted file mode 100644
index 0f6ca81..0000000
--- a/src/mainboard/amd/olivehillplus/mptable.c
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/x86/lapic.h>
-#include <southbridge/amd/pi/hudson/hudson.h>
-
-static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
-{
- mc->mpc_length += length;
- mc->mpc_entry_count++;
-}
-
-static void my_smp_write_bus(struct mp_config_table *mc,
- unsigned char id, const char *bustype)
-{
- struct mpc_config_bus *mpc;
- mpc = smp_next_mpc_entry(mc);
- memset(mpc, '\0', sizeof(*mpc));
- mpc->mpc_type = MP_BUS;
- mpc->mpc_busid = id;
- memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
- smp_add_mpc_entry(mc, sizeof(*mpc));
-}
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
- memcpy(mc->mpc_oem, "AMD ", 8);
-
- smp_write_processors(mc);
-
- //mptable_write_buses(mc, NULL, &bus_isa);
- my_smp_write_bus(mc, 0, "PCI ");
- my_smp_write_bus(mc, 1, "PCI ");
- bus_isa = 0x02;
- my_smp_write_bus(mc, bus_isa, "ISA ");
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
-
- /* Internal VGA */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
- /* SMBUS */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
-
- /* HD Audio */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
- /* on board NIC & Slot PCIE. */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0. */
- PCI_INT(bus_pci, 0x5, 0x0, 0x14);
- PCI_INT(bus_pci, 0x5, 0x1, 0x15);
- PCI_INT(bus_pci, 0x5, 0x2, 0x16);
- PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_pci, 0x6, 0x0, 0x15);
- PCI_INT(bus_pci, 0x6, 0x1, 0x16);
- PCI_INT(bus_pci, 0x6, 0x2, 0x17);
- PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_pci, 0x7, 0x0, 0x16);
- PCI_INT(bus_pci, 0x7, 0x1, 0x17);
- PCI_INT(bus_pci, 0x7, 0x2, 0x14);
- PCI_INT(bus_pci, 0x7, 0x3, 0x15);
- }
-
- /* PCIe Lan*/
- PCI_INT(0x0, 0x06, 0x0, 0x13);
-
- /* FCH PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, 0x10);
- /* FCH PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, 0x11);
- /* FCH PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, 0x12);
- /* FCH PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, 0x13);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/amd/parmer/Kconfig b/src/mainboard/amd/parmer/Kconfig
index ae024dd..94f55ce 100644
--- a/src/mainboard/amd/parmer/Kconfig
+++ b/src/mainboard/amd/parmer/Kconfig
@@ -27,7 +27,6 @@
select DEFAULT_POST_ON_LPC
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_4096
diff --git a/src/mainboard/amd/parmer/mptable.c b/src/mainboard/amd/parmer/mptable.c
deleted file mode 100644
index 3a5540c..0000000
--- a/src/mainboard/amd/parmer/mptable.c
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/x86/lapic.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <southbridge/amd/agesa/hudson/hudson.h>
-
-static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
-{
- mc->mpc_length += length;
- mc->mpc_entry_count++;
-}
-
-static void my_smp_write_bus(struct mp_config_table *mc,
- unsigned char id, const char *bustype)
-{
- struct mpc_config_bus *mpc;
- mpc = smp_next_mpc_entry(mc);
- memset(mpc, '\0', sizeof(*mpc));
- mpc->mpc_type = MP_BUS;
- mpc->mpc_busid = id;
- memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
- smp_add_mpc_entry(mc, sizeof(*mpc));
-}
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
- memcpy(mc->mpc_oem, "AMD ", 8);
-
- smp_write_processors(mc);
-
- //mptable_write_buses(mc, NULL, &bus_isa);
- my_smp_write_bus(mc, 0, "PCI ");
- my_smp_write_bus(mc, 1, "PCI ");
- bus_isa = 0x02;
- my_smp_write_bus(mc, bus_isa, "ISA ");
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
-
- /* Internal VGA */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
- /* SMBUS */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
-
- /* HD Audio */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
- /* on board NIC & Slot PCIE. */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0. */
- PCI_INT(bus_pci, 0x5, 0x0, 0x14);
- PCI_INT(bus_pci, 0x5, 0x1, 0x15);
- PCI_INT(bus_pci, 0x5, 0x2, 0x16);
- PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_pci, 0x6, 0x0, 0x15);
- PCI_INT(bus_pci, 0x6, 0x1, 0x16);
- PCI_INT(bus_pci, 0x6, 0x2, 0x17);
- PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_pci, 0x7, 0x0, 0x16);
- PCI_INT(bus_pci, 0x7, 0x1, 0x17);
- PCI_INT(bus_pci, 0x7, 0x2, 0x14);
- PCI_INT(bus_pci, 0x7, 0x3, 0x15);
- }
-
- /* PCIe Lan*/
- PCI_INT(0x0, 0x06, 0x0, 0x13);
-
- /* FCH PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, 0x10);
- /* FCH PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, 0x11);
- /* FCH PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, 0x12);
- /* FCH PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, 0x13);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/amd/persimmon/Kconfig b/src/mainboard/amd/persimmon/Kconfig
index f243f0f..248e4d4 100644
--- a/src/mainboard/amd/persimmon/Kconfig
+++ b/src/mainboard/amd/persimmon/Kconfig
@@ -27,7 +27,6 @@
select SUPERIO_FINTEK_F81865F
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_4096
diff --git a/src/mainboard/amd/persimmon/mptable.c b/src/mainboard/amd/persimmon/mptable.c
deleted file mode 100644
index bc7a3ac..0000000
--- a/src/mainboard/amd/persimmon/mptable.c
+++ /dev/null
@@ -1,142 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- * Copyright (C) 2014 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <stdint.h>
-#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <drivers/generic/ioapic/chip.h>
-#include <arch/ioapic.h>
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- /* Initialize the MP_Table */
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- /*
- * Type 0: Processor Entries:
- * LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
- * CPU Signature (Stepping, Model, Family),
- * Feature Flags
- */
- smp_write_processors(mc);
-
- /*
- * Type 1: Bus Entries:
- * Bus ID, Bus Type
- */
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /*
- * Type 2: I/O APICs:
- * APIC ID, Version, APIC Flags:EN, Address
- */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /*
- * Type 3: I/O Interrupt Table Entries:
- * Int Type, Int Polarity, Int Level, Source Bus ID,
- * Source Bus IRQ, Dest APIC ID, Dest PIN#
- */
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
-
- /* APU Internal Graphic Device */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]);
-
- /* SMBUS / ACPI */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]);
-
- /* Southbridge HD Audio */
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]);
-
- /* LPC */
- PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
- PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
- PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]);
- PCI_INT(0x0, 0x14, 0x5, intr_data_ptr[PIRQ_OHCI4]);
-
- /* IDE */
- PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_IDE]);
-
- /* SATA */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
-
- /* on board NIC & Slot PCIE */
- PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */
- PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0 */
- PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */
- PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */
- PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */
- PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */
- }
-
- /* PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */
- /* PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */
- /* PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */
- /* PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
- IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/amd/south_station/Kconfig b/src/mainboard/amd/south_station/Kconfig
index 42841cb..0d76d50 100644
--- a/src/mainboard/amd/south_station/Kconfig
+++ b/src/mainboard/amd/south_station/Kconfig
@@ -27,7 +27,6 @@
select SUPERIO_FINTEK_F81865F
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_4096
select GFXUMA
diff --git a/src/mainboard/amd/south_station/mptable.c b/src/mainboard/amd/south_station/mptable.c
deleted file mode 100644
index b8bd0b3..0000000
--- a/src/mainboard/amd/south_station/mptable.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <string.h>
-#include <stdint.h>
-#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
- memcpy(mc->mpc_oem, "AMD ", 8);
-
- smp_write_processors(mc);
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
-
- /* APU Internal Graphic Device*/
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
- //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
- /* Southbridge HD Audio: */
- PCI_INT(0x0, 0x14, 0x2, 0x12);
-
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
- /* on board NIC & Slot PCIE. */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0. */
- PCI_INT(bus_pci, 0x5, 0x0, 0x14);
- PCI_INT(bus_pci, 0x5, 0x1, 0x15);
- PCI_INT(bus_pci, 0x5, 0x2, 0x16);
- PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_pci, 0x6, 0x0, 0x15);
- PCI_INT(bus_pci, 0x6, 0x1, 0x16);
- PCI_INT(bus_pci, 0x6, 0x2, 0x17);
- PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_pci, 0x7, 0x0, 0x16);
- PCI_INT(bus_pci, 0x7, 0x1, 0x17);
- PCI_INT(bus_pci, 0x7, 0x2, 0x14);
- PCI_INT(bus_pci, 0x7, 0x3, 0x15);
- }
-
- /* PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, 0x10);
- /* PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, 0x11);
- /* PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, 0x12);
- /* PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, 0x13);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/amd/thatcher/Kconfig b/src/mainboard/amd/thatcher/Kconfig
index e556592..b79511f 100644
--- a/src/mainboard/amd/thatcher/Kconfig
+++ b/src/mainboard/amd/thatcher/Kconfig
@@ -27,7 +27,6 @@
select DEFAULT_POST_ON_LPC
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select SUPERIO_SMSC_LPC47N217
diff --git a/src/mainboard/amd/thatcher/mptable.c b/src/mainboard/amd/thatcher/mptable.c
deleted file mode 100644
index 05d222a..0000000
--- a/src/mainboard/amd/thatcher/mptable.c
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/x86/lapic.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <southbridge/amd/agesa/hudson/hudson.h>
-
-static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
-{
- mc->mpc_length += length;
- mc->mpc_entry_count++;
-}
-
-static void my_smp_write_bus(struct mp_config_table *mc,
- unsigned char id, const char *bustype)
-{
- struct mpc_config_bus *mpc;
- mpc = smp_next_mpc_entry(mc);
- memset(mpc, '\0', sizeof(*mpc));
- mpc->mpc_type = MP_BUS;
- mpc->mpc_busid = id;
- memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
- smp_add_mpc_entry(mc, sizeof(*mpc));
-}
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
- u8 byte;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
- memcpy(mc->mpc_oem, "AMD ", 8);
-
- smp_write_processors(mc);
-
- //mptable_write_buses(mc, NULL, &bus_isa);
- my_smp_write_bus(mc, 0, "PCI ");
- my_smp_write_bus(mc, 1, "PCI ");
- bus_isa = 0x02;
- my_smp_write_bus(mc, bus_isa, "ISA ");
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
-
- /* Internal VGA */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
- /* SMBUS */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
-
- /* HD Audio */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
- /* on board NIC & Slot PCIE. */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0. */
- PCI_INT(bus_pci, 0x5, 0x0, 0x14);
- PCI_INT(bus_pci, 0x5, 0x1, 0x15);
- PCI_INT(bus_pci, 0x5, 0x2, 0x16);
- PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_pci, 0x6, 0x0, 0x15);
- PCI_INT(bus_pci, 0x6, 0x1, 0x16);
- PCI_INT(bus_pci, 0x6, 0x2, 0x17);
- PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_pci, 0x7, 0x0, 0x16);
- PCI_INT(bus_pci, 0x7, 0x1, 0x17);
- PCI_INT(bus_pci, 0x7, 0x2, 0x14);
- PCI_INT(bus_pci, 0x7, 0x3, 0x15);
- }
-
- /* PCIe Lan*/
- PCI_INT(0x0, 0x06, 0x0, 0x13);
-
- /* FCH PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, 0x10);
- /* FCH PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, 0x11);
- /* FCH PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, 0x12);
- /* FCH PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, 0x13);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/amd/union_station/Kconfig b/src/mainboard/amd/union_station/Kconfig
index 1532d34..2dc82c9 100644
--- a/src/mainboard/amd/union_station/Kconfig
+++ b/src/mainboard/amd/union_station/Kconfig
@@ -26,7 +26,6 @@
select SOUTHBRIDGE_AMD_CIMX_SB800
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_2048
select GFXUMA
diff --git a/src/mainboard/amd/union_station/mptable.c b/src/mainboard/amd/union_station/mptable.c
deleted file mode 100644
index b8bd0b3..0000000
--- a/src/mainboard/amd/union_station/mptable.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <string.h>
-#include <stdint.h>
-#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
- memcpy(mc->mpc_oem, "AMD ", 8);
-
- smp_write_processors(mc);
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
-
- /* APU Internal Graphic Device*/
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
- //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
- /* Southbridge HD Audio: */
- PCI_INT(0x0, 0x14, 0x2, 0x12);
-
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
- /* on board NIC & Slot PCIE. */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0. */
- PCI_INT(bus_pci, 0x5, 0x0, 0x14);
- PCI_INT(bus_pci, 0x5, 0x1, 0x15);
- PCI_INT(bus_pci, 0x5, 0x2, 0x16);
- PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_pci, 0x6, 0x0, 0x15);
- PCI_INT(bus_pci, 0x6, 0x1, 0x16);
- PCI_INT(bus_pci, 0x6, 0x2, 0x17);
- PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_pci, 0x7, 0x0, 0x16);
- PCI_INT(bus_pci, 0x7, 0x1, 0x17);
- PCI_INT(bus_pci, 0x7, 0x2, 0x14);
- PCI_INT(bus_pci, 0x7, 0x3, 0x15);
- }
-
- /* PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, 0x10);
- /* PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, 0x11);
- /* PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, 0x12);
- /* PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, 0x13);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/asrock/e350m1/Kconfig b/src/mainboard/asrock/e350m1/Kconfig
index 3bbc2a5..18058c9 100644
--- a/src/mainboard/asrock/e350m1/Kconfig
+++ b/src/mainboard/asrock/e350m1/Kconfig
@@ -24,7 +24,6 @@
select SB_SUPERIO_HWM
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_4096
diff --git a/src/mainboard/asrock/e350m1/mptable.c b/src/mainboard/asrock/e350m1/mptable.c
deleted file mode 100644
index ce8cfa0..0000000
--- a/src/mainboard/asrock/e350m1/mptable.c
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-
-#include <arch/ioapic.h>
-#include <arch/smp/mpspec.h>
-#include <stdint.h>
-#include <string.h>
-
-#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
- memcpy(mc->mpc_oem, "ASROCK ", 8);
-
- smp_write_processors(mc);
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
-
- /* APU Internal Graphic Device*/
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
- //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
- /* Southbridge HD Audio: */
- PCI_INT(0x0, 0x14, 0x2, 0x12);
-
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
- /* on board NIC & Slot PCIE. */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0. */
- PCI_INT(bus_pci, 0x5, 0x0, 0x14);
- PCI_INT(bus_pci, 0x5, 0x1, 0x15);
- PCI_INT(bus_pci, 0x5, 0x2, 0x16);
- PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_pci, 0x6, 0x0, 0x15);
- PCI_INT(bus_pci, 0x6, 0x1, 0x16);
- PCI_INT(bus_pci, 0x6, 0x2, 0x17);
- PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_pci, 0x7, 0x0, 0x16);
- PCI_INT(bus_pci, 0x7, 0x1, 0x17);
- PCI_INT(bus_pci, 0x7, 0x2, 0x14);
- PCI_INT(bus_pci, 0x7, 0x3, 0x15);
- }
-
- /* PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, 0x10);
- /* PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, 0x11);
- /* PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, 0x12);
- /* PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, 0x13);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/asrock/imb-a180/Kconfig b/src/mainboard/asrock/imb-a180/Kconfig
index 8fca61c..7110c89 100644
--- a/src/mainboard/asrock/imb-a180/Kconfig
+++ b/src/mainboard/asrock/imb-a180/Kconfig
@@ -24,7 +24,6 @@
select SUPERIO_WINBOND_W83627UHG
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_4096
diff --git a/src/mainboard/asrock/imb-a180/mptable.c b/src/mainboard/asrock/imb-a180/mptable.c
deleted file mode 100644
index 7082013..0000000
--- a/src/mainboard/asrock/imb-a180/mptable.c
+++ /dev/null
@@ -1,158 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/x86/lapic.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <southbridge/amd/agesa/hudson/hudson.h>
-
-static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
-{
- mc->mpc_length += length;
- mc->mpc_entry_count++;
-}
-
-static void my_smp_write_bus(struct mp_config_table *mc,
- unsigned char id, const char *bustype)
-{
- struct mpc_config_bus *mpc;
- mpc = smp_next_mpc_entry(mc);
- memset(mpc, '\0', sizeof(*mpc));
- mpc->mpc_type = MP_BUS;
- mpc->mpc_busid = id;
- memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
- smp_add_mpc_entry(mc, sizeof(*mpc));
-}
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
- memcpy(mc->mpc_oem, "AMD ", 8);
-
- smp_write_processors(mc);
-
- //mptable_write_buses(mc, NULL, &bus_isa);
- my_smp_write_bus(mc, 0, "PCI ");
- my_smp_write_bus(mc, 1, "PCI ");
- bus_isa = 0x02;
- my_smp_write_bus(mc, bus_isa, "ISA ");
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
-
- /* Internal VGA */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
- /* SMBUS */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
-
- /* HD Audio */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
- /* on board NIC & Slot PCIE. */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0. */
- PCI_INT(bus_pci, 0x5, 0x0, 0x14);
- PCI_INT(bus_pci, 0x5, 0x1, 0x15);
- PCI_INT(bus_pci, 0x5, 0x2, 0x16);
- PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_pci, 0x6, 0x0, 0x15);
- PCI_INT(bus_pci, 0x6, 0x1, 0x16);
- PCI_INT(bus_pci, 0x6, 0x2, 0x17);
- PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_pci, 0x7, 0x0, 0x16);
- PCI_INT(bus_pci, 0x7, 0x1, 0x17);
- PCI_INT(bus_pci, 0x7, 0x2, 0x14);
- PCI_INT(bus_pci, 0x7, 0x3, 0x15);
- }
-
- /* PCIe Lan*/
- PCI_INT(0x0, 0x06, 0x0, 0x13);
-
- /* FCH PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, 0x10);
- /* FCH PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, 0x11);
- /* FCH PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, 0x12);
- /* FCH PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, 0x13);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/asus/am1i-a/Kconfig b/src/mainboard/asus/am1i-a/Kconfig
index a0dae9f..8a7e7e9 100644
--- a/src/mainboard/asus/am1i-a/Kconfig
+++ b/src/mainboard/asus/am1i-a/Kconfig
@@ -10,7 +10,6 @@
select USE_OPTION_TABLE
select HAVE_CMOS_DEFAULT
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB
diff --git a/src/mainboard/asus/am1i-a/mptable.c b/src/mainboard/asus/am1i-a/mptable.c
deleted file mode 100644
index 9efcab3..0000000
--- a/src/mainboard/asus/am1i-a/mptable.c
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- * Copyright (C) 2018 Gergely Kiss <mail.gery(a)gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <stdint.h>
-#include <cpu/x86/lapic.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <drivers/generic/ioapic/chip.h>
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- /* Initialize the MP_Table */
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- /*
- * Type 0: Processor Entries:
- * LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
- * CPU Signature (Stepping, Model, Family),
- * Feature Flags
- */
- smp_write_processors(mc);
-
- /*
- * Type 1: Bus Entries:
- * Bus ID, Bus Type
- */
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /*
- * Type 2: I/O APICs:
- * APIC ID, Version, APIC Flags:EN, Address
- */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /*
- * Type 3: I/O Interrupt Table Entries:
- * Int Type, Int Polarity, Int Level, Source Bus ID,
- * Source Bus IRQ, Dest APIC ID, Dest PIN#
- */
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
-
- /* APU Internal Graphic Device */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_A]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_B]);
-
- /* GPP Ports */
- PCI_INT(0x0, 0x02, 0x0, intr_data_ptr[PIRQ_A]);
- PCI_INT(0x0, 0x02, 0x1, intr_data_ptr[PIRQ_B]);
- PCI_INT(0x0, 0x02, 0x2, intr_data_ptr[PIRQ_C]);
- PCI_INT(0x0, 0x02, 0x3, intr_data_ptr[PIRQ_D]);
-
- /* SATA */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
-
- /* USB */
- PCI_INT(0x0, 0x10, 0x0, intr_data_ptr[PIRQ_C]); /* XHCI */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[PIRQ_EHCI1]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[PIRQ_EHCI2]);
-
- /* Southbridge HD Audio */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_HDA]);
-
- /* PCIe slot & Onboard NIC */
- PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_A]);
- PCI_INT(0x1, 0x0, 0x1, intr_data_ptr[PIRQ_B]);
- PCI_INT(0x1, 0x0, 0x2, intr_data_ptr[PIRQ_C]);
- PCI_INT(0x1, 0x0, 0x3, intr_data_ptr[PIRQ_D]);
- PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_B]);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
- IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/asus/f2a85-m/Kconfig b/src/mainboard/asus/f2a85-m/Kconfig
index c1dd063..5d5adb4 100644
--- a/src/mainboard/asus/f2a85-m/Kconfig
+++ b/src/mainboard/asus/f2a85-m/Kconfig
@@ -23,7 +23,6 @@
select SOUTHBRIDGE_AMD_AGESA_HUDSON
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select SUPERIO_ITE_IT8728F if BOARD_ASUS_F2A85_M || BOARD_ASUS_F2A85_M_LE
diff --git a/src/mainboard/asus/f2a85-m/mptable.c b/src/mainboard/asus/f2a85-m/mptable.c
deleted file mode 100644
index b5b0433..0000000
--- a/src/mainboard/asus/f2a85-m/mptable.c
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/ioapic.h>
-#include <arch/smp/mpspec.h>
-#include <cpu/x86/lapic.h>
-#include <stdint.h>
-#include <string.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <southbridge/amd/agesa/hudson/hudson.h>
-
-static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
-{
- mc->mpc_length += length;
- mc->mpc_entry_count++;
-}
-
-static void my_smp_write_bus(struct mp_config_table *mc,
- unsigned char id, const char *bustype)
-{
- struct mpc_config_bus *mpc;
- mpc = smp_next_mpc_entry(mc);
- memset(mpc, '\0', sizeof(*mpc));
- mpc->mpc_type = MP_BUS;
- mpc->mpc_busid = id;
- memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
- smp_add_mpc_entry(mc, sizeof(*mpc));
-}
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
- u8 byte;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
- memcpy(mc->mpc_oem, "AMD ", 8);
-
- smp_write_processors(mc);
-
- //mptable_write_buses(mc, NULL, &bus_isa);
- my_smp_write_bus(mc, 0, "PCI ");
- my_smp_write_bus(mc, 1, "PCI ");
- bus_isa = 0x02;
- my_smp_write_bus(mc, bus_isa, "ISA ");
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
-
- /* IOMMU */
- PCI_INT(0x0, 0x0, 0x0, 0x10);
- PCI_INT(0x0, 0x0, 0x1, 0x11);
- PCI_INT(0x0, 0x0, 0x2, 0x12);
- PCI_INT(0x0, 0x0, 0x3, 0x13);
-
- /* Internal VGA */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
- /* SMBUS */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
-
- /* HD Audio */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
- /* on board NIC & Slot PCIE. */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0. */
- PCI_INT(bus_pci, 0x5, 0x0, 0x14);
- PCI_INT(bus_pci, 0x5, 0x1, 0x15);
- PCI_INT(bus_pci, 0x5, 0x2, 0x16);
- PCI_INT(bus_pci, 0x5, 0x3, 0x17);
- }
-
- /* PCIe Lan*/
- PCI_INT(0x0, 0x06, 0x0, 0x13);
-
- /* FCH PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, 0x10);
- /* FCH PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, 0x11);
- /* FCH PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, 0x12);
- /* FCH PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, 0x13);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/bap/ode_e20XX/Kconfig b/src/mainboard/bap/ode_e20XX/Kconfig
index 2a72deb..6d417ed 100644
--- a/src/mainboard/bap/ode_e20XX/Kconfig
+++ b/src/mainboard/bap/ode_e20XX/Kconfig
@@ -28,7 +28,6 @@
select DEFAULT_POST_ON_LPC
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_4096
select GFXUMA
diff --git a/src/mainboard/bap/ode_e20XX/mptable.c b/src/mainboard/bap/ode_e20XX/mptable.c
deleted file mode 100644
index e4edc5f..0000000
--- a/src/mainboard/bap/ode_e20XX/mptable.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <stdint.h>
-#include <cpu/x86/lapic.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <drivers/generic/ioapic/chip.h>
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- /* Initialize the MP_Table */
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- /*
- * Type 0: Processor Entries:
- * LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
- * CPU Signature (Stepping, Model, Family),
- * Feature Flags
- */
- smp_write_processors(mc);
-
- /*
- * Type 1: Bus Entries:
- * Bus ID, Bus Type
- */
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /*
- * Type 2: I/O APICs:
- * APIC ID, Version, APIC Flags:EN, Address
- */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /*
- * Type 3: I/O Interrupt Table Entries:
- * Int Type, Int Polarity, Int Level, Source Bus ID,
- * Source Bus IRQ, Dest APIC ID, Dest PIN#
- */
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
-
- /* APU Internal Graphic Device */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]);
-
- /* SMBUS / ACPI */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]);
-
- /* Southbridge HD Audio */
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]);
-
- /* LPC */
- PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
- PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
- PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]);
- PCI_INT(0x0, 0x16, 0x2, intr_data_ptr[PIRQ_EHCI3]);
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_OHCI4]);
-
- /* SATA */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
-
- /* on board NIC & Slot PCIE */
- PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]);
- PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]);
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0 */
- PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]);
- PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]);
- PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]);
- PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]);
-
- /* PCI_SLOT 1 */
- PCI_INT(bus_pci, 0x6, 0x0, intr_data_ptr[PIRQ_F]);
- PCI_INT(bus_pci, 0x6, 0x1, intr_data_ptr[PIRQ_G]);
- PCI_INT(bus_pci, 0x6, 0x2, intr_data_ptr[PIRQ_H]);
- PCI_INT(bus_pci, 0x6, 0x3, intr_data_ptr[PIRQ_E]);
-
- /* PCI_SLOT 2 */
- PCI_INT(bus_pci, 0x7, 0x0, intr_data_ptr[PIRQ_G]);
- PCI_INT(bus_pci, 0x7, 0x1, intr_data_ptr[PIRQ_H]);
- PCI_INT(bus_pci, 0x7, 0x2, intr_data_ptr[PIRQ_E]);
- PCI_INT(bus_pci, 0x7, 0x3, intr_data_ptr[PIRQ_F]);
-
- PCI_INT(bus_pci, 0x0, 0x0, intr_data_ptr[PIRQ_C]);
- PCI_INT(bus_pci, 0x0, 0x1, intr_data_ptr[PIRQ_D]);
- PCI_INT(bus_pci, 0x0, 0x2, intr_data_ptr[PIRQ_E]);
- }
-
- /* PCIe Lan*/
- PCI_INT(0x0, 0x06, 0x0, intr_data_ptr[PIRQ_D]);
-
- /* FCH PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_A]);
- /* FCH PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_B]);
- /* FCH PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_C]);
- /* FCH PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_D]);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
- IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/bap/ode_e21XX/Kconfig b/src/mainboard/bap/ode_e21XX/Kconfig
index ff71d5b..c1b78c8 100644
--- a/src/mainboard/bap/ode_e21XX/Kconfig
+++ b/src/mainboard/bap/ode_e21XX/Kconfig
@@ -28,7 +28,6 @@
select DEFAULT_POST_ON_LPC
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_8192
select GFXUMA
diff --git a/src/mainboard/bap/ode_e21XX/mptable.c b/src/mainboard/bap/ode_e21XX/mptable.c
deleted file mode 100644
index 0f6ca81..0000000
--- a/src/mainboard/bap/ode_e21XX/mptable.c
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/x86/lapic.h>
-#include <southbridge/amd/pi/hudson/hudson.h>
-
-static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
-{
- mc->mpc_length += length;
- mc->mpc_entry_count++;
-}
-
-static void my_smp_write_bus(struct mp_config_table *mc,
- unsigned char id, const char *bustype)
-{
- struct mpc_config_bus *mpc;
- mpc = smp_next_mpc_entry(mc);
- memset(mpc, '\0', sizeof(*mpc));
- mpc->mpc_type = MP_BUS;
- mpc->mpc_busid = id;
- memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
- smp_add_mpc_entry(mc, sizeof(*mpc));
-}
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
- memcpy(mc->mpc_oem, "AMD ", 8);
-
- smp_write_processors(mc);
-
- //mptable_write_buses(mc, NULL, &bus_isa);
- my_smp_write_bus(mc, 0, "PCI ");
- my_smp_write_bus(mc, 1, "PCI ");
- bus_isa = 0x02;
- my_smp_write_bus(mc, bus_isa, "ISA ");
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
-
- /* Internal VGA */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
- /* SMBUS */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
-
- /* HD Audio */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
- /* on board NIC & Slot PCIE. */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0. */
- PCI_INT(bus_pci, 0x5, 0x0, 0x14);
- PCI_INT(bus_pci, 0x5, 0x1, 0x15);
- PCI_INT(bus_pci, 0x5, 0x2, 0x16);
- PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_pci, 0x6, 0x0, 0x15);
- PCI_INT(bus_pci, 0x6, 0x1, 0x16);
- PCI_INT(bus_pci, 0x6, 0x2, 0x17);
- PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_pci, 0x7, 0x0, 0x16);
- PCI_INT(bus_pci, 0x7, 0x1, 0x17);
- PCI_INT(bus_pci, 0x7, 0x2, 0x14);
- PCI_INT(bus_pci, 0x7, 0x3, 0x15);
- }
-
- /* PCIe Lan*/
- PCI_INT(0x0, 0x06, 0x0, 0x13);
-
- /* FCH PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, 0x10);
- /* FCH PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, 0x11);
- /* FCH PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, 0x12);
- /* FCH PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, 0x13);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/biostar/a68n_5200/Kconfig b/src/mainboard/biostar/a68n_5200/Kconfig
index f608513..c8d8884 100644
--- a/src/mainboard/biostar/a68n_5200/Kconfig
+++ b/src/mainboard/biostar/a68n_5200/Kconfig
@@ -29,7 +29,6 @@
select SUPERIO_ITE_IT8728F
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_4096
select GFXUMA
diff --git a/src/mainboard/biostar/a68n_5200/mptable.c b/src/mainboard/biostar/a68n_5200/mptable.c
deleted file mode 100644
index 7082013..0000000
--- a/src/mainboard/biostar/a68n_5200/mptable.c
+++ /dev/null
@@ -1,158 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/x86/lapic.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <southbridge/amd/agesa/hudson/hudson.h>
-
-static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
-{
- mc->mpc_length += length;
- mc->mpc_entry_count++;
-}
-
-static void my_smp_write_bus(struct mp_config_table *mc,
- unsigned char id, const char *bustype)
-{
- struct mpc_config_bus *mpc;
- mpc = smp_next_mpc_entry(mc);
- memset(mpc, '\0', sizeof(*mpc));
- mpc->mpc_type = MP_BUS;
- mpc->mpc_busid = id;
- memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
- smp_add_mpc_entry(mc, sizeof(*mpc));
-}
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
- memcpy(mc->mpc_oem, "AMD ", 8);
-
- smp_write_processors(mc);
-
- //mptable_write_buses(mc, NULL, &bus_isa);
- my_smp_write_bus(mc, 0, "PCI ");
- my_smp_write_bus(mc, 1, "PCI ");
- bus_isa = 0x02;
- my_smp_write_bus(mc, bus_isa, "ISA ");
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
-
- /* Internal VGA */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
- /* SMBUS */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
-
- /* HD Audio */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
- /* on board NIC & Slot PCIE. */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0. */
- PCI_INT(bus_pci, 0x5, 0x0, 0x14);
- PCI_INT(bus_pci, 0x5, 0x1, 0x15);
- PCI_INT(bus_pci, 0x5, 0x2, 0x16);
- PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_pci, 0x6, 0x0, 0x15);
- PCI_INT(bus_pci, 0x6, 0x1, 0x16);
- PCI_INT(bus_pci, 0x6, 0x2, 0x17);
- PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_pci, 0x7, 0x0, 0x16);
- PCI_INT(bus_pci, 0x7, 0x1, 0x17);
- PCI_INT(bus_pci, 0x7, 0x2, 0x14);
- PCI_INT(bus_pci, 0x7, 0x3, 0x15);
- }
-
- /* PCIe Lan*/
- PCI_INT(0x0, 0x06, 0x0, 0x13);
-
- /* FCH PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, 0x10);
- /* FCH PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, 0x11);
- /* FCH PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, 0x12);
- /* FCH PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, 0x13);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/biostar/am1ml/Kconfig b/src/mainboard/biostar/am1ml/Kconfig
index 9eaa6fb..c9960e3 100644
--- a/src/mainboard/biostar/am1ml/Kconfig
+++ b/src/mainboard/biostar/am1ml/Kconfig
@@ -24,7 +24,6 @@
select GFXUMA
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB
diff --git a/src/mainboard/biostar/am1ml/mptable.c b/src/mainboard/biostar/am1ml/mptable.c
deleted file mode 100644
index 659a141..0000000
--- a/src/mainboard/biostar/am1ml/mptable.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <stdint.h>
-#include <cpu/x86/lapic.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <drivers/generic/ioapic/chip.h>
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- /* Initialize the MP_Table */
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- /*
- * Type 0: Processor Entries:
- * LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
- * CPU Signature (Stepping, Model, Family),
- * Feature Flags
- */
- smp_write_processors(mc);
-
- /*
- * Type 1: Bus Entries:
- * Bus ID, Bus Type
- */
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /*
- * Type 2: I/O APICs:
- * APIC ID, Version, APIC Flags:EN, Address
- */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /*
- * Type 3: I/O Interrupt Table Entries:
- * Int Type, Int Polarity, Int Level, Source Bus ID,
- * Source Bus IRQ, Dest APIC ID, Dest PIN#
- */
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
-
- /* APU Internal Graphic Device */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]);
-
- /* SMBUS / ACPI */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]);
-
- /* Southbridge HD Audio */
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]);
-
- /* LPC */
- PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
- PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
- PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]);
- PCI_INT(0x0, 0x16, 0x2, intr_data_ptr[PIRQ_EHCI3]);
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_OHCI4]);
-
- /* SATA */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
-
- /* on board NIC & Slot PCIE */
- PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]);
- PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]);
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0 */
- PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]);
- PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]);
- PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]);
- PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]);
-
- /* PCI_SLOT 1 */
- PCI_INT(bus_pci, 0x6, 0x0, intr_data_ptr[PIRQ_F]);
- PCI_INT(bus_pci, 0x6, 0x1, intr_data_ptr[PIRQ_G]);
- PCI_INT(bus_pci, 0x6, 0x2, intr_data_ptr[PIRQ_H]);
- PCI_INT(bus_pci, 0x6, 0x3, intr_data_ptr[PIRQ_E]);
-
- /* PCI_SLOT 2 */
- PCI_INT(bus_pci, 0x7, 0x0, intr_data_ptr[PIRQ_G]);
- PCI_INT(bus_pci, 0x7, 0x1, intr_data_ptr[PIRQ_H]);
- PCI_INT(bus_pci, 0x7, 0x2, intr_data_ptr[PIRQ_E]);
- PCI_INT(bus_pci, 0x7, 0x3, intr_data_ptr[PIRQ_F]);
-
- PCI_INT(bus_pci, 0x0, 0x0, intr_data_ptr[PIRQ_C]);
- PCI_INT(bus_pci, 0x0, 0x1, intr_data_ptr[PIRQ_D]);
- PCI_INT(bus_pci, 0x0, 0x2, intr_data_ptr[PIRQ_E]);
- }
-
- /* PCIe Lan*/
- //PCI_INT(0x0, 0x06, 0x0, intr_data_ptr[PIRQ_D]);
-
- /* FCH PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_A]);
- /* FCH PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_B]);
- /* FCH PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_C]);
- /* FCH PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_D]);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
- IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/elmex/pcm205400/Kconfig b/src/mainboard/elmex/pcm205400/Kconfig
index e94a6d8..5892992 100644
--- a/src/mainboard/elmex/pcm205400/Kconfig
+++ b/src/mainboard/elmex/pcm205400/Kconfig
@@ -39,7 +39,6 @@
select SUPERIO_FINTEK_F81865F
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_4096
diff --git a/src/mainboard/elmex/pcm205400/mptable.c b/src/mainboard/elmex/pcm205400/mptable.c
deleted file mode 100644
index bc7a3ac..0000000
--- a/src/mainboard/elmex/pcm205400/mptable.c
+++ /dev/null
@@ -1,142 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- * Copyright (C) 2014 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <stdint.h>
-#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <drivers/generic/ioapic/chip.h>
-#include <arch/ioapic.h>
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- /* Initialize the MP_Table */
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- /*
- * Type 0: Processor Entries:
- * LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
- * CPU Signature (Stepping, Model, Family),
- * Feature Flags
- */
- smp_write_processors(mc);
-
- /*
- * Type 1: Bus Entries:
- * Bus ID, Bus Type
- */
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /*
- * Type 2: I/O APICs:
- * APIC ID, Version, APIC Flags:EN, Address
- */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /*
- * Type 3: I/O Interrupt Table Entries:
- * Int Type, Int Polarity, Int Level, Source Bus ID,
- * Source Bus IRQ, Dest APIC ID, Dest PIN#
- */
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
-
- /* APU Internal Graphic Device */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]);
-
- /* SMBUS / ACPI */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]);
-
- /* Southbridge HD Audio */
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]);
-
- /* LPC */
- PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
- PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
- PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]);
- PCI_INT(0x0, 0x14, 0x5, intr_data_ptr[PIRQ_OHCI4]);
-
- /* IDE */
- PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_IDE]);
-
- /* SATA */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
-
- /* on board NIC & Slot PCIE */
- PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */
- PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0 */
- PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */
- PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */
- PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */
- PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */
- }
-
- /* PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */
- /* PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */
- /* PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */
- /* PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
- IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/gizmosphere/gizmo/Kconfig b/src/mainboard/gizmosphere/gizmo/Kconfig
index e195e8f..30c88c1 100644
--- a/src/mainboard/gizmosphere/gizmo/Kconfig
+++ b/src/mainboard/gizmosphere/gizmo/Kconfig
@@ -23,7 +23,6 @@
select SOUTHBRIDGE_AMD_CIMX_SB800
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_2048
diff --git a/src/mainboard/gizmosphere/gizmo/mptable.c b/src/mainboard/gizmosphere/gizmo/mptable.c
deleted file mode 100644
index a47336c..0000000
--- a/src/mainboard/gizmosphere/gizmo/mptable.c
+++ /dev/null
@@ -1,127 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- * Copyright (C) 2013 Sage Electronic Engineering, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <string.h>
-#include <stdint.h>
-#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
- memcpy(mc->mpc_oem, "AMD ", 8);
-
- smp_write_processors(mc);
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
-
- /* APU Internal Graphic Device*/
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
- //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
- /* Southbridge HD Audio: */
- PCI_INT(0x0, 0x14, 0x2, 0x12);
-
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
- /* on board NIC & Slot PCIE. */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0. */
- PCI_INT(bus_pci, 0x5, 0x0, 0x14);
- PCI_INT(bus_pci, 0x5, 0x1, 0x15);
- PCI_INT(bus_pci, 0x5, 0x2, 0x16);
- PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_pci, 0x6, 0x0, 0x15);
- PCI_INT(bus_pci, 0x6, 0x1, 0x16);
- PCI_INT(bus_pci, 0x6, 0x2, 0x17);
- PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_pci, 0x7, 0x0, 0x16);
- PCI_INT(bus_pci, 0x7, 0x1, 0x17);
- PCI_INT(bus_pci, 0x7, 0x2, 0x14);
- PCI_INT(bus_pci, 0x7, 0x3, 0x15);
- }
-
- /* PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, 0x10);
- /* PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, 0x11);
- /* PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, 0x12);
- /* PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, 0x13);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/gizmosphere/gizmo2/Kconfig b/src/mainboard/gizmosphere/gizmo2/Kconfig
index 685e271..6a8095d 100644
--- a/src/mainboard/gizmosphere/gizmo2/Kconfig
+++ b/src/mainboard/gizmosphere/gizmo2/Kconfig
@@ -28,7 +28,6 @@
select DEFAULT_POST_ON_LPC
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_4096
diff --git a/src/mainboard/gizmosphere/gizmo2/mptable.c b/src/mainboard/gizmosphere/gizmo2/mptable.c
deleted file mode 100644
index e4edc5f..0000000
--- a/src/mainboard/gizmosphere/gizmo2/mptable.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <stdint.h>
-#include <cpu/x86/lapic.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <drivers/generic/ioapic/chip.h>
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- /* Initialize the MP_Table */
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- /*
- * Type 0: Processor Entries:
- * LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
- * CPU Signature (Stepping, Model, Family),
- * Feature Flags
- */
- smp_write_processors(mc);
-
- /*
- * Type 1: Bus Entries:
- * Bus ID, Bus Type
- */
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /*
- * Type 2: I/O APICs:
- * APIC ID, Version, APIC Flags:EN, Address
- */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /*
- * Type 3: I/O Interrupt Table Entries:
- * Int Type, Int Polarity, Int Level, Source Bus ID,
- * Source Bus IRQ, Dest APIC ID, Dest PIN#
- */
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
-
- /* APU Internal Graphic Device */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]);
-
- /* SMBUS / ACPI */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]);
-
- /* Southbridge HD Audio */
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]);
-
- /* LPC */
- PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
- PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
- PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]);
- PCI_INT(0x0, 0x16, 0x2, intr_data_ptr[PIRQ_EHCI3]);
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_OHCI4]);
-
- /* SATA */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
-
- /* on board NIC & Slot PCIE */
- PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]);
- PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]);
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0 */
- PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]);
- PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]);
- PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]);
- PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]);
-
- /* PCI_SLOT 1 */
- PCI_INT(bus_pci, 0x6, 0x0, intr_data_ptr[PIRQ_F]);
- PCI_INT(bus_pci, 0x6, 0x1, intr_data_ptr[PIRQ_G]);
- PCI_INT(bus_pci, 0x6, 0x2, intr_data_ptr[PIRQ_H]);
- PCI_INT(bus_pci, 0x6, 0x3, intr_data_ptr[PIRQ_E]);
-
- /* PCI_SLOT 2 */
- PCI_INT(bus_pci, 0x7, 0x0, intr_data_ptr[PIRQ_G]);
- PCI_INT(bus_pci, 0x7, 0x1, intr_data_ptr[PIRQ_H]);
- PCI_INT(bus_pci, 0x7, 0x2, intr_data_ptr[PIRQ_E]);
- PCI_INT(bus_pci, 0x7, 0x3, intr_data_ptr[PIRQ_F]);
-
- PCI_INT(bus_pci, 0x0, 0x0, intr_data_ptr[PIRQ_C]);
- PCI_INT(bus_pci, 0x0, 0x1, intr_data_ptr[PIRQ_D]);
- PCI_INT(bus_pci, 0x0, 0x2, intr_data_ptr[PIRQ_E]);
- }
-
- /* PCIe Lan*/
- PCI_INT(0x0, 0x06, 0x0, intr_data_ptr[PIRQ_D]);
-
- /* FCH PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_A]);
- /* FCH PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_B]);
- /* FCH PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_C]);
- /* FCH PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_D]);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
- IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/google/kahlee/mptable.c b/src/mainboard/google/kahlee/mptable.c
deleted file mode 100644
index 5bb70e9..0000000
--- a/src/mainboard/google/kahlee/mptable.c
+++ /dev/null
@@ -1,162 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/x86/lapic.h>
-#include <soc/southbridge.h>
-#include <amdblocks/amd_pci_util.h>
-
-static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
-{
- mc->mpc_length += length;
- mc->mpc_entry_count++;
-}
-
-static void my_smp_write_bus(struct mp_config_table *mc,
- unsigned char id, const char *bustype)
-{
- struct mpc_config_bus *mpc;
- mpc = smp_next_mpc_entry(mc);
- memset(mpc, '\0', sizeof(*mpc));
- mpc->mpc_type = MP_BUS;
- mpc->mpc_busid = id;
- memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
- smp_add_mpc_entry(mc, sizeof(*mpc));
-}
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
- memcpy(mc->mpc_oem, "AMD ", 8);
-
- smp_write_processors(mc);
-
- //mptable_write_buses(mc, NULL, &bus_isa);
- my_smp_write_bus(mc, 0, "PCI ");
- my_smp_write_bus(mc, 1, "PCI ");
- bus_isa = 0x02;
- my_smp_write_bus(mc, bus_isa, "ISA ");
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), \
- MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, \
- (intr), (apicid), (pin))
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, \
- MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), \
- (((dev)<<2)|(int_sign)), ioapic_id, (pin))
-
- /* Internal VGA */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
- /* SMBUS */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
-
- /* HD Audio */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
- /* on board NIC & Slot PCIE. */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0. */
- PCI_INT(bus_pci, 0x5, 0x0, 0x14);
- PCI_INT(bus_pci, 0x5, 0x1, 0x15);
- PCI_INT(bus_pci, 0x5, 0x2, 0x16);
- PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_pci, 0x6, 0x0, 0x15);
- PCI_INT(bus_pci, 0x6, 0x1, 0x16);
- PCI_INT(bus_pci, 0x6, 0x2, 0x17);
- PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_pci, 0x7, 0x0, 0x16);
- PCI_INT(bus_pci, 0x7, 0x1, 0x17);
- PCI_INT(bus_pci, 0x7, 0x2, 0x14);
- PCI_INT(bus_pci, 0x7, 0x3, 0x15);
- }
-
- /* PCIe Lan*/
- PCI_INT(0x0, 0x06, 0x0, 0x13);
-
- /* FCH PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, 0x10);
- /* FCH PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, 0x11);
- /* FCH PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, 0x12);
- /* FCH PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, 0x13);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/hp/abm/Kconfig b/src/mainboard/hp/abm/Kconfig
index 907c025..6239086 100644
--- a/src/mainboard/hp/abm/Kconfig
+++ b/src/mainboard/hp/abm/Kconfig
@@ -29,7 +29,6 @@
select SUPERIO_NUVOTON_NCT5104D
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_8192
diff --git a/src/mainboard/hp/abm/mptable.c b/src/mainboard/hp/abm/mptable.c
deleted file mode 100644
index 7082013..0000000
--- a/src/mainboard/hp/abm/mptable.c
+++ /dev/null
@@ -1,158 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/x86/lapic.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <southbridge/amd/agesa/hudson/hudson.h>
-
-static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
-{
- mc->mpc_length += length;
- mc->mpc_entry_count++;
-}
-
-static void my_smp_write_bus(struct mp_config_table *mc,
- unsigned char id, const char *bustype)
-{
- struct mpc_config_bus *mpc;
- mpc = smp_next_mpc_entry(mc);
- memset(mpc, '\0', sizeof(*mpc));
- mpc->mpc_type = MP_BUS;
- mpc->mpc_busid = id;
- memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
- smp_add_mpc_entry(mc, sizeof(*mpc));
-}
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
- memcpy(mc->mpc_oem, "AMD ", 8);
-
- smp_write_processors(mc);
-
- //mptable_write_buses(mc, NULL, &bus_isa);
- my_smp_write_bus(mc, 0, "PCI ");
- my_smp_write_bus(mc, 1, "PCI ");
- bus_isa = 0x02;
- my_smp_write_bus(mc, bus_isa, "ISA ");
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
-
- /* Internal VGA */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
- /* SMBUS */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
-
- /* HD Audio */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
- /* on board NIC & Slot PCIE. */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0. */
- PCI_INT(bus_pci, 0x5, 0x0, 0x14);
- PCI_INT(bus_pci, 0x5, 0x1, 0x15);
- PCI_INT(bus_pci, 0x5, 0x2, 0x16);
- PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_pci, 0x6, 0x0, 0x15);
- PCI_INT(bus_pci, 0x6, 0x1, 0x16);
- PCI_INT(bus_pci, 0x6, 0x2, 0x17);
- PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_pci, 0x7, 0x0, 0x16);
- PCI_INT(bus_pci, 0x7, 0x1, 0x17);
- PCI_INT(bus_pci, 0x7, 0x2, 0x14);
- PCI_INT(bus_pci, 0x7, 0x3, 0x15);
- }
-
- /* PCIe Lan*/
- PCI_INT(0x0, 0x06, 0x0, 0x13);
-
- /* FCH PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, 0x10);
- /* FCH PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, 0x11);
- /* FCH PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, 0x12);
- /* FCH PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, 0x13);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig
index c6c35df..1f17a15 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig
+++ b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig
@@ -25,7 +25,6 @@
select EC_COMPAL_ENE932
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_SMI_HANDLER
select HAVE_ACPI_TABLES
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c b/src/mainboard/hp/pavilion_m6_1035dx/mptable.c
deleted file mode 100644
index ecc57b0..0000000
--- a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c
+++ /dev/null
@@ -1,162 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/ioapic.h>
-#include <arch/smp/mpspec.h>
-#include <cpu/x86/lapic.h>
-#include <stdint.h>
-#include <string.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <southbridge/amd/agesa/hudson/hudson.h>
-
-static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
-{
- mc->mpc_length += length;
- mc->mpc_entry_count++;
-}
-
-static void my_smp_write_bus(struct mp_config_table *mc,
- unsigned char id, const char *bustype)
-{
- struct mpc_config_bus *mpc;
- mpc = smp_next_mpc_entry(mc);
- memset(mpc, '\0', sizeof(*mpc));
- mpc->mpc_type = MP_BUS;
- mpc->mpc_busid = id;
- memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
- smp_add_mpc_entry(mc, sizeof(*mpc));
-}
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
- memcpy(mc->mpc_oem, "AMD ", 8);
-
- smp_write_processors(mc);
-
- //mptable_write_buses(mc, NULL, &bus_isa);
- my_smp_write_bus(mc, 0, "PCI ");
- my_smp_write_bus(mc, 1, "PCI ");
- bus_isa = 0x02;
- my_smp_write_bus(mc, bus_isa, "ISA ");
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
-
- /* IOMMU */
- PCI_INT(0x0, 0x00, 0x0, 0x10);
- PCI_INT(0x0, 0x00, 0x1, 0x11);
- PCI_INT(0x0, 0x00, 0x2, 0x12);
- PCI_INT(0x0, 0x00, 0x3, 0x13);
-
- /* Internal VGA */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
- /* SMBUS */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
-
- /* HD Audio */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
- /* on board NIC & Slot PCIE. */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0. */
- PCI_INT(bus_pci, 0x5, 0x0, 0x14);
- PCI_INT(bus_pci, 0x5, 0x1, 0x15);
- PCI_INT(bus_pci, 0x5, 0x2, 0x16);
- PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_pci, 0x6, 0x0, 0x15);
- PCI_INT(bus_pci, 0x6, 0x1, 0x16);
- PCI_INT(bus_pci, 0x6, 0x2, 0x17);
- PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_pci, 0x7, 0x0, 0x16);
- PCI_INT(bus_pci, 0x7, 0x1, 0x17);
- PCI_INT(bus_pci, 0x7, 0x2, 0x14);
- PCI_INT(bus_pci, 0x7, 0x3, 0x15);
- }
-
- /* PCIe Lan*/
- PCI_INT(0x0, 0x06, 0x0, 0x13);
-
- /* FCH PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, 0x10);
- /* FCH PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, 0x11);
- /* FCH PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, 0x12);
- /* FCH PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, 0x13);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/jetway/nf81-t56n-lf/Kconfig b/src/mainboard/jetway/nf81-t56n-lf/Kconfig
index dfa01b9..dddca36 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/Kconfig
+++ b/src/mainboard/jetway/nf81-t56n-lf/Kconfig
@@ -28,7 +28,6 @@
select SUPERIO_FINTEK_F71869AD
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_2048
diff --git a/src/mainboard/jetway/nf81-t56n-lf/mptable.c b/src/mainboard/jetway/nf81-t56n-lf/mptable.c
deleted file mode 100644
index 9a983b4..0000000
--- a/src/mainboard/jetway/nf81-t56n-lf/mptable.c
+++ /dev/null
@@ -1,143 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- * Copyright (C) 2014 Sage Electronic Engineering, LLC.
- * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/ioapic.h>
-#include <arch/smp/mpspec.h>
-#include <drivers/generic/ioapic/chip.h>
-#include <stdint.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- /* Initialize the MP_Table */
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- /*
- * Type 0: Processor Entries:
- * LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
- * CPU Signature (Stepping, Model, Family),
- * Feature Flags
- */
- smp_write_processors(mc);
-
- /*
- * Type 1: Bus Entries:
- * Bus ID, Bus Type
- */
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /*
- * Type 2: I/O APICs:
- * APIC ID, Version, APIC Flags:EN, Address
- */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /*
- * Type 3: I/O Interrupt Table Entries:
- * Int Type, Int Polarity, Int Level, Source Bus ID,
- * Source Bus IRQ, Dest APIC ID, Dest PIN#
- */
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
-
- /* APU Internal Graphic Device */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]);
-
- /* SMBUS / ACPI */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]);
-
- /* Southbridge HD Audio */
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]);
-
- /* LPC */
- PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
- PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
- PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]);
- PCI_INT(0x0, 0x14, 0x5, intr_data_ptr[PIRQ_OHCI4]);
-
- /* IDE */
- PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_IDE]);
-
- /* SATA */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
-
- /* On-board NIC & Slot PCIE. */
- PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */
- PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0 */
- PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */
- PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */
- PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */
- PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */
- }
-
- /* On-board Realtek NIC 2. (PCIe PortA) */
- PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */
- /* PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */
- /* PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */
- /* PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
- IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/lenovo/g505s/Kconfig b/src/mainboard/lenovo/g505s/Kconfig
index 6ffe508..7f0d7bf 100644
--- a/src/mainboard/lenovo/g505s/Kconfig
+++ b/src/mainboard/lenovo/g505s/Kconfig
@@ -24,7 +24,6 @@
select DEFAULT_POST_ON_LPC
select EC_COMPAL_ENE932
select HAVE_OPTION_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_SMI_HANDLER
select HAVE_ACPI_TABLES
diff --git a/src/mainboard/lenovo/g505s/mptable.c b/src/mainboard/lenovo/g505s/mptable.c
deleted file mode 100644
index ecc57b0..0000000
--- a/src/mainboard/lenovo/g505s/mptable.c
+++ /dev/null
@@ -1,162 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/ioapic.h>
-#include <arch/smp/mpspec.h>
-#include <cpu/x86/lapic.h>
-#include <stdint.h>
-#include <string.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <southbridge/amd/agesa/hudson/hudson.h>
-
-static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
-{
- mc->mpc_length += length;
- mc->mpc_entry_count++;
-}
-
-static void my_smp_write_bus(struct mp_config_table *mc,
- unsigned char id, const char *bustype)
-{
- struct mpc_config_bus *mpc;
- mpc = smp_next_mpc_entry(mc);
- memset(mpc, '\0', sizeof(*mpc));
- mpc->mpc_type = MP_BUS;
- mpc->mpc_busid = id;
- memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
- smp_add_mpc_entry(mc, sizeof(*mpc));
-}
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
- memcpy(mc->mpc_oem, "AMD ", 8);
-
- smp_write_processors(mc);
-
- //mptable_write_buses(mc, NULL, &bus_isa);
- my_smp_write_bus(mc, 0, "PCI ");
- my_smp_write_bus(mc, 1, "PCI ");
- bus_isa = 0x02;
- my_smp_write_bus(mc, bus_isa, "ISA ");
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
-
- /* IOMMU */
- PCI_INT(0x0, 0x00, 0x0, 0x10);
- PCI_INT(0x0, 0x00, 0x1, 0x11);
- PCI_INT(0x0, 0x00, 0x2, 0x12);
- PCI_INT(0x0, 0x00, 0x3, 0x13);
-
- /* Internal VGA */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
- /* SMBUS */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
-
- /* HD Audio */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
- /* on board NIC & Slot PCIE. */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0. */
- PCI_INT(bus_pci, 0x5, 0x0, 0x14);
- PCI_INT(bus_pci, 0x5, 0x1, 0x15);
- PCI_INT(bus_pci, 0x5, 0x2, 0x16);
- PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_pci, 0x6, 0x0, 0x15);
- PCI_INT(bus_pci, 0x6, 0x1, 0x16);
- PCI_INT(bus_pci, 0x6, 0x2, 0x17);
- PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_pci, 0x7, 0x0, 0x16);
- PCI_INT(bus_pci, 0x7, 0x1, 0x17);
- PCI_INT(bus_pci, 0x7, 0x2, 0x14);
- PCI_INT(bus_pci, 0x7, 0x3, 0x15);
- }
-
- /* PCIe Lan*/
- PCI_INT(0x0, 0x06, 0x0, 0x13);
-
- /* FCH PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, 0x10);
- /* FCH PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, 0x11);
- /* FCH PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, 0x12);
- /* FCH PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, 0x13);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/lippert/frontrunner-af/Kconfig b/src/mainboard/lippert/frontrunner-af/Kconfig
index 4a007bf..64a8f14 100644
--- a/src/mainboard/lippert/frontrunner-af/Kconfig
+++ b/src/mainboard/lippert/frontrunner-af/Kconfig
@@ -27,7 +27,6 @@
select SUPERIO_SMSC_SMSCSUPERIO
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
# This erases 28 KB and writes 10 KB register dumps to SPI flash on every
# boot, wasting 3 s and causing wear! Therefore disable S3 for now.
#select HAVE_ACPI_RESUME
diff --git a/src/mainboard/lippert/frontrunner-af/mptable.c b/src/mainboard/lippert/frontrunner-af/mptable.c
deleted file mode 100644
index 78b8ec2..0000000
--- a/src/mainboard/lippert/frontrunner-af/mptable.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <string.h>
-#include <stdint.h>
-#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
- memcpy(mc->mpc_oem, "AMD ", 8);
-
- smp_write_processors(mc);
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
-
- /* APU Internal Graphic Device*/
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
- //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
- /* Southbridge HD Audio: */
- PCI_INT(0x0, 0x14, 0x2, 0x12);
-
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
- /* on board NIC & Slot PCIE. */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0. */
- PCI_INT(bus_pci, 0x5, 0x0, 0x14);
- PCI_INT(bus_pci, 0x5, 0x1, 0x15);
- PCI_INT(bus_pci, 0x5, 0x2, 0x16);
- PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_pci, 0x6, 0x0, 0x15);
- PCI_INT(bus_pci, 0x6, 0x1, 0x16);
- PCI_INT(bus_pci, 0x6, 0x2, 0x17);
- PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_pci, 0x7, 0x0, 0x16);
- PCI_INT(bus_pci, 0x7, 0x1, 0x17);
- PCI_INT(bus_pci, 0x7, 0x2, 0x14);
- PCI_INT(bus_pci, 0x7, 0x3, 0x15);
- }
-
- /* PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, 0x10);
- /* PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, 0x11);
- /* PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, 0x12);
- /* PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, 0x13);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/lippert/toucan-af/Kconfig b/src/mainboard/lippert/toucan-af/Kconfig
index b62da2e..e97099b 100644
--- a/src/mainboard/lippert/toucan-af/Kconfig
+++ b/src/mainboard/lippert/toucan-af/Kconfig
@@ -29,7 +29,6 @@
select SUPERIO_WINBOND_W83627DHG
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
# This erases 28 KB and writes 10 KB register dumps to SPI flash on every
# boot, wasting 3 s and causing wear! Therefore disable S3 for now.
#select HAVE_ACPI_RESUME
diff --git a/src/mainboard/lippert/toucan-af/mptable.c b/src/mainboard/lippert/toucan-af/mptable.c
deleted file mode 100644
index 78b8ec2..0000000
--- a/src/mainboard/lippert/toucan-af/mptable.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <string.h>
-#include <stdint.h>
-#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
- memcpy(mc->mpc_oem, "AMD ", 8);
-
- smp_write_processors(mc);
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
-
- /* APU Internal Graphic Device*/
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
- //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
- /* Southbridge HD Audio: */
- PCI_INT(0x0, 0x14, 0x2, 0x12);
-
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
- /* on board NIC & Slot PCIE. */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0. */
- PCI_INT(bus_pci, 0x5, 0x0, 0x14);
- PCI_INT(bus_pci, 0x5, 0x1, 0x15);
- PCI_INT(bus_pci, 0x5, 0x2, 0x16);
- PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_pci, 0x6, 0x0, 0x15);
- PCI_INT(bus_pci, 0x6, 0x1, 0x16);
- PCI_INT(bus_pci, 0x6, 0x2, 0x17);
- PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_pci, 0x7, 0x0, 0x16);
- PCI_INT(bus_pci, 0x7, 0x1, 0x17);
- PCI_INT(bus_pci, 0x7, 0x2, 0x14);
- PCI_INT(bus_pci, 0x7, 0x3, 0x15);
- }
-
- /* PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, 0x10);
- /* PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, 0x11);
- /* PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, 0x12);
- /* PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, 0x13);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/msi/ms7721/Kconfig b/src/mainboard/msi/ms7721/Kconfig
index 1fee747..b57bc48 100644
--- a/src/mainboard/msi/ms7721/Kconfig
+++ b/src/mainboard/msi/ms7721/Kconfig
@@ -25,7 +25,6 @@
select SOUTHBRIDGE_AMD_AGESA_HUDSON
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
select SUPERIO_FINTEK_F71869AD
select BOARD_ROMSIZE_KB_8192
diff --git a/src/mainboard/msi/ms7721/mptable.c b/src/mainboard/msi/ms7721/mptable.c
deleted file mode 100644
index fd55eda..0000000
--- a/src/mainboard/msi/ms7721/mptable.c
+++ /dev/null
@@ -1,150 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/ioapic.h>
-#include <arch/smp/mpspec.h>
-#include <cpu/x86/lapic.h>
-#include <stdint.h>
-#include <string.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <southbridge/amd/agesa/hudson/hudson.h>
-
-static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
-{
- mc->mpc_length += length;
- mc->mpc_entry_count++;
-}
-
-static void my_smp_write_bus(struct mp_config_table *mc,
- unsigned char id, const char *bustype)
-{
- struct mpc_config_bus *mpc;
- mpc = smp_next_mpc_entry(mc);
- memset(mpc, '\0', sizeof(*mpc));
- mpc->mpc_type = MP_BUS;
- mpc->mpc_busid = id;
- memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
- smp_add_mpc_entry(mc, sizeof(*mpc));
-}
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
- memcpy(mc->mpc_oem, "AMD ", 8);
-
- smp_write_processors(mc);
-
- //mptable_write_buses(mc, NULL, &bus_isa);
- my_smp_write_bus(mc, 0, "PCI ");
- my_smp_write_bus(mc, 1, "PCI ");
- bus_isa = 0x02;
- my_smp_write_bus(mc, bus_isa, "ISA ");
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
-
- /* IOMMU */
- PCI_INT(0x0, 0x0, 0x0, 0x10);
- PCI_INT(0x0, 0x0, 0x1, 0x11);
- PCI_INT(0x0, 0x0, 0x2, 0x12);
- PCI_INT(0x0, 0x0, 0x3, 0x13);
-
- /* Internal VGA */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
- /* SMBUS */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
-
- /* HD Audio */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
- /* on board NIC & Slot PCIE. */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0. */
- PCI_INT(bus_pci, 0x5, 0x0, 0x14);
- PCI_INT(bus_pci, 0x5, 0x1, 0x15);
- PCI_INT(bus_pci, 0x5, 0x2, 0x16);
- PCI_INT(bus_pci, 0x5, 0x3, 0x17);
- }
-
- /* PCIe Lan*/
- PCI_INT(0x0, 0x06, 0x0, 0x13);
-
- /* FCH PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, 0x10);
- /* FCH PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, 0x11);
- /* FCH PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, 0x12);
- /* FCH PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, 0x13);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig
index 3396845..9871051 100644
--- a/src/mainboard/pcengines/apu1/Kconfig
+++ b/src/mainboard/pcengines/apu1/Kconfig
@@ -23,7 +23,6 @@
select SOUTHBRIDGE_AMD_CIMX_SB800
select SUPERIO_NUVOTON_NCT5104D
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select HAVE_OPTION_TABLE
diff --git a/src/mainboard/pcengines/apu1/mptable.c b/src/mainboard/pcengines/apu1/mptable.c
deleted file mode 100644
index 89e5dfc..0000000
--- a/src/mainboard/pcengines/apu1/mptable.c
+++ /dev/null
@@ -1,133 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- * Copyright (C) 2014 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <stdint.h>
-#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <drivers/generic/ioapic/chip.h>
-#include <arch/ioapic.h>
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- /* Initialize the MP_Table */
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- /*
- * Type 0: Processor Entries:
- * LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
- * CPU Signature (Stepping, Model, Family),
- * Feature Flags
- */
- smp_write_processors(mc);
-
- /*
- * Type 1: Bus Entries:
- * Bus ID, Bus Type
- */
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /*
- * Type 2: I/O APICs:
- * APIC ID, Version, APIC Flags:EN, Address
- */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /*
- * Type 3: I/O Interrupt Table Entries:
- * Int Type, Int Polarity, Int Level, Source Bus ID,
- * Source Bus IRQ, Dest APIC ID, Dest PIN#
- */
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
-
- /* APU Internal Graphic Device */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]);
-
- /* SMBUS / ACPI */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]);
-
- /* Southbridge HD Audio */
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]);
-
- /* LPC */
- PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
- PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
- PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]);
- PCI_INT(0x0, 0x14, 0x5, intr_data_ptr[PIRQ_OHCI4]);
-
- /* IDE */
- PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_IDE]);
-
- /* SATA */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
-
- /* on board NIC & Slot PCIE */
- PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */
- PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */
- PCI_INT(0x3, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */
- PCI_INT(0x4, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */
-
- /* PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */
- /* PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */
- /* PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */
- /* PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
- IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig
index 8c713e5..604d490 100644
--- a/src/mainboard/pcengines/apu2/Kconfig
+++ b/src/mainboard/pcengines/apu2/Kconfig
@@ -26,7 +26,6 @@
select DEFAULT_POST_ON_LPC
select SUPERIO_NUVOTON_NCT5104D
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_8192
select USE_BLOBS
diff --git a/src/mainboard/pcengines/apu2/mptable.c b/src/mainboard/pcengines/apu2/mptable.c
deleted file mode 100644
index 772ee31..0000000
--- a/src/mainboard/pcengines/apu2/mptable.c
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- * Copyright (C) 2014 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <stdint.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /* Initialize the MP_Table */
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- /*
- * Type 0: Processor Entries:
- * LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
- * CPU Signature (Stepping, Model, Family),
- * Feature Flags
- */
- smp_write_processors(mc);
-
- /*
- * Type 1: Bus Entries:
- * Bus ID, Bus Type
- */
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /*
- * Type 2: I/O APICs:
- * APIC ID, Version, APIC Flags:EN, Address
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
- /*
- * Type 3: I/O Interrupt Table Entries:
- * Int Type, Int Polarity, Int Level, Source Bus ID,
- * Source Bus IRQ, Dest APIC ID, Dest PIN#
- */
-
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
-
-
- /* SMBUS / ACPI */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]);
-
- /* SD card */
- PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_SD]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[PIRQ_EHCI1]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[PIRQ_EHCI2]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[PIRQ_EHCI3]);
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_OHCI4]);
-
- /* SATA */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
-
- /* on board NIC & Slot PCIE */
- PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]);
- PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]);
-
-
- /* GPP0 */
- PCI_INT(0x0, 0x2, 0x0, 0x10); // Network 3
- /* GPP1 */
- PCI_INT(0x0, 0x2, 0x1, 0x11); // Network 2
- /* GPP2 */
- PCI_INT(0x0, 0x2, 0x2, 0x12); // Network 1
- /* GPP3 */
- PCI_INT(0x0, 0x2, 0x3, 0x13); // mPCI
- /* GPP4 */
- PCI_INT(0x0, 0x2, 0x4, 0x14); // mPCI
-
- IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
-
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */
- return (unsigned long)smp_write_config_table(v);
-}
--
To view, visit https://review.coreboot.org/c/coreboot/+/38313
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Idd13b8b006fce7383f3f73c3c0a5d51a71c0155b
Gerrit-Change-Number: 38313
Gerrit-PatchSet: 1
Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Gerrit-MessageType: newchange
2 days, 4 hours
- 4
- 19
Change in coreboot[master]: soc/intel/common: Add romstage common stage file
by Bernardo Perez Priego (Code Review)
Bernardo Perez Priego has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37628 )
Change subject: soc/intel/common: Add romstage common stage file
......................................................................
soc/intel/common: Add romstage common stage file
This patch will ensures all intel soc is using common stage
files to make coreboot design flow align across all socs.
CPU, SA, PCH, MCH programming sequence might be different between
socs but the function call should route from same location across
all soc.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com>
Change-Id: I06d43ac29f5e87ce731a470e5e145adea07ece4c
---
M src/cpu/intel/car/romstage.c
A src/soc/intel/common/basecode/include/intelbasecode/romstage.h
A src/soc/intel/common/basecode/romstage/Makefile.inc
A src/soc/intel/common/basecode/romstage/romstage.c
4 files changed, 162 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/37628/1
diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c
index 1f8eb9a..55d3c9d 100644
--- a/src/cpu/intel/car/romstage.c
+++ b/src/cpu/intel/car/romstage.c
@@ -52,9 +52,6 @@
for (i = 0; i < num_guards; i++)
stack_base[i] = stack_guard;
- if (CONFIG(VBOOT_EARLY_EC_SYNC))
- vboot_sync_ec();
-
mainboard_romstage_entry();
/* Check the stack. */
@@ -64,9 +61,6 @@
printk(BIOS_DEBUG, "Smashed stack detected in romstage!\n");
}
- if (CONFIG(SMM_TSEG))
- smm_list_regions();
-
prepare_and_run_postcar(&early_mtrrs);
/* We do not return here. */
}
diff --git a/src/soc/intel/common/basecode/include/intelbasecode/romstage.h b/src/soc/intel/common/basecode/include/intelbasecode/romstage.h
new file mode 100644
index 0000000..0cebbbf
--- /dev/null
+++ b/src/soc/intel/common/basecode/include/intelbasecode/romstage.h
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOC_INTEL_COMMON_BASECODE_ROMSTAGE_H
+#define SOC_INTEL_COMMON_BASECODE_ROMSTAGE_H
+
+#include <stddef.h>
+#include <stdint.h>
+#include <fsp/soc_binding.h>
+
+struct romstage_ops {
+ void (*soc_early_init)(void);
+ void (*soc_init)(void);
+ void (*pch_early_init)(void);
+ void (*pch_init)(void);
+ void (*cpu_early_init)(void);
+ void (*cpu_init)(void);
+ bool (*is_s3wake)(void);
+ void (*soc_mem_init_params)(FSP_M_CONFIG *mupd);
+};
+
+/* SoC Override function */
+struct romstage_ops *soc_get_ops(void);
+
+#endif
diff --git a/src/soc/intel/common/basecode/romstage/Makefile.inc b/src/soc/intel/common/basecode/romstage/Makefile.inc
new file mode 100644
index 0000000..29763fb
--- /dev/null
+++ b/src/soc/intel/common/basecode/romstage/Makefile.inc
@@ -0,0 +1 @@
+romstage-y += romstage.c
diff --git a/src/soc/intel/common/basecode/romstage/romstage.c b/src/soc/intel/common/basecode/romstage/romstage.c
new file mode 100644
index 0000000..55c4ab5
--- /dev/null
+++ b/src/soc/intel/common/basecode/romstage/romstage.c
@@ -0,0 +1,124 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/early_variables.h>
+#include <romstage_common.h>
+#include <cpu/x86/pae.h>
+#include <intelbasecode/romstage.h>
+#include <intelblocks/systemagent.h>
+#include <soc/iomap.h>
+#include <soc/romstage.h>
+
+static const struct romstage_ops s_romstage_ops;
+
+__weak struct romstage_ops *soc_get_ops(void)
+{
+ return (struct romstage_ops *)&s_romstage_ops;
+}
+
+void romstage_early_init(void)
+{
+ struct romstage_ops *rs_ops = soc_get_ops();
+
+ rs_ops->soc_early_init();
+ rs_ops->pch_early_init();
+ rs_ops->cpu_early_init();
+}
+
+void romstage_init(void)
+{
+ struct romstage_ops *rs_ops = soc_get_ops();
+
+ rs_ops->soc_init();
+ rs_ops->pch_init();
+ rs_ops->cpu_init();
+}
+
+void romstage_cmn_soc_early_init(void)
+{
+ systemagent_early_init();
+ heci_init(HECI1_BASE_ADDRESS);
+}
+
+void romstage_cmn_soc_init(void)
+{
+}
+
+void romstage_cmn_pch_early_init(void)
+{
+}
+
+void romstage_cmn_cpu_early_init(void)
+{
+}
+
+void romstage_cmn_pch_init(void)
+{
+}
+
+void romstage_cmn_cpu_init(void)
+{
+}
+
+bool romstage_cmn_is_s3wake(void)
+{
+ struct chipset_power_state *ps = pmc_get_power_state();
+ return pmc_fill_power_state(ps) == ACPI_S3;
+}
+
+void romstage_cmn_soc_mem_init_param(FSP_M_CONFIG *m_cfg)
+{
+}
+
+static const struct romstage_ops s_romstage_ops = {
+ &romstage_cmn_soc_early_init,
+ &romstage_cmn_soc_init,
+ &romstage_cmn_pch_early_init,
+ &romstage_cmn_pch_init,
+ &romstage_cmn_cpu_early_init,
+ &romstage_cmn_cpu_init,
+ &romstage_cmn_is_s3wake,
+ &romstage_cmn_mb_mem_init_param,
+ &romstage_cmn_soc_mem_init_param
+};
+
+/*
+ Main romstage function
+*/
+asmlinkage void mainboard_romstage_entry(void)
+{
+ if (CONFIG(VBOOT_EARLY_EC_SYNC))
+ vboot_sync_ec(rs_ops->fill_power_state());
+
+ romstage_early_init();
+ romstage_init();
+ fsp_memory_init(rs_ops->is_s3wake());
+
+ if (CONFIG(SMM_TSEG))
+ smm_list_regions();
+}
+
+/*
+ Callback function for FSP memory initialization
+*/
+void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
+{
+ struct romstage_ops *rs_ops = soc_get_ops();
+
+ FSP_M_CONFIG *m_cfg;
+ rs_ops->soc_mem_init_params(m_cfg);
+ mainboard_memory_init_params(m_cfg);
+}
+
--
To view, visit https://review.coreboot.org/c/coreboot/+/37628
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I06d43ac29f5e87ce731a470e5e145adea07ece4c
Gerrit-Change-Number: 37628
Gerrit-PatchSet: 1
Gerrit-Owner: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com>
Gerrit-MessageType: newchange
2 days, 8 hours
- 4
- 12
Change in coreboot[master]: mb/asus/p8z77-m: New board
by Keith Hui (Code Review)
Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38988 )
Change subject: mb/asus/p8z77-m: New board
......................................................................
mb/asus/p8z77-m: New board
Constructed out of a mix of autoport results, p8z77-m_pro, and
inteltool/superiotool dumps.
Does not yet boot. Submitting for eyeballs and help.
Change-Id: If756e791ddce747cb1706414be8e41e83f88922b
Signed-off-by: Keith Hui <buurin(a)gmail.com>
---
A src/mainboard/asus/p8z77-m/Kconfig
A src/mainboard/asus/p8z77-m/Kconfig.name
A src/mainboard/asus/p8z77-m/Makefile.inc
A src/mainboard/asus/p8z77-m/acpi/ec.asl
A src/mainboard/asus/p8z77-m/acpi/platform.asl
A src/mainboard/asus/p8z77-m/acpi/superio.asl
A src/mainboard/asus/p8z77-m/acpi_tables.c
A src/mainboard/asus/p8z77-m/cmos.default
A src/mainboard/asus/p8z77-m/cmos.layout
A src/mainboard/asus/p8z77-m/data.vbt
A src/mainboard/asus/p8z77-m/devicetree.cb
A src/mainboard/asus/p8z77-m/dsdt.asl
A src/mainboard/asus/p8z77-m/early_init.c
A src/mainboard/asus/p8z77-m/gma-mainboard.ads
A src/mainboard/asus/p8z77-m/gpio.c
A src/mainboard/asus/p8z77-m/hda_verb.c
A src/mainboard/asus/p8z77-m/mainboard.c
17 files changed, 969 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/38988/1
diff --git a/src/mainboard/asus/p8z77-m/Kconfig b/src/mainboard/asus/p8z77-m/Kconfig
new file mode 100644
index 0000000..260597d
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/Kconfig
@@ -0,0 +1,45 @@
+##
+## This file is part of the coreboot project.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+if BOARD_ASUS_P8Z77_M
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select BOARD_ROMSIZE_KB_8192
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select INTEL_INT15
+ select NORTHBRIDGE_INTEL_SANDYBRIDGE
+ select SERIRQ_CONTINUOUS_MODE
+ select SOUTHBRIDGE_INTEL_C216
+ select MAINBOARD_HAS_LPC_TPM
+ select MAINBOARD_HAS_TPM1
+ select HAVE_OPTION_TABLE
+ select HAVE_CMOS_DEFAULT
+ select MAINBOARD_HAS_LIBGFXINIT
+ select INTEL_GMA_HAVE_VBT
+ select SUPERIO_NUVOTON_NCT6779D
+
+config MAINBOARD_DIR
+ string
+ default "asus/p8z77-m"
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "P8Z77-M"
+
+config MAX_CPUS
+ int
+ default 8
+
+endif
diff --git a/src/mainboard/asus/p8z77-m/Kconfig.name b/src/mainboard/asus/p8z77-m/Kconfig.name
new file mode 100644
index 0000000..a797a5b
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/Kconfig.name
@@ -0,0 +1,15 @@
+##
+## This file is part of the coreboot project.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+config BOARD_ASUS_P8Z77_M
+ bool "P8Z77-M"
diff --git a/src/mainboard/asus/p8z77-m/Makefile.inc b/src/mainboard/asus/p8z77-m/Makefile.inc
new file mode 100644
index 0000000..a12efbb
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/Makefile.inc
@@ -0,0 +1,20 @@
+##
+## This file is part of the coreboot project.
+##
+## This program is free software: you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation, either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+bootblock-y += gpio.c
+romstage-y += gpio.c
+
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+bootblock-y += early_init.c
+romstage-y += early_init.c
diff --git a/src/mainboard/asus/p8z77-m/acpi/ec.asl b/src/mainboard/asus/p8z77-m/acpi/ec.asl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/acpi/ec.asl
diff --git a/src/mainboard/asus/p8z77-m/acpi/platform.asl b/src/mainboard/asus/p8z77-m/acpi/platform.asl
new file mode 100644
index 0000000..d2cad26
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/acpi/platform.asl
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* This file is part of the coreboot project. */
+
+Method(_WAK,1)
+{
+ Return(Package(){0,0})
+}
+
+Method(_PTS,1)
+{
+}
diff --git a/src/mainboard/asus/p8z77-m/acpi/superio.asl b/src/mainboard/asus/p8z77-m/acpi/superio.asl
new file mode 100644
index 0000000..f2b35ba
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/acpi/superio.asl
@@ -0,0 +1 @@
+#include <drivers/pc80/pc/ps2_controller.asl>
diff --git a/src/mainboard/asus/p8z77-m/acpi_tables.c b/src/mainboard/asus/p8z77-m/acpi_tables.c
new file mode 100644
index 0000000..9c22f19
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/acpi_tables.c
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Vlado Cibic <vladocb(a)protonmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/bd82x6x/nvs.h>
+
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+ /* critical temp that will shutdown the pc == 95C degrees */
+ gnvs->tcrt = 95;
+
+ /* temp to start throttling the cpu == 85C */
+ gnvs->tpsv = 85;
+}
diff --git a/src/mainboard/asus/p8z77-m/cmos.default b/src/mainboard/asus/p8z77-m/cmos.default
new file mode 100644
index 0000000..725ab98
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/cmos.default
@@ -0,0 +1,24 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2019 Vlado Cibic <vladocb(a)protonmail.com>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+boot_option=Fallback
+debug_level=Debug
+gfx_uma_size=224M
+nmi=Enable
+sata_mode=AHCI
+#usb3_xxxx options are only used with MRC blob, ignored else
+usb3_mode=Enable
+usb3_drv=Enable
+usb3_streams=Enable
diff --git a/src/mainboard/asus/p8z77-m/cmos.layout b/src/mainboard/asus/p8z77-m/cmos.layout
new file mode 100644
index 0000000..da29d1c
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/cmos.layout
@@ -0,0 +1,185 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2019 Vlado Cibic <vladocb(a)protonmail.com>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+# Status Register A
+# -----------------------------------------------------------------
+# Status Register B
+# -----------------------------------------------------------------
+# Status Register C
+#96 4 r 0 status_c_rsvd
+#100 1 r 0 uf_flag
+#101 1 r 0 af_flag
+#102 1 r 0 pf_flag
+#103 1 r 0 irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104 7 r 0 status_d_rsvd
+#111 1 r 0 valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112 8 r 0 diag_rsvd1
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+#120 264 r 0 unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 3 boot_option
+388 4 h 0 reboot_counter
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+#392 3 r 0 unused
+395 4 e 4 debug_level
+#399 1 r 0 unused
+#400 8 r 0 reserved for century byte
+
+# -----------------------------------------------------------------
+# coreboot config options: southbridge
+
+# Non Maskable Interrupt(NMI) support, which is an interrupt that may
+# occur on a RAM or unrecoverable error.
+408 1 e 1 nmi
+
+409 2 e 5 power_on_after_fail
+411 1 e 6 sata_mode
+
+# -----------------------------------------------------------------
+# coreboot config options: northbridge
+
+# gfx_uma_size
+# Quantity of shared video memory the IGP can use
+#
+416 5 e 7 gfx_uma_size
+
+# -----------------------------------------------------------------
+# coreboot config options: usb3
+
+# usb3_mode
+# Controls how the motherboard's USB3 ports act at boot time
+421 2 e 8 usb3_mode
+
+# usb3_drv
+# Load (or not) pre-OS xHCI USB3 bios driver
+#
+423 1 e 1 usb3_drv
+
+# usb3_streams
+# Streams can provide more speed (as they can use 64Kb packets),
+# but they might cause incompatibilities with some devices.
+#
+424 1 e 1 usb3_streams
+
+# -----------------------------------------------------------------
+# Sandy/Ivy Bridge MRC Scrambler Seed values
+# note: MUST NOT be covered by checksum!
+464 32 r 0 mrc_scrambler_seed
+496 32 r 0 mrc_scrambler_seed_s3
+528 16 r 0 mrc_scrambler_seed_chk
+
+# -----------------------------------------------------------------
+# coreboot config options: check sums
+544 16 h 0 check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+#ID value text
+
+# Generic on/off enum
+1 0 Disable
+1 1 Enable
+
+# boot_option
+3 0 Fallback
+3 1 Normal
+
+# debug_level
+4 0 Emergency
+4 1 Alert
+4 2 Critical
+4 3 Error
+4 4 Warning
+4 5 Notice
+4 6 Info
+4 7 Debug
+4 8 Spew
+
+# power_on_after_fail
+5 0 Disable
+5 1 Enable
+5 2 Keep
+
+# sata_mode
+6 0 AHCI
+6 1 Compatible
+
+# gfx_uma_size (Intel IGP Video RAM size)
+7 0 32M
+7 1 64M
+7 2 96M
+7 3 128M
+7 4 160M
+7 5 192M
+7 6 224M
+7 7 256M
+7 8 288M
+7 9 320M
+7 10 352M
+7 11 384M
+7 12 416M
+7 13 448M
+7 14 480M
+7 15 512M
+7 16 544M
+7 17 576M
+7 18 608M
+7 19 640M
+7 20 672M
+7 21 704M
+7 22 736M
+7 23 768M
+7 24 800M
+7 25 832M
+7 26 864M
+7 27 896M
+7 28 928M
+7 29 960M
+7 30 992M
+
+# usb3_mode
+# Disable = Use the port always as USB 2.0 for compatibility
+# Enable = Use the port always as USB 3.0 for speed
+# Auto = Initialize the port as USB 2.0, until the OS loads
+# xHCI USB 3.0 driver
+# SmartAuto = Same as Auto but, if the OS loads the xHCI USB 3.0 driver
+# and the computer is reset, keep the USB 3.0 mode.
+#
+8 0 Disable
+8 1 Enable
+8 2 Auto
+8 3 SmartAuto
+
+# -----------------------------------------------------------------
+# <startBit[must be byte-aligned]> <endBit[must be byte aligned]>
+# <bit where to start storing checksum[must be 16bits-aligned]>
+checksums
+
+checksum 392 431 544
diff --git a/src/mainboard/asus/p8z77-m/data.vbt b/src/mainboard/asus/p8z77-m/data.vbt
new file mode 100644
index 0000000..26ab42d
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/data.vbt
Binary files differ
diff --git a/src/mainboard/asus/p8z77-m/devicetree.cb b/src/mainboard/asus/p8z77-m/devicetree.cb
new file mode 100644
index 0000000..03a20b9
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/devicetree.cb
@@ -0,0 +1,108 @@
+##
+## This file is part of the coreboot project.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did
+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }"
+ register "gfx.ndid" = "3"
+ device cpu_cluster 0x0 on
+ chip cpu/intel/model_206ax
+ register "c1_acpower" = "1"
+ register "c1_battery" = "1"
+ register "c2_acpower" = "3"
+ register "c2_battery" = "3"
+ register "c3_acpower" = "5"
+ register "c3_battery" = "5"
+ device lapic 0x0 on end
+ device lapic 0xacac off end
+ end
+ end
+ device domain 0x0 on
+ subsystemid 0x1043 0x84ca inherit
+ device pci 00.0 on end # Host bridge
+ device pci 01.0 on end # PCIe Bridge for discrete graphics
+ device pci 02.0 on end # Internal graphics VGA controller
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+ register "c2_latency" = "0x0065"
+ register "gen1_dec" = "0x000c0291"
+ register "gen4_dec" = "0x00000000"
+ register "pcie_port_coalesce" = "1"
+ register "sata_interface_speed_support" = "0x3" # 0x3=SATAIII
+ register "sata_port_map" = "0x3f"
+ register "spi_lvscc" = "0x2005"
+ register "spi_uvscc" = "0x2005"
+ register "superspeed_capable_ports" = "0x0000000f"
+ register "xhci_overcurrent_mapping" = "0x00000c03"
+ register "xhci_switchable_ports" = "0x0000000f" # the 4 ports
+
+ device pci 14.0 on end # USB 3.0 Controller
+ device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT
+ device pci 19.0 off end # Intel Gigabit Ethernet
+ device pci 1a.0 on end # USB2 EHCI #2
+ device pci 1b.0 on end # High Definition Audio Audio controller
+ device pci 1c.0 on end # PCIe Port #1
+ device pci 1c.1 off end # PCIe Port #2
+ device pci 1c.2 off end # PCIe Port #3
+ device pci 1c.3 off end # PCIe Port #4
+ device pci 1c.4 off end # PCIe Port #5
+ device pci 1c.5 on end # PCIe Port #6
+ device pci 1c.6 on end # PCIe Port #7
+ device pci 1c.7 off end # PCIe Port #8
+ device pci 1d.0 on end # USB2 EHCI #1
+ device pci 1e.0 off end # PCI bridge
+ device pci 1f.0 on # LPC bridge PCI-LPC bridge
+ chip superio/nuvoton/nct6779d
+ device pnp 2e.1 off end # Parallel
+ device pnp 2e.2 on # UART A
+ io 0x60 = 0x3f8 # COM2 address
+ end
+ device pnp 2e.3 off end # UART B, IR
+ device pnp 2e.5 on # PS2 KBC
+ io 0x60 = 0x0060 # KBC1 base
+ io 0x62 = 0x0064 # KBC2 base
+ irq 0x70 = 1 # Keyboard IRQ
+ irq 0x72 = 12 # Mouse IRQ
+
+ # KBC 12Mhz/A20 speed/sw KBRST
+ drq 0xf0 = 0x82
+ end
+ device pnp 2e.6 off end # CIR
+ device pnp 2e.7 on end # GPIOs 6-8
+ device pnp 2e.8 off end # WDT1 GPIO 0-1
+ device pnp 2e.9 off end # GPIO 1-8
+ device pnp 2e.a on # ACPI
+ drq 0xe4 = 0x10 # Enable 3VSBS to power RAM on S3
+ drq 0xe7 = 0x10 # 0.5s S3 delay for compatibility
+ end
+ device pnp 2e.b off end # HWM, LED
+ device pnp 2e.d off end # WDT1
+ device pnp 2e.e off end # CIR wake-up
+ device pnp 2e.f on # GPIO PP/OD
+ drq 0xe6 = 0x7f # GP7 PP
+ end
+ device pnp 2e.14 on end # Port 80 UART
+ device pnp 2e.16 off end # Deep sleep
+ end
+ chip drivers/pc80/tpm
+ device pnp 4e.0 on end # TPM
+ end
+ end
+ device pci 1f.2 on end # SATA Controller 1
+ device pci 1f.3 on end # SMBus
+ device pci 1f.5 off end # SATA Controller 2
+ device pci 1f.6 off end # Thermal
+ end
+ end
+end
diff --git a/src/mainboard/asus/p8z77-m/dsdt.asl b/src/mainboard/asus/p8z77-m/dsdt.asl
new file mode 100644
index 0000000..62d44ea
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/dsdt.asl
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Vlado Cibic <vladocb(a)protonmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
+
+#include <arch/acpi.h>
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, /* DSDT revision: ACPI 2.0 and up */
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20141018 /* OEM revision */
+)
+{
+ #include "acpi/platform.asl"
+ #include "acpi/superio.asl"
+ #include <cpu/intel/common/acpi/cpu.asl>
+ #include <southbridge/intel/common/acpi/platform.asl>
+
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
+
+ Device (\_SB.PCI0)
+ {
+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
+ }
+}
diff --git a/src/mainboard/asus/p8z77-m/early_init.c b/src/mainboard/asus/p8z77-m/early_init.c
new file mode 100644
index 0000000..52c0e03
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/early_init.c
@@ -0,0 +1,197 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <bootblock_common.h>
+#include <device/pnp_ops.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <arch/io.h>
+#include <device/pnp.h>
+#include <stdint.h>
+
+#include <superio/nuvoton/common/nuvoton.h>
+#include <superio/nuvoton/nct6779d/nct6779d.h>
+
+#include <option.h>
+
+#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <northbridge/intel/sandybridge/raminit.h>
+#include <northbridge/intel/sandybridge/pei_data.h>
+
+#define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1)
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+ /* {enable, current, oc_pin} */
+ { 1, 2, 0 }, /* Port 0: USB3 front internal header, top */
+ { 1, 2, 0 }, /* Port 1: USB3 front internal header, bottom */
+ { 1, 2, 1 }, /* Port 2: USB3 rear, ETH top */
+ { 1, 2, 1 }, /* Port 3: USB3 rear, ETH bottom */
+ { 1, 2, 2 }, /* Port 4: USB2 rear, PS2 top */
+ { 1, 2, 2 }, /* Port 5: USB2 rear, PS2 bottom */
+ { 1, 2, 3 }, /* Port 6: USB2 internal header USB78, top */
+ { 1, 2, 3 }, /* Port 7: USB2 internal header USB78, bottom */
+ { 1, 2, 4 }, /* Port 8: USB2 internal header USB910, top */
+ { 1, 2, 4 }, /* Port 9: USB2 internal header USB910, bottom */
+ { 1, 2, 6 }, /* Port 10: USB2 internal header USB1112, top */
+ { 1, 2, 5 }, /* Port 11: USB2 internal header USB1112, bottom */
+ { 0, 2, 5 }, /* Port 12: Unused. Asus proprietary DEBUG_PORT ??? */
+ { 0, 2, 6 } /* Port 13: Unused. Asus proprietary DEBUG_PORT ??? */
+};
+
+/* Global config register values. */
+static const u8 register_values[] = {
+ /*
+ * Before accessing CR10, CR11, CR13 and CR14, CR26 [Bit4] must be set to logic 1.
+ * - NCT6779D datasheet, page 293
+ */
+ /* reg, value */
+ 0x26, (1 << 4),
+ 0x13, 0xff, /* IRQs 0-15 active low */
+ 0x14, 0xff,
+ 0x1b, 0x60,
+ 0x22, 0xdf, /* Power down UART B */
+ 0x2a, 0x48, /* UART A instead of GPIO8x */
+ 0x2c, 0x00, /* PECI */
+};
+
+void bootblock_mainboard_early_init(void)
+{
+ int max = ARRAY_SIZE(register_values);
+ int i;
+
+ nuvoton_pnp_enter_conf_state(SERIAL_DEV);
+
+ /* Set registers as specified in the register_values[] array. */
+ for (i = 0; i < max; i += 2)
+ pnp_write_config(SERIAL_DEV, register_values[i], register_values[i + 1]);
+
+ pnp_set_logical_device(SERIAL_DEV);
+ pnp_set_enable(SERIAL_DEV, 0);
+ pnp_set_iobase(SERIAL_DEV, PNP_IDX_IO0, CONFIG_TTYS0_BASE);
+ pnp_set_enable(SERIAL_DEV, 1);
+ nuvoton_pnp_exit_conf_state(SERIAL_DEV);
+}
+
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+{
+ read_spd(&spd[0], 0x50, id_only);
+ read_spd(&spd[1], 0x51, id_only);
+ read_spd(&spd[2], 0x52, id_only);
+ read_spd(&spd[3], 0x53, id_only);
+}
+
+int mainboard_should_reset_usb(int s3resume)
+{
+ return !s3resume;
+}
+
+void mainboard_fill_pei_data(struct pei_data *pei_data)
+{
+ /*
+ * USB3 mode:
+ * 0 = Disable: work always as USB 2.0(ehci)
+ * 1 = Enable: work always as USB 3.0(xhci)
+ * 2 = Auto: work as USB2.0(ehci) until OS loads USB3 xhci driver
+ * 3 = Smart Auto : same than Auto, but if OS loads USB3 driver
+ * and reboots, it will keep the USB3.0 speed
+ */
+ int usb3_mode = 1;
+ get_option(&usb3_mode, "usb3_mode");
+ usb3_mode &= 0x3; /* ensure it's 0/1/2/3 only */
+
+ /* Load USB3 pre-OS xHCI driver */
+ int usb3_drv = 1;
+ get_option(&usb3_drv, "usb3_drv");
+ usb3_drv &= 0x1; /* ensure it's 0/1 only */
+
+ /* Use USB3 xHCI streams */
+ int usb3_streams = 1;
+ get_option(&usb3_streams, "usb3_streams");
+ usb3_streams &= 0x1; /* ensure it's 0/1 only */
+
+ struct pei_data pd = {
+ .pei_version = PEI_VERSION,
+ .mchbar = (uintptr_t)DEFAULT_MCHBAR,
+ .dmibar = (uintptr_t)DEFAULT_DMIBAR,
+ .epbar = DEFAULT_EPBAR,
+ .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
+ .smbusbar = SMBUS_IO_BASE,
+ .wdbbar = 0x4000000,
+ .wdbsize = 0x1000,
+ .hpet_address = CONFIG_HPET_ADDRESS,
+ .rcba = (uintptr_t)DEFAULT_RCBABASE,
+ .pmbase = DEFAULT_PMBASE,
+ .gpiobase = DEFAULT_GPIOBASE,
+ .thermalbase = 0xfed08000,
+ .system_type = 1, /* 0=Mobile, 1=Desktop/Server */
+ .tseg_size = CONFIG_SMM_TSEG_SIZE,
+ .spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 }, /* SMBus mul 2 */
+ .ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
+ .ec_present = 0, /* Asus 2203 bios shows XUECA016, but no EC */
+ .gbe_enable = 0, /* Board uses no Intel GbE but a RTL8111F */
+ .dimm_channel0_disabled = 0, /* Both DIMM enabled */
+ .dimm_channel1_disabled = 0, /* Both DIMM enabled */
+ .max_ddr3_freq = 1600, /* 1333=Sandy; 1600=Ivy */
+ .usb_port_config = {
+ /* {enabled, oc_pin, cable len 0x0080=<8inches/20cm} */
+ { 1, 0, 0x0080 }, /* USB3 front internal header */
+ { 1, 0, 0x0080 }, /* USB3 front internal header */
+ { 1, 1, 0x0080 }, /* USB3 ETH top connector */
+ { 1, 1, 0x0080 }, /* USB3 ETH botton connector */
+ { 1, 2, 0x0080 }, /* USB2 PS2 top connector */
+ { 1, 2, 0x0080 }, /* USB2 PS2 botton connector */
+ { 1, 3, 0x0080 }, /* USB2 internal header (USB78) */
+ { 1, 3, 0x0080 }, /* USB2 internal header (USB78) */
+ { 1, 4, 0x0080 }, /* USB2 internal header (USB910) */
+ { 1, 4, 0x0080 }, /* USB2 internal header (USB910) */
+ { 1, 6, 0x0080 }, /* USB2 internal header (USB1112) */
+ { 1, 5, 0x0080 }, /* USB2 internal header (USB1112) */
+ { 0, 5, 0x0080 }, /* Unused. Asus DEBUG_PORT ??? */
+ { 0, 6, 0x0080 } /* Unused. Asus DEBUG_PORT ??? */
+ },
+ .usb3 = {
+ /* 0=Disable; 1=Enable (start at USB3 speed)
+ * 2=Auto (start as USB2 speed until OS loads)
+ * 3=Smart Auto (like Auto but keep speed on reboot)
+ */
+ usb3_mode,
+ /* 4 bit switch mask. 0=not switchable, 1=switchable
+ * Means once it's loaded the OS, it can swap ports
+ * from/to EHCI/xHCI. Z77 has four USB3 ports, so 0xf
+ */
+ 0xf,
+ usb3_drv, /* 1=Load xHCI pre-OS drv */
+ /* 0=Don't use xHCI streams for better compatibility
+ * 1=use xHCI streams for better speed
+ */
+ usb3_streams
+ },
+ /* ASUS P8Z77-M Pro manual says 1.35v DIMMs are supported */
+ .ddr3lv_support = 1,
+ /* PCIe 3.0 support. As we use Ivy Bridge, let's enable it,
+ * but might cause some system instability !
+ */
+ .pcie_init = 1,
+ /* Command Rate. 0=Auto; 1=1N; 2=2N.
+ * Leave it always at Auto for compatibility & stability
+ */
+ .nmode = 0,
+ /* DDR refresh rate. 0=Auto based on DRAM's temperature;
+ * 1=Normal rate for speed; 2=Double rate for stability
+ */
+ .ddr_refresh_rate_config = 0
+ };
+
+ /* copy the data to output PEI */
+ *pei_data = pd;
+}
diff --git a/src/mainboard/asus/p8z77-m/gma-mainboard.ads b/src/mainboard/asus/p8z77-m/gma-mainboard.ads
new file mode 100644
index 0000000..d7afe73
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/gma-mainboard.ads
@@ -0,0 +1,34 @@
+--
+-- This file is part of the coreboot project.
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ -- FIXME: check this
+ ports : constant Port_List :=
+ (DP1,
+ DP2,
+ DP3,
+ HDMI1,
+ HDMI2,
+ HDMI3,
+ Analog,
+ Internal);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/asus/p8z77-m/gpio.c b/src/mainboard/asus/p8z77-m/gpio.c
new file mode 100644
index 0000000..03e1507
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/gpio.c
@@ -0,0 +1,194 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio1 = GPIO_MODE_GPIO,
+ .gpio2 = GPIO_MODE_NATIVE,
+ .gpio3 = GPIO_MODE_NATIVE,
+ .gpio4 = GPIO_MODE_NATIVE,
+ .gpio5 = GPIO_MODE_NATIVE,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_NATIVE,
+ .gpio10 = GPIO_MODE_NATIVE,
+ .gpio11 = GPIO_MODE_NATIVE,
+ .gpio12 = GPIO_MODE_GPIO,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_NATIVE,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio16 = GPIO_MODE_GPIO,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_NATIVE,
+ .gpio19 = GPIO_MODE_NATIVE,
+ .gpio20 = GPIO_MODE_NATIVE,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_NATIVE,
+ .gpio23 = GPIO_MODE_NATIVE,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_NATIVE,
+ .gpio26 = GPIO_MODE_NATIVE,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_GPIO,
+ .gpio30 = GPIO_MODE_NATIVE,
+ .gpio31 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT,
+ .gpio1 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_OUTPUT,
+ .gpio12 = GPIO_DIR_OUTPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_OUTPUT,
+ .gpio16 = GPIO_DIR_INPUT,
+ .gpio17 = GPIO_DIR_INPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_OUTPUT,
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_OUTPUT,
+ .gpio29 = GPIO_DIR_OUTPUT,
+ .gpio31 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio8 = GPIO_LEVEL_HIGH,
+ .gpio12 = GPIO_LEVEL_LOW,
+ .gpio15 = GPIO_LEVEL_LOW,
+ .gpio24 = GPIO_LEVEL_LOW,
+ .gpio28 = GPIO_LEVEL_LOW,
+ .gpio29 = GPIO_LEVEL_HIGH,
+ .gpio31 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio1 = GPIO_INVERT,
+ .gpio13 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_GPIO,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_NATIVE,
+ .gpio36 = GPIO_MODE_NATIVE,
+ .gpio37 = GPIO_MODE_NATIVE,
+ .gpio38 = GPIO_MODE_NATIVE,
+ .gpio39 = GPIO_MODE_NATIVE,
+ .gpio40 = GPIO_MODE_NATIVE,
+ .gpio41 = GPIO_MODE_NATIVE,
+ .gpio42 = GPIO_MODE_NATIVE,
+ .gpio43 = GPIO_MODE_NATIVE,
+ .gpio44 = GPIO_MODE_NATIVE,
+ .gpio45 = GPIO_MODE_GPIO,
+ .gpio46 = GPIO_MODE_GPIO,
+ .gpio47 = GPIO_MODE_NATIVE,
+ .gpio48 = GPIO_MODE_NATIVE,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio50 = GPIO_MODE_NATIVE,
+ .gpio51 = GPIO_MODE_NATIVE,
+ .gpio52 = GPIO_MODE_NATIVE,
+ .gpio53 = GPIO_MODE_NATIVE,
+ .gpio54 = GPIO_MODE_NATIVE,
+ .gpio55 = GPIO_MODE_NATIVE,
+ .gpio56 = GPIO_MODE_NATIVE,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_NATIVE,
+ .gpio60 = GPIO_MODE_NATIVE,
+ .gpio61 = GPIO_MODE_NATIVE,
+ .gpio62 = GPIO_MODE_NATIVE,
+ .gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio32 = GPIO_DIR_OUTPUT,
+ .gpio33 = GPIO_DIR_OUTPUT,
+ .gpio34 = GPIO_DIR_INPUT,
+ .gpio45 = GPIO_DIR_INPUT,
+ .gpio46 = GPIO_DIR_INPUT,
+ .gpio49 = GPIO_DIR_INPUT,
+ .gpio57 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio32 = GPIO_LEVEL_HIGH,
+ .gpio33 = GPIO_LEVEL_HIGH,
+ .gpio57 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_NATIVE,
+ .gpio65 = GPIO_MODE_NATIVE,
+ .gpio66 = GPIO_MODE_NATIVE,
+ .gpio67 = GPIO_MODE_NATIVE,
+ .gpio68 = GPIO_MODE_GPIO,
+ .gpio69 = GPIO_MODE_GPIO,
+ .gpio70 = GPIO_MODE_NATIVE,
+ .gpio71 = GPIO_MODE_NATIVE,
+ .gpio72 = GPIO_MODE_GPIO,
+ .gpio73 = GPIO_MODE_NATIVE,
+ .gpio74 = GPIO_MODE_NATIVE,
+ .gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio68 = GPIO_DIR_INPUT,
+ .gpio69 = GPIO_DIR_INPUT,
+ .gpio72 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/asus/p8z77-m/hda_verb.c b/src/mainboard/asus/p8z77-m/hda_verb.c
new file mode 100644
index 0000000..f240025
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/hda_verb.c
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x10ec0887, /* Codec Vendor / Device ID: Realtek */
+ 0x104384a8, /* Subsystem ID */
+ 15, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(0, 0x104384a8),
+ AZALIA_PIN_CFG(0, 0x11, 0x90430130),
+ AZALIA_PIN_CFG(0, 0x12, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x14, 0x01014410),
+ AZALIA_PIN_CFG(0, 0x15, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x18, 0x01a19c50),
+ AZALIA_PIN_CFG(0, 0x19, 0x02a19c60),
+ AZALIA_PIN_CFG(0, 0x1a, 0x0181345f),
+ AZALIA_PIN_CFG(0, 0x1b, 0x02214c20),
+ AZALIA_PIN_CFG(0, 0x1c, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x1d, 0x4016c629),
+ AZALIA_PIN_CFG(0, 0x1e, 0x01446140),
+ AZALIA_PIN_CFG(0, 0x1f, 0x411111f0),
+
+ 0x80862806, /* Codec Vendor / Device ID: Intel */
+ 0x80860101, /* Subsystem ID */
+ 4, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(3, 0x80860101),
+ AZALIA_PIN_CFG(3, 0x05, 0x58560010),
+ AZALIA_PIN_CFG(3, 0x06, 0x58560020),
+ AZALIA_PIN_CFG(3, 0x07, 0x18560030),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/asus/p8z77-m/mainboard.c b/src/mainboard/asus/p8z77-m/mainboard.c
new file mode 100644
index 0000000..b97b648
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/mainboard.c
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* This file is part of the coreboot project. */
+
+#include <device/device.h>
+#include <drivers/intel/gma/int15.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+static void mainboard_enable(struct device *dev)
+{
+ /* FIXME: fix those values*/
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
+ GMA_INT15_PANEL_FIT_DEFAULT,
+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
--
To view, visit https://review.coreboot.org/c/coreboot/+/38988
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: If756e791ddce747cb1706414be8e41e83f88922b
Gerrit-Change-Number: 38988
Gerrit-PatchSet: 1
Gerrit-Owner: Keith Hui <buurin(a)gmail.com>
Gerrit-MessageType: newchange
4 days, 15 hours
- 6
- 40
Change in coreboot[master]: inteltool: gemini lake gpio support + UHD 605 graphics detection
by Name of user not set (Code Review)
coreboot(a)s.paape.io has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36033 )
Change subject: inteltool: gemini lake gpio support + UHD 605 graphics detection
......................................................................
inteltool: gemini lake gpio support + UHD 605 graphics detection
Signed-off-by: lead4good <coreboot(a)s.paape.io>
Change-Id: If8b04e58359bb8ff17318f86b6d9a57def94a401
---
M util/inteltool/gpio.c
M util/inteltool/gpio_groups.c
M util/inteltool/inteltool.c
M util/inteltool/inteltool.h
M util/inteltool/pcr.c
5 files changed, 317 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/36033/1
diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c
index efeab56..da4eadd 100644
--- a/util/inteltool/gpio.c
+++ b/util/inteltool/gpio.c
@@ -1035,6 +1035,7 @@
case PCI_DEVICE_ID_INTEL_QM170:
case PCI_DEVICE_ID_INTEL_HM170:
case PCI_DEVICE_ID_INTEL_CM236:
+ case PCI_DEVICE_ID_INTEL_GLK:
case PCI_DEVICE_ID_INTEL_APL_LPC:
case PCI_DEVICE_ID_INTEL_DNV_LPC:
case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE:
diff --git a/util/inteltool/gpio_groups.c b/util/inteltool/gpio_groups.c
index 321cf97..cc1d99e 100644
--- a/util/inteltool/gpio_groups.c
+++ b/util/inteltool/gpio_groups.c
@@ -45,6 +45,310 @@
* (if it's the first column, GPIO is the default, no matter the name)
*/
+static const char *const glk_group_northwest_names[] = {
+ "GPIO_0", "JTAG_TCK", "n/a", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_1", "JTAG_TRST_N", "n/a", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_2", "JTAG_TMS", "n/a", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_3", "JTAG_TDI", "n/a", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_4", "JTAG_TDO", "n/a", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_5", "JTAGX", "n/a", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_6", "JTAG_PREQ_N", "n/a", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_7", "JTAG_PRDY_N", "n/a", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_8", "n/a", "n/a", "CNV_DEBUG_09", "CNV_DEBUG_00", "n/a", "n/a",
+ "GPIO_9", "n/a", "n/a", "CNV_DEBUG_10", "CNV_DEBUG_01", "n/a", "n/a",
+ "GPIO_10", "n/a", "n/a", "CNV_DEBUG_11", "CNV_DEBUG_02", "n/a", "n/a",
+ "GPIO_11", "n/a", "n/a", "CNV_DEBUG_12", "CNV_DEBUG_03", "n/a", "n/a",
+ "GPIO_12", "n/a", "n/a", "CNV_DEBUG_13", "CNV_DEBUG_04", "n/a", "n/a",
+ "GPIO_13", "n/a", "n/a", "CNV_DEBUG_14", "CNV_DEBUG_05", "n/a", "n/a",
+ "GPIO_14", "n/a", "n/a", "CNV_DEBUG_15", "CNV_DEBUG_06", "n/a", "n/a",
+ "GPIO_15", "n/a", "n/a", "CNV_DEBUG_16", "CNV_DEBUG_07", "n/a", "n/a",
+ "GPIO_16", "n/a", "n/a", "CNV_DEBUG_17", "CNV_DEBUG_08", "n/a", "n/a",
+ "GPIO_17", "n/a", "CNV_MFUART0_RXD", "CNV_DEBUG_00", "n/a", "n/a", "n/a",
+ "GPIO_18", "n/a", "CNV_MFUART0_TXD", "CNV_DEBUG_01", "n/a", "n/a", "n/a",
+ "GPIO_19", "n/a", "CNV_MFUART0_RTS_N", "CNV_DEBUG_02", "n/a", "n/a", "n/a",
+ "GPIO_20", "n/a", "CNV_MFUART0_CTS_N", "CNV_DEBUG_03", "n/a", "n/a", "n/a",
+ "GPIO_21", "n/a", "CNV_MFUART2_RXD", "CNV_DEBUG_04", "n/a", "n/a", "n/a",
+ "GPIO_22", "n/a", "CNV_MFUART2_TXD", "CNV_DEBUG_05", "n/a", "n/a", "n/a",
+ "GPIO_23", "n/a", "CNV_GNSS_PA_BLANKING", "CNV_DEBUG_06", "PMIC_STDBY", "n/a", "n/a",
+ "GPIO_24", "n/a", "CNV_GNSS_FTA", "CNV_DEBUG_07", "PMIC_PWRGOOD", "n/a", "n/a",
+ "GPIO_25", "n/a", "CNV_GNSS_SYSCK", "CNV_DEBUG_08", "PMIC_RESET_N", "n/a", "n/a",
+ "GPIO_26", "n/a", "SIO_UART1_RXD", "ISH_UART1_RXD", "CNV_BT_UART_RXD", "n/a", "n/a",
+ "GPIO_27", "n/a", "SIO_UART1_TXD", "ISH_UART1_TXD", "CNV_BT_UART_TXD", "n/a", "n/a",
+ "GPIO_28", "n/a", "SIO_UART1_RTS_N", "ISH_UART1_RTS_N", "CNV_BT_UART_RTS_N", "n/a", "n/a",
+ "GPIO_29", "n/a", "SIO_UART1_CTS_N", "ISH_UART1_CTS_N", "CNV_BT_UART_CTS_N", "n/a", "n/a",
+ "GPIO_30", "n/a", "SATA_GP0", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_31", "n/a", "SATA_GP1", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_32", "n/a", "SATA_DE_VSLP0", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_33", "n/a", "SATA_DE_VSLP1", "SUSCLK1", "n/a", "n/a", "n/a",
+ "GPIO_34", "n/a", "SATA_LEDN", "SUSCLK2", "n/a", "n/a", "n/a",
+ "GPIO_35", "n/a", "n/a", "n/a", "SPKR", "n/a", "BSSB_CLK",
+ "GPIO_36", "n/a", "n/a", "CNV_BTEN", "n/a", "n/a", "BSSB_DI",
+ "GPIO_37", "n/a", "n/a", "CNV_GNEN", "n/a", "n/a", "n/a",
+ "GPIO_38", "n/a", "n/a", "CNV_WFEN", "n/a", "n/a", "n/a",
+ "GPIO_39", "n/a", "n/a", "CNV_WCEN", "n/a", "n/a", "n/a",
+ "GPIO_40", "n/a", "n/a", "CNVBT_HOST_WAKE_N", "n/a", "n/a", "n/a",
+ "GPIO_41", "n/a", "n/a", "CNV_GNSS_HOST_WAKE_N", "n/a", "n/a", "n/a",
+ "GPIO_42", "MDSI_A_TE", "PWM0", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_43", "MDSI_C_TE", "PWM1", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_44", "USB2_OC0_N", "PWM2", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_45", "USB2_OC1_N", "PWM3", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_46", "MIPI_I2C_SDA", "n/a", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_47", "MIPI_I2C_SCL", "n/a", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_48", "PMC_I2C_SDA", "n/a", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_49", "PMC_I2C_SCL", "n/a", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_50", "SIO_I2C0_SDA", "n/a", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_51", "SIO_I2C0_SCL", "n/a", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_52", "SIO_I2C1_SDA", "n/a", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_53", "SIO_I2C1_SCL", "n/a", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_54", "SIO_I2C2_SDA", "n/a", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_55", "SIO_I2C2_SCL", "n/a", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_56", "SIO_I2C3_SDA", "n/a", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_57", "SIO_I2C3_SCL", "n/a", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_58", "SIO_I2C4_SDA", "n/a", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_59", "SIO_I2C4_SCL", "n/a", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_60", "SIO_UART0_RXD", "ISH_UART0_RXD", "CNV_GNSS_UART_RXD", "n/a", "n/a", "n/a",
+ "GPIO_61", "SIO_UART0_TXD", "ISH_UART0_TXD", "CNV_GNSS_UART_TXD", "n/a", "n/a", "n/a",
+ "GPIO_62", "SIO_UART0_RTS_N", "ISH_UART0_RTS_N", "CNV_GNSS_UART_RTS_N", "n/a", "n/a", "n/a",
+ "GPIO_63", "SIO_UART0_CTS_N", "ISH_UART0_CTS_N", "CNV_GNSS_UART_CTS_N", "n/a", "n/a", "n/a",
+ "GPIO_64", "SIO_UART2_RXD", "ISH_UART2_RXD", "CNV_MFUART1_RXD", "n/a", "n/a", "n/a",
+ "GPIO_65", "SIO_UART2_TXD", "ISH_UART2_TXD", "CNV_MFUART1_TXD", "n/a", "n/a", "n/a",
+ "GPIO_66", "SIO_UART2_RTS_N", "ISH_UART2_RTS_N", "CNV_MFUART1_RTS_N", "n/a", "n/a", "n/a",
+ "GPIO_67", "SIO_UART2_CTS_N", "ISH_UART2_CTS_N", "CNV_MFUART1_CTS_N", "n/a", "n/a", "n/a",
+ "GPIO_68", "PMC_SPI_FS0", "n/a", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_69", "PMC_SPI_FS1", "n/a", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_70", "PMC_SPI_FS2", "n/a", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_71", "PMC_SPI_RXD", "n/a", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_72", "PMC_SPI_TXD", "n/a", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_73", "PMC_SPI_CLK", "n/a", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_74", "THERMTRIP_N", "n/a", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_75", "PROCHOT_N", "n/a", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_211","EMMC_RST_N", "n/a", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_212", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_213", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_214", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a",
+};
+
+static const struct gpio_group glk_group_northwest = {
+ .display = "------- GPIO Group NorthWest -------",
+ .pad_count = ARRAY_SIZE(glk_group_northwest_names) / 7,
+ .func_count = 7,
+ .pad_names = glk_group_northwest_names,
+};
+
+static const struct gpio_group *const glk_community_northwest_groups[] = {
+ &glk_group_northwest,
+};
+
+static const struct gpio_community glk_community_northwest = {
+ .name = "----- GPIO Community NorthWest -----",
+ .pcr_port_id = 0xc4,
+ .group_count = ARRAY_SIZE(glk_community_northwest_groups),
+ .groups = glk_community_northwest_groups,
+};
+
+static const char *const glk_group_north_names[] = {
+ "GPIO_76", "SVID0_ALERT_N", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_77", "SVID0_DATA", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_78", "SVID0_CLK", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_79", "SIO_SPI_0_CLK", "ISH_SPI_0_CLK", "n/a", "n/a", "n/a",
+ "GPIO_80", "SIO_SPI_0_FS0", "ISH_SPI_0_FS0", "n/a", "n/a", "n/a",
+ "GPIO_81", "SIO_SPI_0_FS1", "ISH_SPI_0_FS1", "FST_SPI_CS2_N", "n/a", "n/a",
+ "GPIO_82", "SIO_SPI_0_RXD", "ISH_SPI_0_RXD", "n/a", "n/a", "n/a",
+ "GPIO_83", "SIO_SPI_0_TXD", "ISH_SPI_0_TXD", "n/a", "n/a", "n/a",
+ "GPIO_84", "SIO_SPI_2_CLK", "ISH_SPI_1_CLK", "TOUCH_SPI_CLK", "n/a", "n/a",
+ "GPIO_85", "SIO_SPI_2_FS0", "ISH_SPI_1_FS0", "TOUCH_SPI_FS0", "n/a", "n/a",
+ "GPIO_86", "SIO_SPI_2_FS1", "ISH_SPI_1_FS1", "TOUCH_SPI_D0", "n/a", "n/a",
+ "GPIO_87", "SIO_SPI_2_FS2", "n/a", "TOUCH_SPI_D1", "n/a", "n/a",
+ "GPIO_88", "SIO_SPI_2_RXD", "ISH_SPI_1_RXD", "TOUCH_SPI_D2", "n/a", "n/a",
+ "GPIO_89", "SIO_SPI_2_TXD", "ISH_SPI_0_TXD", "TOUCH_SPI_D3", "n/a", "n/a",
+ "GPIO_90", "FST_SPI_CS0_N", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_91", "FST_SPI_CS1_N", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_92", "FST_SPI_MOSI_IO0", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_93", "FST_SPI_MISO_IO1", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_94", "FST_SPI_IO2", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_95", "FST_SPI_IO3", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_96", "FST_SPI_CLK", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_97", "FST_SPI_CLK_FB", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_98", "PMU_PLTRST_N", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_99", "PMU_PWRBTN_N", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_100", "PMU_SLP_S0_N", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_101", "PMU_SLP_S3_N", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_102", "PMU_SLP_S4_N", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_103", "SUSPWRDNACK", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_104", "EMMC_PWR_EN_N", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_105", "n/a", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_106", "PMU_BATLOW_N", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_107", "PMU_RSTBTN_N", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_108", "PMU_SUSCLK", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_109", "SUS_STAT_N", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_110", "SIO_I2C5_SDA", "ISH_I2C0_SDA", "n/a", "n/a", "n/a",
+ "GPIO_111", "SIO_I2C5_SCL", "ISH_I2C0_SCL", "n/a", "n/a", "n/a",
+ "GPIO_112", "SIO_I2C6_SDA", "ISH_I2C1_SDA", "n/a", "n/a", "n/a",
+ "GPIO_113", "SIO_I2C6_SCL", "ISH_I2C1_ScL", "n/a", "n/a", "n/a",
+ "GPIO_114", "SIO_I2C7_SDA", "ISH_I2C2_SDA", "SUSCLK1", "n/a", "n/a",
+ "GPIO_115", "SIO_I2C7_SCL", "ISH_I2C2_SCL", "SUSCLK2", "n/a", "n/a",
+ "GPIO_116", "PCIE_WAKE0_N", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_117", "PCIE_WAKE1_N", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_118", "PCIE_WAKE2_N", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_119", "PCIE_WAKE3_N", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_120", "PCIE_CLKREQ0_N", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_121", "PCIE_CLKREQ1_N", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_122", "PCIE_CLKREQ2_N", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_123", "PCIE_CLKREQ3_N", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_124", "DDI0_DDC_SDA", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_125", "DDI0_DDC_SCL", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_126", "DDI1_DDC_SDA", "SIO_I2C5_SDA", "n/a", "n/a", "n/a",
+ "GPIO_127", "DDI1_DDC_SCL", "SIO_I2C5_SCL", "n/a", "n/a", "n/a",
+ "GPIO_128", "PNL0_VDDEN", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_129", "PNL0_BKLTEN", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_130", "PNL0_BKLCTL", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_131", "DDI0_HPD", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_132", "DDI1_HPD", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_133", "DDI2_HPD", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_134", "n/a", "n/a", "n/a", "ISH_GPIO_10", "n/a",
+ "GPIO_135", "n/a", "n/a", "n/a", "ISH_GPIO_11", "n/a",
+ "GPIO_136", "n/a", "n/a", "n/a", "ISH_GPIO_12", "n/a",
+ "GPIO_137", "n/a", "n/a", "n/a", "ISH_GPIO_13", "n/a",
+ "GPIO_138", "n/a", "SIO_UART3_RXD", "ISH_UART0_RXD", "ISH_GPIO_14", "SATA_GP0",
+ "GPIO_139", "n/a", "SIO_UART3_TXD", "ISH_UART0_TXD", "ISH_GPIO_15", "SATA_GP1",
+ "GPIO_140", "n/a", "SIO_UART3_RTS_N", "ISH_UART0_RTS_N", "n/a", "SATA_DEVSLP0",
+ "GPIO_141", "n/a", "SIO_UART3_CTS_N", "ISH_UART0_CTS_N", "n/a", "SATA_DEVSLP1",
+ "GPIO_142", "n/a", "SIO_SPI_1_CLK", "ISH_SPI_0_CLK", "n/a", "SATA_LEDN",
+ "GPIO_143", "n/a", "SIO_SPI_1_FS0", "ISH_SPI_0_FS0", "JTAG2_TCK", "n/a",
+ "GPIO_144", "n/a", "SIO_SPI_1_FS1", "ISH_SPI_0_FS1", "PNL1_VDDEN", "n/a",
+ "GPIO_145", "n/a", "SIO_SPI_1_RXD", "ISH_SPI_0_RXD", "PNL1_BKLTEN", "n/a",
+ "GPIO_146", "n/a", "SIO_SPI_1_TXD", "ISH_SPI_0_TXD", "PNL1_BKLTCTL", "n/a",
+ "GPIO_147", "LPC_SERIRQ", "ESPI_RESET_N", "n/a", "n/a", "n/a",
+ "GPIO_148", "LPC_CLKOUT0", "ESPI_CLK", "n/a", "n/a", "n/a",
+ "GPIO_149", "LPC_CLKOUT1", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_150", "LPC_AD0", "ESPI_IO_0", "n/a", "n/a", "n/a",
+ "GPIO_151", "LPC_AD1", "ESPI_IO_1", "n/a", "n/a", "n/a",
+ "GPIO_152", "LPC_AD2", "ESPI_IO_2", "n/a", "n/a", "n/a",
+ "GPIO_153", "LPC_AD3", "ESPI_IO_3", "n/a", "n/a", "n/a",
+ "GPIO_154", "LPC_CLKRUN_N", "n/a", "n/a", "n/a", "n/a",
+ "GPIO_155", "LPC_FRAME_N", "ESPI_CS_N", "n/a", "n/a", "n/a",
+};
+
+static const struct gpio_group glk_group_north = {
+ .display = "----- GPIO Group North -----",
+ .pad_count = ARRAY_SIZE(glk_group_north_names) / 6,
+ .func_count = 6,
+ .pad_names = glk_group_north_names,
+};
+
+static const struct gpio_group *const glk_community_north_groups[] = {
+ &glk_group_north,
+};
+
+static const struct gpio_community glk_community_north = {
+ .name = "--- GPIO Community North ---",
+ .pcr_port_id = 0xc5,
+ .group_count = ARRAY_SIZE(glk_community_north_groups),
+ .groups = glk_community_north_groups,
+};
+
+static const char *const glk_group_audio_names[] = {
+ "GPIO_156", "AVS_I2S0_MCLK", "n/a", "n/a",
+ "GPIO_157", "AVS_I2S0_BCLK", "n/a", "n/a",
+ "GPIO_158", "AVS_I2S0_WS_SYNC", "n/a", "n/a",
+ "GPIO_159", "AVS_I2S0_SDI", "n/a", "n/a",
+ "GPIO_160", "AVS_I2S0_SDO", "n/a", "n/a",
+ "GPIO_161", "AVS_I2S1_MCLK", "n/a", "n/a",
+ "GPIO_162", "AVS_I2S1_BCLK", "n/a", "CNV_BT_I2S_BCLK",
+ "GPIO_163", "AVS_I2S1_WS_SYNC", "n/a", "CNV_BT_I2S_WS_SYNC",
+ "GPIO_164", "AVS_I2S1_SDI", "n/a", "CNV_BT_I2S_SDI",
+ "GPIO_165", "AVS_I2S1_SDO", "n/a", "CNV_BT_I2S_SDO",
+ "GPIO_166", "AVS_HDA_BCLK", "AVS_I2S2_BCLK", "n/a",
+ "GPIO_167", "AVS_HDA_WS_SYNC", "AVS_I2S2_WS_SYNC", "n/a",
+ "GPIO_168", "AVS_HDA_SDI", "AVS_I2S2_SDI", "n/a",
+ "GPIO_169", "AVS_HDA_SDO", "AVS_I2S2_SDO", "n/a",
+ "GPIO_170", "AVS_HDA_RST_N", "AVS_I2S1_MCLK", "n/a",
+ "GPIO_171", "AVS_DMIC_CLK_A1", "n/a", "n/a",
+ "GPIO_172", "AVS_DMIC_CLK_B1", "n/a", "n/a",
+ "GPIO_173", "AVS_DMIC_DATA_1", "n/a", "n/a",
+ "GPIO_174", "AVS_DMIC_CLK_AB2", "n/a", "n/a",
+ "GPIO_175", "AVS_DMIC_DATA_2", "n/a", "n/a",
+};
+
+static const struct gpio_group glk_group_audio = {
+ .display = "----- GPIO Group Audio -----",
+ .pad_count = ARRAY_SIZE(glk_group_audio_names) / 4,
+ .func_count = 4,
+ .pad_names = glk_group_audio_names,
+};
+
+static const struct gpio_group *const glk_community_audio_groups[] = {
+ &glk_group_audio,
+};
+
+static const struct gpio_community glk_community_audio = {
+ .name = "--- GPIO Community Audio ---",
+ .pcr_port_id = 0xc9,
+ .group_count = ARRAY_SIZE(glk_community_audio_groups),
+ .groups = glk_community_audio_groups,
+};
+
+static const char *const glk_group_scc_names[] = {
+ "GPIO_176", "SMB_ALERT_N", "n/a", "n/a",
+ "GPIO_177", "SMB_CLK", "SIO_I2C7_SCL", "n/a",
+ "GPIO_178", "SMB_DATA", "SIO_I2C7_SDA", "n/a",
+ "GPIO_187", "SDCARD_LVL_WP", "n/a", "n/a",
+ "GPIO_179", "SDCARD_CLK", "n/a", "n/a",
+ "GPIO_180", "SDCARD_CLK_FB", "n/a", "n/a",
+ "GPIO_181", "SDCARD_D0", "n/a", "n/a",
+ "GPIO_182", "SDCARD_D1", "n/a", "n/a",
+ "GPIO_183", "SDCARD_D2", "n/a", "n/a",
+ "GPIO_184", "SDCARD_D3", "n/a", "n/a",
+ "GPIO_185", "SDCARD_CMD", "n/a", "n/a",
+ "GPIO_186", "SDCARD_CD_N", "n/a", "n/a",
+ "GPIO_188", "SDCARD_PWR_DWN_N", "n/a", "n/a",
+ "GPIO_210", "n/a", "n/a", "n/a",
+ "GPIO_189", "OSC_CLK_OUT_0", "n/a", "n/a",
+ "GPIO_190", "OSC_CLK_OUT_1", "n/a", "n/a",
+ "GPIO_191", "CNV_BRI_DT", "n/a", "SIO_UART1_RTS_N",
+ "GPIO_192", "CNV_BRI_RST", "n/a", "SIO_UART1_RXD",
+ "GPIO_193", "CNV_RGI_DT", "n/a", "SIO_UART1_TXD",
+ "GPIO_194", "CNV_RGI_RST", "n/a", "SIO_UART1_CTS_N",
+ "GPIO_195", "CNV_RF_RESET_N", "n/a", "AVS_I2S1_WS_SYNC",
+ "GPIO_196", "XTAL_CLKREQ", "n/a", "AVS_I2S1_SDO",
+ "GPIO_197", "SDIO_CLK_FB", "n/a", "n/a",
+ "GPIO_198", "EMMC_CLK", "n/a", "n/a",
+ "GPIO_199", "EMMC_D0", "n/a", "n/a",
+ "GPIO_200", "EMMC_D1", "n/a", "n/a",
+ "GPIO_201", "EMMC_D2", "n/a", "n/a",
+ "GPIO_202", "EMMC_D3", "n/a", "n/a",
+ "GPIO_203", "EMMC_D4", "n/a", "n/a",
+ "GPIO_204", "EMMC_D5", "n/a", "n/a",
+ "GPIO_205", "EMMC_D6", "n/a", "n/a",
+ "GPIO_206", "EMMC_D7", "n/a", "n/a",
+ "GPIO_207", "EMMC_CMD", "n/a", "n/a",
+ "GPIO_208", "EMMC_RCLK", "n/a", "n/a",
+ "GPIO_209", "EMMC_RST_N", "n/a", "n/a",
+};
+
+static const struct gpio_group glk_group_scc = {
+ .display = "----- GPIO Group SCC -----",
+ .pad_count = ARRAY_SIZE(glk_group_scc_names) / 4,
+ .func_count = 4,
+ .pad_names = glk_group_scc_names,
+};
+
+static const struct gpio_group *const glk_community_scc_groups[] = {
+ &glk_group_scc,
+};
+
+static const struct gpio_community glk_community_scc = {
+ .name = "--- GPIO Community SCC ---",
+ .pcr_port_id = 0xc8,
+ .group_count = ARRAY_SIZE(glk_community_scc_groups),
+ .groups = glk_community_scc_groups,
+};
+
+static const struct gpio_community *const glk_communities[] = {
+ &glk_community_northwest, &glk_community_north,
+ &glk_community_audio, &glk_community_scc,
+};
+
static const char *const apl_group_north_names[] = {
"*GPIO_0", "n/a", "n/a", "n/a", "n/a", "n/a",
"*GPIO_1", "n/a", "n/a", "n/a", "n/a", "n/a",
@@ -2284,6 +2588,12 @@
communities = apl_communities;
pcr_init(sb);
break;
+ case PCI_DEVICE_ID_INTEL_GLK:
+ community_count = ARRAY_SIZE(glk_communities);
+ communities = glk_communities;
+ pad_stepping = 16;
+ pcr_init(sb);
+ break;
case PCI_DEVICE_ID_INTEL_H310:
case PCI_DEVICE_ID_INTEL_H370:
case PCI_DEVICE_ID_INTEL_Z390:
diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c
index db80bd2..5aa4592 100644
--- a/util/inteltool/inteltool.c
+++ b/util/inteltool/inteltool.c
@@ -300,6 +300,7 @@
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C224, "C224"},
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C226, "C226"},
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H81, "H81"},
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GLK, "Gemini Lake" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_APL_LPC, "Apollo Lake" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_LPC, "Denverton" },
/* Intel GPUs */
@@ -395,6 +396,8 @@
"Intel(R) HD Graphics 530" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HD_530_2,
"Intel(R) HD Graphics 530" },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UHD_605,
+ "Intel(R) UHD Graphics 605" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UHD_615_1,
"Intel(R) UHD Graphics 615" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UHD_615_2,
diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h
index fc6dc4b..9ad1a5f 100644
--- a/util/inteltool/inteltool.h
+++ b/util/inteltool/inteltool.h
@@ -264,6 +264,7 @@
#define PCI_DEVICE_ID_INTEL_BAYTRAIL_GFX 0x0f31
#define CPUID_BAYTRAIL 0x30670
+#define PCI_DEVICE_ID_INTEL_GLK 0x31e8
#define PCI_DEVICE_ID_INTEL_APL_LPC 0x5ae8
#define PCI_DEVICE_ID_INTEL_DNV_LPC 0x19dc
@@ -340,6 +341,7 @@
#define PCI_DEVICE_ID_INTEL_HD_520 0x1916
#define PCI_DEVICE_ID_INTEL_HD_530_1 0x191B
#define PCI_DEVICE_ID_INTEL_HD_530_2 0x1912
+#define PCI_DEVICE_ID_INTEL_UHD_605 0x3185
#define PCI_DEVICE_ID_INTEL_UHD_615_1 0x591C
#define PCI_DEVICE_ID_INTEL_UHD_615_2 0x591E
#define PCI_DEVICE_ID_INTEL_UHD_617 0x87C0
diff --git a/util/inteltool/pcr.c b/util/inteltool/pcr.c
index ef6bb39..fec7457 100644
--- a/util/inteltool/pcr.c
+++ b/util/inteltool/pcr.c
@@ -120,6 +120,7 @@
p2sb = pci_get_dev(sb->access, 0, 0, 0x1f, 1);
break;
case PCI_DEVICE_ID_INTEL_APL_LPC:
+ case PCI_DEVICE_ID_INTEL_GLK:
p2sb = pci_get_dev(sb->access, 0, 0, 0x0d, 0);
break;
case PCI_DEVICE_ID_INTEL_H310:
--
To view, visit https://review.coreboot.org/c/coreboot/+/36033
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: If8b04e58359bb8ff17318f86b6d9a57def94a401
Gerrit-Change-Number: 36033
Gerrit-PatchSet: 1
Gerrit-Owner: coreboot(a)s.paape.io
Gerrit-MessageType: newchange
5 days, 16 hours
- 5
- 10
Change in coreboot[master]: soc/intel/xeon_sp: add ACPI to control GPIO [WIP]
by Maxim Polyakov (Code Review)
Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39979 )
Change subject: soc/intel/xeon_sp: add ACPI to control GPIO [WIP]
......................................................................
soc/intel/xeon_sp: add ACPI to control GPIO [WIP]
Change-Id: I07c882077eb3c035faae81641bc860e69db224b4
Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com>
---
A src/soc/intel/xeon_sp/acpi/gpio.asl
1 file changed, 177 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/39979/1
diff --git a/src/soc/intel/xeon_sp/acpi/gpio.asl b/src/soc/intel/xeon_sp/acpi/gpio.asl
new file mode 100644
index 0000000..4a981b7
--- /dev/null
+++ b/src/soc/intel/xeon_sp/acpi/gpio.asl
@@ -0,0 +1,177 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+#include <soc/gpio.h>
+
+#define GPIOTXSTATE_MASK 0x1
+#define GPIORXSTATE_MASK 0x1
+
+Device (GPIO)
+{
+ Name (_HID, "INT3536")
+ Name (_UID, 1)
+ Name (_DDN, "GPIO Controller")
+
+ Name (RBUF, ResourceTemplate()
+ {
+ Memory32Fixed (ReadWrite, 0, 0, COM0)
+ Memory32Fixed (ReadWrite, 0, 0, COM1)
+ Memory32Fixed (ReadWrite, 0, 0, COM3)
+ Memory32Fixed (ReadWrite, 0, 0, COM4)
+ Memory32Fixed (ReadWrite, 0, 0, COM5)
+ Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ)
+ { 0 }
+ })
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ /* GPIO Community 0 */
+ CreateDWordField (^RBUF, ^COM0._BAS, BAS0)
+ CreateDWordField (^RBUF, ^COM0._LEN, LEN0)
+ Store (^^PCRB (PID_GPIOCOM0), BAS0)
+ Store (GPIO_BASE_SIZE, LEN0)
+
+ /* GPIO Community 1 */
+ CreateDWordField (^RBUF, ^COM1._BAS, BAS1)
+ CreateDWordField (^RBUF, ^COM1._LEN, LEN1)
+ Store (^^PCRB (PID_GPIOCOM1), BAS1)
+ Store (GPIO_BASE_SIZE, LEN1)
+
+ /* GPIO Community 3 */
+ CreateDWordField (^RBUF, ^COM3._BAS, BAS3)
+ CreateDWordField (^RBUF, ^COM3._LEN, LEN3)
+ Store (^^PCRB (PID_GPIOCOM3), BAS3)
+ Store (GPIO_BASE_SIZE, LEN3)
+
+ /* GPIO Community 4 */
+ CreateDWordField (^RBUF, ^COM4._BAS, BAS4)
+ CreateDWordField (^RBUF, ^COM4._LEN, LEN4)
+ Store (^^PCRB (PID_GPIOCOM4), BAS4)
+ Store (GPIO_BASE_SIZE, LEN4)
+
+ /* GPIO Community 5 */
+ CreateDWordField (^RBUF, ^COM5._BAS, BAS5)
+ CreateDWordField (^RBUF, ^COM5._LEN, LEN5)
+ Store (^^PCRB (PID_GPIOCOM5), BAS5)
+ Store (GPIO_BASE_SIZE, LEN5)
+
+ CreateDWordField (^RBUF, ^GIRQ._INT, IRQN)
+ And (^^PCRR (PID_GPIOCOM0, GPIO_MISCCFG),
+ GPIO_DRIVER_IRQ_ROUTE_MASK, Local0)
+
+ /* TODO: Check this!
+ If (LEqual (Local0, GPIO_DRIVER_IRQ_ROUTE_IRQ14)) {
+ Store (GPIO_IRQ14, IRQN)
+ } Else {
+ Store (GPIO_IRQ15, IRQN)
+ }
+ */
+
+ Return (RBUF)
+ }
+
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0xF)
+ }
+}
+
+/*
+ * Get GPIO DW0 Address
+ * Arg0 - GPIO Number
+ */
+Method (GADD, 1, NotSerialized)
+{
+ /* GPIO Community 0 */
+ If (LAnd (LGreaterEqual (Arg0, GPP_A0), LLessEqual (Arg0, GPP_F23)))
+ {
+ Store (PID_GPIOCOM0, Local0)
+ Subtract (Arg0, GPP_A0, Local1)
+ }
+ /* GPIO Community 1 */
+ If (LAnd (LGreaterEqual (Arg0, GPP_C0), LLessEqual (Arg0, GPP_H23)))
+ {
+ Store (PID_GPIOCOM1, Local0)
+ Subtract (Arg0, GPP_C0, Local1)
+ }
+ /* GPIO Community 3 */
+ If (LAnd (LGreaterEqual (Arg0, GPP_I0), LLessEqual (Arg0, GPP_I10)))
+ {
+ Store (PID_GPIOCOM3, Local0)
+ Subtract (Arg0, GPP_I0, Local1)
+ }
+ /* GPIO Community 4 */
+ If (LAnd (LGreaterEqual (Arg0, GPP_J0), LLessEqual (Arg0, GPP_K10)))
+ {
+ Store (PID_GPIOCOM4, Local0)
+ Subtract (Arg0, GPP_J0, Local1)
+ }
+ /* GPIO Community 5 */
+ If (LAnd (LGreaterEqual (Arg0, GPP_G0), LLessEqual (Arg0, GPP_L19)))
+ {
+ Store (PID_GPIOCOM5, Local0)
+ Subtract (Arg0, GPP_G0, Local1)
+ }
+ Store (PCRB (Local0), Local2)
+ Add (Local2, PAD_CFG_BASE, Local2)
+ Return (Add (Local2, Multiply (Local1, 8)))
+}
+
+/*
+ * Get GPIO Rx Value
+ * Arg0 - GPIO Number
+ */
+Method (GRXS, 1, Serialized)
+{
+ OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
+ Field (PREG, AnyAcc, NoLock, Preserve)
+ {
+ VAL0, 32
+ }
+ And (GPIORXSTATE_MASK, ShiftRight (VAL0, PAD_CFG0_RX_STATE_BIT), Local0)
+
+ Return (Local0)
+}
+
+/*
+ * Get GPIO Tx Value
+ * Arg0 - GPIO Number
+ */
+Method (GTXS, 1, Serialized)
+{
+ OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
+ Field (PREG, AnyAcc, NoLock, Preserve)
+ {
+ VAL0, 32
+ }
+ And (GPIOTXSTATE_MASK, ShiftRight (VAL0, PAD_CFG0_TX_STATE_BIT), Local0)
+
+ Return (Local0)
+}
+
+/*
+ * Set GPIO Tx Value
+ * Arg0 - GPIO Number
+ */
+Method (STXS, 1, Serialized)
+{
+ OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
+ Field (PREG, AnyAcc, NoLock, Preserve)
+ {
+ VAL0, 32
+ }
+ Or (GPIOTXSTATE_MASK, VAL0, VAL0)
+}
+
+/*
+ * Clear GPIO Tx Value
+ * Arg0 - GPIO Number
+ */
+Method (CTXS, 1, Serialized)
+{
+ OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
+ Field (PREG, AnyAcc, NoLock, Preserve)
+ {
+ VAL0, 32
+ }
+ And (Not (GPIOTXSTATE_MASK), VAL0, VAL0)
+}
--
To view, visit https://review.coreboot.org/c/coreboot/+/39979
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I07c882077eb3c035faae81641bc860e69db224b4
Gerrit-Change-Number: 39979
Gerrit-PatchSet: 1
Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com>
Gerrit-MessageType: newchange
1 week, 1 day
- 7
- 48
Change in coreboot[master]: mb/acer/aspire_vn7_572g: Adds support for an Acer laptop Adds initial...
by Benjamin Doron (Code Review)
Benjamin Doron has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35523 )
Change subject: mb/acer/aspire_vn7_572g: Adds support for an Acer laptop Adds initial, rudimentary support for Acer Aspire VN7-572G. May not boot correctly or at all. For testing purposes only.
......................................................................
mb/acer/aspire_vn7_572g: Adds support for an Acer laptop
Adds initial, rudimentary support for Acer Aspire VN7-572G. May not boot correctly or at all. For testing purposes only.
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6
Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com>
---
A src/mainboard/acer/Kconfig
A src/mainboard/acer/Kconfig.name
A src/mainboard/acer/aspire_vn7_572g/Kconfig
A src/mainboard/acer/aspire_vn7_572g/Kconfig.name
A src/mainboard/acer/aspire_vn7_572g/Makefile.inc
A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl
A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl
A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl
A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl
A src/mainboard/acer/aspire_vn7_572g/acpi_tables.c
A src/mainboard/acer/aspire_vn7_572g/board_info.txt
A src/mainboard/acer/aspire_vn7_572g/devicetree.cb
A src/mainboard/acer/aspire_vn7_572g/dsdt.asl
A src/mainboard/acer/aspire_vn7_572g/gpio.h
A src/mainboard/acer/aspire_vn7_572g/hda_verb.c
A src/mainboard/acer/aspire_vn7_572g/mainboard.c
A src/mainboard/acer/aspire_vn7_572g/ramstage.c
A src/mainboard/acer/aspire_vn7_572g/romstage.c
18 files changed, 1,282 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/1
diff --git a/src/mainboard/acer/Kconfig b/src/mainboard/acer/Kconfig
new file mode 100644
index 0000000..f56a2a2
--- /dev/null
+++ b/src/mainboard/acer/Kconfig
@@ -0,0 +1,16 @@
+if VENDOR_ACER
+
+choice
+ prompt "Mainboard model"
+
+source "src/mainboard/acer/*/Kconfig.name"
+
+endchoice
+
+source "src/mainboard/acer/*/Kconfig"
+
+config MAINBOARD_VENDOR
+ string "Mainboard Vendor"
+ default "Acer"
+
+endif # VENDOR_ACER
diff --git a/src/mainboard/acer/Kconfig.name b/src/mainboard/acer/Kconfig.name
new file mode 100644
index 0000000..bb177f9
--- /dev/null
+++ b/src/mainboard/acer/Kconfig.name
@@ -0,0 +1,2 @@
+config VENDOR_ACER
+ bool "Acer"
diff --git a/src/mainboard/acer/aspire_vn7_572g/Kconfig b/src/mainboard/acer/aspire_vn7_572g/Kconfig
new file mode 100644
index 0000000..4b3c127
--- /dev/null
+++ b/src/mainboard/acer/aspire_vn7_572g/Kconfig
@@ -0,0 +1,68 @@
+if BOARD_ACER_VN7_572G
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select SYSTEM_TYPE_LAPTOP
+ select BOARD_ROMSIZE_KB_8192
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+ select SOC_INTEL_SKYLAKE
+ select MAINBOARD_USES_FSP2_0
+ select SPD_READ_BY_WORD
+ select MAINBOARD_HAS_LPC_TPM
+ select NO_POST # This platform has no way to see POST codes so disable them by default.
+
+config IRQ_SLOT_COUNT
+ int
+ default 18
+
+config MAINBOARD_VENDOR
+ string
+ default "Acer"
+
+config MAINBOARD_FAMILY
+ string
+ default "Aspire V Nitro"
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "Aspire VN7-572G"
+
+config MAINBOARD_DIR
+ string
+ default "acer/aspire_vn7_572g"
+
+config DEVICETREE
+ string
+ default "devicetree.cb"
+
+config MAX_CPUS
+ int
+ default 4
+
+config VGA_BIOS_ID
+ string
+ default "8086,1916"
+
+config DIMM_MAX
+ int
+ default 2
+
+config DIMM_SPD_SIZE
+ int
+ default 512
+
+config CPU_MICROCODE_CBFS_LEN
+ hex
+ default 0x18000
+
+config CPU_MICROCODE_CBFS_LOC
+ hex
+ default 0xFFE115A0
+
+config CBFS_SIZE
+ hex
+ default 0x5c0000
+
+endif
diff --git a/src/mainboard/acer/aspire_vn7_572g/Kconfig.name b/src/mainboard/acer/aspire_vn7_572g/Kconfig.name
new file mode 100644
index 0000000..b881680
--- /dev/null
+++ b/src/mainboard/acer/aspire_vn7_572g/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_ACER_VN7_572G
+ bool "Aspire VN7-572G"
diff --git a/src/mainboard/acer/aspire_vn7_572g/Makefile.inc b/src/mainboard/acer/aspire_vn7_572g/Makefile.inc
new file mode 100644
index 0000000..35f0f6c
--- /dev/null
+++ b/src/mainboard/acer/aspire_vn7_572g/Makefile.inc
@@ -0,0 +1,17 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2015 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+ramstage-y += ramstage.c
+ramstage-y += hda_verb.c
diff --git a/src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl b/src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl
new file mode 100644
index 0000000..2eed489
--- /dev/null
+++ b/src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl
@@ -0,0 +1,328 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Name (EMBA, 0xFE800000)
+
+Device (EC0)
+{
+ Name (_HID, EisaId ("PNP0C09")) /* Embedded Controller Device */ // _HID: Hardware ID
+
+ Name (_GPE, 0x50) // _GPE: General Purpose Events
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (0x0F)
+ }
+
+ Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
+ IO (Decode16, 0x62, 0x62, 0, 1) // Range Minimum, Range Maximum, Alignment, Length
+ IO (Decode16, 0x66, 0x66, 0, 1) // Range Minimum, Range Maximum, Alignment, Length
+ })
+ OperationRegion (ECO1, SystemIO, 0x62, One)
+ Field (ECO1, ByteAcc, Lock, Preserve)
+ {
+ PX62, 8
+ }
+
+ OperationRegion (ECO2, SystemIO, 0x66, One)
+ Field (ECO2, ByteAcc, Lock, Preserve)
+ {
+ PX66, 8
+ }
+
+ OperationRegion (ECMB, SystemMemory, EMBA, 0x0200)
+ OperationRegion (RAM, EmbeddedControl, Zero, 0xFF)
+ Field (RAM, ByteAcc, Lock, Preserve)
+ {
+ CMDB, 8,
+ Offset (0x06),
+ CMD2, 8,
+ CMD1, 8,
+ CMD0, 8,
+ Offset (0x0A),
+ , 1, /* Reserved */
+ , 1, /* Reserved */
+ Offset (0x10),
+ EQEN, 1,
+ , 1, /* Reserved */
+ Offset (0x4E),
+ ISEN, 1, /* Sense? (0=Not Exist, 1=Exist) */
+ Offset (0x51),
+ , 3, /* Reserved */
+ TPEN, 1,
+ Offset (0x52),
+ WLEX, 1, /* Wireless LAN (0=Not Exist, 1=Exist) */
+ BTEX, 1, /* Bluetooth? (0=Not Exist, 1=Exist) */
+ EX3G, 1, /* 3G (0=Not Exist, 1=Exist) */
+ , 3, /* Reserved */
+ RFEX, 1,
+ Offset (0x57),
+ , 7, /* Reserved */
+ AHKB, 1,
+ AHKE, 8,
+ Offset (0x5C),
+ Offset (0x5D),
+ Offset (0x70),
+ , 1, /* Reserved */
+ KLID, 1, /* LID? */
+ , 3, /* Reserved */
+ KACS, 1, /* AC power? */
+ Offset (0x71),
+ WLEN, 1, /* Wireless LAN (0=Not Enabled, 1=Enabled) */
+ BTEN, 1, /* Bluetooth (0=Not Enabled, 1=Enabled) */
+ , 3, /* Reserved */
+ ISS3, 1,
+ ISS4, 1,
+ ISS5, 1,
+ Offset (0x74),
+ , 2, /* Reserved */
+ , 1, /* Reserved */
+ TPEX, 1,
+ Offset (0x75),
+ BLST, 1,
+ LMIB, 1,
+ Offset (0x76),
+ ECSS, 4,
+ EOSS, 4
+ }
+
+ Method (_REG, 2, NotSerialized) // _REG: Region Availability
+ {
+ /* Initialize AC power state */
+ Store (KACS, \PWRS)
+
+ /* Initialize LID switch state */
+ Store (KLID, \LIDS)
+ }
+
+ /* KEY_BRIGHTNESSUP */
+ Method (_Q1C, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ Notify (^^^GFX0.DD1F, 0x86) // Device-Specific
+ }
+
+ /* KEY_BRIGHTNESSDOWN */
+ Method (_Q1D, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ Notify (^^^GFX0.DD1F, 0x87) // Device-Specific
+ }
+
+ /* Battery Information Event */
+ Method (_Q40, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ Notify (BAT0, 0x81) // Information Change
+ }
+
+ /* AC event */
+ Method (_Q50, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ Notify (ADP1, 0x80) // Status Change
+ }
+
+ /* Lid event */
+ Method (_Q52, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ Notify (LID0, 0x80) // Status Change
+ }
+
+ /* Battery Information Event */
+ Method (_Q41, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ Notify (BAT0, 0x81) // Information Change
+ }
+
+ /* Battery Status Event */
+ Method (_Q48, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ Notify (BAT0, 0x80) // Status Change
+ }
+
+ Method (ECWK, 1, NotSerialized)
+ {
+ EQEN = One
+ Notify (BAT0, 0x81) // Information Change
+ If (((Arg0 == 0x03) || (Arg0 == 0x04)))
+ {
+ Notify (SLPB, 0x02) // Device Wake
+ }
+ }
+
+ Name (B0ST, Zero)
+ Field (ECMB, ByteAcc, Lock, Preserve)
+ {
+ Offset (0x08),
+ MB0S, 8
+ }
+
+ OperationRegion (MBB0, SystemMemory, (EMBA + 0x80), 0xFF)
+ Field (MBB0, ByteAcc, Lock, Preserve)
+ {
+ MBRC, 16,
+ MBFC, 16,
+ MBPE, 16,
+ MBAC, 16,
+ MBVO, 16,
+ , 15,
+ MBCM, 1,
+ MBCU, 16,
+ MBTV, 16
+ }
+
+ Method (GBIF, 3, NotSerialized)
+ {
+ If (Arg2)
+ {
+ Arg1 [One] = 0xFFFFFFFF
+ Arg1 [0x02] = 0xFFFFFFFF
+ Arg1 [0x04] = 0xFFFFFFFF
+ Arg1 [0x05] = Zero
+ Arg1 [0x06] = Zero
+ }
+
+ Return (Arg1)
+ }
+
+ Method (GBST, 4, NotSerialized)
+ {
+ Local0 = Zero
+
+ If ((Arg1 & One))
+ {
+ Local1 = MBAC /* \_SB_.PCI0.LPCB.EC0_.MBAC */
+ Local2 = MBRC /* \_SB_.PCI0.LPCB.EC0_.MBRC */
+ If (ACST)
+ {
+ If ((Arg1 & 0x20))
+ {
+ Local2 = MBFC /* \_SB_.PCI0.LPCB.EC0_.MBFC */
+ }
+ }
+
+ Local3 = MBVO /* \_SB_.PCI0.LPCB.EC0_.MBVO */
+ If ((Local1 >= 0x8000))
+ {
+ If ((Local0 & One))
+ {
+ Local1 = (0x00010000 - Local1)
+ }
+ Else
+ {
+ Local1 = Zero
+ }
+ }
+
+ If (Arg2)
+ {
+ Local1 *= Local3
+ Divide (Local1, 0x03E8, Local1)
+ }
+ }
+ Else
+ {
+ Local0 = Zero
+ Local1 = 0xFFFFFFFF
+ Local2 = 0xFFFFFFFF
+ Local3 = 0xFFFFFFFF
+ }
+
+ Arg3 [Zero] = Local0
+ Arg3 [One] = Local1
+ Arg3 [0x02] = Local2
+ Arg3 [0x03] = Local3
+ Return (Arg3)
+ }
+
+ Name (ACST, One)
+ Device (ADP1)
+ {
+ Name (_HID, "ACPI0003") /* Power Source Device */ // _HID: Hardware ID
+ Name (_PCL, Package () { \_SB }) // _PCL: Power Consumer List
+ Method (_PSR) // _PSR: Power Source
+ {
+ Return (\PWRS)
+ }
+ Method (_STA) // _STA: Status
+ {
+ Return (0x0F)
+ }
+ }
+
+ Device (BAT0)
+ {
+ Name (_HID, EisaId ("PNP0C0A")) /* Control Method Battery */ // _HID: Hardware ID
+ Name (_UID, Zero) // _UID: Unique ID
+ Method (_PCL, 0, NotSerialized) // _PCL: Power Consumer List
+ {
+ Return (_SB) /* \_SB_ */
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ If (B0ST)
+ {
+ Return (0x1F)
+ }
+ Else
+ {
+ Return (0x0F)
+ }
+ }
+
+ Name (B0IP, Package (0x0D)
+ {
+ 0x00000001, /* 0x00: Power Unit: mAH */
+ 0xFFFFFFFF, /* 0x01: Design Capacity */
+ 0xFFFFFFFF, /* 0x02: Last Full Charge Capacity */
+ 0x00000001, /* 0x03: Battery Technology: Rechargeable */
+ 0xFFFFFFFF, /* 0x04: Design Voltage */
+ 0x00000000, /* 0x05: Design Capacity of Warning */
+ 0x00000000, /* 0x06: Design Capacity of Low */
+ 0x00000001, /* 0x07: Capacity Granularity 1 */
+ 0x00000001, /* 0x08: Capacity Granularity 2 */
+ "", /* 0x09: Model Number */
+ "100", /* 0x0a: Serial Number */
+ "Lion", /* 0x0b: Battery Type */
+ 0x00000000 /* 0x0c: OEM Information */
+ })
+
+ Method (_BIF, 0, NotSerialized) // _BIF: Battery Information
+ {
+ Local6 = B0ST /* \_SB_.PCI0.LPCB.EC0_.B0ST */
+ While ((Local6))
+ {
+ Local1 = MB0S /* \_SB_.PCI0.LPCB.EC0_.MB0S */
+ If ((Local1 & 0x08))
+ {
+ Local6 = Zero
+ }
+ }
+
+ Return (GBIF (Zero, B0IP, Local6))
+ }
+
+ Name (B0SP, Package (0x04)
+ {
+ 0x00000000, /* 0x00: Battery State */
+ 0xFFFFFFFF, /* 0x01: Battery Present Rate */
+ 0xFFFFFFFF, /* 0x02: Battery Remaining Capacity */
+ 0xFFFFFFFF /* 0x03: Battery Present Voltage */
+ })
+
+ Method (_BST, 0, NotSerialized) // _BST: Battery Status
+ {
+ Local0 = (DerefOf (B0IP [Zero]) ^ One)
+ Return (GBST (Zero, MB0S, Local0, B0SP))
+ }
+ }
+}
diff --git a/src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl b/src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl
new file mode 100644
index 0000000..e145a2b
--- /dev/null
+++ b/src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl
@@ -0,0 +1,68 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+OperationRegion (SANV, SystemMemory, 0x7CE5FD98, Zero)
+Field (SANV, AnyAcc, Lock, Preserve)
+{
+ BRTL, 8
+}
+
+Scope (\_SB.PCI0)
+{
+ Device (GFX0)
+ {
+ Name (_ADR, 0x00020000) // _ADR: Address
+
+ Device (DD1F)
+ {
+ Method (_ADR, 0, Serialized) // _ADR: Address
+ {
+ Return (0x1F)
+ }
+
+ Method (_BCL, 0, NotSerialized) // _BCL: Brightness Control Levels
+ {
+ Return (Package (0x0C)
+ {
+ 0x50,
+ 0x32,
+ 0x0A,
+ 0x14,
+ 0x1E,
+ 0x28,
+ 0x32,
+ 0x3C,
+ 0x46,
+ 0x50,
+ 0x5A,
+ 0x64
+ })
+ }
+
+ Method (_BCM, 1, NotSerialized) // _BCM: Brightness Control Method
+ {
+ If (((Arg0 >= Zero) && (Arg0 <= 0x64)))
+ {
+ BRTL = Arg0
+ }
+ }
+
+ Method (_BQC, 0, NotSerialized) // _BQC: Brightness Query Current
+ {
+ Return (BRTL) /* \BRTL */
+ }
+ }
+ }
+}
diff --git a/src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl b/src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl
new file mode 100644
index 0000000..90e75f2
--- /dev/null
+++ b/src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl
@@ -0,0 +1,54 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Scope (\_SB)
+{
+ Device (LID0) /* Lid Device */
+ {
+ Name (_HID, EisaId ("PNP0C0D"))
+
+ Method (_STA) // _STA: Status
+ {
+ Return (0xF)
+ }
+
+ Method (_LID) // _LID: Lid Status
+ {
+ Return (\LIDS)
+ }
+ }
+
+ Device (PWRB)
+ {
+ Name (_HID, EisaId ("PNP0C0C"))
+
+ Method (_STA)
+ {
+ Return (0xF)
+ }
+
+ Name (_PRW, Package () { 27, 4 })
+ }
+
+ Device (SLPB) /* Sleep Button Device */ // _HID: Hardware ID
+ {
+ Name (_HID, EisaId ("PNP0C0E"))
+
+ Method (_STA) // _STA: Status
+ {
+ Return (0xF)
+ }
+ }
+}
diff --git a/src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl b/src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl
new file mode 100644
index 0000000..92c272e
--- /dev/null
+++ b/src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl
@@ -0,0 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <drivers/pc80/pc/ps2_controller.asl>
diff --git a/src/mainboard/acer/aspire_vn7_572g/acpi_tables.c b/src/mainboard/acer/aspire_vn7_572g/acpi_tables.c
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/acer/aspire_vn7_572g/acpi_tables.c
diff --git a/src/mainboard/acer/aspire_vn7_572g/board_info.txt b/src/mainboard/acer/aspire_vn7_572g/board_info.txt
new file mode 100644
index 0000000..f16707e
--- /dev/null
+++ b/src/mainboard/acer/aspire_vn7_572g/board_info.txt
@@ -0,0 +1,8 @@
+Vendor name: Acer
+Board name: Aspire VN7-572G
+Category: laptop
+ROM package: SOIC8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
+Release year: 2015
diff --git a/src/mainboard/acer/aspire_vn7_572g/devicetree.cb b/src/mainboard/acer/aspire_vn7_572g/devicetree.cb
new file mode 100644
index 0000000..f38b0b8
--- /dev/null
+++ b/src/mainboard/acer/aspire_vn7_572g/devicetree.cb
@@ -0,0 +1,218 @@
+chip soc/intel/skylake
+
+ # Disable deep Sx states
+ register "deep_s3_enable_ac" = "0"
+ register "deep_s3_enable_dc" = "0"
+ register "deep_s5_enable_ac" = "0"
+ register "deep_s5_enable_dc" = "0"
+ register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
+
+ register "eist_enable" = "1"
+
+ # Set the Thermal Control Circuit (TCC) activaction value to 95C
+ # even though FSP integration guide says to set it to 100C for SKL-U
+ # (offset at 0), because when the TCC activates at 100C, the CPU
+ # will have already shut itself down from overheating protection.
+ register "tcc_offset" = "5" # TCC of 95C
+
+ # GPE configuration
+ # Note that GPE events called out in ASL code rely on this
+ # route. i.e. If this route changes then the affected GPE
+ # offset bits also need to be changed.
+ register "gpe0_dw0" = "GPP_C"
+ register "gpe0_dw1" = "GPP_D"
+ register "gpe0_dw2" = "GPP_E"
+
+ # EC host command ranges are in 0x60-0x66
+ register "gen1_dec" = "0x00000061"
+
+ # Enable "Intel Speed Shift Technology"
+ register "speed_shift_enable" = "1"
+
+ # Disable DPTF
+ register "dptf_enable" = "0"
+
+ # FSP Configuration
+ register "ProbelessTrace" = "0"
+ register "EnableLan" = "0"
+ register "EnableSata" = "1"
+ register "SataSalpSupport" = "1"
+ register "SataMode" = "0"
+ register "SataPortsEnable[0]" = "1"
+ register "SataPortsEnable[1]" = "1"
+ register "SataPortsEnable[2]" = "1"
+ register "SataPortsDevSlp[0]" = "0"
+ register "SataPortsDevSlp[1]" = "0"
+ register "SataPortsDevSlp[2]" = "0"
+ register "EnableAzalia" = "1"
+ register "DspEnable" = "1"
+ register "IoBufferOwnership" = "0"
+ register "EnableTraceHub" = "0"
+ register "SsicPortEnable" = "0"
+ register "SmbusEnable" = "1"
+ register "Cio2Enable" = "0"
+ register "ScsEmmcEnabled" = "0"
+ register "ScsEmmcHs400Enabled" = "0"
+ register "ScsSdCardEnabled" = "0"
+ register "PttSwitch" = "0"
+ register "SkipExtGfxScan" = "0"
+ register "Device4Enable" = "0"
+ register "HeciEnabled" = "1"
+ register "SaGv" = "0"
+ register "PmConfigSlpS3MinAssert" = "2" # 50ms
+ register "PmConfigSlpS4MinAssert" = "1" # 1s
+ register "PmConfigSlpSusMinAssert" = "3" # 500ms
+ register "PmConfigSlpAMinAssert" = "3" # 2s
+ register "PmTimerDisabled" = "0"
+
+ # EC/KBC requires continuous mode
+ register "serirq_mode" = "SERIRQ_CONTINUOUS"
+
+ register "pirqa_routing" = "PCH_IRQ11"
+ register "pirqb_routing" = "PCH_IRQ10"
+ register "pirqc_routing" = "PCH_IRQ11"
+ register "pirqd_routing" = "PCH_IRQ11"
+ register "pirqe_routing" = "PCH_IRQ11"
+ register "pirqf_routing" = "PCH_IRQ11"
+ register "pirqg_routing" = "PCH_IRQ11"
+ register "pirqh_routing" = "PCH_IRQ11"
+
+ # VR Settings Configuration for 4 Domains
+ #+----------------+-----------+-----------+-------------+----------+
+ #| Domain/Setting | SA | IA | GT Unsliced | GT |
+ #+----------------+-----------+-----------+-------------+----------+
+ #| Psi1Threshold | 20A | 20A | 20A | 20A |
+ #| Psi2Threshold | 4A | 5A | 5A | 5A |
+ #| Psi3Threshold | 1A | 1A | 1A | 1A |
+ #| Psi3Enable | 1 | 1 | 1 | 1 |
+ #| Psi4Enable | 1 | 1 | 1 | 1 |
+ #| ImonSlope | 0 | 0 | 0 | 0 |
+ #| ImonOffset | 0 | 0 | 0 | 0 |
+ #| IccMax | 7A | 34A | 35A | 35A |
+ #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
+ #+----------------+-----------+-----------+-------------+----------+
+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(4),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(7),
+ .voltage_limit = 1520,
+ }"
+
+ register "domain_vr_config[VR_IA_CORE]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(34),
+ .voltage_limit = 1520,
+ }"
+
+ register "domain_vr_config[VR_GT_UNSLICED]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(35),
+ .voltage_limit = 1520,
+ }"
+
+ register "domain_vr_config[VR_GT_SLICED]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(35),
+ .voltage_limit = 1520,
+ }"
+
+ # Enable Root Ports 1, 9 and 10
+ register "PcieRpEnable[2]" = "1"
+ register "PcieRpLtrEnable[2]" = "1"
+ register "PcieRpEnable[8]" = "1"
+ register "PcieRpLtrEnable[8]" = "1"
+ register "PcieRpEnable[9]" = "1"
+ register "PcieRpLtrEnable[9]" = "1"
+
+# register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port
+ register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-A Port (right)
+ register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-A Port (right)
+ register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" # Type-A Port (left)
+ register "usb2_ports[4]" = "USB2_PORT_FLEX(OC2)" # Bluetooth
+ register "usb2_ports[6]" = "USB2_PORT_FLEX(OC2)" # Webcam
+ register "usb2_ports[7]" = "USB2_PORT_FLEX(OC2)" # SD
+
+ # OC0 should be for Type-C but it seems to not have been wired, according to
+ # the available schematics, even though it is labeled as USB_OC_TYPEC.
+# register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (right)
+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (right)
+
+ # PL2 override 25W
+ register "tdp_pl2_override" = "25"
+
+ # Send an extra VR mailbox command for the PS4 exit issue
+ register "SendVrMbxCmd" = "2"
+
+ # Lock Down
+ register "common_soc_config" = "{
+ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+ }"
+
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+ device domain 0 on
+ device pci 00.0 on end # Host Bridge
+ device pci 02.0 on end # Integrated Graphics Device
+ device pci 14.0 on end # USB xHCI
+ device pci 14.1 on end # USB xDCI (OTG)
+ device pci 14.2 on end # Thermal Subsystem
+ device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT Redirection
+ device pci 16.4 off end # Management Engine Interface 3
+ device pci 17.0 on end # SATA
+ device pci 1c.0 on end # PCI Express Port 1
+ device pci 1c.1 off end # PCI Express Port 2
+ device pci 1c.2 off end # PCI Express Port 3
+ device pci 1c.3 off end # PCI Express Port 4
+ device pci 1c.4 off end # PCI Express Port 5
+ device pci 1c.5 off end # PCI Express Port 6
+ device pci 1c.6 off end # PCI Express Port 7
+ device pci 1c.7 off end # PCI Express Port 8
+ device pci 1d.0 on end # PCI Express Port 9
+ device pci 1d.1 on end # PCI Express Port 10
+ device pci 1d.2 off end # PCI Express Port 11
+ device pci 1d.3 off end # PCI Express Port 12
+ device pci 1f.0 on
+ chip drivers/pc80/tpm
+ device pnp 0c31.0 on end
+ end
+ end # LPC Interface
+ device pci 1f.1 off end # P2SB
+ device pci 1f.2 on end # Power Management Controller
+ device pci 1f.3 on end # Intel HDA
+ device pci 1f.4 on end # SMBus
+ device pci 1f.5 on end # PCH SPI
+ device pci 1f.6 off end # GbE
+ end
+end
diff --git a/src/mainboard/acer/aspire_vn7_572g/dsdt.asl b/src/mainboard/acer/aspire_vn7_572g/dsdt.asl
new file mode 100644
index 0000000..c9bcb7d
--- /dev/null
+++ b/src/mainboard/acer/aspire_vn7_572g/dsdt.asl
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2016 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, // DSDT revision: ACPI v2.0 and up
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20141018 // OEM revision
+)
+{
+ // Some generic macros
+ #include <soc/intel/skylake/acpi/platform.asl>
+
+ // global NVS and variables
+ #include <soc/intel/skylake/acpi/globalnvs.asl>
+
+ // CPU
+ #include <cpu/intel/common/acpi/cpu.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <soc/intel/skylake/acpi/systemagent.asl>
+ #include <soc/intel/skylake/acpi/pch.asl>
+ }
+ }
+
+ // Chipset specific sleep states
+ #include <soc/intel/skylake/acpi/sleepstates.asl>
+
+ // Mainboard specific
+ #include "acpi/mainboard.asl"
+
+ // Graphics display
+ #include "acpi/graphics.asl"
+}
diff --git a/src/mainboard/acer/aspire_vn7_572g/gpio.h b/src/mainboard/acer/aspire_vn7_572g/gpio.h
new file mode 100644
index 0000000..4d98da1
--- /dev/null
+++ b/src/mainboard/acer/aspire_vn7_572g/gpio.h
@@ -0,0 +1,201 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+#ifndef __ACPI__
+
+/* Pad configuration in ramstage. */
+static const struct pad_config gpio_table[] = {
+_PAD_CFG_STRUCT(GPP_A0, 0x44000703, 0x0), /* RCIN# */
+_PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x3c00), /* LAD0 */
+_PAD_CFG_STRUCT(GPP_A2, 0x44000702, 0x3c00), /* LAD1 */
+_PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x3c00), /* LAD2 */
+_PAD_CFG_STRUCT(GPP_A4, 0x44000702, 0x3c00), /* LAD3 */
+_PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x0), /* LFRAME# */
+_PAD_CFG_STRUCT(GPP_A6, 0x44000702, 0x0), /* SERIRQ */
+_PAD_CFG_STRUCT(GPP_A7, 0x44000702, 0x0), /* PIRQA# */
+_PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x0), /* CLKRUN# */
+_PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x1000), /* CLKOUT_LPC0 */
+_PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x1000), /* CLKOUT_LPC1 */
+_PAD_CFG_STRUCT(GPP_A11, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_A12, 0x44000100, 0x0), /* GPIO */
+_PAD_CFG_STRUCT(GPP_A13, 0x44000700, 0x0), /* SUSWARN#/SUSPWRDNACK */
+_PAD_CFG_STRUCT(GPP_A14, 0x44000700, 0x0), /* SUS_STAT# */
+_PAD_CFG_STRUCT(GPP_A15, 0x44000700, 0x1000), /* SUS_ACK# */
+_PAD_CFG_STRUCT(GPP_A16, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_A17, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_A18, 0x44000102, 0x0), /* GPIO */
+_PAD_CFG_STRUCT(GPP_A19, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_A20, 0x44000100, 0x0), /* GPIO */
+_PAD_CFG_STRUCT(GPP_A21, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_A22, 0x44000201, 0x0), /* GPIO */
+_PAD_CFG_STRUCT(GPP_A23, 0x44000201, 0x1000), /* GPIO */
+
+_PAD_CFG_STRUCT(GPP_B0, 0x44000700, 0x0), /* CORE_VID0 */
+_PAD_CFG_STRUCT(GPP_B1, 0x44000700, 0x0), /* CORE_VID1 */
+_PAD_CFG_STRUCT(GPP_B2, 0x44000100, 0x0), /* GPIO */
+_PAD_CFG_STRUCT(GPP_B3, 0x80100102, 0x0), /* GPIO */
+_PAD_CFG_STRUCT(GPP_B4, 0x44000200, 0x0), /* GPIO */
+_PAD_CFG_STRUCT(GPP_B5, 0x44000702, 0x0), /* SRCCLKREQ0# */
+_PAD_CFG_STRUCT(GPP_B6, 0x44000702, 0x0), /* SRCCLKREQ1# */
+_PAD_CFG_STRUCT(GPP_B7, 0x44000700, 0x0), /* SRCCLKREQ2# */
+_PAD_CFG_STRUCT(GPP_B8, 0x44000702, 0x0), /* SRCCLKREQ3# */
+_PAD_CFG_STRUCT(GPP_B9, 0x44000702, 0x0), /* SRCCLKREQ4# */
+_PAD_CFG_STRUCT(GPP_B10, 0x44000702, 0x0), /* SRCCLKREQ5# */
+_PAD_CFG_STRUCT(GPP_B11, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_B12, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x0), /* PLTRST# */
+_PAD_CFG_STRUCT(GPP_B14, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_B15, 0x44000200, 0x0), /* GPIO */
+_PAD_CFG_STRUCT(GPP_B16, 0x44000200, 0x0), /* GPIO */
+_PAD_CFG_STRUCT(GPP_B17, 0x42880100, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_B18, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_B19, 0x44000100, 0x0), /* GPIO */
+_PAD_CFG_STRUCT(GPP_B20, 0x44000102, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_B21, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_B22, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_B23, 0x44000201, 0x1000), /* GPIO */
+
+_PAD_CFG_STRUCT(GPP_C0, 0x44000702, 0x0), /* SMBCLK */
+_PAD_CFG_STRUCT(GPP_C1, 0x44000702, 0x1000), /* SMBDATA */
+_PAD_CFG_STRUCT(GPP_C2, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_C3, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_C4, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_C5, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_C6, 0x44000702, 0x0), /* SML1CLK */
+_PAD_CFG_STRUCT(GPP_C7, 0x44000702, 0x1000), /* SML1DATA */
+_PAD_CFG_STRUCT(GPP_C8, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_C9, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_C10, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_C11, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_C12, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_C13, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_C14, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_C15, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_C16, 0x44000702, 0x0), /* I2C0_SDA */
+_PAD_CFG_STRUCT(GPP_C17, 0x44000702, 0x0), /* I2C0_SCL */
+_PAD_CFG_STRUCT(GPP_C18, 0x44000702, 0x0), /* I2C1_SDA */
+_PAD_CFG_STRUCT(GPP_C19, 0x44000702, 0x0), /* I2C1_SCL */
+_PAD_CFG_STRUCT(GPP_C20, 0x44000702, 0x0), /* UART2_RXD */
+_PAD_CFG_STRUCT(GPP_C21, 0x44000700, 0x0), /* UART2_TXD */
+_PAD_CFG_STRUCT(GPP_C22, 0x44000700, 0x0), /* UART2_RTS# */
+_PAD_CFG_STRUCT(GPP_C23, 0x44000702, 0x0), /* UART2_CTS# */
+
+_PAD_CFG_STRUCT(GPP_D0, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_D1, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_D2, 0x44000700, 0x0), /* SPI1_MISO */
+_PAD_CFG_STRUCT(GPP_D3, 0x44000700, 0x0), /* SPI1_MOSI */
+_PAD_CFG_STRUCT(GPP_D4, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_D5, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_D6, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_D7, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_D8, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_D9, 0x40000102, 0x0), /* GPIO */
+_PAD_CFG_STRUCT(GPP_D10, 0x40000102, 0x0), /* GPIO */
+_PAD_CFG_STRUCT(GPP_D11, 0x40000102, 0x0), /* GPIO */
+_PAD_CFG_STRUCT(GPP_D12, 0x40000102, 0x0), /* GPIO */
+_PAD_CFG_STRUCT(GPP_D13, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_D14, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_D15, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_D16, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_D17, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_D18, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_D19, 0x44000700, 0x0), /* DMIC_CLK0 */
+_PAD_CFG_STRUCT(GPP_D20, 0x44000700, 0x0), /* DMIC_DATA0 */
+_PAD_CFG_STRUCT(GPP_D21, 0x44000700, 0x0), /* SPI1_IO2 */
+_PAD_CFG_STRUCT(GPP_D22, 0x44000700, 0x0), /* SPI1_IO3 */
+_PAD_CFG_STRUCT(GPP_D23, 0x44000201, 0x1000), /* GPIO */
+
+_PAD_CFG_STRUCT(GPP_E0, 0x44000700, 0x0), /* SATAXPCIE0 */
+_PAD_CFG_STRUCT(GPP_E1, 0x44000700, 0x0), /* SATAXPCIE1 */
+_PAD_CFG_STRUCT(GPP_E2, 0x44000702, 0x0), /* SATAXPCIE2 */
+_PAD_CFG_STRUCT(GPP_E3, 0x44000201, 0x0), /* GPIO */
+_PAD_CFG_STRUCT(GPP_E4, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_E5, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_E6, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_E7, 0x40900100, 0x0), /* GPIO */
+_PAD_CFG_STRUCT(GPP_E8, 0xffffffff, 0xffffff00),/* RESERVED */
+_PAD_CFG_STRUCT(GPP_E9, 0x44000702, 0x0), /* USB2_OC0# */
+_PAD_CFG_STRUCT(GPP_E10, 0x44000702, 0x0), /* USB2_OC1# */
+_PAD_CFG_STRUCT(GPP_E11, 0x44000702, 0x0), /* USB2_OC2# */
+_PAD_CFG_STRUCT(GPP_E12, 0x44000702, 0x0), /* USB2_OC3# */
+_PAD_CFG_STRUCT(GPP_E13, 0x44000700, 0x0), /* DDPB_HPD0 */
+_PAD_CFG_STRUCT(GPP_E14, 0x44000700, 0x0), /* DDPC_HPD1 */
+_PAD_CFG_STRUCT(GPP_E15, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_E16, 0x80880102, 0x0), /* GPIO */
+_PAD_CFG_STRUCT(GPP_E17, 0x44000702, 0x0), /* EDP_HPD */
+_PAD_CFG_STRUCT(GPP_E18, 0x44000702, 0x0), /* DDPB_CTRLCLK */
+_PAD_CFG_STRUCT(GPP_E19, 0x44000702, 0x1000), /* DDPB_CTRLDATA */
+_PAD_CFG_STRUCT(GPP_E20, 0x44000700, 0x0), /* DDPC_CTRLCLK */
+_PAD_CFG_STRUCT(GPP_E21, 0x44000702, 0x1000), /* DDPC_CTRLDATA */
+_PAD_CFG_STRUCT(GPP_E22, 0x40100000, 0x0), /* GPIO */
+_PAD_CFG_STRUCT(GPP_E23, 0x44000201, 0x1000), /* GPIO */
+
+_PAD_CFG_STRUCT(GPD0, 0x4000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPD1, 0x4000702, 0x0), /* ACPRESENT */
+_PAD_CFG_STRUCT(GPD2, 0x4000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPD3, 0x4000702, 0x3000), /* PWRBTN# */
+_PAD_CFG_STRUCT(GPD4, 0x4000700, 0x0), /* SLP_S3# */
+_PAD_CFG_STRUCT(GPD5, 0x4000700, 0x0), /* SLP_S4# */
+_PAD_CFG_STRUCT(GPD6, 0x4000601, 0x1000), /* SLP_A# */
+_PAD_CFG_STRUCT(GPD7, 0x4000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPD8, 0x4000700, 0x0), /* SUSCLK */
+_PAD_CFG_STRUCT(GPD9, 0x4000601, 0x1000), /* SLP_WLAN# */
+_PAD_CFG_STRUCT(GPD10, 0x4000601, 0x1000), /* SLP_S5# */
+_PAD_CFG_STRUCT(GPD11, 0x4000201, 0x1000), /* GPIO */
+
+_PAD_CFG_STRUCT(GPP_F0, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F1, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F2, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F3, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F4, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F5, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F6, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F7, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F8, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F9, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F10, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F11, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F12, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F13, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F14, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F15, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F16, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F17, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F18, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F19, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F20, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F21, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F22, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F23, 0x40100100, 0x0), /* GPIO */
+
+_PAD_CFG_STRUCT(GPP_G0, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_G1, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_G2, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_G3, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_G4, 0x44000200, 0x0), /* GPIO */
+_PAD_CFG_STRUCT(GPP_G5, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_G6, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_G7, 0x44000201, 0x1000), /* GPIO */
+};
+
+#endif
+
+#endif
diff --git a/src/mainboard/acer/aspire_vn7_572g/hda_verb.c b/src/mainboard/acer/aspire_vn7_572g/hda_verb.c
new file mode 100644
index 0000000..8cd5f97
--- /dev/null
+++ b/src/mainboard/acer/aspire_vn7_572g/hda_verb.c
@@ -0,0 +1,72 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Purism SPC.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ /* coreboot specific header */
+ 0x10ec0255, /* Codec Vendor / Device ID: Realtek ALC255 */
+ 0x10251037, /* Subsystem ID */
+ 0x0000000c, /* Number of jacks (NID entries) */
+
+ 0x0017ff00, /* Function Reset */
+ 0x0017ff00, /* Double Function Reset */
+ 0x0017ff00,
+ 0x0017ff00,
+
+ /* Bits 31:28 - Codec Address */
+ /* Bits 27:20 - NID */
+ /* Bits 19:8 - Verb ID */
+ /* Bits 7:0 - Payload */
+
+ /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x10251037 */
+ AZALIA_SUBVENDOR(0x0, 0x10251037),
+
+ /* Pin Widget Verb Table */
+
+ /* Pin Complex (NID 0x12) */
+ AZALIA_PIN_CFG(0x0, 0x12, 0x411111c0),
+
+ /* Pin Complex (NID 0x14) */
+ AZALIA_PIN_CFG(0x0, 0x14, 0x90172120),
+
+ /* Pin Complex (NID 0x17) */
+ AZALIA_PIN_CFG(0x0, 0x17, 0x40000000),
+
+ /* Pin Complex (NID 0x18) */
+ AZALIA_PIN_CFG(0x0, 0x18, 0x411111f0),
+
+ /* Pin Complex (NID 0x19) */
+ AZALIA_PIN_CFG(0x0, 0x19, 0x411111f0),
+
+ /* Pin Complex (NID 0x1A) */
+ AZALIA_PIN_CFG(0x0, 0x1A, 0x411111f0),
+
+ /* Pin Complex (NID 0x1B) */
+ AZALIA_PIN_CFG(0x0, 0x1B, 0x411111f0),
+
+ /* Pin Complex (NID 0x1D) */
+ AZALIA_PIN_CFG(0x0, 0x1D, 0x40700001),
+
+ /* Pin Complex (NID 0x1E) */
+ AZALIA_PIN_CFG(0x0, 0x1E, 0x411111f0),
+
+ /* Pin Complex (NID 0x21) */
+ AZALIA_PIN_CFG(0x0, 0x21, 0x02211030),
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/acer/aspire_vn7_572g/mainboard.c b/src/mainboard/acer/aspire_vn7_572g/mainboard.c
new file mode 100644
index 0000000..462b995
--- /dev/null
+++ b/src/mainboard/acer/aspire_vn7_572g/mainboard.c
@@ -0,0 +1,50 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Purism SPC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <smbios.h>
+#include <string.h>
+#include <cbfs.h>
+
+#define MAX_SERIAL_LENGTH 0x100
+
+const char *smbios_mainboard_serial_number(void)
+{
+ static char serial_number[MAX_SERIAL_LENGTH + 1] = {0};
+ struct cbfsf file;
+
+ if (serial_number[0] != 0)
+ return serial_number;
+
+ if (cbfs_boot_locate(&file, "serial_number", NULL) == 0) {
+ struct region_device cbfs_region;
+ size_t serial_len;
+
+ cbfs_file_data(&cbfs_region, &file);
+
+ serial_len = region_device_sz(&cbfs_region);
+ if (serial_len <= MAX_SERIAL_LENGTH) {
+ if (rdev_readat(&cbfs_region, serial_number, 0,
+ serial_len) == serial_len) {
+ serial_number[serial_len] = 0;
+ return serial_number;
+ }
+ }
+ }
+
+ strncpy(serial_number, CONFIG_MAINBOARD_SERIAL_NUMBER,
+ MAX_SERIAL_LENGTH);
+
+ return serial_number;
+}
diff --git a/src/mainboard/acer/aspire_vn7_572g/ramstage.c b/src/mainboard/acer/aspire_vn7_572g/ramstage.c
new file mode 100644
index 0000000..94f8071
--- /dev/null
+++ b/src/mainboard/acer/aspire_vn7_572g/ramstage.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corporation
+ * Copyright (C) 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/ramstage.h>
+#include "gpio.h"
+
+void mainboard_silicon_init_params(FSP_SIL_UPD *params)
+{
+ /* Configure pads prior to SiliconInit() in case there's any
+ * dependencies during hardware initialization. */
+ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
diff --git a/src/mainboard/acer/aspire_vn7_572g/romstage.c b/src/mainboard/acer/aspire_vn7_572g/romstage.c
new file mode 100644
index 0000000..86ef5af
--- /dev/null
+++ b/src/mainboard/acer/aspire_vn7_572g/romstage.c
@@ -0,0 +1,84 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2015 Intel Corporation
+ * Copyright (C) 2017 Purism SPC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <assert.h>
+#include <soc/romstage.h>
+#include <spd_bin.h>
+#include <string.h>
+
+static void mainboard_fill_dq_map_data(void *dq_map_ch0, void *dq_map_ch1)
+{
+ /* DQ byte map */
+ const u8 dq_map[2][12] = {
+ { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,
+ 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 },
+ { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC,
+ 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } };
+ memcpy(dq_map_ch0, dq_map[0], sizeof(dq_map[0]));
+ memcpy(dq_map_ch1, dq_map[1], sizeof(dq_map[1]));
+}
+
+static void mainboard_fill_dqs_map_data(void *dqs_map_ch0, void *dqs_map_ch1)
+{
+ /* DQS CPU<>DRAM map */
+ const u8 dqs_map[2][8] = {
+ { 0, 1, 3, 2, 4, 5, 6, 7 },
+ { 1, 0, 4, 5, 2, 3, 6, 7 } };
+ memcpy(dqs_map_ch0, dqs_map[0], sizeof(dqs_map[0]));
+ memcpy(dqs_map_ch1, dqs_map[1], sizeof(dqs_map[1]));
+}
+
+static void mainboard_fill_rcomp_res_data(void *rcomp_ptr)
+{
+ /* Rcomp resistor */
+ const u16 RcompResistor[3] = { 121, 81, 100 };
+ memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor));
+}
+
+static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr)
+{
+ /* Rcomp target */
+ const u16 RcompTarget[5] = { 100, 40, 20, 20, 26 };
+ memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget));
+}
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+ FSP_M_CONFIG *mem_cfg;
+ struct spd_block blk = {
+ .addr_map = { 0x50, 0x52 },
+ };
+
+ mem_cfg = &mupd->FspmConfig;
+
+ get_spd_smbus(&blk);
+ dump_spd_info(&blk);
+ assert(blk.spd_array[0][0] != 0);
+
+ mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0,
+ &mem_cfg->DqByteMapCh1);
+ mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0,
+ &mem_cfg->DqsMapCpu2DramCh1);
+ mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor);
+ mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);
+
+ mem_cfg->DqPinsInterleaved = TRUE;
+ mem_cfg->MemorySpdDataLen = blk.len;
+ mem_cfg->MemorySpdPtr00 = (uintptr_t) blk.spd_array[0];
+ mem_cfg->MemorySpdPtr10 = (uintptr_t) blk.spd_array[1];
+}
--
To view, visit https://review.coreboot.org/c/coreboot/+/35523
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6
Gerrit-Change-Number: 35523
Gerrit-PatchSet: 1
Gerrit-Owner: Benjamin Doron
Gerrit-MessageType: newchange
1 week, 1 day
- 8
- 291
Change in ...coreboot[master]: soc/intel/denverton_ns: Rewrite pmutil using pmclib
by Patrick Georgi (Code Review)
Hello Julien Viard de Galbert,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/31072
to review the following change.
Change subject: soc/intel/denverton_ns: Rewrite pmutil using pmclib
......................................................................
soc/intel/denverton_ns: Rewrite pmutil using pmclib
Change-Id: I13ab94e7440886f77e3091b16e50e48b17151751
Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net>
---
M src/soc/intel/denverton_ns/include/soc/pm.h
M src/soc/intel/denverton_ns/pmutil.c
M src/soc/intel/denverton_ns/smihandler.c
M src/soc/intel/denverton_ns/smm.c
4 files changed, 33 insertions(+), 184 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/31072/1
diff --git a/src/soc/intel/denverton_ns/include/soc/pm.h b/src/soc/intel/denverton_ns/include/soc/pm.h
index 09ce158..0aab0e2 100644
--- a/src/soc/intel/denverton_ns/include/soc/pm.h
+++ b/src/soc/intel/denverton_ns/include/soc/pm.h
@@ -47,18 +47,6 @@
struct chipset_power_state *fill_power_state(void);
/* Power Management Utility Functions. */
-uint32_t clear_smi_status(void);
-uint16_t clear_pm1_status(void);
-uint32_t clear_tco_status(void);
-uint32_t clear_gpe_status(void);
void clear_pmc_status(void);
-void enable_smi(uint32_t mask);
-void disable_smi(uint32_t mask);
-void enable_pm1(uint16_t events);
-void enable_pm1_control(uint32_t mask);
-void disable_pm1_control(uint32_t mask);
-void enable_gpe(uint32_t mask);
-void disable_gpe(uint32_t mask);
-void disable_all_gpe(void);
#endif /* _DENVERTON_NS_PM_H_ */
diff --git a/src/soc/intel/denverton_ns/pmutil.c b/src/soc/intel/denverton_ns/pmutil.c
index ccf0d95..344f8b9 100644
--- a/src/soc/intel/denverton_ns/pmutil.c
+++ b/src/soc/intel/denverton_ns/pmutil.c
@@ -19,29 +19,12 @@
#include <arch/io.h>
#include <console/console.h>
+#include <intelblocks/pmclib.h>
#include <soc/iomap.h>
#include <soc/soc_util.h>
#include <soc/pm.h>
-static void print_num_status_bits(int num_bits, uint32_t status,
- const char *const bit_names[])
-{
- int i;
-
- if (!status)
- return;
-
- for (i = num_bits - 1; i >= 0; i--) {
- if (status & (1 << i)) {
- if (bit_names[i])
- printk(BIOS_DEBUG, "%s ", bit_names[i]);
- else
- printk(BIOS_DEBUG, "BIT%d ", i);
- }
- }
-}
-
-static uint32_t print_smi_status(uint32_t smi_sts)
+const char *const *soc_smi_sts_array(size_t *a)
{
static const char *const smi_sts_bits[] = {
[2] = "BIOS",
@@ -67,93 +50,11 @@
[31] = "LEGACY_USB3",
};
- if (!smi_sts)
- return 0;
-
- printk(BIOS_DEBUG, "SMI_STS: ");
- print_num_status_bits(ARRAY_SIZE(smi_sts_bits), smi_sts, smi_sts_bits);
- printk(BIOS_DEBUG, "\n");
-
- return smi_sts;
+ *a = ARRAY_SIZE(smi_sts_bits);
+ return smi_sts_bits;
}
-static uint32_t reset_smi_status(void)
-{
- uint16_t pmbase = get_pmbase();
- uint32_t smi_sts = inl((uint16_t)(pmbase + SMI_STS));
- outl(smi_sts, (uint16_t)(pmbase + SMI_STS));
- return smi_sts;
-}
-
-uint32_t clear_smi_status(void) { return print_smi_status(reset_smi_status()); }
-
-void enable_smi(uint32_t mask)
-{
- uint16_t pmbase = get_pmbase();
- uint32_t smi_en = inl((uint16_t)(pmbase + SMI_EN));
- smi_en |= mask;
- outl(smi_en, (uint16_t)(pmbase + SMI_EN));
-}
-
-void disable_smi(uint32_t mask)
-{
- uint16_t pmbase = get_pmbase();
- uint32_t smi_en = inl((uint16_t)(pmbase + SMI_EN));
- smi_en &= ~mask;
- outl(smi_en, (uint16_t)(pmbase + SMI_EN));
-}
-
-void enable_pm1_control(uint32_t mask)
-{
- uint16_t pmbase = get_pmbase();
- uint32_t pm1_cnt = inl((uint16_t)(pmbase + PM1_CNT));
- pm1_cnt |= mask;
- outl(pm1_cnt, (uint16_t)(pmbase + PM1_CNT));
-}
-
-void disable_pm1_control(uint32_t mask)
-{
- uint16_t pmbase = get_pmbase();
- uint32_t pm1_cnt = inl((uint16_t)(pmbase + PM1_CNT));
- pm1_cnt &= ~mask;
- outl(pm1_cnt, (uint16_t)(pmbase + PM1_CNT));
-}
-
-static uint16_t reset_pm1_status(void)
-{
- uint16_t pmbase = get_pmbase();
- uint16_t pm1_sts = inw((uint16_t)(pmbase + PM1_STS));
- outw(pm1_sts, (uint16_t)(pmbase + PM1_STS));
- return pm1_sts;
-}
-
-static uint16_t print_pm1_status(uint16_t pm1_sts)
-{
- static const char *const pm1_sts_bits[] = {
- [0] = "TMROF", [4] = "BM", [5] = "GBL",
- [8] = "PWRBTN", [10] = "RTC", [11] = "PRBTNOR",
- [15] = "WAK",
- };
-
- if (!pm1_sts)
- return 0;
-
- printk(BIOS_SPEW, "PM1_STS: ");
- print_num_status_bits(ARRAY_SIZE(pm1_sts_bits), pm1_sts, pm1_sts_bits);
- printk(BIOS_SPEW, "\n");
-
- return pm1_sts;
-}
-
-uint16_t clear_pm1_status(void) { return print_pm1_status(reset_pm1_status()); }
-
-void enable_pm1(uint16_t events)
-{
- uint16_t pmbase = get_pmbase();
- outw(events, (uint16_t)(pmbase + PM1_EN));
-}
-
-static uint32_t print_tco_status(uint32_t tco_sts)
+const char *const *soc_tco_sts_array(size_t *a)
{
static const char *const tco_sts_bits[] = {
[0] = "NMI2SMI", [1] = "OS_TCO_SMI",
@@ -164,17 +65,11 @@
[17] = "SECOND_TO", [20] = "SMLINK_SLV_SMI",
};
- if (!tco_sts)
- return 0;
-
- printk(BIOS_DEBUG, "TCO_STS: ");
- print_num_status_bits(ARRAY_SIZE(tco_sts_bits), tco_sts, tco_sts_bits);
- printk(BIOS_DEBUG, "\n");
-
- return tco_sts;
+ *a = ARRAY_SIZE(tco_sts_bits);
+ return tco_sts_bits;
}
-static uint32_t reset_tco_status(void)
+uint32_t soc_reset_tco_status(void)
{
uint16_t tcobase = get_tcobase();
uint32_t tco_sts = inl((uint16_t)(tcobase + TCO1_STS));
@@ -184,35 +79,7 @@
return tco_sts & tco_en;
}
-uint32_t clear_tco_status(void) { return print_tco_status(reset_tco_status()); }
-
-void enable_gpe(uint32_t mask)
-{
- uint16_t pmbase = get_pmbase();
- uint32_t gpe0_en = inl((uint16_t)(pmbase + GPE0_EN(GPE_STD)));
- gpe0_en |= mask;
- outl(gpe0_en, (uint16_t)(pmbase + GPE0_EN(GPE_STD)));
-}
-
-void disable_gpe(uint32_t mask)
-{
- uint16_t pmbase = get_pmbase();
- uint32_t gpe0_en = inl((uint16_t)(pmbase + GPE0_EN(GPE_STD)));
- gpe0_en &= ~mask;
- outl(gpe0_en, (uint16_t)(pmbase + GPE0_EN(GPE_STD)));
-}
-
-void disable_all_gpe(void) { disable_gpe(~0); }
-
-static uint32_t reset_gpe_status(void)
-{
- uint16_t pmbase = get_pmbase();
- uint32_t gpe_sts = inl((uint16_t)(pmbase + GPE0_STS(GPE_STD)));
- outl(gpe_sts, (uint16_t)(pmbase + GPE0_STS(GPE_STD)));
- return gpe_sts;
-}
-
-static uint32_t print_gpe_sts(uint32_t gpe_sts)
+const char *const *soc_std_gpe_sts_array(size_t *a)
{
static const char *const gpe_sts_bits[] = {
[0] = "GPIO_0", [1] = "GPIO_1",
@@ -233,16 +100,8 @@
[30] = "GPIO_30", [31] = "GPIO_31",
};
- if (!gpe_sts)
- return gpe_sts;
-
- printk(BIOS_DEBUG, "GPE0a_STS: ");
- print_num_status_bits(ARRAY_SIZE(gpe_sts_bits), gpe_sts, gpe_sts_bits);
- printk(BIOS_DEBUG, "\n");
-
- return gpe_sts;
+ *a = ARRAY_SIZE(gpe_sts_bits);
+ return gpe_sts_bits;
}
-uint32_t clear_gpe_status(void) { return print_gpe_sts(reset_gpe_status()); }
-
void clear_pmc_status(void) { /* TODO */ }
diff --git a/src/soc/intel/denverton_ns/smihandler.c b/src/soc/intel/denverton_ns/smihandler.c
index 85f99d7..e1e7bc4 100644
--- a/src/soc/intel/denverton_ns/smihandler.c
+++ b/src/soc/intel/denverton_ns/smihandler.c
@@ -25,6 +25,7 @@
#include <device/pci_def.h>
#include <elog.h>
#include <intelblocks/fast_spi.h>
+#include <intelblocks/pmclib.h>
#include <spi-generic.h>
#include <soc/iomap.h>
#include <soc/soc_util.h>
@@ -52,7 +53,7 @@
return 0;
}
-void southbridge_smi_set_eos(void) { enable_smi(EOS); }
+void southbridge_smi_set_eos(void) { pmc_enable_smi(EOS); }
global_nvs_t *smm_get_gnvs(void) { return gnvs; }
@@ -98,7 +99,7 @@
uint16_t pmbase = get_pmbase();
/* First, disable further SMIs */
- disable_smi(SLP_SMI_EN);
+ pmc_disable_smi(SLP_SMI_EN);
/* Figure out SLP_TYP */
reg32 = inl((uint16_t)(pmbase + PM1_CNT));
@@ -131,7 +132,7 @@
printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n");
/* Disable all GPE */
- disable_all_gpe();
+ pmc_disable_all_gpe();
/* also iterates over all bridges on bus 0 */
busmaster_disable_on_bus(0);
@@ -145,7 +146,7 @@
* event again. We need to set BIT13 (SLP_EN) though to make the
* sleep happen.
*/
- enable_pm1_control(SLP_EN);
+ pmc_enable_pm1_control(SLP_EN);
/* Make sure to stop executing code here for S3/S4/S5 */
if (slp_typ > 1)
@@ -158,7 +159,7 @@
reg32 = inl((uint16_t)(pmbase + PM1_CNT));
if (reg32 & SCI_EN) {
/* The OS is not an ACPI OS, so we set the state to S0 */
- disable_pm1_control(SLP_EN | SLP_TYP);
+ pmc_disable_pm1_control(SLP_EN | SLP_TYP);
}
}
@@ -237,11 +238,11 @@
printk(BIOS_DEBUG, "P-state control\n");
break;
case APM_CNT_ACPI_DISABLE:
- disable_pm1_control(SCI_EN);
+ pmc_disable_pm1_control(SCI_EN);
printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n");
break;
case APM_CNT_ACPI_ENABLE:
- enable_pm1_control(SCI_EN);
+ pmc_enable_pm1_control(SCI_EN);
printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n");
break;
case APM_CNT_FINALIZE:
@@ -268,23 +269,23 @@
static void southbridge_smi_pm1(void)
{
- uint16_t pm1_sts = clear_pm1_status();
+ uint16_t pm1_sts = pmc_clear_pm1_status();
/* While OSPM is not active, poweroff immediately
* on a power button event.
*/
if (pm1_sts & PWRBTN_STS) {
// power button pressed
- disable_pm1_control(-1UL);
- enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT));
+ pmc_disable_pm1_control(-1UL);
+ pmc_enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT));
}
}
-static void southbridge_smi_gpe0(void) { clear_gpe_status(); }
+static void southbridge_smi_gpe0(void) { pmc_clear_all_gpe_status(); }
static void southbridge_smi_tco(void)
{
- uint32_t tco_sts = clear_tco_status();
+ uint32_t tco_sts = pmc_clear_tco_status();
/* Any TCO event? */
if (!tco_sts)
@@ -354,7 +355,7 @@
/* We need to clear the SMI status registers, or we won't see what's
* happening in the following calls.
*/
- smi_sts = clear_smi_status();
+ smi_sts = pmc_clear_smi_status();
/* Call SMI sub handler for each of the status bits */
for (i = 0; i < ARRAY_SIZE(southbridge_smi); i++) {
diff --git a/src/soc/intel/denverton_ns/smm.c b/src/soc/intel/denverton_ns/smm.c
index 9d3fa75..65d2499 100644
--- a/src/soc/intel/denverton_ns/smm.c
+++ b/src/soc/intel/denverton_ns/smm.c
@@ -23,6 +23,7 @@
#include <cpu/x86/smm.h>
#include <string.h>
+#include <intelblocks/pmclib.h>
#include <soc/iomap.h>
#include <soc/soc_util.h>
#include <soc/pm.h>
@@ -48,10 +49,10 @@
}
/* Dump and clear status registers */
- clear_smi_status();
- clear_pm1_status();
- clear_tco_status();
- clear_gpe_status();
+ pmc_clear_smi_status();
+ pmc_clear_pm1_status();
+ pmc_clear_tco_status();
+ pmc_clear_all_gpe_status();
clear_pmc_status();
}
@@ -60,8 +61,8 @@
printk(BIOS_DEBUG, "Enabling SMIs.\n");
/* Configure events Disable pcie wake. */
- enable_pm1(PWRBTN_EN | GBL_EN | PCIEXPWAK_DIS);
- disable_gpe(PME_B0_EN);
+ pmc_enable_pm1(PWRBTN_EN | GBL_EN | PCIEXPWAK_DIS);
+ pmc_disable_std_gpe(PME_B0_EN);
/* Enable SMI generation:
* - on APMC writes (io 0xb2)
@@ -71,7 +72,7 @@
* - on TCO events
* - on microcontroller writes (io 0x62/0x66)
*/
- enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS);
+ pmc_enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS);
}
void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I13ab94e7440886f77e3091b16e50e48b17151751
Gerrit-Change-Number: 31072
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name>
Gerrit-MessageType: newchange
1 week, 2 days
- 4
- 6
Change in coreboot[master]: [WIP] AGESA,binaryPI boards: Move IRQ table programming
by Kyösti Mälkki (Code Review)
Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38564 )
Change subject: [WIP] AGESA,binaryPI boards: Move IRQ table programming
......................................................................
[WIP] AGESA,binaryPI boards: Move IRQ table programming
IRQ programming should be done outside (obsolete) MP table
generation.
Change-Id: Ibce2af4de91549c4c9743cd997f625164672a713
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/mainboard/amd/inagua/mainboard.c
M src/mainboard/amd/inagua/mptable.c
M src/mainboard/amd/olivehill/mainboard.c
M src/mainboard/amd/olivehill/mptable.c
M src/mainboard/amd/olivehillplus/mainboard.c
M src/mainboard/amd/olivehillplus/mptable.c
M src/mainboard/amd/parmer/mainboard.c
M src/mainboard/amd/parmer/mptable.c
M src/mainboard/amd/south_station/mainboard.c
M src/mainboard/amd/south_station/mptable.c
M src/mainboard/amd/thatcher/mainboard.c
M src/mainboard/amd/thatcher/mptable.c
M src/mainboard/amd/union_station/mainboard.c
M src/mainboard/amd/union_station/mptable.c
M src/mainboard/asrock/e350m1/mainboard.c
M src/mainboard/asrock/e350m1/mptable.c
M src/mainboard/asrock/imb-a180/mainboard.c
M src/mainboard/asrock/imb-a180/mptable.c
M src/mainboard/asus/f2a85-m/mainboard.c
M src/mainboard/asus/f2a85-m/mptable.c
M src/mainboard/bap/ode_e21XX/mainboard.c
M src/mainboard/bap/ode_e21XX/mptable.c
M src/mainboard/biostar/a68n_5200/mainboard.c
M src/mainboard/biostar/a68n_5200/mptable.c
M src/mainboard/gizmosphere/gizmo/mainboard.c
M src/mainboard/gizmosphere/gizmo/mptable.c
M src/mainboard/hp/abm/mainboard.c
M src/mainboard/hp/abm/mptable.c
M src/mainboard/hp/pavilion_m6_1035dx/mainboard.c
M src/mainboard/hp/pavilion_m6_1035dx/mptable.c
M src/mainboard/lenovo/g505s/mainboard.c
M src/mainboard/lenovo/g505s/mptable.c
M src/mainboard/lippert/frontrunner-af/mainboard.c
M src/mainboard/lippert/frontrunner-af/mptable.c
M src/mainboard/lippert/toucan-af/mainboard.c
M src/mainboard/lippert/toucan-af/mptable.c
M src/mainboard/msi/ms7721/mainboard.c
M src/mainboard/msi/ms7721/mptable.c
38 files changed, 661 insertions(+), 715 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/38564/1
diff --git a/src/mainboard/amd/inagua/mainboard.c b/src/mainboard/amd/inagua/mainboard.c
index 47a267b..06faa6d 100644
--- a/src/mainboard/amd/inagua/mainboard.c
+++ b/src/mainboard/amd/inagua/mainboard.c
@@ -17,6 +17,20 @@
#include <console/console.h>
#include <device/device.h>
+static const u8 mainboard_intr_data[] = {
+ [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, /* INTA# - INTH# */
+ [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, /* Misc-nil, 0, 1, 2, INT from Serial irq */
+ [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x12, 0x1F, 0x00,
+ [0x18] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00,
+ [0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ [0x30] = 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00,
+ [0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ [0x40] = 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ [0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ [0x50] = 0x10, 0x11, 0x12, 0x13
+};
+
static void init_gpios(void)
{
/**
diff --git a/src/mainboard/amd/inagua/mptable.c b/src/mainboard/amd/inagua/mptable.c
index 1b4e64a..b8bd0b3 100644
--- a/src/mainboard/amd/inagua/mptable.c
+++ b/src/mainboard/amd/inagua/mptable.c
@@ -14,26 +14,11 @@
*/
#include <arch/smp/mpspec.h>
-#include <arch/io.h>
#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-u8 intr_data[] = {
- [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
- [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
- [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,
- [0x18] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,
- [0x28] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- [0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,
- [0x38] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- [0x40] = 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,
- [0x48] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- [0x50] = 0x10,0x11,0x12,0x13
-};
-
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
@@ -59,13 +44,6 @@
/* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
- u8 byte;
-
- for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
- outb(byte | 0x80, 0xC00);
- outb(intr_data[byte], 0xC01);
- }
-
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
@@ -79,23 +57,23 @@
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
/* APU Internal Graphic Device*/
- PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
+ PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
+ PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
//PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* Southbridge HD Audio: */
PCI_INT(0x0, 0x14, 0x2, 0x12);
- PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
- PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
+ PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */
+ PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
+ PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
+ PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
+ PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
+ PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
/* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
+ PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
/* on board NIC & Slot PCIE. */
diff --git a/src/mainboard/amd/olivehill/mainboard.c b/src/mainboard/amd/olivehill/mainboard.c
index 65e838b..514b9c3 100644
--- a/src/mainboard/amd/olivehill/mainboard.c
+++ b/src/mainboard/amd/olivehill/mainboard.c
@@ -15,6 +15,31 @@
#include <console/console.h>
#include <device/device.h>
+#include <southbridge/amd/common/amd_pci_util.h>
+
+static const u8 mainboard_picr_data[0x54] = {
+ 0x03, 0x04, 0x05, 0x07, 0x0B, 0x0A, 0x1F, 0x1F, 0xFA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
+ 0x1F, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x05, 0x04, 0x05, 0x04, 0x04, 0x05, 0x04, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x04, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x03, 0x04, 0x05, 0x07
+};
+static const u8 mainboard_intr_data[0x54] = {
+ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
+ 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x05, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x10, 0x11, 0x12, 0x13
+};
+
+/* PIRQ Setup */
+static void pirq_setup(void)
+{
+ intr_data_ptr = mainboard_intr_data;
+ picr_data_ptr = mainboard_picr_data;
+}
/**********************************************
* enable the dedicated function in mainboard.
@@ -22,6 +47,7 @@
static void mainboard_enable(struct device *dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
+ pirq_setup();
}
struct chip_operations mainboard_ops = {
diff --git a/src/mainboard/amd/olivehill/mptable.c b/src/mainboard/amd/olivehill/mptable.c
index 52374f1..7082013 100644
--- a/src/mainboard/amd/olivehill/mptable.c
+++ b/src/mainboard/amd/olivehill/mptable.c
@@ -14,30 +14,13 @@
*/
#include <arch/smp/mpspec.h>
-#include <arch/io.h>
#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <cpu/x86/lapic.h>
+#include <southbridge/amd/common/amd_pci_util.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
-u8 picr_data[0x54] = {
- 0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
- 0x1F,0x1F,0x1F,0x03,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x05,0x04,0x05,0x04,0x04,0x05,0x04,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x04,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x03,0x04,0x05,0x07
-};
-u8 intr_data[0x54] = {
- 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
- 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x10,0x11,0x12,0x13
-};
-
static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
{
mc->mpc_length += length;
@@ -60,7 +43,6 @@
{
struct mp_config_table *mc;
int bus_isa;
- u8 byte;
/*
* By the time this function gets called, the IOAPIC registers
@@ -87,17 +69,6 @@
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
- /* PIC IRQ routine */
- for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
- outb(byte, 0xC00);
- outb(picr_data[byte], 0xC01);
- }
-
- /* APIC IRQ routine */
- for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
- outb(byte | 0x80, 0xC00);
- outb(intr_data[byte], 0xC01);
- }
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
@@ -111,27 +82,27 @@
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
/* Internal VGA */
- PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
+ PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
+ PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
/* SMBUS */
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* HD Audio */
- PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]);
+ PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
/* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]);
- PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
- PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]);
+ PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
+ PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
+ PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
+ PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
+ PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
+ PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
+ PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
/* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]);
- PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
+ PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
+ PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
/* on board NIC & Slot PCIE. */
diff --git a/src/mainboard/amd/olivehillplus/mainboard.c b/src/mainboard/amd/olivehillplus/mainboard.c
index 1367b03..9fb3a30 100644
--- a/src/mainboard/amd/olivehillplus/mainboard.c
+++ b/src/mainboard/amd/olivehillplus/mainboard.c
@@ -15,16 +15,44 @@
#include <console/console.h>
#include <device/device.h>
+#include <southbridge/amd/common/amd_pci_util.h>
#include <device/pci_def.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
+
+static const u8 mainboard_picr_data[0x54] = {
+ 0x03, 0x04, 0x05, 0x07, 0x0B, 0x0A, 0x1F, 0x1F, 0xFA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
+ 0x1F, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x05, 0x04, 0x05, 0x04, 0x04, 0x05, 0x04, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x04, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x03, 0x04, 0x05, 0x07
+};
+
+static const u8 mainboard_intr_data[0x54] = {
+ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
+ 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x05, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x10, 0x11, 0x12, 0x13
+};
+
+/* PIRQ Setup */
+static void pirq_setup(void)
+{
+ intr_data_ptr = mainboard_intr_data;
+ picr_data_ptr = mainboard_picr_data;
+}
+
/**********************************************
* enable the dedicated function in mainboard.
**********************************************/
static void mainboard_enable(struct device *dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
+ pirq_setup();
}
struct chip_operations mainboard_ops = {
diff --git a/src/mainboard/amd/olivehillplus/mptable.c b/src/mainboard/amd/olivehillplus/mptable.c
index 6c81d06..0f6ca81 100644
--- a/src/mainboard/amd/olivehillplus/mptable.c
+++ b/src/mainboard/amd/olivehillplus/mptable.c
@@ -14,30 +14,12 @@
*/
#include <arch/smp/mpspec.h>
-#include <arch/io.h>
#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <cpu/x86/lapic.h>
#include <southbridge/amd/pi/hudson/hudson.h>
-u8 picr_data[0x54] = {
- 0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
- 0x1F,0x1F,0x1F,0x03,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x05,0x04,0x05,0x04,0x04,0x05,0x04,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x04,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x03,0x04,0x05,0x07
-};
-u8 intr_data[0x54] = {
- 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
- 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x10,0x11,0x12,0x13
-};
-
static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
{
mc->mpc_length += length;
@@ -60,7 +42,6 @@
{
struct mp_config_table *mc;
int bus_isa;
- u8 byte;
/*
* By the time this function gets called, the IOAPIC registers
@@ -87,17 +68,7 @@
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
- /* PIC IRQ routine */
- for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
- outb(byte, 0xC00);
- outb(picr_data[byte], 0xC01);
- }
- /* APIC IRQ routine */
- for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
- outb(byte | 0x80, 0xC00);
- outb(intr_data[byte], 0xC01);
- }
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
@@ -110,27 +81,27 @@
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
/* Internal VGA */
- PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
+ PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
+ PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
/* SMBUS */
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* HD Audio */
- PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]);
+ PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
/* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]);
- PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
- PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]);
+ PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
+ PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
+ PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
+ PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
+ PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
+ PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
+ PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
/* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]);
- PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
+ PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
+ PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
/* on board NIC & Slot PCIE. */
diff --git a/src/mainboard/amd/parmer/mainboard.c b/src/mainboard/amd/parmer/mainboard.c
index 0051d74..668a648 100644
--- a/src/mainboard/amd/parmer/mainboard.c
+++ b/src/mainboard/amd/parmer/mainboard.c
@@ -15,6 +15,31 @@
#include <console/console.h>
#include <device/device.h>
+#include <southbridge/amd/common/amd_pci_util.h>
+
+static const u8 mainboard_picr_data[0x54] = {
+ 0x1F, 0x1f, 0x1f, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x0A, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
+ 0x09, 0x1F, 0x1F, 0x0B, 0x1F, 0x0B, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x1F, 0x1F, 0x1F, 0x1F
+};
+static const u8 mainboard_intr_data[0x54] = {
+ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
+ 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x05, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x10, 0x11, 0x12, 0x13
+};
+
+/* PIRQ Setup */
+static void pirq_setup(void)
+{
+ intr_data_ptr = mainboard_intr_data;
+ picr_data_ptr = mainboard_picr_data;
+}
/*************************************************
* enable the dedicated function in parmer board.
@@ -22,6 +47,7 @@
static void mainboard_enable(struct device *dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
+ pirq_setup();
}
struct chip_operations mainboard_ops = {
diff --git a/src/mainboard/amd/parmer/mptable.c b/src/mainboard/amd/parmer/mptable.c
index c2b9f98..3a5540c 100644
--- a/src/mainboard/amd/parmer/mptable.c
+++ b/src/mainboard/amd/parmer/mptable.c
@@ -14,30 +14,13 @@
*/
#include <arch/smp/mpspec.h>
-#include <arch/io.h>
#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <cpu/x86/lapic.h>
+#include <southbridge/amd/common/amd_pci_util.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
-u8 picr_data[0x54] = {
- 0x1F,0x1f,0x1f,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
- 0x09,0x1F,0x1F,0x0B,0x1F,0x0B,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x1F,0x1F,0x1F,0x1F
-};
-u8 intr_data[0x54] = {
- 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
- 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x10,0x11,0x12,0x13
-};
-
static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
{
mc->mpc_length += length;
@@ -60,7 +43,6 @@
{
struct mp_config_table *mc;
int bus_isa;
- u8 byte;
/*
* By the time this function gets called, the IOAPIC registers
@@ -86,18 +68,6 @@
/* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
- /* PIC IRQ routine */
- for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
- outb(byte, 0xC00);
- outb(picr_data[byte], 0xC01);
- }
-
- /* APIC IRQ routine */
- for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
- outb(byte | 0x80, 0xC00);
- outb(intr_data[byte], 0xC01);
- }
-
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
@@ -110,27 +80,27 @@
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
/* Internal VGA */
- PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
+ PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
+ PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
/* SMBUS */
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* HD Audio */
- PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]);
+ PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
/* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]);
- PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
- PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]);
+ PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
+ PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
+ PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
+ PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
+ PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
+ PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
+ PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
/* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]);
- PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
+ PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
+ PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
/* on board NIC & Slot PCIE. */
diff --git a/src/mainboard/amd/south_station/mainboard.c b/src/mainboard/amd/south_station/mainboard.c
index d9e4c5f..59b4b17 100644
--- a/src/mainboard/amd/south_station/mainboard.c
+++ b/src/mainboard/amd/south_station/mainboard.c
@@ -17,6 +17,23 @@
#include <console/console.h>
#include <delay.h>
#include <device/device.h>
+#include <southbridge/amd/common/amd_pci_util.h>
+
+static const u8 mainboard_intr_data[] = {
+ [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, /* INTA# - INTH# */
+ [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, /* Misc-nil, 0, 1, 2, INT from Serial irq */
+ [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x12, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x10, 0x11, 0x12, 0x13
+};
+
+/* PIRQ Setup */
+static void pirq_setup(void)
+{
+ intr_data_ptr = mainboard_intr_data;
+}
/**
* Southstation using SB GPIO 17/18 to control the Red/Green LED
@@ -45,6 +62,8 @@
static void mainboard_enable(struct device *dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
+ pirq_setup();
+
southstation_led_init();
/*
diff --git a/src/mainboard/amd/south_station/mptable.c b/src/mainboard/amd/south_station/mptable.c
index c38708e..b8bd0b3 100644
--- a/src/mainboard/amd/south_station/mptable.c
+++ b/src/mainboard/amd/south_station/mptable.c
@@ -14,22 +14,11 @@
*/
#include <arch/smp/mpspec.h>
-#include <arch/io.h>
#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-u8 intr_data[] = {
- [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
- [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
- [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x10,0x11,0x12,0x13
-};
-
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
@@ -55,13 +44,6 @@
/* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
- u8 byte;
-
- for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
- outb(byte | 0x80, 0xC00);
- outb(intr_data[byte], 0xC01);
- }
-
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
@@ -75,23 +57,23 @@
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
/* APU Internal Graphic Device*/
- PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
+ PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
+ PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
//PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* Southbridge HD Audio: */
PCI_INT(0x0, 0x14, 0x2, 0x12);
- PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
- PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
+ PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */
+ PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
+ PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
+ PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
+ PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
+ PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
/* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
+ PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
/* on board NIC & Slot PCIE. */
diff --git a/src/mainboard/amd/thatcher/mainboard.c b/src/mainboard/amd/thatcher/mainboard.c
index ef8f9c1..4bd608e 100644
--- a/src/mainboard/amd/thatcher/mainboard.c
+++ b/src/mainboard/amd/thatcher/mainboard.c
@@ -15,9 +15,34 @@
#include <console/console.h>
#include <device/device.h>
+#include <southbridge/amd/common/amd_pci_util.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/msr.h>
+static const u8 mainboard_picr_data[] = {
+ 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x0A, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
+ 0x09, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x1F, 0x1F, 0x1F, 0x1F
+};
+static const u8 mainboard_intr_data[0x54] = {
+ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
+ 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x05, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x10, 0x11, 0x12, 0x13
+};
+
+/* PIRQ Setup */
+static void pirq_setup(void)
+{
+ intr_data_ptr = mainboard_intr_data;
+ picr_data_ptr = mainboard_picr_data;
+}
+
/*************************************************
* enable the dedicated function in thatcher board.
*************************************************/
@@ -26,6 +51,7 @@
msr_t msr;
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
+ pirq_setup();
msr = rdmsr(LS_CFG_MSR);
msr.lo &= ~(1 << 28);
diff --git a/src/mainboard/amd/thatcher/mptable.c b/src/mainboard/amd/thatcher/mptable.c
index b23d036..05d222a 100644
--- a/src/mainboard/amd/thatcher/mptable.c
+++ b/src/mainboard/amd/thatcher/mptable.c
@@ -14,30 +14,13 @@
*/
#include <arch/smp/mpspec.h>
-#include <arch/io.h>
#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <cpu/x86/lapic.h>
+#include <southbridge/amd/common/amd_pci_util.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
-u8 picr_data[] = {
- 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
- 0x09,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x1F,0x1F,0x1F,0x1F
-};
-u8 intr_data[0x54] = {
- 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
- 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x10,0x11,0x12,0x13
-};
-
static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
{
mc->mpc_length += length;
@@ -86,18 +69,6 @@
/* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
- /* PIC IRQ routine */
- for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
- outb(byte, 0xC00);
- outb(picr_data[byte], 0xC01);
- }
-
- /* APIC IRQ routine */
- for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
- outb(byte | 0x80, 0xC00);
- outb(intr_data[byte], 0xC01);
- }
-
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
@@ -110,27 +81,27 @@
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
/* Internal VGA */
- PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
+ PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
+ PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
/* SMBUS */
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* HD Audio */
- PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]);
+ PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
/* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]);
- PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
- PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]);
+ PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
+ PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
+ PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
+ PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
+ PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
+ PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
+ PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
/* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]);
- PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
+ PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
+ PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
/* on board NIC & Slot PCIE. */
diff --git a/src/mainboard/amd/union_station/mainboard.c b/src/mainboard/amd/union_station/mainboard.c
index d680520..d677c4e 100644
--- a/src/mainboard/amd/union_station/mainboard.c
+++ b/src/mainboard/amd/union_station/mainboard.c
@@ -16,14 +16,32 @@
#include <amdblocks/acpimmio.h>
#include <console/console.h>
#include <device/device.h>
+#include <southbridge/amd/common/amd_pci_util.h>
#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> /* Platform Specific Definitions */
+static const u8 mainboard_intr_data[] = {
+ [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, /* INTA# - INTH# */
+ [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, /* Misc-nil, 0, 1, 2, INT from Serial irq */
+ [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x12, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x10, 0x11, 0x12, 0x13
+};
+
+/* PIRQ Setup */
+static void pirq_setup(void)
+{
+ intr_data_ptr = mainboard_intr_data;
+}
+
/**********************************************
* Enable the dedicated functions of the board.
**********************************************/
static void mainboard_enable(struct device *dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
+ pirq_setup();
/*
* Initialize ASF registers to an arbitrary address because someone
diff --git a/src/mainboard/amd/union_station/mptable.c b/src/mainboard/amd/union_station/mptable.c
index c38708e..b8bd0b3 100644
--- a/src/mainboard/amd/union_station/mptable.c
+++ b/src/mainboard/amd/union_station/mptable.c
@@ -14,22 +14,11 @@
*/
#include <arch/smp/mpspec.h>
-#include <arch/io.h>
#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-u8 intr_data[] = {
- [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
- [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
- [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x10,0x11,0x12,0x13
-};
-
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
@@ -55,13 +44,6 @@
/* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
- u8 byte;
-
- for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
- outb(byte | 0x80, 0xC00);
- outb(intr_data[byte], 0xC01);
- }
-
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
@@ -75,23 +57,23 @@
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
/* APU Internal Graphic Device*/
- PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
+ PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
+ PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
//PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* Southbridge HD Audio: */
PCI_INT(0x0, 0x14, 0x2, 0x12);
- PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
- PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
+ PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */
+ PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
+ PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
+ PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
+ PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
+ PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
/* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
+ PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
/* on board NIC & Slot PCIE. */
diff --git a/src/mainboard/asrock/e350m1/mainboard.c b/src/mainboard/asrock/e350m1/mainboard.c
index 96744a3..d8764bc 100644
--- a/src/mainboard/asrock/e350m1/mainboard.c
+++ b/src/mainboard/asrock/e350m1/mainboard.c
@@ -16,15 +16,33 @@
#include <amdblocks/acpimmio.h>
#include <console/console.h>
#include <device/device.h>
+#include <southbridge/amd/common/amd_pci_util.h>
#include <device/mmio.h>
#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
+static const u8 mainboard_intr_data[] = {
+ [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, /* INTA# - INTH# */
+ [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, /* Misc-nil, 0, 1, 2, INT from Serial irq */
+ [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x12, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x10, 0x11, 0x12, 0x13
+};
+
+/* PIRQ Setup */
+static void pirq_setup(void)
+{
+ intr_data_ptr = mainboard_intr_data;
+}
+
/**********************************************
* Enable the dedicated functions of the board.
**********************************************/
static void mainboard_enable(struct device *dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
+ pirq_setup();
/* Power off unused clock pins of GPP PCIe devices
* GPP CLK0 connected to unpopulated mini PCIe slot
diff --git a/src/mainboard/asrock/e350m1/mptable.c b/src/mainboard/asrock/e350m1/mptable.c
index 6093e8f..0eeaa0b 100644
--- a/src/mainboard/asrock/e350m1/mptable.c
+++ b/src/mainboard/asrock/e350m1/mptable.c
@@ -14,25 +14,13 @@
*/
-#include <arch/io.h>
#include <arch/ioapic.h>
#include <arch/smp/mpspec.h>
#include <stdint.h>
#include <string.h>
-
+#include <southbridge/amd/common/amd_pci_util.h>
#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-
-u8 intr_data[] = {
- [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
- [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
- [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x10,0x11,0x12,0x13
-};
-
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
@@ -58,13 +46,6 @@
/* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
- u8 byte;
-
- for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
- outb(byte | 0x80, 0xC00);
- outb(intr_data[byte], 0xC01);
- }
-
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
@@ -78,23 +59,23 @@
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
/* APU Internal Graphic Device*/
- PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
+ PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
+ PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
//PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* Southbridge HD Audio: */
PCI_INT(0x0, 0x14, 0x2, 0x12);
- PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
- PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
+ PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */
+ PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
+ PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
+ PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
+ PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
+ PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
/* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
+ PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
/* on board NIC & Slot PCIE. */
diff --git a/src/mainboard/asrock/imb-a180/mainboard.c b/src/mainboard/asrock/imb-a180/mainboard.c
index 65e838b..e463589 100644
--- a/src/mainboard/asrock/imb-a180/mainboard.c
+++ b/src/mainboard/asrock/imb-a180/mainboard.c
@@ -15,6 +15,32 @@
#include <console/console.h>
#include <device/device.h>
+#include <southbridge/amd/common/amd_pci_util.h>
+
+static const u8 mainboard_picr_data[0x54] = {
+ 0x03, 0x04, 0x05, 0x07, 0x0B, 0x0A, 0x1F, 0x1F, 0xFA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
+ 0x1F, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x05, 0x04, 0x05, 0x04, 0x04, 0x05, 0x04, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x04, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x03, 0x04, 0x05, 0x07
+};
+
+static const u8 mainboard_intr_data[0x54] = {
+ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
+ 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x05, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x10, 0x11, 0x12, 0x13
+};
+
+/* PIRQ Setup */
+static void pirq_setup(void)
+{
+ intr_data_ptr = mainboard_intr_data;
+ picr_data_ptr = mainboard_picr_data;
+}
/**********************************************
* enable the dedicated function in mainboard.
@@ -22,6 +48,7 @@
static void mainboard_enable(struct device *dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
+ pirq_setup();
}
struct chip_operations mainboard_ops = {
diff --git a/src/mainboard/asrock/imb-a180/mptable.c b/src/mainboard/asrock/imb-a180/mptable.c
index 37080ea..7082013 100644
--- a/src/mainboard/asrock/imb-a180/mptable.c
+++ b/src/mainboard/asrock/imb-a180/mptable.c
@@ -14,31 +14,13 @@
*/
#include <arch/smp/mpspec.h>
-#include <arch/io.h>
#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <cpu/x86/lapic.h>
+#include <southbridge/amd/common/amd_pci_util.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
-
-u8 picr_data[0x54] = {
- 0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
- 0x1F,0x1F,0x1F,0x03,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x05,0x04,0x05,0x04,0x04,0x05,0x04,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x04,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x03,0x04,0x05,0x07
-};
-u8 intr_data[0x54] = {
- 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
- 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x10,0x11,0x12,0x13
-};
-
static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
{
mc->mpc_length += length;
@@ -61,7 +43,6 @@
{
struct mp_config_table *mc;
int bus_isa;
- u8 byte;
/*
* By the time this function gets called, the IOAPIC registers
@@ -88,17 +69,6 @@
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
- /* PIC IRQ routine */
- for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
- outb(byte, 0xC00);
- outb(picr_data[byte], 0xC01);
- }
-
- /* APIC IRQ routine */
- for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
- outb(byte | 0x80, 0xC00);
- outb(intr_data[byte], 0xC01);
- }
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
@@ -112,27 +82,27 @@
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
/* Internal VGA */
- PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
+ PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
+ PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
/* SMBUS */
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* HD Audio */
- PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]);
+ PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
/* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]);
- PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
- PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]);
+ PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
+ PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
+ PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
+ PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
+ PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
+ PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
+ PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
/* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]);
- PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
+ PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
+ PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
/* on board NIC & Slot PCIE. */
diff --git a/src/mainboard/asus/f2a85-m/mainboard.c b/src/mainboard/asus/f2a85-m/mainboard.c
index 2a0e618..719039f 100644
--- a/src/mainboard/asus/f2a85-m/mainboard.c
+++ b/src/mainboard/asus/f2a85-m/mainboard.c
@@ -17,6 +17,31 @@
#include <cpu/x86/msr.h>
#include <cpu/amd/msr.h>
#include <device/device.h>
+#include <southbridge/amd/common/amd_pci_util.h>
+
+static const u8 mainboard_picr_data[] = {
+ 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x0A, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
+ 0x09, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x1F, 0x1F, 0x1F, 0x1F
+};
+static const u8 mainboard_intr_data[0x54] = {
+ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
+ 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x05, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x10, 0x11, 0x12, 0x13
+};
+
+/* PIRQ Setup */
+static void pirq_setup(void)
+{
+ intr_data_ptr = mainboard_intr_data;
+ picr_data_ptr = mainboard_picr_data;
+}
/*************************************************
* enable the dedicated function in thatcher board.
@@ -26,6 +51,7 @@
msr_t msr;
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
+ pirq_setup();
msr = rdmsr(LS_CFG_MSR);
msr.lo &= ~(1 << 28);
diff --git a/src/mainboard/asus/f2a85-m/mptable.c b/src/mainboard/asus/f2a85-m/mptable.c
index 303f3bf..fd55eda 100644
--- a/src/mainboard/asus/f2a85-m/mptable.c
+++ b/src/mainboard/asus/f2a85-m/mptable.c
@@ -13,31 +13,14 @@
* GNU General Public License for more details.
*/
-#include <arch/io.h>
#include <arch/ioapic.h>
#include <arch/smp/mpspec.h>
#include <cpu/x86/lapic.h>
#include <stdint.h>
#include <string.h>
+#include <southbridge/amd/common/amd_pci_util.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
-u8 picr_data[] = {
- 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
- 0x09,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x1F,0x1F,0x1F,0x1F
-};
-u8 intr_data[0x54] = {
- 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
- 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x10,0x11,0x12,0x13
-};
-
static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
{
mc->mpc_length += length;
@@ -60,7 +43,6 @@
{
struct mp_config_table *mc;
int bus_isa;
- u8 byte;
/*
* By the time this function gets called, the IOAPIC registers
@@ -86,18 +68,6 @@
/* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
- /* PIC IRQ routine */
- for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
- outb(byte, 0xC00);
- outb(picr_data[byte], 0xC01);
- }
-
- /* APIC IRQ routine */
- for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
- outb(byte | 0x80, 0xC00);
- outb(intr_data[byte], 0xC01);
- }
-
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
@@ -116,27 +86,27 @@
PCI_INT(0x0, 0x0, 0x3, 0x13);
/* Internal VGA */
- PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
+ PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
+ PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
/* SMBUS */
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* HD Audio */
- PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]);
+ PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
/* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]);
- PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
- PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]);
+ PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
+ PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
+ PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
+ PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
+ PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
+ PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
+ PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
/* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]);
- PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
+ PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
+ PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
/* on board NIC & Slot PCIE. */
diff --git a/src/mainboard/bap/ode_e21XX/mainboard.c b/src/mainboard/bap/ode_e21XX/mainboard.c
index 1367b03..f659d3a 100644
--- a/src/mainboard/bap/ode_e21XX/mainboard.c
+++ b/src/mainboard/bap/ode_e21XX/mainboard.c
@@ -15,16 +15,42 @@
#include <console/console.h>
#include <device/device.h>
+#include <southbridge/amd/common/amd_pci_util.h>
#include <device/pci_def.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
+static const u8 mainboard_picr_data[0x54] = {
+ 0x03, 0x04, 0x05, 0x07, 0x0B, 0x0A, 0x1F, 0x1F, 0xFA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
+ 0x1F, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x05, 0x04, 0x05, 0x04, 0x04, 0x05, 0x04, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x04, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x03, 0x04, 0x05, 0x07
+};
+static const u8 mainboard_intr_data[0x54] = {
+ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
+ 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x05, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x10, 0x11, 0x12, 0x13
+};
+
+/* PIRQ Setup */
+static void pirq_setup(void)
+{
+ intr_data_ptr = mainboard_intr_data;
+ picr_data_ptr = mainboard_picr_data;
+}
+
/**********************************************
* enable the dedicated function in mainboard.
**********************************************/
static void mainboard_enable(struct device *dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
+ pirq_setup();
}
struct chip_operations mainboard_ops = {
diff --git a/src/mainboard/bap/ode_e21XX/mptable.c b/src/mainboard/bap/ode_e21XX/mptable.c
index 6c81d06..0f6ca81 100644
--- a/src/mainboard/bap/ode_e21XX/mptable.c
+++ b/src/mainboard/bap/ode_e21XX/mptable.c
@@ -14,30 +14,12 @@
*/
#include <arch/smp/mpspec.h>
-#include <arch/io.h>
#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <cpu/x86/lapic.h>
#include <southbridge/amd/pi/hudson/hudson.h>
-u8 picr_data[0x54] = {
- 0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
- 0x1F,0x1F,0x1F,0x03,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x05,0x04,0x05,0x04,0x04,0x05,0x04,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x04,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x03,0x04,0x05,0x07
-};
-u8 intr_data[0x54] = {
- 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
- 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x10,0x11,0x12,0x13
-};
-
static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
{
mc->mpc_length += length;
@@ -60,7 +42,6 @@
{
struct mp_config_table *mc;
int bus_isa;
- u8 byte;
/*
* By the time this function gets called, the IOAPIC registers
@@ -87,17 +68,7 @@
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
- /* PIC IRQ routine */
- for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
- outb(byte, 0xC00);
- outb(picr_data[byte], 0xC01);
- }
- /* APIC IRQ routine */
- for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
- outb(byte | 0x80, 0xC00);
- outb(intr_data[byte], 0xC01);
- }
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
@@ -110,27 +81,27 @@
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
/* Internal VGA */
- PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
+ PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
+ PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
/* SMBUS */
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* HD Audio */
- PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]);
+ PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
/* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]);
- PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
- PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]);
+ PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
+ PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
+ PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
+ PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
+ PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
+ PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
+ PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
/* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]);
- PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
+ PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
+ PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
/* on board NIC & Slot PCIE. */
diff --git a/src/mainboard/biostar/a68n_5200/mainboard.c b/src/mainboard/biostar/a68n_5200/mainboard.c
index 65e838b..514b9c3 100644
--- a/src/mainboard/biostar/a68n_5200/mainboard.c
+++ b/src/mainboard/biostar/a68n_5200/mainboard.c
@@ -15,6 +15,31 @@
#include <console/console.h>
#include <device/device.h>
+#include <southbridge/amd/common/amd_pci_util.h>
+
+static const u8 mainboard_picr_data[0x54] = {
+ 0x03, 0x04, 0x05, 0x07, 0x0B, 0x0A, 0x1F, 0x1F, 0xFA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
+ 0x1F, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x05, 0x04, 0x05, 0x04, 0x04, 0x05, 0x04, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x04, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x03, 0x04, 0x05, 0x07
+};
+static const u8 mainboard_intr_data[0x54] = {
+ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
+ 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x05, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x10, 0x11, 0x12, 0x13
+};
+
+/* PIRQ Setup */
+static void pirq_setup(void)
+{
+ intr_data_ptr = mainboard_intr_data;
+ picr_data_ptr = mainboard_picr_data;
+}
/**********************************************
* enable the dedicated function in mainboard.
@@ -22,6 +47,7 @@
static void mainboard_enable(struct device *dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
+ pirq_setup();
}
struct chip_operations mainboard_ops = {
diff --git a/src/mainboard/biostar/a68n_5200/mptable.c b/src/mainboard/biostar/a68n_5200/mptable.c
index 52374f1..7082013 100644
--- a/src/mainboard/biostar/a68n_5200/mptable.c
+++ b/src/mainboard/biostar/a68n_5200/mptable.c
@@ -14,30 +14,13 @@
*/
#include <arch/smp/mpspec.h>
-#include <arch/io.h>
#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <cpu/x86/lapic.h>
+#include <southbridge/amd/common/amd_pci_util.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
-u8 picr_data[0x54] = {
- 0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
- 0x1F,0x1F,0x1F,0x03,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x05,0x04,0x05,0x04,0x04,0x05,0x04,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x04,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x03,0x04,0x05,0x07
-};
-u8 intr_data[0x54] = {
- 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
- 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x10,0x11,0x12,0x13
-};
-
static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
{
mc->mpc_length += length;
@@ -60,7 +43,6 @@
{
struct mp_config_table *mc;
int bus_isa;
- u8 byte;
/*
* By the time this function gets called, the IOAPIC registers
@@ -87,17 +69,6 @@
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
- /* PIC IRQ routine */
- for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
- outb(byte, 0xC00);
- outb(picr_data[byte], 0xC01);
- }
-
- /* APIC IRQ routine */
- for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
- outb(byte | 0x80, 0xC00);
- outb(intr_data[byte], 0xC01);
- }
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
@@ -111,27 +82,27 @@
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
/* Internal VGA */
- PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
+ PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
+ PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
/* SMBUS */
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* HD Audio */
- PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]);
+ PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
/* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]);
- PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
- PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]);
+ PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
+ PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
+ PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
+ PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
+ PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
+ PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
+ PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
/* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]);
- PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
+ PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
+ PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
/* on board NIC & Slot PCIE. */
diff --git a/src/mainboard/gizmosphere/gizmo/mainboard.c b/src/mainboard/gizmosphere/gizmo/mainboard.c
index 63d9453..caa4530 100644
--- a/src/mainboard/gizmosphere/gizmo/mainboard.c
+++ b/src/mainboard/gizmosphere/gizmo/mainboard.c
@@ -19,14 +19,32 @@
#include <console/console.h>
#include <delay.h>
#include <device/device.h>
+#include <southbridge/amd/common/amd_pci_util.h>
#include <device/pci_ops.h>
+static const u8 mainboard_intr_data[] = {
+ [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, /* INTA# - INTH# */
+ [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, /* Misc-nil, 0, 1, 2, INT from Serial irq */
+ [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x12, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x10, 0x11, 0x12, 0x13
+};
+
+/* PIRQ Setup */
+static void pirq_setup(void)
+{
+ intr_data_ptr = mainboard_intr_data;
+}
+
/**********************************************
* Enable the dedicated functions of the board.
**********************************************/
static void mainboard_enable(struct device *dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
+ pirq_setup();
/* enable GPP CLK0 thru CLK1 */
/* disable GPP CLK2 thru SLT_GFX_CLK */
diff --git a/src/mainboard/gizmosphere/gizmo/mptable.c b/src/mainboard/gizmosphere/gizmo/mptable.c
index dca5f3c..94a5d0c 100644
--- a/src/mainboard/gizmosphere/gizmo/mptable.c
+++ b/src/mainboard/gizmosphere/gizmo/mptable.c
@@ -15,22 +15,12 @@
*/
#include <arch/smp/mpspec.h>
-#include <arch/io.h>
#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
+#include <southbridge/amd/common/amd_pci_util.h>
#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-u8 intr_data[] = {
- [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
- [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
- [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x10,0x11,0x12,0x13
-};
-
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
@@ -56,13 +46,6 @@
/* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
- u8 byte;
-
- for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
- outb(byte | 0x80, 0xC00);
- outb(intr_data[byte], 0xC01);
- }
-
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
@@ -76,23 +59,23 @@
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
/* APU Internal Graphic Device*/
- PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
+ PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
+ PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
//PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* Southbridge HD Audio: */
PCI_INT(0x0, 0x14, 0x2, 0x12);
- PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
- PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
+ PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */
+ PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
+ PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
+ PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
+ PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
+ PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
/* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
+ PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
/* on board NIC & Slot PCIE. */
diff --git a/src/mainboard/hp/abm/mainboard.c b/src/mainboard/hp/abm/mainboard.c
index aaa899b..b5156cc 100644
--- a/src/mainboard/hp/abm/mainboard.c
+++ b/src/mainboard/hp/abm/mainboard.c
@@ -21,6 +21,25 @@
#include <southbridge/amd/agesa/hudson/pci_devs.h>
#include <northbridge/amd/agesa/family16kb/pci_devs.h>
+#if 0
+static const u8 mainboard_picr_data[0x54] = {
+ 0x03, 0x04, 0x05, 0x07, 0x0B, 0x0A, 0x1F, 0x1F, 0xFA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
+ 0x1F, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x05, 0x04, 0x05, 0x04, 0x04, 0x05, 0x04, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x04, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x03, 0x04, 0x05, 0x07
+};
+static const u8 mainboard_intr_data[0x54] = {
+ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
+ 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x05, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x10, 0x11, 0x12, 0x13
+};
+#endif
+
/***********************************************************
* These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
* This table is responsible for physically routing the PIC and
@@ -33,21 +52,21 @@
* MP Tables. TODO: Make ACPI use these values too.
*/
static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = {
- [0x00] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B, /* INTA# - INTH# */
- [0x08] = 0x00,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
- [0x10] = 0x1F,0x1F,0x1F,0x0A,0x1F,0x1F,0x1F,0x0A, /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerfMon, SD */
- [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, /* IMC INT0 - 5 */
- [0x30] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A, /* USB Devs 18/19/20/22 INTA-C */
- [0x40] = 0x0B,0x0B, /* IDE, SATA */
+ [0x00] = 0x0A, 0x0B, 0x0A, 0x0B, 0x0A, 0x0B, 0x0A, 0x0B, /* INTA# - INTH# */
+ [0x08] = 0x00, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, /* Misc-nil, 0, 1, 2, INT from Serial irq */
+ [0x10] = 0x1F, 0x1F, 0x1F, 0x0A, 0x1F, 0x1F, 0x1F, 0x0A, /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerfMon, SD */
+ [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, /* IMC INT0 - 5 */
+ [0x30] = 0x0A, 0x0B, 0x0A, 0x0B, 0x0A, 0x0B, 0x0A, /* USB Devs 18/19/20/22 INTA-C */
+ [0x40] = 0x0B, 0x0B, /* IDE, SATA */
};
static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = {
- [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
- [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
- [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x10, /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon, SD */
- [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, /* IMC INT0 - 5 */
- [0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12, /* USB Devs 18/19/22/20 INTA-C */
- [0x40] = 0x11,0x13, /* IDE, SATA */
+ [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, /* INTA# - INTH# */
+ [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, /* Misc-nil, 0, 1, 2, INT from Serial irq */
+ [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x12, 0x1F, 0x10, /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon, SD */
+ [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, /* IMC INT0 - 5 */
+ [0x30] = 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, /* USB Devs 18/19/22/20 INTA-C */
+ [0x40] = 0x11, 0x13, /* IDE, SATA */
};
/*
diff --git a/src/mainboard/hp/abm/mptable.c b/src/mainboard/hp/abm/mptable.c
index 52374f1..7082013 100644
--- a/src/mainboard/hp/abm/mptable.c
+++ b/src/mainboard/hp/abm/mptable.c
@@ -14,30 +14,13 @@
*/
#include <arch/smp/mpspec.h>
-#include <arch/io.h>
#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <cpu/x86/lapic.h>
+#include <southbridge/amd/common/amd_pci_util.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
-u8 picr_data[0x54] = {
- 0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
- 0x1F,0x1F,0x1F,0x03,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x05,0x04,0x05,0x04,0x04,0x05,0x04,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x04,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x03,0x04,0x05,0x07
-};
-u8 intr_data[0x54] = {
- 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
- 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x10,0x11,0x12,0x13
-};
-
static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
{
mc->mpc_length += length;
@@ -60,7 +43,6 @@
{
struct mp_config_table *mc;
int bus_isa;
- u8 byte;
/*
* By the time this function gets called, the IOAPIC registers
@@ -87,17 +69,6 @@
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
- /* PIC IRQ routine */
- for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
- outb(byte, 0xC00);
- outb(picr_data[byte], 0xC01);
- }
-
- /* APIC IRQ routine */
- for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
- outb(byte | 0x80, 0xC00);
- outb(intr_data[byte], 0xC01);
- }
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
@@ -111,27 +82,27 @@
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
/* Internal VGA */
- PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
+ PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
+ PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
/* SMBUS */
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* HD Audio */
- PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]);
+ PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
/* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]);
- PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
- PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]);
+ PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
+ PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
+ PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
+ PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
+ PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
+ PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
+ PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
/* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]);
- PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
+ PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
+ PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
/* on board NIC & Slot PCIE. */
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c
index da450c6..d874bc2f 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c
+++ b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c
@@ -18,9 +18,27 @@
#include <arch/acpi.h>
#include <console/console.h>
#include <device/device.h>
+#include <southbridge/amd/common/amd_pci_util.h>
#include <southbridge/amd/agesa/hudson/smi.h>
+static const u8 mainboard_picr_data[0x54] = {
+ 0x1F, 0x1f, 0x1f, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x0A, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
+ 0x09, 0x1F, 0x1F, 0x0B, 0x1F, 0x0B, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x1F, 0x1F, 0x1F, 0x1F
+};
+static const u8 mainboard_intr_data[0x54] = {
+ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
+ 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x05, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x10, 0x11, 0x12, 0x13
+};
+
static void pavilion_cold_boot_init(void)
{
/* Lid SMI is only used in non-ACPI mode; leave it off in S3 resume */
@@ -29,9 +47,17 @@
pavilion_m6_1035dx_ec_init();
}
+/* PIRQ Setup */
+static void pirq_setup(void)
+{
+ intr_data_ptr = mainboard_intr_data;
+ picr_data_ptr = mainboard_picr_data;
+}
+
static void mainboard_enable(struct device *dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
+ pirq_setup();
hudson_configure_gevent_smi(EC_SMI_GEVENT, SMI_MODE_SMI, SMI_LVL_HIGH);
hudson_enable_smi_generation();
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c b/src/mainboard/hp/pavilion_m6_1035dx/mptable.c
index f3c2f0a..ecc57b0 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c
+++ b/src/mainboard/hp/pavilion_m6_1035dx/mptable.c
@@ -13,31 +13,14 @@
* GNU General Public License for more details.
*/
-#include <arch/io.h>
#include <arch/ioapic.h>
#include <arch/smp/mpspec.h>
#include <cpu/x86/lapic.h>
#include <stdint.h>
#include <string.h>
+#include <southbridge/amd/common/amd_pci_util.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
-u8 picr_data[0x54] = {
- 0x1F,0x1f,0x1f,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
- 0x09,0x1F,0x1F,0x0B,0x1F,0x0B,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x1F,0x1F,0x1F,0x1F
-};
-u8 intr_data[0x54] = {
- 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
- 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x10,0x11,0x12,0x13
-};
-
static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
{
mc->mpc_length += length;
@@ -60,7 +43,6 @@
{
struct mp_config_table *mc;
int bus_isa;
- u8 byte;
/*
* By the time this function gets called, the IOAPIC registers
@@ -86,18 +68,6 @@
/* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
- /* PIC IRQ routine */
- for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
- outb(byte, 0xC00);
- outb(picr_data[byte], 0xC01);
- }
-
- /* APIC IRQ routine */
- for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
- outb(byte | 0x80, 0xC00);
- outb(intr_data[byte], 0xC01);
- }
-
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
@@ -116,27 +86,27 @@
PCI_INT(0x0, 0x00, 0x3, 0x13);
/* Internal VGA */
- PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
+ PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
+ PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
/* SMBUS */
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* HD Audio */
- PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]);
+ PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
/* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]);
- PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
- PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]);
+ PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
+ PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
+ PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
+ PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
+ PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
+ PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
+ PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
/* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]);
- PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
+ PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
+ PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
/* on board NIC & Slot PCIE. */
diff --git a/src/mainboard/lenovo/g505s/mainboard.c b/src/mainboard/lenovo/g505s/mainboard.c
index c9e00b6..ff9db03 100644
--- a/src/mainboard/lenovo/g505s/mainboard.c
+++ b/src/mainboard/lenovo/g505s/mainboard.c
@@ -18,9 +18,28 @@
#include <arch/acpi.h>
#include <console/console.h>
#include <device/device.h>
+#include <southbridge/amd/common/amd_pci_util.h>
#include <southbridge/amd/agesa/hudson/smi.h>
+static const u8 mainboard_picr_data[0x54] = {
+ 0x1F, 0x1f, 0x1f, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x0A, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
+ 0x09, 0x1F, 0x1F, 0x0B, 0x1F, 0x0B, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x1F, 0x1F, 0x1F, 0x1F
+};
+static const u8 mainboard_intr_data[0x54] = {
+ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
+ 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x05, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x10, 0x11, 0x12, 0x13
+};
+
+
static void pavilion_cold_boot_init(void)
{
/* Lid SMI is only used in non-ACPI mode; leave it off in S3 resume */
@@ -29,9 +48,17 @@
lenovo_g505s_ec_init();
}
+/* PIRQ Setup */
+static void pirq_setup(void)
+{
+ intr_data_ptr = mainboard_intr_data;
+ picr_data_ptr = mainboard_picr_data;
+}
+
static void mainboard_enable(struct device *dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
+ pirq_setup();
hudson_configure_gevent_smi(EC_SMI_GEVENT, SMI_MODE_SMI, SMI_LVL_HIGH);
hudson_enable_smi_generation();
diff --git a/src/mainboard/lenovo/g505s/mptable.c b/src/mainboard/lenovo/g505s/mptable.c
index f3c2f0a..ecc57b0 100644
--- a/src/mainboard/lenovo/g505s/mptable.c
+++ b/src/mainboard/lenovo/g505s/mptable.c
@@ -13,31 +13,14 @@
* GNU General Public License for more details.
*/
-#include <arch/io.h>
#include <arch/ioapic.h>
#include <arch/smp/mpspec.h>
#include <cpu/x86/lapic.h>
#include <stdint.h>
#include <string.h>
+#include <southbridge/amd/common/amd_pci_util.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
-u8 picr_data[0x54] = {
- 0x1F,0x1f,0x1f,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
- 0x09,0x1F,0x1F,0x0B,0x1F,0x0B,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x1F,0x1F,0x1F,0x1F
-};
-u8 intr_data[0x54] = {
- 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
- 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x10,0x11,0x12,0x13
-};
-
static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
{
mc->mpc_length += length;
@@ -60,7 +43,6 @@
{
struct mp_config_table *mc;
int bus_isa;
- u8 byte;
/*
* By the time this function gets called, the IOAPIC registers
@@ -86,18 +68,6 @@
/* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
- /* PIC IRQ routine */
- for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
- outb(byte, 0xC00);
- outb(picr_data[byte], 0xC01);
- }
-
- /* APIC IRQ routine */
- for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
- outb(byte | 0x80, 0xC00);
- outb(intr_data[byte], 0xC01);
- }
-
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
@@ -116,27 +86,27 @@
PCI_INT(0x0, 0x00, 0x3, 0x13);
/* Internal VGA */
- PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
+ PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
+ PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
/* SMBUS */
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* HD Audio */
- PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]);
+ PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
/* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]);
- PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
- PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]);
+ PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
+ PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
+ PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
+ PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
+ PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
+ PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
+ PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
/* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]);
- PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
+ PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
+ PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
/* on board NIC & Slot PCIE. */
diff --git a/src/mainboard/lippert/frontrunner-af/mainboard.c b/src/mainboard/lippert/frontrunner-af/mainboard.c
index 9e3eab7..56972d4 100644
--- a/src/mainboard/lippert/frontrunner-af/mainboard.c
+++ b/src/mainboard/lippert/frontrunner-af/mainboard.c
@@ -17,6 +17,7 @@
#include <amdblocks/acpimmio.h>
#include <console/console.h>
#include <device/device.h>
+#include <southbridge/amd/common/amd_pci_util.h>
#include <arch/io.h>
#include <device/mmio.h>
#include <device/pci_ops.h>
@@ -26,6 +27,16 @@
#include <southbridge/amd/cimx/sb800/gpio_oem.h>
#include "sema.h"
+static const u8 mainboard_intr_data[] = {
+ [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, /* INTA# - INTH# */
+ [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, /* Misc-nil, 0, 1, 2, INT from Serial irq */
+ [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x12, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x10, 0x11, 0x12, 0x13
+};
+
/* Init SIO GPIOs. */
#define SIO_RUNTIME_BASE 0x0E00
static const u16 sio_init_table[] = { // hi = offset, lo = value
@@ -57,6 +68,12 @@
0x5780, // GP65: USB power 4/5 = open drain output
};
+/* PIRQ Setup */
+static void pirq_setup(void)
+{
+ intr_data_ptr = mainboard_intr_data;
+}
+
static void init(struct device *dev)
{
volatile u8 *spi_base; /* base addr of Hudson's SPI host controller */
diff --git a/src/mainboard/lippert/frontrunner-af/mptable.c b/src/mainboard/lippert/frontrunner-af/mptable.c
index 347b781..78b8ec2 100644
--- a/src/mainboard/lippert/frontrunner-af/mptable.c
+++ b/src/mainboard/lippert/frontrunner-af/mptable.c
@@ -14,22 +14,11 @@
*/
#include <arch/smp/mpspec.h>
-#include <arch/io.h>
#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-u8 intr_data[] = {
- [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
- [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
- [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x10,0x11,0x12,0x13
-};
-
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
@@ -55,13 +44,6 @@
/* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
- u8 byte;
-
- for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
- outb(byte | 0x80, 0xC00);
- outb(intr_data[byte], 0xC01);
- }
-
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
@@ -75,23 +57,23 @@
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
/* APU Internal Graphic Device*/
- PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
+ PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
+ PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
//PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* Southbridge HD Audio: */
PCI_INT(0x0, 0x14, 0x2, 0x12);
- PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
- PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
+ PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */
+ PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
+ PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
+ PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
+ PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
+ PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
/* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
+ PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
/* on board NIC & Slot PCIE. */
diff --git a/src/mainboard/lippert/toucan-af/mainboard.c b/src/mainboard/lippert/toucan-af/mainboard.c
index 158613f..e8fc09a 100644
--- a/src/mainboard/lippert/toucan-af/mainboard.c
+++ b/src/mainboard/lippert/toucan-af/mainboard.c
@@ -17,6 +17,7 @@
#include <amdblocks/acpimmio.h>
#include <console/console.h>
#include <device/device.h>
+#include <southbridge/amd/common/amd_pci_util.h>
#include <device/mmio.h>
#include <device/pci_ops.h>
#include <device/pci_def.h>
@@ -25,6 +26,16 @@
#include <southbridge/amd/cimx/sb800/gpio_oem.h>
#include "mainboard/lippert/frontrunner-af/sema.h"
+static const u8 mainboard_intr_data[] = {
+ [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, /* INTA# - INTH# */
+ [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, /* Misc-nil, 0, 1, 2, INT from Serial irq */
+ [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x12, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x10, 0x11, 0x12, 0x13
+};
+
static void init(struct device *dev)
{
volatile u8 *spi_base; /* base addr of Hudson's SPI host controller */
@@ -95,6 +106,12 @@
printk(BIOS_DEBUG, CONFIG_MAINBOARD_PART_NUMBER " EXIT %s\n", __func__);
}
+/* PIRQ Setup */
+static void pirq_setup(void)
+{
+ intr_data_ptr = mainboard_intr_data;
+}
+
/**********************************************
* Enable the dedicated functions of the board.
**********************************************/
diff --git a/src/mainboard/lippert/toucan-af/mptable.c b/src/mainboard/lippert/toucan-af/mptable.c
index 347b781..78b8ec2 100644
--- a/src/mainboard/lippert/toucan-af/mptable.c
+++ b/src/mainboard/lippert/toucan-af/mptable.c
@@ -14,22 +14,11 @@
*/
#include <arch/smp/mpspec.h>
-#include <arch/io.h>
#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-u8 intr_data[] = {
- [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
- [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
- [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x10,0x11,0x12,0x13
-};
-
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
@@ -55,13 +44,6 @@
/* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
- u8 byte;
-
- for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
- outb(byte | 0x80, 0xC00);
- outb(intr_data[byte], 0xC01);
- }
-
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
@@ -75,23 +57,23 @@
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
/* APU Internal Graphic Device*/
- PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
+ PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
+ PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
//PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* Southbridge HD Audio: */
PCI_INT(0x0, 0x14, 0x2, 0x12);
- PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
- PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
+ PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */
+ PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
+ PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
+ PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
+ PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
+ PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
/* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
+ PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
/* on board NIC & Slot PCIE. */
diff --git a/src/mainboard/msi/ms7721/mainboard.c b/src/mainboard/msi/ms7721/mainboard.c
index 2a0e618..719039f 100644
--- a/src/mainboard/msi/ms7721/mainboard.c
+++ b/src/mainboard/msi/ms7721/mainboard.c
@@ -17,6 +17,31 @@
#include <cpu/x86/msr.h>
#include <cpu/amd/msr.h>
#include <device/device.h>
+#include <southbridge/amd/common/amd_pci_util.h>
+
+static const u8 mainboard_picr_data[] = {
+ 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x0A, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
+ 0x09, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x1F, 0x1F, 0x1F, 0x1F
+};
+static const u8 mainboard_intr_data[0x54] = {
+ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
+ 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x05, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x10, 0x11, 0x12, 0x13
+};
+
+/* PIRQ Setup */
+static void pirq_setup(void)
+{
+ intr_data_ptr = mainboard_intr_data;
+ picr_data_ptr = mainboard_picr_data;
+}
/*************************************************
* enable the dedicated function in thatcher board.
@@ -26,6 +51,7 @@
msr_t msr;
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
+ pirq_setup();
msr = rdmsr(LS_CFG_MSR);
msr.lo &= ~(1 << 28);
diff --git a/src/mainboard/msi/ms7721/mptable.c b/src/mainboard/msi/ms7721/mptable.c
index 303f3bf..fd55eda 100644
--- a/src/mainboard/msi/ms7721/mptable.c
+++ b/src/mainboard/msi/ms7721/mptable.c
@@ -13,31 +13,14 @@
* GNU General Public License for more details.
*/
-#include <arch/io.h>
#include <arch/ioapic.h>
#include <arch/smp/mpspec.h>
#include <cpu/x86/lapic.h>
#include <stdint.h>
#include <string.h>
+#include <southbridge/amd/common/amd_pci_util.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
-u8 picr_data[] = {
- 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
- 0x09,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x1F,0x1F,0x1F,0x1F
-};
-u8 intr_data[0x54] = {
- 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
- 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x10,0x11,0x12,0x13
-};
-
static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
{
mc->mpc_length += length;
@@ -60,7 +43,6 @@
{
struct mp_config_table *mc;
int bus_isa;
- u8 byte;
/*
* By the time this function gets called, the IOAPIC registers
@@ -86,18 +68,6 @@
/* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
- /* PIC IRQ routine */
- for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
- outb(byte, 0xC00);
- outb(picr_data[byte], 0xC01);
- }
-
- /* APIC IRQ routine */
- for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
- outb(byte | 0x80, 0xC00);
- outb(intr_data[byte], 0xC01);
- }
-
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
@@ -116,27 +86,27 @@
PCI_INT(0x0, 0x0, 0x3, 0x13);
/* Internal VGA */
- PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
+ PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
+ PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
/* SMBUS */
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* HD Audio */
- PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]);
+ PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
/* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]);
- PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
- PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]);
+ PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
+ PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
+ PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
+ PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
+ PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
+ PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
+ PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
/* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]);
- PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
+ PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
+ PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
/* on board NIC & Slot PCIE. */
--
To view, visit https://review.coreboot.org/c/coreboot/+/38564
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ibce2af4de91549c4c9743cd997f625164672a713
Gerrit-Change-Number: 38564
Gerrit-PatchSet: 1
Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Gerrit-MessageType: newchange
1 week, 4 days
- 4
- 17
Change in coreboot[master]: device/pci: Ensure full 16-bit VGA port i/o decoding
by Nico Huber (Code Review)
Hello Kyösti Mälkki, Patrick Rudolph, Michael Niewöhner,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/35516
to review the following change.
Change subject: device/pci: Ensure full 16-bit VGA port i/o decoding
......................................................................
device/pci: Ensure full 16-bit VGA port i/o decoding
So, the PCI to PCI bridge specification had a pitfall for us:
Originally, when decoding i/o ports for legacy VGA cycles, bridges
should only consider the 10 least significant bits of the port address.
This means all VGA registers were aliased every 1024 ports!
e.g. 0x3b0 was also decoded as 0x7b0, 0xbb0 etc.
However, it seems, we never reserved the aliased ports, resulting in
random conflicts. We neither use much external VGA nor many i/o ports
these days, so nobody noticed.
To avoid this mess, a bridge control bit (VGA16) was introduced in
2003 to enable decoding of 16-bit port addresses. As we don't want
to clutter our i/o port space, we'll now simply fail for VGA behind
bridges that don't support it. Famous last words: I assume there
can't be many bridges left that don't support this bit ;)
Change-Id: Id7a07f069dd54331df79f605c6bcda37882a602d
Signed-off-by: Nico Huber <nico.h(a)gmx.de>
---
M src/device/device.c
M src/device/pci_device.c
M src/include/device/device.h
M src/include/device/pci_def.h
4 files changed, 48 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/35516/1
diff --git a/src/device/device.c b/src/device/device.c
index 44d1f95..523bd1c 100644
--- a/src/device/device.c
+++ b/src/device/device.c
@@ -757,6 +757,12 @@
while ((dev = dev_find_class(PCI_CLASS_DISPLAY_VGA << 8, dev))) {
if (!dev->enabled)
continue;
+ if (dev->bus->no_vga) {
+ printk(BIOS_WARNING, "Ignoring VGA at %s"
+ ", a bridge on the path isn't supported",
+ dev_path(dev));
+ continue;
+ }
printk(BIOS_DEBUG, "found VGA at %s\n", dev_path(dev));
@@ -797,7 +803,7 @@
while (bus) {
printk(BIOS_DEBUG, "Setting PCI_BRIDGE_CTL_VGA for bridge %s\n",
dev_path(bus->dev));
- bus->bridge_ctrl |= PCI_BRIDGE_CTL_VGA;
+ bus->bridge_ctrl |= PCI_BRIDGE_CTL_VGA | PCI_BRIDGE_CTL_VGA16;
bus = (bus == bus->dev->bus) ? 0 : bus->dev->bus;
}
}
diff --git a/src/device/pci_device.c b/src/device/pci_device.c
index 7ecb652..2fadb55 100644
--- a/src/device/pci_device.c
+++ b/src/device/pci_device.c
@@ -788,6 +788,43 @@
};
/**
+ * Check for compatibility to route legacy VGA cycles through a bridge.
+ *
+ * Originally, when decoding i/o ports for legacy VGA cycles, bridges
+ * should only consider the 10 least significant bits of the port address.
+ * This means all VGA registers were aliased every 1024 ports!
+ * e.g. 0x3b0 was also decoded as 0x7b0, 0xbb0 etc.
+ *
+ * To avoid this mess, a bridge control bit (VGA16) was introduced in
+ * 2003 to enable decoding of 16-bit port addresses. As we don't want
+ * to clutter our i/o port space, we simply fail for VGA behind bridges
+ * that don't support it (set .no_vga = 1).
+ */
+static void pci_bridge_vga_compat(struct bus *const bus)
+{
+ uint16_t bridge_ctrl;
+
+ bridge_ctrl = pci_read_config16(bus->dev, PCI_BRIDGE_CONTROL);
+
+ /* Ensure VGA decoding is disabled during probing (it should
+ be by default, but we run blobs nowadays) */
+ bridge_ctrl &= ~PCI_BRIDGE_CTL_VGA;
+ pci_write_config16(bus->dev, PCI_BRIDGE_CONTROL, bridge_ctrl);
+
+ /* If the upstream bridge doesn't support VGA, we don't have to check */
+ bus->no_vga |= bus->dev->bus->no_vga;
+ if (bus->no_vga)
+ return;
+
+ /* Test if we can enable 16-bit decoding */
+ bridge_ctrl |= PCI_BRIDGE_CTL_VGA16;
+ pci_write_config16(bus->dev, PCI_BRIDGE_CONTROL, bridge_ctrl);
+ bridge_ctrl = pci_read_config16(bus->dev, PCI_BRIDGE_CONTROL);
+
+ bus->no_vga = !(bridge_ctrl & PCI_BRIDGE_CTL_VGA16);
+}
+
+/**
* Detect the type of downstream bridge.
*
* This function is a heuristic to detect which type of bus is downstream
@@ -1288,6 +1325,8 @@
bus = dev->link_list;
+ pci_bridge_vga_compat(bus);
+
pci_bridge_route(bus, PCI_ROUTE_SCAN);
do_scan_bus(bus, 0x00, 0xff);
diff --git a/src/include/device/device.h b/src/include/device/device.h
index b2221cc..78e234e 100644
--- a/src/include/device/device.h
+++ b/src/include/device/device.h
@@ -94,6 +94,7 @@
unsigned int reset_needed : 1;
unsigned int disable_relaxed_ordering : 1;
unsigned int ht_link_up : 1;
+ unsigned int no_vga : 1; /* We can't support VGA behind this bridge */
};
/*
diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h
index bc5bc79..c8b86d5 100644
--- a/src/include/device/pci_def.h
+++ b/src/include/device/pci_def.h
@@ -138,6 +138,7 @@
#define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
#define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */
#define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
+#define PCI_BRIDGE_CTL_VGA16 0x10 /* Enable 16-bit i/o port decoding */
#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
#define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
/* Fast Back2Back enabled on secondary interface */
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Id7a07f069dd54331df79f605c6bcda37882a602d
Gerrit-Change-Number: 35516
Gerrit-PatchSet: 1
Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Gerrit-Reviewer: Michael Niewöhner
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-MessageType: newchange
1 week, 5 days
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