March 2020 - coreboot-gerrit - mail.coreboot.org

Change in coreboot[master]: util/inteltool: fix Ie00fef5a5ba2779e0ff45640cff5cc9f1d096dc1 on FreeBSD

by Idwer Vollering (Code Review)

Idwer Vollering has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37767 ) Change subject: util/inteltool: fix Ie00fef5a5ba2779e0ff45640cff5cc9f1d096dc1 on FreeBSD ...................................................................... util/inteltool: fix Ie00fef5a5ba2779e0ff45640cff5cc9f1d096dc1 on FreeBSD Change-Id: I4aba72f39b528fd70451a4656fd6c835ff766e49 Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- M util/inteltool/Makefile M util/inteltool/inteltool.h 2 files changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/37767/1 diff --git a/util/inteltool/Makefile b/util/inteltool/Makefile index cd02fa8..918b6ec 100644 --- a/util/inteltool/Makefile +++ b/util/inteltool/Makefile @@ -23,6 +23,7 @@ INSTALL ?= /usr/bin/env install PREFIX ?= /usr/local CFLAGS ?= -O2 -g -Wall -Wextra -Wmissing-prototypes +CFLAGS += -Wno-unused-function LDFLAGS += -lpci -lz CPPFLAGS += -I$(top)/src/commonlib/include diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index fc6dc4b..81ebc72 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -370,7 +370,7 @@ #define rdmsr freebsd_rdmsr #define wrmsr freebsd_wrmsr typedef struct { uint32_t hi, lo; } msr_t; -msr_t freebsd_rdmsr(int addr); +static msr_t freebsd_rdmsr(int addr); int freebsd_wrmsr(int addr, msr_t msr); #endif typedef struct { uint16_t addr; int size; char *name; } io_register_t; -- To view, visit https://review.coreboot.org/c/coreboot/+/37767 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4aba72f39b528fd70451a4656fd6c835ff766e49 Gerrit-Change-Number: 37767 Gerrit-PatchSet: 1 Gerrit-Owner: Idwer Vollering <vidwer(a)gmail.com> Gerrit-MessageType: newchange

6 hours, 52 minutes

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Change in coreboot[master]: Documentation: Use correct MiB units instead of MB

by Evgeny Zinoviev (Code Review)

Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39685 ) Change subject: Documentation: Use correct MiB units instead of MB ...................................................................... Documentation: Use correct MiB units instead of MB Fix a common mistake of using MB where MiB is what actually is meant. 1 MB = (10^3)^2 = 1000000 1 MiB = (2^10)^2 = 1048576 Change-Id: I78327652b6c6526318071a9d4bafd7ec279ea614 Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- M Documentation/ifdtool/layout.md M Documentation/mainboard/facebook/monolith.md M Documentation/mainboard/hp/8760w.md M Documentation/mainboard/intel/kblrvp11.md M Documentation/mainboard/lenovo/montevina_series.md M Documentation/mainboard/lenovo/t440p.md M Documentation/mainboard/msi/ms7707/ms7707.md M Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md 8 files changed, 21 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/39685/1 diff --git a/Documentation/ifdtool/layout.md b/Documentation/ifdtool/layout.md index 2513929..77319b8 100644 --- a/Documentation/ifdtool/layout.md +++ b/Documentation/ifdtool/layout.md @@ -19,7 +19,7 @@ | IFD Region | IFD Region name | FMAP Name | Notes | | index | | | | +============+==================+===========+===========================================+ -| 0 | Flash Descriptor | SI_DESC | Always the top 4KB of flash | +| 0 | Flash Descriptor | SI_DESC | Always the top 4 KiB of flash | +------------+------------------+-----------+-------------------------------------------+ | 1 | BIOS | SI_BIOS | This is the region that contains coreboot | +------------+------------------+-----------+-------------------------------------------+ @@ -40,9 +40,9 @@ The ifdtool can be used to manipulate a firmware image with a IFD. This tool will not take into account the FMAP while modifying the image which can lead to unexpected and hard to debug issues with the firmware image. For example if the -ME region is defined at 6 MB in the IFD but the FMAP only allocates 4 MB for the -ME, then when the ME is added by the ifdtool 6 MB will be written which could -overwrite 2 MB of the BIOS. +ME region is defined at 6 MiB in the IFD but the FMAP only allocates 4 MiB for +the ME, then when the ME is added by the ifdtool 6 MiB will be written which +could overwrite 2 MiB of the BIOS. In order to validate that the FMAP and the IFD are compatible the ifdtool provides --validate (-t) option. `ifdtool -t` will read both the IFD and the @@ -75,4 +75,4 @@ FMAP area SI_PDR: offset: 0x007fc000 length: 0x00004000 -``` \ No newline at end of file +``` diff --git a/Documentation/mainboard/facebook/monolith.md b/Documentation/mainboard/facebook/monolith.md index cdd3208..a775395 100644 --- a/Documentation/mainboard/facebook/monolith.md +++ b/Documentation/mainboard/facebook/monolith.md @@ -41,8 +41,8 @@ 00003000:006FFFFF me 00001000:00002fff gbe ``` -3) Use `ifdtool -n <layout_file> <flash_image>` to resize the *bios* region from the default 6MB - to 9 MB, this is required to create sufficient space for LinuxBoot. +3) Use `ifdtool -n <layout_file> <flash_image>` to resize the *bios* region from the default 6 MiB + to 9 MiB, this is required to create sufficient space for LinuxBoot. NOTE: Please make sure only the firmware descriptor (*fd*) region is changed. Older versions of the ifdtool corrupt the *me* region. 4) Use `ifdtool -x <resized_flash_image>` to extract the components. diff --git a/Documentation/mainboard/hp/8760w.md b/Documentation/mainboard/hp/8760w.md index 714745a..7e5c0ca 100644 --- a/Documentation/mainboard/hp/8760w.md +++ b/Documentation/mainboard/hp/8760w.md @@ -33,7 +33,7 @@ ## Flashing instructions -HP EliteBook 8760w has an 8MB SOIC-8 flash chip on the bottom of the +HP EliteBook 8760w has an 8 MiB SOIC-8 flash chip on the bottom of the mainboard. You just need to remove the service cover, and use an SOIC-8 clip to read and flash the chip. diff --git a/Documentation/mainboard/intel/kblrvp11.md b/Documentation/mainboard/intel/kblrvp11.md index 4ccb392..d536bea 100644 --- a/Documentation/mainboard/intel/kblrvp11.md +++ b/Documentation/mainboard/intel/kblrvp11.md @@ -60,7 +60,7 @@ 2. Make sure power supply is disconnected from board. 3. Connect Dediprog SF600 to header at J7H1. 4. Ensure that "currently working on" is in "application memory chip 1" -5. Go to "file" and select the .rom file (16 MB) to program chip1. +5. Go to "file" and select the .rom file (16 MiB) to program chip1. 6. Execute the batch operation to erase and program the chip. ## Technology diff --git a/Documentation/mainboard/lenovo/montevina_series.md b/Documentation/mainboard/lenovo/montevina_series.md index 62e8796..94836d5 100644 --- a/Documentation/mainboard/lenovo/montevina_series.md +++ b/Documentation/mainboard/lenovo/montevina_series.md @@ -44,7 +44,7 @@ ```eval_rst +---------------------------+---------------------------+---------------------------+ -| 4 MB chip | 8 MB chip | 16 MB chip | +| 4 MiB chip | 8 MiB chip | 16 MiB chip | +===========================+===========================+===========================+ | .. code-block:: none | .. code-block:: none | .. code-block:: none | | | | | @@ -88,12 +88,12 @@ $ make ``` -If your flash is not 8 MB, you need to change values of `flcomp_density1` and +If your flash is not 8 MiB, you need to change values of `flcomp_density1` and `flreg1_limit` in the ifd-x200.set file according to following table: ```eval_rst +-----------------+-------+-------+--------+ -| | 4 MB | 8 MB | 16 MB | +| | 4 MiB | 8 MiB | 16 MiB | +=================+=======+=======+========+ | flcomp_density1 | 0x3 | 0x4 | 0x5 | +-----------------+-------+-------+--------+ @@ -114,7 +114,7 @@ ``` Mainboard ---> ROM chip size (8192 KB (8 MB)) # According to your chip - (0x7fd000) Size of CBFS filesystem in ROM # or 0x3fd000 for 4 MB chip / 0x1ffd000 for 16 MB chip + (0x7fd000) Size of CBFS filesystem in ROM # or 0x3fd000 for 4 MiB chip / 0x1ffd000 for 16 MiB chip Chipset ---> [*] Add Intel descriptor.bin file @@ -142,7 +142,7 @@ ```eval_rst +---------------------------------+---------------------------------+ -| 4 MB chip | 8 MB chip | +| 4 MiB chip | 8 MiB chip | +=================================+=================================+ | .. code-block:: none | .. code-block:: none | | | | @@ -159,6 +159,6 @@ On each boot of vendor BIOS `ec` area in flash is checked for having firmware there, and if there is one, it proceedes to update firmware on H8S/2116 (when both external power and main battery are attached). Once update is performed, -first 64 KB of `ec` area is erased. Visit +first 64 KiB of `ec` area is erased. Visit [thinkpad-ec repository](https://github.com/hamishcoleman/thinkpad-ec) to learn more about how to extract EC firmware from vendor updates. diff --git a/Documentation/mainboard/lenovo/t440p.md b/Documentation/mainboard/lenovo/t440p.md index fb01870..ffc5808 100644 --- a/Documentation/mainboard/lenovo/t440p.md +++ b/Documentation/mainboard/lenovo/t440p.md @@ -8,15 +8,15 @@ ## Flashing instructions -T440p has two flash chips, an 8MB W25Q64FV and a 4MB W25Q32FV. To flash +T440p has two flash chips, an 8 MiB W25Q64FV and a 4 MiB W25Q32FV. To flash coreboot, you just need to remove the big door according to the T440 -[Hardware Maintenance Manual] and flash the 4MB chip. +[Hardware Maintenance Manual] and flash the 4 MiB chip. ![T440p flash chip](t440p_flash_chip.jpg) -To access the 8MB chip, you need to remove the base cover. +To access the 8 MiB chip, you need to remove the base cover. -![T440p 8MB flash chip](t440p_all_flash_chips.jpg) +![T440p 8 MiB flash chip](t440p_all_flash_chips.jpg) The flash layout of the OEM firmware is as follows: diff --git a/Documentation/mainboard/msi/ms7707/ms7707.md b/Documentation/mainboard/msi/ms7707/ms7707.md index c27ff60..83b860c 100644 --- a/Documentation/mainboard/msi/ms7707/ms7707.md +++ b/Documentation/mainboard/msi/ms7707/ms7707.md @@ -2,7 +2,7 @@ * MSI MS-7707 V1.1 (Medion OEM Akoya P4385D MSN10014555) * SandyBridge Intel P67 (BD82x6x) -* Winbond 25Q32BV (4MB) +* Winbond 25Q32BV (4 MiB) * Fintek F71808A SuperIO * Intel 82579V Gigabit * NEC uPD720200 USB 3.0 Host Controller diff --git a/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md b/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md index 2cb945a..56ec4be 100644 --- a/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md +++ b/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md @@ -17,7 +17,7 @@ ## De-blobbing - [Intel FSP2.0] can not be removed as long as there is no free replacement -- Intel ME can be cleaned using me_cleaner (~4.5 MB more free space) +- Intel ME can be cleaned using me_cleaner (~4.5 MiB more free space) - Intel Ethernet Controller Firmware can be removed when it's extended functionality is not needed. For more details refer to the respective datasheet (e.g 333016-008 for I210). - Boards with [AST2400] BMC/IPMI: Firmware can be replaced by [OpenBMC] -- To view, visit https://review.coreboot.org/c/coreboot/+/39685 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78327652b6c6526318071a9d4bafd7ec279ea614 Gerrit-Change-Number: 39685 Gerrit-PatchSet: 1 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-MessageType: newchange

8 hours, 22 minutes

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Change in coreboot[master]: src/soc/intel/cannonlake: Configure top swap based on ucode version

by Varshit B Pandya (Code Review)

Varshit B Pandya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34656 ) Change subject: src/soc/intel/cannonlake: Configure top swap based on ucode version ...................................................................... src/soc/intel/cannonlake: Configure top swap based on ucode version Disable top swap if ucode version is 0(invalid) Change-Id: I0ed2ca9e350acf0385ce5d790d319235df6c9f21 --- M src/soc/intel/cannonlake/bootblock/cpu.c 1 file changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/34656/1 diff --git a/src/soc/intel/cannonlake/bootblock/cpu.c b/src/soc/intel/cannonlake/bootblock/cpu.c index f60f319..c96bca8 100644 --- a/src/soc/intel/cannonlake/bootblock/cpu.c +++ b/src/soc/intel/cannonlake/bootblock/cpu.c @@ -14,14 +14,39 @@ * GNU General Public License for more details. */ +#include <arch/cpu.h> +#include <cpu/x86/msr.h> #include <intelblocks/cpulib.h> #include <intelblocks/fast_spi.h> +#include <intelblocks/rtc.h> +#include <reset.h> #include <soc/bootblock.h> +#define BIOS_SIGN_ID 0x8B + +static void check_ucode_and_update_top_swap(void) +{ + /* Code to check the MCU version and Update TS */ + msr_t microcode_ver; + unsigned int cpu_id; + microcode_ver.lo = 0; + microcode_ver.hi = 0; + wrmsr(BIOS_SIGN_ID, microcode_ver); + cpu_id = cpu_get_cpuid(); + microcode_ver = rdmsr(BIOS_SIGN_ID); + if (microcode_ver.hi == 0x0) { + configure_rtc_buc_top_swap(TS_DISABLE); + do_board_reset(); + } +} + void bootblock_cpu_init(void) { /* Temporarily cache the memory-mapped boot media. */ if (CONFIG(BOOT_DEVICE_MEMORY_MAPPED) && CONFIG(BOOT_DEVICE_SPI_FLASH)) fast_spi_cache_bios_region(); + + /* Code to check the MCU version and Update TS */ + check_ucode_and_update_top_swap(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/34656 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ed2ca9e350acf0385ce5d790d319235df6c9f21 Gerrit-Change-Number: 34656 Gerrit-PatchSet: 1 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-MessageType: newchange

1 day, 17 hours

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Change in em100[master]: WIP: Parse command table from installer file

by Stefan Reinauer (Code Review)

Stefan Reinauer has uploaded this change for review. ( https://review.coreboot.org/c/em100/+/37538 ) Change subject: WIP: Parse command table from installer file ...................................................................... WIP: Parse command table from installer file Change-Id: I126a16e2ae5d5b9df5846d9bef45fde307751c05 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- M Makefile A ini.c A ini.h M trace.c 4 files changed, 527 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/em100 refs/changes/38/37538/1 diff --git a/Makefile b/Makefile index fd1be91..7f90cef 100644 --- a/Makefile +++ b/Makefile @@ -36,7 +36,7 @@ XZ = xz/xz_crc32.c xz/xz_crc64.c xz/xz_dec_bcj.c xz/xz_dec_lzma2.c xz/xz_dec_stream.c SOURCES = em100.c firmware.c fpga.c hexdump.c sdram.c spi.c system.c trace.c usb.c -SOURCES += image.c curl.c chips.c tar.c $(XZ) +SOURCES += image.c curl.c chips.c tar.c ini.c $(XZ) OBJECTS = $(SOURCES:.c=.o) all: dep em100 diff --git a/ini.c b/ini.c new file mode 100644 index 0000000..b4d5921 --- /dev/null +++ b/ini.c @@ -0,0 +1,284 @@ +/* inih -- simple .INI file parser + +SPDX-License-Identifier: BSD-3-Clause + +Copyright (C) 2009-2019, Ben Hoyt + +inih is released under the New BSD license (see LICENSE.txt). Go to the project +home page for more info: + +https://github.com/benhoyt/inih + +*/ + +#if defined(_MSC_VER) && !defined(_CRT_SECURE_NO_WARNINGS) +#define _CRT_SECURE_NO_WARNINGS +#endif + +#include <stdio.h> +#include <ctype.h> +#include <string.h> + +#include "ini.h" + +#if !INI_USE_STACK +#include <stdlib.h> +#endif + +#define MAX_SECTION 50 +#define MAX_NAME 50 + +/* Used by ini_parse_string() to keep track of string parsing state. */ +typedef struct { + const char* ptr; + size_t num_left; +} ini_parse_string_ctx; + +/* Strip whitespace chars off end of given string, in place. Return s. */ +static char* rstrip(char* s) +{ + char* p = s + strlen(s); + while (p > s && isspace((unsigned char)(*--p))) + *p = '\0'; + return s; +} + +/* Return pointer to first non-whitespace char in given string. */ +static char* lskip(const char* s) +{ + while (*s && isspace((unsigned char)(*s))) + s++; + return (char*)s; +} + +/* Return pointer to first char (of chars) or inline comment in given string, + or pointer to null at end of string if neither found. Inline comment must + be prefixed by a whitespace character to register as a comment. */ +static char* find_chars_or_comment(const char* s, const char* chars) +{ +#if INI_ALLOW_INLINE_COMMENTS + int was_space = 0; + while (*s && (!chars || !strchr(chars, *s)) && + !(was_space && strchr(INI_INLINE_COMMENT_PREFIXES, *s))) { + was_space = isspace((unsigned char)(*s)); + s++; + } +#else + while (*s && (!chars || !strchr(chars, *s))) { + s++; + } +#endif + return (char*)s; +} + +/* Version of strncpy that ensures dest (size bytes) is null-terminated. */ +static char* strncpy0(char* dest, const char* src, size_t size) +{ + strncpy(dest, src, size - 1); + dest[size - 1] = '\0'; + return dest; +} + +/* See documentation in header file. */ +int ini_parse_stream(ini_reader reader, void* stream, ini_handler handler, + void* user) +{ + /* Uses a fair bit of stack (use heap instead if you need to) */ +#if INI_USE_STACK + char line[INI_MAX_LINE]; + int max_line = INI_MAX_LINE; +#else + char* line; + size_t max_line = INI_INITIAL_ALLOC; +#endif +#if INI_ALLOW_REALLOC && !INI_USE_STACK + char* new_line; + size_t offset; +#endif + char section[MAX_SECTION] = ""; + char prev_name[MAX_NAME] = ""; + + char* start; + char* end; + char* name; + char* value; + int lineno = 0; + int error = 0; + +#if !INI_USE_STACK + line = (char*)malloc(INI_INITIAL_ALLOC); + if (!line) { + return -2; + } +#endif + +#if INI_HANDLER_LINENO +#define HANDLER(u, s, n, v) handler(u, s, n, v, lineno) +#else +#define HANDLER(u, s, n, v) handler(u, s, n, v) +#endif + + /* Scan through stream line by line */ + while (reader(line, (int)max_line, stream) != NULL) { +#if INI_ALLOW_REALLOC && !INI_USE_STACK + offset = strlen(line); + while (offset == max_line - 1 && line[offset - 1] != '\n') { + max_line *= 2; + if (max_line > INI_MAX_LINE) + max_line = INI_MAX_LINE; + new_line = realloc(line, max_line); + if (!new_line) { + free(line); + return -2; + } + line = new_line; + if (reader(line + offset, (int)(max_line - offset), stream) == NULL) + break; + if (max_line >= INI_MAX_LINE) + break; + offset += strlen(line + offset); + } +#endif + + lineno++; + + start = line; +#if INI_ALLOW_BOM + if (lineno == 1 && (unsigned char)start[0] == 0xEF && + (unsigned char)start[1] == 0xBB && + (unsigned char)start[2] == 0xBF) { + start += 3; + } +#endif + start = lskip(rstrip(start)); + + if (strchr(INI_START_COMMENT_PREFIXES, *start)) { + /* Start-of-line comment */ + } +#if INI_ALLOW_MULTILINE + else if (*prev_name && *start && start > line) { + /* Non-blank line with leading whitespace, treat as continuation + of previous name's value (as per Python configparser). */ + if (!HANDLER(user, section, prev_name, start) && !error) + error = lineno; + } +#endif + else if (*start == '[') { + /* A "[section]" line */ + end = find_chars_or_comment(start + 1, "]"); + if (*end == ']') { + *end = '\0'; + strncpy0(section, start + 1, sizeof(section)); + *prev_name = '\0'; +#if INI_CALL_HANDLER_ON_NEW_SECTION + if (!HANDLER(user, section, NULL, NULL) && !error) + error = lineno; +#endif + } + else if (!error) { + /* No ']' found on section line */ + error = lineno; + } + } + else if (*start) { + /* Not a comment, must be a name[=:]value pair */ + end = find_chars_or_comment(start, "=:"); + if (*end == '=' || *end == ':') { + *end = '\0'; + name = rstrip(start); + value = end + 1; +#if INI_ALLOW_INLINE_COMMENTS + end = find_chars_or_comment(value, NULL); + if (*end) + *end = '\0'; +#endif + value = lskip(value); + rstrip(value); + + /* Valid name[=:]value pair found, call handler */ + strncpy0(prev_name, name, sizeof(prev_name)); + if (!HANDLER(user, section, name, value) && !error) + error = lineno; + } + else if (!error) { + /* No '=' or ':' found on name[=:]value line */ +#if INI_ALLOW_NO_VALUE + *end = '\0'; + name = rstrip(start); + if (!HANDLER(user, section, name, NULL) && !error) + error = lineno; +#else + error = lineno; +#endif + } + } + +#if INI_STOP_ON_FIRST_ERROR + if (error) + break; +#endif + } + +#if !INI_USE_STACK + free(line); +#endif + + return error; +} + +/* See documentation in header file. */ +int ini_parse_file(FILE* file, ini_handler handler, void* user) +{ + return ini_parse_stream((ini_reader)fgets, file, handler, user); +} + +/* See documentation in header file. */ +int ini_parse(const char* filename, ini_handler handler, void* user) +{ + FILE* file; + int error; + + file = fopen(filename, "r"); + if (!file) + return -1; + error = ini_parse_file(file, handler, user); + fclose(file); + return error; +} + +/* An ini_reader function to read the next line from a string buffer. This + is the fgets() equivalent used by ini_parse_string(). */ +static char* ini_reader_string(char* str, int num, void* stream) { + ini_parse_string_ctx* ctx = (ini_parse_string_ctx*)stream; + const char* ctx_ptr = ctx->ptr; + size_t ctx_num_left = ctx->num_left; + char* strp = str; + char c; + + if (ctx_num_left == 0 || num < 2) + return NULL; + + while (num > 1 && ctx_num_left != 0) { + c = *ctx_ptr++; + ctx_num_left--; + *strp++ = c; + if (c == '\n') + break; + num--; + } + + *strp = '\0'; + ctx->ptr = ctx_ptr; + ctx->num_left = ctx_num_left; + return str; +} + +/* See documentation in header file. */ +int ini_parse_string(const char* string, ini_handler handler, void* user) { + ini_parse_string_ctx ctx; + + ctx.ptr = string; + ctx.num_left = strlen(string); + return ini_parse_stream((ini_reader)ini_reader_string, &ctx, handler, + user); +} diff --git a/ini.h b/ini.h new file mode 100644 index 0000000..d2e07e6 --- /dev/null +++ b/ini.h @@ -0,0 +1,148 @@ +/* inih -- simple .INI file parser + +SPDX-License-Identifier: BSD-3-Clause + +Copyright (C) 2009-2019, Ben Hoyt + +inih is released under the New BSD license (see LICENSE.txt). Go to the project +home page for more info: + +https://github.com/benhoyt/inih + +*/ + +#ifndef __INI_H__ +#define __INI_H__ + +/* Make this header file easier to include in C++ code */ +#ifdef __cplusplus +extern "C" { +#endif + +#include <stdio.h> + +/* Nonzero if ini_handler callback should accept lineno parameter. */ +#ifndef INI_HANDLER_LINENO +#define INI_HANDLER_LINENO 0 +#endif + +/* Typedef for prototype of handler function. */ +#if INI_HANDLER_LINENO +typedef int (*ini_handler)(void* user, const char* section, + const char* name, const char* value, + int lineno); +#else +typedef int (*ini_handler)(void* user, const char* section, + const char* name, const char* value); +#endif + +/* Typedef for prototype of fgets-style reader function. */ +typedef char* (*ini_reader)(char* str, int num, void* stream); + +/* Parse given INI-style file. May have [section]s, name=value pairs + (whitespace stripped), and comments starting with ';' (semicolon). Section + is "" if name=value pair parsed before any section heading. name:value + pairs are also supported as a concession to Python's configparser. + + For each name=value pair parsed, call handler function with given user + pointer as well as section, name, and value (data only valid for duration + of handler call). Handler should return nonzero on success, zero on error. + + Returns 0 on success, line number of first error on parse error (doesn't + stop on first error), -1 on file open error, or -2 on memory allocation + error (only when INI_USE_STACK is zero). +*/ +int ini_parse(const char* filename, ini_handler handler, void* user); + +/* Same as ini_parse(), but takes a FILE* instead of filename. This doesn't + close the file when it's finished -- the caller must do that. */ +int ini_parse_file(FILE* file, ini_handler handler, void* user); + +/* Same as ini_parse(), but takes an ini_reader function pointer instead of + filename. Used for implementing custom or string-based I/O (see also + ini_parse_string). */ +int ini_parse_stream(ini_reader reader, void* stream, ini_handler handler, + void* user); + +/* Same as ini_parse(), but takes a zero-terminated string with the INI data +instead of a file. Useful for parsing INI data from a network socket or +already in memory. */ +int ini_parse_string(const char* string, ini_handler handler, void* user); + +/* Nonzero to allow multi-line value parsing, in the style of Python's + configparser. If allowed, ini_parse() will call the handler with the same + name for each subsequent line parsed. */ +#ifndef INI_ALLOW_MULTILINE +#define INI_ALLOW_MULTILINE 1 +#endif + +/* Nonzero to allow a UTF-8 BOM sequence (0xEF 0xBB 0xBF) at the start of + the file. See https://github.com/benhoyt/inih/issues/21 */ +#ifndef INI_ALLOW_BOM +#define INI_ALLOW_BOM 1 +#endif + +/* Chars that begin a start-of-line comment. Per Python configparser, allow + both ; and # comments at the start of a line by default. */ +#ifndef INI_START_COMMENT_PREFIXES +#define INI_START_COMMENT_PREFIXES ";#" +#endif + +/* Nonzero to allow inline comments (with valid inline comment characters + specified by INI_INLINE_COMMENT_PREFIXES). Set to 0 to turn off and match + Python 3.2+ configparser behaviour. */ +#ifndef INI_ALLOW_INLINE_COMMENTS +#define INI_ALLOW_INLINE_COMMENTS 1 +#endif +#ifndef INI_INLINE_COMMENT_PREFIXES +#define INI_INLINE_COMMENT_PREFIXES ";" +#endif + +/* Nonzero to use stack for line buffer, zero to use heap (malloc/free). */ +#ifndef INI_USE_STACK +#define INI_USE_STACK 1 +#endif + +/* Maximum line length for any line in INI file (stack or heap). Note that + this must be 3 more than the longest line (due to '\r', '\n', and '\0'). */ +#ifndef INI_MAX_LINE +#define INI_MAX_LINE 200 +#endif + +/* Nonzero to allow heap line buffer to grow via realloc(), zero for a + fixed-size buffer of INI_MAX_LINE bytes. Only applies if INI_USE_STACK is + zero. */ +#ifndef INI_ALLOW_REALLOC +#define INI_ALLOW_REALLOC 0 +#endif + +/* Initial size in bytes for heap line buffer. Only applies if INI_USE_STACK + is zero. */ +#ifndef INI_INITIAL_ALLOC +#define INI_INITIAL_ALLOC 200 +#endif + +/* Stop parsing on first error (default is to keep parsing). */ +#ifndef INI_STOP_ON_FIRST_ERROR +#define INI_STOP_ON_FIRST_ERROR 0 +#endif + +/* Nonzero to call the handler at the start of each new section (with + name and value NULL). Default is to only call the handler on + each name=value pair. */ +#ifndef INI_CALL_HANDLER_ON_NEW_SECTION +#define INI_CALL_HANDLER_ON_NEW_SECTION 0 +#endif + +/* Nonzero to allow a name without a value (no '=' or ':' on the line) and + call the handler with value NULL in this case. Default is to treat + no-value lines as an error. */ +#ifndef INI_ALLOW_NO_VALUE +#define INI_ALLOW_NO_VALUE 0 +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __INI_H__ */ diff --git a/trace.c b/trace.c index 31b6e06..07d93ab 100644 --- a/trace.c +++ b/trace.c @@ -12,8 +12,89 @@ */ #include <stdio.h> +#include <stdlib.h> #include <string.h> #include "em100.h" +#include "ini.h" + +typedef struct +{ + int id; + int iomode; + int address; + int data; + int dummy; + const char *description; + const char *remarks; +} spi_command_t; + +spi_command_t spi_commands[256]; + +static int handler(void* user, const char* section, const char* name, + const char* value) +{ + spi_command_t *cmd = (spi_command_t *)user; + + int id = strtol(section, NULL, 16); + if (id < 0 || id > 255) + return 0; /* unknown command */ + + cmd[id].id = id; + /* + * [00] + * IO_Mode=0 + * Address=0 + * Data=0 + * Dummy=0 + * Description=No operation(0x00) + * Remarks=Macronix + */ + + if (strcmp(name, "IO_Mode") == 0) { + cmd[id].iomode = atoi(value); + } else if (strcmp(name, "Address") == 0) { + cmd[id].address = atoi(value); + } else if (strcmp(name, "Data") == 0) { + cmd[id].data = atoi(value); + } else if (strcmp(name, "Dummy") == 0) { + cmd[id].dummy = atoi(value); + } else if (strcmp(name, "Description") == 0) { + cmd[id].description = strdup(value); + } else if (strcmp(name, "Remarks") == 0) { + cmd[id].remarks = strdup(value); + } else { + return 0; /* unknown name, error */ + } + + return 1; +} + +static int read_command_table(void) +{ + int i; + char *command_table_name = get_em100_file("EM100ProCmdIOTable.ini"); + + if (ini_parse(command_table_name, handler, &spi_commands) < 0) { + printf("Can't load 'EM100ProCmdIOTable.ini'\n"); + free(command_table_name); + return 1; + } + free(command_table_name); + + for (i=0; i<256; i++) { + if (spi_commands[i].id != i) + continue; + printf("SPI Command: %02x\n", spi_commands[i].id); + printf(" iomode: %d\n", spi_commands[i].iomode); + printf(" address: %d\n", spi_commands[i].address); + printf(" data: %d\n", spi_commands[i].data); + printf(" dummy: %d\n", spi_commands[i].dummy); + printf(" description: %s\n", spi_commands[i].description); + printf(" remarks: %s\n", spi_commands[i].remarks); + } + + return 0; +} /* SPI Trace related operations */ @@ -34,15 +115,6 @@ return 1; } -/** - * read_spi_trace: fetch SPI trace data - * @param em100: em100 device structure - * globals: curpos, counter, cmdid - * - * out(16 bytes): bc 00 00 00 08 00 00 00 00 15 00 00 00 00 00 00 - * in(8x8192 bytes): 2 bytes (BE) number of records (0..0x3ff), - * then records of 8 bytes each - */ static unsigned int counter = 0; static unsigned char curpos = 0; static unsigned char cmdid = 0xff; // timestamp, so never a valid command id @@ -145,6 +217,16 @@ } #define MAX_TRACE_BLOCKLENGTH 6 + +/** + * read_spi_trace: fetch SPI trace data + * @param em100: em100 device structure + * globals: curpos, counter, cmdid + * + * out(16 bytes): bc 00 00 00 08 00 00 00 00 15 00 00 00 00 00 00 + * in(8x8192 bytes): 2 bytes (BE) number of records (0..0x3ff), + * then records of 8 bytes each + */ int read_spi_trace(struct em100 *em100, int display_terminal, unsigned long addr_offset) { @@ -159,6 +241,9 @@ static unsigned long long start_timestamp = 0; static struct spi_cmd_values *spi_cmd_vals = &spi_command_list[3]; + if (!read_command_table()) + return 0; + if (!read_report_buffer(em100, reportdata)) return 0; -- To view, visit https://review.coreboot.org/c/em100/+/37538 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-Change-Id: I126a16e2ae5d5b9df5846d9bef45fde307751c05 Gerrit-Change-Number: 37538 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

3 days, 2 hours

1
7
0 0

Change in coreboot[master]: cbfs: Add metadata cache

by Julius Werner (Code Review)

Hello Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/38423 to review the following change. Change subject: cbfs: Add metadata cache ...................................................................... cbfs: Add metadata cache This patch adds a new CBFS "mcache" (metadata cache) -- a memory buffer that stores the headers of all CBFS files. Similar to the existing FMAP cache, this cache should reduce the amount of SPI accesses we need to do every boot: rather than having to re-read all CBFS headers from SPI flash every time we're looking for a file, we can just walk the same list in this in-memory copy and finally use it to directly access the flash at the right position for the file data. This patch adds the code to support the cache but doesn't enable it on any platform. The next one will turn it on by default. Change-Id: I5b1084bfdad1c6ab0ee1b143ed8dd796827f4c65 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M src/commonlib/Makefile.inc A src/commonlib/bsd/cbfs_mcache.c M src/commonlib/bsd/include/commonlib/bsd/cb_err.h M src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h M src/commonlib/include/commonlib/cbmem_id.h M src/include/cbfs.h M src/include/memlayout.h M src/include/symbols.h M src/lib/Kconfig M src/lib/cbfs.c M src/lib/coreboot_table.c M src/security/vboot/vboot_common.h M src/security/vboot/vboot_loader.c 13 files changed, 346 insertions(+), 31 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/38423/1 diff --git a/src/commonlib/Makefile.inc b/src/commonlib/Makefile.inc index b2225cb..1a38e4a 100644 --- a/src/commonlib/Makefile.inc +++ b/src/commonlib/Makefile.inc @@ -37,6 +37,13 @@ ramstage-y += bsd/cbfs_private.c smm-y += bsd/cbfs_private.c +bootblock-y += bsd/cbfs_mcache.c +verstage-y += bsd/cbfs_mcache.c +romstage-y += bsd/cbfs_mcache.c +postcar-y += bsd/cbfs_mcache.c +ramstage-y += bsd/cbfs_mcache.c +smm-y += bsd/cbfs_mcache.c + decompressor-y += bsd/lz4_wrapper.c bootblock-y += bsd/lz4_wrapper.c verstage-y += bsd/lz4_wrapper.c diff --git a/src/commonlib/bsd/cbfs_mcache.c b/src/commonlib/bsd/cbfs_mcache.c new file mode 100644 index 0000000..d97dcce --- /dev/null +++ b/src/commonlib/bsd/cbfs_mcache.c @@ -0,0 +1,147 @@ +/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later */ + +#include <commonlib/bsd/cbfs_private.h> + +#define MCACHE_TOKEN_MAGIC 0xd +#define MCACHE_OFFSET_FULL 0 +#define MCACHE_OFFSET_END 1 + +struct mcache_token { + uint32_t offset : 28; + uint32_t magic : 4; +}; + +struct cbfs_mcache_build_args { + void *mcache; + void *end; + size_t offset; + int count; +}; + +static void make_token(struct cbfs_mcache_build_args *args, size_t new_offset) +{ + struct mcache_token *token = args->mcache; + + /* If there's no space for the token, lookup() will know the cache is full anyway. */ + if (args->end - args->mcache < sizeof(*token)) + return; + + token->magic = MCACHE_TOKEN_MAGIC; + token->offset = new_offset; + + args->mcache += sizeof(*token); +} + +static cb_err_t build_walker(cbfs_dev_t dev, size_t offset, union cbfs_mdata *mdata, + bool do_hash, void *arg) +{ + struct cbfs_mcache_build_args *args = arg; + const uint32_t data_offset = be32toh(mdata->h.offset); + const uint32_t data_length = be32toh(mdata->h.len); + + if (offset != args->offset) + make_token(args, offset); + + if (args->end - args->mcache < data_offset) { + make_token(args, MCACHE_OFFSET_FULL); + return CB_CBFS_CACHE_FULL; + } + + if (cbfs_copy_fill_metadata(args->mcache, mdata, dev, offset, do_hash) != CB_SUCCESS) + return CB_CBFS_IO; + + args->mcache += data_offset; + args->offset = ALIGN_UP(offset + data_offset + data_length, CBFS_ALIGNMENT); + args->count++; + + return CB_CBFS_NOT_FOUND; +} + +cb_err_t cbfs_mcache_build(cbfs_dev_t dev, void *mcache, size_t size, + struct vb2_hash *master_hash) +{ + struct cbfs_mcache_build_args args = { + .mcache = mcache, + .end = mcache + size, + .offset = 0, + .count = 0, + }; + + cb_err_t ret = cbfs_walk(dev, build_walker, &args, master_hash, 0); + if (ret == CB_CBFS_CACHE_FULL) + ERROR("mcache overflow, should increase CBFS_MCACHE size!\n"); + else if (ret != CB_CBFS_NOT_FOUND) + return ret; + + make_token(&args, MCACHE_OFFSET_END); + LOG("mcache @%p built for %d files, used %#zx bytes\n", + mcache, args.count, args.mcache - mcache); + return CB_SUCCESS; +} + +cb_err_t cbfs_mcache_lookup(cbfs_dev_t dev, void *mcache, size_t mcache_size, const char *name, + union cbfs_mdata *mdata_out, size_t *data_offset_out, + struct vb2_hash *master_hash) +{ + size_t namesize = strlen(name) + 1; /* Count trailing \0 so we can memcmp() it. */ + void *end = mcache + mcache_size; + void *current = mcache; + + size_t offset = 0; + while (end - current >= sizeof(struct mcache_token)) { + union cbfs_mdata *mdata = current; + + if (memcmp(mdata->h.magic, CBFS_FILE_MAGIC, sizeof(mdata->h.magic)) != 0) { + struct mcache_token *token = current; + if (token->magic != MCACHE_TOKEN_MAGIC) { + ERROR("CBFS mcache corrupted at %p\n", token); + return CB_ERR; + } + if (token->offset == MCACHE_OFFSET_END) + return CB_CBFS_NOT_FOUND; + if (token->offset == MCACHE_OFFSET_FULL) + break; + offset = token->offset; + current += sizeof(*token); + continue; + } + + const uint32_t data_offset = be32toh(mdata->h.offset); + const uint32_t data_length = be32toh(mdata->h.len); + if (namesize <= cbfs_filename_size(&mdata->h) && + memcmp(name, mdata->filename, namesize) == 0) { + LOG("Found '%s' @%#zx size %#x in mcache @%p\n", + name, offset, data_length, current); + *data_offset_out = offset + data_offset; + memcpy(mdata_out, mdata, data_offset); + return CB_SUCCESS; + } + + offset = ALIGN_UP(offset + data_offset + data_length, CBFS_ALIGNMENT); + current += data_offset; + } + + return cbfs_lookup(dev, name, mdata_out, data_offset_out, master_hash); +} + +size_t cbfs_mcache_real_size(void *mcache, size_t mcache_size) +{ + void *end = mcache + mcache_size; + void *current = mcache; + + while (end - current >= sizeof(struct mcache_token)) { + union cbfs_mdata *mdata = current; + + if (memcmp(mdata->h.magic, CBFS_FILE_MAGIC, sizeof(mdata->h.magic)) != 0) { + struct mcache_token *token = current; + current += sizeof(*token); + if (token->offset == MCACHE_OFFSET_END || + token->offset == MCACHE_OFFSET_FULL) + break; + } else { + current += be32toh(mdata->h.offset); + } + } + + return current - mcache; +} diff --git a/src/commonlib/bsd/include/commonlib/bsd/cb_err.h b/src/commonlib/bsd/include/commonlib/bsd/cb_err.h index ab422e1..18aa4d7 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/cb_err.h +++ b/src/commonlib/bsd/include/commonlib/bsd/cb_err.h @@ -39,6 +39,7 @@ CB_CBFS_IO = -400, /**< Underlying I/O error */ CB_CBFS_NOT_FOUND = -401, /**< File not found in directory */ CB_CBFS_HASH = -402, /**< Master hash validation failed */ + CB_CBFS_CACHE_FULL = -403, /**< Metadata cache overflowed */ }; /* Don't typedef the enum directly, so the size is unambiguous for serialization. */ diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h b/src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h index b4fc1c7..374a460 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h +++ b/src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h @@ -92,4 +92,22 @@ cb_err_t cbfs_lookup(cbfs_dev_t dev, const char *name, union cbfs_mdata *mdata_out, size_t *data_offset_out, struct vb2_hash *master_hash); +/* Build an in-memory CBFS metadata cache out of the CBFS on |dev| into a |mcache_size| bytes + * memory area at |mcache|. Also verify |master_hash| unless it is NULL. */ +cb_err_t cbfs_mcache_build(cbfs_dev_t dev, void *mcache, size_t mcache_size, + struct vb2_hash *master_hash); + +/* + * Find a file named |name| in a CBFS metadata cache and copy its metadata into |mdata_out|. + * Pass out offset to the file data (on the storage backend). May fall back to cbfs_lookup() if + * metadata cache was too small for CBFS. |dev| and |master_hash| must have the same values as + * originally passed to cbfs_mcache_build(). + */ +cb_err_t cbfs_mcache_lookup(cbfs_dev_t dev, void *mcache, size_t mcache_size, const char *name, + union cbfs_mdata *mdata_out, size_t *data_offset_out, + struct vb2_hash *master_hash); + +/* Returns the amount of bytes actually used by the CBFS metadata cache in |mcache|. */ +size_t cbfs_mcache_real_size(void *mcache, size_t mcache_size); + #endif /* _COMMONLIB_BSD_CBFS_PRIVATE_H_ */ diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h index b063cd1..8f4f7f3 100644 --- a/src/commonlib/include/commonlib/cbmem_id.h +++ b/src/commonlib/include/commonlib/cbmem_id.h @@ -79,6 +79,8 @@ #define CBMEM_ID_ROM2 0x524f4d32 #define CBMEM_ID_ROM3 0x524f4d33 #define CBMEM_ID_FMAP 0x464d4150 +#define CBMEM_ID_CBFS_RO_MCACHE 0x524d5346 +#define CBMEM_ID_CBFS_RW_MCACHE 0x574d5346 #define CBMEM_ID_FSP_LOGO 0x4c4f474f #define CBMEM_ID_TO_NAME_TABLE \ @@ -141,5 +143,7 @@ { CBMEM_ID_ROM1, "VGA ROM #1 "}, \ { CBMEM_ID_ROM2, "VGA ROM #2 "}, \ { CBMEM_ID_ROM3, "VGA ROM #3 "}, \ - { CBMEM_ID_FMAP, "FMAP "}, + { CBMEM_ID_FMAP, "FMAP "}, \ + { CBMEM_ID_CBFS_RO_MCACHE, "RO MCACHE "}, \ + { CBMEM_ID_CBFS_RW_MCACHE, "RW MCACHE "} #endif /* _CBMEM_ID_H_ */ diff --git a/src/include/cbfs.h b/src/include/cbfs.h index 2d16aa7..82c92d7 100644 --- a/src/include/cbfs.h +++ b/src/include/cbfs.h @@ -18,6 +18,7 @@ #include <commonlib/cbfs.h> #include <program_loading.h> +#include <types.h> /*********************************************** * Perform CBFS operations on the boot device. * @@ -59,8 +60,18 @@ /* Load stage into memory filling in prog. Return 0 on success. < 0 on error. */ int cbfs_prog_stage_load(struct prog *prog); -/* Returns the region device of the currently active CBFS. - Return < 0 on error, 0 on success. */ -int cbfs_boot_region_device(struct region_device *rdev); +struct cbfs_boot_device { + struct region_device rdev; + void *mcache; + size_t mcache_size; +}; + +/* + * Retrieves the currently active CBFS boot device. If |force_ro| is set, will + * always return the read-only CBFS instead (this only makes a difference when + * CONFIG_VBOOT is enabled). May perform certain CBFS initialization tasks. + * Returns NULL on error (e.g. boot device IO error). + */ +const struct cbfs_boot_device *cbfs_get_boot_device(bool force_ro); #endif diff --git a/src/include/memlayout.h b/src/include/memlayout.h index e3aeec6..0d430dee 100644 --- a/src/include/memlayout.h +++ b/src/include/memlayout.h @@ -81,6 +81,9 @@ _ = ASSERT(sz >= FMAP_SIZE, \ STR(FMAP does not fit in FMAP_CACHE! (sz < FMAP_SIZE))); +#define CBFS_MCACHE(addr, sz) \ + REGION(cbfs_mcache, addr, sz, 8) + #if ENV_ROMSTAGE_OR_BEFORE #define PRERAM_CBFS_CACHE(addr, size) \ REGION(preram_cbfs_cache, addr, size, 4) \ diff --git a/src/include/symbols.h b/src/include/symbols.h index eec4701..a8e1a82 100644 --- a/src/include/symbols.h +++ b/src/include/symbols.h @@ -34,6 +34,7 @@ DECLARE_REGION(preram_cbfs_cache) DECLARE_REGION(postram_cbfs_cache) DECLARE_REGION(cbfs_cache) +DECLARE_REGION(cbfs_mcache) DECLARE_REGION(fmap_cache) DECLARE_REGION(payload) diff --git a/src/lib/Kconfig b/src/lib/Kconfig index dd9974a..26bf0be 100644 --- a/src/lib/Kconfig +++ b/src/lib/Kconfig @@ -75,3 +75,24 @@ If your platform really doesn't want to use an FMAP cache (e.g. due to space constraints), you can select this to disable warnings and save a bit more code. + +config NO_CBFS_MCACHE + bool + default y + help + Disables the CBFS metadata cache. This means that your platform does + not need to provide a CBFS_MCACHE section in memlayout and can save + the associated CAR/SRAM size. In that case every single CBFS file + lookup must re-read the same CBFS directory entries from flash to find + the respective file. + +config CBFS_MCACHE_RW_PERCENTAGE + int + depends on VBOOT + default 25 if CHROMEOS # Chrome OS stores many L10n files in RO only + default 50 + help + The amount of the CBFS_MCACHE area that's used for the RW CBFS, in + percent from 0 to 100. The remaining area will be used for the RO + CBFS. Default is an even 50/50 split. When VBOOT is disabled, this + will automatically be 0 (meaning the whole MCACHE is used for RO). diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index d6fb99c..40290fd 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -15,6 +15,7 @@ */ #include <assert.h> +#include <cbmem.h> #include <console/console.h> #include <string.h> #include <stdlib.h> @@ -30,30 +31,40 @@ #include <security/vboot/vboot_crtm.h> #include <security/vboot/vboot_common.h> +static cb_err_t cbfs_boot_lookup(const struct cbfs_boot_device *cbd, + const char *name, union cbfs_mdata *mdata, size_t *data_offset) +{ + if (CONFIG(NO_CBFS_MCACHE)) + return cbfs_lookup(&cbd->rdev, name, mdata, data_offset, NULL); + else + return cbfs_mcache_lookup(&cbd->rdev, + cbd->mcache, cbd->mcache_size, + name, mdata, data_offset, NULL); +} + int cbfs_boot_locate(struct cbfsf *fh, const char *name, uint32_t *type) { - struct region_device rdev; - - if (cbfs_boot_region_device(&rdev)) + const struct cbfs_boot_device *cbd = cbfs_get_boot_device(false); + if (!cbd) return -1; union cbfs_mdata mdata; size_t data_offset; - cb_err_t err = cbfs_lookup(&rdev, name, &mdata, &data_offset, NULL); + cb_err_t err = cbfs_boot_lookup(cbd, name, &mdata, &data_offset); if (CONFIG(VBOOT_ENABLE_CBFS_FALLBACK) && err == CB_CBFS_NOT_FOUND) { printk(BIOS_INFO, "CBFS: Fall back to RO region for %s\n", name); - if (fmap_locate_area_as_rdev("COREBOOT", &rdev)) + if (!(cbd = cbfs_get_boot_device(true))) return -1; - err = cbfs_lookup(&rdev, name, &mdata, &data_offset, NULL); + err = cbfs_boot_lookup(cbd, name, &mdata, &data_offset); } if (err) return -1; size_t msize = be32toh(mdata.h.offset); - if (rdev_chain(&fh->metadata, &rdev, data_offset - msize, msize) || - rdev_chain(&fh->data, &rdev, data_offset, be32toh(mdata.h.len))) + if (rdev_chain(&fh->metadata, &cbd->rdev, data_offset - msize, msize) || + rdev_chain(&fh->data, &cbd->rdev, data_offset, be32toh(mdata.h.len))) return -1; if (type) { if (!*type) @@ -280,9 +291,66 @@ return 0; } -int cbfs_boot_region_device(struct region_device *rdev) +const struct cbfs_boot_device *cbfs_get_boot_device(bool force_ro) { + static struct cbfs_boot_device ro; + + if (!force_ro) { + const struct cbfs_boot_device *rw = vboot_get_cbfs_boot_device(); + if (rw) + return rw; + } + + if (region_device_sz(&ro.rdev)) + return &ro; + + if (!CONFIG(NO_CBFS_MCACHE)) { + const struct cbmem_entry *entry; + if (cbmem_possibly_online() && + (entry = cbmem_entry_find(CBMEM_ID_CBFS_RO_MCACHE))) { + ro.mcache = cbmem_entry_start(entry); + ro.mcache_size = cbmem_entry_size(entry); + } else if (ENV_ROMSTAGE_OR_BEFORE) { + ro.mcache = _cbfs_mcache; + ro.mcache_size = REGION_SIZE(cbfs_mcache) * + (100 - CONFIG_CBFS_MCACHE_RW_PERCENTAGE) / 100; + } + } + boot_device_init(); - return vboot_locate_cbfs(rdev) && - fmap_locate_area_as_rdev("COREBOOT", rdev); + if (fmap_locate_area_as_rdev("COREBOOT", &ro.rdev)) + return NULL; + + if (!CONFIG(NO_CBFS_MCACHE) && ENV_BOOTBLOCK) { + static bool mcache_done = false; + if (!mcache_done && ro.mcache_size > 0 && cbfs_mcache_build( + &ro.rdev, ro.mcache, ro.mcache_size, NULL)) + return NULL; + mcache_done = true; + } + return &ro; } + +#if !CONFIG(NO_CBFS_MCACHE) +static void mcache_to_cbmem(const struct cbfs_boot_device *cbd, u32 cbmem_id) +{ + if (!cbd) + return; + + size_t real_size = cbfs_mcache_real_size(cbd->mcache, cbd->mcache_size); + void *cbmem_mcache = cbmem_add(cbmem_id, real_size); + if (!cbmem_mcache) { + printk(BIOS_ERR, "ERROR: Cannot allocate CBMEM mcache %#x (%#zx bytes)!\n", + cbmem_id, real_size); + return; + } + memcpy(cbmem_mcache, cbd->mcache, real_size); +} + +static void cbfs_mcache_migrate(int unused) +{ + mcache_to_cbmem(vboot_get_cbfs_boot_device(), CBMEM_ID_CBFS_RW_MCACHE); + mcache_to_cbmem(cbfs_get_boot_device(true), CBMEM_ID_CBFS_RO_MCACHE); +} +ROMSTAGE_CBMEM_INIT_HOOK(cbfs_mcache_migrate) +#endif diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index e42cb3b..b46ca57 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -243,11 +243,8 @@ { struct lb_boot_media_params *bmp; const struct region_device *boot_dev; - struct region_device cbfs_dev; - - boot_device_init(); - - if (cbfs_boot_region_device(&cbfs_dev)) + const struct cbfs_boot_device *cbd = cbfs_get_boot_device(false); + if (!cbd) return; boot_dev = boot_device_ro(); @@ -258,8 +255,8 @@ bmp->tag = LB_TAG_BOOT_MEDIA_PARAMS; bmp->size = sizeof(*bmp); - bmp->cbfs_offset = region_device_offset(&cbfs_dev); - bmp->cbfs_size = region_device_sz(&cbfs_dev); + bmp->cbfs_offset = region_device_offset(&cbd->rdev); + bmp->cbfs_size = region_device_sz(&cbd->rdev); bmp->boot_media_size = region_device_sz(boot_dev); bmp->fmap_offset = get_fmap_flash_offset(); diff --git a/src/security/vboot/vboot_common.h b/src/security/vboot/vboot_common.h index 976c26a..0ebefb6 100644 --- a/src/security/vboot/vboot_common.h +++ b/src/security/vboot/vboot_common.h @@ -16,6 +16,7 @@ #define __VBOOT_VBOOT_COMMON_H__ #include <commonlib/region.h> +#include <cbfs.h> #include <stdint.h> #include <vboot_api.h> #include <vboot_struct.h> @@ -71,7 +72,7 @@ int vboot_recovery_mode_memory_retrain(void); int vboot_can_enable_udc(void); void vboot_run_logic(void); -int vboot_locate_cbfs(struct region_device *rdev); +const struct cbfs_boot_device *vboot_get_cbfs_boot_device(void); #else /* !CONFIG_VBOOT */ static inline int vboot_developer_mode_enabled(void) { return 0; } static inline int vboot_recovery_mode_enabled(void) { return 0; } @@ -79,7 +80,7 @@ /* If VBOOT is not enabled, we are okay enabling USB device controller (UDC). */ static inline int vboot_can_enable_udc(void) { return 1; } static inline void vboot_run_logic(void) {} -static inline int vboot_locate_cbfs(struct region_device *rdev) { return -1; } +const struct cbfs_boot_device *vboot_get_cbfs_boot_device(void) { return NULL; } #endif void vboot_save_nvdata_only(struct vb2_context *ctx); diff --git a/src/security/vboot/vboot_loader.c b/src/security/vboot/vboot_loader.c index 7e63775..a8db7a3 100644 --- a/src/security/vboot/vboot_loader.c +++ b/src/security/vboot/vboot_loader.c @@ -13,7 +13,10 @@ * GNU General Public License for more details. */ +#include <boot_device.h> #include <cbfs.h> +#include <cbmem.h> +#include <commonlib/bsd/cbfs_private.h> #include <console/console.h> #include <ec/google/chromeec/ec.h> #include <rmodule.h> @@ -34,12 +37,26 @@ int vboot_executed; +static void build_rw_mcache(void) +{ + if (CONFIG(NO_CBFS_MCACHE)) + return; + + if (vboot_get_context()->flags & VB2_CONTEXT_RECOVERY_MODE) + return; /* No RW mcache if we're staying in RO. */ + + const struct cbfs_boot_device *cbd = vboot_get_cbfs_boot_device(); + if (cbfs_mcache_build(&cbd->rdev, cbd->mcache, cbd->mcache_size, NULL)) + die("Failed to build RW mcache."); /* TODO: -> recovery? */ +} + void vboot_run_logic(void) { if (verification_should_run()) { /* Note: this path is not used for VBOOT_RETURN_FROM_VERSTAGE */ verstage_main(); vboot_executed = 1; + build_rw_mcache(); } else if (verstage_should_load()) { struct cbfsf file; struct prog verstage = @@ -67,21 +84,40 @@ return; vboot_executed = 1; + build_rw_mcache(); } } -int vboot_locate_cbfs(struct region_device *rdev) +const struct cbfs_boot_device *vboot_get_cbfs_boot_device(void) { - struct vb2_context *ctx; - /* Don't honor vboot results until the vboot logic has run. */ if (!vboot_logic_executed()) - return -1; + return NULL; - ctx = vboot_get_context(); + static struct cbfs_boot_device cbd; + if (region_device_sz(&cbd.rdev)) + return &cbd; + struct vb2_context *ctx = vboot_get_context(); if (ctx->flags & VB2_CONTEXT_RECOVERY_MODE) - return -1; + return NULL; - return vboot_locate_firmware(ctx, rdev); + boot_device_init(); + if (vboot_locate_firmware(ctx, &cbd.rdev)) + return NULL; + + if (!CONFIG(NO_CBFS_MCACHE)) { + const struct cbmem_entry *entry; + if (cbmem_possibly_online() && + (entry = cbmem_entry_find(CBMEM_ID_CBFS_RW_MCACHE))) { + cbd.mcache = cbmem_entry_start(entry); + cbd.mcache_size = cbmem_entry_size(entry); + } else if (ENV_ROMSTAGE_OR_BEFORE) { + cbd.mcache_size = REGION_SIZE(cbfs_mcache) * + CONFIG_CBFS_MCACHE_RW_PERCENTAGE / 100; + cbd.mcache = _ecbfs_mcache - cbd.mcache_size; + } + } + + return &cbd; } -- To view, visit https://review.coreboot.org/c/coreboot/+/38423 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b1084bfdad1c6ab0ee1b143ed8dd796827f4c65 Gerrit-Change-Number: 38423 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

5 days, 19 hours

6
60
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Change in coreboot[master]: soc/intel/{apl,glk}: add options to configure GPU

by Maxim Polyakov (Code Review)

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39374 ) Change subject: soc/intel/{apl,glk}: add options to configure GPU ...................................................................... soc/intel/{apl,glk}: add options to configure GPU Adds options to select the primary GPU device and configure IGD, which allows to override the appropriate FSP options in the SoC code. These changes do not affect the configuration of the boards with the Apollo Lake and Gemini Lake processors, because if these parameters are not defined in the devicetree, they will be set to the default values. Change-Id: Idcd117217cf412ee0722aff52db4b3c8ec2a226c Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/soc/intel/apollolake/chip.h M src/soc/intel/apollolake/romstage.c 2 files changed, 64 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/39374/1 diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index 40cd39b..0375cec 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -44,6 +44,46 @@ /* Common structure containing soc config data required by common code*/ struct soc_intel_common_config common_soc_config; + /* Select DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size */ + enum { + DVMT_64MB = 2, /* Default */ + DVMT_96MB, + DVMT_128MB, + DVMT_160MB, + DVMT_192MB, + DVMT_224MB, + DVMT_256MB, + DVMT_288MB, + DVMT_320MB, + DVMT_352MB, + DVMT_384MB, + DVMT_416MB, + DVMT_448MB, + DVMT_480MB, + DVMT_512MB, + } igd_dvmt_50_pre_alloc_size; + + /* Select the Aperture Size for GPU device */ + enum { + APERTURE_128MB = 1, /* Default */ + APERTURE_256MB, + APERTURE_512MB, + } igd_aperture_size; + + /* Select the GTT Size for GPU device */ + enum { + GTT_2MB = 1, + GTT_4MB, + GTT_8MB, /* Default */ + } igd_gtt_size; + + /* Select primary GPU device */ + enum { + PRIMARY_AUTO = 0, /* Default */ + PRIMARY_IGD = 2, + PRIMARY_PCI = 3, + } primary_gpu; + /* * Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has * four CLKREQ inputs, but six root ports. Root ports without an diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 05cd0db..1576802 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -264,12 +264,34 @@ } } +static void soc_gpu_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + const struct soc_intel_apollolake_config *soc_cfg = config_of_soc(); + const struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD); + + m_cfg->PrimaryVideoAdaptor = soc_cfg->primary_gpu; + if (dev && dev->enabled && (soc_cfg->primary_gpu != PRIMARY_PCI)) { + /* + * Override FSP settings for IGD only if they are set in the devicetree. + * Otherwise, the default values from UPD will be used for them + */ + if (soc_cfg->igd_dvmt_50_pre_alloc_size) + m_cfg->IgdDvmt50PreAlloc = soc_cfg->igd_dvmt_50_pre_alloc_size; + + if (soc_cfg->igd_aperture_size) + m_cfg->IgdApertureSize = soc_cfg->igd_aperture_size; + + if (soc_cfg->igd_gtt_size) + m_cfg->GttSize = soc_cfg->igd_gtt_size; + } +} + static void soc_memory_init_params(FSPM_UPD *mupd) { #if CONFIG(SOC_INTEL_GLK) /* Only for GLK */ FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; - m_cfg->PrmrrSize = get_prmrr_size(); /* @@ -307,6 +329,7 @@ check_full_retrain(mupd); fill_console_params(mupd); + soc_gpu_init_params(mupd); if (CONFIG(SOC_INTEL_GLK)) soc_memory_init_params(mupd); -- To view, visit https://review.coreboot.org/c/coreboot/+/39374 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idcd117217cf412ee0722aff52db4b3c8ec2a226c Gerrit-Change-Number: 39374 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

6 days, 8 hours

4
24
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Change in coreboot[master]: [WIP]drivers: Replace multiple fill_fb_framebuffer with single instance

by Patrick Rudolph (Code Review)

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39003 ) Change subject: [WIP]drivers: Replace multiple fill_fb_framebuffer with single instance ...................................................................... [WIP]drivers: Replace multiple fill_fb_framebuffer with single instance Replace all duplications of fill_fb_framebuffer and provide a single one. Should not change the current behaviour. TODO: Libgfxinit seems to expose one,too Change-Id: Ife507f7e7beaf59854e533551b4b87ea6980c1f4 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/device/oprom/realmode/x86.c M src/device/oprom/yabel/vbe.c M src/drivers/intel/fsp1_1/fsp_gop.c M src/drivers/intel/fsp2_0/graphics.c M src/drivers/intel/fsp2_0/include/fsp/util.h M src/drivers/xgi/common/xgi_coreboot.c M src/lib/Kconfig M src/lib/Makefile.inc 8 files changed, 111 insertions(+), 185 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/39003/1 diff --git a/src/device/oprom/realmode/x86.c b/src/device/oprom/realmode/x86.c index 8ba0241..4c11e6f 100644 --- a/src/device/oprom/realmode/x86.c +++ b/src/device/oprom/realmode/x86.c @@ -23,6 +23,7 @@ #include <pc80/i8254.h> #include <string.h> #include <vbe.h> +#include <framebuffer_info.h> /* we use x86emu's register file representation */ #include <x86emu/regs.h> @@ -218,6 +219,7 @@ #if CONFIG(FRAMEBUFFER_SET_VESA_MODE) static vbe_mode_info_t mode_info; static int mode_info_valid; +static struct edid_fb_info *fb_info; static int vbe_mode_info_valid(void) { @@ -362,6 +364,28 @@ } vbe_set_mode(&mode_info); + + if (!vbe_mode_info_valid()) + return; + + if (!fb_info) { + fb_info = fb_new_framebuffer_info(); + } + if (fb_info) { + fb_fill_framebuffer_info_ex(fb_info, mode_info.vesa.phys_base_ptr, + le16_to_cpu(mode_info.vesa.x_resolution), + le16_to_cpu(mode_info.vesa.y_resolution), + le16_to_cpu(mode_info.vesa.bytes_per_scanline), + mode_info.vesa.bits_per_pixel, + mode_info.vesa.reserved_mask_pos, + mode_info.vesa.reserved_mask_size, + mode_info.vesa.red_mask_pos, + mode_info.vesa.red_mask_size, + mode_info.vesa.green_mask_pos, + mode_info.vesa.green_mask_size, + mode_info.vesa.blue_mask_pos, + mode_info.vesa.blue_mask_size); + } } void vbe_textmode_console(void) @@ -373,34 +397,6 @@ die("\nError: In %s function\n", __func__); } -int fill_lb_framebuffer(struct lb_framebuffer *framebuffer) -{ - if (!vbe_mode_info_valid()) - return -1; - - framebuffer->physical_address = mode_info.vesa.phys_base_ptr; - - framebuffer->x_resolution = le16_to_cpu(mode_info.vesa.x_resolution); - framebuffer->y_resolution = le16_to_cpu(mode_info.vesa.y_resolution); - framebuffer->bytes_per_line = - le16_to_cpu(mode_info.vesa.bytes_per_scanline); - framebuffer->bits_per_pixel = mode_info.vesa.bits_per_pixel; - - framebuffer->red_mask_pos = mode_info.vesa.red_mask_pos; - framebuffer->red_mask_size = mode_info.vesa.red_mask_size; - - framebuffer->green_mask_pos = mode_info.vesa.green_mask_pos; - framebuffer->green_mask_size = mode_info.vesa.green_mask_size; - - framebuffer->blue_mask_pos = mode_info.vesa.blue_mask_pos; - framebuffer->blue_mask_size = mode_info.vesa.blue_mask_size; - - framebuffer->reserved_mask_pos = mode_info.vesa.reserved_mask_pos; - framebuffer->reserved_mask_size = mode_info.vesa.reserved_mask_size; - - return 0; -} - #endif void run_bios(struct device *dev, unsigned long addr) diff --git a/src/device/oprom/yabel/vbe.c b/src/device/oprom/yabel/vbe.c index a3d736f..2c05338 100644 --- a/src/device/oprom/yabel/vbe.c +++ b/src/device/oprom/yabel/vbe.c @@ -162,6 +162,7 @@ } static int mode_info_valid; +static struct edid_fb_info *fb_info; static int vbe_mode_info_valid(void) { @@ -747,33 +748,28 @@ mode_info.video_mode = (1 << 14) | CONFIG_FRAMEBUFFER_VESA_MODE; vbe_get_mode_info(&mode_info); vbe_set_mode(&mode_info); -} -int fill_lb_framebuffer(struct lb_framebuffer *framebuffer) -{ if (!vbe_mode_info_valid()) - return -1; + return; - framebuffer->physical_address = le32_to_cpu(mode_info.vesa.phys_base_ptr); - - framebuffer->x_resolution = le16_to_cpu(mode_info.vesa.x_resolution); - framebuffer->y_resolution = le16_to_cpu(mode_info.vesa.y_resolution); - framebuffer->bytes_per_line = le16_to_cpu(mode_info.vesa.bytes_per_scanline); - framebuffer->bits_per_pixel = mode_info.vesa.bits_per_pixel; - - framebuffer->red_mask_pos = mode_info.vesa.red_mask_pos; - framebuffer->red_mask_size = mode_info.vesa.red_mask_size; - - framebuffer->green_mask_pos = mode_info.vesa.green_mask_pos; - framebuffer->green_mask_size = mode_info.vesa.green_mask_size; - - framebuffer->blue_mask_pos = mode_info.vesa.blue_mask_pos; - framebuffer->blue_mask_size = mode_info.vesa.blue_mask_size; - - framebuffer->reserved_mask_pos = mode_info.vesa.reserved_mask_pos; - framebuffer->reserved_mask_size = mode_info.vesa.reserved_mask_size; - - return 0; + if (!fb_info) { + fb_info = fb_new_framebuffer_info(); + } + if (fb_info) { + fb_fill_framebuffer_info_ex(fb_info, mode_info.vesa.phys_base_ptr, + le16_to_cpu(mode_info.vesa.x_resolution), + le16_to_cpu(mode_info.vesa.y_resolution), + le16_to_cpu(mode_info.vesa.bytes_per_scanline), + mode_info.vesa.bits_per_pixel, + mode_info.vesa.reserved_mask_pos, + mode_info.vesa.reserved_mask_size, + mode_info.vesa.red_mask_pos, + mode_info.vesa.red_mask_size, + mode_info.vesa.green_mask_pos, + mode_info.vesa.green_mask_size, + mode_info.vesa.blue_mask_pos, + mode_info.vesa.blue_mask_size); + } } void vbe_textmode_console(void) diff --git a/src/drivers/intel/fsp1_1/fsp_gop.c b/src/drivers/intel/fsp1_1/fsp_gop.c index eb64151..9b555e6 100644 --- a/src/drivers/intel/fsp1_1/fsp_gop.c +++ b/src/drivers/intel/fsp1_1/fsp_gop.c @@ -12,10 +12,12 @@ */ #include <boot/coreboot_tables.h> +#include <bootstate.h> #include <console/console.h> +#include <framebuffer_info.h> #include <fsp/util.h> -int fill_lb_framebuffer(struct lb_framebuffer *framebuffer) +static void fill_framebuffer_info(void *unused) { VOID *hob_list_ptr; hob_list_ptr = get_hob_list(); @@ -30,20 +32,15 @@ printk(BIOS_DEBUG, "FSP_DEBUG: Graphics Data HOB present\n"); vbt_gop = GET_GUID_HOB_DATA(vbt_hob); - framebuffer->physical_address = vbt_gop->FrameBufferBase; - framebuffer->x_resolution = vbt_gop->GraphicsMode.HorizontalResolution; - framebuffer->y_resolution = vbt_gop->GraphicsMode.VerticalResolution; - framebuffer->bytes_per_line = vbt_gop->GraphicsMode.PixelsPerScanLine - * 4; - framebuffer->bits_per_pixel = 32; - framebuffer->red_mask_pos = 16; - framebuffer->red_mask_size = 8; - framebuffer->green_mask_pos = 8; - framebuffer->green_mask_size = 8; - framebuffer->blue_mask_pos = 0; - framebuffer->blue_mask_size = 8; - framebuffer->reserved_mask_pos = 24; - framebuffer->reserved_mask_size = 8; + struct edid_fb_info *info = fb_new_framebuffer_info(); + if (!info) + return; - return 0; + fb_fill_framebuffer_info(info, vbt_gop->FrameBufferBase, + vbt_gop->GraphicsMode.HorizontalResolution, + vbt_gop->GraphicsMode.VerticalResolution, + vbt_gop->GraphicsMode.PixelsPerScanLine * 4, + 32); } + +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, fill_framebuffer_info, NULL); diff --git a/src/drivers/intel/fsp2_0/graphics.c b/src/drivers/intel/fsp2_0/graphics.c index be7afdb..f35556f 100644 --- a/src/drivers/intel/fsp2_0/graphics.c +++ b/src/drivers/intel/fsp2_0/graphics.c @@ -17,6 +17,7 @@ #include <fsp/util.h> #include <soc/intel/common/vbt.h> #include <types.h> +#include <framebuffer_info.h> enum pixel_format { pixel_rgbx_8bpc = 0, @@ -58,48 +59,18 @@ [pixel_bgrx_8bpc] = { {16, 8}, {8, 8}, {0, 8}, {24, 8} }, }; -enum cb_err fsp_fill_lb_framebuffer(struct lb_framebuffer *framebuffer) +__weak uintptr_t fsp_soc_get_igd_bar(void) { - size_t size; - const struct hob_graphics_info *ginfo; - const struct fsp_framebuffer *fbinfo; - - ginfo = fsp_find_extension_hob_by_guid(fsp_graphics_info_guid, &size); - - if (!ginfo) { - printk(BIOS_ALERT, "Graphics hand-off block not found\n"); - return CB_ERR; - } - - if (ginfo->pixel_format >= ARRAY_SIZE(fsp_framebuffer_format_map)) { - printk(BIOS_ALERT, "FSP set unknown framebuffer format: %d\n", - ginfo->pixel_format); - return CB_ERR; - } - - fbinfo = fsp_framebuffer_format_map + ginfo->pixel_format; - - framebuffer->physical_address = ginfo->framebuffer_base; - framebuffer->x_resolution = ginfo->horizontal_resolution; - framebuffer->y_resolution = ginfo->vertical_resolution; - framebuffer->bytes_per_line = ginfo->pixels_per_scanline * 4; - framebuffer->bits_per_pixel = 32; - framebuffer->red_mask_pos = fbinfo->red.pos; - framebuffer->red_mask_size = fbinfo->red.size; - framebuffer->green_mask_pos = fbinfo->green.pos; - framebuffer->green_mask_size = fbinfo->green.size; - framebuffer->blue_mask_pos = fbinfo->blue.pos; - framebuffer->blue_mask_size = fbinfo->blue.size; - framebuffer->reserved_mask_pos = fbinfo->rsvd.pos; - framebuffer->reserved_mask_size = fbinfo->rsvd.pos; - - return CB_SUCCESS; + return 0; } -int fill_lb_framebuffer(struct lb_framebuffer *framebuffer) +static void fill_framebuffer_info(void *unused) { + size_t size; enum cb_err ret; uintptr_t framebuffer_bar; + const struct hob_graphics_info *ginfo; + const struct fsp_framebuffer *fbinfo; /* Pci enumeration happens after silicon init. * After enumeration graphic framebuffer base may be relocated. @@ -109,24 +80,44 @@ if (!framebuffer_bar) { printk(BIOS_ALERT, "Framebuffer BAR invalid\n"); - return -1; - } - - ret = fsp_fill_lb_framebuffer(framebuffer); - if (ret != CB_SUCCESS) { - printk(BIOS_ALERT, "FSP did not return a valid framebuffer\n"); - return -1; + return; } /* Resource allocator can move the BAR around after FSP configures it */ - framebuffer->physical_address = framebuffer_bar; - printk(BIOS_DEBUG, "Graphics framebuffer located at 0x%llx\n", - framebuffer->physical_address); + printk(BIOS_DEBUG, "Graphics framebuffer located at 0x%llx\n", framebuffer_bar); - return 0; + ginfo = fsp_find_extension_hob_by_guid(fsp_graphics_info_guid, &size); + + if (!ginfo) { + printk(BIOS_ALERT, "Graphics hand-off block not found\n"); + return; + } + + if (ginfo->pixel_format >= ARRAY_SIZE(fsp_framebuffer_format_map)) { + printk(BIOS_ALERT, "FSP set unknown framebuffer format: %d\n", + ginfo->pixel_format); + return; + } + + fbinfo = fsp_framebuffer_format_map + ginfo->pixel_format; + + struct edid_fb_info *info = fb_new_framebuffer_info(); + if (!info) + return; + + fb_fill_framebuffer_info_ex(fb_info, ginfo->framebuffer_base, + ginfo->horizontal_resolution, + ginfo->vertical_resolution, + ginfo->pixels_per_scanline * 4, + 32, + fbinfo->rsvd.pos, + fbinfo->rsvd.size, + fbinfo->red.pos, + fbinfo->red.size, + fbinfo->green.pos, + fbinfo->green.size, + fbinfo->blue.pos, + fbinfo->blue.size); } -__weak uintptr_t fsp_soc_get_igd_bar(void) -{ - return 0; -} +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, fill_framebuffer_info, NULL); diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h index 303bafe..15e7390 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/util.h +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -76,7 +76,6 @@ void *fsp_get_hob_list_ptr(void); const void *fsp_find_extension_hob_by_guid(const uint8_t *guid, size_t *size); const void *fsp_find_nv_storage_data(size_t *size); -enum cb_err fsp_fill_lb_framebuffer(struct lb_framebuffer *framebuffer); int fsp_find_range_hob(struct range_entry *re, const uint8_t guid[16]); void fsp_display_fvi_version_hob(void); void fsp_find_reserved_memory(struct range_entry *re); diff --git a/src/drivers/xgi/common/xgi_coreboot.c b/src/drivers/xgi/common/xgi_coreboot.c index d65e007..235cbe2 100644 --- a/src/drivers/xgi/common/xgi_coreboot.c +++ b/src/drivers/xgi/common/xgi_coreboot.c @@ -21,6 +21,7 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <pc80/vga.h> +#include <framebuffer_info.h> #include "xgi_coreboot.h" #include "vstruct.h" @@ -31,8 +32,7 @@ #include "vb_setmode.h" #include "XGI_main.c" -static int xgi_vbe_valid; -static struct lb_framebuffer xgi_fb; +static struct edid_fb_info *fb_info; int xgifb_probe(struct pci_dev *pdev, struct xgifb_video_info *xgifb_info) { @@ -359,43 +359,16 @@ XGIbios_mode[xgifb_info->mode_idx].bpp, xgifb_info->refresh_rate); - /* Set LinuxBIOS framebuffer information */ - xgi_vbe_valid = 1; - xgi_fb.physical_address = xgifb_info->video_base; - xgi_fb.x_resolution = xgifb_info->video_width; - xgi_fb.y_resolution = xgifb_info->video_height; - xgi_fb.bytes_per_line = - xgifb_info->video_width * xgifb_info->video_bpp; - xgi_fb.bits_per_pixel = xgifb_info->video_bpp; - - xgi_fb.reserved_mask_pos = 0; - xgi_fb.reserved_mask_size = 0; - switch (xgifb_info->video_bpp) { - case 32: - case 24: - /* packed into 4-byte words */ - xgi_fb.reserved_mask_pos = 24; - xgi_fb.reserved_mask_size = 8; - xgi_fb.red_mask_pos = 16; - xgi_fb.red_mask_size = 8; - xgi_fb.green_mask_pos = 8; - xgi_fb.green_mask_size = 8; - xgi_fb.blue_mask_pos = 0; - xgi_fb.blue_mask_size = 8; - break; - case 16: - /* packed into 2-byte words */ - xgi_fb.red_mask_pos = 11; - xgi_fb.red_mask_size = 5; - xgi_fb.green_mask_pos = 5; - xgi_fb.green_mask_size = 6; - xgi_fb.blue_mask_pos = 0; - xgi_fb.blue_mask_size = 5; - break; - default: - printk(BIOS_SPEW, "%s: unsupported BPP %d\n", __func__, - xgifb_info->video_bpp); - xgi_vbe_valid = 0; + /* Set framebuffer information */ + if (!fb_info) { + fb_info = fb_new_framebuffer_info(); + } + if (fb_info) { + fb_fill_framebuffer_info(fb_info, xgifb_info->video_base, + xgifb_info->video_width, + xgifb_info->video_height, + xgifb_info->video_width * xgifb_info->video_bpp, + xgifb_info->video_bpp); } } else { /* @@ -415,22 +388,6 @@ return 0; } - -static int vbe_mode_info_valid(void) -{ - return xgi_vbe_valid; -} - -int fill_lb_framebuffer(struct lb_framebuffer *framebuffer) -{ - if (!vbe_mode_info_valid()) - return -1; - - *framebuffer = xgi_fb; - - return 0; -} - struct xgifb_video_info *xgifb_video_info_ptr; struct xgifb_video_info *pci_get_drvdata(struct pci_dev *pdev) { diff --git a/src/lib/Kconfig b/src/lib/Kconfig index dd9974a..d831975 100644 --- a/src/lib/Kconfig +++ b/src/lib/Kconfig @@ -5,14 +5,6 @@ implementation. This activates a stub that logs the missing board reset and halts execution. -config NO_EDID_FILL_FB - bool - default y if !MAINBOARD_DO_NATIVE_VGA_INIT - help - Don't include default fill_lb_framebuffer() implementation. Select - this if your drivers uses MAINBOARD_DO_NATIVE_VGA_INIT but provides - its own fill_lb_framebuffer() implementation. - config RAMSTAGE_ADA bool help diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 2333f64..a1fb8c2 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -134,9 +134,7 @@ ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c ramstage-$(CONFIG_COVERAGE) += libgcov.c ramstage-y += edid.c -ifneq ($(CONFIG_NO_EDID_FILL_FB),y) ramstage-y += edid_fill_fb.c -endif ramstage-y += memrange.c ramstage-$(CONFIG_COOP_MULTITASKING) += thread.c ramstage-$(CONFIG_TIMER_QUEUE) += timer_queue.c -- To view, visit https://review.coreboot.org/c/coreboot/+/39003 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife507f7e7beaf59854e533551b4b87ea6980c1f4 Gerrit-Change-Number: 39003 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: lib: Rename edid_fill_fb.c

by Patrick Rudolph (Code Review)

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39431 ) Change subject: lib: Rename edid_fill_fb.c ...................................................................... lib: Rename edid_fill_fb.c Rename edid_fill_fb.c to framebuffer_info.c as it doesn't deal with EDID that much any more. Change-Id: Ic7eb6432eee9808aaa9a48e6bcd61bf136a8b938 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/lib/Makefile.inc R src/lib/framebuffer_info.c 2 files changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/39431/1 diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index a1fb8c2..76ace63 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -134,7 +134,7 @@ ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c ramstage-$(CONFIG_COVERAGE) += libgcov.c ramstage-y += edid.c -ramstage-y += edid_fill_fb.c +ramstage-y += framebuffer_info.c ramstage-y += memrange.c ramstage-$(CONFIG_COOP_MULTITASKING) += thread.c ramstage-$(CONFIG_TIMER_QUEUE) += timer_queue.c diff --git a/src/lib/edid_fill_fb.c b/src/lib/framebuffer_info.c similarity index 100% rename from src/lib/edid_fill_fb.c rename to src/lib/framebuffer_info.c -- To view, visit https://review.coreboot.org/c/coreboot/+/39431 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7eb6432eee9808aaa9a48e6bcd61bf136a8b938 Gerrit-Change-Number: 39431 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

1 week

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Change in coreboot[master]: soc/intel/fsp-car: Halt on improperly configured coreboot

by Arthur Heymans (Code Review)

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37280 ) Change subject: soc/intel/fsp-car: Halt on improperly configured coreboot ...................................................................... soc/intel/fsp-car: Halt on improperly configured coreboot Test if Kconfig symbols actually match what FSP does. If it is not the case it best to halt right away instead of continuing to boot with possibly hard to debug problems. Change-Id: I8520adc868f08938af27ee686a8777c281afd4f9 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/37280/1 diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S index 4174f36..bde3849 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S @@ -86,6 +86,11 @@ cmp $0, %eax jnz .halt_forever + /* Check sanity of coreboot Kconfig symbols that need to match what FSP + does */ + cmpl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %edx + jne .halt_forever + /* Setup bootblock stack */ movl _ecar_stack, %esp -- To view, visit https://review.coreboot.org/c/coreboot/+/37280 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8520adc868f08938af27ee686a8777c281afd4f9 Gerrit-Change-Number: 37280 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

1 week

2
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Change in coreboot[master]: drivers/intel/fsp1.1/car: Halt on improperly configured coreboot

by Arthur Heymans (Code Review)

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37281 ) Change subject: drivers/intel/fsp1.1/car: Halt on improperly configured coreboot ...................................................................... drivers/intel/fsp1.1/car: Halt on improperly configured coreboot Test if Kconfig symbols actually match what FSP does. If it is not the case it best to halt right away instead of continuing to boot with possibly hard to debug problems. Change-Id: Ieec8259149cc8fd71c40fd1511a6a2cfa67c5337 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/intel/fsp1_1/cache_as_ram.S 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/37281/1 diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.S b/src/drivers/intel/fsp1_1/cache_as_ram.S index fb39884..748c267 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.S +++ b/src/drivers/intel/fsp1_1/cache_as_ram.S @@ -143,6 +143,11 @@ cmp $0, %eax jne halt2 + /* Check sanity of coreboot Kconfig symbols that need to match what FSP + does */ + cmpl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %edx + jne .halt_forever + /* Setup BSP stack */ movl _ecar_stack, %esp -- To view, visit https://review.coreboot.org/c/coreboot/+/37281 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieec8259149cc8fd71c40fd1511a6a2cfa67c5337 Gerrit-Change-Number: 37281 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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coreboot-gerrit March 2020