May 2019 - coreboot-gerrit - mail.coreboot.org

Change in ...coreboot[master]: superio/nsc: Use common defines for NSC PC8xxxx chips

by Peter Lemenkov (Code Review)

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31427 Change subject: superio/nsc: Use common defines for NSC PC8xxxx chips ...................................................................... superio/nsc: Use common defines for NSC PC8xxxx chips * Some common NSC defines moved to superio/nsc/common * All NSC's pc8xxxx chips uses these common definitions * Lenovo T60/X60/Z61t/T400 docking updated to use these common defines * HP ProLiant DL165 G6 Fam10 updated to use this common code Build tested - Lenovo T60/X60/Z61t/T400, HP ProLiant DL165 G6 Fam10 builds fine. Change-Id: Iffdb4752f3075b1a1b391d4cf8d4416748bfe485 Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/hp/dl165_g6_fam10/romstage.c M src/mainboard/lenovo/t400/dock.c M src/mainboard/lenovo/t60/dock.c M src/mainboard/lenovo/x60/dock.c M src/mainboard/lenovo/z61t/dock.c A src/superio/nsc/common/superio_defs.h D src/superio/nsc/pc87309/pc87309.h M src/superio/nsc/pc87309/superio.c D src/superio/nsc/pc87360/pc87360.h M src/superio/nsc/pc87360/superio.c D src/superio/nsc/pc87366/pc87366.h M src/superio/nsc/pc87366/superio.c D src/superio/nsc/pc87382/pc87382.h M src/superio/nsc/pc87382/superio.c D src/superio/nsc/pc87384/pc87384.h M src/superio/nsc/pc87384/superio.c D src/superio/nsc/pc87392/pc87392.h M src/superio/nsc/pc87392/superio.c M src/superio/nsc/pc87417/pc87417.h M src/superio/nsc/pc87417/superio.c 20 files changed, 219 insertions(+), 369 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/31427/1 diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index 6d2eed4..7f5411e 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -34,6 +34,7 @@ #include <spd.h> #include <delay.h> #include <superio/serverengines/pilot/pilot.h> +#include <superio/nsc/common/superio_defs.h> #include <superio/nsc/pc87417/pc87417.h> #include <cpu/x86/bist.h> #include <cpu/amd/car.h> @@ -50,7 +51,7 @@ #include "cpu/amd/quadcore/quadcore.c" #define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1) -#define RTC_DEV PNP_DEV(0x4e, PC87417_RTC) +#define RTC_DEV PNP_DEV(0x4e, PC8XXXX_RTC) void activate_spd_rom(const struct mem_controller *ctrl); int spd_read_byte(unsigned int device, unsigned int address); diff --git a/src/mainboard/lenovo/t400/dock.c b/src/mainboard/lenovo/t400/dock.c index 6d1a80c..58788e7 100644 --- a/src/mainboard/lenovo/t400/dock.c +++ b/src/mainboard/lenovo/t400/dock.c @@ -23,7 +23,7 @@ #include <device/pnp.h> #include <delay.h> #include "dock.h" -#include <superio/nsc/pc87382/pc87382.h> +#include <superio/nsc/common/superio_defs.h> #include <southbridge/intel/i82801ix/i82801ix.h> #include <ec/lenovo/h8/h8.h> @@ -64,8 +64,8 @@ return 0; } -static const pnp_devfn_t l_dlpc = PNP_DEV(0x164e, PC87382_DOCK); -static const pnp_devfn_t l_gpio = PNP_DEV(0x164e, PC87382_GPIO); +static const pnp_devfn_t l_dlpc = PNP_DEV(0x164e, PC8XXXX_DOCK); +static const pnp_devfn_t l_gpio = PNP_DEV(0x164e, PC8XXXX_GPIO); static int pc87382_init(pnp_devfn_t dlpc, u16 dlpc_base) { @@ -170,20 +170,18 @@ /* Docking station side. */ -#include <superio/nsc/pc87384/pc87384.h> - -static const pnp_devfn_t r_gpio = PNP_DEV(SUPERIO_DEV, PC87384_GPIO); -static const pnp_devfn_t r_serial = PNP_DEV(SUPERIO_DEV, PC87384_SP1); +static const pnp_devfn_t r_gpio = PNP_DEV(SUPERIO_DEV, PC8XXXX_GPIO); +static const pnp_devfn_t r_serial = PNP_DEV(SUPERIO_DEV, PC8XXXX_SP1); static const struct pin_config remote_gpio[] = { - {0x00, PC87384_GPIO_PIN_DEBOUNCE | PC87384_GPIO_PIN_PULLUP}, - {0x01, PC87384_GPIO_PIN_TYPE_PUSH_PULL | PC87384_GPIO_PIN_OE}, - {0x02, PC87384_GPIO_PIN_TYPE_PUSH_PULL | PC87384_GPIO_PIN_OE}, - {0x03, PC87384_GPIO_PIN_DEBOUNCE | PC87384_GPIO_PIN_PULLUP}, - {0x04, PC87384_GPIO_PIN_DEBOUNCE | PC87384_GPIO_PIN_PULLUP}, - {0x05, PC87384_GPIO_PIN_DEBOUNCE | PC87384_GPIO_PIN_PULLUP}, - {0x06, PC87384_GPIO_PIN_DEBOUNCE | PC87384_GPIO_PIN_PULLUP}, - {0x07, PC87384_GPIO_PIN_DEBOUNCE | PC87384_GPIO_PIN_PULLUP}, + {0x00, PC8XXXX_GPIO_PIN_DEBOUNCE | PC8XXXX_GPIO_PIN_PULLUP}, + {0x01, PC8XXXX_GPIO_PIN_TYPE_PUSH_PULL | PC8XXXX_GPIO_PIN_OE}, + {0x02, PC8XXXX_GPIO_PIN_TYPE_PUSH_PULL | PC8XXXX_GPIO_PIN_OE}, + {0x03, PC8XXXX_GPIO_PIN_DEBOUNCE | PC8XXXX_GPIO_PIN_PULLUP}, + {0x04, PC8XXXX_GPIO_PIN_DEBOUNCE | PC8XXXX_GPIO_PIN_PULLUP}, + {0x05, PC8XXXX_GPIO_PIN_DEBOUNCE | PC8XXXX_GPIO_PIN_PULLUP}, + {0x06, PC8XXXX_GPIO_PIN_DEBOUNCE | PC8XXXX_GPIO_PIN_PULLUP}, + {0x07, PC8XXXX_GPIO_PIN_DEBOUNCE | PC8XXXX_GPIO_PIN_PULLUP}, }; static int pc87384_init(void) diff --git a/src/mainboard/lenovo/t60/dock.c b/src/mainboard/lenovo/t60/dock.c index 05dd65e..57a5a00 100644 --- a/src/mainboard/lenovo/t60/dock.c +++ b/src/mainboard/lenovo/t60/dock.c @@ -18,7 +18,7 @@ #include <arch/io.h> #include <delay.h> #include "dock.h" -#include <superio/nsc/pc87384/pc87384.h> +#include <superio/nsc/common/superio_defs.h> #include "ec/acpi/ec.h" #include "ec/lenovo/pmh7/pmh7.h" #include <southbridge/intel/i82801gx/i82801gx.h> @@ -128,38 +128,38 @@ dock_write_register(0x22, 0xa9); /* enable serial port */ - dock_write_register(0x07, PC87384_SP1); + dock_write_register(0x07, PC8XXXX_SP1); dock_write_register(0x30, 0x01); - dock_write_register(0x07, PC87384_GPIO); + dock_write_register(0x07, PC8XXXX_GPIO); dock_write_register(0x60, 0x16); dock_write_register(0x61, 0x20); /* enable GPIO */ dock_write_register(0x30, 0x01); - dock_gpio_set_mode(0x00, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x00, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x01, PC87384_GPIO_PIN_TYPE_PUSH_PULL | - PC87384_GPIO_PIN_OE, 0x00); + dock_gpio_set_mode(0x01, PC8XXXX_GPIO_PIN_TYPE_PUSH_PULL | + PC8XXXX_GPIO_PIN_OE, 0x00); - dock_gpio_set_mode(0x02, PC87384_GPIO_PIN_TYPE_PUSH_PULL | - PC87384_GPIO_PIN_OE, 0x00); + dock_gpio_set_mode(0x02, PC8XXXX_GPIO_PIN_TYPE_PUSH_PULL | + PC8XXXX_GPIO_PIN_OE, 0x00); - dock_gpio_set_mode(0x03, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x03, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x04, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x04, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x05, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x05, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x06, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x06, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x07, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x07, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, 0x00); /* no GPIO events enabled for PORT0 */ diff --git a/src/mainboard/lenovo/x60/dock.c b/src/mainboard/lenovo/x60/dock.c index b94d818..cf5e71d 100644 --- a/src/mainboard/lenovo/x60/dock.c +++ b/src/mainboard/lenovo/x60/dock.c @@ -20,7 +20,7 @@ #include <delay.h> #include "dock.h" #include <southbridge/intel/i82801gx/i82801gx.h> -#include <superio/nsc/pc87392/pc87392.h> +#include <superio/nsc/common/superio_defs.h> static void dlpc_write_register(int reg, int value) { @@ -165,58 +165,58 @@ dock_write_register(0x61, 0x20); /* init GPIO pins */ - dock_gpio_set_mode(0x00, PC87392_GPIO_PIN_DEBOUNCE | - PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x00, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x01, PC87392_GPIO_PIN_DEBOUNCE | - PC87392_GPIO_PIN_PULLUP, - PC87392_GPIO_PIN_TRIGGERS_SMI); + dock_gpio_set_mode(0x01, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, + PC8XXXX_GPIO_PIN_TRIGGERS_SMI); - dock_gpio_set_mode(0x02, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x03, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x04, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x05, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x06, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x07, PC87392_GPIO_PIN_PULLUP, 0x02); + dock_gpio_set_mode(0x02, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x03, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x04, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x05, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x06, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x07, PC8XXXX_GPIO_PIN_PULLUP, 0x02); - dock_gpio_set_mode(0x10, PC87392_GPIO_PIN_DEBOUNCE | - PC87392_GPIO_PIN_PULLUP, - PC87392_GPIO_PIN_TRIGGERS_SMI); + dock_gpio_set_mode(0x10, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, + PC8XXXX_GPIO_PIN_TRIGGERS_SMI); - dock_gpio_set_mode(0x11, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x12, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x13, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x14, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x15, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x16, PC87392_GPIO_PIN_PULLUP | - PC87392_GPIO_PIN_OE, 0x00); + dock_gpio_set_mode(0x11, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x12, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x13, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x14, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x15, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x16, PC8XXXX_GPIO_PIN_PULLUP | + PC8XXXX_GPIO_PIN_OE, 0x00); - dock_gpio_set_mode(0x17, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x17, PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x20, PC87392_GPIO_PIN_TYPE_PUSH_PULL | - PC87392_GPIO_PIN_OE, 0x00); + dock_gpio_set_mode(0x20, PC8XXXX_GPIO_PIN_TYPE_PUSH_PULL | + PC8XXXX_GPIO_PIN_OE, 0x00); - dock_gpio_set_mode(0x21, PC87392_GPIO_PIN_TYPE_PUSH_PULL | - PC87392_GPIO_PIN_OE, 0x00); + dock_gpio_set_mode(0x21, PC8XXXX_GPIO_PIN_TYPE_PUSH_PULL | + PC8XXXX_GPIO_PIN_OE, 0x00); - dock_gpio_set_mode(0x22, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x23, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x24, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x25, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x26, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x27, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x22, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x23, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x24, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x25, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x26, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x27, PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x30, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x31, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x32, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x33, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x34, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x30, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x31, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x32, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x33, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x34, PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x35, PC87392_GPIO_PIN_PULLUP | - PC87392_GPIO_PIN_OE, 0x00); + dock_gpio_set_mode(0x35, PC8XXXX_GPIO_PIN_PULLUP | + PC8XXXX_GPIO_PIN_OE, 0x00); - dock_gpio_set_mode(0x36, PC87392_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x37, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x36, PC8XXXX_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x37, PC8XXXX_GPIO_PIN_PULLUP, 0x00); /* enable GPIO */ dock_write_register(0x30, 0x01); diff --git a/src/mainboard/lenovo/z61t/dock.c b/src/mainboard/lenovo/z61t/dock.c index 05dd65e..57a5a00 100644 --- a/src/mainboard/lenovo/z61t/dock.c +++ b/src/mainboard/lenovo/z61t/dock.c @@ -18,7 +18,7 @@ #include <arch/io.h> #include <delay.h> #include "dock.h" -#include <superio/nsc/pc87384/pc87384.h> +#include <superio/nsc/common/superio_defs.h> #include "ec/acpi/ec.h" #include "ec/lenovo/pmh7/pmh7.h" #include <southbridge/intel/i82801gx/i82801gx.h> @@ -128,38 +128,38 @@ dock_write_register(0x22, 0xa9); /* enable serial port */ - dock_write_register(0x07, PC87384_SP1); + dock_write_register(0x07, PC8XXXX_SP1); dock_write_register(0x30, 0x01); - dock_write_register(0x07, PC87384_GPIO); + dock_write_register(0x07, PC8XXXX_GPIO); dock_write_register(0x60, 0x16); dock_write_register(0x61, 0x20); /* enable GPIO */ dock_write_register(0x30, 0x01); - dock_gpio_set_mode(0x00, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x00, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x01, PC87384_GPIO_PIN_TYPE_PUSH_PULL | - PC87384_GPIO_PIN_OE, 0x00); + dock_gpio_set_mode(0x01, PC8XXXX_GPIO_PIN_TYPE_PUSH_PULL | + PC8XXXX_GPIO_PIN_OE, 0x00); - dock_gpio_set_mode(0x02, PC87384_GPIO_PIN_TYPE_PUSH_PULL | - PC87384_GPIO_PIN_OE, 0x00); + dock_gpio_set_mode(0x02, PC8XXXX_GPIO_PIN_TYPE_PUSH_PULL | + PC8XXXX_GPIO_PIN_OE, 0x00); - dock_gpio_set_mode(0x03, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x03, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x04, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x04, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x05, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x05, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x06, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x06, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, 0x00); - dock_gpio_set_mode(0x07, PC87384_GPIO_PIN_DEBOUNCE | - PC87384_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x07, PC8XXXX_GPIO_PIN_DEBOUNCE | + PC8XXXX_GPIO_PIN_PULLUP, 0x00); /* no GPIO events enabled for PORT0 */ diff --git a/src/superio/nsc/common/superio_defs.h b/src/superio/nsc/common/superio_defs.h new file mode 100644 index 0000000..cc35508 --- /dev/null +++ b/src/superio/nsc/common/superio_defs.h @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * Copyright (C) 2004 Tyan + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_NSC_COMMON_SUPERIO_DEFS_H +#define SUPERIO_NSC_COMMON_SUPERIO_DEFS_H + +#define PC8XXXX_FDC 0x00 /* Floppy */ +#define PC8XXXX_PP 0x01 /* Parallel port */ +#define PC8XXXX_SP2 0x02 /* COM 2 / IR */ +#define PC8XXXX_SP1 0x03 /* COM 1 */ +#define PC8XXXX_SWC 0x04 /* System wakeup control */ +//#define PC8XXXX_PM 0x04 /* Power management */ +#define PC8XXXX_KBCM 0x05 /* Mouse */ +#define PC8XXXX_KBCK 0x06 /* Keyboard */ +#define PC8XXXX_GPIO 0x07 /* General purpose IO */ +//#define PC8XXXX_HM 0x08 +#define PC8XXXX_FSD 0x08 /* Fan speed device */ +#define PC8XXXX_ACB 0x08 +#define PC8XXXX_FSCM 0x09 +#define PC8XXXX_FMC 0x09 +#define PC8XXXX_WDT 0x0A +#define PC8XXXX_GMP 0x0B +#define PC8XXXX_MIDI 0x0C +#define PC8XXXX_VLM 0x0D +#define PC8XXXX_TMS 0x0E +#define PC8XXXX_XBUS 0x0F +#define PC8XXXX_RTC 0x10 +#define PC8XXXX_MHC 0x14 +#define PC8XXXX_DOCK 0x19 + +#define PC8XXXX_GPIO_PIN_OE 0x01 +#define PC8XXXX_GPIO_PIN_TYPE_PUSH_PULL 0x02 +#define PC8XXXX_GPIO_PIN_PULLUP 0x04 +#define PC8XXXX_GPIO_PIN_LOCK 0x08 +#define PC8XXXX_GPIO_PIN_TRIG_LEVEL 0x10 +#define PC8XXXX_GPIO_PIN_TRIG_LOW 0x20 +#define PC8XXXX_GPIO_PIN_DEBOUNCE 0x40 + +#define PC8XXXX_GPIO_PIN_TRIGGERS_IRQ 0x01 +#define PC8XXXX_GPIO_PIN_TRIGGERS_SMI 0x02 + +#endif /* SUPERIO_NSC_COMMON_SUPERIO_DEFS_H */ diff --git a/src/superio/nsc/pc87309/pc87309.h b/src/superio/nsc/pc87309/pc87309.h deleted file mode 100644 index 3b912ea..0000000 --- a/src/superio/nsc/pc87309/pc87309.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_NSC_PC87309_H -#define SUPERIO_NSC_PC87309_H - -/* Datasheet: PC87309 SuperI/O Plug and Play Compatible Chip. */ - -#define PC87309_FDC 0x00 /* Floppy */ -#define PC87309_PP 0x01 /* Parallel port */ -#define PC87309_SP2 0x02 /* Com2 / IR */ -#define PC87309_SP1 0x03 /* Com1 */ -#define PC87309_PM 0x04 /* Power management */ -#define PC87309_KBCM 0x05 /* Mouse */ -#define PC87309_KBCK 0x06 /* Keyboard */ - -#endif /* SUPERIO_NSC_PC87309_H */ diff --git a/src/superio/nsc/pc87309/superio.c b/src/superio/nsc/pc87309/superio.c index 458c501..f63bea9 100644 --- a/src/superio/nsc/pc87309/superio.c +++ b/src/superio/nsc/pc87309/superio.c @@ -19,7 +19,7 @@ #include <device/pnp.h> #include <pc80/keyboard.h> #include <stdlib.h> -#include "pc87309.h" +#include <superio/nsc/common/superio_defs.h> static void init(struct device *dev) { @@ -28,7 +28,7 @@ return; switch (dev->path.pnp.device) { - case PC87309_KBCK: + case PC8XXXX_KBCK: pc_keyboard_init(NO_AUX_DEVICE); break; } @@ -43,14 +43,14 @@ }; static struct pnp_info pnp_dev_info[] = { - { NULL, PC87309_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, PC87309_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, PC87309_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, + { NULL, PC8XXXX_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, + { NULL, PC8XXXX_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, + { NULL, PC8XXXX_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, 0x07f8, }, - { NULL, PC87309_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, + { NULL, PC8XXXX_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, /* TODO: PM. */ - { NULL, PC87309_KBCM, PNP_IRQ0, }, - { NULL, PC87309_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x7f8, }, + { NULL, PC8XXXX_KBCM, PNP_IRQ0, }, + { NULL, PC8XXXX_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x7f8, }, }; static void enable_dev(struct device *dev) diff --git a/src/superio/nsc/pc87360/pc87360.h b/src/superio/nsc/pc87360/pc87360.h deleted file mode 100644 index c969746..0000000 --- a/src/superio/nsc/pc87360/pc87360.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_NSC_PC87360_H -#define SUPERIO_NSC_PC87360_H - -#define PC87360_FDC 0x00 /* Floppy */ -#define PC87360_PP 0x01 /* Parallel port */ -#define PC87360_SP2 0x02 /* Com2 */ -#define PC87360_SP1 0x03 /* Com1 */ -#define PC87360_SWC 0x04 -#define PC87360_KBCM 0x05 /* Mouse */ -#define PC87360_KBCK 0x06 /* Keyboard */ -#define PC87360_GPIO 0x07 -#define PC87360_ACB 0x08 -#define PC87360_FSCM 0x09 -#define PC87360_WDT 0x0A - -#endif /* SUPERIO_NSC_PC87360_H */ diff --git a/src/superio/nsc/pc87360/superio.c b/src/superio/nsc/pc87360/superio.c index cf5c7ca..85f21a2 100644 --- a/src/superio/nsc/pc87360/superio.c +++ b/src/superio/nsc/pc87360/superio.c @@ -21,7 +21,7 @@ #include <string.h> #include <pc80/keyboard.h> #include <stdlib.h> -#include "pc87360.h" +#include <superio/nsc/common/superio_defs.h> static void init(struct device *dev) { @@ -29,7 +29,7 @@ return; switch (dev->path.pnp.device) { - case PC87360_KBCK: + case PC8XXXX_KBCK: pc_keyboard_init(NO_AUX_DEVICE); break; } @@ -44,18 +44,18 @@ }; static struct pnp_info pnp_dev_info[] = { - { NULL, PC87360_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, PC87360_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, PC87360_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, + { NULL, PC8XXXX_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, + { NULL, PC8XXXX_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, + { NULL, PC8XXXX_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, 0x07f8, }, - { NULL, PC87360_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, - { NULL, PC87360_SWC, PNP_IO0 | PNP_IRQ0, 0xfff0, }, - { NULL, PC87360_KBCM, PNP_IRQ0, }, - { NULL, PC87360_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, }, - { NULL, PC87360_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8, }, - { NULL, PC87360_ACB, PNP_IO0 | PNP_IRQ0, 0xfff8, }, - { NULL, PC87360_FSCM, PNP_IO0 | PNP_IRQ0, 0xfff8, }, - { NULL, PC87360_WDT, PNP_IO0 | PNP_IRQ0, 0xfffc, }, + { NULL, PC8XXXX_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, + { NULL, PC8XXXX_SWC, PNP_IO0 | PNP_IRQ0, 0xfff0, }, + { NULL, PC8XXXX_KBCM, PNP_IRQ0, }, + { NULL, PC8XXXX_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, }, + { NULL, PC8XXXX_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8, }, + { NULL, PC8XXXX_ACB, PNP_IO0 | PNP_IRQ0, 0xfff8, }, + { NULL, PC8XXXX_FSCM, PNP_IO0 | PNP_IRQ0, 0xfff8, }, + { NULL, PC8XXXX_WDT, PNP_IO0 | PNP_IRQ0, 0xfffc, }, }; static void enable_dev(struct device *dev) diff --git a/src/superio/nsc/pc87366/pc87366.h b/src/superio/nsc/pc87366/pc87366.h deleted file mode 100644 index b1df69f..0000000 --- a/src/superio/nsc/pc87366/pc87366.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_NSC_PC87366_H -#define SUPERIO_NSC_PC87366_H - -#define PC87366_FDC 0x00 /* Floppy */ -#define PC87366_PP 0x01 /* Parallel port */ -#define PC87366_SP2 0x02 /* Com2 */ -#define PC87366_SP1 0x03 /* Com1 */ -#define PC87366_SWC 0x04 -#define PC87366_KBCM 0x05 /* Mouse */ -#define PC87366_KBCK 0x06 /* Keyboard */ -#define PC87366_GPIO 0x07 -#define PC87366_ACB 0x08 -#define PC87366_FSCM 0x09 -#define PC87366_WDT 0x0A -#define PC87366_GMP 0x0b -#define PC87366_MIDI 0x0C -#define PC87366_VLM 0x0D -#define PC87366_TMS 0x0E - -#endif /* SUPERIO_NSC_PC87366_H */ diff --git a/src/superio/nsc/pc87366/superio.c b/src/superio/nsc/pc87366/superio.c index e1cba17..60e5e23 100644 --- a/src/superio/nsc/pc87366/superio.c +++ b/src/superio/nsc/pc87366/superio.c @@ -21,7 +21,7 @@ #include <string.h> #include <pc80/keyboard.h> #include <stdlib.h> -#include "pc87366.h" +#include <superio/nsc/common/superio_defs.h> static void init(struct device *dev) { @@ -29,7 +29,7 @@ return; switch (dev->path.pnp.device) { - case PC87366_KBCK: + case PC8XXXX_KBCK: pc_keyboard_init(NO_AUX_DEVICE); break; } @@ -44,18 +44,18 @@ }; static struct pnp_info pnp_dev_info[] = { - { NULL, PC87366_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, PC87366_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, PC87366_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, + { NULL, PC8XXXX_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, + { NULL, PC8XXXX_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, + { NULL, PC8XXXX_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, 0x07f8, }, - { NULL, PC87366_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, - { NULL, PC87366_SWC, PNP_IO0 | PNP_IRQ0, 0xfff0, }, - { NULL, PC87366_KBCM, PNP_IRQ0, }, - { NULL, PC87366_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, }, - { NULL, PC87366_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8, }, - { NULL, PC87366_ACB, PNP_IO0 | PNP_IRQ0, 0xfff8, }, - { NULL, PC87366_FSCM, PNP_IO0 | PNP_IRQ0, 0xfff8, }, - { NULL, PC87366_WDT, PNP_IO0 | PNP_IRQ0, 0xfffc, }, + { NULL, PC8XXXX_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, + { NULL, PC8XXXX_SWC, PNP_IO0 | PNP_IRQ0, 0xfff0, }, + { NULL, PC8XXXX_KBCM, PNP_IRQ0, }, + { NULL, PC8XXXX_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, }, + { NULL, PC8XXXX_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8, }, + { NULL, PC8XXXX_ACB, PNP_IO0 | PNP_IRQ0, 0xfff8, }, + { NULL, PC8XXXX_FSCM, PNP_IO0 | PNP_IRQ0, 0xfff8, }, + { NULL, PC8XXXX_WDT, PNP_IO0 | PNP_IRQ0, 0xfffc, }, }; static void enable_dev(struct device *dev) diff --git a/src/superio/nsc/pc87382/pc87382.h b/src/superio/nsc/pc87382/pc87382.h deleted file mode 100644 index 6826f45..0000000 --- a/src/superio/nsc/pc87382/pc87382.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_NSC_PC87382_H -#define SUPERIO_NSC_PC87382_H - -#define PC87382_IR 0x02 -#define PC87382_SP1 0x03 -#define PC87382_GPIO 0x07 -#define PC87382_DOCK 0x19 -#endif diff --git a/src/superio/nsc/pc87382/superio.c b/src/superio/nsc/pc87382/superio.c index 688f08c..6a21f51 100644 --- a/src/superio/nsc/pc87382/superio.c +++ b/src/superio/nsc/pc87382/superio.c @@ -19,7 +19,7 @@ #include <device/pnp.h> #include <string.h> #include <stdlib.h> -#include "pc87382.h" +#include <superio/nsc/common/superio_defs.h> static void init(struct device *dev) { @@ -27,10 +27,10 @@ return; switch (dev->path.pnp.device) { - case PC87382_DOCK: + case PC8XXXX_DOCK: break; - case PC87382_GPIO: + case PC8XXXX_GPIO: break; } } @@ -44,11 +44,11 @@ }; static struct pnp_info pnp_dev_info[] = { - { NULL, PC87382_IR, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, + { NULL, PC8XXXX_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, 0x07f8 }, - { NULL, PC87382_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8 }, - { NULL, PC87382_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff0 }, - { NULL, PC87382_DOCK, PNP_IO0 | PNP_IRQ0, 0xfffe }, + { NULL, PC8XXXX_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8 }, + { NULL, PC8XXXX_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff0 }, + { NULL, PC8XXXX_DOCK, PNP_IO0 | PNP_IRQ0, 0xfffe }, }; static void enable_dev(struct device *dev) diff --git a/src/superio/nsc/pc87384/pc87384.h b/src/superio/nsc/pc87384/pc87384.h deleted file mode 100644 index 2184584..0000000 --- a/src/superio/nsc/pc87384/pc87384.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_NSC_PC87384_H -#define SUPERIO_NSC_PC87384_H - -#define PC87384_PP 0x01 -#define PC87384_SP2 0x02 -#define PC87384_SP1 0x03 -#define PC87384_GPIO 0x07 - -#define PC87384_GPIO_PIN_OE 0x01 -#define PC87384_GPIO_PIN_TYPE_PUSH_PULL 0x02 -#define PC87384_GPIO_PIN_PULLUP 0x04 -#define PC87384_GPIO_PIN_LOCK 0x08 -#define PC87384_GPIO_PIN_TRIG_LEVEL 0x10 -#define PC87384_GPIO_PIN_TRIG_LOW 0x20 -#define PC87384_GPIO_PIN_DEBOUNCE 0x40 - -#define PC87384_GPIO_PIN_TRIGGERS_IRQ 0x01 - -#endif diff --git a/src/superio/nsc/pc87384/superio.c b/src/superio/nsc/pc87384/superio.c index f34acd5..9548d2c 100644 --- a/src/superio/nsc/pc87384/superio.c +++ b/src/superio/nsc/pc87384/superio.c @@ -19,7 +19,7 @@ #include <device/pnp.h> #include <string.h> #include <stdlib.h> -#include "pc87384.h" +#include <superio/nsc/common/superio_defs.h> static struct device_operations ops = { .read_resources = pnp_read_resources, @@ -29,10 +29,10 @@ }; static struct pnp_info pnp_dev_info[] = { - { NULL, PC87384_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8 }, - { NULL, PC87384_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8 }, - { NULL, PC87384_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8 }, - { NULL, PC87384_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff0 }, + { NULL, PC8XXXX_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8 }, + { NULL, PC8XXXX_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8 }, + { NULL, PC8XXXX_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8 }, + { NULL, PC8XXXX_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff0 }, }; static void enable_dev(struct device *dev) diff --git a/src/superio/nsc/pc87392/pc87392.h b/src/superio/nsc/pc87392/pc87392.h deleted file mode 100644 index 5832435..0000000 --- a/src/superio/nsc/pc87392/pc87392.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_NSC_PC87392_H -#define SUPERIO_NSC_PC87392_H - -#define PC87392_FDC 0x00 -#define PC87392_PP 0x01 -#define PC87392_SP2 0x02 -#define PC87392_SP1 0x03 -#define PC87392_GPIO 0x07 -#define PC87392_WDT 0x0A - -#define PC87392_GPIO_PIN_OE 0x01 -#define PC87392_GPIO_PIN_TYPE_PUSH_PULL 0x02 -#define PC87392_GPIO_PIN_PULLUP 0x04 -#define PC87392_GPIO_PIN_LOCK 0x08 -#define PC87392_GPIO_PIN_TRIG_LEVEL 0x10 -#define PC87392_GPIO_PIN_TRIG_LOW 0x20 -#define PC87392_GPIO_PIN_DEBOUNCE 0x40 - -#define PC87392_GPIO_PIN_TRIGGERS_IRQ 0x01 -#define PC87392_GPIO_PIN_TRIGGERS_SMI 0x02 - -#endif diff --git a/src/superio/nsc/pc87392/superio.c b/src/superio/nsc/pc87392/superio.c index edd4619..9971b5c 100644 --- a/src/superio/nsc/pc87392/superio.c +++ b/src/superio/nsc/pc87392/superio.c @@ -19,7 +19,7 @@ #include <device/pnp.h> #include <string.h> #include <stdlib.h> -#include "pc87392.h" +#include <superio/nsc/common/superio_defs.h> static void init(struct device *dev) { @@ -36,13 +36,13 @@ }; static struct pnp_info pnp_dev_info[] = { - { NULL, PC87392_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8 }, - { NULL, PC87392_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8 }, - { NULL, PC87392_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, + { NULL, PC8XXXX_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8 }, + { NULL, PC8XXXX_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8 }, + { NULL, PC8XXXX_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, 0x07f8 }, - { NULL, PC87392_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8 }, - { NULL, PC87392_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8 }, - { NULL, PC87392_WDT, PNP_IO0 | PNP_IRQ0, 0xfffc }, + { NULL, PC8XXXX_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8 }, + { NULL, PC8XXXX_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8 }, + { NULL, PC8XXXX_WDT, PNP_IO0 | PNP_IRQ0, 0xfffc }, }; static void enable_dev(struct device *dev) diff --git a/src/superio/nsc/pc87417/pc87417.h b/src/superio/nsc/pc87417/pc87417.h index b50a920..e6c7f79 100644 --- a/src/superio/nsc/pc87417/pc87417.h +++ b/src/superio/nsc/pc87417/pc87417.h @@ -19,17 +19,6 @@ #ifndef SUPERIO_NSC_PC87417_H #define SUPERIO_NSC_PC87417_H -#define PC87417_FDC 0x00 /* Floppy */ -#define PC87417_PP 0x01 /* Parallel Port */ -#define PC87417_SP2 0x02 /* Com2 */ -#define PC87417_SP1 0x03 /* Com1 */ -#define PC87417_SWC 0x04 /* System Wake-Up Controller (SWC) */ -#define PC87417_KBCM 0x05 /* Mouse */ -#define PC87417_KBCK 0x06 /* Keyboard */ -#define PC87417_GPIO 0x07 -#define PC87417_XBUS 0x0F -#define PC87417_RTC 0x10 - #define PC87417_GPIO_DEV PNP_DEV(0x2e, PC87417_GPIO) /* This is to get around a romcc bug */ /* #define PC87417_XBUS_DEV PNP_DEV(0x2e, PC87417_XBUS) */ diff --git a/src/superio/nsc/pc87417/superio.c b/src/superio/nsc/pc87417/superio.c index f0e0bb1..a4e8022 100644 --- a/src/superio/nsc/pc87417/superio.c +++ b/src/superio/nsc/pc87417/superio.c @@ -22,7 +22,7 @@ #include <string.h> #include <pc80/keyboard.h> #include <stdlib.h> -#include "pc87417.h" +#include <superio/nsc/common/superio_defs.h> static void init(struct device *dev) { @@ -30,7 +30,7 @@ return; switch (dev->path.pnp.device) { - case PC87417_KBCK: + case PC8XXXX_KBCK: pc_keyboard_init(NO_AUX_DEVICE); break; } @@ -45,17 +45,17 @@ }; static struct pnp_info pnp_dev_info[] = { - { NULL, PC87417_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, PC87417_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { NULL, PC87417_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, + { NULL, PC8XXXX_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, + { NULL, PC8XXXX_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, + { NULL, PC8XXXX_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, 0x07f8, }, - { NULL, PC87417_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, - { NULL, PC87417_SWC, PNP_IO0 | PNP_IRQ0, 0xfff0, }, - { NULL, PC87417_KBCM, PNP_IRQ0, }, - { NULL, PC87417_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, }, - { NULL, PC87417_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8, }, - { NULL, PC87417_XBUS, PNP_IO0 | PNP_IRQ0, 0xffe0, }, - { NULL, PC87417_RTC, PNP_IO0 | PNP_IO1, 0xfffe, 0xfffe, }, + { NULL, PC8XXXX_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, + { NULL, PC8XXXX_SWC, PNP_IO0 | PNP_IRQ0, 0xfff0, }, + { NULL, PC8XXXX_KBCM, PNP_IRQ0, }, + { NULL, PC8XXXX_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, }, + { NULL, PC8XXXX_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8, }, + { NULL, PC8XXXX_XBUS, PNP_IO0 | PNP_IRQ0, 0xffe0, }, + { NULL, PC8XXXX_RTC, PNP_IO0 | PNP_IO1, 0xfffe, 0xfffe, }, }; static void enable_dev(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/31427 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iffdb4752f3075b1a1b391d4cf8d4416748bfe485 Gerrit-Change-Number: 31427 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

3 days, 17 hours

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Change in ...coreboot[master]: intel/skylake: nhlt: Add 24 bit blobs for Max98373

by Jenny Tc (Code Review)

Jenny Tc has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31635 Change subject: intel/skylake: nhlt: Add 24 bit blobs for Max98373 ...................................................................... intel/skylake: nhlt: Add 24 bit blobs for Max98373 Enable 24 bit nhlt blobs and remove 16 bit blobs. 16 bit and 24 bit blobs cannot be supported together since the OS NHLT parsing relies on container bit format. The container bit format for 16 and 24 bit capture are same (32) and putting both blobs in configs results in selecting the first blob. To enable 24 and 16 bit blobs together, the core nhlt parsing logic has to be changed which would impact SKL and KBL platforms. In order to minimize the impact, the 16 bit blob is removed considering that the machine driver for max98373 is expected to support only format due to topology configuration for 16 and 24 bit. BUG=b:110795132 BRANCH=none TEST=Verify playback after flashing CQ-DEPEND=*806750 Change-Id: I62cc109fb0aca9269736779a6ce80980b0571b78 Signed-off-by: Jenny TC <jenny.tc(a)intel.com> --- M src/soc/intel/skylake/nhlt/Makefile.inc M src/soc/intel/skylake/nhlt/max98373.c 2 files changed, 6 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/31635/1 diff --git a/src/soc/intel/skylake/nhlt/Makefile.inc b/src/soc/intel/skylake/nhlt/Makefile.inc index 5c8bd80..548747a 100644 --- a/src/soc/intel/skylake/nhlt/Makefile.inc +++ b/src/soc/intel/skylake/nhlt/Makefile.inc @@ -21,7 +21,6 @@ DMIC_4CH_48KHZ_32B = dmic-4ch-48khz-32b.bin NAU88L25 = nau88l25-2ch-48khz-24b.bin MAX98357_RENDER = max98357-render-2ch-48khz-24b.bin -MAX98373_RENDER_16B = max98373-render-2ch-48khz-16b.bin MAX98373_RENDER_24B = max98373-render-2ch-48khz-24b.bin MAX98927_RENDER_24B = max98927-render-2ch-48khz-24b.bin MAX98927_RENDER_16B = max98927-render-2ch-48khz-16b.bin diff --git a/src/soc/intel/skylake/nhlt/max98373.c b/src/soc/intel/skylake/nhlt/max98373.c index 0e3a413..a781943 100644 --- a/src/soc/intel/skylake/nhlt/max98373.c +++ b/src/soc/intel/skylake/nhlt/max98373.c @@ -25,35 +25,26 @@ .speaker_mask = SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT, .settings_file = "max98373-render-2ch-48khz-24b.bin", }, - /* 48 KHz 16-bits per sample. */ - { - .num_channels = 2, - .sample_freq_khz = 48, - .container_bits_per_sample = 16, - .valid_bits_per_sample = 16, - .speaker_mask = SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT, - .settings_file = "max98373-render-2ch-48khz-16b.bin", - } }; static const struct nhlt_format_config max98373_capture_formats[] = { - /* 48 KHz 16-bits per sample - Quad Channel. */ + /* 48 KHz 24-bits per sample - Quad Channel. */ { .num_channels = 4, .sample_freq_khz = 48, .container_bits_per_sample = 32, - .valid_bits_per_sample = 16, + .valid_bits_per_sample = 24, .speaker_mask = SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT, - .settings_file = "max98373-render-2ch-48khz-16b.bin", + .settings_file = "max98373-render-2ch-48khz-24b.bin", }, - /* 48 KHz 16-bits per sample - Stereo Channel */ + /* 48 KHz 24-bits per sample - Stereo Channel */ { .num_channels = 2, .sample_freq_khz = 48, .container_bits_per_sample = 32, - .valid_bits_per_sample = 16, + .valid_bits_per_sample = 24, .speaker_mask = SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT, - .settings_file = "max98373-render-2ch-48khz-16b.bin", + .settings_file = "max98373-render-2ch-48khz-24b.bin", }, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/31635 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62cc109fb0aca9269736779a6ce80980b0571b78 Gerrit-Change-Number: 31635 Gerrit-PatchSet: 1 Gerrit-Owner: Jenny Tc <jenny.tc(a)intel.com> Gerrit-MessageType: newchange

4 days

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Change in ...coreboot[master]: arch/x86: Add option for running Romstage out of RAM

by Martin Roth (Code Review)

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32414 Change subject: arch/x86: Add option for running Romstage out of RAM ...................................................................... arch/x86: Add option for running Romstage out of RAM AMD's Picasso SOC brings up memory before releasing the X86 processor, and jumps directly to Romstage. Add a global config option to handle that. TEST=None BUG=b:130804851 Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: I678b1f74546ea30abcc655a0daed795d6cfa0034 --- M src/Kconfig M src/arch/x86/assembly_entry.S M src/arch/x86/memlayout.ld 3 files changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/32414/1 diff --git a/src/Kconfig b/src/Kconfig index 62b3818..bfa0b51 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -146,6 +146,16 @@ time spent decompressing. Doesn't work for XIP stages (assume all ARCH_X86 for now) for obvious reasons. +config ROMSTAGE_IN_RAM + bool + depends on ARCH_X86 + help + Some newer x86 processors come alive with memory enabled, and the + reset vector's physical address falling within DRAM. Select this + item to build romstage to execute in DRAM instead of XIP. Because + this is not a standard, the soc/ or cpu/ code must handle the reset + natively before jumping into the standard romstage code. + config COMPRESS_BOOTBLOCK bool help diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S index 4ead9ea..01c0865 100644 --- a/src/arch/x86/assembly_entry.S +++ b/src/arch/x86/assembly_entry.S @@ -26,6 +26,16 @@ * variables that are stage specific. */ .section ".text._start", "ax", @progbits +#if ENV_ROMSTAGE && IS_ENABLED(CONFIG_ROMSTAGE_IN_RAM) +/* + * Systems that run romstage in DRAM, i.e. where romstage is the first + * executed code, are responsible for getting the processor into protected + * mode, setting the stack pointer, and jumping to this location. + */ +.global _romstage_in_ram_continue +_romstage_in_ram_continue: + +#else .global _start _start: @@ -34,6 +44,7 @@ /* reset stack pointer to CAR stack */ mov $_car_stack_end, %esp +#endif /* clear CAR_GLOBAL area as it is not shared */ cld diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld index cc72552..da63b05 100644 --- a/src/arch/x86/memlayout.ld +++ b/src/arch/x86/memlayout.ld @@ -57,6 +57,10 @@ #endif } +#if ENV_ROMSTAGE && CONFIG(ROMSTAGE_IN_RAM) +#include <soc/romstage.ld> +#endif + #if ENV_BOOTBLOCK /* Bootblock specific scripts which provide more SECTION directives. */ #include <cpu/x86/16bit/entry16.ld> -- To view, visit https://review.coreboot.org/c/coreboot/+/32414 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I678b1f74546ea30abcc655a0daed795d6cfa0034 Gerrit-Change-Number: 32414 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

4 days, 6 hours

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Change in ...coreboot[master]: Adding Asus A88XM-E FM2+ motherboard with documentation

by Balázs Vinarz (Code Review)

Balázs Vinarz has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30987 Change subject: Adding Asus A88XM-E FM2+ motherboard with documentation ...................................................................... Adding Asus A88XM-E FM2+ motherboard with documentation Signed-off-by: Balazs Vinarz <vinibali1(a)gmail.com> Change-Id: I60fa0636ba41f5f1a6a3faa2764bf2f0a968cf90 --- A Documentation/mainboard/asus/a88xm-e.md A src/mainboard/asus/a88xm-e/BiosCallOuts.c A src/mainboard/asus/a88xm-e/Kconfig A src/mainboard/asus/a88xm-e/Kconfig.name A src/mainboard/asus/a88xm-e/Makefile.inc A src/mainboard/asus/a88xm-e/OemCustomize.c A src/mainboard/asus/a88xm-e/OptionsIds.h A src/mainboard/asus/a88xm-e/acpi/cpstate.asl A src/mainboard/asus/a88xm-e/acpi/gpe.asl A src/mainboard/asus/a88xm-e/acpi/mainboard.asl A src/mainboard/asus/a88xm-e/acpi/routing.asl A src/mainboard/asus/a88xm-e/acpi/sata.asl A src/mainboard/asus/a88xm-e/acpi/si.asl A src/mainboard/asus/a88xm-e/acpi/sleep.asl A src/mainboard/asus/a88xm-e/acpi/superio.asl A src/mainboard/asus/a88xm-e/acpi/thermal.asl A src/mainboard/asus/a88xm-e/acpi/usb_oc.asl A src/mainboard/asus/a88xm-e/acpi_tables.c A src/mainboard/asus/a88xm-e/board_info.txt A src/mainboard/asus/a88xm-e/buildOpts.c A src/mainboard/asus/a88xm-e/cmos.layout A src/mainboard/asus/a88xm-e/devicetree_a88xm-e.cb A src/mainboard/asus/a88xm-e/dsdt.asl A src/mainboard/asus/a88xm-e/irq_tables.c A src/mainboard/asus/a88xm-e/mainboard.c A src/mainboard/asus/a88xm-e/mptable.c A src/mainboard/asus/a88xm-e/romstage.c 27 files changed, 2,371 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/30987/1 diff --git a/Documentation/mainboard/asus/a88xm-e.md b/Documentation/mainboard/asus/a88xm-e.md new file mode 100644 index 0000000..5f50c5a --- /dev/null +++ b/Documentation/mainboard/asus/a88xm-e.md @@ -0,0 +1,131 @@ +# ASUS A88XM-E + +This page describes how to run coreboot on the [ASUS A88XM-E]. + +## Technology + +Both "Trinity" and "Richland" FM2 desktop processing units are working, +the CPU architecture in these CPUs/APUs are [Piledriver], +and their GPU is [TeraScale 3] (VLIW4-based). + +Kaveri is non-working at the moment (FM2+), +the CPU architecture in these CPUs/APUs are [Steamroller], +and their GPU is [Sea Islands] (GCN2-based). + +```eval_rst ++------------------+--------------------------------------------------+ +| A88XM-E | | ++------------------+--------------------------------------------------+ +| DDR voltage IC | Nuvoton 3101S | ++------------------+--------------------------------------------------+ +| Network | Realtek RTL8111G - Not working | ++------------------+--------------------------------------------------+ +| Northbridge | Integrated into CPU with IMC and GPU (APUs only) | ++------------------+--------------------------------------------------+ +| Southbridge | Bolton-D4 | ++------------------+--------------------------------------------------+ +| Sound IC | Realtek ALC887 | ++------------------+--------------------------------------------------+ +| Super I/O | ITE 8603E | ++------------------+--------------------------------------------------+ +| VRM controller | DIGI VRM ASP1206 | ++------------------+--------------------------------------------------+ +``` + +## Flashing coreboot + +```eval_rst ++---------------------+------------+ +| Type | Value | ++=====================+============+ +| Socketed flash | yes | ++---------------------+------------+ +| Model | [GD25Q64] | ++---------------------+------------+ +| Size | 8 MiB | ++---------------------+------------+ +| Package | DIP-8 | ++---------------------+------------+ +| Write protection | yes | ++---------------------+------------+ +| Dual BIOS feature | no | ++---------------------+------------+ +| Internal flashing | yes | ++---------------------+------------+ +``` + +### Internal programming + +The main SPI flash can be accessed using [flashrom], if the +AmdSpiRomProtect modules have been deleted in the factory image previously. + +## Integrated graphics + +### Retrieve the VGA optionrom from the vendor EFI binary by running: + + # dd if=/dev/mem of=vgabios.bin bs=1k count=64 skip=768 + +This version is usable for all the GPUs. +1002,9901 Trinity (Radeon HD 7660D) +1002,9904 Trinity (Radeon HD 7560D) +1002,990c Richland (Radeon HD 8670D) +1002,990e Richland (Radeon HD 8570D) +1002,9991 Trinity (Radeon HD 7540D) +1002,9993 Trinity (Radeon HD 7480D) +1002,9996 Richland (Radeon HD 8470D) +1002,9998 Richland (Radeon HD 8370D) +1002,999d Richland (Radeon HD 8550D) +1002,130f Kaveri (Radeon R7) + +## Known issues + +- AHCI hot-plug +- Integrated ethernet +- S3 resume +- XHCI + +### XHCI ports can broke after using any of the blobs, restarting the +board with factory image makes it work again as fallback. +Tested even with/without the Bolton and Hudson blobs. + +## Untested + +- audio over HDMI +- IOMMU +- PS/2 mouse + +## TODOs + +- one ATOMBIOS module for all the integrated GPUs +- manage to work with Kaveri/Godavary (missing PSP firmware?) + +## Working + +- ACPI +- CPU frequency scaling +- flashrom under coreboot +- Hardware monitoring +- Integrated graphics +- Keyboard +- KVM virtualization +- Onboard audio +- PCI +- PCIe +- PS/2 keyboard (during payload, bootloader) +- SATA +- Serial port +- SuperIO based fan control +- USB (disabling XHCI controller makes to work as fallback USB2.0 ports) + +## Extra resources + +- [Board manual] + +[ASUS A88XM-E]: https://www.asus.com/Motherboards/A88XME/ +[Board manual]: https://dlcdnets.asus.com/pub/ASUS/mb/SocketFM2/A88XM-E/E9125_A88XM-E.pdf +[flashrom]: https://flashrom.org/Flashrom +[GD25Q64]: http://www.elm-tech.com/ja/products/spi-flash-memory/gd25q64/gd25q64.pdf +[Piledriver]: https://en.wikipedia.org/wiki/Piledriver_%28microarchitecture%29#APU_lines +[Sea Islands]: https://en.wikipedia.org/wiki/Graphics_Core_Next#GCN_2nd_generation +[Steamroller]: https://en.wikipedia.org/wiki/Steamroller_(microarchitecture) +[TeraScale 3]: https://en.wikipedia.org/wiki/TeraScale_%28microarchitecture%29#TeraScale_3 diff --git a/src/mainboard/asus/a88xm-e/BiosCallOuts.c b/src/mainboard/asus/a88xm-e/BiosCallOuts.c new file mode 100644 index 0000000..56c1753 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/BiosCallOuts.c @@ -0,0 +1,98 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <AGESA.h> +#include <northbridge/amd/agesa/BiosCallOuts.h> +#include <northbridge/amd/agesa/state_machine.h> + +#include <vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h> +#include <stdlib.h> + +const BIOS_CALLOUT_STRUCT BiosCallouts[] = +{ + {AGESA_DO_RESET, agesa_Reset }, + {AGESA_READ_SPD, agesa_ReadSpd }, + {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, + {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, + {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData }, + {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, + {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, + {AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage } +}; +const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); + +/** + * ASUS A88XM-E board ALC887-VD Verb Table + * + * Copied from `/sys/class/sound/hwC1D0/init_pin_configs` when running + * the vendor BIOS. + */ +#if !IS_ENABLED(CONFIG_BOARD_ASUS_A88XM_E) +const CODEC_ENTRY a88xm_e_alc887_VerbTbl[] = { + {0x11, 0x90460130}, + {0x12, 0x40330000}, + {0x14, 0x01014010}, + {0x15, 0x411111f0}, + {0x16, 0x411111f0}, + {0x17, 0x411111f0}, + {0x18, 0x01a19040}, + {0x19, 0x02a19050}, + {0x1a, 0x0181304f}, + {0x1b, 0x02214020}, + {0x1c, 0x411111f0}, + {0x1d, 0x4044c601}, + {0x1e, 0x411111f0}, + {0x1f, 0x411111f0} + }; +#else +const CODEC_ENTRY a88xm_e_alc887_VerbTbl[] = { + {0x11, 0x90460130}, + {0x12, 0x40330000}, + {0x14, 0x01014010}, + {0x15, 0x411111f0}, + {0x16, 0x411111f0}, + {0x17, 0x411111f0}, + {0x18, 0x01a19040}, + {0x19, 0x02a19050}, + {0x1a, 0x0181304f}, + {0x1b, 0x02214020}, + {0x1c, 0x411111f0}, + {0x1d, 0x4044c601}, + {0x1e, 0x411111f0}, + {0x1f, 0x411111f0} +}; +#endif + +static const CODEC_TBL_LIST CodecTableList[] = +{ + {0x10ec0887, (CODEC_ENTRY*)&a88xm_e_alc887_VerbTbl[0]}, + {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL} +}; + +void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset) +{ + FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE); +} + +void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env) +{ + /* Azalia Controller OEM Codec Table Pointer */ + FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&CodecTableList[0]); + + /* Fan Control */ + FchParams_env->Imc.ImcEnable = FALSE; + FchParams_env->Hwm.HwMonitorEnable = FALSE; + FchParams_env->Hwm.HwmFchtsiAutoPoll = FALSE;/* 1 enable, 0 disable TSI Auto Polling */ +} diff --git a/src/mainboard/asus/a88xm-e/Kconfig b/src/mainboard/asus/a88xm-e/Kconfig new file mode 100644 index 0000000..70be2f1 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/Kconfig @@ -0,0 +1,117 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# Copyright (C) 2012 Rudolf Marek <r.marek(a)assembler.cz> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +if BOARD_ASUS_A88XM_E + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select CPU_AMD_AGESA_FAMILY15_TN + select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN + select SOUTHBRIDGE_AMD_AGESA_HUDSON + select HAVE_OPTION_TABLE + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select SUPERIO_ITE_IT8728F + select BOARD_ROMSIZE_KB_8192 + select GFXUMA + +choice + prompt "DDR3 memory voltage" + default BOARD_ASUS_A88XM_E_DDR3_VOLT_150 + +config BOARD_ASUS_A88XM_E_DDR3_VOLT_135 + bool "1.35V" + help + Set DRR3 memory voltage to 1.35V +config BOARD_ASUS_A88XM_E_DDR3_VOLT_150 + bool "1.50V" + help + Set DRR3 memory voltage to 1.50V +config BOARD_ASUS_A88XM_E_DDR3_VOLT_165 + bool "1.65V" + help + Set DRR3 memory voltage to 1.65V +endchoice + +config BOARD_ASUS_A88XM_E_DDR3_VOLT_VAL + hex + default 0x9e if BOARD_ASUS_A88XM_E_DDR3_VOLT_135 + default 0x0 if BOARD_ASUS_A88XM_E_DDR3_VOLT_150 + default 0x1e if BOARD_ASUS_A88XM_E_DDR3_VOLT_165 + +config MAINBOARD_DIR + string + default asus/a88xm-e + +config MAINBOARD_PART_NUMBER + string + default "A88XM-E" if BOARD_ASUS_A88XM_E + +config HW_MEM_HOLE_SIZEK + hex + default 0x200000 + +config MAX_CPUS + int + default 4 + +config HUDSON_XHCI_FWM + bool + default n + +config HUDSON_IMC_FWM + bool + default n + +config IRQ_SLOT_COUNT + int + default 11 + +config ONBOARD_VGA_IS_PRIMARY + bool + default y + +config VGA_BIOS_ID + string + default "1002,990e" + +config CONFIG_DRIVERS_PS2_KEYBOARD + bool + default y + +config CONFIG_HUDSON_XHCI_ENABLE + bool + default n + +config HUDSON_LEGACY_FREE + bool + default n + +config POST_IO + bool + default n + +config CONFIG_POST_DEVICE_PCI_PCIE + bool + default y + +config DEVICETREE + string + default "devicetree_a88xm-e.cb" + +endif # BOARD_ASUS_A88XM_E diff --git a/src/mainboard/asus/a88xm-e/Kconfig.name b/src/mainboard/asus/a88xm-e/Kconfig.name new file mode 100644 index 0000000..492d610 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ASUS_A88XM_E + bool "A88XM-E" diff --git a/src/mainboard/asus/a88xm-e/Makefile.inc b/src/mainboard/asus/a88xm-e/Makefile.inc new file mode 100644 index 0000000..f8895fa --- /dev/null +++ b/src/mainboard/asus/a88xm-e/Makefile.inc @@ -0,0 +1,22 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +romstage-y += buildOpts.c +romstage-y += BiosCallOuts.c +romstage-y += OemCustomize.c + +ramstage-y += buildOpts.c +ramstage-y += BiosCallOuts.c +ramstage-y += OemCustomize.c diff --git a/src/mainboard/asus/a88xm-e/OemCustomize.c b/src/mainboard/asus/a88xm-e/OemCustomize.c new file mode 100644 index 0000000..4c4c5bf --- /dev/null +++ b/src/mainboard/asus/a88xm-e/OemCustomize.c @@ -0,0 +1,177 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <Porting.h> +#include <AGESA.h> + +#include <northbridge/amd/agesa/state_machine.h> +#include <PlatformMemoryConfiguration.h> + +/* + * Lane ID Mapping (from Fam15h BKDG: Table 45: Lane Id Mapping) + * + * Lane Id + * 0 P_UMI_[T,R]X[P,N]0 - southbridge link, connect via dev 8 + * 1 P_UMI_[T,R]X[P,N]1 - southbridge link, connect via dev 8 + * 2 P_UMI_[T,R]X[P,N]2 - southbridge link, connect via dev 8 + * 3 P_UMI_[T,R]X[P,N]3 - southbridge link, connect via dev 8 + * 4 P_GPP_[T,R]X[P,N]0 - may connect to PCI dev 4 - 7 + * 5 P_GPP_[T,R]X[P,N]1 - may connect to PCI dev 4 - 7 + * 6 P_GPP_[T,R]X[P,N]2 - may connect to PCI dev 4 - 7 + * 7 P_GPP_[T,R]X[P,N]3 - may connect to PCI dev 4 - 7 + * 8 P_GFX_[T,R]X[P,N]0 - may be used to form GFX slot or DDI + * 9 P_GFX_[T,R]X[P,N]1 - may be used to form GFX slot or DDI + * 10 P_GFX_[T,R]X[P,N]2 - may be used to form GFX slot or DDI + * 11 P_GFX_[T,R]X[P,N]3 - may be used to form GFX slot or DDI + * 12 P_GFX_[T,R]X[P,N]4 - may be used to form GFX slot or DDI + * 13 P_GFX_[T,R]X[P,N]5 - may be used to form GFX slot or DDI + * 14 P_GFX_[T,R]X[P,N]6 - may be used to form GFX slot or DDI + * 15 P_GFX_[T,R]X[P,N]7 - may be used to form GFX slot or DDI + * 16 P_GFX_[T,R]X[P,N]8 - may be used to form GFX slot or DDI + * 17 P_GFX_[T,R]X[P,N]9 - may be used to form GFX slot or DDI + * 18 P_GFX_[T,R]X[P,N]10 - may be used to form GFX slot or DDI + * 19 P_GFX_[T,R]X[P,N]11 - may be used to form GFX slot or DDI + * 20 P_GFX_[T,R]X[P,N]12 - may be used to form GFX slot or DDI + * 21 P_GFX_[T,R]X[P,N]13 - may be used to form GFX slot or DDI + * 22 P_GFX_[T,R]X[P,N]14 - may be used to form GFX slot or DDI + * 23 P_GFX_[T,R]X[P,N]15 - may be used to form GFX slot or DDI + * 24 DP0_TX[P,N]0 - rest is just for DDI (graphics outputs) + * 25 DP0_TX[P,N]1 + * 26 DP0_TX[P,N]2 + * 27 DP0_TX[P,N]3 + * 28 DP1_TX[P,N]0 + * 29 DP1_TX[P,N]1 + * 30 DP1_TX[P,N]2 + * 31 DP1_TX[P,N]3 + * 32 DP2_TX[P,N]0 + * 33 DP2_TX[P,N]1 + * 34 DP2_TX[P,N]2 + * 35 DP2_TX[P,N]3 + * 36 DP2_TX[P,N]4 + * 37 DP2_TX[P,N]5 + * 38 DP2_TX[P,N]6 + */ + +static const PCIe_PORT_DESCRIPTOR PortList[] = { + /* PCIe port, Lanes 8:23, PCI Device Number 2, blue x16 slot */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 23), + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 1) + }, + /* PCIe port, Lanes 4:7, PCI Device Number 4, black x16 slot (in fact x4) */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7), + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 1) + }, + /* PCIe port, Lanes 0:3, UMI link to SB, PCI Device Number 8 */ + { + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3), + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0) + }, +}; + +/* + * It is not known, if the setup is complete. + * + * Tested and works: VGA/DVI + * Untested: HDMI + */ +static const PCIe_DDI_DESCRIPTOR DdiList[] = { + // DP0 to HDMI0/DP + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 24, 27), + PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux1, Hdp1) + }, + // DP1 to FCH + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 28, 31), + PCIE_DDI_DATA_INITIALIZER(ConnectorTypeNutmegDpToVga, Aux2, Hdp2) + }, + // DP2 to HDMI1/DP + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 32, 35), + PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux3, Hdp3) + }, +}; + +static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { + .Flags = DESCRIPTOR_TERMINATE_LIST, + .SocketId = 0, + .PciePortList = PortList, + .DdiLinkList = DdiList, +}; + +void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) +{ + FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface; + FchReset->Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchReset->Xhci1Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); +} + +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) +{ + InitEarly->GnbConfig.PcieComplexList = &PcieComplex; + InitEarly->GnbConfig.PsppPolicy = 0; +} + +/*---------------------------------------------------------------------------------------- + * CUSTOMER OVERIDES MEMORY TABLE + *---------------------------------------------------------------------------------------- + */ + +/* + * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA + * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable + * is populated, AGESA will base its settings on the data from the table. Otherwise, it will + * use its default conservative settings. + */ + +static CONST PSO_ENTRY ROMDATA MemoryTable_XM_E[] = { + + NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1), + NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2), + + PSO_END +}; + +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + if (IS_ENABLED(CONFIG_BOARD_ASUS_A88XM_E)) + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *) MemoryTable_XM_E; +} + +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) +{ + /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ + InitMid->GnbMidConfiguration.iGpuVgaMode = 0; +} diff --git a/src/mainboard/asus/a88xm-e/OptionsIds.h b/src/mainboard/asus/a88xm-e/OptionsIds.h new file mode 100644 index 0000000..b45f5a8 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/OptionsIds.h @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/** + * @file + * + * IDS Option File + * + * This file is used to switch on/off IDS features. + * + */ +#ifndef _OPTION_IDS_H_ +#define _OPTION_IDS_H_ + +/** + * + * This file generates the defaults tables for the Integrated Debug Support + * Module. The documented build options are imported from a user controlled + * file for processing. The build options for the Integrated Debug Support + * Module are listed below: + * + * IDSOPT_IDS_ENABLED + * IDSOPT_ERROR_TRAP_ENABLED + * IDSOPT_CONTROL_ENABLED + * IDSOPT_TRACING_ENABLED + * IDSOPT_PERF_ANALYSIS + * IDSOPT_ASSERT_ENABLED + * IDS_DEBUG_PORT + * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED + * + **/ + +//#define IDSOPT_IDS_ENABLED TRUE +//#define IDSOPT_CONTROL_ENABLED TRUE +#define IDSOPT_TRACING_ENABLED TRUE +#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE +//#define IDSOPT_PERF_ANALYSIS TRUE +#define IDSOPT_ASSERT_ENABLED TRUE +//#undef IDSOPT_DEBUG_ENABLED +//#define IDSOPT_DEBUG_ENABLED FALSE +//#undef IDSOPT_HOST_SIMNOW +//#define IDSOPT_HOST_SIMNOW FALSE +//#undef IDSOPT_HOST_HDT +//#define IDSOPT_HOST_HDT FALSE +//#define IDS_DEBUG_PORT 0x80 + +#endif diff --git a/src/mainboard/asus/a88xm-e/acpi/cpstate.asl b/src/mainboard/asus/a88xm-e/acpi/cpstate.asl new file mode 100644 index 0000000..69de2d8 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/acpi/cpstate.asl @@ -0,0 +1,112 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* This file defines the processor and performance state capability + * for each core in the system. It is included into the DSDT for each + * core. It assumes that each core of the system has the same performance + * characteristics. +*/ +/* +#include <arch/acpi.h> +DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001) + { + Scope (\_PR) { + Processor(CPU0,0,0x808,0x06) { + #include "cpstate.asl" + } + Processor(CPU1,1,0x0,0x0) { + #include "cpstate.asl" + } + Processor(CPU2,2,0x0,0x0) { + #include "cpstate.asl" + } + Processor(CPU3,3,0x0,0x0) { + #include "cpstate.asl" + } + } +*/ + /* P-state support: The maximum number of P-states supported by the */ + /* CPUs we'll use is 6. */ + /* Get from AMI BIOS. */ + Name(_PSS, Package(){ + Package() + { + 0x00000D48, + 0x00011170, + 0x00000004, + 0x00000004, + 0x00000000, + 0x00000000 + }, + + Package() + { + 0x00000AF0, + 0x0000C544, + 0x00000004, + 0x00000004, + 0x00000001, + 0x00000001 + }, + + Package() + { + 0x000009C4, + 0x0000B3B0, + 0x00000004, + 0x00000004, + 0x00000002, + 0x00000002 + }, + + Package() + { + 0x00000898, + 0x0000ABE0, + 0x00000004, + 0x00000004, + 0x00000003, + 0x00000003 + }, + + Package() + { + 0x00000708, + 0x0000A410, + 0x00000004, + 0x00000004, + 0x00000004, + 0x00000004 + }, + + Package() + { + 0x00000578, + 0x00006F54, + 0x00000004, + 0x00000004, + 0x00000005, + 0x00000005 + } + }) + + Name(_PCT, Package(){ + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} + }) + + Method(_PPC, 0){ + Return(0) + } diff --git a/src/mainboard/asus/a88xm-e/acpi/gpe.asl b/src/mainboard/asus/a88xm-e/acpi/gpe.asl new file mode 100644 index 0000000..297db37 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/acpi/gpe.asl @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope(\_GPE) { /* Start Scope GPE */ + + /* General event 3 */ + Method(_L03) { + /* DBGO("\\_GPE\\_L00\n") */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Legacy PM event */ + Method(_L08) { + /* DBGO("\\_GPE\\_L08\n") */ + } + + /* Temp warning (TWarn) event */ + Method(_L09) { + /* DBGO("\\_GPE\\_L09\n") */ + /* Notify (\_TZ.TZ00, 0x80) */ + } + + /* USB controller PME# */ + Method(_L0B) { + /* DBGO("\\_GPE\\_L0B\n") */ + Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* ExtEvent0 SCI event */ + Method(_L10) { + /* DBGO("\\_GPE\\_L10\n") */ + } + + + /* ExtEvent1 SCI event */ + Method(_L11) { + /* DBGO("\\_GPE\\_L11\n") */ + } + + /* GPIO0 or GEvent8 event */ + Method(_L18) { + /* DBGO("\\_GPE\\_L18\n") */ + Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Azalia SCI event */ + Method(_L1B) { + /* DBGO("\\_GPE\\_L1B\n") */ + Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } +} /* End Scope GPE */ diff --git a/src/mainboard/asus/a88xm-e/acpi/mainboard.asl b/src/mainboard/asus/a88xm-e/acpi/mainboard.asl new file mode 100644 index 0000000..8398c88 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/acpi/mainboard.asl @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + /* Data to be patched by the BIOS during POST */ + /* FIXME the patching is not done yet! */ + /* Memory related values */ + Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ + Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ + Name(PBLN, 0x0) /* Length of BIOS area */ + + Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ + Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */ + Name(HPBA, 0xFED00000) /* Base address of HPET table */ + + /* Some global data */ + Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ + Name(OSV, Ones) /* Assume nothing */ + Name(PMOD, One) /* Assume APIC */ diff --git a/src/mainboard/asus/a88xm-e/acpi/routing.asl b/src/mainboard/asus/a88xm-e/acpi/routing.asl new file mode 100644 index 0000000..0af6b42 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/acpi/routing.asl @@ -0,0 +1,258 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + /* Routing is in System Bus scope */ + Name(PR0, Package(){ + /* NB devices */ + /* Bus 0, Dev 0 - F15 Host Controller */ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ + Package(){0x0001FFFF, 0, INTB, 0 }, + Package(){0x0001FFFF, 1, INTC, 0 }, + + /* Bus 0, Dev 2 - PCIe Bridge for x16 slot */ + Package(){0x0002FFFF, 0, INTC, 0 }, + Package(){0x0002FFFF, 1, INTD, 0 }, + Package(){0x0002FFFF, 2, INTA, 0 }, + Package(){0x0002FFFF, 3, INTB, 0 }, + + /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ + + /* Bus 0, Dev 4 - PCIe Bridge for 4x slot */ + Package(){0x0004FFFF, 0, INTA, 0 }, + Package(){0x0004FFFF, 1, INTB, 0 }, + Package(){0x0004FFFF, 2, INTC, 0 }, + Package(){0x0004FFFF, 3, INTD, 0 }, + + /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ + /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ + /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ + /* Bus 0, Dev 8 - Southbridge port (normally hidden) */ + + /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */ + Package(){0x0014FFFF, 0, INTA, 0 }, + Package(){0x0014FFFF, 1, INTB, 0 }, + Package(){0x0014FFFF, 2, INTC, 0 }, + Package(){0x0014FFFF, 3, INTD, 0 }, + + /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0 + * EHCI @ func 2 */ + Package(){0x0012FFFF, 0, INTC, 0 }, + Package(){0x0012FFFF, 1, INTB, 0 }, + + Package(){0x0013FFFF, 0, INTC, 0 }, + Package(){0x0013FFFF, 1, INTB, 0 }, + + Package(){0x0016FFFF, 0, INTC, 0 }, + Package(){0x0016FFFF, 1, INTB, 0 }, + + /* SB devices */ + /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */ + Package(){0x0010FFFF, 0, INTC, 0 }, + Package(){0x0010FFFF, 1, INTB, 0 }, + + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, INTD, 0 }, + + /* Bus 0, Dev 21 Pcie Bridge */ + Package(){0x0015FFFF, 0, INTA, 0 }, + Package(){0x0015FFFF, 1, INTB, 0 }, + Package(){0x0015FFFF, 2, INTC, 0 }, + Package(){0x0015FFFF, 3, INTD, 0 }, + }) + + Name(APR0, Package(){ + /* NB devices in APIC mode */ + /* Bus 0, Dev 0 - F15 Host Controller */ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ + Package(){0x0001FFFF, 0, 0, 17 }, + Package(){0x0001FFFF, 1, 0, 18 }, + + /* Bus 0, Dev 2 - PCIe Bridge for x16 PCIe Slot */ + Package(){0x0002FFFF, 0, 0, 18 }, + Package(){0x0002FFFF, 1, 0, 19 }, + Package(){0x0002FFFF, 2, 0, 16 }, + Package(){0x0002FFFF, 3, 0, 17 }, + + /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ + + /* Bus 0, Dev 4 - PCIe Bridge for x4 PCIe Slot black */ + Package(){0x0004FFFF, 0, 0, 16 }, + Package(){0x0004FFFF, 1, 0, 17 }, + Package(){0x0004FFFF, 2, 0, 18 }, + Package(){0x0004FFFF, 3, 0, 19 }, + + /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ + /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ + /* Bus 0, Dev 7 - PCIe Bridge for network card */ + /* Bus 0, Dev 8 - Southbridge port (normally hidden) */ + + /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ + Package(){0x0014FFFF, 0, 0, 16 }, + Package(){0x0014FFFF, 1, 0, 17 }, + Package(){0x0014FFFF, 2, 0, 18 }, + Package(){0x0014FFFF, 3, 0, 19 }, + + /* SB devices in APIC mode */ + /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0 + * EHCI @ func 2 */ + Package(){0x0012FFFF, 0, 0, 18 }, + Package(){0x0012FFFF, 1, 0, 17 }, + + Package(){0x0013FFFF, 0, 0, 18 }, + Package(){0x0013FFFF, 1, 0, 17 }, + + Package(){0x0016FFFF, 0, 0, 18 }, + Package(){0x0016FFFF, 1, 0, 17 }, + + /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */ + Package(){0x0010FFFF, 0, 0, 0x12}, + Package(){0x0010FFFF, 1, 0, 0x11}, + + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, 0, 19 }, + + /* Bus 0, Dev 21 PCIE Bridge */ + Package(){0x0015FFFF, 0, 0, 17 }, + Package(){0x0015FFFF, 1, 0, 18 }, + Package(){0x0015FFFF, 2, 0, 19 }, + Package(){0x0015FFFF, 3, 0, 16 }, + }) + + Name(PS2, Package(){ + /* The external GFX - Hooked to PCIe slot 2 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + Name(APS2, Package(){ + /* The external GFX - Hooked to PCIe slot 2 */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + /* black slot */ + Name(PS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + }) + Name(APS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, + }) + + Name(PS5, Package(){ + /* PCIe slot - Hooked to PCIe slot 5 */ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, + }) + Name(APS5, Package(){ + /* PCIe slot - Hooked to PCIe slot 5 */ + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, + }) + + Name(PS6, Package(){ + /* PCIe slot - Hooked to PCIe slot 6 */ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + Name(APS6, Package(){ + /* PCIe slot - Hooked to PCIe slot 6 */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PS7, Package(){ + /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + + Name(APS7, Package(){ + /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ + Package(){0x0000FFFF, 0, 0, 19 }, + Package(){0x0000FFFF, 1, 0, 16 }, + Package(){0x0000FFFF, 2, 0, 17 }, + Package(){0x0000FFFF, 3, 0, 18 }, + }) + + Name(PBR0, Package(){ + /* PCIx1 on SB */ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + }) + Name(ABR0, Package(){ + /* PCIx1 on SB */ + Package(){0x0000FFFF, 0, 0, 0x10 }, + Package(){0x0000FFFF, 1, 0, 0x11 }, + Package(){0x0000FFFF, 2, 0, 0x12 }, + Package(){0x0000FFFF, 3, 0, 0x13 }, + }) + + Name(PBR1, Package(){ + /* Onboard network */ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, + }) + Name(ABR1, Package(){ + /* Onboard network */ + Package(){0x0000FFFF, 0, 0, 0x11 }, + Package(){0x0000FFFF, 1, 0, 0x12 }, + Package(){0x0000FFFF, 2, 0, 0x13 }, + Package(){0x0000FFFF, 3, 0, 0x10 }, + }) + + /* SB PCI Bridge */ + Name(PCIB, Package(){ + /* PCI slots: slot 0 behind Dev14, Fun4. */ + Package(){0x0005FFFF, 0, 0, 0x14 }, + Package(){0x0005FFFF, 1, 0, 0x15 }, + Package(){0x0005FFFF, 2, 0, 0x16 }, + Package(){0x0005FFFF, 3, 0, 0x17 }, + }) diff --git a/src/mainboard/asus/a88xm-e/acpi/sata.asl b/src/mainboard/asus/a88xm-e/acpi/sata.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/acpi/sata.asl diff --git a/src/mainboard/asus/a88xm-e/acpi/si.asl b/src/mainboard/asus/a88xm-e/acpi/si.asl new file mode 100644 index 0000000..ff0c3cf --- /dev/null +++ b/src/mainboard/asus/a88xm-e/acpi/si.asl @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + Scope(\_SI) { + Method(_SST, 1) { + /* DBGO("\\_SI\\_SST\n") */ + /* DBGO(" New Indicator state: ") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + } + } /* End Scope SI */ diff --git a/src/mainboard/asus/a88xm-e/acpi/sleep.asl b/src/mainboard/asus/a88xm-e/acpi/sleep.asl new file mode 100644 index 0000000..08b7de4 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/acpi/sleep.asl @@ -0,0 +1,96 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Wake status package */ +Name(WKST,Package(){Zero, Zero}) + +/* +* \_PTS - Prepare to Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2, etc +* +* Exit: +* -none- +* +* The _PTS control method is executed at the beginning of the sleep process +* for S1-S5. The sleeping value is passed to the _PTS control method. This +* control method may be executed a relatively long time before entering the +* sleep state and the OS may abort the operation without notification to +* the ACPI driver. This method cannot modify the configuration or power +* state of any device in the system. +*/ +Method(\_PTS, 1) { + /* DBGO("\\_PTS\n") */ + /* DBGO("From S0 to S") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + + /* Clear sleep SMI status flag and enable sleep SMI trap. */ + /*Store(One, CSSM) + Store(One, SSEN)*/ + + /* On older chips, clear PciExpWakeDisEn */ + /*if (LLessEqual(\_SB.SBRI, 0x13)) { + * Store(0,\_SB.PWDE) + *} + */ + + /* Clear wake status structure. */ + Store(0, Index(WKST,0)) + Store(0, Index(WKST,1)) + + Store (0x07, UPWS) +} /* End Method(\_PTS) */ + +/* +* \_BFS OEM Back From Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* -none- +*/ +Method(\_BFS, 1) { + /* DBGO("\\_BFS\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ +} + +/* +* \_WAK System Wake method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* Return package of 2 DWords +* Dword 1 - Status +* 0x00000000 wake succeeded +* 0x00000001 Wake was signaled but failed due to lack of power +* 0x00000002 Wake was signaled but failed due to thermal condition +* Dword 2 - Power Supply state +* if non-zero the effective S-state the power supply entered +*/ +Method(\_WAK, 1) { + /* DBGO("\\_WAK\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + + Return(WKST) +} /* End Method(\_WAK) */ diff --git a/src/mainboard/asus/a88xm-e/acpi/superio.asl b/src/mainboard/asus/a88xm-e/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/acpi/superio.asl diff --git a/src/mainboard/asus/a88xm-e/acpi/thermal.asl b/src/mainboard/asus/a88xm-e/acpi/thermal.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/acpi/thermal.asl diff --git a/src/mainboard/asus/a88xm-e/acpi/usb_oc.asl b/src/mainboard/asus/a88xm-e/acpi/usb_oc.asl new file mode 100644 index 0000000..f5d6980 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/acpi/usb_oc.asl @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* USB overcurrent mapping pins. */ +Name(UOM0, 0) +Name(UOM1, 2) +Name(UOM2, 0) +Name(UOM3, 7) +Name(UOM4, 2) +Name(UOM5, 2) +Name(UOM6, 6) +Name(UOM7, 2) +Name(UOM8, 6) +Name(UOM9, 6) diff --git a/src/mainboard/asus/a88xm-e/acpi_tables.c b/src/mainboard/asus/a88xm-e/acpi_tables.c new file mode 100644 index 0000000..f94fde0 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/acpi_tables.c @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <arch/ioapic.h> +#include <device/pci.h> +#include <string.h> + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + /* Write Hudson IOAPIC, only one */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, + IO_APIC_ADDR, 0); + + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, 0xF); + /* 0: mean bus 0--->ISA */ + /* 0: PIC 0 */ + /* 2: APIC 2 */ + /* 5 mean: 0101 --> Edge-triggered, Active high */ + + /* create all subtables for processors */ + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1); + /* 1: LINT1 connect to NMI */ + + return current; +} diff --git a/src/mainboard/asus/a88xm-e/board_info.txt b/src/mainboard/asus/a88xm-e/board_info.txt new file mode 100644 index 0000000..bc090ff --- /dev/null +++ b/src/mainboard/asus/a88xm-e/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asus.com/Motherboards/A88XME/ +ROM package: DIP8 +ROM protocol: [http://www.winbond.com/hq/product/code-storage-flash-memory/serial-nor-fl... SPI] +ROM socketed: y +Flashrom support: y (without AmdSpiRomProtect modules) +Release year: 2014 diff --git a/src/mainboard/asus/a88xm-e/buildOpts.c b/src/mainboard/asus/a88xm-e/buildOpts.c new file mode 100644 index 0000000..c324532 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/buildOpts.c @@ -0,0 +1,346 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/** + * @file + * + * AMD User options selection for a Brazos platform solution system + * + * This file is placed in the user's platform directory and contains the + * build option selections desired for that platform. + * + * For Information about this file, see @ref platforminstall. + * + */ + +#include <stdlib.h> + +#include <vendorcode/amd/agesa/f15tn/AGESA.h> + +/* Include the files that instantiate the configuration definitions. */ +#include <vendorcode/amd/agesa/f15tn/Include/AdvancedApi.h> +#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h> +#include <vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.h> +#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h> +/* the next two headers depend on heapManager.h */ +#include <vendorcode/amd/agesa/f15tn/Proc/Common/CreateStruct.h> +#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEarlyInit.h> +/* These tables are optional and may be used to adjust memory timing settings */ +#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mm.h> +#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h> + + +/* Select the CPU family. */ +#define INSTALL_FAMILY_10_SUPPORT FALSE +#define INSTALL_FAMILY_12_SUPPORT FALSE +#define INSTALL_FAMILY_14_SUPPORT FALSE +#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE + +/* Select the CPU socket type. */ +#define INSTALL_G34_SOCKET_SUPPORT FALSE +#define INSTALL_C32_SOCKET_SUPPORT FALSE +#define INSTALL_S1G3_SOCKET_SUPPORT FALSE +#define INSTALL_S1G4_SOCKET_SUPPORT FALSE +#define INSTALL_ASB2_SOCKET_SUPPORT FALSE +#define INSTALL_FS1_SOCKET_SUPPORT FALSE +#define INSTALL_FM1_SOCKET_SUPPORT FALSE +#define INSTALL_FP2_SOCKET_SUPPORT FALSE +#define INSTALL_FT1_SOCKET_SUPPORT FALSE +#define INSTALL_AM3_SOCKET_SUPPORT FALSE + +#define INSTALL_FM2_SOCKET_SUPPORT TRUE + +//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_SODIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_ECC_SUPPORT TRUE +//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE +//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE +#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE +#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE +#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE +//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE +#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE +//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE +#define BLDOPT_REMOVE_SRAT FALSE //TRUE +#define BLDOPT_REMOVE_SLIT FALSE //TRUE +#define BLDOPT_REMOVE_WHEA FALSE //TRUE +#define BLDOPT_REMOVE_CRAT TRUE +#define BLDOPT_REMOVE_DMI TRUE +//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE + +//This element selects whether P-States should be forced to be independent, +// as reported by the ACPI _PSD object. For single-link processors, +// setting TRUE for OS to support this feature. + +//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE + +#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS +#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER +/* Build configuration values here. + */ +#define BLDCFG_VRM_CURRENT_LIMIT 90000 +#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0 +#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 0 +#define BLDCFG_PLAT_NUM_IO_APICS 3 +#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST +#define BLDCFG_MEM_INIT_PSTATE 0 + +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE + +#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY +#define BLDCFG_MEMORY_MODE_UNGANGED TRUE +#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE +#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE +#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE +#define BLDCFG_MEMORY_POWER_DOWN TRUE +#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT +#define BLDCFG_ONLINE_SPARE FALSE +#define BLDCFG_BANK_SWIZZLE TRUE +#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO +#define BLDCFG_MEMORY_CLOCK_SELECT DDR1600_FREQUENCY +#define BLDCFG_DQS_TRAINING_CONTROL TRUE +#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE +#define BLDCFG_USE_BURST_MODE FALSE +#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE +#define BLDCFG_ENABLE_ECC_FEATURE FALSE +#define BLDCFG_ECC_REDIRECTION FALSE +#define BLDCFG_SCRUB_DRAM_RATE 0 +#define BLDCFG_SCRUB_L2_RATE 0 +#define BLDCFG_SCRUB_L3_RATE 0 +#define BLDCFG_SCRUB_IC_RATE 0 +#define BLDCFG_SCRUB_DC_RATE 0 +#define BLDCFG_ECC_SYMBOL_SIZE 4 +#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 +#define BLDCFG_ECC_SYNC_FLOOD FALSE +#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE +#define BLDCFG_1GB_ALIGN FALSE +#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE +#define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 // PCIE Spread Spectrum default value 0.36% +#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 + +#define BLDOPT_REMOVE_ALIB FALSE +#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto +#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P' +#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' +#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 + +#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 200 +#define BLDCFG_CFG_ABM_SUPPORT 0 + +//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770 + +// Specify the default values for the VRM controlling the VDDNB plane. +// If not specified, the values used for the core VRM will be applied +//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 // Not currently used on Trinity +//#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L +//#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in calculating the VSRampSlamTime +//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 // Not currently used on Trinity +//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE 0 // Not currently used on Trinity +//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 // Not currently used on Trinity + +#define BLDCFG_VRM_NB_CURRENT_LIMIT 60000 + +#define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3 +#define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3 + +#if IS_ENABLED(CONFIG_GFXUMA) +#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED +#define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED +//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/ +#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M +#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE +#endif + +#define BLDCFG_IOMMU_SUPPORT TRUE + +#define BLDCFG_CFG_GNB_HD_AUDIO TRUE +//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID +//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID +//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID + +/* Process the options... + * This file include MUST occur AFTER the user option selection settings + */ +/* + * Customized OEM build configurations for FCH component + */ +// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00 +// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20 +// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00 +// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400 +// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404 +// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408 +// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410 +// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420 +// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000 +// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000 +// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000 +// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0 +// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00 +// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000 +// #define BLDCFG_AZALIA_SSID 0x780D1022 +// #define BLDCFG_SMBUS_SSID 0x780B1022 +// #define BLDCFG_IDE_SSID 0x780C1022 +// #define BLDCFG_SATA_AHCI_SSID 0x78011022 +// #define BLDCFG_SATA_IDE_SSID 0x78001022 +// #define BLDCFG_SATA_RAID5_SSID 0x78031022 +// #define BLDCFG_SATA_RAID_SSID 0x78021022 +// #define BLDCFG_EHCI_SSID 0x78081022 +// #define BLDCFG_OHCI_SSID 0x78071022 +// #define BLDCFG_LPC_SSID 0x780E1022 +// #define BLDCFG_SD_SSID 0x78061022 +// #define BLDCFG_XHCI_SSID 0x78121022 +// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE +// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE +// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4 +// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE +// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE +// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE +// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE +// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE +// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE +// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE +// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE + +CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = +{ + { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E }, + { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E }, + { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 }, + { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 }, + { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 }, + { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 }, + { CPU_LIST_TERMINAL } +}; + +#define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList + + // This is the delivery package title, "BrazosPI" + // This string MUST be exactly 8 characters long +#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} + + // This is the release version number of the AGESA component + // This string MUST be exactly 12 characters long +#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} + +/* MEMORY_BUS_SPEED */ +#define DDR400_FREQUENCY 200 ///< DDR 400 +#define DDR533_FREQUENCY 266 ///< DDR 533 +#define DDR667_FREQUENCY 333 ///< DDR 667 +#define DDR800_FREQUENCY 400 ///< DDR 800 +#define DDR1066_FREQUENCY 533 ///< DDR 1066 +#define DDR1333_FREQUENCY 667 ///< DDR 1333 +#define DDR1600_FREQUENCY 800 ///< DDR 1600 +#define DDR1866_FREQUENCY 933 ///< DDR 1866 +#define DDR2100_FREQUENCY 1050 ///< DDR 2100 +#define DDR2133_FREQUENCY 1066 ///< DDR 2133 +#define DDR2400_FREQUENCY 1200 ///< DDR 2400 +#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency + +/* QUANDRANK_TYPE*/ +#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM +#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM + +/* USER_MEMORY_TIMING_MODE */ +#define TIMING_MODE_AUTO 0 ///< Use best rate possible +#define TIMING_MODE_LIMITED 1 ///< Set user top limit +#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed + +/* POWER_DOWN_MODE */ +#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode +#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode + +/* + * Agesa optional capabilities selection. + * Uncomment and mark FALSE those features you wish to include in the build. + * Comment out or mark TRUE those features you want to REMOVE from the build. + */ + +#define DFLT_SMBUS0_BASE_ADDRESS 0xB00 +#define DFLT_SMBUS1_BASE_ADDRESS 0xB20 +/* The AGESA likes to enable 512 bytes region on this base for LPC bus */ +#define DFLT_SIO_PME_BASE_ADDRESS 0xE00 +#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800 +#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804 +#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808 +#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810 +#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820 +#define DFLT_SPI_BASE_ADDRESS 0xFEC10000 +#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 +#define DFLT_HPET_BASE_ADDRESS 0xFED00000 +#define DFLT_SMI_CMD_PORT 0xB0 +#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 +#define DFLT_GEC_BASE_ADDRESS 0xFED61000 +#define DFLT_AZALIA_SSID 0x780D1022 +#define DFLT_SMBUS_SSID 0x780B1022 +#define DFLT_IDE_SSID 0x780C1022 +#define DFLT_SATA_AHCI_SSID 0x78011022 +#define DFLT_SATA_IDE_SSID 0x78001022 +#define DFLT_SATA_RAID5_SSID 0x78031022 +#define DFLT_SATA_RAID_SSID 0x78021022 +#define DFLT_EHCI_SSID 0x78081022 +#define DFLT_OHCI_SSID 0x78071022 +#define DFLT_LPC_SSID 0x780E1022 +#define DFLT_SD_SSID 0x78061022 +#define DFLT_XHCI_SSID 0x78121022 +#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE +#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE +#define DFLT_FCH_GPP_LINK_CONFIG PortA1B1C1D1 +#define DFLT_FCH_GPP_PORT0_PRESENT TRUE +#define DFLT_FCH_GPP_PORT1_PRESENT TRUE +#define DFLT_FCH_GPP_PORT2_PRESENT FALSE +#define DFLT_FCH_GPP_PORT3_PRESENT FALSE +#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE +//#define BLDCFG_IR_PIN_CONTROL 0x33 +//#define FCH_NO_XHCI_SUPPORT FALSE +GPIO_CONTROL a88xm_e_gpio[] = { +// {183, Function1, PullUpB}, + {-1} +}; +#define BLDCFG_FCH_GPIO_CONTROL_LIST (&a88xm_e_gpio[0]) + +// The following definitions specify the default values for various parameters in which there are +// no clearly defined defaults to be used in the common file. The values below are based on product +// and BKDG content, please consult the AGESA Memory team for consultation. +#define DFLT_SCRUB_DRAM_RATE (0) +#define DFLT_SCRUB_L2_RATE (0) +#define DFLT_SCRUB_L3_RATE (0) +#define DFLT_SCRUB_IC_RATE (0) +#define DFLT_SCRUB_DC_RATE (0) +#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define DFLT_VRM_SLEW_RATE (5000) + +/* Moving this include up will break AGESA. */ +#include <PlatformInstall.h> diff --git a/src/mainboard/asus/a88xm-e/cmos.layout b/src/mainboard/asus/a88xm-e/cmos.layout new file mode 100644 index 0000000..e1dbd9a --- /dev/null +++ b/src/mainboard/asus/a88xm-e/cmos.layout @@ -0,0 +1,66 @@ +#***************************************************************************** +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +#***************************************************************************** + +entries + +0 384 r 0 reserved_memory +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#392 3 r 0 unused +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +456 1 e 1 ECC_memory +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 diff --git a/src/mainboard/asus/a88xm-e/devicetree_a88xm-e.cb b/src/mainboard/asus/a88xm-e/devicetree_a88xm-e.cb new file mode 100644 index 0000000..e2b0eea --- /dev/null +++ b/src/mainboard/asus/a88xm-e/devicetree_a88xm-e.cb @@ -0,0 +1,143 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +chip northbridge/amd/agesa/family15tn/root_complex + + device cpu_cluster 0 on + chip cpu/amd/agesa/family15tn + device lapic 10 on end + end + end + + device domain 0 on + subsystemid 0x1022 0x1410 inherit + chip northbridge/amd/agesa/family15tn # CPU side of HT root complex + + chip northbridge/amd/agesa/family15tn # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 0.2 on end # IOMMU + device pci 1.0 on end # Internal Graphics + device pci 1.1 on end # Internal Audio (iGPU) + device pci 2.0 on end # PCIE x4/x16 yellow (?) + device pci 3.0 on end # unused? + device pci 4.0 on end # PCIE x4/x16 yellow (?) + device pci 5.0 off end # unused + device pci 6.0 off end # unused? + device pci 7.0 off end # LAN + device pci 8.0 off end # NB/SB Link P2P bridge + end #chip northbridge/amd/agesa/family15tn # PCI side of HT root complex + + chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus + device pci 10.0 on end # XHCI HC0 + device pci 10.1 on end # XHCI HC1 + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SMBUS + chip drivers/generic/generic #dimm 0 + device i2c 50 on end # 7-bit SPD address + end + chip drivers/generic/generic #dimm 1 + device i2c 51 on end # 7-bit SPD address + end + end # SM + device pci 14.1 off end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/ite/it8728f + register "TMPIN1.mode" = "THERMAL_RESISTOR" + register "TMPIN2.mode" = "THERMAL_RESISTOR" + register "TMPIN3.mode" = "THERMAL_RESISTOR" + + register "FAN1.mode" = "FAN_SMART_AUTOMATIC" + register "FAN1.smart.tmpin" = "1" + register "FAN1.smart.tmp_off" = "0x80" # never + register "FAN1.smart.tmp_start" = "20" + register "FAN1.smart.tmp_full" = "70" + register "FAN1.smart.tmp_delta" = "0" + register "FAN1.smart.smoothing" = "1" + register "FAN1.smart.pwm_start" = "20" + register "FAN1.smart.slope" = "32" + + # Enable tacho reading for chassis fan. + register "FAN2.mode" = "FAN_MODE_OFF" + + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.4 on # Env Controller + io 0x60 = 0x290 + io 0x62 = 0x220 + irq 0x70 = 0 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 off # Mouse + irq 0x70 = 12 + end + device pnp 2e.7 on # GPIO + io 0x60 = 0x228 #SMI + io 0x62 = 0x300 #Simple I/O + io 0x64 = 0x238 #Phony resource IT8603E does not have it + irq 0x70 = 0 + end + device pnp 2e.a off end # CIR + end #superio/ite/it8728f + end # + device pci 14.3 off end # LPC + device pci 14.4 on end # PCI 0x4384 + device pci 14.5 off end # USB 2 + device pci 14.6 off end # Gec + device pci 14.7 off end # SD + device pci 15.0 on end # PCIe 0 - onboard PCIe 1x + device pci 15.1 off end # unused + device pci 15.2 on end # PCI bridge + device pci 15.3 off end # unused + end #chip southbridge/amd/agesa/hudson + + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + + register "spdAddrLookup" = " + { + { {0xA0, 0x00}, {0xA2, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses + { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses + }" + + end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex + end #domain +end #chip northbridge/amd/agesa/family15tn/root_complex diff --git a/src/mainboard/asus/a88xm-e/dsdt.asl b/src/mainboard/asus/a88xm-e/dsdt.asl new file mode 100644 index 0000000..45a2606 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/dsdt.asl @@ -0,0 +1,110 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* DefinitionBlock Statement */ +#include <arch/acpi.h> +DefinitionBlock ( + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x00010001 /* OEM Revision */ + ) +{ /* Start of ASL file */ + /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ + + /* Globals for the platform */ + #include "acpi/mainboard.asl" + + /* Describe the USB Overcurrent pins */ + #include "acpi/usb_oc.asl" + + /* PCI IRQ mapping for the Southbridge */ + #include <southbridge/amd/agesa/hudson/acpi/pcie.asl> + + /* Describe the processor tree (\_PR) */ + #include <cpu/amd/agesa/family15tn/acpi/cpu.asl> + + /* Describe the supported Sleep States for this Southbridge */ + #include <southbridge/amd/common/acpi/sleepstates.asl> + + /* Describe the Sleep Methods (WAK, PTS, GTS, etc.) for this platform */ + #include "acpi/sleep.asl" + + Scope(\_SB) { + /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> + + /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ + #include "acpi/routing.asl" + + Device(PWRB) { + Name(_HID, EISAID("PNP0C0C")) + Name(_UID, 0xAA) + Name(_PRW, Package () {3, 0x04}) + Name(_STA, 0x0B) + } + + Device(PCI0) { + /* Describe the AMD Northbridge */ + #include <northbridge/amd/agesa/family15tn/acpi/northbridge.asl> + + /* Describe the AMD Fusion Controller Hub Southbridge */ + #include <southbridge/amd/agesa/hudson/acpi/fch.asl> + + /** + * TODO: The devices listed here (SBR0 and SBR1) do not appear to + * be referenced anywhere and could possibly be removed. + */ + Device(SBR0) { /* PCIe 1x SB */ + Name(_ADR, 0x00150000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(ABR0) } /* APIC mode */ + Return (PBR0) /* PIC mode */ + } + } + + Device(SBR1) { /* Onboard network */ + Name(_ADR, 0x00150001) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT, 0) { + If(PMOD){ Return(ABR1) } /* APIC mode */ + Return (PBR1) /* PIC mode */ + } + } + } + + /* Describe PCI INT[A-H] for the Southbridge */ + #include <southbridge/amd/agesa/hudson/acpi/pci_int.asl> + + } /* End Scope(_SB) */ + + /* Describe SMBUS for the Southbridge */ + #include <southbridge/amd/agesa/hudson/acpi/smbus.asl> + + /* Define the General Purpose Events for the platform */ + #include "acpi/gpe.asl" + + /* Define the Thermal zones and methods for the platform */ + #include "acpi/thermal.asl" + + /* Define the System Indicators for the platform */ + #include "acpi/si.asl" + +} +/* End of ASL file */ diff --git a/src/mainboard/asus/a88xm-e/irq_tables.c b/src/mainboard/asus/a88xm-e/irq_tables.c new file mode 100644 index 0000000..88d2160 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/irq_tables.c @@ -0,0 +1,101 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/pirq_routing.h> +#include <console/console.h> +#include <device/pci_def.h> +#include <stdint.h> +#include <string.h> + +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, + u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, + u8 slot, u8 rfu) +{ + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; +} + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + struct irq_routing_table *pirq; + struct irq_info *pirq_info; + u32 slot_num; + u8 *v; + + u8 sum = 0; + int i; + + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15; + + /* This table must be between 0xf0000 & 0x100000 */ + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); + + pirq = (void *)(addr); + v = (u8 *) (addr); + + pirq->signature = PIRQ_SIGNATURE; + pirq->version = PIRQ_VERSION; + + pirq->rtr_bus = 0; + pirq->rtr_devfn = PCI_DEVFN(0x14, 4); + + pirq->exclusive_irqs = 0; + + pirq->rtr_vendor = 0x1002; + pirq->rtr_device = 0x4384; + + pirq->miniport_data = 0; + + memset(pirq->rfu, 0, sizeof(pirq->rfu)); + + pirq_info = (void *)(&pirq->checksum + 1); + slot_num = 0; + + /* pci bridge */ + write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), + 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, + 0); + pirq_info++; + + slot_num++; + + pirq->size = 32 + 16 * slot_num; + + for (i = 0; i < pirq->size; i++) + sum += v[i]; + + sum = pirq->checksum - sum; + + if (sum != pirq->checksum) { + pirq->checksum = sum; + } + + printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + + return (unsigned long)pirq_info; +} diff --git a/src/mainboard/asus/a88xm-e/mainboard.c b/src/mainboard/asus/a88xm-e/mainboard.c new file mode 100644 index 0000000..2a0e618 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/mainboard.c @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/msr.h> +#include <device/device.h> + +/************************************************* + * enable the dedicated function in thatcher board. + *************************************************/ +static void mainboard_enable(struct device *dev) +{ + msr_t msr; + + printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + + msr = rdmsr(LS_CFG_MSR); + msr.lo &= ~(1 << 28); + wrmsr(LS_CFG_MSR, msr); + + msr = rdmsr(DC_CFG_MSR); + msr.lo &= ~(1 << 4); + msr.lo &= ~(1 << 13); + wrmsr(DC_CFG_MSR, msr); + + msr = rdmsr(BU_CFG_MSR); + msr.lo &= ~(1 << 23); + wrmsr(BU_CFG_MSR, msr); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/asus/a88xm-e/mptable.c b/src/mainboard/asus/a88xm-e/mptable.c new file mode 100644 index 0000000..d97663d --- /dev/null +++ b/src/mainboard/asus/a88xm-e/mptable.c @@ -0,0 +1,181 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <arch/ioapic.h> +#include <arch/smp/mpspec.h> +#include <cpu/x86/lapic.h> +#include <device/pci.h> +#include <stdint.h> +#include <string.h> +#include <southbridge/amd/agesa/hudson/hudson.h> + +u8 picr_data[] = { + 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + 0x09,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x1F,0x1F,0x1F,0x1F +}; +u8 intr_data[0x54] = { + 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x10,0x11,0x12,0x13 +}; + +static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length) +{ + mc->mpc_length += length; + mc->mpc_entry_count++; +} + +static void my_smp_write_bus(struct mp_config_table *mc, + unsigned char id, const char *bustype) +{ + struct mpc_config_bus *mpc; + mpc = smp_next_mpc_entry(mc); + memset(mpc, '\0', sizeof(*mpc)); + mpc->mpc_type = MP_BUS; + mpc->mpc_busid = id; + memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); + smp_add_mpc_entry(mc, sizeof(*mpc)); +} + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + int bus_isa; + u8 byte; + + /* + * By the time this function gets called, the IOAPIC registers + * have been written so they can be read to get the correct + * APIC ID and Version + */ + u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); + u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LOCAL_APIC_ADDR); + memcpy(mc->mpc_oem, "AMD ", 8); + + smp_write_processors(mc); + + //mptable_write_buses(mc, NULL, &bus_isa); + my_smp_write_bus(mc, 0, "PCI "); + my_smp_write_bus(mc, 1, "PCI "); + bus_isa = 0x02; + my_smp_write_bus(mc, bus_isa, "ISA "); + + /* I/O APICs: APIC ID Version State Address */ + smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); + + /* PIC IRQ routine */ + for (byte = 0x0; byte < sizeof(picr_data); byte ++) { + outb(byte, 0xC00); + outb(picr_data[byte], 0xC01); + } + + /* APIC IRQ routine */ + for (byte = 0x0; byte < sizeof(intr_data); byte ++) { + outb(byte | 0x80, 0xC00); + outb(intr_data[byte], 0xC01); + } + + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ +#define IO_LOCAL_INT(type, intr, apicid, pin) \ + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); + + /* PCI interrupts are level triggered, and are + * associated with a specific bus/device/function tuple. + */ +#define PCI_INT(bus, dev, int_sign, pin) \ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) + + /* IOMMU */ + PCI_INT(0x0, 0x0, 0x0, 0x10); + PCI_INT(0x0, 0x0, 0x1, 0x11); + PCI_INT(0x0, 0x0, 0x2, 0x12); + PCI_INT(0x0, 0x0, 0x3, 0x13); + + /* Internal VGA */ + PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); + PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); + + /* SMBUS */ + PCI_INT(0x0, 0x14, 0x0, 0x10); + + /* HD Audio */ + PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]); + + /* USB */ + PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); + PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); + PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); + PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); + PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); + PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); + PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]); + + /* sata */ + PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]); + PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); + + /* on board NIC & Slot PCIE. */ + + /* PCI slots */ + struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + if (dev && dev->enabled) { + u8 bus_pci = dev->link_list->secondary; + /* PCI_SLOT 0. */ + PCI_INT(bus_pci, 0x5, 0x0, 0x14); + PCI_INT(bus_pci, 0x5, 0x1, 0x15); + PCI_INT(bus_pci, 0x5, 0x2, 0x16); + PCI_INT(bus_pci, 0x5, 0x3, 0x17); + } + + /* PCIe Lan*/ + PCI_INT(0x0, 0x06, 0x0, 0x13); + + /* FCH PCIe PortA */ + PCI_INT(0x0, 0x15, 0x0, 0x10); + /* FCH PCIe PortB */ + PCI_INT(0x0, 0x15, 0x1, 0x11); + /* FCH PCIe PortC */ + PCI_INT(0x0, 0x15, 0x2, 0x12); + /* FCH PCIe PortD */ + PCI_INT(0x0, 0x15, 0x3, 0x13); + + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); + IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); + /* There is no extension information... */ + + /* Compute the checksums */ + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/asus/a88xm-e/romstage.c b/src/mainboard/asus/a88xm-e/romstage.c new file mode 100644 index 0000000..0a85c27 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/romstage.c @@ -0,0 +1,102 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2012 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> + +#include <northbridge/amd/agesa/state_machine.h> +#include <southbridge/amd/common/amd_defs.h> +#include <southbridge/amd/agesa/hudson/hudson.h> +#include <southbridge/amd/agesa/hudson/smbus.h> +#include <stdint.h> +#include <string.h> + +#include <superio/ite/common/ite.h> +#include <superio/ite/it8728f/it8728f.h> + +#define MMIO_NON_POSTED_START 0xfed00000 +#define MMIO_NON_POSTED_END 0xfedfffff +#define SB_MMIO_MISC32(x) *(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR + 0xE00 + (x)) + +static void sbxxx_enable_48mhzout(void) +{ + /* most likely programming to 48MHz out signal */ + u32 reg32; + reg32 = SB_MMIO_MISC32(0x28); + reg32 &= 0xffc7ffff; + reg32 |= 0x00100000; + SB_MMIO_MISC32(0x28) = reg32; + + reg32 = SB_MMIO_MISC32(0x40); + reg32 &= ~0x80u; + SB_MMIO_MISC32(0x40) = reg32; +} + +static void superio_init_e(void) +{ + pnp_devfn_t uart = PNP_DEV(0x2e, IT8728F_SP1); + pnp_devfn_t gpio = PNP_DEV(0x2e, IT8728F_GPIO); + + ite_kill_watchdog(gpio); + ite_enable_serial(uart, CONFIG_TTYS0_BASE); + ite_enable_3vsbsw(gpio); +} + +void board_BeforeAgesa(struct sysinfo *cb) +{ + u8 byte; + pci_devfn_t dev; + + if (IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE)) + hudson_pci_port80(); + else if (IS_ENABLED(CONFIG_POST_DEVICE_LPC)) + hudson_lpc_port80(); + + /* enable SIO LPC decode */ + dev = PCI_DEV(0, 0x14, 3); + byte = pci_read_config8(dev, 0x48); + byte |= 3; /* 2e, 2f */ + pci_write_config8(dev, 0x48, byte); + + /* enable serial decode */ + byte = pci_read_config8(dev, 0x44); + byte |= (1 << 6); /* 0x3f8 */ + pci_write_config8(dev, 0x44, byte); + + post_code(0x30); + + /* enable SB MMIO space */ + outb(0x24, 0xcd6); + outb(0x1, 0xcd7); + + /* enable SIO clock */ + sbxxx_enable_48mhzout(); + + if (IS_ENABLED(CONFIG_BOARD_ASUS_A88XM_E)) + superio_init_e(); + + /* turn on secondary smbus at b20 */ + outb(0x28, 0xcd6); + byte = inb(0xcd7); + byte |= 1; + outb(byte, 0xcd7); + + /* set DDR3 voltage */ + byte = CONFIG_BOARD_ASUS_A88XM_E_DDR3_VOLT_VAL; + + /* default is byte = 0x0, so no need to set it in this case */ + if (byte) + do_smbus_write_byte(0xb20, 0x15, 0x3, byte); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/30987 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60fa0636ba41f5f1a6a3faa2764bf2f0a968cf90 Gerrit-Change-Number: 30987 Gerrit-PatchSet: 1 Gerrit-Owner: Balázs Vinarz <vinibali1(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: lenovo/g505s: Add the discrete VGA support for AMD Lenovo G505S laptop

by mikeb mikeb (Code Review)

Hello Mike Banon, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31450 to review the following change. Change subject: lenovo/g505s: Add the discrete VGA support for AMD Lenovo G505S laptop ...................................................................... lenovo/g505s: Add the discrete VGA support for AMD Lenovo G505S laptop Make it possible to enable CONFIG_MULTIPLE_VGA_ADAPTERS option for G505S which is currently not used by any of coreboot-supported boards. Also enable the discrete graphics PCI bus leading to HD 8570M (1002,6663) or R5 M230 (1002,6665) discrete VGA and add the G505S-specific workaround for PCI resource allocation problems to AMD AGESA vendorcode. Based on the original patches by Hans Jürgen Kitter <eforname(a)freemail.hu>. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Signed-off-by: Hans Jürgen Kitter <eforname(a)freemail.hu> Change-Id: I98793fa3b1ad8ee7d0b7962a328f7d5c1b0c2f88 --- M src/device/Kconfig M src/mainboard/lenovo/g505s/devicetree.cb M src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c 3 files changed, 17 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/31450/1 diff --git a/src/device/Kconfig b/src/device/Kconfig index 33c1e5b3..5d2087e 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -247,8 +247,15 @@ Enable this option for a good compromise between security and speed. config MULTIPLE_VGA_ADAPTERS + prompt "Multiple VGA Adapters" bool + depends on BOARD_LENOVO_G505S default n + help + Some motherboards may have more than one VGA adapter - for example, + there are versions of Lenovo G505S that have a discrete VGA adapter + in addition to its' integrated VGA adapter which is a part of APU. + Enable this option to try to initialize this discrete VGA adapter. menu "Display" depends on HAVE_VGA_TEXT_FRAMEBUFFER || HAVE_LINEAR_FRAMEBUFFER diff --git a/src/mainboard/lenovo/g505s/devicetree.cb b/src/mainboard/lenovo/g505s/devicetree.cb index 99f42d6..1f33c27 100644 --- a/src/mainboard/lenovo/g505s/devicetree.cb +++ b/src/mainboard/lenovo/g505s/devicetree.cb @@ -27,7 +27,7 @@ device pci 0.2 on end # IOMMU device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX device pci 1.1 on end # Internal Multimedia - device pci 2.0 off end + device pci 2.0 on end # Discrete Graphics PCI bus 0x666X device pci 3.0 off end device pci 4.0 on end # PCIE MINI0 device pci 5.0 on end # PCIE MINI1 diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c index c566061..ee6d2c2 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c @@ -437,8 +437,15 @@ RefPtr = MemPtr->ParameterListPtr; // Memory Map/Mgt. - // Mask Bottom IO with 0xF8 to force hole size to have granularity of 128MB - RefPtr->BottomIo = 0xE0; + if ((IS_ENABLED(CONFIG_BOARD_LENOVO_G505S)) && + (IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS))) { + // Set to 0xD0 instead of 0xE0 to avoid the PCI resource allocation problems + RefPtr->BottomIo = 0xD0; + } + else { + // Mask Bottom IO with 0xF8 to force hole size to have granularity of 128MB + RefPtr->BottomIo = 0xE0; + } RefPtr->UmaMode = UserOptions.CfgUmaMode; RefPtr->UmaSize = UserOptions.CfgUmaSize; RefPtr->MemHoleRemapping = TRUE; -- To view, visit https://review.coreboot.org/c/coreboot/+/31450 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I98793fa3b1ad8ee7d0b7962a328f7d5c1b0c2f88 Gerrit-Change-Number: 31450 Gerrit-PatchSet: 1 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/lenovo/*: Add support for VBOOT on 12MiB devices

by Patrick Rudolph (Code Review)

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32617 Change subject: mb/lenovo/*: Add support for VBOOT on 12MiB devices ...................................................................... mb/lenovo/*: Add support for VBOOT on 12MiB devices Enable VBOOT support on all devices that have a 8 MiB flash, using a single RW_MAIN_A partition, allowing the use of tianocore payload in both RW_MAIN_A and WP_RO. * Add VBNV section to cmos.layout * Add FMAP for VBOOT and regular boot * Select Kconfigs for VBOOT * Enable VBOOT_SLOTS_RW_A by default Untested. Change-Id: I8a35a06ece1e9d57a2ef23970e61ae26fafce543 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/lenovo/t430/Kconfig A src/mainboard/lenovo/t430/board.fmd M src/mainboard/lenovo/t430/cmos.layout A src/mainboard/lenovo/t430/vboot-rwa.fmd M src/mainboard/lenovo/t430s/Kconfig A src/mainboard/lenovo/t430s/board.fmd M src/mainboard/lenovo/t430s/cmos.layout A src/mainboard/lenovo/t430s/vboot-rwa.fmd M src/mainboard/lenovo/t530/Kconfig A src/mainboard/lenovo/t530/board.fmd M src/mainboard/lenovo/t530/cmos.layout A src/mainboard/lenovo/t530/vboot-rwa.fmd M src/mainboard/lenovo/x131e/Kconfig A src/mainboard/lenovo/x131e/board.fmd M src/mainboard/lenovo/x131e/cmos.layout A src/mainboard/lenovo/x131e/vboot-rwa.fmd M src/mainboard/lenovo/x1_carbon_gen1/Kconfig A src/mainboard/lenovo/x1_carbon_gen1/board.fmd M src/mainboard/lenovo/x1_carbon_gen1/cmos.layout A src/mainboard/lenovo/x1_carbon_gen1/vboot-rwa.fmd M src/mainboard/lenovo/x230/Kconfig A src/mainboard/lenovo/x230/board.fmd M src/mainboard/lenovo/x230/cmos.layout A src/mainboard/lenovo/x230/vboot-rwa.fmd 24 files changed, 408 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/32617/1 diff --git a/src/mainboard/lenovo/t430/Kconfig b/src/mainboard/lenovo/t430/Kconfig index dbeaadb..fdccd66 100644 --- a/src/mainboard/lenovo/t430/Kconfig +++ b/src/mainboard/lenovo/t430/Kconfig @@ -26,6 +26,21 @@ select INTEL_GMA_HAVE_VBT select MAINBOARD_USES_IFD_GBE_REGION +config VBOOT + select VBOOT_VBNV_CMOS + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + select HAS_RECOVERY_MRC_CACHE + +config VBOOT_SLOTS_RW_AB + default y + +config VBOOT_VBNV_OFFSET + hex + default 0x2a + config MAINBOARD_DIR string default lenovo/t430 diff --git a/src/mainboard/lenovo/t430/board.fmd b/src/mainboard/lenovo/t430/board.fmd new file mode 100644 index 0000000..9180e12 --- /dev/null +++ b/src/mainboard/lenovo/t430/board.fmd @@ -0,0 +1,16 @@ +FLASH@0xff400000 0xc00000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME@0x3000 0x4ed000 + } + SI_BIOS@0x500000 0x700000 { + RW_MRC_CACHE@0 0x10000 + SMMSTORE(PRESERVE)@0x10000 0x40000 + + WP_RO@0x50000 0x6a0000 { + FMAP@0x0 0x800 + COREBOOT(CBFS)@0x1000 0x69f000 + } + } +} diff --git a/src/mainboard/lenovo/t430/cmos.layout b/src/mainboard/lenovo/t430/cmos.layout index 1b50e7f..f9757f0 100644 --- a/src/mainboard/lenovo/t430/cmos.layout +++ b/src/mainboard/lenovo/t430/cmos.layout @@ -80,6 +80,9 @@ #437 3 r 0 unused 440 8 h 0 volume +# VBOOT +448 128 r 0 vbnv + # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed 928 32 r 0 mrc_scrambler_seed_s3 diff --git a/src/mainboard/lenovo/t430/vboot-rwa.fmd b/src/mainboard/lenovo/t430/vboot-rwa.fmd new file mode 100644 index 0000000..58eb9e3 --- /dev/null +++ b/src/mainboard/lenovo/t430/vboot-rwa.fmd @@ -0,0 +1,34 @@ +FLASH@0xff400000 0xc00000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME@0x3000 0x4ed000 + } + SI_BIOS@0x500000 0x700000 { + RW_SECTION_A@0x00000 0x280000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x16ffc0 + RW_FWID_A@0x17ffc0 0x40 + } + RW_SECTION_B@0x280000 0x280000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x16ffc0 + RW_FWID_B@0x17ffc0 0x40 + } + UNIFIED_MRC_CACHE@0x500000 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_VPD(PRESERVE)@0x520000 0x1000 + SMMSTORE(PRESERVE)@0x521000 0x40000 + + WP_RO@0x581000 0x17f000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_PADDING@0x840 0x7c0 + RO_VPD(PRESERVE)@0x1000 0x1000 + GBB@0x2000 0x1e000 + COREBOOT(CBFS)@0x20000 0x15f000 + } + } +} diff --git a/src/mainboard/lenovo/t430s/Kconfig b/src/mainboard/lenovo/t430s/Kconfig index bad1837..a56f577 100644 --- a/src/mainboard/lenovo/t430s/Kconfig +++ b/src/mainboard/lenovo/t430s/Kconfig @@ -26,6 +26,21 @@ # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE +config VBOOT + select VBOOT_VBNV_CMOS + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + select HAS_RECOVERY_MRC_CACHE + +config VBOOT_SLOTS_RW_AB + default y + +config VBOOT_VBNV_OFFSET + hex + default 0x2a + config MAINBOARD_DIR string default lenovo/t430s diff --git a/src/mainboard/lenovo/t430s/board.fmd b/src/mainboard/lenovo/t430s/board.fmd new file mode 100644 index 0000000..9180e12 --- /dev/null +++ b/src/mainboard/lenovo/t430s/board.fmd @@ -0,0 +1,16 @@ +FLASH@0xff400000 0xc00000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME@0x3000 0x4ed000 + } + SI_BIOS@0x500000 0x700000 { + RW_MRC_CACHE@0 0x10000 + SMMSTORE(PRESERVE)@0x10000 0x40000 + + WP_RO@0x50000 0x6a0000 { + FMAP@0x0 0x800 + COREBOOT(CBFS)@0x1000 0x69f000 + } + } +} diff --git a/src/mainboard/lenovo/t430s/cmos.layout b/src/mainboard/lenovo/t430s/cmos.layout index 97d97ed..891a294 100644 --- a/src/mainboard/lenovo/t430s/cmos.layout +++ b/src/mainboard/lenovo/t430s/cmos.layout @@ -80,6 +80,9 @@ #436 4 r 0 unused 440 8 h 0 volume +# VBOOT +448 128 r 0 vbnv + # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed 928 32 r 0 mrc_scrambler_seed_s3 diff --git a/src/mainboard/lenovo/t430s/vboot-rwa.fmd b/src/mainboard/lenovo/t430s/vboot-rwa.fmd new file mode 100644 index 0000000..58eb9e3 --- /dev/null +++ b/src/mainboard/lenovo/t430s/vboot-rwa.fmd @@ -0,0 +1,34 @@ +FLASH@0xff400000 0xc00000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME@0x3000 0x4ed000 + } + SI_BIOS@0x500000 0x700000 { + RW_SECTION_A@0x00000 0x280000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x16ffc0 + RW_FWID_A@0x17ffc0 0x40 + } + RW_SECTION_B@0x280000 0x280000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x16ffc0 + RW_FWID_B@0x17ffc0 0x40 + } + UNIFIED_MRC_CACHE@0x500000 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_VPD(PRESERVE)@0x520000 0x1000 + SMMSTORE(PRESERVE)@0x521000 0x40000 + + WP_RO@0x581000 0x17f000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_PADDING@0x840 0x7c0 + RO_VPD(PRESERVE)@0x1000 0x1000 + GBB@0x2000 0x1e000 + COREBOOT(CBFS)@0x20000 0x15f000 + } + } +} diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index b36460d..df011e4 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -27,6 +27,21 @@ if BOARD_LENOVO_BASEBOARD_T530 +config VBOOT + select VBOOT_VBNV_CMOS + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + select HAS_RECOVERY_MRC_CACHE + +config VBOOT_SLOTS_RW_AB + default y + +config VBOOT_VBNV_OFFSET + hex + default 0x2a + config VARIANT_DIR string default "t530" if BOARD_LENOVO_T530 diff --git a/src/mainboard/lenovo/t530/board.fmd b/src/mainboard/lenovo/t530/board.fmd new file mode 100644 index 0000000..9180e12 --- /dev/null +++ b/src/mainboard/lenovo/t530/board.fmd @@ -0,0 +1,16 @@ +FLASH@0xff400000 0xc00000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME@0x3000 0x4ed000 + } + SI_BIOS@0x500000 0x700000 { + RW_MRC_CACHE@0 0x10000 + SMMSTORE(PRESERVE)@0x10000 0x40000 + + WP_RO@0x50000 0x6a0000 { + FMAP@0x0 0x800 + COREBOOT(CBFS)@0x1000 0x69f000 + } + } +} diff --git a/src/mainboard/lenovo/t530/cmos.layout b/src/mainboard/lenovo/t530/cmos.layout index 3400a4d..0c8c546 100644 --- a/src/mainboard/lenovo/t530/cmos.layout +++ b/src/mainboard/lenovo/t530/cmos.layout @@ -81,6 +81,9 @@ 440 8 h 0 volume +# VBOOT +448 128 r 0 vbnv + # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed 928 32 r 0 mrc_scrambler_seed_s3 diff --git a/src/mainboard/lenovo/t530/vboot-rwa.fmd b/src/mainboard/lenovo/t530/vboot-rwa.fmd new file mode 100644 index 0000000..58eb9e3 --- /dev/null +++ b/src/mainboard/lenovo/t530/vboot-rwa.fmd @@ -0,0 +1,34 @@ +FLASH@0xff400000 0xc00000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME@0x3000 0x4ed000 + } + SI_BIOS@0x500000 0x700000 { + RW_SECTION_A@0x00000 0x280000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x16ffc0 + RW_FWID_A@0x17ffc0 0x40 + } + RW_SECTION_B@0x280000 0x280000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x16ffc0 + RW_FWID_B@0x17ffc0 0x40 + } + UNIFIED_MRC_CACHE@0x500000 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_VPD(PRESERVE)@0x520000 0x1000 + SMMSTORE(PRESERVE)@0x521000 0x40000 + + WP_RO@0x581000 0x17f000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_PADDING@0x840 0x7c0 + RO_VPD(PRESERVE)@0x1000 0x1000 + GBB@0x2000 0x1e000 + COREBOOT(CBFS)@0x20000 0x15f000 + } + } +} diff --git a/src/mainboard/lenovo/x131e/Kconfig b/src/mainboard/lenovo/x131e/Kconfig index e7da8d0..3da7b3b 100644 --- a/src/mainboard/lenovo/x131e/Kconfig +++ b/src/mainboard/lenovo/x131e/Kconfig @@ -21,6 +21,21 @@ select SERIRQ_CONTINUOUS_MODE select INTEL_GMA_HAVE_VBT +config VBOOT + select VBOOT_VBNV_CMOS + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + select HAS_RECOVERY_MRC_CACHE + +config VBOOT_SLOTS_RW_AB + default y + +config VBOOT_VBNV_OFFSET + hex + default 0x2a + config MAINBOARD_DIR string default lenovo/x131e diff --git a/src/mainboard/lenovo/x131e/board.fmd b/src/mainboard/lenovo/x131e/board.fmd new file mode 100644 index 0000000..9180e12 --- /dev/null +++ b/src/mainboard/lenovo/x131e/board.fmd @@ -0,0 +1,16 @@ +FLASH@0xff400000 0xc00000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME@0x3000 0x4ed000 + } + SI_BIOS@0x500000 0x700000 { + RW_MRC_CACHE@0 0x10000 + SMMSTORE(PRESERVE)@0x10000 0x40000 + + WP_RO@0x50000 0x6a0000 { + FMAP@0x0 0x800 + COREBOOT(CBFS)@0x1000 0x69f000 + } + } +} diff --git a/src/mainboard/lenovo/x131e/cmos.layout b/src/mainboard/lenovo/x131e/cmos.layout index 93c74fb..41b8354 100644 --- a/src/mainboard/lenovo/x131e/cmos.layout +++ b/src/mainboard/lenovo/x131e/cmos.layout @@ -79,6 +79,9 @@ 440 8 h 0 volume +# VBOOT +448 128 r 0 vbnv + # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed 928 32 r 0 mrc_scrambler_seed_s3 diff --git a/src/mainboard/lenovo/x131e/vboot-rwa.fmd b/src/mainboard/lenovo/x131e/vboot-rwa.fmd new file mode 100644 index 0000000..58eb9e3 --- /dev/null +++ b/src/mainboard/lenovo/x131e/vboot-rwa.fmd @@ -0,0 +1,34 @@ +FLASH@0xff400000 0xc00000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME@0x3000 0x4ed000 + } + SI_BIOS@0x500000 0x700000 { + RW_SECTION_A@0x00000 0x280000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x16ffc0 + RW_FWID_A@0x17ffc0 0x40 + } + RW_SECTION_B@0x280000 0x280000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x16ffc0 + RW_FWID_B@0x17ffc0 0x40 + } + UNIFIED_MRC_CACHE@0x500000 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_VPD(PRESERVE)@0x520000 0x1000 + SMMSTORE(PRESERVE)@0x521000 0x40000 + + WP_RO@0x581000 0x17f000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_PADDING@0x840 0x7c0 + RO_VPD(PRESERVE)@0x1000 0x1000 + GBB@0x2000 0x1e000 + COREBOOT(CBFS)@0x20000 0x15f000 + } + } +} diff --git a/src/mainboard/lenovo/x1_carbon_gen1/Kconfig b/src/mainboard/lenovo/x1_carbon_gen1/Kconfig index 520853c..29060d9 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/Kconfig +++ b/src/mainboard/lenovo/x1_carbon_gen1/Kconfig @@ -26,6 +26,21 @@ # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE +config VBOOT + select VBOOT_VBNV_CMOS + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + select HAS_RECOVERY_MRC_CACHE + +config VBOOT_SLOTS_RW_AB + default y + +config VBOOT_VBNV_OFFSET + hex + default 0x2a + config MAINBOARD_DIR string default lenovo/x1_carbon_gen1 diff --git a/src/mainboard/lenovo/x1_carbon_gen1/board.fmd b/src/mainboard/lenovo/x1_carbon_gen1/board.fmd new file mode 100644 index 0000000..9180e12 --- /dev/null +++ b/src/mainboard/lenovo/x1_carbon_gen1/board.fmd @@ -0,0 +1,16 @@ +FLASH@0xff400000 0xc00000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME@0x3000 0x4ed000 + } + SI_BIOS@0x500000 0x700000 { + RW_MRC_CACHE@0 0x10000 + SMMSTORE(PRESERVE)@0x10000 0x40000 + + WP_RO@0x50000 0x6a0000 { + FMAP@0x0 0x800 + COREBOOT(CBFS)@0x1000 0x69f000 + } + } +} diff --git a/src/mainboard/lenovo/x1_carbon_gen1/cmos.layout b/src/mainboard/lenovo/x1_carbon_gen1/cmos.layout index bb25261..55a8a58 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/cmos.layout +++ b/src/mainboard/lenovo/x1_carbon_gen1/cmos.layout @@ -80,6 +80,9 @@ 440 8 h 0 volume +# VBOOT +448 128 r 0 vbnv + # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed 928 32 r 0 mrc_scrambler_seed_s3 diff --git a/src/mainboard/lenovo/x1_carbon_gen1/vboot-rwa.fmd b/src/mainboard/lenovo/x1_carbon_gen1/vboot-rwa.fmd new file mode 100644 index 0000000..58eb9e3 --- /dev/null +++ b/src/mainboard/lenovo/x1_carbon_gen1/vboot-rwa.fmd @@ -0,0 +1,34 @@ +FLASH@0xff400000 0xc00000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME@0x3000 0x4ed000 + } + SI_BIOS@0x500000 0x700000 { + RW_SECTION_A@0x00000 0x280000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x16ffc0 + RW_FWID_A@0x17ffc0 0x40 + } + RW_SECTION_B@0x280000 0x280000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x16ffc0 + RW_FWID_B@0x17ffc0 0x40 + } + UNIFIED_MRC_CACHE@0x500000 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_VPD(PRESERVE)@0x520000 0x1000 + SMMSTORE(PRESERVE)@0x521000 0x40000 + + WP_RO@0x581000 0x17f000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_PADDING@0x840 0x7c0 + RO_VPD(PRESERVE)@0x1000 0x1000 + GBB@0x2000 0x1e000 + COREBOOT(CBFS)@0x20000 0x15f000 + } + } +} diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig index 5b34b83..e7d7720 100644 --- a/src/mainboard/lenovo/x230/Kconfig +++ b/src/mainboard/lenovo/x230/Kconfig @@ -27,6 +27,21 @@ # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE +config VBOOT + select VBOOT_VBNV_CMOS + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + select HAS_RECOVERY_MRC_CACHE + +config VBOOT_SLOTS_RW_AB + default y + +config VBOOT_VBNV_OFFSET + hex + default 0x2a + config MAINBOARD_DIR string default lenovo/x230 diff --git a/src/mainboard/lenovo/x230/board.fmd b/src/mainboard/lenovo/x230/board.fmd new file mode 100644 index 0000000..9180e12 --- /dev/null +++ b/src/mainboard/lenovo/x230/board.fmd @@ -0,0 +1,16 @@ +FLASH@0xff400000 0xc00000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME@0x3000 0x4ed000 + } + SI_BIOS@0x500000 0x700000 { + RW_MRC_CACHE@0 0x10000 + SMMSTORE(PRESERVE)@0x10000 0x40000 + + WP_RO@0x50000 0x6a0000 { + FMAP@0x0 0x800 + COREBOOT(CBFS)@0x1000 0x69f000 + } + } +} diff --git a/src/mainboard/lenovo/x230/cmos.layout b/src/mainboard/lenovo/x230/cmos.layout index 27197fb..9903400 100644 --- a/src/mainboard/lenovo/x230/cmos.layout +++ b/src/mainboard/lenovo/x230/cmos.layout @@ -80,6 +80,9 @@ 440 8 h 0 volume +# VBOOT +448 128 r 0 vbnv + # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed 928 32 r 0 mrc_scrambler_seed_s3 diff --git a/src/mainboard/lenovo/x230/vboot-rwa.fmd b/src/mainboard/lenovo/x230/vboot-rwa.fmd new file mode 100644 index 0000000..58eb9e3 --- /dev/null +++ b/src/mainboard/lenovo/x230/vboot-rwa.fmd @@ -0,0 +1,34 @@ +FLASH@0xff400000 0xc00000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME@0x3000 0x4ed000 + } + SI_BIOS@0x500000 0x700000 { + RW_SECTION_A@0x00000 0x280000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x16ffc0 + RW_FWID_A@0x17ffc0 0x40 + } + RW_SECTION_B@0x280000 0x280000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x16ffc0 + RW_FWID_B@0x17ffc0 0x40 + } + UNIFIED_MRC_CACHE@0x500000 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_VPD(PRESERVE)@0x520000 0x1000 + SMMSTORE(PRESERVE)@0x521000 0x40000 + + WP_RO@0x581000 0x17f000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_PADDING@0x840 0x7c0 + RO_VPD(PRESERVE)@0x1000 0x1000 + GBB@0x2000 0x1e000 + COREBOOT(CBFS)@0x20000 0x15f000 + } + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/32617 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8a35a06ece1e9d57a2ef23970e61ae26fafce543 Gerrit-Change-Number: 32617 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 week, 3 days

8
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Change in ...coreboot[master]: [WIP]x86: Introduce the blobolator

by Patrick Rudolph (Code Review)

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32020 Change subject: [WIP]x86: Introduce the blobolator ...................................................................... [WIP]x86: Introduce the blobolator This is a PoC to run arbitrary code and blobs inside an emulated virtual machine using libx86emu, thus the name blobolator. The libx86emu has been patched to the following: * redirect IO to the host machine it's running on * trace IO * start in protected mode * add mechanism to drop IO access * add Kconfig to debug code it is running Implemented features: * Run ramstage in libx86emu * Run postcar in libx86emu TODO: * Add support to trace only blobs, not stages. * Improve translation of known IO to human readable format ** COM ** PCI ** APIC ** PIT ** POST Tested on qemu. Sucessfully run ramstage in blobolator. Change-Id: I13e47f45e69376d046f35c04363fe3db1cfaa610 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/Kconfig M src/arch/x86/boot.c M src/mainboard/emulation/qemu-i440fx/romstage.c M src/mainboard/emulation/qemu-q35/romstage.c M src/vendorcode/Makefile.inc A src/vendorcode/libx86emu/Makefile.inc A src/vendorcode/libx86emu/blobolator.c A src/vendorcode/libx86emu/decode.c A src/vendorcode/libx86emu/include/decode.h A src/vendorcode/libx86emu/include/mem.h A src/vendorcode/libx86emu/include/ops.h A src/vendorcode/libx86emu/include/prim_ops.h A src/vendorcode/libx86emu/include/x86emu.h A src/vendorcode/libx86emu/include/x86emu_int.h A src/vendorcode/libx86emu/mem.c A src/vendorcode/libx86emu/ops.c A src/vendorcode/libx86emu/ops2.c A src/vendorcode/libx86emu/prim_ops.c 18 files changed, 14,512 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/32020/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/32020 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I13e47f45e69376d046f35c04363fe3db1cfaa610 Gerrit-Change-Number: 32020 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

1 week, 4 days

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Change in ...coreboot[master]: security/lockdown: Write-protect WP_RO

by Patrick Rudolph (Code Review)

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32705 Change subject: security/lockdown: Write-protect WP_RO ...................................................................... security/lockdown: Write-protect WP_RO Add another choice to boot media protection and write-protect WP_RO in case VBOOT is enabled. Tested on Lenovo T520: The WP_RO region is write-protected. Change-Id: I72c3e1a0720514b9b85b0433944ab5fb7109b2a2 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/security/lockdown/Kconfig M src/security/lockdown/bootmedia.c 2 files changed, 29 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/32705/1 diff --git a/src/security/lockdown/Kconfig b/src/security/lockdown/Kconfig index bb4d072..1e982d8 100644 --- a/src/security/lockdown/Kconfig +++ b/src/security/lockdown/Kconfig @@ -15,6 +15,18 @@ config BOOTMEDIA_LOCK_NONE bool "Don't lock boot media sections" +config BOOTMEDIA_LOCK_VBOOT_RO + bool "Write-protect WP_RO region in boot media" + depends on VBOOT + help + Select this if you want to write-protect the WP_RO region as specified + in the VBOOT FMAP. You will only be able to write the regions + FW_MAIN_A/FW_MAIN_B, which are not write-protected using the internal + programmer. + The locking will take place during the chipset lockdown, which + is either triggered by coreboot (when INTEL_CHIPSET_LOCKDOWN is set) + or has to be triggered later (e.g. by the payload or the OS). + config BOOTMEDIA_LOCK_RO bool "Write-protect the whole boot media" help diff --git a/src/security/lockdown/bootmedia.c b/src/security/lockdown/bootmedia.c index 8fb4ae9..6fa2de2 100644 --- a/src/security/lockdown/bootmedia.c +++ b/src/security/lockdown/bootmedia.c @@ -17,6 +17,7 @@ #include <commonlib/region.h> #include <console/console.h> #include <bootstate.h> +#include <fmap.h> /* * Enable write protection on the WP_RO region of the bootmedia. @@ -47,8 +48,23 @@ "of whole bootmedia\n"); locked = true; } - } + } else if (CONFIG(BOOTMEDIA_LOCK_VBOOT_RO)) { + struct region_device dev; + if (fmap_locate_area_as_rdev("WP_RO", &dev) < 0) { + printk(BIOS_ERR, "BM-LOCKDOWN: Could not find region 'WP_RO'\n"); + } else { + for (size_t i = 0; i < ARRAY_SIZE(wp_prot); i++) { + printk(BIOS_DEBUG, "BM-LOCKDOWN: Trying write-protection" + "#%zu ...\n", i); + if (boot_device_wp_region(&dev, wp_prot[i]) < 0) + continue; + printk(BIOS_INFO, "BM-LOCKDOWN: Enabled write-protection of" + "WP_RO region\n"); + locked = true; + } + } + } if (!locked) printk(BIOS_INFO, "BM-LOCKDOWN: Didn't enable bootmedia protection\n"); } -- To view, visit https://review.coreboot.org/c/coreboot/+/32705 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72c3e1a0720514b9b85b0433944ab5fb7109b2a2 Gerrit-Change-Number: 32705 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

2 weeks, 3 days

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Change in ...coreboot[master]: src/mainboard/sony: Add Sony VPCEH2K1E

by Angel Pons (Code Review)

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30973 Change subject: src/mainboard/sony: Add Sony VPCEH2K1E ...................................................................... src/mainboard/sony: Add Sony VPCEH2K1E Run autoport. It has a Nvidia graphics card and a Nuvoton NPCE795 EC. Change-Id: Ibf324f1276611ab06d5906cab87ad538bfad7218 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- A src/mainboard/sony/vpceh2k1e/Kconfig A src/mainboard/sony/vpceh2k1e/Kconfig.name A src/mainboard/sony/vpceh2k1e/Makefile.inc A src/mainboard/sony/vpceh2k1e/acpi/ec.asl A src/mainboard/sony/vpceh2k1e/acpi/platform.asl A src/mainboard/sony/vpceh2k1e/acpi/superio.asl A src/mainboard/sony/vpceh2k1e/acpi_tables.c A src/mainboard/sony/vpceh2k1e/board_info.txt A src/mainboard/sony/vpceh2k1e/devicetree.cb A src/mainboard/sony/vpceh2k1e/dsdt.asl A src/mainboard/sony/vpceh2k1e/gpio.c A src/mainboard/sony/vpceh2k1e/hda_verb.c A src/mainboard/sony/vpceh2k1e/mainboard.c A src/mainboard/sony/vpceh2k1e/romstage.c 14 files changed, 700 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/30973/1 diff --git a/src/mainboard/sony/vpceh2k1e/Kconfig b/src/mainboard/sony/vpceh2k1e/Kconfig new file mode 100644 index 0000000..7d1f6ca --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/Kconfig @@ -0,0 +1,44 @@ +if BOARD_SONY_VPCEH2K1E + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_4096 + select CPU_INTEL_SOCKET_RPGA989 + select EC_ACPI + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_BD82X6X + select SYSTEM_TYPE_LAPTOP + select USE_NATIVE_RAMINIT + +config MAINBOARD_DIR + string + default sony_corporation/vpceh2k1e + +config MAINBOARD_PART_NUMBER + string + default "VPCEH2K1E" + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x908b + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x104d + +config DRAM_RESET_GATE_GPIO # FIXME: check this + int + default 60 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX # FIXME: check this + int + default 2 +endif diff --git a/src/mainboard/sony/vpceh2k1e/Kconfig.name b/src/mainboard/sony/vpceh2k1e/Kconfig.name new file mode 100644 index 0000000..3de2fcc --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_SONY_VPCEH2K1E + bool "VPCEH2K1E" diff --git a/src/mainboard/sony/vpceh2k1e/Makefile.inc b/src/mainboard/sony/vpceh2k1e/Makefile.inc new file mode 100644 index 0000000..3dae61e --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/Makefile.inc @@ -0,0 +1 @@ +romstage-y += gpio.c diff --git a/src/mainboard/sony/vpceh2k1e/acpi/ec.asl b/src/mainboard/sony/vpceh2k1e/acpi/ec.asl new file mode 100644 index 0000000..9988369 --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/acpi/ec.asl @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Angel Pons <th3fanbus(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device(EC) +{ + Name (_HID, EISAID("PNP0C09")) + Name (_UID, 0) + Name (_GPE, 23) +/* FIXME: EC support */ +} diff --git a/src/mainboard/sony/vpceh2k1e/acpi/platform.asl b/src/mainboard/sony/vpceh2k1e/acpi/platform.asl new file mode 100644 index 0000000..15d53d9 --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/acpi/platform.asl @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Angel Pons <th3fanbus(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_WAK,1) +{ + /* FIXME: EC support */ + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ + /* FIXME: EC support */ +} diff --git a/src/mainboard/sony/vpceh2k1e/acpi/superio.asl b/src/mainboard/sony/vpceh2k1e/acpi/superio.asl new file mode 100644 index 0000000..8bfc1a0 --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/acpi/superio.asl @@ -0,0 +1,17 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Angel Pons <th3fanbus(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/sony/vpceh2k1e/acpi_tables.c b/src/mainboard/sony/vpceh2k1e/acpi_tables.c new file mode 100644 index 0000000..7d634a0 --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/acpi_tables.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + // the lid is open by default. + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/sony/vpceh2k1e/board_info.txt b/src/mainboard/sony/vpceh2k1e/board_info.txt new file mode 100644 index 0000000..689ca8f --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/board_info.txt @@ -0,0 +1,5 @@ +Category: laptop +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: n diff --git a/src/mainboard/sony/vpceh2k1e/devicetree.cb b/src/mainboard/sony/vpceh2k1e/devicetree.cb new file mode 100644 index 0000000..d96ae12 --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/devicetree.cb @@ -0,0 +1,63 @@ +chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" + register "gfx.ndid" = "3" + device cpu_cluster 0x0 on + chip cpu/intel/socket_rPGA989 + device lapic 0x0 on + end + end + chip cpu/intel/model_206ax + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0xacac off + end + end + end + device domain 0x0 on + subsystemid 0x104d 0x908b inherit + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "1" + register "gen1_dec" = "0x000c0601" + register "gen2_dec" = "0x000c1641" + register "gen3_dec" = "0x00040069" + register "gpi7_routing" = "2" + register "p_cnt_throttling_supported" = "1" + register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x9" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 off end # Intel Gigabit Ethernet + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio Audio controller + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 on end # PCIe Port #4 + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 on end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on end # LPC bridge PCI-LPC bridge + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 off end # Thermal + end + device pci 00.0 on end # Host bridge + device pci 01.0 on end # PCIe Bridge for discrete graphics + device pci 02.0 off end # Internal graphics + end +end diff --git a/src/mainboard/sony/vpceh2k1e/dsdt.asl b/src/mainboard/sony/vpceh2k1e/dsdt.asl new file mode 100644 index 0000000..675703b --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/dsdt.asl @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Angel Pons <th3fanbus(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI 2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 // OEM revision +) +{ + /* Some generic macros */ + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + + /* global NVS and variables. */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/sony/vpceh2k1e/gpio.c b/src/mainboard/sony/vpceh2k1e/gpio.c new file mode 100644 index 0000000..5a16e8e --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/gpio.c @@ -0,0 +1,235 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_GPIO, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio26 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_INPUT, + .gpio29 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, + .gpio30 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio2 = GPIO_INVERT, + .gpio3 = GPIO_INVERT, + .gpio4 = GPIO_INVERT, + .gpio5 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio9 = GPIO_INVERT, + .gpio10 = GPIO_INVERT, + .gpio11 = GPIO_INVERT, + .gpio12 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, + .gpio15 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_GPIO, + .gpio42 = GPIO_MODE_GPIO, + .gpio43 = GPIO_MODE_GPIO, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_INPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_INPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_OUTPUT, + .gpio61 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio49 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, + .gpio66 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/sony/vpceh2k1e/hda_verb.c b/src/mainboard/sony/vpceh2k1e/hda_verb.c new file mode 100644 index 0000000..d2c4fa3 --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/hda_verb.c @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x14f1506e, /* Codec Vendor / Device ID: Conexant */ + 0x104d5a00, /* Subsystem ID */ + + 0x0000000b, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x0, 0x104d5a00), + + /* NID 0x19. */ + AZALIA_PIN_CFG(0x0, 0x19, 0x03211040), + + /* NID 0x1a. */ + AZALIA_PIN_CFG(0x0, 0x1a, 0x400001f0), + + /* NID 0x1b. */ + AZALIA_PIN_CFG(0x0, 0x1b, 0x03a15030), + + /* NID 0x1c. */ + AZALIA_PIN_CFG(0x0, 0x1c, 0x400001f0), + + /* NID 0x1d. */ + AZALIA_PIN_CFG(0x0, 0x1d, 0x400001f0), + + /* NID 0x1e. */ + AZALIA_PIN_CFG(0x0, 0x1e, 0x400001f0), + + /* NID 0x1f. */ + AZALIA_PIN_CFG(0x0, 0x1f, 0x90170110), + + /* NID 0x20. */ + AZALIA_PIN_CFG(0x0, 0x20, 0x400001f0), + + /* NID 0x22. */ + AZALIA_PIN_CFG(0x0, 0x22, 0x400001f0), + + /* NID 0x23. */ + AZALIA_PIN_CFG(0x0, 0x23, 0x90a70150), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/sony/vpceh2k1e/mainboard.c b/src/mainboard/sony/vpceh2k1e/mainboard.c new file mode 100644 index 0000000..08cb738 --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/mainboard.c @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Angel Pons <th3fanbus(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <ec/acpi/ec.h> +#include <console/console.h> +#include <pc80/keyboard.h> + +static void mainboard_init(struct device *dev) +{ + /* FIXME: trim this down or remove if necessary */ + if (0) { + int i; + const u8 dmp[256] = { + /* 00 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x94, 0x94, 0x94, 0x94, 0x94, 0x94, + /* 10 */ 0x94, 0x94, 0x05, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 20 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 30 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x14, 0xc0, 0x00, + /* 40 */ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 50 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x2d, 0x29, 0x00, 0x31, 0x00, 0x00, 0x00, 0x00, + /* 60 */ 0x41, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x6e, 0x0a, 0x28, 0x0a, 0x01, 0x01, 0x26, 0x00, 0x00, 0x00, + /* 70 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 80 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 90 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* a0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* b0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* c0 */ 0x10, 0x02, 0x00, 0x00, 0x09, 0x4a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x44, + /* d0 */ 0x00, 0xff, 0x00, 0x00, 0x01, 0x00, 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x0b, 0x1a, + /* e0 */ 0x28, 0x28, 0x28, 0x00, 0x00, 0x00, 0x58, 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* f0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, + }; + + printk(BIOS_DEBUG, "Replaying EC dump ..."); + for (i = 0; i < 256; i++) + ec_write (i, dmp[i]); + printk(BIOS_DEBUG, "done\n"); + } + pc_keyboard_init(NO_AUX_DEVICE); +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = mainboard_init; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/sony/vpceh2k1e/romstage.c b/src/mainboard/sony/vpceh2k1e/romstage.c new file mode 100644 index 0000000..0e1c365 --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/romstage.c @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <lib.h> +#include <timestamp.h> +#include <arch/byteorder.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <arch/acpi.h> +#include <console/console.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/gpio.h> +#include <arch/cpu.h> +#include <cpu/x86/msr.h> + +void pch_enable_lpc(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1c01); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x000c0601); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c1641); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00040069); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000000); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); +} + +void mainboard_rcba_config(void) +{ +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, + { 1, 1, 1 }, + { 1, 1, 2 }, + { 0, 1, -1 }, + { 1, 1, 3 }, + { 0, 0, -1 }, + { 0, 0, -1 }, + { 0, 0, -1 }, + { 0, 1, -1 }, + { 1, 0, -1 }, + { 0, 0, -1 }, + { 0, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, +}; + +void mainboard_early_init(int s3resume) +{ +} + +void mainboard_config_superio(void) +{ +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[2], 0x52, id_only); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/30973 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf324f1276611ab06d5906cab87ad538bfad7218 Gerrit-Change-Number: 30973 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 weeks, 5 days

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Change in ...coreboot[master]: cpu/intel: Use macro instead of numbers

by HAOUAS Elyes (Code Review)

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31196 Change subject: cpu/intel: Use macro instead of numbers ...................................................................... cpu/intel: Use macro instead of numbers Change-Id: Ic18c219beaec3dad197916a1e235a027c1c74a89 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/intel/fsp_model_406dx/model_406dx_init.c M src/cpu/intel/haswell/haswell_init.c M src/cpu/intel/model_1067x/model_1067x_init.c M src/cpu/intel/model_106cx/model_106cx_init.c M src/cpu/intel/model_206ax/model_206ax_init.c M src/cpu/intel/model_6ex/model_6ex_init.c M src/cpu/intel/model_6fx/model_6fx_init.c 7 files changed, 10 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/31196/1 diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx_init.c b/src/cpu/intel/fsp_model_406dx/model_406dx_init.c index 7994f0b..06b37a9 100644 --- a/src/cpu/intel/fsp_model_406dx/model_406dx_init.c +++ b/src/cpu/intel/fsp_model_406dx/model_406dx_init.c @@ -47,9 +47,9 @@ msr_t msr; msr = rdmsr(IA32_MISC_ENABLE); - msr.lo |= (1 << 0); /* Fast String enable */ + msr.lo |= FAST_STRINGS_ENABLE_BIT; msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ - msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ + msr.lo |= SPEED_STEP_ENABLE_BIT; wrmsr(IA32_MISC_ENABLE, msr); /* Disable Thermal interrupts */ diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index aa77964..08abdf5 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -578,9 +578,9 @@ msr_t msr; msr = rdmsr(IA32_MISC_ENABLE); - msr.lo |= (1 << 0); /* Fast String enable */ + msr.lo |= FAST_STRINGS_ENABLE_BIT; msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ - msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ + msr.lo |= SPEED_STEP_ENABLE_BIT; wrmsr(IA32_MISC_ENABLE, msr); /* Disable Thermal interrupts */ diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index 6068be1..97ed39d 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -199,7 +199,7 @@ msr.lo |= (1 << 10); /* FERR# multiplexing */ if (eist) - msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ + msr.lo |= SPEED_STEP_ENABLE_BIT; /* Enable C2E */ if (((sub_cstates >> (2 * 4)) & 0xf) >= 2) diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c index e443026..1c0d081 100644 --- a/src/cpu/intel/model_106cx/model_106cx_init.c +++ b/src/cpu/intel/model_106cx/model_106cx_init.c @@ -65,7 +65,7 @@ msr.lo |= (1 << 10); /* FERR# multiplexing */ // TODO: Only if IA32_PLATFORM_ID[17] = 0 and IA32_PLATFORM_ID[50] = 1 - msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ + msr.lo |= SPEED_STEP_ENABLE_BIT; // TODO Do we want Deep C4 and Dynamic L2 shrinking? wrmsr(IA32_MISC_ENABLE, msr); diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 33ad1e7..c2e0364 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -338,9 +338,9 @@ msr_t msr; msr = rdmsr(IA32_MISC_ENABLE); - msr.lo |= (1 << 0); /* Fast String enable */ + msr.lo |= FAST_STRINGS_ENABLE_BIT; msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ - msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ + msr.lo |= SPEED_STEP_ENABLE_BIT; wrmsr(IA32_MISC_ENABLE, msr); /* Disable Thermal interrupts */ diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index 19a22f1..fbc6964 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -67,7 +67,7 @@ msr.lo |= (1 << 10); /* FERR# multiplexing */ // TODO: Only if IA32_PLATFORM_ID[17] = 0 and IA32_PLATFORM_ID[50] = 1 - msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ + msr.lo |= SPEED_STEP_ENABLE_BIT; /* Enable C2E */ msr.lo |= (1 << 26); diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index 4e19896..adc0265 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -70,7 +70,7 @@ msr.lo |= (1 << 10); /* FERR# multiplexing */ // TODO: Only if IA32_PLATFORM_ID[17] = 0 and IA32_PLATFORM_ID[50] = 1 - msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ + msr.lo |= SPEED_STEP_ENABLE_BIT; /* Enable C2E */ msr.lo |= (1 << 26); -- To view, visit https://review.coreboot.org/c/coreboot/+/31196 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic18c219beaec3dad197916a1e235a027c1c74a89 Gerrit-Change-Number: 31196 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 weeks, 6 days

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