May 2019 - coreboot-gerrit - mail.coreboot.org

Change in ...coreboot[master]: SKL: Add ACPI brightness control

by Matthew Garrett (Code Review)

Matthew Garrett has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32549 Change subject: SKL: Add ACPI brightness control ...................................................................... SKL: Add ACPI brightness control Hook up the generic src/drivers/intel/gma ACPI backlight control for Skylake. Based on a patch by Matt DeVillier <matt.devillier(a)gmail.com>. Signed-off-by: Matthew Garrett <mjg59(a)google.com> Change-Id: I993770fdcd0a28cee756df2bd6a795498f175952 --- M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/include/intelblocks/graphics.h M src/soc/intel/skylake/acpi/globalnvs.asl M src/soc/intel/skylake/acpi/pch.asl M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/graphics.c M src/soc/intel/skylake/include/soc/nvs.h 7 files changed, 40 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/32549/1 diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 5d3b4a1..6489e8e 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -33,6 +33,10 @@ pci_dev_init(dev); } +__weak void gma_ssdt(struct device *dev) +{ +} + static uintptr_t graphics_get_bar(unsigned long index) { struct device *dev = SA_DEV_IGD; @@ -104,6 +108,7 @@ .init = graphics_soc_init, .ops_pci = &pci_dev_ops_pci, .write_acpi_tables = graphics_soc_write_acpi_opregion, + .acpi_fill_ssdt_generator = gma_ssdt, }; static const unsigned short pci_device_ids[] = { diff --git a/src/soc/intel/common/block/include/intelblocks/graphics.h b/src/soc/intel/common/block/include/intelblocks/graphics.h index 6be7661..077f0db 100644 --- a/src/soc/intel/common/block/include/intelblocks/graphics.h +++ b/src/soc/intel/common/block/include/intelblocks/graphics.h @@ -51,4 +51,7 @@ void graphics_gtt_rmw(unsigned long reg, uint32_t andmask, uint32_t ormask); uintptr_t graphics_get_memory_base(void); +void gma_ssdt(struct device *dev); +struct i915_gpu_controller_info *intel_igd_get_controller_info(void); + #endif /* SOC_INTEL_COMMON_BLOCK_GRAPHICS_H */ diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl index c4544e8..6963f70 100644 --- a/src/soc/intel/skylake/acpi/globalnvs.asl +++ b/src/soc/intel/skylake/acpi/globalnvs.asl @@ -70,6 +70,9 @@ EPCS, 8, // 0x43 - SGX Enabled status EMNA, 64, // 0x44 - 0x4B EPC base address ELNG, 64, // 0x4C - 0x53 EPC Length + BRTL, 32, // 0x54 - 0x57 Brightness Level + CSTE, 16, // 0x58 - 0x59 Current display state + NSTE, 16, // 0x5a - 0x5b Next display state /* IGD OpRegion */ Offset (0xb4), diff --git a/src/soc/intel/skylake/acpi/pch.asl b/src/soc/intel/skylake/acpi/pch.asl index 0aba2e7..f0095bc 100644 --- a/src/soc/intel/skylake/acpi/pch.asl +++ b/src/soc/intel/skylake/acpi/pch.asl @@ -56,6 +56,9 @@ /* USB XHCI 0:14.0 */ #include "xhci.asl" +/* Graphics */ +#include <drivers/intel/gma/acpi/pch.asl> + Method (_OSC, 4) { /* Check for proper GUID */ diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 57d51e7..51bb740 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -22,6 +22,7 @@ #include <arch/acpi_device.h> #include <device/i2c_simple.h> #include <drivers/i2c/designware/dw_i2c.h> +#include <drivers/intel/gma/i915.h> #include <intelblocks/chip.h> #include <intelblocks/gspi.h> #include <intelblocks/lpc_lib.h> @@ -580,6 +581,8 @@ /* Enable/Disable Sata power optimization */ u8 SataPwrOptEnable; + + struct i915_gpu_controller_info gfx; }; typedef struct soc_intel_skylake_config config_t; diff --git a/src/soc/intel/skylake/graphics.c b/src/soc/intel/skylake/graphics.c index 07ee67a..1be5f9d 100644 --- a/src/soc/intel/skylake/graphics.c +++ b/src/soc/intel/skylake/graphics.c @@ -122,3 +122,22 @@ printk(BIOS_DEBUG, "current = %lx\n", current); return current; } + +struct i915_gpu_controller_info *intel_igd_get_controller_info(void) +{ + struct device *dev = dev_find_slot(0, PCI_DEVFN(0x2, 0)); + if (!dev) + return NULL; + struct soc_intel_skylake_config *chip = dev->chip_info; + return &chip->gfx; +} + +void gma_ssdt(struct device *dev) +{ + struct i915_gpu_controller_info *gfx = intel_igd_get_controller_info(); + + if (!gfx) + return; + + drivers_intel_gma_displays_ssdt_generate(gfx); +} diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h index 72b1ac9..5a2ca38 100644 --- a/src/soc/intel/skylake/include/soc/nvs.h +++ b/src/soc/intel/skylake/include/soc/nvs.h @@ -60,7 +60,10 @@ u8 ecps; /* 0x43 - SGX Enabled status */ u64 emna; /* 0x44 - 0x4B EPC base address */ u64 elng; /* 0x4C - 0x53 EPC Length */ - u8 rsvd[96]; + u32 brtl; /* 0x54 - 0x57 Brightness Level */ + u16 cste; /* 0x58 - 0x59 Current display state */ + u16 nste; /* 0x5a - 0x5b Next display state */ + u8 rsvd[88]; /* IGD OpRegion */ u32 aslb; /* 0xb4 - IGD OpRegion Base Address */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32549 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I993770fdcd0a28cee756df2bd6a795498f175952 Gerrit-Change-Number: 32549 Gerrit-PatchSet: 1 Gerrit-Owner: Matthew Garrett <mjg59(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Adding Asus A88XM-E FM2+ motherboard with documentation

by Balázs Vinarz (Code Review)

Balázs Vinarz has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30987 Change subject: Adding Asus A88XM-E FM2+ motherboard with documentation ...................................................................... Adding Asus A88XM-E FM2+ motherboard with documentation Signed-off-by: Balazs Vinarz <vinibali1(a)gmail.com> Change-Id: I60fa0636ba41f5f1a6a3faa2764bf2f0a968cf90 --- A Documentation/mainboard/asus/a88xm-e.md A src/mainboard/asus/a88xm-e/BiosCallOuts.c A src/mainboard/asus/a88xm-e/Kconfig A src/mainboard/asus/a88xm-e/Kconfig.name A src/mainboard/asus/a88xm-e/Makefile.inc A src/mainboard/asus/a88xm-e/OemCustomize.c A src/mainboard/asus/a88xm-e/OptionsIds.h A src/mainboard/asus/a88xm-e/acpi/cpstate.asl A src/mainboard/asus/a88xm-e/acpi/gpe.asl A src/mainboard/asus/a88xm-e/acpi/mainboard.asl A src/mainboard/asus/a88xm-e/acpi/routing.asl A src/mainboard/asus/a88xm-e/acpi/sata.asl A src/mainboard/asus/a88xm-e/acpi/si.asl A src/mainboard/asus/a88xm-e/acpi/sleep.asl A src/mainboard/asus/a88xm-e/acpi/superio.asl A src/mainboard/asus/a88xm-e/acpi/thermal.asl A src/mainboard/asus/a88xm-e/acpi/usb_oc.asl A src/mainboard/asus/a88xm-e/acpi_tables.c A src/mainboard/asus/a88xm-e/board_info.txt A src/mainboard/asus/a88xm-e/buildOpts.c A src/mainboard/asus/a88xm-e/cmos.layout A src/mainboard/asus/a88xm-e/devicetree_a88xm-e.cb A src/mainboard/asus/a88xm-e/dsdt.asl A src/mainboard/asus/a88xm-e/irq_tables.c A src/mainboard/asus/a88xm-e/mainboard.c A src/mainboard/asus/a88xm-e/mptable.c A src/mainboard/asus/a88xm-e/romstage.c 27 files changed, 2,371 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/30987/1 diff --git a/Documentation/mainboard/asus/a88xm-e.md b/Documentation/mainboard/asus/a88xm-e.md new file mode 100644 index 0000000..5f50c5a --- /dev/null +++ b/Documentation/mainboard/asus/a88xm-e.md @@ -0,0 +1,131 @@ +# ASUS A88XM-E + +This page describes how to run coreboot on the [ASUS A88XM-E]. + +## Technology + +Both "Trinity" and "Richland" FM2 desktop processing units are working, +the CPU architecture in these CPUs/APUs are [Piledriver], +and their GPU is [TeraScale 3] (VLIW4-based). + +Kaveri is non-working at the moment (FM2+), +the CPU architecture in these CPUs/APUs are [Steamroller], +and their GPU is [Sea Islands] (GCN2-based). + +```eval_rst ++------------------+--------------------------------------------------+ +| A88XM-E | | ++------------------+--------------------------------------------------+ +| DDR voltage IC | Nuvoton 3101S | ++------------------+--------------------------------------------------+ +| Network | Realtek RTL8111G - Not working | ++------------------+--------------------------------------------------+ +| Northbridge | Integrated into CPU with IMC and GPU (APUs only) | ++------------------+--------------------------------------------------+ +| Southbridge | Bolton-D4 | ++------------------+--------------------------------------------------+ +| Sound IC | Realtek ALC887 | ++------------------+--------------------------------------------------+ +| Super I/O | ITE 8603E | ++------------------+--------------------------------------------------+ +| VRM controller | DIGI VRM ASP1206 | ++------------------+--------------------------------------------------+ +``` + +## Flashing coreboot + +```eval_rst ++---------------------+------------+ +| Type | Value | ++=====================+============+ +| Socketed flash | yes | ++---------------------+------------+ +| Model | [GD25Q64] | ++---------------------+------------+ +| Size | 8 MiB | ++---------------------+------------+ +| Package | DIP-8 | ++---------------------+------------+ +| Write protection | yes | ++---------------------+------------+ +| Dual BIOS feature | no | ++---------------------+------------+ +| Internal flashing | yes | ++---------------------+------------+ +``` + +### Internal programming + +The main SPI flash can be accessed using [flashrom], if the +AmdSpiRomProtect modules have been deleted in the factory image previously. + +## Integrated graphics + +### Retrieve the VGA optionrom from the vendor EFI binary by running: + + # dd if=/dev/mem of=vgabios.bin bs=1k count=64 skip=768 + +This version is usable for all the GPUs. +1002,9901 Trinity (Radeon HD 7660D) +1002,9904 Trinity (Radeon HD 7560D) +1002,990c Richland (Radeon HD 8670D) +1002,990e Richland (Radeon HD 8570D) +1002,9991 Trinity (Radeon HD 7540D) +1002,9993 Trinity (Radeon HD 7480D) +1002,9996 Richland (Radeon HD 8470D) +1002,9998 Richland (Radeon HD 8370D) +1002,999d Richland (Radeon HD 8550D) +1002,130f Kaveri (Radeon R7) + +## Known issues + +- AHCI hot-plug +- Integrated ethernet +- S3 resume +- XHCI + +### XHCI ports can broke after using any of the blobs, restarting the +board with factory image makes it work again as fallback. +Tested even with/without the Bolton and Hudson blobs. + +## Untested + +- audio over HDMI +- IOMMU +- PS/2 mouse + +## TODOs + +- one ATOMBIOS module for all the integrated GPUs +- manage to work with Kaveri/Godavary (missing PSP firmware?) + +## Working + +- ACPI +- CPU frequency scaling +- flashrom under coreboot +- Hardware monitoring +- Integrated graphics +- Keyboard +- KVM virtualization +- Onboard audio +- PCI +- PCIe +- PS/2 keyboard (during payload, bootloader) +- SATA +- Serial port +- SuperIO based fan control +- USB (disabling XHCI controller makes to work as fallback USB2.0 ports) + +## Extra resources + +- [Board manual] + +[ASUS A88XM-E]: https://www.asus.com/Motherboards/A88XME/ +[Board manual]: https://dlcdnets.asus.com/pub/ASUS/mb/SocketFM2/A88XM-E/E9125_A88XM-E.pdf +[flashrom]: https://flashrom.org/Flashrom +[GD25Q64]: http://www.elm-tech.com/ja/products/spi-flash-memory/gd25q64/gd25q64.pdf +[Piledriver]: https://en.wikipedia.org/wiki/Piledriver_%28microarchitecture%29#APU_lines +[Sea Islands]: https://en.wikipedia.org/wiki/Graphics_Core_Next#GCN_2nd_generation +[Steamroller]: https://en.wikipedia.org/wiki/Steamroller_(microarchitecture) +[TeraScale 3]: https://en.wikipedia.org/wiki/TeraScale_%28microarchitecture%29#TeraScale_3 diff --git a/src/mainboard/asus/a88xm-e/BiosCallOuts.c b/src/mainboard/asus/a88xm-e/BiosCallOuts.c new file mode 100644 index 0000000..56c1753 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/BiosCallOuts.c @@ -0,0 +1,98 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <AGESA.h> +#include <northbridge/amd/agesa/BiosCallOuts.h> +#include <northbridge/amd/agesa/state_machine.h> + +#include <vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h> +#include <stdlib.h> + +const BIOS_CALLOUT_STRUCT BiosCallouts[] = +{ + {AGESA_DO_RESET, agesa_Reset }, + {AGESA_READ_SPD, agesa_ReadSpd }, + {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, + {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, + {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData }, + {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, + {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, + {AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage } +}; +const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); + +/** + * ASUS A88XM-E board ALC887-VD Verb Table + * + * Copied from `/sys/class/sound/hwC1D0/init_pin_configs` when running + * the vendor BIOS. + */ +#if !IS_ENABLED(CONFIG_BOARD_ASUS_A88XM_E) +const CODEC_ENTRY a88xm_e_alc887_VerbTbl[] = { + {0x11, 0x90460130}, + {0x12, 0x40330000}, + {0x14, 0x01014010}, + {0x15, 0x411111f0}, + {0x16, 0x411111f0}, + {0x17, 0x411111f0}, + {0x18, 0x01a19040}, + {0x19, 0x02a19050}, + {0x1a, 0x0181304f}, + {0x1b, 0x02214020}, + {0x1c, 0x411111f0}, + {0x1d, 0x4044c601}, + {0x1e, 0x411111f0}, + {0x1f, 0x411111f0} + }; +#else +const CODEC_ENTRY a88xm_e_alc887_VerbTbl[] = { + {0x11, 0x90460130}, + {0x12, 0x40330000}, + {0x14, 0x01014010}, + {0x15, 0x411111f0}, + {0x16, 0x411111f0}, + {0x17, 0x411111f0}, + {0x18, 0x01a19040}, + {0x19, 0x02a19050}, + {0x1a, 0x0181304f}, + {0x1b, 0x02214020}, + {0x1c, 0x411111f0}, + {0x1d, 0x4044c601}, + {0x1e, 0x411111f0}, + {0x1f, 0x411111f0} +}; +#endif + +static const CODEC_TBL_LIST CodecTableList[] = +{ + {0x10ec0887, (CODEC_ENTRY*)&a88xm_e_alc887_VerbTbl[0]}, + {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL} +}; + +void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset) +{ + FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE); +} + +void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env) +{ + /* Azalia Controller OEM Codec Table Pointer */ + FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&CodecTableList[0]); + + /* Fan Control */ + FchParams_env->Imc.ImcEnable = FALSE; + FchParams_env->Hwm.HwMonitorEnable = FALSE; + FchParams_env->Hwm.HwmFchtsiAutoPoll = FALSE;/* 1 enable, 0 disable TSI Auto Polling */ +} diff --git a/src/mainboard/asus/a88xm-e/Kconfig b/src/mainboard/asus/a88xm-e/Kconfig new file mode 100644 index 0000000..70be2f1 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/Kconfig @@ -0,0 +1,117 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# Copyright (C) 2012 Rudolf Marek <r.marek(a)assembler.cz> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +if BOARD_ASUS_A88XM_E + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select CPU_AMD_AGESA_FAMILY15_TN + select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN + select SOUTHBRIDGE_AMD_AGESA_HUDSON + select HAVE_OPTION_TABLE + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select SUPERIO_ITE_IT8728F + select BOARD_ROMSIZE_KB_8192 + select GFXUMA + +choice + prompt "DDR3 memory voltage" + default BOARD_ASUS_A88XM_E_DDR3_VOLT_150 + +config BOARD_ASUS_A88XM_E_DDR3_VOLT_135 + bool "1.35V" + help + Set DRR3 memory voltage to 1.35V +config BOARD_ASUS_A88XM_E_DDR3_VOLT_150 + bool "1.50V" + help + Set DRR3 memory voltage to 1.50V +config BOARD_ASUS_A88XM_E_DDR3_VOLT_165 + bool "1.65V" + help + Set DRR3 memory voltage to 1.65V +endchoice + +config BOARD_ASUS_A88XM_E_DDR3_VOLT_VAL + hex + default 0x9e if BOARD_ASUS_A88XM_E_DDR3_VOLT_135 + default 0x0 if BOARD_ASUS_A88XM_E_DDR3_VOLT_150 + default 0x1e if BOARD_ASUS_A88XM_E_DDR3_VOLT_165 + +config MAINBOARD_DIR + string + default asus/a88xm-e + +config MAINBOARD_PART_NUMBER + string + default "A88XM-E" if BOARD_ASUS_A88XM_E + +config HW_MEM_HOLE_SIZEK + hex + default 0x200000 + +config MAX_CPUS + int + default 4 + +config HUDSON_XHCI_FWM + bool + default n + +config HUDSON_IMC_FWM + bool + default n + +config IRQ_SLOT_COUNT + int + default 11 + +config ONBOARD_VGA_IS_PRIMARY + bool + default y + +config VGA_BIOS_ID + string + default "1002,990e" + +config CONFIG_DRIVERS_PS2_KEYBOARD + bool + default y + +config CONFIG_HUDSON_XHCI_ENABLE + bool + default n + +config HUDSON_LEGACY_FREE + bool + default n + +config POST_IO + bool + default n + +config CONFIG_POST_DEVICE_PCI_PCIE + bool + default y + +config DEVICETREE + string + default "devicetree_a88xm-e.cb" + +endif # BOARD_ASUS_A88XM_E diff --git a/src/mainboard/asus/a88xm-e/Kconfig.name b/src/mainboard/asus/a88xm-e/Kconfig.name new file mode 100644 index 0000000..492d610 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ASUS_A88XM_E + bool "A88XM-E" diff --git a/src/mainboard/asus/a88xm-e/Makefile.inc b/src/mainboard/asus/a88xm-e/Makefile.inc new file mode 100644 index 0000000..f8895fa --- /dev/null +++ b/src/mainboard/asus/a88xm-e/Makefile.inc @@ -0,0 +1,22 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +romstage-y += buildOpts.c +romstage-y += BiosCallOuts.c +romstage-y += OemCustomize.c + +ramstage-y += buildOpts.c +ramstage-y += BiosCallOuts.c +ramstage-y += OemCustomize.c diff --git a/src/mainboard/asus/a88xm-e/OemCustomize.c b/src/mainboard/asus/a88xm-e/OemCustomize.c new file mode 100644 index 0000000..4c4c5bf --- /dev/null +++ b/src/mainboard/asus/a88xm-e/OemCustomize.c @@ -0,0 +1,177 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <Porting.h> +#include <AGESA.h> + +#include <northbridge/amd/agesa/state_machine.h> +#include <PlatformMemoryConfiguration.h> + +/* + * Lane ID Mapping (from Fam15h BKDG: Table 45: Lane Id Mapping) + * + * Lane Id + * 0 P_UMI_[T,R]X[P,N]0 - southbridge link, connect via dev 8 + * 1 P_UMI_[T,R]X[P,N]1 - southbridge link, connect via dev 8 + * 2 P_UMI_[T,R]X[P,N]2 - southbridge link, connect via dev 8 + * 3 P_UMI_[T,R]X[P,N]3 - southbridge link, connect via dev 8 + * 4 P_GPP_[T,R]X[P,N]0 - may connect to PCI dev 4 - 7 + * 5 P_GPP_[T,R]X[P,N]1 - may connect to PCI dev 4 - 7 + * 6 P_GPP_[T,R]X[P,N]2 - may connect to PCI dev 4 - 7 + * 7 P_GPP_[T,R]X[P,N]3 - may connect to PCI dev 4 - 7 + * 8 P_GFX_[T,R]X[P,N]0 - may be used to form GFX slot or DDI + * 9 P_GFX_[T,R]X[P,N]1 - may be used to form GFX slot or DDI + * 10 P_GFX_[T,R]X[P,N]2 - may be used to form GFX slot or DDI + * 11 P_GFX_[T,R]X[P,N]3 - may be used to form GFX slot or DDI + * 12 P_GFX_[T,R]X[P,N]4 - may be used to form GFX slot or DDI + * 13 P_GFX_[T,R]X[P,N]5 - may be used to form GFX slot or DDI + * 14 P_GFX_[T,R]X[P,N]6 - may be used to form GFX slot or DDI + * 15 P_GFX_[T,R]X[P,N]7 - may be used to form GFX slot or DDI + * 16 P_GFX_[T,R]X[P,N]8 - may be used to form GFX slot or DDI + * 17 P_GFX_[T,R]X[P,N]9 - may be used to form GFX slot or DDI + * 18 P_GFX_[T,R]X[P,N]10 - may be used to form GFX slot or DDI + * 19 P_GFX_[T,R]X[P,N]11 - may be used to form GFX slot or DDI + * 20 P_GFX_[T,R]X[P,N]12 - may be used to form GFX slot or DDI + * 21 P_GFX_[T,R]X[P,N]13 - may be used to form GFX slot or DDI + * 22 P_GFX_[T,R]X[P,N]14 - may be used to form GFX slot or DDI + * 23 P_GFX_[T,R]X[P,N]15 - may be used to form GFX slot or DDI + * 24 DP0_TX[P,N]0 - rest is just for DDI (graphics outputs) + * 25 DP0_TX[P,N]1 + * 26 DP0_TX[P,N]2 + * 27 DP0_TX[P,N]3 + * 28 DP1_TX[P,N]0 + * 29 DP1_TX[P,N]1 + * 30 DP1_TX[P,N]2 + * 31 DP1_TX[P,N]3 + * 32 DP2_TX[P,N]0 + * 33 DP2_TX[P,N]1 + * 34 DP2_TX[P,N]2 + * 35 DP2_TX[P,N]3 + * 36 DP2_TX[P,N]4 + * 37 DP2_TX[P,N]5 + * 38 DP2_TX[P,N]6 + */ + +static const PCIe_PORT_DESCRIPTOR PortList[] = { + /* PCIe port, Lanes 8:23, PCI Device Number 2, blue x16 slot */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 23), + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 1) + }, + /* PCIe port, Lanes 4:7, PCI Device Number 4, black x16 slot (in fact x4) */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7), + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 1) + }, + /* PCIe port, Lanes 0:3, UMI link to SB, PCI Device Number 8 */ + { + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3), + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0) + }, +}; + +/* + * It is not known, if the setup is complete. + * + * Tested and works: VGA/DVI + * Untested: HDMI + */ +static const PCIe_DDI_DESCRIPTOR DdiList[] = { + // DP0 to HDMI0/DP + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 24, 27), + PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux1, Hdp1) + }, + // DP1 to FCH + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 28, 31), + PCIE_DDI_DATA_INITIALIZER(ConnectorTypeNutmegDpToVga, Aux2, Hdp2) + }, + // DP2 to HDMI1/DP + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 32, 35), + PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux3, Hdp3) + }, +}; + +static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { + .Flags = DESCRIPTOR_TERMINATE_LIST, + .SocketId = 0, + .PciePortList = PortList, + .DdiLinkList = DdiList, +}; + +void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) +{ + FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface; + FchReset->Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchReset->Xhci1Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); +} + +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) +{ + InitEarly->GnbConfig.PcieComplexList = &PcieComplex; + InitEarly->GnbConfig.PsppPolicy = 0; +} + +/*---------------------------------------------------------------------------------------- + * CUSTOMER OVERIDES MEMORY TABLE + *---------------------------------------------------------------------------------------- + */ + +/* + * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA + * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable + * is populated, AGESA will base its settings on the data from the table. Otherwise, it will + * use its default conservative settings. + */ + +static CONST PSO_ENTRY ROMDATA MemoryTable_XM_E[] = { + + NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1), + NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2), + + PSO_END +}; + +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + if (IS_ENABLED(CONFIG_BOARD_ASUS_A88XM_E)) + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *) MemoryTable_XM_E; +} + +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) +{ + /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ + InitMid->GnbMidConfiguration.iGpuVgaMode = 0; +} diff --git a/src/mainboard/asus/a88xm-e/OptionsIds.h b/src/mainboard/asus/a88xm-e/OptionsIds.h new file mode 100644 index 0000000..b45f5a8 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/OptionsIds.h @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/** + * @file + * + * IDS Option File + * + * This file is used to switch on/off IDS features. + * + */ +#ifndef _OPTION_IDS_H_ +#define _OPTION_IDS_H_ + +/** + * + * This file generates the defaults tables for the Integrated Debug Support + * Module. The documented build options are imported from a user controlled + * file for processing. The build options for the Integrated Debug Support + * Module are listed below: + * + * IDSOPT_IDS_ENABLED + * IDSOPT_ERROR_TRAP_ENABLED + * IDSOPT_CONTROL_ENABLED + * IDSOPT_TRACING_ENABLED + * IDSOPT_PERF_ANALYSIS + * IDSOPT_ASSERT_ENABLED + * IDS_DEBUG_PORT + * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED + * + **/ + +//#define IDSOPT_IDS_ENABLED TRUE +//#define IDSOPT_CONTROL_ENABLED TRUE +#define IDSOPT_TRACING_ENABLED TRUE +#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE +//#define IDSOPT_PERF_ANALYSIS TRUE +#define IDSOPT_ASSERT_ENABLED TRUE +//#undef IDSOPT_DEBUG_ENABLED +//#define IDSOPT_DEBUG_ENABLED FALSE +//#undef IDSOPT_HOST_SIMNOW +//#define IDSOPT_HOST_SIMNOW FALSE +//#undef IDSOPT_HOST_HDT +//#define IDSOPT_HOST_HDT FALSE +//#define IDS_DEBUG_PORT 0x80 + +#endif diff --git a/src/mainboard/asus/a88xm-e/acpi/cpstate.asl b/src/mainboard/asus/a88xm-e/acpi/cpstate.asl new file mode 100644 index 0000000..69de2d8 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/acpi/cpstate.asl @@ -0,0 +1,112 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* This file defines the processor and performance state capability + * for each core in the system. It is included into the DSDT for each + * core. It assumes that each core of the system has the same performance + * characteristics. +*/ +/* +#include <arch/acpi.h> +DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001) + { + Scope (\_PR) { + Processor(CPU0,0,0x808,0x06) { + #include "cpstate.asl" + } + Processor(CPU1,1,0x0,0x0) { + #include "cpstate.asl" + } + Processor(CPU2,2,0x0,0x0) { + #include "cpstate.asl" + } + Processor(CPU3,3,0x0,0x0) { + #include "cpstate.asl" + } + } +*/ + /* P-state support: The maximum number of P-states supported by the */ + /* CPUs we'll use is 6. */ + /* Get from AMI BIOS. */ + Name(_PSS, Package(){ + Package() + { + 0x00000D48, + 0x00011170, + 0x00000004, + 0x00000004, + 0x00000000, + 0x00000000 + }, + + Package() + { + 0x00000AF0, + 0x0000C544, + 0x00000004, + 0x00000004, + 0x00000001, + 0x00000001 + }, + + Package() + { + 0x000009C4, + 0x0000B3B0, + 0x00000004, + 0x00000004, + 0x00000002, + 0x00000002 + }, + + Package() + { + 0x00000898, + 0x0000ABE0, + 0x00000004, + 0x00000004, + 0x00000003, + 0x00000003 + }, + + Package() + { + 0x00000708, + 0x0000A410, + 0x00000004, + 0x00000004, + 0x00000004, + 0x00000004 + }, + + Package() + { + 0x00000578, + 0x00006F54, + 0x00000004, + 0x00000004, + 0x00000005, + 0x00000005 + } + }) + + Name(_PCT, Package(){ + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} + }) + + Method(_PPC, 0){ + Return(0) + } diff --git a/src/mainboard/asus/a88xm-e/acpi/gpe.asl b/src/mainboard/asus/a88xm-e/acpi/gpe.asl new file mode 100644 index 0000000..297db37 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/acpi/gpe.asl @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope(\_GPE) { /* Start Scope GPE */ + + /* General event 3 */ + Method(_L03) { + /* DBGO("\\_GPE\\_L00\n") */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Legacy PM event */ + Method(_L08) { + /* DBGO("\\_GPE\\_L08\n") */ + } + + /* Temp warning (TWarn) event */ + Method(_L09) { + /* DBGO("\\_GPE\\_L09\n") */ + /* Notify (\_TZ.TZ00, 0x80) */ + } + + /* USB controller PME# */ + Method(_L0B) { + /* DBGO("\\_GPE\\_L0B\n") */ + Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* ExtEvent0 SCI event */ + Method(_L10) { + /* DBGO("\\_GPE\\_L10\n") */ + } + + + /* ExtEvent1 SCI event */ + Method(_L11) { + /* DBGO("\\_GPE\\_L11\n") */ + } + + /* GPIO0 or GEvent8 event */ + Method(_L18) { + /* DBGO("\\_GPE\\_L18\n") */ + Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Azalia SCI event */ + Method(_L1B) { + /* DBGO("\\_GPE\\_L1B\n") */ + Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } +} /* End Scope GPE */ diff --git a/src/mainboard/asus/a88xm-e/acpi/mainboard.asl b/src/mainboard/asus/a88xm-e/acpi/mainboard.asl new file mode 100644 index 0000000..8398c88 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/acpi/mainboard.asl @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + /* Data to be patched by the BIOS during POST */ + /* FIXME the patching is not done yet! */ + /* Memory related values */ + Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ + Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ + Name(PBLN, 0x0) /* Length of BIOS area */ + + Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ + Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */ + Name(HPBA, 0xFED00000) /* Base address of HPET table */ + + /* Some global data */ + Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ + Name(OSV, Ones) /* Assume nothing */ + Name(PMOD, One) /* Assume APIC */ diff --git a/src/mainboard/asus/a88xm-e/acpi/routing.asl b/src/mainboard/asus/a88xm-e/acpi/routing.asl new file mode 100644 index 0000000..0af6b42 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/acpi/routing.asl @@ -0,0 +1,258 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + /* Routing is in System Bus scope */ + Name(PR0, Package(){ + /* NB devices */ + /* Bus 0, Dev 0 - F15 Host Controller */ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ + Package(){0x0001FFFF, 0, INTB, 0 }, + Package(){0x0001FFFF, 1, INTC, 0 }, + + /* Bus 0, Dev 2 - PCIe Bridge for x16 slot */ + Package(){0x0002FFFF, 0, INTC, 0 }, + Package(){0x0002FFFF, 1, INTD, 0 }, + Package(){0x0002FFFF, 2, INTA, 0 }, + Package(){0x0002FFFF, 3, INTB, 0 }, + + /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ + + /* Bus 0, Dev 4 - PCIe Bridge for 4x slot */ + Package(){0x0004FFFF, 0, INTA, 0 }, + Package(){0x0004FFFF, 1, INTB, 0 }, + Package(){0x0004FFFF, 2, INTC, 0 }, + Package(){0x0004FFFF, 3, INTD, 0 }, + + /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ + /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ + /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ + /* Bus 0, Dev 8 - Southbridge port (normally hidden) */ + + /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */ + Package(){0x0014FFFF, 0, INTA, 0 }, + Package(){0x0014FFFF, 1, INTB, 0 }, + Package(){0x0014FFFF, 2, INTC, 0 }, + Package(){0x0014FFFF, 3, INTD, 0 }, + + /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0 + * EHCI @ func 2 */ + Package(){0x0012FFFF, 0, INTC, 0 }, + Package(){0x0012FFFF, 1, INTB, 0 }, + + Package(){0x0013FFFF, 0, INTC, 0 }, + Package(){0x0013FFFF, 1, INTB, 0 }, + + Package(){0x0016FFFF, 0, INTC, 0 }, + Package(){0x0016FFFF, 1, INTB, 0 }, + + /* SB devices */ + /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */ + Package(){0x0010FFFF, 0, INTC, 0 }, + Package(){0x0010FFFF, 1, INTB, 0 }, + + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, INTD, 0 }, + + /* Bus 0, Dev 21 Pcie Bridge */ + Package(){0x0015FFFF, 0, INTA, 0 }, + Package(){0x0015FFFF, 1, INTB, 0 }, + Package(){0x0015FFFF, 2, INTC, 0 }, + Package(){0x0015FFFF, 3, INTD, 0 }, + }) + + Name(APR0, Package(){ + /* NB devices in APIC mode */ + /* Bus 0, Dev 0 - F15 Host Controller */ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ + Package(){0x0001FFFF, 0, 0, 17 }, + Package(){0x0001FFFF, 1, 0, 18 }, + + /* Bus 0, Dev 2 - PCIe Bridge for x16 PCIe Slot */ + Package(){0x0002FFFF, 0, 0, 18 }, + Package(){0x0002FFFF, 1, 0, 19 }, + Package(){0x0002FFFF, 2, 0, 16 }, + Package(){0x0002FFFF, 3, 0, 17 }, + + /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ + + /* Bus 0, Dev 4 - PCIe Bridge for x4 PCIe Slot black */ + Package(){0x0004FFFF, 0, 0, 16 }, + Package(){0x0004FFFF, 1, 0, 17 }, + Package(){0x0004FFFF, 2, 0, 18 }, + Package(){0x0004FFFF, 3, 0, 19 }, + + /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ + /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ + /* Bus 0, Dev 7 - PCIe Bridge for network card */ + /* Bus 0, Dev 8 - Southbridge port (normally hidden) */ + + /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ + Package(){0x0014FFFF, 0, 0, 16 }, + Package(){0x0014FFFF, 1, 0, 17 }, + Package(){0x0014FFFF, 2, 0, 18 }, + Package(){0x0014FFFF, 3, 0, 19 }, + + /* SB devices in APIC mode */ + /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0 + * EHCI @ func 2 */ + Package(){0x0012FFFF, 0, 0, 18 }, + Package(){0x0012FFFF, 1, 0, 17 }, + + Package(){0x0013FFFF, 0, 0, 18 }, + Package(){0x0013FFFF, 1, 0, 17 }, + + Package(){0x0016FFFF, 0, 0, 18 }, + Package(){0x0016FFFF, 1, 0, 17 }, + + /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */ + Package(){0x0010FFFF, 0, 0, 0x12}, + Package(){0x0010FFFF, 1, 0, 0x11}, + + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, 0, 19 }, + + /* Bus 0, Dev 21 PCIE Bridge */ + Package(){0x0015FFFF, 0, 0, 17 }, + Package(){0x0015FFFF, 1, 0, 18 }, + Package(){0x0015FFFF, 2, 0, 19 }, + Package(){0x0015FFFF, 3, 0, 16 }, + }) + + Name(PS2, Package(){ + /* The external GFX - Hooked to PCIe slot 2 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + Name(APS2, Package(){ + /* The external GFX - Hooked to PCIe slot 2 */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + /* black slot */ + Name(PS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + }) + Name(APS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, + }) + + Name(PS5, Package(){ + /* PCIe slot - Hooked to PCIe slot 5 */ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, + }) + Name(APS5, Package(){ + /* PCIe slot - Hooked to PCIe slot 5 */ + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, + }) + + Name(PS6, Package(){ + /* PCIe slot - Hooked to PCIe slot 6 */ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + Name(APS6, Package(){ + /* PCIe slot - Hooked to PCIe slot 6 */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PS7, Package(){ + /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + + Name(APS7, Package(){ + /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ + Package(){0x0000FFFF, 0, 0, 19 }, + Package(){0x0000FFFF, 1, 0, 16 }, + Package(){0x0000FFFF, 2, 0, 17 }, + Package(){0x0000FFFF, 3, 0, 18 }, + }) + + Name(PBR0, Package(){ + /* PCIx1 on SB */ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + }) + Name(ABR0, Package(){ + /* PCIx1 on SB */ + Package(){0x0000FFFF, 0, 0, 0x10 }, + Package(){0x0000FFFF, 1, 0, 0x11 }, + Package(){0x0000FFFF, 2, 0, 0x12 }, + Package(){0x0000FFFF, 3, 0, 0x13 }, + }) + + Name(PBR1, Package(){ + /* Onboard network */ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, + }) + Name(ABR1, Package(){ + /* Onboard network */ + Package(){0x0000FFFF, 0, 0, 0x11 }, + Package(){0x0000FFFF, 1, 0, 0x12 }, + Package(){0x0000FFFF, 2, 0, 0x13 }, + Package(){0x0000FFFF, 3, 0, 0x10 }, + }) + + /* SB PCI Bridge */ + Name(PCIB, Package(){ + /* PCI slots: slot 0 behind Dev14, Fun4. */ + Package(){0x0005FFFF, 0, 0, 0x14 }, + Package(){0x0005FFFF, 1, 0, 0x15 }, + Package(){0x0005FFFF, 2, 0, 0x16 }, + Package(){0x0005FFFF, 3, 0, 0x17 }, + }) diff --git a/src/mainboard/asus/a88xm-e/acpi/sata.asl b/src/mainboard/asus/a88xm-e/acpi/sata.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/acpi/sata.asl diff --git a/src/mainboard/asus/a88xm-e/acpi/si.asl b/src/mainboard/asus/a88xm-e/acpi/si.asl new file mode 100644 index 0000000..ff0c3cf --- /dev/null +++ b/src/mainboard/asus/a88xm-e/acpi/si.asl @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + Scope(\_SI) { + Method(_SST, 1) { + /* DBGO("\\_SI\\_SST\n") */ + /* DBGO(" New Indicator state: ") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + } + } /* End Scope SI */ diff --git a/src/mainboard/asus/a88xm-e/acpi/sleep.asl b/src/mainboard/asus/a88xm-e/acpi/sleep.asl new file mode 100644 index 0000000..08b7de4 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/acpi/sleep.asl @@ -0,0 +1,96 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Wake status package */ +Name(WKST,Package(){Zero, Zero}) + +/* +* \_PTS - Prepare to Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2, etc +* +* Exit: +* -none- +* +* The _PTS control method is executed at the beginning of the sleep process +* for S1-S5. The sleeping value is passed to the _PTS control method. This +* control method may be executed a relatively long time before entering the +* sleep state and the OS may abort the operation without notification to +* the ACPI driver. This method cannot modify the configuration or power +* state of any device in the system. +*/ +Method(\_PTS, 1) { + /* DBGO("\\_PTS\n") */ + /* DBGO("From S0 to S") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + + /* Clear sleep SMI status flag and enable sleep SMI trap. */ + /*Store(One, CSSM) + Store(One, SSEN)*/ + + /* On older chips, clear PciExpWakeDisEn */ + /*if (LLessEqual(\_SB.SBRI, 0x13)) { + * Store(0,\_SB.PWDE) + *} + */ + + /* Clear wake status structure. */ + Store(0, Index(WKST,0)) + Store(0, Index(WKST,1)) + + Store (0x07, UPWS) +} /* End Method(\_PTS) */ + +/* +* \_BFS OEM Back From Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* -none- +*/ +Method(\_BFS, 1) { + /* DBGO("\\_BFS\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ +} + +/* +* \_WAK System Wake method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* Return package of 2 DWords +* Dword 1 - Status +* 0x00000000 wake succeeded +* 0x00000001 Wake was signaled but failed due to lack of power +* 0x00000002 Wake was signaled but failed due to thermal condition +* Dword 2 - Power Supply state +* if non-zero the effective S-state the power supply entered +*/ +Method(\_WAK, 1) { + /* DBGO("\\_WAK\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + + Return(WKST) +} /* End Method(\_WAK) */ diff --git a/src/mainboard/asus/a88xm-e/acpi/superio.asl b/src/mainboard/asus/a88xm-e/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/acpi/superio.asl diff --git a/src/mainboard/asus/a88xm-e/acpi/thermal.asl b/src/mainboard/asus/a88xm-e/acpi/thermal.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/acpi/thermal.asl diff --git a/src/mainboard/asus/a88xm-e/acpi/usb_oc.asl b/src/mainboard/asus/a88xm-e/acpi/usb_oc.asl new file mode 100644 index 0000000..f5d6980 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/acpi/usb_oc.asl @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* USB overcurrent mapping pins. */ +Name(UOM0, 0) +Name(UOM1, 2) +Name(UOM2, 0) +Name(UOM3, 7) +Name(UOM4, 2) +Name(UOM5, 2) +Name(UOM6, 6) +Name(UOM7, 2) +Name(UOM8, 6) +Name(UOM9, 6) diff --git a/src/mainboard/asus/a88xm-e/acpi_tables.c b/src/mainboard/asus/a88xm-e/acpi_tables.c new file mode 100644 index 0000000..f94fde0 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/acpi_tables.c @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <arch/ioapic.h> +#include <device/pci.h> +#include <string.h> + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + /* Write Hudson IOAPIC, only one */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, + IO_APIC_ADDR, 0); + + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, 0xF); + /* 0: mean bus 0--->ISA */ + /* 0: PIC 0 */ + /* 2: APIC 2 */ + /* 5 mean: 0101 --> Edge-triggered, Active high */ + + /* create all subtables for processors */ + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1); + /* 1: LINT1 connect to NMI */ + + return current; +} diff --git a/src/mainboard/asus/a88xm-e/board_info.txt b/src/mainboard/asus/a88xm-e/board_info.txt new file mode 100644 index 0000000..bc090ff --- /dev/null +++ b/src/mainboard/asus/a88xm-e/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asus.com/Motherboards/A88XME/ +ROM package: DIP8 +ROM protocol: [http://www.winbond.com/hq/product/code-storage-flash-memory/serial-nor-flas… SPI] +ROM socketed: y +Flashrom support: y (without AmdSpiRomProtect modules) +Release year: 2014 diff --git a/src/mainboard/asus/a88xm-e/buildOpts.c b/src/mainboard/asus/a88xm-e/buildOpts.c new file mode 100644 index 0000000..c324532 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/buildOpts.c @@ -0,0 +1,346 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/** + * @file + * + * AMD User options selection for a Brazos platform solution system + * + * This file is placed in the user's platform directory and contains the + * build option selections desired for that platform. + * + * For Information about this file, see @ref platforminstall. + * + */ + +#include <stdlib.h> + +#include <vendorcode/amd/agesa/f15tn/AGESA.h> + +/* Include the files that instantiate the configuration definitions. */ +#include <vendorcode/amd/agesa/f15tn/Include/AdvancedApi.h> +#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h> +#include <vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.h> +#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h> +/* the next two headers depend on heapManager.h */ +#include <vendorcode/amd/agesa/f15tn/Proc/Common/CreateStruct.h> +#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEarlyInit.h> +/* These tables are optional and may be used to adjust memory timing settings */ +#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mm.h> +#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h> + + +/* Select the CPU family. */ +#define INSTALL_FAMILY_10_SUPPORT FALSE +#define INSTALL_FAMILY_12_SUPPORT FALSE +#define INSTALL_FAMILY_14_SUPPORT FALSE +#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE + +/* Select the CPU socket type. */ +#define INSTALL_G34_SOCKET_SUPPORT FALSE +#define INSTALL_C32_SOCKET_SUPPORT FALSE +#define INSTALL_S1G3_SOCKET_SUPPORT FALSE +#define INSTALL_S1G4_SOCKET_SUPPORT FALSE +#define INSTALL_ASB2_SOCKET_SUPPORT FALSE +#define INSTALL_FS1_SOCKET_SUPPORT FALSE +#define INSTALL_FM1_SOCKET_SUPPORT FALSE +#define INSTALL_FP2_SOCKET_SUPPORT FALSE +#define INSTALL_FT1_SOCKET_SUPPORT FALSE +#define INSTALL_AM3_SOCKET_SUPPORT FALSE + +#define INSTALL_FM2_SOCKET_SUPPORT TRUE + +//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_SODIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_ECC_SUPPORT TRUE +//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE +//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE +#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE +#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE +#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE +//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE +#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE +//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE +#define BLDOPT_REMOVE_SRAT FALSE //TRUE +#define BLDOPT_REMOVE_SLIT FALSE //TRUE +#define BLDOPT_REMOVE_WHEA FALSE //TRUE +#define BLDOPT_REMOVE_CRAT TRUE +#define BLDOPT_REMOVE_DMI TRUE +//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE + +//This element selects whether P-States should be forced to be independent, +// as reported by the ACPI _PSD object. For single-link processors, +// setting TRUE for OS to support this feature. + +//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE + +#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS +#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER +/* Build configuration values here. + */ +#define BLDCFG_VRM_CURRENT_LIMIT 90000 +#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0 +#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 0 +#define BLDCFG_PLAT_NUM_IO_APICS 3 +#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST +#define BLDCFG_MEM_INIT_PSTATE 0 + +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE + +#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY +#define BLDCFG_MEMORY_MODE_UNGANGED TRUE +#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE +#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE +#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE +#define BLDCFG_MEMORY_POWER_DOWN TRUE +#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT +#define BLDCFG_ONLINE_SPARE FALSE +#define BLDCFG_BANK_SWIZZLE TRUE +#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO +#define BLDCFG_MEMORY_CLOCK_SELECT DDR1600_FREQUENCY +#define BLDCFG_DQS_TRAINING_CONTROL TRUE +#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE +#define BLDCFG_USE_BURST_MODE FALSE +#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE +#define BLDCFG_ENABLE_ECC_FEATURE FALSE +#define BLDCFG_ECC_REDIRECTION FALSE +#define BLDCFG_SCRUB_DRAM_RATE 0 +#define BLDCFG_SCRUB_L2_RATE 0 +#define BLDCFG_SCRUB_L3_RATE 0 +#define BLDCFG_SCRUB_IC_RATE 0 +#define BLDCFG_SCRUB_DC_RATE 0 +#define BLDCFG_ECC_SYMBOL_SIZE 4 +#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 +#define BLDCFG_ECC_SYNC_FLOOD FALSE +#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE +#define BLDCFG_1GB_ALIGN FALSE +#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE +#define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 // PCIE Spread Spectrum default value 0.36% +#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 + +#define BLDOPT_REMOVE_ALIB FALSE +#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto +#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P' +#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' +#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 + +#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 200 +#define BLDCFG_CFG_ABM_SUPPORT 0 + +//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770 + +// Specify the default values for the VRM controlling the VDDNB plane. +// If not specified, the values used for the core VRM will be applied +//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 // Not currently used on Trinity +//#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L +//#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in calculating the VSRampSlamTime +//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 // Not currently used on Trinity +//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE 0 // Not currently used on Trinity +//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 // Not currently used on Trinity + +#define BLDCFG_VRM_NB_CURRENT_LIMIT 60000 + +#define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3 +#define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3 + +#if IS_ENABLED(CONFIG_GFXUMA) +#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED +#define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED +//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/ +#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M +#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE +#endif + +#define BLDCFG_IOMMU_SUPPORT TRUE + +#define BLDCFG_CFG_GNB_HD_AUDIO TRUE +//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID +//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID +//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID + +/* Process the options... + * This file include MUST occur AFTER the user option selection settings + */ +/* + * Customized OEM build configurations for FCH component + */ +// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00 +// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20 +// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00 +// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400 +// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404 +// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408 +// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410 +// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420 +// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000 +// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000 +// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000 +// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0 +// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00 +// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000 +// #define BLDCFG_AZALIA_SSID 0x780D1022 +// #define BLDCFG_SMBUS_SSID 0x780B1022 +// #define BLDCFG_IDE_SSID 0x780C1022 +// #define BLDCFG_SATA_AHCI_SSID 0x78011022 +// #define BLDCFG_SATA_IDE_SSID 0x78001022 +// #define BLDCFG_SATA_RAID5_SSID 0x78031022 +// #define BLDCFG_SATA_RAID_SSID 0x78021022 +// #define BLDCFG_EHCI_SSID 0x78081022 +// #define BLDCFG_OHCI_SSID 0x78071022 +// #define BLDCFG_LPC_SSID 0x780E1022 +// #define BLDCFG_SD_SSID 0x78061022 +// #define BLDCFG_XHCI_SSID 0x78121022 +// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE +// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE +// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4 +// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE +// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE +// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE +// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE +// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE +// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE +// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE +// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE + +CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = +{ + { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E }, + { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E }, + { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 }, + { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 }, + { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 }, + { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 }, + { CPU_LIST_TERMINAL } +}; + +#define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList + + // This is the delivery package title, "BrazosPI" + // This string MUST be exactly 8 characters long +#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} + + // This is the release version number of the AGESA component + // This string MUST be exactly 12 characters long +#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} + +/* MEMORY_BUS_SPEED */ +#define DDR400_FREQUENCY 200 ///< DDR 400 +#define DDR533_FREQUENCY 266 ///< DDR 533 +#define DDR667_FREQUENCY 333 ///< DDR 667 +#define DDR800_FREQUENCY 400 ///< DDR 800 +#define DDR1066_FREQUENCY 533 ///< DDR 1066 +#define DDR1333_FREQUENCY 667 ///< DDR 1333 +#define DDR1600_FREQUENCY 800 ///< DDR 1600 +#define DDR1866_FREQUENCY 933 ///< DDR 1866 +#define DDR2100_FREQUENCY 1050 ///< DDR 2100 +#define DDR2133_FREQUENCY 1066 ///< DDR 2133 +#define DDR2400_FREQUENCY 1200 ///< DDR 2400 +#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency + +/* QUANDRANK_TYPE*/ +#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM +#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM + +/* USER_MEMORY_TIMING_MODE */ +#define TIMING_MODE_AUTO 0 ///< Use best rate possible +#define TIMING_MODE_LIMITED 1 ///< Set user top limit +#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed + +/* POWER_DOWN_MODE */ +#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode +#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode + +/* + * Agesa optional capabilities selection. + * Uncomment and mark FALSE those features you wish to include in the build. + * Comment out or mark TRUE those features you want to REMOVE from the build. + */ + +#define DFLT_SMBUS0_BASE_ADDRESS 0xB00 +#define DFLT_SMBUS1_BASE_ADDRESS 0xB20 +/* The AGESA likes to enable 512 bytes region on this base for LPC bus */ +#define DFLT_SIO_PME_BASE_ADDRESS 0xE00 +#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800 +#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804 +#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808 +#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810 +#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820 +#define DFLT_SPI_BASE_ADDRESS 0xFEC10000 +#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 +#define DFLT_HPET_BASE_ADDRESS 0xFED00000 +#define DFLT_SMI_CMD_PORT 0xB0 +#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 +#define DFLT_GEC_BASE_ADDRESS 0xFED61000 +#define DFLT_AZALIA_SSID 0x780D1022 +#define DFLT_SMBUS_SSID 0x780B1022 +#define DFLT_IDE_SSID 0x780C1022 +#define DFLT_SATA_AHCI_SSID 0x78011022 +#define DFLT_SATA_IDE_SSID 0x78001022 +#define DFLT_SATA_RAID5_SSID 0x78031022 +#define DFLT_SATA_RAID_SSID 0x78021022 +#define DFLT_EHCI_SSID 0x78081022 +#define DFLT_OHCI_SSID 0x78071022 +#define DFLT_LPC_SSID 0x780E1022 +#define DFLT_SD_SSID 0x78061022 +#define DFLT_XHCI_SSID 0x78121022 +#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE +#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE +#define DFLT_FCH_GPP_LINK_CONFIG PortA1B1C1D1 +#define DFLT_FCH_GPP_PORT0_PRESENT TRUE +#define DFLT_FCH_GPP_PORT1_PRESENT TRUE +#define DFLT_FCH_GPP_PORT2_PRESENT FALSE +#define DFLT_FCH_GPP_PORT3_PRESENT FALSE +#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE +//#define BLDCFG_IR_PIN_CONTROL 0x33 +//#define FCH_NO_XHCI_SUPPORT FALSE +GPIO_CONTROL a88xm_e_gpio[] = { +// {183, Function1, PullUpB}, + {-1} +}; +#define BLDCFG_FCH_GPIO_CONTROL_LIST (&a88xm_e_gpio[0]) + +// The following definitions specify the default values for various parameters in which there are +// no clearly defined defaults to be used in the common file. The values below are based on product +// and BKDG content, please consult the AGESA Memory team for consultation. +#define DFLT_SCRUB_DRAM_RATE (0) +#define DFLT_SCRUB_L2_RATE (0) +#define DFLT_SCRUB_L3_RATE (0) +#define DFLT_SCRUB_IC_RATE (0) +#define DFLT_SCRUB_DC_RATE (0) +#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define DFLT_VRM_SLEW_RATE (5000) + +/* Moving this include up will break AGESA. */ +#include <PlatformInstall.h> diff --git a/src/mainboard/asus/a88xm-e/cmos.layout b/src/mainboard/asus/a88xm-e/cmos.layout new file mode 100644 index 0000000..e1dbd9a --- /dev/null +++ b/src/mainboard/asus/a88xm-e/cmos.layout @@ -0,0 +1,66 @@ +#***************************************************************************** +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +#***************************************************************************** + +entries + +0 384 r 0 reserved_memory +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#392 3 r 0 unused +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +456 1 e 1 ECC_memory +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 diff --git a/src/mainboard/asus/a88xm-e/devicetree_a88xm-e.cb b/src/mainboard/asus/a88xm-e/devicetree_a88xm-e.cb new file mode 100644 index 0000000..e2b0eea --- /dev/null +++ b/src/mainboard/asus/a88xm-e/devicetree_a88xm-e.cb @@ -0,0 +1,143 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +chip northbridge/amd/agesa/family15tn/root_complex + + device cpu_cluster 0 on + chip cpu/amd/agesa/family15tn + device lapic 10 on end + end + end + + device domain 0 on + subsystemid 0x1022 0x1410 inherit + chip northbridge/amd/agesa/family15tn # CPU side of HT root complex + + chip northbridge/amd/agesa/family15tn # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 0.2 on end # IOMMU + device pci 1.0 on end # Internal Graphics + device pci 1.1 on end # Internal Audio (iGPU) + device pci 2.0 on end # PCIE x4/x16 yellow (?) + device pci 3.0 on end # unused? + device pci 4.0 on end # PCIE x4/x16 yellow (?) + device pci 5.0 off end # unused + device pci 6.0 off end # unused? + device pci 7.0 off end # LAN + device pci 8.0 off end # NB/SB Link P2P bridge + end #chip northbridge/amd/agesa/family15tn # PCI side of HT root complex + + chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus + device pci 10.0 on end # XHCI HC0 + device pci 10.1 on end # XHCI HC1 + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SMBUS + chip drivers/generic/generic #dimm 0 + device i2c 50 on end # 7-bit SPD address + end + chip drivers/generic/generic #dimm 1 + device i2c 51 on end # 7-bit SPD address + end + end # SM + device pci 14.1 off end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/ite/it8728f + register "TMPIN1.mode" = "THERMAL_RESISTOR" + register "TMPIN2.mode" = "THERMAL_RESISTOR" + register "TMPIN3.mode" = "THERMAL_RESISTOR" + + register "FAN1.mode" = "FAN_SMART_AUTOMATIC" + register "FAN1.smart.tmpin" = "1" + register "FAN1.smart.tmp_off" = "0x80" # never + register "FAN1.smart.tmp_start" = "20" + register "FAN1.smart.tmp_full" = "70" + register "FAN1.smart.tmp_delta" = "0" + register "FAN1.smart.smoothing" = "1" + register "FAN1.smart.pwm_start" = "20" + register "FAN1.smart.slope" = "32" + + # Enable tacho reading for chassis fan. + register "FAN2.mode" = "FAN_MODE_OFF" + + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.4 on # Env Controller + io 0x60 = 0x290 + io 0x62 = 0x220 + irq 0x70 = 0 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 off # Mouse + irq 0x70 = 12 + end + device pnp 2e.7 on # GPIO + io 0x60 = 0x228 #SMI + io 0x62 = 0x300 #Simple I/O + io 0x64 = 0x238 #Phony resource IT8603E does not have it + irq 0x70 = 0 + end + device pnp 2e.a off end # CIR + end #superio/ite/it8728f + end # + device pci 14.3 off end # LPC + device pci 14.4 on end # PCI 0x4384 + device pci 14.5 off end # USB 2 + device pci 14.6 off end # Gec + device pci 14.7 off end # SD + device pci 15.0 on end # PCIe 0 - onboard PCIe 1x + device pci 15.1 off end # unused + device pci 15.2 on end # PCI bridge + device pci 15.3 off end # unused + end #chip southbridge/amd/agesa/hudson + + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + + register "spdAddrLookup" = " + { + { {0xA0, 0x00}, {0xA2, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses + { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses + }" + + end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex + end #domain +end #chip northbridge/amd/agesa/family15tn/root_complex diff --git a/src/mainboard/asus/a88xm-e/dsdt.asl b/src/mainboard/asus/a88xm-e/dsdt.asl new file mode 100644 index 0000000..45a2606 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/dsdt.asl @@ -0,0 +1,110 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* DefinitionBlock Statement */ +#include <arch/acpi.h> +DefinitionBlock ( + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x00010001 /* OEM Revision */ + ) +{ /* Start of ASL file */ + /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ + + /* Globals for the platform */ + #include "acpi/mainboard.asl" + + /* Describe the USB Overcurrent pins */ + #include "acpi/usb_oc.asl" + + /* PCI IRQ mapping for the Southbridge */ + #include <southbridge/amd/agesa/hudson/acpi/pcie.asl> + + /* Describe the processor tree (\_PR) */ + #include <cpu/amd/agesa/family15tn/acpi/cpu.asl> + + /* Describe the supported Sleep States for this Southbridge */ + #include <southbridge/amd/common/acpi/sleepstates.asl> + + /* Describe the Sleep Methods (WAK, PTS, GTS, etc.) for this platform */ + #include "acpi/sleep.asl" + + Scope(\_SB) { + /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> + + /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ + #include "acpi/routing.asl" + + Device(PWRB) { + Name(_HID, EISAID("PNP0C0C")) + Name(_UID, 0xAA) + Name(_PRW, Package () {3, 0x04}) + Name(_STA, 0x0B) + } + + Device(PCI0) { + /* Describe the AMD Northbridge */ + #include <northbridge/amd/agesa/family15tn/acpi/northbridge.asl> + + /* Describe the AMD Fusion Controller Hub Southbridge */ + #include <southbridge/amd/agesa/hudson/acpi/fch.asl> + + /** + * TODO: The devices listed here (SBR0 and SBR1) do not appear to + * be referenced anywhere and could possibly be removed. + */ + Device(SBR0) { /* PCIe 1x SB */ + Name(_ADR, 0x00150000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(ABR0) } /* APIC mode */ + Return (PBR0) /* PIC mode */ + } + } + + Device(SBR1) { /* Onboard network */ + Name(_ADR, 0x00150001) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT, 0) { + If(PMOD){ Return(ABR1) } /* APIC mode */ + Return (PBR1) /* PIC mode */ + } + } + } + + /* Describe PCI INT[A-H] for the Southbridge */ + #include <southbridge/amd/agesa/hudson/acpi/pci_int.asl> + + } /* End Scope(_SB) */ + + /* Describe SMBUS for the Southbridge */ + #include <southbridge/amd/agesa/hudson/acpi/smbus.asl> + + /* Define the General Purpose Events for the platform */ + #include "acpi/gpe.asl" + + /* Define the Thermal zones and methods for the platform */ + #include "acpi/thermal.asl" + + /* Define the System Indicators for the platform */ + #include "acpi/si.asl" + +} +/* End of ASL file */ diff --git a/src/mainboard/asus/a88xm-e/irq_tables.c b/src/mainboard/asus/a88xm-e/irq_tables.c new file mode 100644 index 0000000..88d2160 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/irq_tables.c @@ -0,0 +1,101 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/pirq_routing.h> +#include <console/console.h> +#include <device/pci_def.h> +#include <stdint.h> +#include <string.h> + +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, + u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, + u8 slot, u8 rfu) +{ + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; +} + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + struct irq_routing_table *pirq; + struct irq_info *pirq_info; + u32 slot_num; + u8 *v; + + u8 sum = 0; + int i; + + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15; + + /* This table must be between 0xf0000 & 0x100000 */ + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); + + pirq = (void *)(addr); + v = (u8 *) (addr); + + pirq->signature = PIRQ_SIGNATURE; + pirq->version = PIRQ_VERSION; + + pirq->rtr_bus = 0; + pirq->rtr_devfn = PCI_DEVFN(0x14, 4); + + pirq->exclusive_irqs = 0; + + pirq->rtr_vendor = 0x1002; + pirq->rtr_device = 0x4384; + + pirq->miniport_data = 0; + + memset(pirq->rfu, 0, sizeof(pirq->rfu)); + + pirq_info = (void *)(&pirq->checksum + 1); + slot_num = 0; + + /* pci bridge */ + write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), + 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, + 0); + pirq_info++; + + slot_num++; + + pirq->size = 32 + 16 * slot_num; + + for (i = 0; i < pirq->size; i++) + sum += v[i]; + + sum = pirq->checksum - sum; + + if (sum != pirq->checksum) { + pirq->checksum = sum; + } + + printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + + return (unsigned long)pirq_info; +} diff --git a/src/mainboard/asus/a88xm-e/mainboard.c b/src/mainboard/asus/a88xm-e/mainboard.c new file mode 100644 index 0000000..2a0e618 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/mainboard.c @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/msr.h> +#include <device/device.h> + +/************************************************* + * enable the dedicated function in thatcher board. + *************************************************/ +static void mainboard_enable(struct device *dev) +{ + msr_t msr; + + printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + + msr = rdmsr(LS_CFG_MSR); + msr.lo &= ~(1 << 28); + wrmsr(LS_CFG_MSR, msr); + + msr = rdmsr(DC_CFG_MSR); + msr.lo &= ~(1 << 4); + msr.lo &= ~(1 << 13); + wrmsr(DC_CFG_MSR, msr); + + msr = rdmsr(BU_CFG_MSR); + msr.lo &= ~(1 << 23); + wrmsr(BU_CFG_MSR, msr); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/asus/a88xm-e/mptable.c b/src/mainboard/asus/a88xm-e/mptable.c new file mode 100644 index 0000000..d97663d --- /dev/null +++ b/src/mainboard/asus/a88xm-e/mptable.c @@ -0,0 +1,181 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <arch/ioapic.h> +#include <arch/smp/mpspec.h> +#include <cpu/x86/lapic.h> +#include <device/pci.h> +#include <stdint.h> +#include <string.h> +#include <southbridge/amd/agesa/hudson/hudson.h> + +u8 picr_data[] = { + 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + 0x09,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x1F,0x1F,0x1F,0x1F +}; +u8 intr_data[0x54] = { + 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x10,0x11,0x12,0x13 +}; + +static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length) +{ + mc->mpc_length += length; + mc->mpc_entry_count++; +} + +static void my_smp_write_bus(struct mp_config_table *mc, + unsigned char id, const char *bustype) +{ + struct mpc_config_bus *mpc; + mpc = smp_next_mpc_entry(mc); + memset(mpc, '\0', sizeof(*mpc)); + mpc->mpc_type = MP_BUS; + mpc->mpc_busid = id; + memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); + smp_add_mpc_entry(mc, sizeof(*mpc)); +} + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + int bus_isa; + u8 byte; + + /* + * By the time this function gets called, the IOAPIC registers + * have been written so they can be read to get the correct + * APIC ID and Version + */ + u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); + u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LOCAL_APIC_ADDR); + memcpy(mc->mpc_oem, "AMD ", 8); + + smp_write_processors(mc); + + //mptable_write_buses(mc, NULL, &bus_isa); + my_smp_write_bus(mc, 0, "PCI "); + my_smp_write_bus(mc, 1, "PCI "); + bus_isa = 0x02; + my_smp_write_bus(mc, bus_isa, "ISA "); + + /* I/O APICs: APIC ID Version State Address */ + smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); + + /* PIC IRQ routine */ + for (byte = 0x0; byte < sizeof(picr_data); byte ++) { + outb(byte, 0xC00); + outb(picr_data[byte], 0xC01); + } + + /* APIC IRQ routine */ + for (byte = 0x0; byte < sizeof(intr_data); byte ++) { + outb(byte | 0x80, 0xC00); + outb(intr_data[byte], 0xC01); + } + + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ +#define IO_LOCAL_INT(type, intr, apicid, pin) \ + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); + + /* PCI interrupts are level triggered, and are + * associated with a specific bus/device/function tuple. + */ +#define PCI_INT(bus, dev, int_sign, pin) \ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) + + /* IOMMU */ + PCI_INT(0x0, 0x0, 0x0, 0x10); + PCI_INT(0x0, 0x0, 0x1, 0x11); + PCI_INT(0x0, 0x0, 0x2, 0x12); + PCI_INT(0x0, 0x0, 0x3, 0x13); + + /* Internal VGA */ + PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); + PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); + + /* SMBUS */ + PCI_INT(0x0, 0x14, 0x0, 0x10); + + /* HD Audio */ + PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]); + + /* USB */ + PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); + PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); + PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); + PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); + PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); + PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); + PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]); + + /* sata */ + PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]); + PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); + + /* on board NIC & Slot PCIE. */ + + /* PCI slots */ + struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + if (dev && dev->enabled) { + u8 bus_pci = dev->link_list->secondary; + /* PCI_SLOT 0. */ + PCI_INT(bus_pci, 0x5, 0x0, 0x14); + PCI_INT(bus_pci, 0x5, 0x1, 0x15); + PCI_INT(bus_pci, 0x5, 0x2, 0x16); + PCI_INT(bus_pci, 0x5, 0x3, 0x17); + } + + /* PCIe Lan*/ + PCI_INT(0x0, 0x06, 0x0, 0x13); + + /* FCH PCIe PortA */ + PCI_INT(0x0, 0x15, 0x0, 0x10); + /* FCH PCIe PortB */ + PCI_INT(0x0, 0x15, 0x1, 0x11); + /* FCH PCIe PortC */ + PCI_INT(0x0, 0x15, 0x2, 0x12); + /* FCH PCIe PortD */ + PCI_INT(0x0, 0x15, 0x3, 0x13); + + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); + IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); + /* There is no extension information... */ + + /* Compute the checksums */ + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/asus/a88xm-e/romstage.c b/src/mainboard/asus/a88xm-e/romstage.c new file mode 100644 index 0000000..0a85c27 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/romstage.c @@ -0,0 +1,102 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2012 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> + +#include <northbridge/amd/agesa/state_machine.h> +#include <southbridge/amd/common/amd_defs.h> +#include <southbridge/amd/agesa/hudson/hudson.h> +#include <southbridge/amd/agesa/hudson/smbus.h> +#include <stdint.h> +#include <string.h> + +#include <superio/ite/common/ite.h> +#include <superio/ite/it8728f/it8728f.h> + +#define MMIO_NON_POSTED_START 0xfed00000 +#define MMIO_NON_POSTED_END 0xfedfffff +#define SB_MMIO_MISC32(x) *(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR + 0xE00 + (x)) + +static void sbxxx_enable_48mhzout(void) +{ + /* most likely programming to 48MHz out signal */ + u32 reg32; + reg32 = SB_MMIO_MISC32(0x28); + reg32 &= 0xffc7ffff; + reg32 |= 0x00100000; + SB_MMIO_MISC32(0x28) = reg32; + + reg32 = SB_MMIO_MISC32(0x40); + reg32 &= ~0x80u; + SB_MMIO_MISC32(0x40) = reg32; +} + +static void superio_init_e(void) +{ + pnp_devfn_t uart = PNP_DEV(0x2e, IT8728F_SP1); + pnp_devfn_t gpio = PNP_DEV(0x2e, IT8728F_GPIO); + + ite_kill_watchdog(gpio); + ite_enable_serial(uart, CONFIG_TTYS0_BASE); + ite_enable_3vsbsw(gpio); +} + +void board_BeforeAgesa(struct sysinfo *cb) +{ + u8 byte; + pci_devfn_t dev; + + if (IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE)) + hudson_pci_port80(); + else if (IS_ENABLED(CONFIG_POST_DEVICE_LPC)) + hudson_lpc_port80(); + + /* enable SIO LPC decode */ + dev = PCI_DEV(0, 0x14, 3); + byte = pci_read_config8(dev, 0x48); + byte |= 3; /* 2e, 2f */ + pci_write_config8(dev, 0x48, byte); + + /* enable serial decode */ + byte = pci_read_config8(dev, 0x44); + byte |= (1 << 6); /* 0x3f8 */ + pci_write_config8(dev, 0x44, byte); + + post_code(0x30); + + /* enable SB MMIO space */ + outb(0x24, 0xcd6); + outb(0x1, 0xcd7); + + /* enable SIO clock */ + sbxxx_enable_48mhzout(); + + if (IS_ENABLED(CONFIG_BOARD_ASUS_A88XM_E)) + superio_init_e(); + + /* turn on secondary smbus at b20 */ + outb(0x28, 0xcd6); + byte = inb(0xcd7); + byte |= 1; + outb(byte, 0xcd7); + + /* set DDR3 voltage */ + byte = CONFIG_BOARD_ASUS_A88XM_E_DDR3_VOLT_VAL; + + /* default is byte = 0x0, so no need to set it in this case */ + if (byte) + do_smbus_write_byte(0xb20, 0x15, 0x3, byte); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/30987 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60fa0636ba41f5f1a6a3faa2764bf2f0a968cf90 Gerrit-Change-Number: 30987 Gerrit-PatchSet: 1 Gerrit-Owner: Balázs Vinarz <vinibali1(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: configs: add Lenovo G505S sample configuration (use with dGPU patches)

by mikeb mikeb (Code Review)

Hello Mike Banon, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/32352 to review the following change. Change subject: configs: add Lenovo G505S sample configuration (use with dGPU patches) ...................................................................... configs: add Lenovo G505S sample configuration (use with dGPU patches) This sample .config could not be merged before the dGPU patches at CB:31929 (see https://review.coreboot.org/c/coreboot/+/31929 for more information). I'm sharing it with you here partially for the archival purposes. After you have installed the dGPU patches above, you can use this .config as the base configuration for your G505S by saving it to ./coreboot/.config - however, you may want to change some of its' configs! For example: it specifies CONFIG_VGA_BIOS_DGPU_FILE="pci1002,6665.rom" CONFIG_VGA_BIOS_DGPU_ID="1002,6665" which is compatible with R5-M230 discrete GPU, but if your G505S has HD-8570M discrete GPU instead - you will need to change these configs to ",6663" etc. Or, if your G505S does not have a discrete GPU at all, please disable CONFIG_MULTIPLE_VGA_ADAPTERS=y and those DGPU configs will be disabled. Also, if you are using a SSD - you may want to change the "CONFIG_HUDSON_SATA_MODE" from "0: NATIVE" to "2: AHCI". In addition, I've disabled this WiFi adapter at my .config to save some space: If you have any questions/suggestions regarding this .config, please contact me. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I85f17395afca52ef690f24fcef746d74bb72aab7 --- A configs/config.lenovo_g505s_use_with_dgpu_patches 1 file changed, 746 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/32352/1 diff --git a/configs/config.lenovo_g505s_use_with_dgpu_patches b/configs/config.lenovo_g505s_use_with_dgpu_patches new file mode 100644 index 0000000..5ff218f --- /dev/null +++ b/configs/config.lenovo_g505s_use_with_dgpu_patches @@ -0,0 +1,746 @@ +# +# ./coreboot/.config for Lenovo G505S - 17 April 2019 +# +### +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_COREBOOT_BUILD=y +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set +# CONFIG_USE_OPTION_TABLE is not set +CONFIG_COMPRESS_RAMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_COLLECT_TIMESTAMPS=y +# CONFIG_TIMESTAMPS_ON_CONSOLE is not set +# CONFIG_USE_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_UBSAN is not set +# CONFIG_NO_RELOCATABLE_RAMSTAGE is not set +CONFIG_RELOCATABLE_RAMSTAGE=y +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_BOOTSPLASH_IMAGE is not set + +# +# Mainboard +# + +# +# Important: Run 'make distclean' before switching boards +# +# CONFIG_VENDOR_ADI is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_ADVANSUS is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_AVALUE is not set +# CONFIG_VENDOR_BAP is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_CAVIUM is not set +# CONFIG_VENDOR_COMPULAB is not set +# CONFIG_VENDOR_CUBIETECH is not set +# CONFIG_VENDOR_ELMEX is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_FACEBOOK is not set +# CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GIZMOSPHERE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IEI is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_KONTRON is not set +CONFIG_VENDOR_LENOVO=y +# CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_OCP is not set +# CONFIG_VENDOR_OPENCELLULAR is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set +# CONFIG_VENDOR_SCALEWAY is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SIFIVE is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_TYAN is not set +# CONFIG_VENDOR_VIA is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_DIR="lenovo/g505s" +CONFIG_MAINBOARD_PART_NUMBER="LENOVO G505S" +CONFIG_MAX_CPUS=4 +CONFIG_CBFS_SIZE=0x400000 +CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/config_seabios" +CONFIG_MAINBOARD_VENDOR="LENOVO" +CONFIG_HW_MEM_HOLE_SIZEK=0x200000 +CONFIG_VGA_BIOS_ID="1002,990b" +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +# CONFIG_HUDSON_LEGACY_FREE is not set +CONFIG_DIMM_SPD_SIZE=256 +CONFIG_VGA_BIOS=y +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +CONFIG_VGA_BIOS_FILE="pci1002,990b.rom" +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="LENOVO" +CONFIG_DEVICETREE="devicetree.cb" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 +# CONFIG_HUDSON_XHCI_FWM is not set +CONFIG_POST_IO=y +CONFIG_DCACHE_RAM_BASE=0x30000 +CONFIG_DCACHE_RAM_SIZE=0x10000 +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_OVERRIDE_DEVICETREE="" +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +CONFIG_FMDFILE="" +CONFIG_MMCONF_BASE_ADDRESS=0xF8000000 +CONFIG_POST_DEVICE=y +# CONFIG_DRIVERS_UART_8250IO is not set +# CONFIG_VBOOT is not set +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="LENOVO G505S" +CONFIG_BOARD_LENOVO_G505S=y +# CONFIG_BOARD_LENOVO_L520 is not set +# CONFIG_BOARD_LENOVO_S230U is not set +# CONFIG_BOARD_LENOVO_T400 is not set +# CONFIG_BOARD_LENOVO_T500 is not set +# CONFIG_BOARD_LENOVO_R400 is not set +# CONFIG_BOARD_LENOVO_W500 is not set +# CONFIG_BOARD_LENOVO_T420 is not set +# CONFIG_BOARD_LENOVO_T420S is not set +# CONFIG_BOARD_LENOVO_THINKPAD_T430 is not set +# CONFIG_BOARD_LENOVO_T430S is not set +# CONFIG_BOARD_LENOVO_T431S is not set +# CONFIG_BOARD_LENOVO_T520 is not set +# CONFIG_BOARD_LENOVO_W520 is not set +# CONFIG_BOARD_LENOVO_T530 is not set +# CONFIG_BOARD_LENOVO_W530 is not set +# CONFIG_BOARD_LENOVO_T60 is not set +# CONFIG_BOARD_LENOVO_THINKCENTRE_A58 is not set +# CONFIG_BOARD_LENOVO_X131E is not set +# CONFIG_BOARD_LENOVO_X1_CARBON_GEN1 is not set +# CONFIG_BOARD_LENOVO_X200 is not set +# CONFIG_BOARD_LENOVO_X201 is not set +# CONFIG_BOARD_LENOVO_X220 is not set +# CONFIG_BOARD_LENOVO_X220I is not set +# CONFIG_BOARD_LENOVO_X1 is not set +# CONFIG_BOARD_LENOVO_X230 is not set +# CONFIG_BOARD_LENOVO_X60 is not set +# CONFIG_BOARD_LENOVO_Z61T is not set +# CONFIG_BOARD_LENOVO_BASEBOARD_T520 is not set +# CONFIG_BOARD_LENOVO_BASEBOARD_T530 is not set +CONFIG_CPU_ADDR_BITS=48 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 +# CONFIG_USBDEBUG is not set +CONFIG_MAINBOARD_VERSION="1.0" +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_SMBIOS_ENCLOSURE_TYPE=0x09 +CONFIG_HEAP_SIZE=0xc0000 +CONFIG_BOARD_ROMSIZE_KB_4096=y +# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +CONFIG_COREBOOT_ROMSIZE_KB_4096=y +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=4096 +CONFIG_ROM_SIZE=0x400000 +CONFIG_SYSTEM_TYPE_LAPTOP=y +# CONFIG_SYSTEM_TYPE_TABLET is not set +# CONFIG_SYSTEM_TYPE_DETACHABLE is not set +# CONFIG_SYSTEM_TYPE_CONVERTIBLE is not set +# CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set + +# +# Chipset +# + +# +# SoC +# +CONFIG_UDELAY_LAPIC_FIXED_FSB=200 +CONFIG_MMCONF_BUS_NUMBER=64 +CONFIG_S3_VGA_ROM_RUN=y +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_ACPI_CPU_STRING="\\_PR.CP%02d" +# CONFIG_SOC_CAVIUM_CN81XX is not set +CONFIG_ARCH_ARMV8_EXTENSION=0 +CONFIG_STACK_SIZE=0x1000 +# CONFIG_SOC_CAVIUM_COMMON is not set +# CONFIG_SOC_INTEL_GLK is not set +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_COMMON_CLOCK=y +CONFIG_PCIEXP_CLK_PM=y +CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/amd/agesa/hudson/bootblock.c" +# CONFIG_SOC_INTEL_COMMON_CANNONLAKE_BASE is not set +# CONFIG_SOC_INTEL_COFFEELAKE is not set +# CONFIG_SOC_INTEL_WHISKEYLAKE is not set +# CONFIG_SOC_INTEL_COMETLAKE is not set +# CONFIG_SOC_INTEL_CANNONLAKE_PCH_H is not set +CONFIG_CONSOLE_CBMEM=y +CONFIG_UART_PCI_ADDR=0x0 +# CONFIG_SOC_INTEL_KABYLAKE is not set +# CONFIG_SOC_MEDIATEK_MT8173 is not set +# CONFIG_SOC_MEDIATEK_MT8183 is not set +# CONFIG_SOC_NVIDIA_TEGRA124 is not set +# CONFIG_SOC_NVIDIA_TEGRA210 is not set +# CONFIG_SOC_QC_IPQ40XX is not set +# CONFIG_SOC_QC_IPQ806X is not set +# CONFIG_SOC_QUALCOMM_QCS405 is not set +# CONFIG_SOC_QUALCOMM_SDM845 is not set +# CONFIG_SOC_ROCKCHIP_RK3288 is not set +# CONFIG_SOC_ROCKCHIP_RK3399 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set +# CONFIG_SOC_UCB_RISCV is not set + +# +# CPU +# +# CONFIG_CPU_ALLWINNER_A10 is not set +CONFIG_XIP_ROM_SIZE=0x100000 +CONFIG_NUM_IPI_STARTS=2 +CONFIG_CPU_AMD_AGESA=y +# CONFIG_ENABLE_MRC_CACHE is not set +CONFIG_S3_DATA_POS=0xFFFF0000 +CONFIG_S3_DATA_SIZE=32768 +CONFIG_CPU_AMD_AGESA_FAMILY15_TN=y +# CONFIG_CPU_AMD_PI is not set +# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +# CONFIG_SSE2 is not set +# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set +# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +# CONFIG_CPU_TI_AM335X is not set +# CONFIG_PARALLEL_CPU_INIT is not set +# CONFIG_PARALLEL_MP is not set +# CONFIG_UDELAY_IO is not set +CONFIG_UDELAY_LAPIC=y +CONFIG_LAPIC_MONOTONIC_TIMER=y +# CONFIG_UDELAY_TSC is not set +# CONFIG_UDELAY_TIMER2 is not set +CONFIG_TSC_SYNC_LFENCE=y +# CONFIG_TSC_SYNC_MFENCE is not set +# CONFIG_NO_FIXED_XIP_ROM_SIZE is not set +CONFIG_LOGICAL_CPUS=y +# CONFIG_SMM_TSEG is not set +# CONFIG_SMM_LAPIC_REMAP_MITIGATION is not set +# CONFIG_SERIALIZED_SMM_INITIALIZATION is not set +CONFIG_X86_AMD_FIXED_MTRRS=y +# CONFIG_PLATFORM_USES_FSP1_0 is not set +# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +# CONFIG_SOC_SETS_MSRS is not set +CONFIG_CACHE_AS_RAM=y +CONFIG_NO_CAR_GLOBAL_MIGRATION=y +CONFIG_SMP=y +# CONFIG_SUPPORT_CPU_UCODE_IN_CBFS is not set +# CONFIG_USES_MICROCODE_HEADER_FILES is not set + +# +# Northbridge +# +CONFIG_NORTHBRIDGE_AMD_AGESA=y +# CONFIG_CONSOLE_VGA_MULTI is not set +CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN=y +# CONFIG_NORTHBRIDGE_AMD_PI is not set +CONFIG_MAX_PIRQ_LINKS=4 + +# +# Southbridge +# +CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON=y +CONFIG_SOUTHBRIDGE_SPECIFIC_OPTIONS=y +# CONFIG_HUDSON_XHCI_ENABLE is not set +# CONFIG_HUDSON_IMC_ENABLE is not set +# CONFIG_HUDSON_GEC_FWM is not set +CONFIG_HUDSON_SATA_MODE=0 + +# +# NATIVE +# +CONFIG_ACPI_ENABLE_THERMAL_ZONE=y +# CONFIG_AMD_SB_CIMX is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ is not set +# CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM is not set +# CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE is not set + +# +# Super I/O +# +# CONFIG_SUPERIO_NUVOTON_NCT6776_COM_A is not set + +# +# Embedded Controllers +# +CONFIG_EC_COMPAL_ENE932=y +# CONFIG_EC_GOOGLE_WILCO is not set +CONFIG_EC_BASE_ACPI_DATA=0x930 +CONFIG_EC_BASE_ACPI_COMMAND=0x934 +CONFIG_EC_BASE_HOST_DATA=0x940 +CONFIG_EC_BASE_HOST_COMMAND=0x944 +CONFIG_EC_BASE_PACKET=0x950 +CONFIG_SEABIOS_PS2_TIMEOUT=0 + +# +# AMD Platform Initialization +# +# CONFIG_CPU_AMD_AGESA_BINARY_PI is not set +CONFIG_CPU_AMD_AGESA_OPENSOURCE=y +# CONFIG_CAVIUM_BDK is not set +# CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_GOOGLE_SMBIOS_MAINBOARD_VERSION is not set +# CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_UDK_2015_BINDING is not set +# CONFIG_UDK_2017_BINDING is not set +CONFIG_UDK_2013_VERSION=2013 +CONFIG_UDK_2015_VERSION=2015 +CONFIG_UDK_2017_VERSION=2017 +CONFIG_UDK_VERSION=2013 +# CONFIG_USE_SIEMENS_HWILIB is not set +# CONFIG_ARCH_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARM is not set +# CONFIG_ARCH_VERSTAGE_ARM is not set +# CONFIG_ARCH_ROMSTAGE_ARM is not set +# CONFIG_ARCH_RAMSTAGE_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV4 is not set +# CONFIG_ARCH_VERSTAGE_ARMV4 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV4 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV4 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set +# CONFIG_ARCH_VERSTAGE_ARMV7 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_R is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_R is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7_R is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7_R is not set +# CONFIG_ARM_LPAE is not set +# CONFIG_ARCH_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARM64 is not set +# CONFIG_ARCH_VERSTAGE_ARM64 is not set +# CONFIG_ARCH_ROMSTAGE_ARM64 is not set +# CONFIG_ARCH_RAMSTAGE_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV8_64 is not set +# CONFIG_ARCH_VERSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV8_64 is not set +# CONFIG_ARM64_USE_ARCH_TIMER is not set +# CONFIG_ARM64_A53_ERRATUM_843419 is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_BOOTBLOCK_MIPS is not set +# CONFIG_ARCH_VERSTAGE_MIPS is not set +# CONFIG_ARCH_ROMSTAGE_MIPS is not set +# CONFIG_ARCH_RAMSTAGE_MIPS is not set +# CONFIG_ARCH_PPC64 is not set +# CONFIG_ARCH_BOOTBLOCK_PPC64 is not set +# CONFIG_ARCH_VERSTAGE_PPC64 is not set +# CONFIG_ARCH_ROMSTAGE_PPC64 is not set +# CONFIG_ARCH_RAMSTAGE_PPC64 is not set +# CONFIG_ARCH_RISCV is not set +CONFIG_ARCH_RISCV_M=y +# CONFIG_ARCH_RISCV_S is not set +# CONFIG_ARCH_RISCV_U is not set +# CONFIG_ARCH_RISCV_RV64 is not set +# CONFIG_ARCH_RISCV_RV32 is not set +# CONFIG_ARCH_RISCV_PMP is not set +# CONFIG_ARCH_BOOTBLOCK_RISCV is not set +# CONFIG_ARCH_VERSTAGE_RISCV is not set +# CONFIG_ARCH_ROMSTAGE_RISCV is not set +# CONFIG_ARCH_RAMSTAGE_RISCV is not set +# CONFIG_RISCV_USE_ARCH_TIMER is not set +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_POSTCAR_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +# CONFIG_ARCH_BOOTBLOCK_X86_64 is not set +# CONFIG_ARCH_VERSTAGE_X86_64 is not set +# CONFIG_ARCH_ROMSTAGE_X86_64 is not set +# CONFIG_ARCH_POSTCAR_X86_64 is not set +# CONFIG_ARCH_RAMSTAGE_X86_64 is not set +# CONFIG_USE_MARCH_586 is not set +# CONFIG_AP_IN_SIPI_WAIT is not set +# CONFIG_SIPI_VECTOR_IN_ROM is not set +CONFIG_RAMBASE=0xe00000 +CONFIG_RAMTOP=0x1000000 +CONFIG_CBMEM_TOP_BACKUP=y +# CONFIG_EARLY_EBDA_INIT is not set +CONFIG_PC80_SYSTEM=y +# CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set +# CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set +# CONFIG_HAVE_CMOS_DEFAULT is not set +CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y +# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set +# CONFIG_HPET_ADDRESS_OVERRIDE is not set +CONFIG_HPET_ADDRESS=0xfed00000 +CONFIG_ID_SECTION_OFFSET=0x80 +CONFIG_POSTCAR_STAGE=y +# CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set +# CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" +# CONFIG_COLLECT_TIMESTAMPS_NO_TSC is not set +CONFIG_COLLECT_TIMESTAMPS_TSC=y +# CONFIG_PAGING_IN_CACHE_AS_RAM is not set +# CONFIG_IDT_IN_EVERY_STAGE is not set +CONFIG_HAVE_CF9_RESET=y +CONFIG_HAVE_CF9_RESET_PREPARE=y + +# +# Devices +# +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_HAVE_VBE_LINEAR_FRAMEBUFFER=y +# CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT is not set +# CONFIG_MAINBOARD_HAS_LIBGFXINIT is not set +CONFIG_MAINBOARD_HAS_MULTIPLE_VGA_ADAPTERS=y +CONFIG_VGA_ROM_RUN=y +# CONFIG_NO_GFX_INIT is not set +# CONFIG_ALWAYS_LOAD_OPROM is not set +CONFIG_ON_DEVICE_ROM_LOAD=y +# CONFIG_PCI_OPTION_ROM_RUN_REALMODE is not set +CONFIG_PCI_OPTION_ROM_RUN_YABEL=y +CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES=y +# CONFIG_YABEL_PCI_FAKE_WRITING_OTHER_DEVICES_CONFIG is not set +CONFIG_YABEL_VIRTMEM_LOCATION=0x1000000 +CONFIG_YABEL_DIRECTHW=y +CONFIG_MULTIPLE_VGA_ADAPTERS=y + +# +# Display +# +CONFIG_FRAMEBUFFER_SET_VESA_MODE=y +# CONFIG_FRAMEBUFFER_VESA_MODE_100 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_101 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_102 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_103 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_104 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_105 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_106 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_107 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_108 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_109 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_10A is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_10B is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_10C is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_10D is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_10E is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_10F is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_110 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_111 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_112 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_113 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_114 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_115 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_116 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_117 is not set +CONFIG_FRAMEBUFFER_VESA_MODE_118=y +# CONFIG_FRAMEBUFFER_VESA_MODE_119 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_11A is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_11B is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_USER is not set +CONFIG_FRAMEBUFFER_VESA_MODE=0x118 +CONFIG_BOOTSPLASH=y +# CONFIG_VGA_TEXT_FRAMEBUFFER is not set +CONFIG_VBE_LINEAR_FRAMEBUFFER=y +CONFIG_LINEAR_FRAMEBUFFER=y +# CONFIG_SMBUS_HAS_AUX_CHANNELS is not set +CONFIG_PCI=y +# CONFIG_NO_MMCONF_SUPPORT is not set +CONFIG_MMCONF_SUPPORT=y +# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +# CONFIG_AZALIA_PLUGIN_SUPPORT is not set +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +CONFIG_VGA_BIOS_DGPU=y +CONFIG_VGA_BIOS_DGPU_FILE="pci1002,6665.rom" +CONFIG_VGA_BIOS_DGPU_ID="1002,6665" +# CONFIG_SOFTWARE_I2C is not set + +# +# Generic Drivers +# +# CONFIG_DRIVERS_AS3722_RTC is not set +# CONFIG_GIC is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_DRIVERS_LENOVO_WACOM is not set +# CONFIG_RT8168_GET_MAC_FROM_VPD is not set +# CONFIG_RT8168_SET_LED_MODE is not set +# CONFIG_SMMSTORE_IN_CBFS is not set +CONFIG_SPI_FLASH=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +# CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY is not set +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_AMIC=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B is not set +# CONFIG_SPI_FLASH_HAS_VOLATILE_GROUP is not set +# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +CONFIG_NO_UART_ON_SUPERIO=y +# CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set +# CONFIG_UART_OVERRIDE_REFCLK is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_DRIVERS_UART_8250MEM_32 is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +# CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +# CONFIG_VPD is not set +CONFIG_DRIVERS_AMD_PI=y +CONFIG_SMBIOS_PROVIDED_BY_MOBO=y +# CONFIG_DRIVERS_I2C_MAX98373 is not set +# CONFIG_DRIVERS_I2C_MAX98927 is not set +# CONFIG_DRIVERS_I2C_PCA9538 is not set +# CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_RT5663 is not set +# CONFIG_DRIVERS_I2C_RTD2132 is not set +# CONFIG_DRIVERS_I2C_RX6110SA is not set +# CONFIG_DRIVERS_I2C_SX9310 is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_ATMEL is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_CR50 is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_GENERIC is not set +# CONFIG_PLATFORM_USES_FSP2_0 is not set +# CONFIG_PLATFORM_USES_FSP2_1 is not set +# CONFIG_INTEL_DDI is not set +# CONFIG_INTEL_EDID is not set +# CONFIG_INTEL_INT15 is not set +# CONFIG_INTEL_GMA_ACPI is not set +# CONFIG_INTEL_GMA_SSC_ALTERNATE_REF is not set +# CONFIG_INTEL_GMA_SWSMISCI is not set +# CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_DRIVERS_INTEL_MIPI_CAMERA is not set +# CONFIG_DRIVERS_INTEL_WIFI is not set +# CONFIG_USE_SAR is not set +# CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS is not set +# CONFIG_DRIVER_MAXIM_MAX77686 is not set +# CONFIG_DRIVER_PARADE_PS8625 is not set +# CONFIG_DRIVER_PARADE_PS8640 is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_LPC_TPM is not set +# CONFIG_MAINBOARD_HAS_LPC_TPM is not set +# CONFIG_DRIVERS_RICOH_RCE822 is not set +# CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_NC_FPGA_NOTIFY_CB_READY is not set +# CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_MAINBOARD_HAS_SPI_TPM_CR50 is not set +# CONFIG_DRIVER_TI_TPS65090 is not set +# CONFIG_DRIVERS_TI_TPS65913 is not set +# CONFIG_DRIVERS_TI_TPS65913_RTC is not set +# CONFIG_DRIVERS_USB_ACPI is not set +# CONFIG_DRIVER_XPOWERS_AXP209 is not set +# CONFIG_COMMONLIB_STORAGE is not set + +# +# Security +# + +# +# Verified Boot (vboot) +# + +# +# Trusted Platform Module +# +CONFIG_USER_NO_TPM=y +# CONFIG_ACPI_SATA_GENERATOR is not set +# CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES is not set +# CONFIG_ACPI_AMD_HARDWARE_SLEEP_VALUES is not set +# CONFIG_BOOT_DEVICE_NOT_SPI_FLASH is not set +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +# CONFIG_BOOT_DEVICE_SUPPORTS_WRITES is not set +# CONFIG_RTC is not set + +# +# Console +# +# CONFIG_POSTCAR_CONSOLE is not set +CONFIG_SQUELCH_EARLY_SMP=y +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +# CONFIG_CONSOLE_SPI_FLASH is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +# CONFIG_NO_POST is not set +# CONFIG_CMOS_POST is not set +# CONFIG_CONSOLE_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +# CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HWBASE_DEBUG_CB=y +CONFIG_HAVE_ACPI_RESUME=y +# CONFIG_ACPI_HUGE_LOWMEM_BACKUP is not set +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +# CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set +CONFIG_HAVE_MONOTONIC_TIMER=y +# CONFIG_GENERIC_UDELAY is not set +# CONFIG_TIMER_QUEUE is not set +CONFIG_HAVE_OPTION_TABLE=y +# CONFIG_PIRQ_ROUTE is not set +CONFIG_HAVE_SMI_HANDLER=y +# CONFIG_PCI_IO_CFG_EXT is not set +CONFIG_IOAPIC=y +# CONFIG_USE_WATCHDOG_ON_BOOT is not set +CONFIG_GFXUMA=y +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_HAVE_MP_TABLE=y +# CONFIG_COMMON_FADT is not set +# CONFIG_ACPI_NHLT is not set + +# +# System tables +# +CONFIG_GENERATE_MP_TABLE=y +# CONFIG_GENERATE_PIRQ_TABLE is not set +CONFIG_GENERATE_SMBIOS_TABLES=y + +# +# Payload +# +# CONFIG_PAYLOAD_NONE is not set +# CONFIG_PAYLOAD_ELF is not set +# CONFIG_PAYLOAD_BAYOU is not set +# CONFIG_PAYLOAD_FILO is not set +# CONFIG_PAYLOAD_GRUB2 is not set +# CONFIG_PAYLOAD_LINUXBOOT is not set +CONFIG_PAYLOAD_SEABIOS=y +# CONFIG_PAYLOAD_UBOOT is not set +# CONFIG_PAYLOAD_YABITS is not set +# CONFIG_PAYLOAD_LINUX is not set +# CONFIG_PAYLOAD_TIANOCORE is not set +CONFIG_PAYLOAD_FILE="payloads/external/SeaBIOS/seabios/out/bios.bin.elf" +# CONFIG_SEABIOS_STABLE is not set +CONFIG_SEABIOS_MASTER=y +# CONFIG_SEABIOS_REVISION is not set +# CONFIG_SEABIOS_THREAD_OPTIONROMS is not set +CONFIG_SEABIOS_BOOTORDER_FILE="" +# CONFIG_SEABIOS_ADD_SERCON_PORT_FILE is not set +CONFIG_SEABIOS_DEBUG_LEVEL=-1 + +# +# Using default SeaBIOS log level +# +CONFIG_PAYLOAD_OPTIONS="" +# CONFIG_PXE is not set +CONFIG_COMPRESSED_PAYLOAD_LZMA=y +# CONFIG_COMPRESSED_PAYLOAD_LZ4 is not set +# CONFIG_PAYLOAD_IS_FLAT_BINARY is not set +CONFIG_COMPRESS_SECONDARY_PAYLOAD=y + +# +# Secondary Payloads +# +CONFIG_COREINFO_SECONDARY_PAYLOAD=y +# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set +# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set +CONFIG_TINT_SECONDARY_PAYLOAD=y + +# +# Debugging +# + +# +# CPU Debug Settings +# +# CONFIG_DEBUG_SMM_RELOCATION is not set + +# +# General Debug Settings +# +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +# CONFIG_HAVE_DEBUG_RAM_SETUP is not set +# CONFIG_HAVE_DEBUG_SMBUS is not set +# CONFIG_DEBUG_SMI is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_ACPI is not set +# CONFIG_DEBUG_CONSOLE_INIT is not set +# CONFIG_X86EMU_DEBUG is not set +# CONFIG_DEBUG_SPI_FLASH is not set +# CONFIG_TRACE is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set +# CONFIG_HAVE_EM100_SUPPORT is not set +CONFIG_NO_EDID_FILL_FB=y +# CONFIG_ENABLE_APIC_EXT_ID is not set +CONFIG_WARNINGS_ARE_ERRORS=y +# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set +# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set +# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set +# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set +# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set +# CONFIG_REG_SCRIPT is not set +# CONFIG_NO_XIP_EARLY_STAGES is not set +# CONFIG_EARLY_CBMEM_LIST is not set +CONFIG_RELOCATABLE_MODULES=y +CONFIG_BOOTBLOCK_CUSTOM=y + -- To view, visit https://review.coreboot.org/c/coreboot/+/32352 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85f17395afca52ef690f24fcef746d74bb72aab7 Gerrit-Change-Number: 32352 Gerrit-PatchSet: 1 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

2 days

4
28
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Change in ...coreboot[master]: drivers/intel/gma: Add `new-pch.asl` for Skylake+

by Nico Huber (Code Review)

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31503 Change subject: drivers/intel/gma: Add `new-pch.asl` for Skylake+ ...................................................................... drivers/intel/gma: Add `new-pch.asl` for Skylake+ This should work as `pch.asl` equivalent for Skylake and later platforms. Untested. Change-Id: I0b21d9a0288f0f8d6cb0a4776909bffdae7576f5 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- A src/drivers/intel/gma/acpi/new-pch.asl 1 file changed, 42 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/31503/1 diff --git a/src/drivers/intel/gma/acpi/new-pch.asl b/src/drivers/intel/gma/acpi/new-pch.asl new file mode 100644 index 0000000..b24a350 --- /dev/null +++ b/src/drivers/intel/gma/acpi/new-pch.asl @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (GFX0) +{ + Name (_ADR, 0x00020000) + + OperationRegion (GFXC, PCI_Config, 0x00, 0x0100) + Field (GFXC, DWordAcc, NoLock, Preserve) + { + Offset (0x10), + BAR0, 64, + Offset (0xe4), + ASLE, 32, + Offset (0xfc), + ASLS, 32, + } + + OperationRegion (GFRG, SystemMemory, And (BAR0, 0xfffffffffffffff0), 0x400000) + Field (GFRG, DWordAcc, NoLock, Preserve) + { + Offset (0xc8254), + BCLV, 16, + BCLM, 16 + } + +#include "configure_brightness_levels.asl" +#include "common.asl" +} -- To view, visit https://review.coreboot.org/c/coreboot/+/31503 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b21d9a0288f0f8d6cb0a4776909bffdae7576f5 Gerrit-Change-Number: 31503 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

4 days, 20 hours

7
22
0 0

Change in ...coreboot[master]: payloads/ipxe: Enable HTTPS support

by Felix Singer (Code Review)

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31086 Change subject: payloads/ipxe: Enable HTTPS support ...................................................................... payloads/ipxe: Enable HTTPS support HTTPS needs a newer iPXE version than 2017.3, because it doesn't work with this release. Tested under master branch. Change-Id: Ia25d4ce9260fa8c00fdea0e19f5e927559371af0 Signed-off-by: Felix Singer <migy(a)darmstadt.ccc.de> --- M payloads/external/iPXE/Makefile 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/31086/1 diff --git a/payloads/external/iPXE/Makefile b/payloads/external/iPXE/Makefile index a8b1245..05b6f4dd 100644 --- a/payloads/external/iPXE/Makefile +++ b/payloads/external/iPXE/Makefile @@ -54,6 +54,7 @@ sed 's|#define\s*COMCONSOLE.*|#define COMCONSOLE $(IPXE_UART)|' "$(project_dir)/src/config/serial.h" > "$(project_dir)/src/config/serial.h.tmp" sed 's|#define\s*COMSPEED.*|#define COMSPEED $(CONFIG_TTYS0_BAUD)|' "$(project_dir)/src/config/serial.h.tmp" > "$(project_dir)/src/config/serial.h" endif + sed -ie 's|.*DOWNLOAD_PROTO_HTTPS|#define DOWNLOAD_PROTO_HTTPS|g' "$(project_dir)/src/config/general.h" build: config echo " MAKE $(project_name) $(TAG-y)" -- To view, visit https://review.coreboot.org/c/coreboot/+/31086 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia25d4ce9260fa8c00fdea0e19f5e927559371af0 Gerrit-Change-Number: 31086 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-MessageType: newchange

6 days, 17 hours

5
12
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Change in ...coreboot[master]: soc/intel/cannonlake: Set correct serirq mode based on SERIRQ_CONTINU...

by Jeremy Soller (Code Review)

Jeremy Soller has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31536 Change subject: soc/intel/cannonlake: Set correct serirq mode based on SERIRQ_CONTINUOUS_MODE ...................................................................... soc/intel/cannonlake: Set correct serirq mode based on SERIRQ_CONTINUOUS_MODE Change-Id: I9ad4f5a6c7391fc6e813ec1306c708f449a69f59 --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/fsp_params.c 2 files changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/31536/1 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index cd8819d..3716640 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -172,6 +172,13 @@ default 24 if SOC_INTEL_CANNONLAKE_PCH_H default 16 +config SERIRQ_CONTINUOUS_MODE + bool + default n + help + If you set this option to y, the serial IRQ machine will be + operated in continuous mode. + config SMM_TSEG_SIZE hex default 0x800000 diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index c276c86..c95a68f 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -246,6 +246,12 @@ /* Set TccActivationOffset */ tconfig->TccActivationOffset = config->tcc_offset; + + /* Set correct Sirq mode based on config */ + if (IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE)) + params->PchSirqMode = 1; + else + params->PchSirqMode = 0; } /* Mainboard GPIO Configuration */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31536 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ad4f5a6c7391fc6e813ec1306c708f449a69f59 Gerrit-Change-Number: 31536 Gerrit-PatchSet: 1 Gerrit-Owner: Jeremy Soller <jackpot51(a)gmail.com> Gerrit-MessageType: newchange

1 week, 6 days

7
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Change in ...coreboot[master]: nb/intel/i945: Correct mask for CxDRT1

by HAOUAS Elyes (Code Review)

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31144 Change subject: nb/intel/i945: Correct mask for CxDRT1 ...................................................................... nb/intel/i945: Correct mask for CxDRT1 [27:24] and [31:30] are reserved, so we shouldn't change them. Tested on i945G-M4 board. Change-Id: I0cac9160c756405838706edb0461575241faae35 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/raminit.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/31144/1 diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index f3c3df6..2a62ca3 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -1475,7 +1475,7 @@ /* Calculate DRT1 */ - temp_drt = MCHBAR32(C0DRT1) & 0x00020088; + temp_drt = MCHBAR32(C0DRT1) & 0xcf020088; /* DRAM RASB Precharge */ temp_drt |= (sysinfo->trp - 2) << 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/31144 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0cac9160c756405838706edb0461575241faae35 Gerrit-Change-Number: 31144 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Add support for the 51nb X210

by Matthew Garrett (Code Review)

Matthew Garrett has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32531 Change subject: Add support for the 51nb X210 ...................................................................... Add support for the 51nb X210 The 51nb X210 is a replacement motherboard for Thinkpad X200/X201 systems, based on a modern Kabylake CPU. It also ships with no firmware protection, making it an ideal Coreboot target. This port is based on the support for the Skylake-based Purism Librem 13v3, with the following significant changes: * EC firmware is contained within the system SPI flash, and so a blob of EC firmware must be injected to a defined location during image build. A tool has been provided to do this. * GPIO layout is different - this is currently just a raw import of the GPIO configuration from the vendor firmware * The system has two DIMMs, so an additional SPD address has been added * The USB port layout is different * The EC must be enabled at boot time through SuperIO-style logical device configuration * EC register layout is different, necessitating changes in the ACPI tables * The HDA pins are different * The genx_dec config is different Signed-off-by: Matthew Garrett <mjg59(a)google.com> Change-Id: If74621e76d703f629b54f1feb1acfc95cc72d183 --- M Makefile.inc A configs/config.51nb_x210 M src/Kconfig A src/ec/51nb/51nb.c A src/ec/51nb/Kconfig A src/ec/51nb/Makefile.inc A src/ec/51nb/ec.h A src/mainboard/51nb/Kconfig A src/mainboard/51nb/Kconfig.name A src/mainboard/51nb/x210/Kconfig A src/mainboard/51nb/x210/Kconfig.name A src/mainboard/51nb/x210/Makefile.inc A src/mainboard/51nb/x210/acpi/ec.asl A src/mainboard/51nb/x210/acpi/graphics.asl A src/mainboard/51nb/x210/acpi/mainboard.asl A src/mainboard/51nb/x210/acpi/platform.asl A src/mainboard/51nb/x210/acpi/superio.asl A src/mainboard/51nb/x210/acpi_tables.c A src/mainboard/51nb/x210/board_info.txt A src/mainboard/51nb/x210/devicetree.cb A src/mainboard/51nb/x210/dsdt.asl A src/mainboard/51nb/x210/gpio.h A src/mainboard/51nb/x210/hda_verb.c A src/mainboard/51nb/x210/hda_verb.h A src/mainboard/51nb/x210/mainboard.c A src/mainboard/51nb/x210/pei_data.c A src/mainboard/51nb/x210/pei_data.h A src/mainboard/51nb/x210/ramstage.c A src/mainboard/51nb/x210/romstage.c A util/51nb/51nb_ec_insert.c A util/51nb/Makefile 31 files changed, 2,530 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/32531/1 diff --git a/Makefile.inc b/Makefile.inc index fc04a16..6e379dd 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -88,7 +88,7 @@ ####################################################################### # root source directories of coreboot subdirs-y := src/lib src/commonlib/ src/console src/device src/acpi -subdirs-y += src/ec/acpi $(wildcard src/ec/*/*) $(wildcard src/southbridge/*/*) +subdirs-y += src/ec/acpi src/ec/51nb $(wildcard src/ec/*/*) $(wildcard src/southbridge/*/*) subdirs-y += $(wildcard src/soc/*/*) $(wildcard src/northbridge/*/*) subdirs-y += src/superio subdirs-y += $(wildcard src/drivers/*) $(wildcard src/drivers/*/*) diff --git a/configs/config.51nb_x210 b/configs/config.51nb_x210 new file mode 100644 index 0000000..6217eb6 --- /dev/null +++ b/configs/config.51nb_x210 @@ -0,0 +1,838 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_COREBOOT_BUILD=y +CONFIG_LOCALVERSION="1" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set +CONFIG_COMPRESS_RAMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_COLLECT_TIMESTAMPS=y +# CONFIG_TIMESTAMPS_ON_CONSOLE is not set +CONFIG_USE_BLOBS=y +# CONFIG_COVERAGE is not set +# CONFIG_UBSAN is not set +# CONFIG_NO_RELOCATABLE_RAMSTAGE is not set +CONFIG_RELOCATABLE_RAMSTAGE=y +CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM=y +# CONFIG_UPDATE_IMAGE is not set +CONFIG_BOOTSPLASH_IMAGE=y +CONFIG_BOOTSPLASH_FILE="" + +# +# Mainboard +# + +# +# Important: Run 'make distclean' before switching boards +# +CONFIG_VENDOR_51NB=y +# CONFIG_VENDOR_ADI is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_ADVANSUS is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_AVALUE is not set +# CONFIG_VENDOR_BAP is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_CAVIUM is not set +# CONFIG_VENDOR_COMPULAB is not set +# CONFIG_VENDOR_CUBIETECH is not set +# CONFIG_VENDOR_ELMEX is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_FACEBOOK is not set +# CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GIZMOSPHERE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IEI is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LENOVO is not set +# CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_OCP is not set +# CONFIG_VENDOR_OPENCELLULAR is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set +# CONFIG_VENDOR_SCALEWAY is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SIFIVE is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_TYAN is not set +# CONFIG_VENDOR_VIA is not set +CONFIG_BOARD_51NB_X210=y +CONFIG_IRQ_SLOT_COUNT=18 +CONFIG_MAINBOARD_VENDOR="51nb" +CONFIG_MAINBOARD_FAMILY="X210" +CONFIG_MAINBOARD_PART_NUMBER="X210" +CONFIG_MAINBOARD_VERSION="2.0" +CONFIG_MAINBOARD_DIR="51nb/x210" +CONFIG_DEVICETREE="devicetree.cb" +CONFIG_MAX_CPUS=8 +# CONFIG_NO_POST is not set +CONFIG_VGA_BIOS_ID="8086,5917" +CONFIG_DIMM_MAX=2 +CONFIG_DIMM_SPD_SIZE=512 +CONFIG_CPU_MICROCODE_CBFS_LEN=0x18000 +CONFIG_CPU_MICROCODE_CBFS_LOC=0xFFE115A0 +CONFIG_CBFS_SIZE=0x5c0000 +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_VGA_BIOS=y +CONFIG_MAINBOARD_SERIAL_NUMBER="Unknown Serial Number" +CONFIG_VGA_BIOS_FILE="vgabios.bin" +CONFIG_C_ENV_BOOTBLOCK_SIZE=0xC000 +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="51nb" +CONFIG_INTEL_GMA_VBT_FILE="vbt.bin" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 +# CONFIG_POST_IO is not set +CONFIG_DCACHE_RAM_BASE=0xfef00000 +CONFIG_DCACHE_RAM_SIZE=0x40000 +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_OVERRIDE_DEVICETREE="" +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +CONFIG_FMDFILE="" +CONFIG_DCACHE_BSP_STACK_SIZE=0x4000 +CONFIG_MMCONF_BASE_ADDRESS=0xe0000000 +CONFIG_HAVE_INTEL_FIRMWARE=y +# CONFIG_POST_DEVICE is not set +# CONFIG_DRIVERS_UART_8250IO is not set +# CONFIG_VBOOT is not set +CONFIG_TPM_PIRQ=0x0 +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="X210" +CONFIG_IFD_BIN_PATH="descriptor.bin" +CONFIG_ME_BIN_PATH="me.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_FSP_M_FILE="$(obj)/Fsp_M.fd" +CONFIG_FSP_S_FILE="$(obj)/Fsp_S.fd" +CONFIG_FSP_S_CBFS="fsps.bin" +CONFIG_FSP_M_CBFS="fspm.bin" +CONFIG_CPU_ADDR_BITS=36 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 +CONFIG_DRIVERS_PS2_KEYBOARD=y +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_SMBIOS_ENCLOSURE_TYPE=0x09 +CONFIG_HEAP_SIZE=0x80000 +CONFIG_BOARD_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +CONFIG_COREBOOT_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=8192 +CONFIG_ROM_SIZE=0x800000 +CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y +CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +CONFIG_POWER_STATE_DEFAULT_ON_AFTER_FAILURE=y +# CONFIG_POWER_STATE_OFF_AFTER_FAILURE is not set +CONFIG_POWER_STATE_ON_AFTER_FAILURE=y +# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set +CONFIG_MAINBOARD_POWER_FAILURE_STATE=1 +CONFIG_SYSTEM_TYPE_LAPTOP=y +# CONFIG_SYSTEM_TYPE_TABLET is not set +# CONFIG_SYSTEM_TYPE_DETACHABLE is not set +# CONFIG_SYSTEM_TYPE_CONVERTIBLE is not set +# CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set + +# +# Chipset +# + +# +# SoC +# +CONFIG_CPU_SPECIFIC_OPTIONS=y +CONFIG_SMM_TSEG_SIZE=0x800000 +CONFIG_SMM_RESERVED_SIZE=0x200000 +CONFIG_SMM_MODULE_STACK_SIZE=0x400 +CONFIG_ACPI_CPU_STRING="\\_PR.CP%02d" +CONFIG_DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ=120 +# CONFIG_SOC_CAVIUM_CN81XX is not set +CONFIG_ARCH_ARMV8_EXTENSION=0 +CONFIG_STACK_SIZE=0x1000 +# CONFIG_SOC_CAVIUM_COMMON is not set +# CONFIG_SOC_INTEL_GLK is not set +CONFIG_PCR_BASE_ADDRESS=0xfd000000 +CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ=120 +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_FSP_HEADER_PATH="3rdparty/fsp/KabylakeFspBinPkg/Include/" +CONFIG_FSP_FD_PATH="3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd" +# CONFIG_NHLT_MAX98357 is not set +# CONFIG_NHLT_DA7219 is not set +# CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS is not set +CONFIG_IFD_CHIPSET="sklkbl" +CONFIG_CPU_BCLK_MHZ=100 +CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL=0x30 +CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL=0xc35 +CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX=2 +CONFIG_SOC_INTEL_I2C_DEV_MAX=6 +# CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE is not set +CONFIG_IED_REGION_SIZE=0x400000 +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_COMMON_CLOCK=y +CONFIG_PCIEXP_CLK_PM=y +# CONFIG_SOC_INTEL_COMMON_CANNONLAKE_BASE is not set +# CONFIG_SOC_INTEL_COFFEELAKE is not set +# CONFIG_SOC_INTEL_WHISKEYLAKE is not set +# CONFIG_SOC_INTEL_COMETLAKE is not set +# CONFIG_SOC_INTEL_CANNONLAKE_PCH_H is not set +# CONFIG_NHLT_MAX98373 is not set +CONFIG_MAX_ROOT_PORTS=24 +# CONFIG_CONSOLE_CBMEM is not set +CONFIG_UART_PCI_ADDR=0x0 +CONFIG_SOC_INTEL_SKYLAKE=y +CONFIG_SOC_INTEL_KABYLAKE=y +CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=10 +CONFIG_MAINBOARD_USES_FSP2_0=y +CONFIG_USE_FSP2_0_DRIVER=y +# CONFIG_EXCLUDE_NATIVE_SD_INTERFACE is not set +# CONFIG_SKYLAKE_SOC_PCH_H is not set +# CONFIG_NHLT_DMIC_2CH is not set +# CONFIG_NHLT_DMIC_4CH is not set +# CONFIG_NHLT_NAU88L25 is not set +# CONFIG_NHLT_SSM4567 is not set +# CONFIG_NHLT_RT5514 is not set +# CONFIG_NHLT_RT5663 is not set +# CONFIG_NHLT_MAX98927 is not set +# CONFIG_NO_FADT_8042 is not set +CONFIG_SOC_INTEL_COMMON=y + +# +# Intel SoC Common Code +# +CONFIG_SOC_INTEL_COMMON_BLOCK=y +CONFIG_SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG=y +CONFIG_SOC_INTEL_COMMON_BLOCK_CPU=y +CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT=y +CONFIG_SOC_INTEL_COMMON_BLOCK_CAR=y +# CONFIG_INTEL_CAR_NEM is not set +# CONFIG_INTEL_CAR_CQOS is not set +CONFIG_INTEL_CAR_NEM_ENHANCED=y + +# +# Multiple Processor (MP) Initialization Options +# +CONFIG_USE_COREBOOT_NATIVE_MP_INIT=y +# CONFIG_USE_INTEL_FSP_MP_INIT is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_CSE=y +CONFIG_SOC_INTEL_COMMON_BLOCK_DSP=y +CONFIG_SOC_INTEL_COMMON_BLOCK_EBDA=y +CONFIG_SOC_INTEL_COMMON_BLOCK_FAST_SPI=y +CONFIG_FAST_SPI_DISABLE_WRITE_STATUS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL=y +# CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS=y +# CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_MULTI_ACPI_DEVICES is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GRAPHICS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI=y +# CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_HDA=y +CONFIG_SOC_INTEL_COMMON_BLOCK_I2C=y +CONFIG_SOC_INTEL_COMMON_BLOCK_ITSS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_LPC=y +CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB=y +CONFIG_SOC_INTEL_COMMON_BLOCK_PCIE=y +CONFIG_SOC_INTEL_COMMON_BLOCK_PCR=y +CONFIG_SOC_INTEL_COMMON_BLOCK_PMC=y +# CONFIG_PMC_INVALID_READ_AFTER_WRITE is not set +CONFIG_PMC_GLOBAL_RESET_ENABLE_LOCK=y +CONFIG_SOC_INTEL_COMMON_BLOCK_RTC=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SATA=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SCS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SGX=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_TCO=y +CONFIG_SOC_INTEL_COMMON_BLOCK_TCO_ENABLE_THROUGH_SMBUS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SMM=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP=y +# CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_ESPI_DISABLE is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS=0 +CONFIG_SOC_INTEL_COMMON_BLOCK_SPI=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SA=y +CONFIG_SA_PCIEX_LENGTH=0x4000000 +CONFIG_PCIEX_LENGTH_64MB=y +# CONFIG_SA_ENABLE_IMR is not set +CONFIG_SA_ENABLE_DPR=y +CONFIG_SOC_INTEL_COMMON_BLOCK_TIMER=y +CONFIG_SOC_INTEL_COMMON_BLOCK_UART=y +CONFIG_SOC_INTEL_COMMON_BLOCK_XDCI=y +CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI=y +CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI_ELOG=y + +# +# Intel SoC Common PCH Code +# +CONFIG_SOC_INTEL_COMMON_PCH_BASE=y +CONFIG_SOC_INTEL_COMMON_PCH_LOCKDOWN=y +CONFIG_PCH_SPECIFIC_OPTIONS=y + +# +# Intel SoC Common coreboot stages +# +# CONFIG_DISPLAY_SMM_MEMORY_MAP is not set +CONFIG_SOC_INTEL_COMMON_RESET=y +CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE=y +# CONFIG_ACPI_CONSOLE is not set +# CONFIG_MMA is not set +# CONFIG_SOC_INTEL_COMMON_ACPI is not set +# CONFIG_SOC_INTEL_COMMON_ACPI_EC_PTS_WAK is not set +CONFIG_SOC_INTEL_COMMON_NHLT=y +# CONFIG_SOC_INTEL_DEBUG_CONSENT is not set +# CONFIG_SOC_MEDIATEK_MT8173 is not set +# CONFIG_SOC_MEDIATEK_MT8183 is not set +# CONFIG_SOC_NVIDIA_TEGRA124 is not set +# CONFIG_SOC_NVIDIA_TEGRA210 is not set +# CONFIG_SOC_QC_IPQ40XX is not set +# CONFIG_SOC_QC_IPQ806X is not set +# CONFIG_SOC_QUALCOMM_QCS405 is not set +# CONFIG_SOC_QUALCOMM_SDM845 is not set +# CONFIG_SOC_ROCKCHIP_RK3288 is not set +# CONFIG_SOC_ROCKCHIP_RK3399 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set +# CONFIG_SOC_UCB_RISCV is not set + +# +# CPU +# +# CONFIG_CPU_ALLWINNER_A10 is not set +CONFIG_NUM_IPI_STARTS=2 +# CONFIG_CPU_AMD_AGESA is not set +# CONFIG_CPU_AMD_PI is not set +# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +CONFIG_SSE2=y +CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y +# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_IA32_FC_LOCK_BIT=y +CONFIG_MICROCODE_UPDATE_PRE_RAM=y +# CONFIG_CPU_TI_AM335X is not set +# CONFIG_PARALLEL_CPU_INIT is not set +CONFIG_PARALLEL_MP=y +CONFIG_PARALLEL_MP_AP_WORK=y +# CONFIG_UDELAY_IO is not set +# CONFIG_UDELAY_LAPIC is not set +CONFIG_UDELAY_TSC=y +CONFIG_TSC_CONSTANT_RATE=y +CONFIG_TSC_MONOTONIC_TIMER=y +# CONFIG_UDELAY_TIMER2 is not set +# CONFIG_TSC_SYNC_LFENCE is not set +CONFIG_TSC_SYNC_MFENCE=y +CONFIG_NO_FIXED_XIP_ROM_SIZE=y +CONFIG_LOGICAL_CPUS=y +CONFIG_SMM_TSEG=y +CONFIG_SMM_MODULE_HEAP_SIZE=0x4000 +CONFIG_SMM_STUB_STACK_SIZE=0x400 +# CONFIG_SMM_LAPIC_REMAP_MITIGATION is not set +# CONFIG_SERIALIZED_SMM_INITIALIZATION is not set +# CONFIG_X86_AMD_FIXED_MTRRS is not set +# CONFIG_PLATFORM_USES_FSP1_0 is not set +# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +# CONFIG_SOC_SETS_MSRS is not set +CONFIG_CACHE_AS_RAM=y +CONFIG_NO_CAR_GLOBAL_MIGRATION=y +CONFIG_SMP=y +CONFIG_SSE=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +# CONFIG_USES_MICROCODE_HEADER_FILES is not set +CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y +CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +# CONFIG_CPU_MICROCODE_CBFS_NONE is not set + +# +# Northbridge +# +# CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_NORTHBRIDGE_AMD_PI is not set +CONFIG_MAX_PIRQ_LINKS=4 + +# +# Southbridge +# +# CONFIG_AMD_SB_CIMX is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ is not set +# CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM is not set +CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y +CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y + +# +# Super I/O +# +# CONFIG_SUPERIO_NUVOTON_NCT6776_COM_A is not set + +# +# Embedded Controllers +# +CONFIG_EC_51NB=y + +# +# Please select the following otherwise your laptop cannot be powered on. +# +CONFIG_51NB_EC_FIRMWARE=y +CONFIG_51NB_EC_FW="ec.bin" +CONFIG_51NB_EC_FW_OFFSET="0x00200000" +# CONFIG_EC_GOOGLE_WILCO is not set +CONFIG_EC_BASE_ACPI_DATA=0x930 +CONFIG_EC_BASE_ACPI_COMMAND=0x934 +CONFIG_EC_BASE_HOST_DATA=0x940 +CONFIG_EC_BASE_HOST_COMMAND=0x944 +CONFIG_EC_BASE_PACKET=0x950 + +# +# Intel Firmware +# +CONFIG_HAVE_ME_BIN=y +# CONFIG_CHECK_ME is not set +# CONFIG_USE_ME_CLEANER is not set +# CONFIG_MAINBOARD_USES_IFD_GBE_REGION is not set +# CONFIG_MAINBOARD_USES_IFD_EC_REGION is not set +# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set +CONFIG_UNLOCK_FLASH_REGIONS=y +# CONFIG_CAVIUM_BDK is not set +# CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_GOOGLE_SMBIOS_MAINBOARD_VERSION is not set +# CONFIG_UEFI_2_4_BINDING is not set +CONFIG_UDK_2015_BINDING=y +# CONFIG_UDK_2017_BINDING is not set +CONFIG_UDK_2013_VERSION=2013 +CONFIG_UDK_2015_VERSION=2015 +CONFIG_UDK_2017_VERSION=2017 +CONFIG_UDK_VERSION=2015 +# CONFIG_USE_SIEMENS_HWILIB is not set +# CONFIG_ARCH_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARM is not set +# CONFIG_ARCH_VERSTAGE_ARM is not set +# CONFIG_ARCH_ROMSTAGE_ARM is not set +# CONFIG_ARCH_RAMSTAGE_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV4 is not set +# CONFIG_ARCH_VERSTAGE_ARMV4 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV4 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV4 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set +# CONFIG_ARCH_VERSTAGE_ARMV7 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_R is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_R is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7_R is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7_R is not set +# CONFIG_ARM_LPAE is not set +# CONFIG_ARCH_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARM64 is not set +# CONFIG_ARCH_VERSTAGE_ARM64 is not set +# CONFIG_ARCH_ROMSTAGE_ARM64 is not set +# CONFIG_ARCH_RAMSTAGE_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV8_64 is not set +# CONFIG_ARCH_VERSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV8_64 is not set +# CONFIG_ARM64_USE_ARCH_TIMER is not set +# CONFIG_ARM64_A53_ERRATUM_843419 is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_BOOTBLOCK_MIPS is not set +# CONFIG_ARCH_VERSTAGE_MIPS is not set +# CONFIG_ARCH_ROMSTAGE_MIPS is not set +# CONFIG_ARCH_RAMSTAGE_MIPS is not set +# CONFIG_ARCH_PPC64 is not set +# CONFIG_ARCH_BOOTBLOCK_PPC64 is not set +# CONFIG_ARCH_VERSTAGE_PPC64 is not set +# CONFIG_ARCH_ROMSTAGE_PPC64 is not set +# CONFIG_ARCH_RAMSTAGE_PPC64 is not set +# CONFIG_ARCH_RISCV is not set +CONFIG_ARCH_RISCV_M=y +# CONFIG_ARCH_RISCV_S is not set +# CONFIG_ARCH_RISCV_U is not set +# CONFIG_ARCH_RISCV_RV64 is not set +# CONFIG_ARCH_RISCV_RV32 is not set +# CONFIG_ARCH_RISCV_PMP is not set +# CONFIG_ARCH_BOOTBLOCK_RISCV is not set +# CONFIG_ARCH_VERSTAGE_RISCV is not set +# CONFIG_ARCH_ROMSTAGE_RISCV is not set +# CONFIG_ARCH_RAMSTAGE_RISCV is not set +# CONFIG_RISCV_USE_ARCH_TIMER is not set +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_POSTCAR_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +# CONFIG_ARCH_BOOTBLOCK_X86_64 is not set +# CONFIG_ARCH_VERSTAGE_X86_64 is not set +# CONFIG_ARCH_ROMSTAGE_X86_64 is not set +# CONFIG_ARCH_POSTCAR_X86_64 is not set +# CONFIG_ARCH_RAMSTAGE_X86_64 is not set +# CONFIG_USE_MARCH_586 is not set +# CONFIG_AP_IN_SIPI_WAIT is not set +# CONFIG_SIPI_VECTOR_IN_ROM is not set +CONFIG_RAMBASE=0xe00000 +CONFIG_RAMTOP=0x1000000 +# CONFIG_CBMEM_TOP_BACKUP is not set +CONFIG_EARLY_EBDA_INIT=y +CONFIG_PC80_SYSTEM=y +# CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set +# CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set +CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y +# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set +# CONFIG_HPET_ADDRESS_OVERRIDE is not set +CONFIG_HPET_ADDRESS=0xfed00000 +CONFIG_ID_SECTION_OFFSET=0x80 +CONFIG_POSTCAR_STAGE=y +# CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set +# CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" +CONFIG_ACPI_HAVE_PCAT_8259=y +# CONFIG_COLLECT_TIMESTAMPS_NO_TSC is not set +CONFIG_COLLECT_TIMESTAMPS_TSC=y +# CONFIG_PAGING_IN_CACHE_AS_RAM is not set +# CONFIG_IDT_IN_EVERY_STAGE is not set +CONFIG_HAVE_CF9_RESET=y + +# +# Devices +# +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y +CONFIG_HAVE_FSP_GOP=y +# CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT is not set +# CONFIG_MAINBOARD_HAS_LIBGFXINIT is not set +# CONFIG_VGA_ROM_RUN is not set +CONFIG_RUN_FSP_GOP=y +# CONFIG_NO_GFX_INIT is not set +# CONFIG_MULTIPLE_VGA_ADAPTERS is not set + +# +# Display +# +CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y +CONFIG_LINEAR_FRAMEBUFFER=y +# CONFIG_SMBUS_HAS_AUX_CHANNELS is not set +CONFIG_PCI=y +# CONFIG_NO_MMCONF_SUPPORT is not set +CONFIG_MMCONF_SUPPORT=y +# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +# CONFIG_AZALIA_PLUGIN_SUPPORT is not set +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +# CONFIG_VGA_BIOS_DGPU is not set +CONFIG_INTEL_GMA_ADD_VBT=y +# CONFIG_SOFTWARE_I2C is not set + +# +# Generic Drivers +# +# CONFIG_DRIVERS_AS3722_RTC is not set +# CONFIG_ELOG is not set +# CONFIG_GIC is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_DRIVERS_LENOVO_WACOM is not set +CONFIG_CACHE_MRC_SETTINGS=y +CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000 +CONFIG_MRC_SETTINGS_PROTECT=y +# CONFIG_HAS_RECOVERY_MRC_CACHE is not set +# CONFIG_MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN is not set +# CONFIG_MRC_SETTINGS_VARIABLE_DATA is not set +# CONFIG_MRC_WRITE_NV_LATE is not set +# CONFIG_RT8168_GET_MAC_FROM_VPD is not set +# CONFIG_RT8168_SET_LED_MODE is not set +CONFIG_SMMSTORE=y +# CONFIG_SMMSTORE_IN_CBFS is not set +CONFIG_SMMSTORE_REGION="SMMSTORE" +CONFIG_SMMSTORE_FILENAME="smm_store" +CONFIG_SMMSTORE_SIZE=0x40000 +CONFIG_SPI_FLASH=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y +CONFIG_SPI_FLASH_SMM=y +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +# CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B is not set +# CONFIG_SPI_FLASH_HAS_VOLATILE_GROUP is not set +# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +CONFIG_TPM_INIT=y +# CONFIG_NO_UART_ON_SUPERIO is not set +# CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set +# CONFIG_UART_OVERRIDE_REFCLK is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_DRIVERS_UART_8250MEM_32 is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +# CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set +# CONFIG_HAVE_USBDEBUG is not set +# CONFIG_HAVE_USBDEBUG_OPTIONS is not set +# CONFIG_VPD is not set +# CONFIG_DRIVERS_AMD_PI is not set +# CONFIG_SMBIOS_PROVIDED_BY_MOBO is not set +CONFIG_DRIVERS_I2C_DESIGNWARE=y +# CONFIG_DRIVERS_I2C_DESIGNWARE_DEBUG is not set +# CONFIG_DRIVERS_I2C_MAX98373 is not set +# CONFIG_DRIVERS_I2C_MAX98927 is not set +# CONFIG_DRIVERS_I2C_PCA9538 is not set +# CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_RT5663 is not set +# CONFIG_DRIVERS_I2C_RTD2132 is not set +# CONFIG_DRIVERS_I2C_RX6110SA is not set +# CONFIG_DRIVERS_I2C_SX9310 is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_ATMEL is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_CR50 is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_GENERIC is not set +# CONFIG_DISPLAY_HOBS is not set +# CONFIG_DISPLAY_UPD_DATA is not set +CONFIG_PLATFORM_USES_FSP2_0=y +# CONFIG_PLATFORM_USES_FSP2_1 is not set +# CONFIG_DISPLAY_FSP_CALLS_AND_STATUS is not set +# CONFIG_DISPLAY_FSP_HEADER is not set +CONFIG_FSP_USE_REPO=y +# CONFIG_FSP_CAR is not set +CONFIG_FSP_M_XIP=y +# CONFIG_FSP_T_XIP is not set +# CONFIG_FSP_USES_CB_STACK is not set +# CONFIG_VERIFY_HOBS is not set +# CONFIG_DISPLAY_FSP_VERSION_INFO is not set +# CONFIG_INTEL_DDI is not set +# CONFIG_INTEL_EDID is not set +# CONFIG_INTEL_INT15 is not set +CONFIG_INTEL_GMA_ACPI=y +# CONFIG_INTEL_GMA_SSC_ALTERNATE_REF is not set +# CONFIG_INTEL_GMA_SWSMISCI is not set +# CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_DRIVERS_INTEL_MIPI_CAMERA is not set +# CONFIG_DRIVERS_INTEL_WIFI is not set +# CONFIG_USE_SAR is not set +# CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS is not set +# CONFIG_DRIVER_MAXIM_MAX77686 is not set +# CONFIG_DRIVER_PARADE_PS8625 is not set +# CONFIG_DRIVER_PARADE_PS8640 is not set +CONFIG_DRIVERS_MC146818=y +CONFIG_LPC_TPM=y +CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000 +CONFIG_MAINBOARD_HAS_LPC_TPM=y +# CONFIG_DRIVERS_RICOH_RCE822 is not set +# CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_NC_FPGA_NOTIFY_CB_READY is not set +# CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_MAINBOARD_HAS_SPI_TPM_CR50 is not set +# CONFIG_DRIVER_TI_TPS65090 is not set +# CONFIG_DRIVERS_TI_TPS65913 is not set +# CONFIG_DRIVERS_TI_TPS65913_RTC is not set +# CONFIG_DRIVERS_USB_ACPI is not set +# CONFIG_DRIVER_XPOWERS_AXP209 is not set +# CONFIG_COMMONLIB_STORAGE is not set + +# +# Security +# + +# +# Verified Boot (vboot) +# + +# +# Trusted Platform Module +# +CONFIG_TPM2=y +# CONFIG_USER_NO_TPM is not set +# CONFIG_USER_TPM1 is not set +CONFIG_USER_TPM2=y +# CONFIG_DEBUG_TPM is not set +# CONFIG_TPM_RDRESP_NEED_DELAY is not set +# CONFIG_ACPI_SATA_GENERATOR is not set +CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y +# CONFIG_ACPI_AMD_HARDWARE_SLEEP_VALUES is not set +# CONFIG_BOOT_DEVICE_NOT_SPI_FLASH is not set +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y +CONFIG_RTC=y + +# +# Console +# +CONFIG_BOOTBLOCK_CONSOLE=y +CONFIG_POSTCAR_CONSOLE=y +CONFIG_SQUELCH_EARLY_SMP=y +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +# CONFIG_CONSOLE_SPI_FLASH is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +# CONFIG_CMOS_POST is not set +# CONFIG_CONSOLE_POST is not set +# CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HWBASE_DEBUG_CB=y +CONFIG_HAVE_ACPI_RESUME=y +# CONFIG_ACPI_HUGE_LOWMEM_BACKUP is not set +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +# CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set +CONFIG_HAVE_MONOTONIC_TIMER=y +# CONFIG_GENERIC_UDELAY is not set +# CONFIG_TIMER_QUEUE is not set +# CONFIG_HAVE_OPTION_TABLE is not set +# CONFIG_PIRQ_ROUTE is not set +CONFIG_HAVE_SMI_HANDLER=y +# CONFIG_PCI_IO_CFG_EXT is not set +CONFIG_IOAPIC=y +# CONFIG_USE_WATCHDOG_ON_BOOT is not set +# CONFIG_GFXUMA is not set +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_COMMON_FADT=y +CONFIG_ACPI_NHLT=y + +# +# System tables +# +# CONFIG_GENERATE_MP_TABLE is not set +# CONFIG_GENERATE_PIRQ_TABLE is not set +CONFIG_GENERATE_SMBIOS_TABLES=y + +# +# Payload +# +# CONFIG_PAYLOAD_NONE is not set +# CONFIG_PAYLOAD_ELF is not set +# CONFIG_PAYLOAD_BAYOU is not set +# CONFIG_PAYLOAD_FILO is not set +# CONFIG_PAYLOAD_GRUB2 is not set +# CONFIG_PAYLOAD_LINUXBOOT is not set +# CONFIG_PAYLOAD_SEABIOS is not set +# CONFIG_PAYLOAD_UBOOT is not set +# CONFIG_PAYLOAD_YABITS is not set +# CONFIG_PAYLOAD_LINUX is not set +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_PAYLOAD_FILE="payloads/external/tianocore/tianocore/Build/UEFIPAYLOAD.fd" +CONFIG_PAYLOAD_OPTIONS="" +# CONFIG_PXE is not set +CONFIG_TIANOCORE_STABLE=y +# CONFIG_TIANOCORE_REVISION is not set +# CONFIG_TIANOCORE_TARGET_IA32 is not set +CONFIG_TIANOCORE_TARGET_X64=y +# CONFIG_TIANOCORE_DEBUG is not set +CONFIG_TIANOCORE_RELEASE=y +# CONFIG_TIANOCORE_USE_8254_TIMER is not set +# CONFIG_TIANOCORE_BOOTSPLASH_IMAGE is not set +CONFIG_COMPRESSED_PAYLOAD_LZMA=y +# CONFIG_COMPRESSED_PAYLOAD_LZ4 is not set +# CONFIG_PAYLOAD_IS_FLAT_BINARY is not set +CONFIG_COMPRESS_SECONDARY_PAYLOAD=y + +# +# Secondary Payloads +# +CONFIG_COREINFO_SECONDARY_PAYLOAD=y +CONFIG_MEMTEST_SECONDARY_PAYLOAD=y +# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set +# CONFIG_TINT_SECONDARY_PAYLOAD is not set +CONFIG_MEMTEST_STABLE=y +# CONFIG_MEMTEST_MASTER is not set +# CONFIG_MEMTEST_REVISION is not set + +# +# Debugging +# + +# +# CPU Debug Settings +# +CONFIG_HAVE_DISPLAY_MTRRS=y +# CONFIG_DISPLAY_MTRRS is not set +# CONFIG_DEBUG_SMM_RELOCATION is not set + +# +# General Debug Settings +# +# CONFIG_FATAL_ASSERTS is not set +CONFIG_HAVE_DEBUG_GPIO=y +# CONFIG_DEBUG_GPIO is not set +# CONFIG_DEBUG_CBFS is not set +# CONFIG_HAVE_DEBUG_RAM_SETUP is not set +# CONFIG_HAVE_DEBUG_SMBUS is not set +# CONFIG_DEBUG_SMI is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_ACPI is not set +# CONFIG_DEBUG_CONSOLE_INIT is not set +# CONFIG_DEBUG_SPI_FLASH is not set +# CONFIG_TRACE is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set +CONFIG_HAVE_EM100_SUPPORT=y +# CONFIG_EM100 is not set +CONFIG_NO_EDID_FILL_FB=y +# CONFIG_ENABLE_APIC_EXT_ID is not set +CONFIG_WARNINGS_ARE_ERRORS=y +# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set +# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set +# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set +# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set +# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set +CONFIG_REG_SCRIPT=y +# CONFIG_NO_XIP_EARLY_STAGES is not set +# CONFIG_EARLY_CBMEM_LIST is not set +CONFIG_RELOCATABLE_MODULES=y +CONFIG_GENERIC_GPIO_LIB=y +CONFIG_SPD_READ_BY_WORD=y +CONFIG_C_ENVIRONMENT_BOOTBLOCK=y diff --git a/src/Kconfig b/src/Kconfig index 90c724e..4688fd3 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -369,6 +369,7 @@ source "src/superio/*/*/Kconfig" comment "Embedded Controllers" source "src/ec/acpi/Kconfig" +source "src/ec/51nb/Kconfig" source "src/ec/*/*/Kconfig" # FIXME move to vendorcode source "src/drivers/intel/fsp1_0/Kconfig" diff --git a/src/ec/51nb/51nb.c b/src/ec/51nb/51nb.c new file mode 100644 index 0000000..2559176 --- /dev/null +++ b/src/ec/51nb/51nb.c @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <device/device.h> + +#include "ec.h" + +static void ec_51nb_ops_enable(struct device *dev) +{ + /* Enable function 5 (PS/2 AUX) */ + outb(LDN_SEL, SETUP_COMMAND); + outb(0x05, SETUP_DATA); + outb(LDN_ENABLE, SETUP_COMMAND); + outb(0x01, SETUP_DATA); + + /* Enable function 6 (PS/2 KB) */ + outb(LDN_SEL, SETUP_COMMAND); + outb(0x06, SETUP_DATA); + outb(LDN_ENABLE, SETUP_COMMAND); + outb(0x01, SETUP_DATA); + + /* Enable funcion 17 (EC) */ + outb(LDN_SEL, SETUP_COMMAND); + outb(0x11, SETUP_DATA); + outb(LDN_ENABLE, SETUP_COMMAND); + outb(0x01, SETUP_DATA); +} + +struct chip_operations ec_51nb_ops = { + CHIP_NAME("51NB EC") + .enable_dev = ec_51nb_ops_enable, +}; diff --git a/src/ec/51nb/Kconfig b/src/ec/51nb/Kconfig new file mode 100644 index 0000000..ca93a7e --- /dev/null +++ b/src/ec/51nb/Kconfig @@ -0,0 +1,45 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2017 Iru Cai +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config EC_51NB + bool + help + Support for the 51NB EC + +if EC_51NB + +comment "Please select the following otherwise your laptop cannot be powered on." + +config 51NB_EC_FIRMWARE + bool "Add firmware images for 51NB EC" + depends on EC_51NB + default y + help + Select this option to add the firmware blob for the 51NB EC. + You need this blob to power on your machine. + +config 51NB_EC_FW + string "51NB EC firmware path" + depends on 51NB_EC_FIRMWARE + default "ec.bin" + help + The path and filename of the file to use as 51NB firmware. + +config 51NB_EC_FW_OFFSET + string + depends on 51NB_EC_FIRMWARE + default "0x00200000" + +endif diff --git a/src/ec/51nb/Makefile.inc b/src/ec/51nb/Makefile.inc new file mode 100644 index 0000000..b41febb --- /dev/null +++ b/src/ec/51nb/Makefile.inc @@ -0,0 +1,43 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2017 Iru Cai +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ifeq ($(CONFIG_EC_51NB),y) +51NB_EC_INSERT:=$(top)/util/51nb/51nb_ec_insert +INTERMEDIATE+=51nb_ec_insert + +51nb_ec_insert: $(obj)/coreboot.pre +ifeq ($(CONFIG_51NB_EC_FIRMWARE),y) + printf " Building 51nb_ec_insert.\n" + $(MAKE) -C util/51nb + printf " Inserting EC firmware blobs.\n" + $(51NB_EC_INSERT) $(obj)/coreboot.pre \ + $(CONFIG_51NB_EC_FW) $(CONFIG_51NB_EC_FW_OFFSET) +endif + +PHONY+=51nb_ec_insert + +build_complete:: +ifeq ($(CONFIG_51NB_EC_FIRMWARE),) + printf "\n** WARNING **\n" + printf "You haven't added the firmware blobs for 51NB EC.\n" + printf "You may be unable to power on your laptop without these blobs.\n" + printf "Please select the following option to add them:\n\n" + printf " Chipset --->\n" + printf " [*] Add firmware images for 51NB EC\n\n" +endif + +ramstage-y += 51nb.c + +endif diff --git a/src/ec/51nb/ec.h b/src/ec/51nb/ec.h new file mode 100644 index 0000000..831514c --- /dev/null +++ b/src/ec/51nb/ec.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef _EC_51NB_H +#define _EC_51NB_H + +#define SETUP_COMMAND 0x4e +#define SETUP_DATA 0x4f +#define LDN_SEL 0x07 +#define LDN_ENABLE 0x30 + +#endif /* _EC_51NB_H */ diff --git a/src/mainboard/51nb/Kconfig b/src/mainboard/51nb/Kconfig new file mode 100644 index 0000000..12d2c0d --- /dev/null +++ b/src/mainboard/51nb/Kconfig @@ -0,0 +1,31 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 Google LLC +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +if VENDOR_51NB + +choice + prompt "Mainboard model" + +source "src/mainboard/51nb/*/Kconfig.name" + +endchoice + +source "src/mainboard/51nb/*/Kconfig" + +config MAINBOARD_VENDOR + string "Mainboard Vendor" + default "51NB" + +endif # VENDOR_51NB diff --git a/src/mainboard/51nb/Kconfig.name b/src/mainboard/51nb/Kconfig.name new file mode 100644 index 0000000..6f99514 --- /dev/null +++ b/src/mainboard/51nb/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_51NB + bool "51NB" diff --git a/src/mainboard/51nb/x210/Kconfig b/src/mainboard/51nb/x210/Kconfig new file mode 100644 index 0000000..d5dd278 --- /dev/null +++ b/src/mainboard/51nb/x210/Kconfig @@ -0,0 +1,76 @@ +config BOARD_51NB_X210 + select SYSTEM_TYPE_LAPTOP + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select SOC_INTEL_KABYLAKE + select MAINBOARD_USES_FSP2_0 + select SPD_READ_BY_WORD + select MAINBOARD_HAS_LPC_TPM + select EC_51NB + +if BOARD_51NB_X210 + +config IRQ_SLOT_COUNT + int + default 18 + +config MAINBOARD_VENDOR + string + default "51NB" + +config MAINBOARD_FAMILY + string + default "X210" + +config MAINBOARD_PART_NUMBER + string + default "X210" + +config MAINBOARD_VERSION + string + default "1.0" + +config MAINBOARD_DIR + string + default "51nb/x210" + +config DEVICETREE + string + default "devicetree.cb" + +config MAX_CPUS + int + default 8 + +config NO_POST + def_bool y + help + This platform does not have any way to see POST codes + so disable them by default. + +config VGA_BIOS_ID + string + default "8086,5917" + +config DIMM_MAX + int + default 2 + +config DIMM_SPD_SIZE + int + default 512 + +config CPU_MICROCODE_CBFS_LEN + hex + default 0x18000 + +config CPU_MICROCODE_CBFS_LOC + hex + default 0xFFE115A0 + +config CBFS_SIZE + hex + default 0x5c0000 + +endif diff --git a/src/mainboard/51nb/x210/Kconfig.name b/src/mainboard/51nb/x210/Kconfig.name new file mode 100644 index 0000000..1cae5dd --- /dev/null +++ b/src/mainboard/51nb/x210/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_51NB_X210 + bool "51NB X210" diff --git a/src/mainboard/51nb/x210/Makefile.inc b/src/mainboard/51nb/x210/Makefile.inc new file mode 100644 index 0000000..5d44e9b --- /dev/null +++ b/src/mainboard/51nb/x210/Makefile.inc @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 Google LLC +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +romstage-y += pei_data.c + +ramstage-y += pei_data.c +ramstage-y += ramstage.c +ramstage-y += hda_verb.c diff --git a/src/mainboard/51nb/x210/acpi/ec.asl b/src/mainboard/51nb/x210/acpi/ec.asl new file mode 100644 index 0000000..1b0d6c2 --- /dev/null +++ b/src/mainboard/51nb/x210/acpi/ec.asl @@ -0,0 +1,216 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (EC) +{ + Name (_HID, EisaId ("PNP0C09")) + Name (_UID, 0) + + Name (_GPE, 0x4F) // _GPE: General Purpose Events + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x62, 0x62, 1, 1) + IO (Decode16, 0x66, 0x66, 1, 1) + }) + + OperationRegion (ERAM, EmbeddedControl, Zero, 0xFF) + Field (ERAM, ByteAcc, Lock, Preserve) + { + Offset (0x50), + CTMP, 8, + CFAN, 8, + B1SS, 1, + BSTS, 2, + ACIN, 1, + Offset (0x53), + BKLG, 8, + TOUP, 1, + WIRE, 1, + BLTH, 1, + LIDC, 1, + APFG, 1, + WRST, 1, + BTST, 1, + ACEB, 1, + CAME, 1, + Offset (0x60), + DGCP, 16, + FLCP, 16, + DGVO, 16, + BDW, 16, + BDL, 16, + BPR, 16, + BRC, 16, + BPV, 16 + } + + Method (_REG, 2, NotSerialized) + { + /* Initialize AC power state */ + Store (ACIN, \PWRS) + + /* Initialize LID switch state */ + Store (LIDC, \LIDS) + } + + /* KEY_BRIGHTNESSUP */ + Method (_Q04) + { + Notify(\_SB.PCI0.GFX0.LCD, 0x86) + } + + /* KEY_BRIGHTNESSDOWN */ + Method (_Q05) + { + Notify(\_SB.PCI0.GFX0.LCD, 0x87) + } + + /* Battery Information Event */ + Method (_Q0C) + { + Notify (BAT, 0x81) + } + + /* AC event */ + Method (_Q0D) + { + Store (ACIN, \PWRS) + Notify (AC, 0x80) + } + + /* Lid event */ + Method (_Q0E) + { + Store (LIDC, \LIDS) + Notify (LID0, 0x80) + } + + /* Battery Information Event */ + Method (_Q13) + { + Notify (BAT, 0x81) + } + + /* Battery Status Event */ + Method (_Q14) + { + Notify (BAT, 0x80) + } + + Device (AC) + { + Name (_HID, "ACPI0003") + Name (_PCL, Package () { \_SB }) + + Method (_STA) + { + Return (0x0F) + } + Method (_PSR) + { + Return (\PWRS) + } + } + + Device (BAT) + { + Name (_HID, EisaId ("PNP0C0A")) + Name (_UID, 1) + Name (_PCL, Package () { \_SB }) + + Method (_STA, 0, NotSerialized) // _STA: Status + { + If (B1SS) + { + Return (0x1F) + } + Else + { + Return (0x0F) + } + } + + Name (PBIF, Package () { + 0x00000001, /* 0x00: Power Unit: mAH */ + 0xFFFFFFFF, /* 0x01: Design Capacity */ + 0xFFFFFFFF, /* 0x02: Last Full Charge Capacity */ + 0x00000001, /* 0x03: Battery Technology: Rechargeable */ + 0xFFFFFFFF, /* 0x04: Design Voltage */ + 0x00000000, /* 0x05: Design Capacity of Warning */ + 0xFFFFFFFF, /* 0x06: Design Capacity of Low */ + 0x00000001, /* 0x07: Capacity Granularity 1 */ + 0x00000001, /* 0x08: Capacity Granularity 2 */ + "Y91", /* 0x09: Model Number */ + "", /* 0x0a: Serial Number */ + "LION", /* 0x0b: Battery Type */ + "CJOYIN" /* 0x0c: OEM Information */ + }) + + Method (_BIF, 0, Serialized) + { + /* Design Capacity */ + Store (DGCP, Index (PBIF, 1)) + + /* Last Full Charge Capacity */ + Store (FLCP, Index (PBIF, 2)) + + /* Design Voltage */ + Store (DGVO, Index (PBIF, 4)) + + /* Design Capacity of Warning */ + Store (BDW, Index (PBIF, 5)) + + /* Design Capacity of Low */ + Store (BDL, Index (PBIF, 6)) + + Return (PBIF) + } + + Name (PBST, Package () { + 0x00000000, /* 0x00: Battery State */ + 0xFFFFFFFF, /* 0x01: Battery Present Rate */ + 0xFFFFFFFF, /* 0x02: Battery Remaining Capacity */ + 0xFFFFFFFF, /* 0x03: Battery Present Voltage */ + }) + + Method (_BST, 0, NotSerialized) // _BST: Battery Status + { + /* + * 0: BATTERY STATE + * + * bit 0 = discharging + * bit 1 = charging + * bit 2 = critical level + */ + Store (BSTS, Index (PBST, 0)) + + /* + * 1: BATTERY PRESENT RATE + */ + Store (BPR, Index (PBST, 1)) + + /* + * 2: BATTERY REMAINING CAPACITY + */ + Store (BRC, Index (PBST, 2)) + + /* + * 3: BATTERY PRESENT VOLTAGE + */ + Store (BPV, Index (PBST, 3)) + + Return (PBST) + } + } +} diff --git a/src/mainboard/51nb/x210/acpi/graphics.asl b/src/mainboard/51nb/x210/acpi/graphics.asl new file mode 100644 index 0000000..ce9fb04 --- /dev/null +++ b/src/mainboard/51nb/x210/acpi/graphics.asl @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB.PCI0.GFX0) +{ + Device (LCD) + { + Method (_ADR, 0, Serialized) + { + Return (0x1F) + } + + Method (_BCL, 0, NotSerialized) + { + Return (Package (0x12) + { + 0x0A, + 0x0F, + 0x00, + 0x01, + 0x02, + 0x03, + 0x04, + 0x05, + 0x06, + 0x07, + 0x08, + 0x09, + 0x0A, + 0x0B, + 0x0C, + 0x0D, + 0x0E, + 0x0F + }) + } + Method (_BCM, 1, NotSerialized) + { + \_SB.PCI0.LPCB.EC.BKLG = Arg0 + } + Method (_BQC, 0, NotSerialized) + { + Return (\_SB.PCI0.LPCB.EC.BKLG) + } + } +} diff --git a/src/mainboard/51nb/x210/acpi/mainboard.asl b/src/mainboard/51nb/x210/acpi/mainboard.asl new file mode 100644 index 0000000..efe0e8d --- /dev/null +++ b/src/mainboard/51nb/x210/acpi/mainboard.asl @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Google LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB) +{ + Device (LID0) + { + Name (_HID, EisaId ("PNP0C0D")) + + Method (_STA) + { + Return (0xF) + } + + Method (_LID) + { + Return (\LIDS) + } + } + + Device (PWRB) + { + Name (_HID, EisaId ("PNP0C0C")) + + Method (_STA) + { + Return (0xF) + } + + Name (_PRW, Package () { 27, 4 }) + } + + Device (SLPB) + { + Name (_HID, EisaId ("PNP0C0E")) + + Method (_STA) + { + Return (0xF) + } + } +} diff --git a/src/mainboard/51nb/x210/acpi/platform.asl b/src/mainboard/51nb/x210/acpi/platform.asl new file mode 100644 index 0000000..7ea85b6 --- /dev/null +++ b/src/mainboard/51nb/x210/acpi/platform.asl @@ -0,0 +1,86 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2014-2019 Google LLC + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Enable ACPI _SWS methods */ +#include <soc/intel/common/acpi/acpi_wake_source.asl> + +/* The APM port can be used for generating software SMIs */ + +OperationRegion (APMP, SystemIO, 0xb2, 2) +Field (APMP, ByteAcc, NoLock, Preserve) +{ + APMC, 8, // APM command + APMS, 8 // APM status +} + +/* Port 80 POST */ + +OperationRegion (POST, SystemIO, 0x80, 1) +Field (POST, ByteAcc, Lock, Preserve) +{ + DBG0, 8 +} + +/* IO-Trap at 0x800. + * This is the ACPI->SMI communication interface. + */ +OperationRegion (IO_T, SystemIO, 0x800, 0x10) +Field (IO_T, ByteAcc, NoLock, Preserve) +{ + Offset (0x8), + TRP0, 8 /* IO-Trap at 0x808 */ +} + +/* SMI I/O Trap */ +Method (TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) // SMI Function + Store (0, TRP0) // Generate trap + Return (SMIF) // Return value of SMI handler +} + +/* + * The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC. + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local Apic/IOAPIC configuration. + */ + +Method (_PIC, 1) +{ + /* Remember the OS' IRQ routing choice. */ + Store (Arg0, PICM) +} + +/* + * The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method (_PTS, 1) +{ +} + +/* The _WAK method is called on system wakeup */ + +Method (_WAK, 1) +{ + Store(\_SB.PCI0.LPCB.EC.LIDC, \LIDS) + Store(\_SB.PCI0.LPCB.EC.ACIN, \PWRS) + Return (Package (){ 0, 0 }) +} diff --git a/src/mainboard/51nb/x210/acpi/superio.asl b/src/mainboard/51nb/x210/acpi/superio.asl new file mode 100644 index 0000000..92c272e --- /dev/null +++ b/src/mainboard/51nb/x210/acpi/superio.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/51nb/x210/acpi_tables.c b/src/mainboard/51nb/x210/acpi_tables.c new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/51nb/x210/acpi_tables.c diff --git a/src/mainboard/51nb/x210/board_info.txt b/src/mainboard/51nb/x210/board_info.txt new file mode 100644 index 0000000..65c4608 --- /dev/null +++ b/src/mainboard/51nb/x210/board_info.txt @@ -0,0 +1,8 @@ +Vendor name: 51NB +Board name: Thinkpad X210 +Category: laptop +ROM package: SOIC8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2017 diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb new file mode 100644 index 0000000..9463470 --- /dev/null +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -0,0 +1,222 @@ +chip soc/intel/skylake + + # Enable deep Sx states + register "deep_s3_enable_ac" = "0" + register "deep_s3_enable_dc" = "0" + register "deep_s5_enable_ac" = "0" + register "deep_s5_enable_dc" = "0" + register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" + + register "eist_enable" = "1" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_C" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + register "gen1_dec" = "0x000c0081" + register "gen2_dec" = "0x000c0681" + register "gen3_dec" = "0x000c1641" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # Disable DPTF + register "dptf_enable" = "0" + + # FSP Configuration + register "ProbelessTrace" = "0" + register "EnableLan" = "0" + register "EnableSata" = "1" + register "SataSalpSupport" = "0" + register "SataMode" = "0" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsEnable[2]" = "1" + register "SataPortsDevSlp[0]" = "0" + register "SataPortsDevSlp[2]" = "0" + register "SataSpeedLimit" = "2" + register "EnableAzalia" = "1" + register "DspEnable" = "0" + register "IoBufferOwnership" = "0" + register "EnableTraceHub" = "0" + register "SsicPortEnable" = "0" + register "SmbusEnable" = "1" + register "Cio2Enable" = "0" + register "ScsEmmcEnabled" = "0" + register "ScsEmmcHs400Enabled" = "0" + register "ScsSdCardEnabled" = "0" + register "PttSwitch" = "0" + register "SkipExtGfxScan" = "1" + register "Device4Enable" = "1" + register "HeciEnabled" = "1" + register "SaGv" = "3" + register "PmConfigSlpS3MinAssert" = "2" # 50ms + register "PmConfigSlpS4MinAssert" = "1" # 1s + register "PmConfigSlpSusMinAssert" = "3" # 500ms + register "PmConfigSlpAMinAssert" = "3" # 2s + register "PmTimerDisabled" = "0" + + register "serirq_mode" = "SERIRQ_CONTINUOUS" + + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + # VR Settings Configuration for 4 Domains + #+----------------+-----------+-----------+-------------+----------+ + #| Domain/Setting | SA | IA | GT Unsliced | GT | + #+----------------+-----------+-----------+-------------+----------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax | 6A | 64A | 31A | 31A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #+----------------+-----------+-----------+-------------+----------+ + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(4), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 0, + .psi4enable = 0, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(6), + .voltage_limit = 1520, + .ac_loadline = 1030, + .dc_loadline = 1030, + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 0, + .psi4enable = 0, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(64), + .voltage_limit = 1520, + .ac_loadline = 240, + .dc_loadline = 240, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 0, + .psi4enable = 0, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(31), + .voltage_limit = 1520, + .ac_loadline = 310, + .dc_loadline = 310, + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 0, + .psi4enable = 0, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(31), + .voltage_limit = 1520, + .ac_loadline = 310, + .dc_loadline = 310, + }" + + # Enable Root Ports 1, 4 and 9 + register "PcieRpEnable[2]" = "1" + register "PcieRpLtrEnable[2]" = "1" + register "PcieRpEnable[3]" = "1" + register "PcieRpLtrEnable[3]" = "1" + register "PcieRpEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + + register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-A Port (left) + register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-A Port (left) + register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" # Type-A Port (right) + register "usb2_ports[6]" = "USB2_PORT_FLEX(OC2)" # webcam + register "usb2_ports[7]" = "USB2_PORT_FLEX(OC2)" # WiFi PCIe port USB + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (left) + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (left) + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (right) + + # PL1 override 25W + register "tdp_pl1_override" = "25" + + # PL2 override 44W + register "tdp_pl2_override" = "44" + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + + # Lock Down + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 14.0 on end # USB xHCI + device pci 14.1 on end # USB xDCI (OTG) + device pci 14.2 on end # Thermal Subsystem + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 on end # SATA + device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 on end # PCI Express Port 4 + device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1f.0 on + chip ec/51nb + device pnp 0c09.0 on end + end + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end # LPC Interface + device pci 1f.1 off end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/51nb/x210/dsdt.asl b/src/mainboard/51nb/x210/dsdt.asl new file mode 100644 index 0000000..f651532 --- /dev/null +++ b/src/mainboard/51nb/x210/dsdt.asl @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015-2019 Google LLC + * Copyright (C) 2015 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x05, // DSDT revision: ACPI v5.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + #include "acpi/platform.asl" + + // global NVS and variables + #include <soc/intel/skylake/acpi/globalnvs.asl> + + // CPU + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + + } + + // Chipset specific sleep states + #include <soc/intel/skylake/acpi/sleepstates.asl> + + // Mainboard specific + #include "acpi/mainboard.asl" + + // Graphics display + #include "acpi/graphics.asl" +} diff --git a/src/mainboard/51nb/x210/gpio.h b/src/mainboard/51nb/x210/gpio.h new file mode 100644 index 0000000..2a00d54 --- /dev/null +++ b/src/mainboard/51nb/x210/gpio.h @@ -0,0 +1,194 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +#ifndef __ACPI__ + +/* Pad configuration in ramstage. */ +static const struct pad_config gpio_table[] = { +/* RCIN# */_PAD_CFG_STRUCT(GPP_A0, 0x44000702, 0x0), +/* LAD0 */_PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x3c00), +/* LAD1 */_PAD_CFG_STRUCT(GPP_A2, 0x44000702, 0x3c00), +/* LAD2 */_PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x3c00), +/* LAD3 */_PAD_CFG_STRUCT(GPP_A4, 0x44000702, 0x3c00), +/* LFRAME# */_PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x0), +/* SERIRQ */_PAD_CFG_STRUCT(GPP_A6, 0x44000702, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_A7, 0x44000201, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_A8, 0x44000300, 0x3000), +/* CLKOUT_LPC0 */_PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x1000), +/* CLKOUT_LPC1 */_PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x1000), +/* GPIO */_PAD_CFG_STRUCT(GPP_A11, 0x44000200, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_A12, 0x4000200, 0x0), +/* SUSWARN#/SUSPWRDNACK */_PAD_CFG_STRUCT(GPP_A13, 0x44000700, 0x0), +/* SUS_STAT# */_PAD_CFG_STRUCT(GPP_A14, 0x44000700, 0x0), +/* SUS_ACK# */_PAD_CFG_STRUCT(GPP_A15, 0x44000702, 0x3000), +/* CLKOUT_48 */_PAD_CFG_STRUCT(GPP_A16, 0x44000500, 0x0), +/* ISH_GP7 */_PAD_CFG_STRUCT(GPP_A17, 0x44000700, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_A18, 0x44000300, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_A19, 0x44000300, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_A20, 0x44000300, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_A21, 0x44000300, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_A22, 0x44000201, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_A23, 0x44000100, 0x1000), +/* n/a */_PAD_CFG_STRUCT(GPP_B0, 0x44000700, 0x0), +/* n/a */_PAD_CFG_STRUCT(GPP_B1, 0x44000700, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_B2, 0x44000300, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_B3, 0x84000102, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_B4, 0x44000201, 0x0), +/* SRCCLKREQ0# */_PAD_CFG_STRUCT(GPP_B5, 0x44000700, 0x0), +/* SRCCLKREQ1# */_PAD_CFG_STRUCT(GPP_B6, 0x44000700, 0x0), +/* SRCCLKREQ2# */_PAD_CFG_STRUCT(GPP_B7, 0x44000702, 0x0), +/* SRCCLKREQ3# */_PAD_CFG_STRUCT(GPP_B8, 0x44000702, 0x0), +/* SRCCLKREQ4# */_PAD_CFG_STRUCT(GPP_B9, 0x44000700, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_B10, 0x44000102, 0x0), +/* n/a */_PAD_CFG_STRUCT(GPP_B11, 0x44000700, 0x0), +/* SLP_S0# */_PAD_CFG_STRUCT(GPP_B12, 0x44000700, 0x0), +/* PLTRST# */_PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_B14, 0x44000201, 0x1000), +/* GPIO */_PAD_CFG_STRUCT(GPP_B15, 0x44000300, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_B16, 0x84800102, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_B17, 0x84800102, 0x3000), +/* GPIO */_PAD_CFG_STRUCT(GPP_B18, 0x84800102, 0x3000), +/* GPIO */_PAD_CFG_STRUCT(GPP_B19, 0x44000300, 0x0), +/* GSPI1_CLK */_PAD_CFG_STRUCT(GPP_B20, 0x44000700, 0x1000), +/* GSPI1_MISO */_PAD_CFG_STRUCT(GPP_B21, 0x44000700, 0x1000), +/* GSPIO_MOSI */_PAD_CFG_STRUCT(GPP_B22, 0x44000700, 0x1000), +/* GPIO */_PAD_CFG_STRUCT(GPP_B23, 0x44000201, 0x1000), +/* SMBCLK */_PAD_CFG_STRUCT(GPP_C0, 0x44000702, 0x0), +/* SMBDATA */_PAD_CFG_STRUCT(GPP_C1, 0x44000702, 0x1000), +/* GPIO */_PAD_CFG_STRUCT(GPP_C2, 0x44000201, 0x1000), +/* SML0CLK */_PAD_CFG_STRUCT(GPP_C3, 0x44000702, 0x3000), +/* SML0DATA */_PAD_CFG_STRUCT(GPP_C4, 0x44000702, 0x3000), +/* GPIO */_PAD_CFG_STRUCT(GPP_C5, 0x44800100, 0x1000), +/* RESERVED */_PAD_CFG_STRUCT(GPP_C6, 0xffffffff, 0xffffff00), +/* RESERVED */_PAD_CFG_STRUCT(GPP_C7, 0xffffffff, 0xffffff00), +/* UART0_RXD */_PAD_CFG_STRUCT(GPP_C8, 0x44000702, 0x3000), +/* UART0_TXD */_PAD_CFG_STRUCT(GPP_C9, 0x44000700, 0x0), +/* UART0_RTS# */_PAD_CFG_STRUCT(GPP_C10, 0x44000700, 0x0), +/* UART0_CTS# */_PAD_CFG_STRUCT(GPP_C11, 0x44000702, 0x0), +/* UART1_RXD */_PAD_CFG_STRUCT(GPP_C12, 0x44000702, 0x0), +/* UART1_TXD */_PAD_CFG_STRUCT(GPP_C13, 0x44000700, 0x0), +/* UART1_RTS# */_PAD_CFG_STRUCT(GPP_C14, 0x44000700, 0x0), +/* UART1_CTS# */_PAD_CFG_STRUCT(GPP_C15, 0x44000702, 0x0), +/* I2C0_SDA */_PAD_CFG_STRUCT(GPP_C16, 0x44000702, 0x3000), +/* I2C0_SCL */_PAD_CFG_STRUCT(GPP_C17, 0x44000702, 0x3000), +/* I2C1_SDA */_PAD_CFG_STRUCT(GPP_C18, 0x44000702, 0x3000), +/* I2C1_SCL */_PAD_CFG_STRUCT(GPP_C19, 0x44000702, 0x3000), +/* UART2_RXD */_PAD_CFG_STRUCT(GPP_C20, 0x44000702, 0x3000), +/* UART2_TXD */_PAD_CFG_STRUCT(GPP_C21, 0x44000700, 0x0), +/* UART2_RTS# */_PAD_CFG_STRUCT(GPP_C22, 0x44000700, 0x0), +/* UART2_CTS# */_PAD_CFG_STRUCT(GPP_C23, 0x44000702, 0x0), +/* n/a */_PAD_CFG_STRUCT(GPP_D0, 0x44000700, 0x0), +/* n/a */_PAD_CFG_STRUCT(GPP_D1, 0x44000700, 0x0), +/* n/a */_PAD_CFG_STRUCT(GPP_D2, 0x44000700, 0x0), +/* n/a */_PAD_CFG_STRUCT(GPP_D3, 0x44000700, 0x0), +/* ISH_I2C2_SDA */_PAD_CFG_STRUCT(GPP_D4, 0x44000700, 0x0), +/* I2S_SFRM */_PAD_CFG_STRUCT(GPP_D5, 0x44000702, 0x3000), +/* I2S_TXD */_PAD_CFG_STRUCT(GPP_D6, 0x44000702, 0x3000), +/* I2S_RXD */_PAD_CFG_STRUCT(GPP_D7, 0x44000702, 0x3000), +/* I2S_SCLK */_PAD_CFG_STRUCT(GPP_D8, 0x44000702, 0x3000), +/* GPIO */_PAD_CFG_STRUCT(GPP_D9, 0x44000102, 0x3000), +/* GPIO */_PAD_CFG_STRUCT(GPP_D10, 0x44000102, 0x3000), +/* GPIO */_PAD_CFG_STRUCT(GPP_D11, 0x44000102, 0x3000), +/* GPIO */_PAD_CFG_STRUCT(GPP_D12, 0x44000102, 0x3000), +/* ISH_UART0_RXD */_PAD_CFG_STRUCT(GPP_D13, 0x44000702, 0x3000), +/* ISH_UART0_TXD */_PAD_CFG_STRUCT(GPP_D14, 0x44000700, 0x3000), +/* ISH_UART0_RTS# */_PAD_CFG_STRUCT(GPP_D15, 0x44000700, 0x0), +/* ISH_UART0_CTS# */_PAD_CFG_STRUCT(GPP_D16, 0x44000702, 0x0), +/* DMIC_CLK1 */_PAD_CFG_STRUCT(GPP_D17, 0x44000700, 0x0), +/* DMIC_DATA1 */_PAD_CFG_STRUCT(GPP_D18, 0x44000700, 0x1000), +/* DMIC_CLK0 */_PAD_CFG_STRUCT(GPP_D19, 0x44000700, 0x0), +/* DMIC_DATA0 */_PAD_CFG_STRUCT(GPP_D20, 0x44000700, 0x1000), +/* n/a */_PAD_CFG_STRUCT(GPP_D21, 0x44000700, 0x0), +/* n/a */_PAD_CFG_STRUCT(GPP_D22, 0x44000700, 0x0), +/* ISH_I2C2_SCL */_PAD_CFG_STRUCT(GPP_D23, 0x44000700, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_E0, 0x44000200, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_E1, 0x44800102, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_E2, 0x44000300, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_E3, 0x44000103, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_E4, 0x44000300, 0x0), +/* SATA_DEVSLP1 */_PAD_CFG_STRUCT(GPP_E5, 0x4000700, 0x0), +/* SATA_DEVSLP2 */_PAD_CFG_STRUCT(GPP_E6, 0x4000700, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_E7, 0x44000300, 0x0), +/* SATA_LED# */_PAD_CFG_STRUCT(GPP_E8, 0x44000700, 0x0), +/* USB_OC0# */_PAD_CFG_STRUCT(GPP_E9, 0x44000702, 0x0), +/* USB_OC1# */_PAD_CFG_STRUCT(GPP_E10, 0x44000702, 0x0), +/* USB_OC2# */_PAD_CFG_STRUCT(GPP_E11, 0x44000702, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_E12, 0x44000300, 0x0), +/* n/a */_PAD_CFG_STRUCT(GPP_E13, 0x44000700, 0x0), +/* n/a */_PAD_CFG_STRUCT(GPP_E14, 0x44000700, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_E15, 0x80880102, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_E16, 0x84000102, 0x0), +/* n/a */_PAD_CFG_STRUCT(GPP_E17, 0x44000702, 0x0), +/* n/a */_PAD_CFG_STRUCT(GPP_E18, 0x44000700, 0x3000), +/* n/a */_PAD_CFG_STRUCT(GPP_E19, 0x44000700, 0x1000), +/* n/a */_PAD_CFG_STRUCT(GPP_E20, 0x44000702, 0x3000), +/* n/a */_PAD_CFG_STRUCT(GPP_E21, 0x44000702, 0x1000), +/* GPIO */_PAD_CFG_STRUCT(GPP_E22, 0x44000000, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_E23, 0x44000201, 0x1000), +/* BATLOW# */_PAD_CFG_STRUCT(GPD0, 0x4000702, 0x3000), +/* ACPRESENT */_PAD_CFG_STRUCT(GPD1, 0x4000702, 0x0), +/* LAN_WAKE# */_PAD_CFG_STRUCT(GPD2, 0x4000602, 0x3c00), +/* PWRBTN# */_PAD_CFG_STRUCT(GPD3, 0x4000702, 0x3000), +/* SLP_S3# */_PAD_CFG_STRUCT(GPD4, 0x4000700, 0x0), +/* SLP_S4# */_PAD_CFG_STRUCT(GPD5, 0x4000700, 0x0), +/* SLP_A# */_PAD_CFG_STRUCT(GPD6, 0x4000700, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPD7, 0x4000301, 0x0), +/* SUSCLK */_PAD_CFG_STRUCT(GPD8, 0x4000700, 0x0), +/* SLP_WLAN# */_PAD_CFG_STRUCT(GPD9, 0x4000700, 0x0), +/* SLP_S5# */_PAD_CFG_STRUCT(GPD10, 0x4000700, 0x0), +/* LANPHYPC */_PAD_CFG_STRUCT(GPD11, 0x4000700, 0x0), +/* SATAXPCIE3 */_PAD_CFG_STRUCT(GPP_F0, 0x44000700, 0x0), +/* SATAXPCIE4 */_PAD_CFG_STRUCT(GPP_F1, 0x44000700, 0x0), +/* SATAXPCIE5 */_PAD_CFG_STRUCT(GPP_F2, 0x44000700, 0x0), +/* SATAXPCIE6 */_PAD_CFG_STRUCT(GPP_F3, 0x44000700, 0x0), +/* SATAXPCIE7 */_PAD_CFG_STRUCT(GPP_F4, 0x44000702, 0x2003000), +/* SATA_DEVSLP3 */_PAD_CFG_STRUCT(GPP_F5, 0x44000702, 0x2003000), +/* SATA_DEVSLP4 */_PAD_CFG_STRUCT(GPP_F6, 0x44000702, 0x2003000), +/* SATA_DEVSLP5 */_PAD_CFG_STRUCT(GPP_F7, 0x44000702, 0x2003000), +/* SATA_DEVSLP6 */_PAD_CFG_STRUCT(GPP_F8, 0x44000702, 0x2003000), +/* SATA_DEVSLP7 */_PAD_CFG_STRUCT(GPP_F9, 0x44000702, 0x2003000), +/* n/a */_PAD_CFG_STRUCT(GPP_F10, 0x44000b02, 0x2003000), +/* n/a */_PAD_CFG_STRUCT(GPP_F11, 0x44000b02, 0x2003000), +/* SATA_SDATAOUT1 */_PAD_CFG_STRUCT(GPP_F12, 0x44000700, 0x0), +/* SATA_SDATAOUT2 */_PAD_CFG_STRUCT(GPP_F13, 0x44000700, 0x0), +/* n/a */_PAD_CFG_STRUCT(GPP_F14, 0x44000700, 0x0), +/* USB_OC4# */_PAD_CFG_STRUCT(GPP_F15, 0x44000700, 0x0), +/* USB_OC5# */_PAD_CFG_STRUCT(GPP_F16, 0x44000700, 0x0), +/* USB_OC6# */_PAD_CFG_STRUCT(GPP_F17, 0x44000700, 0x0), +/* USB_OC7# */_PAD_CFG_STRUCT(GPP_F18, 0x44000700, 0x0), +/* eDP_VDDEN */_PAD_CFG_STRUCT(GPP_F19, 0x44000700, 0x0), +/* eDP_BKLTEN */_PAD_CFG_STRUCT(GPP_F20, 0x44000700, 0x0), +/* eDP_BKLTCTL */_PAD_CFG_STRUCT(GPP_F21, 0x44000700, 0x0), +/* n/a */_PAD_CFG_STRUCT(GPP_F22, 0x44000700, 0x0), +/* GPIO */_PAD_CFG_STRUCT(GPP_F23, 0x44000102, 0x0), +/* FAN_TACH_0 */_PAD_CFG_STRUCT(GPP_G0, 0x44000700, 0x0), +/* FAN_TACH_1 */_PAD_CFG_STRUCT(GPP_G1, 0x44000700, 0x0), +/* FAN_TACH_2 */_PAD_CFG_STRUCT(GPP_G2, 0x44000700, 0x0), +/* FAN_TACH_3 */_PAD_CFG_STRUCT(GPP_G3, 0x44000700, 0x0), +/* FAN_TACH_4 */_PAD_CFG_STRUCT(GPP_G4, 0x44000700, 0x0), +/* FAN_TACH_5 */_PAD_CFG_STRUCT(GPP_G5, 0x44000702, 0x0), +/* FAN_TACH_6 */_PAD_CFG_STRUCT(GPP_G6, 0x44000700, 0x0), +/* FAN_TACH_7 */_PAD_CFG_STRUCT(GPP_G7, 0x44000700, 0x1000), +}; + +#endif + +#endif diff --git a/src/mainboard/51nb/x210/hda_verb.c b/src/mainboard/51nb/x210/hda_verb.c new file mode 100644 index 0000000..e8eecdf --- /dev/null +++ b/src/mainboard/51nb/x210/hda_verb.c @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation + * (Written by Naresh G Solanki <naresh.solanki(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootstate.h> +#include <chip.h> +#include <console/console.h> +#include <device/azalia_device.h> +#include <soc/intel/common/hda_verb.h> +#include <soc/pci_devs.h> + +#include "hda_verb.h" + +static void codecs_init(u8 *base, u32 codec_mask) +{ + int i; + + /* Can support up to 4 codecs */ + for (i = 3; i >= 0; i--) { + if (codec_mask & (1 << i)) + hda_codec_init(base, i, cim_verb_data_size, + cim_verb_data); + } + + if (pc_beep_verbs_size) + hda_codec_write(base, pc_beep_verbs_size, pc_beep_verbs); +} + +static void mb_hda_codec_init(void *unused) +{ + static struct soc_intel_skylake_config *config; + u8 *base; + struct resource *res; + u32 codec_mask; + struct device *dev; + + dev = SA_DEV_ROOT; + /* Check if HDA is enabled, else return */ + if (dev == NULL || dev->chip_info == NULL) + return; + + config = dev->chip_info; + + /* + * IoBufferOwnership 0:HD-A Link, 1:Shared HD-A Link and I2S Port, + * 3:I2S Ports. In HDA mode where codec need to be programmed with + * verb table + */ + if (config->IoBufferOwnership == 3) + return; + + /* Find base address */ + dev = dev_find_slot(0, PCH_DEVFN_HDA); + if (dev == NULL) + return; + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (!res) + return; + + base = res2mmio(res, 0, 0); + printk(BIOS_DEBUG, "HDA: base = %p\n", base); + + codec_mask = hda_codec_detect(base); + + if (codec_mask) { + printk(BIOS_DEBUG, "HDA: codec_mask = %02x\n", codec_mask); + codecs_init(base, codec_mask); + } +} + +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, mb_hda_codec_init, NULL); diff --git a/src/mainboard/51nb/x210/hda_verb.h b/src/mainboard/51nb/x210/hda_verb.h new file mode 100644 index 0000000..c721c25 --- /dev/null +++ b/src/mainboard/51nb/x210/hda_verb.h @@ -0,0 +1,76 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016-2019 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef HDA_VERB_H +#define HDA_VERB_H + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x14f15069, /* Codec Vendor / Device ID: Conexant CX20585 */ + 0x17aa2155, /* Subsystem ID */ + 0x0000000c, /* Number of jacks (NID entries) */ + + 0x0017ff00, /* Function Reset */ + 0x0017ff00, /* Double Function Reset */ + 0x0017ff00, + 0x0017ff00, + + /* Bits 31:28 - Codec Address */ + /* Bits 27:20 - NID */ + /* Bits 19:8 - Verb ID */ + /* Bits 7:0 - Payload */ + + /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x17aa2155 */ + AZALIA_SUBVENDOR(0x0, 0x17aa2155), + + /* Pin Widget Verb Table */ + + /* Pin Complex (NID 0x19) */ + AZALIA_PIN_CFG(0x0, 0x19, 0x042140f0), + + /* Pin Complex (NID 0x1A) */ + AZALIA_PIN_CFG(0x0, 0x1a, 0x61a190f0), + + /* Pin Complex (NID 0x1B) */ + AZALIA_PIN_CFG(0x0, 0x1b, 0x04a190f0), + + /* Pin Complex (NID 0x1C) */ + AZALIA_PIN_CFG(0x0, 0x1c, 0x612140f0), + + /* Pin Complex (NID 0x1D) */ + AZALIA_PIN_CFG(0x0, 0x1d, 0x601700f0), + + /* Pin Complex (NID 0x1E) */ + AZALIA_PIN_CFG(0x0, 0x1e, 0x40f001f0), + + /* Pin Complex (NID 0x1F) */ + AZALIA_PIN_CFG(0x0, 0x1f, 0x901701f0), + + /* Pin Complex (NID 0x20) */ + AZALIA_PIN_CFG(0x0, 0x1B, 0x40f001f0), + + /* Pin Complex (NID 0x22) */ + AZALIA_PIN_CFG(0x0, 0x22, 0x40f001f0), + + /* Pin Complex (NID 0x23) */ + AZALIA_PIN_CFG(0x0, 0x23, 0x90a601f0), +}; + +const u32 pc_beep_verbs[] = { +}; +AZALIA_ARRAY_SIZES; +#endif diff --git a/src/mainboard/51nb/x210/mainboard.c b/src/mainboard/51nb/x210/mainboard.c new file mode 100644 index 0000000..8e9266d --- /dev/null +++ b/src/mainboard/51nb/x210/mainboard.c @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Purism SPC + * Copyright (C) 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbfs.h> +#include <device/device.h> +#include <intelblocks/lpc_lib.h> +#include <string.h> +#include <smbios.h> + +#define MAX_SERIAL_LENGTH 0x100 + +const char *smbios_mainboard_serial_number(void) +{ + static char serial_number[MAX_SERIAL_LENGTH + 1] = {0}; + struct cbfsf file; + + if (serial_number[0] != 0) + return serial_number; + + if (cbfs_boot_locate(&file, "serial_number", NULL) == 0) { + struct region_device cbfs_region; + size_t serial_len; + + cbfs_file_data(&cbfs_region, &file); + + serial_len = region_device_sz(&cbfs_region); + if (serial_len <= MAX_SERIAL_LENGTH) { + if (rdev_readat(&cbfs_region, serial_number, 0, + serial_len) == serial_len) { + serial_number[serial_len] = 0; + return serial_number; + } + } + } + + strncpy(serial_number, CONFIG_MAINBOARD_SERIAL_NUMBER, + MAX_SERIAL_LENGTH); + + return serial_number; +} + +static void mainboard_enable(struct device *dev) +{ + /* Route 0x4e/4f to LPC */ + lpc_enable_fixed_io_ranges(LPC_IOE_EC_4E_4F); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/51nb/x210/pei_data.c b/src/mainboard/51nb/x210/pei_data.c new file mode 100644 index 0000000..0be917d --- /dev/null +++ b/src/mainboard/51nb/x210/pei_data.c @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation + * Copyright (C) 2017 Purism SPC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <soc/pei_data.h> +#include <soc/pei_wrapper.h> +#include "pei_data.h" + +void mainboard_fill_dq_map_data(void *dq_map_ptr) +{ + /* DQ byte map */ + const u8 dq_map[2][12] = { + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, + { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, + 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; + memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); +} + +void mainboard_fill_dqs_map_data(void *dqs_map_ptr) +{ + /* DQS CPU<>DRAM map */ + const u8 dqs_map[2][8] = { + { 0, 1, 3, 2, 4, 5, 6, 7 }, + { 1, 0, 4, 5, 2, 3, 6, 7 } }; + memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map)); +} + +void mainboard_fill_rcomp_res_data(void *rcomp_ptr) +{ + /* Rcomp resistor */ + const u16 RcompResistor[3] = { 121, 81, 100 }; + memcpy(rcomp_ptr, RcompResistor, + sizeof(RcompResistor)); +} + +void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) +{ + /* Rcomp target */ + const u16 RcompTarget[5] = { 100, 40, 20, 20, 26 }; + memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); +} + +void mainboard_fill_pei_data(struct pei_data *pei_data) +{ + mainboard_fill_dq_map_data(&pei_data->dq_map); + mainboard_fill_dqs_map_data(&pei_data->dqs_map); + mainboard_fill_rcomp_res_data(&pei_data->RcompResistor); + mainboard_fill_rcomp_strength_data(&pei_data->RcompTarget); +} diff --git a/src/mainboard/51nb/x210/pei_data.h b/src/mainboard/51nb/x210/pei_data.h new file mode 100644 index 0000000..320d980 --- /dev/null +++ b/src/mainboard/51nb/x210/pei_data.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Purism SPC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _MAINBOARD_PEI_DATA_H_ +#define _MAINBOARD_PEI_DATA_H_ + +void mainboard_fill_dq_map_data(void *dq_map_ptr); +void mainboard_fill_dqs_map_data(void *dqs_map_ptr); +void mainboard_fill_rcomp_res_data(void *rcomp_ptr); +void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr); + +#endif diff --git a/src/mainboard/51nb/x210/ramstage.c b/src/mainboard/51nb/x210/ramstage.c new file mode 100644 index 0000000..7888c39 --- /dev/null +++ b/src/mainboard/51nb/x210/ramstage.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corporation + * Copyright (C) 2015-2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/ramstage.h> +#include "gpio.h" + +void mainboard_silicon_init_params(FSP_SIL_UPD *params) +{ + /* Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/51nb/x210/romstage.c b/src/mainboard/51nb/x210/romstage.c new file mode 100644 index 0000000..98270f0 --- /dev/null +++ b/src/mainboard/51nb/x210/romstage.c @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2015-2019 Google LLC + * Copyright (C) 2015 Intel Corporation + * Copyright (C) 2017 Purism SPC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <string.h> +#include <assert.h> +#include <soc/romstage.h> +#include <spd_bin.h> +#include <arch/io.h> +#include "pei_data.h" + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg; + struct spd_block blk = { + .addr_map = { 0x50, 0x52 }, + }; + + mem_cfg = &mupd->FspmConfig; + + get_spd_smbus(&blk); + dump_spd_info(&blk); + assert(blk.spd_array[0][0] != 0); + + mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0); + mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0); + mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); + mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); + + mem_cfg->DqPinsInterleaved = TRUE; + mem_cfg->MemorySpdDataLen = blk.len; + mem_cfg->MemorySpdPtr00 = (uintptr_t) blk.spd_array[0]; + mem_cfg->MemorySpdPtr10 = (uintptr_t) blk.spd_array[1]; +} diff --git a/util/51nb/51nb_ec_insert.c b/util/51nb/51nb_ec_insert.c new file mode 100644 index 0000000..0f5e204 --- /dev/null +++ b/util/51nb/51nb_ec_insert.c @@ -0,0 +1,99 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Iru Cai <mytbk920423(a)gmail.com> + * Copyright (C) 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdio.h> +#include <stdlib.h> + +static void usage(const char *s) +{ + printf("insert firmware blobs:\n\t" + "%s <rom file> <fw> <fw offset>\n\n", + s); + exit(1); +} + +static void FseekEnd(FILE *fp, long o) +{ + if (fseek(fp, o, SEEK_END) != 0) { + puts("fseek() error!\n"); + exit(1); + } +} + +static long negoffset(long a, long romsz) +{ + if (a > 0) { + if (a & 0x80000000) /* the address in memory, and sizeof(long) + is 8 */ + return a - 0x100000000; + else /* the file offset */ + return a - romsz; + } else { + return a; + } +} + +int main(int argc, char *argv[]) +{ + FILE *fp, *fw; + long offset; + + if (argc != 4) + usage(argv[0]); + + fp = fopen(argv[1], "rb+"); + if (fp == NULL) { + puts("Error opening firmware image!"); + exit(1); + } + + fw = fopen(argv[2], "rb"); + offset = strtoul(argv[3], NULL, 0); + if (fw == NULL) { + puts("Error opening file!"); + exit(1); + } + + if (offset & 0xf) { + puts("The offsets must be aligned to 0x100"); + exit(1); + } + + long romsz; + FseekEnd(fp, -1); + romsz = ftell(fp) + 1; + printf("size of %s: 0x%lx\n", argv[1], romsz); + + if (romsz & 0xff) { + puts("The ROM size must be multiple of 0x100"); + exit(1); + } + + offset = negoffset(offset, romsz); + + puts(""); + + /* write fw1 and fw2 */ + char c; + FseekEnd(fp, offset); + printf("writing to 0x%lx\n", ftell(fp)); + while (fread(&c, 1, 1, fw) == 1) { + fwrite(&c, 1, 1, fp); + } + fclose(fw); + fclose(fp); + return 0; +} diff --git a/util/51nb/Makefile b/util/51nb/Makefile new file mode 100644 index 0000000..b6c13d6 --- /dev/null +++ b/util/51nb/Makefile @@ -0,0 +1,12 @@ +obj = 51nb_ec_insert +HOSTCC := $(if $(shell type gcc 2>/dev/null),gcc,cc) + +all: $(obj) + +%: %.c + $(HOSTCC) -Wall -o $@ $< + +clean: + rm -f 51nb_ec_insert + +.PHONY: all clean -- To view, visit https://review.coreboot.org/c/coreboot/+/32531 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If74621e76d703f629b54f1feb1acfc95cc72d183 Gerrit-Change-Number: 32531 Gerrit-PatchSet: 1 Gerrit-Owner: Matthew Garrett <mjg59(a)google.com> Gerrit-MessageType: newchange

1 week, 6 days

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Change in ...coreboot[master]: intel/skylake: nhlt: Add 24 bit blobs for Max98373

by Jenny Tc (Code Review)

Jenny Tc has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31635 Change subject: intel/skylake: nhlt: Add 24 bit blobs for Max98373 ...................................................................... intel/skylake: nhlt: Add 24 bit blobs for Max98373 Enable 24 bit nhlt blobs and remove 16 bit blobs. 16 bit and 24 bit blobs cannot be supported together since the OS NHLT parsing relies on container bit format. The container bit format for 16 and 24 bit capture are same (32) and putting both blobs in configs results in selecting the first blob. To enable 24 and 16 bit blobs together, the core nhlt parsing logic has to be changed which would impact SKL and KBL platforms. In order to minimize the impact, the 16 bit blob is removed considering that the machine driver for max98373 is expected to support only format due to topology configuration for 16 and 24 bit. BUG=b:110795132 BRANCH=none TEST=Verify playback after flashing CQ-DEPEND=*806750 Change-Id: I62cc109fb0aca9269736779a6ce80980b0571b78 Signed-off-by: Jenny TC <jenny.tc(a)intel.com> --- M src/soc/intel/skylake/nhlt/Makefile.inc M src/soc/intel/skylake/nhlt/max98373.c 2 files changed, 6 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/31635/1 diff --git a/src/soc/intel/skylake/nhlt/Makefile.inc b/src/soc/intel/skylake/nhlt/Makefile.inc index 5c8bd80..548747a 100644 --- a/src/soc/intel/skylake/nhlt/Makefile.inc +++ b/src/soc/intel/skylake/nhlt/Makefile.inc @@ -21,7 +21,6 @@ DMIC_4CH_48KHZ_32B = dmic-4ch-48khz-32b.bin NAU88L25 = nau88l25-2ch-48khz-24b.bin MAX98357_RENDER = max98357-render-2ch-48khz-24b.bin -MAX98373_RENDER_16B = max98373-render-2ch-48khz-16b.bin MAX98373_RENDER_24B = max98373-render-2ch-48khz-24b.bin MAX98927_RENDER_24B = max98927-render-2ch-48khz-24b.bin MAX98927_RENDER_16B = max98927-render-2ch-48khz-16b.bin diff --git a/src/soc/intel/skylake/nhlt/max98373.c b/src/soc/intel/skylake/nhlt/max98373.c index 0e3a413..a781943 100644 --- a/src/soc/intel/skylake/nhlt/max98373.c +++ b/src/soc/intel/skylake/nhlt/max98373.c @@ -25,35 +25,26 @@ .speaker_mask = SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT, .settings_file = "max98373-render-2ch-48khz-24b.bin", }, - /* 48 KHz 16-bits per sample. */ - { - .num_channels = 2, - .sample_freq_khz = 48, - .container_bits_per_sample = 16, - .valid_bits_per_sample = 16, - .speaker_mask = SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT, - .settings_file = "max98373-render-2ch-48khz-16b.bin", - } }; static const struct nhlt_format_config max98373_capture_formats[] = { - /* 48 KHz 16-bits per sample - Quad Channel. */ + /* 48 KHz 24-bits per sample - Quad Channel. */ { .num_channels = 4, .sample_freq_khz = 48, .container_bits_per_sample = 32, - .valid_bits_per_sample = 16, + .valid_bits_per_sample = 24, .speaker_mask = SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT, - .settings_file = "max98373-render-2ch-48khz-16b.bin", + .settings_file = "max98373-render-2ch-48khz-24b.bin", }, - /* 48 KHz 16-bits per sample - Stereo Channel */ + /* 48 KHz 24-bits per sample - Stereo Channel */ { .num_channels = 2, .sample_freq_khz = 48, .container_bits_per_sample = 32, - .valid_bits_per_sample = 16, + .valid_bits_per_sample = 24, .speaker_mask = SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT, - .settings_file = "max98373-render-2ch-48khz-16b.bin", + .settings_file = "max98373-render-2ch-48khz-24b.bin", }, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/31635 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62cc109fb0aca9269736779a6ce80980b0571b78 Gerrit-Change-Number: 31635 Gerrit-PatchSet: 1 Gerrit-Owner: Jenny Tc <jenny.tc(a)intel.com> Gerrit-MessageType: newchange

2 weeks

8
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Change in ...coreboot[master]: crossgcc: Upgrade GCC to 9.1.0

by HAOUAS Elyes (Code Review)

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32564 Change subject: crossgcc: Upgrade GCC to 9.1.0 ...................................................................... crossgcc: Upgrade GCC to 9.1.0 Change-Id: Id6f65548764654ae5539ac3c835853ea2fa1c5e0 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc D util/crossgcc/patches/gcc-8.3.0_nds32_ite.patch R util/crossgcc/patches/gcc-9.1.0_ada-musl_workaround.patch R util/crossgcc/patches/gcc-9.1.0_gnat.patch R util/crossgcc/patches/gcc-9.1.0_libgcc.patch D util/crossgcc/sum/gcc-8.3.0.tar.xz.cksum A util/crossgcc/sum/gcc-9.1.0.tar.xz.cksum 7 files changed, 2 insertions(+), 21,021 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/32564/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/32564 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6f65548764654ae5539ac3c835853ea2fa1c5e0 Gerrit-Change-Number: 32564 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 weeks, 1 day

8
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