Change in ...coreboot[master]: autoport: Add support for Haswell-LynxPoint platform
by Iru Cai (vimacs) (Code Review)
Hello Iru Cai,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/30890
to review the following change.
Change subject: autoport: Add support for Haswell-LynxPoint platform
......................................................................
autoport: Add support for Haswell-LynxPoint platform
It can now generate a buildable source for Clevo W650SZ.
TODO:
- Support Lynx Point LP (GPIO registers differ from non-LP)
- Use PCH HD-Audio in azilia instead of the CPU/Northbridge HD-Audio
Change-Id: I4f6e8c97b5122101de2f36bba8ba9f8ddd5b813a
Signed-off-by: Iru Cai <mytbk920423(a)gmail.com>
---
M util/autoport/azalia.go
A util/autoport/haswell.go
A util/autoport/lynxpoint.go
M util/autoport/main.go
4 files changed, 625 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/30890/1
diff --git a/util/autoport/azalia.go b/util/autoport/azalia.go
index c525189..3090dd0 100644
--- a/util/autoport/azalia.go
+++ b/util/autoport/azalia.go
@@ -62,4 +62,9 @@
RegisterPCI(0x8086, 0x1c20, azalia{})
/* C216/ivybridge */
RegisterPCI(0x8086, 0x1e20, azalia{})
+ /* Haswell */
+ RegisterPCI(0x8086, 0x0c0c, azalia{})
+ /* Lynx Point */
+ RegisterPCI(0x8086, 0x8c20, azalia{})
+ RegisterPCI(0x8086, 0x9c20, azalia{})
}
diff --git a/util/autoport/haswell.go b/util/autoport/haswell.go
new file mode 100644
index 0000000..d3c9d9f
--- /dev/null
+++ b/util/autoport/haswell.go
@@ -0,0 +1,119 @@
+package main
+
+type haswellmc struct {
+ variant string
+}
+
+func (i haswellmc) Scan(ctx Context, addr PCIDevData) {
+ inteltool := ctx.InfoSource.GetInteltool()
+
+ /* FIXME:XX Move this somewhere else. */
+ MainboardIncludes = append(MainboardIncludes, "drivers/intel/gma/int15.h")
+ MainboardEnable += (` /* FIXME: fix those values*/
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+`)
+
+ DevTree = DevTreeNode{
+ Chip: "northbridge/intel/haswell",
+ MissingParent: "northbridge",
+ Comment: "FIXME: check gfx.ndid and gfx.did",
+ Registers: map[string]string{
+ "gpu_dp_b_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 2) & 7),
+ "gpu_dp_c_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 10) & 7),
+ "gpu_dp_d_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 18) & 7),
+ "gpu_panel_port_select": FormatInt32((inteltool.IGD[0xc7208] >> 30) & 3),
+ "gpu_panel_power_up_delay": FormatInt32((inteltool.IGD[0xc7208] >> 16) & 0x1fff),
+ "gpu_panel_power_backlight_on_delay": FormatInt32(inteltool.IGD[0xc7208] & 0x1fff),
+ "gpu_panel_power_down_delay": FormatInt32((inteltool.IGD[0xc720c] >> 16) & 0x1fff),
+ "gpu_panel_power_backlight_off_delay": FormatInt32(inteltool.IGD[0xc720c] & 0x1fff),
+ "gpu_panel_power_cycle_delay": FormatInt32(inteltool.IGD[0xc7210] & 0xff),
+ "gpu_cpu_backlight": FormatHex32(inteltool.IGD[0x48254]),
+ "gpu_pch_backlight": FormatHex32((inteltool.IGD[0xc8254] >> 16) * 0x10001),
+ "gpu_ddi_e_connected": FormatBool(((inteltool.IGD[0x64000] >> 4) & 1) == 0),
+ /* FIXME:XX hardcoded. */
+ "gfx.ndid": "3",
+ "gfx.did": "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }",
+ },
+ Children: []DevTreeNode{
+ {
+ Chip: "cpu_cluster",
+ Dev: 0,
+ Children: []DevTreeNode{
+ {
+ Chip: "cpu/intel/haswell",
+ Children: []DevTreeNode{
+ {
+ Chip: "lapic",
+ Dev: 0,
+ },
+ {
+ Chip: "lapic",
+ Dev: 0xacac,
+ Disabled: true,
+ },
+ },
+ Registers: map[string]string{
+ /* FIXME:XX hardcoded. */
+ "c1_acpower": "1",
+ "c2_acpower": "3",
+ "c3_acpower": "5",
+ "c1_battery": "1",
+ "c2_battery": "3",
+ "c3_battery": "5",
+ },
+ },
+ },
+ },
+
+ {
+ Chip: "domain",
+ Dev: 0,
+ PCIController: true,
+ ChildPCIBus: 0,
+ PCISlots: []PCISlot{
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x0, Func: 0}, writeEmpty: true, additionalComment: "Host bridge"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1, Func: 0}, writeEmpty: true, additionalComment: "PCIe Bridge for discrete graphics"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x2, Func: 0}, writeEmpty: true, additionalComment: "Internal graphics"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x3, Func: 0}, writeEmpty: true, additionalComment: "Mini-HD audio"},
+ },
+ },
+ },
+ }
+
+ PutPCIDev(addr, "Host bridge")
+
+ /* FIXME:XX some configs are unsupported. */
+
+ KconfigBool["CPU_INTEL_HASWELL"] = true
+ KconfigBool["NORTHBRIDGE_INTEL_HASWELL"] = true
+ KconfigBool["INTEL_INT15"] = true
+ KconfigBool["HAVE_ACPI_TABLES"] = true
+ KconfigBool["HAVE_ACPI_RESUME"] = true
+
+ KconfigInt["MAX_CPUS"] = 8
+
+ DSDTIncludes = append(DSDTIncludes, DSDTInclude{
+ File: "cpu/intel/common/acpi/cpu.asl",
+ })
+
+ DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{
+ File: "northbridge/intel/haswell/acpi/haswell.asl",
+ }, DSDTInclude{
+ File: "drivers/intel/gma/acpi/default_brightness_levels.asl",
+ })
+}
+
+func init() {
+ RegisterPCI(0x8086, 0x0c00, haswellmc{variant: "Desktop"})
+ RegisterPCI(0x8086, 0x0c04, haswellmc{variant: "Mobile"})
+ RegisterPCI(0x8086, 0x0a04, haswellmc{variant: "ULT"})
+ RegisterPCI(0x8086, 0x0c08, haswellmc{variant: "Server"})
+ for _, id := range []uint16{
+ 0x0402, 0x0412, 0x0422,
+ 0x0406, 0x0416, 0x0426,
+ 0x0d16, 0x0d26, 0x0d36,
+ 0x0a06, 0x0a16, 0x0a26,
+ } {
+ RegisterPCI(0x8086, id, GenericVGA{GenericPCI{Comment: "VGA controller"}})
+ }
+}
diff --git a/util/autoport/lynxpoint.go b/util/autoport/lynxpoint.go
new file mode 100644
index 0000000..df20c3f
--- /dev/null
+++ b/util/autoport/lynxpoint.go
@@ -0,0 +1,495 @@
+package main
+
+import (
+ "fmt"
+ "os"
+)
+
+type lynxpoint struct {
+ variant string
+ node *DevTreeNode
+}
+
+func (b lynxpoint) writeGPIOSet(ctx Context, sb *os.File,
+ val uint32, set uint, partno int, constraint uint32) {
+
+ max := uint(32)
+ if set == 3 {
+ max = 12
+ }
+
+ bits := [6][2]string{
+ {"GPIO_MODE_NATIVE", "GPIO_MODE_GPIO"},
+ {"GPIO_DIR_OUTPUT", "GPIO_DIR_INPUT"},
+ {"GPIO_LEVEL_LOW", "GPIO_LEVEL_HIGH"},
+ {"GPIO_RESET_PWROK", "GPIO_RESET_RSMRST"},
+ {"GPIO_NO_INVERT", "GPIO_INVERT"},
+ {"GPIO_NO_BLINK", "GPIO_BLINK"},
+ }
+
+ for i := uint(0); i < max; i++ {
+ if ((constraint>>i)&1 == 1) {
+ fmt.Fprintf(sb, " .gpio%d = %s,\n",
+ (set-1)*32+i,
+ bits[partno][(val>>i)&1])
+ }
+ }
+}
+
+func (b lynxpoint) GPIO(ctx Context, inteltool InteltoolData) {
+ var constraint uint32
+ gpio := Create(ctx, "gpio.c")
+ defer gpio.Close()
+
+ AddROMStageFile("gpio.c", "")
+
+ Add_gpl(gpio)
+ gpio.WriteString("#include <southbridge/intel/common/gpio.h>\n\n")
+
+ /* TODO: different in LP PCH */
+ addresses := [3][6]int{
+ {0x00, 0x04, 0x0c, 0x60, 0x2c, 0x18},
+ {0x30, 0x34, 0x38, 0x64, -1, -1},
+ {0x40, 0x44, 0x48, 0x68, -1, -1},
+ }
+
+ for set := 1; set <= 3; set++ {
+ for partno, part := range []string{"mode", "direction", "level", "reset", "invert", "blink"} {
+ addr := addresses[set-1][partno]
+ if addr < 0 {
+ continue
+ }
+ fmt.Fprintf(gpio, "static const struct pch_gpio_set%d pch_gpio_set%d_%s = {\n",
+ set, set, part)
+
+ constraint = 0xffffffff
+ switch part {
+ case "direction":
+ /* Ignored on native mode */
+ constraint = inteltool.GPIO[uint16(addresses[set-1][0])]
+ case "level":
+ /* Level doesn't matter for input */
+ constraint = inteltool.GPIO[uint16(addresses[set-1][0])]
+ constraint &^= inteltool.GPIO[uint16(addresses[set-1][1])]
+ case "reset":
+ /* Only show reset */
+ constraint = inteltool.GPIO[uint16(addresses[set-1][3])]
+ case "invert":
+ /* Only on input and only show inverted GPIO */
+ constraint = inteltool.GPIO[uint16(addresses[set-1][0])]
+ constraint &= inteltool.GPIO[uint16(addresses[set-1][1])]
+ constraint &= inteltool.GPIO[uint16(addresses[set-1][4])]
+ case "blink":
+ /* Only on output and only show blinking GPIO */
+ constraint = inteltool.GPIO[uint16(addresses[set-1][0])]
+ constraint &^= inteltool.GPIO[uint16(addresses[set-1][1])]
+ constraint &= inteltool.GPIO[uint16(addresses[set-1][5])]
+ }
+ b.writeGPIOSet(ctx, gpio, inteltool.GPIO[uint16(addr)], uint(set), partno, constraint)
+ gpio.WriteString("};\n\n")
+ }
+ }
+
+ gpio.WriteString(`const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
+`)
+}
+
+func (b lynxpoint) IsPCIeHotplug(ctx Context, port int) bool {
+ portDev, ok := PCIMap[PCIAddr{Bus: 0, Dev: 0x1c, Func: port}]
+ if !ok {
+ return false
+ }
+ return (portDev.ConfigDump[0xdb] & (1 << 6)) != 0
+}
+
+func (b lynxpoint) GetGPIOHeader() string {
+ return "southbridge/intel/lynxpoint/pch.h"
+}
+
+func (b lynxpoint) EnableGPE(in int) {
+ b.node.Registers[fmt.Sprintf("gpi%d_routing", in)] = "2"
+}
+
+func (b lynxpoint) EncodeGPE(in int) int {
+ return in + 0x10
+}
+
+func (b lynxpoint) DecodeGPE(in int) int {
+ return in - 0x10
+}
+
+func (b lynxpoint) NeedRouteGPIOManually() {
+ b.node.Comment += ", FIXME: set gpiX_routing for EC support"
+}
+
+func (b lynxpoint) Scan(ctx Context, addr PCIDevData) {
+
+ SouthBridge = &b
+
+ inteltool := ctx.InfoSource.GetInteltool()
+ b.GPIO(ctx, inteltool)
+
+ KconfigBool["SOUTHBRIDGE_INTEL_LYNXPOINT"] = true
+ if b.variant == "Lynx Point LP" {
+ KconfigBool["INTEL_LYNXPOINT_LP"] = true
+ }
+ KconfigBool["SERIRQ_CONTINUOUS_MODE"] = true
+ KconfigInt["USBDEBUG_HCD_INDEX"] = 2
+ KconfigComment["USBDEBUG_HCD_INDEX"] = "FIXME: check this"
+ dmi := ctx.InfoSource.GetDMI()
+ if dmi.Vendor == "LENOVO" {
+ KconfigInt["DRAM_RESET_GATE_GPIO"] = 10
+ } else {
+ KconfigInt["DRAM_RESET_GATE_GPIO"] = 60
+ }
+ KconfigComment["DRAM_RESET_GATE_GPIO"] = "FIXME: check this"
+
+ /* Not strictly speaking correct. These subsys/subvendor referer to PCI devices.
+ But most systems don't have any of those. But the config needs to be set
+ nevertheless. So set it to southbridge subsys/subvendor. */
+ KconfigHex["MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID"] = uint32(GetLE16(addr.ConfigDump[0x2c:0x2e]))
+ KconfigHex["MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID"] = uint32(GetLE16(addr.ConfigDump[0x2e:0x30]))
+
+ ich9GetFlashSize(ctx)
+
+ DSDTDefines = append(DSDTDefines,
+ DSDTDefine{
+ Key: "BRIGHTNESS_UP",
+ Value: "\\_SB.PCI0.GFX0.INCB",
+ },
+ DSDTDefine{
+ Key: "BRIGHTNESS_DOWN",
+ Value: "\\_SB.PCI0.GFX0.DECB",
+ },
+ DSDTDefine{
+ Key: "ACPI_VIDEO_DEVICE",
+ Value: "\\_SB.PCI0.GFX0",
+ })
+
+ /* SPI init */
+ MainboardIncludes = append(MainboardIncludes, "southbridge/intel/lynxpoint/pch.h")
+
+ cur := DevTreeNode{
+ Chip: "southbridge/intel/lynxpoint",
+ Comment: "Intel Series 8 Lynx Point PCH",
+
+ Registers: map[string]string{
+ "pirqa_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x60]),
+ "pirqb_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x61]),
+ "pirqc_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x62]),
+ "pirqd_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x63]),
+ "pirqe_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x68]),
+ "pirqf_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x69]),
+ "pirqg_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x6a]),
+ "pirqh_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x6b]),
+ "sata_ahci": "1",
+ "gen1_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x84:0x88]),
+ "gen2_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x88:0x8c]),
+ "gen3_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x8c:0x90]),
+ "gen4_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x90:0x94]),
+ "sata_port_map": fmt.Sprintf("0x%x", PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 2}].ConfigDump[0x92]&0x3f),
+ },
+ PCISlots: []PCISlot{
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x14, Func: 0}, writeEmpty: false, additionalComment: "USB 3.0 Controller"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 0}, writeEmpty: true, additionalComment: "Management Engine Interface 1"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 1}, writeEmpty: true, additionalComment: "Management Engine Interface 2"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 2}, writeEmpty: true, additionalComment: "Management Engine IDE-R"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 3}, writeEmpty: true, additionalComment: "Management Engine KT"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x19, Func: 0}, writeEmpty: true, additionalComment: "Intel Gigabit Ethernet"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1a, Func: 0}, writeEmpty: true, additionalComment: "USB2 EHCI #2"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1b, Func: 0}, writeEmpty: true, additionalComment: "High Definition Audio"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 0}, writeEmpty: true, additionalComment: "PCIe Port #1"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 1}, writeEmpty: true, additionalComment: "PCIe Port #2"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 2}, writeEmpty: true, additionalComment: "PCIe Port #3"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 3}, writeEmpty: true, additionalComment: "PCIe Port #4"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 4}, writeEmpty: true, additionalComment: "PCIe Port #5"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 5}, writeEmpty: true, additionalComment: "PCIe Port #6"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 6}, writeEmpty: true, additionalComment: "PCIe Port #7"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 7}, writeEmpty: true, additionalComment: "PCIe Port #8"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1d, Func: 0}, writeEmpty: true, additionalComment: "USB2 EHCI #1"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1e, Func: 0}, writeEmpty: true, additionalComment: "PCI bridge"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 0}, writeEmpty: true, additionalComment: "LPC bridge"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 2}, writeEmpty: true, additionalComment: "SATA Controller 1"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 3}, writeEmpty: true, additionalComment: "SMBus"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 5}, writeEmpty: true, additionalComment: "SATA Controller 2"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 6}, writeEmpty: true, additionalComment: "Thermal"},
+ },
+ }
+
+ b.node = &cur
+
+ PutPCIChip(addr, cur)
+ PutPCIDevParent(addr, "PCI-LPC bridge", "lpc")
+
+ DSDTIncludes = append(DSDTIncludes, DSDTInclude{
+ File: "southbridge/intel/lynxpoint/acpi/platform.asl",
+ })
+ DSDTIncludes = append(DSDTIncludes, DSDTInclude{
+ File: "southbridge/intel/lynxpoint/acpi/globalnvs.asl",
+ Comment: "global NVS and variables",
+ })
+ DSDTIncludes = append(DSDTIncludes, DSDTInclude{
+ File: "southbridge/intel/lynxpoint/acpi/sleepstates.asl",
+ })
+ DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{
+ File: "southbridge/intel/lynxpoint/acpi/pch.asl",
+ })
+
+ sb := Create(ctx, "romstage.c")
+ defer sb.Close()
+ Add_gpl(sb)
+ sb.WriteString(`#include <stdint.h>
+#include <cpu/intel/romstage.h>
+#include <cpu/intel/haswell/haswell.h>
+#include <northbridge/intel/haswell/haswell.h>
+#include <northbridge/intel/haswell/pei_data.h>
+#include <southbridge/intel/common/gpio.h>
+#include <southbridge/intel/lynxpoint/pch.h>
+
+static const struct rcba_config_instruction rcba_config[] = {
+`)
+ RestoreDIRRoute(sb, "D31IR", uint16(inteltool.RCBA[0x3140]))
+ RestoreDIRRoute(sb, "D29IR", uint16(inteltool.RCBA[0x3144]))
+ RestoreDIRRoute(sb, "D28IR", uint16(inteltool.RCBA[0x3146]))
+ RestoreDIRRoute(sb, "D27IR", uint16(inteltool.RCBA[0x3148]))
+ RestoreDIRRoute(sb, "D26IR", uint16(inteltool.RCBA[0x314c]))
+ RestoreDIRRoute(sb, "D25IR", uint16(inteltool.RCBA[0x3150]))
+ RestoreDIRRoute(sb, "D22IR", uint16(inteltool.RCBA[0x315c]))
+ RestoreDIRRoute(sb, "D20IR", uint16(inteltool.RCBA[0x3160]))
+
+ sb.WriteString(`
+ RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS),
+
+ RCBA_END_CONFIG,
+};`)
+
+ sb.WriteString(`
+
+void mainboard_config_superio(void)
+{
+}
+
+void mainboard_romstage_entry(unsigned long bist)
+{
+ struct pei_data pei_data = {
+ .pei_version = PEI_VERSION,
+ .mchbar = (uintptr_t)DEFAULT_MCHBAR,
+ .dmibar = (uintptr_t)DEFAULT_DMIBAR,
+ .epbar = DEFAULT_EPBAR,
+ .pciexbar = DEFAULT_PCIEXBAR,
+ .smbusbar = SMBUS_IO_BASE,
+ .wdbbar = 0x4000000,
+ .wdbsize = 0x1000,
+ .hpet_address = HPET_ADDR,
+ .rcba = (uintptr_t)DEFAULT_RCBA,
+ .pmbase = DEFAULT_PMBASE,
+ .gpiobase = DEFAULT_GPIOBASE,
+ .temp_mmio_base = 0xfed08000,
+ .system_type = 1, /* desktop/server, FIXME: check this */
+ .tseg_size = CONFIG_SMM_TSEG_SIZE,
+ .spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 }, /* FIXME: check this */
+ .ec_present = 0,
+ .dimm_channel0_disabled = 0, /* FIXME: leave channel 0 enabled */
+ .dimm_channel1_disabled = 0, /* FIXME: leave channel 1 enabled */
+ .max_ddr3_freq = 1600,
+ .usb2_ports = {
+ /* Length, Enable, OCn#, Location */
+`)
+
+ pdo1 := PCIMap[PCIAddr{Bus: 0, Dev: 0x1d, Func: 0}].ConfigDump[0x64]
+ ocmap1 := PCIMap[PCIAddr{Bus: 0, Dev: 0x1d, Func: 0}].ConfigDump[0x74:0x78]
+ pdo2 := PCIMap[PCIAddr{Bus: 0, Dev: 0x1a, Func: 0}].ConfigDump[0x64]
+ ocmap2 := PCIMap[PCIAddr{Bus: 0, Dev: 0x1a, Func: 0}].ConfigDump[0x74:0x78]
+
+ for port := uint(0); port < 14; port++ {
+ var port_oc int = -1
+ var port_pos string
+ var port_disable uint8
+
+ if port < 8 {
+ port_disable = (pdo1 >> port) & 1
+ for oc := 0; oc < 4; oc++ {
+ if ((ocmap1[oc] & (1 << port)) != 0) {
+ port_oc = oc
+ break
+ }
+ }
+ } else {
+ port_disable = (pdo2 >> (port - 8)) & 1
+ for oc := 0; oc < 4; oc++ {
+ if ((ocmap2[oc] & (1 << (port - 8))) != 0) {
+ port_oc = oc + 4
+ break
+ }
+ }
+ }
+ if port_disable == 1 {
+ port_pos = "USB_PORT_SKIP"
+ } else {
+ port_pos = "USB_PORT_BACK_PANEL"
+ }
+ if port_oc == -1 {
+ fmt.Fprintf(sb, " { 0x0040, %d, USB_OC_PIN_SKIP, %s },\n",
+ (port_disable ^ 1), port_pos)
+ } else {
+ fmt.Fprintf(sb, " { 0x0040, %d, %d, %s },\n",
+ (port_disable ^ 1), port_oc, port_pos)
+ }
+ }
+
+ sb.WriteString(` },
+ .usb3_ports = {
+`)
+
+ xpdo := PCIMap[PCIAddr{Bus: 0, Dev: 0x14, Func: 0}].ConfigDump[0xe8]
+ u3ocm := PCIMap[PCIAddr{Bus: 0, Dev: 0x14, Func: 0}].ConfigDump[0xc8:0xd0]
+
+ for port := uint(0); port < 6; port++ {
+ var port_oc int = -1
+ port_disable := (xpdo >> port) & 1
+ for oc := 0; oc < 8; oc++ {
+ if (u3ocm[oc] & (1 << port)) != 0 {
+ port_oc = oc
+ break
+ }
+ }
+ if port_oc == -1 {
+ fmt.Fprintf(sb, " { %d, USB_OC_PIN_SKIP },\n",
+ (port_disable ^ 1))
+ } else {
+ fmt.Fprintf(sb, " { %d, %d },\n",
+ (port_disable ^ 1), port_oc)
+ }
+ }
+
+ sb.WriteString(` },
+ };
+
+ struct romstage_params romstage_params = {
+ .pei_data = &pei_data,
+ .gpio_map = &mainboard_gpio_map,
+ .rcba_config = &rcba_config[0],
+ .bist = bist,
+ };
+
+ romstage_common(&romstage_params);
+}`)
+
+ gnvs := Create(ctx, "acpi_tables.c")
+ defer gnvs.Close()
+
+ Add_gpl(gnvs)
+ gnvs.WriteString(`#include <southbridge/intel/lynxpoint/nvs.h>
+
+/* FIXME: check this function. */
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+ /* Disable USB ports in S3 by default */
+ gnvs->s3u0 = 0;
+ gnvs->s3u1 = 0;
+
+ /* Disable USB ports in S5 by default */
+ gnvs->s5u0 = 0;
+ gnvs->s5u1 = 0;
+
+ // the lid is open by default.
+ gnvs->lids = 1;
+
+ gnvs->tcrt = 100;
+ gnvs->tpsv = 90;
+}
+`)
+
+}
+
+func init() {
+ for _, id := range []uint16 {
+ 0x8c41, 0x8c49, 0x8c4b, 0x8c4f,
+ } {
+ RegisterPCI(0x8086, uint16(id), lynxpoint{variant: "Lynx Point Mobile"})
+ }
+
+ for _, id := range []uint16 {
+ 0x8c42, 0x8c44, 0x8c46, 0x8c4a,
+ 0x8c4c, 0x8c4e, 0x8c50, 0x8c5c,
+ } {
+ RegisterPCI(0x8086, uint16(id), lynxpoint{variant: "Lynx Point Desktop"})
+ }
+
+ for _, id := range []uint16 {
+ 0x8c52, 0x8c54, 0x8c56,
+ } {
+ RegisterPCI(0x8086, uint16(id), lynxpoint{variant: "Lynx Point Server"})
+ }
+
+ for _, id := range []uint16 {
+ 0x9c41, 0x9c43, 0x9c45,
+ } {
+ RegisterPCI(0x8086, uint16(id), lynxpoint{variant: "Lynx Point LP"})
+ }
+
+ /* PCIe bridge */
+ for _, id := range []uint16{
+ 0x8c10, 0x8c12, 0x8c14, 0x8c16, 0x8c18, 0x8c1a, 0x8c1c, 0x8c1e,
+ 0x9c10, 0x9c12, 0x9c14, 0x9c16, 0x9c18, 0x9c1a,
+ } {
+ RegisterPCI(0x8086, id, GenericPCI{})
+ }
+
+ /* SMBus controller */
+ RegisterPCI(0x8086, 0x1c22, GenericPCI{MissingParent: "smbus"})
+ RegisterPCI(0x8086, 0x1e22, GenericPCI{MissingParent: "smbus"})
+ RegisterPCI(0x8086, 0x8c22, GenericPCI{MissingParent: "smbus"})
+ RegisterPCI(0x8086, 0x9c22, GenericPCI{MissingParent: "smbus"})
+
+ /* SATA */
+ for _, id := range []uint16{
+ 0x8c00, 0x8c02, 0x8c04, 0x8c06, 0x8c08, 0x8c0e,
+ 0x8c01, 0x8c03, 0x8c05, 0x8c07, 0x8c09, 0x8c0f,
+ 0x9c03, 0x9c05, 0x9c07, 0x9c0f,
+ } {
+ RegisterPCI(0x8086, id, GenericPCI{})
+ }
+
+ /* EHCI */
+ for _, id := range []uint16{
+ 0x9c26, 0x8c26, 0x8c2d,
+ } {
+ RegisterPCI(0x8086, id, GenericPCI{})
+ }
+
+ /* XHCI */
+ RegisterPCI(0x8086, 0x8c31, GenericPCI{})
+ RegisterPCI(0x8086, 0x9c31, GenericPCI{})
+
+ /* ME and children */
+ for _, id := range []uint16{
+ 0x8c3a, 0x8c3b,
+ } {
+ RegisterPCI(0x8086, id, GenericPCI{})
+ }
+
+ /* Ethernet */
+ RegisterPCI(0x8086, 0x8c33, GenericPCI{})
+}
diff --git a/util/autoport/main.go b/util/autoport/main.go
index 05a829b..c1920a7 100644
--- a/util/autoport/main.go
+++ b/util/autoport/main.go
@@ -236,6 +236,12 @@
pcidev.ConfigDump[addr])
}
+func RestoreDIRRoute(f *os.File, regname string, val uint16) {
+ fmt.Fprintf(f, " RCBA_SET_REG_16(%s, DIR_ROUTE(PIRQ%c, PIRQ%c, PIRQ%c, PIRQ%c)),\n",
+ regname, 'A' + (val & 7), 'A' + ((val >> 4) & 7),
+ 'A' + ((val >> 8) & 7), 'A' + ((val >> 12) & 7))
+}
+
func RestorePCI32Simple(f *os.File, pcidev PCIDevData, addr uint16) {
fmt.Fprintf(f, " pci_write_config32(PCI_DEV(%d, 0x%02x, %d), 0x%02x, 0x%02x%02x%02x%02x);\n",
pcidev.Bus, pcidev.Dev, pcidev.Func, addr,
--
To view, visit https://review.coreboot.org/c/coreboot/+/30890
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I4f6e8c97b5122101de2f36bba8ba9f8ddd5b813a
Gerrit-Change-Number: 30890
Gerrit-PatchSet: 1
Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com>
Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com>
Gerrit-MessageType: newchange
5 days, 20 hours
- 7
- 43
Change in ...coreboot[master]: superio/ite: Add and use it8528e
by Patrick Rudolph (Code Review)
Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30957
Change subject: superio/ite: Add and use it8528e
......................................................................
superio/ite: Add and use it8528e
* Add SuperIO ITE8528E
* Use ITE8528E to configure serial on wedge100s
TODO: Add support for accessing EC space.
Tested on wedge100s. The serial works without CONFIG_CONSOLE_SERIAL.
Change-Id: I72aa756e123d6f99d9ef4fe955c4b7f1be25d547
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/mainboard/ocp/wedge100s/Kconfig
M src/mainboard/ocp/wedge100s/devicetree.cb
M src/superio/ite/Makefile.inc
A src/superio/ite/it8528e/Kconfig
A src/superio/ite/it8528e/Makefile.inc
A src/superio/ite/it8528e/chip.h
A src/superio/ite/it8528e/it8528e.h
A src/superio/ite/it8528e/superio.c
8 files changed, 226 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/30957/1
diff --git a/src/mainboard/ocp/wedge100s/Kconfig b/src/mainboard/ocp/wedge100s/Kconfig
index ce9c097..6224340 100644
--- a/src/mainboard/ocp/wedge100s/Kconfig
+++ b/src/mainboard/ocp/wedge100s/Kconfig
@@ -16,6 +16,7 @@
select MAINBOARD_HAS_LPC_TPM
select MAINBOARD_HAS_TPM1
select DRIVERS_UART_8250IO
+ select SUPERIO_ITE_IT8528E
config VBOOT
select VBOOT_VBNV_CMOS
diff --git a/src/mainboard/ocp/wedge100s/devicetree.cb b/src/mainboard/ocp/wedge100s/devicetree.cb
index 3d66d0d..fc6dccc 100644
--- a/src/mainboard/ocp/wedge100s/devicetree.cb
+++ b/src/mainboard/ocp/wedge100s/devicetree.cb
@@ -11,6 +11,58 @@
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
+ chip superio/ite/it8528e
+ # COM1, routed to COM-e header
+ device pnp 6e.1 on
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ # COM2, routed to COM-e header
+ device pnp 6e.2 on
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 6e.4 off end
+ device pnp 6e.5 off end
+ device pnp 6e.6 off end
+ device pnp 6e.a off end
+ device pnp 6e.f off end
+ device pnp 6e.10 off
+ io 0x60 = 0x70
+ io 0x62 = 0x72
+ irq 0x70 = 8
+ end
+ device pnp 6e.11 off
+ io 0x60 = 0x620
+ io 0x62 = 0x660
+ irq 0x70 = 1
+ end
+ device pnp 6e.12 off
+ io 0x60 = 0x680
+ io 0x62 = 0x6c0
+ irq 0x70 = 1
+ end
+ device pnp 6e.13 off
+ io 0x60 = 0x300
+ irq 0x70 = 2
+ end
+ device pnp 6e.14 off end
+ device pnp 6e.17 off
+ io 0x60 = 0x6a0
+ io 0x62 = 0x6e0
+ irq 0x70 = 1
+ end
+ device pnp 6e.18 off
+ io 0x60 = 0x740
+ io 0x62 = 0x780
+ irq 0x70 = 1
+ end
+ device pnp 6e.19 off
+ io 0x60 = 0x7a0
+ io 0x62 = 0x7c0
+ irq 0x70 = 1
+ end
+ end #superio/ite/it8528e
end # LPC Bridge
device pci 1f.2 on end # SATA Controller
device pci 1f.3 on end # SMBus Controller
diff --git a/src/superio/ite/Makefile.inc b/src/superio/ite/Makefile.inc
index e73fd71..551abe9 100644
--- a/src/superio/ite/Makefile.inc
+++ b/src/superio/ite/Makefile.inc
@@ -20,6 +20,7 @@
## include generic ite environment controller driver
ramstage-$(CONFIG_SUPERIO_ITE_ENV_CTRL) += common/env_ctrl.c
+subdirs-y += it8528e
subdirs-y += it8623e
subdirs-y += it8671f
subdirs-y += it8712f
diff --git a/src/superio/ite/it8528e/Kconfig b/src/superio/ite/it8528e/Kconfig
new file mode 100644
index 0000000..3815c28
--- /dev/null
+++ b/src/superio/ite/it8528e/Kconfig
@@ -0,0 +1,18 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2019 Patrick Rudolph <patrick.rudolph(a)9elements.com>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+config SUPERIO_ITE_IT8528E
+ bool
+ select SUPERIO_ITE_COMMON_PRE_RAM
diff --git a/src/superio/ite/it8528e/Makefile.inc b/src/superio/ite/it8528e/Makefile.inc
new file mode 100644
index 0000000..def04e5
--- /dev/null
+++ b/src/superio/ite/it8528e/Makefile.inc
@@ -0,0 +1,17 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2019 Patrick Rudolph <patrick.rudolph(a)9elements.com>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+ramstage-$(CONFIG_SUPERIO_ITE_IT8528E) += superio.c
diff --git a/src/superio/ite/it8528e/chip.h b/src/superio/ite/it8528e/chip.h
new file mode 100644
index 0000000..ef7e14f
--- /dev/null
+++ b/src/superio/ite/it8528e/chip.h
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Patrick Rudolph <patrick.rudolph(a)9elements.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SUPERIO_ITE_IT8528E_CHIP_H
+#define SUPERIO_ITE_IT8528E_CHIP_H
+
+#include <superio/ite/common/env_ctrl_chip.h>
+
+struct superio_ite_it8528e_config {
+ // FIXME: Add support for EC
+};
+
+#endif /* SUPERIO_ITE_IT8528E_CHIP_H */
diff --git a/src/superio/ite/it8528e/it8528e.h b/src/superio/ite/it8528e/it8528e.h
new file mode 100644
index 0000000..7b19349
--- /dev/null
+++ b/src/superio/ite/it8528e/it8528e.h
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Patrick Rudolph <patrick.rudolph(a)9elements.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SUPERIO_ITE_IT8528E_H
+#define SUPERIO_ITE_IT8528E_H
+
+#define IT8528E_SP1 0x01 /* Com1 */
+#define IT8528E_SP2 0x02 /* Com2 */
+#define IT8528E_SWUC 0x04 /* System Wake-Up */
+#define IT8528E_KBCM 0x05 /* PS/2 mouse */
+#define IT8528E_KBCK 0x06 /* PS/2 keyboard */
+#define IT8528E_IR 0x0a /* Consumer IR */
+#define IT8528E_SMFI 0x0f /* Shared Memory/Flash Interface */
+#define IT8528E_RTCT 0x10 /* RTC-like Timer */
+#define IT8528E_PMC1 0x11 /* Power Management Channel 1 */
+#define IT8528E_PMC2 0x12 /* Power Management Channel 2 */
+#define IT8528E_SSPI 0x13 /* Serial Periphial Interface */
+#define IT8528E_PECI 0x14 /* Platform EC Interface */
+#define IT8528E_PMC3 0x17 /* Power Management Channel 3 */
+#define IT8528E_PMC4 0x18 /* Power Management Channel 4 */
+#define IT8528E_PMC5 0x19 /* Power Management Channel 5 */
+
+
+#endif /* SUPERIO_ITE_IT8528E_H */
diff --git a/src/superio/ite/it8528e/superio.c b/src/superio/ite/it8528e/superio.c
new file mode 100644
index 0000000..ae2a8e9
--- /dev/null
+++ b/src/superio/ite/it8528e/superio.c
@@ -0,0 +1,74 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de>
+ * Copyright (C) 2007 Philipp Degler <pdegler(a)rumms.uni-mannheim.de>
+ * Copyright (C) 2017 Gergely Kiss <mail.gery(a)gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/device.h>
+#include <device/pnp.h>
+#include <arch/io.h>
+#include <stdlib.h>
+#include <superio/conf_mode.h>
+
+#include "chip.h"
+#include "it8528e.h"
+
+static void it8528e_init(struct device *dev)
+{
+ // FIXME: Init EC
+}
+
+static struct device_operations ops = {
+ .read_resources = pnp_read_resources,
+ .set_resources = pnp_set_resources,
+ .enable_resources = pnp_enable_resources,
+ .enable = pnp_alt_enable,
+ .init = it8528e_init,
+ .ops_pnp_mode = &pnp_conf_mode_870155_aa,
+};
+
+static struct pnp_info pnp_dev_info[] = {
+ { NULL, IT8528E_SP1, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
+ { NULL, IT8528E_SP2, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
+ { NULL, IT8528E_SWUC, PNP_IO0 | PNP_IRQ0, 0xfff0, },
+ { NULL, IT8528E_KBCM, PNP_IRQ0, },
+ /* Documentation: Programm io0 = 0x60 and io1 = 0x64 */
+ { NULL, IT8528E_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff, },
+ { NULL, IT8528E_IR, PNP_IO0 | PNP_IRQ0, 0xfff8, },
+ { NULL, IT8528E_SMFI, PNP_IO0 | PNP_IRQ0, 0xfff0, },
+ /* Documentation: Programm io0 = 0x70 and io1 = 0x272 */
+ { NULL, IT8528E_RTCT, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IO3 | PNP_IRQ0,
+ 0xfffe, 0xfffe, 0xfffe, 0xfffe},
+ /* Documentation: Programm io0 = 0x62 and io1 = 0x66 */
+ { NULL, IT8528E_PMC1, PNP_IO0 | PNP_IO1 | PNP_IRQ0 , 0x07ff, 0x07ff },
+ { NULL, IT8528E_PMC2, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IRQ0 , 0x07fc,
+ 0x07fc, 0xfff0 },
+ /* Documentation is unclear if PMC3-5 have LPC I/O decoding support */
+ { NULL, IT8528E_PMC3, PNP_IO0 | PNP_IO1 | PNP_IRQ0 , 0x07ff, 0x07ff },
+ { NULL, IT8528E_PMC4, PNP_IO0 | PNP_IO1 | PNP_IRQ0 , 0x07ff, 0x07ff },
+ { NULL, IT8528E_PMC5, PNP_IO0 | PNP_IO1 | PNP_IRQ0 , 0x07ff, 0x07ff },
+ { NULL, IT8528E_SSPI, PNP_IO0 | PNP_IRQ0, 0xfff8 },
+ { NULL, IT8528E_PECI, PNP_IO0 , 0xfff8 },
+};
+
+static void enable_dev(struct device *dev)
+{
+ pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
+}
+
+struct chip_operations superio_ite_it8528e_ops = {
+ CHIP_NAME("ITE IT8528E Super I/O")
+ .enable_dev = enable_dev,
+};
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I72aa756e123d6f99d9ef4fe955c4b7f1be25d547
Gerrit-Change-Number: 30957
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Gerrit-MessageType: newchange
3 weeks, 4 days
- 6
- 22
Change in ...coreboot[master]: Adding Asus A88XM-E FM2+ motherboard with documentation
by Balázs Vinarz (Code Review)
Balázs Vinarz has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30987
Change subject: Adding Asus A88XM-E FM2+ motherboard with documentation
......................................................................
Adding Asus A88XM-E FM2+ motherboard with documentation
Signed-off-by: Balazs Vinarz <vinibali1(a)gmail.com>
Change-Id: I60fa0636ba41f5f1a6a3faa2764bf2f0a968cf90
---
A Documentation/mainboard/asus/a88xm-e.md
A src/mainboard/asus/a88xm-e/BiosCallOuts.c
A src/mainboard/asus/a88xm-e/Kconfig
A src/mainboard/asus/a88xm-e/Kconfig.name
A src/mainboard/asus/a88xm-e/Makefile.inc
A src/mainboard/asus/a88xm-e/OemCustomize.c
A src/mainboard/asus/a88xm-e/OptionsIds.h
A src/mainboard/asus/a88xm-e/acpi/cpstate.asl
A src/mainboard/asus/a88xm-e/acpi/gpe.asl
A src/mainboard/asus/a88xm-e/acpi/mainboard.asl
A src/mainboard/asus/a88xm-e/acpi/routing.asl
A src/mainboard/asus/a88xm-e/acpi/sata.asl
A src/mainboard/asus/a88xm-e/acpi/si.asl
A src/mainboard/asus/a88xm-e/acpi/sleep.asl
A src/mainboard/asus/a88xm-e/acpi/superio.asl
A src/mainboard/asus/a88xm-e/acpi/thermal.asl
A src/mainboard/asus/a88xm-e/acpi/usb_oc.asl
A src/mainboard/asus/a88xm-e/acpi_tables.c
A src/mainboard/asus/a88xm-e/board_info.txt
A src/mainboard/asus/a88xm-e/buildOpts.c
A src/mainboard/asus/a88xm-e/cmos.layout
A src/mainboard/asus/a88xm-e/devicetree_a88xm-e.cb
A src/mainboard/asus/a88xm-e/dsdt.asl
A src/mainboard/asus/a88xm-e/irq_tables.c
A src/mainboard/asus/a88xm-e/mainboard.c
A src/mainboard/asus/a88xm-e/mptable.c
A src/mainboard/asus/a88xm-e/romstage.c
27 files changed, 2,371 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/30987/1
diff --git a/Documentation/mainboard/asus/a88xm-e.md b/Documentation/mainboard/asus/a88xm-e.md
new file mode 100644
index 0000000..5f50c5a
--- /dev/null
+++ b/Documentation/mainboard/asus/a88xm-e.md
@@ -0,0 +1,131 @@
+# ASUS A88XM-E
+
+This page describes how to run coreboot on the [ASUS A88XM-E].
+
+## Technology
+
+Both "Trinity" and "Richland" FM2 desktop processing units are working,
+the CPU architecture in these CPUs/APUs are [Piledriver],
+and their GPU is [TeraScale 3] (VLIW4-based).
+
+Kaveri is non-working at the moment (FM2+),
+the CPU architecture in these CPUs/APUs are [Steamroller],
+and their GPU is [Sea Islands] (GCN2-based).
+
+```eval_rst
++------------------+--------------------------------------------------+
+| A88XM-E | |
++------------------+--------------------------------------------------+
+| DDR voltage IC | Nuvoton 3101S |
++------------------+--------------------------------------------------+
+| Network | Realtek RTL8111G - Not working |
++------------------+--------------------------------------------------+
+| Northbridge | Integrated into CPU with IMC and GPU (APUs only) |
++------------------+--------------------------------------------------+
+| Southbridge | Bolton-D4 |
++------------------+--------------------------------------------------+
+| Sound IC | Realtek ALC887 |
++------------------+--------------------------------------------------+
+| Super I/O | ITE 8603E |
++------------------+--------------------------------------------------+
+| VRM controller | DIGI VRM ASP1206 |
++------------------+--------------------------------------------------+
+```
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+------------+
+| Type | Value |
++=====================+============+
+| Socketed flash | yes |
++---------------------+------------+
+| Model | [GD25Q64] |
++---------------------+------------+
+| Size | 8 MiB |
++---------------------+------------+
+| Package | DIP-8 |
++---------------------+------------+
+| Write protection | yes |
++---------------------+------------+
+| Dual BIOS feature | no |
++---------------------+------------+
+| Internal flashing | yes |
++---------------------+------------+
+```
+
+### Internal programming
+
+The main SPI flash can be accessed using [flashrom], if the
+AmdSpiRomProtect modules have been deleted in the factory image previously.
+
+## Integrated graphics
+
+### Retrieve the VGA optionrom from the vendor EFI binary by running:
+
+ # dd if=/dev/mem of=vgabios.bin bs=1k count=64 skip=768
+
+This version is usable for all the GPUs.
+1002,9901 Trinity (Radeon HD 7660D)
+1002,9904 Trinity (Radeon HD 7560D)
+1002,990c Richland (Radeon HD 8670D)
+1002,990e Richland (Radeon HD 8570D)
+1002,9991 Trinity (Radeon HD 7540D)
+1002,9993 Trinity (Radeon HD 7480D)
+1002,9996 Richland (Radeon HD 8470D)
+1002,9998 Richland (Radeon HD 8370D)
+1002,999d Richland (Radeon HD 8550D)
+1002,130f Kaveri (Radeon R7)
+
+## Known issues
+
+- AHCI hot-plug
+- Integrated ethernet
+- S3 resume
+- XHCI
+
+### XHCI ports can broke after using any of the blobs, restarting the
+board with factory image makes it work again as fallback.
+Tested even with/without the Bolton and Hudson blobs.
+
+## Untested
+
+- audio over HDMI
+- IOMMU
+- PS/2 mouse
+
+## TODOs
+
+- one ATOMBIOS module for all the integrated GPUs
+- manage to work with Kaveri/Godavary (missing PSP firmware?)
+
+## Working
+
+- ACPI
+- CPU frequency scaling
+- flashrom under coreboot
+- Hardware monitoring
+- Integrated graphics
+- Keyboard
+- KVM virtualization
+- Onboard audio
+- PCI
+- PCIe
+- PS/2 keyboard (during payload, bootloader)
+- SATA
+- Serial port
+- SuperIO based fan control
+- USB (disabling XHCI controller makes to work as fallback USB2.0 ports)
+
+## Extra resources
+
+- [Board manual]
+
+[ASUS A88XM-E]: https://www.asus.com/Motherboards/A88XME/
+[Board manual]: https://dlcdnets.asus.com/pub/ASUS/mb/SocketFM2/A88XM-E/E9125_A88XM-E.pdf
+[flashrom]: https://flashrom.org/Flashrom
+[GD25Q64]: http://www.elm-tech.com/ja/products/spi-flash-memory/gd25q64/gd25q64.pdf
+[Piledriver]: https://en.wikipedia.org/wiki/Piledriver_%28microarchitecture%29#APU_lines
+[Sea Islands]: https://en.wikipedia.org/wiki/Graphics_Core_Next#GCN_2nd_generation
+[Steamroller]: https://en.wikipedia.org/wiki/Steamroller_(microarchitecture)
+[TeraScale 3]: https://en.wikipedia.org/wiki/TeraScale_%28microarchitecture%29#TeraScale_3
diff --git a/src/mainboard/asus/a88xm-e/BiosCallOuts.c b/src/mainboard/asus/a88xm-e/BiosCallOuts.c
new file mode 100644
index 0000000..56c1753
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/BiosCallOuts.c
@@ -0,0 +1,98 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <AGESA.h>
+#include <northbridge/amd/agesa/BiosCallOuts.h>
+#include <northbridge/amd/agesa/state_machine.h>
+
+#include <vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h>
+#include <stdlib.h>
+
+const BIOS_CALLOUT_STRUCT BiosCallouts[] =
+{
+ {AGESA_DO_RESET, agesa_Reset },
+ {AGESA_READ_SPD, agesa_ReadSpd },
+ {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported },
+ {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp },
+ {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData },
+ {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess },
+ {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
+ {AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage }
+};
+const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
+
+/**
+ * ASUS A88XM-E board ALC887-VD Verb Table
+ *
+ * Copied from `/sys/class/sound/hwC1D0/init_pin_configs` when running
+ * the vendor BIOS.
+ */
+#if !IS_ENABLED(CONFIG_BOARD_ASUS_A88XM_E)
+const CODEC_ENTRY a88xm_e_alc887_VerbTbl[] = {
+ {0x11, 0x90460130},
+ {0x12, 0x40330000},
+ {0x14, 0x01014010},
+ {0x15, 0x411111f0},
+ {0x16, 0x411111f0},
+ {0x17, 0x411111f0},
+ {0x18, 0x01a19040},
+ {0x19, 0x02a19050},
+ {0x1a, 0x0181304f},
+ {0x1b, 0x02214020},
+ {0x1c, 0x411111f0},
+ {0x1d, 0x4044c601},
+ {0x1e, 0x411111f0},
+ {0x1f, 0x411111f0}
+ };
+#else
+const CODEC_ENTRY a88xm_e_alc887_VerbTbl[] = {
+ {0x11, 0x90460130},
+ {0x12, 0x40330000},
+ {0x14, 0x01014010},
+ {0x15, 0x411111f0},
+ {0x16, 0x411111f0},
+ {0x17, 0x411111f0},
+ {0x18, 0x01a19040},
+ {0x19, 0x02a19050},
+ {0x1a, 0x0181304f},
+ {0x1b, 0x02214020},
+ {0x1c, 0x411111f0},
+ {0x1d, 0x4044c601},
+ {0x1e, 0x411111f0},
+ {0x1f, 0x411111f0}
+};
+#endif
+
+static const CODEC_TBL_LIST CodecTableList[] =
+{
+ {0x10ec0887, (CODEC_ENTRY*)&a88xm_e_alc887_VerbTbl[0]},
+ {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL}
+};
+
+void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset)
+{
+ FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE);
+}
+
+void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env)
+{
+ /* Azalia Controller OEM Codec Table Pointer */
+ FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&CodecTableList[0]);
+
+ /* Fan Control */
+ FchParams_env->Imc.ImcEnable = FALSE;
+ FchParams_env->Hwm.HwMonitorEnable = FALSE;
+ FchParams_env->Hwm.HwmFchtsiAutoPoll = FALSE;/* 1 enable, 0 disable TSI Auto Polling */
+}
diff --git a/src/mainboard/asus/a88xm-e/Kconfig b/src/mainboard/asus/a88xm-e/Kconfig
new file mode 100644
index 0000000..70be2f1
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/Kconfig
@@ -0,0 +1,117 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+# Copyright (C) 2012 Rudolf Marek <r.marek(a)assembler.cz>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+if BOARD_ASUS_A88XM_E
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select CPU_AMD_AGESA_FAMILY15_TN
+ select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN
+ select SOUTHBRIDGE_AMD_AGESA_HUDSON
+ select HAVE_OPTION_TABLE
+ select HAVE_PIRQ_TABLE
+ select HAVE_MP_TABLE
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select SUPERIO_ITE_IT8728F
+ select BOARD_ROMSIZE_KB_8192
+ select GFXUMA
+
+choice
+ prompt "DDR3 memory voltage"
+ default BOARD_ASUS_A88XM_E_DDR3_VOLT_150
+
+config BOARD_ASUS_A88XM_E_DDR3_VOLT_135
+ bool "1.35V"
+ help
+ Set DRR3 memory voltage to 1.35V
+config BOARD_ASUS_A88XM_E_DDR3_VOLT_150
+ bool "1.50V"
+ help
+ Set DRR3 memory voltage to 1.50V
+config BOARD_ASUS_A88XM_E_DDR3_VOLT_165
+ bool "1.65V"
+ help
+ Set DRR3 memory voltage to 1.65V
+endchoice
+
+config BOARD_ASUS_A88XM_E_DDR3_VOLT_VAL
+ hex
+ default 0x9e if BOARD_ASUS_A88XM_E_DDR3_VOLT_135
+ default 0x0 if BOARD_ASUS_A88XM_E_DDR3_VOLT_150
+ default 0x1e if BOARD_ASUS_A88XM_E_DDR3_VOLT_165
+
+config MAINBOARD_DIR
+ string
+ default asus/a88xm-e
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "A88XM-E" if BOARD_ASUS_A88XM_E
+
+config HW_MEM_HOLE_SIZEK
+ hex
+ default 0x200000
+
+config MAX_CPUS
+ int
+ default 4
+
+config HUDSON_XHCI_FWM
+ bool
+ default n
+
+config HUDSON_IMC_FWM
+ bool
+ default n
+
+config IRQ_SLOT_COUNT
+ int
+ default 11
+
+config ONBOARD_VGA_IS_PRIMARY
+ bool
+ default y
+
+config VGA_BIOS_ID
+ string
+ default "1002,990e"
+
+config CONFIG_DRIVERS_PS2_KEYBOARD
+ bool
+ default y
+
+config CONFIG_HUDSON_XHCI_ENABLE
+ bool
+ default n
+
+config HUDSON_LEGACY_FREE
+ bool
+ default n
+
+config POST_IO
+ bool
+ default n
+
+config CONFIG_POST_DEVICE_PCI_PCIE
+ bool
+ default y
+
+config DEVICETREE
+ string
+ default "devicetree_a88xm-e.cb"
+
+endif # BOARD_ASUS_A88XM_E
diff --git a/src/mainboard/asus/a88xm-e/Kconfig.name b/src/mainboard/asus/a88xm-e/Kconfig.name
new file mode 100644
index 0000000..492d610
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_ASUS_A88XM_E
+ bool "A88XM-E"
diff --git a/src/mainboard/asus/a88xm-e/Makefile.inc b/src/mainboard/asus/a88xm-e/Makefile.inc
new file mode 100644
index 0000000..f8895fa
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/Makefile.inc
@@ -0,0 +1,22 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+romstage-y += buildOpts.c
+romstage-y += BiosCallOuts.c
+romstage-y += OemCustomize.c
+
+ramstage-y += buildOpts.c
+ramstage-y += BiosCallOuts.c
+ramstage-y += OemCustomize.c
diff --git a/src/mainboard/asus/a88xm-e/OemCustomize.c b/src/mainboard/asus/a88xm-e/OemCustomize.c
new file mode 100644
index 0000000..4c4c5bf
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/OemCustomize.c
@@ -0,0 +1,177 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <Porting.h>
+#include <AGESA.h>
+
+#include <northbridge/amd/agesa/state_machine.h>
+#include <PlatformMemoryConfiguration.h>
+
+/*
+ * Lane ID Mapping (from Fam15h BKDG: Table 45: Lane Id Mapping)
+ *
+ * Lane Id
+ * 0 P_UMI_[T,R]X[P,N]0 - southbridge link, connect via dev 8
+ * 1 P_UMI_[T,R]X[P,N]1 - southbridge link, connect via dev 8
+ * 2 P_UMI_[T,R]X[P,N]2 - southbridge link, connect via dev 8
+ * 3 P_UMI_[T,R]X[P,N]3 - southbridge link, connect via dev 8
+ * 4 P_GPP_[T,R]X[P,N]0 - may connect to PCI dev 4 - 7
+ * 5 P_GPP_[T,R]X[P,N]1 - may connect to PCI dev 4 - 7
+ * 6 P_GPP_[T,R]X[P,N]2 - may connect to PCI dev 4 - 7
+ * 7 P_GPP_[T,R]X[P,N]3 - may connect to PCI dev 4 - 7
+ * 8 P_GFX_[T,R]X[P,N]0 - may be used to form GFX slot or DDI
+ * 9 P_GFX_[T,R]X[P,N]1 - may be used to form GFX slot or DDI
+ * 10 P_GFX_[T,R]X[P,N]2 - may be used to form GFX slot or DDI
+ * 11 P_GFX_[T,R]X[P,N]3 - may be used to form GFX slot or DDI
+ * 12 P_GFX_[T,R]X[P,N]4 - may be used to form GFX slot or DDI
+ * 13 P_GFX_[T,R]X[P,N]5 - may be used to form GFX slot or DDI
+ * 14 P_GFX_[T,R]X[P,N]6 - may be used to form GFX slot or DDI
+ * 15 P_GFX_[T,R]X[P,N]7 - may be used to form GFX slot or DDI
+ * 16 P_GFX_[T,R]X[P,N]8 - may be used to form GFX slot or DDI
+ * 17 P_GFX_[T,R]X[P,N]9 - may be used to form GFX slot or DDI
+ * 18 P_GFX_[T,R]X[P,N]10 - may be used to form GFX slot or DDI
+ * 19 P_GFX_[T,R]X[P,N]11 - may be used to form GFX slot or DDI
+ * 20 P_GFX_[T,R]X[P,N]12 - may be used to form GFX slot or DDI
+ * 21 P_GFX_[T,R]X[P,N]13 - may be used to form GFX slot or DDI
+ * 22 P_GFX_[T,R]X[P,N]14 - may be used to form GFX slot or DDI
+ * 23 P_GFX_[T,R]X[P,N]15 - may be used to form GFX slot or DDI
+ * 24 DP0_TX[P,N]0 - rest is just for DDI (graphics outputs)
+ * 25 DP0_TX[P,N]1
+ * 26 DP0_TX[P,N]2
+ * 27 DP0_TX[P,N]3
+ * 28 DP1_TX[P,N]0
+ * 29 DP1_TX[P,N]1
+ * 30 DP1_TX[P,N]2
+ * 31 DP1_TX[P,N]3
+ * 32 DP2_TX[P,N]0
+ * 33 DP2_TX[P,N]1
+ * 34 DP2_TX[P,N]2
+ * 35 DP2_TX[P,N]3
+ * 36 DP2_TX[P,N]4
+ * 37 DP2_TX[P,N]5
+ * 38 DP2_TX[P,N]6
+ */
+
+static const PCIe_PORT_DESCRIPTOR PortList[] = {
+ /* PCIe port, Lanes 8:23, PCI Device Number 2, blue x16 slot */
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 23),
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 1)
+ },
+ /* PCIe port, Lanes 4:7, PCI Device Number 4, black x16 slot (in fact x4) */
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7),
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 1)
+ },
+ /* PCIe port, Lanes 0:3, UMI link to SB, PCI Device Number 8 */
+ {
+ DESCRIPTOR_TERMINATE_LIST,
+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 0)
+ },
+};
+
+/*
+ * It is not known, if the setup is complete.
+ *
+ * Tested and works: VGA/DVI
+ * Untested: HDMI
+ */
+static const PCIe_DDI_DESCRIPTOR DdiList[] = {
+ // DP0 to HDMI0/DP
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 24, 27),
+ PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux1, Hdp1)
+ },
+ // DP1 to FCH
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 28, 31),
+ PCIE_DDI_DATA_INITIALIZER(ConnectorTypeNutmegDpToVga, Aux2, Hdp2)
+ },
+ // DP2 to HDMI1/DP
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 32, 35),
+ PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux3, Hdp3)
+ },
+};
+
+static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
+ .Flags = DESCRIPTOR_TERMINATE_LIST,
+ .SocketId = 0,
+ .PciePortList = PortList,
+ .DdiLinkList = DdiList,
+};
+
+void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
+{
+ FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface;
+ FchReset->Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
+ FchReset->Xhci1Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
+}
+
+void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
+{
+ InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
+ InitEarly->GnbConfig.PsppPolicy = 0;
+}
+
+/*----------------------------------------------------------------------------------------
+ * CUSTOMER OVERIDES MEMORY TABLE
+ *----------------------------------------------------------------------------------------
+ */
+
+/*
+ * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
+ * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
+ * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
+ * use its default conservative settings.
+ */
+
+static CONST PSO_ENTRY ROMDATA MemoryTable_XM_E[] = {
+
+ NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1),
+ NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2),
+
+ PSO_END
+};
+
+void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
+{
+ if (IS_ENABLED(CONFIG_BOARD_ASUS_A88XM_E))
+ InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *) MemoryTable_XM_E;
+}
+
+void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid)
+{
+ /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
+ InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
+}
diff --git a/src/mainboard/asus/a88xm-e/OptionsIds.h b/src/mainboard/asus/a88xm-e/OptionsIds.h
new file mode 100644
index 0000000..b45f5a8
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/OptionsIds.h
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/**
+ * @file
+ *
+ * IDS Option File
+ *
+ * This file is used to switch on/off IDS features.
+ *
+ */
+#ifndef _OPTION_IDS_H_
+#define _OPTION_IDS_H_
+
+/**
+ *
+ * This file generates the defaults tables for the Integrated Debug Support
+ * Module. The documented build options are imported from a user controlled
+ * file for processing. The build options for the Integrated Debug Support
+ * Module are listed below:
+ *
+ * IDSOPT_IDS_ENABLED
+ * IDSOPT_ERROR_TRAP_ENABLED
+ * IDSOPT_CONTROL_ENABLED
+ * IDSOPT_TRACING_ENABLED
+ * IDSOPT_PERF_ANALYSIS
+ * IDSOPT_ASSERT_ENABLED
+ * IDS_DEBUG_PORT
+ * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
+ *
+ **/
+
+//#define IDSOPT_IDS_ENABLED TRUE
+//#define IDSOPT_CONTROL_ENABLED TRUE
+#define IDSOPT_TRACING_ENABLED TRUE
+#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE
+//#define IDSOPT_PERF_ANALYSIS TRUE
+#define IDSOPT_ASSERT_ENABLED TRUE
+//#undef IDSOPT_DEBUG_ENABLED
+//#define IDSOPT_DEBUG_ENABLED FALSE
+//#undef IDSOPT_HOST_SIMNOW
+//#define IDSOPT_HOST_SIMNOW FALSE
+//#undef IDSOPT_HOST_HDT
+//#define IDSOPT_HOST_HDT FALSE
+//#define IDS_DEBUG_PORT 0x80
+
+#endif
diff --git a/src/mainboard/asus/a88xm-e/acpi/cpstate.asl b/src/mainboard/asus/a88xm-e/acpi/cpstate.asl
new file mode 100644
index 0000000..69de2d8
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/cpstate.asl
@@ -0,0 +1,112 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* This file defines the processor and performance state capability
+ * for each core in the system. It is included into the DSDT for each
+ * core. It assumes that each core of the system has the same performance
+ * characteristics.
+*/
+/*
+#include <arch/acpi.h>
+DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001)
+ {
+ Scope (\_PR) {
+ Processor(CPU0,0,0x808,0x06) {
+ #include "cpstate.asl"
+ }
+ Processor(CPU1,1,0x0,0x0) {
+ #include "cpstate.asl"
+ }
+ Processor(CPU2,2,0x0,0x0) {
+ #include "cpstate.asl"
+ }
+ Processor(CPU3,3,0x0,0x0) {
+ #include "cpstate.asl"
+ }
+ }
+*/
+ /* P-state support: The maximum number of P-states supported by the */
+ /* CPUs we'll use is 6. */
+ /* Get from AMI BIOS. */
+ Name(_PSS, Package(){
+ Package()
+ {
+ 0x00000D48,
+ 0x00011170,
+ 0x00000004,
+ 0x00000004,
+ 0x00000000,
+ 0x00000000
+ },
+
+ Package()
+ {
+ 0x00000AF0,
+ 0x0000C544,
+ 0x00000004,
+ 0x00000004,
+ 0x00000001,
+ 0x00000001
+ },
+
+ Package()
+ {
+ 0x000009C4,
+ 0x0000B3B0,
+ 0x00000004,
+ 0x00000004,
+ 0x00000002,
+ 0x00000002
+ },
+
+ Package()
+ {
+ 0x00000898,
+ 0x0000ABE0,
+ 0x00000004,
+ 0x00000004,
+ 0x00000003,
+ 0x00000003
+ },
+
+ Package()
+ {
+ 0x00000708,
+ 0x0000A410,
+ 0x00000004,
+ 0x00000004,
+ 0x00000004,
+ 0x00000004
+ },
+
+ Package()
+ {
+ 0x00000578,
+ 0x00006F54,
+ 0x00000004,
+ 0x00000004,
+ 0x00000005,
+ 0x00000005
+ }
+ })
+
+ Name(_PCT, Package(){
+ ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
+ ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}
+ })
+
+ Method(_PPC, 0){
+ Return(0)
+ }
diff --git a/src/mainboard/asus/a88xm-e/acpi/gpe.asl b/src/mainboard/asus/a88xm-e/acpi/gpe.asl
new file mode 100644
index 0000000..297db37
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/gpe.asl
@@ -0,0 +1,72 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Scope(\_GPE) { /* Start Scope GPE */
+
+ /* General event 3 */
+ Method(_L03) {
+ /* DBGO("\\_GPE\\_L00\n") */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* Legacy PM event */
+ Method(_L08) {
+ /* DBGO("\\_GPE\\_L08\n") */
+ }
+
+ /* Temp warning (TWarn) event */
+ Method(_L09) {
+ /* DBGO("\\_GPE\\_L09\n") */
+ /* Notify (\_TZ.TZ00, 0x80) */
+ }
+
+ /* USB controller PME# */
+ Method(_L0B) {
+ /* DBGO("\\_GPE\\_L0B\n") */
+ Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* ExtEvent0 SCI event */
+ Method(_L10) {
+ /* DBGO("\\_GPE\\_L10\n") */
+ }
+
+
+ /* ExtEvent1 SCI event */
+ Method(_L11) {
+ /* DBGO("\\_GPE\\_L11\n") */
+ }
+
+ /* GPIO0 or GEvent8 event */
+ Method(_L18) {
+ /* DBGO("\\_GPE\\_L18\n") */
+ Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* Azalia SCI event */
+ Method(_L1B) {
+ /* DBGO("\\_GPE\\_L1B\n") */
+ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+} /* End Scope GPE */
diff --git a/src/mainboard/asus/a88xm-e/acpi/mainboard.asl b/src/mainboard/asus/a88xm-e/acpi/mainboard.asl
new file mode 100644
index 0000000..8398c88
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/mainboard.asl
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+ /* Data to be patched by the BIOS during POST */
+ /* FIXME the patching is not done yet! */
+ /* Memory related values */
+ Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
+ Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
+ Name(PBLN, 0x0) /* Length of BIOS area */
+
+ Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
+ Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
+ Name(HPBA, 0xFED00000) /* Base address of HPET table */
+
+ /* Some global data */
+ Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
+ Name(OSV, Ones) /* Assume nothing */
+ Name(PMOD, One) /* Assume APIC */
diff --git a/src/mainboard/asus/a88xm-e/acpi/routing.asl b/src/mainboard/asus/a88xm-e/acpi/routing.asl
new file mode 100644
index 0000000..0af6b42
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/routing.asl
@@ -0,0 +1,258 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+ /* Routing is in System Bus scope */
+ Name(PR0, Package(){
+ /* NB devices */
+ /* Bus 0, Dev 0 - F15 Host Controller */
+ Package(){0x0000FFFF, 0, INTA, 0 },
+ Package(){0x0000FFFF, 1, INTB, 0 },
+ Package(){0x0000FFFF, 2, INTC, 0 },
+ Package(){0x0000FFFF, 3, INTD, 0 },
+
+ /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
+ Package(){0x0001FFFF, 0, INTB, 0 },
+ Package(){0x0001FFFF, 1, INTC, 0 },
+
+ /* Bus 0, Dev 2 - PCIe Bridge for x16 slot */
+ Package(){0x0002FFFF, 0, INTC, 0 },
+ Package(){0x0002FFFF, 1, INTD, 0 },
+ Package(){0x0002FFFF, 2, INTA, 0 },
+ Package(){0x0002FFFF, 3, INTB, 0 },
+
+ /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
+
+ /* Bus 0, Dev 4 - PCIe Bridge for 4x slot */
+ Package(){0x0004FFFF, 0, INTA, 0 },
+ Package(){0x0004FFFF, 1, INTB, 0 },
+ Package(){0x0004FFFF, 2, INTC, 0 },
+ Package(){0x0004FFFF, 3, INTD, 0 },
+
+ /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
+ /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
+ /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
+ /* Bus 0, Dev 8 - Southbridge port (normally hidden) */
+
+ /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
+ Package(){0x0014FFFF, 0, INTA, 0 },
+ Package(){0x0014FFFF, 1, INTB, 0 },
+ Package(){0x0014FFFF, 2, INTC, 0 },
+ Package(){0x0014FFFF, 3, INTD, 0 },
+
+ /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0
+ * EHCI @ func 2 */
+ Package(){0x0012FFFF, 0, INTC, 0 },
+ Package(){0x0012FFFF, 1, INTB, 0 },
+
+ Package(){0x0013FFFF, 0, INTC, 0 },
+ Package(){0x0013FFFF, 1, INTB, 0 },
+
+ Package(){0x0016FFFF, 0, INTC, 0 },
+ Package(){0x0016FFFF, 1, INTB, 0 },
+
+ /* SB devices */
+ /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */
+ Package(){0x0010FFFF, 0, INTC, 0 },
+ Package(){0x0010FFFF, 1, INTB, 0 },
+
+ /* Bus 0, Dev 17 - SATA controller */
+ Package(){0x0011FFFF, 0, INTD, 0 },
+
+ /* Bus 0, Dev 21 Pcie Bridge */
+ Package(){0x0015FFFF, 0, INTA, 0 },
+ Package(){0x0015FFFF, 1, INTB, 0 },
+ Package(){0x0015FFFF, 2, INTC, 0 },
+ Package(){0x0015FFFF, 3, INTD, 0 },
+ })
+
+ Name(APR0, Package(){
+ /* NB devices in APIC mode */
+ /* Bus 0, Dev 0 - F15 Host Controller */
+ Package(){0x0000FFFF, 0, 0, 16 },
+ Package(){0x0000FFFF, 1, 0, 17 },
+ Package(){0x0000FFFF, 2, 0, 18 },
+ Package(){0x0000FFFF, 3, 0, 19 },
+
+ /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
+ Package(){0x0001FFFF, 0, 0, 17 },
+ Package(){0x0001FFFF, 1, 0, 18 },
+
+ /* Bus 0, Dev 2 - PCIe Bridge for x16 PCIe Slot */
+ Package(){0x0002FFFF, 0, 0, 18 },
+ Package(){0x0002FFFF, 1, 0, 19 },
+ Package(){0x0002FFFF, 2, 0, 16 },
+ Package(){0x0002FFFF, 3, 0, 17 },
+
+ /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
+
+ /* Bus 0, Dev 4 - PCIe Bridge for x4 PCIe Slot black */
+ Package(){0x0004FFFF, 0, 0, 16 },
+ Package(){0x0004FFFF, 1, 0, 17 },
+ Package(){0x0004FFFF, 2, 0, 18 },
+ Package(){0x0004FFFF, 3, 0, 19 },
+
+ /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
+ /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
+ /* Bus 0, Dev 7 - PCIe Bridge for network card */
+ /* Bus 0, Dev 8 - Southbridge port (normally hidden) */
+
+ /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
+ Package(){0x0014FFFF, 0, 0, 16 },
+ Package(){0x0014FFFF, 1, 0, 17 },
+ Package(){0x0014FFFF, 2, 0, 18 },
+ Package(){0x0014FFFF, 3, 0, 19 },
+
+ /* SB devices in APIC mode */
+ /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0
+ * EHCI @ func 2 */
+ Package(){0x0012FFFF, 0, 0, 18 },
+ Package(){0x0012FFFF, 1, 0, 17 },
+
+ Package(){0x0013FFFF, 0, 0, 18 },
+ Package(){0x0013FFFF, 1, 0, 17 },
+
+ Package(){0x0016FFFF, 0, 0, 18 },
+ Package(){0x0016FFFF, 1, 0, 17 },
+
+ /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */
+ Package(){0x0010FFFF, 0, 0, 0x12},
+ Package(){0x0010FFFF, 1, 0, 0x11},
+
+ /* Bus 0, Dev 17 - SATA controller */
+ Package(){0x0011FFFF, 0, 0, 19 },
+
+ /* Bus 0, Dev 21 PCIE Bridge */
+ Package(){0x0015FFFF, 0, 0, 17 },
+ Package(){0x0015FFFF, 1, 0, 18 },
+ Package(){0x0015FFFF, 2, 0, 19 },
+ Package(){0x0015FFFF, 3, 0, 16 },
+ })
+
+ Name(PS2, Package(){
+ /* The external GFX - Hooked to PCIe slot 2 */
+ Package(){0x0000FFFF, 0, INTD, 0 },
+ Package(){0x0000FFFF, 1, INTA, 0 },
+ Package(){0x0000FFFF, 2, INTB, 0 },
+ Package(){0x0000FFFF, 3, INTC, 0 },
+ })
+ Name(APS2, Package(){
+ /* The external GFX - Hooked to PCIe slot 2 */
+ Package(){0x0000FFFF, 0, 0, 18 },
+ Package(){0x0000FFFF, 1, 0, 19 },
+ Package(){0x0000FFFF, 2, 0, 16 },
+ Package(){0x0000FFFF, 3, 0, 17 },
+ })
+
+ /* black slot */
+ Name(PS4, Package(){
+ /* PCIe slot - Hooked to PCIe slot 4 */
+ Package(){0x0000FFFF, 0, INTA, 0 },
+ Package(){0x0000FFFF, 1, INTB, 0 },
+ Package(){0x0000FFFF, 2, INTC, 0 },
+ Package(){0x0000FFFF, 3, INTD, 0 },
+ })
+ Name(APS4, Package(){
+ /* PCIe slot - Hooked to PCIe slot 4 */
+ Package(){0x0000FFFF, 0, 0, 16 },
+ Package(){0x0000FFFF, 1, 0, 17 },
+ Package(){0x0000FFFF, 2, 0, 18 },
+ Package(){0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name(PS5, Package(){
+ /* PCIe slot - Hooked to PCIe slot 5 */
+ Package(){0x0000FFFF, 0, INTB, 0 },
+ Package(){0x0000FFFF, 1, INTC, 0 },
+ Package(){0x0000FFFF, 2, INTD, 0 },
+ Package(){0x0000FFFF, 3, INTA, 0 },
+ })
+ Name(APS5, Package(){
+ /* PCIe slot - Hooked to PCIe slot 5 */
+ Package(){0x0000FFFF, 0, 0, 17 },
+ Package(){0x0000FFFF, 1, 0, 18 },
+ Package(){0x0000FFFF, 2, 0, 19 },
+ Package(){0x0000FFFF, 3, 0, 16 },
+ })
+
+ Name(PS6, Package(){
+ /* PCIe slot - Hooked to PCIe slot 6 */
+ Package(){0x0000FFFF, 0, INTC, 0 },
+ Package(){0x0000FFFF, 1, INTD, 0 },
+ Package(){0x0000FFFF, 2, INTA, 0 },
+ Package(){0x0000FFFF, 3, INTB, 0 },
+ })
+ Name(APS6, Package(){
+ /* PCIe slot - Hooked to PCIe slot 6 */
+ Package(){0x0000FFFF, 0, 0, 18 },
+ Package(){0x0000FFFF, 1, 0, 19 },
+ Package(){0x0000FFFF, 2, 0, 16 },
+ Package(){0x0000FFFF, 3, 0, 17 },
+ })
+
+ Name(PS7, Package(){
+ /* The onboard Ethernet chip - Hooked to PCIe slot 7 */
+ Package(){0x0000FFFF, 0, INTD, 0 },
+ Package(){0x0000FFFF, 1, INTA, 0 },
+ Package(){0x0000FFFF, 2, INTB, 0 },
+ Package(){0x0000FFFF, 3, INTC, 0 },
+ })
+
+ Name(APS7, Package(){
+ /* The onboard Ethernet chip - Hooked to PCIe slot 7 */
+ Package(){0x0000FFFF, 0, 0, 19 },
+ Package(){0x0000FFFF, 1, 0, 16 },
+ Package(){0x0000FFFF, 2, 0, 17 },
+ Package(){0x0000FFFF, 3, 0, 18 },
+ })
+
+ Name(PBR0, Package(){
+ /* PCIx1 on SB */
+ Package(){0x0000FFFF, 0, INTA, 0 },
+ Package(){0x0000FFFF, 1, INTB, 0 },
+ Package(){0x0000FFFF, 2, INTC, 0 },
+ Package(){0x0000FFFF, 3, INTD, 0 },
+ })
+ Name(ABR0, Package(){
+ /* PCIx1 on SB */
+ Package(){0x0000FFFF, 0, 0, 0x10 },
+ Package(){0x0000FFFF, 1, 0, 0x11 },
+ Package(){0x0000FFFF, 2, 0, 0x12 },
+ Package(){0x0000FFFF, 3, 0, 0x13 },
+ })
+
+ Name(PBR1, Package(){
+ /* Onboard network */
+ Package(){0x0000FFFF, 0, INTB, 0 },
+ Package(){0x0000FFFF, 1, INTC, 0 },
+ Package(){0x0000FFFF, 2, INTD, 0 },
+ Package(){0x0000FFFF, 3, INTA, 0 },
+ })
+ Name(ABR1, Package(){
+ /* Onboard network */
+ Package(){0x0000FFFF, 0, 0, 0x11 },
+ Package(){0x0000FFFF, 1, 0, 0x12 },
+ Package(){0x0000FFFF, 2, 0, 0x13 },
+ Package(){0x0000FFFF, 3, 0, 0x10 },
+ })
+
+ /* SB PCI Bridge */
+ Name(PCIB, Package(){
+ /* PCI slots: slot 0 behind Dev14, Fun4. */
+ Package(){0x0005FFFF, 0, 0, 0x14 },
+ Package(){0x0005FFFF, 1, 0, 0x15 },
+ Package(){0x0005FFFF, 2, 0, 0x16 },
+ Package(){0x0005FFFF, 3, 0, 0x17 },
+ })
diff --git a/src/mainboard/asus/a88xm-e/acpi/sata.asl b/src/mainboard/asus/a88xm-e/acpi/sata.asl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/sata.asl
diff --git a/src/mainboard/asus/a88xm-e/acpi/si.asl b/src/mainboard/asus/a88xm-e/acpi/si.asl
new file mode 100644
index 0000000..ff0c3cf
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/si.asl
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+ Scope(\_SI) {
+ Method(_SST, 1) {
+ /* DBGO("\\_SI\\_SST\n") */
+ /* DBGO(" New Indicator state: ") */
+ /* DBGO(Arg0) */
+ /* DBGO("\n") */
+ }
+ } /* End Scope SI */
diff --git a/src/mainboard/asus/a88xm-e/acpi/sleep.asl b/src/mainboard/asus/a88xm-e/acpi/sleep.asl
new file mode 100644
index 0000000..08b7de4
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/sleep.asl
@@ -0,0 +1,96 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* Wake status package */
+Name(WKST,Package(){Zero, Zero})
+
+/*
+* \_PTS - Prepare to Sleep method
+*
+* Entry:
+* Arg0=The value of the sleeping state S1=1, S2=2, etc
+*
+* Exit:
+* -none-
+*
+* The _PTS control method is executed at the beginning of the sleep process
+* for S1-S5. The sleeping value is passed to the _PTS control method. This
+* control method may be executed a relatively long time before entering the
+* sleep state and the OS may abort the operation without notification to
+* the ACPI driver. This method cannot modify the configuration or power
+* state of any device in the system.
+*/
+Method(\_PTS, 1) {
+ /* DBGO("\\_PTS\n") */
+ /* DBGO("From S0 to S") */
+ /* DBGO(Arg0) */
+ /* DBGO("\n") */
+
+ /* Clear sleep SMI status flag and enable sleep SMI trap. */
+ /*Store(One, CSSM)
+ Store(One, SSEN)*/
+
+ /* On older chips, clear PciExpWakeDisEn */
+ /*if (LLessEqual(\_SB.SBRI, 0x13)) {
+ * Store(0,\_SB.PWDE)
+ *}
+ */
+
+ /* Clear wake status structure. */
+ Store(0, Index(WKST,0))
+ Store(0, Index(WKST,1))
+
+ Store (0x07, UPWS)
+} /* End Method(\_PTS) */
+
+/*
+* \_BFS OEM Back From Sleep method
+*
+* Entry:
+* Arg0=The value of the sleeping state S1=1, S2=2
+*
+* Exit:
+* -none-
+*/
+Method(\_BFS, 1) {
+ /* DBGO("\\_BFS\n") */
+ /* DBGO("From S") */
+ /* DBGO(Arg0) */
+ /* DBGO(" to S0\n") */
+}
+
+/*
+* \_WAK System Wake method
+*
+* Entry:
+* Arg0=The value of the sleeping state S1=1, S2=2
+*
+* Exit:
+* Return package of 2 DWords
+* Dword 1 - Status
+* 0x00000000 wake succeeded
+* 0x00000001 Wake was signaled but failed due to lack of power
+* 0x00000002 Wake was signaled but failed due to thermal condition
+* Dword 2 - Power Supply state
+* if non-zero the effective S-state the power supply entered
+*/
+Method(\_WAK, 1) {
+ /* DBGO("\\_WAK\n") */
+ /* DBGO("From S") */
+ /* DBGO(Arg0) */
+ /* DBGO(" to S0\n") */
+
+ Return(WKST)
+} /* End Method(\_WAK) */
diff --git a/src/mainboard/asus/a88xm-e/acpi/superio.asl b/src/mainboard/asus/a88xm-e/acpi/superio.asl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/superio.asl
diff --git a/src/mainboard/asus/a88xm-e/acpi/thermal.asl b/src/mainboard/asus/a88xm-e/acpi/thermal.asl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/thermal.asl
diff --git a/src/mainboard/asus/a88xm-e/acpi/usb_oc.asl b/src/mainboard/asus/a88xm-e/acpi/usb_oc.asl
new file mode 100644
index 0000000..f5d6980
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/usb_oc.asl
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* USB overcurrent mapping pins. */
+Name(UOM0, 0)
+Name(UOM1, 2)
+Name(UOM2, 0)
+Name(UOM3, 7)
+Name(UOM4, 2)
+Name(UOM5, 2)
+Name(UOM6, 6)
+Name(UOM7, 2)
+Name(UOM8, 6)
+Name(UOM9, 6)
diff --git a/src/mainboard/asus/a88xm-e/acpi_tables.c b/src/mainboard/asus/a88xm-e/acpi_tables.c
new file mode 100644
index 0000000..f94fde0
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi_tables.c
@@ -0,0 +1,46 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
+#include <arch/ioapic.h>
+#include <device/pci.h>
+#include <string.h>
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+ /* create all subtables for processors */
+ current = acpi_create_madt_lapics(current);
+
+ /* Write Hudson IOAPIC, only one */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS,
+ IO_APIC_ADDR, 0);
+
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 0, 2, 0);
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 9, 9, 0xF);
+ /* 0: mean bus 0--->ISA */
+ /* 0: PIC 0 */
+ /* 2: APIC 2 */
+ /* 5 mean: 0101 --> Edge-triggered, Active high */
+
+ /* create all subtables for processors */
+ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1);
+ /* 1: LINT1 connect to NMI */
+
+ return current;
+}
diff --git a/src/mainboard/asus/a88xm-e/board_info.txt b/src/mainboard/asus/a88xm-e/board_info.txt
new file mode 100644
index 0000000..bc090ff
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/board_info.txt
@@ -0,0 +1,7 @@
+Category: desktop
+Board URL: https://www.asus.com/Motherboards/A88XME/
+ROM package: DIP8
+ROM protocol: [http://www.winbond.com/hq/product/code-storage-flash-memory/serial-nor-flas… SPI]
+ROM socketed: y
+Flashrom support: y (without AmdSpiRomProtect modules)
+Release year: 2014
diff --git a/src/mainboard/asus/a88xm-e/buildOpts.c b/src/mainboard/asus/a88xm-e/buildOpts.c
new file mode 100644
index 0000000..c324532
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/buildOpts.c
@@ -0,0 +1,346 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/**
+ * @file
+ *
+ * AMD User options selection for a Brazos platform solution system
+ *
+ * This file is placed in the user's platform directory and contains the
+ * build option selections desired for that platform.
+ *
+ * For Information about this file, see @ref platforminstall.
+ *
+ */
+
+#include <stdlib.h>
+
+#include <vendorcode/amd/agesa/f15tn/AGESA.h>
+
+/* Include the files that instantiate the configuration definitions. */
+#include <vendorcode/amd/agesa/f15tn/Include/AdvancedApi.h>
+#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h>
+#include <vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.h>
+#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h>
+/* the next two headers depend on heapManager.h */
+#include <vendorcode/amd/agesa/f15tn/Proc/Common/CreateStruct.h>
+#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEarlyInit.h>
+/* These tables are optional and may be used to adjust memory timing settings */
+#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mm.h>
+#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h>
+
+
+/* Select the CPU family. */
+#define INSTALL_FAMILY_10_SUPPORT FALSE
+#define INSTALL_FAMILY_12_SUPPORT FALSE
+#define INSTALL_FAMILY_14_SUPPORT FALSE
+#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE
+
+/* Select the CPU socket type. */
+#define INSTALL_G34_SOCKET_SUPPORT FALSE
+#define INSTALL_C32_SOCKET_SUPPORT FALSE
+#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
+#define INSTALL_S1G4_SOCKET_SUPPORT FALSE
+#define INSTALL_ASB2_SOCKET_SUPPORT FALSE
+#define INSTALL_FS1_SOCKET_SUPPORT FALSE
+#define INSTALL_FM1_SOCKET_SUPPORT FALSE
+#define INSTALL_FP2_SOCKET_SUPPORT FALSE
+#define INSTALL_FT1_SOCKET_SUPPORT FALSE
+#define INSTALL_AM3_SOCKET_SUPPORT FALSE
+
+#define INSTALL_FM2_SOCKET_SUPPORT TRUE
+
+//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE
+#define BLDOPT_REMOVE_SODIMMS_SUPPORT TRUE
+#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE
+#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE
+#define BLDOPT_REMOVE_ECC_SUPPORT TRUE
+//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE
+//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE
+#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE
+#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE
+#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE
+//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE
+#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE
+//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE
+#define BLDOPT_REMOVE_SRAT FALSE //TRUE
+#define BLDOPT_REMOVE_SLIT FALSE //TRUE
+#define BLDOPT_REMOVE_WHEA FALSE //TRUE
+#define BLDOPT_REMOVE_CRAT TRUE
+#define BLDOPT_REMOVE_DMI TRUE
+//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE
+
+//This element selects whether P-States should be forced to be independent,
+// as reported by the ACPI _PSD object. For single-link processors,
+// setting TRUE for OS to support this feature.
+
+//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE
+
+#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS
+#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER
+/* Build configuration values here.
+ */
+#define BLDCFG_VRM_CURRENT_LIMIT 90000
+#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0
+#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 0
+#define BLDCFG_PLAT_NUM_IO_APICS 3
+#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
+#define BLDCFG_MEM_INIT_PSTATE 0
+
+#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
+
+#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY
+#define BLDCFG_MEMORY_MODE_UNGANGED TRUE
+#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE
+#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
+#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE
+#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE
+#define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE
+#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE
+#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE
+#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE
+#define BLDCFG_MEMORY_POWER_DOWN TRUE
+#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT
+#define BLDCFG_ONLINE_SPARE FALSE
+#define BLDCFG_BANK_SWIZZLE TRUE
+#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
+#define BLDCFG_MEMORY_CLOCK_SELECT DDR1600_FREQUENCY
+#define BLDCFG_DQS_TRAINING_CONTROL TRUE
+#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE
+#define BLDCFG_USE_BURST_MODE FALSE
+#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE
+#define BLDCFG_ENABLE_ECC_FEATURE FALSE
+#define BLDCFG_ECC_REDIRECTION FALSE
+#define BLDCFG_SCRUB_DRAM_RATE 0
+#define BLDCFG_SCRUB_L2_RATE 0
+#define BLDCFG_SCRUB_L3_RATE 0
+#define BLDCFG_SCRUB_IC_RATE 0
+#define BLDCFG_SCRUB_DC_RATE 0
+#define BLDCFG_ECC_SYMBOL_SIZE 4
+#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000
+#define BLDCFG_ECC_SYNC_FLOOD FALSE
+#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE
+#define BLDCFG_1GB_ALIGN FALSE
+#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE
+#define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 // PCIE Spread Spectrum default value 0.36%
+#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770
+
+#define BLDOPT_REMOVE_ALIB FALSE
+#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto
+#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P'
+#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0'
+#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6
+
+#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 200
+#define BLDCFG_CFG_ABM_SUPPORT 0
+
+//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770
+
+// Specify the default values for the VRM controlling the VDDNB plane.
+// If not specified, the values used for the core VRM will be applied
+//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 // Not currently used on Trinity
+//#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L
+//#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in calculating the VSRampSlamTime
+//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 // Not currently used on Trinity
+//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE 0 // Not currently used on Trinity
+//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 // Not currently used on Trinity
+
+#define BLDCFG_VRM_NB_CURRENT_LIMIT 60000
+
+#define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3
+#define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3
+
+#if IS_ENABLED(CONFIG_GFXUMA)
+#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED
+#define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED
+//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/
+#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M
+#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE
+#endif
+
+#define BLDCFG_IOMMU_SUPPORT TRUE
+
+#define BLDCFG_CFG_GNB_HD_AUDIO TRUE
+//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID
+//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID
+//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID
+
+/* Process the options...
+ * This file include MUST occur AFTER the user option selection settings
+ */
+/*
+ * Customized OEM build configurations for FCH component
+ */
+// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00
+// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20
+// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00
+// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400
+// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404
+// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408
+// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410
+// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420
+// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000
+// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000
+// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000
+// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0
+// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00
+// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000
+// #define BLDCFG_AZALIA_SSID 0x780D1022
+// #define BLDCFG_SMBUS_SSID 0x780B1022
+// #define BLDCFG_IDE_SSID 0x780C1022
+// #define BLDCFG_SATA_AHCI_SSID 0x78011022
+// #define BLDCFG_SATA_IDE_SSID 0x78001022
+// #define BLDCFG_SATA_RAID5_SSID 0x78031022
+// #define BLDCFG_SATA_RAID_SSID 0x78021022
+// #define BLDCFG_EHCI_SSID 0x78081022
+// #define BLDCFG_OHCI_SSID 0x78071022
+// #define BLDCFG_LPC_SSID 0x780E1022
+// #define BLDCFG_SD_SSID 0x78061022
+// #define BLDCFG_XHCI_SSID 0x78121022
+// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE
+// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE
+// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4
+// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE
+// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE
+// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE
+// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE
+// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE
+// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE
+// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE
+// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE
+
+CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
+{
+ { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E },
+ { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E },
+ { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 },
+ { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 },
+ { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 },
+ { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 },
+ { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 },
+ { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 },
+ { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 },
+ { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 },
+ { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 },
+ { CPU_LIST_TERMINAL }
+};
+
+#define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList
+
+ // This is the delivery package title, "BrazosPI"
+ // This string MUST be exactly 8 characters long
+#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'}
+
+ // This is the release version number of the AGESA component
+ // This string MUST be exactly 12 characters long
+#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '}
+
+/* MEMORY_BUS_SPEED */
+#define DDR400_FREQUENCY 200 ///< DDR 400
+#define DDR533_FREQUENCY 266 ///< DDR 533
+#define DDR667_FREQUENCY 333 ///< DDR 667
+#define DDR800_FREQUENCY 400 ///< DDR 800
+#define DDR1066_FREQUENCY 533 ///< DDR 1066
+#define DDR1333_FREQUENCY 667 ///< DDR 1333
+#define DDR1600_FREQUENCY 800 ///< DDR 1600
+#define DDR1866_FREQUENCY 933 ///< DDR 1866
+#define DDR2100_FREQUENCY 1050 ///< DDR 2100
+#define DDR2133_FREQUENCY 1066 ///< DDR 2133
+#define DDR2400_FREQUENCY 1200 ///< DDR 2400
+#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency
+
+/* QUANDRANK_TYPE*/
+#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
+#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
+
+/* USER_MEMORY_TIMING_MODE */
+#define TIMING_MODE_AUTO 0 ///< Use best rate possible
+#define TIMING_MODE_LIMITED 1 ///< Set user top limit
+#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
+
+/* POWER_DOWN_MODE */
+#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
+#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
+
+/*
+ * Agesa optional capabilities selection.
+ * Uncomment and mark FALSE those features you wish to include in the build.
+ * Comment out or mark TRUE those features you want to REMOVE from the build.
+ */
+
+#define DFLT_SMBUS0_BASE_ADDRESS 0xB00
+#define DFLT_SMBUS1_BASE_ADDRESS 0xB20
+/* The AGESA likes to enable 512 bytes region on this base for LPC bus */
+#define DFLT_SIO_PME_BASE_ADDRESS 0xE00
+#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800
+#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804
+#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808
+#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810
+#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820
+#define DFLT_SPI_BASE_ADDRESS 0xFEC10000
+#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0
+#define DFLT_HPET_BASE_ADDRESS 0xFED00000
+#define DFLT_SMI_CMD_PORT 0xB0
+#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00
+#define DFLT_GEC_BASE_ADDRESS 0xFED61000
+#define DFLT_AZALIA_SSID 0x780D1022
+#define DFLT_SMBUS_SSID 0x780B1022
+#define DFLT_IDE_SSID 0x780C1022
+#define DFLT_SATA_AHCI_SSID 0x78011022
+#define DFLT_SATA_IDE_SSID 0x78001022
+#define DFLT_SATA_RAID5_SSID 0x78031022
+#define DFLT_SATA_RAID_SSID 0x78021022
+#define DFLT_EHCI_SSID 0x78081022
+#define DFLT_OHCI_SSID 0x78071022
+#define DFLT_LPC_SSID 0x780E1022
+#define DFLT_SD_SSID 0x78061022
+#define DFLT_XHCI_SSID 0x78121022
+#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE
+#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE
+#define DFLT_FCH_GPP_LINK_CONFIG PortA1B1C1D1
+#define DFLT_FCH_GPP_PORT0_PRESENT TRUE
+#define DFLT_FCH_GPP_PORT1_PRESENT TRUE
+#define DFLT_FCH_GPP_PORT2_PRESENT FALSE
+#define DFLT_FCH_GPP_PORT3_PRESENT FALSE
+#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE
+#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE
+#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE
+#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE
+//#define BLDCFG_IR_PIN_CONTROL 0x33
+//#define FCH_NO_XHCI_SUPPORT FALSE
+GPIO_CONTROL a88xm_e_gpio[] = {
+// {183, Function1, PullUpB},
+ {-1}
+};
+#define BLDCFG_FCH_GPIO_CONTROL_LIST (&a88xm_e_gpio[0])
+
+// The following definitions specify the default values for various parameters in which there are
+// no clearly defined defaults to be used in the common file. The values below are based on product
+// and BKDG content, please consult the AGESA Memory team for consultation.
+#define DFLT_SCRUB_DRAM_RATE (0)
+#define DFLT_SCRUB_L2_RATE (0)
+#define DFLT_SCRUB_L3_RATE (0)
+#define DFLT_SCRUB_IC_RATE (0)
+#define DFLT_SCRUB_DC_RATE (0)
+#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
+#define DFLT_VRM_SLEW_RATE (5000)
+
+/* Moving this include up will break AGESA. */
+#include <PlatformInstall.h>
diff --git a/src/mainboard/asus/a88xm-e/cmos.layout b/src/mainboard/asus/a88xm-e/cmos.layout
new file mode 100644
index 0000000..e1dbd9a
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/cmos.layout
@@ -0,0 +1,66 @@
+#*****************************************************************************
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#*****************************************************************************
+
+entries
+
+0 384 r 0 reserved_memory
+384 1 e 4 boot_option
+388 4 h 0 reboot_counter
+#392 3 r 0 unused
+395 1 e 1 hw_scrubber
+396 1 e 1 interleave_chip_selects
+397 2 e 8 max_mem_clock
+399 1 e 2 multi_core
+400 1 e 1 power_on_after_fail
+412 4 e 6 debug_level
+440 4 e 9 slow_cpu
+444 1 e 1 nmi
+445 1 e 1 iommu
+456 1 e 1 ECC_memory
+728 256 h 0 user_data
+984 16 h 0 check_sum
+# Reserve the extended AMD configuration registers
+1000 24 r 0 amd_reserved
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+6 5 Notice
+6 6 Info
+6 7 Debug
+6 8 Spew
+8 0 400Mhz
+8 1 333Mhz
+8 2 266Mhz
+8 3 200Mhz
+9 0 off
+9 1 87.5%
+9 2 75.0%
+9 3 62.5%
+9 4 50.0%
+9 5 37.5%
+9 6 25.0%
+9 7 12.5%
+
+checksums
+
+checksum 392 983 984
diff --git a/src/mainboard/asus/a88xm-e/devicetree_a88xm-e.cb b/src/mainboard/asus/a88xm-e/devicetree_a88xm-e.cb
new file mode 100644
index 0000000..e2b0eea
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/devicetree_a88xm-e.cb
@@ -0,0 +1,143 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+chip northbridge/amd/agesa/family15tn/root_complex
+
+ device cpu_cluster 0 on
+ chip cpu/amd/agesa/family15tn
+ device lapic 10 on end
+ end
+ end
+
+ device domain 0 on
+ subsystemid 0x1022 0x1410 inherit
+ chip northbridge/amd/agesa/family15tn # CPU side of HT root complex
+
+ chip northbridge/amd/agesa/family15tn # PCI side of HT root complex
+ device pci 0.0 on end # Root Complex
+ device pci 0.2 on end # IOMMU
+ device pci 1.0 on end # Internal Graphics
+ device pci 1.1 on end # Internal Audio (iGPU)
+ device pci 2.0 on end # PCIE x4/x16 yellow (?)
+ device pci 3.0 on end # unused?
+ device pci 4.0 on end # PCIE x4/x16 yellow (?)
+ device pci 5.0 off end # unused
+ device pci 6.0 off end # unused?
+ device pci 7.0 off end # LAN
+ device pci 8.0 off end # NB/SB Link P2P bridge
+ end #chip northbridge/amd/agesa/family15tn # PCI side of HT root complex
+
+ chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus
+ device pci 10.0 on end # XHCI HC0
+ device pci 10.1 on end # XHCI HC1
+ device pci 11.0 on end # SATA
+ device pci 12.0 on end # USB
+ device pci 12.2 on end # USB
+ device pci 13.0 on end # USB
+ device pci 13.2 on end # USB
+ device pci 14.0 on # SMBUS
+ chip drivers/generic/generic #dimm 0
+ device i2c 50 on end # 7-bit SPD address
+ end
+ chip drivers/generic/generic #dimm 1
+ device i2c 51 on end # 7-bit SPD address
+ end
+ end # SM
+ device pci 14.1 off end # IDE 0x439c
+ device pci 14.2 on end # HDA 0x4383
+ device pci 14.3 on # LPC 0x439d
+ chip superio/ite/it8728f
+ register "TMPIN1.mode" = "THERMAL_RESISTOR"
+ register "TMPIN2.mode" = "THERMAL_RESISTOR"
+ register "TMPIN3.mode" = "THERMAL_RESISTOR"
+
+ register "FAN1.mode" = "FAN_SMART_AUTOMATIC"
+ register "FAN1.smart.tmpin" = "1"
+ register "FAN1.smart.tmp_off" = "0x80" # never
+ register "FAN1.smart.tmp_start" = "20"
+ register "FAN1.smart.tmp_full" = "70"
+ register "FAN1.smart.tmp_delta" = "0"
+ register "FAN1.smart.smoothing" = "1"
+ register "FAN1.smart.pwm_start" = "20"
+ register "FAN1.smart.slope" = "32"
+
+ # Enable tacho reading for chassis fan.
+ register "FAN2.mode" = "FAN_MODE_OFF"
+
+ device pnp 2e.0 off # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.2 off # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.3 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.4 on # Env Controller
+ io 0x60 = 0x290
+ io 0x62 = 0x220
+ irq 0x70 = 0
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ end
+ device pnp 2e.6 off # Mouse
+ irq 0x70 = 12
+ end
+ device pnp 2e.7 on # GPIO
+ io 0x60 = 0x228 #SMI
+ io 0x62 = 0x300 #Simple I/O
+ io 0x64 = 0x238 #Phony resource IT8603E does not have it
+ irq 0x70 = 0
+ end
+ device pnp 2e.a off end # CIR
+ end #superio/ite/it8728f
+ end #
+ device pci 14.3 off end # LPC
+ device pci 14.4 on end # PCI 0x4384
+ device pci 14.5 off end # USB 2
+ device pci 14.6 off end # Gec
+ device pci 14.7 off end # SD
+ device pci 15.0 on end # PCIe 0 - onboard PCIe 1x
+ device pci 15.1 off end # unused
+ device pci 15.2 on end # PCI bridge
+ device pci 15.3 off end # unused
+ end #chip southbridge/amd/agesa/hudson
+
+ device pci 18.0 on end
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ device pci 18.4 on end
+ device pci 18.5 on end
+
+ register "spdAddrLookup" = "
+ {
+ { {0xA0, 0x00}, {0xA2, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
+ { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
+ }"
+
+ end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex
+ end #domain
+end #chip northbridge/amd/agesa/family15tn/root_complex
diff --git a/src/mainboard/asus/a88xm-e/dsdt.asl b/src/mainboard/asus/a88xm-e/dsdt.asl
new file mode 100644
index 0000000..45a2606
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/dsdt.asl
@@ -0,0 +1,110 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* DefinitionBlock Statement */
+#include <arch/acpi.h>
+DefinitionBlock (
+ "DSDT.AML", /* Output filename */
+ "DSDT", /* Signature */
+ 0x02, /* DSDT Revision, needs to be 2 for 64bit */
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x00010001 /* OEM Revision */
+ )
+{ /* Start of ASL file */
+ /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */
+
+ /* Globals for the platform */
+ #include "acpi/mainboard.asl"
+
+ /* Describe the USB Overcurrent pins */
+ #include "acpi/usb_oc.asl"
+
+ /* PCI IRQ mapping for the Southbridge */
+ #include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
+
+ /* Describe the processor tree (\_PR) */
+ #include <cpu/amd/agesa/family15tn/acpi/cpu.asl>
+
+ /* Describe the supported Sleep States for this Southbridge */
+ #include <southbridge/amd/common/acpi/sleepstates.asl>
+
+ /* Describe the Sleep Methods (WAK, PTS, GTS, etc.) for this platform */
+ #include "acpi/sleep.asl"
+
+ Scope(\_SB) {
+ /* global utility methods expected within the \_SB scope */
+ #include <arch/x86/acpi/globutil.asl>
+
+ /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
+ #include "acpi/routing.asl"
+
+ Device(PWRB) {
+ Name(_HID, EISAID("PNP0C0C"))
+ Name(_UID, 0xAA)
+ Name(_PRW, Package () {3, 0x04})
+ Name(_STA, 0x0B)
+ }
+
+ Device(PCI0) {
+ /* Describe the AMD Northbridge */
+ #include <northbridge/amd/agesa/family15tn/acpi/northbridge.asl>
+
+ /* Describe the AMD Fusion Controller Hub Southbridge */
+ #include <southbridge/amd/agesa/hudson/acpi/fch.asl>
+
+ /**
+ * TODO: The devices listed here (SBR0 and SBR1) do not appear to
+ * be referenced anywhere and could possibly be removed.
+ */
+ Device(SBR0) { /* PCIe 1x SB */
+ Name(_ADR, 0x00150000)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(ABR0) } /* APIC mode */
+ Return (PBR0) /* PIC mode */
+ }
+ }
+
+ Device(SBR1) { /* Onboard network */
+ Name(_ADR, 0x00150001)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT, 0) {
+ If(PMOD){ Return(ABR1) } /* APIC mode */
+ Return (PBR1) /* PIC mode */
+ }
+ }
+ }
+
+ /* Describe PCI INT[A-H] for the Southbridge */
+ #include <southbridge/amd/agesa/hudson/acpi/pci_int.asl>
+
+ } /* End Scope(_SB) */
+
+ /* Describe SMBUS for the Southbridge */
+ #include <southbridge/amd/agesa/hudson/acpi/smbus.asl>
+
+ /* Define the General Purpose Events for the platform */
+ #include "acpi/gpe.asl"
+
+ /* Define the Thermal zones and methods for the platform */
+ #include "acpi/thermal.asl"
+
+ /* Define the System Indicators for the platform */
+ #include "acpi/si.asl"
+
+}
+/* End of ASL file */
diff --git a/src/mainboard/asus/a88xm-e/irq_tables.c b/src/mainboard/asus/a88xm-e/irq_tables.c
new file mode 100644
index 0000000..88d2160
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/irq_tables.c
@@ -0,0 +1,101 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/pirq_routing.h>
+#include <console/console.h>
+#include <device/pci_def.h>
+#include <stdint.h>
+#include <string.h>
+
+static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
+ u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
+ u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
+ u8 slot, u8 rfu)
+{
+ pirq_info->bus = bus;
+ pirq_info->devfn = devfn;
+ pirq_info->irq[0].link = link0;
+ pirq_info->irq[0].bitmap = bitmap0;
+ pirq_info->irq[1].link = link1;
+ pirq_info->irq[1].bitmap = bitmap1;
+ pirq_info->irq[2].link = link2;
+ pirq_info->irq[2].bitmap = bitmap2;
+ pirq_info->irq[3].link = link3;
+ pirq_info->irq[3].bitmap = bitmap3;
+ pirq_info->slot = slot;
+ pirq_info->rfu = rfu;
+}
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+ struct irq_routing_table *pirq;
+ struct irq_info *pirq_info;
+ u32 slot_num;
+ u8 *v;
+
+ u8 sum = 0;
+ int i;
+
+ /* Align the table to be 16 byte aligned. */
+ addr += 15;
+ addr &= ~15;
+
+ /* This table must be between 0xf0000 & 0x100000 */
+ printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
+
+ pirq = (void *)(addr);
+ v = (u8 *) (addr);
+
+ pirq->signature = PIRQ_SIGNATURE;
+ pirq->version = PIRQ_VERSION;
+
+ pirq->rtr_bus = 0;
+ pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
+
+ pirq->exclusive_irqs = 0;
+
+ pirq->rtr_vendor = 0x1002;
+ pirq->rtr_device = 0x4384;
+
+ pirq->miniport_data = 0;
+
+ memset(pirq->rfu, 0, sizeof(pirq->rfu));
+
+ pirq_info = (void *)(&pirq->checksum + 1);
+ slot_num = 0;
+
+ /* pci bridge */
+ write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4),
+ 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
+ 0);
+ pirq_info++;
+
+ slot_num++;
+
+ pirq->size = 32 + 16 * slot_num;
+
+ for (i = 0; i < pirq->size; i++)
+ sum += v[i];
+
+ sum = pirq->checksum - sum;
+
+ if (sum != pirq->checksum) {
+ pirq->checksum = sum;
+ }
+
+ printk(BIOS_INFO, "write_pirq_routing_table done.\n");
+
+ return (unsigned long)pirq_info;
+}
diff --git a/src/mainboard/asus/a88xm-e/mainboard.c b/src/mainboard/asus/a88xm-e/mainboard.c
new file mode 100644
index 0000000..2a0e618
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/mainboard.c
@@ -0,0 +1,46 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/msr.h>
+#include <device/device.h>
+
+/*************************************************
+ * enable the dedicated function in thatcher board.
+ *************************************************/
+static void mainboard_enable(struct device *dev)
+{
+ msr_t msr;
+
+ printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
+
+ msr = rdmsr(LS_CFG_MSR);
+ msr.lo &= ~(1 << 28);
+ wrmsr(LS_CFG_MSR, msr);
+
+ msr = rdmsr(DC_CFG_MSR);
+ msr.lo &= ~(1 << 4);
+ msr.lo &= ~(1 << 13);
+ wrmsr(DC_CFG_MSR, msr);
+
+ msr = rdmsr(BU_CFG_MSR);
+ msr.lo &= ~(1 << 23);
+ wrmsr(BU_CFG_MSR, msr);
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/asus/a88xm-e/mptable.c b/src/mainboard/asus/a88xm-e/mptable.c
new file mode 100644
index 0000000..d97663d
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/mptable.c
@@ -0,0 +1,181 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <arch/ioapic.h>
+#include <arch/smp/mpspec.h>
+#include <cpu/x86/lapic.h>
+#include <device/pci.h>
+#include <stdint.h>
+#include <string.h>
+#include <southbridge/amd/agesa/hudson/hudson.h>
+
+u8 picr_data[] = {
+ 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
+ 0x09,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x1F,0x1F,0x1F,0x1F
+};
+u8 intr_data[0x54] = {
+ 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
+ 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x10,0x11,0x12,0x13
+};
+
+static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length)
+{
+ mc->mpc_length += length;
+ mc->mpc_entry_count++;
+}
+
+static void my_smp_write_bus(struct mp_config_table *mc,
+ unsigned char id, const char *bustype)
+{
+ struct mpc_config_bus *mpc;
+ mpc = smp_next_mpc_entry(mc);
+ memset(mpc, '\0', sizeof(*mpc));
+ mpc->mpc_type = MP_BUS;
+ mpc->mpc_busid = id;
+ memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
+ smp_add_mpc_entry(mc, sizeof(*mpc));
+}
+
+static void *smp_write_config_table(void *v)
+{
+ struct mp_config_table *mc;
+ int bus_isa;
+ u8 byte;
+
+ /*
+ * By the time this function gets called, the IOAPIC registers
+ * have been written so they can be read to get the correct
+ * APIC ID and Version
+ */
+ u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
+
+ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+
+ mptable_init(mc, LOCAL_APIC_ADDR);
+ memcpy(mc->mpc_oem, "AMD ", 8);
+
+ smp_write_processors(mc);
+
+ //mptable_write_buses(mc, NULL, &bus_isa);
+ my_smp_write_bus(mc, 0, "PCI ");
+ my_smp_write_bus(mc, 1, "PCI ");
+ bus_isa = 0x02;
+ my_smp_write_bus(mc, bus_isa, "ISA ");
+
+ /* I/O APICs: APIC ID Version State Address */
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
+
+ /* PIC IRQ routine */
+ for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
+ outb(byte, 0xC00);
+ outb(picr_data[byte], 0xC01);
+ }
+
+ /* APIC IRQ routine */
+ for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
+ outb(byte | 0x80, 0xC00);
+ outb(intr_data[byte], 0xC01);
+ }
+
+ /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
+#define IO_LOCAL_INT(type, intr, apicid, pin) \
+ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
+ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
+
+ /* PCI interrupts are level triggered, and are
+ * associated with a specific bus/device/function tuple.
+ */
+#define PCI_INT(bus, dev, int_sign, pin) \
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
+
+ /* IOMMU */
+ PCI_INT(0x0, 0x0, 0x0, 0x10);
+ PCI_INT(0x0, 0x0, 0x1, 0x11);
+ PCI_INT(0x0, 0x0, 0x2, 0x12);
+ PCI_INT(0x0, 0x0, 0x3, 0x13);
+
+ /* Internal VGA */
+ PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
+ PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
+
+ /* SMBUS */
+ PCI_INT(0x0, 0x14, 0x0, 0x10);
+
+ /* HD Audio */
+ PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]);
+
+ /* USB */
+ PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]);
+ PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
+ PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
+ PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
+ PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
+ PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
+ PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]);
+
+ /* sata */
+ PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]);
+ PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
+
+ /* on board NIC & Slot PCIE. */
+
+ /* PCI slots */
+ struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+ }
+
+ /* PCIe Lan*/
+ PCI_INT(0x0, 0x06, 0x0, 0x13);
+
+ /* FCH PCIe PortA */
+ PCI_INT(0x0, 0x15, 0x0, 0x10);
+ /* FCH PCIe PortB */
+ PCI_INT(0x0, 0x15, 0x1, 0x11);
+ /* FCH PCIe PortC */
+ PCI_INT(0x0, 0x15, 0x2, 0x12);
+ /* FCH PCIe PortD */
+ PCI_INT(0x0, 0x15, 0x3, 0x13);
+
+ /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
+ IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
+ IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
+ /* There is no extension information... */
+
+ /* Compute the checksums */
+ return mptable_finalize(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+ void *v;
+ v = smp_write_floating_table(addr, 0);
+ return (unsigned long)smp_write_config_table(v);
+}
diff --git a/src/mainboard/asus/a88xm-e/romstage.c b/src/mainboard/asus/a88xm-e/romstage.c
new file mode 100644
index 0000000..0a85c27
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/romstage.c
@@ -0,0 +1,102 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2012 Rudolf Marek <r.marek(a)assembler.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+
+#include <northbridge/amd/agesa/state_machine.h>
+#include <southbridge/amd/common/amd_defs.h>
+#include <southbridge/amd/agesa/hudson/hudson.h>
+#include <southbridge/amd/agesa/hudson/smbus.h>
+#include <stdint.h>
+#include <string.h>
+
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8728f/it8728f.h>
+
+#define MMIO_NON_POSTED_START 0xfed00000
+#define MMIO_NON_POSTED_END 0xfedfffff
+#define SB_MMIO_MISC32(x) *(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR + 0xE00 + (x))
+
+static void sbxxx_enable_48mhzout(void)
+{
+ /* most likely programming to 48MHz out signal */
+ u32 reg32;
+ reg32 = SB_MMIO_MISC32(0x28);
+ reg32 &= 0xffc7ffff;
+ reg32 |= 0x00100000;
+ SB_MMIO_MISC32(0x28) = reg32;
+
+ reg32 = SB_MMIO_MISC32(0x40);
+ reg32 &= ~0x80u;
+ SB_MMIO_MISC32(0x40) = reg32;
+}
+
+static void superio_init_e(void)
+{
+ pnp_devfn_t uart = PNP_DEV(0x2e, IT8728F_SP1);
+ pnp_devfn_t gpio = PNP_DEV(0x2e, IT8728F_GPIO);
+
+ ite_kill_watchdog(gpio);
+ ite_enable_serial(uart, CONFIG_TTYS0_BASE);
+ ite_enable_3vsbsw(gpio);
+}
+
+void board_BeforeAgesa(struct sysinfo *cb)
+{
+ u8 byte;
+ pci_devfn_t dev;
+
+ if (IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE))
+ hudson_pci_port80();
+ else if (IS_ENABLED(CONFIG_POST_DEVICE_LPC))
+ hudson_lpc_port80();
+
+ /* enable SIO LPC decode */
+ dev = PCI_DEV(0, 0x14, 3);
+ byte = pci_read_config8(dev, 0x48);
+ byte |= 3; /* 2e, 2f */
+ pci_write_config8(dev, 0x48, byte);
+
+ /* enable serial decode */
+ byte = pci_read_config8(dev, 0x44);
+ byte |= (1 << 6); /* 0x3f8 */
+ pci_write_config8(dev, 0x44, byte);
+
+ post_code(0x30);
+
+ /* enable SB MMIO space */
+ outb(0x24, 0xcd6);
+ outb(0x1, 0xcd7);
+
+ /* enable SIO clock */
+ sbxxx_enable_48mhzout();
+
+ if (IS_ENABLED(CONFIG_BOARD_ASUS_A88XM_E))
+ superio_init_e();
+
+ /* turn on secondary smbus at b20 */
+ outb(0x28, 0xcd6);
+ byte = inb(0xcd7);
+ byte |= 1;
+ outb(byte, 0xcd7);
+
+ /* set DDR3 voltage */
+ byte = CONFIG_BOARD_ASUS_A88XM_E_DDR3_VOLT_VAL;
+
+ /* default is byte = 0x0, so no need to set it in this case */
+ if (byte)
+ do_smbus_write_byte(0xb20, 0x15, 0x3, byte);
+}
--
To view, visit https://review.coreboot.org/c/coreboot/+/30987
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I60fa0636ba41f5f1a6a3faa2764bf2f0a968cf90
Gerrit-Change-Number: 30987
Gerrit-PatchSet: 1
Gerrit-Owner: Balázs Vinarz <vinibali1(a)gmail.com>
Gerrit-MessageType: newchange
1 month, 2 weeks
- 9
- 252
Change in ...coreboot[master]: SeaBIOS - unofficial patches: advanced_bootmenu and multiple_floppies
by mikeb mikeb (Code Review)
Hello Mike Banon,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/32351
to review the following change.
Change subject: SeaBIOS - unofficial patches: advanced_bootmenu and multiple_floppies
......................................................................
SeaBIOS - unofficial patches: advanced_bootmenu and multiple_floppies
If you'd like to add the useful floppies to your coreboot (read about them at
http://dangerousprototypes.com/docs/Lenovo_G505S_hacking#Useful_floppies ), or
to use your USB numpad for choosing a SeaBIOS boot entry, then this change is
for you! It contains two valuable patches together with a Makefile mod needed to
automatically apply these patches to a cloned SeaBIOS before its' compilation.
advanced_bootmenu: up to 35 entries (2 pages if >18), numpad support (console)
https://mail.coreboot.org/hyperkitty/list/seabios@seabios.org/thread/CKWLNT…
[PATCH v2] ramdisk: search for all available floppy images instead of one
https://mail.coreboot.org/pipermail/seabios/2018-December/012670.html
Patch descriptions are available at these links, and just in case here's a copy:
advanced_bootmenu: up to 35 entries (2 pages if >18), numpad support (console)
Add support for up to 35 boot menu entries (2 pages if >18). To solve the
">10" problem currently experienced by SeaBIOS users (there are no 11, 12, etc.
keys on a keyboard - so impossible to choose the last menu entries if you got
>10 entries because of multiple hard drives / secondary payloads / floppies)
- the boot menu has been extended to the letter keys. NOTE: TPM menu has been
moved from T to M letter: it is at the end of keyboard's 3rd row of letters and
"Trusted" is adjective while "Module" is a noun; alternatively could press '-'.
Also, add support for a numpad. Small USB numpad could be really convenient for
choosing the boot entries at coreboot boards used as (maybe headless) servers.
'/' char on numpad could be used to open the boot menu or to exit it. If there
are >10 boot menu entries - the numpad console interface will be enabled: press
one or two digit keys and then ENTER to confirm your choice, or remove a digit
by pressing the '.Del' key. Also you could call TPM with '-' key at any moment,
or boot with a single key press of your fullsize keyboard.
[PATCH v2] ramdisk: search for all available floppy images instead of one
All the floppy images available at CBFS will be found and listed in a boot menu,
instead of the first found. Could be highly valuable if you are participating in
a hobby OS development - would like to test multiple versions of your floppy at
the same coreboot image, to reduce the amount of re-flashes and accelerate the
development at bare metal - or simply you would like to access multiple floppies
as a coreboot user. For example: KolibriOS (nice assembly OS with GUI and apps),
FreeDOS, MichalOS, Snowdrop and memtest (coreboot's memtest version is buggy,
e.g. external USB keyboard isn't working at some laptops; floppy is much better)
Signed-off-by: Mike Banon <mikebdp2(a)gmail.com>
Change-Id: Idf4efba31091a8678b51c2f6541d440c5cc6d37d
---
M payloads/external/SeaBIOS/Makefile
A payloads/external/SeaBIOS/advanced_bootmenu.patch
A payloads/external/SeaBIOS/multiple_floppies.patch
3 files changed, 551 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/32351/1
diff --git a/payloads/external/SeaBIOS/Makefile b/payloads/external/SeaBIOS/Makefile
index e505c8c..ae58c8c 100644
--- a/payloads/external/SeaBIOS/Makefile
+++ b/payloads/external/SeaBIOS/Makefile
@@ -76,7 +76,18 @@
# echo "# CONFIG_SMBIOS is not set" >> seabios/.config
$(MAKE) -C seabios olddefconfig OUT=out/
-build: config
+patch:
+ if [ -d seabios ]; then \
+ cd seabios; \
+ if [ ! -f .patched ]; then \
+ echo " PATCH SeaBIOS $(TAG-y)"; \
+ patch -p1 < ./../advanced_bootmenu.patch; \
+ patch -p1 < ./../multiple_floppies.patch; \
+ touch .patched; \
+ fi; \
+ fi
+
+build: config patch
echo " MAKE SeaBIOS $(TAG-y)"
$(MAKE) -C seabios OUT=out/
diff --git a/payloads/external/SeaBIOS/advanced_bootmenu.patch b/payloads/external/SeaBIOS/advanced_bootmenu.patch
new file mode 100644
index 0000000..c914588
--- /dev/null
+++ b/payloads/external/SeaBIOS/advanced_bootmenu.patch
@@ -0,0 +1,332 @@
+diff --git a/src/boot.c b/src/boot.c
+index 9f82f3c..f94dd27 100644
+--- a/src/boot.c
++++ b/src/boot.c
+@@ -463,6 +463,7 @@ get_keystroke(int msec)
+ * Boot menu and BCV execution
+ ****************************************************************/
+
++#define BOOTMENU_PAGE_SIZE 18
+ #define DEFAULT_BOOTMENU_WAIT 2500
+
+ // Show IPL option menu.
+@@ -478,59 +479,282 @@ interactive_bootmenu(void)
+ ;
+
+ char *bootmsg = romfile_loadfile("etc/boot-menu-message", NULL);
+- int menukey = romfile_loadint("etc/boot-menu-key", 1);
+- printf("%s", bootmsg ?: "\nPress ESC for boot menu.\n\n");
++ int menukey = romfile_loadint("etc/boot-menu-key", 1); // custom menukey
++ printf("%s", bootmsg ?: "\nPress ESC or \\ / slash for boot menu.\n\n");
+ free(bootmsg);
+
+ u32 menutime = romfile_loadint("etc/boot-menu-wait", DEFAULT_BOOTMENU_WAIT);
+ enable_bootsplash();
+ int scan_code = get_keystroke(menutime);
+ disable_bootsplash();
+- if (scan_code != menukey)
++ if (scan_code != menukey && // custom menukey
++ scan_code != 1 && // ESC
++ scan_code != 43 && // '\' char on keyboard
++ scan_code != 53 && // '/' char on keyboard
++ scan_code != 98) { // '/' char on numpad
++ if (scan_code == -1)
++ printf("No key pressed.\n");
++ else
++ printf("Not a menukey pressed.\n");
+ return;
++ }
+
+ while (get_keystroke(0) >= 0)
+ ;
+
+- printf("Select boot device:\n\n");
+ wait_threads();
+
+- // Show menu items
++ char keyboard_keys[35] = {'1','2','3','4','5','6','7','8','9','0',
++ 'q','w','e','r','t','y','u','i','o','p',
++ 'a','s','d','f','g','h','j','k','l',
++ 'z','x','c','v','b','n'}; /* m = TPM */
++ int numpad_scancodes[10] = { 82, 79, 80, 81, 75, 76, 77, 71, 72, 73 };
++ int numpi = 0; // Key index: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9.
++ int digits = 0; // Numerical length of a current choice number.
++ int decode = 0; // Decode the current choice number into a letter?
++ int entry_id = 0;
++ char desc[77];
++
++ printf("Select boot device");
++
++ // Show menu items after counting them and determining a number of pages.
++ // Only 35 boot menu items (36 if to count a TPM) are supported currently.
++
+ int maxmenu = 0;
+ struct bootentry_s *pos;
+- hlist_for_each_entry(pos, &BootList, node) {
+- char desc[77];
++ hlist_for_each_entry(pos, &BootList, node)
+ maxmenu++;
+- printf("%d. %s\n", maxmenu
++
++ if (maxmenu > 10) {
++ if (maxmenu > 35)
++ maxmenu = 35;
++ if (maxmenu > BOOTMENU_PAGE_SIZE)
++ printf(" - page 1 :");
++ else
++ printf(": ");
++ printf(" // press ENTER after your numpad input");
++ if (maxmenu > BOOTMENU_PAGE_SIZE)
++ printf(" - if any -\n "
++ " // - or to switch between the pages...\n");
++ else
++ printf(" (if any)\n\n");
++ } else {
++ printf(":\n\n");
++ }
++
++ hlist_for_each_entry(pos, &BootList, node) {
++ if (entry_id == BOOTMENU_PAGE_SIZE) // Show only the first page.
++ break;
++ printf("%c. %s\n", keyboard_keys[entry_id]
+ , strtcpy(desc, pos->description, ARRAY_SIZE(desc)));
++ entry_id++;
+ }
++ int tpm_cshm = 0;
+ if (tpm_can_show_menu()) {
+- printf("\nt. TPM Configuration\n");
++ tpm_cshm = 1;
++ printf("\nm-. TPM Configuration");
+ }
+-
+- // Get key press. If the menu key is ESC, do not restart boot unless
+- // 1.5 seconds have passed. Otherwise users (trained by years of
+- // repeatedly hitting keys to enter the BIOS) will end up hitting ESC
+- // multiple times and immediately booting the primary boot device.
+- int esc_accepted_time = irqtimer_calc(menukey == 1 ? 1500 : 0);
++ printf("\n> ");
++
++ // Do not restart boot on menukey press, unless DEFAULT_BOOTMENU_WAIT msecs
++ // have passed. Otherwise users (trained by years of repeatedly hitting keys
++ // to enter the BIOS) will end up hitting menukey multiple times and
++ // immediately booting the primary boot device.
++ int esc_accepted_time = irqtimer_calc(DEFAULT_BOOTMENU_WAIT);
++ int choice = 0, kb_choice = 0;
++ int page_num = 1;
++ int enter = 0;
++ int backspace = 0;
++ int tpm_show_menu = 0;
+ for (;;) {
+ scan_code = get_keystroke(1000);
+- if (scan_code == 1 && !irqtimer_check(esc_accepted_time))
+- continue;
+- if (tpm_can_show_menu() && scan_code == 20 /* t */) {
++ if (scan_code == menukey || // custom menukey
++ scan_code == 1 || // ESC
++ scan_code == 43 || // '\' char on keyboard
++ scan_code == 53 || // '/' char on keyboard
++ scan_code == 98) { // '/' char on numpad
++ if (!irqtimer_check(esc_accepted_time))
++ continue;
++ if (digits == 2) // Remove the decoded "(*)"
++ printf(" \b\b\b");
++ /* Remove the existing input before printing a message. */
++ for (; digits > 0; digits--)
++ printf("\b \b");
++ printf("Menukey pressed.\n");
++ return;
++ }
++ kb_choice = 0;
++ /* 4 rows of keyboard_keys: 1 row with numbers, 3 rows with letters.
++ Use any of them to select a boot device (except the TPM 'm-' keys) */
++ // 1st range: 1-9 and 0 (10) keys <==> 2-11 scan codes <==> 1-10 choice
++ if (scan_code >= 2 && scan_code <= 11) kb_choice = scan_code - 1;
++ // 2nd range: Q-P row of letters <==> 16-25 scan codes <==> 11-20 choice
++ if (scan_code >= 16 && scan_code <= 25) kb_choice = scan_code - 5;
++ // 3rd range: A-L row of letters <==> 30-38 scan codes <==> 21-29 choice
++ if (scan_code >= 30 && scan_code <= 38) kb_choice = scan_code - 9;
++ // 4th range: Z-N row of letters <==> 44-49 scan codes <==> 30-35 choice
++ if (scan_code >= 44 && scan_code <= 49) kb_choice = scan_code - 14;
++ // ENTER: (28) on keyboard, (96) on numpad.
++ if (scan_code == 28 || scan_code == 96)
++ enter = 1;
++ // BCKSPC: '<-'(14) and 'Delete'(111) on keyboard, '.Del'(83) on numpad.
++ if (scan_code == 14 || scan_code == 111 || scan_code == 83)
++ backspace = 1;
++ // TPM keys: 'm'(50) and '-'(12) chars on keyboard, '-'(74) on numpad.
++ if ((scan_code == 50 || scan_code == 12 || scan_code == 74) && tpm_cshm)
++ tpm_show_menu = 1;
++
++ if (kb_choice != 0 || tpm_show_menu) {
++ if (kb_choice > maxmenu) {
++ if (!tpm_show_menu)
++ continue;
++ } else {
++ choice = kb_choice;
++ }
++ if (digits == 2) // Remove the decoded "(*)"
++ printf(" \b\b\b");
++ /* Remove the existing input before printing a choice. */
++ for (; digits > 0; digits--)
++ printf("\b \b");
++ if (!tpm_show_menu) {
++ // Choice is any of the detected boot devices ==> lets boot!
++ break;
++ }
++ } else {
++ // Internal/USB Numpad console interface.
++ if (digits < 9) {
++ for (numpi = 0; numpi < 10; numpi++) {
++ if (scan_code == numpad_scancodes[numpi]) {
++ if (maxmenu <= 10) { // Console interface is not needed.
++ if ((numpi != 0 && numpi <= maxmenu) ||
++ (numpi == 0 && 10 <= maxmenu)) { // 10(0)
++ choice = numpi;
++ enter = 1; // Fake ENTER to boot this entry now.
++ } else { // If no such an entry, don't try to boot.
++ break;
++ }
++ } else {
++ if (digits == 2) {
++ printf(" \b\b\b"); // Remove the decoded "(*)"
++ if (choice == 0) {
++ printf("\b\b \b\b"); // Remove "10".
++ digits = 0;
++ }
++ }
++ choice = 10 * choice + numpi;
++ }
++ if (choice > 0) {
++ printf("%d", numpi); // Print the entered digit.
++ digits++;
++ } else {
++ if (10 <= maxmenu)
++ printf("10(0)\b\b\b");
++ else
++ printf("10(?)\b\b\b");
++ digits = 2;
++ }
++ if (choice > 9 && digits == 2) // Decode into a letter.
++ decode = 1;
++ break;
++ }
++ }
++ }
++ if (backspace && digits > 0) {
++ backspace = 0;
++ choice = choice / 10;
++ if (digits == 2) {
++ printf(" \b\b\b"); // Remove the decoded "(*)"
++ // 0 turned into 10: one more Backspace is needed to remove.
++ if (choice == 0) {
++ printf("\b \b");
++ digits--;
++ }
++ }
++ printf("\b \b"); // Remove the last entered digit.
++ digits--;
++ if (choice > 9 && digits == 2) // Decode into a letter.
++ decode = 1;
++ }
++ if (decode) { // Decode the current choice number into a letter.
++ decode = 0;
++ if (choice <= maxmenu) {
++ printf("(%c)", keyboard_keys[choice-1]);
++ } else {
++ if (tpm_cshm && choice == 36)
++ printf("(m)"); // For TPM.
++ else
++ printf("(?)"); // No matching letter found.
++ }
++ printf("\b\b\b"); // Move a cursor before the "(*)"
++ }
++ }
++
++ if (enter) {
++ enter = 0;
++ if (choice == 0) {
++ if (digits == 2) { // for 0 that turned into 10
++ if (10 <= maxmenu)
++ break;
++ else
++ continue;
++ }
++ // If there are two pages - switch between them.
++ if (maxmenu > BOOTMENU_PAGE_SIZE) {
++ entry_id = 0;
++ page_num = 3 - page_num; // 3 - 1 = 2; 3 - 2 = 1.
++ printf("\n\nSelect boot device - page %d :"
++ " // press ENTER after your numpad input"
++ " - if any -\n "
++ " // - or to switch between the pages...\n",
++ page_num);
++ hlist_for_each_entry(pos, &BootList, node) {
++ if ((page_num == 1 && entry_id == BOOTMENU_PAGE_SIZE) ||
++ (page_num == 2 && entry_id == 35))
++ break;
++ if (page_num == 1 || entry_id >= BOOTMENU_PAGE_SIZE)
++ printf("%c. %s\n", keyboard_keys[entry_id],
++ strtcpy(desc, pos->description, ARRAY_SIZE(desc)));
++ entry_id++;
++ }
++ if (tpm_cshm)
++ printf("\nm-. TPM Configuration");
++ printf("\n> ");
++ }
++ } else {
++ if (choice > maxmenu) {
++ if (tpm_cshm && choice == 36)
++ tpm_show_menu = 1;
++ } else {
++ // Choice is any of the detected boot devices ==> lets boot!
++ break;
++ }
++ }
++ }
++
++ if (tpm_show_menu) {
++ tpm_show_menu = 0;
++ choice = 0;
++ if (digits == 0)
++ printf("TPM key pressed.");
++ else
++ digits = 0;
+ printf("\n");
+ tpm_menu();
++ printf("> ");
+ }
+- if (scan_code >= 1 && scan_code <= maxmenu+1)
+- break;
++ }
++
++ if (choice == 0) // 10(0)
++ choice = 10;
++
++ if (digits == 0 && choice < 36) {
++ printf("%c", keyboard_keys[choice-1]);
++ if (choice > 9) // Decode into a number.
++ printf("(%d)", choice);
+ }
+ printf("\n");
+- if (scan_code == 0x01)
+- // ESC
+- return;
+
+ // Find entry and make top priority.
+- int choice = scan_code - 1;
+ hlist_for_each_entry(pos, &BootList, node) {
+ if (! --choice)
+ break;
+diff --git a/src/config.h b/src/config.h
+index 93c8dbc..f85cc14 100644
+--- a/src/config.h
++++ b/src/config.h
+@@ -19,7 +19,7 @@
+ // Space to reserve in high-memory for tables
+ #define BUILD_MAX_HIGHTABLE (256*1024)
+ // Largest supported externaly facing drive id
+-#define BUILD_MAX_EXTDRIVE 16
++#define BUILD_MAX_EXTDRIVE 36
+ // Number of bytes the smbios may be and still live in the f-segment
+ #define BUILD_MAX_SMBIOS_FSEG 600
+ // Maximum number of bytes the mptable may be and still be copied to f-segment
diff --git a/payloads/external/SeaBIOS/multiple_floppies.patch b/payloads/external/SeaBIOS/multiple_floppies.patch
new file mode 100644
index 0000000..5249394
--- /dev/null
+++ b/payloads/external/SeaBIOS/multiple_floppies.patch
@@ -0,0 +1,207 @@
+diff --git a/src/block.h b/src/block.h
+index f64e880..aaa236f 100644
+--- a/src/block.h
++++ b/src/block.h
+@@ -2,7 +2,7 @@
+ #define __BLOCK_H
+
+ #include "types.h" // u32
+-
++#include "romfile.h" // struct romfile_s
+
+ /****************************************************************
+ * Disk command request
+@@ -48,6 +48,7 @@ struct drive_s {
+ struct drive_s {
+ u8 type; // Driver type (DTYPE_*)
+ u8 floppy_type; // Type of floppy (only for floppy drives).
++ struct romfile_s *floppy_file; // Floppy file (only for virtual floppies).
+ struct chs_s lchs; // Logical CHS
+ u64 sectors; // Total sectors count
+ u32 cntl_id; // Unique id for a given driver type.
+diff --git a/src/boot.c b/src/boot.c
+index 9f82f3c..79f1e7d 100644
+--- a/src/boot.c
++++ b/src/boot.c
+@@ -584,7 +584,7 @@ bcv_prepboot(void)
+ break;
+ case IPL_TYPE_FLOPPY:
+ map_floppy_drive(pos->drive);
+- add_bev(IPL_TYPE_FLOPPY, 0);
++ add_bev(IPL_TYPE_FLOPPY, (u32)pos->drive);
+ break;
+ case IPL_TYPE_HARDDISK:
+ map_hd_drive(pos->drive);
+@@ -733,6 +733,12 @@ do_boot(int seq_nr)
+ static void
+ do_boot(int seq_nr)
+ {
++
++ int ret;
++ void *pos;
++ struct romfile_s *file;
++ struct drive_s *drive;
++
+ if (! CONFIG_BOOT)
+ panic("Boot support not compiled in.\n");
+
+@@ -744,6 +750,16 @@ do_boot(int seq_nr)
+ switch (ie->type) {
+ case IPL_TYPE_FLOPPY:
+ printf("Booting from Floppy...\n");
++ drive = (struct drive_s *)ie->vector;
++ file = drive->floppy_file;
++ // File is NULL if a floppy is physical.
++ if (file) {
++ // Copy virtual floppy image into ram.
++ pos = (void *)drive->cntl_id;
++ ret = file->copy(file, pos, file->size);
++ if (ret < 0)
++ break;
++ }
+ boot_disk(0x00, CheckFloppySig);
+ break;
+ case IPL_TYPE_HARDDISK:
+diff --git a/src/hw/floppy.c b/src/hw/floppy.c
+index 9e6647d..5b37c6c 100644
+--- a/src/hw/floppy.c
++++ b/src/hw/floppy.c
+@@ -107,7 +107,7 @@ struct floppyinfo_s FloppyInfo[] VARFSEG = {
+ };
+
+ struct drive_s *
+-init_floppy(int floppyid, int ftype)
++init_floppy(int floppyid, int ftype, struct romfile_s *ffile)
+ {
+ if (ftype <= 0 || ftype >= ARRAY_SIZE(FloppyInfo)) {
+ dprintf(1, "Bad floppy type %d\n", ftype);
+@@ -124,6 +124,7 @@ init_floppy(int floppyid, int ftype)
+ drive->type = DTYPE_FLOPPY;
+ drive->blksize = DISK_SECTOR_SIZE;
+ drive->floppy_type = ftype;
++ drive->floppy_file = ffile;
+ drive->sectors = (u64)-1;
+
+ memcpy(&drive->lchs, &FloppyInfo[ftype].chs
+@@ -134,7 +135,7 @@ addFloppy(int floppyid, int ftype)
+ static void
+ addFloppy(int floppyid, int ftype)
+ {
+- struct drive_s *drive = init_floppy(floppyid, ftype);
++ struct drive_s *drive = init_floppy(floppyid, ftype, 0);
+ if (!drive)
+ return;
+ char *desc = znprintf(MAXDESCSIZE, "Floppy [drive %c]", 'A' + floppyid);
+diff --git a/src/hw/ramdisk.c b/src/hw/ramdisk.c
+index b9e9baa..a679385 100644
+--- a/src/hw/ramdisk.c
++++ b/src/hw/ramdisk.c
+@@ -23,40 +23,69 @@ ramdisk_setup(void)
+ if (!CONFIG_FLASH_FLOPPY)
+ return;
+
+- // Find image.
+- struct romfile_s *file = romfile_findprefix("floppyimg/", NULL);
+- if (!file)
+- return;
+- const char *filename = file->name;
+- u32 size = file->size;
+- dprintf(3, "Found floppy file %s of size %d\n", filename, size);
+- int ftype = find_floppy_type(size);
+- if (ftype < 0) {
+- dprintf(3, "No floppy type found for ramdisk size\n");
++ struct romfile_s *file = NULL;
++ char *filename, *desc;
++ u32 size, max_size = 0;
++ int ftype;
++ void *pos;
++ struct drive_s *drive;
++
++ // Find the max floppy size
++ for (;;) {
++ // Find the next image.
++ file = romfile_findprefix("floppyimg/", file);
++ if (!file)
++ break;
++ filename = file->name;
++ size = file->size;
++ dprintf(3, "Found floppy file %s of size %d\n", filename, size);
++ // Check if this size is valid.
++ ftype = find_floppy_type(size);
++ if (ftype < 0) {
++ dprintf(3, "No floppy type found for ramdisk size\n");
++ } else {
++ if (size > max_size)
++ max_size = size;
++ }
++ }
++ if (max_size == 0) {
++ dprintf(3, "No floppies found\n");
+ return;
+ }
+
+ // Allocate ram for image.
+- void *pos = memalign_tmphigh(PAGE_SIZE, size);
++ pos = memalign_tmphigh(PAGE_SIZE, max_size);
+ if (!pos) {
+ warn_noalloc();
+ return;
+ }
+- e820_add((u32)pos, size, E820_RESERVED);
++ e820_add((u32)pos, max_size, E820_RESERVED);
++ dprintf(3, "Allocate %u bytes for a floppy\n", max_size);
+
+- // Copy image into ram.
+- int ret = file->copy(file, pos, size);
+- if (ret < 0)
+- return;
+-
+- // Setup driver.
+- struct drive_s *drive = init_floppy((u32)pos, ftype);
+- if (!drive)
+- return;
+- drive->type = DTYPE_RAMDISK;
+- dprintf(1, "Mapping floppy %s to addr %p\n", filename, pos);
+- char *desc = znprintf(MAXDESCSIZE, "Ramdisk [%s]", &filename[10]);
+- boot_add_floppy(drive, desc, bootprio_find_named_rom(filename, 0));
++ // Setup the floppy drivers.
++ file = NULL;
++ for (;;) {
++ // Find the next image.
++ file = romfile_findprefix("floppyimg/", file);
++ if (!file)
++ return;
++ filename = file->name;
++ size = file->size;
++ dprintf(3, "Found floppy file %s of size %d\n", filename, size);
++ ftype = find_floppy_type(size);
++ if (ftype < 0) {
++ dprintf(3, "No floppy type found for ramdisk size\n");
++ } else {
++ // Setup driver.
++ drive = init_floppy((u32)pos, ftype, file);
++ if (!drive)
++ return;
++ drive->type = DTYPE_RAMDISK;
++ dprintf(1, "Mapping floppy %s to addr %p\n", filename, pos);
++ desc = znprintf(MAXDESCSIZE, "Ramdisk [%s]", &filename[10]);
++ boot_add_floppy(drive, desc, bootprio_find_named_rom(filename, 0));
++ }
++ }
+ }
+
+ static int
+diff --git a/src/util.h b/src/util.h
+index 9c06850..ce3a26d 100644
+--- a/src/util.h
++++ b/src/util.h
+@@ -147,7 +147,8 @@ void dma_setup(void);
+ // hw/floppy.c
+ extern struct floppy_ext_dbt_s diskette_param_table2;
+ void floppy_setup(void);
+-struct drive_s *init_floppy(int floppyid, int ftype);
++extern struct romfile_s *ffile;
++struct drive_s *init_floppy(int floppyid, int ftype, struct romfile_s *ffile);
+ int find_floppy_type(u32 size);
+ int floppy_process_op(struct disk_op_s *op);
+ void floppy_tick(void);
--
To view, visit https://review.coreboot.org/c/coreboot/+/32351
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Idf4efba31091a8678b51c2f6541d440c5cc6d37d
Gerrit-Change-Number: 32351
Gerrit-PatchSet: 1
Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com>
Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com>
Gerrit-MessageType: newchange
1 month, 2 weeks
- 5
- 23
Change in ...coreboot[master]: configs: add Lenovo G505S sample configuration (use with dGPU patches)
by mikeb mikeb (Code Review)
Hello Mike Banon,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/32352
to review the following change.
Change subject: configs: add Lenovo G505S sample configuration (use with dGPU patches)
......................................................................
configs: add Lenovo G505S sample configuration (use with dGPU patches)
This sample .config could not be merged before the dGPU patches at CB:31929
(see https://review.coreboot.org/c/coreboot/+/31929 for more information).
I'm sharing it with you here partially for the archival purposes.
After you have installed the dGPU patches above, you can use this .config
as the base configuration for your G505S by saving it to ./coreboot/.config -
however, you may want to change some of its' configs! For example: it specifies
CONFIG_VGA_BIOS_DGPU_FILE="pci1002,6665.rom"
CONFIG_VGA_BIOS_DGPU_ID="1002,6665"
which is compatible with R5-M230 discrete GPU, but if your G505S has HD-8570M
discrete GPU instead - you will need to change these configs to ",6663" etc.
Or, if your G505S does not have a discrete GPU at all, please disable
CONFIG_MULTIPLE_VGA_ADAPTERS=y
and those DGPU configs will be disabled. Also, if you are using a SSD - you
may want to change the "CONFIG_HUDSON_SATA_MODE" from "0: NATIVE" to "2: AHCI".
In addition, I've disabled this WiFi adapter at my .config to save some space:
If you have any questions/suggestions regarding this .config, please contact me.
Signed-off-by: Mike Banon <mikebdp2(a)gmail.com>
Change-Id: I85f17395afca52ef690f24fcef746d74bb72aab7
---
A configs/config.lenovo_g505s_use_with_dgpu_patches
1 file changed, 746 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/32352/1
diff --git a/configs/config.lenovo_g505s_use_with_dgpu_patches b/configs/config.lenovo_g505s_use_with_dgpu_patches
new file mode 100644
index 0000000..5ff218f
--- /dev/null
+++ b/configs/config.lenovo_g505s_use_with_dgpu_patches
@@ -0,0 +1,746 @@
+#
+# ./coreboot/.config for Lenovo G505S - 17 April 2019
+#
+###
+#
+# Automatically generated file; DO NOT EDIT.
+# coreboot configuration
+#
+
+#
+# General setup
+#
+CONFIG_COREBOOT_BUILD=y
+CONFIG_LOCALVERSION=""
+CONFIG_CBFS_PREFIX="fallback"
+CONFIG_COMPILER_GCC=y
+# CONFIG_COMPILER_LLVM_CLANG is not set
+# CONFIG_ANY_TOOLCHAIN is not set
+# CONFIG_CCACHE is not set
+# CONFIG_FMD_GENPARSER is not set
+# CONFIG_UTIL_GENPARSER is not set
+# CONFIG_USE_OPTION_TABLE is not set
+CONFIG_COMPRESS_RAMSTAGE=y
+CONFIG_INCLUDE_CONFIG_FILE=y
+CONFIG_COLLECT_TIMESTAMPS=y
+# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
+# CONFIG_USE_BLOBS is not set
+# CONFIG_COVERAGE is not set
+# CONFIG_UBSAN is not set
+# CONFIG_NO_RELOCATABLE_RAMSTAGE is not set
+CONFIG_RELOCATABLE_RAMSTAGE=y
+# CONFIG_UPDATE_IMAGE is not set
+# CONFIG_BOOTSPLASH_IMAGE is not set
+
+#
+# Mainboard
+#
+
+#
+# Important: Run 'make distclean' before switching boards
+#
+# CONFIG_VENDOR_ADI is not set
+# CONFIG_VENDOR_ADLINK is not set
+# CONFIG_VENDOR_ADVANSUS is not set
+# CONFIG_VENDOR_AMD is not set
+# CONFIG_VENDOR_AOPEN is not set
+# CONFIG_VENDOR_APPLE is not set
+# CONFIG_VENDOR_ASROCK is not set
+# CONFIG_VENDOR_ASUS is not set
+# CONFIG_VENDOR_AVALUE is not set
+# CONFIG_VENDOR_BAP is not set
+# CONFIG_VENDOR_BIOSTAR is not set
+# CONFIG_VENDOR_CAVIUM is not set
+# CONFIG_VENDOR_COMPULAB is not set
+# CONFIG_VENDOR_CUBIETECH is not set
+# CONFIG_VENDOR_ELMEX is not set
+# CONFIG_VENDOR_EMULATION is not set
+# CONFIG_VENDOR_ESD is not set
+# CONFIG_VENDOR_FACEBOOK is not set
+# CONFIG_VENDOR_FOXCONN is not set
+# CONFIG_VENDOR_GETAC is not set
+# CONFIG_VENDOR_GIGABYTE is not set
+# CONFIG_VENDOR_GIZMOSPHERE is not set
+# CONFIG_VENDOR_GOOGLE is not set
+# CONFIG_VENDOR_HP is not set
+# CONFIG_VENDOR_IBASE is not set
+# CONFIG_VENDOR_IEI is not set
+# CONFIG_VENDOR_INTEL is not set
+# CONFIG_VENDOR_JETWAY is not set
+# CONFIG_VENDOR_KONTRON is not set
+CONFIG_VENDOR_LENOVO=y
+# CONFIG_VENDOR_LIPPERT is not set
+# CONFIG_VENDOR_MSI is not set
+# CONFIG_VENDOR_OCP is not set
+# CONFIG_VENDOR_OPENCELLULAR is not set
+# CONFIG_VENDOR_PACKARDBELL is not set
+# CONFIG_VENDOR_PCENGINES is not set
+# CONFIG_VENDOR_PURISM is not set
+# CONFIG_VENDOR_RODA is not set
+# CONFIG_VENDOR_SAMSUNG is not set
+# CONFIG_VENDOR_SAPPHIRE is not set
+# CONFIG_VENDOR_SCALEWAY is not set
+# CONFIG_VENDOR_SIEMENS is not set
+# CONFIG_VENDOR_SIFIVE is not set
+# CONFIG_VENDOR_SUPERMICRO is not set
+# CONFIG_VENDOR_TI is not set
+# CONFIG_VENDOR_TYAN is not set
+# CONFIG_VENDOR_VIA is not set
+CONFIG_BOARD_SPECIFIC_OPTIONS=y
+CONFIG_MAINBOARD_DIR="lenovo/g505s"
+CONFIG_MAINBOARD_PART_NUMBER="LENOVO G505S"
+CONFIG_MAX_CPUS=4
+CONFIG_CBFS_SIZE=0x400000
+CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/config_seabios"
+CONFIG_MAINBOARD_VENDOR="LENOVO"
+CONFIG_HW_MEM_HOLE_SIZEK=0x200000
+CONFIG_VGA_BIOS_ID="1002,990b"
+CONFIG_ONBOARD_VGA_IS_PRIMARY=y
+# CONFIG_HUDSON_LEGACY_FREE is not set
+CONFIG_DIMM_SPD_SIZE=256
+CONFIG_VGA_BIOS=y
+CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
+CONFIG_VGA_BIOS_FILE="pci1002,990b.rom"
+CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000
+CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="LENOVO"
+CONFIG_DEVICETREE="devicetree.cb"
+CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
+# CONFIG_HUDSON_XHCI_FWM is not set
+CONFIG_POST_IO=y
+CONFIG_DCACHE_RAM_BASE=0x30000
+CONFIG_DCACHE_RAM_SIZE=0x10000
+CONFIG_MAX_REBOOT_CNT=3
+CONFIG_OVERRIDE_DEVICETREE=""
+CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
+CONFIG_FMDFILE=""
+CONFIG_MMCONF_BASE_ADDRESS=0xF8000000
+CONFIG_POST_DEVICE=y
+# CONFIG_DRIVERS_UART_8250IO is not set
+# CONFIG_VBOOT is not set
+CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="LENOVO G505S"
+CONFIG_BOARD_LENOVO_G505S=y
+# CONFIG_BOARD_LENOVO_L520 is not set
+# CONFIG_BOARD_LENOVO_S230U is not set
+# CONFIG_BOARD_LENOVO_T400 is not set
+# CONFIG_BOARD_LENOVO_T500 is not set
+# CONFIG_BOARD_LENOVO_R400 is not set
+# CONFIG_BOARD_LENOVO_W500 is not set
+# CONFIG_BOARD_LENOVO_T420 is not set
+# CONFIG_BOARD_LENOVO_T420S is not set
+# CONFIG_BOARD_LENOVO_THINKPAD_T430 is not set
+# CONFIG_BOARD_LENOVO_T430S is not set
+# CONFIG_BOARD_LENOVO_T431S is not set
+# CONFIG_BOARD_LENOVO_T520 is not set
+# CONFIG_BOARD_LENOVO_W520 is not set
+# CONFIG_BOARD_LENOVO_T530 is not set
+# CONFIG_BOARD_LENOVO_W530 is not set
+# CONFIG_BOARD_LENOVO_T60 is not set
+# CONFIG_BOARD_LENOVO_THINKCENTRE_A58 is not set
+# CONFIG_BOARD_LENOVO_X131E is not set
+# CONFIG_BOARD_LENOVO_X1_CARBON_GEN1 is not set
+# CONFIG_BOARD_LENOVO_X200 is not set
+# CONFIG_BOARD_LENOVO_X201 is not set
+# CONFIG_BOARD_LENOVO_X220 is not set
+# CONFIG_BOARD_LENOVO_X220I is not set
+# CONFIG_BOARD_LENOVO_X1 is not set
+# CONFIG_BOARD_LENOVO_X230 is not set
+# CONFIG_BOARD_LENOVO_X60 is not set
+# CONFIG_BOARD_LENOVO_Z61T is not set
+# CONFIG_BOARD_LENOVO_BASEBOARD_T520 is not set
+# CONFIG_BOARD_LENOVO_BASEBOARD_T530 is not set
+CONFIG_CPU_ADDR_BITS=48
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
+# CONFIG_USBDEBUG is not set
+CONFIG_MAINBOARD_VERSION="1.0"
+# CONFIG_DRIVERS_PS2_KEYBOARD is not set
+CONFIG_PCIEXP_L1_SUB_STATE=y
+CONFIG_SMBIOS_ENCLOSURE_TYPE=0x09
+CONFIG_HEAP_SIZE=0xc0000
+CONFIG_BOARD_ROMSIZE_KB_4096=y
+# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
+CONFIG_COREBOOT_ROMSIZE_KB_4096=y
+# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
+CONFIG_COREBOOT_ROMSIZE_KB=4096
+CONFIG_ROM_SIZE=0x400000
+CONFIG_SYSTEM_TYPE_LAPTOP=y
+# CONFIG_SYSTEM_TYPE_TABLET is not set
+# CONFIG_SYSTEM_TYPE_DETACHABLE is not set
+# CONFIG_SYSTEM_TYPE_CONVERTIBLE is not set
+# CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set
+
+#
+# Chipset
+#
+
+#
+# SoC
+#
+CONFIG_UDELAY_LAPIC_FIXED_FSB=200
+CONFIG_MMCONF_BUS_NUMBER=64
+CONFIG_S3_VGA_ROM_RUN=y
+CONFIG_EHCI_BAR=0xfef00000
+CONFIG_ACPI_CPU_STRING="\\_PR.CP%02d"
+# CONFIG_SOC_CAVIUM_CN81XX is not set
+CONFIG_ARCH_ARMV8_EXTENSION=0
+CONFIG_STACK_SIZE=0x1000
+# CONFIG_SOC_CAVIUM_COMMON is not set
+# CONFIG_SOC_INTEL_GLK is not set
+CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
+CONFIG_ROMSTAGE_ADDR=0x2000000
+CONFIG_VERSTAGE_ADDR=0x2000000
+CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
+CONFIG_PCIEXP_ASPM=y
+CONFIG_PCIEXP_COMMON_CLOCK=y
+CONFIG_PCIEXP_CLK_PM=y
+CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/amd/agesa/hudson/bootblock.c"
+# CONFIG_SOC_INTEL_COMMON_CANNONLAKE_BASE is not set
+# CONFIG_SOC_INTEL_COFFEELAKE is not set
+# CONFIG_SOC_INTEL_WHISKEYLAKE is not set
+# CONFIG_SOC_INTEL_COMETLAKE is not set
+# CONFIG_SOC_INTEL_CANNONLAKE_PCH_H is not set
+CONFIG_CONSOLE_CBMEM=y
+CONFIG_UART_PCI_ADDR=0x0
+# CONFIG_SOC_INTEL_KABYLAKE is not set
+# CONFIG_SOC_MEDIATEK_MT8173 is not set
+# CONFIG_SOC_MEDIATEK_MT8183 is not set
+# CONFIG_SOC_NVIDIA_TEGRA124 is not set
+# CONFIG_SOC_NVIDIA_TEGRA210 is not set
+# CONFIG_SOC_QC_IPQ40XX is not set
+# CONFIG_SOC_QC_IPQ806X is not set
+# CONFIG_SOC_QUALCOMM_QCS405 is not set
+# CONFIG_SOC_QUALCOMM_SDM845 is not set
+# CONFIG_SOC_ROCKCHIP_RK3288 is not set
+# CONFIG_SOC_ROCKCHIP_RK3399 is not set
+# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set
+# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set
+# CONFIG_SOC_UCB_RISCV is not set
+
+#
+# CPU
+#
+# CONFIG_CPU_ALLWINNER_A10 is not set
+CONFIG_XIP_ROM_SIZE=0x100000
+CONFIG_NUM_IPI_STARTS=2
+CONFIG_CPU_AMD_AGESA=y
+# CONFIG_ENABLE_MRC_CACHE is not set
+CONFIG_S3_DATA_POS=0xFFFF0000
+CONFIG_S3_DATA_SIZE=32768
+CONFIG_CPU_AMD_AGESA_FAMILY15_TN=y
+# CONFIG_CPU_AMD_PI is not set
+# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set
+# CONFIG_SSE2 is not set
+# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set
+# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set
+# CONFIG_CPU_TI_AM335X is not set
+# CONFIG_PARALLEL_CPU_INIT is not set
+# CONFIG_PARALLEL_MP is not set
+# CONFIG_UDELAY_IO is not set
+CONFIG_UDELAY_LAPIC=y
+CONFIG_LAPIC_MONOTONIC_TIMER=y
+# CONFIG_UDELAY_TSC is not set
+# CONFIG_UDELAY_TIMER2 is not set
+CONFIG_TSC_SYNC_LFENCE=y
+# CONFIG_TSC_SYNC_MFENCE is not set
+# CONFIG_NO_FIXED_XIP_ROM_SIZE is not set
+CONFIG_LOGICAL_CPUS=y
+# CONFIG_SMM_TSEG is not set
+# CONFIG_SMM_LAPIC_REMAP_MITIGATION is not set
+# CONFIG_SERIALIZED_SMM_INITIALIZATION is not set
+CONFIG_X86_AMD_FIXED_MTRRS=y
+# CONFIG_PLATFORM_USES_FSP1_0 is not set
+# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set
+# CONFIG_SOC_SETS_MSRS is not set
+CONFIG_CACHE_AS_RAM=y
+CONFIG_NO_CAR_GLOBAL_MIGRATION=y
+CONFIG_SMP=y
+# CONFIG_SUPPORT_CPU_UCODE_IN_CBFS is not set
+# CONFIG_USES_MICROCODE_HEADER_FILES is not set
+
+#
+# Northbridge
+#
+CONFIG_NORTHBRIDGE_AMD_AGESA=y
+# CONFIG_CONSOLE_VGA_MULTI is not set
+CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN=y
+# CONFIG_NORTHBRIDGE_AMD_PI is not set
+CONFIG_MAX_PIRQ_LINKS=4
+
+#
+# Southbridge
+#
+CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON=y
+CONFIG_SOUTHBRIDGE_SPECIFIC_OPTIONS=y
+# CONFIG_HUDSON_XHCI_ENABLE is not set
+# CONFIG_HUDSON_IMC_ENABLE is not set
+# CONFIG_HUDSON_GEC_FWM is not set
+CONFIG_HUDSON_SATA_MODE=0
+
+#
+# NATIVE
+#
+CONFIG_ACPI_ENABLE_THERMAL_ZONE=y
+# CONFIG_AMD_SB_CIMX is not set
+# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set
+# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set
+# CONFIG_SOUTHBRIDGE_INTEL_COMMON is not set
+# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set
+# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS is not set
+# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI is not set
+# CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN is not set
+# CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ is not set
+# CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN is not set
+# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM is not set
+# CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE is not set
+
+#
+# Super I/O
+#
+# CONFIG_SUPERIO_NUVOTON_NCT6776_COM_A is not set
+
+#
+# Embedded Controllers
+#
+CONFIG_EC_COMPAL_ENE932=y
+# CONFIG_EC_GOOGLE_WILCO is not set
+CONFIG_EC_BASE_ACPI_DATA=0x930
+CONFIG_EC_BASE_ACPI_COMMAND=0x934
+CONFIG_EC_BASE_HOST_DATA=0x940
+CONFIG_EC_BASE_HOST_COMMAND=0x944
+CONFIG_EC_BASE_PACKET=0x950
+CONFIG_SEABIOS_PS2_TIMEOUT=0
+
+#
+# AMD Platform Initialization
+#
+# CONFIG_CPU_AMD_AGESA_BINARY_PI is not set
+CONFIG_CPU_AMD_AGESA_OPENSOURCE=y
+# CONFIG_CAVIUM_BDK is not set
+# CONFIG_MAINBOARD_HAS_CHROMEOS is not set
+# CONFIG_GOOGLE_SMBIOS_MAINBOARD_VERSION is not set
+# CONFIG_UEFI_2_4_BINDING is not set
+# CONFIG_UDK_2015_BINDING is not set
+# CONFIG_UDK_2017_BINDING is not set
+CONFIG_UDK_2013_VERSION=2013
+CONFIG_UDK_2015_VERSION=2015
+CONFIG_UDK_2017_VERSION=2017
+CONFIG_UDK_VERSION=2013
+# CONFIG_USE_SIEMENS_HWILIB is not set
+# CONFIG_ARCH_ARM is not set
+# CONFIG_ARCH_BOOTBLOCK_ARM is not set
+# CONFIG_ARCH_VERSTAGE_ARM is not set
+# CONFIG_ARCH_ROMSTAGE_ARM is not set
+# CONFIG_ARCH_RAMSTAGE_ARM is not set
+# CONFIG_ARCH_BOOTBLOCK_ARMV4 is not set
+# CONFIG_ARCH_VERSTAGE_ARMV4 is not set
+# CONFIG_ARCH_ROMSTAGE_ARMV4 is not set
+# CONFIG_ARCH_RAMSTAGE_ARMV4 is not set
+# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set
+# CONFIG_ARCH_VERSTAGE_ARMV7 is not set
+# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set
+# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set
+# CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set
+# CONFIG_ARCH_VERSTAGE_ARMV7_M is not set
+# CONFIG_ARCH_BOOTBLOCK_ARMV7_R is not set
+# CONFIG_ARCH_VERSTAGE_ARMV7_R is not set
+# CONFIG_ARCH_ROMSTAGE_ARMV7_R is not set
+# CONFIG_ARCH_RAMSTAGE_ARMV7_R is not set
+# CONFIG_ARM_LPAE is not set
+# CONFIG_ARCH_ARM64 is not set
+# CONFIG_ARCH_BOOTBLOCK_ARM64 is not set
+# CONFIG_ARCH_VERSTAGE_ARM64 is not set
+# CONFIG_ARCH_ROMSTAGE_ARM64 is not set
+# CONFIG_ARCH_RAMSTAGE_ARM64 is not set
+# CONFIG_ARCH_BOOTBLOCK_ARMV8_64 is not set
+# CONFIG_ARCH_VERSTAGE_ARMV8_64 is not set
+# CONFIG_ARCH_ROMSTAGE_ARMV8_64 is not set
+# CONFIG_ARCH_RAMSTAGE_ARMV8_64 is not set
+# CONFIG_ARM64_USE_ARCH_TIMER is not set
+# CONFIG_ARM64_A53_ERRATUM_843419 is not set
+# CONFIG_ARCH_MIPS is not set
+# CONFIG_ARCH_BOOTBLOCK_MIPS is not set
+# CONFIG_ARCH_VERSTAGE_MIPS is not set
+# CONFIG_ARCH_ROMSTAGE_MIPS is not set
+# CONFIG_ARCH_RAMSTAGE_MIPS is not set
+# CONFIG_ARCH_PPC64 is not set
+# CONFIG_ARCH_BOOTBLOCK_PPC64 is not set
+# CONFIG_ARCH_VERSTAGE_PPC64 is not set
+# CONFIG_ARCH_ROMSTAGE_PPC64 is not set
+# CONFIG_ARCH_RAMSTAGE_PPC64 is not set
+# CONFIG_ARCH_RISCV is not set
+CONFIG_ARCH_RISCV_M=y
+# CONFIG_ARCH_RISCV_S is not set
+# CONFIG_ARCH_RISCV_U is not set
+# CONFIG_ARCH_RISCV_RV64 is not set
+# CONFIG_ARCH_RISCV_RV32 is not set
+# CONFIG_ARCH_RISCV_PMP is not set
+# CONFIG_ARCH_BOOTBLOCK_RISCV is not set
+# CONFIG_ARCH_VERSTAGE_RISCV is not set
+# CONFIG_ARCH_ROMSTAGE_RISCV is not set
+# CONFIG_ARCH_RAMSTAGE_RISCV is not set
+# CONFIG_RISCV_USE_ARCH_TIMER is not set
+CONFIG_ARCH_X86=y
+CONFIG_ARCH_BOOTBLOCK_X86_32=y
+CONFIG_ARCH_VERSTAGE_X86_32=y
+CONFIG_ARCH_ROMSTAGE_X86_32=y
+CONFIG_ARCH_POSTCAR_X86_32=y
+CONFIG_ARCH_RAMSTAGE_X86_32=y
+# CONFIG_ARCH_BOOTBLOCK_X86_64 is not set
+# CONFIG_ARCH_VERSTAGE_X86_64 is not set
+# CONFIG_ARCH_ROMSTAGE_X86_64 is not set
+# CONFIG_ARCH_POSTCAR_X86_64 is not set
+# CONFIG_ARCH_RAMSTAGE_X86_64 is not set
+# CONFIG_USE_MARCH_586 is not set
+# CONFIG_AP_IN_SIPI_WAIT is not set
+# CONFIG_SIPI_VECTOR_IN_ROM is not set
+CONFIG_RAMBASE=0xe00000
+CONFIG_RAMTOP=0x1000000
+CONFIG_CBMEM_TOP_BACKUP=y
+# CONFIG_EARLY_EBDA_INIT is not set
+CONFIG_PC80_SYSTEM=y
+# CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set
+# CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set
+# CONFIG_HAVE_CMOS_DEFAULT is not set
+CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y
+# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set
+# CONFIG_HPET_ADDRESS_OVERRIDE is not set
+CONFIG_HPET_ADDRESS=0xfed00000
+CONFIG_ID_SECTION_OFFSET=0x80
+CONFIG_POSTCAR_STAGE=y
+# CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set
+# CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set
+CONFIG_BOOTBLOCK_SIMPLE=y
+# CONFIG_BOOTBLOCK_NORMAL is not set
+CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c"
+# CONFIG_COLLECT_TIMESTAMPS_NO_TSC is not set
+CONFIG_COLLECT_TIMESTAMPS_TSC=y
+# CONFIG_PAGING_IN_CACHE_AS_RAM is not set
+# CONFIG_IDT_IN_EVERY_STAGE is not set
+CONFIG_HAVE_CF9_RESET=y
+CONFIG_HAVE_CF9_RESET_PREPARE=y
+
+#
+# Devices
+#
+CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
+CONFIG_HAVE_VBE_LINEAR_FRAMEBUFFER=y
+# CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT is not set
+# CONFIG_MAINBOARD_HAS_LIBGFXINIT is not set
+CONFIG_MAINBOARD_HAS_MULTIPLE_VGA_ADAPTERS=y
+CONFIG_VGA_ROM_RUN=y
+# CONFIG_NO_GFX_INIT is not set
+# CONFIG_ALWAYS_LOAD_OPROM is not set
+CONFIG_ON_DEVICE_ROM_LOAD=y
+# CONFIG_PCI_OPTION_ROM_RUN_REALMODE is not set
+CONFIG_PCI_OPTION_ROM_RUN_YABEL=y
+CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES=y
+# CONFIG_YABEL_PCI_FAKE_WRITING_OTHER_DEVICES_CONFIG is not set
+CONFIG_YABEL_VIRTMEM_LOCATION=0x1000000
+CONFIG_YABEL_DIRECTHW=y
+CONFIG_MULTIPLE_VGA_ADAPTERS=y
+
+#
+# Display
+#
+CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
+# CONFIG_FRAMEBUFFER_VESA_MODE_100 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_101 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_102 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_103 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_104 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_105 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_106 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_107 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_108 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_109 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_10A is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_10B is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_10C is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_10D is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_10E is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_10F is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_110 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_111 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_112 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_113 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_114 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_115 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_116 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_117 is not set
+CONFIG_FRAMEBUFFER_VESA_MODE_118=y
+# CONFIG_FRAMEBUFFER_VESA_MODE_119 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_11A is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_11B is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_USER is not set
+CONFIG_FRAMEBUFFER_VESA_MODE=0x118
+CONFIG_BOOTSPLASH=y
+# CONFIG_VGA_TEXT_FRAMEBUFFER is not set
+CONFIG_VBE_LINEAR_FRAMEBUFFER=y
+CONFIG_LINEAR_FRAMEBUFFER=y
+# CONFIG_SMBUS_HAS_AUX_CHANNELS is not set
+CONFIG_PCI=y
+# CONFIG_NO_MMCONF_SUPPORT is not set
+CONFIG_MMCONF_SUPPORT=y
+# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set
+CONFIG_PCIX_PLUGIN_SUPPORT=y
+CONFIG_CARDBUS_PLUGIN_SUPPORT=y
+# CONFIG_AZALIA_PLUGIN_SUPPORT is not set
+CONFIG_PCIEXP_PLUGIN_SUPPORT=y
+# CONFIG_EARLY_PCI_BRIDGE is not set
+CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
+CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
+CONFIG_VGA_BIOS_DGPU=y
+CONFIG_VGA_BIOS_DGPU_FILE="pci1002,6665.rom"
+CONFIG_VGA_BIOS_DGPU_ID="1002,6665"
+# CONFIG_SOFTWARE_I2C is not set
+
+#
+# Generic Drivers
+#
+# CONFIG_DRIVERS_AS3722_RTC is not set
+# CONFIG_GIC is not set
+# CONFIG_IPMI_KCS is not set
+# CONFIG_DRIVERS_LENOVO_WACOM is not set
+# CONFIG_RT8168_GET_MAC_FROM_VPD is not set
+# CONFIG_RT8168_SET_LED_MODE is not set
+# CONFIG_SMMSTORE_IN_CBFS is not set
+CONFIG_SPI_FLASH=y
+CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
+# CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY is not set
+# CONFIG_SPI_FLASH_NO_FAST_READ is not set
+CONFIG_SPI_FLASH_ADESTO=y
+CONFIG_SPI_FLASH_AMIC=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B is not set
+# CONFIG_SPI_FLASH_HAS_VOLATILE_GROUP is not set
+# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set
+CONFIG_NO_UART_ON_SUPERIO=y
+# CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set
+# CONFIG_UART_OVERRIDE_REFCLK is not set
+# CONFIG_DRIVERS_UART_8250MEM is not set
+# CONFIG_DRIVERS_UART_8250MEM_32 is not set
+# CONFIG_HAVE_UART_SPECIAL is not set
+# CONFIG_DRIVERS_UART_OXPCIE is not set
+# CONFIG_DRIVERS_UART_PL011 is not set
+# CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set
+CONFIG_HAVE_USBDEBUG=y
+CONFIG_HAVE_USBDEBUG_OPTIONS=y
+# CONFIG_VPD is not set
+CONFIG_DRIVERS_AMD_PI=y
+CONFIG_SMBIOS_PROVIDED_BY_MOBO=y
+# CONFIG_DRIVERS_I2C_MAX98373 is not set
+# CONFIG_DRIVERS_I2C_MAX98927 is not set
+# CONFIG_DRIVERS_I2C_PCA9538 is not set
+# CONFIG_DRIVERS_I2C_PCF8523 is not set
+# CONFIG_DRIVERS_I2C_RT5663 is not set
+# CONFIG_DRIVERS_I2C_RTD2132 is not set
+# CONFIG_DRIVERS_I2C_RX6110SA is not set
+# CONFIG_DRIVERS_I2C_SX9310 is not set
+# CONFIG_MAINBOARD_HAS_I2C_TPM_ATMEL is not set
+# CONFIG_MAINBOARD_HAS_I2C_TPM_CR50 is not set
+# CONFIG_MAINBOARD_HAS_I2C_TPM_GENERIC is not set
+# CONFIG_PLATFORM_USES_FSP2_0 is not set
+# CONFIG_PLATFORM_USES_FSP2_1 is not set
+# CONFIG_INTEL_DDI is not set
+# CONFIG_INTEL_EDID is not set
+# CONFIG_INTEL_INT15 is not set
+# CONFIG_INTEL_GMA_ACPI is not set
+# CONFIG_INTEL_GMA_SSC_ALTERNATE_REF is not set
+# CONFIG_INTEL_GMA_SWSMISCI is not set
+# CONFIG_DRIVER_INTEL_I210 is not set
+# CONFIG_DRIVERS_INTEL_MIPI_CAMERA is not set
+# CONFIG_DRIVERS_INTEL_WIFI is not set
+# CONFIG_USE_SAR is not set
+# CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS is not set
+# CONFIG_DRIVER_MAXIM_MAX77686 is not set
+# CONFIG_DRIVER_PARADE_PS8625 is not set
+# CONFIG_DRIVER_PARADE_PS8640 is not set
+CONFIG_DRIVERS_MC146818=y
+# CONFIG_LPC_TPM is not set
+# CONFIG_MAINBOARD_HAS_LPC_TPM is not set
+# CONFIG_DRIVERS_RICOH_RCE822 is not set
+# CONFIG_DRIVER_SIEMENS_NC_FPGA is not set
+# CONFIG_NC_FPGA_NOTIFY_CB_READY is not set
+# CONFIG_DRIVERS_SIL_3114 is not set
+# CONFIG_MAINBOARD_HAS_SPI_TPM_CR50 is not set
+# CONFIG_DRIVER_TI_TPS65090 is not set
+# CONFIG_DRIVERS_TI_TPS65913 is not set
+# CONFIG_DRIVERS_TI_TPS65913_RTC is not set
+# CONFIG_DRIVERS_USB_ACPI is not set
+# CONFIG_DRIVER_XPOWERS_AXP209 is not set
+# CONFIG_COMMONLIB_STORAGE is not set
+
+#
+# Security
+#
+
+#
+# Verified Boot (vboot)
+#
+
+#
+# Trusted Platform Module
+#
+CONFIG_USER_NO_TPM=y
+# CONFIG_ACPI_SATA_GENERATOR is not set
+# CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES is not set
+# CONFIG_ACPI_AMD_HARDWARE_SLEEP_VALUES is not set
+# CONFIG_BOOT_DEVICE_NOT_SPI_FLASH is not set
+CONFIG_BOOT_DEVICE_SPI_FLASH=y
+CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
+# CONFIG_BOOT_DEVICE_SUPPORTS_WRITES is not set
+# CONFIG_RTC is not set
+
+#
+# Console
+#
+# CONFIG_POSTCAR_CONSOLE is not set
+CONFIG_SQUELCH_EARLY_SMP=y
+# CONFIG_SPKMODEM is not set
+# CONFIG_CONSOLE_NE2K is not set
+CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
+# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
+# CONFIG_CONSOLE_SPI_FLASH is not set
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
+# CONFIG_NO_POST is not set
+# CONFIG_CMOS_POST is not set
+# CONFIG_CONSOLE_POST is not set
+CONFIG_POST_DEVICE_NONE=y
+# CONFIG_POST_DEVICE_LPC is not set
+# CONFIG_POST_DEVICE_PCI_PCIE is not set
+CONFIG_POST_IO_PORT=0x80
+# CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set
+CONFIG_HWBASE_DEBUG_CB=y
+CONFIG_HAVE_ACPI_RESUME=y
+# CONFIG_ACPI_HUGE_LOWMEM_BACKUP is not set
+CONFIG_RESUME_PATH_SAME_AS_BOOT=y
+# CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set
+# CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set
+# CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set
+CONFIG_HAVE_MONOTONIC_TIMER=y
+# CONFIG_GENERIC_UDELAY is not set
+# CONFIG_TIMER_QUEUE is not set
+CONFIG_HAVE_OPTION_TABLE=y
+# CONFIG_PIRQ_ROUTE is not set
+CONFIG_HAVE_SMI_HANDLER=y
+# CONFIG_PCI_IO_CFG_EXT is not set
+CONFIG_IOAPIC=y
+# CONFIG_USE_WATCHDOG_ON_BOOT is not set
+CONFIG_GFXUMA=y
+CONFIG_HAVE_ACPI_TABLES=y
+CONFIG_HAVE_MP_TABLE=y
+# CONFIG_COMMON_FADT is not set
+# CONFIG_ACPI_NHLT is not set
+
+#
+# System tables
+#
+CONFIG_GENERATE_MP_TABLE=y
+# CONFIG_GENERATE_PIRQ_TABLE is not set
+CONFIG_GENERATE_SMBIOS_TABLES=y
+
+#
+# Payload
+#
+# CONFIG_PAYLOAD_NONE is not set
+# CONFIG_PAYLOAD_ELF is not set
+# CONFIG_PAYLOAD_BAYOU is not set
+# CONFIG_PAYLOAD_FILO is not set
+# CONFIG_PAYLOAD_GRUB2 is not set
+# CONFIG_PAYLOAD_LINUXBOOT is not set
+CONFIG_PAYLOAD_SEABIOS=y
+# CONFIG_PAYLOAD_UBOOT is not set
+# CONFIG_PAYLOAD_YABITS is not set
+# CONFIG_PAYLOAD_LINUX is not set
+# CONFIG_PAYLOAD_TIANOCORE is not set
+CONFIG_PAYLOAD_FILE="payloads/external/SeaBIOS/seabios/out/bios.bin.elf"
+# CONFIG_SEABIOS_STABLE is not set
+CONFIG_SEABIOS_MASTER=y
+# CONFIG_SEABIOS_REVISION is not set
+# CONFIG_SEABIOS_THREAD_OPTIONROMS is not set
+CONFIG_SEABIOS_BOOTORDER_FILE=""
+# CONFIG_SEABIOS_ADD_SERCON_PORT_FILE is not set
+CONFIG_SEABIOS_DEBUG_LEVEL=-1
+
+#
+# Using default SeaBIOS log level
+#
+CONFIG_PAYLOAD_OPTIONS=""
+# CONFIG_PXE is not set
+CONFIG_COMPRESSED_PAYLOAD_LZMA=y
+# CONFIG_COMPRESSED_PAYLOAD_LZ4 is not set
+# CONFIG_PAYLOAD_IS_FLAT_BINARY is not set
+CONFIG_COMPRESS_SECONDARY_PAYLOAD=y
+
+#
+# Secondary Payloads
+#
+CONFIG_COREINFO_SECONDARY_PAYLOAD=y
+# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set
+# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set
+CONFIG_TINT_SECONDARY_PAYLOAD=y
+
+#
+# Debugging
+#
+
+#
+# CPU Debug Settings
+#
+# CONFIG_DEBUG_SMM_RELOCATION is not set
+
+#
+# General Debug Settings
+#
+# CONFIG_FATAL_ASSERTS is not set
+# CONFIG_DEBUG_CBFS is not set
+# CONFIG_HAVE_DEBUG_RAM_SETUP is not set
+# CONFIG_HAVE_DEBUG_SMBUS is not set
+# CONFIG_DEBUG_SMI is not set
+# CONFIG_DEBUG_MALLOC is not set
+# CONFIG_DEBUG_ACPI is not set
+# CONFIG_DEBUG_CONSOLE_INIT is not set
+# CONFIG_X86EMU_DEBUG is not set
+# CONFIG_DEBUG_SPI_FLASH is not set
+# CONFIG_TRACE is not set
+# CONFIG_DEBUG_BOOT_STATE is not set
+# CONFIG_DEBUG_ADA_CODE is not set
+# CONFIG_HAVE_EM100_SUPPORT is not set
+CONFIG_NO_EDID_FILL_FB=y
+# CONFIG_ENABLE_APIC_EXT_ID is not set
+CONFIG_WARNINGS_ARE_ERRORS=y
+# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set
+# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set
+# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set
+# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set
+# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set
+# CONFIG_REG_SCRIPT is not set
+# CONFIG_NO_XIP_EARLY_STAGES is not set
+# CONFIG_EARLY_CBMEM_LIST is not set
+CONFIG_RELOCATABLE_MODULES=y
+CONFIG_BOOTBLOCK_CUSTOM=y
+
--
To view, visit https://review.coreboot.org/c/coreboot/+/32352
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I85f17395afca52ef690f24fcef746d74bb72aab7
Gerrit-Change-Number: 32352
Gerrit-PatchSet: 1
Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com>
Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com>
Gerrit-MessageType: newchange
1 month, 2 weeks
- 4
- 40
Change in ...coreboot[master]: soc/intel/denverton_ns: Rewrite pmutil using pmclib
by Patrick Georgi (Code Review)
Hello Julien Viard de Galbert,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/31072
to review the following change.
Change subject: soc/intel/denverton_ns: Rewrite pmutil using pmclib
......................................................................
soc/intel/denverton_ns: Rewrite pmutil using pmclib
Change-Id: I13ab94e7440886f77e3091b16e50e48b17151751
Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net>
---
M src/soc/intel/denverton_ns/include/soc/pm.h
M src/soc/intel/denverton_ns/pmutil.c
M src/soc/intel/denverton_ns/smihandler.c
M src/soc/intel/denverton_ns/smm.c
4 files changed, 33 insertions(+), 184 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/31072/1
diff --git a/src/soc/intel/denverton_ns/include/soc/pm.h b/src/soc/intel/denverton_ns/include/soc/pm.h
index 09ce158..0aab0e2 100644
--- a/src/soc/intel/denverton_ns/include/soc/pm.h
+++ b/src/soc/intel/denverton_ns/include/soc/pm.h
@@ -47,18 +47,6 @@
struct chipset_power_state *fill_power_state(void);
/* Power Management Utility Functions. */
-uint32_t clear_smi_status(void);
-uint16_t clear_pm1_status(void);
-uint32_t clear_tco_status(void);
-uint32_t clear_gpe_status(void);
void clear_pmc_status(void);
-void enable_smi(uint32_t mask);
-void disable_smi(uint32_t mask);
-void enable_pm1(uint16_t events);
-void enable_pm1_control(uint32_t mask);
-void disable_pm1_control(uint32_t mask);
-void enable_gpe(uint32_t mask);
-void disable_gpe(uint32_t mask);
-void disable_all_gpe(void);
#endif /* _DENVERTON_NS_PM_H_ */
diff --git a/src/soc/intel/denverton_ns/pmutil.c b/src/soc/intel/denverton_ns/pmutil.c
index ccf0d95..344f8b9 100644
--- a/src/soc/intel/denverton_ns/pmutil.c
+++ b/src/soc/intel/denverton_ns/pmutil.c
@@ -19,29 +19,12 @@
#include <arch/io.h>
#include <console/console.h>
+#include <intelblocks/pmclib.h>
#include <soc/iomap.h>
#include <soc/soc_util.h>
#include <soc/pm.h>
-static void print_num_status_bits(int num_bits, uint32_t status,
- const char *const bit_names[])
-{
- int i;
-
- if (!status)
- return;
-
- for (i = num_bits - 1; i >= 0; i--) {
- if (status & (1 << i)) {
- if (bit_names[i])
- printk(BIOS_DEBUG, "%s ", bit_names[i]);
- else
- printk(BIOS_DEBUG, "BIT%d ", i);
- }
- }
-}
-
-static uint32_t print_smi_status(uint32_t smi_sts)
+const char *const *soc_smi_sts_array(size_t *a)
{
static const char *const smi_sts_bits[] = {
[2] = "BIOS",
@@ -67,93 +50,11 @@
[31] = "LEGACY_USB3",
};
- if (!smi_sts)
- return 0;
-
- printk(BIOS_DEBUG, "SMI_STS: ");
- print_num_status_bits(ARRAY_SIZE(smi_sts_bits), smi_sts, smi_sts_bits);
- printk(BIOS_DEBUG, "\n");
-
- return smi_sts;
+ *a = ARRAY_SIZE(smi_sts_bits);
+ return smi_sts_bits;
}
-static uint32_t reset_smi_status(void)
-{
- uint16_t pmbase = get_pmbase();
- uint32_t smi_sts = inl((uint16_t)(pmbase + SMI_STS));
- outl(smi_sts, (uint16_t)(pmbase + SMI_STS));
- return smi_sts;
-}
-
-uint32_t clear_smi_status(void) { return print_smi_status(reset_smi_status()); }
-
-void enable_smi(uint32_t mask)
-{
- uint16_t pmbase = get_pmbase();
- uint32_t smi_en = inl((uint16_t)(pmbase + SMI_EN));
- smi_en |= mask;
- outl(smi_en, (uint16_t)(pmbase + SMI_EN));
-}
-
-void disable_smi(uint32_t mask)
-{
- uint16_t pmbase = get_pmbase();
- uint32_t smi_en = inl((uint16_t)(pmbase + SMI_EN));
- smi_en &= ~mask;
- outl(smi_en, (uint16_t)(pmbase + SMI_EN));
-}
-
-void enable_pm1_control(uint32_t mask)
-{
- uint16_t pmbase = get_pmbase();
- uint32_t pm1_cnt = inl((uint16_t)(pmbase + PM1_CNT));
- pm1_cnt |= mask;
- outl(pm1_cnt, (uint16_t)(pmbase + PM1_CNT));
-}
-
-void disable_pm1_control(uint32_t mask)
-{
- uint16_t pmbase = get_pmbase();
- uint32_t pm1_cnt = inl((uint16_t)(pmbase + PM1_CNT));
- pm1_cnt &= ~mask;
- outl(pm1_cnt, (uint16_t)(pmbase + PM1_CNT));
-}
-
-static uint16_t reset_pm1_status(void)
-{
- uint16_t pmbase = get_pmbase();
- uint16_t pm1_sts = inw((uint16_t)(pmbase + PM1_STS));
- outw(pm1_sts, (uint16_t)(pmbase + PM1_STS));
- return pm1_sts;
-}
-
-static uint16_t print_pm1_status(uint16_t pm1_sts)
-{
- static const char *const pm1_sts_bits[] = {
- [0] = "TMROF", [4] = "BM", [5] = "GBL",
- [8] = "PWRBTN", [10] = "RTC", [11] = "PRBTNOR",
- [15] = "WAK",
- };
-
- if (!pm1_sts)
- return 0;
-
- printk(BIOS_SPEW, "PM1_STS: ");
- print_num_status_bits(ARRAY_SIZE(pm1_sts_bits), pm1_sts, pm1_sts_bits);
- printk(BIOS_SPEW, "\n");
-
- return pm1_sts;
-}
-
-uint16_t clear_pm1_status(void) { return print_pm1_status(reset_pm1_status()); }
-
-void enable_pm1(uint16_t events)
-{
- uint16_t pmbase = get_pmbase();
- outw(events, (uint16_t)(pmbase + PM1_EN));
-}
-
-static uint32_t print_tco_status(uint32_t tco_sts)
+const char *const *soc_tco_sts_array(size_t *a)
{
static const char *const tco_sts_bits[] = {
[0] = "NMI2SMI", [1] = "OS_TCO_SMI",
@@ -164,17 +65,11 @@
[17] = "SECOND_TO", [20] = "SMLINK_SLV_SMI",
};
- if (!tco_sts)
- return 0;
-
- printk(BIOS_DEBUG, "TCO_STS: ");
- print_num_status_bits(ARRAY_SIZE(tco_sts_bits), tco_sts, tco_sts_bits);
- printk(BIOS_DEBUG, "\n");
-
- return tco_sts;
+ *a = ARRAY_SIZE(tco_sts_bits);
+ return tco_sts_bits;
}
-static uint32_t reset_tco_status(void)
+uint32_t soc_reset_tco_status(void)
{
uint16_t tcobase = get_tcobase();
uint32_t tco_sts = inl((uint16_t)(tcobase + TCO1_STS));
@@ -184,35 +79,7 @@
return tco_sts & tco_en;
}
-uint32_t clear_tco_status(void) { return print_tco_status(reset_tco_status()); }
-
-void enable_gpe(uint32_t mask)
-{
- uint16_t pmbase = get_pmbase();
- uint32_t gpe0_en = inl((uint16_t)(pmbase + GPE0_EN(GPE_STD)));
- gpe0_en |= mask;
- outl(gpe0_en, (uint16_t)(pmbase + GPE0_EN(GPE_STD)));
-}
-
-void disable_gpe(uint32_t mask)
-{
- uint16_t pmbase = get_pmbase();
- uint32_t gpe0_en = inl((uint16_t)(pmbase + GPE0_EN(GPE_STD)));
- gpe0_en &= ~mask;
- outl(gpe0_en, (uint16_t)(pmbase + GPE0_EN(GPE_STD)));
-}
-
-void disable_all_gpe(void) { disable_gpe(~0); }
-
-static uint32_t reset_gpe_status(void)
-{
- uint16_t pmbase = get_pmbase();
- uint32_t gpe_sts = inl((uint16_t)(pmbase + GPE0_STS(GPE_STD)));
- outl(gpe_sts, (uint16_t)(pmbase + GPE0_STS(GPE_STD)));
- return gpe_sts;
-}
-
-static uint32_t print_gpe_sts(uint32_t gpe_sts)
+const char *const *soc_std_gpe_sts_array(size_t *a)
{
static const char *const gpe_sts_bits[] = {
[0] = "GPIO_0", [1] = "GPIO_1",
@@ -233,16 +100,8 @@
[30] = "GPIO_30", [31] = "GPIO_31",
};
- if (!gpe_sts)
- return gpe_sts;
-
- printk(BIOS_DEBUG, "GPE0a_STS: ");
- print_num_status_bits(ARRAY_SIZE(gpe_sts_bits), gpe_sts, gpe_sts_bits);
- printk(BIOS_DEBUG, "\n");
-
- return gpe_sts;
+ *a = ARRAY_SIZE(gpe_sts_bits);
+ return gpe_sts_bits;
}
-uint32_t clear_gpe_status(void) { return print_gpe_sts(reset_gpe_status()); }
-
void clear_pmc_status(void) { /* TODO */ }
diff --git a/src/soc/intel/denverton_ns/smihandler.c b/src/soc/intel/denverton_ns/smihandler.c
index 85f99d7..e1e7bc4 100644
--- a/src/soc/intel/denverton_ns/smihandler.c
+++ b/src/soc/intel/denverton_ns/smihandler.c
@@ -25,6 +25,7 @@
#include <device/pci_def.h>
#include <elog.h>
#include <intelblocks/fast_spi.h>
+#include <intelblocks/pmclib.h>
#include <spi-generic.h>
#include <soc/iomap.h>
#include <soc/soc_util.h>
@@ -52,7 +53,7 @@
return 0;
}
-void southbridge_smi_set_eos(void) { enable_smi(EOS); }
+void southbridge_smi_set_eos(void) { pmc_enable_smi(EOS); }
global_nvs_t *smm_get_gnvs(void) { return gnvs; }
@@ -98,7 +99,7 @@
uint16_t pmbase = get_pmbase();
/* First, disable further SMIs */
- disable_smi(SLP_SMI_EN);
+ pmc_disable_smi(SLP_SMI_EN);
/* Figure out SLP_TYP */
reg32 = inl((uint16_t)(pmbase + PM1_CNT));
@@ -131,7 +132,7 @@
printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n");
/* Disable all GPE */
- disable_all_gpe();
+ pmc_disable_all_gpe();
/* also iterates over all bridges on bus 0 */
busmaster_disable_on_bus(0);
@@ -145,7 +146,7 @@
* event again. We need to set BIT13 (SLP_EN) though to make the
* sleep happen.
*/
- enable_pm1_control(SLP_EN);
+ pmc_enable_pm1_control(SLP_EN);
/* Make sure to stop executing code here for S3/S4/S5 */
if (slp_typ > 1)
@@ -158,7 +159,7 @@
reg32 = inl((uint16_t)(pmbase + PM1_CNT));
if (reg32 & SCI_EN) {
/* The OS is not an ACPI OS, so we set the state to S0 */
- disable_pm1_control(SLP_EN | SLP_TYP);
+ pmc_disable_pm1_control(SLP_EN | SLP_TYP);
}
}
@@ -237,11 +238,11 @@
printk(BIOS_DEBUG, "P-state control\n");
break;
case APM_CNT_ACPI_DISABLE:
- disable_pm1_control(SCI_EN);
+ pmc_disable_pm1_control(SCI_EN);
printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n");
break;
case APM_CNT_ACPI_ENABLE:
- enable_pm1_control(SCI_EN);
+ pmc_enable_pm1_control(SCI_EN);
printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n");
break;
case APM_CNT_FINALIZE:
@@ -268,23 +269,23 @@
static void southbridge_smi_pm1(void)
{
- uint16_t pm1_sts = clear_pm1_status();
+ uint16_t pm1_sts = pmc_clear_pm1_status();
/* While OSPM is not active, poweroff immediately
* on a power button event.
*/
if (pm1_sts & PWRBTN_STS) {
// power button pressed
- disable_pm1_control(-1UL);
- enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT));
+ pmc_disable_pm1_control(-1UL);
+ pmc_enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT));
}
}
-static void southbridge_smi_gpe0(void) { clear_gpe_status(); }
+static void southbridge_smi_gpe0(void) { pmc_clear_all_gpe_status(); }
static void southbridge_smi_tco(void)
{
- uint32_t tco_sts = clear_tco_status();
+ uint32_t tco_sts = pmc_clear_tco_status();
/* Any TCO event? */
if (!tco_sts)
@@ -354,7 +355,7 @@
/* We need to clear the SMI status registers, or we won't see what's
* happening in the following calls.
*/
- smi_sts = clear_smi_status();
+ smi_sts = pmc_clear_smi_status();
/* Call SMI sub handler for each of the status bits */
for (i = 0; i < ARRAY_SIZE(southbridge_smi); i++) {
diff --git a/src/soc/intel/denverton_ns/smm.c b/src/soc/intel/denverton_ns/smm.c
index 9d3fa75..65d2499 100644
--- a/src/soc/intel/denverton_ns/smm.c
+++ b/src/soc/intel/denverton_ns/smm.c
@@ -23,6 +23,7 @@
#include <cpu/x86/smm.h>
#include <string.h>
+#include <intelblocks/pmclib.h>
#include <soc/iomap.h>
#include <soc/soc_util.h>
#include <soc/pm.h>
@@ -48,10 +49,10 @@
}
/* Dump and clear status registers */
- clear_smi_status();
- clear_pm1_status();
- clear_tco_status();
- clear_gpe_status();
+ pmc_clear_smi_status();
+ pmc_clear_pm1_status();
+ pmc_clear_tco_status();
+ pmc_clear_all_gpe_status();
clear_pmc_status();
}
@@ -60,8 +61,8 @@
printk(BIOS_DEBUG, "Enabling SMIs.\n");
/* Configure events Disable pcie wake. */
- enable_pm1(PWRBTN_EN | GBL_EN | PCIEXPWAK_DIS);
- disable_gpe(PME_B0_EN);
+ pmc_enable_pm1(PWRBTN_EN | GBL_EN | PCIEXPWAK_DIS);
+ pmc_disable_std_gpe(PME_B0_EN);
/* Enable SMI generation:
* - on APMC writes (io 0xb2)
@@ -71,7 +72,7 @@
* - on TCO events
* - on microcontroller writes (io 0x62/0x66)
*/
- enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS);
+ pmc_enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS);
}
void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
--
To view, visit https://review.coreboot.org/c/coreboot/+/31072
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I13ab94e7440886f77e3091b16e50e48b17151751
Gerrit-Change-Number: 31072
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name>
Gerrit-MessageType: newchange
2 months
- 3
- 4
Change in ...coreboot[master]: HACK sdm845: Drag in all of the binary blobs
by T.Michael Turney (Code Review)
Hello T Michael Turney,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/32450
to review the following change.
Change subject: HACK sdm845: Drag in all of the binary blobs
......................................................................
HACK sdm845: Drag in all of the binary blobs
This patch is a hack until licensing issues are resolved.
There is a lot of ugliness in the Makefile.inc to allow
build-bot to accept this patch without having access
to the binary blobs required to run on Napali hardware.
Change-Id: Ia7bd9fdc7295364c63366a6efe9a5c92db9b5b1a
Signed-off-by: T Michael Turney <mturney(a)codeaurora.org>
---
M src/soc/qualcomm/sdm845/Makefile.inc
1 file changed, 104 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/32450/1
diff --git a/src/soc/qualcomm/sdm845/Makefile.inc b/src/soc/qualcomm/sdm845/Makefile.inc
index 34064a1..8c64a2f 100644
--- a/src/soc/qualcomm/sdm845/Makefile.inc
+++ b/src/soc/qualcomm/sdm845/Makefile.inc
@@ -73,13 +73,117 @@
CPPFLAGS_common += -Isrc/soc/qualcomm/sdm845/include
CPPFLAGS_common += -Isrc/soc/qualcomm/common/include
+SDM845_BLOB := $(top)/3rdparty/blobs/soc/qualcomm/sdm845
+
BL31_MAKEARGS += PLAT=sdm845
ifeq ($(CONFIG_QC_SDI_ENABLE),y)
BL31_MAKEARGS += DEBUG=1
endif
+################################################################################
+ifeq ($(CONFIG_QC_SDI_ENABLE),y)
+QCSDI_FILE := $(SDM845_BLOB)/QcSdi.elf
+qcsdi_file := $(shell ls $(QCSDI_FILE))
+ifneq (,$(findstring $(QCSDI_FILE),$(qcsdi_file)))
+ QCSDI_CBFS := $(CONFIG_CBFS_PREFIX)/qcsdi
+ $(QCSDI_CBFS)-file := $(QCSDI_FILE)
+ $(QCSDI_CBFS)-type := stage
+ $(QCSDI_CBFS)-compression := none
+ cbfs-files-y += $(QCSDI_CBFS)
+endif
+endif
+
+################################################################################
+QCLIB_FILE := $(SDM845_BLOB)/QcLib.elf
+qclib_file := $(shell ls $(QCLIB_FILE))
+ifneq (,$(findstring $(QCLIB_FILE),$(qclib_file)))
+ QCLIB_CBFS := $(CONFIG_CBFS_PREFIX)/qclib
+ $(QCLIB_CBFS)-file := $(QCLIB_FILE)
+ $(QCLIB_CBFS)-type := stage
+ $(QCLIB_CBFS)-compression := none
+ cbfs-files-y += $(QCLIB_CBFS)
+endif
+
+################################################################################
+PMIC_FILE := $(SDM845_BLOB)/Pmic.bin
+pmic_file := $(shell ls $(PMIC_FILE))
+ifneq (,$(findstring $(PMIC_FILE),$(pmic_file)))
+ PMIC_CBFS := $(CONFIG_CBFS_PREFIX)/pmiccfg
+ $(PMIC_CBFS)-file := $(PMIC_FILE)
+ $(PMIC_CBFS)-type := raw
+ $(PMIC_CBFS)-compression := none
+ cbfs-files-y += $(PMIC_CBFS)
+endif
+
+################################################################################
+DCB_FILE := $(SDM845_BLOB)/6000_0200_1_dcb.bin
+dcb_file := $(shell ls $(DCB_FILE))
+ifneq (,$(findstring $(DCB_FILE),$(dcb_file)))
+ DCB_CBFS := $(CONFIG_CBFS_PREFIX)/dcb
+ $(DCB_CBFS)-file := $(DCB_FILE)
+ $(DCB_CBFS)-type := raw
+ $(DCB_CBFS)-compression := none
+ cbfs-files-y += $(DCB_CBFS)
+endif
+
+################################################################################
+AOP_FILE := $(SDM845_BLOB)/aop.mbn
+aop_file := $(shell ls $(AOP_FILE))
+ifneq (,$(findstring $(AOP_FILE),$(aop_file)))
+ AOP_CBFS := $(CONFIG_CBFS_PREFIX)/aop
+ $(AOP_CBFS)-file := $(AOP_FILE)
+ $(AOP_CBFS)-type := payload
+ $(AOP_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
+ cbfs-files-y += $(AOP_CBFS)
+endif
+
+################################################################################
+UART_FW_FILE := $(SDM845_BLOB)/uart_fw.bin
+uart_fw_file := $(shell ls $(UART_FW_FILE))
+ifneq (,$(findstring $(UART_FW_FILE),$(uart_fw_file)))
+ UART_FW_CBFS := $(CONFIG_CBFS_PREFIX)/uart_fw
+ $(UART_FW_CBFS)-file := $(UART_FW_FILE)
+ $(UART_FW_CBFS)-type := raw
+ $(UART_FW_CBFS)-compression := none
+ cbfs-files-y += $(UART_FW_CBFS)
+endif
+
+################################################################################
+SPI_FW_FILE := $(SDM845_BLOB)/spi_fw.bin
+spi_fw_file := $(shell ls $(SPI_FW_FILE))
+ifneq (,$(findstring $(SPI_FW_FILE),$(spi_fw_file)))
+ SPI_FW_CBFS := $(CONFIG_CBFS_PREFIX)/spi_fw
+ $(SPI_FW_CBFS)-file := $(SPI_FW_FILE)
+ $(SPI_FW_CBFS)-type := raw
+ $(SPI_FW_CBFS)-compression := none
+ cbfs-files-y += $(SPI_FW_CBFS)
+endif
+
+################################################################################
+I2C_FW_FILE := $(SDM845_BLOB)/i2c_fw.bin
+i2c_fw_file := $(shell ls $(I2C_FW_FILE))
+ifneq (,$(findstring $(I2C_FW_FILE),$(i2c_fw_file)))
+ I2C_FW_CBFS := $(CONFIG_CBFS_PREFIX)/i2c_fw
+ $(I2C_FW_CBFS)-file := $(I2C_FW_FILE)
+ $(I2C_FW_CBFS)-type := raw
+ $(I2C_FW_CBFS)-compression := none
+ cbfs-files-y += $(I2C_FW_CBFS)
+endif
+
+################################################################################
+QC_SEC_FILE := $(SDM845_BLOB)/qc_sec.mbn
+qc_sec_file := $(shell ls $(QC_SEC_FILE))
+ifneq (,$(findstring $(QC_SEC_FILE),$(qc_sec_file)))
+$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.elf
+ @util/qualcomm/createxbl.py -f $(objcbfs)/bootblock.elf \
+ -x $(QC_SEC_FILE) -o $(objcbfs)/merged_bb_qcsec.mbn \
+ -a 64 -d 64 -c 64
+ @util/qualcomm/qgpt.py $(objcbfs)/merged_bb_qcsec.mbn \
+ $(objcbfs)/bootblock.bin
+else
$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
@printf "Generating: $(subst $(obj)/,,$(@))\n"
cp $(objcbfs)/bootblock.raw.bin $(objcbfs)/bootblock.bin
+endif
endif
--
To view, visit https://review.coreboot.org/c/coreboot/+/32450
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ia7bd9fdc7295364c63366a6efe9a5c92db9b5b1a
Gerrit-Change-Number: 32450
Gerrit-PatchSet: 1
Gerrit-Owner: T.Michael Turney <tturne(a)codeaurora.org>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: T Michael Turney <mturney(a)codeaurora.org>
Gerrit-Reviewer: T.Michael Turney <tturne(a)codeaurora.org>
Gerrit-MessageType: newchange
2 months, 1 week
- 2
- 1
Change in ...coreboot[master]: [RFC]lib/coreboot_tables: Introduce BOOT_MEDIA_PARAMS2
by Patrick Rudolph (Code Review)
Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33107
Change subject: [RFC]lib/coreboot_tables: Introduce BOOT_MEDIA_PARAMS2
......................................................................
[RFC]lib/coreboot_tables: Introduce BOOT_MEDIA_PARAMS2
BOOT_MEDIA_PARAMS2 exposes the boot media MMIO address if it's
memory mapped in addition to various regions inside the bootmedia.
That information can be used by payloads to:
* Support VBOOT on SeaBIOS, as it otherwise uses the RO CBFS only
* Support Intel Apollolake and platforms that don't map the end of
the BIOS region to the end of the address space
* Support fwupd and flashrom finding the FMAP in memory
Change-Id: Ia0b1ac927b8782cc99cd7f34d8bf5c4ef60b5570
Signed-off-by: Patrick Rudolph <siro(a)das-labor.org>
---
M src/commonlib/include/commonlib/coreboot_tables.h
M src/lib/coreboot_table.c
2 files changed, 118 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/33107/1
diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h
index 198ad27..a854e44 100644
--- a/src/commonlib/include/commonlib/coreboot_tables.h
+++ b/src/commonlib/include/commonlib/coreboot_tables.h
@@ -392,6 +392,81 @@
struct mac_address mac_addrs[0];
};
+/**
+ * coreboot boot media params2
+ *
+ * The coreboot 'boot media params2' contain information about the
+ * bootmedia layout, allowing a payload to read the boot media
+ * without the need to parse (platform specific) layout files.
+ *
+ * It extends 'boot media params' by MMIO addresses and a second CBFS
+ * pointer.
+ *
+ * If the boot media is memory mapped, as it's usually done on x86 platforms,
+ * the FMAP and CBFS can be easily accessed by any software without the need
+ * for platform specific drivers.
+ *
+ * If the boot media is not memory mapped, the `mmap_mmio_address` is set
+ * to ~0ULL. In that case the software must use platform specific drivers
+ * to access the boot media (like flashrom or Linux's MTD).
+ *
+ * The memory mapped area is `mmap_size` bytes in size, starting `mmap_offset`
+ * bytes from `mmap_mmio_address`.
+ * The memory mapped area might be smaller than `boot_media_size` bytes,
+ * which gives the total size in bytes as seen by an external programmer.
+ *
+ * Software utilizing the coreboot boot media params2 shall check if the
+ * region to be access falls completely within the memory mapped region,
+ * before trying to access them.
+ * In addition it should not assume that the whole boot media is memory mapped.
+ *
+ * Example on Intel Apollolake:
+ *
+ * physical memory boot media
+ * +-----------+
+ * | |
+ * | |
+ * +-----------+ MMAP MMIO address +-----------------+ --------
+ * | ~UNAVAIL~ | | | IFD | | | | |
+ * | | MMAP offset | | | | | |
+ * | | | | | | | | |
+ * +-----------+ --- <<< +-----------------+ | | | |
+ * | BIOS REG | | | BIOS | | | | |
+ * | | | | | | | | |
+ * | | | |+---------------+| --+-+-+-+CBFS offset
+ * | | | || CBFS Active || | | |
+ * | | MMAP size |+---------------+| --+-+-+FMAP offset
+ * | | | || FMAP || | |
+ * | | | |+---------------+| --+-+CBFS legacy offset
+ * | | | || COREBOOT(CBFS)|| |
+ * +-----------+ --- <<< |+---------------+| |
+ * | TXE SRAM | || BIOS UNUSABLE || |
+ * | | |+---------------+| |
+ * +-----------+ +-----------------+ |
+ * |DEVICE EXTENSION | |
+ * | | |
+ * +-----------------+ -+Boot media size
+ */
+
+#define LB_TAG_BOOT_MEDIA_PARAMS2 0x0036
+struct lb_boot_media_params2 {
+ uint32_t tag;
+ uint32_t size;
+ /* offsets are relative to start of boot media */
+ uint64_t fmap_offset;
+ uint64_t cbfs_offset;
+ uint64_t cbfs_legacy_offset;
+ uint64_t mmap_offset;
+ /* Size is in bytes */
+ uint64_t cbfs_size;
+ uint64_t fmap_size;
+ uint64_t boot_media_size;
+ uint64_t cbfs_legacy_size;
+ uint64_t mmap_size;
+ /* MMIO address of MMAPed boot media, ~0ULL if not MMAPed.*/
+ uint64_t mmap_mmio_address;
+};
+
#define LB_TAG_SERIALNO 0x002a
#define MAX_SERIALNO_LENGTH 32
diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c
index 6e44f5d..c5807fd 100644
--- a/src/lib/coreboot_table.c
+++ b/src/lib/coreboot_table.c
@@ -261,8 +261,10 @@
static void lb_boot_media_params(struct lb_header *header)
{
struct lb_boot_media_params *bmp;
+ struct lb_boot_media_params2 *bmp2;
struct cbfs_props props;
const struct region_device *boot_dev;
+ struct region ar;
struct region_device fmrd;
boot_device_init();
@@ -285,6 +287,47 @@
bmp->fmap_offset = ~(uint64_t)0;
if (find_fmap_directory(&fmrd) == 0)
bmp->fmap_offset = region_device_offset(&fmrd);
+
+ /* LB_TAG_BOOT_MEDIA_PARAMS2 exposes additional parameters:
+ * - MMAPed boot media address
+ * - legacy CBFS position (RO partition in case of VBOOT)
+ */
+ bmp2 = (struct lb_boot_media_params2 *)lb_new_record(header);
+ bmp2->tag = LB_TAG_BOOT_MEDIA_PARAMS2;
+ bmp2->size = sizeof(*bmp2);
+
+ bmp2->cbfs_offset = bmp->cbfs_offset;
+ bmp2->cbfs_size = bmp->cbfs_size;
+ bmp2->boot_media_size = bmp->boot_media_size;
+ bmp2->fmap_offset = bmp->fmap_offset;
+
+ if (find_fmap_directory(&fmrd) == 0)
+ bmp2->fmap_size = region_device_size(&fmrd);
+
+ if (fmap_locate_area("COREBOOT", &ar)) {
+ printk(BIOS_INFO, "Can't find 'COREBOOT' area in FMAP\n");
+ bmp2->cbfs_legacy_offset = ~(uint64_t)0;
+ bmp2->cbfs_legacy_size = 0;
+ } else {
+ bmp2->cbfs_legacy_offset = ar.offset;
+ bmp2->cbfs_legacy_size = ar.size;
+ }
+
+ if (CONFIG(COMMON_CBFS_SPI_WRAPPER)) {
+ /* rdev_mmap will return a pointer to _postram_cbfs_cache */
+ bmp2->mmap_offset = ~(uint64_t)0;
+ bmp2->mmap_size = 0;
+ bmp2->mmap_mmio_address = ~(uint64_t)0;
+ } else {
+ /* FIXME: Introduce API to set correct values here */
+ bmp2->mmap_offset = 0;
+ bmp2->mmap_size = bmp2->boot_media_size;
+ /* Get address to MMAP boot media */
+ uintptr_t off = (uintptr_t)rdev_mmap(boot_dev, 0,
+ bmp2->mmap_size);
+ bmp2->mmap_mmio_address = off;
+ rdev_munmap(boot_dev, (void *)off);
+ }
}
static void lb_ram_code(struct lb_header *header)
--
To view, visit https://review.coreboot.org/c/coreboot/+/33107
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ia0b1ac927b8782cc99cd7f34d8bf5c4ef60b5570
Gerrit-Change-Number: 33107
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-MessageType: newchange
3 months, 1 week
- 9
- 21
Change in ...coreboot[master]: payloads/iPXE: Enable support for verifying images
by Felix Singer (Code Review)
Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31087
Change subject: payloads/iPXE: Enable support for verifying images
......................................................................
payloads/iPXE: Enable support for verifying images
Change-Id: Ic3356062758dba80f74116ff3ab82b3b9e8375b1
Signed-off-by: Felix Singer <migy(a)darmstadt.ccc.de>
---
M payloads/external/iPXE/Makefile
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/31087/1
diff --git a/payloads/external/iPXE/Makefile b/payloads/external/iPXE/Makefile
index a8b1245..a5bf7be 100644
--- a/payloads/external/iPXE/Makefile
+++ b/payloads/external/iPXE/Makefile
@@ -54,6 +54,7 @@
sed 's|#define\s*COMCONSOLE.*|#define COMCONSOLE $(IPXE_UART)|' "$(project_dir)/src/config/serial.h" > "$(project_dir)/src/config/serial.h.tmp"
sed 's|#define\s*COMSPEED.*|#define COMSPEED $(CONFIG_TTYS0_BAUD)|' "$(project_dir)/src/config/serial.h.tmp" > "$(project_dir)/src/config/serial.h"
endif
+ sed -ie 's|.*IMAGE_TRUST_CMD|#define IMAGE_TRUST_CMD|g' "$(project_dir)/src/config/general.h"
build: config
echo " MAKE $(project_name) $(TAG-y)"
--
To view, visit https://review.coreboot.org/c/coreboot/+/31087
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ic3356062758dba80f74116ff3ab82b3b9e8375b1
Gerrit-Change-Number: 31087
Gerrit-PatchSet: 1
Gerrit-Owner: Felix Singer <migy(a)darmstadt.ccc.de>
Gerrit-MessageType: newchange
3 months, 1 week
- 1
- 2
Change in ...coreboot[master]: cpu/intel: Use macro instead of numbers
by HAOUAS Elyes (Code Review)
HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31196
Change subject: cpu/intel: Use macro instead of numbers
......................................................................
cpu/intel: Use macro instead of numbers
Change-Id: Ic18c219beaec3dad197916a1e235a027c1c74a89
Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr>
---
M src/cpu/intel/fsp_model_406dx/model_406dx_init.c
M src/cpu/intel/haswell/haswell_init.c
M src/cpu/intel/model_1067x/model_1067x_init.c
M src/cpu/intel/model_106cx/model_106cx_init.c
M src/cpu/intel/model_206ax/model_206ax_init.c
M src/cpu/intel/model_6ex/model_6ex_init.c
M src/cpu/intel/model_6fx/model_6fx_init.c
7 files changed, 10 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/31196/1
diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx_init.c b/src/cpu/intel/fsp_model_406dx/model_406dx_init.c
index 7994f0b..06b37a9 100644
--- a/src/cpu/intel/fsp_model_406dx/model_406dx_init.c
+++ b/src/cpu/intel/fsp_model_406dx/model_406dx_init.c
@@ -47,9 +47,9 @@
msr_t msr;
msr = rdmsr(IA32_MISC_ENABLE);
- msr.lo |= (1 << 0); /* Fast String enable */
+ msr.lo |= FAST_STRINGS_ENABLE_BIT;
msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */
- msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */
+ msr.lo |= SPEED_STEP_ENABLE_BIT;
wrmsr(IA32_MISC_ENABLE, msr);
/* Disable Thermal interrupts */
diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c
index aa77964..08abdf5 100644
--- a/src/cpu/intel/haswell/haswell_init.c
+++ b/src/cpu/intel/haswell/haswell_init.c
@@ -578,9 +578,9 @@
msr_t msr;
msr = rdmsr(IA32_MISC_ENABLE);
- msr.lo |= (1 << 0); /* Fast String enable */
+ msr.lo |= FAST_STRINGS_ENABLE_BIT;
msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */
- msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */
+ msr.lo |= SPEED_STEP_ENABLE_BIT;
wrmsr(IA32_MISC_ENABLE, msr);
/* Disable Thermal interrupts */
diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
index 6068be1..97ed39d 100644
--- a/src/cpu/intel/model_1067x/model_1067x_init.c
+++ b/src/cpu/intel/model_1067x/model_1067x_init.c
@@ -199,7 +199,7 @@
msr.lo |= (1 << 10); /* FERR# multiplexing */
if (eist)
- msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */
+ msr.lo |= SPEED_STEP_ENABLE_BIT;
/* Enable C2E */
if (((sub_cstates >> (2 * 4)) & 0xf) >= 2)
diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c
index e443026..1c0d081 100644
--- a/src/cpu/intel/model_106cx/model_106cx_init.c
+++ b/src/cpu/intel/model_106cx/model_106cx_init.c
@@ -65,7 +65,7 @@
msr.lo |= (1 << 10); /* FERR# multiplexing */
// TODO: Only if IA32_PLATFORM_ID[17] = 0 and IA32_PLATFORM_ID[50] = 1
- msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */
+ msr.lo |= SPEED_STEP_ENABLE_BIT;
// TODO Do we want Deep C4 and Dynamic L2 shrinking?
wrmsr(IA32_MISC_ENABLE, msr);
diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c
index 33ad1e7..c2e0364 100644
--- a/src/cpu/intel/model_206ax/model_206ax_init.c
+++ b/src/cpu/intel/model_206ax/model_206ax_init.c
@@ -338,9 +338,9 @@
msr_t msr;
msr = rdmsr(IA32_MISC_ENABLE);
- msr.lo |= (1 << 0); /* Fast String enable */
+ msr.lo |= FAST_STRINGS_ENABLE_BIT;
msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */
- msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */
+ msr.lo |= SPEED_STEP_ENABLE_BIT;
wrmsr(IA32_MISC_ENABLE, msr);
/* Disable Thermal interrupts */
diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c
index 19a22f1..fbc6964 100644
--- a/src/cpu/intel/model_6ex/model_6ex_init.c
+++ b/src/cpu/intel/model_6ex/model_6ex_init.c
@@ -67,7 +67,7 @@
msr.lo |= (1 << 10); /* FERR# multiplexing */
// TODO: Only if IA32_PLATFORM_ID[17] = 0 and IA32_PLATFORM_ID[50] = 1
- msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */
+ msr.lo |= SPEED_STEP_ENABLE_BIT;
/* Enable C2E */
msr.lo |= (1 << 26);
diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c
index 4e19896..adc0265 100644
--- a/src/cpu/intel/model_6fx/model_6fx_init.c
+++ b/src/cpu/intel/model_6fx/model_6fx_init.c
@@ -70,7 +70,7 @@
msr.lo |= (1 << 10); /* FERR# multiplexing */
// TODO: Only if IA32_PLATFORM_ID[17] = 0 and IA32_PLATFORM_ID[50] = 1
- msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */
+ msr.lo |= SPEED_STEP_ENABLE_BIT;
/* Enable C2E */
msr.lo |= (1 << 26);
--
To view, visit https://review.coreboot.org/c/coreboot/+/31196
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ic18c219beaec3dad197916a1e235a027c1c74a89
Gerrit-Change-Number: 31196
Gerrit-PatchSet: 1
Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr>
Gerrit-MessageType: newchange
3 months, 1 week
- 4
- 11