Change in ...coreboot[master]: autoport: Add support for Haswell-LynxPoint platform
by Iru Cai (vimacs) (Code Review)
Hello Iru Cai,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/30890
to review the following change.
Change subject: autoport: Add support for Haswell-LynxPoint platform
......................................................................
autoport: Add support for Haswell-LynxPoint platform
It can now generate a buildable source for Clevo W650SZ.
TODO:
- Support Lynx Point LP (GPIO registers differ from non-LP)
- Use PCH HD-Audio in azilia instead of the CPU/Northbridge HD-Audio
Change-Id: I4f6e8c97b5122101de2f36bba8ba9f8ddd5b813a
Signed-off-by: Iru Cai <mytbk920423(a)gmail.com>
---
M util/autoport/azalia.go
A util/autoport/haswell.go
A util/autoport/lynxpoint.go
M util/autoport/main.go
4 files changed, 625 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/30890/1
diff --git a/util/autoport/azalia.go b/util/autoport/azalia.go
index c525189..3090dd0 100644
--- a/util/autoport/azalia.go
+++ b/util/autoport/azalia.go
@@ -62,4 +62,9 @@
RegisterPCI(0x8086, 0x1c20, azalia{})
/* C216/ivybridge */
RegisterPCI(0x8086, 0x1e20, azalia{})
+ /* Haswell */
+ RegisterPCI(0x8086, 0x0c0c, azalia{})
+ /* Lynx Point */
+ RegisterPCI(0x8086, 0x8c20, azalia{})
+ RegisterPCI(0x8086, 0x9c20, azalia{})
}
diff --git a/util/autoport/haswell.go b/util/autoport/haswell.go
new file mode 100644
index 0000000..d3c9d9f
--- /dev/null
+++ b/util/autoport/haswell.go
@@ -0,0 +1,119 @@
+package main
+
+type haswellmc struct {
+ variant string
+}
+
+func (i haswellmc) Scan(ctx Context, addr PCIDevData) {
+ inteltool := ctx.InfoSource.GetInteltool()
+
+ /* FIXME:XX Move this somewhere else. */
+ MainboardIncludes = append(MainboardIncludes, "drivers/intel/gma/int15.h")
+ MainboardEnable += (` /* FIXME: fix those values*/
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+`)
+
+ DevTree = DevTreeNode{
+ Chip: "northbridge/intel/haswell",
+ MissingParent: "northbridge",
+ Comment: "FIXME: check gfx.ndid and gfx.did",
+ Registers: map[string]string{
+ "gpu_dp_b_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 2) & 7),
+ "gpu_dp_c_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 10) & 7),
+ "gpu_dp_d_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 18) & 7),
+ "gpu_panel_port_select": FormatInt32((inteltool.IGD[0xc7208] >> 30) & 3),
+ "gpu_panel_power_up_delay": FormatInt32((inteltool.IGD[0xc7208] >> 16) & 0x1fff),
+ "gpu_panel_power_backlight_on_delay": FormatInt32(inteltool.IGD[0xc7208] & 0x1fff),
+ "gpu_panel_power_down_delay": FormatInt32((inteltool.IGD[0xc720c] >> 16) & 0x1fff),
+ "gpu_panel_power_backlight_off_delay": FormatInt32(inteltool.IGD[0xc720c] & 0x1fff),
+ "gpu_panel_power_cycle_delay": FormatInt32(inteltool.IGD[0xc7210] & 0xff),
+ "gpu_cpu_backlight": FormatHex32(inteltool.IGD[0x48254]),
+ "gpu_pch_backlight": FormatHex32((inteltool.IGD[0xc8254] >> 16) * 0x10001),
+ "gpu_ddi_e_connected": FormatBool(((inteltool.IGD[0x64000] >> 4) & 1) == 0),
+ /* FIXME:XX hardcoded. */
+ "gfx.ndid": "3",
+ "gfx.did": "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }",
+ },
+ Children: []DevTreeNode{
+ {
+ Chip: "cpu_cluster",
+ Dev: 0,
+ Children: []DevTreeNode{
+ {
+ Chip: "cpu/intel/haswell",
+ Children: []DevTreeNode{
+ {
+ Chip: "lapic",
+ Dev: 0,
+ },
+ {
+ Chip: "lapic",
+ Dev: 0xacac,
+ Disabled: true,
+ },
+ },
+ Registers: map[string]string{
+ /* FIXME:XX hardcoded. */
+ "c1_acpower": "1",
+ "c2_acpower": "3",
+ "c3_acpower": "5",
+ "c1_battery": "1",
+ "c2_battery": "3",
+ "c3_battery": "5",
+ },
+ },
+ },
+ },
+
+ {
+ Chip: "domain",
+ Dev: 0,
+ PCIController: true,
+ ChildPCIBus: 0,
+ PCISlots: []PCISlot{
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x0, Func: 0}, writeEmpty: true, additionalComment: "Host bridge"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1, Func: 0}, writeEmpty: true, additionalComment: "PCIe Bridge for discrete graphics"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x2, Func: 0}, writeEmpty: true, additionalComment: "Internal graphics"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x3, Func: 0}, writeEmpty: true, additionalComment: "Mini-HD audio"},
+ },
+ },
+ },
+ }
+
+ PutPCIDev(addr, "Host bridge")
+
+ /* FIXME:XX some configs are unsupported. */
+
+ KconfigBool["CPU_INTEL_HASWELL"] = true
+ KconfigBool["NORTHBRIDGE_INTEL_HASWELL"] = true
+ KconfigBool["INTEL_INT15"] = true
+ KconfigBool["HAVE_ACPI_TABLES"] = true
+ KconfigBool["HAVE_ACPI_RESUME"] = true
+
+ KconfigInt["MAX_CPUS"] = 8
+
+ DSDTIncludes = append(DSDTIncludes, DSDTInclude{
+ File: "cpu/intel/common/acpi/cpu.asl",
+ })
+
+ DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{
+ File: "northbridge/intel/haswell/acpi/haswell.asl",
+ }, DSDTInclude{
+ File: "drivers/intel/gma/acpi/default_brightness_levels.asl",
+ })
+}
+
+func init() {
+ RegisterPCI(0x8086, 0x0c00, haswellmc{variant: "Desktop"})
+ RegisterPCI(0x8086, 0x0c04, haswellmc{variant: "Mobile"})
+ RegisterPCI(0x8086, 0x0a04, haswellmc{variant: "ULT"})
+ RegisterPCI(0x8086, 0x0c08, haswellmc{variant: "Server"})
+ for _, id := range []uint16{
+ 0x0402, 0x0412, 0x0422,
+ 0x0406, 0x0416, 0x0426,
+ 0x0d16, 0x0d26, 0x0d36,
+ 0x0a06, 0x0a16, 0x0a26,
+ } {
+ RegisterPCI(0x8086, id, GenericVGA{GenericPCI{Comment: "VGA controller"}})
+ }
+}
diff --git a/util/autoport/lynxpoint.go b/util/autoport/lynxpoint.go
new file mode 100644
index 0000000..df20c3f
--- /dev/null
+++ b/util/autoport/lynxpoint.go
@@ -0,0 +1,495 @@
+package main
+
+import (
+ "fmt"
+ "os"
+)
+
+type lynxpoint struct {
+ variant string
+ node *DevTreeNode
+}
+
+func (b lynxpoint) writeGPIOSet(ctx Context, sb *os.File,
+ val uint32, set uint, partno int, constraint uint32) {
+
+ max := uint(32)
+ if set == 3 {
+ max = 12
+ }
+
+ bits := [6][2]string{
+ {"GPIO_MODE_NATIVE", "GPIO_MODE_GPIO"},
+ {"GPIO_DIR_OUTPUT", "GPIO_DIR_INPUT"},
+ {"GPIO_LEVEL_LOW", "GPIO_LEVEL_HIGH"},
+ {"GPIO_RESET_PWROK", "GPIO_RESET_RSMRST"},
+ {"GPIO_NO_INVERT", "GPIO_INVERT"},
+ {"GPIO_NO_BLINK", "GPIO_BLINK"},
+ }
+
+ for i := uint(0); i < max; i++ {
+ if ((constraint>>i)&1 == 1) {
+ fmt.Fprintf(sb, " .gpio%d = %s,\n",
+ (set-1)*32+i,
+ bits[partno][(val>>i)&1])
+ }
+ }
+}
+
+func (b lynxpoint) GPIO(ctx Context, inteltool InteltoolData) {
+ var constraint uint32
+ gpio := Create(ctx, "gpio.c")
+ defer gpio.Close()
+
+ AddROMStageFile("gpio.c", "")
+
+ Add_gpl(gpio)
+ gpio.WriteString("#include <southbridge/intel/common/gpio.h>\n\n")
+
+ /* TODO: different in LP PCH */
+ addresses := [3][6]int{
+ {0x00, 0x04, 0x0c, 0x60, 0x2c, 0x18},
+ {0x30, 0x34, 0x38, 0x64, -1, -1},
+ {0x40, 0x44, 0x48, 0x68, -1, -1},
+ }
+
+ for set := 1; set <= 3; set++ {
+ for partno, part := range []string{"mode", "direction", "level", "reset", "invert", "blink"} {
+ addr := addresses[set-1][partno]
+ if addr < 0 {
+ continue
+ }
+ fmt.Fprintf(gpio, "static const struct pch_gpio_set%d pch_gpio_set%d_%s = {\n",
+ set, set, part)
+
+ constraint = 0xffffffff
+ switch part {
+ case "direction":
+ /* Ignored on native mode */
+ constraint = inteltool.GPIO[uint16(addresses[set-1][0])]
+ case "level":
+ /* Level doesn't matter for input */
+ constraint = inteltool.GPIO[uint16(addresses[set-1][0])]
+ constraint &^= inteltool.GPIO[uint16(addresses[set-1][1])]
+ case "reset":
+ /* Only show reset */
+ constraint = inteltool.GPIO[uint16(addresses[set-1][3])]
+ case "invert":
+ /* Only on input and only show inverted GPIO */
+ constraint = inteltool.GPIO[uint16(addresses[set-1][0])]
+ constraint &= inteltool.GPIO[uint16(addresses[set-1][1])]
+ constraint &= inteltool.GPIO[uint16(addresses[set-1][4])]
+ case "blink":
+ /* Only on output and only show blinking GPIO */
+ constraint = inteltool.GPIO[uint16(addresses[set-1][0])]
+ constraint &^= inteltool.GPIO[uint16(addresses[set-1][1])]
+ constraint &= inteltool.GPIO[uint16(addresses[set-1][5])]
+ }
+ b.writeGPIOSet(ctx, gpio, inteltool.GPIO[uint16(addr)], uint(set), partno, constraint)
+ gpio.WriteString("};\n\n")
+ }
+ }
+
+ gpio.WriteString(`const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
+`)
+}
+
+func (b lynxpoint) IsPCIeHotplug(ctx Context, port int) bool {
+ portDev, ok := PCIMap[PCIAddr{Bus: 0, Dev: 0x1c, Func: port}]
+ if !ok {
+ return false
+ }
+ return (portDev.ConfigDump[0xdb] & (1 << 6)) != 0
+}
+
+func (b lynxpoint) GetGPIOHeader() string {
+ return "southbridge/intel/lynxpoint/pch.h"
+}
+
+func (b lynxpoint) EnableGPE(in int) {
+ b.node.Registers[fmt.Sprintf("gpi%d_routing", in)] = "2"
+}
+
+func (b lynxpoint) EncodeGPE(in int) int {
+ return in + 0x10
+}
+
+func (b lynxpoint) DecodeGPE(in int) int {
+ return in - 0x10
+}
+
+func (b lynxpoint) NeedRouteGPIOManually() {
+ b.node.Comment += ", FIXME: set gpiX_routing for EC support"
+}
+
+func (b lynxpoint) Scan(ctx Context, addr PCIDevData) {
+
+ SouthBridge = &b
+
+ inteltool := ctx.InfoSource.GetInteltool()
+ b.GPIO(ctx, inteltool)
+
+ KconfigBool["SOUTHBRIDGE_INTEL_LYNXPOINT"] = true
+ if b.variant == "Lynx Point LP" {
+ KconfigBool["INTEL_LYNXPOINT_LP"] = true
+ }
+ KconfigBool["SERIRQ_CONTINUOUS_MODE"] = true
+ KconfigInt["USBDEBUG_HCD_INDEX"] = 2
+ KconfigComment["USBDEBUG_HCD_INDEX"] = "FIXME: check this"
+ dmi := ctx.InfoSource.GetDMI()
+ if dmi.Vendor == "LENOVO" {
+ KconfigInt["DRAM_RESET_GATE_GPIO"] = 10
+ } else {
+ KconfigInt["DRAM_RESET_GATE_GPIO"] = 60
+ }
+ KconfigComment["DRAM_RESET_GATE_GPIO"] = "FIXME: check this"
+
+ /* Not strictly speaking correct. These subsys/subvendor referer to PCI devices.
+ But most systems don't have any of those. But the config needs to be set
+ nevertheless. So set it to southbridge subsys/subvendor. */
+ KconfigHex["MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID"] = uint32(GetLE16(addr.ConfigDump[0x2c:0x2e]))
+ KconfigHex["MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID"] = uint32(GetLE16(addr.ConfigDump[0x2e:0x30]))
+
+ ich9GetFlashSize(ctx)
+
+ DSDTDefines = append(DSDTDefines,
+ DSDTDefine{
+ Key: "BRIGHTNESS_UP",
+ Value: "\\_SB.PCI0.GFX0.INCB",
+ },
+ DSDTDefine{
+ Key: "BRIGHTNESS_DOWN",
+ Value: "\\_SB.PCI0.GFX0.DECB",
+ },
+ DSDTDefine{
+ Key: "ACPI_VIDEO_DEVICE",
+ Value: "\\_SB.PCI0.GFX0",
+ })
+
+ /* SPI init */
+ MainboardIncludes = append(MainboardIncludes, "southbridge/intel/lynxpoint/pch.h")
+
+ cur := DevTreeNode{
+ Chip: "southbridge/intel/lynxpoint",
+ Comment: "Intel Series 8 Lynx Point PCH",
+
+ Registers: map[string]string{
+ "pirqa_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x60]),
+ "pirqb_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x61]),
+ "pirqc_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x62]),
+ "pirqd_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x63]),
+ "pirqe_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x68]),
+ "pirqf_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x69]),
+ "pirqg_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x6a]),
+ "pirqh_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x6b]),
+ "sata_ahci": "1",
+ "gen1_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x84:0x88]),
+ "gen2_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x88:0x8c]),
+ "gen3_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x8c:0x90]),
+ "gen4_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x90:0x94]),
+ "sata_port_map": fmt.Sprintf("0x%x", PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 2}].ConfigDump[0x92]&0x3f),
+ },
+ PCISlots: []PCISlot{
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x14, Func: 0}, writeEmpty: false, additionalComment: "USB 3.0 Controller"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 0}, writeEmpty: true, additionalComment: "Management Engine Interface 1"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 1}, writeEmpty: true, additionalComment: "Management Engine Interface 2"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 2}, writeEmpty: true, additionalComment: "Management Engine IDE-R"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 3}, writeEmpty: true, additionalComment: "Management Engine KT"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x19, Func: 0}, writeEmpty: true, additionalComment: "Intel Gigabit Ethernet"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1a, Func: 0}, writeEmpty: true, additionalComment: "USB2 EHCI #2"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1b, Func: 0}, writeEmpty: true, additionalComment: "High Definition Audio"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 0}, writeEmpty: true, additionalComment: "PCIe Port #1"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 1}, writeEmpty: true, additionalComment: "PCIe Port #2"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 2}, writeEmpty: true, additionalComment: "PCIe Port #3"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 3}, writeEmpty: true, additionalComment: "PCIe Port #4"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 4}, writeEmpty: true, additionalComment: "PCIe Port #5"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 5}, writeEmpty: true, additionalComment: "PCIe Port #6"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 6}, writeEmpty: true, additionalComment: "PCIe Port #7"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 7}, writeEmpty: true, additionalComment: "PCIe Port #8"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1d, Func: 0}, writeEmpty: true, additionalComment: "USB2 EHCI #1"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1e, Func: 0}, writeEmpty: true, additionalComment: "PCI bridge"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 0}, writeEmpty: true, additionalComment: "LPC bridge"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 2}, writeEmpty: true, additionalComment: "SATA Controller 1"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 3}, writeEmpty: true, additionalComment: "SMBus"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 5}, writeEmpty: true, additionalComment: "SATA Controller 2"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 6}, writeEmpty: true, additionalComment: "Thermal"},
+ },
+ }
+
+ b.node = &cur
+
+ PutPCIChip(addr, cur)
+ PutPCIDevParent(addr, "PCI-LPC bridge", "lpc")
+
+ DSDTIncludes = append(DSDTIncludes, DSDTInclude{
+ File: "southbridge/intel/lynxpoint/acpi/platform.asl",
+ })
+ DSDTIncludes = append(DSDTIncludes, DSDTInclude{
+ File: "southbridge/intel/lynxpoint/acpi/globalnvs.asl",
+ Comment: "global NVS and variables",
+ })
+ DSDTIncludes = append(DSDTIncludes, DSDTInclude{
+ File: "southbridge/intel/lynxpoint/acpi/sleepstates.asl",
+ })
+ DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{
+ File: "southbridge/intel/lynxpoint/acpi/pch.asl",
+ })
+
+ sb := Create(ctx, "romstage.c")
+ defer sb.Close()
+ Add_gpl(sb)
+ sb.WriteString(`#include <stdint.h>
+#include <cpu/intel/romstage.h>
+#include <cpu/intel/haswell/haswell.h>
+#include <northbridge/intel/haswell/haswell.h>
+#include <northbridge/intel/haswell/pei_data.h>
+#include <southbridge/intel/common/gpio.h>
+#include <southbridge/intel/lynxpoint/pch.h>
+
+static const struct rcba_config_instruction rcba_config[] = {
+`)
+ RestoreDIRRoute(sb, "D31IR", uint16(inteltool.RCBA[0x3140]))
+ RestoreDIRRoute(sb, "D29IR", uint16(inteltool.RCBA[0x3144]))
+ RestoreDIRRoute(sb, "D28IR", uint16(inteltool.RCBA[0x3146]))
+ RestoreDIRRoute(sb, "D27IR", uint16(inteltool.RCBA[0x3148]))
+ RestoreDIRRoute(sb, "D26IR", uint16(inteltool.RCBA[0x314c]))
+ RestoreDIRRoute(sb, "D25IR", uint16(inteltool.RCBA[0x3150]))
+ RestoreDIRRoute(sb, "D22IR", uint16(inteltool.RCBA[0x315c]))
+ RestoreDIRRoute(sb, "D20IR", uint16(inteltool.RCBA[0x3160]))
+
+ sb.WriteString(`
+ RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS),
+
+ RCBA_END_CONFIG,
+};`)
+
+ sb.WriteString(`
+
+void mainboard_config_superio(void)
+{
+}
+
+void mainboard_romstage_entry(unsigned long bist)
+{
+ struct pei_data pei_data = {
+ .pei_version = PEI_VERSION,
+ .mchbar = (uintptr_t)DEFAULT_MCHBAR,
+ .dmibar = (uintptr_t)DEFAULT_DMIBAR,
+ .epbar = DEFAULT_EPBAR,
+ .pciexbar = DEFAULT_PCIEXBAR,
+ .smbusbar = SMBUS_IO_BASE,
+ .wdbbar = 0x4000000,
+ .wdbsize = 0x1000,
+ .hpet_address = HPET_ADDR,
+ .rcba = (uintptr_t)DEFAULT_RCBA,
+ .pmbase = DEFAULT_PMBASE,
+ .gpiobase = DEFAULT_GPIOBASE,
+ .temp_mmio_base = 0xfed08000,
+ .system_type = 1, /* desktop/server, FIXME: check this */
+ .tseg_size = CONFIG_SMM_TSEG_SIZE,
+ .spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 }, /* FIXME: check this */
+ .ec_present = 0,
+ .dimm_channel0_disabled = 0, /* FIXME: leave channel 0 enabled */
+ .dimm_channel1_disabled = 0, /* FIXME: leave channel 1 enabled */
+ .max_ddr3_freq = 1600,
+ .usb2_ports = {
+ /* Length, Enable, OCn#, Location */
+`)
+
+ pdo1 := PCIMap[PCIAddr{Bus: 0, Dev: 0x1d, Func: 0}].ConfigDump[0x64]
+ ocmap1 := PCIMap[PCIAddr{Bus: 0, Dev: 0x1d, Func: 0}].ConfigDump[0x74:0x78]
+ pdo2 := PCIMap[PCIAddr{Bus: 0, Dev: 0x1a, Func: 0}].ConfigDump[0x64]
+ ocmap2 := PCIMap[PCIAddr{Bus: 0, Dev: 0x1a, Func: 0}].ConfigDump[0x74:0x78]
+
+ for port := uint(0); port < 14; port++ {
+ var port_oc int = -1
+ var port_pos string
+ var port_disable uint8
+
+ if port < 8 {
+ port_disable = (pdo1 >> port) & 1
+ for oc := 0; oc < 4; oc++ {
+ if ((ocmap1[oc] & (1 << port)) != 0) {
+ port_oc = oc
+ break
+ }
+ }
+ } else {
+ port_disable = (pdo2 >> (port - 8)) & 1
+ for oc := 0; oc < 4; oc++ {
+ if ((ocmap2[oc] & (1 << (port - 8))) != 0) {
+ port_oc = oc + 4
+ break
+ }
+ }
+ }
+ if port_disable == 1 {
+ port_pos = "USB_PORT_SKIP"
+ } else {
+ port_pos = "USB_PORT_BACK_PANEL"
+ }
+ if port_oc == -1 {
+ fmt.Fprintf(sb, " { 0x0040, %d, USB_OC_PIN_SKIP, %s },\n",
+ (port_disable ^ 1), port_pos)
+ } else {
+ fmt.Fprintf(sb, " { 0x0040, %d, %d, %s },\n",
+ (port_disable ^ 1), port_oc, port_pos)
+ }
+ }
+
+ sb.WriteString(` },
+ .usb3_ports = {
+`)
+
+ xpdo := PCIMap[PCIAddr{Bus: 0, Dev: 0x14, Func: 0}].ConfigDump[0xe8]
+ u3ocm := PCIMap[PCIAddr{Bus: 0, Dev: 0x14, Func: 0}].ConfigDump[0xc8:0xd0]
+
+ for port := uint(0); port < 6; port++ {
+ var port_oc int = -1
+ port_disable := (xpdo >> port) & 1
+ for oc := 0; oc < 8; oc++ {
+ if (u3ocm[oc] & (1 << port)) != 0 {
+ port_oc = oc
+ break
+ }
+ }
+ if port_oc == -1 {
+ fmt.Fprintf(sb, " { %d, USB_OC_PIN_SKIP },\n",
+ (port_disable ^ 1))
+ } else {
+ fmt.Fprintf(sb, " { %d, %d },\n",
+ (port_disable ^ 1), port_oc)
+ }
+ }
+
+ sb.WriteString(` },
+ };
+
+ struct romstage_params romstage_params = {
+ .pei_data = &pei_data,
+ .gpio_map = &mainboard_gpio_map,
+ .rcba_config = &rcba_config[0],
+ .bist = bist,
+ };
+
+ romstage_common(&romstage_params);
+}`)
+
+ gnvs := Create(ctx, "acpi_tables.c")
+ defer gnvs.Close()
+
+ Add_gpl(gnvs)
+ gnvs.WriteString(`#include <southbridge/intel/lynxpoint/nvs.h>
+
+/* FIXME: check this function. */
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+ /* Disable USB ports in S3 by default */
+ gnvs->s3u0 = 0;
+ gnvs->s3u1 = 0;
+
+ /* Disable USB ports in S5 by default */
+ gnvs->s5u0 = 0;
+ gnvs->s5u1 = 0;
+
+ // the lid is open by default.
+ gnvs->lids = 1;
+
+ gnvs->tcrt = 100;
+ gnvs->tpsv = 90;
+}
+`)
+
+}
+
+func init() {
+ for _, id := range []uint16 {
+ 0x8c41, 0x8c49, 0x8c4b, 0x8c4f,
+ } {
+ RegisterPCI(0x8086, uint16(id), lynxpoint{variant: "Lynx Point Mobile"})
+ }
+
+ for _, id := range []uint16 {
+ 0x8c42, 0x8c44, 0x8c46, 0x8c4a,
+ 0x8c4c, 0x8c4e, 0x8c50, 0x8c5c,
+ } {
+ RegisterPCI(0x8086, uint16(id), lynxpoint{variant: "Lynx Point Desktop"})
+ }
+
+ for _, id := range []uint16 {
+ 0x8c52, 0x8c54, 0x8c56,
+ } {
+ RegisterPCI(0x8086, uint16(id), lynxpoint{variant: "Lynx Point Server"})
+ }
+
+ for _, id := range []uint16 {
+ 0x9c41, 0x9c43, 0x9c45,
+ } {
+ RegisterPCI(0x8086, uint16(id), lynxpoint{variant: "Lynx Point LP"})
+ }
+
+ /* PCIe bridge */
+ for _, id := range []uint16{
+ 0x8c10, 0x8c12, 0x8c14, 0x8c16, 0x8c18, 0x8c1a, 0x8c1c, 0x8c1e,
+ 0x9c10, 0x9c12, 0x9c14, 0x9c16, 0x9c18, 0x9c1a,
+ } {
+ RegisterPCI(0x8086, id, GenericPCI{})
+ }
+
+ /* SMBus controller */
+ RegisterPCI(0x8086, 0x1c22, GenericPCI{MissingParent: "smbus"})
+ RegisterPCI(0x8086, 0x1e22, GenericPCI{MissingParent: "smbus"})
+ RegisterPCI(0x8086, 0x8c22, GenericPCI{MissingParent: "smbus"})
+ RegisterPCI(0x8086, 0x9c22, GenericPCI{MissingParent: "smbus"})
+
+ /* SATA */
+ for _, id := range []uint16{
+ 0x8c00, 0x8c02, 0x8c04, 0x8c06, 0x8c08, 0x8c0e,
+ 0x8c01, 0x8c03, 0x8c05, 0x8c07, 0x8c09, 0x8c0f,
+ 0x9c03, 0x9c05, 0x9c07, 0x9c0f,
+ } {
+ RegisterPCI(0x8086, id, GenericPCI{})
+ }
+
+ /* EHCI */
+ for _, id := range []uint16{
+ 0x9c26, 0x8c26, 0x8c2d,
+ } {
+ RegisterPCI(0x8086, id, GenericPCI{})
+ }
+
+ /* XHCI */
+ RegisterPCI(0x8086, 0x8c31, GenericPCI{})
+ RegisterPCI(0x8086, 0x9c31, GenericPCI{})
+
+ /* ME and children */
+ for _, id := range []uint16{
+ 0x8c3a, 0x8c3b,
+ } {
+ RegisterPCI(0x8086, id, GenericPCI{})
+ }
+
+ /* Ethernet */
+ RegisterPCI(0x8086, 0x8c33, GenericPCI{})
+}
diff --git a/util/autoport/main.go b/util/autoport/main.go
index 05a829b..c1920a7 100644
--- a/util/autoport/main.go
+++ b/util/autoport/main.go
@@ -236,6 +236,12 @@
pcidev.ConfigDump[addr])
}
+func RestoreDIRRoute(f *os.File, regname string, val uint16) {
+ fmt.Fprintf(f, " RCBA_SET_REG_16(%s, DIR_ROUTE(PIRQ%c, PIRQ%c, PIRQ%c, PIRQ%c)),\n",
+ regname, 'A' + (val & 7), 'A' + ((val >> 4) & 7),
+ 'A' + ((val >> 8) & 7), 'A' + ((val >> 12) & 7))
+}
+
func RestorePCI32Simple(f *os.File, pcidev PCIDevData, addr uint16) {
fmt.Fprintf(f, " pci_write_config32(PCI_DEV(%d, 0x%02x, %d), 0x%02x, 0x%02x%02x%02x%02x);\n",
pcidev.Bus, pcidev.Dev, pcidev.Func, addr,
--
To view, visit https://review.coreboot.org/c/coreboot/+/30890
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I4f6e8c97b5122101de2f36bba8ba9f8ddd5b813a
Gerrit-Change-Number: 30890
Gerrit-PatchSet: 1
Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com>
Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com>
Gerrit-MessageType: newchange
2 weeks, 2 days
- 11
- 64
Change in ...coreboot[master]: soc/intel/apl: enable lpc at bootblock
by Thomas Heijligen (Code Review)
Hello Nico Huber,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/31371
to review the following change.
Change subject: soc/intel/apl: enable lpc at bootblock
......................................................................
soc/intel/apl: enable lpc at bootblock
Serial console can be attached to lpc bus. Enable it for early debug
Change-Id: Ib3d09e4eb23655825b7603f49f0bad31116ac6e1
Signed-off-by: Nico Huber <nico.huber(a)secunet.com>
Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.com>
---
M src/soc/intel/apollolake/bootblock/bootblock.c
M src/soc/intel/apollolake/chip.h
M src/soc/intel/apollolake/lpc.c
M src/soc/intel/common/block/lpc/lpc_lib.c
4 files changed, 21 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/31371/1
diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c
index cf3e839..e0217ef 100644
--- a/src/soc/intel/apollolake/bootblock/bootblock.c
+++ b/src/soc/intel/apollolake/bootblock/bootblock.c
@@ -20,6 +20,7 @@
#include <device/pci.h>
#include <intelblocks/cpulib.h>
#include <intelblocks/fast_spi.h>
+#include <intelblocks/lpc_lib.h>
#include <intelblocks/p2sb.h>
#include <intelblocks/pcr.h>
#include <intelblocks/rtc.h>
@@ -120,4 +121,6 @@
paging_set_default_pat();
paging_enable_for_car("pdpt", "pt");
}
+
+ pch_enable_lpc();
}
diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h
index b8f9f8c..2f25a3b 100644
--- a/src/soc/intel/apollolake/chip.h
+++ b/src/soc/intel/apollolake/chip.h
@@ -44,6 +44,9 @@
/* Common structure containing soc config data required by common code*/
struct soc_intel_common_config common_soc_config;
+ /* Generic i/o decode ranges routed to LPC */
+ uint32_t lpc_gen_dec[4];
+
/*
* Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has
* four CLKREQ inputs, but six root ports. Root ports without an
diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c
index a20b82a..ffa4cf5 100644
--- a/src/soc/intel/apollolake/lpc.c
+++ b/src/soc/intel/apollolake/lpc.c
@@ -42,6 +42,18 @@
return apl_lpc_fixed_mmio_ranges;
}
+void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec)
+{
+ const struct soc_intel_apollolake_config *const config = dev->chip_info;
+
+ if (!config) {
+ memset(gen_io_dec, 0x00, sizeof(config->lpc_gen_dec));
+ return;
+ }
+
+ memcpy(gen_io_dec, config->lpc_gen_dec, sizeof(config->lpc_gen_dec));
+}
+
static const struct pad_config lpc_gpios[] = {
#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
#if !IS_ENABLED(CONFIG_SOC_ESPI)
diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c
index fb50b74..d584d2c 100644
--- a/src/soc/intel/common/block/lpc/lpc_lib.c
+++ b/src/soc/intel/common/block/lpc/lpc_lib.c
@@ -24,6 +24,9 @@
#include <lib.h>
#include "lpc_def.h"
#include <soc/pci_devs.h>
+#include <stdint.h>
+
+__weak void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec) {}
uint16_t lpc_enable_fixed_io_ranges(uint16_t io_enables)
{
--
To view, visit https://review.coreboot.org/c/coreboot/+/31371
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ib3d09e4eb23655825b7603f49f0bad31116ac6e1
Gerrit-Change-Number: 31371
Gerrit-PatchSet: 1
Gerrit-Owner: Thomas Heijligen <src(a)posteo.de>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
Gerrit-MessageType: newchange
1 month
- 7
- 15
Change in ...coreboot[master]: soc/intel/denverton_ns: Rewrite pmutil using pmclib
by Patrick Georgi (Code Review)
Hello Julien Viard de Galbert,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/31072
to review the following change.
Change subject: soc/intel/denverton_ns: Rewrite pmutil using pmclib
......................................................................
soc/intel/denverton_ns: Rewrite pmutil using pmclib
Change-Id: I13ab94e7440886f77e3091b16e50e48b17151751
Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net>
---
M src/soc/intel/denverton_ns/include/soc/pm.h
M src/soc/intel/denverton_ns/pmutil.c
M src/soc/intel/denverton_ns/smihandler.c
M src/soc/intel/denverton_ns/smm.c
4 files changed, 33 insertions(+), 184 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/31072/1
diff --git a/src/soc/intel/denverton_ns/include/soc/pm.h b/src/soc/intel/denverton_ns/include/soc/pm.h
index 09ce158..0aab0e2 100644
--- a/src/soc/intel/denverton_ns/include/soc/pm.h
+++ b/src/soc/intel/denverton_ns/include/soc/pm.h
@@ -47,18 +47,6 @@
struct chipset_power_state *fill_power_state(void);
/* Power Management Utility Functions. */
-uint32_t clear_smi_status(void);
-uint16_t clear_pm1_status(void);
-uint32_t clear_tco_status(void);
-uint32_t clear_gpe_status(void);
void clear_pmc_status(void);
-void enable_smi(uint32_t mask);
-void disable_smi(uint32_t mask);
-void enable_pm1(uint16_t events);
-void enable_pm1_control(uint32_t mask);
-void disable_pm1_control(uint32_t mask);
-void enable_gpe(uint32_t mask);
-void disable_gpe(uint32_t mask);
-void disable_all_gpe(void);
#endif /* _DENVERTON_NS_PM_H_ */
diff --git a/src/soc/intel/denverton_ns/pmutil.c b/src/soc/intel/denverton_ns/pmutil.c
index ccf0d95..344f8b9 100644
--- a/src/soc/intel/denverton_ns/pmutil.c
+++ b/src/soc/intel/denverton_ns/pmutil.c
@@ -19,29 +19,12 @@
#include <arch/io.h>
#include <console/console.h>
+#include <intelblocks/pmclib.h>
#include <soc/iomap.h>
#include <soc/soc_util.h>
#include <soc/pm.h>
-static void print_num_status_bits(int num_bits, uint32_t status,
- const char *const bit_names[])
-{
- int i;
-
- if (!status)
- return;
-
- for (i = num_bits - 1; i >= 0; i--) {
- if (status & (1 << i)) {
- if (bit_names[i])
- printk(BIOS_DEBUG, "%s ", bit_names[i]);
- else
- printk(BIOS_DEBUG, "BIT%d ", i);
- }
- }
-}
-
-static uint32_t print_smi_status(uint32_t smi_sts)
+const char *const *soc_smi_sts_array(size_t *a)
{
static const char *const smi_sts_bits[] = {
[2] = "BIOS",
@@ -67,93 +50,11 @@
[31] = "LEGACY_USB3",
};
- if (!smi_sts)
- return 0;
-
- printk(BIOS_DEBUG, "SMI_STS: ");
- print_num_status_bits(ARRAY_SIZE(smi_sts_bits), smi_sts, smi_sts_bits);
- printk(BIOS_DEBUG, "\n");
-
- return smi_sts;
+ *a = ARRAY_SIZE(smi_sts_bits);
+ return smi_sts_bits;
}
-static uint32_t reset_smi_status(void)
-{
- uint16_t pmbase = get_pmbase();
- uint32_t smi_sts = inl((uint16_t)(pmbase + SMI_STS));
- outl(smi_sts, (uint16_t)(pmbase + SMI_STS));
- return smi_sts;
-}
-
-uint32_t clear_smi_status(void) { return print_smi_status(reset_smi_status()); }
-
-void enable_smi(uint32_t mask)
-{
- uint16_t pmbase = get_pmbase();
- uint32_t smi_en = inl((uint16_t)(pmbase + SMI_EN));
- smi_en |= mask;
- outl(smi_en, (uint16_t)(pmbase + SMI_EN));
-}
-
-void disable_smi(uint32_t mask)
-{
- uint16_t pmbase = get_pmbase();
- uint32_t smi_en = inl((uint16_t)(pmbase + SMI_EN));
- smi_en &= ~mask;
- outl(smi_en, (uint16_t)(pmbase + SMI_EN));
-}
-
-void enable_pm1_control(uint32_t mask)
-{
- uint16_t pmbase = get_pmbase();
- uint32_t pm1_cnt = inl((uint16_t)(pmbase + PM1_CNT));
- pm1_cnt |= mask;
- outl(pm1_cnt, (uint16_t)(pmbase + PM1_CNT));
-}
-
-void disable_pm1_control(uint32_t mask)
-{
- uint16_t pmbase = get_pmbase();
- uint32_t pm1_cnt = inl((uint16_t)(pmbase + PM1_CNT));
- pm1_cnt &= ~mask;
- outl(pm1_cnt, (uint16_t)(pmbase + PM1_CNT));
-}
-
-static uint16_t reset_pm1_status(void)
-{
- uint16_t pmbase = get_pmbase();
- uint16_t pm1_sts = inw((uint16_t)(pmbase + PM1_STS));
- outw(pm1_sts, (uint16_t)(pmbase + PM1_STS));
- return pm1_sts;
-}
-
-static uint16_t print_pm1_status(uint16_t pm1_sts)
-{
- static const char *const pm1_sts_bits[] = {
- [0] = "TMROF", [4] = "BM", [5] = "GBL",
- [8] = "PWRBTN", [10] = "RTC", [11] = "PRBTNOR",
- [15] = "WAK",
- };
-
- if (!pm1_sts)
- return 0;
-
- printk(BIOS_SPEW, "PM1_STS: ");
- print_num_status_bits(ARRAY_SIZE(pm1_sts_bits), pm1_sts, pm1_sts_bits);
- printk(BIOS_SPEW, "\n");
-
- return pm1_sts;
-}
-
-uint16_t clear_pm1_status(void) { return print_pm1_status(reset_pm1_status()); }
-
-void enable_pm1(uint16_t events)
-{
- uint16_t pmbase = get_pmbase();
- outw(events, (uint16_t)(pmbase + PM1_EN));
-}
-
-static uint32_t print_tco_status(uint32_t tco_sts)
+const char *const *soc_tco_sts_array(size_t *a)
{
static const char *const tco_sts_bits[] = {
[0] = "NMI2SMI", [1] = "OS_TCO_SMI",
@@ -164,17 +65,11 @@
[17] = "SECOND_TO", [20] = "SMLINK_SLV_SMI",
};
- if (!tco_sts)
- return 0;
-
- printk(BIOS_DEBUG, "TCO_STS: ");
- print_num_status_bits(ARRAY_SIZE(tco_sts_bits), tco_sts, tco_sts_bits);
- printk(BIOS_DEBUG, "\n");
-
- return tco_sts;
+ *a = ARRAY_SIZE(tco_sts_bits);
+ return tco_sts_bits;
}
-static uint32_t reset_tco_status(void)
+uint32_t soc_reset_tco_status(void)
{
uint16_t tcobase = get_tcobase();
uint32_t tco_sts = inl((uint16_t)(tcobase + TCO1_STS));
@@ -184,35 +79,7 @@
return tco_sts & tco_en;
}
-uint32_t clear_tco_status(void) { return print_tco_status(reset_tco_status()); }
-
-void enable_gpe(uint32_t mask)
-{
- uint16_t pmbase = get_pmbase();
- uint32_t gpe0_en = inl((uint16_t)(pmbase + GPE0_EN(GPE_STD)));
- gpe0_en |= mask;
- outl(gpe0_en, (uint16_t)(pmbase + GPE0_EN(GPE_STD)));
-}
-
-void disable_gpe(uint32_t mask)
-{
- uint16_t pmbase = get_pmbase();
- uint32_t gpe0_en = inl((uint16_t)(pmbase + GPE0_EN(GPE_STD)));
- gpe0_en &= ~mask;
- outl(gpe0_en, (uint16_t)(pmbase + GPE0_EN(GPE_STD)));
-}
-
-void disable_all_gpe(void) { disable_gpe(~0); }
-
-static uint32_t reset_gpe_status(void)
-{
- uint16_t pmbase = get_pmbase();
- uint32_t gpe_sts = inl((uint16_t)(pmbase + GPE0_STS(GPE_STD)));
- outl(gpe_sts, (uint16_t)(pmbase + GPE0_STS(GPE_STD)));
- return gpe_sts;
-}
-
-static uint32_t print_gpe_sts(uint32_t gpe_sts)
+const char *const *soc_std_gpe_sts_array(size_t *a)
{
static const char *const gpe_sts_bits[] = {
[0] = "GPIO_0", [1] = "GPIO_1",
@@ -233,16 +100,8 @@
[30] = "GPIO_30", [31] = "GPIO_31",
};
- if (!gpe_sts)
- return gpe_sts;
-
- printk(BIOS_DEBUG, "GPE0a_STS: ");
- print_num_status_bits(ARRAY_SIZE(gpe_sts_bits), gpe_sts, gpe_sts_bits);
- printk(BIOS_DEBUG, "\n");
-
- return gpe_sts;
+ *a = ARRAY_SIZE(gpe_sts_bits);
+ return gpe_sts_bits;
}
-uint32_t clear_gpe_status(void) { return print_gpe_sts(reset_gpe_status()); }
-
void clear_pmc_status(void) { /* TODO */ }
diff --git a/src/soc/intel/denverton_ns/smihandler.c b/src/soc/intel/denverton_ns/smihandler.c
index 85f99d7..e1e7bc4 100644
--- a/src/soc/intel/denverton_ns/smihandler.c
+++ b/src/soc/intel/denverton_ns/smihandler.c
@@ -25,6 +25,7 @@
#include <device/pci_def.h>
#include <elog.h>
#include <intelblocks/fast_spi.h>
+#include <intelblocks/pmclib.h>
#include <spi-generic.h>
#include <soc/iomap.h>
#include <soc/soc_util.h>
@@ -52,7 +53,7 @@
return 0;
}
-void southbridge_smi_set_eos(void) { enable_smi(EOS); }
+void southbridge_smi_set_eos(void) { pmc_enable_smi(EOS); }
global_nvs_t *smm_get_gnvs(void) { return gnvs; }
@@ -98,7 +99,7 @@
uint16_t pmbase = get_pmbase();
/* First, disable further SMIs */
- disable_smi(SLP_SMI_EN);
+ pmc_disable_smi(SLP_SMI_EN);
/* Figure out SLP_TYP */
reg32 = inl((uint16_t)(pmbase + PM1_CNT));
@@ -131,7 +132,7 @@
printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n");
/* Disable all GPE */
- disable_all_gpe();
+ pmc_disable_all_gpe();
/* also iterates over all bridges on bus 0 */
busmaster_disable_on_bus(0);
@@ -145,7 +146,7 @@
* event again. We need to set BIT13 (SLP_EN) though to make the
* sleep happen.
*/
- enable_pm1_control(SLP_EN);
+ pmc_enable_pm1_control(SLP_EN);
/* Make sure to stop executing code here for S3/S4/S5 */
if (slp_typ > 1)
@@ -158,7 +159,7 @@
reg32 = inl((uint16_t)(pmbase + PM1_CNT));
if (reg32 & SCI_EN) {
/* The OS is not an ACPI OS, so we set the state to S0 */
- disable_pm1_control(SLP_EN | SLP_TYP);
+ pmc_disable_pm1_control(SLP_EN | SLP_TYP);
}
}
@@ -237,11 +238,11 @@
printk(BIOS_DEBUG, "P-state control\n");
break;
case APM_CNT_ACPI_DISABLE:
- disable_pm1_control(SCI_EN);
+ pmc_disable_pm1_control(SCI_EN);
printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n");
break;
case APM_CNT_ACPI_ENABLE:
- enable_pm1_control(SCI_EN);
+ pmc_enable_pm1_control(SCI_EN);
printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n");
break;
case APM_CNT_FINALIZE:
@@ -268,23 +269,23 @@
static void southbridge_smi_pm1(void)
{
- uint16_t pm1_sts = clear_pm1_status();
+ uint16_t pm1_sts = pmc_clear_pm1_status();
/* While OSPM is not active, poweroff immediately
* on a power button event.
*/
if (pm1_sts & PWRBTN_STS) {
// power button pressed
- disable_pm1_control(-1UL);
- enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT));
+ pmc_disable_pm1_control(-1UL);
+ pmc_enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT));
}
}
-static void southbridge_smi_gpe0(void) { clear_gpe_status(); }
+static void southbridge_smi_gpe0(void) { pmc_clear_all_gpe_status(); }
static void southbridge_smi_tco(void)
{
- uint32_t tco_sts = clear_tco_status();
+ uint32_t tco_sts = pmc_clear_tco_status();
/* Any TCO event? */
if (!tco_sts)
@@ -354,7 +355,7 @@
/* We need to clear the SMI status registers, or we won't see what's
* happening in the following calls.
*/
- smi_sts = clear_smi_status();
+ smi_sts = pmc_clear_smi_status();
/* Call SMI sub handler for each of the status bits */
for (i = 0; i < ARRAY_SIZE(southbridge_smi); i++) {
diff --git a/src/soc/intel/denverton_ns/smm.c b/src/soc/intel/denverton_ns/smm.c
index 9d3fa75..65d2499 100644
--- a/src/soc/intel/denverton_ns/smm.c
+++ b/src/soc/intel/denverton_ns/smm.c
@@ -23,6 +23,7 @@
#include <cpu/x86/smm.h>
#include <string.h>
+#include <intelblocks/pmclib.h>
#include <soc/iomap.h>
#include <soc/soc_util.h>
#include <soc/pm.h>
@@ -48,10 +49,10 @@
}
/* Dump and clear status registers */
- clear_smi_status();
- clear_pm1_status();
- clear_tco_status();
- clear_gpe_status();
+ pmc_clear_smi_status();
+ pmc_clear_pm1_status();
+ pmc_clear_tco_status();
+ pmc_clear_all_gpe_status();
clear_pmc_status();
}
@@ -60,8 +61,8 @@
printk(BIOS_DEBUG, "Enabling SMIs.\n");
/* Configure events Disable pcie wake. */
- enable_pm1(PWRBTN_EN | GBL_EN | PCIEXPWAK_DIS);
- disable_gpe(PME_B0_EN);
+ pmc_enable_pm1(PWRBTN_EN | GBL_EN | PCIEXPWAK_DIS);
+ pmc_disable_std_gpe(PME_B0_EN);
/* Enable SMI generation:
* - on APMC writes (io 0xb2)
@@ -71,7 +72,7 @@
* - on TCO events
* - on microcontroller writes (io 0x62/0x66)
*/
- enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS);
+ pmc_enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS);
}
void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I13ab94e7440886f77e3091b16e50e48b17151751
Gerrit-Change-Number: 31072
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name>
Gerrit-MessageType: newchange
1 month, 2 weeks
- 5
- 7
Change in ...coreboot[master]: mb/apple: Add MacBook Pro 10,1 (A1398) support
by Evgeny Zinoviev (Code Review)
Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32673
Change subject: mb/apple: Add MacBook Pro 10,1 (A1398) support
......................................................................
mb/apple: Add MacBook Pro 10,1 (A1398) support
MacBook Pro Retina 15 (Mid 2012) with Ivy Bridge CPU.
This is WIP. Not for merging.
Change-Id: Ica03aba442493c0d369a3d360ad569ddc16954df
Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io>
---
M 3rdparty/vboot
A src/mainboard/apple/macbookpro10_1/Kconfig
A src/mainboard/apple/macbookpro10_1/Kconfig.name
A src/mainboard/apple/macbookpro10_1/Makefile.inc
A src/mainboard/apple/macbookpro10_1/acpi/ec.asl
A src/mainboard/apple/macbookpro10_1/acpi/platform.asl
A src/mainboard/apple/macbookpro10_1/acpi/superio.asl
A src/mainboard/apple/macbookpro10_1/acpi_tables.c
A src/mainboard/apple/macbookpro10_1/board_info.txt
A src/mainboard/apple/macbookpro10_1/devicetree.cb
A src/mainboard/apple/macbookpro10_1/dsdt.asl
A src/mainboard/apple/macbookpro10_1/gma-mainboard.ads
A src/mainboard/apple/macbookpro10_1/gpio.c
A src/mainboard/apple/macbookpro10_1/hda_verb.c
A src/mainboard/apple/macbookpro10_1/mainboard.c
A src/mainboard/apple/macbookpro10_1/romstage.c
16 files changed, 758 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/32673/1
diff --git a/3rdparty/vboot b/3rdparty/vboot
index e7edff6..304aa42 160000
--- a/3rdparty/vboot
+++ b/3rdparty/vboot
@@ -1 +1 @@
-Subproject commit e7edff6653e16ed915c3ad12234d133d1ef4dcc9
+Subproject commit 304aa429c1a04cda3ab2ce37b9e31af84405bfca
diff --git a/src/mainboard/apple/macbookpro10_1/Kconfig b/src/mainboard/apple/macbookpro10_1/Kconfig
new file mode 100644
index 0000000..603f3ee
--- /dev/null
+++ b/src/mainboard/apple/macbookpro10_1/Kconfig
@@ -0,0 +1,46 @@
+if BOARD_APPLE_MACBOOKPRO10_1
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select BOARD_ROMSIZE_KB_8192
+ select EC_ACPI
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select INTEL_INT15
+ select NORTHBRIDGE_INTEL_IVYBRIDGE
+ select SERIRQ_CONTINUOUS_MODE
+ select SOUTHBRIDGE_INTEL_C216
+ select SYSTEM_TYPE_LAPTOP
+ select USE_NATIVE_RAMINIT
+ select MAINBOARD_HAS_LIBGFXINIT
+ select GFX_GMA_INTERNAL_IS_EDP
+ select SERIRQ_CONTINUOUS_MODE
+
+config MAINBOARD_DIR
+ string
+ default apple/macbookpro10_1
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "MacBookPro10,1"
+
+config VGA_BIOS_FILE
+ string
+ default "pci8086,0166.rom"
+
+config VGA_BIOS_ID
+ string
+ default "8086,0166"
+
+config DRAM_RESET_GATE_GPIO
+ int
+ default 28
+
+config MAX_CPUS
+ int
+ default 8
+
+config USBDEBUG_HCD_INDEX # FIXME: check this
+ int
+ default 2
+endif
diff --git a/src/mainboard/apple/macbookpro10_1/Kconfig.name b/src/mainboard/apple/macbookpro10_1/Kconfig.name
new file mode 100644
index 0000000..c257f7a
--- /dev/null
+++ b/src/mainboard/apple/macbookpro10_1/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_APPLE_MACBOOKPRO10_1
+ bool "MacBookPro10,1"
diff --git a/src/mainboard/apple/macbookpro10_1/Makefile.inc b/src/mainboard/apple/macbookpro10_1/Makefile.inc
new file mode 100644
index 0000000..fd60338
--- /dev/null
+++ b/src/mainboard/apple/macbookpro10_1/Makefile.inc
@@ -0,0 +1,7 @@
+romstage-y += gpio.c
+
+cbfs-files-y += spd.bin
+spd.bin-file := spd.bin
+spd.bin-type := spd
+
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/apple/macbookpro10_1/acpi/ec.asl b/src/mainboard/apple/macbookpro10_1/acpi/ec.asl
new file mode 100644
index 0000000..f70cb3d
--- /dev/null
+++ b/src/mainboard/apple/macbookpro10_1/acpi/ec.asl
@@ -0,0 +1,20 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Device(EC)
+{
+ Name (_HID, EISAID("PNP0C09"))
+ Name (_UID, 0)
+ Name (_GPE, 23)
+/* FIXME: EC support */
+}
diff --git a/src/mainboard/apple/macbookpro10_1/acpi/platform.asl b/src/mainboard/apple/macbookpro10_1/acpi/platform.asl
new file mode 100644
index 0000000..a17c6ea
--- /dev/null
+++ b/src/mainboard/apple/macbookpro10_1/acpi/platform.asl
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Method(_WAK,1)
+{
+ /* FIXME: EC support */
+ Return(Package(){0,0})
+}
+
+Method(_PTS,1)
+{
+ /* FIXME: EC support */
+}
diff --git a/src/mainboard/apple/macbookpro10_1/acpi/superio.asl b/src/mainboard/apple/macbookpro10_1/acpi/superio.asl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/apple/macbookpro10_1/acpi/superio.asl
diff --git a/src/mainboard/apple/macbookpro10_1/acpi_tables.c b/src/mainboard/apple/macbookpro10_1/acpi_tables.c
new file mode 100644
index 0000000..c48f0bd
--- /dev/null
+++ b/src/mainboard/apple/macbookpro10_1/acpi_tables.c
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/bd82x6x/nvs.h>
+
+/* FIXME: check this function. */
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+ /* Disable USB ports in S3 by default */
+ gnvs->s3u0 = 0;
+ gnvs->s3u1 = 0;
+
+ /* Disable USB ports in S5 by default */
+ gnvs->s5u0 = 0;
+ gnvs->s5u1 = 0;
+
+ // the lid is open by default.
+ gnvs->lids = 1;
+
+ gnvs->tcrt = 100;
+ gnvs->tpsv = 90;
+}
diff --git a/src/mainboard/apple/macbookpro10_1/board_info.txt b/src/mainboard/apple/macbookpro10_1/board_info.txt
new file mode 100644
index 0000000..81a5134
--- /dev/null
+++ b/src/mainboard/apple/macbookpro10_1/board_info.txt
@@ -0,0 +1,6 @@
+Category: laptop
+ROM protocol: SPI
+Flashrom support: n
+ROM package: SOIC-8
+ROM socketed: n
+Release year: 2012
diff --git a/src/mainboard/apple/macbookpro10_1/devicetree.cb b/src/mainboard/apple/macbookpro10_1/devicetree.cb
new file mode 100644
index 0000000..f9e7eb4
--- /dev/null
+++ b/src/mainboard/apple/macbookpro10_1/devicetree.cb
@@ -0,0 +1,124 @@
+chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did
+ #register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }"
+ register "gfx.did" = "{ 0x80000410, 0x80000320, 0x80000410, 0x80000410, 0x00000005 }"
+ register "gfx.link_frequency_270_mhz" = "0"
+ register "gfx.ndid" = "3"
+ register "gfx.use_spread_spectrum_clock" = "1"
+ register "gpu_cpu_backlight" = "0xffffffff"
+ register "gpu_dp_b_hotplug" = "7"
+ register "gpu_dp_c_hotplug" = "7"
+ register "gpu_dp_d_hotplug" = "7"
+ register "gpu_panel_port_select" = "3"
+ register "gpu_panel_power_backlight_off_delay" = "8191"
+ register "gpu_panel_power_backlight_on_delay" = "8191"
+ register "gpu_panel_power_cycle_delay" = "255"
+ register "gpu_panel_power_down_delay" = "8191"
+ register "gpu_panel_power_up_delay" = "8191"
+ register "gpu_pch_backlight" = "0xffffffff"
+ device cpu_cluster 0x0 on
+ chip cpu/intel/model_206ax # FIXME: check all registers
+ register "c1_acpower" = "1"
+ register "c1_battery" = "1"
+ register "c2_acpower" = "3"
+ register "c2_battery" = "3"
+ register "c3_acpower" = "5"
+ register "c3_battery" = "5"
+ device lapic 0x0 on
+ end
+ device lapic 0xacac off
+ end
+ end
+ end
+ device domain 0x0 on
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+ register "c2_latency" = "0x0065"
+ register "docking_supported" = "0"
+ register "gen1_dec" = "0x000c0681"
+ register "gen2_dec" = "0x000c1641"
+ register "gen3_dec" = "0x001c0301"
+ register "gen4_dec" = "0x00fc0701"
+ register "gpi7_routing" = "2"
+ register "p_cnt_throttling_supported" = "1"
+ register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
+ register "pcie_port_coalesce" = "1"
+ register "sata_interface_speed_support" = "0x3"
+ register "sata_port_map" = "0x1"
+ register "spi_lvscc" = "0x0"
+ register "spi_uvscc" = "0x2005"
+ register "superspeed_capable_ports" = "0x0000000f"
+ register "xhci_overcurrent_mapping" = "0x08040201"
+ register "xhci_switchable_ports" = "0x0000000f"
+ device pci 14.0 on # USB 3.0 Controller
+ subsystemid 0x8086 0x7270
+ end
+ device pci 16.0 on # Management Engine Interface 1
+ subsystemid 0x8086 0x7270
+ end
+ device pci 16.1 off # Management Engine Interface 2
+ end
+ device pci 16.2 off # Management Engine IDE-R
+ end
+ device pci 16.3 off # Management Engine KT
+ end
+ device pci 19.0 off # Intel Gigabit Ethernet
+ end
+ device pci 1a.0 on # USB2 EHCI #2
+ subsystemid 0x8086 0x7270
+ end
+ device pci 1b.0 on # High Definition Audio Audio controller
+ subsystemid 0x8086 0x7270
+ end
+ device pci 1c.0 on # PCIe Port #1
+ subsystemid 0x8086 0x7270
+ end
+ device pci 1c.1 on # PCIe Port #2
+ subsystemid 0x8086 0x7270
+ end
+ device pci 1c.2 off # PCIe Port #3
+ end
+ device pci 1c.3 off # PCIe Port #4
+ end
+ device pci 1c.4 off # PCIe Port #5
+ end
+ device pci 1c.5 off # PCIe Port #6
+ end
+ device pci 1c.6 off # PCIe Port #7
+ end
+ device pci 1c.7 off # PCIe Port #8
+ end
+ device pci 1d.0 on # USB2 EHCI #1
+ subsystemid 0x8086 0x7270
+ end
+ device pci 1e.0 off # PCI bridge
+ end
+ device pci 1f.0 on # LPC bridge PCI-LPC bridge
+ subsystemid 0x8086 0x7270
+ end
+ device pci 1f.2 on # SATA Controller 1
+ subsystemid 0x8086 0x7270
+ end
+ device pci 1f.3 on # SMBus
+ subsystemid 0x8086 0x7270
+ end
+ device pci 1f.5 off # SATA Controller 2
+ end
+ device pci 1f.6 off # Thermal
+ end
+ end
+ device pci 00.0 on # Host bridge Host bridge
+ subsystemid 0x106b 0x00f7
+ end
+ device pci 01.0 on # PCIe Bridge for discrete graphics
+ subsystemid 0x106b 0x00f7
+ end
+ device pci 02.0 on # Internal graphics VGA controller
+ subsystemid 0x106b 0x00f7
+ end
+ device pci 01.2 on
+ subsystemid 0x106b 0x00f7
+ end
+ device pci 01.1 on
+ subsystemid 0x106b 0x00f7
+ end
+ end
+end
diff --git a/src/mainboard/apple/macbookpro10_1/dsdt.asl b/src/mainboard/apple/macbookpro10_1/dsdt.asl
new file mode 100644
index 0000000..455ac17
--- /dev/null
+++ b/src/mainboard/apple/macbookpro10_1/dsdt.asl
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
+#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
+
+#include <arch/acpi.h>
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, // DSDT revision: ACPI 2.0 and up
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20141018 // OEM revision
+)
+{
+ /* Some generic macros */
+ #include "acpi/platform.asl"
+ #include <cpu/intel/common/acpi/cpu.asl>
+ #include <southbridge/intel/bd82x6x/acpi/platform.asl>
+ /* global NVS and variables. */
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+ #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
+
+ Device (\_SB.PCI0)
+ {
+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
+ }
+}
diff --git a/src/mainboard/apple/macbookpro10_1/gma-mainboard.ads b/src/mainboard/apple/macbookpro10_1/gma-mainboard.ads
new file mode 100644
index 0000000..d4a5d7d
--- /dev/null
+++ b/src/mainboard/apple/macbookpro10_1/gma-mainboard.ads
@@ -0,0 +1,34 @@
+--
+-- This file is part of the coreboot project.
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ ports : constant Port_List :=
+ (DP1,
+ DP2,
+ DP3,
+ HDMI1,
+ HDMI2,
+ HDMI3,
+ Analog,
+ Internal,
+ others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/apple/macbookpro10_1/gpio.c b/src/mainboard/apple/macbookpro10_1/gpio.c
new file mode 100644
index 0000000..a445687
--- /dev/null
+++ b/src/mainboard/apple/macbookpro10_1/gpio.c
@@ -0,0 +1,243 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio1 = GPIO_MODE_GPIO,
+ .gpio2 = GPIO_MODE_GPIO,
+ .gpio3 = GPIO_MODE_GPIO,
+ .gpio4 = GPIO_MODE_GPIO,
+ .gpio5 = GPIO_MODE_GPIO,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_NATIVE,
+ .gpio10 = GPIO_MODE_GPIO,
+ .gpio11 = GPIO_MODE_GPIO,
+ .gpio12 = GPIO_MODE_GPIO,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_GPIO,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio16 = GPIO_MODE_GPIO,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_NATIVE,
+ .gpio19 = GPIO_MODE_GPIO,
+ .gpio20 = GPIO_MODE_NATIVE,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio23 = GPIO_MODE_GPIO,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_NATIVE,
+ .gpio26 = GPIO_MODE_GPIO,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_GPIO,
+ .gpio30 = GPIO_MODE_NATIVE,
+ .gpio31 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT,
+ .gpio1 = GPIO_DIR_INPUT,
+ .gpio2 = GPIO_DIR_INPUT,
+ .gpio3 = GPIO_DIR_INPUT,
+ .gpio4 = GPIO_DIR_INPUT,
+ .gpio5 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_OUTPUT,
+ .gpio10 = GPIO_DIR_INPUT,
+ .gpio11 = GPIO_DIR_INPUT,
+ .gpio12 = GPIO_DIR_OUTPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio14 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_OUTPUT,
+ .gpio16 = GPIO_DIR_OUTPUT,
+ .gpio17 = GPIO_DIR_INPUT,
+ .gpio19 = GPIO_DIR_OUTPUT,
+ .gpio21 = GPIO_DIR_OUTPUT,
+ .gpio22 = GPIO_DIR_OUTPUT,
+ .gpio23 = GPIO_DIR_OUTPUT,
+ .gpio24 = GPIO_DIR_OUTPUT,
+ .gpio26 = GPIO_DIR_INPUT,
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_OUTPUT,
+ .gpio29 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio8 = GPIO_LEVEL_HIGH,
+ .gpio12 = GPIO_LEVEL_LOW,
+ .gpio15 = GPIO_LEVEL_HIGH,
+ .gpio16 = GPIO_LEVEL_LOW,
+ .gpio19 = GPIO_LEVEL_HIGH,
+ .gpio21 = GPIO_LEVEL_LOW,
+ .gpio22 = GPIO_LEVEL_LOW,
+ .gpio23 = GPIO_LEVEL_HIGH,
+ .gpio24 = GPIO_LEVEL_LOW,
+ .gpio28 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+ .gpio11 = GPIO_RESET_RSMRST,
+ .gpio15 = GPIO_RESET_RSMRST,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio1 = GPIO_INVERT,
+ .gpio2 = GPIO_INVERT,
+ .gpio4 = GPIO_INVERT,
+ .gpio5 = GPIO_INVERT,
+ .gpio7 = GPIO_INVERT,
+ .gpio14 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_NATIVE,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_GPIO,
+ .gpio36 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio40 = GPIO_MODE_NATIVE,
+ .gpio41 = GPIO_MODE_NATIVE,
+ .gpio42 = GPIO_MODE_NATIVE,
+ .gpio43 = GPIO_MODE_NATIVE,
+ .gpio44 = GPIO_MODE_NATIVE,
+ .gpio45 = GPIO_MODE_NATIVE,
+ .gpio46 = GPIO_MODE_NATIVE,
+ .gpio47 = GPIO_MODE_GPIO,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio50 = GPIO_MODE_GPIO,
+ .gpio51 = GPIO_MODE_GPIO,
+ .gpio52 = GPIO_MODE_GPIO,
+ .gpio53 = GPIO_MODE_GPIO,
+ .gpio54 = GPIO_MODE_GPIO,
+ .gpio55 = GPIO_MODE_GPIO,
+ .gpio56 = GPIO_MODE_GPIO,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_NATIVE,
+ .gpio60 = GPIO_MODE_GPIO,
+ .gpio61 = GPIO_MODE_NATIVE,
+ .gpio62 = GPIO_MODE_NATIVE,
+ .gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio33 = GPIO_DIR_INPUT,
+ .gpio34 = GPIO_DIR_OUTPUT,
+ .gpio35 = GPIO_DIR_OUTPUT,
+ .gpio36 = GPIO_DIR_OUTPUT,
+ .gpio37 = GPIO_DIR_INPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio47 = GPIO_DIR_INPUT,
+ .gpio48 = GPIO_DIR_OUTPUT,
+ .gpio49 = GPIO_DIR_OUTPUT,
+ .gpio50 = GPIO_DIR_INPUT,
+ .gpio51 = GPIO_DIR_OUTPUT,
+ .gpio52 = GPIO_DIR_OUTPUT,
+ .gpio53 = GPIO_DIR_OUTPUT,
+ .gpio54 = GPIO_DIR_OUTPUT,
+ .gpio55 = GPIO_DIR_OUTPUT,
+ .gpio56 = GPIO_DIR_INPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+ .gpio60 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio34 = GPIO_LEVEL_HIGH,
+ .gpio35 = GPIO_LEVEL_LOW,
+ .gpio36 = GPIO_LEVEL_LOW,
+ .gpio48 = GPIO_LEVEL_HIGH,
+ .gpio49 = GPIO_LEVEL_HIGH,
+ .gpio51 = GPIO_LEVEL_HIGH,
+ .gpio52 = GPIO_LEVEL_LOW,
+ .gpio53 = GPIO_LEVEL_HIGH,
+ .gpio54 = GPIO_LEVEL_LOW,
+ .gpio55 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_GPIO,
+ .gpio65 = GPIO_MODE_GPIO,
+ .gpio66 = GPIO_MODE_GPIO,
+ .gpio67 = GPIO_MODE_GPIO,
+ .gpio68 = GPIO_MODE_GPIO,
+ .gpio69 = GPIO_MODE_GPIO,
+ .gpio70 = GPIO_MODE_GPIO,
+ .gpio71 = GPIO_MODE_GPIO,
+ .gpio72 = GPIO_MODE_NATIVE,
+ .gpio73 = GPIO_MODE_GPIO,
+ .gpio74 = GPIO_MODE_GPIO,
+ .gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio64 = GPIO_DIR_OUTPUT,
+ .gpio65 = GPIO_DIR_OUTPUT,
+ .gpio66 = GPIO_DIR_OUTPUT,
+ .gpio67 = GPIO_DIR_OUTPUT,
+ .gpio68 = GPIO_DIR_INPUT,
+ .gpio69 = GPIO_DIR_INPUT,
+ .gpio70 = GPIO_DIR_INPUT,
+ .gpio71 = GPIO_DIR_INPUT,
+ .gpio73 = GPIO_DIR_INPUT,
+ .gpio74 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+ .gpio64 = GPIO_LEVEL_LOW,
+ .gpio65 = GPIO_LEVEL_LOW,
+ .gpio66 = GPIO_LEVEL_LOW,
+ .gpio67 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/apple/macbookpro10_1/hda_verb.c b/src/mainboard/apple/macbookpro10_1/hda_verb.c
new file mode 100644
index 0000000..b8e4855
--- /dev/null
+++ b/src/mainboard/apple/macbookpro10_1/hda_verb.c
@@ -0,0 +1,58 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x10134206, /* Codec Vendor / Device ID: Cirrus */
+ 0x106b2800, /* Subsystem ID */
+
+ 0x0000000b, /* Number of 4 dword sets */
+ /* NID 0x01: Subsystem ID. */
+ AZALIA_SUBVENDOR(0x0, 0x106b2800),
+
+ /* NID 0x09. */
+ AZALIA_PIN_CFG(0x0, 0x09, 0x002b4020),
+
+ /* NID 0x0a. */
+ AZALIA_PIN_CFG(0x0, 0x0a, 0x90100112),
+
+ /* NID 0x0b. */
+ AZALIA_PIN_CFG(0x0, 0x0b, 0x90100110),
+
+ /* NID 0x0c. */
+ AZALIA_PIN_CFG(0x0, 0x0c, 0x400000f0),
+
+ /* NID 0x0d. */
+ AZALIA_PIN_CFG(0x0, 0x0d, 0x400000f0),
+
+ /* NID 0x0e. */
+ AZALIA_PIN_CFG(0x0, 0x0e, 0x90a60100),
+
+ /* NID 0x0f. */
+ AZALIA_PIN_CFG(0x0, 0x0f, 0x400000f0),
+
+ /* NID 0x10. */
+ AZALIA_PIN_CFG(0x0, 0x10, 0x004be030),
+
+ /* NID 0x12. */
+ AZALIA_PIN_CFG(0x0, 0x12, 0x400000f0),
+
+ /* NID 0x15. */
+ AZALIA_PIN_CFG(0x0, 0x15, 0x400000f0),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/apple/macbookpro10_1/mainboard.c b/src/mainboard/apple/macbookpro10_1/mainboard.c
new file mode 100644
index 0000000..3910541
--- /dev/null
+++ b/src/mainboard/apple/macbookpro10_1/mainboard.c
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/device.h>
+#include <drivers/intel/gma/int15.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <ec/acpi/ec.h>
+#include <console/console.h>
+
+static void mainboard_init(struct device *dev)
+{
+
+}
+
+static void mainboard_enable(struct device *dev)
+{
+ dev->ops->init = mainboard_init;
+
+ /* FIXME: fix those values*/
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
+ GMA_INT15_PANEL_FIT_DEFAULT,
+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/apple/macbookpro10_1/romstage.c b/src/mainboard/apple/macbookpro10_1/romstage.c
new file mode 100644
index 0000000..c35604b
--- /dev/null
+++ b/src/mainboard/apple/macbookpro10_1/romstage.c
@@ -0,0 +1,82 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* FIXME: Check if all includes are needed. */
+
+#include <stdint.h>
+#include <string.h>
+#include <timestamp.h>
+#include <arch/byteorder.h>
+#include <arch/io.h>
+#include <device/mmio.h>
+#include <device/pci_ops.h>
+#include <device/pnp_ops.h>
+#include <console/console.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/gpio.h>
+#include <cbfs.h>
+
+void pch_enable_lpc(void)
+{
+ pci_write_config16(PCH_LPC_DEV, 0x82, 0x3f0f);
+ pci_write_config32(PCH_LPC_DEV, 0x84, 0x000c0681);
+ pci_write_config32(PCH_LPC_DEV, 0x88, 0x000c1641);
+ pci_write_config32(PCH_LPC_DEV, 0x8c, 0x001c0301);
+ pci_write_config32(PCH_LPC_DEV, 0x90, 0x00fc0701);
+ pci_write_config16(PCH_LPC_DEV, 0x80, 0x0070);
+}
+
+void mainboard_rcba_config(void)
+{
+}
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+ { 1, 0, 0 },
+ { 1, 0, 1 },
+ { 1, 0, 2 },
+ { 1, 0, 3 },
+ { 1, 0, -1 },
+ { 1, 0, -1 },
+ { 1, 0, -1 },
+ { 1, 0, -1 },
+ { 1, 0, -1 },
+ { 1, 0, -1 },
+ { 1, 0, -1 },
+ { 1, 0, -1 },
+ { 1, 0, -1 },
+ { 1, 0, -1 },
+};
+
+void mainboard_early_init(int s3resume)
+{
+}
+
+void mainboard_config_superio(void)
+{
+}
+
+// FIXME
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+{
+ void *spd_file;
+ size_t spd_file_len = 0;
+ spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,
+ &spd_file_len);
+ if (spd_file && spd_file_len >= 128) {
+ memcpy(&spd[0], spd_file, 128);
+ memcpy(&spd[2], spd_file, 128);
+ }
+}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ica03aba442493c0d369a3d360ad569ddc16954df
Gerrit-Change-Number: 32673
Gerrit-PatchSet: 1
Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.com>
Gerrit-MessageType: newchange
2 months, 4 weeks
- 5
- 37
Change in ...coreboot[master]: Documentation/security/vboot: Add logic to verify stage/blob using VB...
by Amol N Sukerkar (Code Review)
Amol N Sukerkar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32159
Change subject: Documentation/security/vboot: Add logic to verify stage/blob using VBOOT 2.1 library
......................................................................
Documentation/security/vboot: Add logic to verify stage/blob using
VBOOT 2.1 library
Added documentation to explain the logic that makes use of VBOOT 2.1 library to
verify Coreboot stages/blobs.
Signed-off-by: Sukerkar, Amol N <amol.n.sukerkar(a)intel.com>
Change-Id: I1eb174bb4f4d84eb8f6befdce18421b6b85ccc02
---
M Documentation/security/index.md
A Documentation/security/vboot/flash_partition.png
A Documentation/security/vboot/vboot_21_logic.png
A Documentation/security/vboot/vboot_flow_20.png
A Documentation/security/vboot/vboot_flow_21.png
A Documentation/security/vboot/verified_boot_21.md
6 files changed, 115 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/32159/1
diff --git a/Documentation/security/index.md b/Documentation/security/index.md
index 89db42e..aebfc82 100644
--- a/Documentation/security/index.md
+++ b/Documentation/security/index.md
@@ -5,3 +5,4 @@
## Vendor
- [Measured Boot](vboot/measured_boot.md)
+- [Verified Boot with VBOOT 2.1](vboot/verified_boot_21.md)
diff --git a/Documentation/security/vboot/flash_partition.png b/Documentation/security/vboot/flash_partition.png
new file mode 100644
index 0000000..91e459b
--- /dev/null
+++ b/Documentation/security/vboot/flash_partition.png
Binary files differ
diff --git a/Documentation/security/vboot/vboot_21_logic.png b/Documentation/security/vboot/vboot_21_logic.png
new file mode 100644
index 0000000..d32e99e
--- /dev/null
+++ b/Documentation/security/vboot/vboot_21_logic.png
Binary files differ
diff --git a/Documentation/security/vboot/vboot_flow_20.png b/Documentation/security/vboot/vboot_flow_20.png
new file mode 100644
index 0000000..fce4c5d
--- /dev/null
+++ b/Documentation/security/vboot/vboot_flow_20.png
Binary files differ
diff --git a/Documentation/security/vboot/vboot_flow_21.png b/Documentation/security/vboot/vboot_flow_21.png
new file mode 100644
index 0000000..24859fe
--- /dev/null
+++ b/Documentation/security/vboot/vboot_flow_21.png
Binary files differ
diff --git a/Documentation/security/vboot/verified_boot_21.md b/Documentation/security/vboot/verified_boot_21.md
new file mode 100644
index 0000000..15253b3
--- /dev/null
+++ b/Documentation/security/vboot/verified_boot_21.md
@@ -0,0 +1,114 @@
+# Enabling Intel BootGuard Support in Coreboot
+
+## Introduction
+
+One of the primary and key requirement for Intel customers is to enable Secure
+Boot in their platform where root of trust resides in the hardware and is
+immutable. While the obvious choice when it comes to hardware root of trust is
+Intel Bootguard for IA platforms, the mechanism that extends the chain
+of trust from hardware to bootloader, to payload/OS loader and eventually to the
+OS is currently not implemented in Coreboot mainly due to licensing constraints.
+This document describes the mechanism implemented in Coreboot using Google VBOOT
+libraries version 2.1 that makes use of Intel BootGuard technology as Root of
+Trust and extends the chain of trust to Coreboot which in turn extends it to the
+payload. Note: UEFI payload will use secure boot mechanism to verify and launch
+OS but that is beyond the scope of this document and will not be covered here.
+More details about VBOOT support in Coreboot are available at
+https://www.coreboot.org/git-docs/Intel/vboot.html.
+
+
+## Intel BootGuard Technology
+
+Intel BootGuard is a platform boot integrity
+protection technology. It allows initial stage of bootloader to be verified (and
+measured in TPM) by a piece of firmware (ACM) which itself is verified by Intel
+CPU microcode. A high level summary of the steps required to enable Intel
+BootGuard are: 1. Use Intel FSP-T with Coreboot bootloader. It contains the
+logic of correctly handling BtGuard enabled state. 2. Integrate ACM
+(Authenticated Code module) binary in bootloader image. 3. Generate BtGuard Key
+Manifest(BtG KM) and BtGuard Boot PolicyManifest(BtG BPM) and embed them in
+bootloader image. a. BtG KM contains the hash of the key used for signing BtG
+BPM. BtG KM is signed by the key whose hash is embedded in field-programmable
+fuses. b. BtG BPM contains the hash of initial stage of boot loader. It also
+stores other policies related to Intel TXT, BtG DMA protection etc. 4. Add
+entries for CPU microcode patch, ACM, BtG KM and BtG BPM in FIT table. 5.
+Update BootGuard related field-programmable fuses on the test platform.
+
+
+## VBOOT in Coreboot
+
+The current implementation of VBOOT tool support and logic
+in Coreboot is at version 2.0. The architecture, design and usage of this
+feature has been described here,
+https://www.coreboot.org/git-docs/Intel/vboot.html.
+
+### VBOOT 2.0 in Coreboot (Currently available)
+
+As described in the location mentioned above, the VBOOT 2.0 verified boot logic
+flow works as follows. Upon boot, verstage attempts to verify the read-write
+section A. It gets the public root key from GBB area and verifies the VBLOCK
+area in read-write section A. If the verification is successful, then verstage
+instructs Coreboot to boot rest of the firmware in read-write section A
+(romstage, postcar, ramstage and payload). If the verification fails, then,
+VBOOT falls back on read-only area to boot.
+The flow chart below shows this flow:
+
+**VBOOT 2.0 Verification Flow in Coreboot**
+![VBOOT_20_Flow_in_Coreboot][VBOOT_Flow_20]
+
+[VBOOT_Flow_20]: vboot_flow_20.png
+
+While this design implements verified boot to a certain extent, it does not take
+into account a few use-cases and concerns some Intel customers run into. A
+couple of them are as listed below,
+- Some hardware designs cannot support ‘read-only’ flash region as Root of Trust
+ and therefore prefer Intel BootGuard technology as RoT for verified boot
+mechanism.
+- In some use-cases, some of the firmware components may come from different
+ media, for instance, customer could boot payload from USB thumb drive instead
+of SPI flash. In that case, the entire read-write section will not have all the
+firmware components. There needs to be a mechanism to verify payload along with
+other components.
+- In exisiting implementation, all the firmware components in the boot chain are
+ verified in verstage. This may result in a TOCTOU attack where right after the
+verification phase, some firmware stages/components (such as payload, FSP, etc.)
+can be swapped with malware. To extend the vboot security model, the mechanism
+described below is proposed where the root of trust Bootguard begins by
+verifying the IBB and the chain of trust is extended only to the next
+stage/component at every verification pass. For instance, once Bootguard
+verifies IBB which contains verstage, romstage and postcar), postcar then uses
+the VBOOT mechanism to verify ramstage. Once ramstage is loaded into DRAM,
+ramstage in turn will verify FSP and payload.
+
+### Proposed Changes using VBOOT2.1 Libraries
+
+The proposed changes are described as follows. Upon power on of the device,
+Intel Bootguard attempts to verify IBB. IBB in this case, replaces the read-only
+portion of the flash map and contains bootblock, verstage, romstage and postcar
+stage. If the verification is successful, Intel Bootguard launches IBB and the
+system boots until postcar stage. In postcar stage, GBB is extracted and GBB
+verified the VBLOCK. Once VBLOCK is verified, postcar stage extracts the
+ramstage hash from VBLOCK and verifies the ramstage after it has been loaded
+into DRAM. This is done to ensure maximum security. Once ramstage is verified,
+ramstage is launched. At this point, ramstage extracts the hash of FSPS, DSDT
+ACPI table and payload in that order, and verifies and launches them
+sequentially. At any point, if the verification fails, the system boot will
+halt.
+
+**Stage/Blob Verification using VBOOT2.1 Library**
+![VBOOT_Stage_Blob_Verification][VBOOT_Flow_21]
+
+[VBOOT_Flow_21]: vboot_flow_21.png
+
+### Flash Partition and Code Flow in Coreboot
+
+**Flash Partition for Verification using VBOOT 2.1 Library**
+![VBOOT_Verification_2_1_Flash][Flash_Partition]
+
+[Flash_Partition]: flash_partition.png
+
+**Verification Logic using VBOOT 2.1 Library**
+![VBOOT_Verification_2_1_Logic][vboot_21_logic]
+
+[vboot_21_logic]: vboot_21_logic.png
+
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I1eb174bb4f4d84eb8f6befdce18421b6b85ccc02
Gerrit-Change-Number: 32159
Gerrit-PatchSet: 1
Gerrit-Owner: Amol N Sukerkar <amol.n.sukerkar(a)intel.com>
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3 months
- 5
- 12
Change in ...coreboot[master]: Add KASAN stubs to coreboot.
by Abdullah Zafar (Code Review)
Abdullah Zafar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32231
Change subject: Add KASAN stubs to coreboot.
......................................................................
Add KASAN stubs to coreboot.
Add option in Kconfig to compile with KASAN. Modify src/lib/Makefile.inc to enable gcc KASAN.
Remove lint errors and warnings from kasan.c.
Signed-off-by: 11abdullah11 <abdullahzafar4876(a)yahoo.com>
Changes to be committed:
modified: src/Kconfig
modified: src/lib/Makefile.inc
new file: src/lib/kasan.c
Change-Id: Id13970514e37dfffb751391fb3e7e6b53ccc7577
---
M src/Kconfig
M src/lib/Makefile.inc
A src/lib/kasan.c
3 files changed, 45 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/32231/1
diff --git a/src/Kconfig b/src/Kconfig
index 62b3818..96e746e 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -219,6 +219,15 @@
coverage information in CBMEM for extraction from user space.
If unsure, say N.
+config KASAN
+ bool "Kernel Address sanitizer support"
+ default y
+ help
+ Instrument the code with checks for UAF and OOB erros. If unsure,
+ say N because it adds a small performance penalty and may abort
+ on code that happens to work in spite of the UB.
+
+
config UBSAN
bool "Undefined behavior sanitizer support"
default n
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 1350152..88afaaa 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -19,6 +19,12 @@
CFLAGS_ramstage += -fsanitize=undefined
endif
+ifeq ($(CONFIG_KASAN),y)
+ramstage-y += kasan.c
+CFLAGS_ramstage += -fsanitize=kernel-address
+endif
+
+
decompressor-y += decompressor.c
$(call src-to-obj,decompressor,$(dir)/decompressor.c): $(objcbfs)/bootblock.lz4
$(call src-to-obj,decompressor,$(dir)/decompressor.c): CCACHE_EXTRAFILES=$(objcbfs)/bootblock.lz4
@@ -83,7 +89,7 @@
romstage-y += memrange.c
romstage-$(CONFIG_PRIMITIVE_MEMTEST) += primitive_memtest.c
ramstage-$(CONFIG_PRIMITIVE_MEMTEST) += primitive_memtest.c
-romstage-y += ramtest.c
+romstage-$(CONFIG_CACHE_AS_RAM) += ramtest.c
romstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c
ramstage-y += region_file.c
romstage-y += region_file.c
diff --git a/src/lib/kasan.c b/src/lib/kasan.c
new file mode 100644
index 0000000..3f482e9
--- /dev/null
+++ b/src/lib/kasan.c
@@ -0,0 +1,29 @@
+#include <stddef.h>
+
+/*
+ *Empty stubs for required by gcc to add compiler code
+ */
+void __asan_handle_no_return(void);
+void __asan_load1_noabort(unsigned long addr);
+void __asan_store1_noabort(unsigned long addr);
+void __asan_load2_noabort(unsigned long addr);
+void __asan_store2_noabort(unsigned long addr);
+void __asan_load4_noabort(unsigned long addr);
+void __asan_store4_noabort(unsigned long addr);
+void __asan_load8_noabort(unsigned long addr);
+void __asan_store8_noabort(unsigned long addr);
+void __asan_loadN_noabort(unsigned long addr, size_t x);
+void __asan_storeN_noabort(unsigned long addr, size_t x);
+
+
+void __asan_handle_no_return(void) { }
+void __asan_load1_noabort(unsigned long addr) { }
+void __asan_store1_noabort(unsigned long addr) { }
+void __asan_load2_noabort(unsigned long addr) { }
+void __asan_store2_noabort(unsigned long addr) { }
+void __asan_load4_noabort(unsigned long addr) { }
+void __asan_store4_noabort(unsigned long addr) { }
+void __asan_store8_noabort(unsigned long addr) { }
+void __asan_load8_noabort(unsigned long addr) { }
+void __asan_loadN_noabort(unsigned long addr, size_t i) { }
+void __asan_storeN_noabort(unsigned long addr, size_t i) { }
--
To view, visit https://review.coreboot.org/c/coreboot/+/32231
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Id13970514e37dfffb751391fb3e7e6b53ccc7577
Gerrit-Change-Number: 32231
Gerrit-PatchSet: 1
Gerrit-Owner: Abdullah Zafar <abdullahzafar4876(a)yahoo.com>
Gerrit-MessageType: newchange
3 months, 3 weeks
- 5
- 18
Change in ...coreboot[master]: WIP: temp for dispaly conflick
by jitao shi (Code Review)
jitao shi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33106
Change subject: WIP: temp for dispaly conflick
......................................................................
WIP: temp for dispaly conflick
Temp
squlash patches
google/krane: Add Panel TV101WUM-NL6 support.
google/kukui: Elaborate panel support for Kukui family boards.
google/kukui: Enable config for coreboot display
mediatek/mt8183: add dsi driver for mt8183
google/kukui: Enable display on internal panel
mediatek/mt8183: Add display driver
Change-Id: I09d127ab491bca98f3a9c9b7d4ad4b09674c963d
---
D 3rdparty/blobs
M src/mainboard/google/kukui/Kconfig
M src/mainboard/google/kukui/Makefile.inc
A src/mainboard/google/kukui/display.c
A src/mainboard/google/kukui/display.h
M src/mainboard/google/kukui/mainboard.c
A src/mainboard/google/kukui/panel_krane.c
A src/mainboard/google/kukui/panel_kukui.c
M src/soc/mediatek/mt8183/Makefile.inc
A src/soc/mediatek/mt8183/ddp.c
A src/soc/mediatek/mt8183/dsi.c
M src/soc/mediatek/mt8183/include/soc/addressmap.h
A src/soc/mediatek/mt8183/include/soc/ddp.h
A src/soc/mediatek/mt8183/include/soc/dsi.h
14 files changed, 2,372 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/33106/1
diff --git a/3rdparty/blobs b/3rdparty/blobs
deleted file mode 160000
index ca6cfcd..0000000
--- a/3rdparty/blobs
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit ca6cfcdbe1cdeb38c2622ee2e5236cc4657e3377
diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig
index 6831d1e..5893722 100644
--- a/src/mainboard/google/kukui/Kconfig
+++ b/src/mainboard/google/kukui/Kconfig
@@ -37,6 +37,9 @@
select EC_GOOGLE_CHROMEEC_SPI
select MAINBOARD_HAS_SPI_TPM_CR50 if VBOOT
select MAINBOARD_HAS_TPM2 if VBOOT
+ select MAINBOARD_HAS_NATIVE_VGA_INIT
+ select MAINBOARD_FORCE_NATIVE_VGA_INIT
+ select HAVE_LINEAR_FRAMEBUFFER
config MAINBOARD_DIR
string
diff --git a/src/mainboard/google/kukui/Makefile.inc b/src/mainboard/google/kukui/Makefile.inc
index a0556c1..8a023a5 100644
--- a/src/mainboard/google/kukui/Makefile.inc
+++ b/src/mainboard/google/kukui/Makefile.inc
@@ -22,6 +22,9 @@
ramstage-y += boardid.c
ramstage-y += chromeos.c
+ramstage-y += display.c
+ramstage-$(CONFIG_BOARD_GOOGLE_KUKUI) += panel_kukui.c
+ramstage-$(CONFIG_BOARD_GOOGLE_KRANE) += panel_krane.c
ramstage-y += mainboard.c
ramstage-y += memlayout.ld
ramstage-y += reset.c
diff --git a/src/mainboard/google/kukui/display.c b/src/mainboard/google/kukui/display.c
new file mode 100644
index 0000000..c7f7f91
--- /dev/null
+++ b/src/mainboard/google/kukui/display.c
@@ -0,0 +1,127 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Huaqin Telecom Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <delay.h>
+#include <device/device.h>
+#include <edid.h>
+#include <gpio.h>
+#include <soc/auxadc.h>
+#include <soc/ddp.h>
+#include <soc/dsi.h>
+#include <soc/gpio.h>
+#include <boardid.h>
+
+#include "display.h"
+#include "gpio.h"
+
+static void _display_startup(struct edid *edid,
+ struct lcm_init_table *init_table,
+ u32 init_table_size)
+{
+ int ret = 0;
+ u32 mipi_dsi_flags;
+
+ if ((edid == NULL) || (init_table == NULL)) {
+ printk(BIOS_ERR, "%s: wrong parameters\n", __func__);
+ return;
+ }
+
+ mipi_dsi_flags = MIPI_DSI_MODE_VIDEO |
+ MIPI_DSI_MODE_VIDEO_SYNC_PULSE | MIPI_DSI_MODE_LPM;
+
+ edid_set_framebuffer_bits_per_pixel(edid, 32, 0);
+
+ mtk_ddp_init();
+ ret = mtk_dsi_init(mipi_dsi_flags, MIPI_DSI_FMT_RGB888, 4,
+ false, edid, init_table, init_table_size);
+
+ if (ret < 0) {
+ printk(BIOS_ERR, "dsi init fail\n");
+ return;
+ }
+
+ mtk_ddp_mode_set(edid);
+
+ set_vbe_mode_info_valid(edid, (uintptr_t)0);
+}
+
+static struct edid *get_edid(struct board_display_intf *intf)
+{
+ struct panel_info *info = intf->cur_panel_info;
+
+ if (info)
+ return info->edid;
+ return NULL;
+}
+
+static struct lcm_init_table *get_panel_init_table(struct board_display_intf
+ *intf, u32 *table_size)
+{
+ struct panel_info *info = intf->cur_panel_info;
+
+ if (info) {
+ *table_size = info->table_size;
+ return info->init_table;
+ }
+
+ *table_size = 0;
+ return NULL;
+}
+
+static const char *get_panel_name(struct board_display_intf *intf)
+{
+ struct panel_info *info = intf->cur_panel_info;
+
+ if (info)
+ return info->panel_name;
+ return NULL;
+}
+
+/* Exported Functions */
+
+struct board_display_intf *get_current_display_intf(void)
+{
+ return &panel_display_intf;
+}
+
+int update_panel_info(struct board_display_intf *intf)
+{
+ int i;
+ union panel_id id = intf->get_panel_id(intf);
+
+ if (intf->is_panel_id_valid(id)) {
+ for (i = 0; i < intf->all_panel_info_size; ++i) {
+ if (id.value == intf->all_panel_info[i].disp_id.value) {
+ intf->cur_panel_info = &intf->all_panel_info[i];
+ return 0;
+ }
+ }
+ }
+ return -1;
+}
+
+void display_startup(struct board_display_intf *intf)
+{
+ struct edid *edid;
+ u32 init_table_size;
+ struct lcm_init_table *init_table;
+
+ edid = get_edid(intf);
+ init_table = get_panel_init_table(intf, &init_table_size);
+ printk(BIOS_INFO, "%s: name:%s init_table_size:%d\n",
+ __func__, get_panel_name(intf), init_table_size);
+ _display_startup(edid, init_table, init_table_size);
+}
diff --git a/src/mainboard/google/kukui/display.h b/src/mainboard/google/kukui/display.h
new file mode 100644
index 0000000..d7b8bd9
--- /dev/null
+++ b/src/mainboard/google/kukui/display.h
@@ -0,0 +1,99 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Huaqin Telecom Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MAINBOARD_GOOGLE_DISPLAY_H__
+#define __MAINBOARD_GOOGLE_DISPLAY_H__
+
+#include <soc/dsi.h>
+#include <soc/gpio.h>
+
+#define MAKE_AS_A_STRING(arg) #arg
+
+enum kukui_panel_id {
+ PANEL_KUKUI_FIRST = 0,
+ PANEL_KUKUI_INNOLUX = 0,
+ PANEL_KUKUI_P097PFG_SSD2858,
+ PANEL_KUKUI_UNKNOWN,
+ PANEL_KUKUI_COUNT,
+ PANEL_KUKUI_UNINITIALIZED
+};
+
+enum krane_panel_id {
+ PANEL_KRANE_FIRST = 0,
+ PANEL_KRANE_BOE_TV101WUM_NL6,
+ PANEL_KRANE_UNKNOWN,
+ PANEL_KRANE_COUNT,
+ PANEL_KRANE_UNINITIALIZED
+};
+
+
+union panel_id {
+ enum kukui_panel_id kukui_panel;
+ enum krane_panel_id krane_panel;
+ int value;
+};
+
+struct panel_info {
+ union panel_id disp_id; /* the ID for panel */
+ const char *panel_name; /* display panel name */
+ int voltage; /* voltage of LCM_ID */
+ struct edid *edid; /* edid info of this panel */
+ struct lcm_init_table *init_table; /* init command table */
+ u32 table_size; /* init command table size */
+};
+
+#define PANEL(_panel_id, _voltage, _edid, _init_table) \
+ { \
+ .disp_id = {_panel_id},\
+ .panel_name = MAKE_AS_A_STRING(_panel_id),\
+ .voltage = _voltage,\
+ .edid = &_edid,\
+ .init_table = _init_table,\
+ .table_size = ARRAY_SIZE(_init_table)} \
+
+
+struct board_display_intf {
+ const char *board; /* board name */
+ struct panel_info *all_panel_info; /* all supported panel info */
+ u32 all_panel_info_size; /* num of supported panel */
+ /*
+ * Runtime member
+ */
+ struct panel_info *cur_panel_info; /* detected panel info */
+ /*
+ * board related functions
+ */
+
+ union panel_id (*get_panel_id)(struct board_display_intf *intf);
+ bool (*is_panel_id_valid)(union panel_id id);
+ int (*backlight)(struct board_display_intf *intf);
+ int (*power)(struct board_display_intf *intf);
+};
+
+/*
+ * Exported functions
+ */
+
+struct board_display_intf *get_current_display_intf(void);
+int update_panel_info(struct board_display_intf *intf);
+void display_startup(struct board_display_intf *intf);
+
+
+/*
+ * Panel Interface for boards
+ */
+extern struct board_display_intf panel_display_intf;
+
+#endif
diff --git a/src/mainboard/google/kukui/mainboard.c b/src/mainboard/google/kukui/mainboard.c
index 7a31909..4e7c20b 100644
--- a/src/mainboard/google/kukui/mainboard.c
+++ b/src/mainboard/google/kukui/mainboard.c
@@ -13,8 +13,17 @@
* GNU General Public License for more details.
*/
+#include <boardid.h>
+#include <bootmode.h>
+#include <console/console.h>
+#include <delay.h>
#include <device/device.h>
#include <soc/bl31_plat_params.h>
+#include "display.h"
+#include <edid.h>
+#include <gpio.h>
+#include <soc/ddp.h>
+#include <soc/dsi.h>
#include <soc/gpio.h>
#include <soc/mmu_operations.h>
#include <soc/mtcmos.h>
@@ -70,6 +79,28 @@
static void mainboard_init(struct device *dev)
{
+ struct board_display_intf *cur_disp_intf = NULL;
+
+ if (display_init_required()) {
+ printk(BIOS_INFO, "Starting display init.\n");
+
+ cur_disp_intf = get_current_display_intf();
+ if (cur_disp_intf && !update_panel_info(cur_disp_intf)) {
+ mtcmos_display_power_on();
+ mtcmos_protect_display_bus();
+
+ cur_disp_intf->backlight(cur_disp_intf);
+ cur_disp_intf->power(cur_disp_intf);
+ display_startup(cur_disp_intf);
+ } else {
+ printk(BIOS_ERR,
+ "%s: Can't find correct display interface\n",
+ __func__);
+ }
+
+ } else
+ printk(BIOS_ERR, "Skipping display init.\n");
+
configure_emmc();
configure_usb();
configure_audio();
diff --git a/src/mainboard/google/kukui/panel_krane.c b/src/mainboard/google/kukui/panel_krane.c
new file mode 100644
index 0000000..b6fa9a5
--- /dev/null
+++ b/src/mainboard/google/kukui/panel_krane.c
@@ -0,0 +1,409 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Huaqin Telecom Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <delay.h>
+#include <device/device.h>
+#include <edid.h>
+#include <gpio.h>
+#include <soc/auxadc.h>
+#include <soc/ddp.h>
+#include <soc/dsi.h>
+#include <soc/gpio.h>
+#include <boardid.h>
+
+#include "display.h"
+#include "gpio.h"
+
+static struct edid krane_boe_tv101wum_nl6_edid = {
+ .panel_bits_per_color = 8,
+ .panel_bits_per_pixel = 24,
+ .mode = {
+ .name = "1200x1920@60Hz",
+ .pixel_clock = 159425,
+ .lvds_dual_channel = 0,
+ .refresh = 60,
+ .ha = 1200, .hbl = 164, .hso = 100, .hspw = 24, .hborder = 0,
+ .va = 1920, .vbl = 28, .vso = 10, .vspw = 4, .vborder = 0,
+ .phsync = '-', .pvsync = '-',
+ .x_mm = 135, .y_mm = 216,
+ },
+};
+
+struct lcm_init_table boe_tv101wum_nl6_init_cmd[] = {
+ {INIT_DCS_CMD, 1, { 0x10 } },
+ {DELAY_CMD, 34, {} },
+ {INIT_DCS_CMD, 2, { 0xB0, 0x05 } },
+ {INIT_DCS_CMD, 2, { 0xB1, 0xE5 } },
+ {INIT_DCS_CMD, 2, { 0xB3, 0x52 } },
+ {INIT_DCS_CMD, 2, { 0xB0, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xB3, 0x88 } },
+ {INIT_DCS_CMD, 2, { 0xB0, 0x04 } },
+ {INIT_DCS_CMD, 2, { 0xB8, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xB0, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xB6, 0x03 } },
+ {INIT_DCS_CMD, 2, { 0xBA, 0x8B } },
+ {INIT_DCS_CMD, 2, { 0xBF, 0x1A } },
+ {INIT_DCS_CMD, 2, { 0xC0, 0x0F } },
+ {INIT_DCS_CMD, 2, { 0xC2, 0x0C } },
+ {INIT_DCS_CMD, 2, { 0xC3, 0x02 } },
+ {INIT_DCS_CMD, 2, { 0xC4, 0x0C } },
+ {INIT_DCS_CMD, 2, { 0xC5, 0x02 } },
+ {INIT_DCS_CMD, 2, { 0xB0, 0x01 } },
+ {INIT_DCS_CMD, 2, { 0xE0, 0x26 } },
+ {INIT_DCS_CMD, 2, { 0xE1, 0x26 } },
+ {INIT_DCS_CMD, 2, { 0xDC, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xDD, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xCC, 0x26 } },
+ {INIT_DCS_CMD, 2, { 0xCD, 0x26 } },
+ {INIT_DCS_CMD, 2, { 0xC8, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xC9, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xD2, 0x03 } },
+ {INIT_DCS_CMD, 2, { 0xD3, 0x03 } },
+ {INIT_DCS_CMD, 2, { 0xE6, 0x04 } },
+ {INIT_DCS_CMD, 2, { 0xE7, 0x04 } },
+ {INIT_DCS_CMD, 2, { 0xC4, 0x09 } },
+ {INIT_DCS_CMD, 2, { 0xC5, 0x09 } },
+ {INIT_DCS_CMD, 2, { 0xD8, 0x0A } },
+ {INIT_DCS_CMD, 2, { 0xD9, 0x0A } },
+ {INIT_DCS_CMD, 2, { 0xC2, 0x0B } },
+ {INIT_DCS_CMD, 2, { 0xC3, 0x0B } },
+ {INIT_DCS_CMD, 2, { 0xD6, 0x0C } },
+ {INIT_DCS_CMD, 2, { 0xD7, 0x0C } },
+ {INIT_DCS_CMD, 2, { 0xC0, 0x05 } },
+ {INIT_DCS_CMD, 2, { 0xC1, 0x05 } },
+ {INIT_DCS_CMD, 2, { 0xD4, 0x06 } },
+ {INIT_DCS_CMD, 2, { 0xD5, 0x06 } },
+ {INIT_DCS_CMD, 2, { 0xCA, 0x07 } },
+ {INIT_DCS_CMD, 2, { 0xCB, 0x07 } },
+ {INIT_DCS_CMD, 2, { 0xDE, 0x08 } },
+ {INIT_DCS_CMD, 2, { 0xDF, 0x08 } },
+ {INIT_DCS_CMD, 2, { 0xB0, 0x02 } },
+ {INIT_DCS_CMD, 2, { 0xC0, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xC1, 0x0D } },
+ {INIT_DCS_CMD, 2, { 0xC2, 0x17 } },
+ {INIT_DCS_CMD, 2, { 0xC3, 0x26 } },
+ {INIT_DCS_CMD, 2, { 0xC4, 0x31 } },
+ {INIT_DCS_CMD, 2, { 0xC5, 0x1C } },
+ {INIT_DCS_CMD, 2, { 0xC6, 0x2C } },
+ {INIT_DCS_CMD, 2, { 0xC7, 0x33 } },
+ {INIT_DCS_CMD, 2, { 0xC8, 0x31 } },
+ {INIT_DCS_CMD, 2, { 0xC9, 0x37 } },
+ {INIT_DCS_CMD, 2, { 0xCA, 0x37 } },
+ {INIT_DCS_CMD, 2, { 0xCB, 0x37 } },
+ {INIT_DCS_CMD, 2, { 0xCC, 0x39 } },
+ {INIT_DCS_CMD, 2, { 0xCD, 0x2E } },
+ {INIT_DCS_CMD, 2, { 0xCE, 0x2F } },
+ {INIT_DCS_CMD, 2, { 0xCF, 0x2F } },
+ {INIT_DCS_CMD, 2, { 0xD0, 0x07 } },
+ {INIT_DCS_CMD, 2, { 0xD2, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xD3, 0x0D } },
+ {INIT_DCS_CMD, 2, { 0xD4, 0x17 } },
+ {INIT_DCS_CMD, 2, { 0xD5, 0x26 } },
+ {INIT_DCS_CMD, 2, { 0xD6, 0x31 } },
+ {INIT_DCS_CMD, 2, { 0xD7, 0x3F } },
+ {INIT_DCS_CMD, 2, { 0xD8, 0x3F } },
+ {INIT_DCS_CMD, 2, { 0xD9, 0x3F } },
+ {INIT_DCS_CMD, 2, { 0xDA, 0x3F } },
+ {INIT_DCS_CMD, 2, { 0xDB, 0x37 } },
+ {INIT_DCS_CMD, 2, { 0xDC, 0x37 } },
+ {INIT_DCS_CMD, 2, { 0xDD, 0x37 } },
+ {INIT_DCS_CMD, 2, { 0xDE, 0x39 } },
+ {INIT_DCS_CMD, 2, { 0xDF, 0x2E } },
+ {INIT_DCS_CMD, 2, { 0xE0, 0x2F } },
+ {INIT_DCS_CMD, 2, { 0xE1, 0x2F } },
+ {INIT_DCS_CMD, 2, { 0xE2, 0x07 } },
+ {INIT_DCS_CMD, 2, { 0xB0, 0x03 } },
+ {INIT_DCS_CMD, 2, { 0xC8, 0x0B } },
+ {INIT_DCS_CMD, 2, { 0xC9, 0x07 } },
+ {INIT_DCS_CMD, 2, { 0xC3, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xE7, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xC5, 0x2A } },
+ {INIT_DCS_CMD, 2, { 0xDE, 0x2A } },
+ {INIT_DCS_CMD, 2, { 0xCA, 0x43 } },
+ {INIT_DCS_CMD, 2, { 0xC9, 0x07 } },
+ {INIT_DCS_CMD, 2, { 0xE4, 0xC0 } },
+ {INIT_DCS_CMD, 2, { 0xE5, 0x0D } },
+ {INIT_DCS_CMD, 2, { 0xCB, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xB0, 0x06 } },
+ {INIT_DCS_CMD, 2, { 0xB8, 0xA5 } },
+ {INIT_DCS_CMD, 2, { 0xC0, 0xA5 } },
+ {INIT_DCS_CMD, 2, { 0xC7, 0x0F } },
+ {INIT_DCS_CMD, 2, { 0xD5, 0x32 } },
+ {INIT_DCS_CMD, 2, { 0xB8, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xC0, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xBC, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xB0, 0x07 } },
+ {INIT_DCS_CMD, 2, { 0xB1, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xB2, 0x02 } },
+ {INIT_DCS_CMD, 2, { 0xB3, 0x0F } },
+ {INIT_DCS_CMD, 2, { 0xB4, 0x25 } },
+ {INIT_DCS_CMD, 2, { 0xB5, 0x39 } },
+ {INIT_DCS_CMD, 2, { 0xB6, 0x4E } },
+ {INIT_DCS_CMD, 2, { 0xB7, 0x72 } },
+ {INIT_DCS_CMD, 2, { 0xB8, 0x97 } },
+ {INIT_DCS_CMD, 2, { 0xB9, 0xDC } },
+ {INIT_DCS_CMD, 2, { 0xBA, 0x22 } },
+ {INIT_DCS_CMD, 2, { 0xBB, 0xA4 } },
+ {INIT_DCS_CMD, 2, { 0xBC, 0x2B } },
+ {INIT_DCS_CMD, 2, { 0xBD, 0x2F } },
+ {INIT_DCS_CMD, 2, { 0xBE, 0xA9 } },
+ {INIT_DCS_CMD, 2, { 0xBF, 0x25 } },
+ {INIT_DCS_CMD, 2, { 0xC0, 0x61 } },
+ {INIT_DCS_CMD, 2, { 0xC1, 0x97 } },
+ {INIT_DCS_CMD, 2, { 0xC2, 0xB2 } },
+ {INIT_DCS_CMD, 2, { 0xC3, 0xCD } },
+ {INIT_DCS_CMD, 2, { 0xC4, 0xD9 } },
+ {INIT_DCS_CMD, 2, { 0xC5, 0xE7 } },
+ {INIT_DCS_CMD, 2, { 0xC6, 0xF4 } },
+ {INIT_DCS_CMD, 2, { 0xC7, 0xFA } },
+ {INIT_DCS_CMD, 2, { 0xC8, 0xFC } },
+ {INIT_DCS_CMD, 2, { 0xC9, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xCA, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xCB, 0x16 } },
+ {INIT_DCS_CMD, 2, { 0xCC, 0xAF } },
+ {INIT_DCS_CMD, 2, { 0xCD, 0xFF } },
+ {INIT_DCS_CMD, 2, { 0xCE, 0xFF } },
+ {INIT_DCS_CMD, 2, { 0xB0, 0x08 } },
+ {INIT_DCS_CMD, 2, { 0xB1, 0x04 } },
+ {INIT_DCS_CMD, 2, { 0xB2, 0x05 } },
+ {INIT_DCS_CMD, 2, { 0xB3, 0x11 } },
+ {INIT_DCS_CMD, 2, { 0xB4, 0x24 } },
+ {INIT_DCS_CMD, 2, { 0xB5, 0x39 } },
+ {INIT_DCS_CMD, 2, { 0xB6, 0x4F } },
+ {INIT_DCS_CMD, 2, { 0xB7, 0x72 } },
+ {INIT_DCS_CMD, 2, { 0xB8, 0x98 } },
+ {INIT_DCS_CMD, 2, { 0xB9, 0xDC } },
+ {INIT_DCS_CMD, 2, { 0xBA, 0x23 } },
+ {INIT_DCS_CMD, 2, { 0xBB, 0xA6 } },
+ {INIT_DCS_CMD, 2, { 0xBC, 0x2C } },
+ {INIT_DCS_CMD, 2, { 0xBD, 0x30 } },
+ {INIT_DCS_CMD, 2, { 0xBE, 0xAA } },
+ {INIT_DCS_CMD, 2, { 0xBF, 0x26 } },
+ {INIT_DCS_CMD, 2, { 0xC0, 0x62 } },
+ {INIT_DCS_CMD, 2, { 0xC1, 0x9B } },
+ {INIT_DCS_CMD, 2, { 0xC2, 0xB5 } },
+ {INIT_DCS_CMD, 2, { 0xC3, 0xCF } },
+ {INIT_DCS_CMD, 2, { 0xC4, 0xDB } },
+ {INIT_DCS_CMD, 2, { 0xC5, 0xE8 } },
+ {INIT_DCS_CMD, 2, { 0xC6, 0xF5 } },
+ {INIT_DCS_CMD, 2, { 0xC7, 0xFA } },
+ {INIT_DCS_CMD, 2, { 0xC8, 0xFC } },
+ {INIT_DCS_CMD, 2, { 0xC9, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xCA, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xCB, 0x16 } },
+ {INIT_DCS_CMD, 2, { 0xCC, 0xAF } },
+ {INIT_DCS_CMD, 2, { 0xCD, 0xFF } },
+ {INIT_DCS_CMD, 2, { 0xCE, 0xFF } },
+ {INIT_DCS_CMD, 2, { 0xB0, 0x09 } },
+ {INIT_DCS_CMD, 2, { 0xB1, 0x04 } },
+ {INIT_DCS_CMD, 2, { 0xB2, 0x02 } },
+ {INIT_DCS_CMD, 2, { 0xB3, 0x16 } },
+ {INIT_DCS_CMD, 2, { 0xB4, 0x24 } },
+ {INIT_DCS_CMD, 2, { 0xB5, 0x3B } },
+ {INIT_DCS_CMD, 2, { 0xB6, 0x4F } },
+ {INIT_DCS_CMD, 2, { 0xB7, 0x73 } },
+ {INIT_DCS_CMD, 2, { 0xB8, 0x99 } },
+ {INIT_DCS_CMD, 2, { 0xB9, 0xE0 } },
+ {INIT_DCS_CMD, 2, { 0xBA, 0x26 } },
+ {INIT_DCS_CMD, 2, { 0xBB, 0xAD } },
+ {INIT_DCS_CMD, 2, { 0xBC, 0x36 } },
+ {INIT_DCS_CMD, 2, { 0xBD, 0x3A } },
+ {INIT_DCS_CMD, 2, { 0xBE, 0xAE } },
+ {INIT_DCS_CMD, 2, { 0xBF, 0x2A } },
+ {INIT_DCS_CMD, 2, { 0xC0, 0x66 } },
+ {INIT_DCS_CMD, 2, { 0xC1, 0x9E } },
+ {INIT_DCS_CMD, 2, { 0xC2, 0xB8 } },
+ {INIT_DCS_CMD, 2, { 0xC3, 0xD1 } },
+ {INIT_DCS_CMD, 2, { 0xC4, 0xDD } },
+ {INIT_DCS_CMD, 2, { 0xC5, 0xE9 } },
+ {INIT_DCS_CMD, 2, { 0xC6, 0xF6 } },
+ {INIT_DCS_CMD, 2, { 0xC7, 0xFA } },
+ {INIT_DCS_CMD, 2, { 0xC8, 0xFC } },
+ {INIT_DCS_CMD, 2, { 0xC9, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xCA, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xCB, 0x16 } },
+ {INIT_DCS_CMD, 2, { 0xCC, 0xAF } },
+ {INIT_DCS_CMD, 2, { 0xCD, 0xFF } },
+ {INIT_DCS_CMD, 2, { 0xCE, 0xFF } },
+ {INIT_DCS_CMD, 2, { 0xB0, 0x0A } },
+ {INIT_DCS_CMD, 2, { 0xB1, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xB2, 0x02 } },
+ {INIT_DCS_CMD, 2, { 0xB3, 0x0F } },
+ {INIT_DCS_CMD, 2, { 0xB4, 0x25 } },
+ {INIT_DCS_CMD, 2, { 0xB5, 0x39 } },
+ {INIT_DCS_CMD, 2, { 0xB6, 0x4E } },
+ {INIT_DCS_CMD, 2, { 0xB7, 0x72 } },
+ {INIT_DCS_CMD, 2, { 0xB8, 0x97 } },
+ {INIT_DCS_CMD, 2, { 0xB9, 0xDC } },
+ {INIT_DCS_CMD, 2, { 0xBA, 0x22 } },
+ {INIT_DCS_CMD, 2, { 0xBB, 0xA4 } },
+ {INIT_DCS_CMD, 2, { 0xBC, 0x2B } },
+ {INIT_DCS_CMD, 2, { 0xBD, 0x2F } },
+ {INIT_DCS_CMD, 2, { 0xBE, 0xA9 } },
+ {INIT_DCS_CMD, 2, { 0xBF, 0x25 } },
+ {INIT_DCS_CMD, 2, { 0xC0, 0x61 } },
+ {INIT_DCS_CMD, 2, { 0xC1, 0x97 } },
+ {INIT_DCS_CMD, 2, { 0xC2, 0xB2 } },
+ {INIT_DCS_CMD, 2, { 0xC3, 0xCD } },
+ {INIT_DCS_CMD, 2, { 0xC4, 0xD9 } },
+ {INIT_DCS_CMD, 2, { 0xC5, 0xE7 } },
+ {INIT_DCS_CMD, 2, { 0xC6, 0xF4 } },
+ {INIT_DCS_CMD, 2, { 0xC7, 0xFA } },
+ {INIT_DCS_CMD, 2, { 0xC8, 0xFC } },
+ {INIT_DCS_CMD, 2, { 0xC9, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xCA, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xCB, 0x16 } },
+ {INIT_DCS_CMD, 2, { 0xCC, 0xAF } },
+ {INIT_DCS_CMD, 2, { 0xCD, 0xFF } },
+ {INIT_DCS_CMD, 2, { 0xCE, 0xFF } },
+ {INIT_DCS_CMD, 2, { 0xB0, 0x0B } },
+ {INIT_DCS_CMD, 2, { 0xB1, 0x04 } },
+ {INIT_DCS_CMD, 2, { 0xB2, 0x05 } },
+ {INIT_DCS_CMD, 2, { 0xB3, 0x11 } },
+ {INIT_DCS_CMD, 2, { 0xB4, 0x24 } },
+ {INIT_DCS_CMD, 2, { 0xB5, 0x39 } },
+ {INIT_DCS_CMD, 2, { 0xB6, 0x4F } },
+ {INIT_DCS_CMD, 2, { 0xB7, 0x72 } },
+ {INIT_DCS_CMD, 2, { 0xB8, 0x98 } },
+ {INIT_DCS_CMD, 2, { 0xB9, 0xDC } },
+ {INIT_DCS_CMD, 2, { 0xBA, 0x23 } },
+ {INIT_DCS_CMD, 2, { 0xBB, 0xA6 } },
+ {INIT_DCS_CMD, 2, { 0xBC, 0x2C } },
+ {INIT_DCS_CMD, 2, { 0xBD, 0x30 } },
+ {INIT_DCS_CMD, 2, { 0xBE, 0xAA } },
+ {INIT_DCS_CMD, 2, { 0xBF, 0x26 } },
+ {INIT_DCS_CMD, 2, { 0xC0, 0x62 } },
+ {INIT_DCS_CMD, 2, { 0xC1, 0x9B } },
+ {INIT_DCS_CMD, 2, { 0xC2, 0xB5 } },
+ {INIT_DCS_CMD, 2, { 0xC3, 0xCF } },
+ {INIT_DCS_CMD, 2, { 0xC4, 0xDB } },
+ {INIT_DCS_CMD, 2, { 0xC5, 0xE8 } },
+ {INIT_DCS_CMD, 2, { 0xC6, 0xF5 } },
+ {INIT_DCS_CMD, 2, { 0xC7, 0xFA } },
+ {INIT_DCS_CMD, 2, { 0xC8, 0xFC } },
+ {INIT_DCS_CMD, 2, { 0xC9, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xCA, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xCB, 0x16 } },
+ {INIT_DCS_CMD, 2, { 0xCC, 0xAF } },
+ {INIT_DCS_CMD, 2, { 0xCD, 0xFF } },
+ {INIT_DCS_CMD, 2, { 0xCE, 0xFF } },
+ {INIT_DCS_CMD, 2, { 0xB0, 0x0C } },
+ {INIT_DCS_CMD, 2, { 0xB1, 0x04 } },
+ {INIT_DCS_CMD, 2, { 0xB2, 0x02 } },
+ {INIT_DCS_CMD, 2, { 0xB3, 0x16 } },
+ {INIT_DCS_CMD, 2, { 0xB4, 0x24 } },
+ {INIT_DCS_CMD, 2, { 0xB5, 0x3B } },
+ {INIT_DCS_CMD, 2, { 0xB6, 0x4F } },
+ {INIT_DCS_CMD, 2, { 0xB7, 0x73 } },
+ {INIT_DCS_CMD, 2, { 0xB8, 0x99 } },
+ {INIT_DCS_CMD, 2, { 0xB9, 0xE0 } },
+ {INIT_DCS_CMD, 2, { 0xBA, 0x26 } },
+ {INIT_DCS_CMD, 2, { 0xBB, 0xAD } },
+ {INIT_DCS_CMD, 2, { 0xBC, 0x36 } },
+ {INIT_DCS_CMD, 2, { 0xBD, 0x3A } },
+ {INIT_DCS_CMD, 2, { 0xBE, 0xAE } },
+ {INIT_DCS_CMD, 2, { 0xBF, 0x2A } },
+ {INIT_DCS_CMD, 2, { 0xC0, 0x66 } },
+ {INIT_DCS_CMD, 2, { 0xC1, 0x9E } },
+ {INIT_DCS_CMD, 2, { 0xC2, 0xB8 } },
+ {INIT_DCS_CMD, 2, { 0xC3, 0xD1 } },
+ {INIT_DCS_CMD, 2, { 0xC4, 0xDD } },
+ {INIT_DCS_CMD, 2, { 0xC5, 0xE9 } },
+ {INIT_DCS_CMD, 2, { 0xC6, 0xF6 } },
+ {INIT_DCS_CMD, 2, { 0xC7, 0xFA } },
+ {INIT_DCS_CMD, 2, { 0xC8, 0xFC } },
+ {INIT_DCS_CMD, 2, { 0xC9, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xCA, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xCB, 0x16 } },
+ {INIT_DCS_CMD, 2, { 0xCC, 0xAF } },
+ {INIT_DCS_CMD, 2, { 0xCD, 0xFF } },
+ {INIT_DCS_CMD, 2, { 0xCE, 0xFF } },
+ {INIT_DCS_CMD, 2, { 0xB0, 0x00 } },
+ {INIT_DCS_CMD, 2, { 0xB3, 0x08 } },
+ {INIT_DCS_CMD, 2, { 0xB0, 0x04 } },
+ {INIT_DCS_CMD, 2, { 0xB8, 0x68 } },
+ {DELAY_CMD, 10, {} },
+ {INIT_DCS_CMD, 1, { 0x11 } },
+ {DELAY_CMD, 120, {} },
+ {INIT_DCS_CMD, 1, { 0x29 } },
+ {DELAY_CMD, 20, {} },
+
+};
+
+struct panel_info krane_panel_info[] = {
+ PANEL(PANEL_KRANE_BOE_TV101WUM_NL6,
+ 74000,
+ krane_boe_tv101wum_nl6_edid,
+ boe_tv101wum_nl6_init_cmd),
+ {{PANEL_KRANE_UNKNOWN}, "PANEL_KRANE_UNKNOWN",
+ 0, NULL, NULL, 0},
+};
+
+static union panel_id krane_get_panel_id(struct board_display_intf *intf)
+{
+ return (union panel_id)PANEL_KRANE_BOE_TV101WUM_NL6;
+};
+
+static bool krane_is_panel_id_valid(union panel_id id)
+{
+ if (id.value < PANEL_KRANE_UNKNOWN)
+ return true;
+ return false;
+};
+
+static int krane_backlight(struct board_display_intf *intf)
+{
+ gpio_output(GPIO(PERIPHERAL_EN13), 1);
+ gpio_output(GPIO(DISP_PWM), 1); /* DISP_PWM0 */
+
+ return 0;
+};
+
+static int krane_power(struct board_display_intf *intf)
+{
+ if (board_id() < 2) {
+ /* board from p1 */
+ gpio_output(GPIO(LCM_RST), 0);
+ udelay(100);
+ gpio_output(GPIO(LCM_RST), 1);
+ mdelay(20);
+ } else {
+ /* board from p2 */
+ gpio_output(GPIO(LCM_RST), 0);
+ udelay(1500);
+ gpio_output(GPIO(SIM2_SRST), 1);
+ mdelay(5);
+ gpio_output(GPIO(PERIPHERAL_EN9), 1);
+ gpio_output(GPIO(MISC_BSI_CK_3), 1);
+ mdelay(100);
+ gpio_output(GPIO(LCM_RST), 1);
+ mdelay(10);
+ }
+
+ return 0;
+
+};
+
+struct board_display_intf panel_display_intf = {
+ .board = "krane",
+ .all_panel_info = krane_panel_info,
+ .all_panel_info_size = ARRAY_SIZE(krane_panel_info),
+ .cur_panel_info = NULL,
+ .get_panel_id = &krane_get_panel_id,
+ .is_panel_id_valid = &krane_is_panel_id_valid,
+ .backlight = &krane_backlight,
+ .power = &krane_power,
+};
diff --git a/src/mainboard/google/kukui/panel_kukui.c b/src/mainboard/google/kukui/panel_kukui.c
new file mode 100644
index 0000000..be76aa4
--- /dev/null
+++ b/src/mainboard/google/kukui/panel_kukui.c
@@ -0,0 +1,194 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Huaqin Telecom Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <delay.h>
+#include <device/device.h>
+#include <edid.h>
+#include <gpio.h>
+#include <soc/auxadc.h>
+#include <soc/ddp.h>
+#include <soc/dsi.h>
+#include <soc/gpio.h>
+#include <boardid.h>
+
+#include "display.h"
+#include "gpio.h"
+
+static struct edid kukui_innolux_edid = {
+ .panel_bits_per_color = 8,
+ .panel_bits_per_pixel = 24,
+ .mode = {
+ .name = "768x1024@60Hz",
+ .pixel_clock = 56900,
+ .lvds_dual_channel = 0,
+ .refresh = 60,
+ .ha = 768, .hbl = 120, .hso = 40, .hspw = 40, .hborder = 0,
+ .va = 1024, .vbl = 44, .vso = 20, .vspw = 4, .vborder = 0,
+ .phsync = '-', .pvsync = '-',
+ .x_mm = 120, .y_mm = 160,
+ },
+};
+
+static struct lcm_init_table lcm_init_cmd[] = {
+ {INIT_DCS_CMD, 1, {MIPI_DCS_EXIT_SLEEP_MODE} },
+ {DELAY_CMD, 120, {} },
+ {INIT_DCS_CMD, 1, {MIPI_DCS_SET_DISPLAY_ON} },
+ {DELAY_CMD, 120, {} },
+};
+
+static struct edid kukui_p097pfg_ssd2858_edid = {
+ .panel_bits_per_color = 8,
+ .panel_bits_per_pixel = 24,
+ .mode = {
+ .name = "1536x2048@60Hz",
+ .pixel_clock = 211660,
+ .lvds_dual_channel = 0,
+ .refresh = 60,
+ .ha = 1536, .hbl = 160, .hso = 140, .hspw = 10, .hborder = 0,
+ .va = 2048, .vbl = 32, .vso = 20, .vspw = 2, .vborder = 0,
+ .phsync = '-', .pvsync = '-',
+ .x_mm = 147, .y_mm = 196,
+ },
+};
+
+struct lcm_init_table lcm_p097pfg_ssd2858_init_cmd[] = {
+ /* SSD2858 config */
+ {INIT_GENENIC_CMD, 2, {0xff, 0x00} },
+ /* LOCKCNT=0x1f4, MRX=0, POSTDIV=1 (/2} }, MULT=0x49
+ * 27 Mhz => 985.5 Mhz
+ */
+ {INIT_GENENIC_CMD, 6, {0x00, 0x08, 0x01, 0xf4, 0x01, 0x49} },
+ /* MTXDIV=1, SYSDIV=3 (=> 4) */
+ {INIT_GENENIC_CMD, 6, {0x00, 0x0c, 0x00, 0x00, 0x00, 0x03} },
+ /* MTXVPF=24bpp, MRXLS=4 lanes, MRXVB=bypass, MRXECC=1, MRXEOT=1
+ * MRXEE=1
+ */
+ {INIT_GENENIC_CMD, 6, {0x00, 0x14, 0x0c, 0x3d, 0x80, 0x0f} },
+ {INIT_GENENIC_CMD, 6, {0x00, 0x20, 0x15, 0x92, 0x56, 0x7d} },
+ {INIT_GENENIC_CMD, 6, {0x00, 0x24, 0x00, 0x00, 0x30, 0x00} },
+
+ {INIT_GENENIC_CMD, 6, {0x10, 0x08, 0x01, 0x20, 0x08, 0x45} },
+ {INIT_GENENIC_CMD, 6, {0x10, 0x1c, 0x00, 0x00, 0x00, 0x00} },
+ {INIT_GENENIC_CMD, 6, {0x20, 0x0c, 0x00, 0x00, 0x00, 0x04} },
+ /* Pixel clock 985.5 Mhz * 0x49/0x4b = 959 Mhz */
+ {INIT_GENENIC_CMD, 6, {0x20, 0x10, 0x00, 0x4b, 0x00, 0x49} },
+ {INIT_GENENIC_CMD, 6, {0x20, 0xa0, 0x00, 0x00, 0x00, 0x00} },
+ /* EOT=1, LPE = 0, LSOUT=4 lanes, LPD=25 */
+ {INIT_GENENIC_CMD, 6, {0x60, 0x08, 0x00, 0xd9, 0x00, 0x08} },
+ {INIT_GENENIC_CMD, 6, {0x60, 0x14, 0x01, 0x00, 0x01, 0x06} },
+ /* DSI0 enable (default: probably not needed) */
+ {INIT_GENENIC_CMD, 6, {0x60, 0x80, 0x00, 0x00, 0x00, 0x0f} },
+ /* DSI1 enable */
+ {INIT_GENENIC_CMD, 6, {0x60, 0xa0, 0x00, 0x00, 0x00, 0x0f} },
+
+ /* HSA=0x18, VSA=0x02, HBP=0x50, VBP=0x0c */
+ {INIT_GENENIC_CMD, 6, {0x60, 0x0c, 0x0c, 0x50, 0x02, 0x18} },
+ /* VACT= 0x800 (2048} }, VFP= 0x14, HFP=0x50 */
+ {INIT_GENENIC_CMD, 6, {0x60, 0x10, 0x08, 0x00, 0x14, 0x50} },
+ /* HACT=0x300 (768) */
+ {INIT_GENENIC_CMD, 6, {0x60, 0x84, 0x00, 0x00, 0x03, 0x00} },
+ {INIT_GENENIC_CMD, 6, {0x60, 0xa4, 0x00, 0x00, 0x03, 0x00} },
+
+ /* Take panel out of sleep. */
+ {INIT_GENENIC_CMD, 2, {0xff, 0x01} },
+ {INIT_DCS_CMD, 1, {0x11} },
+ {DELAY_CMD, 120, {} },
+ {INIT_DCS_CMD, 1, {0x29} },
+ {DELAY_CMD, 20, {} },
+ {INIT_GENENIC_CMD, 2, {0xff, 0x00} },
+
+ {DELAY_CMD, 120, {} },
+ {INIT_DCS_CMD, 1, {0x11} },
+ {DELAY_CMD, 120, {} },
+ {INIT_DCS_CMD, 1, {0x29} },
+ {DELAY_CMD, 20, {} },
+};
+
+struct panel_info kukui_panel_info[] = {
+ PANEL(PANEL_KUKUI_INNOLUX,
+ 74000,
+ kukui_innolux_edid,
+ lcm_init_cmd),
+ PANEL(PANEL_KUKUI_P097PFG_SSD2858,
+ 212000,
+ kukui_p097pfg_ssd2858_edid,
+ lcm_p097pfg_ssd2858_init_cmd),
+ {{PANEL_KUKUI_UNKNOWN}, "PANEL_KUKUI_UNKNOWN",
+ 0, NULL, NULL, 0},
+};
+
+static union panel_id kukui_get_panel_id(struct board_display_intf *intf)
+{
+ if (board_id() < 2)
+ return (union panel_id)PANEL_KUKUI_INNOLUX;
+ else
+ return (union panel_id)PANEL_KUKUI_P097PFG_SSD2858;
+};
+
+static bool kukui_is_panel_id_valid(union panel_id id)
+{
+ if (id.value < PANEL_KUKUI_UNKNOWN)
+ return true;
+ return false;
+};
+
+static int kukui_backlight(struct board_display_intf *intf)
+{
+ gpio_output(GPIO(PERIPHERAL_EN13), 1);
+ gpio_output(GPIO(DISP_PWM), 1); /* DISP_PWM0 */
+
+ return 0;
+};
+
+static int kukui_power(struct board_display_intf *intf)
+{
+ if (board_id() < 2) {
+ /* board from p1 */
+ gpio_output(GPIO(LCM_RST), 0);
+ udelay(100);
+ gpio_output(GPIO(LCM_RST), 1);
+ mdelay(20);
+ } else {
+ /* board from p2 */
+ gpio_output(GPIO(LCM_RST), 0);
+ gpio_output(GPIO(BPI_BUS3), 0);
+ gpio_output(GPIO(MISC_BSI_CK_3), 1);
+ gpio_output(GPIO(PERIPHERAL_EN9), 1);
+ gpio_output(GPIO(SIM2_SRST), 1);
+ gpio_output(GPIO(SIM2_SIO), 1);
+ gpio_output(GPIO(BPI_OLAT1), 1);
+ gpio_output(GPIO(SIM2_SCLK), 1);
+ mdelay(20);
+ gpio_output(GPIO(LCM_RST), 1);
+ mdelay(20);
+ gpio_output(GPIO(BPI_BUS3), 1);
+ mdelay(20);
+ }
+
+ return 0;
+
+};
+
+struct board_display_intf panel_display_intf = {
+ .board = "kukui",
+ .all_panel_info = kukui_panel_info,
+ .all_panel_info_size = ARRAY_SIZE(kukui_panel_info),
+ .cur_panel_info = NULL,
+ .get_panel_id = &kukui_get_panel_id,
+ .is_panel_id_valid = &kukui_is_panel_id_valid,
+ .backlight = &kukui_backlight,
+ .power = &kukui_power,
+};
diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc
index ce498c1..0afa335 100644
--- a/src/soc/mediatek/mt8183/Makefile.inc
+++ b/src/soc/mediatek/mt8183/Makefile.inc
@@ -42,6 +42,8 @@
ramstage-y += auxadc.c
ramstage-y += ../common/cbmem.c emi.c
+ramstage-y += ddp.c
+ramstage-y += dsi.c
ramstage-y += ../common/gpio.c gpio.c
ramstage-y += ../common/mmu_operations.c mmu_operations.c
ramstage-y += ../common/mtcmos.c mtcmos.c
diff --git a/src/soc/mediatek/mt8183/ddp.c b/src/soc/mediatek/mt8183/ddp.c
new file mode 100644
index 0000000..d845981
--- /dev/null
+++ b/src/soc/mediatek/mt8183/ddp.c
@@ -0,0 +1,202 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <delay.h>
+#include <device/mmio.h>
+#include <edid.h>
+#include <stdlib.h>
+#include <string.h>
+#include <stddef.h>
+#include <soc/addressmap.h>
+#include <soc/ddp.h>
+
+#define RDMA_FIFO_PSEUDO_SIZE(bytes) (((bytes) / 16) << 16)
+#define RDMA_OUTPUT_VALID_FIFO_THRESHOLD(bytes) ((bytes) / 16)
+
+static void disp_config_main_path_connection(void)
+{
+ write32(&mmsys_cfg->disp_ovl0_mout_en, OVL0_MOUT_EN_OVL0_2L);
+ write32(&mmsys_cfg->disp_ovl0_2l_mout_en, OVL0_2L_MOUT_EN_DISP_PATH0);
+ write32(&mmsys_cfg->disp_path0_sel_in, DISP_PATH0_SEL_IN_OVL0_2L);
+ write32(&mmsys_cfg->disp_rdma0_sout_sel_in, RDMA0_SOUT_SEL_IN_COLOR);
+ write32(&mmsys_cfg->disp_dither0_mout_en, DITHER0_MOUT_EN_DISP_DSI0);
+ write32(&mmsys_cfg->dsi0_sel_in, DSI0_SEL_IN_DITHER0_MOUT);
+}
+
+static void disp_config_main_path_mutex(void)
+{
+ write32(&disp_mutex->mutex[0].mod, MUTEX_MOD_MAIN_PATH);
+
+ /* Clock source from DSI0 */
+ write32(&disp_mutex->mutex[0].ctl,
+ MUTEX_SOF_DSI0 | (MUTEX_SOF_DSI0 << 6));
+ write32(&disp_mutex->mutex[0].en, BIT(0));
+}
+
+static void ovl_set_roi(u32 idx, u32 width, u32 height, u32 color)
+{
+ write32(&disp_ovl[idx]->roi_size, height << 16 | width);
+ write32(&disp_ovl[idx]->roi_bgclr, color);
+}
+
+static void ovl_layer_enable(u32 idx)
+{
+ write32(&disp_ovl[idx]->rdma[0].ctrl, BIT(0));
+ write32(&disp_ovl[idx]->rdma[0].mem_gmc_setting, RDMA_MEM_GMC);
+
+ setbits_le32(&disp_ovl[idx]->src_con, BIT(0));
+}
+
+static void ovl_bgclr_in_sel(u32 idx)
+{
+ setbits_le32(&disp_ovl[idx]->datapath_con, BIT(2));
+}
+
+static void rdma_start(u32 idx)
+{
+ setbits_le32(&disp_rdma[idx]->global_con, RDMA_ENGINE_EN);
+}
+
+static void rdma_config(u32 idx, u32 width, u32 height, u32 vrefresh)
+{
+ u32 threshold;
+ u32 reg;
+ u32 fifo_size;
+
+ clrsetbits_le32(&disp_rdma[idx]->size_con_0, 0x1FFF, width);
+ clrsetbits_le32(&disp_rdma[idx]->size_con_1, 0xFFFFF, height);
+
+ /*
+ * Enable FIFO underflow since DSI and DPI can't be blocked. Keep the
+ * FIFO pseudo size reset default of 8 KiB. Set the output threshold to
+ * 6 microseconds with 7/6 overhead to account for blanking, and with a
+ * pixel depth of 4 bytes:
+ */
+ fifo_size = RDMA_FIFO_SIZE_0 * KiB;
+
+ threshold = width * height * vrefresh * 4 * 7 / 1000000;
+
+ if (threshold > fifo_size)
+ threshold = fifo_size;
+
+ reg = RDMA_FIFO_UNDERFLOW_EN |
+ RDMA_FIFO_PSEUDO_SIZE(fifo_size) |
+ RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold);
+
+ write32(&disp_rdma[idx]->fifo_con, reg);
+}
+
+static void color_start(u32 width, u32 height)
+{
+ write32(&disp_color->width, width);
+ write32(&disp_color->height, height);
+ write32(&disp_color->cfg_main, COLOR_BYPASS_ALL | COLOR_SEQ_SEL);
+ write32(&disp_color->start, BIT(0));
+}
+
+static void aal_start(u32 width, u32 height)
+{
+ write32(&disp_aal->size, height << 16 | width);
+ write32(&disp_aal->en, PQ_EN);
+}
+
+static void ccorr_start(u32 width, u32 height)
+{
+ write32(&disp_ccorr->size, height << 16 | width);
+ write32(&disp_ccorr->cfg, PQ_RELAY_MODE);
+ write32(&disp_ccorr->en, PQ_EN);
+}
+
+static void dither_start(u32 width, u32 height)
+{
+ write32(&disp_dither->size, height << 16 | width);
+ write32(&disp_dither->cfg, PQ_RELAY_MODE);
+ write32(&disp_dither->en, PQ_EN);
+}
+
+static void gamma_start(u32 width, u32 height)
+{
+ write32(&disp_gamma->size, height << 16 | width);
+ write32(&disp_gamma->en, PQ_EN);
+}
+
+static void ovl_layer_config(u32 idx, u32 fmt, u32 bpp, u32 width, u32 height)
+{
+ write32(&disp_ovl[idx]->layer[0].con, fmt << 12);
+ write32(&disp_ovl[idx]->layer[0].src_size, height << 16 | width);
+ write32(&disp_ovl[idx]->layer[0].pitch, (width * bpp) & 0xFFFF);
+
+ ovl_layer_enable(idx);
+}
+
+static void main_disp_path_setup(u32 width, u32 height, u32 vrefresh)
+{
+ u32 idx = 0;
+
+ /* Setup OVL */
+ for (idx = 0; idx < MAIN_PATH_OVL_NR; idx++) {
+ u32 color = 0;
+
+ if (idx == 0)
+ color = 0xFF0000FF;
+
+ ovl_set_roi(idx, width, height, color);
+ }
+
+ idx = 0;
+ rdma_config(idx, width, height, vrefresh);
+ color_start(width, height);
+ ccorr_start(width, height);
+ aal_start(width, height);
+ gamma_start(width, height);
+ dither_start(width, height);
+ disp_config_main_path_connection();
+ disp_config_main_path_mutex();
+}
+
+static void disp_clock_on(void)
+{
+ clrbits_le32(&mmsys_cfg->mmsys_cg_con0, CG_CON0_DISP_ALL);
+
+ clrbits_le32(&mmsys_cfg->mmsys_cg_con1, CG_CON1_DISP_DSI0 |
+ CG_CON1_DISP_DSI0_INTERFACE);
+}
+
+static void disp_m4u_port_off(void)
+{
+ write32((void *)(SMI_LARB0 + SMI_LARB_NON_SEC_CON), 0);
+}
+
+void mtk_ddp_init(void)
+{
+ disp_clock_on();
+ disp_m4u_port_off();
+}
+
+void mtk_ddp_mode_set(const struct edid *edid)
+{
+ u32 fmt = OVL_INFMT_RGBA8888;
+ u32 bpp = edid->framebuffer_bits_per_pixel / 8;
+ u32 idx = 0;
+ u32 width = edid->mode.ha;
+ u32 height = edid->mode.va;
+ u32 vrefresh = edid->mode.refresh;
+
+ main_disp_path_setup(width, height, vrefresh);
+ rdma_start(idx);
+ ovl_layer_config(idx, fmt, bpp, width, height);
+ ovl_bgclr_in_sel(idx+1);
+}
diff --git a/src/soc/mediatek/mt8183/dsi.c b/src/soc/mediatek/mt8183/dsi.c
new file mode 100644
index 0000000..3bfada7
--- /dev/null
+++ b/src/soc/mediatek/mt8183/dsi.c
@@ -0,0 +1,485 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/mmio.h>
+#include <console/console.h>
+#include <delay.h>
+#include <soc/addressmap.h>
+#include <soc/dsi.h>
+#include <timer.h>
+
+static void dsi_write32(void *a, uint32_t v)
+{
+ write32(a, v);
+}
+
+static void dsi_clrsetbits_le32(void *a, uint32_t m, uint32_t v)
+{
+ clrsetbits_le32(a, m, v);
+}
+
+static void dsi_clrbits_le32(void *a, uint32_t m)
+{
+ clrbits_le32(a, m);
+}
+
+static void dsi_setbits_le32(void *a, uint32_t m)
+{
+ setbits_le32(a, m);
+}
+
+static int mtk_dsi_phy_clk_setting(u32 format, u32 lanes,
+ const struct edid *edid)
+{
+ unsigned int txdiv, txdiv0, txdiv1;
+ u64 pcw;
+ int data_rate;
+ u32 bpp;
+
+ switch (format) {
+ case MIPI_DSI_FMT_RGB565:
+ bpp = 16;
+ break;
+ case MIPI_DSI_FMT_RGB666:
+ case MIPI_DSI_FMT_RGB666_PACKED:
+ bpp = 18;
+ break;
+ case MIPI_DSI_FMT_RGB888:
+ default:
+ bpp = 24;
+ break;
+ }
+
+ data_rate = (u64)(edid->mode.pixel_clock * 1000 * bpp) / lanes;
+
+ printk(BIOS_INFO, "data_rate: %u bps\n", data_rate);
+
+ if (data_rate >= 2000000000) {
+ txdiv = 1;
+ txdiv0 = 0;
+ txdiv1 = 0;
+ } else if (data_rate >= 1000000000) {
+ txdiv = 2;
+ txdiv0 = 1;
+ txdiv1 = 0;
+ } else if (data_rate >= 500000000) {
+ txdiv = 4;
+ txdiv0 = 2;
+ txdiv1 = 0;
+ } else if (data_rate > 250000000) {
+ txdiv = 8;
+ txdiv0 = 3;
+ txdiv1 = 0;
+ } else if (data_rate >= 125000000) {
+ txdiv = 16;
+ txdiv0 = 4;
+ txdiv1 = 0;
+ } else {
+ printk(BIOS_ERR, "data rate (%u) must be >=50. Please check "
+ "pixel clock (%u), bpp (%u), number of lanes (%u)\n",
+ data_rate, edid->mode.pixel_clock, bpp,
+ lanes);
+ return -1;
+ }
+
+ dsi_clrbits_le32(mipi_tx + MIPITX_PLL_CON4, BIT(11) | BIT(10));
+
+ dsi_setbits_le32(mipi_tx + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_PWR_ON);
+ udelay(30);
+ dsi_clrbits_le32(mipi_tx + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_ISO_EN);
+
+ pcw = (u64)((data_rate / 1000000) * (1 << txdiv0) * (1 << txdiv1));
+ pcw <<= 24;
+ pcw /= 26;
+
+ dsi_write32(mipi_tx + MIPITX_PLL_CON0, pcw);
+ dsi_clrsetbits_le32(mipi_tx + MIPITX_PLL_CON1, RG_DSI_PLL_POSDIV,
+ txdiv0 << 8);
+ udelay(30);
+ dsi_setbits_le32(mipi_tx + MIPITX_PLL_CON1, RG_DSI_PLL_EN);
+
+ /* BG_LPF_EN / BG_CORE_EN */
+ dsi_write32(mipi_tx + MIPITX_LANE_CON, 0x3FFF0180);
+ udelay(40);
+ dsi_write32(mipi_tx + MIPITX_LANE_CON, 0x3FFF00c0);
+
+ /* Switch OFF each Lane */
+ dsi_clrbits_le32(mipi_tx + MIPITX_D0_SW_CTL_EN, DSI_SW_CTL_EN);
+ dsi_clrbits_le32(mipi_tx + MIPITX_D1_SW_CTL_EN, DSI_SW_CTL_EN);
+ dsi_clrbits_le32(mipi_tx + MIPITX_D2_SW_CTL_EN, DSI_SW_CTL_EN);
+ dsi_clrbits_le32(mipi_tx + MIPITX_D3_SW_CTL_EN, DSI_SW_CTL_EN);
+ dsi_clrbits_le32(mipi_tx + MIPITX_CK_SW_CTL_EN, DSI_SW_CTL_EN);
+
+ dsi_setbits_le32(mipi_tx + MIPITX_CK_CKMODE_EN, DSI_CK_CKMODE_EN);
+
+ return data_rate;
+}
+
+static void mtk_dsi_phy_timconfig(u32 data_rate,
+ struct mtk_phy_timing *phy_timing)
+{
+ u32 timcon0, timcon1, timcon2, timcon3;
+
+ timcon0 = phy_timing->lpx | phy_timing->da_hs_prepare << 8 |
+ phy_timing->da_hs_zero << 16 | phy_timing->da_hs_trail << 24;
+ timcon1 = phy_timing->ta_go | phy_timing->ta_sure << 8 |
+ phy_timing->ta_get << 16 | phy_timing->da_hs_exit << 24;
+ timcon2 = 1 << 8 | phy_timing->clk_hs_zero << 16 |
+ phy_timing->clk_hs_trail << 24;
+ timcon3 = phy_timing->clk_hs_prepare | phy_timing->clk_hs_post << 8 |
+ phy_timing->clk_hs_exit << 16;
+
+ dsi_write32(&dsi->dsi_phy_timecon0, timcon0);
+ dsi_write32(&dsi->dsi_phy_timecon1, timcon1);
+ dsi_write32(&dsi->dsi_phy_timecon2, timcon2);
+ dsi_write32(&dsi->dsi_phy_timecon3, timcon3);
+}
+
+static void mtk_dsi_reset(void)
+{
+ dsi_write32(&dsi->dsi_con_ctrl, 1);
+ dsi_write32(&dsi->dsi_con_ctrl, 0);
+}
+
+static void mtk_dsi_clk_hs_mode_enable(void)
+{
+ dsi_setbits_le32(&dsi->dsi_phy_lccon, 1);
+}
+
+static void mtk_dsi_set_mode(u32 mode_flags)
+{
+ u32 tmp_reg1 = 0;
+
+ if (mode_flags & MIPI_DSI_MODE_VIDEO) {
+ tmp_reg1 = SYNC_PULSE_MODE;
+
+ if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
+ tmp_reg1 = BURST_MODE;
+
+ if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
+ tmp_reg1 = SYNC_PULSE_MODE;
+ }
+
+ dsi_write32(&dsi->dsi_mode_ctrl, tmp_reg1);
+}
+
+static void mtk_dsi_phy_timing_calc(u32 format, u32 lanes,
+ const struct edid *edid,
+ struct mtk_phy_timing *phy_timing)
+{
+ u32 ui, cycle_time, data_rate;
+ u32 bit_per_pixel;
+
+ switch (format) {
+ case MIPI_DSI_FMT_RGB565:
+ bit_per_pixel = 16;
+ break;
+ case MIPI_DSI_FMT_RGB666:
+ case MIPI_DSI_FMT_RGB666_PACKED:
+ bit_per_pixel = 18;
+ break;
+ case MIPI_DSI_FMT_RGB888:
+ default:
+ bit_per_pixel = 24;
+ break;
+ }
+
+ data_rate = edid->mode.pixel_clock * bit_per_pixel / lanes;
+
+ ui = 1000 / (data_rate / 1000) + 1U;
+ cycle_time = 8000 / (data_rate / 1000) + 1U;
+
+ phy_timing->lpx = DIV_ROUND_UP(60, cycle_time);
+ phy_timing->da_hs_prepare = DIV_ROUND_UP((40 + 5 * ui), cycle_time);
+ phy_timing->da_hs_zero = DIV_ROUND_UP((180 + 6 * ui), cycle_time);
+ phy_timing->da_hs_trail = DIV_ROUND_UP(((4 * ui) + 80), cycle_time);
+
+ if (phy_timing->da_hs_zero > phy_timing->da_hs_prepare)
+ phy_timing->da_hs_zero -= phy_timing->da_hs_prepare;
+
+ phy_timing->ta_go = 4U * phy_timing->lpx;
+ phy_timing->ta_sure = 3U * phy_timing->lpx / 2U;
+ phy_timing->ta_get = 5U * phy_timing->lpx;
+ phy_timing->da_hs_exit = 2U * phy_timing->lpx;
+
+ phy_timing->clk_hs_zero = DIV_ROUND_UP(0x150U, cycle_time);
+ phy_timing->clk_hs_trail = DIV_ROUND_UP(0x64U, cycle_time) + 0xaU;
+
+ phy_timing->clk_hs_prepare = DIV_ROUND_UP(0x40U, cycle_time);
+ phy_timing->clk_hs_post = DIV_ROUND_UP(80U + 52U * ui, cycle_time);
+ phy_timing->clk_hs_exit = 2U * phy_timing->lpx;
+}
+
+static void mtk_dsi_rxtx_control(u32 mode_flags, u32 lanes)
+{
+ u32 tmp_reg = 0;
+
+ switch (lanes) {
+ case 1:
+ tmp_reg = 1 << 2;
+ break;
+ case 2:
+ tmp_reg = 3 << 2;
+ break;
+ case 3:
+ tmp_reg = 7 << 2;
+ break;
+ case 4:
+ default:
+ tmp_reg = 0xf << 2;
+ break;
+ }
+
+ tmp_reg |= (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) << 6;
+ tmp_reg |= (mode_flags & MIPI_DSI_MODE_EOT_PACKET) >> 3;
+
+ dsi_write32(&dsi->dsi_txrx_ctrl, tmp_reg);
+}
+
+static void mtk_dsi_config_vdo_timing(u32 mode_flags, u32 format,
+ const struct edid *edid,
+ struct mtk_phy_timing *phy_timing,
+ u32 lanes)
+{
+ u32 hsync_active_byte;
+ u32 hbp_byte;
+ u32 hfp_byte, tmp_hfp_byte;
+ u32 vbp_byte;
+ u32 vfp_byte;
+ u32 bpp;
+ u32 packet_fmt;
+ u32 hactive;
+ u32 data_phy_cycles;
+
+ if (format == MIPI_DSI_FMT_RGB565)
+ bpp = 2;
+ else
+ bpp = 3;
+
+ vbp_byte = edid->mode.vbl - edid->mode.vso - edid->mode.vspw -
+ edid->mode.vborder;
+ vfp_byte = edid->mode.vso - edid->mode.vborder;
+
+ dsi_write32(&dsi->dsi_vsa_nl, edid->mode.vspw);
+ dsi_write32(&dsi->dsi_vbp_nl, vbp_byte);
+ dsi_write32(&dsi->dsi_vfp_nl, vfp_byte);
+ dsi_write32(&dsi->dsi_vact_nl, edid->mode.va);
+
+ if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
+ hbp_byte = (edid->mode.hbl - edid->mode.hso - edid->mode.hspw -
+ edid->mode.hborder) * bpp - 10;
+ else
+ hbp_byte = (edid->mode.hbl - edid->mode.hso -
+ edid->mode.hborder) * bpp - 10;
+
+ hsync_active_byte = edid->mode.hspw * bpp - 10;
+
+ data_phy_cycles = phy_timing->lpx + phy_timing->da_hs_prepare +
+ phy_timing->da_hs_zero + phy_timing->da_hs_exit + 2;
+
+ tmp_hfp_byte = (edid->mode.hso - edid->mode.hborder) * bpp;
+
+ if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST) {
+ if (tmp_hfp_byte > data_phy_cycles * lanes + 18) {
+ hfp_byte = tmp_hfp_byte - data_phy_cycles * lanes - 18;
+ } else {
+ printk(BIOS_ERR, "HFP less than d-phy, FPS will under 60Hz\n");
+ hfp_byte = tmp_hfp_byte;
+ }
+ } else {
+ if (tmp_hfp_byte > data_phy_cycles * lanes + 12) {
+ hfp_byte = tmp_hfp_byte - data_phy_cycles * lanes - 12;
+ } else {
+ printk(BIOS_ERR, "HFP less than d-phy, FPS will under 60Hz\n");
+ hfp_byte = tmp_hfp_byte;
+ }
+ }
+
+ dsi_write32(&dsi->dsi_hsa_wc, hsync_active_byte);
+ dsi_write32(&dsi->dsi_hbp_wc, hbp_byte);
+ dsi_write32(&dsi->dsi_hfp_wc, hfp_byte);
+
+ switch (format) {
+ case MIPI_DSI_FMT_RGB888:
+ packet_fmt = PACKED_PS_24BIT_RGB888;
+ break;
+ case MIPI_DSI_FMT_RGB666:
+ packet_fmt = LOOSELY_PS_18BIT_RGB666;
+ break;
+ case MIPI_DSI_FMT_RGB666_PACKED:
+ packet_fmt = PACKED_PS_18BIT_RGB666;
+ break;
+ case MIPI_DSI_FMT_RGB565:
+ packet_fmt = PACKED_PS_16BIT_RGB565;
+ break;
+ default:
+ packet_fmt = PACKED_PS_24BIT_RGB888;
+ break;
+ }
+
+ hactive = edid->mode.ha;
+ packet_fmt |= (hactive * bpp) & DSI_PS_WC;
+
+ dsi_write32(&dsi->dsi_psctrl, 0x2c << 24 | packet_fmt);
+ dsi_write32(&dsi->dsi_size_con, edid->mode.va << 16 | hactive);
+}
+
+static void mtk_dsi_start(void)
+{
+ dsi_clrbits_le32(&dsi->dsi_start, 1);
+ dsi_setbits_le32(&dsi->dsi_start, 1);
+}
+
+static void mtk_dsi_cmdq(u8 *data, u8 len, u32 type)
+{
+ struct stopwatch sw;
+ u8 *tx_buf = data;
+ u8 cmdq_size;
+ u32 reg_val, cmdq_mask, i, config, cmdq_off, intsta_0;
+
+ while (read32(&dsi->dsi_intsta) & (1 << 31)) {
+ printk(BIOS_ERR, "%s wait dsi no busy\n", __func__);
+ mdelay(20);
+ }
+
+ dsi_write32(&dsi->dsi_intsta, 0);
+
+ if (MTK_DSI_HOST_IS_READ(type))
+ config = BTA;
+ else
+ config = (len > 2) ? LONG_PACKET : SHORT_PACKET;
+
+ if (len > 2) {
+ cmdq_size = 1 + (len + 3) / 4;
+ cmdq_off = 4;
+ cmdq_mask = CONFIG | DATA_ID | DATA_0 | DATA_1;
+ reg_val = (len << 16) | (type << 8) | config;
+ } else {
+ cmdq_size = 1;
+ cmdq_off = 2;
+ cmdq_mask = CONFIG | DATA_ID;
+ reg_val = (type << 8) | config;
+ }
+
+ for (i = 0; i < 0x20; i = i + 4)
+ dsi_write32((void *)DSI_BASE + 0x200 + i, 0);
+
+ for (i = 0; i < len; i++) {
+ dsi_clrsetbits_le32((void *)DSI_BASE + 0x200 +
+ ((cmdq_off + i) & (0xfffffffc)),
+ (0xff << (((i + cmdq_off) & 3) * 8)),
+ tx_buf[i] << (((i + cmdq_off) & 3) * 8));
+ }
+
+ dsi_clrsetbits_le32(&dsi->dsi_cmdq0, cmdq_mask, reg_val);
+ dsi_clrsetbits_le32(&dsi->dsi_cmdq_size, CMDQ_SIZE, cmdq_size);
+ mtk_dsi_start();
+
+ stopwatch_init_usecs_expire(&sw, 400);
+ do {
+ intsta_0 = read32(&dsi->dsi_intsta);
+ if (intsta_0 & CMD_DONE_INT_FLAG)
+ break;
+ udelay(4);
+ } while (!stopwatch_expired(&sw));
+
+ if (!(intsta_0 & CMD_DONE_INT_FLAG))
+ printk(BIOS_ERR, "dsi send cmd time-out(400uS)\n");
+}
+
+static void push_table(struct lcm_init_table *init_cmd, u32 count)
+{
+ u32 cmd, i;
+ u32 type;
+
+ for (i = 0; i < count; i++) {
+ cmd = init_cmd[i].cmd;
+
+ switch (cmd) {
+ case DELAY_CMD:
+ mdelay(init_cmd[i].len);
+ break;
+
+ case END_OF_TABLE:
+ break;
+
+ case INIT_DCS_CMD:
+ switch (init_cmd[i].len) {
+ case 0:
+ return;
+
+ case 1:
+ type = MIPI_DSI_DCS_SHORT_WRITE;
+ break;
+
+ case 2:
+ type = MIPI_DSI_DCS_SHORT_WRITE_PARAM;
+ break;
+
+ default:
+ type = MIPI_DSI_DCS_LONG_WRITE;
+ break;
+ }
+ mtk_dsi_cmdq(init_cmd[i].data, init_cmd[i].len, type);
+ break;
+
+ case INIT_GENENIC_CMD:
+ default:
+ switch (init_cmd[i].len) {
+ case 0:
+ type = MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM;
+ break;
+ case 1:
+ type = MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM;
+ break;
+ case 2:
+ type = MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM;
+ break;
+ default:
+ type = MIPI_DSI_GENERIC_LONG_WRITE;
+ break;
+ }
+ mtk_dsi_cmdq(init_cmd[i].data, init_cmd[i].len, type);
+ break;
+ }
+ }
+}
+
+int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, bool dual,
+ const struct edid *edid, struct lcm_init_table *init_cmd,
+ u32 count)
+{
+ int data_rate;
+ struct mtk_phy_timing phy_timing;
+
+ mtk_dsi_phy_timing_calc(format, lanes, edid, &phy_timing);
+
+ data_rate = mtk_dsi_phy_clk_setting(format, lanes, edid);
+
+ if (data_rate < 0)
+ return -1;
+
+ dsi_write32(&dsi->dsi_force_commit, 3);
+ mtk_dsi_reset();
+ mtk_dsi_phy_timconfig(data_rate, &phy_timing);
+ mtk_dsi_rxtx_control(mode_flags, lanes);
+ mtk_dsi_config_vdo_timing(mode_flags, format, edid, &phy_timing, lanes);
+ mtk_dsi_clk_hs_mode_enable();
+ push_table(init_cmd, count);
+ mtk_dsi_set_mode(mode_flags);
+ mtk_dsi_start();
+
+ return 0;
+}
diff --git a/src/soc/mediatek/mt8183/include/soc/addressmap.h b/src/soc/mediatek/mt8183/include/soc/addressmap.h
index d41b2b9..75202dd 100644
--- a/src/soc/mediatek/mt8183/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8183/include/soc/addressmap.h
@@ -47,12 +47,27 @@
IOCFG_RT_BASE = IO_PHYS + 0x01C50000,
IOCFG_RM_BASE = IO_PHYS + 0x01D20000,
IOCFG_RB_BASE = IO_PHYS + 0x01D30000,
+ MIPITX_BASE = IO_PHYS + 0x01E50000,
IOCFG_LB_BASE = IO_PHYS + 0x01E70000,
IOCFG_LM_BASE = IO_PHYS + 0x01E80000,
IOCFG_BL_BASE = IO_PHYS + 0x01E90000,
IOCFG_LT_BASE = IO_PHYS + 0x01F20000,
IOCFG_TL_BASE = IO_PHYS + 0x01F30000,
SSUSB_SIF_BASE = IO_PHYS + 0x01F40300,
+ MMSYS_BASE = IO_PHYS + 0x04000000,
+ DISP_OVL0_BASE = IO_PHYS + 0x04008000,
+ DISP_OVL0_2L_BASE = IO_PHYS + 0x04009000,
+ DISP_OVL1_2L_BASE = IO_PHYS + 0x0400A000,
+ DISP_RDMA0_BASE = IO_PHYS + 0x0400B000,
+ DISP_RDMA1_BASE = IO_PHYS + 0x0400C000,
+ DISP_COLOR0_BASE = IO_PHYS + 0x0400E000,
+ DISP_CCORR0_BASE = IO_PHYS + 0x0400F000,
+ DISP_AAL0_BASE = IO_PHYS + 0x04010000,
+ DISP_GAMMA0_BASE = IO_PHYS + 0x04011000,
+ DISP_DITHER0_BASE = IO_PHYS + 0x04012000,
+ DSI_BASE = IO_PHYS + 0x04014000,
+ DISP_MUTEX_BASE = IO_PHYS + 0x04016000,
+ SMI_LARB0 = IO_PHYS + 0x04017000,
SMI_BASE = IO_PHYS + 0x04019000,
};
diff --git a/src/soc/mediatek/mt8183/include/soc/ddp.h b/src/soc/mediatek/mt8183/include/soc/ddp.h
new file mode 100644
index 0000000..1914868
--- /dev/null
+++ b/src/soc/mediatek/mt8183/include/soc/ddp.h
@@ -0,0 +1,315 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DDP_REG_H_
+#define _DDP_REG_H_
+
+#include <soc/addressmap.h>
+#include <types.h>
+
+#define MAIN_PATH_OVL_NR 2
+
+struct mmsys_cfg_regs {
+ u32 reserved_0x000[64]; /* 0x000 */
+ u32 mmsys_cg_con0; /* 0x100 */
+ u32 mmsys_cg_set0; /* 0x104 */
+ u32 mmsys_cg_clr0; /* 0x108 */
+ u32 reserved_0x10C; /* 0x10C */
+ u32 mmsys_cg_con1; /* 0x110 */
+ u32 mmsys_cg_set1; /* 0x114 */
+ u32 mmsys_cg_clr1; /* 0x118 */
+ u32 reserved_0x11C[889]; /* 0x11C */
+ u32 disp_ovl0_mout_en; /* 0xF00 */
+ u32 disp_ovl0_2l_mout_en; /* 0xF04 */
+ u32 disp_ovl1_2l_mout_en; /* 0xF08 */
+ u32 disp_dither0_mout_en; /* 0xF0C */
+ u32 reserved_0xF10[5]; /* 0xF10 - 0xF20 */
+ u32 disp_path0_sel_in; /* 0xF24 */
+ u32 reserved_0xF28; /* 0xF28 */
+ u32 dsi0_sel_in; /* 0xF2C */
+ u32 dpi0_sel_in; /* 0xF30 */
+ u32 reserved_0xF34; /* 0xF34 */
+ u32 disp_ovl0_2l_sel_in; /* 0xF38 */
+ u32 reserved_0xF3C[5]; /* 0xF3C - 0xF4C */
+ u32 disp_rdma0_sout_sel_in; /* 0xF50 */
+ u32 disp_rdma1_sout_sel_in; /* 0xF54 */
+ u32 reserved_0xF58[3]; /* 0xF58 - 0xF60 */
+ u32 dpi0_sel_sout_sel_in; /* 0xF64 */
+};
+
+check_member(mmsys_cfg_regs, mmsys_cg_con0, 0x100);
+check_member(mmsys_cfg_regs, dpi0_sel_sout_sel_in, 0xF64);
+static struct mmsys_cfg_regs *const mmsys_cfg =
+ (void *)MMSYS_BASE;
+
+
+/* DISP_REG_CONFIG_MMSYS_CG_CON0
+ Configures free-run clock gating 0
+ 0: Enable clock
+ 1: Clock gating */
+enum {
+ CG_CON0_SMI_COMMON = BIT(0),
+ CG_CON0_SMI_LARB0 = BIT(1),
+ CG_CON0_GALS_COMMON0 = BIT(3),
+ CG_CON0_GALS_COMMON1 = BIT(4),
+ CG_CON0_DISP_OVL0 = BIT(20),
+ CG_CON0_DISP_OVL0_2L = BIT(21),
+ CG_CON0_DISP_OVL1_2L = BIT(22),
+ CG_CON0_DISP_RDMA0 = BIT(23),
+ CG_CON0_DISP_RDMA1 = BIT(24),
+ CG_CON0_DISP_WDMA0 = BIT(25),
+ CG_CON0_DISP_COLOR0 = BIT(26),
+ CG_CON0_DISP_CCORR0 = BIT(27),
+ CG_CON0_DISP_AAL0 = BIT(28),
+ CG_CON0_DISP_GAMMA0 = BIT(29),
+ CG_CON0_DISP_DITHER0 = BIT(30),
+ CG_CON0_DISP_ALL = CG_CON0_SMI_COMMON |
+ CG_CON0_SMI_LARB0 |
+ CG_CON0_GALS_COMMON0 |
+ CG_CON0_GALS_COMMON1 |
+ CG_CON0_DISP_OVL0 |
+ CG_CON0_DISP_OVL0_2L |
+ CG_CON0_DISP_RDMA0 |
+ CG_CON0_DISP_COLOR0 |
+ CG_CON0_DISP_CCORR0 |
+ CG_CON0_DISP_AAL0 |
+ CG_CON0_DISP_DITHER0 |
+ CG_CON0_DISP_GAMMA0,
+ CG_CON0_ALL = 0xffffffff
+};
+
+/* DISP_REG_CONFIG_MMSYS_CG_CON1
+ Configures free-run clock gating 1
+ 0: Enable clock
+ 1: Clock gating */
+enum {
+ CG_CON1_DISP_DSI0 = BIT(0),
+ CG_CON1_DISP_DSI0_INTERFACE = BIT(1),
+ CG_CON1_DISP_26M = BIT(7),
+
+ CG_CON1_ALL = 0xffffffff
+};
+
+enum {
+ OVL0_MOUT_EN_RDMA0 = BIT(0),
+ OVL0_MOUT_EN_OVL0_2L = BIT(4),
+ OVL0_2L_MOUT_EN_DISP_PATH0 = BIT(0),
+ OVL1_2L_MOUT_EN_DISP_RDMA1 = BIT(4),
+ DITHER0_MOUT_EN_DISP_DSI0 = BIT(0),
+};
+
+enum {
+ DISP_PATH0_SEL_IN_OVL0 = 0,
+ DISP_PATH0_SEL_IN_OVL0_2L = 1,
+ DSI0_SEL_IN_DITHER0_MOUT = 0,
+ DSI0_SEL_IN_RDMA0 = 1,
+ RDMA0_SOUT_SEL_IN_DSI0 = 0,
+ RDMA0_SOUT_SEL_IN_COLOR = 1,
+};
+
+struct disp_mutex_regs {
+ u32 inten;
+ u32 intsta;
+ u32 reserved0[6];
+ struct {
+ u32 en;
+ u32 dummy;
+ u32 rst;
+ u32 ctl;
+ u32 mod;
+ u32 reserved[3];
+ } mutex[12];
+};
+
+static struct disp_mutex_regs *const disp_mutex = (void *)DISP_MUTEX_BASE;
+
+enum {
+ MUTEX_MOD_DISP_RDMA0 = BIT(0),
+ MUTEX_MOD_DISP_RDMA1 = BIT(1),
+ MUTEX_MOD_DISP_OVL0 = BIT(9),
+ MUTEX_MOD_DISP_OVL0_2L = BIT(10),
+ MUTEX_MOD_DISP_OVL1_2L = BIT(11),
+ MUTEX_MOD_DISP_WDMA0 = BIT(12),
+ MUTEX_MOD_DISP_COLOR0 = BIT(13),
+ MUTEX_MOD_DISP_CCORR0 = BIT(14),
+ MUTEX_MOD_DISP_AAL0 = BIT(15),
+ MUTEX_MOD_DISP_GAMMA0 = BIT(16),
+ MUTEX_MOD_DISP_DITHER0 = BIT(17),
+ MUTEX_MOD_DISP_PWM0 = BIT(28),
+ MUTEX_MOD_MAIN_PATH = MUTEX_MOD_DISP_OVL0 | MUTEX_MOD_DISP_OVL0_2L |
+ MUTEX_MOD_DISP_RDMA0 | MUTEX_MOD_DISP_COLOR0 |
+ MUTEX_MOD_DISP_CCORR0 | MUTEX_MOD_DISP_AAL0 |
+ MUTEX_MOD_DISP_GAMMA0 |
+ MUTEX_MOD_DISP_DITHER0,
+};
+
+enum {
+ MUTEX_SOF_SINGLE_MODE = 0,
+ MUTEX_SOF_DSI0 = 1,
+ MUTEX_SOF_DPI0 = 2,
+};
+
+struct disp_ovl_regs {
+ u32 sta;
+ u32 inten;
+ u32 intsta;
+ u32 en;
+ u32 trig;
+ u32 rst;
+ u32 reserved_0x018[2];
+ u32 roi_size;
+ u32 datapath_con;
+ u32 roi_bgclr;
+ u32 src_con;
+ struct {
+ u32 con;
+ u32 srckey;
+ u32 src_size;
+ u32 offset;
+ u32 reserved0;
+ u32 pitch;
+ u32 reserved1[2];
+ } layer[4];
+ u32 reserved_0x0B0[4];
+ struct {
+ u32 ctrl;
+ u32 reserved0;
+ u32 mem_gmc_setting;
+ u32 mem_slow_con;
+ u32 fifo_ctrl;
+ u32 reserved1[3];
+ } rdma[4];
+ u32 reserved_0x140[880];
+ u32 reserved_0xF00[16];
+ u32 l0_addr;
+ u32 reserved_0xF44[7];
+ u32 l1_addr;
+ u32 reserved_0xF64[7];
+ u32 l2_addr;
+ u32 reserved_0xF84[7];
+ u32 l3_addr;
+};
+
+check_member(disp_ovl_regs, l3_addr, 0xFA0);
+static struct disp_ovl_regs *const disp_ovl[2] = {
+ (void *)DISP_OVL0_BASE, (void *)DISP_OVL0_2L_BASE
+};
+
+struct disp_rdma_regs {
+ u32 int_enable;
+ u32 int_status;
+ u32 reserved0[2];
+ u32 global_con;
+ u32 size_con_0;
+ u32 size_con_1;
+ u32 target_line;
+ u32 reserved1;
+ u32 mem_con;
+ u32 reserved2;
+ u32 mem_src_pitch;
+ u32 mem_gmc_setting_0;
+ u32 mem_gmc_setting_1;
+ u32 mem_slow_con;
+ u32 mem_gmc_setting_2;
+ u32 fifo_con;
+ u32 reserved3[4];
+ u32 cf[3][3];
+ u32 cf_pre_add[3];
+ u32 cf_post_add[3];
+ u32 dummy;
+ u32 debug_out_sel;
+};
+
+enum {
+ RDMA_ENGINE_EN = BIT(0),
+ RDMA_FIFO_UNDERFLOW_EN = BIT(31),
+ RDMA_FIFO_SIZE_0 = 5, /* 5K */
+ RDMA_VREFRESH = 60, /* vrefresh 60HZ */
+ RDMA_MEM_GMC = 0x40402020,
+};
+
+check_member(disp_rdma_regs, debug_out_sel, 0x94);
+static struct disp_rdma_regs *const disp_rdma[2] = {
+ (void *)DISP_RDMA0_BASE,
+ (void *)DISP_RDMA1_BASE,
+};
+
+struct disp_color_regs {
+ u8 reserved0[1024];
+ u32 cfg_main;
+ u8 reserved1[2044];
+ u32 start;
+ u8 reserved2[76];
+ u32 width;
+ u32 height;
+};
+
+check_member(disp_color_regs, height, 0xC54);
+static struct disp_color_regs *const disp_color = (void *)DISP_COLOR0_BASE;
+
+enum {
+ COLOR_BYPASS_ALL = BIT(7),
+ COLOR_SEQ_SEL = BIT(13),
+};
+
+struct disp_pq_regs {
+ u32 en;
+ u32 reset;
+ u32 inten;
+ u32 intsta;
+ u32 status;
+ u32 reserved0[3];
+ u32 cfg;
+ u32 reserved1[3];
+ u32 size;
+};
+
+enum {
+ PQ_EN = BIT(0),
+ PQ_RELAY_MODE = BIT(0),
+};
+
+static struct disp_pq_regs *const disp_ccorr = (void *)DISP_CCORR0_BASE;
+
+static struct disp_pq_regs *const disp_aal = (void *)DISP_AAL0_BASE;
+
+static struct disp_pq_regs *const disp_gamma = (void *)DISP_GAMMA0_BASE;
+
+static struct disp_pq_regs *const disp_dither = (void *)DISP_DITHER0_BASE;
+
+enum {
+ SMI_LARB_NON_SEC_CON = 0x380,
+};
+
+enum OVL_INPUT_FORMAT {
+ OVL_INFMT_RGB565 = 0,
+ OVL_INFMT_RGB888 = 1,
+ OVL_INFMT_RGBA8888 = 2,
+ OVL_INFMT_ARGB8888 = 3,
+ OVL_INFMT_UYVY = 4,
+ OVL_INFMT_YUYV = 5,
+ OVL_INFMT_UNKNOWN = 16,
+
+ OVL_COLOR_BASE = 30,
+ OVL_INFMT_BGR565 = OVL_INFMT_RGB565 + OVL_COLOR_BASE,
+ OVL_INFMT_BGR888 = OVL_INFMT_RGB888 + OVL_COLOR_BASE,
+ OVL_INFMT_BGRA8888 = OVL_INFMT_RGBA8888 + OVL_COLOR_BASE,
+ OVL_INFMT_ABGR8888 = OVL_INFMT_ARGB8888 + OVL_COLOR_BASE,
+};
+
+void mtk_ddp_init(void);
+void mtk_ddp_mode_set(const struct edid *edid);
+
+#endif
diff --git a/src/soc/mediatek/mt8183/include/soc/dsi.h b/src/soc/mediatek/mt8183/include/soc/dsi.h
new file mode 100644
index 0000000..dc89668
--- /dev/null
+++ b/src/soc/mediatek/mt8183/include/soc/dsi.h
@@ -0,0 +1,487 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DSI_REG_H_
+#define _DSI_REG_H_
+
+#include <edid.h>
+#include <soc/addressmap.h>
+#include <types.h>
+
+enum mipi_dsi_pixel_format {
+ MIPI_DSI_FMT_RGB888,
+ MIPI_DSI_FMT_RGB666,
+ MIPI_DSI_FMT_RGB666_PACKED,
+ MIPI_DSI_FMT_RGB565
+};
+
+/* video mode */
+enum {
+ MIPI_DSI_MODE_VIDEO = BIT(0),
+ /* video burst mode */
+ MIPI_DSI_MODE_VIDEO_BURST = BIT(1),
+ /* video pulse mode */
+ MIPI_DSI_MODE_VIDEO_SYNC_PULSE = BIT(2),
+ /* enable auto vertical count mode */
+ MIPI_DSI_MODE_VIDEO_AUTO_VERT = BIT(3),
+ /* enable hsync-end packets in vsync-pulse and v-porch area */
+ MIPI_DSI_MODE_VIDEO_HSE = BIT(4),
+ /* disable hfront-porch area */
+ MIPI_DSI_MODE_VIDEO_HFP = BIT(5),
+ /* disable hback-porch area */
+ MIPI_DSI_MODE_VIDEO_HBP = BIT(6),
+ /* disable hsync-active area */
+ MIPI_DSI_MODE_VIDEO_HSA = BIT(7),
+ /* flush display FIFO on vsync pulse */
+ MIPI_DSI_MODE_VSYNC_FLUSH = BIT(8),
+ /* disable EoT packets in HS mode */
+ MIPI_DSI_MODE_EOT_PACKET = BIT(9),
+ /* device supports non-continuous clock behavior (DSI spec 5.6.1) */
+ MIPI_DSI_CLOCK_NON_CONTINUOUS = BIT(10),
+ /* transmit data in low power */
+ MIPI_DSI_MODE_LPM = BIT(11)
+};
+
+struct dsi_regs {
+ u32 dsi_start;
+ u8 reserved0[4];
+ u32 dsi_inten;
+ u32 dsi_intsta;
+ u32 dsi_con_ctrl;
+ u32 dsi_mode_ctrl;
+ u32 dsi_txrx_ctrl;
+ u32 dsi_psctrl;
+ u32 dsi_vsa_nl;
+ u32 dsi_vbp_nl;
+ u32 dsi_vfp_nl;
+ u32 dsi_vact_nl;
+ u32 dsi_lfr_con;
+ u32 dsi_lfr_sta;
+ u32 dsi_size_con;
+ u32 dsi_vfp_early_stop;
+ u32 reserved1[4];
+ u32 dsi_hsa_wc;
+ u32 dsi_hbp_wc;
+ u32 dsi_hfp_wc;
+ u32 dsi_bllp_wc;
+ u32 dsi_cmdq_size;
+ u32 dsi_hstx_cklp_wc;
+ u8 reserved2[156];
+ u32 dsi_phy_lccon;
+ u32 dsi_phy_ld0con;
+ u8 reserved3[4];
+ u32 dsi_phy_timecon0;
+ u32 dsi_phy_timecon1;
+ u32 dsi_phy_timecon2;
+ u32 dsi_phy_timecon3;
+ u8 reserved4[16];
+ u32 dsi_vm_cmd_con;
+ u8 reserved5[92];
+ u32 dsi_force_commit;
+ u8 reserved6[108];
+ u32 dsi_cmdq0;
+};
+
+check_member(dsi_regs, dsi_phy_lccon, 0x104);
+check_member(dsi_regs, dsi_phy_timecon3, 0x11c);
+check_member(dsi_regs, dsi_vm_cmd_con, 0x130);
+check_member(dsi_regs, dsi_force_commit, 0x190);
+check_member(dsi_regs, dsi_cmdq0, 0x200);
+static struct dsi_regs *const dsi = (void *)DSI_BASE;
+
+#define DELAY_CMD 0
+#define END_OF_TABLE 1
+#define INIT_GENENIC_CMD 2
+#define INIT_DCS_CMD 3
+
+struct lcm_init_table {
+ u32 cmd;
+ u32 len;
+ u8 data[64];
+};
+
+struct mtk_phy_timing {
+ u8 lpx;
+ u8 da_hs_prepare;
+ u8 da_hs_zero;
+ u8 da_hs_trail;
+
+ u8 ta_go;
+ u8 ta_sure;
+ u8 ta_get;
+ u8 da_hs_exit;
+
+ u8 clk_hs_zero;
+ u8 clk_hs_trail;
+
+ u8 clk_hs_prepare;
+ u8 clk_hs_post;
+ u8 clk_hs_exit;
+};
+
+/* DSI_INTSTA */
+enum {
+ LPRX_RD_RDY_INT_FLAG = BIT(0),
+ CMD_DONE_INT_FLAG = BIT(1),
+ TE_RDY_INT_FLAG = BIT(2),
+ VM_DONE_INT_FLAG = BIT(3),
+ EXT_TE_RDY_INT_FLAG = BIT(4),
+ DSI_BUSY = BIT(31),
+};
+
+/* DSI_CON_CTRL */
+enum {
+ DSI_RESET = BIT(0),
+ DSI_EN = BIT(1),
+ DSI_DUAL = BIT(4),
+};
+
+/* DSI_MODE_CTRL */
+enum {
+ MODE = 3,
+ CMD_MODE = 0,
+ SYNC_PULSE_MODE = 1,
+ SYNC_EVENT_MODE = 2,
+ BURST_MODE = 3,
+ FRM_MODE = BIT(16),
+ MIX_MODE = BIT(17)
+};
+
+/* DSI_PSCTRL */
+enum {
+ DSI_PS_WC = 0x3fff,
+ DSI_PS_SEL = (3 << 16),
+ PACKED_PS_16BIT_RGB565 = (0 << 16),
+ LOOSELY_PS_18BIT_RGB666 = (1 << 16),
+ PACKED_PS_18BIT_RGB666 = (2 << 16),
+ PACKED_PS_24BIT_RGB888 = (3 << 16)
+};
+
+/* DSI_CMDQ_SIZE */
+enum {
+ CMDQ_SIZE = 0x3f,
+};
+
+/* DSI_PHY_LCCON */
+enum {
+ LC_HS_TX_EN = BIT(0),
+ LC_ULPM_EN = BIT(1),
+ LC_WAKEUP_EN = BIT(2)
+};
+
+/*DSI_PHY_LD0CON */
+enum {
+ LD0_RM_TRIG_EN = BIT(0),
+ LD0_ULPM_EN = BIT(1),
+ LD0_WAKEUP_EN = BIT(2)
+};
+
+enum {
+ LPX = (0xff << 0),
+ HS_PRPR = (0xff << 8),
+ HS_ZERO = (0xff << 16),
+ HS_TRAIL = (0xff << 24)
+};
+
+enum {
+ TA_GO = (0xff << 0),
+ TA_SURE = (0xff << 8),
+ TA_GET = (0xff << 16),
+ DA_HS_EXIT = (0xff << 24)
+};
+
+enum {
+ CONT_DET = (0xff << 0),
+ CLK_ZERO = (0xf << 16),
+ CLK_TRAIL = (0xff << 24)
+};
+
+enum {
+ CLK_HS_PRPR = (0xff << 0),
+ CLK_HS_POST = (0xff << 8),
+ CLK_HS_EXIT = (0xf << 16)
+};
+
+/* DSI_VM_CMD_CON */
+enum {
+ VM_CMD_EN = BIT(0),
+ TS_VFP_EN = BIT(5),
+};
+
+/* DSI_CMDQ0 */
+enum {
+ CONFIG = (0xff << 0),
+ SHORT_PACKET = 0,
+ LONG_PACKET = 2,
+ BTA = BIT(2),
+ DATA_ID = (0xff << 8),
+ DATA_0 = (0xff << 16),
+ DATA_1 = (0xff << 24),
+};
+
+#define MIPITX_LANE_CON 0x000c
+#define MIPITX_PLL_PWR 0x0028
+#define MIPITX_PLL_CON0 0x002c
+#define MIPITX_PLL_CON1 0x0030
+#define MIPITX_PLL_CON2 0x0034
+#define MIPITX_PLL_CON3 0x0038
+#define MIPITX_PLL_CON4 0x003c
+#define MIPITX_D2_SW_CTL_EN 0x0144
+#define MIPITX_D0_SW_CTL_EN 0x0244
+#define MIPITX_CK_CKMODE_EN 0x0328
+#define DSI_CK_CKMODE_EN BIT(0)
+#define MIPITX_CK_SW_CTL_EN 0x0344
+#define MIPITX_D1_SW_CTL_EN 0x0444
+#define MIPITX_D3_SW_CTL_EN 0x0544
+#define DSI_SW_CTL_EN BIT(0)
+#define AD_DSI_PLL_SDM_PWR_ON BIT(0)
+#define AD_DSI_PLL_SDM_ISO_EN BIT(1)
+
+#define RG_DSI_PLL_EN BIT(4)
+#define RG_DSI_PLL_POSDIV (0x7 << 8)
+
+/* MIPITX_REG */
+struct mipi_tx_regs {
+ u32 dsi_con;
+ u32 dsi_clock_lane;
+ u32 dsi_data_lane[4];
+ u8 reserved0[40];
+ u32 dsi_top_con;
+ u32 dsi_bg_con;
+ u8 reserved1[8];
+ u32 dsi_pll_con0;
+ u32 dsi_pll_con1;
+ u32 dsi_pll_con2;
+ u32 dsi_pll_con3;
+ u32 dsi_pll_chg;
+ u32 dsi_pll_top;
+ u32 dsi_pll_pwr;
+ u8 reserved2[4];
+ u32 dsi_rgs;
+ u32 dsi_gpi_en;
+ u32 dsi_gpi_pull;
+ u32 dsi_phy_sel;
+ u32 dsi_sw_ctrl_en;
+ u32 dsi_sw_ctrl_con0;
+ u32 dsi_sw_ctrl_con1;
+ u32 dsi_sw_ctrl_con2;
+ u32 dsi_dbg_con;
+ u32 dsi_dbg_out;
+ u32 dsi_apb_async_sta;
+};
+
+check_member(mipi_tx_regs, dsi_top_con, 0x40);
+check_member(mipi_tx_regs, dsi_pll_pwr, 0x68);
+
+static void *const mipi_tx = (void *)MIPITX_BASE;
+
+/* MIPITX_DSI_CON */
+enum {
+ RG_DSI_LDOCORE_EN = BIT(0),
+ RG_DSI_CKG_LDOOUT_EN = BIT(1),
+ RG_DSI_BCLK_SEL = (3 << 2),
+ RG_DSI_LD_IDX_SEL = (7 << 4),
+ RG_DSI_PHYCLK_SEL = (2 << 8),
+ RG_DSI_DSICLK_FREQ_SEL = BIT(10),
+ RG_DSI_LPTX_CLMP_EN = BIT(11)
+};
+
+/* MIPITX_DSI_CLOCK_LANE */
+enum {
+ LDOOUT_EN = BIT(0),
+ CKLANE_EN = BIT(1),
+ IPLUS1 = BIT(2),
+ LPTX_IPLUS2 = BIT(3),
+ LPTX_IMINUS = BIT(4),
+ LPCD_IPLUS = BIT(5),
+ LPCD_IMLUS = BIT(6),
+ RT_CODE = (0xf << 8)
+};
+
+/* MIPITX_DSI_TOP_CON */
+enum {
+ RG_DSI_LNT_INTR_EN = BIT(0),
+ RG_DSI_LNT_HS_BIAS_EN = BIT(1),
+ RG_DSI_LNT_IMP_CAL_EN = BIT(2),
+ RG_DSI_LNT_TESTMODE_EN = BIT(3),
+ RG_DSI_LNT_IMP_CAL_CODE = (0xf << 4),
+ RG_DSI_LNT_AIO_SEL = (7 << 8),
+ RG_DSI_PAD_TIE_LOW_EN = BIT(11),
+ RG_DSI_DEBUG_INPUT_EN = BIT(12),
+ RG_DSI_PRESERVE = (7 << 13)
+};
+
+/* MIPITX_DSI_BG_CON */
+enum {
+ RG_DSI_BG_CORE_EN = BIT(0),
+ RG_DSI_BG_CKEN = BIT(1),
+ RG_DSI_BG_DIV = (0x3 << 2),
+ RG_DSI_BG_FAST_CHARGE = BIT(4),
+ RG_DSI_V12_SEL = (7 << 5),
+ RG_DSI_V10_SEL = (7 << 8),
+ RG_DSI_V072_SEL = (7 << 11),
+ RG_DSI_V04_SEL = (7 << 14),
+ RG_DSI_V032_SEL = (7 << 17),
+ RG_DSI_V02_SEL = (7 << 20),
+ rsv_23 = BIT(23),
+ RG_DSI_BG_R1_TRIM = (0xf << 24),
+ RG_DSI_BG_R2_TRIM = (0xf << 28)
+};
+
+/* MIPITX_DSI_PLL_CON0 */
+enum {
+ RG_DSI_MPPLL_PLL_EN = BIT(0),
+ RG_DSI_MPPLL_PREDIV = (3 << 1),
+ RG_DSI_MPPLL_TXDIV0 = (3 << 3),
+ RG_DSI_MPPLL_TXDIV1 = (3 << 5),
+ RG_DSI_MPPLL_POSDIV = (7 << 7),
+ RG_DSI_MPPLL_MONVC_EN = BIT(10),
+ RG_DSI_MPPLL_MONREF_EN = BIT(11),
+ RG_DSI_MPPLL_VOD_EN = BIT(12)
+};
+
+/* MIPITX_DSI_PLL_CON1 */
+enum {
+ RG_DSI_MPPLL_SDM_FRA_EN = BIT(0),
+ RG_DSI_MPPLL_SDM_SSC_PH_INIT = BIT(1),
+ RG_DSI_MPPLL_SDM_SSC_EN = BIT(2),
+ RG_DSI_MPPLL_SDM_SSC_PRD = (0xffff << 16)
+};
+
+/* MIPITX_DSI_PLL_PWR */
+enum {
+ RG_DSI_MPPLL_SDM_PWR_ON = BIT(0),
+ RG_DSI_MPPLL_SDM_ISO_EN = BIT(1),
+ RG_DSI_MPPLL_SDM_PWR_ACK = BIT(8)
+};
+
+/* MIPI DSI Processor-to-Peripheral transaction types */
+enum {
+ MIPI_DSI_V_SYNC_START = 0x01,
+ MIPI_DSI_V_SYNC_END = 0x11,
+ MIPI_DSI_H_SYNC_START = 0x21,
+ MIPI_DSI_H_SYNC_END = 0x31,
+
+ MIPI_DSI_COLOR_MODE_OFF = 0x02,
+ MIPI_DSI_COLOR_MODE_ON = 0x12,
+ MIPI_DSI_SHUTDOWN_PERIPHERAL = 0x22,
+ MIPI_DSI_TURN_ON_PERIPHERAL = 0x32,
+
+ MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM = 0x03,
+ MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM = 0x13,
+ MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM = 0x23,
+
+ MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM = 0x04,
+ MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM = 0x14,
+ MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM = 0x24,
+
+ MIPI_DSI_DCS_SHORT_WRITE = 0x05,
+ MIPI_DSI_DCS_SHORT_WRITE_PARAM = 0x15,
+
+ MIPI_DSI_DCS_READ = 0x06,
+
+ MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 0x37,
+
+ MIPI_DSI_END_OF_TRANSMISSION = 0x08,
+
+ MIPI_DSI_NULL_PACKET = 0x09,
+ MIPI_DSI_BLANKING_PACKET = 0x19,
+ MIPI_DSI_GENERIC_LONG_WRITE = 0x29,
+ MIPI_DSI_DCS_LONG_WRITE = 0x39,
+
+ MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 0x0c,
+ MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24 = 0x1c,
+ MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16 = 0x2c,
+
+ MIPI_DSI_PACKED_PIXEL_STREAM_30 = 0x0d,
+ MIPI_DSI_PACKED_PIXEL_STREAM_36 = 0x1d,
+ MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12 = 0x3d,
+
+ MIPI_DSI_PACKED_PIXEL_STREAM_16 = 0x0e,
+ MIPI_DSI_PACKED_PIXEL_STREAM_18 = 0x1e,
+ MIPI_DSI_PIXEL_STREAM_3BYTE_18 = 0x2e,
+ MIPI_DSI_PACKED_PIXEL_STREAM_24 = 0x3e,
+};
+
+/* MIPI DSI Peripheral-to-Processor transaction types */
+enum {
+ MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT = 0x02,
+ MIPI_DSI_RX_END_OF_TRANSMISSION = 0x08,
+ MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE = 0x11,
+ MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE = 0x12,
+ MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE = 0x1a,
+ MIPI_DSI_RX_DCS_LONG_READ_RESPONSE = 0x1c,
+ MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE = 0x21,
+ MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE = 0x22,
+};
+
+/* MIPI DCS commands */
+enum {
+ MIPI_DCS_NOP = 0x00,
+ MIPI_DCS_SOFT_RESET = 0x01,
+ MIPI_DCS_GET_DISPLAY_ID = 0x04,
+ MIPI_DCS_GET_RED_CHANNEL = 0x06,
+ MIPI_DCS_GET_GREEN_CHANNEL = 0x07,
+ MIPI_DCS_GET_BLUE_CHANNEL = 0x08,
+ MIPI_DCS_GET_DISPLAY_STATUS = 0x09,
+ MIPI_DCS_GET_POWER_MODE = 0x0A,
+ MIPI_DCS_GET_ADDRESS_MODE = 0x0B,
+ MIPI_DCS_GET_PIXEL_FORMAT = 0x0C,
+ MIPI_DCS_GET_DISPLAY_MODE = 0x0D,
+ MIPI_DCS_GET_SIGNAL_MODE = 0x0E,
+ MIPI_DCS_GET_DIAGNOSTIC_RESULT = 0x0F,
+ MIPI_DCS_ENTER_SLEEP_MODE = 0x10,
+ MIPI_DCS_EXIT_SLEEP_MODE = 0x11,
+ MIPI_DCS_ENTER_PARTIAL_MODE = 0x12,
+ MIPI_DCS_ENTER_NORMAL_MODE = 0x13,
+ MIPI_DCS_EXIT_INVERT_MODE = 0x20,
+ MIPI_DCS_ENTER_INVERT_MODE = 0x21,
+ MIPI_DCS_SET_GAMMA_CURVE = 0x26,
+ MIPI_DCS_SET_DISPLAY_OFF = 0x28,
+ MIPI_DCS_SET_DISPLAY_ON = 0x29,
+ MIPI_DCS_SET_COLUMN_ADDRESS = 0x2A,
+ MIPI_DCS_SET_PAGE_ADDRESS = 0x2B,
+ MIPI_DCS_WRITE_MEMORY_START = 0x2C,
+ MIPI_DCS_WRITE_LUT = 0x2D,
+ MIPI_DCS_READ_MEMORY_START = 0x2E,
+ MIPI_DCS_SET_PARTIAL_AREA = 0x30,
+ MIPI_DCS_SET_SCROLL_AREA = 0x33,
+ MIPI_DCS_SET_TEAR_OFF = 0x34,
+ MIPI_DCS_SET_TEAR_ON = 0x35,
+ MIPI_DCS_SET_ADDRESS_MODE = 0x36,
+ MIPI_DCS_SET_SCROLL_START = 0x37,
+ MIPI_DCS_EXIT_IDLE_MODE = 0x38,
+ MIPI_DCS_ENTER_IDLE_MODE = 0x39,
+ MIPI_DCS_SET_PIXEL_FORMAT = 0x3A,
+ MIPI_DCS_WRITE_MEMORY_CONTINUE = 0x3C,
+ MIPI_DCS_READ_MEMORY_CONTINUE = 0x3E,
+ MIPI_DCS_SET_TEAR_SCANLINE = 0x44,
+ MIPI_DCS_GET_SCANLINE = 0x45,
+ MIPI_DCS_READ_DDB_START = 0xA1,
+ MIPI_DCS_READ_DDB_CONTINUE = 0xA8,
+};
+
+#define MTK_DSI_HOST_IS_READ(type) \
+ ((type == MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM) || \
+ (type == MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM) || \
+ (type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM) || \
+ (type == MIPI_DSI_DCS_READ))
+
+extern int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, bool dual,
+ const struct edid *edid,
+ struct lcm_init_table *init_cmd,
+ u32 count);
+
+#endif
--
To view, visit https://review.coreboot.org/c/coreboot/+/33106
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I09d127ab491bca98f3a9c9b7d4ad4b09674c963d
Gerrit-Change-Number: 33106
Gerrit-PatchSet: 1
Gerrit-Owner: jitao shi <jitao.shi(a)mediatek.com>
Gerrit-MessageType: newchange
5 months, 4 weeks
- 3
- 6
Change in ...coreboot[master]: getac/p470: Let clang-format handle the coding style
by Patrick Georgi (Code Review)
Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31652
Change subject: getac/p470: Let clang-format handle the coding style
......................................................................
getac/p470: Let clang-format handle the coding style
Also make the format mandatory for the board.
Change-Id: Ib34af7c4db359e132b968fe8409580af05fba9e3
Signed-off-by: Patrick Georgi <pgeorgi(a)google.com>
---
A .clang-format-scope
M src/mainboard/getac/p470/acpi_tables.c
M src/mainboard/getac/p470/cstates.c
M src/mainboard/getac/p470/ec_oem.c
M src/mainboard/getac/p470/ec_oem.h
M src/mainboard/getac/p470/gpio.c
M src/mainboard/getac/p470/hda_verb.c
M src/mainboard/getac/p470/irq_tables.c
M src/mainboard/getac/p470/mainboard.c
M src/mainboard/getac/p470/mainboard.h
M src/mainboard/getac/p470/mptable.c
M src/mainboard/getac/p470/romstage.c
M src/mainboard/getac/p470/smihandler.c
13 files changed, 179 insertions(+), 136 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/31652/1
diff --git a/.clang-format-scope b/.clang-format-scope
new file mode 100644
index 0000000..96c588c
--- /dev/null
+++ b/.clang-format-scope
@@ -0,0 +1 @@
+src/mainboard/getac
diff --git a/src/mainboard/getac/p470/acpi_tables.c b/src/mainboard/getac/p470/acpi_tables.c
index 162c20a..460f345 100644
--- a/src/mainboard/getac/p470/acpi_tables.c
+++ b/src/mainboard/getac/p470/acpi_tables.c
@@ -33,7 +33,7 @@
gnvs->cmbp = 0x00;
}
-static long acpi_create_ecdt(acpi_ecdt_t * ecdt)
+static long acpi_create_ecdt(acpi_ecdt_t *ecdt)
{
/* Attention: Make sure these match the values from
* the DSDT's ec.asl
@@ -43,7 +43,7 @@
acpi_header_t *header = &(ecdt->header);
- memset((void *) ecdt, 0, ecdt_len);
+ memset((void *)ecdt, 0, ecdt_len);
/* fill out header fields */
memcpy(header->signature, "ECDT", 4);
@@ -61,7 +61,7 @@
ecdt->ec_control.addrl = 0x66;
ecdt->ec_control.addrh = 0;
- ecdt->ec_data.space_id = ACPI_ADDRESS_SPACE_IO; /* Memory */
+ ecdt->ec_data.space_id = ACPI_ADDRESS_SPACE_IO; /* Memory */
ecdt->ec_data.bit_width = 8;
ecdt->ec_data.bit_offset = 0;
ecdt->ec_data.addrl = 0x62;
@@ -73,14 +73,12 @@
strncpy((char *)ecdt->ec_id, ec_id, strlen(ec_id));
- header->checksum =
- acpi_checksum((void *) ecdt, ecdt_len);
+ header->checksum = acpi_checksum((void *)ecdt, ecdt_len);
return header->length;
}
-unsigned long mainboard_write_acpi_tables(struct device *device,
- unsigned long start,
+unsigned long mainboard_write_acpi_tables(struct device *device, unsigned long start,
acpi_rsdp_t *rsdp)
{
unsigned long current;
diff --git a/src/mainboard/getac/p470/cstates.c b/src/mainboard/getac/p470/cstates.c
index 38b0d30..2f1f815 100644
--- a/src/mainboard/getac/p470/cstates.c
+++ b/src/mainboard/getac/p470/cstates.c
@@ -16,21 +16,21 @@
#include <southbridge/intel/i82801gx/i82801gx.h>
static acpi_cstate_t cst_entries[] = {
- {
- /* ACPI C1 / CPU C1 */
- 1, 0x01, 1000,
- { ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0, 0 }
- },
- {
- /* ACPI C2 / CPU C2 */
- 2, 0x01, 500,
- { ACPI_ADDRESS_SPACE_IO, 8, 0, { 0 }, DEFAULT_PMBASE + LV2, 0 }
- },
- {
- /* ACPI C3 / CPU C2 */
- 2, 0x11, 250,
- { ACPI_ADDRESS_SPACE_IO, 8, 0, { 0 }, DEFAULT_PMBASE + LV3, 0 }
- },
+ {/* ACPI C1 / CPU C1 */
+ 1,
+ 0x01,
+ 1000,
+ {ACPI_ADDRESS_SPACE_FIXED, 1, 2, {1}, 0, 0}},
+ {/* ACPI C2 / CPU C2 */
+ 2,
+ 0x01,
+ 500,
+ {ACPI_ADDRESS_SPACE_IO, 8, 0, {0}, DEFAULT_PMBASE + LV2, 0}},
+ {/* ACPI C3 / CPU C2 */
+ 2,
+ 0x11,
+ 250,
+ {ACPI_ADDRESS_SPACE_IO, 8, 0, {0}, DEFAULT_PMBASE + LV3, 0}},
};
int get_cst_entries(acpi_cstate_t **entries)
diff --git a/src/mainboard/getac/p470/ec_oem.c b/src/mainboard/getac/p470/ec_oem.c
index 8740167..49b7274 100644
--- a/src/mainboard/getac/p470/ec_oem.c
+++ b/src/mainboard/getac/p470/ec_oem.c
@@ -32,7 +32,7 @@
}
if (!timeout) {
printk(BIOS_DEBUG, "Timeout while sending OEM command 0x%02x to EC!\n",
- command);
+ command);
// return -1;
}
@@ -51,8 +51,7 @@
printk(BIOS_SPEW, ".");
}
if (!timeout) {
- printk(BIOS_DEBUG, "Timeout while sending OEM data 0x%02x to EC!\n",
- data);
+ printk(BIOS_DEBUG, "Timeout while sending OEM data 0x%02x to EC!\n", data);
// return -1;
}
@@ -112,12 +111,18 @@
{
u8 ec_sc = inb(EC_OEM_SC);
printk(BIOS_DEBUG, "Embedded Controller Status: ");
- if (ec_sc & (1 << 6)) printk(BIOS_DEBUG, "SMI_EVT ");
- if (ec_sc & (1 << 5)) printk(BIOS_DEBUG, "SCI_EVT ");
- if (ec_sc & (1 << 4)) printk(BIOS_DEBUG, "BURST ");
- if (ec_sc & (1 << 3)) printk(BIOS_DEBUG, "CMD ");
- if (ec_sc & (1 << 1)) printk(BIOS_DEBUG, "IBF ");
- if (ec_sc & (1 << 0)) printk(BIOS_DEBUG, "OBF ");
+ if (ec_sc & (1 << 6))
+ printk(BIOS_DEBUG, "SMI_EVT ");
+ if (ec_sc & (1 << 5))
+ printk(BIOS_DEBUG, "SCI_EVT ");
+ if (ec_sc & (1 << 4))
+ printk(BIOS_DEBUG, "BURST ");
+ if (ec_sc & (1 << 3))
+ printk(BIOS_DEBUG, "CMD ");
+ if (ec_sc & (1 << 1))
+ printk(BIOS_DEBUG, "IBF ");
+ if (ec_sc & (1 << 0))
+ printk(BIOS_DEBUG, "OBF ");
printk(BIOS_DEBUG, "\n");
return ec_sc;
diff --git a/src/mainboard/getac/p470/ec_oem.h b/src/mainboard/getac/p470/ec_oem.h
index 5d56107..ba42d7e 100644
--- a/src/mainboard/getac/p470/ec_oem.h
+++ b/src/mainboard/getac/p470/ec_oem.h
@@ -17,23 +17,35 @@
#ifndef _MAINBOARD_EC_OEM_H
#define _MAINBOARD_EC_OEM_H
-#define EC_OEM_DATA 0x68
-#define EC_OEM_SC 0x6c
+#define EC_OEM_DATA 0x68
+#define EC_OEM_SC 0x6c
/* EC_SC input */
-#define EC_SMI_EVT (1 << 6) // 1: SMI event pending
-#define EC_SCI_EVT (1 << 5) // 1: SCI event pending
-#define EC_BURST (1 << 4) // controller is in burst mode
-#define EC_CMD (1 << 3) // 1: byte in data register is command
- // 0: byte in data register is data
-#define EC_IBF (1 << 1) // 1: input buffer full (data ready for ec)
-#define EC_OBF (1 << 0) // 1: output buffer full (data ready for host)
+// 1: SMI event pending
+#define EC_SMI_EVT (1 << 6)
+
+// 1: SCI event pending
+#define EC_SCI_EVT (1 << 5)
+
+// controller is in burst mode
+#define EC_BURST (1 << 4)
+
+// 1: byte in data register is command
+// 0: byte in data register is data
+#define EC_CMD (1 << 3)
+
+// 1: input buffer full (data ready for ec)
+#define EC_IBF (1 << 1)
+
+// 1: output buffer full (data ready for host)
+#define EC_OBF (1 << 0)
+
/* EC_SC output */
-#define RD_EC 0x80 // Read Embedded Controller
-#define WR_EC 0x81 // Write Embedded Controller
-#define BE_EC 0x82 // Burst Enable Embedded Controller
-#define BD_EC 0x83 // Burst Disable Embedded Controller
-#define QR_EC 0x84 // Query Embedded Controller
+#define RD_EC 0x80 // Read Embedded Controller
+#define WR_EC 0x81 // Write Embedded Controller
+#define BE_EC 0x82 // Burst Enable Embedded Controller
+#define BD_EC 0x83 // Burst Disable Embedded Controller
+#define QR_EC 0x84 // Query Embedded Controller
int send_ec_oem_command(u8 command);
int send_ec_oem_data(u8 data);
diff --git a/src/mainboard/getac/p470/gpio.c b/src/mainboard/getac/p470/gpio.c
index be52a86..2785bca 100644
--- a/src/mainboard/getac/p470/gpio.c
+++ b/src/mainboard/getac/p470/gpio.c
@@ -74,8 +74,7 @@
.gpio8 = GPIO_INVERT,
};
-static const struct pch_gpio_set1 pch_gpio_set1_blink = {
-};
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {};
static const struct pch_gpio_set2 pch_gpio_set2_mode = {
.gpio33 = GPIO_MODE_GPIO,
@@ -100,16 +99,18 @@
};
const struct pch_gpio_map mainboard_gpio_map = {
- .set1 = {
- .mode = &pch_gpio_set1_mode,
- .direction = &pch_gpio_set1_direction,
- .level = &pch_gpio_set1_level,
- .blink = &pch_gpio_set1_blink,
- .invert = &pch_gpio_set1_invert,
- },
- .set2 = {
- .mode = &pch_gpio_set2_mode,
- .direction = &pch_gpio_set2_direction,
- .level = &pch_gpio_set2_level,
- },
+ .set1 =
+ {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ },
+ .set2 =
+ {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ },
};
diff --git a/src/mainboard/getac/p470/hda_verb.c b/src/mainboard/getac/p470/hda_verb.c
index e858a35..1ec2205 100644
--- a/src/mainboard/getac/p470/hda_verb.c
+++ b/src/mainboard/getac/p470/hda_verb.c
@@ -17,9 +17,9 @@
const u32 cim_verb_data[] = {
/* coreboot specific header */
- 0x10ec0262, // Codec Vendor / Device ID: Realtek ALC262
- 0x10714700, // Subsystem ID
- 0x0000000d, // Number of jacks
+ 0x10ec0262, // Codec Vendor / Device ID: Realtek ALC262
+ 0x10714700, // Subsystem ID
+ 0x0000000d, // Number of jacks
/* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x10ec0000 */
AZALIA_SUBVENDOR(0x0, 0x10EC0000),
diff --git a/src/mainboard/getac/p470/irq_tables.c b/src/mainboard/getac/p470/irq_tables.c
index 06d1492..fa491bf 100644
--- a/src/mainboard/getac/p470/irq_tables.c
+++ b/src/mainboard/getac/p470/irq_tables.c
@@ -17,18 +17,19 @@
#include <arch/pirq_routing.h>
static const struct irq_routing_table intel_irq_routing_table = {
- PIRQ_SIGNATURE, /* u32 signature */
- PIRQ_VERSION, /* u16 version */
- 32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be total 18 devices on the bus */
- 0x00, /* Where the interrupt router lies (bus) */
- (0x1f << 3)|0x0, /* Where the interrupt router lies (dev) */
- 0, /* IRQs devoted exclusively to PCI usage */
- 0x8086, /* Vendor */
- 0x27b0, /* Device */
- 0, /* miniport */
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
- 0xf, /* u8 checksum. */
+ PIRQ_SIGNATURE, /* u32 signature */
+ PIRQ_VERSION, /* u16 version */
+ 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* There can be total 18 devices on the bus */
+ 0x00, /* Where the interrupt router lies (bus) */
+ (0x1f << 3) | 0x0, /* Where the interrupt router lies (dev) */
+ 0, /* IRQs devoted exclusively to PCI usage */
+ 0x8086, /* Vendor */
+ 0x27b0, /* Device */
+ 0, /* miniport */
+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
+ 0xf, /* u8 checksum. */
{
+ // clang-format off
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x00,(0x01 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe?
{0x00,(0x02 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA
@@ -48,8 +49,8 @@
{0x01,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet 8168
{0x02,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0},
{0x03,(0x00 << 3)|0x0, {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0},
- }
-};
+ // clang-format on
+ }};
unsigned long write_pirq_routing_table(unsigned long addr)
{
diff --git a/src/mainboard/getac/p470/mainboard.c b/src/mainboard/getac/p470/mainboard.c
index 5d271fd..0645424 100644
--- a/src/mainboard/getac/p470/mainboard.c
+++ b/src/mainboard/getac/p470/mainboard.c
@@ -25,7 +25,7 @@
#include "mainboard.h"
-#define MAX_LCD_BRIGHTNESS 0xd8
+#define MAX_LCD_BRIGHTNESS 0xd8
static void ec_enable(void)
{
@@ -77,7 +77,8 @@
static void mainboard_init(struct device *dev)
{
ec_enable();
- install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_TXT_STRETCH, 0, 3);
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
+ GMA_INT15_PANEL_FIT_TXT_STRETCH, 0, 3);
}
// mainboard_enable is executed as first thing after
diff --git a/src/mainboard/getac/p470/mainboard.h b/src/mainboard/getac/p470/mainboard.h
index 0e6b24c..d074960 100644
--- a/src/mainboard/getac/p470/mainboard.h
+++ b/src/mainboard/getac/p470/mainboard.h
@@ -13,6 +13,5 @@
struct acpi_rsdp;
-unsigned long mainboard_write_acpi_tables(struct device *device,
- unsigned long start,
+unsigned long mainboard_write_acpi_tables(struct device *device, unsigned long start,
struct acpi_rsdp *rsdp);
diff --git a/src/mainboard/getac/p470/mptable.c b/src/mainboard/getac/p470/mptable.c
index c00102d..80c33df 100644
--- a/src/mainboard/getac/p470/mptable.c
+++ b/src/mainboard/getac/p470/mptable.c
@@ -41,28 +41,42 @@
mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0);
/* Builtin devices on Bus 0 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x8, 0x2, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7d, 0x2, 0x13);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, 0x2, 0x17);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, 0x2, 0x13);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x76, 0x2, 0x12);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x77, 0x2, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x6c, 0x2, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x70, 0x2, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x71, 0x2, 0x11);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x8, 0x2,
+ 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x7d, 0x2,
+ 0x13);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x74, 0x2,
+ 0x17);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x75, 0x2,
+ 0x13);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x76, 0x2,
+ 0x12);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x77, 0x2,
+ 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x6c, 0x2,
+ 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x70, 0x2,
+ 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x71, 0x2,
+ 0x11);
/* Firewire 4:0.0 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x0, 0x2, 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x4, 0x0, 0x2,
+ 0x10);
// riser slot top 5:8.0
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x20, 0x2, 0x14);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x5, 0x20, 0x2,
+ 0x14);
// riser slot middle 5:9.0
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x24, 0x2, 0x15);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x5, 0x24, 0x2,
+ 0x15);
// riser slot bottom 5:a.0
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x28, 0x2, 0x16);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x5, 0x28, 0x2,
+ 0x16);
/* Onboard Ethernet */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2, 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2,
+ 0x10);
/* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
mptable_lintsrc(mc, isa_bus);
diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c
index 3f80664..a591307 100644
--- a/src/mainboard/getac/p470/romstage.c
+++ b/src/mainboard/getac/p470/romstage.c
@@ -36,18 +36,18 @@
printk(BIOS_SPEW, "\n Initializing drive bay...\n");
gpios = inl(DEFAULT_GPIOBASE + 0x38); // GPIO Level 2
- gpios |= (1 << 0); // GPIO33 = ODD
- gpios |= (1 << 1); // GPIO34 = IDE_RST#
- outl(gpios, DEFAULT_GPIOBASE + 0x38); /* GP_LVL2 */
+ gpios |= (1 << 0); // GPIO33 = ODD
+ gpios |= (1 << 1); // GPIO34 = IDE_RST#
+ outl(gpios, DEFAULT_GPIOBASE + 0x38); /* GP_LVL2 */
gpios = inl(DEFAULT_GPIOBASE + 0x0c); // GPIO Level
- gpios &= ~(1 << 13); // ??
- outl(gpios, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */
+ gpios &= ~(1 << 13); // ??
+ outl(gpios, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */
printk(BIOS_SPEW, "\n Initializing Ethernet NIC...\n");
gpios = inl(DEFAULT_GPIOBASE + 0x0c); // GPIO Level
- gpios &= ~(1 << 24); // Enable LAN Power
- outl(gpios, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */
+ gpios &= ~(1 << 24); // Enable LAN Power
+ outl(gpios, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */
}
static void ich7_enable_lpc(void)
@@ -61,9 +61,10 @@
// decode range
pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0007);
// decode range
- pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN
- | MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN | GAMEL_LPC_EN
- | FDD_LPC_EN| lpt_en | COMB_LPC_EN | COMA_LPC_EN);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN,
+ CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN
+ | GAMEL_LPC_EN | FDD_LPC_EN | lpt_en | COMB_LPC_EN
+ | COMA_LPC_EN);
// Enable 0x02e0 - 0x2ff
pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x001c02e1);
// Enable 0x600 - 0x6ff
@@ -93,7 +94,7 @@
{
unsigned int port = dev >> 8;
outb(reg, port);
- outb(val, port+1);
+ outb(val, port + 1);
}
static void early_superio_config(void)
@@ -103,15 +104,15 @@
dev = PNP_DEV(0x4e, 0x00);
pnp_enter_ext_func_mode(dev);
- pnp_write_register(dev, 0x02, 0x0e); // UART power
- pnp_write_register(dev, 0x1b, (0x3e8 >> 2)); // UART3 base
- pnp_write_register(dev, 0x1c, (0x2e8 >> 2)); // UART4 base
+ pnp_write_register(dev, 0x02, 0x0e); // UART power
+ pnp_write_register(dev, 0x1b, (0x3e8 >> 2)); // UART3 base
+ pnp_write_register(dev, 0x1c, (0x2e8 >> 2)); // UART4 base
pnp_write_register(dev, 0x1d, (5 << 4) | 11); // UART3,4 IRQ
- pnp_write_register(dev, 0x1e, 1); // no 32khz clock
- pnp_write_register(dev, 0x24, (0x3f8 >> 2)); // UART1 base
- pnp_write_register(dev, 0x28, (4 << 4) | 0); // UART1,2 IRQ
- pnp_write_register(dev, 0x2c, 0); // DMA0 FIR
- pnp_write_register(dev, 0x30, (0x600 >> 4)); // Runtime Register Block Base
+ pnp_write_register(dev, 0x1e, 1); // no 32khz clock
+ pnp_write_register(dev, 0x24, (0x3f8 >> 2)); // UART1 base
+ pnp_write_register(dev, 0x28, (4 << 4) | 0); // UART1,2 IRQ
+ pnp_write_register(dev, 0x2c, 0); // DMA0 FIR
+ pnp_write_register(dev, 0x30, (0x600 >> 4)); // Runtime Register Block Base
pnp_write_register(dev, 0x31, 0xce); // GPIO1 DIR
pnp_write_register(dev, 0x32, 0x00); // GPIO1 POL
@@ -144,8 +145,8 @@
static void rcba_config(void)
{
/* Set up virtual channel 0 */
- //RCBA32(0x0014) = 0x80000001;
- //RCBA32(0x001c) = 0x03128010;
+ // RCBA32(0x0014) = 0x80000001;
+ // RCBA32(0x001c) = 0x03128010;
/* Device 1f interrupt pin register */
RCBA32(D31IP) = 0x00042220;
diff --git a/src/mainboard/getac/p470/smihandler.c b/src/mainboard/getac/p470/smihandler.c
index 5a82044..ca95447 100644
--- a/src/mainboard/getac/p470/smihandler.c
+++ b/src/mainboard/getac/p470/smihandler.c
@@ -115,7 +115,7 @@
case 0xde:
printk(BIOS_DEBUG, "LAN power off\n");
reg32 = inl(DEFAULT_GPIOBASE + GP_LVL);
- reg32 |= (1 << 24); // Disable LAN Power
+ reg32 |= (1 << 24); // Disable LAN Power
outl(reg32, DEFAULT_GPIOBASE + GP_LVL);
break;
case 0xdf:
@@ -151,27 +151,37 @@
u8 reg8;
switch (hotkey) {
- case 0x3b: break; // Fn+F1
- case 0x3c: break; // Fn+F2
- case 0x3d: break; // Fn+F3
- case 0x3e: break; // Fn+F4
- case 0x3f: break; // Fn+F5
- case 0x40: // Fn+F6 (Decrease Display Brightness)
- reg8 = ec_read(0x17);
- reg8 = (reg8 > 8) ? (reg8 - 8) : 0;
- ec_write(0x17, reg8);
- return;
- case 0x41: // Fn+F7 (Increase Display Brightness)
- reg8 = ec_read(0x17);
- reg8 += 8;
- reg8 = (reg8 >= MAX_LCD_BRIGHTNESS) ? MAX_LCD_BRIGHTNESS : reg8;
- ec_write(0x17, reg8);
- return;
- case 0x42: break; // Fn+F8
- case 0x43: break; // Fn+F9
- case 0x44: break; // Fn+F10
- case 0x57: break; // Fn+F11
- case 0x58: break; // Fn+F12
+ case 0x3b: // Fn+F1
+ break;
+ case 0x3c: // Fn+F2
+ break;
+ case 0x3d: // Fn+F3
+ break;
+ case 0x3e: // Fn+F4
+ break;
+ case 0x3f: // Fn+F5
+ break;
+ case 0x40: // Fn+F6 (Decrease Display Brightness)
+ reg8 = ec_read(0x17);
+ reg8 = (reg8 > 8) ? (reg8 - 8) : 0;
+ ec_write(0x17, reg8);
+ return;
+ case 0x41: // Fn+F7 (Increase Display Brightness)
+ reg8 = ec_read(0x17);
+ reg8 += 8;
+ reg8 = (reg8 >= MAX_LCD_BRIGHTNESS) ? MAX_LCD_BRIGHTNESS : reg8;
+ ec_write(0x17, reg8);
+ return;
+ case 0x42: // Fn+F8
+ break;
+ case 0x43: // Fn+F9
+ break;
+ case 0x44: // Fn+F10
+ break;
+ case 0x57: // Fn+F11
+ break;
+ case 0x58: // Fn+F12
+ break;
}
printk(BIOS_DEBUG, "EC hotkey: %02x\n", hotkey);
}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ib34af7c4db359e132b968fe8409580af05fba9e3
Gerrit-Change-Number: 31652
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-MessageType: newchange
6 months
- 4
- 10
Change in ...coreboot[master]: mb/apple: Add MacBook Air 5,2 (A1466)
by Evgeny Zinoviev (Code Review)
Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32604
Change subject: mb/apple: Add MacBook Air 5,2 (A1466)
......................................................................
mb/apple: Add MacBook Air 5,2 (A1466)
This is WIP.
Change-Id: I1ebe6f87a8254871698be74f913b9d969d722447
Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io>
---
A src/mainboard/apple/macbookair5_2/Kconfig
A src/mainboard/apple/macbookair5_2/Kconfig.name
A src/mainboard/apple/macbookair5_2/Makefile.inc
A src/mainboard/apple/macbookair5_2/acpi/ec.asl
A src/mainboard/apple/macbookair5_2/acpi/platform.asl
A src/mainboard/apple/macbookair5_2/acpi/superio.asl
A src/mainboard/apple/macbookair5_2/acpi_tables.c
A src/mainboard/apple/macbookair5_2/board_info.txt
A src/mainboard/apple/macbookair5_2/devicetree.cb
A src/mainboard/apple/macbookair5_2/dsdt.asl
A src/mainboard/apple/macbookair5_2/gma-mainboard.ads
A src/mainboard/apple/macbookair5_2/gnvs.c
A src/mainboard/apple/macbookair5_2/gpio.c
A src/mainboard/apple/macbookair5_2/hda_verb.c
A src/mainboard/apple/macbookair5_2/mainboard.c
A src/mainboard/apple/macbookair5_2/romstage.c
A src/mainboard/apple/macbookair5_2/spd.bin
17 files changed, 843 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/32604/1
diff --git a/src/mainboard/apple/macbookair5_2/Kconfig b/src/mainboard/apple/macbookair5_2/Kconfig
new file mode 100644
index 0000000..853021f
--- /dev/null
+++ b/src/mainboard/apple/macbookair5_2/Kconfig
@@ -0,0 +1,55 @@
+if BOARD_APPLE_MACBOOKAIR5_2
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select BOARD_ROMSIZE_KB_8192
+ select EC_ACPI
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select INTEL_INT15
+ select NORTHBRIDGE_INTEL_IVYBRIDGE
+ select SERIRQ_CONTINUOUS_MODE
+ select SOUTHBRIDGE_INTEL_C216
+ select SYSTEM_TYPE_LAPTOP
+ select USE_NATIVE_RAMINIT
+ select MAINBOARD_HAS_LIBGFXINIT
+ select GFX_GMA_INTERNAL_IS_LVDS
+ select SERIRQ_CONTINUOUS_MODE
+
+config MAINBOARD_DIR
+ string
+ default apple/macbookair5_2
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "MacBookAir5,2"
+
+config VGA_BIOS_FILE
+ string
+ default "pci8086,0166.rom"
+
+config VGA_BIOS_ID
+ string
+ default "8086,0166"
+
+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+ hex
+ default 0x7270
+
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+ hex
+ default 0x8086
+
+config DRAM_RESET_GATE_GPIO # FIXME: check this
+ int
+ default 60
+
+config MAX_CPUS
+ int
+ default 8
+
+config MAINBOARD_SMBIOS_MANUFACTURER
+ string
+ default "Apple Inc."
+
+endif
diff --git a/src/mainboard/apple/macbookair5_2/Kconfig.name b/src/mainboard/apple/macbookair5_2/Kconfig.name
new file mode 100644
index 0000000..d8a1fbf
--- /dev/null
+++ b/src/mainboard/apple/macbookair5_2/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_APPLE_MACBOOKAIR5_2
+ bool "MacBookAir5,2"
diff --git a/src/mainboard/apple/macbookair5_2/Makefile.inc b/src/mainboard/apple/macbookair5_2/Makefile.inc
new file mode 100644
index 0000000..fd60338
--- /dev/null
+++ b/src/mainboard/apple/macbookair5_2/Makefile.inc
@@ -0,0 +1,7 @@
+romstage-y += gpio.c
+
+cbfs-files-y += spd.bin
+spd.bin-file := spd.bin
+spd.bin-type := spd
+
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/apple/macbookair5_2/acpi/ec.asl b/src/mainboard/apple/macbookair5_2/acpi/ec.asl
new file mode 100644
index 0000000..f70cb3d
--- /dev/null
+++ b/src/mainboard/apple/macbookair5_2/acpi/ec.asl
@@ -0,0 +1,20 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Device(EC)
+{
+ Name (_HID, EISAID("PNP0C09"))
+ Name (_UID, 0)
+ Name (_GPE, 23)
+/* FIXME: EC support */
+}
diff --git a/src/mainboard/apple/macbookair5_2/acpi/platform.asl b/src/mainboard/apple/macbookair5_2/acpi/platform.asl
new file mode 100644
index 0000000..a17c6ea
--- /dev/null
+++ b/src/mainboard/apple/macbookair5_2/acpi/platform.asl
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Method(_WAK,1)
+{
+ /* FIXME: EC support */
+ Return(Package(){0,0})
+}
+
+Method(_PTS,1)
+{
+ /* FIXME: EC support */
+}
diff --git a/src/mainboard/apple/macbookair5_2/acpi/superio.asl b/src/mainboard/apple/macbookair5_2/acpi/superio.asl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/apple/macbookair5_2/acpi/superio.asl
diff --git a/src/mainboard/apple/macbookair5_2/acpi_tables.c b/src/mainboard/apple/macbookair5_2/acpi_tables.c
new file mode 100644
index 0000000..c48f0bd
--- /dev/null
+++ b/src/mainboard/apple/macbookair5_2/acpi_tables.c
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/bd82x6x/nvs.h>
+
+/* FIXME: check this function. */
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+ /* Disable USB ports in S3 by default */
+ gnvs->s3u0 = 0;
+ gnvs->s3u1 = 0;
+
+ /* Disable USB ports in S5 by default */
+ gnvs->s5u0 = 0;
+ gnvs->s5u1 = 0;
+
+ // the lid is open by default.
+ gnvs->lids = 1;
+
+ gnvs->tcrt = 100;
+ gnvs->tpsv = 90;
+}
diff --git a/src/mainboard/apple/macbookair5_2/board_info.txt b/src/mainboard/apple/macbookair5_2/board_info.txt
new file mode 100644
index 0000000..cbd72ee
--- /dev/null
+++ b/src/mainboard/apple/macbookair5_2/board_info.txt
@@ -0,0 +1,6 @@
+Category: laptop
+ROM protocol: SPI
+Flashrom support: n
+ROM package: WSON-8
+ROM socketed: n
+Release year: 2012
diff --git a/src/mainboard/apple/macbookair5_2/devicetree.cb b/src/mainboard/apple/macbookair5_2/devicetree.cb
new file mode 100644
index 0000000..efc5ddb
--- /dev/null
+++ b/src/mainboard/apple/macbookair5_2/devicetree.cb
@@ -0,0 +1,119 @@
+chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did
+ register "gfx.did" = "{ 0x80000410, 0x80000320, 0x80000410, 0x80000410, 0x00000005 }"
+ #register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }"
+ register "gfx.link_frequency_270_mhz" = "0"
+ register "gfx.ndid" = "2"
+ register "gfx.use_spread_spectrum_clock" = "1"
+ register "gpu_cpu_backlight" = "0x00000710"
+ register "gpu_dp_b_hotplug" = "4"
+ register "gpu_dp_c_hotplug" = "4"
+ register "gpu_dp_d_hotplug" = "4"
+ register "gpu_panel_port_select" = "1"
+ register "gpu_panel_power_backlight_off_delay" = "2000"
+ register "gpu_panel_power_backlight_on_delay" = "10"
+ register "gpu_panel_power_cycle_delay" = "6"
+ register "gpu_panel_power_down_delay" = "740"
+ register "gpu_panel_power_up_delay" = "2000"
+ register "gpu_pch_backlight" = "0x07100710"
+ device cpu_cluster 0x0 on
+ chip cpu/intel/model_206ax # FIXME: check all registers
+ register "c1_acpower" = "1"
+ register "c1_battery" = "1"
+ register "c2_acpower" = "3"
+ register "c2_battery" = "3"
+ register "c3_acpower" = "5"
+ register "c3_battery" = "5"
+ device lapic 0x0 on end
+ device lapic 0xacac off end
+ end
+ end
+
+ register "pci_mmio_size" = "2048"
+
+ device domain 0x0 on
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+ register "c2_latency" = "0x0065"
+ register "docking_supported" = "0"
+ register "gen1_dec" = "0x000c0681"
+ register "gen2_dec" = "0x000c1641"
+ register "gen3_dec" = "0x001c0301"
+ register "gen4_dec" = "0x00fc0701"
+ register "gpi7_routing" = "2"
+ register "p_cnt_throttling_supported" = "1"
+ register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
+ register "pcie_port_coalesce" = "1"
+ register "sata_interface_speed_support" = "0x3"
+ register "sata_port_map" = "0x1"
+ register "spi_lvscc" = "0x0"
+ register "spi_uvscc" = "0x2005"
+ register "superspeed_capable_ports" = "0x0000000f"
+ register "xhci_overcurrent_mapping" = "0x08040201"
+ register "xhci_switchable_ports" = "0x0000000f"
+ device pci 14.0 on # USB 3.0 Controller
+ subsystemid 0x8086 0x7270
+ end
+ device pci 16.0 on # Management Engine Interface 1
+ subsystemid 0x8086 0x7270
+ end
+ device pci 16.1 off # Management Engine Interface 2
+ end
+ device pci 16.2 off # Management Engine IDE-R
+ end
+ device pci 16.3 off # Management Engine KT
+ end
+ device pci 19.0 off # Intel Gigabit Ethernet
+ end
+ device pci 1a.0 on # USB2 EHCI #2
+ subsystemid 0x8086 0x7270
+ end
+ device pci 1b.0 on # High Definition Audio Audio controller
+ subsystemid 0x8086 0x7270
+ end
+ device pci 1c.0 on # PCIe Port #1
+ subsystemid 0x8086 0x7270
+ end
+ device pci 1c.1 on # PCIe Port #2
+ subsystemid 0x8086 0x7270
+ end
+ device pci 1c.2 off # PCIe Port #3
+ end
+ device pci 1c.3 off # PCIe Port #4
+ end
+ device pci 1c.4 on # PCIe Port #5
+ subsystemid 0x8086 0x7270
+ end
+ device pci 1c.5 off # PCIe Port #6
+ end
+ device pci 1c.6 off # PCIe Port #7
+ end
+ device pci 1c.7 off # PCIe Port #8
+ end
+ device pci 1d.0 on # USB2 EHCI #1
+ subsystemid 0x8086 0x7270
+ end
+ device pci 1e.0 off # PCI bridge
+ end
+ device pci 1f.0 on # LPC bridge PCI-LPC bridge
+ subsystemid 0x8086 0x7270
+ end
+ device pci 1f.2 on # SATA Controller 1
+ subsystemid 0x8086 0x7270
+ end
+ device pci 1f.3 on # SMBus
+ subsystemid 0x8086 0x7270
+ end
+ device pci 1f.5 off # SATA Controller 2
+ end
+ device pci 1f.6 off # Thermal
+ end
+ end
+ device pci 00.0 on # Host bridge Host bridge
+ subsystemid 0x106b 0x00fe
+ end
+ device pci 01.0 off # PCIe Bridge for discrete graphics
+ end
+ device pci 02.0 on # Internal graphics VGA controller
+ subsystemid 0x106b 0x00fe
+ end
+ end
+end
diff --git a/src/mainboard/apple/macbookair5_2/dsdt.asl b/src/mainboard/apple/macbookair5_2/dsdt.asl
new file mode 100644
index 0000000..455ac17
--- /dev/null
+++ b/src/mainboard/apple/macbookair5_2/dsdt.asl
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
+#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
+
+#include <arch/acpi.h>
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, // DSDT revision: ACPI 2.0 and up
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20141018 // OEM revision
+)
+{
+ /* Some generic macros */
+ #include "acpi/platform.asl"
+ #include <cpu/intel/common/acpi/cpu.asl>
+ #include <southbridge/intel/bd82x6x/acpi/platform.asl>
+ /* global NVS and variables. */
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+ #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
+
+ Device (\_SB.PCI0)
+ {
+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
+ }
+}
diff --git a/src/mainboard/apple/macbookair5_2/gma-mainboard.ads b/src/mainboard/apple/macbookair5_2/gma-mainboard.ads
new file mode 100644
index 0000000..d4a5d7d
--- /dev/null
+++ b/src/mainboard/apple/macbookair5_2/gma-mainboard.ads
@@ -0,0 +1,34 @@
+--
+-- This file is part of the coreboot project.
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ ports : constant Port_List :=
+ (DP1,
+ DP2,
+ DP3,
+ HDMI1,
+ HDMI2,
+ HDMI3,
+ Analog,
+ Internal,
+ others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/apple/macbookair5_2/gnvs.c b/src/mainboard/apple/macbookair5_2/gnvs.c
new file mode 100644
index 0000000..def9e5f
--- /dev/null
+++ b/src/mainboard/apple/macbookair5_2/gnvs.c
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/bd82x6x/nvs.h>
+
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+ /* Disable USB ports in S3 by default */
+ gnvs->s3u0 = 0;
+ gnvs->s3u1 = 0;
+
+ /* Disable USB ports in S5 by default */
+ gnvs->s5u0 = 0;
+ gnvs->s5u1 = 0;
+
+ /* the lid is open by default. */
+ gnvs->lids = 1;
+
+ gnvs->tcrt = 100;
+ gnvs->tpsv = 90;
+}
diff --git a/src/mainboard/apple/macbookair5_2/gpio.c b/src/mainboard/apple/macbookair5_2/gpio.c
new file mode 100644
index 0000000..9f2cd14
--- /dev/null
+++ b/src/mainboard/apple/macbookair5_2/gpio.c
@@ -0,0 +1,242 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio1 = GPIO_MODE_GPIO,
+ .gpio2 = GPIO_MODE_GPIO,
+ .gpio3 = GPIO_MODE_GPIO,
+ .gpio4 = GPIO_MODE_GPIO,
+ .gpio5 = GPIO_MODE_GPIO,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_NATIVE,
+ .gpio10 = GPIO_MODE_GPIO,
+ .gpio11 = GPIO_MODE_GPIO,
+ .gpio12 = GPIO_MODE_GPIO,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_GPIO,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio16 = GPIO_MODE_GPIO,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_NATIVE,
+ .gpio19 = GPIO_MODE_GPIO,
+ .gpio20 = GPIO_MODE_NATIVE,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio23 = GPIO_MODE_GPIO,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_NATIVE,
+ .gpio26 = GPIO_MODE_GPIO,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_GPIO,
+ .gpio30 = GPIO_MODE_NATIVE,
+ .gpio31 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT,
+ .gpio1 = GPIO_DIR_INPUT,
+ .gpio2 = GPIO_DIR_INPUT,
+ .gpio3 = GPIO_DIR_INPUT,
+ .gpio4 = GPIO_DIR_INPUT,
+ .gpio5 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_OUTPUT,
+ .gpio10 = GPIO_DIR_INPUT,
+ .gpio11 = GPIO_DIR_INPUT,
+ .gpio12 = GPIO_DIR_OUTPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio14 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_OUTPUT,
+ .gpio16 = GPIO_DIR_OUTPUT,
+ .gpio17 = GPIO_DIR_INPUT,
+ .gpio19 = GPIO_DIR_OUTPUT,
+ .gpio21 = GPIO_DIR_OUTPUT,
+ .gpio22 = GPIO_DIR_OUTPUT,
+ .gpio23 = GPIO_DIR_OUTPUT,
+ .gpio24 = GPIO_DIR_OUTPUT,
+ .gpio26 = GPIO_DIR_INPUT,
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_OUTPUT,
+ .gpio29 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio8 = GPIO_LEVEL_HIGH,
+ .gpio12 = GPIO_LEVEL_LOW,
+ .gpio15 = GPIO_LEVEL_HIGH,
+ .gpio16 = GPIO_LEVEL_LOW,
+ .gpio19 = GPIO_LEVEL_HIGH,
+ .gpio21 = GPIO_LEVEL_LOW,
+ .gpio22 = GPIO_LEVEL_LOW,
+ .gpio23 = GPIO_LEVEL_HIGH,
+ .gpio24 = GPIO_LEVEL_LOW,
+ .gpio28 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+ .gpio11 = GPIO_RESET_RSMRST,
+ .gpio15 = GPIO_RESET_RSMRST,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio1 = GPIO_INVERT,
+ .gpio2 = GPIO_INVERT,
+ .gpio4 = GPIO_INVERT,
+ .gpio5 = GPIO_INVERT,
+ .gpio7 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_NATIVE,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_GPIO,
+ .gpio36 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio40 = GPIO_MODE_NATIVE,
+ .gpio41 = GPIO_MODE_NATIVE,
+ .gpio42 = GPIO_MODE_NATIVE,
+ .gpio43 = GPIO_MODE_NATIVE,
+ .gpio44 = GPIO_MODE_NATIVE,
+ .gpio45 = GPIO_MODE_NATIVE,
+ .gpio46 = GPIO_MODE_NATIVE,
+ .gpio47 = GPIO_MODE_GPIO,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio50 = GPIO_MODE_GPIO,
+ .gpio51 = GPIO_MODE_GPIO,
+ .gpio52 = GPIO_MODE_GPIO,
+ .gpio53 = GPIO_MODE_GPIO,
+ .gpio54 = GPIO_MODE_GPIO,
+ .gpio55 = GPIO_MODE_GPIO,
+ .gpio56 = GPIO_MODE_GPIO,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_NATIVE,
+ .gpio60 = GPIO_MODE_GPIO,
+ .gpio61 = GPIO_MODE_NATIVE,
+ .gpio62 = GPIO_MODE_NATIVE,
+ .gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio33 = GPIO_DIR_INPUT,
+ .gpio34 = GPIO_DIR_OUTPUT,
+ .gpio35 = GPIO_DIR_OUTPUT,
+ .gpio36 = GPIO_DIR_OUTPUT,
+ .gpio37 = GPIO_DIR_INPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio47 = GPIO_DIR_INPUT,
+ .gpio48 = GPIO_DIR_OUTPUT,
+ .gpio49 = GPIO_DIR_OUTPUT,
+ .gpio50 = GPIO_DIR_INPUT,
+ .gpio51 = GPIO_DIR_OUTPUT,
+ .gpio52 = GPIO_DIR_OUTPUT,
+ .gpio53 = GPIO_DIR_OUTPUT,
+ .gpio54 = GPIO_DIR_OUTPUT,
+ .gpio55 = GPIO_DIR_OUTPUT,
+ .gpio56 = GPIO_DIR_INPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+ .gpio60 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio34 = GPIO_LEVEL_HIGH,
+ .gpio35 = GPIO_LEVEL_LOW,
+ .gpio36 = GPIO_LEVEL_LOW,
+ .gpio48 = GPIO_LEVEL_HIGH,
+ .gpio49 = GPIO_LEVEL_LOW,
+ .gpio51 = GPIO_LEVEL_HIGH,
+ .gpio52 = GPIO_LEVEL_LOW,
+ .gpio53 = GPIO_LEVEL_HIGH,
+ .gpio54 = GPIO_LEVEL_LOW,
+ .gpio55 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_GPIO,
+ .gpio65 = GPIO_MODE_GPIO,
+ .gpio66 = GPIO_MODE_GPIO,
+ .gpio67 = GPIO_MODE_GPIO,
+ .gpio68 = GPIO_MODE_GPIO,
+ .gpio69 = GPIO_MODE_GPIO,
+ .gpio70 = GPIO_MODE_GPIO,
+ .gpio71 = GPIO_MODE_GPIO,
+ .gpio72 = GPIO_MODE_NATIVE,
+ .gpio73 = GPIO_MODE_NATIVE,
+ .gpio74 = GPIO_MODE_GPIO,
+ .gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio64 = GPIO_DIR_OUTPUT,
+ .gpio65 = GPIO_DIR_OUTPUT,
+ .gpio66 = GPIO_DIR_OUTPUT,
+ .gpio67 = GPIO_DIR_OUTPUT,
+ .gpio68 = GPIO_DIR_INPUT,
+ .gpio69 = GPIO_DIR_INPUT,
+ .gpio70 = GPIO_DIR_INPUT,
+ .gpio71 = GPIO_DIR_INPUT,
+ .gpio74 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+ .gpio64 = GPIO_LEVEL_LOW,
+ .gpio65 = GPIO_LEVEL_LOW,
+ .gpio66 = GPIO_LEVEL_LOW,
+ .gpio67 = GPIO_LEVEL_LOW,
+ .gpio74 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/apple/macbookair5_2/hda_verb.c b/src/mainboard/apple/macbookair5_2/hda_verb.c
new file mode 100644
index 0000000..6c8e555
--- /dev/null
+++ b/src/mainboard/apple/macbookair5_2/hda_verb.c
@@ -0,0 +1,76 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x10134206, /* Codec Vendor / Device ID: Cirrus */
+ 0x106b5600, /* Subsystem ID */
+
+ 0x0000000b, /* Number of 4 dword sets */
+ /* NID 0x01: Subsystem ID. */
+ AZALIA_SUBVENDOR(0x0, 0x106b5600),
+
+ /* NID 0x09. */
+ AZALIA_PIN_CFG(0x0, 0x09, 0x0e2b4030),
+
+ /* NID 0x0a. */
+ AZALIA_PIN_CFG(0x0, 0x0a, 0x400000f0),
+
+ /* NID 0x0b. */
+ AZALIA_PIN_CFG(0x0, 0x0b, 0x90100120),
+
+ /* NID 0x0c. */
+ AZALIA_PIN_CFG(0x0, 0x0c, 0x400000f0),
+
+ /* NID 0x0d. */
+ AZALIA_PIN_CFG(0x0, 0x0d, 0x90a00110),
+
+ /* NID 0x0e. */
+ AZALIA_PIN_CFG(0x0, 0x0e, 0x400000f0),
+
+ /* NID 0x0f. */
+ AZALIA_PIN_CFG(0x0, 0x0f, 0x400000f0),
+
+ /* NID 0x10. */
+ AZALIA_PIN_CFG(0x0, 0x10, 0x400000f0),
+
+ /* NID 0x12. */
+ AZALIA_PIN_CFG(0x0, 0x12, 0x400000f0),
+
+ /* NID 0x15. */
+ AZALIA_PIN_CFG(0x0, 0x15, 0x400000f0),
+ 0x80862806, /* Codec Vendor / Device ID: Intel */
+ 0x80860101, /* Subsystem ID */
+
+ 0x00000004, /* Number of 4 dword sets */
+ /* NID 0x01: Subsystem ID. */
+ AZALIA_SUBVENDOR(0x3, 0x80860101),
+
+ /* NID 0x05. */
+ AZALIA_PIN_CFG(0x3, 0x05, 0x18560010),
+
+ /* NID 0x06. */
+ AZALIA_PIN_CFG(0x3, 0x06, 0x18560010),
+
+ /* NID 0x07. */
+ AZALIA_PIN_CFG(0x3, 0x07, 0x18560010),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/apple/macbookair5_2/mainboard.c b/src/mainboard/apple/macbookair5_2/mainboard.c
new file mode 100644
index 0000000..d497c51
--- /dev/null
+++ b/src/mainboard/apple/macbookair5_2/mainboard.c
@@ -0,0 +1,67 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/device.h>
+#include <drivers/intel/gma/int15.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <ec/acpi/ec.h>
+#include <console/console.h>
+
+static void mainboard_init(struct device *dev)
+{
+ /* FIXME: trim this down or remove if necessary */
+// {
+// int i;
+// const u8 dmp[256] = {
+// /* 00 */ 0x40, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+// /* 10 */ 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+// /* 20 */ 0x00, 0x80, 0x16, 0x16, 0xe0, 0x40, 0x4f, 0x4e, 0x7a, 0x34, 0x35, 0x31, 0x38, 0x31, 0x32, 0x44,
+// /* 30 */ 0x4b, 0x52, 0x4e, 0x41, 0x38, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x41, 0x42,
+// /* 40 */ 0x43, 0x44, 0x45, 0x00, 0x02, 0x14, 0x11, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+// /* 50 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+// /* 60 */ 0x03, 0x00, 0x00, 0x00, 0x0f, 0x3d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+// /* 70 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+// /* 80 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+// /* 90 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+// /* a0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+// /* b0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+// /* c0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+// /* d0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+// /* e0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+// /* f0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+// };
+//
+// printk(BIOS_DEBUG, "Replaying EC dump ...");
+// for (i = 0; i < 256; i++)
+// ec_write (i, dmp[i]);
+// printk(BIOS_DEBUG, "done\n");
+// }
+
+ RCBA32(0x38c8) = 0x00002005;
+ RCBA32(0x38c4) = 0x00800000;
+}
+
+static void mainboard_enable(struct device *dev)
+{
+ dev->ops->init = mainboard_init;
+
+// /* FIXME: fix those values*/
+// install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
+// GMA_INT15_PANEL_FIT_DEFAULT,
+// GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/apple/macbookair5_2/romstage.c b/src/mainboard/apple/macbookair5_2/romstage.c
new file mode 100644
index 0000000..6594b15
--- /dev/null
+++ b/src/mainboard/apple/macbookair5_2/romstage.c
@@ -0,0 +1,86 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* FIXME: Check if all includes are needed. */
+
+#include <stdint.h>
+#include <string.h>
+#include <timestamp.h>
+#include <arch/byteorder.h>
+#include <arch/io.h>
+#include <device/mmio.h>
+#include <device/pci_ops.h>
+#include <device/pnp_ops.h>
+#include <console/console.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/gpio.h>
+#include <cbfs.h>
+
+void pch_enable_lpc(void)
+{
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x40, 0x00000401);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0070);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x000c0681);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c1641);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x001c0301);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00fc0701);
+}
+
+void mainboard_rcba_config(void)
+{
+ RCBA32(0x3414) = 0x00000020;
+}
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+ { 1, 0, 0 },
+ { 1, 0, 1 },
+ { 1, 0, 2 },
+ { 1, 0, 3 },
+ { 1, 0, -1 },
+ { 1, 0, -1 },
+ { 1, 0, -1 },
+ { 1, 0, -1 },
+ { 1, 0, -1 },
+ { 1, 0, -1 },
+ { 1, 0, -1 },
+ { 1, 0, -1 },
+ { 1, 0, -1 },
+ { 1, 0, -1 },
+};
+
+void mainboard_early_init(int s3resume)
+{
+}
+
+void mainboard_config_superio(void)
+{
+}
+
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+{
+ void *spd_file;
+ size_t spd_file_len = 0;
+ spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,
+ &spd_file_len);
+ if (spd_file && spd_file_len >= 512) {
+ memcpy(&spd[0], spd_file, 128);
+ memcpy(&spd[2], spd_file + 256, 128);
+ }
+}
diff --git a/src/mainboard/apple/macbookair5_2/spd.bin b/src/mainboard/apple/macbookair5_2/spd.bin
new file mode 100644
index 0000000..2e2a6b4
--- /dev/null
+++ b/src/mainboard/apple/macbookair5_2/spd.bin
Binary files differ
--
To view, visit https://review.coreboot.org/c/coreboot/+/32604
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I1ebe6f87a8254871698be74f913b9d969d722447
Gerrit-Change-Number: 32604
Gerrit-PatchSet: 1
Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.com>
Gerrit-MessageType: newchange
6 months, 1 week
- 6
- 42
Change in ...coreboot[master]: SeaBIOS - unofficial patches: advanced_bootmenu and multiple_floppies
by mikeb mikeb (Code Review)
Hello Mike Banon,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/32351
to review the following change.
Change subject: SeaBIOS - unofficial patches: advanced_bootmenu and multiple_floppies
......................................................................
SeaBIOS - unofficial patches: advanced_bootmenu and multiple_floppies
If you'd like to add the useful floppies to your coreboot (read about them at
http://dangerousprototypes.com/docs/Lenovo_G505S_hacking#Useful_floppies ), or
to use your USB numpad for choosing a SeaBIOS boot entry, then this change is
for you! It contains two valuable patches together with a Makefile mod needed to
automatically apply these patches to a cloned SeaBIOS before its' compilation.
advanced_bootmenu: up to 35 entries (2 pages if >18), numpad support (console)
https://mail.coreboot.org/hyperkitty/list/seabios@seabios.org/thread/CKWLNT…
[PATCH v2] ramdisk: search for all available floppy images instead of one
https://mail.coreboot.org/pipermail/seabios/2018-December/012670.html
Patch descriptions are available at these links, and just in case here's a copy:
advanced_bootmenu: up to 35 entries (2 pages if >18), numpad support (console)
Add support for up to 35 boot menu entries (2 pages if >18). To solve the
">10" problem currently experienced by SeaBIOS users (there are no 11, 12, etc.
keys on a keyboard - so impossible to choose the last menu entries if you got
>10 entries because of multiple hard drives / secondary payloads / floppies)
- the boot menu has been extended to the letter keys. NOTE: TPM menu has been
moved from T to M letter: it is at the end of keyboard's 3rd row of letters and
"Trusted" is adjective while "Module" is a noun; alternatively could press '-'.
Also, add support for a numpad. Small USB numpad could be really convenient for
choosing the boot entries at coreboot boards used as (maybe headless) servers.
'/' char on numpad could be used to open the boot menu or to exit it. If there
are >10 boot menu entries - the numpad console interface will be enabled: press
one or two digit keys and then ENTER to confirm your choice, or remove a digit
by pressing the '.Del' key. Also you could call TPM with '-' key at any moment,
or boot with a single key press of your fullsize keyboard.
[PATCH v2] ramdisk: search for all available floppy images instead of one
All the floppy images available at CBFS will be found and listed in a boot menu,
instead of the first found. Could be highly valuable if you are participating in
a hobby OS development - would like to test multiple versions of your floppy at
the same coreboot image, to reduce the amount of re-flashes and accelerate the
development at bare metal - or simply you would like to access multiple floppies
as a coreboot user. For example: KolibriOS (nice assembly OS with GUI and apps),
FreeDOS, MichalOS, Snowdrop and memtest (coreboot's memtest version is buggy,
e.g. external USB keyboard isn't working at some laptops; floppy is much better)
Signed-off-by: Mike Banon <mikebdp2(a)gmail.com>
Change-Id: Idf4efba31091a8678b51c2f6541d440c5cc6d37d
---
M payloads/external/SeaBIOS/Makefile
A payloads/external/SeaBIOS/advanced_bootmenu.patch
A payloads/external/SeaBIOS/multiple_floppies.patch
3 files changed, 551 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/32351/1
diff --git a/payloads/external/SeaBIOS/Makefile b/payloads/external/SeaBIOS/Makefile
index e505c8c..ae58c8c 100644
--- a/payloads/external/SeaBIOS/Makefile
+++ b/payloads/external/SeaBIOS/Makefile
@@ -76,7 +76,18 @@
# echo "# CONFIG_SMBIOS is not set" >> seabios/.config
$(MAKE) -C seabios olddefconfig OUT=out/
-build: config
+patch:
+ if [ -d seabios ]; then \
+ cd seabios; \
+ if [ ! -f .patched ]; then \
+ echo " PATCH SeaBIOS $(TAG-y)"; \
+ patch -p1 < ./../advanced_bootmenu.patch; \
+ patch -p1 < ./../multiple_floppies.patch; \
+ touch .patched; \
+ fi; \
+ fi
+
+build: config patch
echo " MAKE SeaBIOS $(TAG-y)"
$(MAKE) -C seabios OUT=out/
diff --git a/payloads/external/SeaBIOS/advanced_bootmenu.patch b/payloads/external/SeaBIOS/advanced_bootmenu.patch
new file mode 100644
index 0000000..c914588
--- /dev/null
+++ b/payloads/external/SeaBIOS/advanced_bootmenu.patch
@@ -0,0 +1,332 @@
+diff --git a/src/boot.c b/src/boot.c
+index 9f82f3c..f94dd27 100644
+--- a/src/boot.c
++++ b/src/boot.c
+@@ -463,6 +463,7 @@ get_keystroke(int msec)
+ * Boot menu and BCV execution
+ ****************************************************************/
+
++#define BOOTMENU_PAGE_SIZE 18
+ #define DEFAULT_BOOTMENU_WAIT 2500
+
+ // Show IPL option menu.
+@@ -478,59 +479,282 @@ interactive_bootmenu(void)
+ ;
+
+ char *bootmsg = romfile_loadfile("etc/boot-menu-message", NULL);
+- int menukey = romfile_loadint("etc/boot-menu-key", 1);
+- printf("%s", bootmsg ?: "\nPress ESC for boot menu.\n\n");
++ int menukey = romfile_loadint("etc/boot-menu-key", 1); // custom menukey
++ printf("%s", bootmsg ?: "\nPress ESC or \\ / slash for boot menu.\n\n");
+ free(bootmsg);
+
+ u32 menutime = romfile_loadint("etc/boot-menu-wait", DEFAULT_BOOTMENU_WAIT);
+ enable_bootsplash();
+ int scan_code = get_keystroke(menutime);
+ disable_bootsplash();
+- if (scan_code != menukey)
++ if (scan_code != menukey && // custom menukey
++ scan_code != 1 && // ESC
++ scan_code != 43 && // '\' char on keyboard
++ scan_code != 53 && // '/' char on keyboard
++ scan_code != 98) { // '/' char on numpad
++ if (scan_code == -1)
++ printf("No key pressed.\n");
++ else
++ printf("Not a menukey pressed.\n");
+ return;
++ }
+
+ while (get_keystroke(0) >= 0)
+ ;
+
+- printf("Select boot device:\n\n");
+ wait_threads();
+
+- // Show menu items
++ char keyboard_keys[35] = {'1','2','3','4','5','6','7','8','9','0',
++ 'q','w','e','r','t','y','u','i','o','p',
++ 'a','s','d','f','g','h','j','k','l',
++ 'z','x','c','v','b','n'}; /* m = TPM */
++ int numpad_scancodes[10] = { 82, 79, 80, 81, 75, 76, 77, 71, 72, 73 };
++ int numpi = 0; // Key index: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9.
++ int digits = 0; // Numerical length of a current choice number.
++ int decode = 0; // Decode the current choice number into a letter?
++ int entry_id = 0;
++ char desc[77];
++
++ printf("Select boot device");
++
++ // Show menu items after counting them and determining a number of pages.
++ // Only 35 boot menu items (36 if to count a TPM) are supported currently.
++
+ int maxmenu = 0;
+ struct bootentry_s *pos;
+- hlist_for_each_entry(pos, &BootList, node) {
+- char desc[77];
++ hlist_for_each_entry(pos, &BootList, node)
+ maxmenu++;
+- printf("%d. %s\n", maxmenu
++
++ if (maxmenu > 10) {
++ if (maxmenu > 35)
++ maxmenu = 35;
++ if (maxmenu > BOOTMENU_PAGE_SIZE)
++ printf(" - page 1 :");
++ else
++ printf(": ");
++ printf(" // press ENTER after your numpad input");
++ if (maxmenu > BOOTMENU_PAGE_SIZE)
++ printf(" - if any -\n "
++ " // - or to switch between the pages...\n");
++ else
++ printf(" (if any)\n\n");
++ } else {
++ printf(":\n\n");
++ }
++
++ hlist_for_each_entry(pos, &BootList, node) {
++ if (entry_id == BOOTMENU_PAGE_SIZE) // Show only the first page.
++ break;
++ printf("%c. %s\n", keyboard_keys[entry_id]
+ , strtcpy(desc, pos->description, ARRAY_SIZE(desc)));
++ entry_id++;
+ }
++ int tpm_cshm = 0;
+ if (tpm_can_show_menu()) {
+- printf("\nt. TPM Configuration\n");
++ tpm_cshm = 1;
++ printf("\nm-. TPM Configuration");
+ }
+-
+- // Get key press. If the menu key is ESC, do not restart boot unless
+- // 1.5 seconds have passed. Otherwise users (trained by years of
+- // repeatedly hitting keys to enter the BIOS) will end up hitting ESC
+- // multiple times and immediately booting the primary boot device.
+- int esc_accepted_time = irqtimer_calc(menukey == 1 ? 1500 : 0);
++ printf("\n> ");
++
++ // Do not restart boot on menukey press, unless DEFAULT_BOOTMENU_WAIT msecs
++ // have passed. Otherwise users (trained by years of repeatedly hitting keys
++ // to enter the BIOS) will end up hitting menukey multiple times and
++ // immediately booting the primary boot device.
++ int esc_accepted_time = irqtimer_calc(DEFAULT_BOOTMENU_WAIT);
++ int choice = 0, kb_choice = 0;
++ int page_num = 1;
++ int enter = 0;
++ int backspace = 0;
++ int tpm_show_menu = 0;
+ for (;;) {
+ scan_code = get_keystroke(1000);
+- if (scan_code == 1 && !irqtimer_check(esc_accepted_time))
+- continue;
+- if (tpm_can_show_menu() && scan_code == 20 /* t */) {
++ if (scan_code == menukey || // custom menukey
++ scan_code == 1 || // ESC
++ scan_code == 43 || // '\' char on keyboard
++ scan_code == 53 || // '/' char on keyboard
++ scan_code == 98) { // '/' char on numpad
++ if (!irqtimer_check(esc_accepted_time))
++ continue;
++ if (digits == 2) // Remove the decoded "(*)"
++ printf(" \b\b\b");
++ /* Remove the existing input before printing a message. */
++ for (; digits > 0; digits--)
++ printf("\b \b");
++ printf("Menukey pressed.\n");
++ return;
++ }
++ kb_choice = 0;
++ /* 4 rows of keyboard_keys: 1 row with numbers, 3 rows with letters.
++ Use any of them to select a boot device (except the TPM 'm-' keys) */
++ // 1st range: 1-9 and 0 (10) keys <==> 2-11 scan codes <==> 1-10 choice
++ if (scan_code >= 2 && scan_code <= 11) kb_choice = scan_code - 1;
++ // 2nd range: Q-P row of letters <==> 16-25 scan codes <==> 11-20 choice
++ if (scan_code >= 16 && scan_code <= 25) kb_choice = scan_code - 5;
++ // 3rd range: A-L row of letters <==> 30-38 scan codes <==> 21-29 choice
++ if (scan_code >= 30 && scan_code <= 38) kb_choice = scan_code - 9;
++ // 4th range: Z-N row of letters <==> 44-49 scan codes <==> 30-35 choice
++ if (scan_code >= 44 && scan_code <= 49) kb_choice = scan_code - 14;
++ // ENTER: (28) on keyboard, (96) on numpad.
++ if (scan_code == 28 || scan_code == 96)
++ enter = 1;
++ // BCKSPC: '<-'(14) and 'Delete'(111) on keyboard, '.Del'(83) on numpad.
++ if (scan_code == 14 || scan_code == 111 || scan_code == 83)
++ backspace = 1;
++ // TPM keys: 'm'(50) and '-'(12) chars on keyboard, '-'(74) on numpad.
++ if ((scan_code == 50 || scan_code == 12 || scan_code == 74) && tpm_cshm)
++ tpm_show_menu = 1;
++
++ if (kb_choice != 0 || tpm_show_menu) {
++ if (kb_choice > maxmenu) {
++ if (!tpm_show_menu)
++ continue;
++ } else {
++ choice = kb_choice;
++ }
++ if (digits == 2) // Remove the decoded "(*)"
++ printf(" \b\b\b");
++ /* Remove the existing input before printing a choice. */
++ for (; digits > 0; digits--)
++ printf("\b \b");
++ if (!tpm_show_menu) {
++ // Choice is any of the detected boot devices ==> lets boot!
++ break;
++ }
++ } else {
++ // Internal/USB Numpad console interface.
++ if (digits < 9) {
++ for (numpi = 0; numpi < 10; numpi++) {
++ if (scan_code == numpad_scancodes[numpi]) {
++ if (maxmenu <= 10) { // Console interface is not needed.
++ if ((numpi != 0 && numpi <= maxmenu) ||
++ (numpi == 0 && 10 <= maxmenu)) { // 10(0)
++ choice = numpi;
++ enter = 1; // Fake ENTER to boot this entry now.
++ } else { // If no such an entry, don't try to boot.
++ break;
++ }
++ } else {
++ if (digits == 2) {
++ printf(" \b\b\b"); // Remove the decoded "(*)"
++ if (choice == 0) {
++ printf("\b\b \b\b"); // Remove "10".
++ digits = 0;
++ }
++ }
++ choice = 10 * choice + numpi;
++ }
++ if (choice > 0) {
++ printf("%d", numpi); // Print the entered digit.
++ digits++;
++ } else {
++ if (10 <= maxmenu)
++ printf("10(0)\b\b\b");
++ else
++ printf("10(?)\b\b\b");
++ digits = 2;
++ }
++ if (choice > 9 && digits == 2) // Decode into a letter.
++ decode = 1;
++ break;
++ }
++ }
++ }
++ if (backspace && digits > 0) {
++ backspace = 0;
++ choice = choice / 10;
++ if (digits == 2) {
++ printf(" \b\b\b"); // Remove the decoded "(*)"
++ // 0 turned into 10: one more Backspace is needed to remove.
++ if (choice == 0) {
++ printf("\b \b");
++ digits--;
++ }
++ }
++ printf("\b \b"); // Remove the last entered digit.
++ digits--;
++ if (choice > 9 && digits == 2) // Decode into a letter.
++ decode = 1;
++ }
++ if (decode) { // Decode the current choice number into a letter.
++ decode = 0;
++ if (choice <= maxmenu) {
++ printf("(%c)", keyboard_keys[choice-1]);
++ } else {
++ if (tpm_cshm && choice == 36)
++ printf("(m)"); // For TPM.
++ else
++ printf("(?)"); // No matching letter found.
++ }
++ printf("\b\b\b"); // Move a cursor before the "(*)"
++ }
++ }
++
++ if (enter) {
++ enter = 0;
++ if (choice == 0) {
++ if (digits == 2) { // for 0 that turned into 10
++ if (10 <= maxmenu)
++ break;
++ else
++ continue;
++ }
++ // If there are two pages - switch between them.
++ if (maxmenu > BOOTMENU_PAGE_SIZE) {
++ entry_id = 0;
++ page_num = 3 - page_num; // 3 - 1 = 2; 3 - 2 = 1.
++ printf("\n\nSelect boot device - page %d :"
++ " // press ENTER after your numpad input"
++ " - if any -\n "
++ " // - or to switch between the pages...\n",
++ page_num);
++ hlist_for_each_entry(pos, &BootList, node) {
++ if ((page_num == 1 && entry_id == BOOTMENU_PAGE_SIZE) ||
++ (page_num == 2 && entry_id == 35))
++ break;
++ if (page_num == 1 || entry_id >= BOOTMENU_PAGE_SIZE)
++ printf("%c. %s\n", keyboard_keys[entry_id],
++ strtcpy(desc, pos->description, ARRAY_SIZE(desc)));
++ entry_id++;
++ }
++ if (tpm_cshm)
++ printf("\nm-. TPM Configuration");
++ printf("\n> ");
++ }
++ } else {
++ if (choice > maxmenu) {
++ if (tpm_cshm && choice == 36)
++ tpm_show_menu = 1;
++ } else {
++ // Choice is any of the detected boot devices ==> lets boot!
++ break;
++ }
++ }
++ }
++
++ if (tpm_show_menu) {
++ tpm_show_menu = 0;
++ choice = 0;
++ if (digits == 0)
++ printf("TPM key pressed.");
++ else
++ digits = 0;
+ printf("\n");
+ tpm_menu();
++ printf("> ");
+ }
+- if (scan_code >= 1 && scan_code <= maxmenu+1)
+- break;
++ }
++
++ if (choice == 0) // 10(0)
++ choice = 10;
++
++ if (digits == 0 && choice < 36) {
++ printf("%c", keyboard_keys[choice-1]);
++ if (choice > 9) // Decode into a number.
++ printf("(%d)", choice);
+ }
+ printf("\n");
+- if (scan_code == 0x01)
+- // ESC
+- return;
+
+ // Find entry and make top priority.
+- int choice = scan_code - 1;
+ hlist_for_each_entry(pos, &BootList, node) {
+ if (! --choice)
+ break;
+diff --git a/src/config.h b/src/config.h
+index 93c8dbc..f85cc14 100644
+--- a/src/config.h
++++ b/src/config.h
+@@ -19,7 +19,7 @@
+ // Space to reserve in high-memory for tables
+ #define BUILD_MAX_HIGHTABLE (256*1024)
+ // Largest supported externaly facing drive id
+-#define BUILD_MAX_EXTDRIVE 16
++#define BUILD_MAX_EXTDRIVE 36
+ // Number of bytes the smbios may be and still live in the f-segment
+ #define BUILD_MAX_SMBIOS_FSEG 600
+ // Maximum number of bytes the mptable may be and still be copied to f-segment
diff --git a/payloads/external/SeaBIOS/multiple_floppies.patch b/payloads/external/SeaBIOS/multiple_floppies.patch
new file mode 100644
index 0000000..5249394
--- /dev/null
+++ b/payloads/external/SeaBIOS/multiple_floppies.patch
@@ -0,0 +1,207 @@
+diff --git a/src/block.h b/src/block.h
+index f64e880..aaa236f 100644
+--- a/src/block.h
++++ b/src/block.h
+@@ -2,7 +2,7 @@
+ #define __BLOCK_H
+
+ #include "types.h" // u32
+-
++#include "romfile.h" // struct romfile_s
+
+ /****************************************************************
+ * Disk command request
+@@ -48,6 +48,7 @@ struct drive_s {
+ struct drive_s {
+ u8 type; // Driver type (DTYPE_*)
+ u8 floppy_type; // Type of floppy (only for floppy drives).
++ struct romfile_s *floppy_file; // Floppy file (only for virtual floppies).
+ struct chs_s lchs; // Logical CHS
+ u64 sectors; // Total sectors count
+ u32 cntl_id; // Unique id for a given driver type.
+diff --git a/src/boot.c b/src/boot.c
+index 9f82f3c..79f1e7d 100644
+--- a/src/boot.c
++++ b/src/boot.c
+@@ -584,7 +584,7 @@ bcv_prepboot(void)
+ break;
+ case IPL_TYPE_FLOPPY:
+ map_floppy_drive(pos->drive);
+- add_bev(IPL_TYPE_FLOPPY, 0);
++ add_bev(IPL_TYPE_FLOPPY, (u32)pos->drive);
+ break;
+ case IPL_TYPE_HARDDISK:
+ map_hd_drive(pos->drive);
+@@ -733,6 +733,12 @@ do_boot(int seq_nr)
+ static void
+ do_boot(int seq_nr)
+ {
++
++ int ret;
++ void *pos;
++ struct romfile_s *file;
++ struct drive_s *drive;
++
+ if (! CONFIG_BOOT)
+ panic("Boot support not compiled in.\n");
+
+@@ -744,6 +750,16 @@ do_boot(int seq_nr)
+ switch (ie->type) {
+ case IPL_TYPE_FLOPPY:
+ printf("Booting from Floppy...\n");
++ drive = (struct drive_s *)ie->vector;
++ file = drive->floppy_file;
++ // File is NULL if a floppy is physical.
++ if (file) {
++ // Copy virtual floppy image into ram.
++ pos = (void *)drive->cntl_id;
++ ret = file->copy(file, pos, file->size);
++ if (ret < 0)
++ break;
++ }
+ boot_disk(0x00, CheckFloppySig);
+ break;
+ case IPL_TYPE_HARDDISK:
+diff --git a/src/hw/floppy.c b/src/hw/floppy.c
+index 9e6647d..5b37c6c 100644
+--- a/src/hw/floppy.c
++++ b/src/hw/floppy.c
+@@ -107,7 +107,7 @@ struct floppyinfo_s FloppyInfo[] VARFSEG = {
+ };
+
+ struct drive_s *
+-init_floppy(int floppyid, int ftype)
++init_floppy(int floppyid, int ftype, struct romfile_s *ffile)
+ {
+ if (ftype <= 0 || ftype >= ARRAY_SIZE(FloppyInfo)) {
+ dprintf(1, "Bad floppy type %d\n", ftype);
+@@ -124,6 +124,7 @@ init_floppy(int floppyid, int ftype)
+ drive->type = DTYPE_FLOPPY;
+ drive->blksize = DISK_SECTOR_SIZE;
+ drive->floppy_type = ftype;
++ drive->floppy_file = ffile;
+ drive->sectors = (u64)-1;
+
+ memcpy(&drive->lchs, &FloppyInfo[ftype].chs
+@@ -134,7 +135,7 @@ addFloppy(int floppyid, int ftype)
+ static void
+ addFloppy(int floppyid, int ftype)
+ {
+- struct drive_s *drive = init_floppy(floppyid, ftype);
++ struct drive_s *drive = init_floppy(floppyid, ftype, 0);
+ if (!drive)
+ return;
+ char *desc = znprintf(MAXDESCSIZE, "Floppy [drive %c]", 'A' + floppyid);
+diff --git a/src/hw/ramdisk.c b/src/hw/ramdisk.c
+index b9e9baa..a679385 100644
+--- a/src/hw/ramdisk.c
++++ b/src/hw/ramdisk.c
+@@ -23,40 +23,69 @@ ramdisk_setup(void)
+ if (!CONFIG_FLASH_FLOPPY)
+ return;
+
+- // Find image.
+- struct romfile_s *file = romfile_findprefix("floppyimg/", NULL);
+- if (!file)
+- return;
+- const char *filename = file->name;
+- u32 size = file->size;
+- dprintf(3, "Found floppy file %s of size %d\n", filename, size);
+- int ftype = find_floppy_type(size);
+- if (ftype < 0) {
+- dprintf(3, "No floppy type found for ramdisk size\n");
++ struct romfile_s *file = NULL;
++ char *filename, *desc;
++ u32 size, max_size = 0;
++ int ftype;
++ void *pos;
++ struct drive_s *drive;
++
++ // Find the max floppy size
++ for (;;) {
++ // Find the next image.
++ file = romfile_findprefix("floppyimg/", file);
++ if (!file)
++ break;
++ filename = file->name;
++ size = file->size;
++ dprintf(3, "Found floppy file %s of size %d\n", filename, size);
++ // Check if this size is valid.
++ ftype = find_floppy_type(size);
++ if (ftype < 0) {
++ dprintf(3, "No floppy type found for ramdisk size\n");
++ } else {
++ if (size > max_size)
++ max_size = size;
++ }
++ }
++ if (max_size == 0) {
++ dprintf(3, "No floppies found\n");
+ return;
+ }
+
+ // Allocate ram for image.
+- void *pos = memalign_tmphigh(PAGE_SIZE, size);
++ pos = memalign_tmphigh(PAGE_SIZE, max_size);
+ if (!pos) {
+ warn_noalloc();
+ return;
+ }
+- e820_add((u32)pos, size, E820_RESERVED);
++ e820_add((u32)pos, max_size, E820_RESERVED);
++ dprintf(3, "Allocate %u bytes for a floppy\n", max_size);
+
+- // Copy image into ram.
+- int ret = file->copy(file, pos, size);
+- if (ret < 0)
+- return;
+-
+- // Setup driver.
+- struct drive_s *drive = init_floppy((u32)pos, ftype);
+- if (!drive)
+- return;
+- drive->type = DTYPE_RAMDISK;
+- dprintf(1, "Mapping floppy %s to addr %p\n", filename, pos);
+- char *desc = znprintf(MAXDESCSIZE, "Ramdisk [%s]", &filename[10]);
+- boot_add_floppy(drive, desc, bootprio_find_named_rom(filename, 0));
++ // Setup the floppy drivers.
++ file = NULL;
++ for (;;) {
++ // Find the next image.
++ file = romfile_findprefix("floppyimg/", file);
++ if (!file)
++ return;
++ filename = file->name;
++ size = file->size;
++ dprintf(3, "Found floppy file %s of size %d\n", filename, size);
++ ftype = find_floppy_type(size);
++ if (ftype < 0) {
++ dprintf(3, "No floppy type found for ramdisk size\n");
++ } else {
++ // Setup driver.
++ drive = init_floppy((u32)pos, ftype, file);
++ if (!drive)
++ return;
++ drive->type = DTYPE_RAMDISK;
++ dprintf(1, "Mapping floppy %s to addr %p\n", filename, pos);
++ desc = znprintf(MAXDESCSIZE, "Ramdisk [%s]", &filename[10]);
++ boot_add_floppy(drive, desc, bootprio_find_named_rom(filename, 0));
++ }
++ }
+ }
+
+ static int
+diff --git a/src/util.h b/src/util.h
+index 9c06850..ce3a26d 100644
+--- a/src/util.h
++++ b/src/util.h
+@@ -147,7 +147,8 @@ void dma_setup(void);
+ // hw/floppy.c
+ extern struct floppy_ext_dbt_s diskette_param_table2;
+ void floppy_setup(void);
+-struct drive_s *init_floppy(int floppyid, int ftype);
++extern struct romfile_s *ffile;
++struct drive_s *init_floppy(int floppyid, int ftype, struct romfile_s *ffile);
+ int find_floppy_type(u32 size);
+ int floppy_process_op(struct disk_op_s *op);
+ void floppy_tick(void);
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Idf4efba31091a8678b51c2f6541d440c5cc6d37d
Gerrit-Change-Number: 32351
Gerrit-PatchSet: 1
Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com>
Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com>
Gerrit-MessageType: newchange
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