Change in ...coreboot[master]: fu540: add code to initialize flash
by Xiang Wang (Code Review)
Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30466
Change subject: fu540: add code to initialize flash
......................................................................
fu540: add code to initialize flash
SiFive's ZSBL has initialized flash, but only 16MB of space is
available. I fixed it to use all 32MB.
Change-Id: I8cd803369da5526eff90400c15b91bbf6b477c69
Signed-off-by: Xiang Wang <wxjstz(a)126.com>
---
M src/mainboard/sifive/hifive-unleashed/Makefile.inc
A src/mainboard/sifive/hifive-unleashed/bootblock.c
A src/mainboard/sifive/hifive-unleashed/flash.c
M src/mainboard/sifive/hifive-unleashed/romstage.c
M src/soc/sifive/fu540/Makefile.inc
A src/soc/sifive/fu540/include/soc/spi.h
A src/soc/sifive/fu540/include/soc/spi_flash.h
A src/soc/sifive/fu540/spi.c
8 files changed, 506 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/30466/1
diff --git a/src/mainboard/sifive/hifive-unleashed/Makefile.inc b/src/mainboard/sifive/hifive-unleashed/Makefile.inc
index 27ddcba..2dac283 100644
--- a/src/mainboard/sifive/hifive-unleashed/Makefile.inc
+++ b/src/mainboard/sifive/hifive-unleashed/Makefile.inc
@@ -11,6 +11,10 @@
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
+bootblock-y += flash.c
+bootblock-y += bootblock.c
+
+romstage-y += flash.c
romstage-y += romstage.c
bootblock-y += memlayout.ld
diff --git a/src/mainboard/sifive/hifive-unleashed/bootblock.c b/src/mainboard/sifive/hifive-unleashed/bootblock.c
new file mode 100644
index 0000000..777b2aa
--- /dev/null
+++ b/src/mainboard/sifive/hifive-unleashed/bootblock.c
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 HardenedLinux
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/addressmap.h>
+#include <soc/spi.h>
+#include <soc/spi_flash.h>
+#include <soc/clock.h>
+
+extern void flash_init(void);
+extern void bootblock_mainboard_init(void);
+
+void bootblock_mainboard_init(void)
+{
+ flash_init();
+}
diff --git a/src/mainboard/sifive/hifive-unleashed/flash.c b/src/mainboard/sifive/hifive-unleashed/flash.c
new file mode 100644
index 0000000..a29ac24
--- /dev/null
+++ b/src/mainboard/sifive/hifive-unleashed/flash.c
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 HardenedLinux
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/addressmap.h>
+#include <soc/spi.h>
+#include <soc/spi_flash.h>
+#include <soc/clock.h>
+
+extern void flash_init(void);
+
+const static spi_reg_ffmt ffmt= {
+ .cmd_en = 1,
+ .addr_len = 4,
+ .pad_cnt = 8,
+ .command_proto = SPI_PROTO_S,
+ .addr_proto = SPI_PROTO_S,
+ .data_proto = SPI_PROTO_Q,
+ .command_code = 0x6c
+};
+
+
+void flash_init(void)
+{
+ initialize_spi_flash_mmap_quad(
+ (spi_ctrl*)FU540_QSPI0,
+ clock_get_tlclk_khz(),
+ ffmt.raw_bits,
+ 0x66,
+ 0x99);
+}
diff --git a/src/mainboard/sifive/hifive-unleashed/romstage.c b/src/mainboard/sifive/hifive-unleashed/romstage.c
index 8277141..1675aca 100644
--- a/src/mainboard/sifive/hifive-unleashed/romstage.c
+++ b/src/mainboard/sifive/hifive-unleashed/romstage.c
@@ -21,6 +21,8 @@
#include <soc/clock.h>
#include <soc/sdram.h>
+extern void flash_init(void);
+
void main(void)
{
console_init();
@@ -39,6 +41,7 @@
if (IS_ENABLED(CONFIG_CONSOLE_SERIAL))
uart_init(CONFIG_UART_FOR_CONSOLE);
+ flash_init();
sdram_init();
cbmem_initialize_empty();
diff --git a/src/soc/sifive/fu540/Makefile.inc b/src/soc/sifive/fu540/Makefile.inc
index 4f62f3e..83c7b1c 100644
--- a/src/soc/sifive/fu540/Makefile.inc
+++ b/src/soc/sifive/fu540/Makefile.inc
@@ -18,6 +18,7 @@
bootblock-y += media.c
bootblock-y += bootblock.c
bootblock-y += clock.c
+bootblock-y += spi.c
romstage-y += uart.c
romstage-y += clint.c
@@ -26,6 +27,7 @@
romstage-y += cbmem.c
romstage-y += otp.c
romstage-y += clock.c
+romstage-y += spi.c
ramstage-y += uart.c
ramstage-y += clint.c
@@ -34,6 +36,7 @@
ramstage-y += cbmem.c
ramstage-y += otp.c
ramstage-y += clock.c
+ramstage-y += spi.c
CPPFLAGS_common += -Isrc/soc/sifive/fu540/include
diff --git a/src/soc/sifive/fu540/include/soc/spi.h b/src/soc/sifive/fu540/include/soc/spi.h
new file mode 100644
index 0000000..c40ae7c
--- /dev/null
+++ b/src/soc/sifive/fu540/include/soc/spi.h
@@ -0,0 +1,266 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 SiFive, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef __SOC_SIFIVE_HIFIVE_U_SPI_H__
+#define __SOC_SIFIVE_HIFIVE_U_SPI_H__
+
+#include <stdint.h>
+
+#define _ASSERT_SIZEOF(type, size) _Static_assert(sizeof(type) == (size), #type " must be " #size " bytes wide")
+
+typedef union
+{
+ struct
+ {
+ uint32_t pha : 1;
+ uint32_t pol : 1;
+ uint32_t reserved : 30;
+ };
+ uint32_t raw_bits;
+} spi_reg_sckmode;
+_ASSERT_SIZEOF(spi_reg_sckmode, 4);
+
+
+typedef union
+{
+ struct
+ {
+ uint32_t mode : 2;
+ uint32_t reserved : 30;
+ };
+ uint32_t raw_bits;
+} spi_reg_csmode;
+_ASSERT_SIZEOF(spi_reg_csmode, 4);
+
+
+typedef union
+{
+ struct
+ {
+ uint32_t cssck : 8;
+ uint32_t reserved0 : 8;
+ uint32_t sckcs : 8;
+ uint32_t reserved1 : 8;
+ };
+ uint32_t raw_bits;
+} spi_reg_delay0;
+_ASSERT_SIZEOF(spi_reg_delay0, 4);
+
+
+typedef union
+{
+ struct
+ {
+ uint32_t intercs : 8;
+ uint32_t reserved0 : 8;
+ uint32_t interxfr : 8;
+ uint32_t reserved1 : 8;
+ };
+ uint32_t raw_bits;
+} spi_reg_delay1;
+_ASSERT_SIZEOF(spi_reg_delay1, 4);
+
+
+typedef union
+{
+ struct
+ {
+ uint32_t proto : 2;
+ uint32_t endian : 1;
+ uint32_t dir : 1;
+ uint32_t reserved0 : 12;
+ uint32_t len : 4;
+ uint32_t reserved1 : 12;
+ };
+ uint32_t raw_bits;
+} spi_reg_fmt;
+_ASSERT_SIZEOF(spi_reg_fmt, 4);
+
+
+typedef union
+{
+ struct
+ {
+ uint32_t data : 8;
+ uint32_t reserved : 23;
+ uint32_t full : 1;
+ };
+ uint32_t raw_bits;
+} spi_reg_txdata;
+_ASSERT_SIZEOF(spi_reg_txdata, 4);
+
+
+typedef union
+{
+ struct
+ {
+ uint32_t data : 8;
+ uint32_t reserved : 23;
+ uint32_t empty : 1;
+ };
+ uint32_t raw_bits;
+} spi_reg_rxdata;
+_ASSERT_SIZEOF(spi_reg_rxdata, 4);
+
+
+typedef union
+{
+ struct
+ {
+ uint32_t txmark : 3;
+ uint32_t reserved : 29;
+ };
+ uint32_t raw_bits;
+} spi_reg_txmark;
+_ASSERT_SIZEOF(spi_reg_txmark, 4);
+
+
+typedef union
+{
+ struct
+ {
+ uint32_t rxmark : 3;
+ uint32_t reserved : 29;
+ };
+ uint32_t raw_bits;
+} spi_reg_rxmark;
+_ASSERT_SIZEOF(spi_reg_rxmark, 4);
+
+
+typedef union
+{
+ struct
+ {
+ uint32_t en : 1;
+ uint32_t reserved : 31;
+ };
+ uint32_t raw_bits;
+} spi_reg_fctrl;
+_ASSERT_SIZEOF(spi_reg_fctrl, 4);
+
+
+typedef union
+{
+ struct
+ {
+ uint32_t cmd_en : 1;
+ uint32_t addr_len : 3;
+ uint32_t pad_cnt : 4;
+ uint32_t command_proto : 2;
+ uint32_t addr_proto : 2;
+ uint32_t data_proto : 2;
+ uint32_t reserved : 2;
+ uint32_t command_code : 8;
+ uint32_t pad_code : 8;
+ };
+ uint32_t raw_bits;
+} spi_reg_ffmt;
+_ASSERT_SIZEOF(spi_reg_ffmt, 4);
+
+
+typedef union
+{
+ struct
+ {
+ uint32_t txwm : 1;
+ uint32_t rxwm : 1;
+ uint32_t reserved : 30;
+ };
+ uint32_t raw_bits;
+} spi_reg_ie;
+typedef spi_reg_ie spi_reg_ip;
+_ASSERT_SIZEOF(spi_reg_ie, 4);
+_ASSERT_SIZEOF(spi_reg_ip, 4);
+
+#undef _ASSERT_SIZEOF
+
+
+/**
+ * SPI control register memory map.
+ *
+ * All functions take a pointer to a SPI device's control registers.
+ */
+typedef volatile struct
+{
+ uint32_t sckdiv;
+ spi_reg_sckmode sckmode;
+ uint32_t reserved08;
+ uint32_t reserved0c;
+
+ uint32_t csid;
+ uint32_t csdef;
+ spi_reg_csmode csmode;
+ uint32_t reserved1c;
+
+ uint32_t reserved20;
+ uint32_t reserved24;
+ spi_reg_delay0 delay0;
+ spi_reg_delay1 delay1;
+
+ uint32_t reserved30;
+ uint32_t reserved34;
+ uint32_t reserved38;
+ uint32_t reserved3c;
+
+ spi_reg_fmt fmt;
+ uint32_t reserved44;
+ spi_reg_txdata txdata;
+ spi_reg_rxdata rxdata;
+
+ spi_reg_txmark txmark;
+ spi_reg_rxmark rxmark;
+ uint32_t reserved58;
+ uint32_t reserved5c;
+
+ spi_reg_fctrl fctrl;
+ spi_reg_ffmt ffmt;
+ uint32_t reserved68;
+ uint32_t reserved6c;
+
+ spi_reg_ie ie;
+ spi_reg_ip ip;
+} spi_ctrl;
+
+
+void spi_tx(spi_ctrl* spictrl, uint8_t in);
+uint8_t spi_rx(spi_ctrl* spictrl);
+uint8_t spi_txrx(spi_ctrl* spictrl, uint8_t in);
+
+// Inlining header functions in C
+// https://stackoverflow.com/a/23699777/7433423
+
+/**
+ * Get smallest clock divisor that divides input_khz to a quotient less than or
+ * equal to max_target_khz;
+ */
+static inline unsigned int spi_min_clk_divisor(unsigned int input_khz, unsigned int max_target_khz)
+{
+ // f_sck = f_in / (2 * (div + 1)) => div = (f_in / (2*f_sck)) - 1
+ //
+ // The nearest integer solution for div requires rounding up as to not exceed
+ // max_target_khz.
+ //
+ // div = ceil(f_in / (2*f_sck)) - 1
+ // = floor((f_in - 1 + 2*f_sck) / (2*f_sck)) - 1
+ //
+ // This should not overflow as long as (f_in - 1 + 2*f_sck) does not exceed
+ // 2^32 - 1, which is unlikely since we represent frequencies in kHz.
+ unsigned int quotient = (input_khz + 2 * max_target_khz - 1) / (2 * max_target_khz);
+ // Avoid underflow
+ if (quotient == 0)
+ return 0;
+ return quotient - 1;
+}
+
+#endif /* __SOC_SIFIVE_HIFIVE_U_SPI_H__ */
diff --git a/src/soc/sifive/fu540/include/soc/spi_flash.h b/src/soc/sifive/fu540/include/soc/spi_flash.h
new file mode 100644
index 0000000..9926b82
--- /dev/null
+++ b/src/soc/sifive/fu540/include/soc/spi_flash.h
@@ -0,0 +1,103 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 SiFive, Inc
+ * Copyright (C) 2018 HardenedLinux
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __SOC_SIFIVE_HIFIVE_U_SPI_FLASH_H__
+#define __SOC_SIFIVE_HIFIVE_U_SPI_FLASH_H__
+
+#include <soc/spi.h>
+#include <stdint.h>
+
+#define SPI_PROTO_S 0
+#define SPI_PROTO_D 1
+#define SPI_PROTO_Q 2
+
+/**
+ * Set up SPI for direct, non-memory-mapped access.
+ */
+
+static inline int initialize_spi_flash_direct(
+ spi_ctrl* spictrl,
+ unsigned int spi_clk_input_khz,
+ unsigned int command_enable,
+ unsigned int command_reset)
+{
+ // Max desired SPI clock is 10MHz
+ spictrl->sckdiv = spi_min_clk_divisor(spi_clk_input_khz, 10000);
+
+ spictrl->fctrl.en = 0;
+
+ spi_txrx(spictrl, command_enable);
+ spi_txrx(spictrl, command_reset);
+
+ return 0;
+}
+
+static inline int _initialize_spi_flash_mmap(
+ spi_ctrl* spictrl,
+ unsigned int spi_clk_input_khz,
+ uint32_t ffmt_rawbits,
+ unsigned int command_enable,
+ unsigned int command_reset)
+{
+ // Max desired SPI clock is 10MHz
+ spictrl->sckdiv = spi_min_clk_divisor(spi_clk_input_khz, 10000);
+
+ spictrl->fctrl.en = 0;
+
+ spi_txrx(spictrl, command_enable);
+ spi_txrx(spictrl, command_reset);
+
+ spictrl->ffmt.raw_bits = ffmt_rawbits;
+
+ spictrl->fctrl.en = 1;
+ __asm__ __volatile__ ("fence io, io");
+ return 0;
+}
+
+
+static inline int initialize_spi_flash_mmap_single(
+ spi_ctrl* spictrl,
+ unsigned int spi_clk_input_khz,
+ uint32_t ffmt_rawbits,
+ unsigned int command_enable,
+ unsigned int command_reset)
+{
+ return _initialize_spi_flash_mmap(
+ spictrl,
+ spi_clk_input_khz,
+ ffmt_rawbits,
+ command_enable,
+ command_reset);
+}
+
+
+static inline int initialize_spi_flash_mmap_quad(
+ spi_ctrl* spictrl,
+ unsigned int spi_clk_input_khz,
+ uint32_t ffmt_rawbits,
+ unsigned int command_enable,
+ unsigned int command_reset)
+{
+ return _initialize_spi_flash_mmap(
+ spictrl,
+ spi_clk_input_khz,
+ ffmt_rawbits,
+ command_enable,
+ command_reset);
+}
+
+#endif /* __SOC_SIFIVE_HIFIVE_U_SPI_FLASH_H__ */
+
diff --git a/src/soc/sifive/fu540/spi.c b/src/soc/sifive/fu540/spi.c
new file mode 100644
index 0000000..01a58dd
--- /dev/null
+++ b/src/soc/sifive/fu540/spi.c
@@ -0,0 +1,58 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 SiFive, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/spi.h>
+
+/**
+ * Wait until SPI is ready for transmission and transmit byte.
+ */
+void spi_tx(spi_ctrl* spictrl, uint8_t in)
+{
+#if __riscv_atomic
+ int32_t r;
+ do {
+ asm volatile (
+ "amoor.w %0, %2, %1\n"
+ : "=r" (r), "+A" (spictrl->txdata.raw_bits)
+ : "r" (in)
+ );
+ } while (r < 0);
+#else
+ while ((int32_t) spictrl->txdata.raw_bits < 0);
+ spictrl->txdata.data = in;
+#endif
+}
+
+
+/**
+ * Wait until SPI receive queue has data and read byte.
+ */
+uint8_t spi_rx(spi_ctrl* spictrl)
+{
+ int32_t out;
+ while ((out = (int32_t) spictrl->rxdata.raw_bits) < 0);
+ return (uint8_t) out;
+}
+
+
+/**
+ * Transmit a byte and receive a byte.
+ */
+uint8_t spi_txrx(spi_ctrl* spictrl, uint8_t in)
+{
+ spi_tx(spictrl, in);
+ return spi_rx(spictrl);
+}
+
--
To view, visit https://review.coreboot.org/c/coreboot/+/30466
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I8cd803369da5526eff90400c15b91bbf6b477c69
Gerrit-Change-Number: 30466
Gerrit-PatchSet: 1
Gerrit-Owner: Xiang Wang <wxjstz(a)126.com>
Gerrit-MessageType: newchange
1 week
Change in ...coreboot[master]: mb/qemu-{i440fx,q35}: Use POSTCAR stage to load the ramstage
by Patrick Rudolph (Code Review)
Hello Arthur Heymans,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/30499
to review the following change.
Change subject: mb/qemu-{i440fx,q35}: Use POSTCAR stage to load the ramstage
......................................................................
mb/qemu-{i440fx,q35}: Use POSTCAR stage to load the ramstage
Qemu does not have a real CAR but postcar stage is still useful
to setup pagetables for x86_64 ramstage.
Change-Id: I6638534d99fde312e55b6a6be8c95e4cb25cca80
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Signed-off-by: Patrick Rudolph <siro(a)das-labor.org>
---
M src/lib/Makefile.inc
M src/mainboard/emulation/qemu-i440fx/Kconfig
M src/mainboard/emulation/qemu-i440fx/Makefile.inc
A src/mainboard/emulation/qemu-i440fx/exit_car.S
M src/mainboard/emulation/qemu-i440fx/romstage.c
M src/mainboard/emulation/qemu-q35/Kconfig
M src/mainboard/emulation/qemu-q35/Makefile.inc
M src/mainboard/emulation/qemu-q35/romstage.c
8 files changed, 75 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/30499/1
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 2fd4e4c..48dc664 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -132,6 +132,7 @@
ramstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
ramstage-$(CONFIG_BOOTSPLASH) += jpeg.c
ramstage-$(CONFIG_TRACE) += trace.c
+postcar-$(CONFIG_TRACE) += trace.c
ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
ramstage-$(CONFIG_COVERAGE) += libgcov.c
ramstage-y += edid.c
diff --git a/src/mainboard/emulation/qemu-i440fx/Kconfig b/src/mainboard/emulation/qemu-i440fx/Kconfig
index eb9f011..3a507d3 100644
--- a/src/mainboard/emulation/qemu-i440fx/Kconfig
+++ b/src/mainboard/emulation/qemu-i440fx/Kconfig
@@ -14,6 +14,8 @@
select MAINBOARD_FORCE_NATIVE_VGA_INIT
select BOOTBLOCK_CONSOLE
select NO_CAR_GLOBAL_MIGRATION
+ select POSTCAR_STAGE
+ select POSTCAR_CONSOLE
config MAINBOARD_DIR
string
diff --git a/src/mainboard/emulation/qemu-i440fx/Makefile.inc b/src/mainboard/emulation/qemu-i440fx/Makefile.inc
index 9e2880a..de790e6 100644
--- a/src/mainboard/emulation/qemu-i440fx/Makefile.inc
+++ b/src/mainboard/emulation/qemu-i440fx/Makefile.inc
@@ -2,3 +2,5 @@
ramstage-y += fw_cfg.c
romstage-y += memory.c
ramstage-y += memory.c
+postcar-y += memory.c
+postcar-y += exit_car.S
diff --git a/src/mainboard/emulation/qemu-i440fx/exit_car.S b/src/mainboard/emulation/qemu-i440fx/exit_car.S
new file mode 100644
index 0000000..74f6ed2
--- /dev/null
+++ b/src/mainboard/emulation/qemu-i440fx/exit_car.S
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/cr.h>
+/* jump directly to the main function, as there is no real CAR to tear down. */
+.text
+.global chipset_teardown_car
+chipset_teardown_car:
+ /* Set up new stack. */
+ mov post_car_stack_top, %esp
+ /* Call C code */
+ call main
diff --git a/src/mainboard/emulation/qemu-i440fx/romstage.c b/src/mainboard/emulation/qemu-i440fx/romstage.c
index e31394c..137dfbf 100644
--- a/src/mainboard/emulation/qemu-i440fx/romstage.c
+++ b/src/mainboard/emulation/qemu-i440fx/romstage.c
@@ -20,14 +20,35 @@
#include <cpu/intel/romstage.h>
#include <timestamp.h>
#include <program_loading.h>
+#include <cpu/x86/mtrr.h>
+
+#include "memory.h"
asmlinkage void car_stage_entry(void)
{
+ struct postcar_frame pcf;
+
console_init();
cbmem_recovery(0);
timestamp_add_now(TS_START_ROMSTAGE);
- run_ramstage();
+ if (postcar_frame_init(&pcf, 5 * KiB))
+ die("Unable to initialize postcar frame.\n");
+
+ /* Cache the ROM as WP just below 4GiB. */
+ postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
+
+ /* Cache memory below 4 GiB */
+ postcar_frame_add_mtrr(&pcf, 0, qemu_get_memory_size() * KiB,
+ MTRR_TYPE_WRBACK);
+
+ /* Cache memory beyond 4 GiB */
+ if (qemu_get_high_memory_size() > 0)
+ postcar_frame_add_mtrr(&pcf, (4ULL * GiB),
+ qemu_get_high_memory_size() * KiB,
+ MTRR_TYPE_WRBACK);
+
+ run_postcar_phase(&pcf);
}
diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig
index 1cc7148..07c15f3 100644
--- a/src/mainboard/emulation/qemu-q35/Kconfig
+++ b/src/mainboard/emulation/qemu-q35/Kconfig
@@ -13,6 +13,8 @@
select MAINBOARD_FORCE_NATIVE_VGA_INIT
select BOOTBLOCK_CONSOLE
select NO_CAR_GLOBAL_MIGRATION
+ select POSTCAR_STAGE
+ select POSTCAR_CONSOLE
config MAINBOARD_DIR
string
diff --git a/src/mainboard/emulation/qemu-q35/Makefile.inc b/src/mainboard/emulation/qemu-q35/Makefile.inc
index 1c06d77..a0ac5dd 100644
--- a/src/mainboard/emulation/qemu-q35/Makefile.inc
+++ b/src/mainboard/emulation/qemu-q35/Makefile.inc
@@ -3,4 +3,6 @@
ramstage-y += ../qemu-i440fx/fw_cfg.c
romstage-y += ../qemu-i440fx/memory.c
+postcar-y += ../qemu-i440fx/memory.c
+postcar-y += ../qemu-i440fx/exit_car.S
bootblock-y += bootblock.c
diff --git a/src/mainboard/emulation/qemu-q35/romstage.c b/src/mainboard/emulation/qemu-q35/romstage.c
index 2b8d935..badafdd 100644
--- a/src/mainboard/emulation/qemu-q35/romstage.c
+++ b/src/mainboard/emulation/qemu-q35/romstage.c
@@ -21,9 +21,13 @@
#include <timestamp.h>
#include <southbridge/intel/i82801ix/i82801ix.h>
#include <program_loading.h>
+#include <cpu/x86/mtrr.h>
+
+#include "../qemu-i440fx/memory.h"
asmlinkage void car_stage_entry(void)
{
+ struct postcar_frame pcf;
i82801ix_early_init();
console_init();
@@ -31,5 +35,21 @@
timestamp_add_now(TS_START_ROMSTAGE);
- run_ramstage();
+ if (postcar_frame_init(&pcf, 5 * KiB))
+ die("Unable to initialize postcar frame.\n");
+
+ /* Cache the ROM as WP just below 4GiB. */
+ postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
+
+ /* Cache memory below 4 GiB */
+ postcar_frame_add_mtrr(&pcf, 0, qemu_get_memory_size() * KiB,
+ MTRR_TYPE_WRBACK);
+
+ /* Cache memory beyond 4 GiB */
+ if (qemu_get_high_memory_size() > 0)
+ postcar_frame_add_mtrr(&pcf, (4ULL * GiB),
+ qemu_get_high_memory_size() * KiB,
+ MTRR_TYPE_WRBACK);
+
+ run_postcar_phase(&pcf);
}
--
To view, visit https://review.coreboot.org/c/coreboot/+/30499
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I6638534d99fde312e55b6a6be8c95e4cb25cca80
Gerrit-Change-Number: 30499
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-MessageType: newchange
2 weeks, 3 days
Change in ...coreboot[master]: mb/google/sarien: Set CPU boot up mode to turbo
by Lijian Zhao (Code Review)
Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30446
Change subject: mb/google/sarien: Set CPU boot up mode to turbo
......................................................................
mb/google/sarien: Set CPU boot up mode to turbo
Set CPU to be running at non-turbo maxium speed first and then switch to
turbo maxium speed to accelerate boot performance.
BUG=N/A
TEST=Boot up with sarien platform, check with cbmem -t, boot time had
been 110ms less.
Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com>
Change-Id: I43bdb7ef82a5e6e147b3b506756c118dacdb0321
---
M src/mainboard/google/sarien/variants/arcada/devicetree.cb
M src/mainboard/google/sarien/variants/sarien/devicetree.cb
2 files changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/30446/1
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
index 52840de..ce83d10 100644
--- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
@@ -24,6 +24,7 @@
register "SkipExtGfxScan" = "1"
register "VmxEnable" = "1"
+ register "bootfreq" = "2"
register "speed_shift_enable" = "1"
register "s0ix_enable" = "1"
register "dptf_enable" = "1"
diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
index 47abadc..98566f1 100644
--- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
@@ -28,6 +28,7 @@
register "SkipExtGfxScan" = "1"
register "VmxEnable" = "1"
+ register "bootfreq" = "2"
register "speed_shift_enable" = "1"
register "s0ix_enable" = "1"
register "dptf_enable" = "1"
--
To view, visit https://review.coreboot.org/c/coreboot/+/30446
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I43bdb7ef82a5e6e147b3b506756c118dacdb0321
Gerrit-Change-Number: 30446
Gerrit-PatchSet: 1
Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com>
Gerrit-MessageType: newchange
3 weeks
Change in ...coreboot[master]: soc/intel/cannonlake: Add option for boot frquency
by Lijian Zhao (Code Review)
Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30445
Change subject: soc/intel/cannonlake: Add option for boot frquency
......................................................................
soc/intel/cannonlake: Add option for boot frquency
Cannonlake/Coffeelake FSP have options for CPU boot up frequency
selection, expose that in coreboot side.
Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com>
Change-Id: I6bd5849122c9035bb7f448acf08e258e8c207013
---
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/romstage/fsp_params.c
2 files changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/30445/1
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 3a723d2..7e50a73 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -110,6 +110,11 @@
SaGv_Enabled,
} SaGv;
+ /* Boot Frequency from reset vector.
+ * 0: Maximum battery performance, 1: Maximum non-turbo performance, 2:
+ * Maximum turbo performance @note If 2 is selected, system will start
+ * with non-turbo mode and then switch to turbo. */
+ uint8_t bootfreq;
/* Rank Margin Tool. 1:Enable, 0:Disable */
uint8_t RMT;
diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c
index c3a2509..0514844 100644
--- a/src/soc/intel/cannonlake/romstage/fsp_params.c
+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c
@@ -54,6 +54,8 @@
#if IS_ENABLED(CONFIG_SOC_INTEL_COFFEELAKE)
m_cfg->SkipMpInit = !chip_get_fsp_mp_init();
#endif
+ m_cfg->BootFrequency = config->bootfreq;
+
/* If ISH is enabled, enable ISH elements */
if (!dev)
m_cfg->PchIshEnable = 0;
--
To view, visit https://review.coreboot.org/c/coreboot/+/30445
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I6bd5849122c9035bb7f448acf08e258e8c207013
Gerrit-Change-Number: 30445
Gerrit-PatchSet: 1
Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com>
Gerrit-MessageType: newchange
3 weeks
Change in ...coreboot[master]: src/soc/intel/common/block/pcie: Add a workaround for ThP2 9260
by Gaggery Tsai (Code Review)
Gaggery Tsai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30486
Change subject: src/soc/intel/common/block/pcie: Add a workaround for ThP2 9260
......................................................................
src/soc/intel/common/block/pcie: Add a workaround for ThP2 9260
This patch adds a workaround for ThP2. The PCIe root port LCTL2.TLS
is by default GEN1 and ThP has bad synchronization on polarity
inversion. When the root port request for speed change, ThP doesn’t
confirm the request, and both sides are moving to polling after
timeout, hot reset is issued, and then most of the CFG space is
initialized. From the observation, CCC/ECPM/LTR would be reset to
default but CCC/ECPM of root port and end devices have been
reconfigured in pci_scan. The LTR configuration for root port
is still missing.
BUG=B:117618636
BRANCH=None
TEST=Add THP2_9260_WORKAROUND in Atlas configuration & emerge-atlas
coreboot chromeos-bootimage & Warm/cold reset for 10 times and
didn't see unsupported request related AER error messages &
$lspci -vvs 00:1c.0|grep LTR and ensure LTR+ is present.
Change-Id: Id5d2814488fbc9db927edb2ead972b73ebc336ce
Signed-off-by: Gaggery Tsai <gaggery.tsai(a)intel.com>
---
M src/soc/intel/common/block/pcie/Kconfig
M src/soc/intel/common/block/pcie/pcie.c
2 files changed, 29 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/30486/1
diff --git a/src/soc/intel/common/block/pcie/Kconfig b/src/soc/intel/common/block/pcie/Kconfig
index aa32324..36915fa 100644
--- a/src/soc/intel/common/block/pcie/Kconfig
+++ b/src/soc/intel/common/block/pcie/Kconfig
@@ -13,3 +13,8 @@
Enable debug logs in PCIe module. Allows debug information on memory
base and limit, prefetchable memory base and limit, prefetchable memory
base upper 32 bits and prefetchable memory limit upper 32 bits.
+
+config THP2_9260_WORKAROUND
+ bool
+ help
+ THP2 workaround
diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c
index 3ebb4f6..07a2321 100644
--- a/src/soc/intel/common/block/pcie/pcie.c
+++ b/src/soc/intel/common/block/pcie/pcie.c
@@ -28,12 +28,36 @@
/* PCI-E Sub-System ID */
#define PCIE_SUBSYSTEM_VENDOR_ID 0x94
+/*
+ * Check the LTR for root port and enable it
+ */
+static void pciexp_enable_root_port_ltr(struct device *root, unsigned root_cap)
+{
+ u16 root_ltr;
+ unsigned int val;
+
+ val = pci_read_config16(root, root_cap + PCI_EXP_DEV_CAP2_OFFSET);
+
+ if (val & LTR_MECHANISM_SUPPORT) {
+ root_ltr = pci_read_config16(root, root_cap + PCI_EXP_DEV_CTL_STS2_CAP_OFFSET);
+ root_ltr |= LTR_MECHANISM_EN;
+ pci_write_config16(root, root_cap + PCI_EXP_DEV_CTL_STS2_CAP_OFFSET, root_ltr);
+ }
+}
+
static void pch_pcie_init(struct device *dev)
{
u16 reg16;
+ unsigned int dev_cap;
printk(BIOS_DEBUG, "Initializing PCH PCIe bridge.\n");
+ if (IS_ENABLED(CONFIG_THP2_9260_WORKAROUND)) {
+ dev_cap = pci_find_capability(dev, PCI_CAP_ID_PCIE);
+ if (dev_cap)
+ pciexp_enable_root_port_ltr(dev, dev_cap);
+ }
+
/* Enable SERR */
pci_or_config32(dev, PCI_COMMAND, PCI_COMMAND_SERR);
--
To view, visit https://review.coreboot.org/c/coreboot/+/30486
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Id5d2814488fbc9db927edb2ead972b73ebc336ce
Gerrit-Change-Number: 30486
Gerrit-PatchSet: 1
Gerrit-Owner: Gaggery Tsai <gaggery.tsai(a)intel.com>
Gerrit-MessageType: newchange
4 weeks
Change in ...coreboot[master]: [TEST]sb/intel/common: Remove CAR_GLOBAL use
by Arthur Heymans (Code Review)
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30506
Change subject: [TEST]sb/intel/common: Remove CAR_GLOBAL use
......................................................................
[TEST]sb/intel/common: Remove CAR_GLOBAL use
We have NO_CAR_GLOBAL_MIGRATION now. (yes?)
Change-Id: Ic2c90d264d851ab4abeca07f412d43d088ad96dc
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/southbridge/intel/common/gpio.c
M src/southbridge/intel/common/pmbase.c
M src/southbridge/intel/common/spi.c
3 files changed, 4 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/30506/1
diff --git a/src/southbridge/intel/common/gpio.c b/src/southbridge/intel/common/gpio.c
index 7c8cfe8..140839f 100644
--- a/src/southbridge/intel/common/gpio.c
+++ b/src/southbridge/intel/common/gpio.c
@@ -40,7 +40,7 @@
/* Don't assume GPIO_BASE is still the same */
return pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffe;
#else
- static u16 gpiobase CAR_GLOBAL;
+ static u16 gpiobase;
if (gpiobase)
return gpiobase;
diff --git a/src/southbridge/intel/common/pmbase.c b/src/southbridge/intel/common/pmbase.c
index 2de57d6..b022629 100644
--- a/src/southbridge/intel/common/pmbase.c
+++ b/src/southbridge/intel/common/pmbase.c
@@ -42,7 +42,7 @@
/* Don't assume PMBASE is still the same */
return pci_read_config16(PCH_LPC_DEV, PMBASE) & 0xfffc;
#else
- static u16 pmbase CAR_GLOBAL;
+ static u16 pmbase;
if (pmbase)
return pmbase;
diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c
index 3ca0d6c..6ef6769 100644
--- a/src/southbridge/intel/common/spi.c
+++ b/src/southbridge/intel/common/spi.c
@@ -69,7 +69,7 @@
typedef struct spi_slave ich_spi_slave;
-static int g_ichspi_lock CAR_GLOBAL = 0;
+static int g_ichspi_lock = 0;
typedef struct ich7_spi_regs {
uint16_t spis;
@@ -138,7 +138,7 @@
uint8_t fpr_max;
} ich_spi_controller;
-static ich_spi_controller g_cntlr CAR_GLOBAL;
+static ich_spi_controller g_cntlr;
enum {
SPIS_SCIP = 0x0001,
--
To view, visit https://review.coreboot.org/c/coreboot/+/30506
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ic2c90d264d851ab4abeca07f412d43d088ad96dc
Gerrit-Change-Number: 30506
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-MessageType: newchange
1 month
Change in ...coreboot[master]: soc/intel/baytrail: Don't use CAR_GLOBAL
by Arthur Heymans (Code Review)
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30511
Change subject: soc/intel/baytrail: Don't use CAR_GLOBAL
......................................................................
soc/intel/baytrail: Don't use CAR_GLOBAL
All platforms using this code have NO_CAR_GLOBAL_MIGRATION.
Change-Id: I731bc1c9dec6cb5bbb228b7949a73848cb73eee3
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/soc/intel/baytrail/romstage/romstage.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/30511/1
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index 0e1d57e..72ded61 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -134,7 +134,7 @@
return NULL;
}
-static struct chipset_power_state power_state CAR_GLOBAL;
+static struct chipset_power_state power_state;
static void migrate_power_state(int is_recovery)
{
--
To view, visit https://review.coreboot.org/c/coreboot/+/30511
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I731bc1c9dec6cb5bbb228b7949a73848cb73eee3
Gerrit-Change-Number: 30511
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-MessageType: newchange
1 month, 1 week
Change in ...coreboot[master]: nb/intel/nehalem: Remove CAR_GLOBAL use
by Arthur Heymans (Code Review)
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30505
Change subject: nb/intel/nehalem: Remove CAR_GLOBAL use
......................................................................
nb/intel/nehalem: Remove CAR_GLOBAL use
We have NO_CAR_GLOBAL_MIGRATION now.
Change-Id: I077f235029e3fe3b1368f028981985895d8b766b
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/northbridge/intel/nehalem/raminit.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/30505/1
diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c
index 54ef278..3af88bb 100644
--- a/src/northbridge/intel/nehalem/raminit.c
+++ b/src/northbridge/intel/nehalem/raminit.c
@@ -225,7 +225,7 @@
};
/* Global allocation of timings_car */
-timing_bounds_t timings_car[64] CAR_GLOBAL;
+timing_bounds_t timings_car[64];
static void
write_500(struct raminfo *info, int channel, u32 val, u16 addr, int bits,
--
To view, visit https://review.coreboot.org/c/coreboot/+/30505
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I077f235029e3fe3b1368f028981985895d8b766b
Gerrit-Change-Number: 30505
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-MessageType: newchange
1 month, 1 week
Change in ...coreboot[master]: soc/intel/apollolake: Don't use CAR_GLOBAL
by Arthur Heymans (Code Review)
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30510
Change subject: soc/intel/apollolake: Don't use CAR_GLOBAL
......................................................................
soc/intel/apollolake: Don't use CAR_GLOBAL
All platforms using this code have NO_CAR_GLOBAL_MIGRATION.
Change-Id: I0f393385aa94f18c2e05af3b5a54999575323d18
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/soc/intel/apollolake/meminit.c
M src/soc/intel/apollolake/mmap_boot.c
M src/soc/intel/apollolake/romstage.c
3 files changed, 5 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/30510/1
diff --git a/src/soc/intel/apollolake/meminit.c b/src/soc/intel/apollolake/meminit.c
index 889bbde..a230222 100644
--- a/src/soc/intel/apollolake/meminit.c
+++ b/src/soc/intel/apollolake/meminit.c
@@ -21,7 +21,7 @@
#include <fsp/soc_binding.h>
#include <string.h>
-static size_t memory_size_mib CAR_GLOBAL;
+static size_t memory_size_mib;
size_t memory_in_system_in_mib(void)
{
diff --git a/src/soc/intel/apollolake/mmap_boot.c b/src/soc/intel/apollolake/mmap_boot.c
index 1c3077e..8174502 100644
--- a/src/soc/intel/apollolake/mmap_boot.c
+++ b/src/soc/intel/apollolake/mmap_boot.c
@@ -57,10 +57,10 @@
*
*/
-static size_t bios_size CAR_GLOBAL;
+static size_t bios_size;
-static struct mem_region_device shadow_dev CAR_GLOBAL;
-static struct xlate_region_device real_dev CAR_GLOBAL;
+static struct mem_region_device shadow_dev;
+static struct xlate_region_device real_dev;
static void bios_mmap_init(void)
{
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index 4f4f9f5..4133946 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -58,7 +58,7 @@
0x8d, 0xe6, 0xc0, 0x44, 0x64, 0x1d, 0xe9, 0x42,
};
-static uint32_t fsp_version CAR_GLOBAL;
+static uint32_t fsp_version;
/* High Performance Event Timer Configuration */
#define P2SB_HPTC 0x60
--
To view, visit https://review.coreboot.org/c/coreboot/+/30510
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I0f393385aa94f18c2e05af3b5a54999575323d18
Gerrit-Change-Number: 30510
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-MessageType: newchange
1 month, 1 week
Change in ...coreboot[master]: soc/amd/stoneyridge: Don't use CAR_GLOBAL
by Arthur Heymans (Code Review)
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30509
Change subject: soc/amd/stoneyridge: Don't use CAR_GLOBAL
......................................................................
soc/amd/stoneyridge: Don't use CAR_GLOBAL
All platforms using this code have NO_CAR_GLOBAL_MIGRATION.
Change-Id: I422d5637caa1b55fa6bad30d25f5e34cbba40851
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/soc/amd/stoneyridge/spi.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/30509/1
diff --git a/src/soc/amd/stoneyridge/spi.c b/src/soc/amd/stoneyridge/spi.c
index 9baf433..1f168c2 100644
--- a/src/soc/amd/stoneyridge/spi.c
+++ b/src/soc/amd/stoneyridge/spi.c
@@ -32,7 +32,7 @@
#define SPI_DEBUG_DRIVER IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)
-static uintptr_t spibar CAR_GLOBAL;
+static uintptr_t spibar;
static uintptr_t get_spibase(void)
{
--
To view, visit https://review.coreboot.org/c/coreboot/+/30509
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I422d5637caa1b55fa6bad30d25f5e34cbba40851
Gerrit-Change-Number: 30509
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-MessageType: newchange
1 month, 1 week