Change in ...coreboot[master]: mb/google/hatch: Enable SD card support for hatch
by Maulik V Vaghela (Code Review)
Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30545
Change subject: mb/google/hatch: Enable SD card support for hatch
......................................................................
mb/google/hatch: Enable SD card support for hatch
Enable support for SD card support for hatch
1. Enable PCI device for SD and also configure SD detect GPIO
2. Configure SD card related GPIOs in gpio.c
BUG=b:120914069
BRANCH=none
TEST=check if code compiles correctly and verify GPIO configuration with
schematics
Change-Id: I8ccaa28323b1e1fcc192e245347a96309227660b
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com>
---
M src/mainboard/google/hatch/variants/baseboard/devicetree.cb
M src/mainboard/google/hatch/variants/baseboard/gpio.c
2 files changed, 24 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/30545/1
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
index dc17559..7978b44 100644
--- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
@@ -80,6 +80,9 @@
register "PcieClkSrcUsage[3]" = "13"
register "PcieClkSrcClkReq[3]" = "3"
+ # GPIO for SD card detect
+ register "sdcard_cd_gpio" = "GPP_G5"
+
device domain 0 on
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device
@@ -168,7 +171,7 @@
register "wake" = "GPE0_PME_B0"
device pci 14.3 on end # CNVi wifi
end
- device pci 14.5 off end # SDCard
+ device pci 14.5 on end # SDCard
device pci 15.0 on
chip drivers/i2c/generic
register "hid" = ""ELAN0000""
diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c
index 3d63997..5eeddb0 100644
--- a/src/mainboard/google/hatch/variants/baseboard/gpio.c
+++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c
@@ -19,6 +19,10 @@
#include <commonlib/helpers.h>
static const struct pad_config gpio_table[] = {
+ /* SD_1P8_SEL => NC */
+ PAD_NC(GPP_A16, DN_20K),
+ /* EN_PP3300_SD_DX */
+ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
/* TRACKPAD_INT_ODL */
PAD_CFG_GPI_APIC(GPP_A21, NONE, PLTRST, LEVEL, INVERT),
/* SRCCLKREQ1 */
@@ -103,6 +107,22 @@
PAD_CFG_GPI(GPP_F11, NONE, PLTRST),
/* PCH_MEM_STRAP3 */
PAD_CFG_GPI(GPP_F22, NONE, PLTRST),
+ /* SD_CMD */
+ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),
+ /* SD_DATA0 */
+ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),
+ /* SD_DATA1 */
+ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),
+ /* SD_DATA2 */
+ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1),
+ /* SD_DATA3 */
+ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1),
+ /* SD_CD# */
+ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1),
+ /* SD_CLK */
+ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),
+ /* SD_WP => NC */
+ PAD_NC(GPP_G7, DN_20K),
};
const struct pad_config *__weak variant_gpio_table(size_t *num)
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I8ccaa28323b1e1fcc192e245347a96309227660b
Gerrit-Change-Number: 30545
Gerrit-PatchSet: 1
Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com>
Gerrit-MessageType: newchange
1 day, 17 hours
Change in ...coreboot[master]: fu540: add code to initialize flash
by Xiang Wang (Code Review)
Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30466
Change subject: fu540: add code to initialize flash
......................................................................
fu540: add code to initialize flash
SiFive's ZSBL has initialized flash, but only 16MB of space is
available. I fixed it to use all 32MB.
Change-Id: I8cd803369da5526eff90400c15b91bbf6b477c69
Signed-off-by: Xiang Wang <wxjstz(a)126.com>
---
M src/mainboard/sifive/hifive-unleashed/Makefile.inc
A src/mainboard/sifive/hifive-unleashed/bootblock.c
A src/mainboard/sifive/hifive-unleashed/flash.c
M src/mainboard/sifive/hifive-unleashed/romstage.c
M src/soc/sifive/fu540/Makefile.inc
A src/soc/sifive/fu540/include/soc/spi.h
A src/soc/sifive/fu540/include/soc/spi_flash.h
A src/soc/sifive/fu540/spi.c
8 files changed, 506 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/30466/1
diff --git a/src/mainboard/sifive/hifive-unleashed/Makefile.inc b/src/mainboard/sifive/hifive-unleashed/Makefile.inc
index 27ddcba..2dac283 100644
--- a/src/mainboard/sifive/hifive-unleashed/Makefile.inc
+++ b/src/mainboard/sifive/hifive-unleashed/Makefile.inc
@@ -11,6 +11,10 @@
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
+bootblock-y += flash.c
+bootblock-y += bootblock.c
+
+romstage-y += flash.c
romstage-y += romstage.c
bootblock-y += memlayout.ld
diff --git a/src/mainboard/sifive/hifive-unleashed/bootblock.c b/src/mainboard/sifive/hifive-unleashed/bootblock.c
new file mode 100644
index 0000000..777b2aa
--- /dev/null
+++ b/src/mainboard/sifive/hifive-unleashed/bootblock.c
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 HardenedLinux
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/addressmap.h>
+#include <soc/spi.h>
+#include <soc/spi_flash.h>
+#include <soc/clock.h>
+
+extern void flash_init(void);
+extern void bootblock_mainboard_init(void);
+
+void bootblock_mainboard_init(void)
+{
+ flash_init();
+}
diff --git a/src/mainboard/sifive/hifive-unleashed/flash.c b/src/mainboard/sifive/hifive-unleashed/flash.c
new file mode 100644
index 0000000..a29ac24
--- /dev/null
+++ b/src/mainboard/sifive/hifive-unleashed/flash.c
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 HardenedLinux
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/addressmap.h>
+#include <soc/spi.h>
+#include <soc/spi_flash.h>
+#include <soc/clock.h>
+
+extern void flash_init(void);
+
+const static spi_reg_ffmt ffmt= {
+ .cmd_en = 1,
+ .addr_len = 4,
+ .pad_cnt = 8,
+ .command_proto = SPI_PROTO_S,
+ .addr_proto = SPI_PROTO_S,
+ .data_proto = SPI_PROTO_Q,
+ .command_code = 0x6c
+};
+
+
+void flash_init(void)
+{
+ initialize_spi_flash_mmap_quad(
+ (spi_ctrl*)FU540_QSPI0,
+ clock_get_tlclk_khz(),
+ ffmt.raw_bits,
+ 0x66,
+ 0x99);
+}
diff --git a/src/mainboard/sifive/hifive-unleashed/romstage.c b/src/mainboard/sifive/hifive-unleashed/romstage.c
index 8277141..1675aca 100644
--- a/src/mainboard/sifive/hifive-unleashed/romstage.c
+++ b/src/mainboard/sifive/hifive-unleashed/romstage.c
@@ -21,6 +21,8 @@
#include <soc/clock.h>
#include <soc/sdram.h>
+extern void flash_init(void);
+
void main(void)
{
console_init();
@@ -39,6 +41,7 @@
if (IS_ENABLED(CONFIG_CONSOLE_SERIAL))
uart_init(CONFIG_UART_FOR_CONSOLE);
+ flash_init();
sdram_init();
cbmem_initialize_empty();
diff --git a/src/soc/sifive/fu540/Makefile.inc b/src/soc/sifive/fu540/Makefile.inc
index 4f62f3e..83c7b1c 100644
--- a/src/soc/sifive/fu540/Makefile.inc
+++ b/src/soc/sifive/fu540/Makefile.inc
@@ -18,6 +18,7 @@
bootblock-y += media.c
bootblock-y += bootblock.c
bootblock-y += clock.c
+bootblock-y += spi.c
romstage-y += uart.c
romstage-y += clint.c
@@ -26,6 +27,7 @@
romstage-y += cbmem.c
romstage-y += otp.c
romstage-y += clock.c
+romstage-y += spi.c
ramstage-y += uart.c
ramstage-y += clint.c
@@ -34,6 +36,7 @@
ramstage-y += cbmem.c
ramstage-y += otp.c
ramstage-y += clock.c
+ramstage-y += spi.c
CPPFLAGS_common += -Isrc/soc/sifive/fu540/include
diff --git a/src/soc/sifive/fu540/include/soc/spi.h b/src/soc/sifive/fu540/include/soc/spi.h
new file mode 100644
index 0000000..c40ae7c
--- /dev/null
+++ b/src/soc/sifive/fu540/include/soc/spi.h
@@ -0,0 +1,266 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 SiFive, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef __SOC_SIFIVE_HIFIVE_U_SPI_H__
+#define __SOC_SIFIVE_HIFIVE_U_SPI_H__
+
+#include <stdint.h>
+
+#define _ASSERT_SIZEOF(type, size) _Static_assert(sizeof(type) == (size), #type " must be " #size " bytes wide")
+
+typedef union
+{
+ struct
+ {
+ uint32_t pha : 1;
+ uint32_t pol : 1;
+ uint32_t reserved : 30;
+ };
+ uint32_t raw_bits;
+} spi_reg_sckmode;
+_ASSERT_SIZEOF(spi_reg_sckmode, 4);
+
+
+typedef union
+{
+ struct
+ {
+ uint32_t mode : 2;
+ uint32_t reserved : 30;
+ };
+ uint32_t raw_bits;
+} spi_reg_csmode;
+_ASSERT_SIZEOF(spi_reg_csmode, 4);
+
+
+typedef union
+{
+ struct
+ {
+ uint32_t cssck : 8;
+ uint32_t reserved0 : 8;
+ uint32_t sckcs : 8;
+ uint32_t reserved1 : 8;
+ };
+ uint32_t raw_bits;
+} spi_reg_delay0;
+_ASSERT_SIZEOF(spi_reg_delay0, 4);
+
+
+typedef union
+{
+ struct
+ {
+ uint32_t intercs : 8;
+ uint32_t reserved0 : 8;
+ uint32_t interxfr : 8;
+ uint32_t reserved1 : 8;
+ };
+ uint32_t raw_bits;
+} spi_reg_delay1;
+_ASSERT_SIZEOF(spi_reg_delay1, 4);
+
+
+typedef union
+{
+ struct
+ {
+ uint32_t proto : 2;
+ uint32_t endian : 1;
+ uint32_t dir : 1;
+ uint32_t reserved0 : 12;
+ uint32_t len : 4;
+ uint32_t reserved1 : 12;
+ };
+ uint32_t raw_bits;
+} spi_reg_fmt;
+_ASSERT_SIZEOF(spi_reg_fmt, 4);
+
+
+typedef union
+{
+ struct
+ {
+ uint32_t data : 8;
+ uint32_t reserved : 23;
+ uint32_t full : 1;
+ };
+ uint32_t raw_bits;
+} spi_reg_txdata;
+_ASSERT_SIZEOF(spi_reg_txdata, 4);
+
+
+typedef union
+{
+ struct
+ {
+ uint32_t data : 8;
+ uint32_t reserved : 23;
+ uint32_t empty : 1;
+ };
+ uint32_t raw_bits;
+} spi_reg_rxdata;
+_ASSERT_SIZEOF(spi_reg_rxdata, 4);
+
+
+typedef union
+{
+ struct
+ {
+ uint32_t txmark : 3;
+ uint32_t reserved : 29;
+ };
+ uint32_t raw_bits;
+} spi_reg_txmark;
+_ASSERT_SIZEOF(spi_reg_txmark, 4);
+
+
+typedef union
+{
+ struct
+ {
+ uint32_t rxmark : 3;
+ uint32_t reserved : 29;
+ };
+ uint32_t raw_bits;
+} spi_reg_rxmark;
+_ASSERT_SIZEOF(spi_reg_rxmark, 4);
+
+
+typedef union
+{
+ struct
+ {
+ uint32_t en : 1;
+ uint32_t reserved : 31;
+ };
+ uint32_t raw_bits;
+} spi_reg_fctrl;
+_ASSERT_SIZEOF(spi_reg_fctrl, 4);
+
+
+typedef union
+{
+ struct
+ {
+ uint32_t cmd_en : 1;
+ uint32_t addr_len : 3;
+ uint32_t pad_cnt : 4;
+ uint32_t command_proto : 2;
+ uint32_t addr_proto : 2;
+ uint32_t data_proto : 2;
+ uint32_t reserved : 2;
+ uint32_t command_code : 8;
+ uint32_t pad_code : 8;
+ };
+ uint32_t raw_bits;
+} spi_reg_ffmt;
+_ASSERT_SIZEOF(spi_reg_ffmt, 4);
+
+
+typedef union
+{
+ struct
+ {
+ uint32_t txwm : 1;
+ uint32_t rxwm : 1;
+ uint32_t reserved : 30;
+ };
+ uint32_t raw_bits;
+} spi_reg_ie;
+typedef spi_reg_ie spi_reg_ip;
+_ASSERT_SIZEOF(spi_reg_ie, 4);
+_ASSERT_SIZEOF(spi_reg_ip, 4);
+
+#undef _ASSERT_SIZEOF
+
+
+/**
+ * SPI control register memory map.
+ *
+ * All functions take a pointer to a SPI device's control registers.
+ */
+typedef volatile struct
+{
+ uint32_t sckdiv;
+ spi_reg_sckmode sckmode;
+ uint32_t reserved08;
+ uint32_t reserved0c;
+
+ uint32_t csid;
+ uint32_t csdef;
+ spi_reg_csmode csmode;
+ uint32_t reserved1c;
+
+ uint32_t reserved20;
+ uint32_t reserved24;
+ spi_reg_delay0 delay0;
+ spi_reg_delay1 delay1;
+
+ uint32_t reserved30;
+ uint32_t reserved34;
+ uint32_t reserved38;
+ uint32_t reserved3c;
+
+ spi_reg_fmt fmt;
+ uint32_t reserved44;
+ spi_reg_txdata txdata;
+ spi_reg_rxdata rxdata;
+
+ spi_reg_txmark txmark;
+ spi_reg_rxmark rxmark;
+ uint32_t reserved58;
+ uint32_t reserved5c;
+
+ spi_reg_fctrl fctrl;
+ spi_reg_ffmt ffmt;
+ uint32_t reserved68;
+ uint32_t reserved6c;
+
+ spi_reg_ie ie;
+ spi_reg_ip ip;
+} spi_ctrl;
+
+
+void spi_tx(spi_ctrl* spictrl, uint8_t in);
+uint8_t spi_rx(spi_ctrl* spictrl);
+uint8_t spi_txrx(spi_ctrl* spictrl, uint8_t in);
+
+// Inlining header functions in C
+// https://stackoverflow.com/a/23699777/7433423
+
+/**
+ * Get smallest clock divisor that divides input_khz to a quotient less than or
+ * equal to max_target_khz;
+ */
+static inline unsigned int spi_min_clk_divisor(unsigned int input_khz, unsigned int max_target_khz)
+{
+ // f_sck = f_in / (2 * (div + 1)) => div = (f_in / (2*f_sck)) - 1
+ //
+ // The nearest integer solution for div requires rounding up as to not exceed
+ // max_target_khz.
+ //
+ // div = ceil(f_in / (2*f_sck)) - 1
+ // = floor((f_in - 1 + 2*f_sck) / (2*f_sck)) - 1
+ //
+ // This should not overflow as long as (f_in - 1 + 2*f_sck) does not exceed
+ // 2^32 - 1, which is unlikely since we represent frequencies in kHz.
+ unsigned int quotient = (input_khz + 2 * max_target_khz - 1) / (2 * max_target_khz);
+ // Avoid underflow
+ if (quotient == 0)
+ return 0;
+ return quotient - 1;
+}
+
+#endif /* __SOC_SIFIVE_HIFIVE_U_SPI_H__ */
diff --git a/src/soc/sifive/fu540/include/soc/spi_flash.h b/src/soc/sifive/fu540/include/soc/spi_flash.h
new file mode 100644
index 0000000..9926b82
--- /dev/null
+++ b/src/soc/sifive/fu540/include/soc/spi_flash.h
@@ -0,0 +1,103 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 SiFive, Inc
+ * Copyright (C) 2018 HardenedLinux
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __SOC_SIFIVE_HIFIVE_U_SPI_FLASH_H__
+#define __SOC_SIFIVE_HIFIVE_U_SPI_FLASH_H__
+
+#include <soc/spi.h>
+#include <stdint.h>
+
+#define SPI_PROTO_S 0
+#define SPI_PROTO_D 1
+#define SPI_PROTO_Q 2
+
+/**
+ * Set up SPI for direct, non-memory-mapped access.
+ */
+
+static inline int initialize_spi_flash_direct(
+ spi_ctrl* spictrl,
+ unsigned int spi_clk_input_khz,
+ unsigned int command_enable,
+ unsigned int command_reset)
+{
+ // Max desired SPI clock is 10MHz
+ spictrl->sckdiv = spi_min_clk_divisor(spi_clk_input_khz, 10000);
+
+ spictrl->fctrl.en = 0;
+
+ spi_txrx(spictrl, command_enable);
+ spi_txrx(spictrl, command_reset);
+
+ return 0;
+}
+
+static inline int _initialize_spi_flash_mmap(
+ spi_ctrl* spictrl,
+ unsigned int spi_clk_input_khz,
+ uint32_t ffmt_rawbits,
+ unsigned int command_enable,
+ unsigned int command_reset)
+{
+ // Max desired SPI clock is 10MHz
+ spictrl->sckdiv = spi_min_clk_divisor(spi_clk_input_khz, 10000);
+
+ spictrl->fctrl.en = 0;
+
+ spi_txrx(spictrl, command_enable);
+ spi_txrx(spictrl, command_reset);
+
+ spictrl->ffmt.raw_bits = ffmt_rawbits;
+
+ spictrl->fctrl.en = 1;
+ __asm__ __volatile__ ("fence io, io");
+ return 0;
+}
+
+
+static inline int initialize_spi_flash_mmap_single(
+ spi_ctrl* spictrl,
+ unsigned int spi_clk_input_khz,
+ uint32_t ffmt_rawbits,
+ unsigned int command_enable,
+ unsigned int command_reset)
+{
+ return _initialize_spi_flash_mmap(
+ spictrl,
+ spi_clk_input_khz,
+ ffmt_rawbits,
+ command_enable,
+ command_reset);
+}
+
+
+static inline int initialize_spi_flash_mmap_quad(
+ spi_ctrl* spictrl,
+ unsigned int spi_clk_input_khz,
+ uint32_t ffmt_rawbits,
+ unsigned int command_enable,
+ unsigned int command_reset)
+{
+ return _initialize_spi_flash_mmap(
+ spictrl,
+ spi_clk_input_khz,
+ ffmt_rawbits,
+ command_enable,
+ command_reset);
+}
+
+#endif /* __SOC_SIFIVE_HIFIVE_U_SPI_FLASH_H__ */
+
diff --git a/src/soc/sifive/fu540/spi.c b/src/soc/sifive/fu540/spi.c
new file mode 100644
index 0000000..01a58dd
--- /dev/null
+++ b/src/soc/sifive/fu540/spi.c
@@ -0,0 +1,58 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 SiFive, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/spi.h>
+
+/**
+ * Wait until SPI is ready for transmission and transmit byte.
+ */
+void spi_tx(spi_ctrl* spictrl, uint8_t in)
+{
+#if __riscv_atomic
+ int32_t r;
+ do {
+ asm volatile (
+ "amoor.w %0, %2, %1\n"
+ : "=r" (r), "+A" (spictrl->txdata.raw_bits)
+ : "r" (in)
+ );
+ } while (r < 0);
+#else
+ while ((int32_t) spictrl->txdata.raw_bits < 0);
+ spictrl->txdata.data = in;
+#endif
+}
+
+
+/**
+ * Wait until SPI receive queue has data and read byte.
+ */
+uint8_t spi_rx(spi_ctrl* spictrl)
+{
+ int32_t out;
+ while ((out = (int32_t) spictrl->rxdata.raw_bits) < 0);
+ return (uint8_t) out;
+}
+
+
+/**
+ * Transmit a byte and receive a byte.
+ */
+uint8_t spi_txrx(spi_ctrl* spictrl, uint8_t in)
+{
+ spi_tx(spictrl, in);
+ return spi_rx(spictrl);
+}
+
--
To view, visit https://review.coreboot.org/c/coreboot/+/30466
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I8cd803369da5526eff90400c15b91bbf6b477c69
Gerrit-Change-Number: 30466
Gerrit-PatchSet: 1
Gerrit-Owner: Xiang Wang <wxjstz(a)126.com>
Gerrit-MessageType: newchange
2 days, 13 hours
Change in ...coreboot[master]: drivers/smmstore: Fix some issues
by Arthur Heymans (Code Review)
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30432
Change subject: drivers/smmstore: Fix some issues
......................................................................
drivers/smmstore: Fix some issues
This fixes the following:
- Make the API ARCH independent (no dependency on size_t)
- clean up the code a little
Change-Id: I629be25d2a9b65796ae8f7a700b6bdab57b91b22
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/drivers/smmstore/store.c
M src/include/smmstore.h
M src/soc/intel/common/block/smm/smihandler.c
3 files changed, 86 insertions(+), 67 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/30432/1
diff --git a/src/drivers/smmstore/store.c b/src/drivers/smmstore/store.c
index 409949a..0a62b3c 100644
--- a/src/drivers/smmstore/store.c
+++ b/src/drivers/smmstore/store.c
@@ -62,8 +62,8 @@
if (cbfs_locate_file_in_region(&file,
CONFIG_SMMSTORE_REGION,
CONFIG_SMMSTORE_FILENAME, NULL) < 0) {
- printk(BIOS_WARNING, "smm store: "
- "Unable to find SMM store file in region '%s'\n",
+ printk(BIOS_WARNING,
+ "smm store: Unable to find SMM store file in region '%s'\n",
CONFIG_SMMSTORE_REGION);
return -1;
}
@@ -87,14 +87,13 @@
* returns 0 on success, -1 on failure
* writes up to `*bufsize` bytes into `buf` and updates `*bufsize`
*/
-int smmstore_read_region(void *buf, ssize_t *bufsize)
+int smmstore_read_region(void *buf, uint32_t *bufsize)
{
struct region_device store;
if (bufsize == NULL)
return -1;
- *bufsize = 0;
if (lookup_store(&store) < 0) {
printk(BIOS_WARNING, "reading region failed\n");
return -1;
@@ -109,6 +108,66 @@
return 0;
}
+static enum cb_err scan_end(ssize_t *end)
+{
+ struct region_device store;
+
+ if (lookup_store(&store) < 0) {
+ printk(BIOS_WARNING, "reading region failed\n");
+ return CB_ERR;
+ }
+ ssize_t data_sz = region_device_sz(&store);
+
+ /* scan for end */
+ *end = 0;
+ uint32_t k_sz, v_sz;
+ while (*end < data_sz) {
+ /* make odd corner cases identifiable, eg. invalid v_sz */
+ k_sz = 0;
+
+ if (rdev_readat(&store, &k_sz, *end, sizeof(k_sz)) < 0) {
+ printk(BIOS_WARNING, "failed reading key size\n");
+ return CB_ERR;
+ }
+
+ /* found the end */
+ if (k_sz == 0xffffffff)
+ break;
+
+ /* something is fishy here:
+ * Avoid wrapping (since data_size < MAX_UINT32_T / 2) while
+ * other problems are covered by the loop condition
+ */
+ if (k_sz > data_sz) {
+ printk(BIOS_WARNING, "key size out of bounds\n");
+ return CB_ERR;
+ }
+
+ if (rdev_readat(&store, &v_sz, *end + 4, sizeof(v_sz)) < 0) {
+ printk(BIOS_WARNING, "failed reading value size\n");
+ return CB_ERR;
+ }
+
+ if (v_sz > data_sz) {
+ printk(BIOS_WARNING, "value size out of bounds\n");
+ return CB_ERR;
+ }
+
+ *end += sizeof(k_sz) + sizeof(v_sz) + k_sz + v_sz + 1;
+ *end = ALIGN_UP(*end, sizeof(uint32_t));
+ }
+
+ printk(BIOS_WARNING, "used smm store size might be 0x%zx bytes\n", *end);
+
+ if (k_sz != 0xffffffff) {
+ printk(BIOS_WARNING,
+ "eof of data marker looks invalid: 0x%x\n", k_sz);
+ return CB_ERR;
+ }
+
+ return CB_SUCCESS;
+
+}
/*
* Append data to region
*
@@ -124,78 +183,38 @@
return -1;
}
- ssize_t data_sz = region_device_sz(&store);
-
- /* scan for end */
- ssize_t end = 0;
- uint32_t k_sz, v_sz;
- while (end < data_sz) {
- /* make odd corner cases identifiable, eg. invalid v_sz */
- k_sz = 0;
-
- if (rdev_readat(&store, &k_sz, end, sizeof(k_sz)) < 0) {
- printk(BIOS_WARNING, "failed reading key size\n");
- return -1;
- }
-
- /* found the end */
- if (k_sz == 0xffffffff)
- break;
-
- /* something is fishy here:
- * Avoid wrapping (since data_size < MAX_UINT32_T / 2) while
- * other problems are covered by the loop condition
- */
- if (k_sz > data_sz) {
- printk(BIOS_WARNING, "key size out of bounds\n");
- return -1;
- }
-
- if (rdev_readat(&store, &v_sz, end + 4, sizeof(v_sz)) < 0) {
- printk(BIOS_WARNING, "failed reading value size\n");
- return -1;
- }
-
- if (v_sz > data_sz) {
- printk(BIOS_WARNING, "value size out of bounds\n");
- return -1;
- }
-
- end += 8 + k_sz + v_sz + 1;
- end = ALIGN_UP(end, sizeof(uint32_t));
- }
-
- printk(BIOS_WARNING, "used smm store size might be 0x%zx bytes\n", end);
-
- if (k_sz != 0xffffffff) {
- printk(BIOS_WARNING,
- "eof of data marker looks invalid: 0x%x\n", k_sz);
+ ssize_t end;
+ if (scan_end(&end) == CB_ERR)
return -1;
- }
printk(BIOS_WARNING, "used size looks legit\n");
printk(BIOS_WARNING, "open (%zx, %zx) for writing\n",
region_device_offset(&store), region_device_sz(&store));
- if (boot_device_rw_subregion(&store.region, &store) < 0) {
+ if (boot_device_rw_subregion(region_device_region(&store), &store) < 0) {
printk(BIOS_WARNING, "couldn't open store for writing\n");
return -1;
}
- uint32_t record_sz = 8 + key_sz + value_sz + 1;
- if (end + record_sz >= data_sz) {
+ struct region subregion =
+ {
+ .offset = end,
+ .size = sizeof(key_sz) + sizeof(value_sz) + key_sz + value_sz + 1,
+ };
+
+ if (region_is_subregion(region_device_region(&store), &subregion)) {
printk(BIOS_WARNING, "not enough space for new data\n");
return -1;
}
- if (rdev_writeat(&store, &key_sz, end, 4) != 4) {
+ if (rdev_writeat(&store, &key_sz, end, sizeof(key_sz) != sizeof(key_sz))) {
printk(BIOS_WARNING, "failed writing key size\n");
}
- end += 4;
- if (rdev_writeat(&store, &value_sz, end, 4) != 4) {
+ end += sizeof(key_sz);
+ if (rdev_writeat(&store, &value_sz, end, sizeof(value_sz) != sizeof(key_sz))) {
printk(BIOS_WARNING, "failed writing value size\n");
}
- end += 4;
+ end += sizeof(value_sz);
if (rdev_writeat(&store, key, end, key_sz) != key_sz) {
printk(BIOS_WARNING, "failed writing key data\n");
}
@@ -205,7 +224,7 @@
}
end += value_sz;
uint8_t nul = 0;
- if (rdev_writeat(&store, &nul, end, 1) != 1) {
+ if (rdev_writeat(&store, &nul, end, sizeof(nul)) != sizeof(nul)) {
printk(BIOS_WARNING, "failed writing termination\n");
}
diff --git a/src/include/smmstore.h b/src/include/smmstore.h
index a535c5b..30a8191 100644
--- a/src/include/smmstore.h
+++ b/src/include/smmstore.h
@@ -28,22 +28,22 @@
#define SMMSTORE_CMD_APPEND 3
struct smmstore_params_read {
- void *buf;
- ssize_t bufsize;
+ uint32_t *buf;
+ uint32_t bufsize;
};
struct smmstore_params_append {
- void *key;
- size_t keysize;
- void *val;
- size_t valsize;
+ uint32_t *key;
+ uint32_t keysize;
+ uint32_t *val;
+ uint32_t valsize;
};
/* SMM responder */
uint32_t smmstore_exec(uint8_t command, void *param);
/* implementation */
-int smmstore_read_region(void *buf, ssize_t *bufsize);
+int smmstore_read_region(void *buf, uint32_t *bufsize);
int smmstore_append_data(void *key, uint32_t key_sz,
void *value, uint32_t value_sz);
int smmstore_clear_region(void);
diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c
index 2ffc00f..c125c0c 100644
--- a/src/soc/intel/common/block/smm/smihandler.c
+++ b/src/soc/intel/common/block/smm/smihandler.c
@@ -311,7 +311,7 @@
reg_ebx = save_state_ops->get_reg(io_smi, RBX);
/* drivers/smmstore/smi.c */
- ret = smmstore_exec(sub_command, (void *)reg_ebx);
+ ret = smmstore_exec(sub_command, (uintptr_t *)reg_ebx);
save_state_ops->set_reg(io_smi, RAX, ret);
}
--
To view, visit https://review.coreboot.org/c/coreboot/+/30432
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I629be25d2a9b65796ae8f7a700b6bdab57b91b22
Gerrit-Change-Number: 30432
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-MessageType: newchange
3 days
Change in ...coreboot[master]: mb/google/hatch: Enable PCIe WLAN and BT
by Maulik V Vaghela (Code Review)
Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30467
Change subject: mb/google/hatch: Enable PCIe WLAN and BT
......................................................................
mb/google/hatch: Enable PCIe WLAN and BT
Enable PCIe WLAN for hatch
1. Enable PCI Rp#13 for PCIe WLAN
2. Enable PCI clock source 3 for PCI port 13
3. GPIO pad config for WLAN and BT
USB port for BT has already been enabled so not included in this patch
BUG=b:120914069
BRANCH=none
TEST=check if code compiles correctly and verify GPIO configuration with
schematics
Change-Id: I4f2a6eb37a467ad8b8cdde8fe6b657fabb383b04
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com>
---
M src/mainboard/google/hatch/variants/baseboard/devicetree.cb
M src/mainboard/google/hatch/variants/baseboard/gpio.c
2 files changed, 22 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/30467/1
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
index 0e80ab3..1ad5589 100644
--- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
@@ -49,7 +49,6 @@
register "SataPortsDevSlp[1]" = "1"
register "satapwroptimize" = "1"
-
# Enable Root port 9(x4) for NVMe.
register "PcieRpEnable[8]" = "1"
# RP 9 uses CLK SRC 1
@@ -57,6 +56,12 @@
# ClkReq-to-ClkSrc mapping for CLK SRC 1
register "PcieClkSrcClkReq[1]" = "1"
+ # PCIe port 13 for M.2 E-key WLAN
+ register "PcieRpEnable[13]" = "1"
+ # RP 13 uses CLK SRC 3
+ register "PcieClkSrcUsage[3]" = "13"
+ register "PcieClkSrcClkReq[3]" = "3"
+
device domain 0 on
device pci 00.0 off end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device
@@ -119,7 +124,12 @@
device pci 1d.1 off end # PCI Express Port 10
device pci 1d.2 off end # PCI Express Port 11
device pci 1d.3 off end # PCI Express Port 12
- device pci 1d.4 off end # PCI Express Port 13 (x4)
+ device pci 1d.4 on
+ chip drivers/intel/wifi
+ register "wake" = "GPE0_DW1_01"
+ device pci 00.0 on end
+ end
+ end # PCI Express Port 13 (x4)
device pci 1e.0 on end # UART #0
device pci 1e.1 off end # UART #1
device pci 1e.2 on
diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c
index ce78bb5..4a6341f 100644
--- a/src/mainboard/google/hatch/variants/baseboard/gpio.c
+++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c
@@ -23,6 +23,8 @@
PAD_CFG_GPI_APIC(GPP_A21, NONE, PLTRST, LEVEL, INVERT),
/* SRCCLKREQ1 */
PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
+ /* PCIE_14_WLAN_CLKREQ_ODL */
+ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
/* H1_SLAVE_SPI_CS_L */
PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
/* H1_SLAVE_SPI_CLK */
@@ -31,12 +33,16 @@
PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
/* H1_SLAVE_SPI_MOSI_R */
PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
+ /* PCIE_14_WLAN_WAKE_ODL */
+ PAD_CFG_GPI(GPP_C1, NONE, PLTRST),
/* TOUCHSCREEN_DIS_L */
PAD_CFG_GPO(GPP_C4, 1, DEEP),
/* GPP_C10_TP */
PAD_NC(GPP_C10, DN_20K),
/* GPP_C11_TP */
PAD_NC(GPP_C11, DN_20K),
+ /* BT_DISABLE_L */
+ PAD_CFG_GPO(GPP_C14, 1, DEEP),
/* PCH_I2C_TRACKPAD_SDA */
PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
/* PCH_I2C_TRACKPAD_SCL */
@@ -45,12 +51,14 @@
PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
/* PCH_I2C_TOUCHSCREEN_SCL */
PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
- /* H1_PCH_INT_ODL */
- PAD_CFG_GPI_APIC(GPP_C21, NONE, DEEP, LEVEL, INVERT),
/* PCH_WP_OD */
PAD_CFG_GPI(GPP_C20, NONE, DEEP),
+ /* H1_PCH_INT_ODL */
+ PAD_CFG_GPI_APIC(GPP_C21, NONE, DEEP, LEVEL, INVERT),
/* EC_IN_RW_OD */
PAD_CFG_GPI(GPP_C22, NONE, DEEP),
+ /* WLAN_PE_RST# */
+ PAD_CFG_GPO(GPP_C23, 1, DEEP),
/* TOUCHSCREEN_RST_L */
PAD_CFG_GPO(GPP_D15, 1, DEEP),
/* TOUCHSCREEN_INT_L */
--
To view, visit https://review.coreboot.org/c/coreboot/+/30467
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I4f2a6eb37a467ad8b8cdde8fe6b657fabb383b04
Gerrit-Change-Number: 30467
Gerrit-PatchSet: 1
Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com>
Gerrit-MessageType: newchange
3 days, 15 hours
Change in ...coreboot[master]: Makefile.inc: Create a default SMMSTORE region
by Arthur Heymans (Code Review)
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30421
Change subject: Makefile.inc: Create a default SMMSTORE region
......................................................................
Makefile.inc: Create a default SMMSTORE region
Change-Id: I7b7b75050e0139ea9a0a4f2ad3c0d69a482fb38b
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M Makefile.inc
M src/drivers/smmstore/Kconfig
M util/cbfstool/default-x86.fmd
3 files changed, 26 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/30421/1
diff --git a/Makefile.inc b/Makefile.inc
index 8af291f..7dee1d2 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -869,11 +869,27 @@
endif # ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y)
#
+# X86 SMMSTORE FMAP region
+#
+# position, size and entry line of SMMSTORE relative to BIOS_BASE, if enabled
+ifeq ($(CONFIG_SMMSTORE),y)
+FMAP_SMMSTORE_BASE := $(call int-align, $(call int-add, $(FMAP_CONSOLE_BASE) \
+ $(FMAP_CONSOLE_SIZE) $(FMAP_MRC_CACHE_SIZE)), 0x10000)
+FMAP_SMMSTORE_SIZE := $(CONFIG_SMMSTORE_SIZE)
+FMAP_SMMSTORE_ENTRY := SMMSTORE@$(FMAP_SMMSTORE_BASE) $(FMAP_SMMSTORE_SIZE)
+else # ifeq ($(CONFIG_SMMSTORE),y)
+FMAP_SMMSTORE_BASE := 0
+FMAP_SMMSTORE_SIZE := 0
+FMAP_SMMSTORE_ENTRY :=
+endif # ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y)
+
+#
# X86 FMAP region
#
#
# position, size
-FMAP_FMAP_BASE := $(call int-add, $(FMAP_CONSOLE_SIZE) $(FMAP_MRC_CACHE_SIZE))
+FMAP_FMAP_BASE := $(call int-add, $(FMAP_CONSOLE_BASE) $(FMAP_CONSOLE_SIZE) \
+ $(FMAP_MRC_CACHE_SIZE) $(FMAP_SMMSTORE_SIZE))
FMAP_FMAP_SIZE := 0x200
#
@@ -947,6 +963,7 @@
-e "s,##FMAP_SIZE##,$(FMAP_FMAP_SIZE)," \
-e "s,##CONSOLE_ENTRY##,$(FMAP_CONSOLE_ENTRY)," \
-e "s,##MRC_CACHE_ENTRY##,$(FMAP_MRC_CACHE_ENTRY)," \
+ -e "s,##SMMSTORE_ENTRY##,$(FMAP_SMMSTORE_ENTRY)," \
-e "s,##CBFS_BASE##,$(FMAP_CBFS_BASE)," \
-e "s,##CBFS_SIZE##,$(FMAP_CBFS_SIZE)," \
$(DEFAULT_FLASHMAP) > $@.tmp
diff --git a/src/drivers/smmstore/Kconfig b/src/drivers/smmstore/Kconfig
index 1ab3a5e..f2c97ab 100644
--- a/src/drivers/smmstore/Kconfig
+++ b/src/drivers/smmstore/Kconfig
@@ -37,4 +37,11 @@
string "SMM store file name" if SMMSTORE_IN_CBFS
default "smm_store"
+config SMMSTORE_SIZE
+ hex "size of the SMMSTORE FMAP region"
+ depends on !SMMSTORE_IN_CBFS
+ default 0x40000
+ help
+ Set the size of the default SMMSTORE FMAP region.
+
endif
diff --git a/util/cbfstool/default-x86.fmd b/util/cbfstool/default-x86.fmd
index 174db1f..f0143e9 100644
--- a/util/cbfstool/default-x86.fmd
+++ b/util/cbfstool/default-x86.fmd
@@ -11,6 +11,7 @@
BIOS@##BIOS_BASE## ##BIOS_SIZE## {
##CONSOLE_ENTRY##
##MRC_CACHE_ENTRY##
+ ##SMMSTORE_ENTRY##
FMAP@##FMAP_BASE## ##FMAP_SIZE##
COREBOOT(CBFS)@##CBFS_BASE## ##CBFS_SIZE##
}
--
To view, visit https://review.coreboot.org/c/coreboot/+/30421
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I7b7b75050e0139ea9a0a4f2ad3c0d69a482fb38b
Gerrit-Change-Number: 30421
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-MessageType: newchange
4 days, 4 hours
Change in ...coreboot[master]: soc/intel/cannonlake: Add option for boot frquency
by Lijian Zhao (Code Review)
Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30445
Change subject: soc/intel/cannonlake: Add option for boot frquency
......................................................................
soc/intel/cannonlake: Add option for boot frquency
Cannonlake/Coffeelake FSP have options for CPU boot up frequency
selection, expose that in coreboot side.
Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com>
Change-Id: I6bd5849122c9035bb7f448acf08e258e8c207013
---
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/romstage/fsp_params.c
2 files changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/30445/1
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 3a723d2..7e50a73 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -110,6 +110,11 @@
SaGv_Enabled,
} SaGv;
+ /* Boot Frequency from reset vector.
+ * 0: Maximum battery performance, 1: Maximum non-turbo performance, 2:
+ * Maximum turbo performance @note If 2 is selected, system will start
+ * with non-turbo mode and then switch to turbo. */
+ uint8_t bootfreq;
/* Rank Margin Tool. 1:Enable, 0:Disable */
uint8_t RMT;
diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c
index c3a2509..0514844 100644
--- a/src/soc/intel/cannonlake/romstage/fsp_params.c
+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c
@@ -54,6 +54,8 @@
#if IS_ENABLED(CONFIG_SOC_INTEL_COFFEELAKE)
m_cfg->SkipMpInit = !chip_get_fsp_mp_init();
#endif
+ m_cfg->BootFrequency = config->bootfreq;
+
/* If ISH is enabled, enable ISH elements */
if (!dev)
m_cfg->PchIshEnable = 0;
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I6bd5849122c9035bb7f448acf08e258e8c207013
Gerrit-Change-Number: 30445
Gerrit-PatchSet: 1
Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com>
Gerrit-MessageType: newchange
4 days, 22 hours
Change in ...coreboot[master]: src/soc/intel/common/block/pcie: Add a workaround for ThP2 9260
by Gaggery Tsai (Code Review)
Gaggery Tsai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30486
Change subject: src/soc/intel/common/block/pcie: Add a workaround for ThP2 9260
......................................................................
src/soc/intel/common/block/pcie: Add a workaround for ThP2 9260
This patch adds a workaround for ThP2. The PCIe root port LCTL2.TLS
is by default GEN1 and ThP has bad synchronization on polarity
inversion. When the root port request for speed change, ThP doesn’t
confirm the request, and both sides are moving to polling after
timeout, hot reset is issued, and then most of the CFG space is
initialized. From the observation, CCC/ECPM/LTR would be reset to
default but CCC/ECPM of root port and end devices have been
reconfigured in pci_scan. The LTR configuration for root port
is still missing.
BUG=B:117618636
BRANCH=None
TEST=Add THP2_9260_WORKAROUND in Atlas configuration & emerge-atlas
coreboot chromeos-bootimage & Warm/cold reset for 10 times and
didn't see unsupported request related AER error messages &
$lspci -vvs 00:1c.0|grep LTR and ensure LTR+ is present.
Change-Id: Id5d2814488fbc9db927edb2ead972b73ebc336ce
Signed-off-by: Gaggery Tsai <gaggery.tsai(a)intel.com>
---
M src/soc/intel/common/block/pcie/Kconfig
M src/soc/intel/common/block/pcie/pcie.c
2 files changed, 29 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/30486/1
diff --git a/src/soc/intel/common/block/pcie/Kconfig b/src/soc/intel/common/block/pcie/Kconfig
index aa32324..36915fa 100644
--- a/src/soc/intel/common/block/pcie/Kconfig
+++ b/src/soc/intel/common/block/pcie/Kconfig
@@ -13,3 +13,8 @@
Enable debug logs in PCIe module. Allows debug information on memory
base and limit, prefetchable memory base and limit, prefetchable memory
base upper 32 bits and prefetchable memory limit upper 32 bits.
+
+config THP2_9260_WORKAROUND
+ bool
+ help
+ THP2 workaround
diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c
index 3ebb4f6..07a2321 100644
--- a/src/soc/intel/common/block/pcie/pcie.c
+++ b/src/soc/intel/common/block/pcie/pcie.c
@@ -28,12 +28,36 @@
/* PCI-E Sub-System ID */
#define PCIE_SUBSYSTEM_VENDOR_ID 0x94
+/*
+ * Check the LTR for root port and enable it
+ */
+static void pciexp_enable_root_port_ltr(struct device *root, unsigned root_cap)
+{
+ u16 root_ltr;
+ unsigned int val;
+
+ val = pci_read_config16(root, root_cap + PCI_EXP_DEV_CAP2_OFFSET);
+
+ if (val & LTR_MECHANISM_SUPPORT) {
+ root_ltr = pci_read_config16(root, root_cap + PCI_EXP_DEV_CTL_STS2_CAP_OFFSET);
+ root_ltr |= LTR_MECHANISM_EN;
+ pci_write_config16(root, root_cap + PCI_EXP_DEV_CTL_STS2_CAP_OFFSET, root_ltr);
+ }
+}
+
static void pch_pcie_init(struct device *dev)
{
u16 reg16;
+ unsigned int dev_cap;
printk(BIOS_DEBUG, "Initializing PCH PCIe bridge.\n");
+ if (IS_ENABLED(CONFIG_THP2_9260_WORKAROUND)) {
+ dev_cap = pci_find_capability(dev, PCI_CAP_ID_PCIE);
+ if (dev_cap)
+ pciexp_enable_root_port_ltr(dev, dev_cap);
+ }
+
/* Enable SERR */
pci_or_config32(dev, PCI_COMMAND, PCI_COMMAND_SERR);
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Id5d2814488fbc9db927edb2ead972b73ebc336ce
Gerrit-Change-Number: 30486
Gerrit-PatchSet: 1
Gerrit-Owner: Gaggery Tsai <gaggery.tsai(a)intel.com>
Gerrit-MessageType: newchange
1 week
Change in ...coreboot[master]: WIP: mb/qemu-riscv: update to match current qemu version
by Philipp Hug (Code Review)
Philipp Hug has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30554
Change subject: WIP: mb/qemu-riscv: update to match current qemu version
......................................................................
WIP: mb/qemu-riscv: update to match current qemu version
Boots again to payload not found on qemu.
Change-Id: Ie107eb882cbaac5a5a06c1ff990e7b9364377640
Signed-off-by: Philipp Hug <philipp(a)hug.cx>
---
M src/mainboard/emulation/qemu-riscv/Kconfig
M src/mainboard/emulation/qemu-riscv/Makefile.inc
M src/mainboard/emulation/qemu-riscv/mainboard.c
M src/mainboard/emulation/qemu-riscv/memlayout.ld
D src/mainboard/emulation/qemu-riscv/mtime.c
M src/mainboard/emulation/qemu-riscv/rom_media.c
M src/mainboard/emulation/qemu-riscv/uart.c
7 files changed, 23 insertions(+), 38 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/30554/1
diff --git a/src/mainboard/emulation/qemu-riscv/Kconfig b/src/mainboard/emulation/qemu-riscv/Kconfig
index 528b21e..ecaa764 100644
--- a/src/mainboard/emulation/qemu-riscv/Kconfig
+++ b/src/mainboard/emulation/qemu-riscv/Kconfig
@@ -13,7 +13,8 @@
## GNU General Public License for more details.
# To execute, do:
-# qemu-system-arm -M vexpress-a9 -m 1024M -nographic -kernel build/coreboot.rom
+# util/riscv/make-spike-elf.sh build/coreboot.rom build/coreboot.elf
+# qemu-system-riscv64 -M virt -m 1024M -nographic -kernel build/coreboot.elf
if BOARD_EMULATION_QEMU_RISCV
diff --git a/src/mainboard/emulation/qemu-riscv/Makefile.inc b/src/mainboard/emulation/qemu-riscv/Makefile.inc
index 1d882ac..eb99544 100644
--- a/src/mainboard/emulation/qemu-riscv/Makefile.inc
+++ b/src/mainboard/emulation/qemu-riscv/Makefile.inc
@@ -14,7 +14,7 @@
bootblock-y += uart.c
bootblock-y += rom_media.c
-bootblock-y += mtime.c
+bootblock-y += clint.c
romstage-y += romstage.c
romstage-y += uart.c
@@ -22,8 +22,10 @@
ramstage-y += uart.c
ramstage-y += rom_media.c
-ramstage-y += mtime.c
+ramstage-y += clint.c
bootblock-y += memlayout.ld
romstage-y += memlayout.ld
ramstage-y += memlayout.ld
+
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
diff --git a/src/mainboard/emulation/qemu-riscv/mainboard.c b/src/mainboard/emulation/qemu-riscv/mainboard.c
index 7061bcf..4b428aa 100644
--- a/src/mainboard/emulation/qemu-riscv/mainboard.c
+++ b/src/mainboard/emulation/qemu-riscv/mainboard.c
@@ -16,6 +16,7 @@
#include <console/console.h>
#include <device/device.h>
#include <cbmem.h>
+#include <symbols.h>
static void mainboard_enable(struct device *dev)
{
@@ -24,7 +25,7 @@
die("No dev0; die\n");
}
- ram_resource(dev, 0, 2048, 32768);
+ ram_resource(dev, 0, (uintptr_t)_dram / KiB, CONFIG_DRAM_SIZE_MB * KiB);
cbmem_recovery(0);
}
diff --git a/src/mainboard/emulation/qemu-riscv/memlayout.ld b/src/mainboard/emulation/qemu-riscv/memlayout.ld
index 615d1f2..032fbdd 100644
--- a/src/mainboard/emulation/qemu-riscv/memlayout.ld
+++ b/src/mainboard/emulation/qemu-riscv/memlayout.ld
@@ -14,15 +14,16 @@
*/
#include <memlayout.h>
-
#include <arch/header.ld>
+#define START 0x80000000
+
SECTIONS
{
- DRAM_START(0x0)
- BOOTBLOCK(0x0, 64K)
- ROMSTAGE(0x20000, 128K)
- STACK(0x40000, 0x3ff00)
- PRERAM_CBMEM_CONSOLE(0x80000, 8K)
- RAMSTAGE(0x100000, 16M)
+ DRAM_START(START)
+ BOOTBLOCK(START, 64K)
+ STACK(START + 4M, 4K)
+ ROMSTAGE(START + 4M + 64K, 128K)
+ PRERAM_CBMEM_CONSOLE(START + 4M + 192K, 8K)
+ RAMSTAGE(START + 4M + 200K, 16M)
}
diff --git a/src/mainboard/emulation/qemu-riscv/mtime.c b/src/mainboard/emulation/qemu-riscv/mtime.c
deleted file mode 100644
index f8c2717..0000000
--- a/src/mainboard/emulation/qemu-riscv/mtime.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2018 HardenedLinux
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <mcall.h>
-
-/* FIXME: This is an empty implementation, please improve */
-/* This function is used to initialize HLS()->time/HLS()->timecmp */
-void mtime_init(void)
-{
-}
diff --git a/src/mainboard/emulation/qemu-riscv/rom_media.c b/src/mainboard/emulation/qemu-riscv/rom_media.c
index c171307..bac1984 100644
--- a/src/mainboard/emulation/qemu-riscv/rom_media.c
+++ b/src/mainboard/emulation/qemu-riscv/rom_media.c
@@ -14,11 +14,12 @@
* GNU General Public License for more details.
*/
#include <boot_device.h>
+#include <symbols.h>
-/* This assumes that the CBFS resides at 0x0, which is true for the default
- * configuration. */
+/* This assumes that the CBFS resides at start of dram, which is true for the
+ * default configuration. */
static const struct mem_region_device boot_dev =
- MEM_REGION_DEV_RO_INIT(NULL, CONFIG_ROM_SIZE);
+ MEM_REGION_DEV_RO_INIT(_dram, CONFIG_ROM_SIZE);
const struct region_device *boot_device_ro(void)
{
diff --git a/src/mainboard/emulation/qemu-riscv/uart.c b/src/mainboard/emulation/qemu-riscv/uart.c
index 730ef3e..084362a 100644
--- a/src/mainboard/emulation/qemu-riscv/uart.c
+++ b/src/mainboard/emulation/qemu-riscv/uart.c
@@ -17,8 +17,9 @@
#include <console/uart.h>
#include <arch/io.h>
#include <boot/coreboot_tables.h>
+#include <mainboard/addressmap.h>
-static uint8_t *buf = (void *)0x3f8;
+static uint8_t *buf = (void *)QEMU_VIRT_UART0;
uintptr_t uart_platform_base(int idx)
{
return (uintptr_t) buf;
@@ -47,7 +48,7 @@
{
struct lb_serial serial;
serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
- serial.baseaddr = 0x3f8;
+ serial.baseaddr = QEMU_VIRT_UART0;
serial.baud = 115200;
serial.regwidth = 1;
lb_add_serial(&serial, data);
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ie107eb882cbaac5a5a06c1ff990e7b9364377640
Gerrit-Change-Number: 30554
Gerrit-PatchSet: 1
Gerrit-Owner: Philipp Hug <philipp(a)hug.cx>
Gerrit-MessageType: newchange
2 weeks, 5 days
Change in ...coreboot[master]: src/superio/ite/common: Prepare for new SuperIO
by Michał Żygowski (Code Review)
Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30553
Change subject: src/superio/ite/common: Prepare for new SuperIO
......................................................................
src/superio/ite/common: Prepare for new SuperIO
Introduce 7bit Slope PWM registers. New ITE SuperIO may have contiguous
7bit values for PWM slope.
Add option to enable External Sensor SMBus Host.
Allow early SuperIO serial init in bootblock for platforms supporting
C_ENVIRONMENT_BOOTBLOCK.
Update/add registers macros for IT8786E-F which are not backwards
compatible.
Change-Id: I68fbfe62dfa05d0c166abaefbdc2ab873114b236
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
---
M src/superio/ite/Makefile.inc
M src/superio/ite/common/Kconfig
M src/superio/ite/common/env_ctrl.c
M src/superio/ite/common/env_ctrl.h
M src/superio/ite/common/env_ctrl_chip.h
5 files changed, 53 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/30553/1
diff --git a/src/superio/ite/Makefile.inc b/src/superio/ite/Makefile.inc
index 382dbd7..a54db6f 100644
--- a/src/superio/ite/Makefile.inc
+++ b/src/superio/ite/Makefile.inc
@@ -14,7 +14,11 @@
##
## include generic ite pre-ram stage driver
-romstage-$(CONFIG_SUPERIO_ITE_COMMON_ROMSTAGE) += common/early_serial.c
+
+ifeq ($(CONFIG_SUPERIO_ITE_COMMON_ROMSTAGE),y)
+bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += common/early_serial.c
+romstage-y += common/early_serial.c
+endif
## include generic ite environment controller driver
ramstage-$(CONFIG_SUPERIO_ITE_ENV_CTRL) += common/env_ctrl.c
diff --git a/src/superio/ite/common/Kconfig b/src/superio/ite/common/Kconfig
index 162b7f1..fd6a699 100644
--- a/src/superio/ite/common/Kconfig
+++ b/src/superio/ite/common/Kconfig
@@ -41,4 +41,10 @@
help
The second FAN controller has a separate frequency setting.
+config SUPERIO_ITE_ENV_CTRL_7BIT_SLOPE_REG
+ bool
+ help
+ Slope PWM registers have no separate BIT6 and are set directly by
+ 7-bit values instead.
+
endif
diff --git a/src/superio/ite/common/env_ctrl.c b/src/superio/ite/common/env_ctrl.c
index 1dc5bb6..fb347de 100644
--- a/src/superio/ite/common/env_ctrl.c
+++ b/src/superio/ite/common/env_ctrl.c
@@ -3,6 +3,7 @@
*
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
* Copyright (C) 2016 secunet Security Networks AG
+ * Copyright (C) 2018 Libretrend LDA
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -164,9 +165,14 @@
pwm_ctrl |= ITE_EC_FAN_CTL_TEMPIN(conf->tmpin);
pwm_start = ITE_EC_FAN_CTL_PWM_START_DUTY(conf->pwm_start);
- pwm_start |= ITE_EC_FAN_CTL_PWM_SLOPE_BIT6(conf->slope);
- pwm_auto = ITE_EC_FAN_CTL_PWM_SLOPE_LOWER(conf->slope);
+ if (IS_ENABLED(CONFIG_SUPERIO_ITE_ENV_CTRL_7BIT_SLOPE_REG)) {
+ pwm_auto = conf->slope & 0x7f;
+ } else {
+ pwm_start |= ITE_EC_FAN_CTL_PWM_SLOPE_BIT6(conf->slope);
+ pwm_auto = ITE_EC_FAN_CTL_PWM_SLOPE_LOWER(conf->slope);
+ }
+
if (conf->smoothing)
pwm_auto |= ITE_EC_FAN_CTL_AUTO_SMOOTHING_EN;
@@ -213,7 +219,7 @@
ite_ec_write(base, ITE_EC_FAN_CTL_MODE, reg);
}
- if (IS_ENABLED(SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG)
+ if (IS_ENABLED(CONFIG_SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG)
&& conf->mode >= FAN_MODE_ON) {
reg = ite_ec_read(base, ITE_EC_FAN_TAC_COUNTER_ENABLE);
reg |= ITE_EC_FAN_TAC_16BIT_ENABLE(fan);
@@ -271,6 +277,13 @@
for (i = 0; i < ITE_EC_TMPIN_CNT; ++i)
enable_tmpin(base, i + 1, &conf->tmpin[i]);
+ /* Enable External Sensor SMBus Host if configured */
+ if (conf->smbus_en) {
+ ite_ec_write(base, ITE_EC_INTERFACE_SELECT,
+ ite_ec_read(base, ITE_EC_INTERFACE_SELECT) |
+ ITE_EC_INTERFACE_SMB_ENABLE);
+ }
+
/* Enable reading of voltage pins */
ite_ec_write(base, ITE_EC_ADC_VOLTAGE_CHANNEL_ENABLE, conf->vin_mask);
diff --git a/src/superio/ite/common/env_ctrl.h b/src/superio/ite/common/env_ctrl.h
index 11316db..06a41a5 100644
--- a/src/superio/ite/common/env_ctrl.h
+++ b/src/superio/ite/common/env_ctrl.h
@@ -3,6 +3,7 @@
*
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
* Copyright (C) 2016 secunet Security Networks AG
+ * Copyright (C) 2018 Libretrend LDA
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -48,13 +49,34 @@
#define ITE_EC_FAN_PWM_SMOOTHING_1KHZ (0 << 6)
#define ITE_EC_FAN_PWM_SMOOTHING_256HZ (1 << 6)
#define ITE_EC_FAN_PWM_SMOOTHING_64HZ (2 << 6)
+#if IS_ENABLED(CONFIG_SUPERIO_ITE_IT8786E)
+#define ITE_EC_FAN_PWM_SMOOTHING_16HZ (1 << 6)
+#else
#define ITE_EC_FAN_PWM_SMOOTHING_16HZ (3 << 6)
+#endif
+/* SUPERIO_ITE_IT8786E PWM_SMOOTHING_FREQ contents */
+#define ITE_EC_FAN_PWM_SMOOTHING_1HZ (0 << 6)
+#define ITE_EC_FAN_PWM_SMOOTHING_8HZ (2 << 6)
+#define ITE_EC_FAN_PWM_SMOOTHING_4HZ (3 << 6)
+#define ITE_EC_FAN_CTL5_SEL(x) ((((x)-1) & 3) << 2)
+#define ITE_EC_FAN_CTL5_SEL_NONE (3 << 2)
+#define ITE_EC_FAN_CTL4_SEL(x) (((x)-1) & 3)
+#define ITE_EC_FAN_CTL4_SEL_NONE (3 << 0)
#define ITE_EC_FAN_TAC_COUNTER_ENABLE 0x0c
#define ITE_EC_FAN_TAC_16BIT_ENABLE(x) (1 << ((x)-1))
#define ITE_EC_FAN_TAC_LIMIT(x) (0x10 + ((x)-1))
#define ITE_EC_FAN_TAC_EXT_LIMIT(x) (0x1b + ((x)-1))
+/* SUPERIO_ITE_IT8786E FAN_TAC_CNTRL register content */
+#define ITE_EC_FAN_TAC_CNTRL 0x0c
+#define ITE_EC_TMPIN3_ENHANCED_INT_MODE (1 << 7)
+#define ITE_EC_TMPIN2_ENHANCED_INT_MODE (1 << 6)
+#define ITE_EC_FAN_TAC5_EN (1 << 5)
+#define ITE_EC_FAN_TAC4_EN (1 << 4)
+#define ITE_EC_TMPIN1_ENHANCED_INT_MODE (1 << 3)
+#define ITE_EC_AMDTSI_ERR_EN (1 << 0)
+
#define ITE_EC_FAN_MAIN_CTL 0x13
#define ITE_EC_FAN_MAIN_CTL_TAC_EN(x) (1 << ((x)+3))
#define ITE_EC_FAN_MAIN_CTL_COLL_FULL_SPEED (1 << 3)
@@ -130,6 +152,8 @@
#define ITE_EC_FAN_CTL_PWM_SLOPE_LOWER(s) ((s) & 0x3f)
#define ITE_EC_FAN_CTL_DELTA_TEMP(x) (0x65 + ((x)-1) * 8)
#define ITE_EC_FAN_CTL_DELTA_TEMP_INTRVL(c) ((c) & 0x1f)
+#define ITE_EC_FAN_CTL_TARGET_ZONE(x) (0x66 + ((x)-1) * 8)
+#define ITE_EC_FAN_CTL_TARGET_ZONE_MASK 0x0f
#define ITE_EC_EXTEMP_STATUS 0x88
#define ITE_EC_EXTEMP_STATUS_HOST_BUSY (1 << 0)
diff --git a/src/superio/ite/common/env_ctrl_chip.h b/src/superio/ite/common/env_ctrl_chip.h
index f8f2e1e..4df9b01 100644
--- a/src/superio/ite/common/env_ctrl_chip.h
+++ b/src/superio/ite/common/env_ctrl_chip.h
@@ -3,6 +3,7 @@
*
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
* Copyright (C) 2016 secunet Security Networks AG
+ * Copyright (C) 2018 Libretrend LDA
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -95,6 +96,7 @@
bool tmpin_beep;
bool fan_beep;
bool vin_beep;
+ bool smbus_en;
};
/* Some shorthands for device trees */
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I68fbfe62dfa05d0c166abaefbdc2ab873114b236
Gerrit-Change-Number: 30553
Gerrit-PatchSet: 1
Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Gerrit-MessageType: newchange
2 weeks, 5 days
Change in ...coreboot[master]: mb/google/hatch: Make WP_RO range align with winbond specification
by Subrata Banik (Code Review)
Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30552
Change subject: mb/google/hatch: Make WP_RO range align with winbond specification
......................................................................
mb/google/hatch: Make WP_RO range align with winbond specification
This patch ensures to make memory protected range between
0x800000 - 0xFFFFFF as per winbond spi datasheet
https://www.winbond.com/resource-files/w25q128fv_revhh1_100913_website1.pdf
Change-Id: I52d8dbba14bd060b48a7fe8ee009219413ef89ca
Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
---
M src/mainboard/google/hatch/chromeos.fmd
1 file changed, 4 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/30552/1
diff --git a/src/mainboard/google/hatch/chromeos.fmd b/src/mainboard/google/hatch/chromeos.fmd
index 53ba338..5a2aeec 100644
--- a/src/mainboard/google/hatch/chromeos.fmd
+++ b/src/mainboard/google/hatch/chromeos.fmd
@@ -27,15 +27,15 @@
RW_VPD@0x28000 0x2000
RW_NVRAM@0x2a000 0x6000
}
- RW_LEGACY(CBFS)@0x5d0000 0x200000
- WP_RO@0x7d0000 0x430000 {
+ RW_LEGACY(CBFS)@0x5d0000 0x230000
+ WP_RO@0x800000 0x400000 {
RO_VPD@0x0 0x4000
- RO_SECTION@0x4000 0x42c000 {
+ RO_SECTION@0x4000 0x3fc000 {
FMAP@0x0 0x800
RO_FRID@0x800 0x40
RO_FRID_PAD@0x840 0x7c0
GBB@0x1000 0xef000
- COREBOOT(CBFS)@0xf0000 0x33c000
+ COREBOOT(CBFS)@0xf0000 0x30c000
}
}
}
--
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Gerrit-Branch: master
Gerrit-Change-Id: I52d8dbba14bd060b48a7fe8ee009219413ef89ca
Gerrit-Change-Number: 30552
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>
Gerrit-MessageType: newchange
2 weeks, 5 days