coreboot-gerrit August 2020

coreboot-gerrit@coreboot.org

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1862 discussions

Change in coreboot[master]: nb/intel/sandybridge: Cache cbmem and stage cache in romstage

by Arthur Heymans (Code Review)

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37200 ) Change subject: nb/intel/sandybridge: Cache cbmem and stage cache in romstage ...................................................................... nb/intel/sandybridge: Cache cbmem and stage cache in romstage The compress postcar option will default to 'y' with this. Change-Id: I00de8bc42c5bfbe75cb1fdfd04d5e7ffc74b56e9 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/sandybridge/Kconfig M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_mrc.c 3 files changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/37200/1 diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 0502b50..1745b98 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -20,6 +20,7 @@ select CPU_INTEL_MODEL_206AX select HAVE_DEBUG_RAM_SETUP select INTEL_GMA_ACPI + select ROMSTAGE_CACHED_CBMEM if NORTHBRIDGE_INTEL_SANDYBRIDGE diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index c13ae37..441844e 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -19,6 +19,7 @@ #include <commonlib/region.h> #include <bootmode.h> #include <cf9_reset.h> +#include <cpu/x86/mtrr.h> #include <string.h> #include <arch/cpu.h> #include <device/mmio.h> @@ -422,6 +423,7 @@ report_memory_config(); + setup_romstage_wb_cbmem_cache(); cbmem_was_inited = !cbmem_recovery(s3resume); if (!fast_boot) save_timings(&ctrl); diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 29c766a..9e70fc1 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -17,6 +17,7 @@ #include <console/usb.h> #include <bootmode.h> #include <cf9_reset.h> +#include <cpu/x86/mtrr.h> #include <string.h> #include <device/device.h> #include <device/pci_ops.h> @@ -451,6 +452,7 @@ hexdump32(BIOS_ERR, mrc_var, sizeof(*mrc_var)/sizeof(u32)); } + setup_romstage_wb_cbmem_cache(); cbmem_was_initted = !cbmem_recovery(s3resume); if (!s3resume) save_mrc_data(&pei_data); -- To view, visit https://review.coreboot.org/c/coreboot/+/37200 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00de8bc42c5bfbe75cb1fdfd04d5e7ffc74b56e9 Gerrit-Change-Number: 37200 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

46 minutes

Change in coreboot[master]: nb/intel/nehalem: Cache cbmem and stage cache in romstage

by Arthur Heymans (Code Review)

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37201 ) Change subject: nb/intel/nehalem: Cache cbmem and stage cache in romstage ...................................................................... nb/intel/nehalem: Cache cbmem and stage cache in romstage The compress postcar option will default to 'y' with this. Change-Id: I8b495decc4d283e7f91a0cbdab3484165d0cadf6 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/nehalem/Kconfig M src/northbridge/intel/nehalem/raminit.c 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/37201/1 diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig index 7b56841..bbea9e7 100644 --- a/src/northbridge/intel/nehalem/Kconfig +++ b/src/northbridge/intel/nehalem/Kconfig @@ -22,6 +22,7 @@ select CACHE_MRC_SETTINGS select HAVE_DEBUG_RAM_SETUP select C_ENVIRONMENT_BOOTBLOCK + select ROMSTAGE_CACHED_CBMEM if NORTHBRIDGE_INTEL_NEHALEM diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index fe5d5c9..0fb9b8d 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -4756,6 +4756,7 @@ udelay(1000); dump_timings(&info); + setup_romstage_wb_cbmem_cache(); cbmem_wasnot_inited = cbmem_recovery(s3resume); if (!s3resume) -- To view, visit https://review.coreboot.org/c/coreboot/+/37201 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b495decc4d283e7f91a0cbdab3484165d0cadf6 Gerrit-Change-Number: 37201 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

20 hours, 33 minutes

Change in coreboot[master]: [TESTONLY]nb/intel/x4x: Cache cbmem in romstage

by Arthur Heymans (Code Review)

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37213 ) Change subject: [TESTONLY]nb/intel/x4x: Cache cbmem in romstage ...................................................................... [TESTONLY]nb/intel/x4x: Cache cbmem in romstage Probably not a good idea to avoid eviction in romstage. TESTED: works fine on P5QL-EM. Change-Id: Ib8622f4501f6df005baad003f41f4be3d239f2c6 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/x4x/Kconfig M src/northbridge/intel/x4x/raminit.c 2 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/37213/1 diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig index 2a54e24..6665eb0 100644 --- a/src/northbridge/intel/x4x/Kconfig +++ b/src/northbridge/intel/x4x/Kconfig @@ -27,6 +27,7 @@ select CACHE_MRC_SETTINGS select PARALLEL_MP select C_ENVIRONMENT_BOOTBLOCK + select ROMSTAGE_CACHED_CBMEM config CBFS_SIZE hex diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index 8013af9..e8729fb 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -33,6 +33,7 @@ #include <mrc_cache.h> #include <timestamp.h> #include <types.h> +#include <cpu/x86/mtrr.h> #include "iomap.h" #include "x4x.h" @@ -718,6 +719,7 @@ pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, reg8 | 1); printk(BIOS_DEBUG, "RAM initialization finished.\n"); + setup_romstage_wb_cbmem_cache(); cbmem_was_inited = !cbmem_recovery(s.boot_path == BOOT_PATH_RESUME); if (!fast_boot) mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, -- To view, visit https://review.coreboot.org/c/coreboot/+/37213 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8622f4501f6df005baad003f41f4be3d239f2c6 Gerrit-Change-Number: 37213 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

20 hours, 33 minutes

Change in coreboot[master]: mb/clevo/kbl-u: Install Intel VGA INT15 handler

by Paul Menzel (Code Review)

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43852 ) Change subject: mb/clevo/kbl-u: Install Intel VGA INT15 handler ...................................................................... mb/clevo/kbl-u: Install Intel VGA INT15 handler Timestamp - Option ROM initialization: 77806110188 FMAP: area COREBOOT found @ 350200 (4914688 bytes) CBFS: Locating 'pci8086,5916.rom' CBFS: Found @ offset 11ce00 size 10000 In CBFS, ROM address for PCI: 00:02.0 = 0xffc6d048 PCI ROM image, vendor ID 8086, device ID 0406, ID mismatch: vendor ID 8086, device ID 5916 Copying VGA ROM Image from 0xffc6d048 to 0xc0000, 0x10000 bytes Timestamp - Option ROM copy done: 77877204844 Calling Option ROM... Unsupported software interrupt #0x15 eax 0x1905f34 Unsupported software interrupt #0x15 eax 0x5f51 Unsupported software interrupt #0x15 eax 0x5f40 Unsupported software interrupt #0x15 eax 0x5f52 Unsupported software interrupt #0x15 eax 0x5f49 Unsupported software interrupt #0x15 eax 0x3a95f49 Unsupported software interrupt #0x15 eax 0x5f14 Unsupported software interrupt #0x15 eax 0x405f35 ... Option ROM returned. VGA Option ROM was run Timestamp - Option ROM run done: 78406420234 PCI: 00:02.0 init finished in 210 msecs Change-Id: I126481c745ae701dc438ac664be0f8ff5f6250c1 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- A src/mainboard/clevo/kbl-u/mainboard.c 1 file changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/43852/1 diff --git a/src/mainboard/clevo/kbl-u/mainboard.c b/src/mainboard/clevo/kbl-u/mainboard.c new file mode 100644 index 0000000..01cfef4 --- /dev/null +++ b/src/mainboard/clevo/kbl-u/mainboard.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> + +static void mainboard_enable(struct device *dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, + GMA_INT15_PANEL_FIT_CENTERING, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/43852 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I126481c745ae701dc438ac664be0f8ff5f6250c1 Gerrit-Change-Number: 43852 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

21 hours, 3 minutes

Change in coreboot[master]: soc/mediatek/mt8192: Do dramc analog init setting

by CK HU (Code Review)

Hello Duan huayang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44727 to review the following change. Change subject: soc/mediatek/mt8192: Do dramc analog init setting ...................................................................... soc/mediatek/mt8192: Do dramc analog init setting Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> Change-Id: I53b30a2bbed5acb363f85f7cbc7f255fdbc52304 --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/dramc_ana_init_config.c M src/soc/mediatek/mt8192/dramc_pi_basic_api.c A src/soc/mediatek/mt8192/dramc_subsys_config.c M src/soc/mediatek/mt8192/emi.c 5 files changed, 1,411 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/44727/1 diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index bfa3316..e3463cd 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -17,6 +17,7 @@ romstage-y += ../common/cbmem.c romstage-y += dramc_pi_main.c dramc_pi_basic_api.c dramc_pi_calibration_api.c dramc_utility.c dramc_dvfs.c dramc_tracking.c +romstage-y += dramc_subsys_config.c dramc_ana_init_config.c romstage-y += emi.c romstage-y += flash_controller.c romstage-y += ../common/gpio.c gpio.c diff --git a/src/soc/mediatek/mt8192/dramc_ana_init_config.c b/src/soc/mediatek/mt8192/dramc_ana_init_config.c new file mode 100644 index 0000000..0fd3a9a --- /dev/null +++ b/src/soc/mediatek/mt8192/dramc_ana_init_config.c @@ -0,0 +1,1242 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/dramc_pi_api.h> +#include <soc/dramc_register.h> + +static void suspend_on(void) +{ + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_lp_ctrl0, + B0_LP_CTRL0_RG_ARDMSUS_10_B0, 0); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_lp_ctrl0, + B1_LP_CTRL0_RG_ARDMSUS_10_B1, 0); + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.ca_lp_ctrl0, + CA_LP_CTRL0_RG_ARDMSUS_10_CA, 0); + dramc_set_broadcast(DRAMC_BROADCAST_ON); +} + +void resetb_pull_dn(void) +{ + SET32_BITFIELDS(&ch[0].phy_ao.ca_cmd11, + CA_CMD11_RG_RRESETB_DRVP, 1, + CA_CMD11_RG_RRESETB_DRVN, 1, + CA_CMD11_RG_TX_RRESETB_DDR3_SEL, 1, + CA_CMD11_RG_TX_RRESETB_PULL_DN, 1); + SET32_BITFIELDS(&ch[0].phy_ao.misc_ctrl1, + MISC_CTRL1_R_DMRRESETB_I_OPT, 1); + SET32_BITFIELDS(&ch[0].phy_ao.misc_ctrl1, + MISC_CTRL1_R_DMDA_RRESETB_E, 1); + SET32_BITFIELDS(&ch[0].phy_ao.ca_cmd11, + CA_CMD11_RG_TX_RRESETB_PULL_DN, 0); +} + +static void spm_control(ana_top_config *a_cfg) +{ + u8 new_8x_mode = a_cfg->new_8x_mode; + + SET32_BITFIELDS(&ch[0].phy_ao.misc_lp_ctrl, + MISC_LP_CTRL_RG_ARDMSUS_10_LP_SEL, 1, + MISC_LP_CTRL_RG_RIMP_DMSUS_10_LP_SEL, 1, + MISC_LP_CTRL_RG_RRESETB_LP_SEL, 1, + MISC_LP_CTRL_RG_RPHYPLL_RESETB_LP_SEL, 1, + MISC_LP_CTRL_RG_RPHYPLL_EN_LP_SEL, 1, + MISC_LP_CTRL_RG_RCLRPLL_EN_LP_SEL, 1, + MISC_LP_CTRL_RG_RPHYPLL_ADA_MCK8X_EN_LP_SEL, 1, + MISC_LP_CTRL_RG_RPHYPLL_AD_MCK8X_EN_LP_SEL, 1, + MISC_LP_CTRL_RG_RPHYPLL_TOP_REV_0_LP_SEL, 1, + MISC_LP_CTRL_RG_SC_ARPI_RESETB_8X_SEQ_LP_SEL, new_8x_mode, + MISC_LP_CTRL_RG_ADA_MCK8X_8X_SEQ_LP_SEL, new_8x_mode, + MISC_LP_CTRL_RG_AD_MCK8X_8X_SEQ_LP_SEL, new_8x_mode, + MISC_LP_CTRL_RG_MIDPI_EN_8X_SEQ_LP_SEL, new_8x_mode, + MISC_LP_CTRL_RG_MIDPI_CKDIV4_EN_8X_SEQ_LP_SEL, new_8x_mode, + MISC_LP_CTRL_RG_MCK8X_CG_SRC_LP_SEL, new_8x_mode, + MISC_LP_CTRL_RG_MCK8X_CG_SRC_AND_LP_SEL, new_8x_mode); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_lp_ctrl0, + B0_LP_CTRL0_RG_ARDMSUS_10_B0_LP_SEL, 1, + B0_LP_CTRL0_RG_ARDQ_RESETB_B0_LP_SEL, 1, + B0_LP_CTRL0_RG_ARPI_RESETB_B0_LP_SEL, 1, + B0_LP_CTRL0_RG_B0_MS_SLV_LP_SEL, 0, + B0_LP_CTRL0_RG_ARDLL_PHDET_EN_B0_LP_SEL, 1, + B0_LP_CTRL0_RG_RX_ARDQ_BIAS_EN_B0_LP_SEL, 0, + B0_LP_CTRL0_DA_ARPI_CG_MCK_B0_LP_SEL, 1, + B0_LP_CTRL0_DA_ARPI_CG_MCK_FB2DLL_B0_LP_SEL, 1, + B0_LP_CTRL0_DA_ARPI_CG_MCTL_B0_LP_SEL, 1, + B0_LP_CTRL0_DA_ARPI_CG_FB_B0_LP_SEL, 1, + B0_LP_CTRL0_DA_ARPI_CG_DQ_B0_LP_SEL, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_lp_ctrl0, + B0_LP_CTRL0_DA_ARPI_CG_DQM_B0_LP_SEL, 1, + B0_LP_CTRL0_DA_ARPI_CG_DQS_B0_LP_SEL, 1, + B0_LP_CTRL0_DA_ARPI_CG_DQSIEN_B0_LP_SEL, 1, + B0_LP_CTRL0_DA_ARPI_MPDIV_CG_B0_LP_SEL, 1, + B0_LP_CTRL0_RG_RX_ARDQ_VREF_EN_B0_LP_SEL, 1, + B0_LP_CTRL0_DA_ARPI_MIDPI_EN_B0_LP_SEL, 1, + B0_LP_CTRL0_DA_ARPI_MIDPI_CKDIV4_EN_B0_LP_SEL, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_lp_ctrl0, + B1_LP_CTRL0_RG_ARDMSUS_10_B1_LP_SEL, 1, + B1_LP_CTRL0_RG_ARDQ_RESETB_B1_LP_SEL, 1, + B1_LP_CTRL0_RG_ARPI_RESETB_B1_LP_SEL, 1, + B1_LP_CTRL0_RG_B1_MS_SLV_LP_SEL, 0, + B1_LP_CTRL0_RG_ARDLL_PHDET_EN_B1_LP_SEL, 1, + B1_LP_CTRL0_RG_RX_ARDQ_BIAS_EN_B1_LP_SEL, 0, + B1_LP_CTRL0_DA_ARPI_CG_MCK_B1_LP_SEL, 1, + B1_LP_CTRL0_DA_ARPI_CG_MCK_FB2DLL_B1_LP_SEL, 1, + B1_LP_CTRL0_DA_ARPI_CG_MCTL_B1_LP_SEL, 1, + B1_LP_CTRL0_DA_ARPI_CG_FB_B1_LP_SEL, 1, + B1_LP_CTRL0_DA_ARPI_CG_DQ_B1_LP_SEL, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_lp_ctrl0, + B1_LP_CTRL0_DA_ARPI_CG_DQM_B1_LP_SEL, 1, + B1_LP_CTRL0_DA_ARPI_CG_DQS_B1_LP_SEL, 1, + B1_LP_CTRL0_DA_ARPI_CG_DQSIEN_B1_LP_SEL, 1, + B1_LP_CTRL0_DA_ARPI_MPDIV_CG_B1_LP_SEL, 1, + B1_LP_CTRL0_RG_RX_ARDQ_VREF_EN_B1_LP_SEL, 1, + B1_LP_CTRL0_DA_ARPI_MIDPI_EN_B1_LP_SEL, 1, + B1_LP_CTRL0_DA_ARPI_MIDPI_CKDIV4_EN_B1_LP_SEL, 1); + + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.ca_lp_ctrl0, + CA_LP_CTRL0_RG_ARDMSUS_10_CA_LP_SEL, 1, + CA_LP_CTRL0_RG_ARCMD_RESETB_LP_SEL, 1, + CA_LP_CTRL0_RG_ARPI_RESETB_CA_LP_SEL, 1, + CA_LP_CTRL0_RG_ARDLL_PHDET_EN_CA_LP_SEL, 1, + CA_LP_CTRL0_RG_TX_ARCS_PULL_UP_LP_SEL, 1, + CA_LP_CTRL0_RG_TX_ARCS_PULL_DN_LP_SEL, 1, + CA_LP_CTRL0_RG_TX_ARCA_PULL_UP_LP_SEL, 1, + CA_LP_CTRL0_RG_TX_ARCA_PULL_DN_LP_SEL, 1, + CA_LP_CTRL0_DA_ARPI_CG_MCK_CA_LP_SEL, 1, + CA_LP_CTRL0_DA_ARPI_CG_MCK_FB2DLL_CA_LP_SEL, 1, + CA_LP_CTRL0_DA_ARPI_CG_MCTL_CA_LP_SEL, 1, + CA_LP_CTRL0_DA_ARPI_CG_FB_CA_LP_SEL, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.ca_lp_ctrl0, + CA_LP_CTRL0_DA_ARPI_CG_CS_LP_SEL, 1, + CA_LP_CTRL0_DA_ARPI_CG_CLK_LP_SEL, 1, + CA_LP_CTRL0_DA_ARPI_CG_CMD_LP_SEL, 1, + CA_LP_CTRL0_DA_ARPI_CG_CLKIEN_LP_SEL, 1, + CA_LP_CTRL0_DA_ARPI_MPDIV_CG_CA_LP_SEL, 1, + CA_LP_CTRL0_RG_RX_ARCMD_VREF_EN_LP_SEL, 1, + CA_LP_CTRL0_DA_ARPI_MIDPI_EN_CA_LP_SEL, 1, + CA_LP_CTRL0_DA_ARPI_MIDPI_CKDIV4_EN_CA_LP_SEL, 1, + CA_LP_CTRL0_RG_RX_ARCMD_BIAS_EN_LP_SEL, 0); + } + + if (a_cfg->dll_async_en == 1) { + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.ca_lp_ctrl0, + CA_LP_CTRL0_RG_CA_MS_SLV_LP_SEL, a_cfg->all_slave_en==0); + } else { + SET32_BITFIELDS(&ch[0].phy_ao.ca_lp_ctrl0, + CA_LP_CTRL0_RG_CA_MS_SLV_LP_SEL, a_cfg->all_slave_en==0); + SET32_BITFIELDS(&ch[1].phy_ao.ca_lp_ctrl0, + CA_LP_CTRL0_RG_CA_MS_SLV_LP_SEL, 0); + } + dramc_set_broadcast(DRAMC_BROADCAST_ON); + + SET32_BITFIELDS(&ch[0].phy_ao.misc_cg_ctrl9, + MISC_CG_CTRL9_RG_M_CK_OPENLOOP_MODE_EN, 1, + MISC_CG_CTRL9_RG_MCK4X_I_OPENLOOP_MODE_EN, 1, + MISC_CG_CTRL9_RG_CG_DDR400_MCK4X_I_OFF, 1, + MISC_CG_CTRL9_RG_DDR400_MCK4X_I_FORCE_ON, 0, + MISC_CG_CTRL9_RG_MCK4X_I_FB_CK_CG_OFF, 1, + MISC_CG_CTRL9_RG_MCK4X_Q_OPENLOOP_MODE_EN, 1, + MISC_CG_CTRL9_RG_CG_DDR400_MCK4X_Q_OFF, 1, + MISC_CG_CTRL9_RG_DDR400_MCK4X_Q_FORCE_ON, 0, + MISC_CG_CTRL9_RG_MCK4X_Q_FB_CK_CG_OFF, 1); +} + +static void ana_tx_nonshuffle_config(ana_top_config *a_cfg) +{ + SET32_BITFIELDS(&ch[0].phy_ao.ca_cmd6, + CA_CMD6_RG_TX_ARCMD_DDR3_SEL, 0, + CA_CMD6_RG_TX_ARCMD_DDR4_SEL, 0, + CA_CMD6_RG_TX_ARCMD_LP4_SEL, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq6, + B0_DQ6_RG_TX_ARDQ_DDR3_SEL_B0, 0, + B0_DQ6_RG_TX_ARDQ_DDR4_SEL_B0, !(a_cfg->aphy_comb_en), + B0_DQ6_RG_TX_ARDQ_LP4_SEL_B0, a_cfg->aphy_comb_en); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq6, + B1_DQ6_RG_TX_ARDQ_DDR3_SEL_B1, 0, + B1_DQ6_RG_TX_ARDQ_DDR4_SEL_B1, !(a_cfg->aphy_comb_en), + B1_DQ6_RG_TX_ARDQ_LP4_SEL_B1, a_cfg->aphy_comb_en); + dramc_dbg("[CONFIGURE PHASE]: ANA_TX\n"); + SET32_BITFIELDS(&ch[0].phy_ao.ca_cmd2, + CA_CMD2_RG_TX_ARCMD_OE_DIS_CA, 1, + CA_CMD2_RG_TX_ARCMD_ODTEN_DIS_CA, 0, + CA_CMD2_RG_TX_ARCLK_OE_DIS_CA, 0, + CA_CMD2_RG_TX_ARCLK_ODTEN_DIS_CA, 0, + CA_CMD2_RG_TX_ARCS_OE_TIE_SEL_CA, 1, + CA_CMD2_RG_TX_ARCS_OE_TIE_EN_CA, 1, + CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA, 0, + CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA, 0xff); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq2, + B0_DQ2_RG_TX_ARDQ_OE_DIS_B0, 0, + B0_DQ2_RG_TX_ARDQ_ODTEN_DIS_B0, 0, + B0_DQ2_RG_TX_ARDQM0_OE_DIS_B0, 0, + B0_DQ2_RG_TX_ARDQM0_ODTEN_DIS_B0, 0, + B0_DQ2_RG_TX_ARDQS0_OE_DIS_B0, 0, + B0_DQ2_RG_TX_ARDQS0_ODTEN_DIS_B0, 0); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq2, + B1_DQ2_RG_TX_ARDQ_OE_DIS_B1, 0, + B1_DQ2_RG_TX_ARDQ_ODTEN_DIS_B1, 0, + B1_DQ2_RG_TX_ARDQM0_OE_DIS_B1, 0, + B1_DQ2_RG_TX_ARDQM0_ODTEN_DIS_B1, 0, + B1_DQ2_RG_TX_ARDQS0_OE_DIS_B1, 0, + B1_DQ2_RG_TX_ARDQS0_ODTEN_DIS_B1, 0); + SET32_BITFIELDS(&ch[0].phy_ao.ca_cmd3, + CA_CMD3_RG_TX_ARCMD_EN, 1, + CA_CMD3_RG_ARCMD_RESETB, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq3, + B0_DQ3_RG_ARDQ_RESETB_B0, 1, + B0_DQ3_RG_TX_ARDQ_EN_B0, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq3, + B1_DQ3_RG_ARDQ_RESETB_B1, 1, + B1_DQ3_RG_TX_ARDQ_EN_B1, 1); +} + +static void ana_rx_nonshuffle_config(void) +{ + SET32_BITFIELDS(&ch[0].phy_ao.ca_cmd6, + CA_CMD6_RG_RX_ARCMD_DDR3_SEL, 0, + CA_CMD6_RG_RX_ARCMD_DDR4_SEL, 0, + CA_CMD6_RG_RX_ARCMD_BIAS_VREF_SEL, 0, + CA_CMD6_RG_RX_ARCMD_RES_BIAS_EN, 0); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq5, + B0_DQ5_RG_RX_ARDQ_VREF_EN_B0, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq6, + B0_DQ6_RG_RX_ARDQ_DDR3_SEL_B0, 0, + B0_DQ6_RG_RX_ARDQ_DDR4_SEL_B0, 1, + B0_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B0, 0, + B0_DQ6_RG_RX_ARDQ_BIAS_EN_B0, 1, + B0_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B0, 0, + B0_DQ6_RG_RX_ARDQ_RES_BIAS_EN_B0, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq3, + B0_DQ3_RG_RX_ARDQ_STBENCMP_EN_B0, 1, + B0_DQ3_RG_RX_ARDQ_SMT_EN_B0, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq5, + B1_DQ5_RG_RX_ARDQ_VREF_EN_B1, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq6, + B1_DQ6_RG_RX_ARDQ_DDR3_SEL_B1, 0, + B1_DQ6_RG_RX_ARDQ_DDR4_SEL_B1, 1, + B1_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B1, 0, + B1_DQ6_RG_RX_ARDQ_BIAS_EN_B1, 1, + B1_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B1, 0, + B1_DQ6_RG_RX_ARDQ_RES_BIAS_EN_B1, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq3, + B1_DQ3_RG_RX_ARDQ_STBENCMP_EN_B1, 1, + B1_DQ3_RG_RX_ARDQ_SMT_EN_B1, 1); + SET32_BITFIELDS(&ch[0].phy_ao.ca_cmd9, + CA_CMD9_RG_RX_ARCMD_STBEN_RESETB, 1, + CA_CMD9_RG_RX_ARCLK_STBEN_RESETB, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq9, + B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0, 1, + B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq9, + B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1, 1, + B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1, 1); + SET32_BITFIELDS(&ch[0].phy_ao.ca_cmd8, + CA_CMD8_RG_RX_ARCLK_SER_RST_MODE, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq8, + B0_DQ8_RG_RX_ARDQS_SER_RST_MODE_B0, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq8, + B1_DQ8_RG_RX_ARDQS_SER_RST_MODE_B1, 1); +} + +static void dig_dcm_nonshuffle_config(void) +{ + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rx_cg_ctrl, + MISC_SHU_RX_CG_CTRL_RX_DCM_EXT_DLY, 3); +} + +static void ana_imp_configure(void) +{ + SET32_BITFIELDS(&ch[0].phy_ao.misc_imp_ctrl1, + MISC_IMP_CTRL1_RG_RIMP_DDR3_SEL, 0); + SET32_BITFIELDS(&ch[0].phy_ao.misc_imp_ctrl1, + MISC_IMP_CTRL1_RG_RIMP_DDR4_SEL, 1); + SET32_BITFIELDS(&ch[0].phy_ao.misc_imp_ctrl1, + MISC_IMP_CTRL1_RG_RIMP_BIAS_EN, 0, + MISC_IMP_CTRL1_RG_RIMP_ODT_EN, 0, + MISC_IMP_CTRL1_RG_RIMP_PRE_EN, 0, + MISC_IMP_CTRL1_RG_RIMP_VREF_EN, 0); +} + +static void ana_dll_non_shuffle_config(dram_freq_grp freq_group, + ana_top_config *a_cfg) +{ + u8 pd_zone = (freq_group >= DDRFREQ_2133) ? 0x2 : 0x3; + + if (a_cfg->dll_idle_mode == 1) { + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + if (a_cfg->dll_async_en == 1) { + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.ca_dll_arpi5, + CA_DLL_ARPI5_RG_ARDLL_IDLE_EN_CA, 0, + CA_DLL_ARPI5_RG_ARDLL_PD_ZONE_CA, pd_zone); + SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[0].b0_dll_arpi5, + B0_DLL_ARPI5_RG_ARDLL_IDLE_EN_B0, 1, + B0_DLL_ARPI5_RG_ARDLL_PD_ZONE_B0, pd_zone); + SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[1].b0_dll_arpi5, + B1_DLL_ARPI5_RG_ARDLL_IDLE_EN_B1, 1, + B1_DLL_ARPI5_RG_ARDLL_PD_ZONE_B1, pd_zone); + } + } else { + SET32_BITFIELDS(&ch[0].phy_ao.ca_dll_arpi5, + CA_DLL_ARPI5_RG_ARDLL_IDLE_EN_CA, 0, + CA_DLL_ARPI5_RG_ARDLL_PD_ZONE_CA, pd_zone); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dll_arpi5, + B0_DLL_ARPI5_RG_ARDLL_IDLE_EN_B0, 1, + B0_DLL_ARPI5_RG_ARDLL_PD_ZONE_B0, pd_zone); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dll_arpi5, + B1_DLL_ARPI5_RG_ARDLL_IDLE_EN_B1, 1, + B1_DLL_ARPI5_RG_ARDLL_PD_ZONE_B1, pd_zone); + SET32_BITFIELDS(&ch[1].phy_ao.ca_dll_arpi5, + CA_DLL_ARPI5_RG_ARDLL_IDLE_EN_CA, 1, + CA_DLL_ARPI5_RG_ARDLL_PD_ZONE_CA, pd_zone); + SET32_BITFIELDS(&ch[1].phy_ao.dvs_b[0].b0_dll_arpi5, + B0_DLL_ARPI5_RG_ARDLL_IDLE_EN_B0, 1, + B0_DLL_ARPI5_RG_ARDLL_PD_ZONE_B0, pd_zone); + SET32_BITFIELDS(&ch[1].phy_ao.dvs_b[1].b0_dll_arpi5, + B1_DLL_ARPI5_RG_ARDLL_IDLE_EN_B1, 1, + B1_DLL_ARPI5_RG_ARDLL_PD_ZONE_B1, pd_zone); + } + dramc_set_broadcast(DRAMC_BROADCAST_ON); + } + + SET32_BITFIELDS(&ch[0].phy_ao.ca_dll_arpi1, + CA_DLL_ARPI1_RG_ARPI_CLKIEN_JUMP_EN, 0, + CA_DLL_ARPI1_RG_ARPI_CMD_JUMP_EN, 0, + CA_DLL_ARPI1_RG_ARPI_CLK_JUMP_EN, 0, + CA_DLL_ARPI1_RG_ARPI_CS_JUMP_EN, 0, + CA_DLL_ARPI1_RG_ARPI_FB_JUMP_EN_CA, 0, + CA_DLL_ARPI1_RG_ARPI_MCTL_JUMP_EN_CA, 0, + CA_DLL_ARPI1_RG_ARPISM_MCK_SEL_CA, 1, + CA_DLL_ARPI1_RG_ARPISM_MCK_SEL_CA_REG_OPT, 0); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dll_arpi1, + B0_DLL_ARPI1_RG_ARPI_DQSIEN_JUMP_EN_B0, 0, + B0_DLL_ARPI1_RG_ARPI_DQ_JUMP_EN_B0, 0, + B0_DLL_ARPI1_RG_ARPI_DQM_JUMP_EN_B0, 0, + B0_DLL_ARPI1_RG_ARPI_DQS_JUMP_EN_B0, 0, + B0_DLL_ARPI1_RG_ARPI_FB_JUMP_EN_B0, 0, + B0_DLL_ARPI1_RG_ARPI_MCTL_JUMP_EN_B0, 0, + B0_DLL_ARPI1_RG_ARPISM_MCK_SEL_B0, 0, + B0_DLL_ARPI1_RG_ARPISM_MCK_SEL_B0_REG_OPT, 0); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dll_arpi1, + B1_DLL_ARPI1_RG_ARPI_DQSIEN_JUMP_EN_B1, 0, + B1_DLL_ARPI1_RG_ARPI_DQ_JUMP_EN_B1, 0, + B1_DLL_ARPI1_RG_ARPI_DQM_JUMP_EN_B1, 0, + B1_DLL_ARPI1_RG_ARPI_DQS_JUMP_EN_B1, 0, + B1_DLL_ARPI1_RG_ARPI_FB_JUMP_EN_B1, 0, + B1_DLL_ARPI1_RG_ARPI_MCTL_JUMP_EN_B1, 0, + B1_DLL_ARPI1_RG_ARPISM_MCK_SEL_B1, 0, + B1_DLL_ARPI1_RG_ARPISM_MCK_SEL_B1_REG_OPT, 0); + + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.ca_dll_arpi5, + CA_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_CA, 0, + CA_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_SEL_CA, 0, + CA_DLL_ARPI5_RG_ARDLL_DIV_DEC_CA, 0, + CA_DLL_ARPI5_RG_ARDLL_MON_SEL_CA, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[0].b0_dll_arpi5, + B0_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_B0, 0, + B0_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_SEL_B0, 0, + B0_DLL_ARPI5_RG_ARDLL_DIV_DEC_B0, 0, + B0_DLL_ARPI5_RG_ARDLL_MON_SEL_B0, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[1].b0_dll_arpi5, + B1_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_B1, 0, + B1_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_SEL_B1, 0, + B1_DLL_ARPI5_RG_ARDLL_DIV_DEC_B1, 0, + B1_DLL_ARPI5_RG_ARDLL_MON_SEL_B1, 0); + } + dramc_set_broadcast(DRAMC_BROADCAST_ON); +} + +static void ana_pll_shuffle_Config(ana_dvfs_core *dvfs_core) +{ + u8 prediv = 1; + u8 posdiv = 0; + u8 fbk_sel = 0; + u8 div16_ck_sel = 0; + u32 pcw; + u32 pll_freq = dvfs_core->pll_freq; + u32 xtal_freq = 26; + + if (dvfs_core->dq_ca_open == 1) + div16_ck_sel = 1; + else + fbk_sel = (pll_freq > 3800) ? 1 : 0; + + pcw = (pll_freq/xtal_freq) << (8 + 1 -fbk_sel-prediv - posdiv); + dramc_dbg("pll_freq:%d, fbk_sel:%d, pcw = %#x\n", pll_freq, fbk_sel, pcw); + + SET32_BITFIELDS(&ch[0].phy_ao.phypll1, + PHYPLL1_RG_RPHYPLL_TST_EN, 0, + PHYPLL1_RG_RPHYPLL_TSTOP_EN, 0); + SET32_BITFIELDS(&ch[0].phy_ao.shu_phypll0, + SHU_PHYPLL0_RG_RPHYPLL_RESERVED, 0, + SHU_PHYPLL0_RG_RPHYPLL_ICHP, 0); + SET32_BITFIELDS(&ch[0].phy_ao.shu_clrpll0, + SHU_CLRPLL0_RG_RCLRPLL_RESERVED, 0, + SHU_CLRPLL0_RG_RCLRPLL_ICHP, 0); + SET32_BITFIELDS(&ch[0].phy_ao.shu_phypll2, + SHU_PHYPLL2_RG_RPHYPLL_PREDIV, prediv, + SHU_PHYPLL2_RG_RPHYPLL_POSDIV, posdiv); + SET32_BITFIELDS(&ch[0].phy_ao.shu_clrpll2, + SHU_CLRPLL2_RG_RCLRPLL_PREDIV, prediv, + SHU_CLRPLL2_RG_RCLRPLL_POSDIV, posdiv); + SET32_BITFIELDS(&ch[0].phy_ao.shu_phypll1, + SHU_PHYPLL1_RG_RPHYPLL_SDM_PCW, pcw, + SHU_PHYPLL1_RG_RPHYPLL_SDM_PCW_CHG, 1, + SHU_PHYPLL1_RG_RPHYPLL_SDM_FRA_EN, 0); + SET32_BITFIELDS(&ch[0].phy_ao.shu_clrpll1, + SHU_CLRPLL1_RG_RCLRPLL_SDM_PCW, pcw, + SHU_CLRPLL1_RG_RCLRPLL_SDM_PCW_CHG, 1, + SHU_CLRPLL1_RG_RCLRPLL_SDM_FRA_EN, 0); + SET32_BITFIELDS(&ch[0].phy_ao.shu_pll1, + SHU_PLL1_RG_RPHYPLLGP_CK_SEL, 1, + SHU_PLL1_R_SHU_AUTO_PLL_MUX, 1); + SET32_BITFIELDS(&ch[0].phy_ao.shu_phypll3, + SHU_PHYPLL3_RG_RPHYPLL_LVROD_EN, 0, + SHU_PHYPLL3_RG_RPHYPLL_RST_DLY, 1, + SHU_PHYPLL3_RG_RPHYPLL_FBKSEL, fbk_sel); + SET32_BITFIELDS(&ch[0].phy_ao.shu_clrpll3, + SHU_CLRPLL3_RG_RCLRPLL_LVROD_EN, 0, + SHU_CLRPLL3_RG_RCLRPLL_RST_DLY, 1, + SHU_CLRPLL3_RG_RCLRPLL_FBKSEL, fbk_sel); + if (dvfs_core->dq_ca_open == 1) { + SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_clk_ctrl0, + SHU_MISC_CLK_CTRL0_M_CK_OPENLOOP_MODE_SEL, + dvfs_core->dq_ca_open); + SET32_BITFIELDS(&ch[0].phy_ao.shu_phypll3, + SHU_PHYPLL3_RG_RPHYPLL_MONCK_EN, 1, + SHU_PHYPLL3_RG_RPHYPLL_DIV_CK_SEL, div16_ck_sel); + SET32_BITFIELDS(&ch[0].phy_ao.shu_clrpll3, + SHU_CLRPLL3_RG_RCLRPLL_MONCK_EN, 1, + SHU_CLRPLL3_RG_RCLRPLL_DIV_CK_SEL, div16_ck_sel); + } + dramc_dbg("PLL\n"); +} + +static void ana_arpi_shuffle_config(ana_top_config *a_cfg, ana_dvfs_core *tr) +{ + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_dll_arpi3, + SHU_CA_DLL_ARPI3_RG_ARPI_CLKIEN_EN, 0, + SHU_CA_DLL_ARPI3_RG_ARPI_CMD_EN, !(tr->dq_semi_open), + SHU_CA_DLL_ARPI3_RG_ARPI_CS_EN, !(tr->dq_semi_open)); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dll_arpi3, + SHU_B0_DLL_ARPI3_RG_ARPI_DQSIEN_EN_B0, !(tr->dq_semi_open), + SHU_B0_DLL_ARPI3_RG_ARPI_DQ_EN_B0, !(tr->dq_semi_open), + SHU_B0_DLL_ARPI3_RG_ARPI_DQM_EN_B0, !(tr->dq_semi_open), + SHU_B0_DLL_ARPI3_RG_ARPI_DQS_EN_B0, !(tr->dq_semi_open), + SHU_B0_DLL_ARPI3_RG_ARPI_FB_EN_B0, !(tr->dq_semi_open)); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dll_arpi3, + SHU_B0_DLL_ARPI3_RG_ARPI_MCTL_EN_B0, + (!(tr->dq_semi_open)) && (a_cfg->rank_mode)); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dll_arpi3, + SHU_B1_DLL_ARPI3_RG_ARPI_DQSIEN_EN_B1, !(tr->dq_semi_open), + SHU_B1_DLL_ARPI3_RG_ARPI_DQ_EN_B1, !(tr->dq_semi_open), + SHU_B1_DLL_ARPI3_RG_ARPI_DQM_EN_B1, !(tr->dq_semi_open), + SHU_B1_DLL_ARPI3_RG_ARPI_DQS_EN_B1, !(tr->dq_semi_open), + SHU_B1_DLL_ARPI3_RG_ARPI_FB_EN_B1, !(tr->dq_semi_open)); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dll_arpi3, + SHU_B1_DLL_ARPI3_RG_ARPI_MCTL_EN_B1, + (!(tr->dq_semi_open)) && (a_cfg->rank_mode)); + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd2, + SHU_CA_CMD2_RG_ARPISM_MCK_SEL_CA_SHU, 1, + SHU_CA_CMD2_RG_ARPI_TX_CG_SYNC_DIS_CA, 1, + SHU_CA_CMD2_RG_ARPI_TX_CG_CA_EN_CA, 1, + SHU_CA_CMD2_RG_ARPI_TX_CG_CLK_EN_CA, 1, + SHU_CA_CMD2_RG_ARPI_TX_CG_CS_EN_CA, 1, + SHU_CA_CMD2_RG_ARPI_PD_MCTL_SEL_CA, 0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq2, + SHU_B0_DQ2_RG_ARPISM_MCK_SEL_B0_SHU, 1, + SHU_B0_DQ2_RG_ARPI_TX_CG_SYNC_DIS_B0, 1, + SHU_B0_DQ2_RG_ARPI_TX_CG_DQ_EN_B0, 1, + SHU_B0_DQ2_RG_ARPI_TX_CG_DQS_EN_B0, 1, + SHU_B0_DQ2_RG_ARPI_TX_CG_DQM_EN_B0, 1, + SHU_B0_DQ2_RG_ARPI_PD_MCTL_SEL_B0, 1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq2, + SHU_B1_DQ2_RG_ARPISM_MCK_SEL_B1_SHU, 1, + SHU_B1_DQ2_RG_ARPI_TX_CG_SYNC_DIS_B1, 1, + SHU_B1_DQ2_RG_ARPI_TX_CG_DQ_EN_B1, 1, + SHU_B1_DQ2_RG_ARPI_TX_CG_DQS_EN_B1, 1, + SHU_B1_DQ2_RG_ARPI_TX_CG_DQM_EN_B1, 1, + SHU_B1_DQ2_RG_ARPI_PD_MCTL_SEL_B1, 1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq7, + SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0, 0, + SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0, 0, + SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0, 0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq7, + SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1, 0, + SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1, 0, + SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1, 0); + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd7, + SHU_CA_CMD7_R_DMTX_ARPI_CG_CS_NEW, 0, + SHU_CA_CMD7_R_DMTX_ARPI_CG_CMD_NEW, 0); +} + +static void ana_tx_shuffle_config(ana_top_config *a_cfg) +{ + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd14, + SHU_CA_CMD14_RG_TX_ARCA_OE_ODTEN_CG_EN_CA, 0); + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd13, + SHU_CA_CMD13_RG_TX_ARCLK_OE_ODTEN_CG_EN_CA, 0, + SHU_CA_CMD13_RG_TX_ARCS_OE_ODTEN_CG_EN_CA, 0); + + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq13, + SHU_B0_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B0, 1, + SHU_B0_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B0, 1, + SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_EN_B0, 0, + SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B0, 0, + SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B0, 0, + SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B0, 0, + SHU_B0_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B0, a_cfg->tx_odt_dis); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq13, + SHU_B1_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B1, 1, + SHU_B1_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B1, 1, + SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_EN_B1, 0, + SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B1, 0, + SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B1, 0, + SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B1, 0, + SHU_B1_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B1, a_cfg->tx_odt_dis); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq14, + SHU_B0_DQ14_RG_TX_ARDQ_OE_ODTEN_CG_EN_B0, 1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq14, + SHU_B1_DQ14_RG_TX_ARDQ_OE_ODTEN_CG_EN_B1, 1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq13, + SHU_B0_DQ13_RG_TX_ARDQS_MCKIO_SEL_B0, 0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq13, + SHU_B1_DQ13_RG_TX_ARDQS_MCKIO_SEL_B1, 0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq14, + SHU_B0_DQ14_RG_TX_ARDQ_MCKIO_SEL_B0, 0, + SHU_B0_DQ14_RG_TX_ARWCK_MCKIO_SEL_B0, 0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq14, + SHU_B1_DQ14_RG_TX_ARDQ_MCKIO_SEL_B1, 0, + SHU_B1_DQ14_RG_TX_ARWCK_MCKIO_SEL_B1, 0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq13, + SHU_B0_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B0, 0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq13, + SHU_B1_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B1, 0); + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd13, + SHU_CA_CMD13_RG_TX_ARCA_DLY_LAT_EN_CA, 0); + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd2, + SHU_CA_CMD2_RG_ARPI_OFFSET_LAT_EN_CA, 0, + SHU_CA_CMD2_RG_ARPI_OFFSET_ASYNC_EN_CA, 0); +} + +static void dig_phy_shu_misc_cg_ctrl(void) +{ + setbits32(&ch[0].phy_ao.misc_shu_cg_ctrl0, 0x33400000); +} + +static void ana_clk_div_config_setting(ana_dvfs_core *tr, ana_top_config *a_cfg) +{ + u8 tx_ardq_sermode=0; + u8 tx_arcr_sermode=0; + u8 ardll_sermode_b=0; + u8 ardll_sermode_c=0; + + dramc_dbg("ANA CLOCK DIV configuration\n"); + switch (tr->dq_p2s_ratio) { + case 4 : + tx_ardq_sermode = 1; + break; + case 8 : + tx_ardq_sermode = 2; + break; + case 16: + tx_ardq_sermode = 3; + break; + default: dramc_dbg("ERROR: tr->dq_p2s_ratio= %2d, Not support!!",tr->dq_p2s_ratio); + break; + } + + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq14, + SHU_B0_DQ14_RG_TX_ARDQ_SER_MODE_B0, tx_ardq_sermode); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq14, + SHU_B1_DQ14_RG_TX_ARDQ_SER_MODE_B1, tx_ardq_sermode); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq6, + SHU_B0_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B0, tx_ardq_sermode); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq6, + SHU_B1_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B1, tx_ardq_sermode); + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd11, + SHU_CA_CMD11_RG_RX_ARCA_DES_MODE_CA, (tr->dq_p2s_ratio == 16 ) ? 3 : 2); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq11, + SHU_B0_DQ11_RG_RX_ARDQ_DES_MODE_B0, (tr->dq_p2s_ratio == 16 ) ? 3 : 2); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq11, + SHU_B1_DQ11_RG_RX_ARDQ_DES_MODE_B1, (tr->dq_p2s_ratio == 16 ) ? 3 : 2); + + switch (tr->ca_p2s_ratio) { + case 2 : + tx_arcr_sermode = (0 + tr->ca_full_rate); + break; + case 4 : + tx_arcr_sermode = (1 + tr->ca_full_rate); + break; + case 8: + tx_arcr_sermode = (2 + tr->ca_full_rate); + break; + default: dramc_dbg("ERROR: tr->ca_p2s_ratio= %2d, Not support!!",tr->ca_p2s_ratio); + break; + } + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd14, + SHU_CA_CMD14_RG_TX_ARCA_SER_MODE_CA, tx_arcr_sermode); + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd6, + SHU_CA_CMD6_RG_RX_ARCMD_RANK_SEL_SER_MODE, tx_arcr_sermode); + + switch (tr->dq_aamck_div) { + case 2 : + ardll_sermode_b = 1; + break; + case 4 : + ardll_sermode_b = 2; + break; + case 8: + ardll_sermode_b = 3; + break; + default: dramc_dbg("WARN: tr->dq_aamck_div= %2d, Because of dq_semi_open, It's don't care.",tr->dq_aamck_div); + break; + } + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dll1, + SHU_B0_DLL1_RG_ARDLL_SER_MODE_B0, ardll_sermode_b); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dll1, + SHU_B1_DLL1_RG_ARDLL_SER_MODE_B1, ardll_sermode_b); + + switch (tr->ca_admck_div) { + case 2 : + ardll_sermode_c = 1; + break; + case 4 : + ardll_sermode_c = 2; + break; + case 8: + ardll_sermode_c = 3; + break; + default: dramc_dbg("ERROR: tr->ca_admck_div= %2d, Not support!!",tr->ca_admck_div); + break; + } + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_dll1, + SHU_CA_DLL1_RG_ARDLL_SER_MODE_CA, ardll_sermode_c); + + dramc_set_broadcast(DRAMC_BROADCAST_ON); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq6, + SHU_B0_DQ6_RG_ARPI_SOPEN_EN_B0, tr->dq_semi_open, + SHU_B0_DQ6_RG_ARPI_OPEN_EN_B0, tr->dq_ca_open); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq6, + SHU_B1_DQ6_RG_ARPI_SOPEN_EN_B1, tr->dq_semi_open, + SHU_B1_DQ6_RG_ARPI_OPEN_EN_B1, tr->dq_ca_open); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq1, + SHU_B0_DQ1_RG_ARPI_MIDPI_EN_B0, + !(tr->dq_semi_open) && (!(tr->dq_ckdiv4_en)), + SHU_B0_DQ1_RG_ARPI_MIDPI_CKDIV4_EN_B0, + !(tr->dq_semi_open) && (tr->dq_ckdiv4_en), + SHU_B0_DQ1_RG_ARPI_MIDPI_8PH_DLY_B0, tr->ph8_dly); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq1, + SHU_B1_DQ1_RG_ARPI_MIDPI_EN_B1, + !(tr->dq_semi_open) && (!(tr->dq_ckdiv4_en)), + SHU_B1_DQ1_RG_ARPI_MIDPI_CKDIV4_EN_B1, + !(tr->dq_semi_open) && (tr->dq_ckdiv4_en), + SHU_B1_DQ1_RG_ARPI_MIDPI_8PH_DLY_B1, tr->ph8_dly); + + if (tr->ca_semi_open == 0) { + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd6, + SHU_CA_CMD6_RG_ARPI_SOPEN_EN_CA, 0, + SHU_CA_CMD6_RG_ARPI_SOPEN_CKGEN_EN_CA, 0, + SHU_CA_CMD6_RG_ARPI_OFFSET_DQSIEN_CA, 0); + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_dll_arpi3, + SHU_CA_DLL_ARPI3_RG_ARPI_FB_EN_CA, 1, + SHU_CA_DLL_ARPI3_RG_ARPI_CLK_EN, 1, + SHU_CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA, 1); + } else { + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_cmd6, + SHU_CA_CMD6_RG_ARPI_SOPEN_EN_CA, 1, + SHU_CA_CMD6_RG_ARPI_SOPEN_CKGEN_EN_CA, 1, + SHU_CA_CMD6_RG_ARPI_OFFSET_DQSIEN_CA, 16); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_dll_arpi3, + SHU_CA_DLL_ARPI3_RG_ARPI_FB_EN_CA, 1, + SHU_CA_DLL_ARPI3_RG_ARPI_CLK_EN, 1); + } + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_dll_arpi3, + SHU_CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA, 1); + SET32_BITFIELDS(&ch[1].phy_ao.shu_ca_dll_arpi3, + SHU_CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA, 0); + dramc_set_broadcast(DRAMC_BROADCAST_ON); + } + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd6, + SHU_CA_CMD6_RG_ARPI_OPEN_EN_CA, tr->dq_ca_open); + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd13, + SHU_CA_CMD13_RG_TX_ARCA_FRATE_EN_CA, tr->ca_full_rate); + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd1, + SHU_CA_CMD1_RG_ARPI_MIDPI_8PH_DLY_CA, tr->ph8_dly); + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd1, + SHU_CA_CMD1_RG_ARPI_MIDPI_CKDIV4_PREDIV_EN_CA, tr->ca_prediv_en); + + if (tr->semi_open_ca_pick_mck_ratio == 4) + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd6, + SHU_CA_CMD6_RG_ARPI_SOPEN_CKGEN_DIV_CA, 0); + else if (tr->semi_open_ca_pick_mck_ratio == 8) + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd6, + SHU_CA_CMD6_RG_ARPI_SOPEN_CKGEN_DIV_CA, 1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dll1, + SHU_B0_DLL1_RG_ARDLL_TRACKING_CA_EN_B0, tr->dq_track_ca_en); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dll1, + SHU_B1_DLL1_RG_ARDLL_TRACKING_CA_EN_B1, tr->dq_track_ca_en); + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_dll_arpi2, + SHU_CA_DLL_ARPI2_RG_ARPI_CG_CLKIEN, 1); +} + +static void ana_dll_shuffle_config(dram_freq_grp freq_group, ana_top_config *a_cfg) +{ + u8 gain = 0; + if (freq_group <= DDRFREQ_1600) { + gain = 2; + dramc_dbg("Add DLL Gain = %d\n",gain); + } + + dramc_dbg("DLL\n"); + if (a_cfg->dll_async_en == 1) { + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_dll0, + SHU_CA_DLL0_RG_ARDLL_GAIN_CA, + (a_cfg->all_slave_en == 0) ? 6 : 7, + SHU_CA_DLL0_RG_ARDLL_IDLECNT_CA, + (a_cfg->all_slave_en == 0) ? 9 : 7, + SHU_CA_DLL0_RG_ARDLL_FAST_PSJP_CA, + !(a_cfg->all_slave_en), + SHU_CA_DLL0_RG_ARDLL_GEAR2_PSJP_CA, 0, + SHU_CA_DLL0_RG_ARDLL_FASTPJ_CK_SEL_CA, + a_cfg->all_slave_en); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_dll1, + SHU_CA_DLL1_RG_ARDLL_PHDET_OUT_SEL_CA, + a_cfg->all_slave_en, + SHU_CA_DLL1_RG_ARDLL_PHDET_IN_SWAP_CA, + a_cfg->all_slave_en, + SHU_CA_DLL1_RG_ARDLL_PGAIN_CA, 0, + SHU_CA_DLL1_RG_ARDLL_PSJP_EN_CA, 1, + SHU_CA_DLL1_RG_ARDLL_PHDIV_CA, 1, + SHU_CA_DLL1_RG_ARDLL_UDIV_EN_CA, 1, + SHU_CA_DLL1_RG_ARDLL_PS_EN_CA, 1, + SHU_CA_DLL1_RG_ARDLL_PD_CK_SEL_CA, + !(a_cfg->all_slave_en)); + } + dramc_set_broadcast(DRAMC_BROADCAST_ON); + } else { + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_dll0, + SHU_CA_DLL0_RG_ARDLL_GAIN_CA, + (a_cfg->all_slave_en == 0) ? 6 + gain : 7 + gain, + SHU_CA_DLL0_RG_ARDLL_IDLECNT_CA, + (a_cfg->all_slave_en == 0) ? 9 : 7, + SHU_CA_DLL0_RG_ARDLL_FAST_PSJP_CA, + !(a_cfg->all_slave_en), + SHU_CA_DLL0_RG_ARDLL_GEAR2_PSJP_CA, 0, + SHU_CA_DLL0_RG_ARDLL_FASTPJ_CK_SEL_CA, + a_cfg->all_slave_en); + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_dll1, + SHU_CA_DLL1_RG_ARDLL_PHDET_OUT_SEL_CA, + a_cfg->all_slave_en, + SHU_CA_DLL1_RG_ARDLL_PHDET_IN_SWAP_CA, + a_cfg->all_slave_en, + SHU_CA_DLL1_RG_ARDLL_PGAIN_CA, 0, + SHU_CA_DLL1_RG_ARDLL_PSJP_EN_CA, 1, + SHU_CA_DLL1_RG_ARDLL_PHDIV_CA, 1, + SHU_CA_DLL1_RG_ARDLL_UDIV_EN_CA, 1, + SHU_CA_DLL1_RG_ARDLL_PS_EN_CA, 1, + SHU_CA_DLL1_RG_ARDLL_PD_CK_SEL_CA, + !(a_cfg->all_slave_en)); + SET32_BITFIELDS(&ch[1].phy_ao.shu_ca_dll0, + SHU_CA_DLL0_RG_ARDLL_GAIN_CA, 7+gain, + SHU_CA_DLL0_RG_ARDLL_IDLECNT_CA, 7, + SHU_CA_DLL0_RG_ARDLL_FAST_PSJP_CA, 0, + SHU_CA_DLL0_RG_ARDLL_GEAR2_PSJP_CA, 0, + SHU_CA_DLL0_RG_ARDLL_FASTPJ_CK_SEL_CA, 1); + SET32_BITFIELDS(&ch[1].phy_ao.shu_ca_dll1, + SHU_CA_DLL1_RG_ARDLL_PHDET_OUT_SEL_CA, 1, + SHU_CA_DLL1_RG_ARDLL_PHDET_IN_SWAP_CA, 1, + SHU_CA_DLL1_RG_ARDLL_PGAIN_CA, 0, + SHU_CA_DLL1_RG_ARDLL_PSJP_EN_CA, 1, + SHU_CA_DLL1_RG_ARDLL_PHDIV_CA, 1, + SHU_CA_DLL1_RG_ARDLL_UDIV_EN_CA, 1, + SHU_CA_DLL1_RG_ARDLL_PS_EN_CA, 1, + SHU_CA_DLL1_RG_ARDLL_PD_CK_SEL_CA, 0); + dramc_set_broadcast(DRAMC_BROADCAST_ON); + } + + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dll0, + SHU_B0_DLL0_RG_ARDLL_GAIN_B0, 7+gain, + SHU_B0_DLL0_RG_ARDLL_IDLECNT_B0, 7, + SHU_B0_DLL0_RG_ARDLL_FAST_PSJP_B0, 0, + SHU_B0_DLL0_RG_ARDLL_GEAR2_PSJP_B0, 0, + SHU_B0_DLL0_RG_ARDLL_FASTPJ_CK_SEL_B0, 1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dll1, + SHU_B0_DLL1_RG_ARDLL_PHDET_OUT_SEL_B0, 1, + SHU_B0_DLL1_RG_ARDLL_PHDET_IN_SWAP_B0, 1, + SHU_B0_DLL1_RG_ARDLL_PGAIN_B0, 0, + SHU_B0_DLL1_RG_ARDLL_PSJP_EN_B0, 1, + SHU_B0_DLL1_RG_ARDLL_PHDIV_B0, 1, + SHU_B0_DLL1_RG_ARDLL_UDIV_EN_B0, 1, + SHU_B0_DLL1_RG_ARDLL_PS_EN_B0, 1, + SHU_B0_DLL1_RG_ARDLL_PD_CK_SEL_B0, 0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dll0, + SHU_B1_DLL0_RG_ARDLL_GAIN_B1, 7+gain, + SHU_B1_DLL0_RG_ARDLL_IDLECNT_B1, 7, + SHU_B1_DLL0_RG_ARDLL_FAST_PSJP_B1, 0, + SHU_B1_DLL0_RG_ARDLL_GEAR2_PSJP_B1, 0, + SHU_B1_DLL0_RG_ARDLL_FASTPJ_CK_SEL_B1, 1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dll1, + SHU_B1_DLL1_RG_ARDLL_PHDET_OUT_SEL_B1, 1, + SHU_B1_DLL1_RG_ARDLL_PHDET_IN_SWAP_B1, 1, + SHU_B1_DLL1_RG_ARDLL_PGAIN_B1, 0, + SHU_B1_DLL1_RG_ARDLL_PSJP_EN_B1, 1, + SHU_B1_DLL1_RG_ARDLL_PHDIV_B1, 1, + SHU_B1_DLL1_RG_ARDLL_UDIV_EN_B1, 1, + SHU_B1_DLL1_RG_ARDLL_PS_EN_B1, 1, + SHU_B1_DLL1_RG_ARDLL_PD_CK_SEL_B1, 0); +} + +static void ana_rx_shuffle_config(dramc_subsys_config *subsys) +{ + u8 rdqs_se_en; + u8 dqsien_mode; + u8 rank_mode; + + rdqs_se_en = 0; + dqsien_mode = subsys->dfs_gp->dqsien_mode; + rank_mode = subsys->a_cfg->rank_mode; + + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq10, + SHU_B0_DQ10_RG_RX_ARDQS_SE_EN_B0, rdqs_se_en, + SHU_B0_DQ10_RG_RX_ARDQS_DQSIEN_MODE_B0, dqsien_mode, + SHU_B0_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B0, 1, + SHU_B0_DQ10_RG_RX_ARDQS_RANK_SEL_LAT_EN_B0, rank_mode, + SHU_B0_DQ10_RG_RX_ARDQS_DQSIEN_RANK_SEL_LAT_EN_B0, rank_mode); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq11, + SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B0, rank_mode, + SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B0, rank_mode); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq2, + SHU_B0_DQ2_RG_ARPI_OFFSET_LAT_EN_B0, rank_mode, + SHU_B0_DQ2_RG_ARPI_OFFSET_ASYNC_EN_B0, rank_mode); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq10, + SHU_B1_DQ10_RG_RX_ARDQS_SE_EN_B1, rdqs_se_en, + SHU_B1_DQ10_RG_RX_ARDQS_DQSIEN_MODE_B1, dqsien_mode, + SHU_B1_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B1, 1, + SHU_B1_DQ10_RG_RX_ARDQS_RANK_SEL_LAT_EN_B1, rank_mode, + SHU_B1_DQ10_RG_RX_ARDQS_DQSIEN_RANK_SEL_LAT_EN_B1, rank_mode); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq11, + SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B1, rank_mode, + SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B1, rank_mode); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq2, + SHU_B1_DQ2_RG_ARPI_OFFSET_LAT_EN_B1, rank_mode, + SHU_B1_DQ2_RG_ARPI_OFFSET_ASYNC_EN_B1, rank_mode); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq10, + SHU_B0_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B0, 0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq2, + SHU_B0_DQ2_RG_ARPI_OFFSET_LAT_EN_B0, 0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq10, + SHU_B1_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B1, 0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq2, + SHU_B1_DQ2_RG_ARPI_OFFSET_LAT_EN_B1, 0); + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd10, + SHU_CA_CMD10_RG_RX_ARCLK_RANK_SEL_LAT_EN_CA, 1, + SHU_CA_CMD10_RG_RX_ARCLK_DQSIEN_RANK_SEL_LAT_EN_CA, 1); + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd11, + SHU_CA_CMD11_RG_RX_ARCA_RANK_SEL_LAT_EN_CA, 1); +} + +static void ana_config_nonshuffle(dram_freq_grp freq_group, ana_top_config *a_cfg) +{ + suspend_on(); + spm_control(a_cfg); + ana_tx_nonshuffle_config(a_cfg); + ana_rx_nonshuffle_config(); + dig_dcm_nonshuffle_config(); + ana_imp_configure(); + ana_dll_non_shuffle_config(freq_group, a_cfg); +} + +static void ana_config_shuffle(dram_freq_grp freq_group, dramc_subsys_config *subsys) +{ + ana_top_config *a_cfg = subsys->a_cfg; + ana_dvfs_core *dvfs_core = subsys->dvfs_core; + + ana_pll_shuffle_Config(dvfs_core); + ana_arpi_shuffle_config(a_cfg, dvfs_core); + ana_tx_shuffle_config(a_cfg); + ana_rx_shuffle_config(subsys); + dig_phy_shu_misc_cg_ctrl(); + ana_clk_div_config_setting(dvfs_core, a_cfg); + ana_dll_shuffle_config(freq_group, a_cfg); +} + +static void ana_phy_config(dram_freq_grp freq_group, dramc_subsys_config *subsys) +{ + ana_top_config *a_cfg = subsys->a_cfg; + + ana_config_nonshuffle(freq_group, a_cfg); + ana_config_shuffle(freq_group, subsys); +} + +static void ana_clockoff_sequence(void) +{ + SET32_BITFIELDS(&ch[0].phy_ao.misc_cg_ctrl0, + MISC_CG_CTRL0_CLK_MEM_SEL, 0, + MISC_CG_CTRL0_W_CHG_MEM, 1); + udelay(1); + SET32_BITFIELDS(&ch[0].phy_ao.misc_cg_ctrl0, + MISC_CG_CTRL0_W_CHG_MEM, 0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dll1, + SHU_B0_DLL1_RG_ARDLL_PHDET_EN_B0, 0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dll1, + SHU_B1_DLL1_RG_ARDLL_PHDET_EN_B1, 0); + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_dll1, + SHU_CA_DLL1_RG_ARDLL_PHDET_EN_CA, 0); + + dramc_set_broadcast(DRAMC_BROADCAST_ON); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dll_arpi2, + SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_B0, 0x1, + SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B0, 0x1, + SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCTL_B0, 0x1, + SHU_B0_DLL_ARPI2_RG_ARPI_CG_FB_B0, 0x1, + SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQS_B0, 0x1, + SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQM_B0, 0x1, + SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQ_B0, 0x1, + SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B0, 0x1, + SHU_B0_DLL_ARPI2_RG_ARPI_MPDIV_CG_B0, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dll_arpi2, + SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCK_B1, 0x1, + SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B1, 0x1, + SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCTL_B1, 0x1, + SHU_B1_DLL_ARPI2_RG_ARPI_CG_FB_B1, 0x1, + SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQS_B1, 0x1, + SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQM_B1, 0x1, + SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQ_B1, 0x1, + SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B1, 0x1, + SHU_B1_DLL_ARPI2_RG_ARPI_MPDIV_CG_B1, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_dll_arpi2, + SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCK_CA, 0x1, + SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_CA, 0x1, + SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCTL_CA, 0x1, + SHU_CA_DLL_ARPI2_RG_ARPI_CG_FB_CA, 0x1, + SHU_CA_DLL_ARPI2_RG_ARPI_CG_CS, 0x1, + SHU_CA_DLL_ARPI2_RG_ARPI_CG_CLK, 0x1, + SHU_CA_DLL_ARPI2_RG_ARPI_CG_CMD, 0x1, + SHU_CA_DLL_ARPI2_RG_ARPI_CG_CLKIEN, 0x1, + SHU_CA_DLL_ARPI2_RG_ARPI_MPDIV_CG_CA, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.shu_pll2, + SHU_PLL2_RG_RPHYPLL_ADA_MCK8X_EN_SHU, 0); + SET32_BITFIELDS(&ch[0].phy_ao.phypll2, + PHYPLL2_RG_RPHYPLL_AD_MCK8X_EN, 0, + PHYPLL2_RG_RPHYPLL_ADA_MCK8X_EN, 0); + SET32_BITFIELDS(&ch[0].phy_ao.phypll0, PHYPLL0_RG_RPHYPLL_EN, 0); + SET32_BITFIELDS(&ch[0].phy_ao.phypll2, PHYPLL2_RG_RPHYPLL_RESETB, 0); +} + +static void ana_pll_sequence(void) +{ + SET32_BITFIELDS(&ch[0].phy_ao.phypll2, PHYPLL2_RG_RPHYPLL_RESETB, 1); + SET32_BITFIELDS(&ch[0].phy_ao.phypll0, PHYPLL0_RG_RPHYPLL_EN, 1); + udelay(20); +} + +static void ana_midpi_sequence(ana_dvfs_core *dvfs_core) +{ + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq1, + SHU_B0_DQ1_RG_ARPI_MIDPI_LDO_VREF_SEL_B0, 1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq1, + SHU_B1_DQ1_RG_ARPI_MIDPI_LDO_VREF_SEL_B1, 1); + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd1, + SHU_CA_CMD1_RG_ARPI_MIDPI_LDO_VREF_SEL_CA, 1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dll_arpi2, + SHU_B0_DLL_ARPI2_RG_ARPI_MPDIV_CG_B0, 1, + SHU_B0_DLL_ARPI2_RG_ARPI_CG_FB_B0, 1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dll_arpi2, + SHU_B1_DLL_ARPI2_RG_ARPI_MPDIV_CG_B1, 1, + SHU_B1_DLL_ARPI2_RG_ARPI_CG_FB_B1, 1); + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_dll_arpi2, + SHU_CA_DLL_ARPI2_RG_ARPI_MPDIV_CG_CA, 1, + SHU_CA_DLL_ARPI2_RG_ARPI_CG_FB_CA, 1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dll_arpi2, + SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_B0, 0x1, + SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B0, 0x1, + SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCTL_B0, 0x1, + SHU_B0_DLL_ARPI2_RG_ARPI_CG_FB_B0, 0x1, + SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQS_B0, 0x1, + SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQM_B0, 0x1, + SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQ_B0, 0x1, + SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B0, 0x1, + SHU_B0_DLL_ARPI2_RG_ARPI_MPDIV_CG_B0, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dll_arpi2, + SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCK_B1, 0x1, + SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B1, 0x1, + SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCTL_B1, 0x1, + SHU_B1_DLL_ARPI2_RG_ARPI_CG_FB_B1, 0x1, + SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQS_B1, 0x1, + SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQM_B1, 0x1, + SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQ_B1, 0x1, + SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B1, 0x1, + SHU_B1_DLL_ARPI2_RG_ARPI_MPDIV_CG_B1, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_dll_arpi2, + SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCK_CA, 0x1, + SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_CA, 0x1, + SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCTL_CA, 0x1, + SHU_CA_DLL_ARPI2_RG_ARPI_CG_FB_CA, 0x1, + SHU_CA_DLL_ARPI2_RG_ARPI_CG_CS, 0x1, + SHU_CA_DLL_ARPI2_RG_ARPI_CG_CLK, 0x1, + SHU_CA_DLL_ARPI2_RG_ARPI_CG_CMD, 0x1, + SHU_CA_DLL_ARPI2_RG_ARPI_CG_CLKIEN, 0x1, + SHU_CA_DLL_ARPI2_RG_ARPI_MPDIV_CG_CA, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.shu_pll2, + SHU_PLL2_RG_RPHYPLL_ADA_MCK8X_EN_SHU, 0); + SET32_BITFIELDS(&ch[0].phy_ao.phypll2, + PHYPLL2_RG_RPHYPLL_AD_MCK8X_EN, 0, + PHYPLL2_RG_RPHYPLL_ADA_MCK8X_EN, 0); + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd1, + SHU_CA_CMD1_RG_ARPI_MIDPI_EN_CA, !(dvfs_core->ca_ckdiv4_en), + SHU_CA_CMD1_RG_ARPI_MIDPI_CKDIV4_EN_CA, dvfs_core->ca_ckdiv4_en); + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd1, + SHU_CA_CMD1_RG_ARPI_MIDPI_CKDIV4_PREDIV_EN_CA, dvfs_core->ca_prediv_en); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].b0_shu_midpi_ctrl, + B0_SHU_MIDPI_CTRL_MIDPI_ENABLE_B0, + (!(dvfs_core->dq_semi_open)) && (!(dvfs_core->dq_ckdiv4_en)), + B0_SHU_MIDPI_CTRL_MIDPI_DIV4_ENABLE_B0, + (!(dvfs_core->dq_semi_open)) && (dvfs_core->dq_ckdiv4_en)); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].b0_shu_midpi_ctrl, + B1_SHU_MIDPI_CTRL_MIDPI_ENABLE_B1, + (!(dvfs_core->dq_semi_open)) && (!(dvfs_core->dq_ckdiv4_en)), + B1_SHU_MIDPI_CTRL_MIDPI_DIV4_ENABLE_B1, + (!(dvfs_core->dq_semi_open)) && (dvfs_core->dq_ckdiv4_en)); + SET32_BITFIELDS(&ch[0].phy_ao.ca_shu_midpi_ctrl, + CA_SHU_MIDPI_CTRL_MIDPI_ENABLE_CA, !(dvfs_core->ca_ckdiv4_en), + CA_SHU_MIDPI_CTRL_MIDPI_DIV4_ENABLE_CA, dvfs_core->ca_ckdiv4_en); + SET32_BITFIELDS(&ch[0].phy_ao.ca_dll_arpi0, + CA_DLL_ARPI0_RG_ARPI_RESETB_CA, 0); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dll_arpi0, + B0_DLL_ARPI0_RG_ARPI_RESETB_B0, 0); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dll_arpi0, + B1_DLL_ARPI0_RG_ARPI_RESETB_B1, 0); + SET32_BITFIELDS(&ch[0].phy_ao.ca_dll_arpi0, + CA_DLL_ARPI0_RG_ARPI_RESETB_CA, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dll_arpi0, + B0_DLL_ARPI0_RG_ARPI_RESETB_B0, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dll_arpi0, + B1_DLL_ARPI0_RG_ARPI_RESETB_B1, 1); + SET32_BITFIELDS(&ch[0].phy_ao.shu_pll2, + SHU_PLL2_RG_RPHYPLL_ADA_MCK8X_EN_SHU, 1); + SET32_BITFIELDS(&ch[0].phy_ao.phypll2, + PHYPLL2_RG_RPHYPLL_AD_MCK8X_EN, 1, + PHYPLL2_RG_RPHYPLL_ADA_MCK8X_EN, 1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dll_arpi2, + SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_B0, 0x0, + SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B0, 0x0, + SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCTL_B0, 0x0, + SHU_B0_DLL_ARPI2_RG_ARPI_CG_FB_B0, 0x0, + SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQS_B0, 0x0, + SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQM_B0, 0x0, + SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQ_B0, 0x0, + SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B0, 0x0, + SHU_B0_DLL_ARPI2_RG_ARPI_MPDIV_CG_B0, dvfs_core->dq_semi_open); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dll_arpi2, + SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCK_B1, 0x0, + SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B1, 0x0, + SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCTL_B1, 0x0, + SHU_B1_DLL_ARPI2_RG_ARPI_CG_FB_B1, 0x0, + SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQS_B1, 0x0, + SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQM_B1, 0x0, + SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQ_B1, 0x0, + SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B1, 0x0, + SHU_B1_DLL_ARPI2_RG_ARPI_MPDIV_CG_B1, dvfs_core->dq_semi_open); + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_dll_arpi2, + SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCK_CA, 0x0, + SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_CA, 0x0, + SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCTL_CA, 0x0, + SHU_CA_DLL_ARPI2_RG_ARPI_CG_FB_CA, 0x0, + SHU_CA_DLL_ARPI2_RG_ARPI_CG_CS, 0x0, + SHU_CA_DLL_ARPI2_RG_ARPI_CG_CLK, 0x0, + SHU_CA_DLL_ARPI2_RG_ARPI_CG_CMD, 0x0, + SHU_CA_DLL_ARPI2_RG_ARPI_CG_CLKIEN, 0x0, + SHU_CA_DLL_ARPI2_RG_ARPI_MPDIV_CG_CA, 0x0); +} + +static void ana_clock_switch(ana_dvfs_core *a_dvfs_cor) +{ + if (a_dvfs_cor->dq_ca_open) { + SET32_BITFIELDS(&ch[0].phy_ao.misc_cg_ctrl0, + MISC_CG_CTRL0_RESERVED_MISC_CG_CTRL0_BIT3_1, 1); + udelay(1); + SET32_BITFIELDS(&ch[0].phy_ao.misc_cg_ctrl0, + MISC_CG_CTRL0_RESERVED_MISC_CG_CTRL0_BIT3_1, 0); + } + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.misc_ckmux_sel, + MISC_CKMUX_SEL_R_PHYCTRLDCM, 1, + MISC_CKMUX_SEL_R_PHYCTRLMUX, 1); + + dramc_set_broadcast(DRAMC_BROADCAST_ON); + SET32_BITFIELDS(&ch[0].phy_ao.misc_cg_ctrl0, + MISC_CG_CTRL0_CLK_MEM_SEL, 1, + MISC_CG_CTRL0_W_CHG_MEM, 1); + + udelay(1); + SET32_BITFIELDS(&ch[0].phy_ao.misc_cg_ctrl0, + MISC_CG_CTRL0_W_CHG_MEM, 0); + SET32_BITFIELDS(&ch[0].phy_ao.misc_cg_ctrl0, + MISC_CG_CTRL0_RG_FREERUN_MCK_CG, 1); + if (a_dvfs_cor->dq_ca_open) + SET32_BITFIELDS(&ch[0].phy_ao.misc_cg_ctrl0, + MISC_CG_CTRL0_RESERVED_MISC_CG_CTRL0_BIT7, 1); +} + +static void ana_dll_sequence(ana_dvfs_core *dvfs_core, ana_top_config *a_cfg) +{ + u8 dll_async_en; + u8 all_slave_en; + + dll_async_en = a_cfg->dll_async_en; + all_slave_en = a_cfg->all_slave_en; + + dramc_dbg("[ANA_INIT] DLL >>\n"); + SET32_BITFIELDS(&ch[0].phy_ao.ca_cmd8, + CA_CMD8_RG_ARDLL_RESETB_CA, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq8, + B0_DQ8_RG_ARDLL_RESETB_B0, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq8, + B1_DQ8_RG_ARDLL_RESETB_B1, 1); + if (all_slave_en == 1) { + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_dll1, + SHU_CA_DLL1_RG_ARDLL_PHDET_EN_CA, 1); + + dramc_set_broadcast(DRAMC_BROADCAST_ON); + udelay(1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dll1, + SHU_B0_DLL1_RG_ARDLL_PHDET_EN_B0, !(dvfs_core->dq_semi_open)); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dll1, + SHU_B1_DLL1_RG_ARDLL_PHDET_EN_B1, !(dvfs_core->dq_semi_open)); + udelay(1); + } else { + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + if (dll_async_en == 1) { + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_dll1, + SHU_CA_DLL1_RG_ARDLL_PHDET_EN_CA, 1); + udelay(1); + } else { + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_dll1, + SHU_CA_DLL1_RG_ARDLL_PHDET_EN_CA, 1); + udelay(1); + SET32_BITFIELDS(&ch[1].phy_ao.shu_ca_dll1, + SHU_CA_DLL1_RG_ARDLL_PHDET_EN_CA, 1); + udelay(1); + } + dramc_set_broadcast(DRAMC_BROADCAST_ON); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dll1, + SHU_B0_DLL1_RG_ARDLL_PHDET_EN_B0, !(dvfs_core->dq_semi_open)); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dll1, + SHU_B1_DLL1_RG_ARDLL_PHDET_EN_B1, !(dvfs_core->dq_semi_open)); + udelay(1); + } +} + +void ana_clk_div_config( ana_dvfs_core *tr, dvfs_group_config *dfs) +{ + u32 semi_open_fmin = 300; + u32 semi_open_fmax = 500; + u32 pi_fmin = 600; + u32 dq_pick; + u32 ca_pick; + u32 ca_mckio; + u32 mckio_semi = 0; + u16 data_rate = dfs->data_rate; + tr->dq_p2s_ratio = dfs->dq_p2s_ratio; + tr->ckr = dfs->ckr; + + tr->ca_p2s_ratio = tr->dq_p2s_ratio/tr->ckr; + tr->dq_ca_open = ( data_rate < (semi_open_fmin * 2)) ? 1 : 0; + tr->dq_semi_open = ( data_rate/2 < pi_fmin) ? (1-tr->dq_ca_open) : + ((data_rate <= semi_open_fmax*2) ? (1-tr->dq_ca_open) : 0); + tr->ca_semi_open = (( data_rate/(tr->ckr*2) < pi_fmin) ? + ((data_rate/(tr->ckr*2) > semi_open_fmax) ? 0 : + (((tr->ca_p2s_ratio>2)||(tr->dq_semi_open)) * (1-tr->dq_ca_open))) : + tr->dq_semi_open); + tr->ca_full_rate = (tr->dq_ca_open == 1) ? ((tr->ckr>1)?1:0) : + ((tr->dq_semi_open*tr->ca_semi_open*(tr->ckr>>1)) + + (( data_rate/(tr->ckr*2) < pi_fmin) ? (1-tr->ca_semi_open) : 0)); + tr->dq_ckdiv4_en = ( tr->dq_semi_open == 1) ? 0 : + ((( (data_rate/2) < 1200) ? 1 : 0) * (1-tr->dq_ca_open)) ; + + ca_mckio = (data_rate/(tr->ckr*2))*(1+tr->ca_full_rate); + dq_pick = (tr->dq_semi_open == 1) ? 0 : (data_rate/2) ; + ca_pick = (tr->ca_semi_open == 1) ? ca_mckio*2 : ((ca_mckio>=pi_fmin) ? + ca_mckio : (( ca_mckio >= (pi_fmin/2)) ? ca_mckio*2 : ca_mckio *4)); + tr->ca_ckdiv4_en = ((ca_pick < 1200) ? 1 : 0) * ( 1- tr->dq_ca_open) ; + tr->ca_prediv_en = (data_rate >= 4800) ? 1 : 0 ; + + if (data_rate <= 1866) + tr->ph8_dly = 0; + else if (data_rate <= 2400) + tr->ph8_dly = 0x11; + else if (data_rate <= 3200) + tr->ph8_dly = 0xc; + else if (data_rate <= 3733) + tr->ph8_dly = 0x9; + else + tr->ph8_dly = 0x7; + + tr->semi_open_ca_pick_mck_ratio = ( mckio_semi == 0) ? + 0 : (ca_pick*tr->dq_p2s_ratio)/data_rate ; + tr->dq_aamck_div = (tr->dq_semi_open == 0) ? + ((tr->dq_p2s_ratio/2)*(1-tr->dq_semi_open)) : 0; + tr->ca_admck_div = ca_pick/(data_rate/tr->dq_p2s_ratio); + tr->dq_track_ca_en = 0 ; + tr->pll_freq = ((dq_pick * 2 * (tr->dq_ckdiv4_en+1)) > (ca_pick * 2 *(tr->ca_ckdiv4_en + 1))) ? + (dq_pick*2*(tr->dq_ckdiv4_en+1)) : (ca_pick*2*(tr->ca_ckdiv4_en+1)); + + if (data_rate==2400) + tr->pll_freq = 2366; + else if (data_rate==1200) + tr->pll_freq = 2288; + else if (data_rate==3200 || data_rate==1600) + tr->pll_freq = 3068; + else if (data_rate==800) + tr->pll_freq = 3016; + else if (data_rate==400) + tr->pll_freq = 4000; +} + +static void ana_init_sequence(ana_dvfs_core *dvfs_core, ana_top_config *a_cfg) +{ + ana_pll_sequence(); + ana_midpi_sequence(dvfs_core); + ana_clock_switch(dvfs_core); + ana_dll_sequence(dvfs_core,a_cfg); +} + +void ana_init(const struct ddr_cali *cali, dramc_subsys_config *subsys) +{ + dram_freq_grp freq_group = cali->freq_group; + + dramc_subsys_pre_config(freq_group, subsys); + dramc_dbg("ANA_INIT\n"); + + SET32_BITFIELDS(&ch[0].phy_ao.ca_cmd2, + CA_CMD2_RG_TX_ARCMD_OE_DIS_CA, 1, + CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA, 0, + CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA, 0xff); + ana_clockoff_sequence(); + ana_phy_config(freq_group, subsys); + ana_init_sequence(subsys->dvfs_core, subsys->a_cfg); + SET32_BITFIELDS(&ch[0].phy_ao.ca_cmd2, + CA_CMD2_RG_TX_ARCMD_OE_DIS_CA, 0, + CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA, 1, + CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA, 0xff); + single_end_dramc_post_config(subsys->lp4_init->lp4y_en); +} diff --git a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c index 1d6b6c2..d32c268 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c @@ -3742,6 +3742,12 @@ static void dramc_setting(const struct ddr_cali *cali) { + dramc_subsys_config subsys; + ana_top_config ana_top_p; + struct gating_config gat_config; + static ana_dvfs_core ana_dvfs; + static dram_config lp4_config; + dvfs_group_config dvfs_config; dram_freq_grp freq_group = cali->freq_group; dramc_set_broadcast(DRAMC_BROADCAST_ON); @@ -3766,6 +3772,13 @@ return; } + resetb_pull_dn(); + subsys.a_cfg = &ana_top_p; + subsys.dvfs_core = &ana_dvfs; + subsys.lp4_init = &lp4_config; + subsys.dfs_gp = &dvfs_config; + subsys.gat_c = &gat_config; + ana_init(cali, &subsys); update_initial_settings(cali); dramc_set_broadcast(DRAMC_BROADCAST_OFF); } diff --git a/src/soc/mediatek/mt8192/dramc_subsys_config.c b/src/soc/mediatek/mt8192/dramc_subsys_config.c new file mode 100644 index 0000000..146e073 --- /dev/null +++ b/src/soc/mediatek/mt8192/dramc_subsys_config.c @@ -0,0 +1,134 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/dramc_pi_api.h> +#include <soc/dramc_register.h> + +static u8 get_dram_RL_WL_mr_field_config(dram_freq_grp freq_group) +{ + u8 mr2_rl_wl = 2; + + switch(freq_group) { + case DDRFREQ_400: + case DDRFREQ_600: + case DDRFREQ_800: + mr2_rl_wl = 2; + break; + case DDRFREQ_933: + mr2_rl_wl = 3; + break; + case DDRFREQ_1200: + mr2_rl_wl = 4; + break; + case DDRFREQ_1600: + mr2_rl_wl = 5; + break; + case DDRFREQ_2133: + mr2_rl_wl = 7; + break; + default: + dramc_dbg("ERROR: Unexpected freq:0x%x\n", freq_group); + break; + } + + return mr2_rl_wl; +} + +void dram_configure(dram_freq_grp freq_group, dram_config *tr) +{ + tr->mr_wl = get_dram_RL_WL_mr_field_config(freq_group); + tr->dbi_wr = 0; + tr->dbi_rd = 0; + tr->lp4y_en = 0; + tr->work_fsp = (freq_group > DDRFREQ_1200) ? 1 : 0; +} + +void dramc_subsys_pre_config(dram_freq_grp freq_group, dramc_subsys_config *subsys) +{ + ana_top_config *a_cfg = subsys->a_cfg; + dram_config *lp4_init = subsys->lp4_init; + dvfs_group_config *dfs_gp = subsys->dfs_gp; + + subsys->freq_group = freq_group; + dfs_gp->ckr = 1; + dfs_gp->dqsien_mode = 1; + lp4_init->ex_row_en[RANK_0] = (get_row_width_from_emi(RANK_0) >= 18) ? 1 : 0; + lp4_init->ex_row_en[RANK_1] = (get_row_width_from_emi(RANK_1) >= 18) ? 1 : 0; + lp4_init->lp4y_en = 0; + a_cfg->new_8x_mode = 1; + a_cfg->aphy_comb_en = 1 ; + a_cfg->dll_idle_mode = 1; + a_cfg->rank_mode = 1; + a_cfg->dll_async_en = 0; + + switch (freq_group) { + case DDRFREQ_400: + dfs_gp->data_rate = 800; + dfs_gp->dq_p2s_ratio = 4; + break; + case DDRFREQ_600: + dfs_gp->data_rate = 1200; + dfs_gp->dq_p2s_ratio = 8; + break; + case DDRFREQ_800: + dfs_gp->data_rate = 1600; + dfs_gp->dq_p2s_ratio = 8; + break; + case DDRFREQ_933: + dfs_gp->data_rate = 1866; + dfs_gp->dq_p2s_ratio = 8; + break; + case DDRFREQ_1200: + dfs_gp->data_rate = 2400; + dfs_gp->dq_p2s_ratio = 8; + break; + case DDRFREQ_1600: + dfs_gp->data_rate = 3200; + dfs_gp->dq_p2s_ratio = 8; + break; + case DDRFREQ_2133: + dfs_gp->data_rate = 4266; + dfs_gp->dq_p2s_ratio = 8; + break; + default: + die("Invalid DDR frequency group %u\n", freq_group); + return; + } + + dram_configure(freq_group, lp4_init); + + a_cfg->all_slave_en = (freq_group <= DDRFREQ_933) ? 1 : 0; + a_cfg->tx_odt_dis = (freq_group <= DDRFREQ_1200) ? 1 : 0 ; + + ana_clk_div_config(subsys->dvfs_core, subsys->dfs_gp); +} + +void single_end_dramc_post_config(u8 lp4y_en) +{ + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd13, + SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_SEL_CA, lp4y_en, + SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_EN_CA, lp4y_en); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq13, + SHU_B0_DQ13_RG_TX_ARDQSB_OE_TIE_SEL_B0, lp4y_en, + SHU_B0_DQ13_RG_TX_ARDQSB_OE_TIE_EN_B0, lp4y_en); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq13, + SHU_B1_DQ13_RG_TX_ARDQSB_OE_TIE_SEL_B1, lp4y_en, + SHU_B1_DQ13_RG_TX_ARDQSB_OE_TIE_EN_B1, lp4y_en); + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd0, + SHU_CA_CMD0_R_LP4Y_WDN_MODE_CLK, 0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq0, + SHU_B0_DQ0_R_LP4Y_WDN_MODE_DQS0, 0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq0, + SHU_B1_DQ0_R_LP4Y_WDN_MODE_DQS1, 0); + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd7, + SHU_CA_CMD7_R_LP4Y_SDN_MODE_CLK, 0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq7, + SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0, lp4y_en); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq7, + SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1, lp4y_en); + SET32_BITFIELDS(&ch[0].phy_ao.ca_cmd7, + CA_CMD7_RG_TX_ARCLKB_PULL_DN_LP4Y, 0); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq7, + B0_DQ7_RG_TX_ARDQS0B_PULL_DN_B0_LP4Y, 0); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq7, + B1_DQ7_RG_TX_ARDQS0B_PULL_DN_B1_LP4Y, 0); +} diff --git a/src/soc/mediatek/mt8192/emi.c b/src/soc/mediatek/mt8192/emi.c index b587993..acd605f 100644 --- a/src/soc/mediatek/mt8192/emi.c +++ b/src/soc/mediatek/mt8192/emi.c @@ -320,6 +320,27 @@ return ma_type; } +u32 get_row_width_from_emi(u32 rank) +{ + u32 emi_cona; + u32 shift_row, shift_ext; + int row_width; + + if (rank == 0) { + shift_row = 12; + shift_ext = 22; + } else if (rank == 1) { + shift_row = 14; + shift_ext = 23; + } else + return -1; + + emi_cona = read32(&emi_reg->cona); + row_width = ((emi_cona >> shift_row) & 0x3) | ((emi_cona >> shift_ext) & 0x4); + + return (row_width + 13); +} + static void emi_sw_setting(void) { setbits32(&emi_mpu->mpu_ctrl_d[1], BIT(4)); -- To view, visit https://review.coreboot.org/c/coreboot/+/44727 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53b30a2bbed5acb363f85f7cbc7f255fdbc52304 Gerrit-Change-Number: 44727 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

22 hours, 7 minutes

Change in coreboot[master]: soc/mediatek/mt8192: Do dramc tx window training

by CK HU (Code Review)

Hello Duan huayang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44720 to review the following change. Change subject: soc/mediatek/mt8192: Do dramc tx window training ...................................................................... soc/mediatek/mt8192: Do dramc tx window training Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> Change-Id: Ica11573c1e0b657be0e8ddcbf81a9e3f2399e258 --- M src/soc/mediatek/mt8192/dramc_pi_calibration_api.c M src/soc/mediatek/mt8192/dramc_pi_main.c 2 files changed, 794 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/44720/1 diff --git a/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c index 363a3bd..602e61d 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c @@ -5,6 +5,11 @@ #include <soc/dramc_register.h> #include <timer.h> +#define PASS_RANGE_NA 0x7fff +#define TX_VREF_RANGE_BEGIN 16 +#define TX_VREF_RANGE_END 50 +#define TX_VREF_RANGE_STEP 2 + static const u8 ca_pinmux_mapping[PINMUX_MAX][CHANNEL_MAX][CA_NUM_LP4] = { [PINMUX_DSC] = { [CHANNEL_A] = {1, 4, 5, 3, 2, 0}, @@ -35,6 +40,12 @@ u16 best_dqdly; } pass_win_data_t; +typedef struct { + u16 vref_used; + u16 winsum_by_vref; + u8 worse_bit_winsize; + u8 worse_bit_idx; +} pass_win_data_vref_t; static const u8 imp_vref_sel[ODT_MAX][IMP_DRV_MAX] = { /* DRVP DRVN ODTP ODTN */ @@ -1704,6 +1715,19 @@ read_dqs_inctl, rank_inctl_root, xrtr2r); } +static void dramc_set_rw_ofoen(u8 chn, u8 onoff) +{ + u32 loop = 0, loop_cnt = 100000; + + while (READ32_BITFIELD(&ch[chn].nao.misc_statusa, MISC_STATUSA_REQQ_EMPTY) != 1) { + loop ++; + if (loop > loop_cnt) { + dramc_dbg("RWOFOEN timout! queue is not empty\n"); + break; + } + } + SET32_BITFIELDS(&ch[chn].ao.scheduler_com, SCHEDULER_COM_RWOFOEN, onoff); +} static void dramc_set_rank_engin2(u8 chn, u8 rank) { @@ -1767,6 +1791,94 @@ dramc_engin2_set_pat(chn, rank, 0); } +static void dramc_engine2_check_complete(u8 chn, u8 status) +{ + u32 loop = 0, loop_max = 100000; + u32 ta2_loop_cnt = 0; + + while ((read32(&ch[chn].nao.testrpt) & status) != status) { + udelay(1); + loop++; + if (loop > loop_max) { + dramc_dbg("testrpt time out, [22:20]=%#x\n", + READ32_BITFIELD(&ch[chn].nao.testrpt, TESTRPT_TESTSTAT)); + break; + } + } + + loop = 0; + if (READ32_BITFIELD(&ch[chn].ao.test2_a3, TEST2_A3_TEST2_PAT_SHIFT)) { + while ((ta2_loop_cnt = read32(&ch[chn].nao.test_loop_cnt)) != 8) { + loop++; + if (loop > loop_max) { + dramc_dbg("test_loop_cnt time out, TEST_LOOP_CNT[%d]\n", + ta2_loop_cnt); + break; + } + } + } +} + +static u32 dramc_engine2_compare(u8 chn) +{ + u8 status = 1; + u32 result = 0xffffffff; + u32 loop_cnt; + u32 shift_ui_flag = 0; + + loop_cnt = READ32_BITFIELD(&ch[chn].ao.test2_a3, TEST2_A3_TESTCNT); + if (loop_cnt == 1) + status = 3; + + shift_ui_flag = READ32_BITFIELD(&ch[chn].ao.test2_a3, TEST2_A3_TEST2_PAT_SHIFT); + + if (!shift_ui_flag) { + dramc_engine2_check_complete(chn, status); + + SET32_BITFIELDS(&ch[chn].ao.test2_a3, + TEST2_A3_TEST2W, 0, + TEST2_A3_TEST2R, 0, + TEST2_A3_TEST1, 0); + udelay(1); + SET32_BITFIELDS(&ch[chn].ao.test2_a3, + TEST2_A3_TEST2W, 0, + TEST2_A3_TEST2R, 1, + TEST2_A3_TEST1, 0); + } + + dramc_engine2_check_complete(chn, status); + result = (read32(&ch[chn].nao.testrpt) >> 4) & status; + + return result; +} + +static u32 dramc_engine2_run(u8 chn) +{ + u32 result = 0xffffffff; + + SET32_BITFIELDS(&ch[chn].ao.test2_a3, + TEST2_A3_TEST2W, 1, + TEST2_A3_TEST2R, 0, + TEST2_A3_TEST1, 0); + dramc_engine2_compare(chn); + udelay(1); + result = read32(&ch[chn].nao.cmp_err); + SET32_BITFIELDS(&ch[chn].ao.test2_a3, + TEST2_A3_TEST2W, 0, + TEST2_A3_TEST2R, 0, + TEST2_A3_TEST1, 0); + + return result; +} + +static void dramc_engine2_end(u8 chn, u32 dummy_rd) +{ + SET32_BITFIELDS(&ch[chn].ao.test2_a4, + TEST2_A4_TEST_REQ_LEN1, 0); + dramc_set_rw_ofoen(chn, 1); + write32(&ch[chn].ao.dummy_rd, dummy_rd); +} + static const u8 uiLPDDR4_RDDQC_Mapping_POP[PINMUX_MAX][CHANNEL_MAX][DQ_DATA_WIDTH] = { [PINMUX_DSC] = { @@ -1843,6 +1955,7 @@ SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dq8, SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1, 1); } + void dramc_rx_window_perbit_cal(const struct ddr_cali* cali, rx_cali_type cali_type) { u8 chn, rank, fsp; @@ -1956,3 +2069,647 @@ bit + 2, final_win_perbit[bit + 2].best_dqdly, bit + 3, final_win_perbit[bit + 3].best_dqdly); } + +static void tx_perbit_calibarion_init(u8 chn, u8 rank, u8 cali_type) +{ + if (cali_type != TX_DQ_DQS_MOVE_DQM_ONLY) { + write32(&ch[chn].phy_ao.byte[0].rk[rank].shu_r0_b0_txdly0, 0); + write32(&ch[chn].phy_ao.byte[0].rk[rank].shu_r0_b0_txdly1, 0); + write32(&ch[chn].phy_ao.byte[1].rk[rank].shu_r0_b0_txdly0, 0); + write32(&ch[chn].phy_ao.byte[1].rk[rank].shu_r0_b0_txdly1, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].rk[rank].shu_r0_b0_txdly3, + SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0, 0x0); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].rk[rank].shu_r0_b0_txdly3, + SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1, 0x0); + } +} + +static void tx_win_transfer_delay_to_uipi(const struct ddr_cali* cali, u16 delay, + u8 pi_to_center, u8 *p_ui_large_dq, u8 *p_ui_small_dq, u8 *p_pi, + u8 *p_ui_large_dqoe, u8 *p_ui_small_dqoe) +{ + dram_freq_grp freq_group = cali->freq_group; + bool is_freq_400 = freq_group == DDRFREQ_400; + + u8 small_ui_to_large, pi = 0, pi_to_ui, tx_dq_oe_shift = 0; + u8 pi_tap = is_freq_400 ? TX_PHASE_DQ_UI_TO_PI_TAP : TX_DQ_UI_TO_PI_TAP; + u16 tmp_val, dqoe_shift; + u8 mr03 = cali->mr_value->mr03[get_fsp(cali)]; + small_ui_to_large = get_mck2ui_div_shift(cali); + tx_dq_oe_shift = 3; + + if (p_pi != NULL) { + pi = delay & (pi_tap-1); + *p_pi =pi; + } + + if (is_freq_400) + pi_to_ui = 0; + else + pi_to_ui = 1; + + tmp_val = (delay /pi_tap) << pi_to_ui; + + if (pi_to_center && (p_pi != NULL) && (!is_freq_400)) { + if (pi < 10) { + pi += (pi_tap) >> 1; + tmp_val --; + } else if (pi > pi_tap - 10) { + pi -= (pi_tap) >> 1; + tmp_val ++; + } + + *p_pi = pi; + } + + *p_ui_small_dq = tmp_val - ((tmp_val >> small_ui_to_large) << small_ui_to_large); + *p_ui_large_dq = (tmp_val >> small_ui_to_large); + + tmp_val -= tx_dq_oe_shift; + + if (((mr03 & 0x80) >> 7) == 1) { + if (get_div_mode(cali) == DIV4_MODE) + dqoe_shift = 4; + else + dqoe_shift = 8; + + tmp_val += dqoe_shift; + } + + *p_ui_small_dqoe = tmp_val - ((tmp_val >> small_ui_to_large) << small_ui_to_large); + *p_ui_large_dqoe = (tmp_val >> small_ui_to_large); +} + +static void tx_set_delay_reg_dq(u8 chn, u8 rank, u8 update_reg_ui, u8 dq_ui_large[], + u8 dq_oen_ui_large[], u8 dq_ui_small[], u8 dq_oen_ui_small[], u8 dql_pi[]) +{ + if (update_reg_ui) { + SET32_BITFIELDS(&ch[chn].ao.shu_rk[rank].shurk_selph_dq0, + SHURK_SELPH_DQ0_TXDLY_DQ0, dq_ui_large[0], + SHURK_SELPH_DQ0_TXDLY_DQ1, dq_ui_large[1], + SHURK_SELPH_DQ0_TXDLY_DQ2, dq_ui_large[0], + SHURK_SELPH_DQ0_TXDLY_DQ3, dq_ui_large[1], + SHURK_SELPH_DQ0_TXDLY_OEN_DQ0, dq_oen_ui_large[0], + SHURK_SELPH_DQ0_TXDLY_OEN_DQ1, dq_oen_ui_large[1], + SHURK_SELPH_DQ0_TXDLY_OEN_DQ2, dq_oen_ui_large[0], + SHURK_SELPH_DQ0_TXDLY_OEN_DQ3, dq_oen_ui_large[1]); + + SET32_BITFIELDS(&ch[chn].ao.shu_rk[rank].shurk_selph_dq2, + SHURK_SELPH_DQ2_DLY_DQ0, dq_ui_small[0], + SHURK_SELPH_DQ2_DLY_DQ1, dq_ui_small[1], + SHURK_SELPH_DQ2_DLY_DQ2, dq_ui_small[0], + SHURK_SELPH_DQ2_DLY_DQ3, dq_ui_small[1], + SHURK_SELPH_DQ2_DLY_OEN_DQ0, dq_oen_ui_small[0], + SHURK_SELPH_DQ2_DLY_OEN_DQ1, dq_oen_ui_small[1], + SHURK_SELPH_DQ2_DLY_OEN_DQ2, dq_oen_ui_small[0], + SHURK_SELPH_DQ2_DLY_OEN_DQ3, dq_oen_ui_small[1]); + } + + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].rk[rank].shu_r0_b0_dq0, + SHU_R0_B0_DQ0_SW_ARPI_DQ_B0, dql_pi[0]); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].rk[rank].shu_r0_b0_dq0, + SHU_R0_B1_DQ0_SW_ARPI_DQ_B1, dql_pi[1]); +} + +static void tx_set_delay_reg_dqm(u8 chn, u8 rank, u8 update_reg_ui, u8 dqm_ui_large[], + u8 dqm_oen_ui_large[], u8 dqm_ui_small[], u8 dqm_oen_ui_small[], u8 dqm_pi[]) +{ + if (update_reg_ui) { + SET32_BITFIELDS(&ch[chn].ao.shu_rk[rank].shurk_selph_dq1, + SHURK_SELPH_DQ1_TXDLY_DQM0, dqm_ui_large[0], + SHURK_SELPH_DQ1_TXDLY_DQM1, dqm_ui_large[1], + SHURK_SELPH_DQ1_TXDLY_DQM2, dqm_ui_large[0], + SHURK_SELPH_DQ1_TXDLY_DQM3, dqm_ui_large[1], + SHURK_SELPH_DQ1_TXDLY_OEN_DQM0, dqm_oen_ui_large[0], + SHURK_SELPH_DQ1_TXDLY_OEN_DQM1, dqm_oen_ui_large[1], + SHURK_SELPH_DQ1_TXDLY_OEN_DQM2, dqm_oen_ui_large[0], + SHURK_SELPH_DQ1_TXDLY_OEN_DQM3, dqm_oen_ui_large[1]); + + SET32_BITFIELDS(&ch[chn].ao.shu_rk[rank].shurk_selph_dq3, + SHURK_SELPH_DQ3_DLY_DQM0, dqm_ui_small[0], + SHURK_SELPH_DQ3_DLY_DQM1, dqm_ui_small[1], + SHURK_SELPH_DQ3_DLY_DQM2, dqm_ui_small[0], + SHURK_SELPH_DQ3_DLY_DQM3, dqm_ui_small[1], + SHURK_SELPH_DQ3_DLY_OEN_DQM0, dqm_oen_ui_small[0], + SHURK_SELPH_DQ3_DLY_OEN_DQM1, dqm_oen_ui_small[1], + SHURK_SELPH_DQ3_DLY_OEN_DQM2, dqm_oen_ui_small[0], + SHURK_SELPH_DQ3_DLY_OEN_DQM3, dqm_oen_ui_small[1]); + } + + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].rk[rank].shu_r0_b0_dq0, + SHU_R0_B0_DQ0_SW_ARPI_DQM_B0, dqm_pi[0]); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].rk[rank].shu_r0_b0_dq0, + SHU_R0_B1_DQ0_SW_ARPI_DQM_B1, dqm_pi[1]); +} + +static void update_tx_tracking(u8 chn, u8 rank, tx_cali_type cali_type, u8 dq_pi[], u8 dqm_pi[]) +{ + if (cali_type == TX_DQ_DQS_MOVE_DQ_ONLY || cali_type == TX_DQ_DQS_MOVE_DQM_ONLY) { + if (cali_type == TX_DQ_DQS_MOVE_DQ_ONLY) { + SET32_BITFIELDS(&ch[chn].ao.shu_rk[rank].shurk_pi, + SHURK_PI_RK0_ARPI_DQ_B0, dq_pi[0], + SHURK_PI_RK0_ARPI_DQ_B1, dq_pi[1]); + SET32_BITFIELDS(&ch[chn].ao.shu_rk[rank].shurk_dqs2dq_cal1, + SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1, dq_pi[1], + SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0, dq_pi[0]); + SET32_BITFIELDS(&ch[chn].ao.shu_rk[rank].shurk_dqs2dq_cal2, + SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1, dq_pi[1], + SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0, dq_pi[0]); + } + + SET32_BITFIELDS(&ch[chn].ao.shu_rk[rank].shurk_pi, + SHURK_PI_RK0_ARPI_DQM_B0, dqm_pi[0], + SHURK_PI_RK0_ARPI_DQM_B1, dqm_pi[1]); + + SET32_BITFIELDS(&ch[chn].ao.shu_rk[rank].shurk_dqs2dq_cal5, + SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1, dqm_pi[1], + SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0, dqm_pi[0]); + } +} + +static void dramc_tx_set_vref(const struct ddr_cali* cali, u8 vref_range, u8 vref) +{ + u8 mr_value = (vref & 0x3f) | (vref_range << 6); + + dramc_mode_reg_write_by_rank(cali, cali->chn, cali->rank, 14, mr_value); +} + +static void tx_scan_range_PI(const struct ddr_cali* cali, tx_cali_type cali_type, + u16 *begin, u16 *end, const u8 dqs_final_delay[2][2]) +{ + u8 mck_to_ui, ui_to_pi, byte; + u8 dq_ui_large_bak[DQS_NUMBER], dq_ui_small_bak[DQS_NUMBER]; + u16 temp_virtual_delay, smallest_virtual_delay = 0xffff; + u16 delay_begin = 0, delay_end = 0; + u32 tx_dly, delay; + + u8 chn = cali->chn; + u8 rank = cali->rank; + + tx_dly = read32(&ch[chn].ao.shu_selph_dqs0); + delay = read32(&ch[chn].ao.shu_selph_dqs1); + mck_to_ui = get_mck2ui_div_shift(cali); + ui_to_pi = 5; + + for (byte = 0; byte < BYTE_NUM; byte++) { + dq_ui_large_bak[byte] = (tx_dly >> (byte << 2)) & 0x7; + dq_ui_small_bak[byte] = (delay >> (byte << 2)) & 0x7; + temp_virtual_delay = (((dq_ui_large_bak[byte] << mck_to_ui) + + dq_ui_small_bak[byte]) << ui_to_pi) + dqs_final_delay[rank][byte]; + + if (temp_virtual_delay < smallest_virtual_delay) + smallest_virtual_delay = temp_virtual_delay; + } + + delay_begin = smallest_virtual_delay; + + if (cali_type == TX_DQ_DQS_MOVE_DQM_ONLY) + delay_begin -= (1 << (mck_to_ui + 5)); + delay_end = delay_begin + ((1 << mck_to_ui) << ui_to_pi); + + *begin = delay_begin; + *end = delay_end; +} + +static void tx_scan_range_vref(const struct ddr_cali* cali, bool enable_vref_scan, + u16 *range, u16 *begin, u16 *end, u16 *step) +{ + u16 vref_begin, vref_end; + u8 odt = get_odt_state(cali); + const struct sdram_params *params = cali->params; + + if (enable_vref_scan) { + vref_begin = params->tx_window_vref[cali->chn][cali->rank]; + vref_end = vref_begin + 1; + }else { + vref_begin = 0; + vref_end = 0; + } + + *range = (!odt); + *begin = vref_begin; + *end = vref_end; + *step = TX_VREF_RANGE_STEP; +} + +static u16 tx_choose_vref(pass_win_data_vref_t vref_info[], u8 vref_num) +{ + u8 vref, worse_bit = 0, win_size_worse_bit = 0; + u16 max_winsum = 0; + u16 final_vref = 0; + + for (vref = 0; vref < vref_num; vref++) + dramc_dbg("TX Vref=%d, minBit %d, minWin=%d, winSum=%d\n", + vref_info[vref].vref_used, + vref_info[vref].worse_bit_idx, + vref_info[vref].worse_bit_winsize, + vref_info[vref].winsum_by_vref); + + for (vref = 0; vref < vref_num; vref++) { + if ((vref_info[vref].worse_bit_winsize > win_size_worse_bit) || + ((vref_info[vref].worse_bit_winsize == win_size_worse_bit) && + (vref_info[vref].winsum_by_vref > max_winsum))) { + win_size_worse_bit = vref_info[vref].worse_bit_winsize; + worse_bit = vref_info[vref].worse_bit_idx; + max_winsum = vref_info[vref].winsum_by_vref; + final_vref = vref_info[vref].vref_used; + } + } + + dramc_dbg("Worse bit %d, Min win %d, Win sum %d, Final Vref %d\n", + worse_bit, win_size_worse_bit, max_winsum, final_vref); + + return final_vref; +} + +static void dramc_tx_window_perbit_cal_find_best_delay(const struct ddr_cali* cali, + tx_cali_type cali_type, bool enable_vref_scan, u16 delay_begin, u16 delay_end, + u16 delay_step, u32 *finish_count, u8 *ui_small_reg_value, + pass_win_data_t win_perbit[DQ_DATA_WIDTH], + pass_win_data_t vref_win_perbit[DQ_DATA_WIDTH]) +{ + u8 chn = cali->chn; + u8 rank = cali->rank; + u8 pi, ui_small, ui_large, oen_ui_small, oen_ui_large; + u8 update_reg_ui; + u8 dq_ui_large[DQS_NUMBER] = {0}, dq_ui_small[DQS_NUMBER] = {0}; + u8 dq_oen_ui_large[DQS_NUMBER] = {0}, dq_oen_ui_small[DQS_NUMBER] = {0}; + u8 dqm_ui_large[DQS_NUMBER] = {0}, dqm_ui_small[DQS_NUMBER] = {0}; + u8 dqm_oen_ui_large[DQS_NUMBER] = {0}, dqm_oen_ui_small[DQS_NUMBER] = {0}; + u8 dq_pi[DQS_NUMBER] = {0}, dqm_pi[DQS_NUMBER] = {0}; + u16 perbit_winsum, vref_winsum; + u32 err_value, fail_bit; + + for (u16 delay = delay_begin; delay < delay_end; delay += delay_step) { + tx_win_transfer_delay_to_uipi(cali, delay, 0, &ui_large, + &ui_small, &pi, &oen_ui_large, &oen_ui_small); + + if (*ui_small_reg_value != ui_small) { + update_reg_ui = 1; + *ui_small_reg_value = ui_small; + } else + update_reg_ui = 0; + + for (u8 byte = 0; byte < DQS_NUMBER; byte++) { + if (update_reg_ui) { + dq_ui_large[byte] = ui_large; + dq_ui_small[byte] = ui_small; + dq_oen_ui_large[byte] = oen_ui_large; + dq_oen_ui_small[byte] = oen_ui_small; + + dqm_ui_large[byte] = ui_large; + dqm_ui_small[byte] = ui_small; + dqm_oen_ui_large[byte] = oen_ui_large; + dqm_oen_ui_small[byte] = oen_ui_small; + } + + dq_pi[byte] = pi; + dqm_pi[byte] = pi; + } + + if (cali_type == TX_DQ_DQS_MOVE_DQ_ONLY || + cali_type == TX_DQ_DQS_MOVE_DQ_DQM) + tx_set_delay_reg_dq(chn, rank, update_reg_ui, dq_ui_large, + dq_oen_ui_large, dq_ui_small, dq_oen_ui_small, dq_pi); + + if (cali_type == TX_DQ_DQS_MOVE_DQM_ONLY || + cali_type == TX_DQ_DQS_MOVE_DQ_DQM) + tx_set_delay_reg_dqm(chn, rank, update_reg_ui, + dqm_ui_large, dqm_oen_ui_large, dqm_ui_small, + dqm_oen_ui_small, dqm_pi); + + err_value = dramc_engine2_run(chn); + + if (!enable_vref_scan && (cali_type != TX_DQ_DQS_MOVE_DQM_ONLY)) + if (err_value != 0) + dramc_dbg("%d |%d %d %d|[0]", delay, ui_large, ui_small, pi); + + for (u8 bit = 0; bit < DQ_DATA_WIDTH; bit++) { + fail_bit = err_value & BIT(bit); + + if (win_perbit[bit].first_pass == PASS_RANGE_NA) { + if (fail_bit == 0) + win_perbit[bit].first_pass = delay; + } else if (win_perbit[bit].last_pass == PASS_RANGE_NA) { + if (fail_bit != 0) + win_perbit[bit].last_pass = delay - delay_step; + else if (delay > (delay_end - delay_step)) + win_perbit[bit].last_pass = delay; + + if (win_perbit[bit].last_pass != PASS_RANGE_NA) { + perbit_winsum = win_perbit[bit].last_pass - + win_perbit[bit].first_pass; + vref_winsum = vref_win_perbit[bit].last_pass - + vref_win_perbit[bit].first_pass; + if (perbit_winsum >= vref_winsum) { + if ((vref_win_perbit[bit].last_pass != + PASS_RANGE_NA) && + vref_winsum > 0) + dramc_dbg("Bit[%d] Bigger window update %d > %d, window broken\n", + bit, perbit_winsum, + vref_winsum); + + if (perbit_winsum > TX_PASS_WIN_CRITERIA) + *finish_count |= BIT(bit); + + vref_win_perbit[bit].first_pass = + win_perbit[bit].first_pass; + vref_win_perbit[bit].last_pass = + win_perbit[bit].last_pass; + } + + win_perbit[bit].first_pass = PASS_RANGE_NA; + win_perbit[bit].last_pass = PASS_RANGE_NA; + } + } + + if (!enable_vref_scan && (cali_type != TX_DQ_DQS_MOVE_DQM_ONLY)) { + if (err_value != 0) { + if (bit % DQS_BIT_NUMBER == 0) + dramc_dbg(" "); + + if (fail_bit == 0) + dramc_dbg("o"); + else + dramc_dbg("x"); + } + } + } + + if (!enable_vref_scan && (cali_type != TX_DQ_DQS_MOVE_DQM_ONLY)) + if (err_value != 0) + dramc_dbg("[MSB]\n"); + + if (*finish_count == 0xffff) + break; + } +} + +static u16 dramc_tx_window_perbit_cal_find_best_vref(const struct ddr_cali* cali, + tx_cali_type cali_type, bool enable_vref_scan, u16 final_range, + u16 vref_begin, u16 vref_end, u16 vref_step, + u16 delay_begin, u16 delay_end, u16 delay_step, u8 *vref_tmp, + u16 center_min[DQS_NUMBER], u16 center_max[DQS_NUMBER], + pass_win_data_t final_win_perbit[DQ_DATA_WIDTH], + pass_win_data_vref_t vref_info[LP4_TX_VREF_DATA_NUM]) +{ + u8 bit, byte, min_bit, min_winsize = 0, bit_tmp; + u8 ui_small_reg_value; + u16 vref_level; + u16 winsum, temp_winsum, max_window_sum = 0; + u32 finish_count; + u32 dummy_rd_bak = 0; + pass_win_data_t win_perbit[DQ_DATA_WIDTH], vref_win_perbit[DQ_DATA_WIDTH]; + + u8 chn = cali->chn; + u8 rank = cali->rank; + + dummy_rd_bak = read32(&ch[chn].ao.dummy_rd); + dramc_engine2_init(chn, rank); + + for (vref_level = vref_begin; vref_level <= vref_end; vref_level += vref_step) { + if (enable_vref_scan) { + dramc_dbg("LP4 TX VrefRange %d, VrefLevel=%d\n", final_range, vref_level); + dramc_tx_set_vref(cali, final_range, vref_level); + } else { + dramc_dbg("TX Vref Scan disable\n"); + } + + finish_count = 0; + temp_winsum = 0; + ui_small_reg_value = 0xff; + + for (bit = 0; bit < DQ_DATA_WIDTH; bit++) { + win_perbit[bit].first_pass = (s16)PASS_RANGE_NA; + win_perbit[bit].last_pass = (s16)PASS_RANGE_NA; + vref_win_perbit[bit].first_pass = (s16)PASS_RANGE_NA; + vref_win_perbit[bit].last_pass = (s16)PASS_RANGE_NA; + } + + dramc_tx_window_perbit_cal_find_best_delay(cali, cali_type,enable_vref_scan, + delay_begin, delay_end, delay_step, &finish_count, &ui_small_reg_value, + win_perbit, vref_win_perbit); + + min_winsize = 0xff; + min_bit = 0xff; + for (bit = 0; bit < DQ_DATA_WIDTH; bit++) { + winsum = vref_win_perbit[bit].last_pass - + vref_win_perbit[bit].first_pass; + if (vref_win_perbit[bit].first_pass == PASS_RANGE_NA) + vref_win_perbit[bit].win_size = 0; + else + vref_win_perbit[bit].win_size = winsum + delay_step; + + if (vref_win_perbit[bit].win_size < min_winsize) { + min_bit = bit; + min_winsize = vref_win_perbit[bit].win_size; + } + + temp_winsum += vref_win_perbit[bit].win_size; + vref_win_perbit[bit].win_center = (vref_win_perbit[bit].first_pass + + vref_win_perbit[bit].last_pass) >> 1; + } + + if (enable_vref_scan) { + if (temp_winsum > max_window_sum) + max_window_sum = temp_winsum; + + vref_info[*vref_tmp].vref_used = vref_level; + vref_info[*vref_tmp].worse_bit_winsize = min_winsize; + vref_info[*vref_tmp].worse_bit_idx = min_bit; + vref_info[*vref_tmp].winsum_by_vref = temp_winsum; + *vref_tmp = *vref_tmp + 1; + } + + if (enable_vref_scan && + (temp_winsum < (max_window_sum * 95 / 100)) && + (min_winsize > TX_PASS_WIN_CRITERIA)) { + dramc_dbg("TX Vref early break, caculate TX vref\n"); + break; + } + } + + dramc_engine2_end(chn, dummy_rd_bak); + if (enable_vref_scan) + return vref_level; + + for (byte = 0; byte < (DQ_DATA_WIDTH / DQS_BIT_NUMBER); byte++) { + center_min[byte] = 0xffff; + center_max[byte] = 0; + + for (bit = 0; bit < DQS_BIT_NUMBER; bit++) { + bit_tmp = byte * DQS_BIT_NUMBER + bit; + memcpy(final_win_perbit, vref_win_perbit, sizeof(vref_win_perbit)); + + if (final_win_perbit[bit_tmp].win_center < center_min[byte]) + center_min[byte] = final_win_perbit[bit_tmp].win_center; + + if (final_win_perbit[bit_tmp].win_center > center_max[byte]) + center_max[byte] = final_win_perbit[bit_tmp].win_center; + } + } + + return vref_level; +} + +void dramc_tx_window_perbit_cal(const struct ddr_cali* cali, + tx_cali_type cali_type, const u8 dqs_final_delay[2][2], bool enable_vref_scan) +{ + u8 chn, rank, fsp, odt; + u8 pi_diff; + u8 bit_tmp, bit, byte, rk; + u8 enable_delaycell = 0; + u8 vref_tmp = 0; + u8 dq_ui_large[DQS_NUMBER], dq_ui_small[DQS_NUMBER], dq_pi[DQS_NUMBER]; + u8 dq_oen_ui_large[DQS_NUMBER], dq_oen_ui_small[DQS_NUMBER]; + u8 dqm_ui_large[DQS_NUMBER] = {0}, dqm_ui_small[DQS_NUMBER] = {0}; + u8 dqm_oen_ui_large[DQS_NUMBER] = {0}, dqm_oen_ui_small[DQS_NUMBER] = {0}; + u8 dqm_pi[DQS_NUMBER] = {0}; + u16 delay, delay_step, dqm_delay; + u16 center_min[DQS_NUMBER] = {0}, center_max[DQS_NUMBER] = {0}; + u16 delaycell_offset[DQ_DATA_WIDTH] = {0}; + u16 final_range = 0, final_vref = 0; + u16 vref_begin, vref_end, vref_step; + u16 delay_begin, delay_end; + u32 frequency; + dram_freq_grp freq_group; + pass_win_data_t final_win_perbit[DQ_DATA_WIDTH]; + pass_win_data_vref_t vref_info[LP4_TX_VREF_DATA_NUM]; + + fsp = get_fsp(cali); + odt = get_odt_state(cali); + bool bypass_cali = !fsp; + const struct sdram_params *params = cali->params; + + chn = cali->chn; + rank = cali->rank; + freq_group = cali->freq_group; + frequency = get_frequency(cali); + + tx_perbit_calibarion_init(chn, rank, cali_type); + + tx_scan_range_PI(cali, cali_type, &delay_begin, &delay_end, dqs_final_delay); + tx_scan_range_vref(cali, enable_vref_scan, &final_range, &vref_begin, &vref_end, &vref_step); + dramc_dbg("delay_begin:%d, delay_end:%d,final_range:%d,vref_begin:%d, vref_end:%d,vref_step:%d\n", + delay_begin, delay_end, final_range, vref_begin, vref_end, vref_step); + + if (freq_group == DDRFREQ_400) + delay_step = 8; + else if (cali_type == TX_DQ_DQS_MOVE_DQ_DQM) + delay_step = 2; + else + delay_step = 1; + + if (bypass_cali) { + for (byte = 0; byte < BYTE_NUM; byte++) { + center_min[byte] = params->tx_center_min[chn][rank][byte]; + center_max[byte] = params->tx_center_max[chn][rank][byte]; + + for (bit = 0; bit < DQS_BIT_NUMBER; bit++) { + bit_tmp = byte * DQS_BIT_NUMBER + bit; + final_win_perbit[bit_tmp].win_center = + params->tx_win_center[chn][rank][bit_tmp]; + } + } + } else { + final_vref = dramc_tx_window_perbit_cal_find_best_vref(cali, cali_type, enable_vref_scan, + final_range, vref_begin, vref_end, vref_step, + delay_begin, delay_end, delay_step, &vref_tmp, + center_min, center_max, final_win_perbit, vref_info); + } + + if (enable_vref_scan) { + if (bypass_cali) + final_vref = params->tx_window_vref[chn][rank]; + else + final_vref = tx_choose_vref(vref_info, vref_tmp); + + dramc_tx_set_vref(cali, final_range, final_vref); + return; + } + + if ((cali_type == TX_DQ_DQS_MOVE_DQ_ONLY) && (freq_group > DDRFREQ_1200)) { + enable_delaycell = 1; + dramc_dbg("[TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =%d/100 ps\n", params->delay_cell_timex100); + } + + for (byte = 0; byte < BYTE_NUM; byte++) { + dramc_dbg(" == TX Byte %d ==\n", byte); + dqm_delay = ((center_min[byte] + center_max[byte]) >> 1); + + if (enable_delaycell == 0) { + delay = dqm_delay; + } else { + delay = center_min[byte]; + + for (bit = 0; bit < DQS_BIT_NUMBER; bit++) { + bit_tmp = byte * DQS_BIT_NUMBER + bit; + pi_diff = final_win_perbit[bit_tmp].win_center - + center_min[byte]; + if (params->delay_cell_timex100 != 0) { + delaycell_offset[bit_tmp] = (pi_diff * 100000000 / + (frequency << 6)) / + params->delay_cell_timex100; + dramc_dbg("delaycell_offset[%d]=%d cells (%d PI)\n", + bit_tmp, delaycell_offset[bit_tmp], pi_diff); + if (delaycell_offset[bit_tmp] > 255) { + dramc_dbg("[WARNING] TX DQ%d delay cell %d >255, adjust to 255 cell\n", + bit, delaycell_offset[bit_tmp]); + delaycell_offset[bit_tmp] = 255; + } + } + } + } + + tx_win_transfer_delay_to_uipi(cali, delay, 1, &dq_ui_large[byte], + &dq_ui_small[byte], &dq_pi[byte], + &dq_oen_ui_large[byte], &dq_oen_ui_small[byte]); + tx_win_transfer_delay_to_uipi(cali, dqm_delay, 1, &dqm_ui_large[byte], + &dqm_ui_small[byte], &dqm_pi[byte], + &dqm_oen_ui_large[byte], &dqm_oen_ui_small[byte]); + + if (cali_type == TX_DQ_DQS_MOVE_DQ_ONLY || cali_type == TX_DQ_DQS_MOVE_DQ_DQM) { + dramc_dbg("Update DQ dly =%d (%d ,%d, %d) DQ OEN =(%d ,%d)\n", + delay, dq_ui_large[byte], dq_ui_small[byte], dq_pi[byte], \ + dq_oen_ui_large[byte], dq_oen_ui_small[byte]); + } + + dramc_dbg("Update DQM dly =%d (%d ,%d, %d) DQM OEN =(%d ,%d)", + dqm_delay, dqm_ui_large[byte], dqm_ui_small[byte], dqm_pi[byte], + dqm_oen_ui_large[byte], dqm_oen_ui_small[byte]); + dramc_dbg("\n"); + } + + for (rk = rank; rk < RANK_MAX; rk++) { + if (cali_type == TX_DQ_DQS_MOVE_DQ_ONLY || cali_type == TX_DQ_DQS_MOVE_DQ_DQM) + tx_set_delay_reg_dq(chn, rk, true, dq_ui_large, dq_oen_ui_large, + dq_ui_small, dq_oen_ui_small, dq_pi); + tx_set_delay_reg_dqm(chn, rk, true, dqm_ui_large, dqm_oen_ui_large, + dqm_ui_small, dqm_oen_ui_small, dqm_pi); + + if (enable_delaycell) { + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].rk[rk].shu_r0_b0_txdly0, + SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0, delaycell_offset[3], + SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0, delaycell_offset[2], + SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0, delaycell_offset[1], + SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0, delaycell_offset[0]); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].rk[rk].shu_r0_b0_txdly1, + SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0, delaycell_offset[7], + SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0, delaycell_offset[6], + SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0, delaycell_offset[5], + SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0, delaycell_offset[4]); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].rk[rk].shu_r0_b0_txdly0, + SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1, delaycell_offset[11], + SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1, delaycell_offset[10], + SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1, delaycell_offset[9], + SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1, delaycell_offset[8]); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].rk[rk].shu_r0_b0_txdly1, + SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1, delaycell_offset[15], + SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1, delaycell_offset[14], + SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1, delaycell_offset[13], + SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1, delaycell_offset[12]); + } + + update_tx_tracking(chn, rk, cali_type, dq_pi, dqm_pi); + } +} diff --git a/src/soc/mediatek/mt8192/dramc_pi_main.c b/src/soc/mediatek/mt8192/dramc_pi_main.c index 41d85a2..f724e54 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_main.c +++ b/src/soc/mediatek/mt8192/dramc_pi_main.c @@ -16,6 +16,26 @@ shift_dq_ui(cali, cali->rank, ui_move); } +static void switch_write_dbi_settings(const struct ddr_cali *cali, dbi_mode dbi_state) +{ + s8 tx_shift; + u8 chn, rank; + struct mr_values *mr_value = cali->mr_value; + u8 mr03 = mr_value->mr03[get_fsp(cali)]; + + chn = cali->chn; + rank = cali->rank; + + tx_shift = dbi_state ? -1 : 1; + dramc_write_shift_mck_write_DBI(cali, tx_shift); + + mr03 = (mr03 & ~(0x1 << 7)) | (dbi_state << 7); + dramc_mode_reg_write_by_rank(chn, rank, 3, mr03); + mr_value->mr03[get_fsp(cali)] = mr03; + + dramc_write_dbi_onoff(dbi_state); +} + static void dramc_ac_timing_optimize(const struct ddr_cali* cali) { u8 rf_group = 0, cab_id = 0; @@ -250,6 +270,23 @@ dramc_rx_dqs_gating_cal(cali, &txdly_min, &txdly_max); dramc_rx_window_perbit_cal(cali, RX_WIN_RD_DQC); + dramc_tx_window_perbit_cal(cali, TX_DQ_DQS_MOVE_DQ_DQM, + dqs_final_delay, false); + if (get_vref_cali(cali) == VREF_CALI_ON) + dramc_tx_window_perbit_cal(cali, TX_DQ_DQS_MOVE_DQ_ONLY, + dqs_final_delay, true); + + dramc_tx_window_perbit_cal(cali, TX_DQ_DQS_MOVE_DQ_ONLY, + dqs_final_delay, false); + + if (get_write_dbi(cali) == DBI_ON) { + dramc_dbg("K DQM with DBI_ON\n"); + switch_write_dbi_settings(cali, DBI_ON); + dramc_tx_window_perbit_cal(cali, TX_DQ_DQS_MOVE_DQM_ONLY, + dqs_final_delay, false); + switch_write_dbi_settings(cali, DBI_OFF); + } + dramc_rx_window_perbit_cal(cali, RX_WIN_TEST_ENG); } dramc_rx_dqs_gating_post_process(cali, txdly_min, txdly_max); -- To view, visit https://review.coreboot.org/c/coreboot/+/44720 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica11573c1e0b657be0e8ddcbf81a9e3f2399e258 Gerrit-Change-Number: 44720 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

22 hours, 16 minutes

Change in coreboot[master]: soc/mediatek/mt8192: Add dramc ac timing setting

by CK HU (Code Review)

Hello Duan huayang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44713 to review the following change. Change subject: soc/mediatek/mt8192: Add dramc ac timing setting ...................................................................... soc/mediatek/mt8192: Add dramc ac timing setting Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> Change-Id: I10e704868e4cd36a938a669879bb1a8632e73e1a --- M src/soc/mediatek/mt8192/dramc_pi_basic_api.c M src/soc/mediatek/mt8192/dramc_pi_main.c A src/soc/mediatek/mt8192/include/soc/dramc_ac_timing.h 3 files changed, 1,320 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/44713/1 diff --git a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c index 31e8d0e..1a5f242 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c @@ -3,6 +3,7 @@ #include <soc/gpio.h> #include <soc/dramc_pi_api.h> #include <soc/dramc_register.h> +#include <soc/dramc_ac_timing.h> #include <string.h> #include <timer.h> @@ -4030,6 +4031,206 @@ dramc_set_broadcast(bc_bak); } +static void ddr_update_ac_timing(const struct ddr_cali *cali) +{ + u8 table_idx; + struct ac_timing ac_tim; + dram_freq_grp freq_group = cali->freq_group; + + u8 rank_inctl = 0, tx_dly = 0, datlat_dsel = 0; + u8 rodt_tracking_mck = 0, root = 0, tx_rank_inctl = 0; + u8 tref_bw = 0, tfaw_05t=0, trrd_05t=0; + u16 xrtwtw = 0, xtrtrt = 0, xrtw2r = 0, xrtr2w = 0, tfaw = 0; + u16 trtw=0, trtw_05t=0, tmrr2w=0, trrd=0; + u16 phs_inctl = 0; + u32 rank_inctl_root; + + for (table_idx = 0; table_idx < AC_TIMING_NUMBER; table_idx++) + if ((ac_timing_tbl[table_idx].freq_group == freq_group) && + (ac_timing_tbl[table_idx].div_mode == get_div_mode(cali)) && + (ac_timing_tbl[table_idx].cbt_mode == get_cbt_mode(cali))) { + dramc_dbg("match AC timing table %d\n", table_idx); + break; + } + + if (table_idx == AC_TIMING_NUMBER) { + dramc_dbg("Error, no match AC timing table\n"); + return; + } + memcpy(&ac_tim, &ac_timing_tbl[table_idx], sizeof(struct ac_timing)); + + trtw = ac_tim.trtw_odt_on; + trtw_05t = ac_tim.trtw_odt_on_05T; + xrtw2r = ac_tim.xrtw2r_odt_on; + xrtr2w = ac_tim.xrtr2w_odt_on; + tfaw = ac_tim.tfaw_4266; + tfaw_05t = ac_tim.tfaw_4266_05T; + trrd = ac_tim.trrd_4266; + trrd_05t = ac_tim.trrd_4266_05T; + xtrtrt = ac_tim.xrtr2r_new_mode; + xrtwtw = ac_tim.xrtw2w_new_mode; + tmrr2w = ac_tim.tmrr2w_odt_on; + rodt_tracking_mck = 0; + trtw = trtw - rodt_tracking_mck; + xrtr2w = xrtr2w - rodt_tracking_mck; + + if (READ32_BITFIELD(&ch[0].phy_ao.shu_misc_rx_pipe_ctrl, + SHU_MISC_RX_PIPE_CTRL_RX_PIPE_BYPASS_EN)) + datlat_dsel = ac_tim.datlat; + else + datlat_dsel = ac_tim.datlat - 1; + + if (ac_tim.dqsinctl >= 2) { + rank_inctl_root = ac_tim.dqsinctl - 2; + } else { + dramc_info("rank_inctl_root <2, need check\n"); + rank_inctl_root = 0; + } + phs_inctl = (ac_tim.dqsinctl == 0) ? 0 : (ac_tim.dqsinctl - 1); + + if (freq_group <= DDRFREQ_800) { + if (get_div_mode(cali) == DIV4_MODE) { + tx_rank_inctl = 1; + tx_dly = 2; + } else { + tx_rank_inctl = 0; + tx_dly = 1; + } + } else { + tx_rank_inctl = 1; + tx_dly = 2; + } + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].ao.shu_actim1, + SHU_ACTIM1_TRAS, ac_tim.tras, + SHU_ACTIM1_TRP, ac_tim.trp, + SHU_ACTIM1_TRPAB, ac_tim.trpab, + SHU_ACTIM1_TMRWCKEL, ac_tim.tmrwckel, + SHU_ACTIM1_TRC, ac_tim.trc); + SET32_BITFIELDS(&ch[chn].ao.shu_actim3, + SHU_ACTIM3_TRFC, ac_tim.trfc, + SHU_ACTIM3_TR2MRR, ac_tim.tr2mrr, + SHU_ACTIM3_TRFCPB, ac_tim.trfcpb); + SET32_BITFIELDS(&ch[chn].ao.shu_actim2, + SHU_ACTIM2_TXP, ac_tim.txp, + SHU_ACTIM2_TMRRI, ac_tim.tmrri, + SHU_ACTIM2_TFAW, tfaw, + SHU_ACTIM2_TR2W, trtw, + SHU_ACTIM2_TRTP, ac_tim.trtp); + SET32_BITFIELDS(&ch[chn].ao.shu_actim0, + SHU_ACTIM0_TRCD, ac_tim.trcd, + SHU_ACTIM0_TWR, ac_tim.twr, + SHU_ACTIM0_TRRD, trrd); + SET32_BITFIELDS(&ch[chn].ao.shu_actim5, + SHU_ACTIM5_TPBR2PBR, ac_tim.tpbr2pbr, + SHU_ACTIM5_TWTPD, ac_tim.twtpd, + SHU_ACTIM5_TPBR2ACT, ac_tim.tpbr2act); + SET32_BITFIELDS(&ch[chn].ao.shu_actim6, + SHU_ACTIM6_TR2MRW, ac_tim.tr2mrw, + SHU_ACTIM6_TW2MRW, ac_tim.tw2mrw, + SHU_ACTIM6_TMRD, ac_tim.tmrd, + SHU_ACTIM6_TZQLAT2, ac_tim.zqlat2, + SHU_ACTIM6_TMRW, ac_tim.tmrw); + SET32_BITFIELDS(&ch[chn].ao.shu_actim4, + SHU_ACTIM4_TMRR2MRW, ac_tim.tmrr2mrw, + SHU_ACTIM4_TMRR2W, tmrr2w, + SHU_ACTIM4_TZQCS, ac_tim.tzqcs, + SHU_ACTIM4_TXREFCNT, ac_tim.txrefcnt); + SET32_BITFIELDS(&ch[chn].ao.shu_ckectrl, SHU_CKECTRL_TCKEPRD, ac_tim.ckeprd); + SET32_BITFIELDS(&ch[chn].ao.shu_actim_xrt, + SHU_ACTIM_XRT_XRTW2W, xrtwtw, + SHU_ACTIM_XRT_XRTW2R, xrtw2r, + SHU_ACTIM_XRT_XRTR2W, xrtr2w, + SHU_ACTIM_XRT_XRTR2R, xtrtrt); + SET32_BITFIELDS(&ch[chn].ao.shu_hwset_vrcg, + SHU_HWSET_VRCG_VRCGDIS_PRDCNT, ac_tim.vrcgdis_prdcnt); + SET32_BITFIELDS(&ch[chn].ao.shu_hwset_mr2, + SHU_HWSET_MR2_HWSET_MR2_OP, ac_tim.hwset_mr2_op); + SET32_BITFIELDS(&ch[chn].ao.shu_hwset_mr13, + SHU_HWSET_MR13_HWSET_MR13_OP, ac_tim.hwset_mr13_op); + SET32_BITFIELDS(&ch[chn].ao.shu_ac_time_05t, + SHU_AC_TIME_05T_TWTR_M05T, ac_tim.twtr_05T, + SHU_AC_TIME_05T_TR2W_05T, trtw_05t, + SHU_AC_TIME_05T_TWTPD_M05T, ac_tim.twtpd_05T, + SHU_AC_TIME_05T_TFAW_05T, tfaw_05t, + SHU_AC_TIME_05T_TRRD_05T, trrd_05t, + SHU_AC_TIME_05T_TWR_M05T, ac_tim.twr_05T, + SHU_AC_TIME_05T_TRAS_05T, ac_tim.tras_05T, + SHU_AC_TIME_05T_TRPAB_05T, ac_tim.trpab_05T, + SHU_AC_TIME_05T_TRP_05T, ac_tim.trp_05T, + SHU_AC_TIME_05T_TRCD_05T, ac_tim.trcd_05T, + SHU_AC_TIME_05T_TRTP_05T, ac_tim.trtp_05T, + SHU_AC_TIME_05T_TXP_05T, ac_tim.txp_05T); + SET32_BITFIELDS(&ch[chn].ao.shu_ac_time_05t, + SHU_AC_TIME_05T_TRFC_05T, ac_tim.trfc_05T, + SHU_AC_TIME_05T_TRFCPB_05T, ac_tim.trfcpb_05T, + SHU_AC_TIME_05T_TPBR2PBR_05T, ac_tim.tpbr2pbr_05T, + SHU_AC_TIME_05T_TPBR2ACT_05T, ac_tim.tpbr2act_05T, + SHU_AC_TIME_05T_TR2MRW_05T, ac_tim.tr2mrw_05T, + SHU_AC_TIME_05T_TW2MRW_05T, ac_tim.tw2mrw_05T, + SHU_AC_TIME_05T_TMRR2MRW_05T, ac_tim.tmrr2mrw_05T, + SHU_AC_TIME_05T_TMRW_05T, ac_tim.tmrw_05T, + SHU_AC_TIME_05T_TMRD_05T, ac_tim.tmrd_05T, + SHU_AC_TIME_05T_TMRWCKEL_05T, ac_tim.tmrwckel_05T, + SHU_AC_TIME_05T_TMRRI_05T, ac_tim.tmrri_05T, + SHU_AC_TIME_05T_TRC_05T, ac_tim.trc_05T); + SET32_BITFIELDS(&ch[chn].ao.shu_actim0, SHU_ACTIM0_TWTR, ac_tim.twtr); + SET32_BITFIELDS(&ch[chn].ao.shu_ckectrl, + SHU_CKECTRL_TPDE, ac_tim.tpde, + SHU_CKECTRL_TPDX, ac_tim.tpdx, + SHU_CKECTRL_TPDE_05T, ac_tim.tpde_05T, + SHU_CKECTRL_TPDX_05T, ac_tim.tpdx_05T); + SET32_BITFIELDS(&ch[chn].ao.shu_actim5, SHU_ACTIM5_TR2PD, ac_tim.trtpd); + SET32_BITFIELDS(&ch[chn].ao.shu_ac_time_05t, + SHU_AC_TIME_05T_TR2PD_05T, ac_tim.trtpd_05T); + SET32_BITFIELDS(&ch[chn].ao.shu_ac_derating0, + SHU_AC_DERATING0_TRCD_DERATE, ac_tim.trcd_derate, + SHU_AC_DERATING0_TRRD_DERATE, ac_tim.trrd_derate); + SET32_BITFIELDS(&ch[chn].ao.shu_ac_derating1, + SHU_AC_DERATING1_TRC_DERATE, ac_tim.trc_derate, + SHU_AC_DERATING1_TRAS_DERATE, ac_tim.tras_derate, + SHU_AC_DERATING1_TRP_DERATE, ac_tim.trp_derate, + SHU_AC_DERATING1_TRPAB_DERATE, ac_tim.trpab_derate); + SET32_BITFIELDS(&ch[chn].ao.shu_ac_derating_05t, + SHU_AC_DERATING_05T_TRRD_05T_DERATE, ac_tim.trrd_derate_05T, + SHU_AC_DERATING_05T_TRAS_05T_DERATE, ac_tim.tras_derate_05T, + SHU_AC_DERATING_05T_TRPAB_05T_DERATE, ac_tim.trpab_derate_05T, + SHU_AC_DERATING_05T_TRP_05T_DERATE, ac_tim.trp_derate_05T, + SHU_AC_DERATING_05T_TRCD_05T_DERATE, ac_tim.trcd_derate_05T, + SHU_AC_DERATING_05T_TRC_05T_DERATE, ac_tim.trc_derate_05T); + SET32_BITFIELDS(&ch[chn].ao.refctrl3, REFCTRL3_REF_DERATING_EN, 0xc0); + SET32_BITFIELDS(&ch[chn].ao.shu_ac_derating0, + SHU_AC_DERATING0_ACDERATEEN, 0x1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rk[0].misc_shu_rk_dqsctl, + MISC_SHU_RK_DQSCTL_DQSINCTL, ac_tim.dqsinctl); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rk[1].misc_shu_rk_dqsctl, + MISC_SHU_RK_DQSCTL_DQSINCTL, ac_tim.dqsinctl); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_odtctrl, + MISC_SHU_ODTCTRL_RODT_LAT, ac_tim.dqsinctl); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_rankctl, + MISC_SHU_RANKCTL_RANKINCTL_PHY, ac_tim.dqsinctl, + MISC_SHU_RANKCTL_RANKINCTL_ROOT1, rank_inctl_root, + MISC_SHU_RANKCTL_RANKINCTL, rank_inctl_root); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_misc_rank_sel_stb, + SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL, phs_inctl); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_rdat, + MISC_SHU_RDAT_DATLAT, ac_tim.datlat, + MISC_SHU_RDAT_DATLAT_DSEL, datlat_dsel, + MISC_SHU_RDAT_DATLAT_DSEL_PHY, datlat_dsel); + SET32_BITFIELDS(&ch[chn].ao.shu_actiming_conf, + SHU_ACTIMING_CONF_REFBW_FR, tref_bw); + rank_inctl = READ32_BITFIELD(&ch[0].phy_ao.misc_shu_rankctl, + MISC_SHU_RANKCTL_RANKINCTL); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_rankctl, + MISC_SHU_RANKCTL_RANKINCTL_RXDLY, rank_inctl); + SET32_BITFIELDS(&ch[chn].ao.shu_tx_rankctl, + SHU_TX_RANKCTL_TXRANKINCTL_ROOT, root, + SHU_TX_RANKCTL_TXRANKINCTL, tx_rank_inctl, + SHU_TX_RANKCTL_TXRANKINCTL_TXDLY, tx_dly); + } +} + static void set_cke2rank_independent(void) { for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { @@ -4121,6 +4322,8 @@ dramc_8_phase_cal(cali); dramc_duty_calibration(cali->params); dramc_mode_reg_init(cali); + + ddr_update_ac_timing(cali); } static void dramc_before_calibration(const struct ddr_cali *cali) diff --git a/src/soc/mediatek/mt8192/dramc_pi_main.c b/src/soc/mediatek/mt8192/dramc_pi_main.c index cf199dc..5ca7bce 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_main.c +++ b/src/soc/mediatek/mt8192/dramc_pi_main.c @@ -6,6 +6,151 @@ #include <soc/pll_common.h> #include <soc/mt6359p.h> +static void dramc_ac_timing_optimize(const struct ddr_cali* cali) +{ + u8 rf_group = 0, cab_id = 0; + u8 trfc, trfc_05t, trfc_pb, trfrc_pb05t, tx_ref_cnt; + + enum { + tRFCAB_130, + tRFCAB_180, + tRFCAB_280, + tRFCAB_380, + tRFCAB_NUM + }; + enum { + GRP_DDR800_DIV4_ACTIM, + GRP_DDR1200_ACTIM, + GRP_DDR1600_ACTIM, + GRP_DDR1866_ACTIM, + GRP_DDR2400_ACTIM, + GRP_DDR3200_ACTIM, + GRP_DDR4266_ACTIM, + GRP_ACTIM_NUM + }; + struct optimize_ac_time { + u8 trfc; + u8 trfc_05t; + u8 trfc_pb; + u8 trfrc_pb05t; + u16 tx_ref_cnt; + }; + + u8 density = cali->density; + dram_freq_grp freq_group = get_freq_group(cali); + + struct optimize_ac_time *ptRFCab_Opt; + struct optimize_ac_time tRFCab_Opt [GRP_ACTIM_NUM][tRFCAB_NUM] = { + [GRP_DDR800_DIV4_ACTIM] = { + {.trfc = 14, .trfc_05t = 0, .trfc_pb = 0, .trfrc_pb05t = 0, .tx_ref_cnt = 28}, + {.trfc = 24, .trfc_05t = 0, .trfc_pb = 6, .trfrc_pb05t = 0, .tx_ref_cnt = 38}, + {.trfc = 44, .trfc_05t = 0, .trfc_pb = 16, .trfrc_pb05t = 0, .tx_ref_cnt = 58}, + {.trfc = 64, .trfc_05t = 0, .trfc_pb = 26, .trfrc_pb05t = 0, .tx_ref_cnt = 78} + }, + [GRP_DDR1200_ACTIM] = { + {.trfc = 8, .trfc_05t = 0, .trfc_pb = 0, .trfrc_pb05t = 0, .tx_ref_cnt = 21}, + {.trfc = 15, .trfc_05t = 1, .trfc_pb = 2, .trfrc_pb05t = 0, .tx_ref_cnt = 29}, + {.trfc = 30, .trfc_05t = 1, .trfc_pb = 9, .trfrc_pb05t = 1, .tx_ref_cnt = 44}, + {.trfc = 45, .trfc_05t = 1, .trfc_pb = 17, .trfrc_pb05t = 0, .tx_ref_cnt = 59} + }, + [GRP_DDR1600_ACTIM] = { + {.trfc = 14, .trfc_05t = 0, .trfc_pb = 0, .trfrc_pb05t = 0, .tx_ref_cnt = 28}, + {.trfc = 24, .trfc_05t = 0, .trfc_pb = 6, .trfrc_pb05t = 0, .tx_ref_cnt = 38}, + {.trfc = 44, .trfc_05t = 0, .trfc_pb = 16, .trfrc_pb05t = 0, .tx_ref_cnt = 58}, + {.trfc = 64, .trfc_05t = 0, .trfc_pb = 26, .trfrc_pb05t = 0, .tx_ref_cnt = 78} + }, + [GRP_DDR1866_ACTIM] = { + {.trfc = 18, .trfc_05t = 1, .trfc_pb = 2, .trfrc_pb05t = 0, .tx_ref_cnt = 33}, + {.trfc = 30, .trfc_05t = 0, .trfc_pb = 9, .trfrc_pb05t = 0, .tx_ref_cnt = 44}, + {.trfc = 53, .trfc_05t = 1, .trfc_pb = 21, .trfrc_pb05t = 0, .tx_ref_cnt = 68}, + {.trfc = 77, .trfc_05t = 0, .trfc_pb = 32, .trfrc_pb05t = 1, .tx_ref_cnt = 91} + }, + [GRP_DDR2400_ACTIM] = { + {.trfc = 27, .trfc_05t = 1, .trfc_pb = 6, .trfrc_pb05t = 1, .tx_ref_cnt = 42}, + {.trfc = 42, .trfc_05t = 1, .trfc_pb = 15, .trfrc_pb05t = 1, .tx_ref_cnt = 57}, + {.trfc = 72, .trfc_05t = 1, .trfc_pb = 30, .trfrc_pb05t = 1, .tx_ref_cnt = 87}, + {.trfc = 102, .trfc_05t = 1, .trfc_pb = 45, .trfrc_pb05t = 1, .tx_ref_cnt = 117} + }, + [GRP_DDR3200_ACTIM] = { + {.trfc = 40, .trfc_05t = 0, .trfc_pb = 12, .trfrc_pb05t = 0, .tx_ref_cnt = 55}, + {.trfc = 60, .trfc_05t = 0, .trfc_pb = 24, .trfrc_pb05t = 0, .tx_ref_cnt = 75}, + {.trfc = 100, .trfc_05t = 0, .trfc_pb = 44, .trfrc_pb05t = 0, .tx_ref_cnt = 115}, + {.trfc = 140, .trfc_05t = 0, .trfc_pb = 64, .trfrc_pb05t = 0, .tx_ref_cnt = 155} + }, + [GRP_DDR4266_ACTIM] = { + {.trfc = 57, .trfc_05t = 1, .trfc_pb = 20, .trfrc_pb05t = 0, .tx_ref_cnt = 74}, + {.trfc = 84, .trfc_05t = 0, .trfc_pb = 36, .trfrc_pb05t = 0, .tx_ref_cnt = 100}, + {.trfc = 137, .trfc_05t = 1, .trfc_pb = 63, .trfrc_pb05t = 0, .tx_ref_cnt = 154}, + {.trfc = 191, .trfc_05t = 0, .trfc_pb = 89, .trfrc_pb05t = 1, .tx_ref_cnt = 207} + } + }; + + switch (density) { + case 0x0: + rf_group = tRFCAB_130; + break; + case 0x1: + case 0x2: + rf_group = tRFCAB_180; + break; + case 0x3: + case 0x4: + rf_group = tRFCAB_280; + break; + case 0x5: + case 0x6: + rf_group = tRFCAB_380; + break; + default: + die("Invalid DDR density %u\n", density); + return; + } + + switch (freq_group) { + case DDRFREQ_400: + cab_id = GRP_DDR800_DIV4_ACTIM; + break; + case DDRFREQ_600: + cab_id = GRP_DDR1200_ACTIM; + break; + case DDRFREQ_800: + cab_id = GRP_DDR1600_ACTIM; + break; + case DDRFREQ_933: + cab_id = GRP_DDR1866_ACTIM; + break; + case DDRFREQ_1200: + cab_id = GRP_DDR2400_ACTIM; + break; + case DDRFREQ_1600: + cab_id = GRP_DDR3200_ACTIM; + break; + case DDRFREQ_2133: + cab_id = GRP_DDR4266_ACTIM; + break; + default: + die("Invalid DDR frequency group %u\n", freq_group); + return; + } + + ptRFCab_Opt = &tRFCab_Opt[cab_id][0]; + trfc = ptRFCab_Opt[rf_group].trfc; + trfc_05t = ptRFCab_Opt[rf_group].trfc_05t; + trfc_pb = ptRFCab_Opt[rf_group].trfc_pb; + trfrc_pb05t = ptRFCab_Opt[rf_group].trfrc_pb05t; + tx_ref_cnt = ptRFCab_Opt[rf_group].tx_ref_cnt; + + for (size_t chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].ao.shu_actim3, SHU_ACTIM3_TRFC, trfc); + SET32_BITFIELDS(&ch[chn].ao.shu_ac_time_05t, SHU_AC_TIME_05T_TRFC_05T, trfc_05t); + SET32_BITFIELDS(&ch[chn].ao.shu_actim4, SHU_ACTIM4_TXREFCNT, tx_ref_cnt); + SET32_BITFIELDS(&ch[chn].ao.shu_actim3, SHU_ACTIM3_TRFCPB, trfc_pb); + SET32_BITFIELDS(&ch[chn].ao.shu_ac_time_05t, SHU_AC_TIME_05T_TRFCPB_05T, trfrc_pb05t); + dramc_dbg("Density (MR8 OP[5:2]) %d, TRFC %d, TRFC_05T %d, TXREFCNT %d, TRFCpb %d, TRFCpb_05T %d\n", + density, trfc, trfc_05t, tx_ref_cnt, trfc_pb, trfrc_pb05t); + } +} + static void set_vcore_voltage_for_each_freq(const struct ddr_cali *cali) { u32 vcore = get_vcore_value(cali); @@ -144,6 +289,8 @@ if (first_freq_k) get_dram_info_after_cal(&cali); + dramc_ac_timing_optimize(&cali); + first_freq_k= false; } } diff --git a/src/soc/mediatek/mt8192/include/soc/dramc_ac_timing.h b/src/soc/mediatek/mt8192/include/soc/dramc_ac_timing.h new file mode 100644 index 0000000..717d247 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/dramc_ac_timing.h @@ -0,0 +1,970 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8192_DRAMC_AC_TIMING_H__ +#define __SOC_MEDIATEK_MT8192_DRAMC_AC_TIMING_H__ + +#include <stdint.h> +#include <sys/types.h> +#include <soc/dramc_common_mt8192.h> + +/* Normal Mode and Byte Mode */ +#define AC_TIMING_NUMBER (DDRFREQ_MAX * 2) + +struct ac_timing { + u8 cbt_mode, read_dbi; + u8 div_mode; + u16 freq_group; + u16 read_lat, write_lat; + u16 dqsinctl, datlat; + u16 tras; + u16 trp; + u16 trpab; + u16 trc; + u16 trfc; + u16 trfcpb; + u16 txp; + u16 trtp; + u16 trcd; + u16 twr; + u16 twtr; + u16 tpbr2pbr; + u16 tpbr2act; + u16 tr2mrw; + u16 tw2mrw; + u16 tmrr2mrw; + u16 tmrw; + u16 tmrd; + u16 tmrwckel; + u16 tpde; + u16 tpdx; + u16 tmrri; + u16 trrd; + u16 trrd_4266; + u16 tfaw; + u16 tfaw_4266; + u16 trtw_odt_off; + u16 trtw_odt_on; + u16 txrefcnt; + u16 tzqcs; + u16 xrtw2w_new_mode; + u16 xrtw2w_old_mode; + u16 xrtw2r_odt_on; + u16 xrtw2r_odt_off; + u16 xrtr2w_odt_on; + u16 xrtr2w_odt_off; + u16 xrtr2r_new_mode; + u16 xrtr2r_old_mode; + u16 tr2mrr; + u16 vrcgdis_prdcnt; + u16 hwset_mr2_op; + u16 hwset_mr13_op; + u16 hwset_vrcg_op; + u16 trcd_derate; + u16 trc_derate; + u16 tras_derate; + u16 trpab_derate; + u16 trp_derate; + u16 trrd_derate; + u16 trtpd; + u16 twtpd; + u16 tmrr2w_odt_off; + u16 tmrr2w_odt_on; + u16 ckeprd; + u16 ckelckcnt; + u16 zqlat2; + u16 tras_05T; + u16 trp_05T; + u16 trpab_05T; + u16 trc_05T; + u16 trfc_05T; + u16 trfcpb_05T; + u16 txp_05T; + u16 trtp_05T; + u16 trcd_05T; + u16 twr_05T; + u16 twtr_05T; + u16 tpbr2pbr_05T; + u16 tpbr2act_05T; + u16 tr2mrw_05T; + u16 tw2mrw_05T; + u16 tmrr2mrw_05T; + u16 tmrw_05T; + u16 tmrd_05T; + u16 tmrwckel_05T; + u16 tpde_05T; + u16 tpdx_05T; + u16 tmrri_05T; + u16 trrd_05T; + u16 trrd_4266_05T; + u16 tfaw_05T; + u16 tfaw_4266_05T; + u16 trtw_odt_off_05T; + u16 trtw_odt_on_05T; + u16 trcd_derate_05T; + u16 trc_derate_05T; + u16 tras_derate_05T; + u16 trpab_derate_05T; + u16 trp_derate_05T; + u16 trrd_derate_05T; + u16 trtpd_05T; + u16 twtpd_05T; +}; + +/* Normal Mode and Byte Mode for each frequency */ +static const struct ac_timing ac_timing_tbl[AC_TIMING_NUMBER] = { + { + .freq_group = DDRFREQ_2133, .cbt_mode = CBT_NORMAL_MODE, .read_dbi = 0, + .read_lat = 36, .write_lat = 18, .div_mode = DIV8_MODE, + .tras = 14, .tras_05T = 0, + .trp = 8, .trp_05T = 1, + .trpab = 10, .trpab_05T = 0, + .trc = 23, .trc_05T = 0, + .trfc = 137, .trfc_05T = 1, + .trfcpb = 63, .trfcpb_05T = 0, + .txp = 1, .txp_05T = 0, + .trtp = 2, .trtp_05T = 1, + .trcd = 10, .trcd_05T = 0, + .twr = 15, .twr_05T = 0, + .twtr = 10, .twtr_05T = 1, + .tpbr2pbr = 41, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 17, .tr2mrw_05T = 0, + .tw2mrw = 11, .tw2mrw_05T = 0, + .tmrr2mrw = 14, .tmrr2mrw_05T = 0, + .tmrw = 6, .tmrw_05T = 0, + .tmrd = 8, .tmrd_05T = 0, + .tmrwckel = 9, .tmrwckel_05T = 0, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 14, .tmrri_05T = 0, + .trrd = 4, .trrd_05T = 1, + .trrd_4266 = 3, .trrd_4266_05T = 0, + .tfaw = 13, .tfaw_05T = 1, + .tfaw_4266 = 8, .tfaw_4266_05T = 0, + .trtw_odt_off = 6, .trtw_odt_off_05T = 0, + .trtw_odt_on = 8, .trtw_odt_on_05T = 0, + .txrefcnt = 154, + .tzqcs = 46, + .xrtw2w_new_mode = 5, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 1, + .xrtw2r_odt_off = 1, + .xrtr2w_odt_on = 7, + .xrtr2w_odt_off = 7, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 7, + .tr2mrr = 4, + .vrcgdis_prdcnt = 54, + .hwset_mr2_op = 63, + .hwset_mr13_op = 216, + .hwset_vrcg_op = 208, + .trcd_derate = 11, .trcd_derate_05T = 0, + .trc_derate = 26, .trc_derate_05T = 0, + .tras_derate = 15, .tras_derate_05T = 0, + .trpab_derate = 11, .trpab_derate_05T = 0, + .trp_derate = 9, .trp_derate_05T = 1, + .trrd_derate = 5, .trrd_derate_05T = 1, + .trtpd = 14, .trtpd_05T = 1, + .twtpd = 18, .twtpd_05T = 0, + .tmrr2w_odt_off = 10, + .tmrr2w_odt_on = 12, + .ckeprd = 3, + .ckelckcnt = 3, + .zqlat2 = 16, + .dqsinctl = 7, .datlat = 18 + }, + { + .freq_group = DDRFREQ_2133, .cbt_mode = CBT_BYTE_MODE1, .read_dbi = 0, + .read_lat = 40, .write_lat = 18, .div_mode = DIV8_MODE, + .tras = 14, .tras_05T = 0, + .trp = 8, .trp_05T = 1, + .trpab = 10, .trpab_05T = 0, + .trc = 23, .trc_05T = 0, + .trfc = 137, .trfc_05T = 1, + .trfcpb = 63, .trfcpb_05T = 0, + .txp = 1, .txp_05T = 0, + .trtp = 2, .trtp_05T = 1, + .trcd = 10, .trcd_05T = 0, + .twr = 16, .twr_05T = 0, + .twtr = 11, .twtr_05T = 1, + .tpbr2pbr = 41, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 18, .tr2mrw_05T = 0, + .tw2mrw = 11, .tw2mrw_05T = 0, + .tmrr2mrw = 15, .tmrr2mrw_05T = 0, + .tmrw = 6, .tmrw_05T = 0, + .tmrd = 8, .tmrd_05T = 0, + .tmrwckel = 9, .tmrwckel_05T = 0, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 14, .tmrri_05T = 0, + .trrd = 4, .trrd_05T = 1, + .trrd_4266 = 3, .trrd_4266_05T = 0, + .tfaw = 13, .tfaw_05T = 1, + .tfaw_4266 = 8, .tfaw_4266_05T = 0, + .trtw_odt_off = 7, .trtw_odt_off_05T = 0, + .trtw_odt_on = 9, .trtw_odt_on_05T = 0, + .txrefcnt = 154, + .tzqcs = 46, + .xrtw2w_new_mode = 5, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 1, + .xrtw2r_odt_off = 1, + .xrtr2w_odt_on = 8, + .xrtr2w_odt_off = 8, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 7, + .tr2mrr = 4, + .vrcgdis_prdcnt = 54, + .hwset_mr2_op = 63, + .hwset_mr13_op = 216, + .hwset_vrcg_op = 208, + .trcd_derate = 11, .trcd_derate_05T = 0, + .trc_derate = 26, .trc_derate_05T = 0, + .tras_derate = 15, .tras_derate_05T = 0, + .trpab_derate = 11, .trpab_derate_05T = 0, + .trp_derate = 9, .trp_derate_05T = 1, + .trrd_derate = 5, .trrd_derate_05T = 1, + .trtpd = 15, .trtpd_05T = 1, + .twtpd = 19, .twtpd_05T = 0, + .tmrr2w_odt_off = 11, + .tmrr2w_odt_on = 13, + .ckeprd = 3, + .ckelckcnt = 3, + .zqlat2 = 16, + .dqsinctl = 7, .datlat = 18 + }, + { + .freq_group = DDRFREQ_1600, .cbt_mode = CBT_NORMAL_MODE, .read_dbi = 0, + .read_lat = 28, .write_lat = 14, .div_mode = DIV8_MODE, + .tras = 8, .tras_05T = 1, + .trp = 6, .trp_05T = 0, + .trpab = 7, .trpab_05T = 0, + .trc = 15, .trc_05T = 0, + .trfc = 100, .trfc_05T = 0, + .trfcpb = 44, .trfcpb_05T = 0, + .txp = 0, .txp_05T = 0, + .trtp = 1, .trtp_05T = 1, + .trcd = 7, .trcd_05T = 1, + .twr = 12, .twr_05T = 1, + .twtr = 7, .twtr_05T = 0, + .tpbr2pbr = 29, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 13, .tr2mrw_05T = 1, + .tw2mrw = 9, .tw2mrw_05T = 0, + .tmrr2mrw = 11, .tmrr2mrw_05T = 1, + .tmrw = 4, .tmrw_05T = 1, + .tmrd = 6, .tmrd_05T = 1, + .tmrwckel = 7, .tmrwckel_05T = 1, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 10, .tmrri_05T = 1, + .trrd = 3, .trrd_05T = 0, + .trrd_4266 = 2, .trrd_4266_05T = 0, + .tfaw = 8, .tfaw_05T = 0, + .tfaw_4266 = 4, .tfaw_4266_05T = 0, + .trtw_odt_off = 4, .trtw_odt_off_05T = 0, + .trtw_odt_on = 6, .trtw_odt_on_05T = 0, + .txrefcnt = 115, + .tzqcs = 34, + .xrtw2w_new_mode = 4, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 1, + .xrtw2r_odt_off = 1, + .xrtr2w_odt_on = 5, + .xrtr2w_odt_off = 5, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 7, + .tr2mrr = 4, + .vrcgdis_prdcnt = 40, + .hwset_mr2_op = 45, + .hwset_mr13_op = 216, + .hwset_vrcg_op = 208, + .trcd_derate = 8, .trcd_derate_05T = 0, + .trc_derate = 17, .trc_derate_05T = 0, + .tras_derate = 9, .tras_derate_05T = 1, + .trpab_derate = 8, .trpab_derate_05T = 0, + .trp_derate = 6, .trp_derate_05T = 1, + .trrd_derate = 4, .trrd_derate_05T = 0, + .trtpd = 12, .trtpd_05T = 0, + .twtpd = 14, .twtpd_05T = 1, + .tmrr2w_odt_off = 8, + .tmrr2w_odt_on = 10, + .ckeprd = 2, + .ckelckcnt = 2, + .zqlat2 = 12, + .dqsinctl = 5, .datlat = 15 + }, + { + .freq_group = DDRFREQ_1600, .cbt_mode = CBT_BYTE_MODE1, .read_dbi = 0, + .read_lat = 32, .write_lat = 14, .div_mode = DIV8_MODE, + .tras = 8, .tras_05T = 1, + .trp = 6, .trp_05T = 0, + .trpab = 7, .trpab_05T = 0, + .trc = 15, .trc_05T = 0, + .trfc = 100, .trfc_05T = 0, + .trfcpb = 44, .trfcpb_05T = 0, + .txp = 0, .txp_05T = 0, + .trtp = 1, .trtp_05T = 1, + .trcd = 7, .trcd_05T = 1, + .twr = 12, .twr_05T = 1, + .twtr = 8, .twtr_05T = 0, + .tpbr2pbr = 29, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 14, .tr2mrw_05T = 1, + .tw2mrw = 9, .tw2mrw_05T = 0, + .tmrr2mrw = 12, .tmrr2mrw_05T = 1, + .tmrw = 4, .tmrw_05T = 1, + .tmrd = 6, .tmrd_05T = 1, + .tmrwckel = 7, .tmrwckel_05T = 1, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 10, .tmrri_05T = 1, + .trrd = 3, .trrd_05T = 0, + .trrd_4266 = 2, .trrd_4266_05T = 0, + .tfaw = 8, .tfaw_05T = 0, + .tfaw_4266 = 4, .tfaw_4266_05T = 0, + .trtw_odt_off = 5, .trtw_odt_off_05T = 0, + .trtw_odt_on = 7, .trtw_odt_on_05T = 0, + .txrefcnt = 115, + .tzqcs = 34, + .xrtw2w_new_mode = 4, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 1, + .xrtw2r_odt_off = 1, + .xrtr2w_odt_on = 6, + .xrtr2w_odt_off = 6, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 7, + .tr2mrr = 4, + .vrcgdis_prdcnt = 40, + .hwset_mr2_op = 45, + .hwset_mr13_op = 216, + .hwset_vrcg_op = 208, + .trcd_derate = 8, .trcd_derate_05T = 0, + .trc_derate = 17, .trc_derate_05T = 0, + .tras_derate = 9, .tras_derate_05T = 1, + .trpab_derate = 8, .trpab_derate_05T = 0, + .trp_derate = 6, .trp_derate_05T = 1, + .trrd_derate = 4, .trrd_derate_05T = 0, + .trtpd = 13, .trtpd_05T = 0, + .twtpd = 15, .twtpd_05T = 1, + .tmrr2w_odt_off = 9, + .tmrr2w_odt_on = 11, + .ckeprd = 2, + .ckelckcnt = 2, + .zqlat2 = 12, + .dqsinctl = 5, .datlat = 15 + }, + { + .freq_group = DDRFREQ_1200, .cbt_mode = CBT_NORMAL_MODE, .read_dbi = 0, + .read_lat = 24, .write_lat = 12, .div_mode = DIV8_MODE, + .tras = 4, .tras_05T = 1, + .trp = 4, .trp_05T = 0, + .trpab = 5, .trpab_05T = 0, + .trc = 9, .trc_05T = 1, + .trfc = 72, .trfc_05T = 1, + .trfcpb = 30, .trfcpb_05T = 1, + .txp = 0, .txp_05T = 1, + .trtp = 1, .trtp_05T = 0, + .trcd = 5, .trcd_05T = 1, + .twr = 9, .twr_05T = 1, + .twtr = 6, .twtr_05T = 1, + .tpbr2pbr = 20, .tpbr2pbr_05T = 1, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 12, .tr2mrw_05T = 0, + .tw2mrw = 8, .tw2mrw_05T = 0, + .tmrr2mrw = 10, .tmrr2mrw_05T = 0, + .tmrw = 4, .tmrw_05T = 0, + .tmrd = 5, .tmrd_05T = 0, + .tmrwckel = 6, .tmrwckel_05T = 0, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 8, .tmrri_05T = 0, + .trrd = 2, .trrd_05T = 1, + .trrd_4266 = 1, .trrd_4266_05T = 1, + .tfaw = 4, .tfaw_05T = 1, + .tfaw_4266 = 1, .tfaw_4266_05T = 1, + .trtw_odt_off = 3, .trtw_odt_off_05T = 0, + .trtw_odt_on = 6, .trtw_odt_on_05T = 0, + .txrefcnt = 87, + .tzqcs = 26, + .xrtw2w_new_mode = 4, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 2, + .xrtw2r_odt_off = 2, + .xrtr2w_odt_on = 5, + .xrtr2w_odt_off = 5, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 6, + .tr2mrr = 4, + .vrcgdis_prdcnt = 31, + .hwset_mr2_op = 36, + .hwset_mr13_op = 24, + .hwset_vrcg_op = 16, + .trcd_derate = 6, .trcd_derate_05T = 0, + .trc_derate = 10, .trc_derate_05T = 1, + .tras_derate = 5, .tras_derate_05T = 0, + .trpab_derate = 5, .trpab_derate_05T = 1, + .trp_derate = 4, .trp_derate_05T = 1, + .trrd_derate = 3, .trrd_derate_05T = 0, + .trtpd = 10, .trtpd_05T = 1, + .twtpd = 12, .twtpd_05T = 0, + .tmrr2w_odt_off = 6, + .tmrr2w_odt_on = 8, + .ckeprd = 2, + .ckelckcnt = 2, + .zqlat2 = 10, + .dqsinctl = 4, .datlat = 13 + }, + { + .freq_group = DDRFREQ_1200, .cbt_mode = CBT_BYTE_MODE1, .read_dbi = 0, + .read_lat = 26, .write_lat = 12, .div_mode = DIV8_MODE, + .tras = 4, .tras_05T = 1, + .trp = 4, .trp_05T = 0, + .trpab = 5, .trpab_05T = 0, + .trc = 9, .trc_05T = 1, + .trfc = 72, .trfc_05T = 1, + .trfcpb = 30, .trfcpb_05T = 1, + .txp = 0, .txp_05T = 1, + .trtp = 1, .trtp_05T = 0, + .trcd = 5, .trcd_05T = 1, + .twr = 10, .twr_05T = 0, + .twtr = 6, .twtr_05T = 0, + .tpbr2pbr = 20, .tpbr2pbr_05T = 1, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 12, .tr2mrw_05T = 1, + .tw2mrw = 8, .tw2mrw_05T = 0, + .tmrr2mrw = 10, .tmrr2mrw_05T = 1, + .tmrw = 4, .tmrw_05T = 0, + .tmrd = 5, .tmrd_05T = 0, + .tmrwckel = 6, .tmrwckel_05T = 0, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 8, .tmrri_05T = 0, + .trrd = 2, .trrd_05T = 1, + .trrd_4266 = 1, .trrd_4266_05T = 1, + .tfaw = 4, .tfaw_05T = 1, + .tfaw_4266 = 1, .tfaw_4266_05T = 1, + .trtw_odt_off = 4, .trtw_odt_off_05T = 0, + .trtw_odt_on = 6, .trtw_odt_on_05T = 0, + .txrefcnt = 87, + .tzqcs = 26, + .xrtw2w_new_mode = 4, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 1, + .xrtw2r_odt_off = 1, + .xrtr2w_odt_on = 5, + .xrtr2w_odt_off = 5, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 6, + .tr2mrr = 4, + .vrcgdis_prdcnt = 31, + .hwset_mr2_op = 36, + .hwset_mr13_op = 24, + .hwset_vrcg_op = 16, + .trcd_derate = 6, .trcd_derate_05T = 0, + .trc_derate = 10, .trc_derate_05T = 1, + .tras_derate = 5, .tras_derate_05T = 0, + .trpab_derate = 5, .trpab_derate_05T = 1, + .trp_derate = 4, .trp_derate_05T = 1, + .trrd_derate = 3, .trrd_derate_05T = 0, + .trtpd = 11, .trtpd_05T = 0, + .twtpd = 13, .twtpd_05T = 0, + .tmrr2w_odt_off = 7, + .tmrr2w_odt_on = 9, + .ckeprd = 2, + .ckelckcnt = 2, + .zqlat2 = 10, + .dqsinctl = 4, .datlat = 13 + }, + { + .freq_group = DDRFREQ_933, .cbt_mode = CBT_NORMAL_MODE, .read_dbi = 0, + .read_lat = 20, .write_lat = 10, .div_mode = DIV8_MODE, + .tras = 1, .tras_05T = 1, + .trp = 3, .trp_05T = 0, + .trpab = 3, .trpab_05T = 1, + .trc = 5, .trc_05T = 0, + .trfc = 53, .trfc_05T = 1, + .trfcpb = 21, .trfcpb_05T = 0, + .txp = 0, .txp_05T = 0, + .trtp = 0, .trtp_05T = 1, + .trcd = 4, .trcd_05T = 1, + .twr = 8, .twr_05T = 1, + .twtr = 5, .twtr_05T = 1, + .tpbr2pbr = 14, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 10, .tr2mrw_05T = 0, + .tw2mrw = 7, .tw2mrw_05T = 0, + .tmrr2mrw = 9, .tmrr2mrw_05T = 0, + .tmrw = 3, .tmrw_05T = 0, + .tmrd = 4, .tmrd_05T = 0, + .tmrwckel = 5, .tmrwckel_05T = 0, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 6, .tmrri_05T = 0, + .trrd = 1, .trrd_05T = 1, + .trrd_4266 = 1, .trrd_4266_05T = 0, + .tfaw = 1, .tfaw_05T = 1, + .tfaw_4266 = 0, .tfaw_4266_05T = 0, + .trtw_odt_off = 3, .trtw_odt_off_05T = 0, + .trtw_odt_on = 5, .trtw_odt_on_05T = 0, + .txrefcnt = 68, + .tzqcs = 19, + .xrtw2w_new_mode = 4, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 2, + .xrtw2r_odt_off = 2, + .xrtr2w_odt_on = 3, + .xrtr2w_odt_off = 3, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 6, + .tr2mrr = 4, + .vrcgdis_prdcnt = 24, + .hwset_mr2_op = 27, + .hwset_mr13_op = 24, + .hwset_vrcg_op = 16, + .trcd_derate = 5, .trcd_derate_05T = 0, + .trc_derate = 6, .trc_derate_05T = 1, + .tras_derate = 2, .tras_derate_05T = 0, + .trpab_derate = 4, .trpab_derate_05T = 0, + .trp_derate = 3, .trp_derate_05T = 1, + .trrd_derate = 2, .trrd_derate_05T = 0, + .trtpd = 9, .trtpd_05T = 1, + .twtpd = 10, .twtpd_05T = 1, + .tmrr2w_odt_off = 5, + .tmrr2w_odt_on = 7, + .ckeprd = 1, + .ckelckcnt = 2, + .zqlat2 = 7, + .dqsinctl = 3, .datlat = 13 + }, + { + .freq_group = DDRFREQ_933, .cbt_mode = CBT_BYTE_MODE1, .read_dbi = 0, + .read_lat = 22, .write_lat = 10, .div_mode = DIV8_MODE, + .tras = 1, .tras_05T = 1, + .trp = 3, .trp_05T = 0, + .trpab = 3, .trpab_05T = 1, + .trc = 5, .trc_05T = 0, + .trfc = 53, .trfc_05T = 1, + .trfcpb = 21, .trfcpb_05T = 0, + .txp = 0, .txp_05T = 0, + .trtp = 0, .trtp_05T = 1, + .trcd = 4, .trcd_05T = 1, + .twr = 8, .twr_05T = 0, + .twtr = 5, .twtr_05T = 0, + .tpbr2pbr = 14, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 10, .tr2mrw_05T = 1, + .tw2mrw = 7, .tw2mrw_05T = 0, + .tmrr2mrw = 9, .tmrr2mrw_05T = 1, + .tmrw = 3, .tmrw_05T = 0, + .tmrd = 4, .tmrd_05T = 0, + .tmrwckel = 5, .tmrwckel_05T = 0, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 6, .tmrri_05T = 0, + .trrd = 1, .trrd_05T = 1, + .trrd_4266 = 1, .trrd_4266_05T = 0, + .tfaw = 1, .tfaw_05T = 1, + .tfaw_4266 = 0, .tfaw_4266_05T = 0, + .trtw_odt_off = 3, .trtw_odt_off_05T = 0, + .trtw_odt_on = 5, .trtw_odt_on_05T = 0, + .txrefcnt = 68, + .tzqcs = 19, + .xrtw2w_new_mode = 4, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 2, + .xrtw2r_odt_off = 1, + .xrtr2w_odt_on = 4, + .xrtr2w_odt_off = 4, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 6, + .tr2mrr = 4, + .vrcgdis_prdcnt = 24, + .hwset_mr2_op = 27, + .hwset_mr13_op = 24, + .hwset_vrcg_op = 16, + .trcd_derate = 5, .trcd_derate_05T = 0, + .trc_derate = 6, .trc_derate_05T = 1, + .tras_derate = 2, .tras_derate_05T = 0, + .trpab_derate = 4, .trpab_derate_05T = 0, + .trp_derate = 3, .trp_derate_05T = 1, + .trrd_derate = 2, .trrd_derate_05T = 0, + .trtpd = 10, .trtpd_05T = 0, + .twtpd = 11, .twtpd_05T = 0, + .tmrr2w_odt_off = 6, + .tmrr2w_odt_on = 8, + .ckeprd = 1, + .ckelckcnt = 2, + .zqlat2 = 7, + .dqsinctl = 3, .datlat = 13 + }, + { + .freq_group = DDRFREQ_800, .cbt_mode = CBT_NORMAL_MODE, .read_dbi = 0, + .read_lat = 14, .write_lat = 8, .div_mode = DIV8_MODE, + .tras = 0, .tras_05T = 0, + .trp = 2, .trp_05T = 1, + .trpab = 3, .trpab_05T = 0, + .trc = 3, .trc_05T = 0, + .trfc = 44, .trfc_05T = 0, + .trfcpb = 16, .trfcpb_05T = 0, + .txp = 0, .txp_05T = 0, + .trtp = 0, .trtp_05T = 1, + .trcd = 4, .trcd_05T = 0, + .twr = 7, .twr_05T = 1, + .twtr = 4, .twtr_05T = 1, + .tpbr2pbr = 11, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 8, .tr2mrw_05T = 1, + .tw2mrw = 6, .tw2mrw_05T = 1, + .tmrr2mrw = 7, .tmrr2mrw_05T = 0, + .tmrw = 3, .tmrw_05T = 0, + .tmrd = 3, .tmrd_05T = 1, + .tmrwckel = 4, .tmrwckel_05T = 1, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 5, .tmrri_05T = 1, + .trrd = 1, .trrd_05T = 0, + .trrd_4266 = 0, .trrd_4266_05T = 1, + .tfaw = 0, .tfaw_05T = 0, + .tfaw_4266 = 0, .tfaw_4266_05T = 0, + .trtw_odt_off = 1, .trtw_odt_off_05T = 0, + .trtw_odt_on = 4, .trtw_odt_on_05T = 0, + .txrefcnt = 58, + .tzqcs = 16, + .xrtw2w_new_mode = 4, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 3, + .xrtw2r_odt_off = 3, + .xrtr2w_odt_on = 3, + .xrtr2w_odt_off = 3, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 6, + .tr2mrr = 4, + .vrcgdis_prdcnt = 20, + .hwset_mr2_op = 18, + .hwset_mr13_op = 24, + .hwset_vrcg_op = 16, + .trcd_derate = 4, .trcd_derate_05T = 0, + .trc_derate = 4, .trc_derate_05T = 0, + .tras_derate = 0, .tras_derate_05T = 1, + .trpab_derate = 3, .trpab_derate_05T = 1, + .trp_derate = 2, .trp_derate_05T = 1, + .trrd_derate = 1, .trrd_derate_05T = 1, + .trtpd = 7, .trtpd_05T = 1, + .twtpd = 9, .twtpd_05T = 1, + .tmrr2w_odt_off = 3, + .tmrr2w_odt_on = 5, + .ckeprd = 1, + .ckelckcnt = 2, + .zqlat2 = 6, + .dqsinctl = 2, .datlat = 10 + }, + { + .freq_group = DDRFREQ_800, .cbt_mode = CBT_BYTE_MODE1, .read_dbi = 0, + .read_lat = 16, .write_lat = 8, .div_mode = DIV8_MODE, + .tras = 0, .tras_05T = 0, + .trp = 2, .trp_05T = 1, + .trpab = 3, .trpab_05T = 0, + .trc = 3, .trc_05T = 0, + .trfc = 44, .trfc_05T = 0, + .trfcpb = 16, .trfcpb_05T = 0, + .txp = 0, .txp_05T = 0, + .trtp = 0, .trtp_05T = 1, + .trcd = 4, .trcd_05T = 0, + .twr = 7, .twr_05T = 0, + .twtr = 4, .twtr_05T = 0, + .tpbr2pbr = 11, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 9, .tr2mrw_05T = 0, + .tw2mrw = 6, .tw2mrw_05T = 1, + .tmrr2mrw = 7, .tmrr2mrw_05T = 1, + .tmrw = 3, .tmrw_05T = 0, + .tmrd = 3, .tmrd_05T = 1, + .tmrwckel = 4, .tmrwckel_05T = 1, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 5, .tmrri_05T = 1, + .trrd = 1, .trrd_05T = 0, + .trrd_4266 = 0, .trrd_4266_05T = 1, + .tfaw = 0, .tfaw_05T = 0, + .tfaw_4266 = 0, .tfaw_4266_05T = 0, + .trtw_odt_off = 2, .trtw_odt_off_05T = 0, + .trtw_odt_on = 4, .trtw_odt_on_05T = 0, + .txrefcnt = 58, + .tzqcs = 16, + .xrtw2w_new_mode = 4, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 3, + .xrtw2r_odt_off = 2, + .xrtr2w_odt_on = 3, + .xrtr2w_odt_off = 3, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 6, + .tr2mrr = 4, + .vrcgdis_prdcnt = 20, + .hwset_mr2_op = 18, + .hwset_mr13_op = 24, + .hwset_vrcg_op = 16, + .trcd_derate = 4, .trcd_derate_05T = 0, + .trc_derate = 4, .trc_derate_05T = 0, + .tras_derate = 0, .tras_derate_05T = 1, + .trpab_derate = 3, .trpab_derate_05T = 1, + .trp_derate = 2, .trp_derate_05T = 1, + .trrd_derate = 1, .trrd_derate_05T = 1, + .trtpd = 8, .trtpd_05T = 0, + .twtpd = 9, .twtpd_05T = 1, + .tmrr2w_odt_off = 4, + .tmrr2w_odt_on = 6, + .ckeprd = 1, + .ckelckcnt = 2, + .zqlat2 = 6, + .dqsinctl = 2, .datlat = 10 + }, + { + .freq_group = DDRFREQ_600, .cbt_mode = CBT_NORMAL_MODE, .read_dbi = 0, + .read_lat = 14, .write_lat = 8, .div_mode = DIV8_MODE, + .tras = 0, .tras_05T = 0, + .trp = 1, .trp_05T = 1, + .trpab = 2, .trpab_05T = 0, + .trc = 0, .trc_05T = 1, + .trfc = 30, .trfc_05T = 1, + .trfcpb = 9, .trfcpb_05T = 1, + .txp = 0, .txp_05T = 0, + .trtp = 0, .trtp_05T = 1, + .trcd = 3, .trcd_05T = 0, + .twr = 6, .twr_05T = 1, + .twtr = 4, .twtr_05T = 1, + .tpbr2pbr = 7, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 8, .tr2mrw_05T = 1, + .tw2mrw = 6, .tw2mrw_05T = 1, + .tmrr2mrw = 7, .tmrr2mrw_05T = 0, + .tmrw = 3, .tmrw_05T = 0, + .tmrd = 3, .tmrd_05T = 0, + .tmrwckel = 4, .tmrwckel_05T = 0, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 4, .tmrri_05T = 0, + .trrd = 1, .trrd_05T = 0, + .trrd_4266 = 0, .trrd_4266_05T = 1, + .tfaw = 0, .tfaw_05T = 0, + .tfaw_4266 = 0, .tfaw_4266_05T = 0, + .trtw_odt_off = 1, .trtw_odt_off_05T = 0, + .trtw_odt_on = 4, .trtw_odt_on_05T = 0, + .txrefcnt = 44, + .tzqcs = 12, + .xrtw2w_new_mode = 4, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 3, + .xrtw2r_odt_off = 3, + .xrtr2w_odt_on = 3, + .xrtr2w_odt_off = 3, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 6, + .tr2mrr = 4, + .vrcgdis_prdcnt = 16, + .hwset_mr2_op = 18, + .hwset_mr13_op = 24, + .hwset_vrcg_op = 16, + .trcd_derate = 3, .trcd_derate_05T = 0, + .trc_derate = 1, .trc_derate_05T = 0, + .tras_derate = 0, .tras_derate_05T = 0, + .trpab_derate = 2, .trpab_derate_05T = 0, + .trp_derate = 1, .trp_derate_05T = 1, + .trrd_derate = 1, .trrd_derate_05T = 0, + .trtpd = 7, .trtpd_05T = 1, + .twtpd = 8, .twtpd_05T = 1, + .tmrr2w_odt_off = 3, + .tmrr2w_odt_on = 5, + .ckeprd = 1, + .ckelckcnt = 2, + .zqlat2 = 5, + .dqsinctl = 2, .datlat = 9 + }, + { + .freq_group = DDRFREQ_600, .cbt_mode = CBT_BYTE_MODE1, .read_dbi = 0, + .read_lat = 16, .write_lat = 8, .div_mode = DIV8_MODE, + .tras = 0, .tras_05T = 0, + .trp = 1, .trp_05T = 1, + .trpab = 2, .trpab_05T = 0, + .trc = 0, .trc_05T = 1, + .trfc = 30, .trfc_05T = 1, + .trfcpb = 9, .trfcpb_05T = 1, + .txp = 0, .txp_05T = 0, + .trtp = 0, .trtp_05T = 1, + .trcd = 3, .trcd_05T = 0, + .twr = 6, .twr_05T = 0, + .twtr = 4, .twtr_05T = 1, + .tpbr2pbr = 7, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 9, .tr2mrw_05T = 0, + .tw2mrw = 6, .tw2mrw_05T = 1, + .tmrr2mrw = 7, .tmrr2mrw_05T = 1, + .tmrw = 3, .tmrw_05T = 0, + .tmrd = 3, .tmrd_05T = 0, + .tmrwckel = 4, .tmrwckel_05T = 0, + .tpde = 1, .tpde_05T = 1, + .tpdx = 1, .tpdx_05T = 0, + .tmrri = 4, .tmrri_05T = 0, + .trrd = 1, .trrd_05T = 0, + .trrd_4266 = 0, .trrd_4266_05T = 1, + .tfaw = 0, .tfaw_05T = 0, + .tfaw_4266 = 0, .tfaw_4266_05T = 0, + .trtw_odt_off = 2, .trtw_odt_off_05T = 0, + .trtw_odt_on = 5, .trtw_odt_on_05T = 0, + .txrefcnt = 44, + .tzqcs = 12, + .xrtw2w_new_mode = 4, + .xrtw2w_old_mode = 6, + .xrtw2r_odt_on = 3, + .xrtw2r_odt_off = 2, + .xrtr2w_odt_on = 3, + .xrtr2w_odt_off = 3, + .xrtr2r_new_mode = 3, + .xrtr2r_old_mode = 6, + .tr2mrr = 4, + .vrcgdis_prdcnt = 16, + .hwset_mr2_op = 18, + .hwset_mr13_op = 24, + .hwset_vrcg_op = 16, + .trcd_derate = 3, .trcd_derate_05T = 0, + .trc_derate = 1, .trc_derate_05T = 0, + .tras_derate = 0, .tras_derate_05T = 0, + .trpab_derate = 2, .trpab_derate_05T = 0, + .trp_derate = 1, .trp_derate_05T = 1, + .trrd_derate = 1, .trrd_derate_05T = 0, + .trtpd = 8, .trtpd_05T = 0, + .twtpd = 9, .twtpd_05T = 0, + .tmrr2w_odt_off = 4, + .tmrr2w_odt_on = 6, + .ckeprd = 1, + .ckelckcnt = 2, + .zqlat2 = 5, + .dqsinctl = 2, .datlat = 9 + }, + { + .freq_group = DDRFREQ_400, .cbt_mode = CBT_NORMAL_MODE, .read_dbi = 0, + .read_lat = 14, .write_lat = 8, .div_mode = DIV4_MODE, + .tras = 1, .tras_05T = 0, + .trp = 2, .trp_05T = 0, + .trpab = 3, .trpab_05T = 0, + .trc = 3, .trc_05T = 0, + .trfc = 44, .trfc_05T = 0, + .trfcpb = 16, .trfcpb_05T = 0, + .txp = 0, .txp_05T = 0, + .trtp = 3, .trtp_05T = 0, + .trcd = 4, .trcd_05T = 0, + .twr = 12, .twr_05T = 0, + .twtr = 10, .twtr_05T = 0, + .tpbr2pbr = 11, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 16, .tr2mrw_05T = 0, + .tw2mrw = 13, .tw2mrw_05T = 0, + .tmrr2mrw = 14, .tmrr2mrw_05T = 0, + .tmrw = 6, .tmrw_05T = 0, + .tmrd = 6, .tmrd_05T = 0, + .tmrwckel = 8, .tmrwckel_05T = 0, + .tpde = 3, .tpde_05T = 0, + .tpdx = 3, .tpdx_05T = 0, + .tmrri = 7, .tmrri_05T = 0, + .trrd = 1, .trrd_05T = 0, + .trrd_4266 = 1, .trrd_4266_05T = 0, + .tfaw = 0, .tfaw_05T = 0, + .tfaw_4266 = 0, .tfaw_4266_05T = 0, + .trtw_odt_off = 6, .trtw_odt_off_05T = 0, + .trtw_odt_on = 11, .trtw_odt_on_05T = 0, + .txrefcnt = 58, + .tzqcs = 16, + .xrtw2w_new_mode = 9, + .xrtw2w_old_mode = 10, + .xrtw2r_odt_on = 7, + .xrtw2r_odt_off = 5, + .xrtr2w_odt_on = 9, + .xrtr2w_odt_off = 9, + .xrtr2r_new_mode = 6, + .xrtr2r_old_mode = 8, + .tr2mrr = 8, + .vrcgdis_prdcnt = 20, + .hwset_mr2_op = 18, + .hwset_mr13_op = 24, + .hwset_vrcg_op = 16, + .trcd_derate = 4, .trcd_derate_05T = 0, + .trc_derate = 4, .trc_derate_05T = 0, + .tras_derate = 1, .tras_derate_05T = 0, + .trpab_derate = 3, .trpab_derate_05T = 0, + .trp_derate = 2, .trp_derate_05T = 0, + .trrd_derate = 2, .trrd_derate_05T = 0, + .trtpd = 15, .trtpd_05T = 0, + .twtpd = 15, .twtpd_05T = 0, + .tmrr2w_odt_off = 10, + .tmrr2w_odt_on = 12, + .ckeprd = 2, + .ckelckcnt = 3, + .zqlat2 = 6, + .dqsinctl = 5, .datlat = 15 + }, + { + .freq_group = DDRFREQ_400, .cbt_mode = CBT_BYTE_MODE1, .read_dbi = 0, + .read_lat = 16, .write_lat = 8, .div_mode = DIV4_MODE, + .tras = 1, .tras_05T = 0, + .trp = 2, .trp_05T = 0, + .trpab = 3, .trpab_05T = 0, + .trc = 3, .trc_05T = 0, + .trfc = 44, .trfc_05T = 0, + .trfcpb = 16, .trfcpb_05T = 0, + .txp = 0, .txp_05T = 0, + .trtp = 3, .trtp_05T = 0, + .trcd = 4, .trcd_05T = 0, + .twr = 12, .twr_05T = 0, + .twtr = 10, .twtr_05T = 0, + .tpbr2pbr = 11, .tpbr2pbr_05T = 0, + .tpbr2act = 0, .tpbr2act_05T = 0, + .tr2mrw = 17, .tr2mrw_05T = 0, + .tw2mrw = 13, .tw2mrw_05T = 0, + .tmrr2mrw = 15, .tmrr2mrw_05T = 0, + .tmrw = 6, .tmrw_05T = 0, + .tmrd = 6, .tmrd_05T = 0, + .tmrwckel = 8, .tmrwckel_05T = 0, + .tpde = 3, .tpde_05T = 0, + .tpdx = 3, .tpdx_05T = 0, + .tmrri = 7, .tmrri_05T = 0, + .trrd = 1, .trrd_05T = 0, + .trrd_4266 = 1, .trrd_4266_05T = 0, + .tfaw = 0, .tfaw_05T = 0, + .tfaw_4266 = 0, .tfaw_4266_05T = 0, + .trtw_odt_off = 7, .trtw_odt_off_05T = 0, + .trtw_odt_on = 12, .trtw_odt_on_05T = 0, + .txrefcnt = 58, + .tzqcs = 16, + .xrtw2w_new_mode = 9, + .xrtw2w_old_mode = 10, + .xrtw2r_odt_on = 6, + .xrtw2r_odt_off = 4, + .xrtr2w_odt_on = 10, + .xrtr2w_odt_off = 10, + .xrtr2r_new_mode = 6, + .xrtr2r_old_mode = 9, + .tr2mrr = 8, + .vrcgdis_prdcnt = 20, + .hwset_mr2_op = 18, + .hwset_mr13_op = 24, + .hwset_vrcg_op = 16, + .trcd_derate = 4, .trcd_derate_05T = 0, + .trc_derate = 4, .trc_derate_05T = 0, + .tras_derate = 1, .tras_derate_05T = 0, + .trpab_derate = 3, .trpab_derate_05T = 0, + .trp_derate = 2, .trp_derate_05T = 0, + .trrd_derate = 2, .trrd_derate_05T = 0, + .trtpd = 16, .trtpd_05T = 0, + .twtpd = 15, .twtpd_05T = 0, + .tmrr2w_odt_off = 11, + .tmrr2w_odt_on = 13, + .ckeprd = 2, + .ckelckcnt = 3, + .zqlat2 = 6, + .dqsinctl = 5, .datlat = 15 + }, +}; +#endif /* __SOC_MEDIATEK_MT8192_DRAMC_AC_TIMING_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/44713 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I10e704868e4cd36a938a669879bb1a8632e73e1a Gerrit-Change-Number: 44713 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

22 hours, 28 minutes

Change in coreboot[master]: soc/mediatek/mt8192: Add dramc 8 phase calibration

by CK HU (Code Review)

Hello Duan huayang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44709 to review the following change. Change subject: soc/mediatek/mt8192: Add dramc 8 phase calibration ...................................................................... soc/mediatek/mt8192: Add dramc 8 phase calibration Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> Change-Id: Ib4ccaa8d43b8382cbc64cf82de86ad1ac16cb89a --- M src/soc/mediatek/mt8192/dramc_pi_basic_api.c M src/soc/mediatek/mt8192/dramc_pi_calibration_api.c 2 files changed, 344 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/44709/1 diff --git a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c index fb250ab..b5b262b 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c @@ -3790,6 +3790,7 @@ { dramc_setting(cali); dramc_reset_delay_chain_before_calibration(); + dramc_8_phase_cal(cali); } static void dramc_before_calibration(const struct ddr_cali *cali) diff --git a/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c index 38a8048..22a2545 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c @@ -236,3 +236,346 @@ dramc_set_broadcast(bc_bak); } +static void dramc_phy_reset(u8 chn) +{ + SET32_BITFIELDS(&ch[chn].ao.rx_set0, RX_SET0_RDATRST, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_ctrl1, MISC_CTRL1_R_DMPHYRST, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[0].b0_dq9, + B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0, 0, + B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[1].b0_dq9, + B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1, 0, + B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1, 0); + udelay(1); + SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[1].b0_dq9, + B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1, 1, + B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[0].b0_dq9, + B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0, 1, + B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_ctrl1, MISC_CTRL1_R_DMPHYRST, 0); + SET32_BITFIELDS(&ch[chn].ao.rx_set0, RX_SET0_RDATRST, 0); +} + +static int dramc_8_phase_cal_find_best_dly(u8 phase_sm, u8 ph_dly, u8 ph_dly_back, + u8 *dqs_level, u8 *ph_dly_final, u8 *ph_dly_loop_break) +{ + u8 early_break_cnt = 5; + static u8 loop_cnt = 0; + static u16 r0 = 0xffff, r180 = 0xffff, r_tmp = 0xffff, p_tmp = 0xffff; + static s16 err_code = 0x7fff, err_code_min = 0x7fff; + u16 dqs_dly = 0, jm_dly_start = 0, jm_dly_end = 512, jm_dly_step = 1; + u32 sample_cnt, ones_cnt[DQS_NUMBER]; + + dramc_dbg("8PH dly = %d\n", ph_dly); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq1, + SHU_B0_DQ1_RG_ARPI_MIDPI_8PH_DLY_B0, ph_dly); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq1, + SHU_B1_DQ1_RG_ARPI_MIDPI_8PH_DLY_B1, ph_dly); + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd1, + SHU_CA_CMD1_RG_ARPI_MIDPI_8PH_DLY_CA, ph_dly); + + for (dqs_dly = jm_dly_start; dqs_dly < jm_dly_end; dqs_dly += jm_dly_step) { + /* Set DQS delay */ + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_phy2, + B0_PHY2_RG_RX_ARDQS_JM_DLY_B0, dqs_dly); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_phy2, + B1_PHY2_RG_RX_ARDQS_JM_DLY_B1, dqs_dly); + dramc_phy_reset(0); + SET32_BITFIELDS(&ch[0].phy_ao.misc_dutyscan1, + MISC_DUTYSCAN1_REG_SW_RST, 1); + SET32_BITFIELDS(&ch[0].phy_ao.misc_dutyscan1, + MISC_DUTYSCAN1_REG_SW_RST, 0); + SET32_BITFIELDS(&ch[0].phy_ao.misc_dutyscan1, + MISC_DUTYSCAN1_RX_EYE_SCAN_EN, 1); + udelay(10); + SET32_BITFIELDS(&ch[0].phy_ao.misc_dutyscan1, + MISC_DUTYSCAN1_RX_EYE_SCAN_EN, 0); + sample_cnt = READ32_BITFIELD(&ch[0].phy_nao.misc_duty_toggle_cnt, + MISC_DUTY_TOGGLE_CNT_TOGGLE_CNT); + ones_cnt[0] = READ32_BITFIELD(&ch[0].phy_nao.misc_duty_dqs0_err_cnt, + MISC_DUTY_DQS0_ERR_CNT_DQS0_ERR_CNT); + + if (ones_cnt[0] < (sample_cnt / 2)) { + if (*dqs_level == 0xff) + dramc_dbg("[L] %d, %8d\n", dqs_dly, ones_cnt[0]); + *dqs_level = 0; + } else { + if (*dqs_level == 0) { + *dqs_level = 1; + dramc_dbg("[H] %d, %8d\n", dqs_dly, ones_cnt[0]); + + if (phase_sm == DQS_8PH_DEGREE_0) { + r0 = dqs_dly; + dramc_dbg("R0 = %d\n", r0); + break; + } else if (phase_sm == DQS_8PH_DEGREE_180) { + r180 = dqs_dly; + if (r180 > r0) { + r_tmp = r0 + ((r180 - r0) >> 2); + dramc_dbg("R = %d, R180 = %d\n", r_tmp, r180); + break; + } else { + *dqs_level = 0xff; + } + } else if (phase_sm == DQS_8PH_DEGREE_45) { + p_tmp = dqs_dly; + dramc_dbg("p_tmp =%d, R0 = %d\n", p_tmp, r0); + if (p_tmp > r0) { + if (r_tmp > p_tmp) + err_code = r_tmp - p_tmp; + else + err_code = p_tmp - r_tmp; + + if (err_code == 0) { + *ph_dly_final = ph_dly; + *ph_dly_loop_break = 1; + } else if (err_code < err_code_min) { + err_code_min = err_code; + *ph_dly_final = ph_dly; + loop_cnt = 0; + } else if (err_code >= err_code_min) { + loop_cnt++; + if (loop_cnt > early_break_cnt) + *ph_dly_loop_break = 1; + } + + dramc_dbg("diff (P-R) = %d, min = %d, break count = %d\n", + err_code, err_code_min, loop_cnt); + break; + } else { + *dqs_level = 0xff; + } + } else { + dramc_dbg("phase_sm err!\n"); + } + } + } + + } + + if ((*dqs_level == 0xff) || (*dqs_level == 0)) { + *ph_dly_final = ph_dly_back; + dramc_dbg("8-Phase SM_%d is fail (to Default)!\n", phase_sm); + return 0; + } else if (*ph_dly_loop_break == 1) + return -1; + + return -2; +} + +static void dramc_8_phase_cal_set_best_dly(const struct ddr_cali *cali, u8 ph_dly_back) +{ + u8 dqsien_pi = 0; + u8 phase_sm, ph_dly = 0, ph_start = 0, ph_end = 0, ph_dly_final = 0xff; + u8 ph_dly_loop_break = 0; + + for (phase_sm = DQS_8PH_DEGREE_0; phase_sm < DQS_8PH_DEGREE_MAX; phase_sm++) { + switch (phase_sm) { + case DQS_8PH_DEGREE_0: + dqsien_pi = 16; + ph_start = 0; + ph_end = 1; + break; + case DQS_8PH_DEGREE_180: + dqsien_pi = 48; + ph_start = 0; + ph_end = 1; + break; + case DQS_8PH_DEGREE_45: + dqsien_pi = 24; + ph_start = 0; + ph_end = 32; + break; + default: + dramc_dbg("phase_sm err!\n"); + break; + } + + dramc_dbg("8-Phase SM_%d, 8PH_dly (%d~%d), DQSIEN PI = %d, 8PH_Dly = %d\n", + phase_sm, ph_start, ph_end, dqsien_pi, ph_dly_back); + + for (u8 rk = RANK_0; rk < cali->support_ranks; rk++) + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[rk].shu_rk_b0_dqsien_pi_dly, + SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0, dqsien_pi); + + for (ph_dly = ph_start; ph_dly < ph_end; ph_dly++) { + u8 dqs_level = 0xff; + int ret = dramc_8_phase_cal_find_best_dly(phase_sm, ph_dly, + ph_dly_back, &dqs_level, + &ph_dly_final, &ph_dly_loop_break); + if (ret == 0) + goto final_found; + if (ph_dly_loop_break == 1) + break; + } + } + +final_found: + dramc_dbg("8 phase calibration ph_dly_final = %d\n", ph_dly_final); + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dq1, + SHU_B0_DQ1_RG_ARPI_MIDPI_8PH_DLY_B0, ph_dly_final); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dq1, + SHU_B1_DQ1_RG_ARPI_MIDPI_8PH_DLY_B1, ph_dly_final); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_cmd1, + SHU_CA_CMD1_RG_ARPI_MIDPI_8PH_DLY_CA, ph_dly_final); + } +} + +void dramc_8_phase_cal(const struct ddr_cali *cali) +{ + u8 ph_dly_back = 0; + dram_freq_grp freq_group = cali->freq_group; + + if (freq_group < DDRFREQ_2133) { + dramc_dbg("Freq %d < 2133, do not need do 8-Phase\n", get_frequency(cali)); + return; + } + + struct reg_bak regs_bak[] = { + {&ch[0].phy_ao.misc_dutyscan1}, + {&ch[0].phy_ao.dvs_b[0].b0_dq6}, + {&ch[0].phy_ao.dvs_b[1].b0_dq6}, + {&ch[0].phy_ao.dvs_b[0].b0_dq5}, + {&ch[0].phy_ao.dvs_b[1].b0_dq5}, + {&ch[0].phy_ao.dvs_b[0].b0_dq3}, + {&ch[0].phy_ao.dvs_b[1].b0_dq3}, + {&ch[0].phy_ao.misc_ctrl1}, + {&ch[0].phy_ao.misc_ctrl4}, + {&ch[0].phy_ao.dvs_b[0].b0_phy2}, + {&ch[0].phy_ao.dvs_b[1].b0_phy2}, + {&ch[0].phy_ao.byte[0].shu_b0_dll_arpi2}, + {&ch[0].phy_ao.byte[1].shu_b0_dll_arpi2}, + {&ch[0].phy_ao.byte[0].shu_b0_dq11}, + {&ch[0].phy_ao.byte[1].shu_b0_dq11}, + {&ch[0].phy_ao.shu_ca_cmd11}, + {&ch[0].phy_ao.misc_stbcal}, + {&ch[0].phy_ao.byte[0].rk[0].shu_rk_b0_dqsien_pi_dly}, + {&ch[0].phy_ao.byte[0].rk[1].shu_rk_b0_dqsien_pi_dly}, + {&ch[0].phy_ao.misc_jmeter}, + {&ch[0].phy_ao.misc_shu_stbcal}, + {&ch[0].phy_ao.shu_ca_dll1}, + {&ch[0].phy_ao.byte[0].shu_b0_dll1}, + {&ch[0].phy_ao.byte[1].shu_b0_dll1}, + {&ch[0].phy_ao.dvs_b[0].b0_dq2}, + {&ch[0].phy_ao.dvs_b[1].b0_dq2}, + {&ch[0].phy_ao.ca_cmd2}, + {&ch[0].phy_ao.byte[0].shu_b0_dq13}, + {&ch[0].phy_ao.byte[1].shu_b0_dq13}, + {&ch[0].phy_ao.shu_ca_cmd13}, + {&ch[1].phy_ao.shu_ca_dll1}, + {&ch[1].phy_ao.byte[0].shu_b0_dll1}, + {&ch[1].phy_ao.byte[1].shu_b0_dll1}, + {&ch[1].phy_ao.dvs_b[0].b0_dq2}, + {&ch[1].phy_ao.dvs_b[1].b0_dq2}, + {&ch[1].phy_ao.ca_cmd2}, + {&ch[1].phy_ao.byte[0].shu_b0_dq13}, + {&ch[1].phy_ao.byte[1].shu_b0_dq13}, + {&ch[1].phy_ao.shu_ca_cmd13}, + }; + for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) + regs_bak[i].value = read32(regs_bak[i].addr); + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[0].b0_dq2, + B0_DQ2_RG_TX_ARDQS_OE_TIE_SEL_B0, 0, + B0_DQ2_RG_TX_ARDQS_OE_TIE_EN_B0, 1, + B0_DQ2_RG_TX_ARWCK_OE_TIE_SEL_B0, 0, + B0_DQ2_RG_TX_ARWCK_OE_TIE_EN_B0, 1, + B0_DQ2_RG_TX_ARWCKB_OE_TIE_SEL_B0, 0, + B0_DQ2_RG_TX_ARWCKB_OE_TIE_EN_B0, 1, + B0_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B0, 0, + B0_DQ2_RG_TX_ARDQM_OE_TIE_EN_B0, 1, + B0_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B0, 0, + B0_DQ2_RG_TX_ARDQ_OE_TIE_EN_B0, 0xff); + SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[1].b0_dq2, + B1_DQ2_RG_TX_ARDQS_OE_TIE_SEL_B1, 0, + B1_DQ2_RG_TX_ARDQS_OE_TIE_EN_B1, 1, + B1_DQ2_RG_TX_ARWCK_OE_TIE_SEL_B1, 0, + B1_DQ2_RG_TX_ARWCK_OE_TIE_EN_B1, 1, + B1_DQ2_RG_TX_ARWCKB_OE_TIE_SEL_B1, 0, + B1_DQ2_RG_TX_ARWCKB_OE_TIE_EN_B1, 1, + B1_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B1, 0, + B1_DQ2_RG_TX_ARDQM_OE_TIE_EN_B1, 1, + B1_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B1, 0, + B1_DQ2_RG_TX_ARDQ_OE_TIE_EN_B1, 0xff); + SET32_BITFIELDS(&ch[chn].phy_ao.ca_cmd2, + CA_CMD2_RG_TX_ARCLK_OE_TIE_SEL_CA, 0, + CA_CMD2_RG_TX_ARCLK_OE_TIE_EN_CA, 1, + CA_CMD2_RG_TX_ARCS_OE_TIE_SEL_CA, 0, + CA_CMD2_RG_TX_ARCS_OE_TIE_EN_CA, 1, + CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA, 0, + CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA, 0xff); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dq13, + SHU_B0_DQ13_RG_TX_ARDQSB_OE_TIE_SEL_B0, 0, + SHU_B0_DQ13_RG_TX_ARDQSB_OE_TIE_EN_B0, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dq13, + SHU_B1_DQ13_RG_TX_ARDQSB_OE_TIE_SEL_B1, 0, + SHU_B1_DQ13_RG_TX_ARDQSB_OE_TIE_EN_B1, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_cmd13, + SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_SEL_CA, 0, + SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_EN_CA, 1); + } + + ph_dly_back = READ32_BITFIELD(&ch[0].phy_ao.byte[0].shu_b0_dq1, + SHU_B0_DQ1_RG_ARPI_MIDPI_8PH_DLY_B0); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_stbcal, + MISC_SHU_STBCAL_STBCALEN, 0x0, + MISC_SHU_STBCAL_STB_SELPHCALEN, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq11, + SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B0, 0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq11, + SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B1, 0); + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd11, + SHU_CA_CMD11_RG_RX_ARCA_RANK_SEL_SER_EN_CA, 0); + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_dll1, + SHU_CA_DLL1_RG_ARDLL_PHDET_EN_CA, 0x0, + SHU_CA_DLL1_RG_ARDLL_PHDET_OUT_SEL_CA, 0x0); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dll1, + SHU_B0_DLL1_RG_ARDLL_PHDET_EN_B0, 0x0, + SHU_B0_DLL1_RG_ARDLL_PHDET_OUT_SEL_B0, 0x0); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dll1, + SHU_B1_DLL1_RG_ARDLL_PHDET_EN_B1, 0x0, + SHU_B1_DLL1_RG_ARDLL_PHDET_OUT_SEL_B1, 0x0); + } + SET32_BITFIELDS(&ch[0].phy_ao.misc_ctrl1, MISC_CTRL1_R_DMDQSIENCG_EN, 0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dll_arpi2, + SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B0, 0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dll_arpi2, + SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B1, 0); + SET32_BITFIELDS(&ch[0].phy_ao.misc_dutyscan1, + MISC_DUTYSCAN1_RX_EYE_SCAN_CG_EN, 1); + SET32_BITFIELDS(&ch[0].phy_ao.misc_ctrl4, MISC_CTRL4_R_OPT2_CG_DQSIEN, 0); + SET32_BITFIELDS(&ch[0].phy_ao.misc_stbcal, MISC_STBCAL_DQSIENCG_NORMAL_EN, 0); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq6, + B0_DQ6_RG_RX_ARDQ_EYE_DLY_DQS_BYPASS_B0, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq6, + B1_DQ6_RG_RX_ARDQ_EYE_DLY_DQS_BYPASS_B1, 1); + SET32_BITFIELDS(&ch[0].phy_ao.misc_dutyscan1, MISC_DUTYSCAN1_RX_EYE_SCAN_EN, 1); + SET32_BITFIELDS(&ch[0].phy_ao.misc_dutyscan1, + MISC_DUTYSCAN1_EYESCAN_DQS_SYNC_EN, 0x1, + MISC_DUTYSCAN1_EYESCAN_NEW_DQ_SYNC_EN, 0x1, + MISC_DUTYSCAN1_EYESCAN_DQ_SYNC_EN, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq5, B0_DQ5_RG_RX_ARDQ_EYE_EN_B0, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq5, B1_DQ5_RG_RX_ARDQ_EYE_EN_B1, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq5, B0_DQ5_RG_RX_ARDQ_VREF_EN_B0, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq5, B1_DQ5_RG_RX_ARDQ_VREF_EN_B1, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq3, B0_DQ3_RG_RX_ARDQ_SMT_EN_B0, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq3, B1_DQ3_RG_RX_ARDQ_SMT_EN_B1, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_phy2, B0_PHY2_RG_RX_ARDQS_JM_EN_B0, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_phy2, B1_PHY2_RG_RX_ARDQS_JM_EN_B1, 1); + SET32_BITFIELDS(&ch[0].phy_ao.misc_jmeter, MISC_JMETER_JMTR_EN, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_phy2, B0_PHY2_RG_RX_ARDQS_JM_SEL_B0, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_phy2, B1_PHY2_RG_RX_ARDQS_JM_SEL_B1, 1); + SET32_BITFIELDS(&ch[0].phy_ao.misc_dutyscan1, MISC_DUTYSCAN1_RX_MIOCK_JIT_EN, 1); + SET32_BITFIELDS(&ch[0].phy_ao.misc_dutyscan1, MISC_DUTYSCAN1_RX_EYE_SCAN_EN, 0); + SET32_BITFIELDS(&ch[0].phy_ao.misc_dutyscan1, MISC_DUTYSCAN1_DQSERRCNT_DIS, 0); + + dramc_8_phase_cal_set_best_dly(cali, ph_dly_back); + + for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) + write32(regs_bak[i].addr, regs_bak[i].value); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/44709 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4ccaa8d43b8382cbc64cf82de86ad1ac16cb89a Gerrit-Change-Number: 44709 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

22 hours, 29 minutes

Change in coreboot[master]: soc/mediatek/mt8192: Do dramc init settings

by CK HU (Code Review)

Hello Duan huayang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44700 to review the following change. Change subject: soc/mediatek/mt8192: Do dramc init settings ...................................................................... soc/mediatek/mt8192: Do dramc init settings Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> Change-Id: Ie4877b69de1bfa4ff981d8eb386efbddb9e0f5c2 --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/dramc_pi_basic_api.c A src/soc/mediatek/mt8192/dramc_pi_main.c A src/soc/mediatek/mt8192/dramc_utility.c M src/soc/mediatek/mt8192/emi.c 5 files changed, 242 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/44700/1 diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index dd80beb..e82f182 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -16,6 +16,7 @@ verstage-y += ../common/uart.c romstage-y += ../common/cbmem.c +romstage-y += dramc_pi_main.c dramc_pi_basic_api.c dramc_utility.c romstage-y += emi.c romstage-y += flash_controller.c romstage-y += ../common/gpio.c gpio.c diff --git a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c new file mode 100644 index 0000000..9b1216c --- /dev/null +++ b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/gpio.h> +#include <soc/dramc_pi_api.h> +#include <soc/dramc_register.h> +#include <string.h> +#include <timer.h> + +void global_option_init(struct ddr_cali *cali) +{ +} + +void dfs_init_for_calibration(const struct ddr_cali *cali) +{ +} diff --git a/src/soc/mediatek/mt8192/dramc_pi_main.c b/src/soc/mediatek/mt8192/dramc_pi_main.c new file mode 100644 index 0000000..e2c7500 --- /dev/null +++ b/src/soc/mediatek/mt8192/dramc_pi_main.c @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/dramc_pi_api.h> +#include <soc/dramc_register.h> +#include <soc/mt6359p.h> + +static void set_vcore_voltage_for_each_freq(const struct ddr_cali *cali) +{ + u32 vcore = get_vcore_value(cali); + + dramc_info("Set DRAM vcore voltage to %u\n", vcore); + mt6359p_buck_set_voltage(MT6359P_GPU11, vcore); +} + +static void dramc_calibration_all_channels(struct ddr_cali *cali) +{ +} + +void init_dram(const struct dramc_data *dparam) +{ + u32 bc_bak; + u8 k_shuffle, k_shuffle_end; + u8 pll_mode = 0; + bool first_freq_k = true; + + struct ddr_cali cali = {0}; + struct mr_values mr_value; + const struct ddr_base_info *ddr_info = &dparam->ddr_info; + + cali.pll_mode = &pll_mode; + cali.mr_value = &mr_value; + cali.support_ranks = ddr_info->support_ranks; + cali.cbt_mode[RANK_0] = ddr_info->cbt_mode[RANK_0]; + cali.cbt_mode[RANK_1] = ddr_info->cbt_mode[RANK_1]; + cali.emi_config = &ddr_info->emi_config; + + dramc_set_broadcast(DRAMC_BROADCAST_ON); + + global_option_init(&cali); + bc_bak = dramc_get_broadcast(); + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + dramc_set_broadcast(bc_bak); + + if (ddr_info->config_dvfs == DRAMC_ENABLE_DVFS) + k_shuffle_end = CALI_SEQ_MAX; + else + k_shuffle_end = CALI_SEQ1; + + for (k_shuffle = CALI_SEQ0; k_shuffle < k_shuffle_end; k_shuffle++) { + set_cali_datas(&cali, dparam, k_shuffle); + set_vcore_voltage_for_each_freq(&cali); + dfs_init_for_calibration(&cali); + + dramc_calibration_all_channels(&cali); + + first_freq_k= false; + } +} diff --git a/src/soc/mediatek/mt8192/dramc_utility.c b/src/soc/mediatek/mt8192/dramc_utility.c new file mode 100644 index 0000000..526059a --- /dev/null +++ b/src/soc/mediatek/mt8192/dramc_utility.c @@ -0,0 +1,166 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/dramc_pi_api.h> +#include <soc/dramc_register.h> +#include <soc/infracfg.h> + +struct dfs_frequency_table { + u32 frequency; + dram_freq_grp freq_group; + dram_div_mode div_mode; + dram_dfs_shu shuffle_saved; + vref_cali_mode vref_cali; + u32 vcore; +}; + +static const struct dfs_frequency_table freq_shuffle_table[DRAM_DFS_SHU_MAX] = { + /* frequency freq_group div_mode shuffle_saved vref_cali vcore*/ + [CALI_SEQ0] = {800, DDRFREQ_800, DIV8_MODE, DRAM_DFS_SHU4, VREF_CALI_ON, 650000}, + [CALI_SEQ1] = {1200, DDRFREQ_1200, DIV8_MODE, DRAM_DFS_SHU2, VREF_CALI_ON, 662500}, + [CALI_SEQ2] = {600, DDRFREQ_600, DIV8_MODE, DRAM_DFS_SHU5, VREF_CALI_OFF, 650000}, + [CALI_SEQ3] = {933, DDRFREQ_933, DIV8_MODE, DRAM_DFS_SHU3, VREF_CALI_OFF, 662500}, + [CALI_SEQ4] = {400, DDRFREQ_400, DIV4_MODE, DRAM_DFS_SHU6, VREF_CALI_OFF, 650000}, + [CALI_SEQ5] = {2133, DDRFREQ_2133, DIV8_MODE, DRAM_DFS_SHU0, VREF_CALI_ON, 725000}, + [CALI_SEQ6] = {1600, DDRFREQ_1600, DIV8_MODE, DRAM_DFS_SHU1, VREF_CALI_OFF, 687500}, +}; + +void dramc_set_broadcast(u32 onoff) +{ + write32(&mt8192_infracfg->dramc_wbr, onoff); +} + +u32 dramc_get_broadcast(void) +{ + return read32(&mt8192_infracfg->dramc_wbr); +} + +u8 get_fsp(const struct ddr_cali *cali) +{ + return cali->fsp; +} + +dram_div_mode get_div_mode(const struct ddr_cali *cali) +{ + return cali->div_mode; +} + +dram_freq_grp get_freq_group(const struct ddr_cali *cali) +{ + return cali->freq_group; +} + +dbi_mode get_write_dbi(const struct ddr_cali *cali) +{ + return cali->w_dbi[get_fsp(cali)]; +} + +dram_odt_state get_odt_state(const struct ddr_cali *cali) +{ + return cali->odt_onoff; +} + +dram_dfs_shu get_shu(const struct ddr_cali *cali) +{ + return cali->shu; +} + +dram_cbt_mode get_cbt_mode(const struct ddr_cali *cali) +{ + return cali->cbt_mode[cali->rank]; +} + +u32 get_vcore_value(const struct ddr_cali *cali) +{ + return cali->vcore_voltage; +} + +u32 get_frequency(const struct ddr_cali *cali) +{ + return cali->frequency; +} + +vref_cali_mode get_vref_cali(const struct ddr_cali *cali) +{ + return cali->vref_cali; +} + +dram_pinmux_type get_pinmux_type(const struct ddr_cali *cali) +{ + return cali->pinmux_type; +} + +u8 get_mck2ui_div_shift(const struct ddr_cali *cali) +{ + if (get_div_mode(cali) == DIV4_MODE) + return 2; + else + return 3; +} + +dram_dfs_shu get_shu_save_by_k_shu(dram_cali_seq k_shu) +{ + return freq_shuffle_table[k_shu].shuffle_saved; +} + +dram_freq_grp get_freq_group_by_shu_save(dram_dfs_shu shu) +{ + for (u8 k_shu = CALI_SEQ0; k_shu < CALI_SEQ_MAX; k_shu++) + if (freq_shuffle_table[k_shu].shuffle_saved == shu) + return freq_shuffle_table[k_shu].freq_group; + + dramc_err("Invalid shuffle:%d\n", shu); + return DDRFREQ_800; +} + +u32 get_frequency_by_shu(dram_dfs_shu shu) +{ + for (u8 k_shu = CALI_SEQ0; k_shu < CALI_SEQ_MAX; k_shu++) + if (freq_shuffle_table[k_shu].shuffle_saved == shu) + return freq_shuffle_table[k_shu].frequency; + + dramc_err("Invalid shuffle:%d\n", shu); + return 800; +} + +dram_freq_grp get_highest_freq_group(void) +{ + dram_freq_grp highest_freq = DDRFREQ_800; + + for (u8 k_shu = CALI_SEQ0; k_shu < CALI_SEQ_MAX; k_shu++) + if (freq_shuffle_table[k_shu].freq_group > highest_freq) + highest_freq = freq_shuffle_table[k_shu].freq_group; + + dramc_dbg("Highest freq is :%d\n", highest_freq); + return highest_freq; +} + +void set_cali_datas(struct ddr_cali *cali, const struct dramc_data *dparam, dram_cali_seq k_shu) +{ + cali->chn = CHANNEL_A; + cali->rank = RANK_0; + cali->fsp = (freq_shuffle_table[k_shu].freq_group < DDRFREQ_1600) ? FSP_0 : FSP_1; + cali->w_dbi[FSP_0] = DBI_OFF; + cali->w_dbi[FSP_1] = DBI_ON; + cali->frequency = freq_shuffle_table[k_shu].frequency; + cali->freq_group = freq_shuffle_table[k_shu].freq_group; + cali->div_mode = freq_shuffle_table[k_shu].div_mode; + cali->shu = freq_shuffle_table[k_shu].shuffle_saved; + cali->vref_cali = freq_shuffle_table[k_shu].vref_cali; + cali->vcore_voltage = freq_shuffle_table[k_shu].vcore; + cali->odt_onoff = (cali->fsp == FSP_0) ? ODT_OFF : ODT_ON; + cali->params = &dparam->freq_params[cali->shu]; + + dramc_dbg("cali data(size:%ld) use fsp:%d, freq_group:%d, div_mode:%d, shu:%d, vref_cali:%d, odt_onoff:%d, vcore:%d\n", + sizeof(*cali), cali->fsp, cali->freq_group, cali->div_mode, cali->shu, + cali->vref_cali, cali->odt_onoff, cali->vcore_voltage); +} + +void dramc_auto_refresh_switch(u8 chn, bool enable) +{ + SET32_BITFIELDS(&ch[chn].ao.refctrl0, REFCTRL0_REFDIS, enable ? 0 : 1); + + if (!enable) { + udelay(READ32_BITFIELD(&ch[chn].nao.misc_statusa, + MISC_STATUSA_REFRESH_QUEUE_CNT)); + } +} diff --git a/src/soc/mediatek/mt8192/emi.c b/src/soc/mediatek/mt8192/emi.c index 9e48918..f83acd3 100644 --- a/src/soc/mediatek/mt8192/emi.c +++ b/src/soc/mediatek/mt8192/emi.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/emi.h> +#include <soc/dramc_pi_api.h> size_t sdram_size(void) { @@ -11,4 +11,5 @@ void mt_set_emi(const struct dramc_data *dparam) { + init_dram(dparam); } -- To view, visit https://review.coreboot.org/c/coreboot/+/44700 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie4877b69de1bfa4ff981d8eb386efbddb9e0f5c2 Gerrit-Change-Number: 44700 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

22 hours, 39 minutes

Change in coreboot[master]: util/inteltool: fix Ie00fef5a5ba2779e0ff45640cff5cc9f1d096dc1 on FreeBSD

by Idwer Vollering (Code Review)

Idwer Vollering has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37767 ) Change subject: util/inteltool: fix Ie00fef5a5ba2779e0ff45640cff5cc9f1d096dc1 on FreeBSD ...................................................................... util/inteltool: fix Ie00fef5a5ba2779e0ff45640cff5cc9f1d096dc1 on FreeBSD Change-Id: I4aba72f39b528fd70451a4656fd6c835ff766e49 Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- M util/inteltool/Makefile M util/inteltool/inteltool.h 2 files changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/37767/1 diff --git a/util/inteltool/Makefile b/util/inteltool/Makefile index cd02fa8..918b6ec 100644 --- a/util/inteltool/Makefile +++ b/util/inteltool/Makefile @@ -23,6 +23,7 @@ INSTALL ?= /usr/bin/env install PREFIX ?= /usr/local CFLAGS ?= -O2 -g -Wall -Wextra -Wmissing-prototypes +CFLAGS += -Wno-unused-function LDFLAGS += -lpci -lz CPPFLAGS += -I$(top)/src/commonlib/include diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index fc6dc4b..81ebc72 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -370,7 +370,7 @@ #define rdmsr freebsd_rdmsr #define wrmsr freebsd_wrmsr typedef struct { uint32_t hi, lo; } msr_t; -msr_t freebsd_rdmsr(int addr); +static msr_t freebsd_rdmsr(int addr); int freebsd_wrmsr(int addr, msr_t msr); #endif typedef struct { uint16_t addr; int size; char *name; } io_register_t; -- To view, visit https://review.coreboot.org/c/coreboot/+/37767 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4aba72f39b528fd70451a4656fd6c835ff766e49 Gerrit-Change-Number: 37767 Gerrit-PatchSet: 1 Gerrit-Owner: Idwer Vollering <vidwer(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit August 2020