August 2020 - coreboot-gerrit - mail.coreboot.org

Change in coreboot[master]: [WIP]amdfwtool: Take a config file instead of command line parameters

by Bao Zheng (Code Review)

Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/42859 to review the following change. Change subject: [WIP]amdfwtool: Take a config file instead of command line parameters ...................................................................... [WIP]amdfwtool: Take a config file instead of command line parameters Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M Makefile.inc M src/soc/amd/picasso/Makefile.inc A src/soc/amd/picasso/fw.cfg M util/amdfwtool/Makefile A util/amdfwtool/Makefile.inc M util/amdfwtool/amdfwtool.c A util/amdfwtool/amdfwtool.h A util/amdfwtool/amdfwtool.sh A util/amdfwtool/data_parse.c A util/amdfwtool/sample.txt 10 files changed, 899 insertions(+), 142 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/42859/1 diff --git a/Makefile.inc b/Makefile.inc index bbb6685..0e10136 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -81,7 +81,7 @@ subdirs-y += src/superio subdirs-y += $(wildcard src/drivers/*) $(wildcard src/drivers/*/*) subdirs-y += src/cpu src/vendorcode -subdirs-y += util/cbfstool util/sconfig util/nvramtool util/pgtblgen +subdirs-y += util/cbfstool util/sconfig util/nvramtool util/pgtblgen util/amdfwtool subdirs-y += util/futility util/marvell util/bincfg util/supermicro subdirs-y += $(wildcard src/arch/*) subdirs-y += src/mainboard/$(MAINBOARDDIR) @@ -566,9 +566,9 @@ cp -a $(top)/util/ifdtool/ifdtool $@ AMDFWTOOL:=$(objutil)/amdfwtool/amdfwtool -$(AMDFWTOOL): $(top)/util/amdfwtool/amdfwtool.c - @printf " HOSTCC $(subst $(obj)/,,$(@))\n" - $(HOSTCC) $(HOSTCFLAGS) -DCONFIG_ROM_SIZE=$(CONFIG_ROM_SIZE) -o $@ $< +#$(AMDFWTOOL): $(top)/util/amdfwtool/amdfwtool.c +# @printf " HOSTCC $(subst $(obj)/,,$(@))\n" +# $(HOSTCC) $(HOSTCFLAGS) -DCONFIG_ROM_SIZE=$(CONFIG_ROM_SIZE) -o $@ $< APCB_EDIT_TOOL:=$(top)/util/apcb/apcb_edit.py @@ -666,7 +666,7 @@ include util/crossgcc/Makefile.inc .PHONY: tools -tools: $(objutil)/kconfig/conf $(objutil)/kconfig/toada $(CBFSTOOL) $(objutil)/cbfstool/cbfs-compression-tool $(FMAPTOOL) $(RMODTOOL) $(IFWITOOL) $(objutil)/nvramtool/nvramtool $(objutil)/sconfig/sconfig $(IFDTOOL) $(CBOOTIMAGE) $(AMDFWTOOL) $(AMDCOMPRESS) $(FUTILITY) $(BINCFG) $(IFITTOOL) $(objutil)/supermicro/smcbiosinfo +tools: $(objutil)/kconfig/conf $(objutil)/kconfig/toada $(CBFSTOOL) $(objutil)/cbfstool/cbfs-compression-tool $(FMAPTOOL) $(RMODTOOL) $(IFWITOOL) $(objutil)/nvramtool/nvramtool $(objutil)/sconfig/sconfig $(IFDTOOL) $(CBOOTIMAGE) $(objutil)/amdfwtool/amdfwtool $(AMDCOMPRESS) $(FUTILITY) $(BINCFG) $(IFITTOOL) $(objutil)/supermicro/smcbiosinfo ########################################################################### # Common recipes for all stages @@ -1094,7 +1094,6 @@ endif $(obj)/coreboot.rom: $(obj)/coreboot.pre $(RAMSTAGE) $(CBFSTOOL) $$(INTERMEDIATE) - @printf " CBFS $(subst $(obj)/,,$(@))\n" # The full ROM may be larger than the CBFS part, so create an empty # file (filled with \377 = 0xff) and copy the CBFS image over it. diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 39269e9..20fb5c2 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -378,14 +378,6 @@ rm -f $@ @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" $(AMDFWTOOL) \ - $(OPT_AMD_PUBKEY_FILE) \ - $(OPT_PSPBTLDR_FILE) \ - $(OPT_PSPSCUREOS_FILE) \ - $(OPT_PSP_SEC_DBG_KEY_FILE) \ - $(OPT_SMUFW1_SUB2_FILE) \ - $(OPT_SMUFW2_SUB2_FILE) \ - $(OPT_SMUFW1_SUB1_FILE) \ - $(OPT_SMUFW2_SUB1_FILE) \ $(OPT_PSP_APCB_FILES) \ $(OPT_APOB_ADDR) \ --apob-nv-size $(shell printf "0x%x" \ @@ -398,38 +390,18 @@ $(OPT_PSP_BIOSBIN_DEST) \ $(OPT_PSP_BIOSBIN_SIZE) \ $(OPT_PSP_SOFTFUSE) \ - $(OPT_PSP_PMUI_FILE1) \ - $(OPT_PSP_PMUI_FILE2) \ - $(OPT_PSP_PMUI_FILE3) \ - $(OPT_PSP_PMUI_FILE4) \ - $(OPT_PSP_PMUD_FILE1) \ - $(OPT_PSP_PMUD_FILE2) \ - $(OPT_PSP_PMUD_FILE3) \ - $(OPT_PSP_PMUD_FILE4) \ - $(OPT_MP2CFG_FILE) \ - $(OPT_ABL0_FILE) \ - $(OPT_ABL1_FILE) \ - $(OPT_ABL2_FILE) \ - $(OPT_ABL3_FILE) \ - $(OPT_ABL4_FILE) \ - $(OPT_ABL5_FILE) \ - $(OPT_ABL6_FILE) \ - $(OPT_ABL7_FILE) \ $(OPT_WHITELIST_FILE) \ - $(OPT_SECG1_FILE) \ - $(OPT_SECG2_FILE) \ - $(OPT_MP2FW1_FILE) \ - $(OPT_MP2FW2_FILE) \ - $(OPT_DRIVERS_FILE) \ - $(OPT_PSP_S0I3_FILE) \ - $(OPT_IKEK_FILE) \ $(OPT_SEC_DEBUG_FILE) \ + --config $(FIRMWARE_LOCATE)/fw.cfg \ --combo-capable \ $(OPT_TOKEN_UNLOCK) \ --flashsize $(CONFIG_ROM_SIZE) \ --location $(shell printf "0x%x" $(PICASSO_FWM_POSITION)) \ --output $@ +# --config /home/baozheng/x86/coreboot-gerrit/src/soc/amd/picasso/fw.cfg \ + + $(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS) rm -f $@ @printf " AMDCOMPRS $(subst $(obj)/,,$(@))\n" diff --git a/src/soc/amd/picasso/fw.cfg b/src/soc/amd/picasso/fw.cfg new file mode 100644 index 0000000..f5b9d13 --- /dev/null +++ b/src/soc/amd/picasso/fw.cfg @@ -0,0 +1,46 @@ +# sample PSP fw config file +# Move to amd_blob +# type file +AMD_PUBKEY_FILE AmdPubKeyRV.bin +PSPBTLDR_FILE PspBootLoader_prod_RV.sbin +#PUBSIGNEDKEY_FILE RtmPubSignedRV.key +PSP_SMUFW1_SUB1_FILE SmuFirmwareRV2.csbin +PSP_SMUFW1_SUB2_FILE SmuFirmwarePCO.csbin +PSP_SMUFW2_SUB1_FILE SmuFirmware2RV2.csbin +PSP_SMUFW2_SUB2_FILE SmuFirmware2PCO.csbin +PSPSCUREOS_FILE psp_os_combined_prod_RV.sbin +#PSPTRUSTLETS_FILE dr_ftpm_prod_RV.csbin +#PSP_SEC_DBG_KEY_FILE RavenSecureDebug_PublicKey.bin +PSPSCUREOS_FILE psp_os_combined_prod_RV.sbin +PSP_ABL0_FILE AgesaBootloader0_prod_RV.csbin +PSP_ABL1_FILE AgesaBootloader1_prod_RV.csbin +PSP_ABL2_FILE AgesaBootloader2_prod_RV.csbin +PSP_ABL3_FILE AgesaBootloader3_prod_RV.csbin +PSP_ABL4_FILE AgesaBootloader4_prod_RV.csbin +PSP_ABL5_FILE AgesaBootloader5_prod_RV.csbin +PSP_ABL6_FILE AgesaBootloader6_prod_RV.csbin +PSP_ABL7_FILE AgesaBootloader7_prod_RV.csbin +#PSP_SEC_DEBUG_FILE secure_unlock_prod_RV.sbin +PSP_IKEK_FILE PspIkekRV.bin +PSP_SECG1_FILE security_policy_RV2_FP5_AM4.sbin +PSP_SECG2_FILE security_policy_PCO_FP5_AM4.sbin +#PSP_MP2FW1_FILE MP2I2CFWRV2.sbin +#PSP_MP2FW2_FILE MP2I2CFWPCO.sbin +#PSP_MP2CFG_FILE MP2FWConfig.sbin +PSP_DRIVERS_FILE drv_sys_prod_RV.sbin +#PSP_SOFTFUSE 0x0000000010000001 +#PSP_S0I3_FILE dr_agesa_prod_RV.sbin +#PSP_APOBNV_BASE +#PSP_APOBNV_SIZE +# +## BDT +#PSP_APCB0_FILE apcb.bin +PSP_PMUI_FILE1 Appb_Rv_1D_Ddr4_Udimm_Imem.csbin +PSP_PMUI_FILE2 Appb_Rv_2D_Ddr4_Imem.csbin +PSP_PMUI_FILE3 Appb_Rv2_1D_ddr4_Udimm_Imem.csbin +PSP_PMUI_FILE4 Appb_Rv2_2D_ddr4_Udimm_Imem.csbin +PSP_PMUD_FILE1 Appb_Rv_1D_Ddr4_Udimm_Dmem.csbin +PSP_PMUD_FILE2 Appb_Rv_2D_Ddr4_Dmem.csbin +PSP_PMUD_FILE3 Appb_Rv2_1D_ddr4_Udimm_Dmem.csbin +PSP_PMUD_FILE4 Appb_Rv2_2D_ddr4_Udimm_Dmem.csbin +#PSP_MP2CFG_FILE MP2FWConfig.sbin diff --git a/util/amdfwtool/Makefile b/util/amdfwtool/Makefile index e9fd91b..9f7a01b 100644 --- a/util/amdfwtool/Makefile +++ b/util/amdfwtool/Makefile @@ -2,15 +2,47 @@ # # All rights reserved. # -# SPDX-License-Identifier: BSD-3-Clause - +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# * Neither the name of Advanced Micro Devices, Inc. nor the names of +# its contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# #***************************************************************************** HOSTCC ?= cc -amdfwtool_exe : amdfwtool.c - $(HOSTCC) amdfwtool.c -o amdfwtool +SRC = amdfwtool.c data_parse.c +OBJ = $(SRC:%.c=%.o) +TARGET = amdfwtool +CFLAGS=-O2 -Wall -Wextra -Wshadow -Wno-sign-compare -amdfwtool : amdfwtool_exe + +$(TARGET): $(OBJ) + $(CC) $(OBJ) $(LDFLAGS) -o $@ + +%.o: %.c $(HEADER) + $(CC) $(CFLAGS) -c -o $@ $< + +amdfwtool_exe : $(TARGET) +# $(HOSTCC) amdfwtool.c -o amdfwtool +# +#amdfwtool : amdfwtool_exe clean: - @rm -f amdfwtool.o amdfwtool amdfwtool.exe + rm -f $(TARGET) $(OBJ) diff --git a/util/amdfwtool/Makefile.inc b/util/amdfwtool/Makefile.inc new file mode 100644 index 0000000..36ff207d --- /dev/null +++ b/util/amdfwtool/Makefile.inc @@ -0,0 +1,52 @@ +#***************************************************************************** +# +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# * Neither the name of Advanced Micro Devices, Inc. nor the names of +# its contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +#***************************************************************************** +#HOSTCC ?= cc + +amdfwtoolobj = amdfwtool.o data_parse.o + +#TARGET = $(objutil)/amdfwtool/amdfwtool +AMDFWTOOLCFLAGS=-O2 -Wall -Wextra -Wshadow -Wno-sign-compare + + +#$(TARGET): $(OBJ) +# $(CC) $(OBJ) $(LDFLAGS) -o $@ + +$(objutil)/amdfwtool/%.o: $(top)/util/amdfwtool/%.c # $(HEADER) + printf " AMDFWTOOL\n" + $(HOSTCC) $(AMDFWTOOLCFLAGS) $(HOSTCFLAGS) -c -o $@ $< + +#amdfwtool_exe : $(TARGET) +# $(HOSTCC) amdfwtool.c -o amdfwtool +# +#amdfwtool : amdfwtool_exe + +#clean: +# rm -f $(TARGET) $(OBJ) +$(objutil)/amdfwtool/amdfwtool: $(addprefix $(objutil)/amdfwtool/,$(amdfwtoolobj)) + printf " AMDFWTOOL\n" + $(HOSTCC) $(addprefix $(objutil)/amdfwtool/,$(amdfwtoolobj)) -o $@ diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index a5e5110..eb0cae8 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -56,6 +56,9 @@ #include <string.h> #include <stdlib.h> #include <getopt.h> +#include <libgen.h> + +#include "amdfwtool.h" #ifndef CONFIG_ROM_SIZE #define CONFIG_ROM_SIZE 0x400000 @@ -98,13 +101,6 @@ */ #define PSP_COMBO 0 -#if defined(__GLIBC__) -typedef unsigned long long int uint64_t; -typedef unsigned int uint32_t; -typedef unsigned char uint8_t; -typedef unsigned short uint16_t; -#endif - /* * Creates the OSI Fletcher checksum. See 8473-1, Appendix C, section C.3. * The checksum field of the passed PDU does not need to be reset to zero. @@ -216,92 +212,11 @@ printf("-R | --sharedmem Location of PSP/FW shared memory\n"); printf("-P | --sharedmem-size Maximum size of the PSP/FW shared memory area\n"); printf("-h | --help show this help\n"); + printf("-C | --config config file\n"); } -typedef enum _amd_bios_type { - AMD_BIOS_APCB = 0x60, - AMD_BIOS_APOB = 0x61, - AMD_BIOS_BIN = 0x62, - AMD_BIOS_APOB_NV = 0x63, - AMD_BIOS_PMUI = 0x64, - AMD_BIOS_PMUD = 0x65, - AMD_BIOS_UCODE = 0x66, - AMD_BIOS_APCB_BK = 0x68, - AMD_BIOS_MP2_CFG = 0x6a, - AMD_BIOS_PSP_SHARED_MEM = 0x6b, - AMD_BIOS_L2_PTR = 0x70, - AMD_BIOS_INVALID, -} amd_bios_type; -#define BDT_LVL1 0x1 -#define BDT_LVL2 0x2 -#define BDT_BOTH (BDT_LVL1 | BDT_LVL2) -typedef struct _amd_bios_entry { - amd_bios_type type; - int region_type; - int reset; - int copy; - int ro; - int zlib; - int inst; - int subpr; - uint64_t src; - uint64_t dest; - size_t size; - char *filename; - int level; -} amd_bios_entry; - -typedef enum _amd_fw_type { - AMD_FW_PSP_PUBKEY = 0, - AMD_FW_PSP_BOOTLOADER = 1, - AMD_FW_PSP_SMU_FIRMWARE = 8, - AMD_FW_PSP_RECOVERY = 3, - AMD_FW_PSP_RTM_PUBKEY = 5, - AMD_FW_PSP_SECURED_OS = 2, - AMD_FW_PSP_NVRAM = 4, - AMD_FW_PSP_SECURED_DEBUG = 9, - AMD_FW_PSP_TRUSTLETS = 12, - AMD_FW_PSP_TRUSTLETKEY = 13, - AMD_FW_PSP_SMU_FIRMWARE2 = 18, - AMD_PSP_FUSE_CHAIN = 11, - AMD_FW_PSP_SMUSCS = 95, - AMD_DEBUG_UNLOCK = 0x13, - AMD_WRAPPED_IKEK = 0x21, - AMD_TOKEN_UNLOCK = 0x22, - AMD_SEC_GASKET = 0x24, - AMD_MP2_FW = 0x25, - AMD_DRIVER_ENTRIES = 0x28, - AMD_S0I3_DRIVER = 0x2d, - AMD_ABL0 = 0x30, - AMD_ABL1 = 0x31, - AMD_ABL2 = 0x32, - AMD_ABL3 = 0x33, - AMD_ABL4 = 0x34, - AMD_ABL5 = 0x35, - AMD_ABL6 = 0x36, - AMD_ABL7 = 0x37, - AMD_FW_PSP_WHITELIST = 0x3a, - AMD_FW_L2_PTR = 0x40, - AMD_FW_PSP_VERSTAGE = 0x52, - AMD_FW_IMC, - AMD_FW_GEC, - AMD_FW_XHCI, - AMD_FW_INVALID, -} amd_fw_type; - -#define PSP_LVL1 0x1 -#define PSP_LVL2 0x2 -#define PSP_BOTH (PSP_LVL1 | PSP_LVL2) -typedef struct _amd_fw_entry { - amd_fw_type type; - uint8_t subprog; - char *filename; - int level; - uint64_t other; -} amd_fw_entry; - -static amd_fw_entry amd_psp_fw_table[] = { +/* static */ amd_fw_entry amd_psp_fw_table[] = { { .type = AMD_FW_PSP_PUBKEY, .level = PSP_BOTH }, { .type = AMD_FW_PSP_BOOTLOADER, .level = PSP_BOTH }, { .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 0, .level = PSP_BOTH }, @@ -343,14 +258,14 @@ { .type = AMD_FW_INVALID }, }; -static amd_fw_entry amd_fw_table[] = { +amd_fw_entry amd_fw_table[] = { { .type = AMD_FW_XHCI }, { .type = AMD_FW_IMC }, { .type = AMD_FW_GEC }, { .type = AMD_FW_INVALID }, }; -static amd_bios_entry amd_bios_table[] = { +amd_bios_entry amd_bios_table[] = { { .type = AMD_BIOS_APCB, .inst = 0, .level = BDT_BOTH }, { .type = AMD_BIOS_APCB, .inst = 1, .level = BDT_BOTH }, { .type = AMD_BIOS_APCB, .inst = 2, .level = BDT_BOTH }, @@ -658,6 +573,28 @@ } } +static void dump_psp_firmwares(amd_fw_entry *fw_table) +{ + amd_fw_entry *index; + + for (index = fw_table; index->type != AMD_FW_INVALID; index++) { + printf("type=%x\n", index->type); + if (index->filename) + printf (" filename=%s\n", index->filename); + } +} + +static void dump_bdt_firmwares(amd_bios_entry *fw_table) +{ + amd_bios_entry *index; + + for (index = fw_table; index->type != AMD_BIOS_INVALID; index++) { + printf("type=%x\n", index->type); + if (index->filename) + printf (" filename=%s\n", index->filename); + } +} + static void integrate_psp_firmwares(context *ctx, psp_directory_table *pspdir, psp_directory_table *pspdir2, @@ -1039,7 +976,7 @@ fill_dir_header(biosdir, count, cookie); } // Unused values: CDE -static const char *optstring = "x:i:g:AMS:p:b:s:r:k:c:n:d:t:u:w:m:T:z:J:B:K:L:Y:N:UW:I:a:Q:V:e:v:j:y:G:O:X:F:H:o:f:l:hZ:qR:P:"; +static const char *optstring = "x:i:g:AMS:p:b:s:r:k:c:n:d:t:u:w:m:T:z:J:B:K:L:Y:N:UW:I:a:Q:V:e:v:j:y:G:O:X:F:H:o:f:l:hZ:qR:P:C"; static struct option long_options[] = { {"xhci", required_argument, 0, 'x' }, @@ -1087,6 +1024,7 @@ {"apob-nv-base", required_argument, 0, 'F' }, {"apob-nv-size", required_argument, 0, 'H' }, /* other */ + {"config", required_argument, 0, 'C' }, {"output", required_argument, 0, 'o' }, {"flashsize", required_argument, 0, 'f' }, {"location", required_argument, 0, 'l' }, @@ -1097,7 +1035,7 @@ {NULL, 0, 0, 0 } }; -static void register_fw_fuse(char *str) +void register_fw_fuse(char *str) { int i; @@ -1145,6 +1083,40 @@ } } +static int register_fw_fuses(int fd, char *dir) +{ + struct stat fd_stat; + unsigned char *config_file; + +// fd = open(, O_RDONLY); +// if (fd < 0) { +// printf("Error opening file: %s: %s\n", +// src_file, strerror(errno)); +// return -1; +// } + + if (fstat(fd, &fd_stat)) { + printf("fstat error 1: %s\n", strerror(errno)); + close(fd); + return -2; + } + + //if (fd_stat.st_size > room) { + // printf("Error: %s will not fit. Exiting.\n", src_file); + // close(fd); + // return -3; + //} + + config_file = malloc (fd_stat.st_size+1); + read(fd, config_file, (size_t)fd_stat.st_size); + + config_file[fd_stat.st_size+1] = '\0'; + + process_config(config_file, dir); + printf("fuse written=[%s,%d] %x\n", __func__, __LINE__, amd_psp_fw_table[16].other); +} + + static void register_bdt_data(amd_bios_type type, int sub, int ins, char name[]) { int i; @@ -1188,8 +1160,8 @@ psp_directory_table *pspdir; int comboable = 0; int fuse_defined = 0; - int targetfd; - char *output = NULL; + int targetfd, configfd; + char *output = NULL, *config = NULL; context ctx = { .rom_size = CONFIG_ROM_SIZE, }; @@ -1427,6 +1399,9 @@ sub = instance = 0; break; + case 'C': + config = optarg; + break; case 'h': usage(); return 0; @@ -1434,9 +1409,29 @@ break; } } + #if 1 + if (!config) { + printf("Error: config file is not specified.\n\n"); + retval = 1; + } - if (!fuse_defined) - register_fw_fuse(DEFAULT_SOFT_FUSE_CHAIN); + configfd = open(config, O_RDONLY); + + if (configfd >=0) { + printf("%s opened\n", config); + register_fw_fuses(configfd, dirname(config)); + } else { + printf("open failed\n"); + } + + + dump_psp_firmwares(amd_psp_fw_table); + dump_bdt_firmwares(amd_bios_table); + printf("close config file\n"); + close (configfd); +#endif + //if (!fuse_defined) + // register_fw_fuse(DEFAULT_SOFT_FUSE_CHAIN); if (!output) { printf("Error: Output value is not specified.\n\n"); @@ -1571,6 +1566,7 @@ amd_romsig->bios1_entry = BUFF_TO_RUN(ctx, biosdir); } + /* TODO:Free the filename. */ targetfd = open(output, O_RDWR | O_CREAT | O_TRUNC, 0666); if (targetfd >= 0) { write(targetfd, amd_romsig, ctx.current - romsig_offset); diff --git a/util/amdfwtool/amdfwtool.h b/util/amdfwtool/amdfwtool.h new file mode 100644 index 0000000..fda41b2 --- /dev/null +++ b/util/amdfwtool/amdfwtool.h @@ -0,0 +1,98 @@ +#ifndef _AMD_FW_TOOL_H_ +#define _AMD_FW_TOOL_H_ +#if defined(__GLIBC__) +typedef unsigned long long int uint64_t; +typedef unsigned int uint32_t; +typedef unsigned char uint8_t; +typedef unsigned short uint16_t; +#endif + + +typedef enum _amd_fw_type { + AMD_FW_PSP_PUBKEY = 0, + AMD_FW_PSP_BOOTLOADER = 1, + AMD_FW_PSP_SMU_FIRMWARE = 8, + AMD_FW_PSP_RECOVERY = 3, + AMD_FW_PSP_RTM_PUBKEY = 5, + AMD_FW_PSP_SECURED_OS = 2, + AMD_FW_PSP_NVRAM = 4, + AMD_FW_PSP_SECURED_DEBUG = 9, + AMD_FW_PSP_TRUSTLETS = 12, + AMD_FW_PSP_TRUSTLETKEY = 13, + AMD_FW_PSP_SMU_FIRMWARE2 = 18, + AMD_PSP_FUSE_CHAIN = 11, + AMD_FW_PSP_SMUSCS = 95, + AMD_DEBUG_UNLOCK = 0x13, + AMD_WRAPPED_IKEK = 0x21, + AMD_TOKEN_UNLOCK = 0x22, + AMD_SEC_GASKET = 0x24, + AMD_MP2_FW = 0x25, + AMD_DRIVER_ENTRIES = 0x28, + AMD_S0I3_DRIVER = 0x2d, + AMD_ABL0 = 0x30, + AMD_ABL1 = 0x31, + AMD_ABL2 = 0x32, + AMD_ABL3 = 0x33, + AMD_ABL4 = 0x34, + AMD_ABL5 = 0x35, + AMD_ABL6 = 0x36, + AMD_ABL7 = 0x37, + AMD_FW_PSP_WHITELIST = 0x3a, + AMD_FW_L2_PTR = 0x40, + AMD_FW_PSP_VERSTAGE = 0x52, + AMD_FW_IMC, + AMD_FW_GEC, + AMD_FW_XHCI, + AMD_FW_INVALID, +} amd_fw_type; + +typedef enum _amd_bios_type { + AMD_BIOS_APCB = 0x60, + AMD_BIOS_APOB = 0x61, + AMD_BIOS_BIN = 0x62, + AMD_BIOS_APOB_NV = 0x63, + AMD_BIOS_PMUI = 0x64, + AMD_BIOS_PMUD = 0x65, + AMD_BIOS_UCODE = 0x66, + AMD_BIOS_APCB_BK = 0x68, + AMD_BIOS_MP2_CFG = 0x6a, + AMD_BIOS_PSP_SHARED_MEM = 0x6b, + AMD_BIOS_L2_PTR = 0x70, + AMD_BIOS_INVALID, +} amd_bios_type; + + +#define BDT_LVL1 0x1 +#define BDT_LVL2 0x2 +#define BDT_BOTH (BDT_LVL1 | BDT_LVL2) +typedef struct _amd_bios_entry { + amd_bios_type type; + char *filename; + int subpr; + int region_type; + int reset; + int copy; + int ro; + int zlib; + int inst; + uint64_t src; + uint64_t dest; + size_t size; + int level; +} amd_bios_entry; + + +#define PSP_LVL1 0x1 +#define PSP_LVL2 0x2 +#define PSP_BOTH (PSP_LVL1 | PSP_LVL2) +typedef struct _amd_fw_entry { + amd_fw_type type; + char *filename; + uint8_t subprog; + int level; + uint64_t other; +} amd_fw_entry; + +void register_fw_fuse(char *str); + +#endif diff --git a/util/amdfwtool/amdfwtool.sh b/util/amdfwtool/amdfwtool.sh new file mode 100644 index 0000000..50006f8 --- /dev/null +++ b/util/amdfwtool/amdfwtool.sh @@ -0,0 +1,60 @@ +#!/bin/sh + +# --pubkey ../../3rdparty/blobs/soc/amd/picasso/PSP/AmdPubKeyRV.bin \ +# --bootloader /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//PspBootLoader_prod_RV.sbin \ +# --rtmpubkey /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//RtmPubSignedRV.key \ +# --secureos /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//psp_os_combined_prod_RV.sbin \ +# --securedebug /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//RavenSecureDebug_PublicKey.bin \ + +# --trustlets /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//dr_ftpm_prod_RV.csbin \ +# --subprogram 2 --smufirmware /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//SmuFirmwarePCO.csbin \ +# --subprogram 2 --smufirmware2 /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//SmuFirmware2PCO.csbin \ +# --subprogram 1 --smufirmware /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//SmuFirmwareRV2.csbin \ +# --subprogram 1 --smufirmware2 /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//SmuFirmware2RV2.csbin \ + +# --soft-fuse 0x0000000010000001 \ +# --subprogram 0 --instance 1 --pmu-inst /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//Appb_Rv_1D_Ddr4_Udimm_Imem.csbin \ +# --subprogram 0 --instance 4 --pmu-inst /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//Appb_Rv_2D_Ddr4_Imem.csbin \ +# --subprogram 1 --instance 1 --pmu-inst /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//Appb_Rv2_1D_ddr4_Udimm_Imem.csbin \ +# --subprogram 1 --instance 4 --pmu-inst /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//Appb_Rv2_2D_ddr4_Udimm_Imem.csbin \ +# --subprogram 0 --instance 1 --pmu-data /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//Appb_Rv_1D_Ddr4_Udimm_Dmem.csbin \ +# --subprogram 0 --instance 4 --pmu-data /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//Appb_Rv_2D_Ddr4_Dmem.csbin \ +# --subprogram 1 --instance 1 --pmu-data /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//Appb_Rv2_1D_ddr4_Udimm_Dmem.csbin \ +# --subprogram 1 --instance 4 --pmu-data /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//Appb_Rv2_2D_ddr4_Udimm_Dmem.csbin \ +# --mp2-config /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//MP2FWConfig.sbin \ +# --abl-image /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//AgesaBootloader0_prod_RV.csbin \ +# --abl-image /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//AgesaBootloader1_prod_RV.csbin \ +# --abl-image /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//AgesaBootloader2_prod_RV.csbin \ +# --abl-image /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//AgesaBootloader3_prod_RV.csbin \ +# --abl-image /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//AgesaBootloader4_prod_RV.csbin \ +# --abl-image /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//AgesaBootloader5_prod_RV.csbin \ +# --abl-image /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//AgesaBootloader6_prod_RV.csbin \ +# --abl-image /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//AgesaBootloader7_prod_RV.csbin \ +# --subprog 1 --sec-gasket /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//security_policy_RV2_FP5_AM4.sbin \ +# --subprog 2 --sec-gasket /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//security_policy_PCO_FP5_AM4.sbin \ +# --subprog 1 --mp2-fw /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//MP2I2CFWRV2.sbin \ +# --subprog 2 --mp2-fw /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//MP2I2CFWPCO.sbin \ +# --drv-entry-pts /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//drv_sys_prod_RV.sbin \ +# --ikek /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//PspIkekRV.bin \ +# --secdebug /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//secure_unlock_prod_RV.sbin \ + +./amdfwtool \ + --instance 0 --apcb ../../3rdparty/blobs/mainboard/amd/mandolin/apcb.bin \ + \ + \ + \ + \ + --apob-base 0x9f00000 \ + \ + --apob-nv-size 0x1000 \ + --bios-bin amd_biospsp.img \ + --bios-bin-dest 8078000 \ + --bios-uncomp-size 0x8000 \ + \ + \ + --combo-capable \ + --token-unlock \ + --flashsize 0x00800000 \ + --location 0xff820000 \ + --config sample.txt \ + --output amdfw.rom diff --git a/util/amdfwtool/data_parse.c b/util/amdfwtool/data_parse.c new file mode 100644 index 0000000..03f1a7f --- /dev/null +++ b/util/amdfwtool/data_parse.c @@ -0,0 +1,457 @@ +#include <stdio.h> +#include <regex.h> +#include <string.h> + +#include "amdfwtool.h" + +/* TODO: a empty line does not matched. */ +static const char blank_or_comment_regex[] = + /* a blank line */ + "(^[[:space:]]*$)" "|" /* or ... */ + /* a line consisting of: optional whitespace followed by */ + "(^[[:space:]]*" + /* a '#' character and optionally, additional characters */ + "#.*$)"; +static regex_t blank_or_comment_expr; + +static const char entries_line_regex[] = + /* optional whitespace */ + "^[[:space:]]*" + /* followed by a chunk of nonwhitespace for macro field */ + "([^[:space:]]+)" + /* followed by one or more whitespace characters */ + "[[:space:]]+" + /* followed by a chunk of nonwhitespace for filename field */ + "([^[:space:]]+)" + /* followed by optional whitespace */ + "[[:space:]]*$"; +static regex_t entries_line_expr; + +static const char entries_subprog_line_regex[] = + /* optional whitespace */ + "^[[:space:]]*" + /* followed by a chunk of nonwhitespace for macro field */ + "([^[:space:]]+)" + /* followed by one or more whitespace characters */ + "[[:space:]]+" + /* followed by a chunk of nonwhitespace for filename field */ + "([^[:space:]]+)" + /* followed by one or more whitespace characters */ + "[[:space:]]+" + /* followed by a chunk of nonwhitespace for filename field */ + "([^[:space:]]+)" + /* followed by optional whitespace */ + "[[:space:]]*$"; +static regex_t entries_subprog_line_expr; + +void compile_reg_expr(int cflags, const char *expr, regex_t *reg) +{ + static const size_t ERROR_BUF_SIZE = 256; + char error_msg[ERROR_BUF_SIZE]; + int result; + + if ((result = regcomp(reg, expr, cflags)) != 0) { + regerror(result, reg, error_msg, ERROR_BUF_SIZE); + printf("%s\n", error_msg); + exit(1); + } +} + +extern amd_fw_entry amd_psp_fw_table[]; +extern amd_bios_entry amd_bios_table[]; +void find_register_fw_filename(char *fw_name, char *filename, uint8_t subprog) +{ + unsigned int fw_type, fw_invalid, fw, entry_size; + void *tableptr; + uint8_t /* subprog = 0, */instance = 0; + + printf("fw_name=%s, fn=%s, subprog=%d\n", fw_name, filename, subprog); + if (strcmp(fw_name, "PSPBTLDR_FILE") == 0) { + fw_type = AMD_FW_PSP_BOOTLOADER; + fw_invalid = AMD_FW_INVALID; + subprog = 0; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); +// printf("fw_type=%x, size=%x\n", fw_type, entry_size); + } else if (strcmp(fw_name, "AMD_PUBKEY_FILE") == 0) { + fw_type = AMD_FW_PSP_PUBKEY; + fw_invalid = AMD_FW_INVALID; + subprog = 0; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); +// printf("fw_type=%x, size=%x\n", fw_type, entry_size); + } else if (strcmp(fw_name, "PUBSIGNEDKEY_FILE") == 0) { + fw_type = AMD_FW_PSP_RTM_PUBKEY; + fw_invalid = AMD_FW_INVALID; + subprog = 0; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSP_SMUFW1_SUB1_FILE") == 0) { + fw_type = AMD_FW_PSP_SMU_FIRMWARE; + subprog = 1; + instance = 0; + fw_invalid = AMD_FW_INVALID; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSP_SMUFW1_SUB2_FILE") == 0) { + fw_type = AMD_FW_PSP_SMU_FIRMWARE; + subprog = 2; + instance = 0; + fw_invalid = AMD_FW_INVALID; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSP_SMUFW2_SUB1_FILE") == 0) { + fw_type = AMD_FW_PSP_SMU_FIRMWARE2; + fw_invalid = AMD_FW_INVALID; + subprog = 1; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSP_SMUFW2_SUB2_FILE") == 0) { + fw_type = AMD_FW_PSP_SMU_FIRMWARE2; + fw_invalid = AMD_FW_INVALID; + subprog = 2; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSP_SEC_DBG_KEY_FILE") == 0) { + fw_type = AMD_FW_PSP_SECURED_DEBUG; + fw_invalid = AMD_FW_INVALID; + subprog = 0; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSP_ABL0_FILE") == 0) { + fw_type = AMD_ABL0; + fw_invalid = AMD_FW_INVALID; + subprog = 0; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSP_ABL1_FILE") == 0) { + fw_type = AMD_ABL1; + fw_invalid = AMD_FW_INVALID; + subprog = 0; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSP_ABL2_FILE") == 0) { + fw_type = AMD_ABL2; + fw_invalid = AMD_FW_INVALID; + subprog = 0; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSP_ABL3_FILE") == 0) { + fw_type = AMD_ABL3; + fw_invalid = AMD_FW_INVALID; + subprog = 0; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSP_ABL4_FILE") == 0) { + fw_type = AMD_ABL4; + fw_invalid = AMD_FW_INVALID; + subprog = 0; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSP_ABL5_FILE") == 0) { + fw_type = AMD_ABL5; + fw_invalid = AMD_FW_INVALID; + subprog = 0; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSP_ABL6_FILE") == 0) { + fw_type = AMD_ABL6; + fw_invalid = AMD_FW_INVALID; + subprog = 0; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSP_ABL7_FILE") == 0) { + fw_type = AMD_ABL7; + fw_invalid = AMD_FW_INVALID; + subprog = 0; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSPSCUREOS_FILE") == 0) { + fw_type = AMD_FW_PSP_SECURED_OS; + fw_invalid = AMD_FW_INVALID; + subprog = 0; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSPTRUSTLETS_FILE") == 0) { + fw_type = AMD_FW_PSP_TRUSTLETS; + fw_invalid = AMD_FW_INVALID; + subprog = 0; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSP_SEC_DEBUG_FILE") == 0) { + fw_type = AMD_DEBUG_UNLOCK; + fw_invalid = AMD_FW_INVALID; + subprog = 0; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSP_IKEK_FILE") == 0) { + fw_type = AMD_WRAPPED_IKEK; + fw_invalid = AMD_FW_INVALID; + subprog = 0; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSP_SECG1_FILE") == 0) { + fw_type = AMD_SEC_GASKET; + fw_invalid = AMD_FW_INVALID; + subprog = 1; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSP_SECG2_FILE") == 0) { + fw_type = AMD_SEC_GASKET; + fw_invalid = AMD_FW_INVALID; + subprog = 2; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSP_MP2FW1_FILE") == 0) { + fw_type = AMD_MP2_FW; + fw_invalid = AMD_FW_INVALID; + subprog = 1; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSP_MP2FW2_FILE") == 0) { + fw_type = AMD_MP2_FW; + fw_invalid = AMD_FW_INVALID; + subprog = 2; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSP_DRIVERS_FILE") == 0) { + fw_type = AMD_DRIVER_ENTRIES; + fw_invalid = AMD_FW_INVALID; + subprog = 0; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSP_S0I3_FILE") == 0) { + fw_type = AMD_S0I3_DRIVER; + fw_invalid = AMD_FW_INVALID; + subprog = 0; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSP_WHITELIST_FILE") == 0) { + fw_type = AMD_FW_PSP_WHITELIST; + fw_invalid = AMD_FW_INVALID; + subprog = 0; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else { + fw_type = AMD_FW_INVALID; +// return ; + /* TODO: Add more */ + } + +// printf("fw_type=%x, size=%x\n", fw_type, entry_size); + printf("Search and fill the filename\n"); + /* Search and fill the filename */ + while (*(unsigned int *)tableptr != fw_invalid) { + if (*(unsigned int *)tableptr == fw_type && + ((amd_bios_entry *)tableptr)->subpr == subprog) { + printf("type=%d,", *(unsigned int *)tableptr); + printf("found, fn=%s\n", filename); + ((amd_fw_entry *)tableptr)->filename = filename; + break; + } else { +// printf("not found type=%d\n", *(unsigned int *)tableptr); + } + tableptr += entry_size; + } + printf("\n"); + printf("Search and fill the filename 2\n\n"); + #if 1 + if (strcmp(fw_name, "PSP_PMUI_FILE1") == 0) { + fw_type = AMD_BIOS_PMUI; + subprog = 0; + instance = 1; + } else if (strcmp(fw_name, "PSP_PMUI_FILE2") == 0) { + fw_type = AMD_BIOS_PMUI; + subprog = 0; + instance = 4; + } else if (strcmp(fw_name, "PSP_PMUI_FILE3") == 0) { + fw_type = AMD_BIOS_PMUI; + subprog = 1; + instance = 1; + } else if (strcmp(fw_name, "PSP_PMUI_FILE4") == 0) { + fw_type = AMD_BIOS_PMUI; + subprog = 1; + instance = 4; + } else if (strcmp(fw_name, "PSP_PMUD_FILE1") == 0) { + fw_type = AMD_BIOS_PMUD; + subprog = 0; + instance = 1; + } else if (strcmp(fw_name, "PSP_PMUD_FILE2") == 0) { + fw_type = AMD_BIOS_PMUD; + subprog = 0; + instance = 4; + } else if (strcmp(fw_name, "PSP_PMUD_FILE3") == 0) { + fw_type = AMD_BIOS_PMUD; + subprog = 1; + instance = 1; + } else if (strcmp(fw_name, "PSP_PMUD_FILE4") == 0) { + fw_type = AMD_BIOS_PMUD; + subprog = 1; + instance = 4; + } else if (strcmp(fw_name, "PSP_MP2CFG_FILE") == 0) { + fw_type = AMD_BIOS_MP2_CFG; + subprog = 0; + instance = 0; + } else { + fw_type = AMD_BIOS_INVALID; + } + tableptr = (void *)amd_bios_table; + if (fw_type != AMD_BIOS_INVALID) { + while (*(unsigned int *)tableptr != AMD_BIOS_INVALID) { + //printf("%x,%x,%x\n", *(unsigned int *)tableptr, ((amd_bios_entry *)tableptr)->subpr, ((amd_bios_entry *)tableptr)->inst); + if (*(unsigned int *)tableptr == fw_type && + ((amd_bios_entry *)tableptr)->subpr == subprog && + ((amd_bios_entry *)tableptr)->inst == instance) { + ((amd_bios_entry *)tableptr)->filename = filename; + //((amd_bios_entry *)tableptr)->subpr = subprog; + //((amd_bios_entry *)tableptr)->inst = instance; + printf("type=%x,", *(unsigned int *)tableptr); + printf("found, fn=%s\n", filename); + break; + } + tableptr += sizeof (amd_bios_entry); + } + } + + printf("Search and fill the filename 3\n\n"); + if (strcmp(fw_name, "PSP_SOFTFUSE") == 0) { + fw_type = AMD_PSP_FUSE_CHAIN; + } else { + fw_type = AMD_BIOS_INVALID; + } + /* char *filename */ + printf("Search and fill the filename 3.1\n\n"); + tableptr = (void *)amd_psp_fw_table; + if (fw_type != AMD_BIOS_INVALID) { + while (*(unsigned int *)tableptr != AMD_BIOS_INVALID) { + printf("%x,%x,%x\n", *(unsigned int *)tableptr, ((amd_bios_entry *)tableptr)->subpr, ((amd_bios_entry *)tableptr)->inst); + if (*(unsigned int *)tableptr == fw_type) { + //((amd_bios_entry *)tableptr)->filename = filename; + //((amd_bios_entry *)tableptr)->subpr = subprog; + ((amd_fw_entry *)tableptr)->other = strtoull(filename, NULL, 16); + printf("type=%x,", *(unsigned int *)tableptr); + printf("found, fuse=%llx\n", ((amd_fw_entry *)tableptr)->other); + break; + } + tableptr += sizeof (amd_fw_entry); + } + } + printf("fuse written=[] %x\n", amd_psp_fw_table[16].other); + + printf("Search and fill the filename 3.9\n\n"); + +#endif + +} + +unsigned int read_line(char **config, char **oneline) +{ + char *ptr = *config; + char *line_start; + int num; + +// printf("read_line %c\n", **config); + if (*ptr == NULL) return -1; + + line_start = ptr; + while (*ptr != '\n' && *ptr != NULL) { + ptr ++; + } + + num = ptr - line_start; + *oneline = malloc(num+1); + + memcpy (*oneline, line_start, num); + *(*oneline + num) = '\0'; + ptr ++; /* skip enter. */ + //*oneline = ptr; +// printf("readline = %s\n", *oneline); + *config = ptr; + return 0; +} +#define N_MATCHES 4 +void process_config(char *config, char *dir) +{ +// char line [ /* LINE_BUF_SIZE */128]; + char *oneline, *current, *path_filename; + regmatch_t match[N_MATCHES]; + uint8_t subprog = 0; + + compile_reg_expr(REG_EXTENDED | REG_NEWLINE, blank_or_comment_regex, &blank_or_comment_expr); + compile_reg_expr(REG_EXTENDED | REG_NEWLINE, entries_line_regex, &entries_line_expr); + compile_reg_expr(REG_EXTENDED | REG_NEWLINE, entries_subprog_line_regex, &entries_subprog_line_expr); + + /* TODO: temp */ + //strcpy (line, "PSPBTLDR_FILE PspBootLoader_prod_RV.sbin\n\0"); +// strcpy (line, "AMD_PUBKEY_FILE AmdPubKeyRV.bin\n\0"); + + /* Get a line */ + current = config; + while (read_line(&current, &oneline) != -1) { + /* get line */ + /* blank comment */ +// printf("%d\n", __LINE__); + if (!regexec(&blank_or_comment_expr, oneline, 0, NULL, 0)){ + printf("skip comment and blank\n"); + continue; + } + +// printf("%d\n", __LINE__); + if (regexec(&entries_line_expr, oneline, 3, match, 0) == 0) { + printf("matched entry\n"); + printf("%d, %d, %d\n", match[0].rm_eo, match[1].rm_eo, match[2].rm_eo); + printf("%d, %d, %d\n", match[0].rm_so, match[1].rm_so, match[2].rm_so); + oneline[match[1].rm_eo] = '\0'; + oneline[match[2].rm_eo] = '\0'; + } else if (regexec(&entries_subprog_line_expr, oneline, 4, match, 0) == 0) { + printf("matched subprog entry\n"); + printf("%d, %d, %d\n", match[0].rm_eo, match[1].rm_eo, match[2].rm_eo, match[3].rm_eo); + printf("%d, %d, %d\n", match[0].rm_so, match[1].rm_so, match[2].rm_so, match[3].rm_so); + oneline[match[1].rm_eo] = '\0'; + oneline[match[2].rm_eo] = '\0'; + oneline[match[3].rm_eo] = '\0'; + subprog = oneline[match[3].rm_so] - '0'; + } else { + printf("no match\n"); + continue; + } +// printf("%d\n", __LINE__); +// printf("%d\n", __LINE__); + +// printf("%s, %s\n", &(oneline[match[1].rm_so]), &(oneline[match[2].rm_so])); + path_filename = malloc(256); + strcpy(path_filename, dir); + strcat(path_filename, "/"); + strcat(path_filename, &(oneline[match[2].rm_so])); + find_register_fw_filename(&(oneline[match[1].rm_so]), path_filename, subprog); + + } + + printf("fuse written=[] %x\n", amd_psp_fw_table[16].other); + +} diff --git a/util/amdfwtool/sample.txt b/util/amdfwtool/sample.txt new file mode 100644 index 0000000..8c3edcc --- /dev/null +++ b/util/amdfwtool/sample.txt @@ -0,0 +1,45 @@ +# sample +# PSP +# type file subprog +AMD_PUBKEY_FILE AmdPubKeyRV.bin +PSPBTLDR_FILE PspBootLoader_prod_RV.sbin +PUBSIGNEDKEY_FILE RtmPubSignedRV.key +PSP_SMUFW1_SUB1_FILE SmuFirmwareRV2.csbin +PSP_SMUFW1_SUB2_FILE SmuFirmwarePCO.csbin +PSP_SMUFW2_SUB1_FILE SmuFirmware2RV2.csbin +PSP_SMUFW2_SUB2_FILE SmuFirmware2PCO.csbin +PSPSCUREOS_FILE psp_os_combined_prod_RV.sbin +PSPTRUSTLETS_FILE dr_ftpm_prod_RV.csbin +PSP_SEC_DBG_KEY_FILE RavenSecureDebug_PublicKey.bin +PSPSCUREOS_FILE psp_os_combined_prod_RV.sbin +PSP_ABL0_FILE AgesaBootloader0_prod_RV.csbin +PSP_ABL1_FILE AgesaBootloader1_prod_RV.csbin +PSP_ABL2_FILE AgesaBootloader2_prod_RV.csbin +PSP_ABL3_FILE AgesaBootloader3_prod_RV.csbin +PSP_ABL4_FILE AgesaBootloader4_prod_RV.csbin +PSP_ABL5_FILE AgesaBootloader5_prod_RV.csbin +PSP_ABL6_FILE AgesaBootloader6_prod_RV.csbin +PSP_ABL7_FILE AgesaBootloader7_prod_RV.csbin +PSP_SEC_DEBUG_FILE secure_unlock_prod_RV.sbin +PSP_IKEK_FILE PspIkekRV.bin +PSP_SECG1_FILE security_policy_RV2_FP5_AM4.sbin +PSP_SECG2_FILE security_policy_PCO_FP5_AM4.sbin +PSP_MP2FW1_FILE MP2I2CFWRV2.sbin +PSP_MP2FW2_FILE MP2I2CFWPCO.sbin +PSP_MP2CFG_FILE MP2FWConfig.sbin +PSP_DRIVERS_FILE drv_sys_prod_RV.sbin +PSP_SOFTFUSE 0x0000000010000001 +PSP_S0I3_FILE dr_agesa_prod_RV.sbin +#PSP_APOBNV_BASE +#PSP_APOBNV_SIZE +# +## BDT +#PSP_APCB0_FILE apcb.bin +PSP_PMUI_FILE1 Appb_Rv_1D_Ddr4_Udimm_Imem.csbin +PSP_PMUI_FILE2 Appb_Rv_2D_Ddr4_Imem.csbin +PSP_PMUI_FILE3 Appb_Rv2_1D_ddr4_Udimm_Imem.csbin +PSP_PMUI_FILE4 Appb_Rv2_2D_ddr4_Udimm_Imem.csbin +PSP_PMUD_FILE1 Appb_Rv_1D_Ddr4_Udimm_Dmem.csbin +PSP_PMUD_FILE2 Appb_Rv_2D_Ddr4_Dmem.csbin +PSP_PMUD_FILE3 Appb_Rv2_1D_ddr4_Udimm_Dmem.csbin +PSP_PMUD_FILE4 Appb_Rv2_2D_ddr4_Udimm_Dmem.csbin -- To view, visit https://review.coreboot.org/c/coreboot/+/42859 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Gerrit-Change-Number: 42859 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-MessageType: newchange

1 hour, 48 minutes

4
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Change in coreboot[master]: mb/google/volteer/halvor: Update settings for audio function

by Frank Wu (Code Review)

Frank Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44409 ) Change subject: mb/google/volteer/halvor: Update settings for audio function ...................................................................... mb/google/volteer/halvor: Update settings for audio function Configure gpio/overridetree settings for audio function. BUG=b:153680359, b:163382106 TEST=FW_NAME=halvor emerge-volteer coreboot chromeos-bootimage Signed-off-by: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Change-Id: I107f6fc21b99d80d69931139dc50e7d5873a8e52 --- M src/mainboard/google/volteer/variants/halvor/gpio.c M src/mainboard/google/volteer/variants/halvor/overridetree.cb 2 files changed, 9 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/44409/1 diff --git a/src/mainboard/google/volteer/variants/halvor/gpio.c b/src/mainboard/google/volteer/variants/halvor/gpio.c index 2a98688..92e33ca 100644 --- a/src/mainboard/google/volteer/variants/halvor/gpio.c +++ b/src/mainboard/google/volteer/variants/halvor/gpio.c @@ -53,6 +53,10 @@ PAD_NC(GPP_C11, NONE), /* C13 : UART1_TXD ==> NC */ PAD_NC(GPP_C13, NONE), + /* C16 : I2C0_SDA ==> PCH_I2C0_1V8_AUDIO_SDA */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* C17 : I2C0_SCL ==> PCH_I2C0_1V8_AUDIO_SCL */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* D7 : SRCCLKREQ2# ==> NC */ PAD_NC(GPP_D7, NONE), @@ -141,6 +145,10 @@ PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2), /* S5 : SNDW2_DATA ==> SOC_DMIC_DATA1 */ PAD_CFG_NF(GPP_S5, NONE, DEEP, NF2), + /* S6 : SNDW3_CLK ==> DMIC_CLK0 */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), + /* S7 : SNDW3_DATA ==> DMIC_DATA0 */ + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), /* GPD11: LANPHYC ==> NC */ PAD_NC(GPD11, NONE), diff --git a/src/mainboard/google/volteer/variants/halvor/overridetree.cb b/src/mainboard/google/volteer/variants/halvor/overridetree.cb index 12e059c..268b1a5 100644 --- a/src/mainboard/google/volteer/variants/halvor/overridetree.cb +++ b/src/mainboard/google/volteer/variants/halvor/overridetree.cb @@ -121,13 +121,6 @@ device i2c 15 on end end end # I2C5 0xA0C6 - device pci 1f.3 on - chip drivers/generic/max98357a - register "hid" = ""MX98357A"" - register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F18)" - register "sdmode_delay" = "5" - device generic 0 on end - end - end # Intel HD audio 0xA0C8-A0CF + device pci 1f.3 on end # Intel HD audio 0xA0C8-A0CF end end -- To view, visit https://review.coreboot.org/c/coreboot/+/44409 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I107f6fc21b99d80d69931139dc50e7d5873a8e52 Gerrit-Change-Number: 44409 Gerrit-PatchSet: 1 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

2 hours, 48 minutes

7
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Change in coreboot[master]: [WIP] sconfig: Allow chipset to provide a base devicetree

by Duncan Laurie (Code Review)

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44037 ) Change subject: [WIP] sconfig: Allow chipset to provide a base devicetree ...................................................................... [WIP] sconfig: Allow chipset to provide a base devicetree This change extends the devicetree override one more layer and allows the chipset to provide the base devicetree. This allows the chipset to assign alias names to devices as well as set default register values. This works for both the baseboard devicetree.cb as well as variant overridetree.cb. chipset.cb: device pci 15.0 alias i2c0 off end devicetree.cb: device ref i2c0 on end Change-Id: Ia7500a62f6211243b519424ef3834b9e7615e2fd Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M Makefile.inc M util/sconfig/lex.yy.c_shipped M util/sconfig/main.c M util/sconfig/sconfig.h M util/sconfig/sconfig.l M util/sconfig/sconfig.tab.c_shipped M util/sconfig/sconfig.tab.h_shipped M util/sconfig/sconfig.y 8 files changed, 632 insertions(+), 697 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/44037/1 diff --git a/Makefile.inc b/Makefile.inc index dc1c6e0..3ae2b95 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -13,6 +13,7 @@ CONFIG_FMDFILE:=$(call strip_quotes,$(CONFIG_FMDFILE)) CONFIG_DEVICETREE:=$(call strip_quotes, $(CONFIG_DEVICETREE)) CONFIG_OVERRIDE_DEVICETREE:=$(call strip_quotes, $(CONFIG_OVERRIDE_DEVICETREE)) +CONFIG_CHIPSET_DEVICETREE:=$(call strip_quotes, $(CONFIG_CHIPSET_DEVICETREE)) CONFIG_MEMLAYOUT_LD_FILE:=$(call strip_quotes, $(CONFIG_MEMLAYOUT_LD_FILE)) ####################################################################### @@ -599,13 +600,18 @@ SCONFIG_OPTIONS += --override_devtree=$(OVERRIDE_DEVICETREE_FILE) endif +ifneq ($(CONFIG_CHIPSET_DEVICETREE),) +CHIPSET_DEVICETREE_FILE := $(src)/$(CONFIG_CHIPSET_DEVICETREE) +SCONFIG_OPTIONS += --chipset_devtree=$(CHIPSET_DEVICETREE_FILE) +endif + DEVICETREE_STATIC_C := $(obj)/mainboard/$(MAINBOARDDIR)/static.c SCONFIG_OPTIONS += --output_c=$(DEVICETREE_STATIC_C) DEVICETREE_STATIC_H := $(obj)/static.h SCONFIG_OPTIONS += --output_h=$(DEVICETREE_STATIC_H) -$(DEVICETREE_STATIC_C): $(DEVICETREE_FILE) $(OVERRIDE_DEVICETREE_FILE) $(objutil)/sconfig/sconfig +$(DEVICETREE_STATIC_C): $(DEVICETREE_FILE) $(OVERRIDE_DEVICETREE_FILE) $(CHIPSET_DEVICETREE_FILE) $(objutil)/sconfig/sconfig @printf " SCONFIG $(subst $(src)/,,$(<))\n" mkdir -p $(dir $(DEVICETREE_STATIC_C)) $(objutil)/sconfig/sconfig $(SCONFIG_OPTIONS) diff --git a/util/sconfig/lex.yy.c_shipped b/util/sconfig/lex.yy.c_shipped index fcf5c3e..18b34b5 100644 --- a/util/sconfig/lex.yy.c_shipped +++ b/util/sconfig/lex.yy.c_shipped @@ -349,8 +349,8 @@ (yy_hold_char) = *yy_cp; \ *yy_cp = '\0'; \ (yy_c_buf_p) = yy_cp; -#define YY_NUM_RULES 48 -#define YY_END_OF_BUFFER 49 +#define YY_NUM_RULES 49 +#define YY_END_OF_BUFFER 50 /* This struct is not used in this scanner, but its presence is necessary. */ struct yy_trans_info @@ -358,31 +358,31 @@ flex_int32_t yy_verify; flex_int32_t yy_nxt; }; -static const flex_int16_t yy_accept[202] = +static const flex_int16_t yy_accept[203] = { 0, - 0, 0, 49, 47, 1, 3, 47, 47, 47, 42, - 42, 40, 43, 47, 43, 43, 43, 43, 43, 47, - 47, 47, 47, 47, 47, 47, 47, 47, 47, 47, - 1, 3, 47, 0, 47, 47, 0, 2, 42, 43, - 47, 47, 47, 8, 47, 47, 43, 47, 47, 47, - 47, 47, 47, 47, 47, 47, 47, 34, 47, 47, - 47, 47, 47, 47, 14, 47, 47, 47, 47, 47, - 47, 47, 47, 47, 46, 46, 47, 0, 41, 47, - 47, 47, 24, 47, 47, 33, 38, 47, 47, 47, - 47, 47, 21, 47, 47, 32, 47, 30, 47, 47, + 0, 0, 50, 48, 1, 3, 48, 48, 48, 43, + 43, 41, 44, 48, 44, 44, 44, 44, 44, 48, + 48, 48, 48, 48, 48, 48, 48, 48, 48, 48, + 1, 3, 48, 0, 48, 48, 0, 2, 43, 44, + 48, 48, 48, 9, 48, 48, 44, 48, 48, 48, + 48, 48, 48, 48, 48, 48, 48, 35, 48, 48, + 48, 48, 48, 48, 15, 48, 48, 48, 48, 48, + 48, 48, 48, 48, 47, 47, 48, 0, 42, 48, + 48, 48, 25, 48, 48, 34, 39, 48, 48, 48, + 48, 48, 22, 48, 48, 33, 48, 31, 48, 48, - 15, 47, 18, 20, 47, 47, 47, 28, 47, 29, - 7, 47, 0, 44, 47, 4, 47, 47, 47, 31, - 47, 47, 47, 47, 47, 47, 47, 47, 27, 47, - 47, 47, 47, 47, 45, 45, 6, 47, 47, 47, - 11, 47, 47, 47, 47, 47, 22, 47, 47, 13, - 47, 47, 47, 47, 5, 25, 47, 47, 16, 47, - 19, 47, 12, 47, 47, 47, 47, 47, 26, 36, - 47, 47, 47, 47, 47, 47, 47, 47, 47, 9, - 47, 47, 47, 10, 47, 17, 47, 47, 47, 35, - 47, 47, 23, 47, 37, 47, 47, 47, 47, 39, + 16, 48, 19, 21, 48, 8, 48, 48, 29, 48, + 30, 7, 48, 0, 45, 48, 4, 48, 48, 48, + 32, 48, 48, 48, 48, 48, 48, 48, 48, 28, + 48, 48, 48, 48, 48, 46, 46, 6, 48, 48, + 48, 12, 48, 48, 48, 48, 48, 23, 48, 48, + 14, 48, 48, 48, 48, 5, 26, 48, 48, 17, + 48, 20, 48, 13, 48, 48, 48, 48, 48, 27, + 37, 48, 48, 48, 48, 48, 48, 48, 48, 48, + 10, 48, 48, 48, 11, 48, 18, 48, 48, 48, + 36, 48, 48, 24, 48, 38, 48, 48, 48, 48, - 0 + 40, 0 } ; static const YY_CHAR yy_ec[256] = @@ -425,61 +425,61 @@ 1, 1, 1, 1, 1, 1, 1, 1, 1 } ; -static const flex_int16_t yy_base[209] = +static const flex_int16_t yy_base[210] = { 0, - 0, 0, 274, 0, 271, 275, 269, 38, 42, 39, - 233, 0, 45, 256, 55, 59, 83, 65, 62, 248, - 243, 68, 25, 48, 54, 75, 246, 75, 233, 0, - 263, 275, 106, 259, 111, 76, 260, 275, 0, 110, - 113, 247, 236, 0, 235, 224, 119, 231, 226, 236, - 225, 233, 237, 224, 231, 231, 225, 231, 216, 216, - 226, 216, 218, 220, 0, 207, 215, 209, 209, 214, - 218, 210, 216, 118, 0, 275, 135, 228, 0, 221, - 214, 200, 213, 203, 210, 0, 0, 201, 199, 205, - 202, 202, 0, 200, 190, 0, 194, 0, 198, 188, + 0, 0, 275, 0, 272, 276, 270, 38, 42, 39, + 234, 0, 45, 257, 55, 59, 83, 65, 62, 249, + 244, 68, 25, 48, 54, 75, 247, 75, 234, 0, + 264, 276, 106, 260, 111, 76, 261, 276, 0, 110, + 113, 248, 237, 0, 236, 225, 119, 232, 227, 237, + 226, 234, 238, 225, 232, 232, 226, 232, 217, 217, + 227, 217, 219, 221, 0, 208, 216, 210, 210, 63, + 220, 212, 218, 118, 0, 276, 135, 230, 0, 223, + 216, 202, 215, 205, 212, 0, 0, 203, 201, 207, + 204, 204, 0, 202, 192, 0, 196, 0, 200, 190, - 0, 191, 0, 0, 197, 189, 188, 0, 179, 0, - 0, 206, 205, 0, 176, 0, 189, 188, 181, 0, - 185, 175, 171, 181, 169, 175, 180, 181, 0, 168, - 175, 162, 165, 154, 0, 275, 0, 166, 170, 162, - 0, 161, 163, 159, 161, 166, 0, 150, 155, 0, - 148, 148, 147, 144, 0, 0, 156, 158, 0, 142, - 159, 145, 0, 152, 156, 137, 137, 144, 0, 0, - 143, 122, 121, 119, 130, 116, 126, 116, 108, 0, - 120, 118, 123, 0, 112, 0, 113, 116, 97, 0, - 89, 86, 0, 85, 0, 75, 65, 52, 61, 0, + 0, 193, 0, 0, 199, 0, 191, 190, 0, 181, + 0, 0, 208, 207, 0, 178, 0, 191, 190, 183, + 0, 187, 177, 173, 183, 171, 177, 182, 183, 0, + 170, 177, 164, 167, 156, 0, 276, 0, 168, 172, + 164, 0, 163, 165, 161, 163, 168, 0, 152, 157, + 0, 150, 150, 149, 146, 0, 0, 158, 160, 0, + 144, 161, 147, 0, 154, 158, 139, 139, 146, 0, + 0, 145, 137, 136, 121, 132, 118, 128, 118, 110, + 0, 122, 120, 125, 0, 114, 0, 115, 118, 110, + 0, 107, 109, 0, 107, 0, 86, 80, 62, 61, - 275, 48, 155, 157, 159, 161, 163, 165 + 0, 276, 48, 155, 157, 159, 161, 163, 165 } ; -static const flex_int16_t yy_def[209] = +static const flex_int16_t yy_def[210] = { 0, - 201, 1, 201, 202, 201, 201, 202, 203, 204, 202, - 10, 202, 10, 202, 10, 10, 10, 10, 10, 202, - 202, 202, 202, 202, 202, 202, 202, 202, 202, 202, - 201, 201, 203, 205, 206, 204, 207, 201, 10, 10, - 10, 202, 202, 202, 202, 202, 10, 202, 202, 202, - 202, 202, 202, 202, 202, 202, 202, 202, 202, 202, - 202, 202, 202, 202, 202, 202, 202, 202, 202, 202, - 202, 202, 202, 202, 202, 201, 206, 208, 41, 202, - 202, 202, 202, 202, 202, 202, 202, 202, 202, 202, - 202, 202, 202, 202, 202, 202, 202, 202, 202, 202, + 202, 1, 202, 203, 202, 202, 203, 204, 205, 203, + 10, 203, 10, 203, 10, 10, 10, 10, 10, 203, + 203, 203, 203, 203, 203, 203, 203, 203, 203, 203, + 202, 202, 204, 206, 207, 205, 208, 202, 10, 10, + 10, 203, 203, 203, 203, 203, 10, 203, 203, 203, + 203, 203, 203, 203, 203, 203, 203, 203, 203, 203, + 203, 203, 203, 203, 203, 203, 203, 203, 203, 203, + 203, 203, 203, 203, 203, 202, 207, 209, 41, 203, + 203, 203, 203, 203, 203, 203, 203, 203, 203, 203, + 203, 203, 203, 203, 203, 203, 203, 203, 203, 203, - 202, 202, 202, 202, 202, 202, 202, 202, 202, 202, - 202, 202, 201, 202, 202, 202, 202, 202, 202, 202, - 202, 202, 202, 202, 202, 202, 202, 202, 202, 202, - 202, 202, 202, 202, 202, 201, 202, 202, 202, 202, - 202, 202, 202, 202, 202, 202, 202, 202, 202, 202, - 202, 202, 202, 202, 202, 202, 202, 202, 202, 202, - 202, 202, 202, 202, 202, 202, 202, 202, 202, 202, - 202, 202, 202, 202, 202, 202, 202, 202, 202, 202, - 202, 202, 202, 202, 202, 202, 202, 202, 202, 202, - 202, 202, 202, 202, 202, 202, 202, 202, 202, 202, + 203, 203, 203, 203, 203, 203, 203, 203, 203, 203, + 203, 203, 203, 202, 203, 203, 203, 203, 203, 203, + 203, 203, 203, 203, 203, 203, 203, 203, 203, 203, + 203, 203, 203, 203, 203, 203, 202, 203, 203, 203, + 203, 203, 203, 203, 203, 203, 203, 203, 203, 203, + 203, 203, 203, 203, 203, 203, 203, 203, 203, 203, + 203, 203, 203, 203, 203, 203, 203, 203, 203, 203, + 203, 203, 203, 203, 203, 203, 203, 203, 203, 203, + 203, 203, 203, 203, 203, 203, 203, 203, 203, 203, + 203, 203, 203, 203, 203, 203, 203, 203, 203, 203, - 0, 201, 201, 201, 201, 201, 201, 201 + 203, 0, 202, 202, 202, 202, 202, 202, 202 } ; -static const flex_int16_t yy_nxt[315] = +static const flex_int16_t yy_nxt[316] = { 0, 4, 5, 6, 7, 8, 9, 10, 11, 10, 12, 13, 13, 14, 4, 4, 4, 15, 13, 16, 17, @@ -488,73 +488,73 @@ 34, 60, 35, 37, 38, 39, 39, 39, 30, 40, 40, 40, 40, 40, 61, 40, 40, 40, 40, 40, 40, 40, 40, 40, 62, 40, 40, 40, 40, 40, - 40, 40, 40, 40, 63, 64, 56, 37, 38, 200, - 43, 65, 45, 66, 199, 198, 52, 44, 46, 40, - 40, 40, 50, 67, 197, 57, 58, 51, 53, 59, + 40, 40, 40, 40, 63, 64, 56, 37, 38, 201, + 43, 65, 45, 66, 106, 107, 52, 44, 46, 40, + 40, 40, 50, 67, 200, 57, 58, 51, 53, 59, - 196, 71, 68, 47, 72, 195, 69, 34, 34, 73, + 199, 71, 68, 47, 72, 198, 69, 34, 34, 73, 75, 48, 78, 78, 49, 30, 40, 40, 40, 79, - 79, 79, 194, 79, 79, 40, 40, 40, 193, 79, - 79, 79, 79, 79, 79, 110, 78, 78, 111, 112, - 192, 191, 190, 189, 188, 187, 186, 185, 184, 183, - 182, 181, 180, 179, 84, 33, 33, 36, 36, 34, - 34, 77, 77, 37, 37, 78, 78, 178, 177, 176, - 175, 174, 173, 172, 171, 170, 169, 168, 167, 166, - 165, 164, 163, 162, 161, 160, 159, 158, 157, 156, - 155, 154, 153, 152, 151, 150, 149, 148, 147, 146, + 79, 79, 197, 79, 79, 40, 40, 40, 196, 79, + 79, 79, 79, 79, 79, 111, 78, 78, 112, 113, + 195, 194, 193, 192, 191, 190, 189, 188, 187, 186, + 185, 184, 183, 182, 84, 33, 33, 36, 36, 34, + 34, 77, 77, 37, 37, 78, 78, 181, 180, 179, + 178, 177, 176, 175, 174, 173, 172, 171, 170, 169, + 168, 167, 166, 165, 164, 163, 162, 161, 160, 159, + 158, 157, 156, 155, 154, 153, 152, 151, 150, 149, - 145, 144, 143, 142, 141, 140, 139, 138, 137, 136, - 135, 134, 133, 132, 131, 130, 129, 128, 127, 126, - 125, 124, 123, 122, 121, 120, 119, 118, 117, 116, - 115, 114, 113, 109, 108, 107, 106, 105, 104, 103, - 102, 101, 100, 99, 98, 97, 96, 95, 94, 93, - 92, 91, 90, 89, 88, 87, 86, 85, 83, 82, - 81, 80, 38, 76, 31, 74, 70, 55, 54, 42, - 41, 32, 31, 201, 3, 201, 201, 201, 201, 201, - 201, 201, 201, 201, 201, 201, 201, 201, 201, 201, - 201, 201, 201, 201, 201, 201, 201, 201, 201, 201, + 148, 147, 146, 145, 144, 143, 142, 141, 140, 139, + 138, 137, 136, 135, 134, 133, 132, 131, 130, 129, + 128, 127, 126, 125, 124, 123, 122, 121, 120, 119, + 118, 117, 116, 115, 114, 110, 109, 108, 105, 104, + 103, 102, 101, 100, 99, 98, 97, 96, 95, 94, + 93, 92, 91, 90, 89, 88, 87, 86, 85, 83, + 82, 81, 80, 38, 76, 31, 74, 70, 55, 54, + 42, 41, 32, 31, 202, 3, 202, 202, 202, 202, + 202, 202, 202, 202, 202, 202, 202, 202, 202, 202, + 202, 202, 202, 202, 202, 202, 202, 202, 202, 202, - 201, 201, 201, 201, 201, 201, 201, 201, 201, 201, - 201, 201, 201, 201 + 202, 202, 202, 202, 202, 202, 202, 202, 202, 202, + 202, 202, 202, 202, 202 } ; -static const flex_int16_t yy_chk[315] = +static const flex_int16_t yy_chk[316] = { 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 8, - 8, 23, 8, 9, 9, 10, 10, 10, 202, 10, + 8, 23, 8, 9, 9, 10, 10, 10, 203, 10, 10, 13, 13, 13, 23, 10, 10, 10, 10, 10, 10, 15, 15, 15, 24, 16, 16, 16, 19, 19, - 19, 18, 18, 18, 24, 25, 22, 36, 36, 199, - 15, 25, 16, 25, 198, 197, 19, 15, 16, 17, - 17, 17, 18, 26, 196, 22, 22, 18, 19, 22, + 19, 18, 18, 18, 24, 25, 22, 36, 36, 200, + 15, 25, 16, 25, 70, 70, 19, 15, 16, 17, + 17, 17, 18, 26, 199, 22, 22, 18, 19, 22, - 194, 28, 26, 17, 28, 192, 26, 33, 33, 28, + 198, 28, 26, 17, 28, 197, 26, 33, 33, 28, 33, 17, 35, 35, 17, 35, 40, 40, 40, 41, - 41, 41, 191, 41, 41, 47, 47, 47, 189, 41, + 41, 41, 195, 41, 41, 47, 47, 47, 193, 41, 41, 41, 41, 41, 41, 74, 77, 77, 74, 77, - 188, 187, 185, 183, 182, 181, 179, 178, 177, 176, - 175, 174, 173, 172, 47, 203, 203, 204, 204, 205, - 205, 206, 206, 207, 207, 208, 208, 171, 168, 167, - 166, 165, 164, 162, 161, 160, 158, 157, 154, 153, - 152, 151, 149, 148, 146, 145, 144, 143, 142, 140, - 139, 138, 134, 133, 132, 131, 130, 128, 127, 126, + 192, 190, 189, 188, 186, 184, 183, 182, 180, 179, + 178, 177, 176, 175, 47, 204, 204, 205, 205, 206, + 206, 207, 207, 208, 208, 209, 209, 174, 173, 172, + 169, 168, 167, 166, 165, 163, 162, 161, 159, 158, + 155, 154, 153, 152, 150, 149, 147, 146, 145, 144, + 143, 141, 140, 139, 135, 134, 133, 132, 131, 129, - 125, 124, 123, 122, 121, 119, 118, 117, 115, 113, - 112, 109, 107, 106, 105, 102, 100, 99, 97, 95, - 94, 92, 91, 90, 89, 88, 85, 84, 83, 82, - 81, 80, 78, 73, 72, 71, 70, 69, 68, 67, - 66, 64, 63, 62, 61, 60, 59, 58, 57, 56, - 55, 54, 53, 52, 51, 50, 49, 48, 46, 45, - 43, 42, 37, 34, 31, 29, 27, 21, 20, 14, - 11, 7, 5, 3, 201, 201, 201, 201, 201, 201, - 201, 201, 201, 201, 201, 201, 201, 201, 201, 201, - 201, 201, 201, 201, 201, 201, 201, 201, 201, 201, + 128, 127, 126, 125, 124, 123, 122, 120, 119, 118, + 116, 114, 113, 110, 108, 107, 105, 102, 100, 99, + 97, 95, 94, 92, 91, 90, 89, 88, 85, 84, + 83, 82, 81, 80, 78, 73, 72, 71, 69, 68, + 67, 66, 64, 63, 62, 61, 60, 59, 58, 57, + 56, 55, 54, 53, 52, 51, 50, 49, 48, 46, + 45, 43, 42, 37, 34, 31, 29, 27, 21, 20, + 14, 11, 7, 5, 3, 202, 202, 202, 202, 202, + 202, 202, 202, 202, 202, 202, 202, 202, 202, 202, + 202, 202, 202, 202, 202, 202, 202, 202, 202, 202, - 201, 201, 201, 201, 201, 201, 201, 201, 201, 201, - 201, 201, 201, 201 + 202, 202, 202, 202, 202, 202, 202, 202, 202, 202, + 202, 202, 202, 202, 202 } ; static yy_state_type yy_last_accepting_state; @@ -819,13 +819,13 @@ while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) { yy_current_state = (int) yy_def[yy_current_state]; - if ( yy_current_state >= 202 ) + if ( yy_current_state >= 203 ) yy_c = yy_meta[yy_c]; } yy_current_state = yy_nxt[yy_base[yy_current_state] + yy_c]; ++yy_cp; } - while ( yy_base[yy_current_state] != 275 ); + while ( yy_base[yy_current_state] != 276 ); yy_find_action: yy_act = yy_accept[yy_current_state]; @@ -881,139 +881,139 @@ YY_BREAK case 8: YY_RULE_SETUP -{return(ASSOCIATION);} +{return(REFERENCE);} YY_BREAK case 9: YY_RULE_SETUP -{return(REGISTER);} +{return(ASSOCIATION);} YY_BREAK case 10: YY_RULE_SETUP -{return(FW_CONFIG_TABLE);} +{return(REGISTER);} YY_BREAK case 11: YY_RULE_SETUP -{return(FW_CONFIG_FIELD);} +{return(FW_CONFIG_TABLE);} YY_BREAK case 12: YY_RULE_SETUP -{return(FW_CONFIG_OPTION);} +{return(FW_CONFIG_FIELD);} YY_BREAK case 13: YY_RULE_SETUP -{return(FW_CONFIG_PROBE);} +{return(FW_CONFIG_OPTION);} YY_BREAK case 14: YY_RULE_SETUP -{yylval.number=1; return(BOOL);} +{return(FW_CONFIG_PROBE);} YY_BREAK case 15: YY_RULE_SETUP -{yylval.number=0; return(BOOL);} +{yylval.number=1; return(BOOL);} YY_BREAK case 16: YY_RULE_SETUP -{yylval.number=3; return(STATUS);} +{yylval.number=0; return(BOOL);} YY_BREAK case 17: YY_RULE_SETUP -{yylval.number=5; return(STATUS);} +{yylval.number=3; return(STATUS);} YY_BREAK case 18: YY_RULE_SETUP -{yylval.number=PCI; return(BUS);} +{yylval.number=5; return(STATUS);} YY_BREAK case 19: YY_RULE_SETUP -{yylval.number=IOAPIC; return(BUS);} +{yylval.number=PCI; return(BUS);} YY_BREAK case 20: YY_RULE_SETUP -{yylval.number=PNP; return(BUS);} +{yylval.number=IOAPIC; return(BUS);} YY_BREAK case 21: YY_RULE_SETUP -{yylval.number=I2C; return(BUS);} +{yylval.number=PNP; return(BUS);} YY_BREAK case 22: YY_RULE_SETUP -{yylval.number=APIC; return(BUS);} +{yylval.number=I2C; return(BUS);} YY_BREAK case 23: YY_RULE_SETUP -{yylval.number=CPU_CLUSTER; return(BUS);} +{yylval.number=APIC; return(BUS);} YY_BREAK case 24: YY_RULE_SETUP -{yylval.number=CPU; return(BUS);} +{yylval.number=CPU_CLUSTER; return(BUS);} YY_BREAK case 25: YY_RULE_SETUP -{yylval.number=DOMAIN; return(BUS);} +{yylval.number=CPU; return(BUS);} YY_BREAK case 26: YY_RULE_SETUP -{yylval.number=GENERIC; return(BUS);} +{yylval.number=DOMAIN; return(BUS);} YY_BREAK case 27: YY_RULE_SETUP -{yylval.number=MMIO; return(BUS);} +{yylval.number=GENERIC; return(BUS);} YY_BREAK case 28: YY_RULE_SETUP -{yylval.number=SPI; return(BUS);} +{yylval.number=MMIO; return(BUS);} YY_BREAK case 29: YY_RULE_SETUP -{yylval.number=USB; return(BUS);} +{yylval.number=SPI; return(BUS);} YY_BREAK case 30: YY_RULE_SETUP -{yylval.number=LPC; return(BUS);} +{yylval.number=USB; return(BUS);} YY_BREAK case 31: YY_RULE_SETUP -{yylval.number=ESPI; return(BUS);} +{yylval.number=LPC; return(BUS);} YY_BREAK case 32: YY_RULE_SETUP -{yylval.number=IRQ; return(RESOURCE);} +{yylval.number=ESPI; return(BUS);} YY_BREAK case 33: YY_RULE_SETUP -{yylval.number=DRQ; return(RESOURCE);} +{yylval.number=IRQ; return(RESOURCE);} YY_BREAK case 34: YY_RULE_SETUP -{yylval.number=IO; return(RESOURCE);} +{yylval.number=DRQ; return(RESOURCE);} YY_BREAK case 35: YY_RULE_SETUP -{return(IOAPIC_IRQ);} +{yylval.number=IO; return(RESOURCE);} YY_BREAK case 36: YY_RULE_SETUP -{return(INHERIT);} +{return(IOAPIC_IRQ);} YY_BREAK case 37: YY_RULE_SETUP -{return(SUBSYSTEMID);} +{return(INHERIT);} YY_BREAK case 38: YY_RULE_SETUP -{return(END);} +{return(SUBSYSTEMID);} YY_BREAK case 39: YY_RULE_SETUP -{return(SLOT_DESC);} +{return(END);} YY_BREAK case 40: YY_RULE_SETUP -{return(EQUALS);} +{return(SLOT_DESC);} YY_BREAK case 41: YY_RULE_SETUP -{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);} +{return(EQUALS);} YY_BREAK case 42: YY_RULE_SETUP @@ -1025,12 +1025,11 @@ YY_BREAK case 44: YY_RULE_SETUP -{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(PCIINT);} +{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);} YY_BREAK case 45: -/* rule 45 can match eol */ YY_RULE_SETUP -{yylval.string = malloc(yyleng-1); strncpy(yylval.string, yytext+1, yyleng-2); yylval.string[yyleng-2]='\0'; return(STRING);} +{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(PCIINT);} YY_BREAK case 46: /* rule 46 can match eol */ @@ -1038,10 +1037,15 @@ {yylval.string = malloc(yyleng-1); strncpy(yylval.string, yytext+1, yyleng-2); yylval.string[yyleng-2]='\0'; return(STRING);} YY_BREAK case 47: +/* rule 47 can match eol */ +YY_RULE_SETUP +{yylval.string = malloc(yyleng-1); strncpy(yylval.string, yytext+1, yyleng-2); yylval.string[yyleng-2]='\0'; return(STRING);} + YY_BREAK +case 48: YY_RULE_SETUP {yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(STRING);} YY_BREAK -case 48: +case 49: YY_RULE_SETUP ECHO; YY_BREAK @@ -1341,7 +1345,7 @@ while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) { yy_current_state = (int) yy_def[yy_current_state]; - if ( yy_current_state >= 202 ) + if ( yy_current_state >= 203 ) yy_c = yy_meta[yy_c]; } yy_current_state = yy_nxt[yy_base[yy_current_state] + yy_c]; @@ -1369,11 +1373,11 @@ while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) { yy_current_state = (int) yy_def[yy_current_state]; - if ( yy_current_state >= 202 ) + if ( yy_current_state >= 203 ) yy_c = yy_meta[yy_c]; } yy_current_state = yy_nxt[yy_base[yy_current_state] + yy_c]; - yy_is_jam = (yy_current_state == 201); + yy_is_jam = (yy_current_state == 202); return yy_is_jam ? 0 : yy_current_state; } diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 251aa3f..842c8af 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -69,6 +69,9 @@ /* Root device of primary tree. */ static struct device base_root_dev; +/* Root device of chipset tree. */ +static struct device chipset_root_dev; + /* Root device of override tree (if applicable). */ static struct device override_root_dev; @@ -88,6 +91,20 @@ .bus = &base_root_bus, }; +static struct bus chipset_root_bus = { + .id = 0, + .dev = &chipset_root_dev, +}; + +static struct device chipset_root_dev = { + .name = "chipset_root", + .chip_instance = &mainboard_instance, + .path = " .type = DEVICE_PATH_ROOT ", + .parent = &chipset_root_bus, + .enabled = 1, + .bus = &chipset_root_bus, +}; + static struct bus override_root_bus = { .id = 0, .dev = &override_root_dev, @@ -689,6 +706,20 @@ return NULL; } +struct device *new_device_reference(struct bus *parent, + struct chip_instance *chip_instance, + const char *reference, int status) +{ + const struct device *dev = find_alias(&base_root_dev, reference); + + if (!dev) { + printf("ERROR: Unable to find device reference %s\n", reference); + exit(1); + } + + return new_device(parent, chip_instance, dev->bustype, dev->devnum, NULL, status); +} + struct device *new_device(struct bus *parent, struct chip_instance *chip_instance, const int bustype, const char *devnum, @@ -721,6 +752,7 @@ new_d = alloc_dev(parent); new_d->bustype = bustype; + new_d->devnum = devnum; new_d->path_a = path_a; new_d->path_b = path_b; @@ -1315,6 +1347,7 @@ printf(" -r | --output_h : Header static.h file (required)\n"); printf(" -m | --mainboard_devtree : Mainboard devicetree file (required)\n"); printf(" -o | --override_devtree : Override devicetree file (optional)\n"); + printf(" -p | --chipset_devtree : Chipset/SOC devicetree file (optional)\n"); exit(1); } @@ -1683,6 +1716,7 @@ static const struct option long_options[] = { { "mainboard_devtree", 1, NULL, 'm' }, { "override_devtree", 1, NULL, 'o' }, + { "chipset_devtree", 1, NULL, 'p' }, { "output_c", 1, NULL, 'c' }, { "output_h", 1, NULL, 'r' }, { "help", 1, NULL, 'h' }, @@ -1690,11 +1724,12 @@ }; const char *override_devtree = NULL; const char *base_devtree = NULL; + const char *chipset_devtree = NULL; const char *outputc = NULL; const char *outputh = NULL; int opt, option_index; - while ((opt = getopt_long(argc, argv, "m:o:c:r:h", long_options, + while ((opt = getopt_long(argc, argv, "m:o:p:c:r:h", long_options, &option_index)) != EOF) { switch (opt) { case 'm': @@ -1703,6 +1738,9 @@ case 'o': override_devtree = strdup(optarg); break; + case 'p': + chipset_devtree = strdup(optarg); + break; case 'c': outputc = strdup(optarg); break; @@ -1718,7 +1756,14 @@ if (!base_devtree || !outputc || !outputh) usage(); - parse_devicetree(base_devtree, &base_root_bus); + if (chipset_devtree) { + /* Use the chipset devicetree as the base, then override + * with the mainboard "base" devicetree. */ + parse_devicetree(chipset_devtree, &base_root_bus); + parse_override_devicetree(base_devtree, &chipset_root_dev); + } else { + parse_devicetree(base_devtree, &base_root_bus); + } if (override_devtree) parse_override_devicetree(override_devtree, &override_root_dev); diff --git a/util/sconfig/sconfig.h b/util/sconfig/sconfig.h index 719519e..f4bd7f1 100644 --- a/util/sconfig/sconfig.h +++ b/util/sconfig/sconfig.h @@ -133,6 +133,7 @@ char *path; int path_a; int path_b; + const char *devnum; /* Type of bus that exists under this device. */ int bustype; @@ -180,6 +181,10 @@ const int bustype, const char *devnum, char *alias, int status); +struct device *new_device_reference(struct bus *parent, + struct chip_instance *chip_instance, + const char *reference, int status); + void add_resource(struct bus *bus, int type, int index, int base); void add_pci_subsystem_ids(struct bus *bus, int vendor, int device, diff --git a/util/sconfig/sconfig.l b/util/sconfig/sconfig.l index 0505150..a772b96 100755 --- a/util/sconfig/sconfig.l +++ b/util/sconfig/sconfig.l @@ -15,6 +15,7 @@ device {return(DEVICE);} alias {return(ALIAS);} use {return(REFERENCE);} +ref {return(REFERENCE);} as {return(ASSOCIATION);} register {return(REGISTER);} fw_config {return(FW_CONFIG_TABLE);} diff --git a/util/sconfig/sconfig.tab.c_shipped b/util/sconfig/sconfig.tab.c_shipped index 52bb79c..496f448 100644 --- a/util/sconfig/sconfig.tab.c_shipped +++ b/util/sconfig/sconfig.tab.c_shipped @@ -1,4 +1,4 @@ -/* A Bison parser, made by GNU Bison 3.5.3. */ +/* A Bison parser, made by GNU Bison 3.6.3. */ /* Bison implementation for Yacc-like parsers in C @@ -34,6 +34,10 @@ /* C LALR(1) parser skeleton written by Richard Stallman, by simplifying the original so-called "semantic" parser. */ +/* DO NOT RELY ON FEATURES THAT ARE NOT DOCUMENTED in the manual, + especially those whose name start with YY_ or yy_. They are + private implementation details that can be changed or removed. */ + /* All symbols defined below should begin with yy or YY, to avoid infringing on user name space. This should be done even for local variables, as they might otherwise be expanded by user macros. @@ -41,14 +45,11 @@ define necessary library symbols; they are noted "INFRINGES ON USER NAME SPACE" below. */ -/* Undocumented macros, especially those whose name start with YY_, - are private implementation details. Do not rely on them. */ - /* Identify Bison output. */ #define YYBISON 1 /* Bison version. */ -#define YYBISON_VERSION "3.5.3" +#define YYBISON_VERSION "3.6.3" /* Skeleton name. */ #define YYSKELETON_NAME "yacc.c" @@ -102,14 +103,6 @@ # endif # endif -/* Enabling verbose error messages. */ -#ifdef YYERROR_VERBOSE -# undef YYERROR_VERBOSE -# define YYERROR_VERBOSE 1 -#else -# define YYERROR_VERBOSE 0 -#endif - /* Use api.header.include to #include this header instead of duplicating it here. */ #ifndef YY_YY_SRC_COREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED @@ -122,54 +115,59 @@ extern int yydebug; #endif -/* Token type. */ +/* Token kinds. */ #ifndef YYTOKENTYPE # define YYTOKENTYPE enum yytokentype { - CHIP = 258, - DEVICE = 259, - REGISTER = 260, - ALIAS = 261, - REFERENCE = 262, - ASSOCIATION = 263, - BOOL = 264, - STATUS = 265, - MANDATORY = 266, - BUS = 267, - RESOURCE = 268, - END = 269, - EQUALS = 270, - HEX = 271, - STRING = 272, - PCI = 273, - PNP = 274, - I2C = 275, - APIC = 276, - CPU_CLUSTER = 277, - CPU = 278, - DOMAIN = 279, - IRQ = 280, - DRQ = 281, - SLOT_DESC = 282, - IO = 283, - NUMBER = 284, - SUBSYSTEMID = 285, - INHERIT = 286, - IOAPIC_IRQ = 287, - IOAPIC = 288, - PCIINT = 289, - GENERIC = 290, - SPI = 291, - USB = 292, - MMIO = 293, - LPC = 294, - ESPI = 295, - FW_CONFIG_TABLE = 296, - FW_CONFIG_FIELD = 297, - FW_CONFIG_OPTION = 298, - FW_CONFIG_PROBE = 299 + YYEMPTY = -2, + YYEOF = 0, /* "end of file" */ + YYerror = 256, /* error */ + YYUNDEF = 257, /* "invalid token" */ + CHIP = 258, /* CHIP */ + DEVICE = 259, /* DEVICE */ + REGISTER = 260, /* REGISTER */ + ALIAS = 261, /* ALIAS */ + REFERENCE = 262, /* REFERENCE */ + ASSOCIATION = 263, /* ASSOCIATION */ + BOOL = 264, /* BOOL */ + STATUS = 265, /* STATUS */ + MANDATORY = 266, /* MANDATORY */ + BUS = 267, /* BUS */ + RESOURCE = 268, /* RESOURCE */ + END = 269, /* END */ + EQUALS = 270, /* EQUALS */ + HEX = 271, /* HEX */ + STRING = 272, /* STRING */ + PCI = 273, /* PCI */ + PNP = 274, /* PNP */ + I2C = 275, /* I2C */ + APIC = 276, /* APIC */ + CPU_CLUSTER = 277, /* CPU_CLUSTER */ + CPU = 278, /* CPU */ + DOMAIN = 279, /* DOMAIN */ + IRQ = 280, /* IRQ */ + DRQ = 281, /* DRQ */ + SLOT_DESC = 282, /* SLOT_DESC */ + IO = 283, /* IO */ + NUMBER = 284, /* NUMBER */ + SUBSYSTEMID = 285, /* SUBSYSTEMID */ + INHERIT = 286, /* INHERIT */ + IOAPIC_IRQ = 287, /* IOAPIC_IRQ */ + IOAPIC = 288, /* IOAPIC */ + PCIINT = 289, /* PCIINT */ + GENERIC = 290, /* GENERIC */ + SPI = 291, /* SPI */ + USB = 292, /* USB */ + MMIO = 293, /* MMIO */ + LPC = 294, /* LPC */ + ESPI = 295, /* ESPI */ + FW_CONFIG_TABLE = 296, /* FW_CONFIG_TABLE */ + FW_CONFIG_FIELD = 297, /* FW_CONFIG_FIELD */ + FW_CONFIG_OPTION = 298, /* FW_CONFIG_OPTION */ + FW_CONFIG_PROBE = 299 /* FW_CONFIG_PROBE */ }; + typedef enum yytokentype yytoken_kind_t; #endif /* Value type. */ @@ -195,6 +193,84 @@ int yyparse (void); #endif /* !YY_YY_SRC_COREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED */ +/* Symbol kind. */ +enum yysymbol_kind_t +{ + YYSYMBOL_YYEMPTY = -2, + YYSYMBOL_YYEOF = 0, /* "end of file" */ + YYSYMBOL_YYerror = 1, /* error */ + YYSYMBOL_YYUNDEF = 2, /* "invalid token" */ + YYSYMBOL_CHIP = 3, /* CHIP */ + YYSYMBOL_DEVICE = 4, /* DEVICE */ + YYSYMBOL_REGISTER = 5, /* REGISTER */ + YYSYMBOL_ALIAS = 6, /* ALIAS */ + YYSYMBOL_REFERENCE = 7, /* REFERENCE */ + YYSYMBOL_ASSOCIATION = 8, /* ASSOCIATION */ + YYSYMBOL_BOOL = 9, /* BOOL */ + YYSYMBOL_STATUS = 10, /* STATUS */ + YYSYMBOL_MANDATORY = 11, /* MANDATORY */ + YYSYMBOL_BUS = 12, /* BUS */ + YYSYMBOL_RESOURCE = 13, /* RESOURCE */ + YYSYMBOL_END = 14, /* END */ + YYSYMBOL_EQUALS = 15, /* EQUALS */ + YYSYMBOL_HEX = 16, /* HEX */ + YYSYMBOL_STRING = 17, /* STRING */ + YYSYMBOL_PCI = 18, /* PCI */ + YYSYMBOL_PNP = 19, /* PNP */ + YYSYMBOL_I2C = 20, /* I2C */ + YYSYMBOL_APIC = 21, /* APIC */ + YYSYMBOL_CPU_CLUSTER = 22, /* CPU_CLUSTER */ + YYSYMBOL_CPU = 23, /* CPU */ + YYSYMBOL_DOMAIN = 24, /* DOMAIN */ + YYSYMBOL_IRQ = 25, /* IRQ */ + YYSYMBOL_DRQ = 26, /* DRQ */ + YYSYMBOL_SLOT_DESC = 27, /* SLOT_DESC */ + YYSYMBOL_IO = 28, /* IO */ + YYSYMBOL_NUMBER = 29, /* NUMBER */ + YYSYMBOL_SUBSYSTEMID = 30, /* SUBSYSTEMID */ + YYSYMBOL_INHERIT = 31, /* INHERIT */ + YYSYMBOL_IOAPIC_IRQ = 32, /* IOAPIC_IRQ */ + YYSYMBOL_IOAPIC = 33, /* IOAPIC */ + YYSYMBOL_PCIINT = 34, /* PCIINT */ + YYSYMBOL_GENERIC = 35, /* GENERIC */ + YYSYMBOL_SPI = 36, /* SPI */ + YYSYMBOL_USB = 37, /* USB */ + YYSYMBOL_MMIO = 38, /* MMIO */ + YYSYMBOL_LPC = 39, /* LPC */ + YYSYMBOL_ESPI = 40, /* ESPI */ + YYSYMBOL_FW_CONFIG_TABLE = 41, /* FW_CONFIG_TABLE */ + YYSYMBOL_FW_CONFIG_FIELD = 42, /* FW_CONFIG_FIELD */ + YYSYMBOL_FW_CONFIG_OPTION = 43, /* FW_CONFIG_OPTION */ + YYSYMBOL_FW_CONFIG_PROBE = 44, /* FW_CONFIG_PROBE */ + YYSYMBOL_YYACCEPT = 45, /* $accept */ + YYSYMBOL_devtree = 46, /* devtree */ + YYSYMBOL_chipchildren = 47, /* chipchildren */ + YYSYMBOL_devicechildren = 48, /* devicechildren */ + YYSYMBOL_chip = 49, /* chip */ + YYSYMBOL_50_1 = 50, /* @1 */ + YYSYMBOL_device = 51, /* device */ + YYSYMBOL_52_2 = 52, /* @2 */ + YYSYMBOL_53_3 = 53, /* @3 */ + YYSYMBOL_alias = 54, /* alias */ + YYSYMBOL_status = 55, /* status */ + YYSYMBOL_resource = 56, /* resource */ + YYSYMBOL_reference = 57, /* reference */ + YYSYMBOL_registers = 58, /* registers */ + YYSYMBOL_subsystemid = 59, /* subsystemid */ + YYSYMBOL_ioapic_irq = 60, /* ioapic_irq */ + YYSYMBOL_smbios_slot_desc = 61, /* smbios_slot_desc */ + YYSYMBOL_fw_config_table = 62, /* fw_config_table */ + YYSYMBOL_fw_config_table_children = 63, /* fw_config_table_children */ + YYSYMBOL_fw_config_field_children = 64, /* fw_config_field_children */ + YYSYMBOL_fw_config_field = 65, /* fw_config_field */ + YYSYMBOL_66_4 = 66, /* $@4 */ + YYSYMBOL_67_5 = 67, /* $@5 */ + YYSYMBOL_68_6 = 68, /* $@6 */ + YYSYMBOL_fw_config_option = 69, /* fw_config_option */ + YYSYMBOL_fw_config_probe = 70 /* fw_config_probe */ +}; +typedef enum yysymbol_kind_t yysymbol_kind_t; + @@ -294,6 +370,7 @@ #define YYSIZEOF(X) YY_CAST (YYPTRDIFF_T, sizeof (X)) + /* Stored state numbers (used for stacks). */ typedef yytype_int8 yy_state_t; @@ -312,6 +389,7 @@ # endif #endif + #ifndef YY_ATTRIBUTE_PURE # if defined __GNUC__ && 2 < __GNUC__ + (96 <= __GNUC_MINOR__) # define YY_ATTRIBUTE_PURE __attribute__ ((__pure__)) @@ -369,7 +447,7 @@ #define YY_ASSERT(E) ((void) (0 && (E))) -#if ! defined yyoverflow || YYERROR_VERBOSE +#if !defined yyoverflow /* The parser invokes alloca or malloc; define the necessary symbols. */ @@ -434,8 +512,7 @@ # endif # endif # endif -#endif /* ! defined yyoverflow || YYERROR_VERBOSE */ - +#endif /* !defined yyoverflow */ #if (! defined yyoverflow \ && (! defined __cplusplus \ @@ -500,25 +577,26 @@ /* YYFINAL -- State number of the termination state. */ #define YYFINAL 2 /* YYLAST -- Last index in YYTABLE. */ -#define YYLAST 64 +#define YYLAST 97 /* YYNTOKENS -- Number of terminals. */ #define YYNTOKENS 45 /* YYNNTS -- Number of nonterminals. */ -#define YYNNTS 25 +#define YYNNTS 26 /* YYNRULES -- Number of rules. */ -#define YYNRULES 48 +#define YYNRULES 50 /* YYNSTATES -- Number of states. */ -#define YYNSTATES 83 +#define YYNSTATES 89 -#define YYUNDEFTOK 2 #define YYMAXUTOK 299 /* YYTRANSLATE(TOKEN-NUM) -- Symbol number corresponding to TOKEN-NUM as returned by yylex, with out-of-bounds checking. */ -#define YYTRANSLATE(YYX) \ - (0 <= (YYX) && (YYX) <= YYMAXUTOK ? yytranslate[YYX] : YYUNDEFTOK) +#define YYTRANSLATE(YYX) \ + (0 <= (YYX) && (YYX) <= YYMAXUTOK \ + ? YY_CAST (yysymbol_kind_t, yytranslate[YYX]) \ + : YYSYMBOL_YYUNDEF) /* YYTRANSLATE[TOKEN-NUM] -- Symbol number corresponding to TOKEN-NUM as returned by yylex. */ @@ -562,34 +640,48 @@ { 0, 24, 24, 24, 24, 26, 26, 26, 26, 26, 28, 28, 28, 28, 28, 28, 28, 28, 28, 30, - 30, 39, 39, 47, 49, 53, 53, 55, 58, 61, - 64, 67, 70, 73, 76, 79, 83, 86, 86, 89, - 89, 92, 92, 98, 98, 104, 104, 110, 114 + 30, 39, 39, 47, 47, 55, 57, 61, 61, 63, + 66, 69, 72, 75, 78, 81, 84, 87, 91, 94, + 94, 97, 97, 100, 100, 106, 106, 112, 112, 118, + 122 }; #endif -#if YYDEBUG || YYERROR_VERBOSE || 0 +/** Accessing symbol of state STATE. */ +#define YY_ACCESSING_SYMBOL(State) YY_CAST (yysymbol_kind_t, yystos[State]) + +#if YYDEBUG || 0 +/* The user-facing name of the symbol whose (internal) number is + YYSYMBOL. No bounds checking. */ +static const char *yysymbol_name (yysymbol_kind_t yysymbol) YY_ATTRIBUTE_UNUSED; + /* YYTNAME[SYMBOL-NUM] -- String name of the symbol SYMBOL-NUM. First, the terminals, then, starting at YYNTOKENS, nonterminals. */ static const char *const yytname[] = { - "$end", "error", "$undefined", "CHIP", "DEVICE", "REGISTER", "ALIAS", - "REFERENCE", "ASSOCIATION", "BOOL", "STATUS", "MANDATORY", "BUS", - "RESOURCE", "END", "EQUALS", "HEX", "STRING", "PCI", "PNP", "I2C", - "APIC", "CPU_CLUSTER", "CPU", "DOMAIN", "IRQ", "DRQ", "SLOT_DESC", "IO", - "NUMBER", "SUBSYSTEMID", "INHERIT", "IOAPIC_IRQ", "IOAPIC", "PCIINT", - "GENERIC", "SPI", "USB", "MMIO", "LPC", "ESPI", "FW_CONFIG_TABLE", - "FW_CONFIG_FIELD", "FW_CONFIG_OPTION", "FW_CONFIG_PROBE", "$accept", - "devtree", "chipchildren", "devicechildren", "chip", "@1", "device", - "@2", "alias", "status", "resource", "reference", "registers", - "subsystemid", "ioapic_irq", "smbios_slot_desc", "fw_config_table", - "fw_config_table_children", "fw_config_field_children", - "fw_config_field", "$@3", "$@4", "$@5", "fw_config_option", - "fw_config_probe", YY_NULLPTR + "\"end of file\"", "error", "\"invalid token\"", "CHIP", "DEVICE", + "REGISTER", "ALIAS", "REFERENCE", "ASSOCIATION", "BOOL", "STATUS", + "MANDATORY", "BUS", "RESOURCE", "END", "EQUALS", "HEX", "STRING", "PCI", + "PNP", "I2C", "APIC", "CPU_CLUSTER", "CPU", "DOMAIN", "IRQ", "DRQ", + "SLOT_DESC", "IO", "NUMBER", "SUBSYSTEMID", "INHERIT", "IOAPIC_IRQ", + "IOAPIC", "PCIINT", "GENERIC", "SPI", "USB", "MMIO", "LPC", "ESPI", + "FW_CONFIG_TABLE", "FW_CONFIG_FIELD", "FW_CONFIG_OPTION", + "FW_CONFIG_PROBE", "$accept", "devtree", "chipchildren", + "devicechildren", "chip", "@1", "device", "@2", "@3", "alias", "status", + "resource", "reference", "registers", "subsystemid", "ioapic_irq", + "smbios_slot_desc", "fw_config_table", "fw_config_table_children", + "fw_config_field_children", "fw_config_field", "$@4", "$@5", "$@6", + "fw_config_option", "fw_config_probe", YY_NULLPTR }; + +static const char * +yysymbol_name (yysymbol_kind_t yysymbol) +{ + return yytname[yysymbol]; +} #endif -# ifdef YYPRINT +#ifdef YYPRINT /* YYTOKNUM[NUM] -- (External) token number corresponding to the (internal) symbol number NUM (which must be that of a token). */ static const yytype_int16 yytoknum[] = @@ -600,9 +692,9 @@ 285, 286, 287, 288, 289, 290, 291, 292, 293, 294, 295, 296, 297, 298, 299 }; -# endif +#endif -#define YYPACT_NINF (-21) +#define YYPACT_NINF (-12) #define yypact_value_is_default(Yyn) \ ((Yyn) == YYPACT_NINF) @@ -616,15 +708,15 @@ STATE-NUM. */ static const yytype_int8 yypact[] = { - -21, 3, -21, -4, -21, -21, -21, -21, -2, -21, - -21, 4, -21, 11, -20, 14, 6, 13, -21, -21, - -21, -21, -21, -1, -21, 2, 17, 26, -21, -21, - -10, 29, 21, 22, -21, -7, -21, 25, -21, 30, - 10, -21, -21, -6, -21, 19, -21, -21, -21, -21, - -21, -21, -21, -3, 20, -21, 33, 23, 24, 34, - -21, -21, -21, -21, -21, -21, -21, -21, 28, 37, - 27, 12, 38, 31, 40, 32, 35, -21, -21, 41, - -21, -21, -21 + -12, 9, -12, 18, -12, -12, -12, -12, 2, -12, + -12, 25, -12, 16, 14, 10, 30, 31, -12, -12, + -12, -12, -12, 17, -12, 32, 22, 3, 44, -12, + -12, -11, 29, 20, 36, 37, -12, -7, -12, 38, + -12, -12, -12, -12, 39, 29, -12, -12, -6, -12, + 28, -12, -12, -12, -12, -12, -3, -12, 33, -12, + 41, 34, 35, 42, -12, -12, -12, -12, -12, -12, + -12, -12, 1, 45, 48, 40, 27, 49, -12, 43, + 50, 46, 47, -12, -12, 51, -12, -12, -12 }; /* YYDEFACT[STATE-NUM] -- Default reduction number in state STATE-NUM. @@ -632,31 +724,31 @@ means the default is an error. */ static const yytype_int8 yydefact[] = { - 2, 0, 1, 0, 38, 3, 4, 19, 0, 9, - 36, 0, 37, 0, 45, 0, 0, 0, 20, 6, - 5, 8, 7, 43, 40, 0, 0, 0, 41, 40, - 0, 23, 0, 0, 40, 0, 46, 0, 39, 0, - 0, 29, 28, 0, 44, 0, 24, 25, 26, 21, - 42, 47, 18, 0, 0, 22, 0, 0, 0, 0, - 11, 10, 12, 16, 13, 14, 15, 17, 0, 0, - 0, 0, 0, 0, 35, 30, 0, 48, 27, 34, - 31, 32, 33 + 2, 0, 1, 0, 40, 3, 4, 19, 0, 9, + 38, 0, 39, 0, 47, 0, 0, 0, 20, 6, + 5, 8, 7, 45, 42, 0, 0, 0, 0, 43, + 42, 0, 0, 25, 0, 0, 42, 0, 48, 0, + 41, 27, 28, 23, 0, 0, 31, 30, 0, 46, + 0, 18, 26, 21, 44, 49, 0, 18, 0, 24, + 0, 0, 0, 0, 11, 10, 12, 16, 13, 14, + 15, 17, 0, 0, 0, 0, 0, 0, 22, 0, + 37, 32, 0, 50, 29, 36, 33, 34, 35 }; /* YYPGOTO[NTERM-NUM]. */ static const yytype_int8 yypgoto[] = { - -21, -21, -21, -21, -8, -21, 8, -21, -21, -21, - -21, -21, 9, -21, -21, -21, -21, -21, -12, -21, - -21, -21, -21, -21, -21 + -12, -12, -12, 13, 12, -12, 58, -12, -12, -12, + 52, -12, -12, 60, -12, -12, -12, -12, -12, 4, + -12, -12, -12, -12, -12, -12 }; /* YYDEFGOTO[NTERM-NUM]. */ static const yytype_int8 yydefgoto[] = { - -1, 1, 13, 53, 5, 9, 20, 52, 40, 49, - 62, 21, 22, 64, 65, 66, 6, 8, 30, 12, - 34, 29, 24, 38, 67 + -1, 1, 13, 56, 64, 9, 65, 57, 51, 45, + 43, 66, 21, 67, 68, 69, 70, 6, 8, 31, + 12, 36, 30, 24, 40, 71 }; /* YYTABLE[YYPACT[STATE-NUM]] -- What to do in state STATE-NUM. If @@ -664,39 +756,45 @@ number is the opposite. If YYTABLE_NINF, syntax error. */ static const yytype_int8 yytable[] = { - 3, 15, 16, 2, 36, 19, 3, 44, 50, 23, - 54, 55, 10, 7, 3, 15, 16, 35, 17, 47, - 48, 14, 43, 26, 56, 18, 25, 57, 28, 58, - 27, 31, 32, 37, 33, 39, 37, 37, 41, 42, - 11, 59, 45, 73, 4, 60, 76, 46, 51, 68, - 69, 72, 70, 71, 74, 77, 75, 79, 82, 0, - 78, 61, 63, 80, 81 + 3, 15, 16, 38, 3, 15, 16, 49, 54, 2, + 58, 59, 3, 5, 58, 78, 10, 25, 34, 3, + 15, 16, 26, 17, 60, 19, 44, 61, 60, 62, + 18, 61, 39, 62, 37, 7, 39, 39, 41, 42, + 48, 63, 14, 23, 11, 63, 29, 27, 28, 32, + 4, 33, 35, 46, 47, 50, 52, 55, 74, 77, + 79, 82, 73, 75, 76, 80, 83, 85, 88, 81, + 72, 20, 84, 22, 0, 0, 87, 86, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 53 }; static const yytype_int8 yycheck[] = { - 3, 4, 5, 0, 14, 13, 3, 14, 14, 29, - 13, 14, 14, 17, 3, 4, 5, 29, 7, 9, - 10, 17, 34, 17, 27, 14, 12, 30, 29, 32, - 17, 29, 15, 43, 8, 6, 43, 43, 17, 17, - 42, 44, 17, 15, 41, 53, 34, 17, 29, 29, - 17, 17, 29, 29, 17, 17, 29, 17, 17, -1, - 29, 53, 53, 31, 29 + 3, 4, 5, 14, 3, 4, 5, 14, 14, 0, + 13, 14, 3, 1, 13, 14, 14, 7, 15, 3, + 4, 5, 12, 7, 27, 13, 6, 30, 27, 32, + 14, 30, 43, 32, 30, 17, 43, 43, 9, 10, + 36, 44, 17, 29, 42, 44, 29, 17, 17, 17, + 41, 29, 8, 17, 17, 17, 17, 29, 17, 17, + 15, 34, 29, 29, 29, 17, 17, 17, 17, 29, + 57, 13, 29, 13, -1, -1, 29, 31, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, 45 }; /* YYSTOS[STATE-NUM] -- The (internal number of the) accessing symbol of state STATE-NUM. */ static const yytype_int8 yystos[] = { - 0, 46, 0, 3, 41, 49, 61, 17, 62, 50, - 14, 42, 64, 47, 17, 4, 5, 7, 14, 49, - 51, 56, 57, 29, 67, 12, 17, 17, 29, 66, - 63, 29, 15, 8, 65, 63, 14, 43, 68, 6, - 53, 17, 17, 63, 14, 17, 17, 9, 10, 54, - 14, 29, 52, 48, 13, 14, 27, 30, 32, 44, - 49, 51, 55, 57, 58, 59, 60, 69, 29, 17, - 29, 29, 17, 15, 17, 29, 34, 17, 29, 17, - 31, 29, 17 + 0, 46, 0, 3, 41, 49, 62, 17, 63, 50, + 14, 42, 65, 47, 17, 4, 5, 7, 14, 49, + 51, 57, 58, 29, 68, 7, 12, 17, 17, 29, + 67, 64, 17, 29, 15, 8, 66, 64, 14, 43, + 69, 9, 10, 55, 6, 54, 17, 17, 64, 14, + 17, 53, 17, 55, 14, 29, 48, 52, 13, 14, + 27, 30, 32, 44, 49, 51, 56, 58, 59, 60, + 61, 70, 48, 29, 17, 29, 29, 17, 14, 15, + 17, 29, 34, 17, 29, 17, 31, 29, 17 }; /* YYR1[YYN] -- Symbol number of symbol that rule YYN derives. */ @@ -704,9 +802,10 @@ { 0, 45, 46, 46, 46, 47, 47, 47, 47, 47, 48, 48, 48, 48, 48, 48, 48, 48, 48, 50, - 49, 52, 51, 53, 53, 54, 54, 55, 56, 57, - 58, 58, 59, 60, 60, 60, 61, 62, 62, 63, - 63, 65, 64, 66, 64, 67, 64, 68, 69 + 49, 52, 51, 53, 51, 54, 54, 55, 55, 56, + 57, 58, 59, 59, 60, 61, 61, 61, 62, 63, + 63, 64, 64, 66, 65, 67, 65, 68, 65, 69, + 70 }; /* YYR2[YYN] -- Number of symbols on the right hand side of rule YYN. */ @@ -714,16 +813,17 @@ { 0, 2, 0, 2, 2, 2, 2, 2, 2, 0, 2, 2, 2, 2, 2, 2, 2, 2, 0, 0, - 5, 0, 8, 0, 2, 1, 1, 4, 4, 4, - 3, 4, 4, 5, 4, 3, 3, 2, 0, 2, - 0, 0, 7, 0, 6, 0, 5, 3, 3 + 5, 0, 8, 0, 7, 0, 2, 1, 1, 4, + 4, 4, 3, 4, 4, 5, 4, 3, 3, 2, + 0, 2, 0, 0, 7, 0, 6, 0, 5, 3, + 3 }; +enum { YYENOMEM = -2 }; + #define yyerrok (yyerrstatus = 0) #define yyclearin (yychar = YYEMPTY) -#define YYEMPTY (-2) -#define YYEOF 0 #define YYACCEPT goto yyacceptlab #define YYABORT goto yyabortlab @@ -749,10 +849,9 @@ } \ while (0) -/* Error token number */ -#define YYTERROR 1 -#define YYERRCODE 256 - +/* Backward compatibility with an undocumented macro. + Use YYerror or YYUNDEF. */ +#define YYERRCODE YYUNDEF /* Enable debugging if requested. */ @@ -770,18 +869,18 @@ } while (0) /* This macro is provided for backward compatibility. */ -#ifndef YY_LOCATION_PRINT -# define YY_LOCATION_PRINT(File, Loc) ((void) 0) -#endif +# ifndef YY_LOCATION_PRINT +# define YY_LOCATION_PRINT(File, Loc) ((void) 0) +# endif -# define YY_SYMBOL_PRINT(Title, Type, Value, Location) \ +# define YY_SYMBOL_PRINT(Title, Kind, Value, Location) \ do { \ if (yydebug) \ { \ YYFPRINTF (stderr, "%s ", Title); \ yy_symbol_print (stderr, \ - Type, Value); \ + Kind, Value); \ YYFPRINTF (stderr, "\n"); \ } \ } while (0) @@ -792,18 +891,19 @@ `-----------------------------------*/ static void -yy_symbol_value_print (FILE *yyo, int yytype, YYSTYPE const * const yyvaluep) +yy_symbol_value_print (FILE *yyo, + yysymbol_kind_t yykind, YYSTYPE const * const yyvaluep) { FILE *yyoutput = yyo; YYUSE (yyoutput); if (!yyvaluep) return; # ifdef YYPRINT - if (yytype < YYNTOKENS) - YYPRINT (yyo, yytoknum[yytype], *yyvaluep); + if (yykind < YYNTOKENS) + YYPRINT (yyo, yytoknum[yykind], *yyvaluep); # endif YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN - YYUSE (yytype); + YYUSE (yykind); YY_IGNORE_MAYBE_UNINITIALIZED_END } @@ -813,12 +913,13 @@ `---------------------------*/ static void -yy_symbol_print (FILE *yyo, int yytype, YYSTYPE const * const yyvaluep) +yy_symbol_print (FILE *yyo, + yysymbol_kind_t yykind, YYSTYPE const * const yyvaluep) { YYFPRINTF (yyo, "%s %s (", - yytype < YYNTOKENS ? "token" : "nterm", yytname[yytype]); + yykind < YYNTOKENS ? "token" : "nterm", yysymbol_name (yykind)); - yy_symbol_value_print (yyo, yytype, yyvaluep); + yy_symbol_value_print (yyo, yykind, yyvaluep); YYFPRINTF (yyo, ")"); } @@ -851,7 +952,8 @@ `------------------------------------------------*/ static void -yy_reduce_print (yy_state_t *yyssp, YYSTYPE *yyvsp, int yyrule) +yy_reduce_print (yy_state_t *yyssp, YYSTYPE *yyvsp, + int yyrule) { int yylno = yyrline[yyrule]; int yynrhs = yyr2[yyrule]; @@ -863,9 +965,8 @@ { YYFPRINTF (stderr, " $%d = ", yyi + 1); yy_symbol_print (stderr, - yystos[+yyssp[yyi + 1 - yynrhs]], - &yyvsp[(yyi + 1) - (yynrhs)] - ); + YY_ACCESSING_SYMBOL (+yyssp[yyi + 1 - yynrhs]), + &yyvsp[(yyi + 1) - (yynrhs)]); YYFPRINTF (stderr, "\n"); } } @@ -880,8 +981,8 @@ multiple parsers can coexist. */ int yydebug; #else /* !YYDEBUG */ -# define YYDPRINTF(Args) -# define YY_SYMBOL_PRINT(Title, Type, Value, Location) +# define YYDPRINTF(Args) ((void) 0) +# define YY_SYMBOL_PRINT(Title, Kind, Value, Location) # define YY_STACK_PRINT(Bottom, Top) # define YY_REDUCE_PRINT(Rule) #endif /* !YYDEBUG */ @@ -904,258 +1005,29 @@ #endif -#if YYERROR_VERBOSE -# ifndef yystrlen -# if defined __GLIBC__ && defined _STRING_H -# define yystrlen(S) (YY_CAST (YYPTRDIFF_T, strlen (S))) -# else -/* Return the length of YYSTR. */ -static YYPTRDIFF_T -yystrlen (const char *yystr) -{ - YYPTRDIFF_T yylen; - for (yylen = 0; yystr[yylen]; yylen++) - continue; - return yylen; -} -# endif -# endif -# ifndef yystpcpy -# if defined __GLIBC__ && defined _STRING_H && defined _GNU_SOURCE -# define yystpcpy stpcpy -# else -/* Copy YYSRC to YYDEST, returning the address of the terminating '\0' in - YYDEST. */ -static char * -yystpcpy (char *yydest, const char *yysrc) -{ - char *yyd = yydest; - const char *yys = yysrc; - while ((*yyd++ = *yys++) != '\0') - continue; - - return yyd - 1; -} -# endif -# endif - -# ifndef yytnamerr -/* Copy to YYRES the contents of YYSTR after stripping away unnecessary - quotes and backslashes, so that it's suitable for yyerror. The - heuristic is that double-quoting is unnecessary unless the string - contains an apostrophe, a comma, or backslash (other than - backslash-backslash). YYSTR is taken from yytname. If YYRES is - null, do not copy; instead, return the length of what the result - would have been. */ -static YYPTRDIFF_T -yytnamerr (char *yyres, const char *yystr) -{ - if (*yystr == '"') - { - YYPTRDIFF_T yyn = 0; - char const *yyp = yystr; - - for (;;) - switch (*++yyp) - { - case '\'': - case ',': - goto do_not_strip_quotes; - - case '\\': - if (*++yyp != '\\') - goto do_not_strip_quotes; - else - goto append; - - append: - default: - if (yyres) - yyres[yyn] = *yyp; - yyn++; - break; - - case '"': - if (yyres) - yyres[yyn] = '\0'; - return yyn; - } - do_not_strip_quotes: ; - } - - if (yyres) - return yystpcpy (yyres, yystr) - yyres; - else - return yystrlen (yystr); -} -# endif - -/* Copy into *YYMSG, which is of size *YYMSG_ALLOC, an error message - about the unexpected token YYTOKEN for the state stack whose top is - YYSSP. - - Return 0 if *YYMSG was successfully written. Return 1 if *YYMSG is - not large enough to hold the message. In that case, also set - *YYMSG_ALLOC to the required number of bytes. Return 2 if the - required number of bytes is too large to store. */ -static int -yysyntax_error (YYPTRDIFF_T *yymsg_alloc, char **yymsg, - yy_state_t *yyssp, int yytoken) -{ - enum { YYERROR_VERBOSE_ARGS_MAXIMUM = 5 }; - /* Internationalized format string. */ - const char *yyformat = YY_NULLPTR; - /* Arguments of yyformat: reported tokens (one for the "unexpected", - one per "expected"). */ - char const *yyarg[YYERROR_VERBOSE_ARGS_MAXIMUM]; - /* Actual size of YYARG. */ - int yycount = 0; - /* Cumulated lengths of YYARG. */ - YYPTRDIFF_T yysize = 0; - - /* There are many possibilities here to consider: - - If this state is a consistent state with a default action, then - the only way this function was invoked is if the default action - is an error action. In that case, don't check for expected - tokens because there are none. - - The only way there can be no lookahead present (in yychar) is if - this state is a consistent state with a default action. Thus, - detecting the absence of a lookahead is sufficient to determine - that there is no unexpected or expected token to report. In that - case, just report a simple "syntax error". - - Don't assume there isn't a lookahead just because this state is a - consistent state with a default action. There might have been a - previous inconsistent state, consistent state with a non-default - action, or user semantic action that manipulated yychar. - - Of course, the expected token list depends on states to have - correct lookahead information, and it depends on the parser not - to perform extra reductions after fetching a lookahead from the - scanner and before detecting a syntax error. Thus, state merging - (from LALR or IELR) and default reductions corrupt the expected - token list. However, the list is correct for canonical LR with - one exception: it will still contain any token that will not be - accepted due to an error action in a later state. - */ - if (yytoken != YYEMPTY) - { - int yyn = yypact[+*yyssp]; - YYPTRDIFF_T yysize0 = yytnamerr (YY_NULLPTR, yytname[yytoken]); - yysize = yysize0; - yyarg[yycount++] = yytname[yytoken]; - if (!yypact_value_is_default (yyn)) - { - /* Start YYX at -YYN if negative to avoid negative indexes in - YYCHECK. In other words, skip the first -YYN actions for - this state because they are default actions. */ - int yyxbegin = yyn < 0 ? -yyn : 0; - /* Stay within bounds of both yycheck and yytname. */ - int yychecklim = YYLAST - yyn + 1; - int yyxend = yychecklim < YYNTOKENS ? yychecklim : YYNTOKENS; - int yyx; - - for (yyx = yyxbegin; yyx < yyxend; ++yyx) - if (yycheck[yyx + yyn] == yyx && yyx != YYTERROR - && !yytable_value_is_error (yytable[yyx + yyn])) - { - if (yycount == YYERROR_VERBOSE_ARGS_MAXIMUM) - { - yycount = 1; - yysize = yysize0; - break; - } - yyarg[yycount++] = yytname[yyx]; - { - YYPTRDIFF_T yysize1 - = yysize + yytnamerr (YY_NULLPTR, yytname[yyx]); - if (yysize <= yysize1 && yysize1 <= YYSTACK_ALLOC_MAXIMUM) - yysize = yysize1; - else - return 2; - } - } - } - } - - switch (yycount) - { -# define YYCASE_(N, S) \ - case N: \ - yyformat = S; \ - break - default: /* Avoid compiler warnings. */ - YYCASE_(0, YY_("syntax error")); - YYCASE_(1, YY_("syntax error, unexpected %s")); - YYCASE_(2, YY_("syntax error, unexpected %s, expecting %s")); - YYCASE_(3, YY_("syntax error, unexpected %s, expecting %s or %s")); - YYCASE_(4, YY_("syntax error, unexpected %s, expecting %s or %s or %s")); - YYCASE_(5, YY_("syntax error, unexpected %s, expecting %s or %s or %s or %s")); -# undef YYCASE_ - } - - { - /* Don't count the "%s"s in the final size, but reserve room for - the terminator. */ - YYPTRDIFF_T yysize1 = yysize + (yystrlen (yyformat) - 2 * yycount) + 1; - if (yysize <= yysize1 && yysize1 <= YYSTACK_ALLOC_MAXIMUM) - yysize = yysize1; - else - return 2; - } - - if (*yymsg_alloc < yysize) - { - *yymsg_alloc = 2 * yysize; - if (! (yysize <= *yymsg_alloc - && *yymsg_alloc <= YYSTACK_ALLOC_MAXIMUM)) - *yymsg_alloc = YYSTACK_ALLOC_MAXIMUM; - return 1; - } - - /* Avoid sprintf, as that infringes on the user's name space. - Don't have undefined behavior even if the translation - produced a string with the wrong number of "%s"s. */ - { - char *yyp = *yymsg; - int yyi = 0; - while ((*yyp = *yyformat) != '\0') - if (*yyp == '%' && yyformat[1] == 's' && yyi < yycount) - { - yyp += yytnamerr (yyp, yyarg[yyi++]); - yyformat += 2; - } - else - { - ++yyp; - ++yyformat; - } - } - return 0; -} -#endif /* YYERROR_VERBOSE */ /*-----------------------------------------------. | Release the memory associated to this symbol. | `-----------------------------------------------*/ static void -yydestruct (const char *yymsg, int yytype, YYSTYPE *yyvaluep) +yydestruct (const char *yymsg, + yysymbol_kind_t yykind, YYSTYPE *yyvaluep) { YYUSE (yyvaluep); if (!yymsg) yymsg = "Deleting"; - YY_SYMBOL_PRINT (yymsg, yytype, yyvaluep, yylocationp); + YY_SYMBOL_PRINT (yymsg, yykind, yyvaluep, yylocationp); YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN - YYUSE (yytype); + YYUSE (yykind); YY_IGNORE_MAYBE_UNINITIALIZED_END } - - /* The lookahead symbol. */ int yychar; @@ -1165,6 +1037,8 @@ int yynerrs; + + /*----------. | yyparse. | `----------*/ @@ -1183,6 +1057,9 @@ Refer to the stacks through separate pointers, to allow yyoverflow to reallocate them elsewhere. */ + /* Their size. */ + YYPTRDIFF_T yystacksize; + /* The state stack. */ yy_state_t yyssa[YYINITDEPTH]; yy_state_t *yyss; @@ -1193,22 +1070,16 @@ YYSTYPE *yyvs; YYSTYPE *yyvsp; - YYPTRDIFF_T yystacksize; - int yyn; + /* The return value of yyparse. */ int yyresult; /* Lookahead token as an internal (translated) token number. */ - int yytoken = 0; + yysymbol_kind_t yytoken = YYSYMBOL_YYEMPTY; /* The variables used to return semantic value and location from the action routines. */ YYSTYPE yyval; -#if YYERROR_VERBOSE - /* Buffer for error messages, and its allocated size. */ - char yymsgbuf[128]; - char *yymsg = yymsgbuf; - YYPTRDIFF_T yymsg_alloc = sizeof yymsgbuf; -#endif + #define YYPOPSTACK(N) (yyvsp -= (N), yyssp -= (N)) @@ -1216,15 +1087,17 @@ Keep to zero when no symbol should be popped. */ int yylen = 0; + yynerrs = 0; + yystate = 0; + yyerrstatus = 0; + + yystacksize = YYINITDEPTH; yyssp = yyss = yyssa; yyvsp = yyvs = yyvsa; - yystacksize = YYINITDEPTH; + YYDPRINTF ((stderr, "Starting parse\n")); - yystate = 0; - yyerrstatus = 0; - yynerrs = 0; yychar = YYEMPTY; /* Cause a token to be read. */ goto yysetstate; @@ -1247,6 +1120,7 @@ YY_IGNORE_USELESS_CAST_BEGIN *yyssp = YY_CAST (yy_state_t, yystate); YY_IGNORE_USELESS_CAST_END + YY_STACK_PRINT (yyss, yyssp); if (yyss + yystacksize - 1 <= yyssp) #if !defined yyoverflow && !defined YYSTACK_RELOCATE @@ -1292,7 +1166,7 @@ goto yyexhaustedlab; YYSTACK_RELOCATE (yyss_alloc, yyss); YYSTACK_RELOCATE (yyvs_alloc, yyvs); -# undef YYSTACK_RELOCATE +# undef YYSTACK_RELOCATE if (yyss1 != yyssa) YYSTACK_FREE (yyss1); } @@ -1331,18 +1205,29 @@ /* Not known => get a lookahead token if don't already have one. */ - /* YYCHAR is either YYEMPTY or YYEOF or a valid lookahead symbol. */ + /* YYCHAR is either empty, or end-of-input, or a valid lookahead. */ if (yychar == YYEMPTY) { - YYDPRINTF ((stderr, "Reading a token: ")); + YYDPRINTF ((stderr, "Reading a token\n")); yychar = yylex (); } if (yychar <= YYEOF) { - yychar = yytoken = YYEOF; + yychar = YYEOF; + yytoken = YYSYMBOL_YYEOF; YYDPRINTF ((stderr, "Now at end of input.\n")); } + else if (yychar == YYerror) + { + /* The scanner already issued an error message, process directly + to error recovery. But do not keep the error token as + lookahead, it is too special and may lead us to an endless + loop in error recovery. */ + yychar = YYUNDEF; + yytoken = YYSYMBOL_YYerror; + goto yyerrlab1; + } else { yytoken = YYTRANSLATE (yychar); @@ -1443,80 +1328,83 @@ break; case 23: + { + (yyval.dev) = new_device_reference(cur_parent, cur_chip_instance, (yyvsp[-1].string), (yyvsp[0].number)); + cur_parent = (yyval.dev)->last_bus; +} + break; + + case 24: + { + cur_parent = (yyvsp[-2].dev)->parent; +} + break; + + case 25: { (yyval.string) = NULL; } break; - case 24: + case 26: { (yyval.string) = (yyvsp[0].string); } break; - case 27: + case 29: { add_resource(cur_parent, (yyvsp[-3].number), strtol((yyvsp[-2].string), NULL, 0), strtol((yyvsp[0].string), NULL, 0)); } break; - case 28: + case 30: { add_reference(cur_chip_instance, (yyvsp[0].string), (yyvsp[-2].string)); } break; - case 29: + case 31: { add_register(cur_chip_instance, (yyvsp[-2].string), (yyvsp[0].string)); } break; - case 30: + case 32: { add_pci_subsystem_ids(cur_parent, strtol((yyvsp[-1].string), NULL, 16), strtol((yyvsp[0].string), NULL, 16), 0); } break; - case 31: + case 33: { add_pci_subsystem_ids(cur_parent, strtol((yyvsp[-2].string), NULL, 16), strtol((yyvsp[-1].string), NULL, 16), 1); } break; - case 32: + case 34: { add_ioapic_info(cur_parent, strtol((yyvsp[-2].string), NULL, 16), (yyvsp[-1].string), strtol((yyvsp[0].string), NULL, 16)); } break; - case 33: + case 35: { add_slot_desc(cur_parent, (yyvsp[-3].string), (yyvsp[-2].string), (yyvsp[-1].string), (yyvsp[0].string)); } break; - case 34: + case 36: { add_slot_desc(cur_parent, (yyvsp[-2].string), (yyvsp[-1].string), (yyvsp[0].string), NULL); } break; - case 35: + case 37: { add_slot_desc(cur_parent, (yyvsp[-1].string), (yyvsp[0].string), NULL, NULL); } break; - case 36: + case 38: { } break; - case 41: + case 43: { cur_field = new_fw_config_field((yyvsp[-2].string), strtoul((yyvsp[-1].string), NULL, 0), strtoul((yyvsp[0].string), NULL, 0)); } break; - case 42: - { } - break; - - case 43: - { - cur_field = new_fw_config_field((yyvsp[-1].string), strtoul((yyvsp[0].string), NULL, 0), strtoul((yyvsp[0].string), NULL, 0)); -} - break; - case 44: { } break; case 45: - { - cur_field = get_fw_config_field((yyvsp[0].string)); + { + cur_field = new_fw_config_field((yyvsp[-1].string), strtoul((yyvsp[0].string), NULL, 0), strtoul((yyvsp[0].string), NULL, 0)); } break; @@ -1525,10 +1413,20 @@ break; case 47: - { add_fw_config_option(cur_field, (yyvsp[-1].string), strtoul((yyvsp[0].string), NULL, 0)); } + { + cur_field = get_fw_config_field((yyvsp[0].string)); +} break; case 48: + { } + break; + + case 49: + { add_fw_config_option(cur_field, (yyvsp[-1].string), strtoul((yyvsp[0].string), NULL, 0)); } + break; + + case 50: { add_fw_config_probe(cur_parent, (yyvsp[-1].string), (yyvsp[0].string)); } break; @@ -1547,11 +1445,10 @@ case of YYERROR or YYBACKUP, subsequent parser actions might lead to an incorrect destructor call or verbose syntax error message before the lookahead is translated. */ - YY_SYMBOL_PRINT ("-> $$ =", yyr1[yyn], &yyval, &yyloc); + YY_SYMBOL_PRINT ("-> $$ =", YY_CAST (yysymbol_kind_t, yyr1[yyn]), &yyval, &yyloc); YYPOPSTACK (yylen); yylen = 0; - YY_STACK_PRINT (yyss, yyssp); *++yyvsp = yyval; @@ -1575,50 +1472,14 @@ yyerrlab: /* Make sure we have latest lookahead translation. See comments at user semantic actions for why this is necessary. */ - yytoken = yychar == YYEMPTY ? YYEMPTY : YYTRANSLATE (yychar); - + yytoken = yychar == YYEMPTY ? YYSYMBOL_YYEMPTY : YYTRANSLATE (yychar); /* If not already recovering from an error, report this error. */ if (!yyerrstatus) { ++yynerrs; -#if ! YYERROR_VERBOSE yyerror (YY_("syntax error")); -#else -# define YYSYNTAX_ERROR yysyntax_error (&yymsg_alloc, &yymsg, \ - yyssp, yytoken) - { - char const *yymsgp = YY_("syntax error"); - int yysyntax_error_status; - yysyntax_error_status = YYSYNTAX_ERROR; - if (yysyntax_error_status == 0) - yymsgp = yymsg; - else if (yysyntax_error_status == 1) - { - if (yymsg != yymsgbuf) - YYSTACK_FREE (yymsg); - yymsg = YY_CAST (char *, YYSTACK_ALLOC (YY_CAST (YYSIZE_T, yymsg_alloc))); - if (!yymsg) - { - yymsg = yymsgbuf; - yymsg_alloc = sizeof yymsgbuf; - yysyntax_error_status = 2; - } - else - { - yysyntax_error_status = YYSYNTAX_ERROR; - yymsgp = yymsg; - } - } - yyerror (yymsgp); - if (yysyntax_error_status == 2) - goto yyexhaustedlab; - } -# undef YYSYNTAX_ERROR -#endif } - - if (yyerrstatus == 3) { /* If just tried and failed to reuse lookahead token after an @@ -1667,13 +1528,14 @@ yyerrlab1: yyerrstatus = 3; /* Each real token shifted decrements this. */ + /* Pop stack until we find a state that shifts the error token. */ for (;;) { yyn = yypact[yystate]; if (!yypact_value_is_default (yyn)) { - yyn += YYTERROR; - if (0 <= yyn && yyn <= YYLAST && yycheck[yyn] == YYTERROR) + yyn += YYSYMBOL_YYerror; + if (0 <= yyn && yyn <= YYLAST && yycheck[yyn] == YYSYMBOL_YYerror) { yyn = yytable[yyn]; if (0 < yyn) @@ -1687,7 +1549,7 @@ yydestruct ("Error: popping", - yystos[yystate], yyvsp); + YY_ACCESSING_SYMBOL (yystate), yyvsp); YYPOPSTACK (1); yystate = *yyssp; YY_STACK_PRINT (yyss, yyssp); @@ -1699,7 +1561,7 @@ /* Shift the error token. */ - YY_SYMBOL_PRINT ("Shifting", yystos[yyn], yyvsp, yylsp); + YY_SYMBOL_PRINT ("Shifting", YY_ACCESSING_SYMBOL (yyn), yyvsp, yylsp); yystate = yyn; goto yynewstate; @@ -1721,7 +1583,7 @@ goto yyreturn; -#if !defined yyoverflow || YYERROR_VERBOSE +#if !defined yyoverflow /*-------------------------------------------------. | yyexhaustedlab -- memory exhaustion comes here. | `-------------------------------------------------*/ @@ -1751,17 +1613,15 @@ while (yyssp != yyss) { yydestruct ("Cleanup: popping", - yystos[+*yyssp], yyvsp); + YY_ACCESSING_SYMBOL (+*yyssp), yyvsp); YYPOPSTACK (1); } #ifndef yyoverflow if (yyss != yyssa) YYSTACK_FREE (yyss); #endif -#if YYERROR_VERBOSE - if (yymsg != yymsgbuf) - YYSTACK_FREE (yymsg); -#endif + return yyresult; } + diff --git a/util/sconfig/sconfig.tab.h_shipped b/util/sconfig/sconfig.tab.h_shipped index b556bba..b05831f 100644 --- a/util/sconfig/sconfig.tab.h_shipped +++ b/util/sconfig/sconfig.tab.h_shipped @@ -1,4 +1,4 @@ -/* A Bison parser, made by GNU Bison 3.5.3. */ +/* A Bison parser, made by GNU Bison 3.6.3. */ /* Bison interface for Yacc-like parsers in C @@ -31,8 +31,9 @@ This special exception was added by the Free Software Foundation in version 2.2 of Bison. */ -/* Undocumented macros, especially those whose name start with YY_, - are private implementation details. Do not rely on them. */ +/* DO NOT RELY ON FEATURES THAT ARE NOT DOCUMENTED in the manual, + especially those whose name start with YY_ or yy_. They are + private implementation details that can be changed or removed. */ #ifndef YY_YY_SRC_COREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED # define YY_YY_SRC_COREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED @@ -44,54 +45,59 @@ extern int yydebug; #endif -/* Token type. */ +/* Token kinds. */ #ifndef YYTOKENTYPE # define YYTOKENTYPE enum yytokentype { - CHIP = 258, - DEVICE = 259, - REGISTER = 260, - ALIAS = 261, - REFERENCE = 262, - ASSOCIATION = 263, - BOOL = 264, - STATUS = 265, - MANDATORY = 266, - BUS = 267, - RESOURCE = 268, - END = 269, - EQUALS = 270, - HEX = 271, - STRING = 272, - PCI = 273, - PNP = 274, - I2C = 275, - APIC = 276, - CPU_CLUSTER = 277, - CPU = 278, - DOMAIN = 279, - IRQ = 280, - DRQ = 281, - SLOT_DESC = 282, - IO = 283, - NUMBER = 284, - SUBSYSTEMID = 285, - INHERIT = 286, - IOAPIC_IRQ = 287, - IOAPIC = 288, - PCIINT = 289, - GENERIC = 290, - SPI = 291, - USB = 292, - MMIO = 293, - LPC = 294, - ESPI = 295, - FW_CONFIG_TABLE = 296, - FW_CONFIG_FIELD = 297, - FW_CONFIG_OPTION = 298, - FW_CONFIG_PROBE = 299 + YYEMPTY = -2, + YYEOF = 0, /* "end of file" */ + YYerror = 256, /* error */ + YYUNDEF = 257, /* "invalid token" */ + CHIP = 258, /* CHIP */ + DEVICE = 259, /* DEVICE */ + REGISTER = 260, /* REGISTER */ + ALIAS = 261, /* ALIAS */ + REFERENCE = 262, /* REFERENCE */ + ASSOCIATION = 263, /* ASSOCIATION */ + BOOL = 264, /* BOOL */ + STATUS = 265, /* STATUS */ + MANDATORY = 266, /* MANDATORY */ + BUS = 267, /* BUS */ + RESOURCE = 268, /* RESOURCE */ + END = 269, /* END */ + EQUALS = 270, /* EQUALS */ + HEX = 271, /* HEX */ + STRING = 272, /* STRING */ + PCI = 273, /* PCI */ + PNP = 274, /* PNP */ + I2C = 275, /* I2C */ + APIC = 276, /* APIC */ + CPU_CLUSTER = 277, /* CPU_CLUSTER */ + CPU = 278, /* CPU */ + DOMAIN = 279, /* DOMAIN */ + IRQ = 280, /* IRQ */ + DRQ = 281, /* DRQ */ + SLOT_DESC = 282, /* SLOT_DESC */ + IO = 283, /* IO */ + NUMBER = 284, /* NUMBER */ + SUBSYSTEMID = 285, /* SUBSYSTEMID */ + INHERIT = 286, /* INHERIT */ + IOAPIC_IRQ = 287, /* IOAPIC_IRQ */ + IOAPIC = 288, /* IOAPIC */ + PCIINT = 289, /* PCIINT */ + GENERIC = 290, /* GENERIC */ + SPI = 291, /* SPI */ + USB = 292, /* USB */ + MMIO = 293, /* MMIO */ + LPC = 294, /* LPC */ + ESPI = 295, /* ESPI */ + FW_CONFIG_TABLE = 296, /* FW_CONFIG_TABLE */ + FW_CONFIG_FIELD = 297, /* FW_CONFIG_FIELD */ + FW_CONFIG_OPTION = 298, /* FW_CONFIG_OPTION */ + FW_CONFIG_PROBE = 299 /* FW_CONFIG_PROBE */ }; + typedef enum yytokentype yytoken_kind_t; #endif /* Value type. */ diff --git a/util/sconfig/sconfig.y b/util/sconfig/sconfig.y index d441ff8..a75b908 100755 --- a/util/sconfig/sconfig.y +++ b/util/sconfig/sconfig.y @@ -44,6 +44,14 @@ cur_parent = $<dev>6->parent; }; +device: DEVICE REFERENCE STRING status { + $<dev>$ = new_device_reference(cur_parent, cur_chip_instance, $<string>3, $<number>4); + cur_parent = $<dev>$->last_bus; +} + devicechildren END { + cur_parent = $<dev>5->parent; +}; + alias: /* empty */ { $<string>$ = NULL; } | ALIAS STRING { -- To view, visit https://review.coreboot.org/c/coreboot/+/44037 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7500a62f6211243b519424ef3834b9e7615e2fd Gerrit-Change-Number: 44037 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

7 hours, 17 minutes

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Change in coreboot[master]: payloads/external: Add STM build as a payload

by Eugene Myers (Code Review)

Hello Eugene Myers, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44687 to review the following change. Change subject: payloads/external: Add STM build as a payload ...................................................................... payloads/external: Add STM build as a payload The patch incorporate the STM build as a part of the coreboot build. A separate patch lists and documents the options that the developer can use. In most cases the default options will suffice. Change-Id: I8c6e0c85edd4e2b0658791553bd9947656e8c796 Signed-off-by: Eugene D Myers <cedarhouse(a)comcast.net> --- M payloads/external/Makefile.inc A payloads/external/stm/Makefile 2 files changed, 59 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/44687/1 diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index ef0990c..6389ca8 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -303,3 +303,17 @@ CONFIG_YABITS_MASTER=$(CONFIG_YABITS_MASTER) \ CONFIG_YABITS_STABLE=$(CONFIG_YABITS_STABLE) \ MFLAGS= MAKEFLAGS= + +# STM + +payloads/external/stm/STM/Stm/build/StmPkg/Core/stm.bin stm: + $(MAKE) -C payloads/external/stm \ + CONFIG_STM_UART=$(CONFIG_STM_UART) \ + CONFIG_STM_HEAPSIZE=$(CONFIG_STM_HEAPSIZE) \ + CONFIG_STM_BUILD=$(CONFIG_STM_BUILD) \ + CONFIG_STM_GIT_REPO=$(CONFIG_STM_GIT_REPO) \ + CONFIG_STM_GIT_BRANCH=$(CONFIG_STM_GIT_BRANCH) \ + CONFIG_STM_STMPE_ENABLED=$(CONFIG_STM_STMPE_ENABLED) \ + CONFIG_STM_CBMEM_CONSOLE=$(CONFIG_STM_CBMEM_CONSOLE) + +.PHONY: stm payloads/external/stm/STM/Stm/build/StmPkg/Core/stm.bin diff --git a/payloads/external/stm/Makefile b/payloads/external/stm/Makefile new file mode 100644 index 0000000..072d91b --- /dev/null +++ b/payloads/external/stm/Makefile @@ -0,0 +1,45 @@ + +project_name=STM +project_dir=$(CURDIR)/$(project_name) +build_dir=$(CURDIR)/$(project_name)/Stm/build +project_git_repo=$(CONFIG_STM_GIT_REPO) +project_git_branch=$(CONFIG_STM_GIT_BRANCH) + + +all: build + +$(project_dir): + echo " Cloning $(project_name) from $(project_git_repo)" + git clone $(project_git_repo) $(project_name) + +fetch: $(project_dir) + echo " Fetching new commits"; + cd $(project_dir); \ + echo " Fetching new commits from the $(project_name) branch $(project_git_branch) git repo"; \ + git pull; + +checkout: fetch + echo " Checking out STM - $(project_git_branch)" + cd $(project_name); git checkout $(project_git_branch); git pull + +build: checkout + echo " Build STM" + cd STM/Stm; \ + rm -rf build; \ + mkdir -p build; \ + cd build; \ + cmake .. -DBIOS=coreboot \ + -DUART=$(CONFIG_STM_UART) \ + -DHEAPSIZE=$(CONFIG_STM_HEAPSIZE) \ + -DCBMEM_ENABLE=$(CONFIG_STM_CBMEM_CONSOLE) \ + -DSTMPE_ENABLED=$(CONFIG_STM_STMPE_ENABLED) \ + -DBUILD=$(CONFIG_STM_BUILD); \ + $(MAKE); + +clean: + rm -rf $(build_dir) + +distclean: + rm -rf $(project_dir) + +.PHONY: checkout build clean distclean fetch -- To view, visit https://review.coreboot.org/c/coreboot/+/44687 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c6e0c85edd4e2b0658791553bd9947656e8c796 Gerrit-Change-Number: 44687 Gerrit-PatchSet: 1 Gerrit-Owner: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Reviewer: Eugene Myers <cedarhouse(a)comcast.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

7 hours, 19 minutes

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Change in coreboot[master]: sb/intel/lynxpoint: Expand RCBA register list

by Angel Pons (Code Review)

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40062 ) Change subject: sb/intel/lynxpoint: Expand RCBA register list ...................................................................... sb/intel/lynxpoint: Expand RCBA register list Some registers do not seem to exist, and many were missing. Change-Id: I6757f4a748cde9f3bed3bacf32112f3259de1d87 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/pch.h 1 file changed, 91 insertions(+), 59 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/40062/1 diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 0a62803..6d6590a 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -445,45 +445,11 @@ /* Southbridge IO BARs */ +#define PMBASE 0x40 #define GPIOBASE 0x48 -#define PMBASE 0x40 +#define CIR0050 0x0050 /* 32bit */ -#define VCH 0x0000 /* 32bit */ -#define VCAP1 0x0004 /* 32bit */ -#define VCAP2 0x0008 /* 32bit */ -#define PVC 0x000c /* 16bit */ -#define PVS 0x000e /* 16bit */ - -#define V0CAP 0x0010 /* 32bit */ -#define V0CTL 0x0014 /* 32bit */ -#define V0STS 0x001a /* 16bit */ - -#define V1CAP 0x001c /* 32bit */ -#define V1CTL 0x0020 /* 32bit */ -#define V1STS 0x0026 /* 16bit */ - -#define RCTCL 0x0100 /* 32bit */ -#define ESD 0x0104 /* 32bit */ -#define ULD 0x0110 /* 32bit */ -#define ULBA 0x0118 /* 64bit */ - -#define RP1D 0x0120 /* 32bit */ -#define RP1BA 0x0128 /* 64bit */ -#define RP2D 0x0130 /* 32bit */ -#define RP2BA 0x0138 /* 64bit */ -#define RP3D 0x0140 /* 32bit */ -#define RP3BA 0x0148 /* 64bit */ -#define RP4D 0x0150 /* 32bit */ -#define RP4BA 0x0158 /* 64bit */ -#define HDD 0x0160 /* 32bit */ -#define HDBA 0x0168 /* 64bit */ -#define RP5D 0x0170 /* 32bit */ -#define RP5BA 0x0178 /* 64bit */ -#define RP6D 0x0180 /* 32bit */ -#define RP6BA 0x0188 /* 64bit */ - -#define RPC 0x0400 /* 32bit */ #define RPFN 0x0404 /* 32bit */ /* Root Port configuratinon space hide */ @@ -495,6 +461,9 @@ /* Root Port function number mask */ #define RPFN_FNMASK(port) (7 << ((port) * 4)) +#define CIR0900 0x0900 /* 32bit */ +#define CIR1100 0x1100 /* 32bit */ + #define TRSR 0x1e00 /* 8bit */ #define TRCR 0x1e10 /* 64bit */ #define TWDR 0x1e18 /* 64bit */ @@ -504,6 +473,41 @@ #define IOTR2 0x1e90 /* 64bit */ #define IOTR3 0x1e98 /* 64bit */ +#define V0CTL 0x2014 /* 32bit */ +#define V0STS 0x201a /* 16bit */ + +#define V1CTL 0x2020 /* 32bit */ +#define V1STS 0x2026 /* 16bit */ + +#define VPCTL 0x2030 /* 32bit */ +#define VPSTS 0x2038 /* 16bit */ + +#define VMCTL 0x2040 /* 32bit */ +#define VMSTS 0x2048 /* 16bit */ + +#define CIR2088 0x2088 +#define REC 0x20ac +#define LCAP 0x21a4 +#define LCTL 0x21a8 +#define DMIC 0x2234 +#define CIR2238 0x2238 +#define CIR228C 0x228c +#define DMC 0x2304 +#define CIR2314 0x2314 +#define CIR2320 0x2320 + +/* IO Buffer Programming */ +#define IOBPIRI 0x2330 +#define IOBPD 0x2334 +#define IOBPS 0x2338 +#define IOBPS_READY 0x0001 +#define IOBPS_TX_MASK 0x0006 +#define IOBPS_MASK 0xff00 +#define IOBPS_READ 0x0600 +#define IOBPS_WRITE 0x0700 +#define IOBPU 0x233a +#define IOBPU_MAGIC 0xf000 + #define TCTL 0x3000 /* 8bit */ #define NOINT 0 @@ -526,18 +530,6 @@ #define PIRQG 6 #define PIRQH 7 -/* IO Buffer Programming */ -#define IOBPIRI 0x2330 -#define IOBPD 0x2334 -#define IOBPS 0x2338 -#define IOBPS_READY 0x0001 -#define IOBPS_TX_MASK 0x0006 -#define IOBPS_MASK 0xff00 -#define IOBPS_READ 0x0600 -#define IOBPS_WRITE 0x0700 -#define IOBPU 0x233a -#define IOBPU_MAGIC 0xf000 - #define D31IP 0x3100 /* 32bit */ #define D31IP_TTIP 24 /* Thermal Throttle Pin */ #define D31IP_SIP2 20 /* SATA Pin 2 */ @@ -581,26 +573,66 @@ #define D20IR 0x3160 /* 16bit */ #define D21IR 0x3164 /* 16bit */ #define D19IR 0x3168 /* 16bit */ -#define ACPIIRQEN 0x31e0 /* 32bit */ -#define OIC 0x31fe /* 16bit */ -#define PMSYNC_CONFIG 0x33c4 /* 32bit */ -#define PMSYNC_CONFIG2 0x33cc /* 32bit */ -#define SOFT_RESET_CTRL 0x38f4 -#define SOFT_RESET_DATA 0x38f8 -#define DIR_ROUTE(a,b,c,d) \ - (((d) << DIR_IDR) | ((c) << DIR_ICR) | \ - ((b) << DIR_IBR) | ((a) << DIR_IAR)) +#define ACPIIRQEN 0x31e0 /* 32bit */ + +#define OIC 0x31fe /* 16bit */ + +#define PRSTS 0x3310 +#define CIR3314 0x3314 +#define PM_CFG 0x3318 +#define CIR3324 0x3324 +#define DEEP_S3_POL 0x3328 +#define DEEP_S4_POL 0x332c +#define DEEP_S5_POL 0x3330 +#define PM_CFG2 0x333c +#define CIR3340 0x3340 +#define CIR3344 0x3344 +#define CIR3348 0x3348 +#define CIR3350 0x3350 +#define CIR3360 0x3360 +#define CIR3368 0x3368 +#define CIR3378 0x3378 +#define CIR337C 0x337c +#define CIR3388 0x3388 +#define CIR3390 0x3390 +#define CIR33A0 0x33a0 +#define CIR33B0 0x33b0 +#define CIR33C0 0x33c0 +#define PMSYNC_CONFIG 0x33c4 /* 32bit */ +#define PMSYNC 0x33c8 +#define PMSYNC_CONFIG2 0x33cc /* 32bit */ +#define CIR33D0 0x33d0 +#define CIR33D4 0x33d4 #define RC 0x3400 /* 32bit */ #define HPTC 0x3404 /* 32bit */ #define GCS 0x3410 /* 32bit */ #define BUC 0x3414 /* 32bit */ -#define PCH_DISABLE_GBE (1 << 5) +#define PCH_DISABLE_GBE (1 << 5) +#define RC 0x3400 /* 32bit */ +#define HPTC 0x3404 /* 32bit */ +#define GCS 0x3410 /* 32bit */ +#define BUC 0x3414 /* 32bit */ #define FD 0x3418 /* 32bit */ +#define CG 0x341c /* 32bit */ +#define FDSW 0x3420 #define DISPBDF 0x3424 /* 16bit */ #define FD2 0x3428 /* 32bit */ -#define CG 0x341c /* 32bit */ +#define GSX_CTRL 0x3454 + +#define CIR3A28 0x3a28 +#define CIR3A2C 0x3a2c +#define CIR3A6C 0x3a6c +#define CIR3A80 0x3a80 +#define CIR3A84 0x3a84 +#define CIR3A88 0x3a88 + +#define SOFT_RESET_CTRL 0x38f4 +#define SOFT_RESET_DATA 0x38f8 + +#define DIR_ROUTE(a, b, c, d) \ + (((d) << DIR_IDR) | ((c) << DIR_ICR) | ((b) << DIR_IBR) | ((a) << DIR_IAR)) /* Function Disable 1 RCBA 0x3418 */ #define PCH_DISABLE_ALWAYS (1 << 0) -- To view, visit https://review.coreboot.org/c/coreboot/+/40062 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6757f4a748cde9f3bed3bacf32112f3259de1d87 Gerrit-Change-Number: 40062 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/supermicro/x11-lga1151v2-series: Add x11sch-l4nf support

by Christian Walter (Code Review)

Christian Walter has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44578 ) Change subject: mb/supermicro/x11-lga1151v2-series: Add x11sch-l4nf support ...................................................................... mb/supermicro/x11-lga1151v2-series: Add x11sch-l4nf support Add initial support for another CFL variant. Quite hacky right now - but seems to boot Linux with Tianocore. Right now I need to enable, but hidden, the two additional NICs. Not sure where this comes from - maybe GPIOs. Change-Id: I4c3d3aaf473ecc6106349245b5de1a6025ae0e9a Signed-off-by: Christian Walter <christian.walter(a)9elements.com> --- M src/mainboard/supermicro/x11-lga1151v2-series/Kconfig M src/mainboard/supermicro/x11-lga1151v2-series/Kconfig.name A src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/Makefile.inc A src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/board_info.txt A src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/gpio.c A src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/include/variant/gpio.h A src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/include/variant/variants.h A src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/overridetree.cb 8 files changed, 460 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/44578/1 diff --git a/src/mainboard/supermicro/x11-lga1151v2-series/Kconfig b/src/mainboard/supermicro/x11-lga1151v2-series/Kconfig index ed29b16..4029fce 100644 --- a/src/mainboard/supermicro/x11-lga1151v2-series/Kconfig +++ b/src/mainboard/supermicro/x11-lga1151v2-series/Kconfig @@ -25,6 +25,7 @@ config MAINBOARD_PART_NUMBER string default "X11SCH-F" if BOARD_SUPERMICRO_X11SCH_F + default "X11SCH-L4NF" if BOARD_SUPERMICRO_X11SCH_L4NF config MAINBOARD_DIR string @@ -33,10 +34,12 @@ config VARIANT_DIR string default "x11sch-f" if BOARD_SUPERMICRO_X11SCH_F + default "x11sch-l4nf" if BOARD_SUPERMICRO_X11SCH_L4NF config MAINBOARD_PART_NUMBER string default "X11SCH-F" if BOARD_SUPERMICRO_X11SCH_F + default "X11SCH-L4NF" if BOARD_SUPERMICRO_X11SCH_L4NF config MAX_CPUS int diff --git a/src/mainboard/supermicro/x11-lga1151v2-series/Kconfig.name b/src/mainboard/supermicro/x11-lga1151v2-series/Kconfig.name index 8ab4f1e..d25b19f 100644 --- a/src/mainboard/supermicro/x11-lga1151v2-series/Kconfig.name +++ b/src/mainboard/supermicro/x11-lga1151v2-series/Kconfig.name @@ -1,3 +1,8 @@ config BOARD_SUPERMICRO_X11SCH_F bool "X11SCH-F" select BOARD_SUPERMICRO_BASEBOARD_X11_LGA1151V2_SERIES + +config BOARD_SUPERMICRO_X11SCH_L4NF + bool "X11SCH-L4NF" + select BOARD_SUPERMICRO_BASEBOARD_X11_LGA1151V2_SERIES + diff --git a/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/Makefile.inc b/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/Makefile.inc new file mode 100644 index 0000000..8914639 --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/Makefile.inc @@ -0,0 +1,2 @@ +bootblock-y += gpio.c +ramstage-y += gpio.c diff --git a/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/board_info.txt b/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/board_info.txt new file mode 100644 index 0000000..a66959a --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/board_info.txt @@ -0,0 +1,7 @@ +Category: server +Vendor name: Supermicro +Board name: X11SCH-L4NF +Board URL: https://www.supermicro.com/en/products/motherboard/X11SCH-F +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/gpio.c b/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/gpio.c new file mode 100644 index 0000000..b2a72f5 --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/gpio.c @@ -0,0 +1,296 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "include/variant/gpio.h" +#include <commonlib/helpers.h> + +/* Pad configuration in ramstage */ +static const struct pad_config gpio_table[] = { + + /* ------- GPIO Community 0 ------- */ + + /* ------- GPIO Group GPP_A ------- */ + _PAD_CFG_STRUCT(GPP_A0, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* ESPI_ALERT1# */ + _PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* ESPI_IO0 */ + _PAD_CFG_STRUCT(GPP_A2, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* ESPI_IO1 */ + _PAD_CFG_STRUCT(GPP_A3, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* ESPI_IO2 */ + _PAD_CFG_STRUCT(GPP_A4, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* ESPI_IO3 */ + _PAD_CFG_STRUCT(GPP_A5, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* ESPI_CS0# */ + _PAD_CFG_STRUCT(GPP_A6, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A7, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* ESPI_ALERT0# */ + _PAD_CFG_STRUCT(GPP_A8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* CLKRUN# */ + _PAD_CFG_STRUCT(GPP_A9, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* ESPI_CLK */ + _PAD_CFG_STRUCT(GPP_A10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), /* CLKOUT_LPC1 */ + _PAD_CFG_STRUCT(GPP_A11, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A12, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), /* SUSWARN#/SUSPWRDNACK */ + _PAD_CFG_STRUCT(GPP_A14, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* ESPI_RESET# */ + _PAD_CFG_STRUCT(GPP_A15, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SUSACK# */ + PAD_CFG_GPO(GPP_A16, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_A17, 0, DEEP), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_A18, NONE, DEEP, OFF, ACPI), /* GPIO */ + /* GPP_A19 - RESERVED */ + _PAD_CFG_STRUCT(GPP_A20, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_A21, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_A22, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_A23, NONE, DEEP, OFF, ACPI), /* GPIO */ + + /* ------- GPIO Group GPP_B ------- */ + PAD_CFG_GPO(GPP_B0, 0, DEEP), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B1, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + PAD_CFG_GPO(GPP_B3, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_B4, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_B5, 0, DEEP), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B6, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + PAD_CFG_GPO(GPP_B7, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_B8, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_B9, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_B10, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_B11, 0, DEEP), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SLP_S0# */ + _PAD_CFG_STRUCT(GPP_B13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* PLTRST# */ + _PAD_CFG_STRUCT(GPP_B14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SPKR */ + PAD_CFG_GPO(GPP_B15, 1, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_B16, 1, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_B17, 0, DEEP), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B18, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B19, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPO(GPP_B20, 1, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_B21, 1, DEEP), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B22, NONE, DEEP, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B23, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* PCHHOT# */ + + /* ------- GPIO Community 1 ------- */ + + /* ------- GPIO Group GPP_C ------- */ + /* GPP_C0 - RESERVED */ + /* GPP_C1 - RESERVED */ + _PAD_CFG_STRUCT(GPP_C2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + /* GPP_C3 - RESERVED */ + /* GPP_C4 - RESERVED */ + PAD_CFG_GPO(GPP_C5, 0, DEEP), /* GPIO */ + /* GPP_C6 - RESERVED */ + /* GPP_C7 - RESERVED */ + _PAD_CFG_STRUCT(GPP_C8, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_C9, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPO(GPP_C10, 1, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_C11, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_C12, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_C13, 0, DEEP), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C14, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + PAD_CFG_GPO(GPP_C15, 0, DEEP), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C16, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0), /* I2C0_SDA */ + _PAD_CFG_STRUCT(GPP_C17, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0), /* I2C0_SCL */ + _PAD_CFG_STRUCT(GPP_C18, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0), /* I2C1_SDA */ + _PAD_CFG_STRUCT(GPP_C19, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0), /* I2C1_SCL */ + /* GPP_C20 - RESERVED */ + PAD_CFG_GPO(GPP_C21, 1, DEEP), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C22, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + + /* ------- GPIO Group GPP_D ------- */ + _PAD_CFG_STRUCT(GPP_D0, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + PAD_CFG_GPO(GPP_D1, 1, PLTRST), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D2, NONE, DEEP, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D3, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D4, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + PAD_CFG_GPO(GPP_D5, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D6, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D7, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D8, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D9, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D10, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D11, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D12, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D13, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D14, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D15, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D16, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D17, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D18, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D19, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D20, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D21, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D22, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D23, 0, DEEP), /* GPIO */ + + /* ------- GPIO Group GPP_G ------- */ + PAD_CFG_GPO(GPP_G0, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_G1, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_G2, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_G3, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_G4, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_G5, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_G6, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_G7, 0, DEEP), /* GPIO */ + + /* ------- GPIO Group AZA ------- */ + + /* ------- GPIO Group VGPIO_0 ------- */ + + /* ------- GPIO Group VGPIO_1 ------- */ + + /* ------- GPIO Community 2 ------- */ + + /* ------- GPIO Group GPD ------- */ + PAD_CFG_GPO(GPD0, 0, DEEP), /* GPIO */ + _PAD_CFG_STRUCT(GPD1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* ACPRESENT */ + _PAD_CFG_STRUCT(GPD2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* LAN_WAKE# */ + _PAD_CFG_STRUCT(GPD3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* PRWBTN# */ + _PAD_CFG_STRUCT(GPD4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SLP_S3# */ + _PAD_CFG_STRUCT(GPD5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SLP_S4# */ + _PAD_CFG_STRUCT(GPD6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), /* SLP_A# */ + _PAD_CFG_STRUCT(GPD7, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + _PAD_CFG_STRUCT(GPD8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SUSCLK */ + PAD_CFG_GPO(GPD9, 0, DEEP), /* GPIO */ + _PAD_CFG_STRUCT(GPD10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SLP_S5# */ + PAD_CFG_GPO(GPD11, 0, DEEP), /* GPIO */ + + /* ------- GPIO Community 3 ------- */ + + /* ------- GPIO Group GPP_K ------- */ + _PAD_CFG_STRUCT(GPP_K0, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_K1, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_K2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_K3, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + PAD_CFG_GPO(GPP_K4, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_K5, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_K6, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_K7, 0, DEEP), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_K8, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPO(GPP_K9, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_K10, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_K11, 0, DEEP), /* GPIO */ + _PAD_CFG_STRUCT(GPP_K12, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_K13, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_K14, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPO(GPP_K15, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_K16, 0, DEEP), /* GPIO */ + _PAD_CFG_STRUCT(GPP_K17, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + PAD_CFG_GPO(GPP_K18, 1, DEEP), /* GPIO */ + _PAD_CFG_STRUCT(GPP_K19, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SMI# */ + PAD_CFG_GPO(GPP_K20, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_K21, 0, DEEP), /* GPIO */ + _PAD_CFG_STRUCT(GPP_K22, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_K23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + + /* ------- GPIO Group GPP_H ------- */ + PAD_CFG_GPO(GPP_H0, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_H1, 0, DEEP), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + PAD_CFG_GPO(GPP_H3, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_H4, 0, DEEP), /* GPIO */ + /* GPP_H5 - RESERVED */ + PAD_CFG_GPO(GPP_H6, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_H7, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_H8, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_H9, 0, DEEP), /* GPIO */ + /* GPP_H10 - RESERVED */ + /* GPP_H11 - RESERVED */ + PAD_CFG_GPO(GPP_H12, 1, PLTRST), /* GPIO */ + /* GPP_H13 - RESERVED */ + /* GPP_H14 - RESERVED */ + _PAD_CFG_STRUCT(GPP_H15, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + /* GPP_H16 - RESERVED */ + /* GPP_H17 - RESERVED */ + _PAD_CFG_STRUCT(GPP_H18, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + PAD_CFG_GPO(GPP_H19, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_H20, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_H21, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_H22, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_H23, 0, DEEP), /* GPIO */ + + /* ------- GPIO Group GPP_E ------- */ + PAD_CFG_GPO(GPP_E0, 0, DEEP), /* GPIO */ + _PAD_CFG_STRUCT(GPP_E1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* SATAXPCIE1 */ + PAD_CFG_GPI_TRIG_OWN(GPP_E2, NONE, DEEP, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_E3, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + PAD_CFG_GPO(GPP_E4, 0, DEEP), /* GPIO */ + _PAD_CFG_STRUCT(GPP_E5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_E6, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + PAD_CFG_GPO(GPP_E7, 0, DEEP), /* GPIO */ + _PAD_CFG_STRUCT(GPP_E8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SATALED# */ + _PAD_CFG_STRUCT(GPP_E9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* USB2_OC0# */ + _PAD_CFG_STRUCT(GPP_E10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* USB2_OC1# */ + _PAD_CFG_STRUCT(GPP_E11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* USB2_OC2# */ + _PAD_CFG_STRUCT(GPP_E12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* USB2_OC3# */ + + /* ------- GPIO Group GPP_F ------- */ + PAD_CFG_GPI_TRIG_OWN(GPP_F0, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F1, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F2, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F3, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F4, NONE, DEEP, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F6, NONE, DEEP, OFF, ACPI), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F7, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F8, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F9, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SATA_SCLOCK */ + _PAD_CFG_STRUCT(GPP_F11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SATA_SLOAD */ + _PAD_CFG_STRUCT(GPP_F12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SATA_SDATAOUT1 */ + _PAD_CFG_STRUCT(GPP_F13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SATA_SDATAOUT0 */ + PAD_CFG_GPO(GPP_F14, 0, DEEP), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F15, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* USB2_OC4# */ + _PAD_CFG_STRUCT(GPP_F16, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* USB2_OC5# */ + PAD_CFG_GPO(GPP_F17, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_F18, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_F19, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_F20, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_F21, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_F22, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_F23, 0, DEEP), /* GPIO */ + + /* ------- GPIO Group SPI ------- */ + + /* ------- GPIO Community 4 ------- */ + + /* ------- GPIO Group GPP_I ------- */ + _PAD_CFG_STRUCT(GPP_I0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* DDPB_HPD0 */ + _PAD_CFG_STRUCT(GPP_I1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* DDPB_HPD1 */ + _PAD_CFG_STRUCT(GPP_I2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* DDPB_HPD2 */ + _PAD_CFG_STRUCT(GPP_I3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0), /* DDPB_HPD3 */ + _PAD_CFG_STRUCT(GPP_I4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0), /* EDP_HPD */ + _PAD_CFG_STRUCT(GPP_I5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0), /* DDPB_CTRLCLK */ + _PAD_CFG_STRUCT(GPP_I6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* DDPB_CTRLDATA */ + _PAD_CFG_STRUCT(GPP_I7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0), /* DDPC_CTRLCLK */ + _PAD_CFG_STRUCT(GPP_I8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0), /* DDPC_CTRLDATA */ + _PAD_CFG_STRUCT(GPP_I9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(20K_PD)), /* DDPD_CTRLCLK */ + _PAD_CFG_STRUCT(GPP_I10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(20K_PD)), /* DDPD_CTRLDATA */ + _PAD_CFG_STRUCT(GPP_I11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* M2_SKT2_CFG0 */ + _PAD_CFG_STRUCT(GPP_I12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* M2_SKT2_CFG1 */ + _PAD_CFG_STRUCT(GPP_I13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* M2_SKT2_CFG2 */ + _PAD_CFG_STRUCT(GPP_I14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(NATIVE)), /* M2_SKT2_CFG3 */ + + /* ------- GPIO Group GPP_J ------- */ + _PAD_CFG_STRUCT(GPP_J0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* CNV_PA_BLANKING */ + _PAD_CFG_STRUCT(GPP_J1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* n/a */ + _PAD_CFG_STRUCT(GPP_J2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* n/a */ + _PAD_CFG_STRUCT(GPP_J3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* n/a */ + PAD_CFG_GPI_TRIG_OWN(GPP_J4, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_J5, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_J6, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPO(GPP_J7, 1, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_J8, 1, DEEP), /* GPIO */ + _PAD_CFG_STRUCT(GPP_J9, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_J10, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_J11, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ +}; + +/* Early pad configuration in romstage. */ +const struct pad_config early_gpio_table[] = { + /* GPP_B0 - Toggle SMBus mux to read DIMM SPDs */ + PAD_CFG_GPO(GPP_B0, 1, DEEP), +}; + +const struct pad_config *get_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +const struct pad_config *get_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/include/variant/gpio.h b/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/include/variant/gpio.h new file mode 100644 index 0000000..018a08f --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/include/variant/gpio.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef X11SCH_F_GPIO_H +#define X11SCH_F_GPIO_H + +#include <soc/gpe.h> +#include <soc/gpio.h> +#include <intelblocks/gpio_defs.h> + +const struct pad_config *get_gpio_table(size_t *num); +const struct pad_config *get_early_gpio_table(size_t *num); + +#endif /* X11SCH_F__GPIO_H */ diff --git a/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/include/variant/variants.h b/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/include/variant/variants.h new file mode 100644 index 0000000..b7ade58 --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/include/variant/variants.h @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/cnl_memcfg_init.h> + +/* Return memory configuration structure */ +const struct cnl_mb_cfg *variant_memcfg_config(void); diff --git a/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/overridetree.cb b/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/overridetree.cb new file mode 100644 index 0000000..9f936f5 --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-l4nf/overridetree.cb @@ -0,0 +1,128 @@ +chip soc/intel/cannonlake + + device cpu_cluster 0 on + device lapic 0 on end + end + + # FSP configuration + register "SaGv" = "SaGv_Enabled" + + register "SataSalpSupport" = "1" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsEnable[2]" = "1" + register "SataPortsEnable[3]" = "1" + register "SataPortsEnable[4]" = "1" + register "SataPortsEnable[5]" = "1" + register "SataPortsEnable[6]" = "1" + register "SataPortsEnable[7]" = "1" + + register "PchHdaDspEnable" = "0" + register "PchHdaAudioLinkHda" = "1" + + register "PcieRpEnable[1]" = "1" + register "PcieRpEnable[5]" = "1" + register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[16]" = "1" + register "PcieRpEnable[20]" = "1" + register "PcieRpEnable[21]" = "1" + register "PcieRpEnable[22]" = "1" + register "PcieRpEnable[23]" = "1" + + register "PcieClkSrcUsage[0]" = "0x80" + register "PcieClkSrcUsage[1]" = "0x80" + register "PcieClkSrcUsage[2]" = "0x80" + register "PcieClkSrcUsage[3]" = "0x80" + register "PcieClkSrcUsage[4]" = "0x80" + register "PcieClkSrcUsage[5]" = "0x80" + register "PcieClkSrcUsage[6]" = "0x80" + register "PcieClkSrcUsage[7]" = "0x80" + register "PcieClkSrcUsage[8]" = "0x80" + register "PcieClkSrcUsage[9]" = "0x80" + register "PcieClkSrcUsage[10]" = "0x80" + register "PcieClkSrcUsage[11]" = "0x80" + register "PcieClkSrcUsage[12]" = "0x80" + register "PcieClkSrcUsage[13]" = "0x80" + register "PcieClkSrcUsage[14]" = "0x80" + register "PcieClkSrcUsage[15]" = "0x80" + + register "PcieClkSrcClkReq[0]" = "0" + register "PcieClkSrcClkReq[1]" = "1" + register "PcieClkSrcClkReq[2]" = "2" + register "PcieClkSrcClkReq[3]" = "3" + register "PcieClkSrcClkReq[4]" = "4" + register "PcieClkSrcClkReq[5]" = "5" + register "PcieClkSrcClkReq[6]" = "6" + register "PcieClkSrcClkReq[7]" = "7" + register "PcieClkSrcClkReq[8]" = "8" + register "PcieClkSrcClkReq[9]" = "9" + register "PcieClkSrcClkReq[10]" = "10" + register "PcieClkSrcClkReq[11]" = "11" + register "PcieClkSrcClkReq[12]" = "12" + register "PcieClkSrcClkReq[13]" = "13" + register "PcieClkSrcClkReq[14]" = "14" + register "PcieClkSrcClkReq[15]" = "15" + + register "gen1_dec" = "0x000c0ca1" # IPMI KCS + + # USB Config 2.0/3.0 + + # USB OC0 + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" + + # USB OC1 + register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" + + # USB OC2 + register "usb2_ports[3]" = "USB2_PORT_MID(OC2)" + register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" + + # USB OC3 + register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" + register "usb2_ports[6]" = "USB2_PORT_MID(OC3)" + + # USB OC4 + register "usb2_ports[7]" = "USB2_PORT_MID(OC4)" + register "usb2_ports[9]" = "USB2_PORT_MID(OC4)" + + # USB OC5 + register "usb2_ports[8]" = "USB2_PORT_MID(OC5)" + register "usb2_ports[10]" = "USB2_PORT_MID(OC5)" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC5)" + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC5)" + + # USB KCS + register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" + + # USB OC6/7 - not connected + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # HECI + register "HeciEnabled" = "1" + # SPS doesn't support all command issued by FSP... + register "DisableHeciRetry" = "1" + + # Internal GFX + register "InternalGfx" = "1" + + # Disable S0ix + register "s0ix_enable" = "0" + + device domain 0 on + device pci 1b.0 hidden end # PCIe Bridge + device pci 1b.4 on end # onboard Ethernet + device pci 1b.5 on end # onboard Ethernet + device pci 1b.6 hidden end # onboard Ethernet + device pci 1b.7 hidden end # onboard Ethernet + device pci 1c.0 on end # PCIe Bridge + device pci 1c.1 on end # Aspeed Graphics + device pci 1c.4 on end # NVMe PCIE x4 + device pci 1d.0 on end # PCIE x4 + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/44578 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c3d3aaf473ecc6106349245b5de1a6025ae0e9a Gerrit-Change-Number: 44578 Gerrit-PatchSet: 1 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-MessageType: newchange

7 hours, 34 minutes

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Change in coreboot[master]: cpu/qemu-x86/car: Move long mode entry right before c entry

by Patrick Rudolph (Code Review)

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37370 ) Change subject: cpu/qemu-x86/car: Move long mode entry right before c entry ...................................................................... cpu/qemu-x86/car: Move long mode entry right before c entry Change-Id: I45e56ed8db9a44c00cd61e962bb82f27926eb23f Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/arch/x86/bootblock_crt0.S M src/cpu/qemu-x86/cache_as_ram_bootblock.S 2 files changed, 3 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/37370/1 diff --git a/src/arch/x86/bootblock_crt0.S b/src/arch/x86/bootblock_crt0.S index 3256731..e167a12 100644 --- a/src/arch/x86/bootblock_crt0.S +++ b/src/arch/x86/bootblock_crt0.S @@ -30,12 +30,6 @@ #include <cpu/x86/16bit/reset16.inc> #include <cpu/x86/32bit/entry32.inc> - /* BIST result in eax */ - mov %eax, %ebx - /* entry64.inc preserves ebx. */ -#include <cpu/x86/64bit/entry64.inc> - mov %ebx, %eax - #if CONFIG(BOOTBLOCK_DEBUG_SPINLOOP) /* Wait for a JTAG debugger to break in and set EBX non-zero */ diff --git a/src/cpu/qemu-x86/cache_as_ram_bootblock.S b/src/cpu/qemu-x86/cache_as_ram_bootblock.S index 1fa0018..f7280bf 100644 --- a/src/cpu/qemu-x86/cache_as_ram_bootblock.S +++ b/src/cpu/qemu-x86/cache_as_ram_bootblock.S @@ -39,6 +39,9 @@ /* Align the stack and keep aligned for call to bootblock_c_entry() */ and $0xfffffff0, %esp + /* entry64.inc preserves ebx. */ +#include <cpu/x86/64bit/entry64.inc> + /* Restore the BIST result and timestamps. */ #if defined(__x86_64__) movd %mm1, %rdi -- To view, visit https://review.coreboot.org/c/coreboot/+/37370 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45e56ed8db9a44c00cd61e962bb82f27926eb23f Gerrit-Change-Number: 37370 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

9 hours, 6 minutes

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Change in coreboot[master]: soc/intel/{apl,glk}: add options to configure GPU

by Maxim Polyakov (Code Review)

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39374 ) Change subject: soc/intel/{apl,glk}: add options to configure GPU ...................................................................... soc/intel/{apl,glk}: add options to configure GPU Adds options to select the primary GPU device and configure IGD, which allows to override the appropriate FSP options in the SoC code. These changes do not affect the configuration of the boards with the Apollo Lake and Gemini Lake processors, because if these parameters are not defined in the devicetree, they will be set to the default values. Change-Id: Idcd117217cf412ee0722aff52db4b3c8ec2a226c Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/soc/intel/apollolake/chip.h M src/soc/intel/apollolake/romstage.c 2 files changed, 64 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/39374/1 diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index 40cd39b..0375cec 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -44,6 +44,46 @@ /* Common structure containing soc config data required by common code*/ struct soc_intel_common_config common_soc_config; + /* Select DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size */ + enum { + DVMT_64MB = 2, /* Default */ + DVMT_96MB, + DVMT_128MB, + DVMT_160MB, + DVMT_192MB, + DVMT_224MB, + DVMT_256MB, + DVMT_288MB, + DVMT_320MB, + DVMT_352MB, + DVMT_384MB, + DVMT_416MB, + DVMT_448MB, + DVMT_480MB, + DVMT_512MB, + } igd_dvmt_50_pre_alloc_size; + + /* Select the Aperture Size for GPU device */ + enum { + APERTURE_128MB = 1, /* Default */ + APERTURE_256MB, + APERTURE_512MB, + } igd_aperture_size; + + /* Select the GTT Size for GPU device */ + enum { + GTT_2MB = 1, + GTT_4MB, + GTT_8MB, /* Default */ + } igd_gtt_size; + + /* Select primary GPU device */ + enum { + PRIMARY_AUTO = 0, /* Default */ + PRIMARY_IGD = 2, + PRIMARY_PCI = 3, + } primary_gpu; + /* * Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has * four CLKREQ inputs, but six root ports. Root ports without an diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 05cd0db..1576802 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -264,12 +264,34 @@ } } +static void soc_gpu_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + const struct soc_intel_apollolake_config *soc_cfg = config_of_soc(); + const struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD); + + m_cfg->PrimaryVideoAdaptor = soc_cfg->primary_gpu; + if (dev && dev->enabled && (soc_cfg->primary_gpu != PRIMARY_PCI)) { + /* + * Override FSP settings for IGD only if they are set in the devicetree. + * Otherwise, the default values from UPD will be used for them + */ + if (soc_cfg->igd_dvmt_50_pre_alloc_size) + m_cfg->IgdDvmt50PreAlloc = soc_cfg->igd_dvmt_50_pre_alloc_size; + + if (soc_cfg->igd_aperture_size) + m_cfg->IgdApertureSize = soc_cfg->igd_aperture_size; + + if (soc_cfg->igd_gtt_size) + m_cfg->GttSize = soc_cfg->igd_gtt_size; + } +} + static void soc_memory_init_params(FSPM_UPD *mupd) { #if CONFIG(SOC_INTEL_GLK) /* Only for GLK */ FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; - m_cfg->PrmrrSize = get_prmrr_size(); /* @@ -307,6 +329,7 @@ check_full_retrain(mupd); fill_console_params(mupd); + soc_gpu_init_params(mupd); if (CONFIG(SOC_INTEL_GLK)) soc_memory_init_params(mupd); -- To view, visit https://review.coreboot.org/c/coreboot/+/39374 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idcd117217cf412ee0722aff52db4b3c8ec2a226c Gerrit-Change-Number: 39374 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

10 hours, 9 minutes

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Change in coreboot[master]: mb/51nb/x210/gpio: Convert configuration to macros

by Maxim Polyakov (Code Review)

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43410 ) Change subject: mb/51nb/x210/gpio: Convert configuration to macros ...................................................................... mb/51nb/x210/gpio: Convert configuration to macros Use the intelp2m utility [1,2] to convert the current pad configuration format to the format with the the PAD_CFG*() macros (*). $ ./intelp2m -n -t 1 -p snr -file src/mainboard/51nb/x210/gpio.h Unlike the raw DW0 and DW1 registers values from the inteltool dump, is more understandable and makes the code much cleaner. [*] To do this, ignore some bit fields. See ... Change-Id: I18c0c321561eee04ff927681b0a231f6d79c63e2 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/51nb/x210/gpio.h 1 file changed, 164 insertions(+), 164 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/43410/1 diff --git a/src/mainboard/51nb/x210/gpio.h b/src/mainboard/51nb/x210/gpio.h index c517b44..d6f164e 100644 --- a/src/mainboard/51nb/x210/gpio.h +++ b/src/mainboard/51nb/x210/gpio.h @@ -10,170 +10,170 @@ /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { -/* RCIN# */_PAD_CFG_STRUCT(GPP_A0, 0x44000702, 0x0), -/* LAD0 */_PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x3c00), -/* LAD1 */_PAD_CFG_STRUCT(GPP_A2, 0x44000702, 0x3c00), -/* LAD2 */_PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x3c00), -/* LAD3 */_PAD_CFG_STRUCT(GPP_A4, 0x44000702, 0x3c00), -/* LFRAME# */_PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x0), -/* SERIRQ */_PAD_CFG_STRUCT(GPP_A6, 0x44000702, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_A7, 0x44000201, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_A8, 0x44000300, 0x3000), -/* CLKOUT_LPC0 */_PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x1000), -/* CLKOUT_LPC1 */_PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x1000), -/* GPIO */_PAD_CFG_STRUCT(GPP_A11, 0x44000200, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_A12, 0x4000200, 0x0), -/* SUSWARN#/SUSPWRDNACK */_PAD_CFG_STRUCT(GPP_A13, 0x44000700, 0x0), -/* SUS_STAT# */_PAD_CFG_STRUCT(GPP_A14, 0x44000700, 0x0), -/* SUS_ACK# */_PAD_CFG_STRUCT(GPP_A15, 0x44000702, 0x3000), -/* CLKOUT_48 */_PAD_CFG_STRUCT(GPP_A16, 0x44000500, 0x0), -/* ISH_GP7 */_PAD_CFG_STRUCT(GPP_A17, 0x44000700, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_A18, 0x44000300, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_A19, 0x44000300, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_A20, 0x44000300, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_A21, 0x44000300, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_A22, 0x44000201, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_A23, 0x44000100, 0x1000), -/* n/a */_PAD_CFG_STRUCT(GPP_B0, 0x44000700, 0x0), -/* n/a */_PAD_CFG_STRUCT(GPP_B1, 0x44000700, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_B2, 0x44000300, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_B3, 0x84000102, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_B4, 0x44000201, 0x0), -/* SRCCLKREQ0# */_PAD_CFG_STRUCT(GPP_B5, 0x44000700, 0x0), -/* SRCCLKREQ1# */_PAD_CFG_STRUCT(GPP_B6, 0x44000700, 0x0), -/* SRCCLKREQ2# */_PAD_CFG_STRUCT(GPP_B7, 0x44000702, 0x0), -/* SRCCLKREQ3# */_PAD_CFG_STRUCT(GPP_B8, 0x44000702, 0x0), -/* SRCCLKREQ4# */_PAD_CFG_STRUCT(GPP_B9, 0x44000700, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_B10, 0x44000102, 0x0), -/* n/a */_PAD_CFG_STRUCT(GPP_B11, 0x44000700, 0x0), -/* SLP_S0# */_PAD_CFG_STRUCT(GPP_B12, 0x44000700, 0x0), -/* PLTRST# */_PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_B14, 0x44000201, 0x1000), -/* GPIO */_PAD_CFG_STRUCT(GPP_B15, 0x44000300, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_B16, 0x84800102, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_B17, 0x84800102, 0x3000), -/* GPIO */_PAD_CFG_STRUCT(GPP_B18, 0x84800102, 0x3000), -/* GPIO */_PAD_CFG_STRUCT(GPP_B19, 0x44000300, 0x0), -/* GSPI1_CLK */_PAD_CFG_STRUCT(GPP_B20, 0x44000700, 0x1000), -/* GSPI1_MISO */_PAD_CFG_STRUCT(GPP_B21, 0x44000700, 0x1000), -/* GSPIO_MOSI */_PAD_CFG_STRUCT(GPP_B22, 0x44000700, 0x1000), -/* GPIO */_PAD_CFG_STRUCT(GPP_B23, 0x44000201, 0x1000), -/* SMBCLK */_PAD_CFG_STRUCT(GPP_C0, 0x44000702, 0x0), -/* SMBDATA */_PAD_CFG_STRUCT(GPP_C1, 0x44000702, 0x1000), -/* GPIO */_PAD_CFG_STRUCT(GPP_C2, 0x44000201, 0x1000), -/* SML0CLK */_PAD_CFG_STRUCT(GPP_C3, 0x44000702, 0x3000), -/* SML0DATA */_PAD_CFG_STRUCT(GPP_C4, 0x44000702, 0x3000), -/* GPIO */_PAD_CFG_STRUCT(GPP_C5, 0x44800100, 0x1000), -/* RESERVED */_PAD_CFG_STRUCT(GPP_C6, 0xffffffff, 0xffffff00), -/* RESERVED */_PAD_CFG_STRUCT(GPP_C7, 0xffffffff, 0xffffff00), -/* UART0_RXD */_PAD_CFG_STRUCT(GPP_C8, 0x44000702, 0x3000), -/* UART0_TXD */_PAD_CFG_STRUCT(GPP_C9, 0x44000700, 0x0), -/* UART0_RTS# */_PAD_CFG_STRUCT(GPP_C10, 0x44000700, 0x0), -/* UART0_CTS# */_PAD_CFG_STRUCT(GPP_C11, 0x44000702, 0x0), -/* UART1_RXD */_PAD_CFG_STRUCT(GPP_C12, 0x44000702, 0x0), -/* UART1_TXD */_PAD_CFG_STRUCT(GPP_C13, 0x44000700, 0x0), -/* UART1_RTS# */_PAD_CFG_STRUCT(GPP_C14, 0x44000700, 0x0), -/* UART1_CTS# */_PAD_CFG_STRUCT(GPP_C15, 0x44000702, 0x0), -/* I2C0_SDA */_PAD_CFG_STRUCT(GPP_C16, 0x44000702, 0x3000), -/* I2C0_SCL */_PAD_CFG_STRUCT(GPP_C17, 0x44000702, 0x3000), -/* I2C1_SDA */_PAD_CFG_STRUCT(GPP_C18, 0x44000702, 0x3000), -/* I2C1_SCL */_PAD_CFG_STRUCT(GPP_C19, 0x44000702, 0x3000), -/* UART2_RXD */_PAD_CFG_STRUCT(GPP_C20, 0x44000702, 0x3000), -/* UART2_TXD */_PAD_CFG_STRUCT(GPP_C21, 0x44000700, 0x0), -/* UART2_RTS# */_PAD_CFG_STRUCT(GPP_C22, 0x44000700, 0x0), -/* UART2_CTS# */_PAD_CFG_STRUCT(GPP_C23, 0x44000702, 0x0), -/* n/a */_PAD_CFG_STRUCT(GPP_D0, 0x44000700, 0x0), -/* n/a */_PAD_CFG_STRUCT(GPP_D1, 0x44000700, 0x0), -/* n/a */_PAD_CFG_STRUCT(GPP_D2, 0x44000700, 0x0), -/* n/a */_PAD_CFG_STRUCT(GPP_D3, 0x44000700, 0x0), -/* ISH_I2C2_SDA */_PAD_CFG_STRUCT(GPP_D4, 0x44000700, 0x0), -/* I2S_SFRM */_PAD_CFG_STRUCT(GPP_D5, 0x44000702, 0x3000), -/* I2S_TXD */_PAD_CFG_STRUCT(GPP_D6, 0x44000702, 0x3000), -/* I2S_RXD */_PAD_CFG_STRUCT(GPP_D7, 0x44000702, 0x3000), -/* I2S_SCLK */_PAD_CFG_STRUCT(GPP_D8, 0x44000702, 0x3000), -/* GPIO */_PAD_CFG_STRUCT(GPP_D9, 0x44000102, 0x3000), -/* GPIO */_PAD_CFG_STRUCT(GPP_D10, 0x44000102, 0x3000), -/* GPIO */_PAD_CFG_STRUCT(GPP_D11, 0x44000102, 0x3000), -/* GPIO */_PAD_CFG_STRUCT(GPP_D12, 0x44000102, 0x3000), -/* ISH_UART0_RXD */_PAD_CFG_STRUCT(GPP_D13, 0x44000702, 0x3000), -/* ISH_UART0_TXD */_PAD_CFG_STRUCT(GPP_D14, 0x44000700, 0x3000), -/* ISH_UART0_RTS# */_PAD_CFG_STRUCT(GPP_D15, 0x44000700, 0x0), -/* ISH_UART0_CTS# */_PAD_CFG_STRUCT(GPP_D16, 0x44000702, 0x0), -/* DMIC_CLK1 */_PAD_CFG_STRUCT(GPP_D17, 0x44000700, 0x0), -/* DMIC_DATA1 */_PAD_CFG_STRUCT(GPP_D18, 0x44000700, 0x1000), -/* DMIC_CLK0 */_PAD_CFG_STRUCT(GPP_D19, 0x44000700, 0x0), -/* DMIC_DATA0 */_PAD_CFG_STRUCT(GPP_D20, 0x44000700, 0x1000), -/* n/a */_PAD_CFG_STRUCT(GPP_D21, 0x44000700, 0x0), -/* n/a */_PAD_CFG_STRUCT(GPP_D22, 0x44000700, 0x0), -/* ISH_I2C2_SCL */_PAD_CFG_STRUCT(GPP_D23, 0x44000700, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_E0, 0x44000200, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_E1, 0x44800102, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_E2, 0x44000300, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_E3, 0x44000103, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_E4, 0x44000300, 0x0), -/* SATA_DEVSLP1 */_PAD_CFG_STRUCT(GPP_E5, 0x4000700, 0x0), -/* SATA_DEVSLP2 */_PAD_CFG_STRUCT(GPP_E6, 0x4000700, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_E7, 0x44000300, 0x0), -/* SATA_LED# */_PAD_CFG_STRUCT(GPP_E8, 0x44000700, 0x0), -/* USB_OC0# */_PAD_CFG_STRUCT(GPP_E9, 0x44000702, 0x0), -/* USB_OC1# */_PAD_CFG_STRUCT(GPP_E10, 0x44000702, 0x0), -/* USB_OC2# */_PAD_CFG_STRUCT(GPP_E11, 0x44000702, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_E12, 0x44000300, 0x0), -/* n/a */_PAD_CFG_STRUCT(GPP_E13, 0x44000700, 0x0), -/* n/a */_PAD_CFG_STRUCT(GPP_E14, 0x44000700, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_E15, 0x80880102, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_E16, 0x84000102, 0x0), -/* n/a */_PAD_CFG_STRUCT(GPP_E17, 0x44000702, 0x0), -/* n/a */_PAD_CFG_STRUCT(GPP_E18, 0x44000700, 0x3000), -/* n/a */_PAD_CFG_STRUCT(GPP_E19, 0x44000700, 0x1000), -/* n/a */_PAD_CFG_STRUCT(GPP_E20, 0x44000702, 0x3000), -/* n/a */_PAD_CFG_STRUCT(GPP_E21, 0x44000702, 0x1000), -/* GPIO */_PAD_CFG_STRUCT(GPP_E22, 0x44000000, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_E23, 0x44000201, 0x1000), -/* BATLOW# */_PAD_CFG_STRUCT(GPD0, 0x4000702, 0x3000), -/* ACPRESENT */_PAD_CFG_STRUCT(GPD1, 0x4000702, 0x0), -/* LAN_WAKE# */_PAD_CFG_STRUCT(GPD2, 0x4000602, 0x3c00), -/* PWRBTN# */_PAD_CFG_STRUCT(GPD3, 0x4000702, 0x3000), -/* SLP_S3# */_PAD_CFG_STRUCT(GPD4, 0x4000700, 0x0), -/* SLP_S4# */_PAD_CFG_STRUCT(GPD5, 0x4000700, 0x0), -/* SLP_A# */_PAD_CFG_STRUCT(GPD6, 0x4000700, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPD7, 0x4000301, 0x0), -/* SUSCLK */_PAD_CFG_STRUCT(GPD8, 0x4000700, 0x0), -/* SLP_WLAN# */_PAD_CFG_STRUCT(GPD9, 0x4000700, 0x0), -/* SLP_S5# */_PAD_CFG_STRUCT(GPD10, 0x4000700, 0x0), -/* LANPHYPC */_PAD_CFG_STRUCT(GPD11, 0x4000700, 0x0), -/* SATAXPCIE3 */_PAD_CFG_STRUCT(GPP_F0, 0x44000700, 0x0), -/* SATAXPCIE4 */_PAD_CFG_STRUCT(GPP_F1, 0x44000700, 0x0), -/* SATAXPCIE5 */_PAD_CFG_STRUCT(GPP_F2, 0x44000700, 0x0), -/* SATAXPCIE6 */_PAD_CFG_STRUCT(GPP_F3, 0x44000700, 0x0), -/* SATAXPCIE7 */_PAD_CFG_STRUCT(GPP_F4, 0x44000702, 0x2003000), -/* SATA_DEVSLP3 */_PAD_CFG_STRUCT(GPP_F5, 0x44000702, 0x2003000), -/* SATA_DEVSLP4 */_PAD_CFG_STRUCT(GPP_F6, 0x44000702, 0x2003000), -/* SATA_DEVSLP5 */_PAD_CFG_STRUCT(GPP_F7, 0x44000702, 0x2003000), -/* SATA_DEVSLP6 */_PAD_CFG_STRUCT(GPP_F8, 0x44000702, 0x2003000), -/* SATA_DEVSLP7 */_PAD_CFG_STRUCT(GPP_F9, 0x44000702, 0x2003000), -/* n/a */_PAD_CFG_STRUCT(GPP_F10, 0x44000b02, 0x2003000), -/* n/a */_PAD_CFG_STRUCT(GPP_F11, 0x44000b02, 0x2003000), -/* SATA_SDATAOUT1 */_PAD_CFG_STRUCT(GPP_F12, 0x44000700, 0x0), -/* SATA_SDATAOUT2 */_PAD_CFG_STRUCT(GPP_F13, 0x44000700, 0x0), -/* n/a */_PAD_CFG_STRUCT(GPP_F14, 0x44000700, 0x0), -/* USB_OC4# */_PAD_CFG_STRUCT(GPP_F15, 0x44000700, 0x0), -/* USB_OC5# */_PAD_CFG_STRUCT(GPP_F16, 0x44000700, 0x0), -/* USB_OC6# */_PAD_CFG_STRUCT(GPP_F17, 0x44000700, 0x0), -/* USB_OC7# */_PAD_CFG_STRUCT(GPP_F18, 0x44000700, 0x0), -/* eDP_VDDEN */_PAD_CFG_STRUCT(GPP_F19, 0x44000700, 0x0), -/* eDP_BKLTEN */_PAD_CFG_STRUCT(GPP_F20, 0x44000700, 0x0), -/* eDP_BKLTCTL */_PAD_CFG_STRUCT(GPP_F21, 0x44000700, 0x0), -/* n/a */_PAD_CFG_STRUCT(GPP_F22, 0x44000700, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_F23, 0x44000102, 0x0), -/* FAN_TACH_0 */_PAD_CFG_STRUCT(GPP_G0, 0x44000700, 0x0), -/* FAN_TACH_1 */_PAD_CFG_STRUCT(GPP_G1, 0x44000700, 0x0), -/* FAN_TACH_2 */_PAD_CFG_STRUCT(GPP_G2, 0x44000700, 0x0), -/* FAN_TACH_3 */_PAD_CFG_STRUCT(GPP_G3, 0x44000700, 0x0), -/* FAN_TACH_4 */_PAD_CFG_STRUCT(GPP_G4, 0x44000700, 0x0), -/* FAN_TACH_5 */_PAD_CFG_STRUCT(GPP_G5, 0x44000702, 0x0), -/* FAN_TACH_6 */_PAD_CFG_STRUCT(GPP_G6, 0x44000700, 0x0), -/* FAN_TACH_7 */_PAD_CFG_STRUCT(GPP_G7, 0x44000700, 0x1000), +/* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* LAD0 */ PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* LAD1 */ PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* LAD2 */ PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* LAD3 */ PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPO(GPP_A7, 1, DEEP), +/* GPIO */ PAD_NC(GPP_A8, 20K_PU), +/* CLKOUT_LPC0 */ PAD_CFG_NF(GPP_A9, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* CLKOUT_LPC1 */ PAD_CFG_NF(GPP_A10, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPO(GPP_A11, 0, DEEP), +/* GPIO */ PAD_CFG_GPO(GPP_A12, 0, PWROK), +/* SUSWARN#/SUSPWRDNACK */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SUS_STAT# */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SUS_ACK# */ PAD_CFG_NF(GPP_A15, 20K_PU, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* CLKOUT_48 */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) - IGNORED */ +/* ISH_GP7 */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_NC(GPP_A18, NONE), +/* GPIO */ PAD_NC(GPP_A19, NONE), +/* GPIO */ PAD_NC(GPP_A20, NONE), +/* GPIO */ PAD_NC(GPP_A21, NONE), +/* GPIO */ PAD_CFG_GPO(GPP_A22, 1, DEEP), +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_A23, 20K_PD, DEEP, OFF, ACPI), +/* n/a */ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* n/a */ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_NC(GPP_B2, NONE), +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_B3, NONE, PLTRST, OFF, ACPI), +/* GPIO */ PAD_CFG_GPO(GPP_B4, 1, DEEP), +/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_B10, NONE, DEEP, OFF, ACPI), +/* n/a */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_TERM_GPO(GPP_B14, 1, 20K_PD, DEEP), +/* GPIO */ PAD_NC(GPP_B15, NONE), +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_B16, NONE, PLTRST, OFF, ACPI), /* (!) DW0 : PAD_RX_POL(INVERT) - IGNORED */ +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_B17, 20K_PU, PLTRST, OFF, ACPI), /* (!) DW0 : PAD_RX_POL(INVERT) - IGNORED */ +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_B18, 20K_PU, PLTRST, OFF, ACPI), /* (!) DW0 : PAD_RX_POL(INVERT) - IGNORED */ +/* GPIO */ PAD_NC(GPP_B19, NONE), +/* GSPI1_CLK */ PAD_CFG_NF(GPP_B20, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GSPI1_MISO */ PAD_CFG_NF(GPP_B21, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GSPIO_MOSI */ PAD_CFG_NF(GPP_B22, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_TERM_GPO(GPP_B23, 1, 20K_PD, DEEP), +/* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SMBDATA */ PAD_CFG_NF(GPP_C1, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_TERM_GPO(GPP_C2, 1, 20K_PD, DEEP), +/* SML0CLK */ PAD_CFG_NF(GPP_C3, 20K_PU, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SML0DATA */ PAD_CFG_NF(GPP_C4, 20K_PU, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_C5, 20K_PD, DEEP, OFF, ACPI), /* (!) DW0 : PAD_RX_POL(INVERT) - IGNORED */ +/* RESERVED - GPP_C6 */ +/* RESERVED - GPP_C7 */ +/* UART0_RXD */ PAD_CFG_NF(GPP_C8, 20K_PU, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* UART0_RTS# */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* UART0_CTS# */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* UART1_RXD */ PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* UART1_TXD */ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* UART1_RTS# */ PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* UART1_CTS# */ PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, 20K_PU, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, 20K_PU, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, 20K_PU, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, 20K_PU, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* UART2_RXD */ PAD_CFG_NF(GPP_C20, 20K_PU, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* UART2_RTS# */ PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* UART2_CTS# */ PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* n/a */ PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* n/a */ PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* n/a */ PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* n/a */ PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* ISH_I2C2_SDA */ PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2S_SFRM */ PAD_CFG_NF(GPP_D5, 20K_PU, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2S_TXD */ PAD_CFG_NF(GPP_D6, 20K_PU, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2S_RXD */ PAD_CFG_NF(GPP_D7, 20K_PU, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2S_SCLK */ PAD_CFG_NF(GPP_D8, 20K_PU, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D9, 20K_PU, DEEP, OFF, ACPI), +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D10, 20K_PU, DEEP, OFF, ACPI), +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D11, 20K_PU, DEEP, OFF, ACPI), +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D12, 20K_PU, DEEP, OFF, ACPI), +/* ISH_UART0_RXD */ PAD_CFG_NF(GPP_D13, 20K_PU, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* ISH_UART0_TXD */ PAD_CFG_NF(GPP_D14, 20K_PU, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* ISH_UART0_RTS# */ PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* ISH_UART0_CTS# */ PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* DMIC_CLK1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* DMIC_DATA1 */ PAD_CFG_NF(GPP_D18, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* n/a */ PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* n/a */ PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* ISH_I2C2_SCL */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPO(GPP_E0, 0, DEEP), +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_E1, NONE, DEEP, OFF, ACPI), /* (!) DW0 : PAD_RX_POL(INVERT) - IGNORED */ +/* GPIO */ PAD_NC(GPP_E2, NONE), +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_E3, NONE, DEEP, OFF, ACPI), /* (!) DW0 : 1 - IGNORED */ +/* GPIO */ PAD_NC(GPP_E4, NONE), +/* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, PWROK, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SATA_DEVSLP2 */ PAD_CFG_NF(GPP_E6, NONE, PWROK, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_NC(GPP_E7, NONE), +/* SATA_LED# */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* USB_OC0# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* USB_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* USB_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_NC(GPP_E12, NONE), +/* n/a */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* n/a */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPI_SCI(GPP_E15, NONE, PLTRST, LEVEL, INVERT), +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_E16, NONE, PLTRST, OFF, ACPI), +/* n/a */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* n/a */ PAD_CFG_NF(GPP_E18, 20K_PU, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* n/a */ PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* n/a */ PAD_CFG_NF(GPP_E20, 20K_PU, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* n/a */ PAD_CFG_NF(GPP_E21, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPIO_BIDIRECT(GPP_E22, 0, NONE, DEEP, OFF, ACPI), +/* GPIO */ PAD_CFG_TERM_GPO(GPP_E23, 1, 20K_PD, DEEP), +/* BATLOW# */ PAD_CFG_NF(GPD0, 20K_PU, PWROK, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, PWROK, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* LAN_WAKE# */ PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) - IGNORED */ +/* PWRBTN# */ PAD_CFG_NF(GPD3, 20K_PU, PWROK, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, PWROK, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, PWROK, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SLP_A# */ PAD_CFG_NF(GPD6, NONE, PWROK, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_NC(GPD7, NONE), /* (!) DW0 : 1 - IGNORED */ +/* SUSCLK */ PAD_CFG_NF(GPD8, NONE, PWROK, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, PWROK, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SLP_S5# */ PAD_CFG_NF(GPD10, NONE, PWROK, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* LANPHYPC */ PAD_CFG_NF(GPD11, NONE, PWROK, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SATAXPCIE3 */ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SATAXPCIE4 */ PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SATAXPCIE5 */ PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SATAXPCIE6 */ PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SATAXPCIE7 */ PAD_CFG_NF(GPP_F4, 20K_PU, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SATA_DEVSLP3 */ PAD_CFG_NF(GPP_F5, 20K_PU, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SATA_DEVSLP4 */ PAD_CFG_NF(GPP_F6, 20K_PU, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SATA_DEVSLP5 */ PAD_CFG_NF(GPP_F7, 20K_PU, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SATA_DEVSLP6 */ PAD_CFG_NF(GPP_F8, 20K_PU, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SATA_DEVSLP7 */ PAD_CFG_NF(GPP_F9, 20K_PU, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* n/a */ PAD_CFG_NF(GPP_F10, 20K_PU, DEEP, NF2), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* n/a */ PAD_CFG_NF(GPP_F11, 20K_PU, DEEP, NF2), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SATA_SDATAOUT1 */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SATA_SDATAOUT2 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* n/a */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* USB_OC4# */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* USB_OC5# */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* USB_OC6# */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* USB_OC7# */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* eDP_VDDEN */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* eDP_BKLTEN */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* eDP_BKLTCTL */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* n/a */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_F23, NONE, DEEP, OFF, ACPI), +/* FAN_TACH_0 */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* FAN_TACH_1 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* FAN_TACH_2 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* FAN_TACH_3 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* FAN_TACH_4 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* FAN_TACH_5 */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* FAN_TACH_6 */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* FAN_TACH_7 */ PAD_CFG_NF(GPP_G7, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ }; #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/43410 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I18c0c321561eee04ff927681b0a231f6d79c63e2 Gerrit-Change-Number: 43410 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

10 hours, 10 minutes

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Change in coreboot[master]: cpu/intel/car/non-evict/cache_as_ram.S: Add support for longmode

by Patrick Rudolph (Code Review)

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44673 ) Change subject: cpu/intel/car/non-evict/cache_as_ram.S: Add support for longmode ...................................................................... cpu/intel/car/non-evict/cache_as_ram.S: Add support for longmode * Use heap for linker script calculated constant to fix relocation symbols in mixed assembly code. * Work around a strange bug that causes the CPU to halt when accessing MMX registers in long mode Tested on HPZ220: * Still boots in x86_32. Change-Id: I3e72a0bebf728fb678308006ea3a3aeb92910a84 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/intel/car/non-evict/cache_as_ram.S 1 file changed, 40 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/44673/1 diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index b24f101..481cbee 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -9,6 +9,27 @@ .global bootblock_pre_c_entry +/* Trick the linker into supporting x86_64 relocations in 32bit code */ +#ifdef __x86_64__ +rom_mtrr_mask: +.quad _rom_mtrr_mask + +rom_mtrr_base: +.quad _rom_mtrr_base + +car_mtrr_mask: +.quad _car_mtrr_mask +#else +rom_mtrr_mask: +.long _rom_mtrr_mask + +rom_mtrr_base: +.long _rom_mtrr_base + +car_mtrr_mask: +.long _car_mtrr_mask +#endif + .code32 _cache_as_ram_setup: @@ -83,7 +104,6 @@ movl $MTRR_PHYS_MASK(1), %ecx wrmsr - post_code(0x23) /* Set Cache-as-RAM base address. */ movl $(MTRR_PHYS_BASE(0)), %ecx @@ -96,20 +116,20 @@ /* Set Cache-as-RAM mask. */ movl $(MTRR_PHYS_MASK(0)), %ecx rdmsr - movl $_car_mtrr_mask, %eax + mov car_mtrr_mask, %eax orl $MTRR_PHYS_MASK_VALID, %eax wrmsr /* Enable cache for our code in Flash because we do XIP here */ movl $MTRR_PHYS_BASE(1), %ecx xorl %edx, %edx - movl $_rom_mtrr_base, %eax + mov rom_mtrr_base, %eax orl $MTRR_TYPE_WRPROT, %eax wrmsr movl $MTRR_PHYS_MASK(1), %ecx rdmsr - movl $_rom_mtrr_mask, %eax + mov rom_mtrr_mask, %eax orl $MTRR_PHYS_MASK_VALID, %eax wrmsr @@ -208,17 +228,24 @@ the pushes below. */ andl $0xfffffff0, %esp - /* entry64.inc preserves ebx. */ +#ifdef __x86_64__ + /* + * BUG: On some x86 platforms acessing MMX register in long mode + * causes a crash. Retrieve them here and then switch to long mode. + */ + movd %mm2, %eax + push %eax + movd %mm1, %eax /* tsc */ + push %eax + movd %mm0, %eax + push %eax + xorl %eax, %eax + push %eax /* BIST */ + #include <cpu/x86/64bit/entry64.inc> -#ifdef __x86_64__ - - movd %mm2, %rdi - shld %rdi, 32 - movd %mm1, %rsi - or %rsi, %rdi /* tsc */ - - movd %mm0, %rsi /* BIST */ + pop %rsi /* BIST */ + pop %rdi /* tsc */ #else subl $4, %esp /* push TSC and BIST to stack */ -- To view, visit https://review.coreboot.org/c/coreboot/+/44673 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e72a0bebf728fb678308006ea3a3aeb92910a84 Gerrit-Change-Number: 44673 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

10 hours, 16 minutes

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coreboot-gerrit August 2020