August 2020 - coreboot-gerrit - mail.coreboot.org

Change in coreboot[master]: superio: nuvoton: add a driver for nct668xd

by Michael Niewöhner (Code Review)

Michael Niewöhner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34948 ) Change subject: superio: nuvoton: add a driver for nct668xd ...................................................................... superio: nuvoton: add a driver for nct668xd Change-Id: I78eca4ba2948c36a386306887f62773580f6e444 --- A src/superio/nuvoton/nct668xd/Kconfig A src/superio/nuvoton/nct668xd/Makefile.inc A src/superio/nuvoton/nct668xd/nct668Xd.h A src/superio/nuvoton/nct668xd/superio.c 4 files changed, 218 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/34948/1 diff --git a/src/superio/nuvoton/nct668xd/Kconfig b/src/superio/nuvoton/nct668xd/Kconfig new file mode 100644 index 0000000..ac31463 --- /dev/null +++ b/src/superio/nuvoton/nct668xd/Kconfig @@ -0,0 +1,24 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 Omar Pakker <omarpakker+coreboot(a)gmail.com> +## Copyright (C) 2019 Michael Niewöhner <foss(a)mniewoehner.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config SUPERIO_NUVOTON_NCT668XD + bool + select SUPERIO_NUVOTON_COMMON_PRE_RAM + +config SUPERIO_NUVOTON_NCT668XD_COM_A + bool + depends on SUPERIO_NUVOTON_NCT668XD + default n diff --git a/src/superio/nuvoton/nct668xd/Makefile.inc b/src/superio/nuvoton/nct668xd/Makefile.inc new file mode 100644 index 0000000..5ab05c6 --- /dev/null +++ b/src/superio/nuvoton/nct668xd/Makefile.inc @@ -0,0 +1,17 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 Omar Pakker <omarpakker+coreboot(a)gmail.com> +## Copyright (C) 2019 Michael Niewöhner <foss(a)mniewoehner.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT668XD) += superio.c diff --git a/src/superio/nuvoton/nct668xd/nct668Xd.h b/src/superio/nuvoton/nct668xd/nct668Xd.h new file mode 100644 index 0000000..6b74b2d --- /dev/null +++ b/src/superio/nuvoton/nct668xd/nct668Xd.h @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Omar Pakker <omarpakker+coreboot(a)gmail.com> + * Copyright (C) 2019 Michael Niewöhner <foss(a)mniewoehner.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_NUVOTON_NCT668XD_H +#define SUPERIO_NUVOTON_NCT668XD_H + +/* WARNING! + * NCT668XD is a "new generation" SuperIO, which implements parts of its + * functionality in firmware. That means one should check if the desired + * function/register is mentioned in the EC Space datasheet before trying + * to modify any registers in HW. + * Both datasheets (HW and EC Space) are available on request from Nuvoton. + * + * These are the warnings from the datasheet: + * 1. All GPIO pin functions should always be customized by firmware. BIOS / + * Driver should not touch all configuration registers here and related IO + * ports unless firmware opens them. + * 2. Under any situations, CR30h should always be controlled by EC and never + * be opened for BIOS / Drivers !! + * 3. Some GPIO pin functions were configured when related SW functions of EC + * Space were enabled. For such situations BIOS or application programs + * should not alter these setting to avoid abnormal function of underlying + * firmware. Please refer to EC Space Specification before going to change + * any configuration setting of GPIO pins. + */ + +/* Logical Device Numbers (LDN) */ +#define NCT668XD_PP 0x01 /* Parallel Port */ +#define NCT668XD_SP1 0x02 /* UART A */ +#define NCT668XD_SP2 0x03 /* UART B, IR */ +#define NCT668XD_KBC 0x05 /* Keyboard Controller */ +#define NCT668XD_CIR 0x06 /* Consumer IR */ +#define NCT668XD_GPIO01234567 0x07 /* GPIO 0-7 */ +#define NCT668XD_PORT80 0x08 /* Port 80 UART */ +#define NCT668XD_GPIO89 0x09 /* GPIO 8-9, GPIO 1-8 Alternate \ + * Func., GPIO 0-1 Enhance Group \ + */ +#define NCT668XD_ACPI 0x0A /* ACPI */ +#define NCT668XD_EC 0x0B /* EC Space */ +#define NCT668XD_DSLP_PWRFAULT 0x0D /* Deep Sleep, Power Fault */ +#define NCT668XD_FAN_ASSIGN 0x0E /* Fan Assignment */ + +/* Virtual LDNs */ +#define NCT668XD_WDT1 ((0 << 8) | NCT668XD_WDT1_WDTMEM_GPIO01) +#define NCT668XD_WDTMEM ((4 << 8) | NCT668XD_WDT1_WDTMEM_GPIO01) +#define NCT668XD_GPIO0 ((0 << 8) | NCT668XD_GPIO01234567) +#define NCT668XD_GPIO1 ((1 << 8) | NCT668XD_GPIO01234567) +#define NCT668XD_GPIO2 ((2 << 8) | NCT668XD_GPIO01234567) +#define NCT668XD_GPIO3 ((3 << 8) | NCT668XD_GPIO01234567) +#define NCT668XD_GPIO4 ((4 << 8) | NCT668XD_GPIO01234567) +#define NCT668XD_GPIO5 ((5 << 8) | NCT668XD_GPIO01234567) +#define NCT668XD_GPIO6 ((6 << 8) | NCT668XD_GPIO01234567) +#define NCT668XD_GPIO7 ((7 << 8) | NCT668XD_GPIO01234567) +#define NCT668XD_GPIO8 ((0 << 8) | NCT668XD_GPIO89) +#define NCT668XD_GPIO9 ((1 << 8) | NCT668XD_GPIO89) +#define NCT668XD_DS5 ((0 << 8) | NCT668XD_DS) +#define NCT668XD_DS3 ((1 << 8) | NCT668XD_DS) +#define NCT668XD_PCHDSW ((3 << 8) | NCT668XD_DS) +#define NCT668XD_DSWWOPT ((4 << 8) | NCT668XD_DS) +#define NCT668XD_DS3OPT ((5 << 8) | NCT668XD_DS) +#define NCT668XD_DSDSS ((6 << 8) | NCT668XD_DS) +#define NCT668XD_DSPU ((7 << 8) | NCT668XD_DS) + + +#endif /* SUPERIO_NUVOTON_NCT668XD_H */ diff --git a/src/superio/nuvoton/nct668xd/superio.c b/src/superio/nuvoton/nct668xd/superio.c new file mode 100644 index 0000000..99d448d --- /dev/null +++ b/src/superio/nuvoton/nct668xd/superio.c @@ -0,0 +1,98 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Felix Held <felix-coreboot(a)felixheld.de> + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * Copyright (C) 2015 Matt DeVillier <matt.devillier(a)gmail.com> + * Copyright (C) 2016 Omar Pakker <omarpakker+coreboot(a)gmail.com> + * Copyright (C) 2019 Michael Niewöhner <foss(a)mniewoehner.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <device/pnp.h> +#include <pc80/keyboard.h> +#include <stdlib.h> +#include <superio/conf_mode.h> + +#include "nct668Xd.h" + + +static void nct668Xd_init(struct device *dev) +{ + if (!dev->enabled) + return; + + switch (dev->path.pnp.device) { + case NCT668XD_KBC: + pc_keyboard_init(NO_AUX_DEVICE); + break; + } +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = nct668Xd_init, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + { NULL, NCT668XD_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, + 0x0ff8, }, + { NULL, NCT668XD_SP1, PNP_IO0 | PNP_IRQ0, + 0x0ff8, }, + { NULL, NCT668XD_SP2, PNP_IO0 | PNP_IRQ0, + 0x0ff8, }, + { NULL, NCT668XD_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, + 0x0fff, 0x0fff, }, + { NULL, NCT668XD_CIR, PNP_IO0 | PNP_IRQ0, + 0x0ff8, }, + { NULL, NCT668XD_PORT80}, + { NULL, NCT668XD_ACPI}, + { NULL, NCT668XD_EC, PNP_IO0 | PNP_IRQ0, + 0x0ff8, }, + { NULL, NCT668XD_DSLP_PWRFAULT}, + { NULL, NCT668XD_FAN_ASSIGN}, + { NULL, NCT668XD_WDT1}, + { NULL, NCT668XD_WDTMEM}, + { NULL, NCT668XD_GPIO0}, + { NULL, NCT668XD_GPIO1}, + { NULL, NCT668XD_GPIO2}, + { NULL, NCT668XD_GPIO3}, + { NULL, NCT668XD_GPIO4}, + { NULL, NCT668XD_GPIO5}, + { NULL, NCT668XD_GPIO6}, + { NULL, NCT668XD_GPIO7}, + { NULL, NCT668XD_GPIO8}, + { NULL, NCT668XD_GPIO9}, + { NULL, NCT668XD_DS5}, + { NULL, NCT668XD_DS3}, + { NULL, NCT668XD_PCHDSW}, + { NULL, NCT668XD_DSWWOPT}, + { NULL, NCT668XD_DS3OPT}, + { NULL, NCT668XD_DSDSS}, + { NULL, NCT668XD_DSPU}, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_nuvoton_nct668Xd_ops = { + CHIP_NAME("NUVOTON NCT668XD Super I/O") + .enable_dev = enable_dev, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/34948 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78eca4ba2948c36a386306887f62773580f6e444 Gerrit-Change-Number: 34948 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-MessageType: newchange

5 hours, 1 minute

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Change in coreboot[master]: x86/lapic: Set EXTINT on BSP only

by Felix Held (Code Review)

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42434 ) Change subject: x86/lapic: Set EXTINT on BSP only ...................................................................... x86/lapic: Set EXTINT on BSP only aac79e0b8f4777f8a912ccdfc483755b7a4da52c changed the LAPIC delivery mode for both the BSP and the APs. The change on the APs caused a regression that massively slows down the boot process. Configuring the AP's LAPIC delivery mode to fixed mode fixes this regression. Change-Id: I78490d2cbe3d9f52e10ef2471508263fd6c146ba Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/cpu/x86/lapic/lapic.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/42434/1 diff --git a/src/cpu/x86/lapic/lapic.c b/src/cpu/x86/lapic/lapic.c index 653c3b2..2e04464 100644 --- a/src/cpu/x86/lapic/lapic.c +++ b/src/cpu/x86/lapic/lapic.c @@ -31,6 +31,8 @@ (LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING); if (boot_cpu()) lvt0_val = SET_LAPIC_DELIVERY_MODE(lvt0_val, LAPIC_MODE_EXINT); + else + lvt0_val = SET_LAPIC_DELIVERY_MODE(lvt0_val, LAPIC_MODE_FIXED); lapic_write_around(LAPIC_LVT0, lvt0_val); lapic_write_around(LAPIC_LVT1, -- To view, visit https://review.coreboot.org/c/coreboot/+/42434 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78490d2cbe3d9f52e10ef2471508263fd6c146ba Gerrit-Change-Number: 42434 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

1 day, 13 hours

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Change in coreboot[master]: mb/acer/aspire_vn7_572g: Adds support for an Acer laptop Adds initial...

by Benjamin Doron (Code Review)

Benjamin Doron has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35523 ) Change subject: mb/acer/aspire_vn7_572g: Adds support for an Acer laptop Adds initial, rudimentary support for Acer Aspire VN7-572G. May not boot correctly or at all. For testing purposes only. ...................................................................... mb/acer/aspire_vn7_572g: Adds support for an Acer laptop Adds initial, rudimentary support for Acer Aspire VN7-572G. May not boot correctly or at all. For testing purposes only. Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> --- A src/mainboard/acer/Kconfig A src/mainboard/acer/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Kconfig A src/mainboard/acer/aspire_vn7_572g/Kconfig.name A src/mainboard/acer/aspire_vn7_572g/Makefile.inc A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl A src/mainboard/acer/aspire_vn7_572g/acpi_tables.c A src/mainboard/acer/aspire_vn7_572g/board_info.txt A src/mainboard/acer/aspire_vn7_572g/devicetree.cb A src/mainboard/acer/aspire_vn7_572g/dsdt.asl A src/mainboard/acer/aspire_vn7_572g/gpio.h A src/mainboard/acer/aspire_vn7_572g/hda_verb.c A src/mainboard/acer/aspire_vn7_572g/mainboard.c A src/mainboard/acer/aspire_vn7_572g/ramstage.c A src/mainboard/acer/aspire_vn7_572g/romstage.c 18 files changed, 1,282 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/1 diff --git a/src/mainboard/acer/Kconfig b/src/mainboard/acer/Kconfig new file mode 100644 index 0000000..f56a2a2 --- /dev/null +++ b/src/mainboard/acer/Kconfig @@ -0,0 +1,16 @@ +if VENDOR_ACER + +choice + prompt "Mainboard model" + +source "src/mainboard/acer/*/Kconfig.name" + +endchoice + +source "src/mainboard/acer/*/Kconfig" + +config MAINBOARD_VENDOR + string "Mainboard Vendor" + default "Acer" + +endif # VENDOR_ACER diff --git a/src/mainboard/acer/Kconfig.name b/src/mainboard/acer/Kconfig.name new file mode 100644 index 0000000..bb177f9 --- /dev/null +++ b/src/mainboard/acer/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_ACER + bool "Acer" diff --git a/src/mainboard/acer/aspire_vn7_572g/Kconfig b/src/mainboard/acer/aspire_vn7_572g/Kconfig new file mode 100644 index 0000000..4b3c127 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/Kconfig @@ -0,0 +1,68 @@ +if BOARD_ACER_VN7_572G + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SYSTEM_TYPE_LAPTOP + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SOC_INTEL_SKYLAKE + select MAINBOARD_USES_FSP2_0 + select SPD_READ_BY_WORD + select MAINBOARD_HAS_LPC_TPM + select NO_POST # This platform has no way to see POST codes so disable them by default. + +config IRQ_SLOT_COUNT + int + default 18 + +config MAINBOARD_VENDOR + string + default "Acer" + +config MAINBOARD_FAMILY + string + default "Aspire V Nitro" + +config MAINBOARD_PART_NUMBER + string + default "Aspire VN7-572G" + +config MAINBOARD_DIR + string + default "acer/aspire_vn7_572g" + +config DEVICETREE + string + default "devicetree.cb" + +config MAX_CPUS + int + default 4 + +config VGA_BIOS_ID + string + default "8086,1916" + +config DIMM_MAX + int + default 2 + +config DIMM_SPD_SIZE + int + default 512 + +config CPU_MICROCODE_CBFS_LEN + hex + default 0x18000 + +config CPU_MICROCODE_CBFS_LOC + hex + default 0xFFE115A0 + +config CBFS_SIZE + hex + default 0x5c0000 + +endif diff --git a/src/mainboard/acer/aspire_vn7_572g/Kconfig.name b/src/mainboard/acer/aspire_vn7_572g/Kconfig.name new file mode 100644 index 0000000..b881680 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ACER_VN7_572G + bool "Aspire VN7-572G" diff --git a/src/mainboard/acer/aspire_vn7_572g/Makefile.inc b/src/mainboard/acer/aspire_vn7_572g/Makefile.inc new file mode 100644 index 0000000..35f0f6c --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/Makefile.inc @@ -0,0 +1,17 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2015 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-y += ramstage.c +ramstage-y += hda_verb.c diff --git a/src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl b/src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl new file mode 100644 index 0000000..2eed489 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl @@ -0,0 +1,328 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Name (EMBA, 0xFE800000) + +Device (EC0) +{ + Name (_HID, EisaId ("PNP0C09")) /* Embedded Controller Device */ // _HID: Hardware ID + + Name (_GPE, 0x50) // _GPE: General Purpose Events + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings + IO (Decode16, 0x62, 0x62, 0, 1) // Range Minimum, Range Maximum, Alignment, Length + IO (Decode16, 0x66, 0x66, 0, 1) // Range Minimum, Range Maximum, Alignment, Length + }) + OperationRegion (ECO1, SystemIO, 0x62, One) + Field (ECO1, ByteAcc, Lock, Preserve) + { + PX62, 8 + } + + OperationRegion (ECO2, SystemIO, 0x66, One) + Field (ECO2, ByteAcc, Lock, Preserve) + { + PX66, 8 + } + + OperationRegion (ECMB, SystemMemory, EMBA, 0x0200) + OperationRegion (RAM, EmbeddedControl, Zero, 0xFF) + Field (RAM, ByteAcc, Lock, Preserve) + { + CMDB, 8, + Offset (0x06), + CMD2, 8, + CMD1, 8, + CMD0, 8, + Offset (0x0A), + , 1, /* Reserved */ + , 1, /* Reserved */ + Offset (0x10), + EQEN, 1, + , 1, /* Reserved */ + Offset (0x4E), + ISEN, 1, /* Sense? (0=Not Exist, 1=Exist) */ + Offset (0x51), + , 3, /* Reserved */ + TPEN, 1, + Offset (0x52), + WLEX, 1, /* Wireless LAN (0=Not Exist, 1=Exist) */ + BTEX, 1, /* Bluetooth? (0=Not Exist, 1=Exist) */ + EX3G, 1, /* 3G (0=Not Exist, 1=Exist) */ + , 3, /* Reserved */ + RFEX, 1, + Offset (0x57), + , 7, /* Reserved */ + AHKB, 1, + AHKE, 8, + Offset (0x5C), + Offset (0x5D), + Offset (0x70), + , 1, /* Reserved */ + KLID, 1, /* LID? */ + , 3, /* Reserved */ + KACS, 1, /* AC power? */ + Offset (0x71), + WLEN, 1, /* Wireless LAN (0=Not Enabled, 1=Enabled) */ + BTEN, 1, /* Bluetooth (0=Not Enabled, 1=Enabled) */ + , 3, /* Reserved */ + ISS3, 1, + ISS4, 1, + ISS5, 1, + Offset (0x74), + , 2, /* Reserved */ + , 1, /* Reserved */ + TPEX, 1, + Offset (0x75), + BLST, 1, + LMIB, 1, + Offset (0x76), + ECSS, 4, + EOSS, 4 + } + + Method (_REG, 2, NotSerialized) // _REG: Region Availability + { + /* Initialize AC power state */ + Store (KACS, \PWRS) + + /* Initialize LID switch state */ + Store (KLID, \LIDS) + } + + /* KEY_BRIGHTNESSUP */ + Method (_Q1C, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Notify (^^^GFX0.DD1F, 0x86) // Device-Specific + } + + /* KEY_BRIGHTNESSDOWN */ + Method (_Q1D, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Notify (^^^GFX0.DD1F, 0x87) // Device-Specific + } + + /* Battery Information Event */ + Method (_Q40, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Notify (BAT0, 0x81) // Information Change + } + + /* AC event */ + Method (_Q50, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Notify (ADP1, 0x80) // Status Change + } + + /* Lid event */ + Method (_Q52, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Notify (LID0, 0x80) // Status Change + } + + /* Battery Information Event */ + Method (_Q41, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Notify (BAT0, 0x81) // Information Change + } + + /* Battery Status Event */ + Method (_Q48, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Notify (BAT0, 0x80) // Status Change + } + + Method (ECWK, 1, NotSerialized) + { + EQEN = One + Notify (BAT0, 0x81) // Information Change + If (((Arg0 == 0x03) || (Arg0 == 0x04))) + { + Notify (SLPB, 0x02) // Device Wake + } + } + + Name (B0ST, Zero) + Field (ECMB, ByteAcc, Lock, Preserve) + { + Offset (0x08), + MB0S, 8 + } + + OperationRegion (MBB0, SystemMemory, (EMBA + 0x80), 0xFF) + Field (MBB0, ByteAcc, Lock, Preserve) + { + MBRC, 16, + MBFC, 16, + MBPE, 16, + MBAC, 16, + MBVO, 16, + , 15, + MBCM, 1, + MBCU, 16, + MBTV, 16 + } + + Method (GBIF, 3, NotSerialized) + { + If (Arg2) + { + Arg1 [One] = 0xFFFFFFFF + Arg1 [0x02] = 0xFFFFFFFF + Arg1 [0x04] = 0xFFFFFFFF + Arg1 [0x05] = Zero + Arg1 [0x06] = Zero + } + + Return (Arg1) + } + + Method (GBST, 4, NotSerialized) + { + Local0 = Zero + + If ((Arg1 & One)) + { + Local1 = MBAC /* \_SB_.PCI0.LPCB.EC0_.MBAC */ + Local2 = MBRC /* \_SB_.PCI0.LPCB.EC0_.MBRC */ + If (ACST) + { + If ((Arg1 & 0x20)) + { + Local2 = MBFC /* \_SB_.PCI0.LPCB.EC0_.MBFC */ + } + } + + Local3 = MBVO /* \_SB_.PCI0.LPCB.EC0_.MBVO */ + If ((Local1 >= 0x8000)) + { + If ((Local0 & One)) + { + Local1 = (0x00010000 - Local1) + } + Else + { + Local1 = Zero + } + } + + If (Arg2) + { + Local1 *= Local3 + Divide (Local1, 0x03E8, Local1) + } + } + Else + { + Local0 = Zero + Local1 = 0xFFFFFFFF + Local2 = 0xFFFFFFFF + Local3 = 0xFFFFFFFF + } + + Arg3 [Zero] = Local0 + Arg3 [One] = Local1 + Arg3 [0x02] = Local2 + Arg3 [0x03] = Local3 + Return (Arg3) + } + + Name (ACST, One) + Device (ADP1) + { + Name (_HID, "ACPI0003") /* Power Source Device */ // _HID: Hardware ID + Name (_PCL, Package () { \_SB }) // _PCL: Power Consumer List + Method (_PSR) // _PSR: Power Source + { + Return (\PWRS) + } + Method (_STA) // _STA: Status + { + Return (0x0F) + } + } + + Device (BAT0) + { + Name (_HID, EisaId ("PNP0C0A")) /* Control Method Battery */ // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Method (_PCL, 0, NotSerialized) // _PCL: Power Consumer List + { + Return (_SB) /* \_SB_ */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + If (B0ST) + { + Return (0x1F) + } + Else + { + Return (0x0F) + } + } + + Name (B0IP, Package (0x0D) + { + 0x00000001, /* 0x00: Power Unit: mAH */ + 0xFFFFFFFF, /* 0x01: Design Capacity */ + 0xFFFFFFFF, /* 0x02: Last Full Charge Capacity */ + 0x00000001, /* 0x03: Battery Technology: Rechargeable */ + 0xFFFFFFFF, /* 0x04: Design Voltage */ + 0x00000000, /* 0x05: Design Capacity of Warning */ + 0x00000000, /* 0x06: Design Capacity of Low */ + 0x00000001, /* 0x07: Capacity Granularity 1 */ + 0x00000001, /* 0x08: Capacity Granularity 2 */ + "", /* 0x09: Model Number */ + "100", /* 0x0a: Serial Number */ + "Lion", /* 0x0b: Battery Type */ + 0x00000000 /* 0x0c: OEM Information */ + }) + + Method (_BIF, 0, NotSerialized) // _BIF: Battery Information + { + Local6 = B0ST /* \_SB_.PCI0.LPCB.EC0_.B0ST */ + While ((Local6)) + { + Local1 = MB0S /* \_SB_.PCI0.LPCB.EC0_.MB0S */ + If ((Local1 & 0x08)) + { + Local6 = Zero + } + } + + Return (GBIF (Zero, B0IP, Local6)) + } + + Name (B0SP, Package (0x04) + { + 0x00000000, /* 0x00: Battery State */ + 0xFFFFFFFF, /* 0x01: Battery Present Rate */ + 0xFFFFFFFF, /* 0x02: Battery Remaining Capacity */ + 0xFFFFFFFF /* 0x03: Battery Present Voltage */ + }) + + Method (_BST, 0, NotSerialized) // _BST: Battery Status + { + Local0 = (DerefOf (B0IP [Zero]) ^ One) + Return (GBST (Zero, MB0S, Local0, B0SP)) + } + } +} diff --git a/src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl b/src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl new file mode 100644 index 0000000..e145a2b --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +OperationRegion (SANV, SystemMemory, 0x7CE5FD98, Zero) +Field (SANV, AnyAcc, Lock, Preserve) +{ + BRTL, 8 +} + +Scope (\_SB.PCI0) +{ + Device (GFX0) + { + Name (_ADR, 0x00020000) // _ADR: Address + + Device (DD1F) + { + Method (_ADR, 0, Serialized) // _ADR: Address + { + Return (0x1F) + } + + Method (_BCL, 0, NotSerialized) // _BCL: Brightness Control Levels + { + Return (Package (0x0C) + { + 0x50, + 0x32, + 0x0A, + 0x14, + 0x1E, + 0x28, + 0x32, + 0x3C, + 0x46, + 0x50, + 0x5A, + 0x64 + }) + } + + Method (_BCM, 1, NotSerialized) // _BCM: Brightness Control Method + { + If (((Arg0 >= Zero) && (Arg0 <= 0x64))) + { + BRTL = Arg0 + } + } + + Method (_BQC, 0, NotSerialized) // _BQC: Brightness Query Current + { + Return (BRTL) /* \BRTL */ + } + } + } +} diff --git a/src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl b/src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl new file mode 100644 index 0000000..90e75f2 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB) +{ + Device (LID0) /* Lid Device */ + { + Name (_HID, EisaId ("PNP0C0D")) + + Method (_STA) // _STA: Status + { + Return (0xF) + } + + Method (_LID) // _LID: Lid Status + { + Return (\LIDS) + } + } + + Device (PWRB) + { + Name (_HID, EisaId ("PNP0C0C")) + + Method (_STA) + { + Return (0xF) + } + + Name (_PRW, Package () { 27, 4 }) + } + + Device (SLPB) /* Sleep Button Device */ // _HID: Hardware ID + { + Name (_HID, EisaId ("PNP0C0E")) + + Method (_STA) // _STA: Status + { + Return (0xF) + } + } +} diff --git a/src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl b/src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl new file mode 100644 index 0000000..92c272e --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/acer/aspire_vn7_572g/acpi_tables.c b/src/mainboard/acer/aspire_vn7_572g/acpi_tables.c new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/acpi_tables.c diff --git a/src/mainboard/acer/aspire_vn7_572g/board_info.txt b/src/mainboard/acer/aspire_vn7_572g/board_info.txt new file mode 100644 index 0000000..f16707e --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/board_info.txt @@ -0,0 +1,8 @@ +Vendor name: Acer +Board name: Aspire VN7-572G +Category: laptop +ROM package: SOIC8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2015 diff --git a/src/mainboard/acer/aspire_vn7_572g/devicetree.cb b/src/mainboard/acer/aspire_vn7_572g/devicetree.cb new file mode 100644 index 0000000..f38b0b8 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/devicetree.cb @@ -0,0 +1,218 @@ +chip soc/intel/skylake + + # Disable deep Sx states + register "deep_s3_enable_ac" = "0" + register "deep_s3_enable_dc" = "0" + register "deep_s5_enable_ac" = "0" + register "deep_s5_enable_dc" = "0" + register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" + + register "eist_enable" = "1" + + # Set the Thermal Control Circuit (TCC) activaction value to 95C + # even though FSP integration guide says to set it to 100C for SKL-U + # (offset at 0), because when the TCC activates at 100C, the CPU + # will have already shut itself down from overheating protection. + register "tcc_offset" = "5" # TCC of 95C + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_C" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + # EC host command ranges are in 0x60-0x66 + register "gen1_dec" = "0x00000061" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # Disable DPTF + register "dptf_enable" = "0" + + # FSP Configuration + register "ProbelessTrace" = "0" + register "EnableLan" = "0" + register "EnableSata" = "1" + register "SataSalpSupport" = "1" + register "SataMode" = "0" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsEnable[2]" = "1" + register "SataPortsDevSlp[0]" = "0" + register "SataPortsDevSlp[1]" = "0" + register "SataPortsDevSlp[2]" = "0" + register "EnableAzalia" = "1" + register "DspEnable" = "1" + register "IoBufferOwnership" = "0" + register "EnableTraceHub" = "0" + register "SsicPortEnable" = "0" + register "SmbusEnable" = "1" + register "Cio2Enable" = "0" + register "ScsEmmcEnabled" = "0" + register "ScsEmmcHs400Enabled" = "0" + register "ScsSdCardEnabled" = "0" + register "PttSwitch" = "0" + register "SkipExtGfxScan" = "0" + register "Device4Enable" = "0" + register "HeciEnabled" = "1" + register "SaGv" = "0" + register "PmConfigSlpS3MinAssert" = "2" # 50ms + register "PmConfigSlpS4MinAssert" = "1" # 1s + register "PmConfigSlpSusMinAssert" = "3" # 500ms + register "PmConfigSlpAMinAssert" = "3" # 2s + register "PmTimerDisabled" = "0" + + # EC/KBC requires continuous mode + register "serirq_mode" = "SERIRQ_CONTINUOUS" + + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + # VR Settings Configuration for 4 Domains + #+----------------+-----------+-----------+-------------+----------+ + #| Domain/Setting | SA | IA | GT Unsliced | GT | + #+----------------+-----------+-----------+-------------+----------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax | 7A | 34A | 35A | 35A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #+----------------+-----------+-----------+-------------+----------+ + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(4), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(7), + .voltage_limit = 1520, + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(34), + .voltage_limit = 1520, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(35), + .voltage_limit = 1520, + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(35), + .voltage_limit = 1520, + }" + + # Enable Root Ports 1, 9 and 10 + register "PcieRpEnable[2]" = "1" + register "PcieRpLtrEnable[2]" = "1" + register "PcieRpEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + register "PcieRpEnable[9]" = "1" + register "PcieRpLtrEnable[9]" = "1" + +# register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port + register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-A Port (right) + register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-A Port (right) + register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" # Type-A Port (left) + register "usb2_ports[4]" = "USB2_PORT_FLEX(OC2)" # Bluetooth + register "usb2_ports[6]" = "USB2_PORT_FLEX(OC2)" # Webcam + register "usb2_ports[7]" = "USB2_PORT_FLEX(OC2)" # SD + + # OC0 should be for Type-C but it seems to not have been wired, according to + # the available schematics, even though it is labeled as USB_OC_TYPEC. +# register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (right) + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (right) + + # PL2 override 25W + register "tdp_pl2_override" = "25" + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + + # Lock Down + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 14.0 on end # USB xHCI + device pci 14.1 on end # USB xDCI (OTG) + device pci 14.2 on end # Thermal Subsystem + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 on end # SATA + device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.1 on end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end # LPC Interface + device pci 1f.1 off end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/acer/aspire_vn7_572g/dsdt.asl b/src/mainboard/acer/aspire_vn7_572g/dsdt.asl new file mode 100644 index 0000000..c9bcb7d --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/dsdt.asl @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2016 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 // OEM revision +) +{ + // Some generic macros + #include <soc/intel/skylake/acpi/platform.asl> + + // global NVS and variables + #include <soc/intel/skylake/acpi/globalnvs.asl> + + // CPU + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + } + + // Chipset specific sleep states + #include <soc/intel/skylake/acpi/sleepstates.asl> + + // Mainboard specific + #include "acpi/mainboard.asl" + + // Graphics display + #include "acpi/graphics.asl" +} diff --git a/src/mainboard/acer/aspire_vn7_572g/gpio.h b/src/mainboard/acer/aspire_vn7_572g/gpio.h new file mode 100644 index 0000000..4d98da1 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/gpio.h @@ -0,0 +1,201 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +#ifndef __ACPI__ + +/* Pad configuration in ramstage. */ +static const struct pad_config gpio_table[] = { +_PAD_CFG_STRUCT(GPP_A0, 0x44000703, 0x0), /* RCIN# */ +_PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x3c00), /* LAD0 */ +_PAD_CFG_STRUCT(GPP_A2, 0x44000702, 0x3c00), /* LAD1 */ +_PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x3c00), /* LAD2 */ +_PAD_CFG_STRUCT(GPP_A4, 0x44000702, 0x3c00), /* LAD3 */ +_PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x0), /* LFRAME# */ +_PAD_CFG_STRUCT(GPP_A6, 0x44000702, 0x0), /* SERIRQ */ +_PAD_CFG_STRUCT(GPP_A7, 0x44000702, 0x0), /* PIRQA# */ +_PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x0), /* CLKRUN# */ +_PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x1000), /* CLKOUT_LPC0 */ +_PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x1000), /* CLKOUT_LPC1 */ +_PAD_CFG_STRUCT(GPP_A11, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_A12, 0x44000100, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_A13, 0x44000700, 0x0), /* SUSWARN#/SUSPWRDNACK */ +_PAD_CFG_STRUCT(GPP_A14, 0x44000700, 0x0), /* SUS_STAT# */ +_PAD_CFG_STRUCT(GPP_A15, 0x44000700, 0x1000), /* SUS_ACK# */ +_PAD_CFG_STRUCT(GPP_A16, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_A17, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_A18, 0x44000102, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_A19, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_A20, 0x44000100, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_A21, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_A22, 0x44000201, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_A23, 0x44000201, 0x1000), /* GPIO */ + +_PAD_CFG_STRUCT(GPP_B0, 0x44000700, 0x0), /* CORE_VID0 */ +_PAD_CFG_STRUCT(GPP_B1, 0x44000700, 0x0), /* CORE_VID1 */ +_PAD_CFG_STRUCT(GPP_B2, 0x44000100, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B3, 0x80100102, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B4, 0x44000200, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B5, 0x44000702, 0x0), /* SRCCLKREQ0# */ +_PAD_CFG_STRUCT(GPP_B6, 0x44000702, 0x0), /* SRCCLKREQ1# */ +_PAD_CFG_STRUCT(GPP_B7, 0x44000700, 0x0), /* SRCCLKREQ2# */ +_PAD_CFG_STRUCT(GPP_B8, 0x44000702, 0x0), /* SRCCLKREQ3# */ +_PAD_CFG_STRUCT(GPP_B9, 0x44000702, 0x0), /* SRCCLKREQ4# */ +_PAD_CFG_STRUCT(GPP_B10, 0x44000702, 0x0), /* SRCCLKREQ5# */ +_PAD_CFG_STRUCT(GPP_B11, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B12, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x0), /* PLTRST# */ +_PAD_CFG_STRUCT(GPP_B14, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B15, 0x44000200, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B16, 0x44000200, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B17, 0x42880100, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B18, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B19, 0x44000100, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B20, 0x44000102, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B21, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B22, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_B23, 0x44000201, 0x1000), /* GPIO */ + +_PAD_CFG_STRUCT(GPP_C0, 0x44000702, 0x0), /* SMBCLK */ +_PAD_CFG_STRUCT(GPP_C1, 0x44000702, 0x1000), /* SMBDATA */ +_PAD_CFG_STRUCT(GPP_C2, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_C3, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_C4, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_C5, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_C6, 0x44000702, 0x0), /* SML1CLK */ +_PAD_CFG_STRUCT(GPP_C7, 0x44000702, 0x1000), /* SML1DATA */ +_PAD_CFG_STRUCT(GPP_C8, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_C9, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_C10, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_C11, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_C12, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_C13, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_C14, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_C15, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_C16, 0x44000702, 0x0), /* I2C0_SDA */ +_PAD_CFG_STRUCT(GPP_C17, 0x44000702, 0x0), /* I2C0_SCL */ +_PAD_CFG_STRUCT(GPP_C18, 0x44000702, 0x0), /* I2C1_SDA */ +_PAD_CFG_STRUCT(GPP_C19, 0x44000702, 0x0), /* I2C1_SCL */ +_PAD_CFG_STRUCT(GPP_C20, 0x44000702, 0x0), /* UART2_RXD */ +_PAD_CFG_STRUCT(GPP_C21, 0x44000700, 0x0), /* UART2_TXD */ +_PAD_CFG_STRUCT(GPP_C22, 0x44000700, 0x0), /* UART2_RTS# */ +_PAD_CFG_STRUCT(GPP_C23, 0x44000702, 0x0), /* UART2_CTS# */ + +_PAD_CFG_STRUCT(GPP_D0, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D1, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D2, 0x44000700, 0x0), /* SPI1_MISO */ +_PAD_CFG_STRUCT(GPP_D3, 0x44000700, 0x0), /* SPI1_MOSI */ +_PAD_CFG_STRUCT(GPP_D4, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D5, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D6, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D7, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D8, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D9, 0x40000102, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D10, 0x40000102, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D11, 0x40000102, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D12, 0x40000102, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D13, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D14, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D15, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D16, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D17, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D18, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_D19, 0x44000700, 0x0), /* DMIC_CLK0 */ +_PAD_CFG_STRUCT(GPP_D20, 0x44000700, 0x0), /* DMIC_DATA0 */ +_PAD_CFG_STRUCT(GPP_D21, 0x44000700, 0x0), /* SPI1_IO2 */ +_PAD_CFG_STRUCT(GPP_D22, 0x44000700, 0x0), /* SPI1_IO3 */ +_PAD_CFG_STRUCT(GPP_D23, 0x44000201, 0x1000), /* GPIO */ + +_PAD_CFG_STRUCT(GPP_E0, 0x44000700, 0x0), /* SATAXPCIE0 */ +_PAD_CFG_STRUCT(GPP_E1, 0x44000700, 0x0), /* SATAXPCIE1 */ +_PAD_CFG_STRUCT(GPP_E2, 0x44000702, 0x0), /* SATAXPCIE2 */ +_PAD_CFG_STRUCT(GPP_E3, 0x44000201, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_E4, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_E5, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_E6, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_E7, 0x40900100, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_E8, 0xffffffff, 0xffffff00),/* RESERVED */ +_PAD_CFG_STRUCT(GPP_E9, 0x44000702, 0x0), /* USB2_OC0# */ +_PAD_CFG_STRUCT(GPP_E10, 0x44000702, 0x0), /* USB2_OC1# */ +_PAD_CFG_STRUCT(GPP_E11, 0x44000702, 0x0), /* USB2_OC2# */ +_PAD_CFG_STRUCT(GPP_E12, 0x44000702, 0x0), /* USB2_OC3# */ +_PAD_CFG_STRUCT(GPP_E13, 0x44000700, 0x0), /* DDPB_HPD0 */ +_PAD_CFG_STRUCT(GPP_E14, 0x44000700, 0x0), /* DDPC_HPD1 */ +_PAD_CFG_STRUCT(GPP_E15, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_E16, 0x80880102, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_E17, 0x44000702, 0x0), /* EDP_HPD */ +_PAD_CFG_STRUCT(GPP_E18, 0x44000702, 0x0), /* DDPB_CTRLCLK */ +_PAD_CFG_STRUCT(GPP_E19, 0x44000702, 0x1000), /* DDPB_CTRLDATA */ +_PAD_CFG_STRUCT(GPP_E20, 0x44000700, 0x0), /* DDPC_CTRLCLK */ +_PAD_CFG_STRUCT(GPP_E21, 0x44000702, 0x1000), /* DDPC_CTRLDATA */ +_PAD_CFG_STRUCT(GPP_E22, 0x40100000, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_E23, 0x44000201, 0x1000), /* GPIO */ + +_PAD_CFG_STRUCT(GPD0, 0x4000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPD1, 0x4000702, 0x0), /* ACPRESENT */ +_PAD_CFG_STRUCT(GPD2, 0x4000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPD3, 0x4000702, 0x3000), /* PWRBTN# */ +_PAD_CFG_STRUCT(GPD4, 0x4000700, 0x0), /* SLP_S3# */ +_PAD_CFG_STRUCT(GPD5, 0x4000700, 0x0), /* SLP_S4# */ +_PAD_CFG_STRUCT(GPD6, 0x4000601, 0x1000), /* SLP_A# */ +_PAD_CFG_STRUCT(GPD7, 0x4000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPD8, 0x4000700, 0x0), /* SUSCLK */ +_PAD_CFG_STRUCT(GPD9, 0x4000601, 0x1000), /* SLP_WLAN# */ +_PAD_CFG_STRUCT(GPD10, 0x4000601, 0x1000), /* SLP_S5# */ +_PAD_CFG_STRUCT(GPD11, 0x4000201, 0x1000), /* GPIO */ + +_PAD_CFG_STRUCT(GPP_F0, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F1, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F2, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F3, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F4, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F5, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F6, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F7, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F8, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F9, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F10, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F11, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F12, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F13, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F14, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F15, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F16, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F17, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F18, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F19, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F20, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F21, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F22, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_F23, 0x40100100, 0x0), /* GPIO */ + +_PAD_CFG_STRUCT(GPP_G0, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_G1, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_G2, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_G3, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_G4, 0x44000200, 0x0), /* GPIO */ +_PAD_CFG_STRUCT(GPP_G5, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_G6, 0x44000201, 0x1000), /* GPIO */ +_PAD_CFG_STRUCT(GPP_G7, 0x44000201, 0x1000), /* GPIO */ +}; + +#endif + +#endif diff --git a/src/mainboard/acer/aspire_vn7_572g/hda_verb.c b/src/mainboard/acer/aspire_vn7_572g/hda_verb.c new file mode 100644 index 0000000..8cd5f97 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/hda_verb.c @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Purism SPC. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0255, /* Codec Vendor / Device ID: Realtek ALC255 */ + 0x10251037, /* Subsystem ID */ + 0x0000000c, /* Number of jacks (NID entries) */ + + 0x0017ff00, /* Function Reset */ + 0x0017ff00, /* Double Function Reset */ + 0x0017ff00, + 0x0017ff00, + + /* Bits 31:28 - Codec Address */ + /* Bits 27:20 - NID */ + /* Bits 19:8 - Verb ID */ + /* Bits 7:0 - Payload */ + + /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x10251037 */ + AZALIA_SUBVENDOR(0x0, 0x10251037), + + /* Pin Widget Verb Table */ + + /* Pin Complex (NID 0x12) */ + AZALIA_PIN_CFG(0x0, 0x12, 0x411111c0), + + /* Pin Complex (NID 0x14) */ + AZALIA_PIN_CFG(0x0, 0x14, 0x90172120), + + /* Pin Complex (NID 0x17) */ + AZALIA_PIN_CFG(0x0, 0x17, 0x40000000), + + /* Pin Complex (NID 0x18) */ + AZALIA_PIN_CFG(0x0, 0x18, 0x411111f0), + + /* Pin Complex (NID 0x19) */ + AZALIA_PIN_CFG(0x0, 0x19, 0x411111f0), + + /* Pin Complex (NID 0x1A) */ + AZALIA_PIN_CFG(0x0, 0x1A, 0x411111f0), + + /* Pin Complex (NID 0x1B) */ + AZALIA_PIN_CFG(0x0, 0x1B, 0x411111f0), + + /* Pin Complex (NID 0x1D) */ + AZALIA_PIN_CFG(0x0, 0x1D, 0x40700001), + + /* Pin Complex (NID 0x1E) */ + AZALIA_PIN_CFG(0x0, 0x1E, 0x411111f0), + + /* Pin Complex (NID 0x21) */ + AZALIA_PIN_CFG(0x0, 0x21, 0x02211030), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/acer/aspire_vn7_572g/mainboard.c b/src/mainboard/acer/aspire_vn7_572g/mainboard.c new file mode 100644 index 0000000..462b995 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/mainboard.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Purism SPC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <smbios.h> +#include <string.h> +#include <cbfs.h> + +#define MAX_SERIAL_LENGTH 0x100 + +const char *smbios_mainboard_serial_number(void) +{ + static char serial_number[MAX_SERIAL_LENGTH + 1] = {0}; + struct cbfsf file; + + if (serial_number[0] != 0) + return serial_number; + + if (cbfs_boot_locate(&file, "serial_number", NULL) == 0) { + struct region_device cbfs_region; + size_t serial_len; + + cbfs_file_data(&cbfs_region, &file); + + serial_len = region_device_sz(&cbfs_region); + if (serial_len <= MAX_SERIAL_LENGTH) { + if (rdev_readat(&cbfs_region, serial_number, 0, + serial_len) == serial_len) { + serial_number[serial_len] = 0; + return serial_number; + } + } + } + + strncpy(serial_number, CONFIG_MAINBOARD_SERIAL_NUMBER, + MAX_SERIAL_LENGTH); + + return serial_number; +} diff --git a/src/mainboard/acer/aspire_vn7_572g/ramstage.c b/src/mainboard/acer/aspire_vn7_572g/ramstage.c new file mode 100644 index 0000000..94f8071 --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/ramstage.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corporation + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/ramstage.h> +#include "gpio.h" + +void mainboard_silicon_init_params(FSP_SIL_UPD *params) +{ + /* Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/acer/aspire_vn7_572g/romstage.c b/src/mainboard/acer/aspire_vn7_572g/romstage.c new file mode 100644 index 0000000..86ef5af --- /dev/null +++ b/src/mainboard/acer/aspire_vn7_572g/romstage.c @@ -0,0 +1,84 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation + * Copyright (C) 2017 Purism SPC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <assert.h> +#include <soc/romstage.h> +#include <spd_bin.h> +#include <string.h> + +static void mainboard_fill_dq_map_data(void *dq_map_ch0, void *dq_map_ch1) +{ + /* DQ byte map */ + const u8 dq_map[2][12] = { + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, + { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, + 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; + memcpy(dq_map_ch0, dq_map[0], sizeof(dq_map[0])); + memcpy(dq_map_ch1, dq_map[1], sizeof(dq_map[1])); +} + +static void mainboard_fill_dqs_map_data(void *dqs_map_ch0, void *dqs_map_ch1) +{ + /* DQS CPU<>DRAM map */ + const u8 dqs_map[2][8] = { + { 0, 1, 3, 2, 4, 5, 6, 7 }, + { 1, 0, 4, 5, 2, 3, 6, 7 } }; + memcpy(dqs_map_ch0, dqs_map[0], sizeof(dqs_map[0])); + memcpy(dqs_map_ch1, dqs_map[1], sizeof(dqs_map[1])); +} + +static void mainboard_fill_rcomp_res_data(void *rcomp_ptr) +{ + /* Rcomp resistor */ + const u16 RcompResistor[3] = { 121, 81, 100 }; + memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor)); +} + +static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) +{ + /* Rcomp target */ + const u16 RcompTarget[5] = { 100, 40, 20, 20, 26 }; + memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); +} + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg; + struct spd_block blk = { + .addr_map = { 0x50, 0x52 }, + }; + + mem_cfg = &mupd->FspmConfig; + + get_spd_smbus(&blk); + dump_spd_info(&blk); + assert(blk.spd_array[0][0] != 0); + + mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0, + &mem_cfg->DqByteMapCh1); + mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0, + &mem_cfg->DqsMapCpu2DramCh1); + mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); + mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); + + mem_cfg->DqPinsInterleaved = TRUE; + mem_cfg->MemorySpdDataLen = blk.len; + mem_cfg->MemorySpdPtr00 = (uintptr_t) blk.spd_array[0]; + mem_cfg->MemorySpdPtr10 = (uintptr_t) blk.spd_array[1]; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/35523 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6 Gerrit-Change-Number: 35523 Gerrit-PatchSet: 1 Gerrit-Owner: Benjamin Doron Gerrit-MessageType: newchange

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Change in ...coreboot[master]: autoport: Add support for Haswell-LynxPoint platform

by Iru Cai (vimacs) (Code Review)

Hello Iru Cai, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/30890 to review the following change. Change subject: autoport: Add support for Haswell-LynxPoint platform ...................................................................... autoport: Add support for Haswell-LynxPoint platform It can now generate a buildable source for Clevo W650SZ. TODO: - Support Lynx Point LP (GPIO registers differ from non-LP) - Use PCH HD-Audio in azilia instead of the CPU/Northbridge HD-Audio Change-Id: I4f6e8c97b5122101de2f36bba8ba9f8ddd5b813a Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- M util/autoport/azalia.go A util/autoport/haswell.go A util/autoport/lynxpoint.go M util/autoport/main.go 4 files changed, 625 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/30890/1 diff --git a/util/autoport/azalia.go b/util/autoport/azalia.go index c525189..3090dd0 100644 --- a/util/autoport/azalia.go +++ b/util/autoport/azalia.go @@ -62,4 +62,9 @@ RegisterPCI(0x8086, 0x1c20, azalia{}) /* C216/ivybridge */ RegisterPCI(0x8086, 0x1e20, azalia{}) + /* Haswell */ + RegisterPCI(0x8086, 0x0c0c, azalia{}) + /* Lynx Point */ + RegisterPCI(0x8086, 0x8c20, azalia{}) + RegisterPCI(0x8086, 0x9c20, azalia{}) } diff --git a/util/autoport/haswell.go b/util/autoport/haswell.go new file mode 100644 index 0000000..d3c9d9f --- /dev/null +++ b/util/autoport/haswell.go @@ -0,0 +1,119 @@ +package main + +type haswellmc struct { + variant string +} + +func (i haswellmc) Scan(ctx Context, addr PCIDevData) { + inteltool := ctx.InfoSource.GetInteltool() + + /* FIXME:XX Move this somewhere else. */ + MainboardIncludes = append(MainboardIncludes, "drivers/intel/gma/int15.h") + MainboardEnable += (` /* FIXME: fix those values*/ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +`) + + DevTree = DevTreeNode{ + Chip: "northbridge/intel/haswell", + MissingParent: "northbridge", + Comment: "FIXME: check gfx.ndid and gfx.did", + Registers: map[string]string{ + "gpu_dp_b_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 2) & 7), + "gpu_dp_c_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 10) & 7), + "gpu_dp_d_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 18) & 7), + "gpu_panel_port_select": FormatInt32((inteltool.IGD[0xc7208] >> 30) & 3), + "gpu_panel_power_up_delay": FormatInt32((inteltool.IGD[0xc7208] >> 16) & 0x1fff), + "gpu_panel_power_backlight_on_delay": FormatInt32(inteltool.IGD[0xc7208] & 0x1fff), + "gpu_panel_power_down_delay": FormatInt32((inteltool.IGD[0xc720c] >> 16) & 0x1fff), + "gpu_panel_power_backlight_off_delay": FormatInt32(inteltool.IGD[0xc720c] & 0x1fff), + "gpu_panel_power_cycle_delay": FormatInt32(inteltool.IGD[0xc7210] & 0xff), + "gpu_cpu_backlight": FormatHex32(inteltool.IGD[0x48254]), + "gpu_pch_backlight": FormatHex32((inteltool.IGD[0xc8254] >> 16) * 0x10001), + "gpu_ddi_e_connected": FormatBool(((inteltool.IGD[0x64000] >> 4) & 1) == 0), + /* FIXME:XX hardcoded. */ + "gfx.ndid": "3", + "gfx.did": "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }", + }, + Children: []DevTreeNode{ + { + Chip: "cpu_cluster", + Dev: 0, + Children: []DevTreeNode{ + { + Chip: "cpu/intel/haswell", + Children: []DevTreeNode{ + { + Chip: "lapic", + Dev: 0, + }, + { + Chip: "lapic", + Dev: 0xacac, + Disabled: true, + }, + }, + Registers: map[string]string{ + /* FIXME:XX hardcoded. */ + "c1_acpower": "1", + "c2_acpower": "3", + "c3_acpower": "5", + "c1_battery": "1", + "c2_battery": "3", + "c3_battery": "5", + }, + }, + }, + }, + + { + Chip: "domain", + Dev: 0, + PCIController: true, + ChildPCIBus: 0, + PCISlots: []PCISlot{ + PCISlot{PCIAddr: PCIAddr{Dev: 0x0, Func: 0}, writeEmpty: true, additionalComment: "Host bridge"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1, Func: 0}, writeEmpty: true, additionalComment: "PCIe Bridge for discrete graphics"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x2, Func: 0}, writeEmpty: true, additionalComment: "Internal graphics"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x3, Func: 0}, writeEmpty: true, additionalComment: "Mini-HD audio"}, + }, + }, + }, + } + + PutPCIDev(addr, "Host bridge") + + /* FIXME:XX some configs are unsupported. */ + + KconfigBool["CPU_INTEL_HASWELL"] = true + KconfigBool["NORTHBRIDGE_INTEL_HASWELL"] = true + KconfigBool["INTEL_INT15"] = true + KconfigBool["HAVE_ACPI_TABLES"] = true + KconfigBool["HAVE_ACPI_RESUME"] = true + + KconfigInt["MAX_CPUS"] = 8 + + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "cpu/intel/common/acpi/cpu.asl", + }) + + DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{ + File: "northbridge/intel/haswell/acpi/haswell.asl", + }, DSDTInclude{ + File: "drivers/intel/gma/acpi/default_brightness_levels.asl", + }) +} + +func init() { + RegisterPCI(0x8086, 0x0c00, haswellmc{variant: "Desktop"}) + RegisterPCI(0x8086, 0x0c04, haswellmc{variant: "Mobile"}) + RegisterPCI(0x8086, 0x0a04, haswellmc{variant: "ULT"}) + RegisterPCI(0x8086, 0x0c08, haswellmc{variant: "Server"}) + for _, id := range []uint16{ + 0x0402, 0x0412, 0x0422, + 0x0406, 0x0416, 0x0426, + 0x0d16, 0x0d26, 0x0d36, + 0x0a06, 0x0a16, 0x0a26, + } { + RegisterPCI(0x8086, id, GenericVGA{GenericPCI{Comment: "VGA controller"}}) + } +} diff --git a/util/autoport/lynxpoint.go b/util/autoport/lynxpoint.go new file mode 100644 index 0000000..df20c3f --- /dev/null +++ b/util/autoport/lynxpoint.go @@ -0,0 +1,495 @@ +package main + +import ( + "fmt" + "os" +) + +type lynxpoint struct { + variant string + node *DevTreeNode +} + +func (b lynxpoint) writeGPIOSet(ctx Context, sb *os.File, + val uint32, set uint, partno int, constraint uint32) { + + max := uint(32) + if set == 3 { + max = 12 + } + + bits := [6][2]string{ + {"GPIO_MODE_NATIVE", "GPIO_MODE_GPIO"}, + {"GPIO_DIR_OUTPUT", "GPIO_DIR_INPUT"}, + {"GPIO_LEVEL_LOW", "GPIO_LEVEL_HIGH"}, + {"GPIO_RESET_PWROK", "GPIO_RESET_RSMRST"}, + {"GPIO_NO_INVERT", "GPIO_INVERT"}, + {"GPIO_NO_BLINK", "GPIO_BLINK"}, + } + + for i := uint(0); i < max; i++ { + if ((constraint>>i)&1 == 1) { + fmt.Fprintf(sb, " .gpio%d = %s,\n", + (set-1)*32+i, + bits[partno][(val>>i)&1]) + } + } +} + +func (b lynxpoint) GPIO(ctx Context, inteltool InteltoolData) { + var constraint uint32 + gpio := Create(ctx, "gpio.c") + defer gpio.Close() + + AddROMStageFile("gpio.c", "") + + Add_gpl(gpio) + gpio.WriteString("#include <southbridge/intel/common/gpio.h>\n\n") + + /* TODO: different in LP PCH */ + addresses := [3][6]int{ + {0x00, 0x04, 0x0c, 0x60, 0x2c, 0x18}, + {0x30, 0x34, 0x38, 0x64, -1, -1}, + {0x40, 0x44, 0x48, 0x68, -1, -1}, + } + + for set := 1; set <= 3; set++ { + for partno, part := range []string{"mode", "direction", "level", "reset", "invert", "blink"} { + addr := addresses[set-1][partno] + if addr < 0 { + continue + } + fmt.Fprintf(gpio, "static const struct pch_gpio_set%d pch_gpio_set%d_%s = {\n", + set, set, part) + + constraint = 0xffffffff + switch part { + case "direction": + /* Ignored on native mode */ + constraint = inteltool.GPIO[uint16(addresses[set-1][0])] + case "level": + /* Level doesn't matter for input */ + constraint = inteltool.GPIO[uint16(addresses[set-1][0])] + constraint &^= inteltool.GPIO[uint16(addresses[set-1][1])] + case "reset": + /* Only show reset */ + constraint = inteltool.GPIO[uint16(addresses[set-1][3])] + case "invert": + /* Only on input and only show inverted GPIO */ + constraint = inteltool.GPIO[uint16(addresses[set-1][0])] + constraint &= inteltool.GPIO[uint16(addresses[set-1][1])] + constraint &= inteltool.GPIO[uint16(addresses[set-1][4])] + case "blink": + /* Only on output and only show blinking GPIO */ + constraint = inteltool.GPIO[uint16(addresses[set-1][0])] + constraint &^= inteltool.GPIO[uint16(addresses[set-1][1])] + constraint &= inteltool.GPIO[uint16(addresses[set-1][5])] + } + b.writeGPIOSet(ctx, gpio, inteltool.GPIO[uint16(addr)], uint(set), partno, constraint) + gpio.WriteString("};\n\n") + } + } + + gpio.WriteString(`const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; +`) +} + +func (b lynxpoint) IsPCIeHotplug(ctx Context, port int) bool { + portDev, ok := PCIMap[PCIAddr{Bus: 0, Dev: 0x1c, Func: port}] + if !ok { + return false + } + return (portDev.ConfigDump[0xdb] & (1 << 6)) != 0 +} + +func (b lynxpoint) GetGPIOHeader() string { + return "southbridge/intel/lynxpoint/pch.h" +} + +func (b lynxpoint) EnableGPE(in int) { + b.node.Registers[fmt.Sprintf("gpi%d_routing", in)] = "2" +} + +func (b lynxpoint) EncodeGPE(in int) int { + return in + 0x10 +} + +func (b lynxpoint) DecodeGPE(in int) int { + return in - 0x10 +} + +func (b lynxpoint) NeedRouteGPIOManually() { + b.node.Comment += ", FIXME: set gpiX_routing for EC support" +} + +func (b lynxpoint) Scan(ctx Context, addr PCIDevData) { + + SouthBridge = &b + + inteltool := ctx.InfoSource.GetInteltool() + b.GPIO(ctx, inteltool) + + KconfigBool["SOUTHBRIDGE_INTEL_LYNXPOINT"] = true + if b.variant == "Lynx Point LP" { + KconfigBool["INTEL_LYNXPOINT_LP"] = true + } + KconfigBool["SERIRQ_CONTINUOUS_MODE"] = true + KconfigInt["USBDEBUG_HCD_INDEX"] = 2 + KconfigComment["USBDEBUG_HCD_INDEX"] = "FIXME: check this" + dmi := ctx.InfoSource.GetDMI() + if dmi.Vendor == "LENOVO" { + KconfigInt["DRAM_RESET_GATE_GPIO"] = 10 + } else { + KconfigInt["DRAM_RESET_GATE_GPIO"] = 60 + } + KconfigComment["DRAM_RESET_GATE_GPIO"] = "FIXME: check this" + + /* Not strictly speaking correct. These subsys/subvendor referer to PCI devices. + But most systems don't have any of those. But the config needs to be set + nevertheless. So set it to southbridge subsys/subvendor. */ + KconfigHex["MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID"] = uint32(GetLE16(addr.ConfigDump[0x2c:0x2e])) + KconfigHex["MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID"] = uint32(GetLE16(addr.ConfigDump[0x2e:0x30])) + + ich9GetFlashSize(ctx) + + DSDTDefines = append(DSDTDefines, + DSDTDefine{ + Key: "BRIGHTNESS_UP", + Value: "\\_SB.PCI0.GFX0.INCB", + }, + DSDTDefine{ + Key: "BRIGHTNESS_DOWN", + Value: "\\_SB.PCI0.GFX0.DECB", + }, + DSDTDefine{ + Key: "ACPI_VIDEO_DEVICE", + Value: "\\_SB.PCI0.GFX0", + }) + + /* SPI init */ + MainboardIncludes = append(MainboardIncludes, "southbridge/intel/lynxpoint/pch.h") + + cur := DevTreeNode{ + Chip: "southbridge/intel/lynxpoint", + Comment: "Intel Series 8 Lynx Point PCH", + + Registers: map[string]string{ + "pirqa_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x60]), + "pirqb_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x61]), + "pirqc_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x62]), + "pirqd_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x63]), + "pirqe_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x68]), + "pirqf_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x69]), + "pirqg_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x6a]), + "pirqh_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x6b]), + "sata_ahci": "1", + "gen1_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x84:0x88]), + "gen2_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x88:0x8c]), + "gen3_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x8c:0x90]), + "gen4_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x90:0x94]), + "sata_port_map": fmt.Sprintf("0x%x", PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 2}].ConfigDump[0x92]&0x3f), + }, + PCISlots: []PCISlot{ + PCISlot{PCIAddr: PCIAddr{Dev: 0x14, Func: 0}, writeEmpty: false, additionalComment: "USB 3.0 Controller"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 0}, writeEmpty: true, additionalComment: "Management Engine Interface 1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 1}, writeEmpty: true, additionalComment: "Management Engine Interface 2"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 2}, writeEmpty: true, additionalComment: "Management Engine IDE-R"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 3}, writeEmpty: true, additionalComment: "Management Engine KT"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x19, Func: 0}, writeEmpty: true, additionalComment: "Intel Gigabit Ethernet"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1a, Func: 0}, writeEmpty: true, additionalComment: "USB2 EHCI #2"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1b, Func: 0}, writeEmpty: true, additionalComment: "High Definition Audio"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 0}, writeEmpty: true, additionalComment: "PCIe Port #1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 1}, writeEmpty: true, additionalComment: "PCIe Port #2"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 2}, writeEmpty: true, additionalComment: "PCIe Port #3"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 3}, writeEmpty: true, additionalComment: "PCIe Port #4"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 4}, writeEmpty: true, additionalComment: "PCIe Port #5"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 5}, writeEmpty: true, additionalComment: "PCIe Port #6"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 6}, writeEmpty: true, additionalComment: "PCIe Port #7"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 7}, writeEmpty: true, additionalComment: "PCIe Port #8"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1d, Func: 0}, writeEmpty: true, additionalComment: "USB2 EHCI #1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1e, Func: 0}, writeEmpty: true, additionalComment: "PCI bridge"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 0}, writeEmpty: true, additionalComment: "LPC bridge"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 2}, writeEmpty: true, additionalComment: "SATA Controller 1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 3}, writeEmpty: true, additionalComment: "SMBus"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 5}, writeEmpty: true, additionalComment: "SATA Controller 2"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 6}, writeEmpty: true, additionalComment: "Thermal"}, + }, + } + + b.node = &cur + + PutPCIChip(addr, cur) + PutPCIDevParent(addr, "PCI-LPC bridge", "lpc") + + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "southbridge/intel/lynxpoint/acpi/platform.asl", + }) + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "southbridge/intel/lynxpoint/acpi/globalnvs.asl", + Comment: "global NVS and variables", + }) + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "southbridge/intel/lynxpoint/acpi/sleepstates.asl", + }) + DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{ + File: "southbridge/intel/lynxpoint/acpi/pch.asl", + }) + + sb := Create(ctx, "romstage.c") + defer sb.Close() + Add_gpl(sb) + sb.WriteString(`#include <stdint.h> +#include <cpu/intel/romstage.h> +#include <cpu/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/pei_data.h> +#include <southbridge/intel/common/gpio.h> +#include <southbridge/intel/lynxpoint/pch.h> + +static const struct rcba_config_instruction rcba_config[] = { +`) + RestoreDIRRoute(sb, "D31IR", uint16(inteltool.RCBA[0x3140])) + RestoreDIRRoute(sb, "D29IR", uint16(inteltool.RCBA[0x3144])) + RestoreDIRRoute(sb, "D28IR", uint16(inteltool.RCBA[0x3146])) + RestoreDIRRoute(sb, "D27IR", uint16(inteltool.RCBA[0x3148])) + RestoreDIRRoute(sb, "D26IR", uint16(inteltool.RCBA[0x314c])) + RestoreDIRRoute(sb, "D25IR", uint16(inteltool.RCBA[0x3150])) + RestoreDIRRoute(sb, "D22IR", uint16(inteltool.RCBA[0x315c])) + RestoreDIRRoute(sb, "D20IR", uint16(inteltool.RCBA[0x3160])) + + sb.WriteString(` + RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS), + + RCBA_END_CONFIG, +};`) + + sb.WriteString(` + +void mainboard_config_superio(void) +{ +} + +void mainboard_romstage_entry(unsigned long bist) +{ + struct pei_data pei_data = { + .pei_version = PEI_VERSION, + .mchbar = (uintptr_t)DEFAULT_MCHBAR, + .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .epbar = DEFAULT_EPBAR, + .pciexbar = DEFAULT_PCIEXBAR, + .smbusbar = SMBUS_IO_BASE, + .wdbbar = 0x4000000, + .wdbsize = 0x1000, + .hpet_address = HPET_ADDR, + .rcba = (uintptr_t)DEFAULT_RCBA, + .pmbase = DEFAULT_PMBASE, + .gpiobase = DEFAULT_GPIOBASE, + .temp_mmio_base = 0xfed08000, + .system_type = 1, /* desktop/server, FIXME: check this */ + .tseg_size = CONFIG_SMM_TSEG_SIZE, + .spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 }, /* FIXME: check this */ + .ec_present = 0, + .dimm_channel0_disabled = 0, /* FIXME: leave channel 0 enabled */ + .dimm_channel1_disabled = 0, /* FIXME: leave channel 1 enabled */ + .max_ddr3_freq = 1600, + .usb2_ports = { + /* Length, Enable, OCn#, Location */ +`) + + pdo1 := PCIMap[PCIAddr{Bus: 0, Dev: 0x1d, Func: 0}].ConfigDump[0x64] + ocmap1 := PCIMap[PCIAddr{Bus: 0, Dev: 0x1d, Func: 0}].ConfigDump[0x74:0x78] + pdo2 := PCIMap[PCIAddr{Bus: 0, Dev: 0x1a, Func: 0}].ConfigDump[0x64] + ocmap2 := PCIMap[PCIAddr{Bus: 0, Dev: 0x1a, Func: 0}].ConfigDump[0x74:0x78] + + for port := uint(0); port < 14; port++ { + var port_oc int = -1 + var port_pos string + var port_disable uint8 + + if port < 8 { + port_disable = (pdo1 >> port) & 1 + for oc := 0; oc < 4; oc++ { + if ((ocmap1[oc] & (1 << port)) != 0) { + port_oc = oc + break + } + } + } else { + port_disable = (pdo2 >> (port - 8)) & 1 + for oc := 0; oc < 4; oc++ { + if ((ocmap2[oc] & (1 << (port - 8))) != 0) { + port_oc = oc + 4 + break + } + } + } + if port_disable == 1 { + port_pos = "USB_PORT_SKIP" + } else { + port_pos = "USB_PORT_BACK_PANEL" + } + if port_oc == -1 { + fmt.Fprintf(sb, " { 0x0040, %d, USB_OC_PIN_SKIP, %s },\n", + (port_disable ^ 1), port_pos) + } else { + fmt.Fprintf(sb, " { 0x0040, %d, %d, %s },\n", + (port_disable ^ 1), port_oc, port_pos) + } + } + + sb.WriteString(` }, + .usb3_ports = { +`) + + xpdo := PCIMap[PCIAddr{Bus: 0, Dev: 0x14, Func: 0}].ConfigDump[0xe8] + u3ocm := PCIMap[PCIAddr{Bus: 0, Dev: 0x14, Func: 0}].ConfigDump[0xc8:0xd0] + + for port := uint(0); port < 6; port++ { + var port_oc int = -1 + port_disable := (xpdo >> port) & 1 + for oc := 0; oc < 8; oc++ { + if (u3ocm[oc] & (1 << port)) != 0 { + port_oc = oc + break + } + } + if port_oc == -1 { + fmt.Fprintf(sb, " { %d, USB_OC_PIN_SKIP },\n", + (port_disable ^ 1)) + } else { + fmt.Fprintf(sb, " { %d, %d },\n", + (port_disable ^ 1), port_oc) + } + } + + sb.WriteString(` }, + }; + + struct romstage_params romstage_params = { + .pei_data = &pei_data, + .gpio_map = &mainboard_gpio_map, + .rcba_config = &rcba_config[0], + .bist = bist, + }; + + romstage_common(&romstage_params); +}`) + + gnvs := Create(ctx, "acpi_tables.c") + defer gnvs.Close() + + Add_gpl(gnvs) + gnvs.WriteString(`#include <southbridge/intel/lynxpoint/nvs.h> + +/* FIXME: check this function. */ +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + // the lid is open by default. + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} +`) + +} + +func init() { + for _, id := range []uint16 { + 0x8c41, 0x8c49, 0x8c4b, 0x8c4f, + } { + RegisterPCI(0x8086, uint16(id), lynxpoint{variant: "Lynx Point Mobile"}) + } + + for _, id := range []uint16 { + 0x8c42, 0x8c44, 0x8c46, 0x8c4a, + 0x8c4c, 0x8c4e, 0x8c50, 0x8c5c, + } { + RegisterPCI(0x8086, uint16(id), lynxpoint{variant: "Lynx Point Desktop"}) + } + + for _, id := range []uint16 { + 0x8c52, 0x8c54, 0x8c56, + } { + RegisterPCI(0x8086, uint16(id), lynxpoint{variant: "Lynx Point Server"}) + } + + for _, id := range []uint16 { + 0x9c41, 0x9c43, 0x9c45, + } { + RegisterPCI(0x8086, uint16(id), lynxpoint{variant: "Lynx Point LP"}) + } + + /* PCIe bridge */ + for _, id := range []uint16{ + 0x8c10, 0x8c12, 0x8c14, 0x8c16, 0x8c18, 0x8c1a, 0x8c1c, 0x8c1e, + 0x9c10, 0x9c12, 0x9c14, 0x9c16, 0x9c18, 0x9c1a, + } { + RegisterPCI(0x8086, id, GenericPCI{}) + } + + /* SMBus controller */ + RegisterPCI(0x8086, 0x1c22, GenericPCI{MissingParent: "smbus"}) + RegisterPCI(0x8086, 0x1e22, GenericPCI{MissingParent: "smbus"}) + RegisterPCI(0x8086, 0x8c22, GenericPCI{MissingParent: "smbus"}) + RegisterPCI(0x8086, 0x9c22, GenericPCI{MissingParent: "smbus"}) + + /* SATA */ + for _, id := range []uint16{ + 0x8c00, 0x8c02, 0x8c04, 0x8c06, 0x8c08, 0x8c0e, + 0x8c01, 0x8c03, 0x8c05, 0x8c07, 0x8c09, 0x8c0f, + 0x9c03, 0x9c05, 0x9c07, 0x9c0f, + } { + RegisterPCI(0x8086, id, GenericPCI{}) + } + + /* EHCI */ + for _, id := range []uint16{ + 0x9c26, 0x8c26, 0x8c2d, + } { + RegisterPCI(0x8086, id, GenericPCI{}) + } + + /* XHCI */ + RegisterPCI(0x8086, 0x8c31, GenericPCI{}) + RegisterPCI(0x8086, 0x9c31, GenericPCI{}) + + /* ME and children */ + for _, id := range []uint16{ + 0x8c3a, 0x8c3b, + } { + RegisterPCI(0x8086, id, GenericPCI{}) + } + + /* Ethernet */ + RegisterPCI(0x8086, 0x8c33, GenericPCI{}) +} diff --git a/util/autoport/main.go b/util/autoport/main.go index 05a829b..c1920a7 100644 --- a/util/autoport/main.go +++ b/util/autoport/main.go @@ -236,6 +236,12 @@ pcidev.ConfigDump[addr]) } +func RestoreDIRRoute(f *os.File, regname string, val uint16) { + fmt.Fprintf(f, " RCBA_SET_REG_16(%s, DIR_ROUTE(PIRQ%c, PIRQ%c, PIRQ%c, PIRQ%c)),\n", + regname, 'A' + (val & 7), 'A' + ((val >> 4) & 7), + 'A' + ((val >> 8) & 7), 'A' + ((val >> 12) & 7)) +} + func RestorePCI32Simple(f *os.File, pcidev PCIDevData, addr uint16) { fmt.Fprintf(f, " pci_write_config32(PCI_DEV(%d, 0x%02x, %d), 0x%02x, 0x%02x%02x%02x%02x);\n", pcidev.Bus, pcidev.Dev, pcidev.Func, addr, -- To view, visit https://review.coreboot.org/c/coreboot/+/30890 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f6e8c97b5122101de2f36bba8ba9f8ddd5b813a Gerrit-Change-Number: 30890 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-MessageType: newchange

2 weeks, 4 days

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Change in coreboot[master]: sc7180: Add display dsi interface programming [Patch 2 of 3]

by Ravi kumar (Code Review)

Ravi kumar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39614 ) Change subject: sc7180: Add display dsi interface programming [Patch 2 of 3] ...................................................................... sc7180: Add display dsi interface programming [Patch 2 of 3] This change adds support for sc7180 dsi interface host programming and target specific hardware resource (ex: dsi-edp bridge/backlight) configuration. Change-Id: Ie64354ce8bc2a64b891fb9478fbca38d6ec4c321 Signed-off-by: Vinod Polimera <vpolimer(a)codeaurora.org> --- A src/soc/qualcomm/sc7180/display/dsi.c A src/soc/qualcomm/sc7180/display/dsi_panel_display.c A src/soc/qualcomm/sc7180/display/target_sc7180.c A src/soc/qualcomm/sc7180/include/soc/display/mipi_dsi.h A src/soc/qualcomm/sc7180/include/soc/display/panel_display.h A src/soc/qualcomm/sc7180/include/soc/display/target_sc7180.h 6 files changed, 1,710 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/39614/1 diff --git a/src/soc/qualcomm/sc7180/display/dsi.c b/src/soc/qualcomm/sc7180/display/dsi.c new file mode 100644 index 0000000..6967ff5 --- /dev/null +++ b/src/soc/qualcomm/sc7180/display/dsi.c @@ -0,0 +1,890 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 Qualcomm Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/mmio.h> +#include <endian.h> +#include <console/console.h> +#include <delay.h> +#include <string.h> +#include <stdlib.h> +#include <soc/mdss_6_2_0.h> +#include <soc/display/msm_panel.h> +#include <soc/display/mipi_dsi.h> +#include <soc/display/dsi_phy.h> + +mdss_dsi_phy_ftable phy_intf; + +void mdss_dsi_panel_shutdown(struct msm_panel_info *pinfo); + +int mdss_dsi_host_init(struct mipi_panel_info *mipi, + uint32_t dual_dsi, + uint32_t broadcast); + +int mdss_dsi_panel_initialize(struct mipi_panel_info *mipi, + uint32_t broadcast); + +int mdss_dsi_reset(struct mipi_panel_info *mipi, uint32_t dual_dsi); + +int mdss_dsi_clear_intr(struct mipi_panel_info *mipi, uint32_t dual_dsi); + +int mdss_dsi_set_intr(uint32_t ctl_base); + +void mdss_dsi_clock_config(uint32_t ctl_base); + + +static int mdss_dsi_cmd_dma_trigger_for_panel(char dual_dsi, + uint32_t ctl_base, + uint32_t sctl_base) +{ + uint32_t ReadValue; + uint32_t count = 0; + int status = 0; + uint32_t base = dual_dsi ? sctl_base : ctl_base; + + mdss_dsi_set_intr(ctl_base); + writel(0x1, ctl_base + CMD_MODE_DMA_SW_TRIGGER); + dsb(); + + if (dual_dsi) { + mdss_dsi_set_intr(sctl_base); + writel(0x1, sctl_base + CMD_MODE_DMA_SW_TRIGGER); + dsb(); + } + + ReadValue = readl(base + INT_CTRL) & 0x00000001; + + while (ReadValue != 0x00000001) { + ReadValue = readl(base + INT_CTRL) & 0x00000001; + count++; + if (count > 0xffff) { + status = FAIL; + printk(BIOS_ERR, + "Panel CMD: count :%d command mode dma test failed\n",count); + printk(BIOS_ERR, + "Panel CMD: read value = %x, addr=%x\n", + ReadValue, (base + INT_CTRL)); + return status; + } + } + + writel((readl(base + INT_CTRL) | 0x01000001), base + INT_CTRL); + return status; +} + +static int mdss_dsi_wait4_video_done(uint32_t ctl_base) +{ + unsigned long read; + unsigned long count = 0; + int status = 0; + + /* If video mode is not enabled, return here */ + if ((readl(ctl_base + CTRL) & BIT(1)) == 0) + return 0; + + read = readl(ctl_base + INT_CTRL); + + /* Enable VIDEO MODE DONE MASK and clear the interrupt */ + read = read | DSI_VIDEO_MODE_DONE_MASK | DSI_VIDEO_MODE_DONE_AK; + writel(read, ctl_base + INT_CTRL); + dsb(); + + do { + read = readl(ctl_base + INT_CTRL) & DSI_VIDEO_MODE_DONE_STAT; + count++; + + if (count > 0xffff) { + status = FAIL; + printk(BIOS_ERR,"Panel CMD: Did not receive video mode done""interrupt\n"); + return status; + } + + } while (!read); + + writel((readl(ctl_base + INT_CTRL) | 0x01000001), ctl_base + INT_CTRL); + printk(BIOS_INFO,"Panel wait_4_video_done: Received video mode done ack\n"); + + /* Skip BLLP 4ms */ + mdelay(4); + + return status; +} + +int mdss_dsi_cmds_tx(struct mipi_panel_info *mipi, + struct mipi_dsi_cmd *cmds, + int count, + char dual_dsi) +{ + + struct mipi_dsi_cmd *cm; + uint8_t pload[256]; + size_t off; + uint32_t size; + uint32_t len; + uint32_t ctl_base, sctl_base; + bool use_tpg = true; + int data = 0; + int ret = 0; + int i = 0; + int j = 0; + uint32_t *bp = NULL; + + /* if dest controller is not specified, default to DSI0 */ + if (!mipi) { + ctl_base = MIPI_DSI0_BASE; + sctl_base = MIPI_DSI1_BASE; + } else { + ctl_base = mipi->ctl_base; + sctl_base = mipi->sctl_base; + } + + /* Align pload at 8 byte boundary */ + off = (size_t) pload; + off &= 0x07; + + if (off) + off = 8 - off; + + off += (size_t) pload; + cm = cmds; + + for (i = 0; i < count; i++) { + /* Wait for VIDEO_MODE_DONE */ + ret = mdss_dsi_wait4_video_done(ctl_base); + + if (ret) + goto wait4video_error; + + /* The payload size has to be a multiple of 4 */ + size = cm->size; + size &= 0x03; + + if (size) + size = 4 - size; + + size += cm->size; + memcpy((uint8_t *)off, (cm->payload), size); + + if (use_tpg == false) { + writel(off, ctl_base + DMA_CMD_OFFSET); + writel(size, ctl_base + DMA_CMD_LENGTH); + + if (dual_dsi) { + writel(off, sctl_base + DMA_CMD_OFFSET); + writel(size, sctl_base + DMA_CMD_LENGTH); + } + + dsb(); + } + else { + data = 0; + bp = (uint32_t *)off; + len = ALIGN(size, 4); + + if (len > DMA_TPG_FIFO_LEN) { + cm++; + continue; + } + + data = BIT(16) | BIT(17); /* select CMD_DMA_PATTERN_SEL to 3 */ + data |= BIT(2); /* select CMD_DMA_FIFO_MODE to 1 */ + data |= BIT(1); + + writel(data, ctl_base + TEST_PATTERN_GEN_CTRL); + + for (j = 0; j < len; j += 4) { + writel(*bp, ctl_base + TEST_PATTERN_GEN_CMD_DMA_INIT_VAL); + wmb(); /* Ensure write happens before next command */ + bp++; + } + + if ((len % 8) != 0) + writel(0x0, ctl_base + TEST_PATTERN_GEN_CMD_DMA_INIT_VAL); + + writel(len, ctl_base + DMA_CMD_LENGTH); + wmb(); /* make sure DMA length is programmed */ + + writel(0x01, ctl_base + CMD_MODE_DMA_SW_TRIGGER); + wmb(); /* make sure DMA trigger happens */ + + + } + + ret += mdss_dsi_cmd_dma_trigger_for_panel(dual_dsi, ctl_base, sctl_base); + + /* Reset the DMA TPG FIFO */ + writel(0x1, ctl_base + TPG_DMA_FIFO_RESET); + wmb(); /* make sure FIFO reset happens */ + + writel(0x0, ctl_base + TPG_DMA_FIFO_RESET); + wmb(); /* make sure FIFO reset happens */ + + /* Disable CMD_DMA_TPG */ + writel(0x0, ctl_base + TEST_PATTERN_GEN_CTRL); + + if (cm->wait) + mdelay(cm->wait); + else + udelay(80); + + cm++; + } + +wait4video_error: + return ret; +} + +int mdss_dsi_cmds_rx(struct mipi_panel_info *mipi, + uint32_t **rp, + int rp_len, + int rdbk_len) +{ + uint32_t *lp, data; + uint32_t *dp; + int i, off; + int rlen, res; + uint32_t ctl_base; + + /* if dest controller is not specified, default to DSI0 */ + if (!mipi) + ctl_base = MIPI_DSI0_BASE; + else + ctl_base = mipi->ctl_base; + + if (rdbk_len > rp_len) + return 0; + + if (rdbk_len <= 2) + rlen = 4; /* short read */ + else + rlen = MIPI_DSI_MRPS + 6; /* 4 bytes header + 2bytes crc */ + + if (rlen > MIPI_DSI_REG_LEN) + return 0; + + res = rlen & 0x03; + + rlen += res; /* 4 byte align */ + lp = *rp; + + rlen += 3; + rlen >>= 2; + + if (rlen > 4) + rlen = 4; /* 4 x 32 bits registers only */ + + off = RDBK_DATA0; + off += ((rlen - 1) * 4); + + for (i = 0; i < rlen; i++) { + data = readl(ctl_base + off); + *lp = ntohl(data); /* to network byte order */ + lp++; + + off -= 4; + } + + if (rdbk_len > 2) { + /* First 4 bytes + paded bytes will be header next + * len bytes would be payload + */ + for (i = 0; i < rdbk_len; i++) { + dp = *rp; + dp[i] = dp[(res + i) >> 2]; + } + } + return rdbk_len; +} + +static void mdss_dsi_force_clk_lane_hs(struct mipi_panel_info *mipi, + uint32_t dual_dsi) +{ + uint32_t tmp; + + if (dual_dsi) { + tmp = readl(mipi->sctl_base + LANE_CTL); + tmp |= BIT(28); + writel(tmp, mipi->sctl_base + LANE_CTL); + } + + tmp = readl(mipi->ctl_base + LANE_CTL); + tmp |= BIT(28); + writel(tmp, mipi->ctl_base + LANE_CTL); +} + +int mdss_dsi_host_init(struct mipi_panel_info *mipi, uint32_t + dual_dsi, uint32_t broadcast) +{ + uint8_t DMA_STREAM1 = 0; // for mdp display processor path + uint8_t EMBED_MODE1 = 1; // from frame buffer + uint8_t POWER_MODE2 = 1; // from frame buffer + uint8_t PACK_TYPE1 = 0; // long packet + uint8_t VC1 = 0; + uint8_t DT1 = 0; // non embedded mode + uint8_t WC1 = 0; // for non embedded mode only + uint8_t DLNx_EN; + uint32_t timing_ctl = 0; + uint32_t ctrl_mode = BIT(8)|BIT(0); //Enable DSI and CLKlane. + uint32_t tmp = 0; + + switch (mipi->num_of_lanes) { + default: + case 1: + DLNx_EN = 1; // 1 lane + break; + + case 2: + DLNx_EN = 3; // 2 lane + break; + + case 3: + DLNx_EN = 7; // 3 lane + break; + + case 4: + DLNx_EN = 0x0F; /* 4 lanes */ + break; + } + + timing_ctl = ((mipi->t_clk_post << 8) | mipi->t_clk_pre); + + if (mipi->cmds_post_tg) { + /* + * Need to send pixel data before sending the ON commands + * so need to configure controller to VIDEO MODE. + */ + ctrl_mode |= BIT(1); + } + else + { + //Default is command mode to send cmds. + ctrl_mode |= BIT(2); + } + + if (dual_dsi) { + writel(0x0001, mipi->sctl_base + SOFT_RESET); + writel(0x0000, mipi->sctl_base + SOFT_RESET); + + /* Turn on all DSI Clks */ + writel((0 << 16) | 0x3f, mipi->sctl_base + CLK_CTRL); + writel(DMA_STREAM1 << 8 | 0x04, mipi->sctl_base + TRIG_CTRL); + + writel(0 << 30 | DLNx_EN << 4 | ctrl_mode, mipi->sctl_base + CTRL); + + writel(broadcast << 31 | EMBED_MODE1 << 28 | POWER_MODE2 << 26 + | PACK_TYPE1 << 24 | VC1 << 22 | DT1 << 16 | WC1, + mipi->sctl_base + COMMAND_MODE_DMA_CTRL); + + writel(timing_ctl, mipi->sctl_base + TIMING_CTL); + + if ((mipi->mode == DSI_CMD_MODE) && + (readl(mipi->sctl_base) >= DSI_HW_REV_241)) { + tmp = readl(mipi->sctl_base + COMMAND_MODE_MDP_CTRL2); + tmp |= BIT(16); /* enable burst mode */ + writel(tmp, mipi->sctl_base + COMMAND_MODE_MDP_CTRL2); + } + + writel(((mipi->rx_eot_ignore & 0x1) << 4) | + (mipi->tx_eot_append & 0x1), + mipi->sctl_base + EOT_PACKET_CTRL); + } + + /* Turn on all DSI Clks */ + writel((0 << 16) | 0x3f, mipi->ctl_base + CLK_CTRL); + writel(DMA_STREAM1 << 8 | 0x04, mipi->ctl_base + TRIG_CTRL); + + writel(0 << 30 | DLNx_EN << 4 | ctrl_mode, mipi->ctl_base + CTRL); + writel(broadcast << 31 | EMBED_MODE1 << 28 | POWER_MODE2 << 26 + | PACK_TYPE1 << 24 | VC1 << 22 | DT1 << 16 | WC1, + mipi->ctl_base + COMMAND_MODE_DMA_CTRL); + + writel(timing_ctl, mipi->ctl_base + TIMING_CTL); + + if ((mipi->mode == DSI_CMD_MODE) && + (readl(mipi->ctl_base) >= DSI_HW_REV_241)) { + tmp = readl(mipi->ctl_base + COMMAND_MODE_MDP_CTRL2); + tmp |= BIT(16); /* enable burst mode */ + writel(tmp, mipi->ctl_base + COMMAND_MODE_MDP_CTRL2); + } + + writel(((mipi->rx_eot_ignore & 0x1) << 4) | (mipi->tx_eot_append & 0x1), + mipi->ctl_base + EOT_PACKET_CTRL); + + return 0; +} + +int mdss_dsi_clear_intr(struct mipi_panel_info *mipi, uint32_t dual_dsi) +{ + uint32_t uIntrStatusReg = readl(mipi->ctl_base + INT_CTRL); + + /* Get CMD mode DMA Done and map to generic HAL interface. */ + uIntrStatusReg = HWIO_OUT_FLD(uIntrStatusReg, INT_CTRL, DSI_CMD_MODE_DMA_DONE_AK, 1); + + /* Get CMD mode MDP Done and map to generic HAL interface. */ + uIntrStatusReg = HWIO_OUT_FLD(uIntrStatusReg, INT_CTRL, DSI_CMD_MODE_MDP_DONE_AK, 1); + + /* Get Video mode Done and map to generic HAL interface. */ + uIntrStatusReg = HWIO_OUT_FLD(uIntrStatusReg, INT_CTRL, DSI_VIDEO_MODE_DONE_AK, 1); + + /* Get the BTA done and map to generic HAL interface. clear the interrupt status bit */ + uIntrStatusReg = HWIO_OUT_FLD(uIntrStatusReg, INT_CTRL, DSI_BTA_DONE_AK, 1); + + uIntrStatusReg = HWIO_OUT_FLD(uIntrStatusReg, INT_CTRL, DSI_ERROR_AK, 1); + + writel(uIntrStatusReg, mipi->ctl_base + INT_CTRL); + writel(0x13FF3BFF, mipi->ctl_base + ERR_INT_MASK0); + + if (dual_dsi) { + writel(uIntrStatusReg, mipi->sctl_base + INT_CTRL); + writel(0x13FF3BFF, mipi->sctl_base + ERR_INT_MASK0); + } + + return 0; +} + +int mdss_dsi_set_intr(uint32_t ctl_base) +{ + uint32_t uRegVal = 0; + + /* Map CMD mode DMA Done to HW interrupts. */ + uRegVal = HWIO_OUT_FLD(uRegVal, INT_CTRL, DSI_CMD_MODE_DMA_DONE_MASK, 1); + + /* Map CMD mode MDP Done to HW interrupts. */ + uRegVal = HWIO_OUT_FLD(uRegVal, INT_CTRL, DSI_CMD_MODE_MDP_DONE_MASK, 1); + + /* Map Video mode Done to HW interrupts. */ + uRegVal = HWIO_OUT_FLD(uRegVal, INT_CTRL, DSI_VIDEO_MODE_DONE_MASK, 1); + + /* If any Error interrupt has been enabled? */ + uRegVal = HWIO_OUT_FLD(uRegVal, INT_CTRL, DSI_ERROR_MASK, 1); + + /* If need to enable DSI_BTA_DONE */ + uRegVal = HWIO_OUT_FLD(uRegVal, INT_CTRL, DSI_BTA_DONE_MASK, 1); + + writel(uRegVal, ctl_base + INT_CTRL); + + return 0; +} +int mdss_dsi_reset(struct mipi_panel_info *mipi, uint32_t dual_dsi) +{ + /* Disable DSI Controller, DSI lane states, + * DSI command-mode and DSI video-mode engines + */ + writel(0x0, mipi->ctl_base + CTRL); + + // DSI soft reset + writel(0x0001, mipi->ctl_base + SOFT_RESET); + writel(0x0000, mipi->ctl_base + SOFT_RESET); + + // set hs timer count speed + writel(0x0004EA60, mipi->ctl_base + HS_TIMER_CTRL); + + // dma fifo reset + writel(0x0001, mipi->ctl_base + TPG_DMA_FIFO_RESET); + writel(0x0000, mipi->ctl_base + TPG_DMA_FIFO_RESET); + + if (dual_dsi) { + /* Disable DSI Controller, DSI lane states, + * DSI command-mode and DSI video-mode engines + */ + writel(0x0, mipi->sctl_base + CTRL); + + // DSI soft reset + writel(0x0001, mipi->sctl_base + SOFT_RESET); + writel(0x0000, mipi->sctl_base + SOFT_RESET); + + // set hs timer count speed + writel(0x0004EA60, mipi->sctl_base + HS_TIMER_CTRL); + + // dma fifo reset + writel(0x0001, mipi->sctl_base + TPG_DMA_FIFO_RESET); + writel(0x0000, mipi->sctl_base + TPG_DMA_FIFO_RESET); + } + + return NO_ERROR; +} + +void mdss_dsi_panel_shutdown(struct msm_panel_info *pinfo) +{ + unsigned long read_val = 0; + uint32_t ctl_base = pinfo->mipi.ctl_base; + uint32_t sctl_base = pinfo->mipi.sctl_base; + + if (pinfo->mipi.panel_off_cmds) { + /* + * Once MDP TG is disabled, reset of DSI controller is + * needed before we send panel OFF commands. + */ + if (pinfo->type == MIPI_VIDEO_PANEL) { + read_val = readl(ctl_base + CTRL); + + writel((read_val & ~BIT(0)), ctl_base + CTRL); + writel(0x0001, ctl_base + SOFT_RESET); + dsb(); + + writel(0x0000, ctl_base + SOFT_RESET); + dsb(); + + /* Enable cmd mode only */ + writel(((read_val & ~BIT(1)) | BIT(2)),ctl_base + CTRL); + } + + if (pinfo->mipi.broadcast) { + if (pinfo->type == MIPI_VIDEO_PANEL) { + read_val = readl(sctl_base + CTRL); + writel((read_val & ~BIT(0)),sctl_base + CTRL); + + writel(0x0001, sctl_base + SOFT_RESET); + dsb(); + + writel(0x0000, sctl_base + SOFT_RESET); + dsb(); + + writel(((read_val & ~BIT(1)) | BIT(2)), + sctl_base + CTRL); + } + } + mdss_dsi_cmds_tx(&pinfo->mipi, pinfo->mipi.panel_off_cmds, + pinfo->mipi.num_of_panel_off_cmds, + pinfo->mipi.broadcast); + } +} + +int mdss_dsi_panel_initialize(struct mipi_panel_info *mipi, + uint32_t broadcast) +{ + int status = 0; + uint32_t ctrl_mode = 0; + + if (!mipi->panel_on_cmds) + goto end; + + ctrl_mode = readl(mipi->ctl_base + CTRL); + + /* Enable command mode before sending the commands. */ + writel(ctrl_mode | 0x04, mipi->ctl_base + CTRL); + + if (broadcast) + writel(ctrl_mode | 0x04, mipi->sctl_base + CTRL); + + mdelay(500); + + status = mdss_dsi_cmds_tx(mipi, + mipi->panel_on_cmds, + mipi->num_of_panel_on_cmds, + broadcast); + + writel(ctrl_mode, mipi->ctl_base + CTRL); + + if (broadcast) + writel(ctrl_mode, mipi->sctl_base + CTRL); + +end: + return status; +} + + + +int mdss_dsi_video_mode_config(struct msm_panel_info *pinfo, + uint16_t disp_width, + uint16_t disp_height, + uint16_t img_width, + uint16_t img_height, + uint16_t hsync_porch0_fp, + uint16_t hsync_porch0_bp, + uint16_t vsync_porch0_fp, + uint16_t vsync_porch0_bp, + uint16_t hsync_width, + uint16_t vsync_width, + uint16_t dst_format, + uint16_t traffic_mode, + uint8_t lane_en, + uint8_t pulse_mode_hsa_he, + uint32_t low_pwr_stop_mode, + uint8_t eof_bllp_pwr, + uint8_t interleav, + uint32_t ctl_base) +{ + int status = 0; + int last_line_interleave_en = 0; + struct dsc_desc *dsc = NULL; + + if (pinfo->compression_mode == COMPRESSION_DSC) + dsc = &pinfo->dsc; + + /*Check if EOF_BLLP_PWR_MODE bit is set*/ + if (eof_bllp_pwr & 0x8) + last_line_interleave_en = 1; + + mdss_dsi_clock_config(ctl_base); + + writel(((disp_width + hsync_porch0_bp) << 16) | hsync_porch0_bp, + ctl_base + VIDEO_MODE_ACTIVE_H); + + writel(((disp_height + vsync_porch0_bp) << 16) | (vsync_porch0_bp), + ctl_base + VIDEO_MODE_ACTIVE_V); + + if (mdp_get_revision() >= MDSS_MDP_HW_REV_620) { + writel(((disp_height + vsync_porch0_fp + + vsync_porch0_bp - 1) << 16) | + (disp_width + hsync_porch0_fp + + hsync_porch0_bp - 1), + + ctl_base + VIDEO_MODE_TOTAL); + } + else { + writel(((disp_height + vsync_porch0_fp + + vsync_porch0_bp) << 16) | + (disp_width + hsync_porch0_fp + + hsync_porch0_bp), + ctl_base + VIDEO_MODE_TOTAL); + } + + writel((hsync_width << 16) | 0, ctl_base + VIDEO_MODE_HSYNC); + writel(0 << 16 | 0, ctl_base + VIDEO_MODE_VSYNC); + writel(vsync_width << 16 | 0, ctl_base + VIDEO_MODE_VSYNC_VPOS); + + writel(low_pwr_stop_mode << 15 | eof_bllp_pwr << 12 | traffic_mode << 8 | dst_format << 4 | 0x0, + ctl_base + VIDEO_MODE_CTRL); + + writel(0x0004EA60, ctl_base + HS_TIMER_CTRL); + + writel(interleav << 30 | 0 << 24 | 0 << 20 | lane_en << 4 + | 0x103, ctl_base + CTRL); + + if (dsc) { + if (dsc->dsi_dsc_config) + dsc->dsi_dsc_config(pinfo->mipi.ctl_base, + DSI_VIDEO_MODE, dsc); + } + + return status; +} + +int mdss_dsi_config(struct msm_fb_panel_data *panel) +{ + int ret = NO_ERROR; + struct msm_panel_info *pinfo; + struct mipi_panel_info *mipi; + struct dsc_desc *dsc = NULL; + struct mipi_dsi_cmd cmd; + + if (!panel) + return ERROR; + + pinfo = &(panel->panel_info); + mipi = &(pinfo->mipi); + + + if (pinfo->compression_mode == COMPRESSION_DSC) { + dsc = &pinfo->dsc; + if (dsc) { + if (dsc->dsc2buf) + dsc->dsc2buf(pinfo); + } + } + + printk(BIOS_INFO, "ctl_base=0x%08x, phy_base=0x%08x\n", mipi->ctl_base,mipi->phy_base); + + mdss_dsi_reset(mipi, mipi->dual_dsi); + + if (mdss_dsi_phy_intf_setup(DSI_PLL_TYPE_10NM, &phy_intf) != NO_ERROR) { + printk(BIOS_ERR, "mdss_dsi_phy_intf_setup returned error\n"); + return ERROR; + } + + if (phy_intf.dsi_phy_init != NULL) + phy_intf.dsi_phy_init(pinfo); + else { + printk(BIOS_ERR, "dsi_phy_init is NULL\n"); + return ERROR; + } + + ret = mdss_dsi_host_init(mipi, + mipi->dual_dsi, + mipi->broadcast); + if (ret) { + printk(BIOS_ERR, "dsi host init error\n"); + goto error; + } + + if (panel->pre_init_func) { + ret = panel->pre_init_func(); + if (ret) { + printk(BIOS_ERR, "pre_init_func error\n"); + goto error; + } + } + + if (mipi->force_clk_lane_hs) + mdss_dsi_force_clk_lane_hs(mipi, mipi->dual_dsi); + + if (!mipi->cmds_post_tg) { + ret = mdss_dsi_panel_initialize(mipi, mipi->broadcast); + if (ret) { + printk(BIOS_ERR, "dsi panel init error\n"); + goto error; + } + } + + if (dsc) { + cmd.size = DCS_HDR_LEN + DSC_PPS_LEN; + cmd.payload = dsc->pps_buf; + cmd.wait = 0x10; + mdss_dsi_cmds_tx(mipi, &cmd, 1, mipi->broadcast); + } + + if (pinfo->rotate && panel->rotate) + pinfo->rotate(); + + /* Reset DSI Interrupt/Error registers */ + mdss_dsi_clear_intr(mipi, mipi->dual_dsi); + +error: + return ret; +} + +int mdss_dsi_post_on(struct msm_fb_panel_data *panel) +{ + int ret = 0; + struct msm_panel_info *pinfo = &(panel->panel_info); + + if (pinfo->mipi.cmds_post_tg) { + ret = mdss_dsi_panel_initialize(&pinfo->mipi, + pinfo->mipi.broadcast); + if (ret) + printk(BIOS_ERR, "dsi panel init error\n"); + } + + return ret; +} + +int mdss_dsi_cmd_mode_config(struct msm_panel_info *pinfo, + uint16_t disp_width, + uint16_t disp_height, + uint16_t img_width, + uint16_t img_height, + uint16_t dst_format, + uint8_t ystride, + uint8_t lane_en, + uint8_t interleav, + uint32_t ctl_base) +{ + uint16_t dst_fmt = 0; + struct dsc_desc *dsc = NULL; + unsigned int data; + uint32_t uRegVal = 0; + + switch (dst_format) { + case DSI_VIDEO_DST_FORMAT_RGB565: + dst_fmt = DSI_CMD_DST_FORMAT_RGB565; + break; + + case DSI_VIDEO_DST_FORMAT_RGB666: + case DSI_VIDEO_DST_FORMAT_RGB666_LOOSE: + dst_fmt = DSI_CMD_DST_FORMAT_RGB666; + break; + + case DSI_VIDEO_DST_FORMAT_RGB888: + dst_fmt = DSI_CMD_DST_FORMAT_RGB888; + break; + + default: + printk(BIOS_ERR, "unsupported dst format\n"); + return ERROR; + } + + mdss_dsi_clock_config(ctl_base); + + writel(0, ctl_base + CTRL); + writel(0x03f03fe0, ctl_base + ERR_INT_MASK0); + + mdss_dsi_set_intr(ctl_base); + + writel(dst_fmt, ctl_base + COMMAND_MODE_MDP_CTRL); + + if (pinfo->compression_mode == COMPRESSION_DSC) + dsc = &pinfo->dsc; + + if (dsc) { + data = dsc->bytes_per_pkt; + + if (pinfo->mipi.insert_dcs_cmd) + data++; + + data <<= 16; + data |= 0x039; + writel(data, ctl_base + COMMAND_MODE_MDP_STREAM0_CTRL); + writel(data, ctl_base + COMMAND_MODE_MDP_STREAM1_CTRL); + + data = dsc->pic_height << 16; + data |= dsc->pclk_per_line; + writel(data, ctl_base + COMMAND_MODE_MDP_STREAM0_TOTAL); + writel(data, ctl_base + COMMAND_MODE_MDP_STREAM1_TOTAL); + + if (dsc->dsi_dsc_config) + dsc->dsi_dsc_config(pinfo->mipi.ctl_base, + DSI_CMD_MODE, dsc); + } + else { + + writel((img_width * ystride + 1) << 16 | 0x0039, + ctl_base + COMMAND_MODE_MDP_STREAM0_CTRL); + writel((img_width * ystride + 1) << 16 | 0x0039, + ctl_base + COMMAND_MODE_MDP_STREAM1_CTRL); + writel(img_height << 16 | img_width, + ctl_base + COMMAND_MODE_MDP_STREAM0_TOTAL); + writel(img_height << 16 | img_width, + ctl_base + COMMAND_MODE_MDP_STREAM1_TOTAL); + } + + uRegVal = readl(ctl_base+COMMAND_MODE_MDP_DCS_CMD_CTRL); + uRegVal = HWIO_OUT_FLD(uRegVal, COMMAND_MODE_MDP_DCS_CMD_CTRL, INSERT_DCS_COMMAND, 0x01); + + writel(uRegVal, ctl_base + COMMAND_MODE_MDP_DCS_CMD_CTRL); + writel(interleav << 30 | 0 << 24 | 0 << 20 | lane_en << 4 | 0x105, ctl_base + CTRL); + + uRegVal = 0; + uRegVal = HWIO_OUT_FLD( uRegVal, COMMAND_MODE_DMA_CTRL, EMBEDDED_MODE, 0x01); + uRegVal = HWIO_OUT_FLD( uRegVal, COMMAND_MODE_DMA_CTRL, POWER_MODE, 0x01); //Low power Mode + + writel(uRegVal, ctl_base + COMMAND_MODE_DMA_CTRL); + writel(BIT(28), ctl_base + MISR_CMD_CTRL); //enable MISR cmd ctrl. + + return 0; +} + +void mdss_dsi_clock_config(uint32_t ctl_base) +{ + /* Default to all clock off */ + uint32_t uClkCtrlReg = 0; + + /* Clock for AHI Bus Master, for DMA out from memory */ + uClkCtrlReg = HWIO_OUT_FLD( uClkCtrlReg, CLK_CTRL, DSI_AHBM_SCLK_ON, 1); + uClkCtrlReg = HWIO_OUT_FLD( uClkCtrlReg, CLK_CTRL, DSI_FORCE_ON_DYN_AHBM_HCLK, 1); + + /* Clock for MDP/DSI, for DMA out from MDP */ + uClkCtrlReg = HWIO_OUT_FLD( uClkCtrlReg, CLK_CTRL, DSI_PCLK_ON, 1); + + /* Clock for rest of DSI */ + uClkCtrlReg = HWIO_OUT_FLD( uClkCtrlReg, CLK_CTRL, DSI_AHBS_HCLK_ON, 1); + uClkCtrlReg = HWIO_OUT_FLD( uClkCtrlReg, CLK_CTRL, DSI_DSICLK_ON, 1); + + uClkCtrlReg = HWIO_OUT_FLD( uClkCtrlReg, CLK_CTRL, DSI_BYTECLK_ON, 1); + uClkCtrlReg = HWIO_OUT_FLD( uClkCtrlReg, CLK_CTRL, DSI_ESCCLK_ON, 1); + + writel(uClkCtrlReg, ctl_base + CLK_CTRL); + +} + + diff --git a/src/soc/qualcomm/sc7180/display/dsi_panel_display.c b/src/soc/qualcomm/sc7180/display/dsi_panel_display.c new file mode 100644 index 0000000..35efa9a --- /dev/null +++ b/src/soc/qualcomm/sc7180/display/dsi_panel_display.c @@ -0,0 +1,472 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 Qualcomm Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/mmio.h> +#include <stdlib.h> +#include <console/console.h> +#include <string.h> +#include <soc/mdss_6_2_0.h> +#include <soc/display/panel.h> +#include <soc/display/msm_panel.h> +#include <soc/display/mipi_dsi.h> +#include <soc/display/panel_display.h> +#include <soc/display/target_sc7180.h> + +int dsi_video_panel_config(struct msm_panel_info *pinfo, + struct lcdc_panel_info *plcdc); + +int dsi_cmd_panel_config(struct msm_panel_info *pinfo, + struct lcdc_panel_info *plcdc); + +static int dsi_platform_base_offset_adjust(uint32_t base) +{ + return target_display_get_base_offset(base); +} + +static int dsi_panel_ctl_base_setup(struct msm_panel_info *pinfo, + char *panel_destination) +{ + int base_offset = 0, + base1_offset = 0, + base_phy_offset = 0, + base1_phy_offset = 0; + + /* + * Base offsets may vary for few platforms. Add the difference to get + * proper base offset for the respective platform. + */ + base_offset = dsi_platform_base_offset_adjust(MIPI_DSI0_BASE); + base1_offset = dsi_platform_base_offset_adjust(MIPI_DSI1_BASE); + base_phy_offset = dsi_platform_base_offset_adjust(DSI0_PHY_BASE); + base1_phy_offset = dsi_platform_base_offset_adjust(DSI1_PHY_BASE); + + if (!strcmp(panel_destination, "DISPLAY_1")) { + pinfo->dest = DISPLAY_1; + pinfo->mipi.ctl_base = MIPI_DSI0_BASE + base_offset; + pinfo->mipi.phy_base = DSI0_PHY_BASE + base_phy_offset; + pinfo->mipi.sctl_base = MIPI_DSI1_BASE + base1_offset; + pinfo->mipi.sphy_base = DSI1_PHY_BASE + base1_phy_offset; + + if (pinfo->mipi.use_dsi1_pll) { + printk(BIOS_ERR, + "%s: Invalid combination: DSI0 controller +" + "DSI1 PLL, using DSI0 PLL\n", __func__); + pinfo->mipi.use_dsi1_pll = 0; + } + + } else if (!strcmp(panel_destination, "DISPLAY_2")) { + pinfo->dest = DISPLAY_2; + pinfo->mipi.ctl_base = MIPI_DSI1_BASE + base1_offset; + pinfo->mipi.phy_base = DSI1_PHY_BASE + base1_phy_offset; + pinfo->mipi.sctl_base = MIPI_DSI0_BASE + base_offset; + pinfo->mipi.sphy_base = DSI0_PHY_BASE + base_phy_offset; + + } else { + pinfo->dest = DISPLAY_UNKNOWN; + printk(BIOS_ERR, "%s: Unknown panel destination: %d\n", + __func__, pinfo->dest); + return ERROR; + } + + return NO_ERROR; +} + +int dsi_panel_init(struct msm_panel_info *pinfo, + struct panel_struct *pstruct) +{ + int ret = NO_ERROR; + /* Resolution setting*/ + pinfo->xres = pstruct->panelres->panel_width; + pinfo->yres = pstruct->panelres->panel_height; + pinfo->lcdc.h_back_porch = pstruct->panelres->hback_porch; + pinfo->lcdc.h_front_porch = pstruct->panelres->hfront_porch; + pinfo->lcdc.h_pulse_width = pstruct->panelres->hpulse_width; + pinfo->lcdc.v_back_porch = pstruct->panelres->vback_porch; + pinfo->lcdc.v_front_porch = pstruct->panelres->vfront_porch; + pinfo->lcdc.v_pulse_width = pstruct->panelres->vpulse_width; + pinfo->lcdc.hsync_skew = pstruct->panelres->hsync_skew; + + pinfo->border_top = pstruct->panelres->vtop_border; + pinfo->border_bottom = pstruct->panelres->vbottom_border; + pinfo->border_left = pstruct->panelres->hleft_border; + pinfo->border_right = pstruct->panelres->hright_border; + + printk(BIOS_INFO, "%s: left=%d right=%d top=%d bottom=%d\n", __func__, + pinfo->border_left, pinfo->border_right, + pinfo->border_top, pinfo->border_bottom); + + pinfo->xres += (pinfo->border_left + pinfo->border_right); + pinfo->yres += (pinfo->border_top + pinfo->border_bottom); + + if (pstruct->paneldata->panel_operating_mode & DUAL_PIPE_FLAG) + pinfo->lcdc.dual_pipe = 1; + + if (pstruct->paneldata->panel_operating_mode & PIPE_SWAP_FLAG) + pinfo->lcdc.pipe_swap = 1; + + if (pstruct->paneldata->panel_operating_mode & SPLIT_DISPLAY_FLAG) + pinfo->lcdc.split_display = 1; + + if (pstruct->paneldata->panel_operating_mode & DST_SPLIT_FLAG) + pinfo->lcdc.dst_split = 1; + + if (pstruct->paneldata->panel_operating_mode & DUAL_DSI_FLAG) + pinfo->mipi.dual_dsi = 1; + + if (pstruct->paneldata->panel_operating_mode & USE_DSI1_PLL_FLAG) + pinfo->mipi.use_dsi1_pll = 1; + + /* Color setting*/ + pinfo->lcdc.border_clr = pstruct->color->border_color; + pinfo->lcdc.underflow_clr = pstruct->color->underflow_color; + pinfo->mipi.rgb_swap = pstruct->color->color_order; + pinfo->bpp = pstruct->color->color_format; + + switch (pinfo->bpp) { + case BPP_16: + pinfo->mipi.dst_format = DSI_VIDEO_DST_FORMAT_RGB565; + break; + case BPP_18: + if (pstruct->color->pixel_packing) + pinfo->mipi.dst_format = DSI_VIDEO_DST_FORMAT_RGB666_LOOSE; + else + pinfo->mipi.dst_format = DSI_VIDEO_DST_FORMAT_RGB666; + break; + case BPP_24: + default: + pinfo->mipi.dst_format = DSI_VIDEO_DST_FORMAT_RGB888; + break; + } + + /* Panel generic info */ + pinfo->mipi.mode = pstruct->paneldata->panel_type; + + if (pinfo->mipi.mode) + pinfo->type = MIPI_CMD_PANEL; + else + pinfo->type = MIPI_VIDEO_PANEL; + + pinfo->clk_rate = pstruct->paneldata->panel_clockrate; + pinfo->orientation = pstruct->paneldata->panel_orientation; + pinfo->mipi.interleave_mode = pstruct->paneldata->interleave_mode; + pinfo->mipi.broadcast = pstruct->paneldata->panel_broadcast_mode; + pinfo->mipi.vc = pstruct->paneldata->dsi_virtualchannel_id; + pinfo->mipi.frame_rate = pstruct->paneldata->panel_framerate; + pinfo->mipi.stream = pstruct->paneldata->dsi_stream; + pinfo->mipi.mode_gpio_state = pstruct->paneldata->mode_gpio_state; + pinfo->mipi.bitclock = pstruct->paneldata->panel_bitclock_freq; + + if (pinfo->mipi.bitclock) { + /* panel_clockrate is depcrated in favor of bitclock_freq */ + pinfo->clk_rate = pinfo->mipi.bitclock; + } + + pinfo->mipi.use_enable_gpio = pstruct->paneldata->panel_with_enable_gpio; + + ret = dsi_panel_ctl_base_setup(pinfo, + pstruct->paneldata->panel_destination); + + if (ret) + return ret; + + /* Video Panel configuration */ + pinfo->mipi.pulse_mode_hsa_he = pstruct->videopanel->hsync_pulse; + pinfo->mipi.hfp_power_stop = pstruct->videopanel->hfp_power_mode; + pinfo->mipi.hbp_power_stop = pstruct->videopanel->hbp_power_mode; + pinfo->mipi.hsa_power_stop = pstruct->videopanel->hsa_power_mode; + pinfo->mipi.eof_bllp_power_stop = pstruct->videopanel->bllp_eof_power_mode; + pinfo->mipi.bllp_power_stop = pstruct->videopanel->bllp_power_mode; + pinfo->mipi.traffic_mode = pstruct->videopanel->traffic_mode; + pinfo->mipi.eof_bllp_power = pstruct->videopanel->bllp_eof_power; + + /* Command Panel configuration */ + pinfo->mipi.insert_dcs_cmd = pstruct->commandpanel->tedcs_command; + pinfo->mipi.wr_mem_continue = pstruct->commandpanel->tevsync_continue_lines; + pinfo->mipi.wr_mem_start = pstruct->commandpanel->tevsync_rdptr_irqline; + pinfo->mipi.te_sel = pstruct->commandpanel->tepin_select; + pinfo->autorefresh_enable = pstruct->commandpanel->autorefresh_enable; + pinfo->autorefresh_framenum = pstruct->commandpanel->autorefresh_framenumdiv; + + /* Data lane configuraiton */ + pinfo->mipi.num_of_lanes = pstruct->laneconfig->dsi_lanes; + pinfo->mipi.data_lane0 = pstruct->laneconfig->lane0_state; + pinfo->mipi.data_lane1 = pstruct->laneconfig->lane1_state; + pinfo->mipi.data_lane2 = pstruct->laneconfig->lane2_state; + pinfo->mipi.data_lane3 = pstruct->laneconfig->lane3_state; + pinfo->mipi.lane_swap = pstruct->laneconfig->dsi_lanemap; + pinfo->mipi.force_clk_lane_hs = pstruct->laneconfig->force_clk_lane_hs; + + pinfo->mipi.t_clk_post = pstruct->paneltiminginfo->tclk_post; + pinfo->mipi.t_clk_pre = pstruct->paneltiminginfo->tclk_pre; + pinfo->mipi.mdp_trigger = pstruct->paneltiminginfo->dsi_mdp_trigger; + pinfo->mipi.dma_trigger = pstruct->paneltiminginfo->dsi_dma_trigger; + + if (pinfo->compression_mode == COMPRESSION_DSC) { + struct dsc_desc *dsc = &pinfo->dsc; + struct dsc_parameters *dsc_params = NULL; + + if (!pstruct->config) { + printk(BIOS_ERR, + "ERROR: DSC cannot be used without topology_config\n"); + return ERROR; + } + dsc_params = pstruct->config->dsc; + if (!dsc_params) { + printk(BIOS_ERR, "ERROR: DSC params are NULL\n"); + return ERROR; + } + + dsc->major = dsc_params->major; + dsc->minor = dsc_params->minor; + dsc->scr_rev = dsc_params->scr_rev; + dsc->pps_id = dsc_params->pps_id; + dsc->slice_height = dsc_params->slice_height; + dsc->slice_width = dsc_params->slice_width; + dsc->bpp = dsc_params->bpp; + dsc->bpc = dsc_params->bpc; + dsc->slice_per_pkt = dsc_params->slice_per_pkt; + dsc->block_pred_enable = dsc_params->block_prediction; + dsc->enable_422 = 0; + dsc->convert_rgb = 1; + dsc->vbr_enable = 0; + + if (dsc->parameter_calc) + dsc->parameter_calc(pinfo); + } + + pinfo->pre_on = dsi_panel_pre_on; + pinfo->pre_off = dsi_panel_pre_off; + pinfo->on = dsi_panel_post_on; + pinfo->off = dsi_panel_post_off; + pinfo->rotate = dsi_panel_rotation; + pinfo->config = dsi_panel_config; + + return NO_ERROR; +} + +/* Panel Callbacks */ +int dsi_panel_pre_on(void) +{ + return target_display_pre_on(); +} + +int dsi_panel_pre_off(void) +{ + return target_display_pre_off(); +} + +int dsi_panel_post_on(void) +{ + int ret = NO_ERROR; + + ret = target_display_post_on(); + if (ret) + return ret; + + return oem_panel_on(); +} + +int dsi_panel_post_off(void) +{ + int ret = NO_ERROR; + + ret = target_display_post_off(); + if (ret) + return ret; + + return oem_panel_off(); +} + +int dsi_panel_rotation(void) +{ + return oem_panel_rotation(); +} + +int dsi_video_panel_config(struct msm_panel_info *pinfo, + struct lcdc_panel_info *plcdc) +{ + int ret = NO_ERROR; + uint8_t lane_enable = 0; + uint32_t panel_width = pinfo->xres; + uint32_t final_xres, final_yres, final_width; + uint32_t final_height, final_hbp, final_hfp, final_vbp; + uint32_t final_vfp, final_hpw, final_vpw, low_pwr_stop; + struct dsc_desc *dsc = NULL; + + if (pinfo->mipi.dual_dsi) + panel_width = panel_width / 2; + + if (pinfo->mipi.data_lane0) + lane_enable |= (1 << 0); + if (pinfo->mipi.data_lane1) + lane_enable |= (1 << 1); + if (pinfo->mipi.data_lane2) + lane_enable |= (1 << 2); + if (pinfo->mipi.data_lane3) + lane_enable |= (1 << 3); + + if (pinfo->compression_mode == COMPRESSION_DSC) { + dsc = &pinfo->dsc; + panel_width = dsc->pclk_per_line; + } + + final_xres = panel_width; + final_width = panel_width + pinfo->lcdc.xres_pad; + final_yres = pinfo->yres; + final_height = pinfo->yres + pinfo->lcdc.yres_pad; + final_hbp = pinfo->lcdc.h_back_porch; + final_hfp = pinfo->lcdc.h_front_porch; + final_vbp = pinfo->lcdc.v_back_porch; + final_vfp = pinfo->lcdc.v_front_porch; + final_hpw = pinfo->lcdc.h_pulse_width; + final_vpw = pinfo->lcdc.v_pulse_width; + low_pwr_stop = (pinfo->mipi.hfp_power_stop << 8) | + (pinfo->mipi.hbp_power_stop << 4) | + pinfo->mipi.hsa_power_stop; + + ret = mdss_dsi_video_mode_config(pinfo, + final_width, final_height, + final_xres, final_yres, + final_hfp, final_hbp + final_hpw, + final_vfp, final_vbp + final_vpw, + final_hpw, final_vpw, + pinfo->mipi.dst_format, + pinfo->mipi.traffic_mode, + lane_enable, + pinfo->mipi.pulse_mode_hsa_he, + low_pwr_stop, + pinfo->mipi.eof_bllp_power, + pinfo->mipi.interleave_mode, + pinfo->mipi.ctl_base); + + if (pinfo->mipi.dual_dsi) + ret = mdss_dsi_video_mode_config(pinfo, + final_width, final_height, + final_xres, final_yres, + final_hfp, final_hbp + final_hpw, + final_vfp, final_vbp + final_vpw, + final_hpw, final_vpw, + pinfo->mipi.dst_format, + pinfo->mipi.traffic_mode, + lane_enable, + pinfo->mipi.pulse_mode_hsa_he, + low_pwr_stop, + pinfo->mipi.eof_bllp_power, + pinfo->mipi.interleave_mode, + pinfo->mipi.sctl_base); + + return ret; +} + +int dsi_cmd_panel_config(struct msm_panel_info *pinfo, + struct lcdc_panel_info *plcdc) +{ + int ret = NO_ERROR; + uint8_t lane_en = 0; + uint8_t ystride = pinfo->bpp / 8; + uint32_t panel_width = pinfo->xres; + struct dsc_desc *dsc = NULL; + uint32_t final_xres, final_yres, final_width; + uint32_t final_height; + + if (pinfo->mipi.dual_dsi) + panel_width = panel_width / 2; + + if (pinfo->mipi.data_lane0) + lane_en |= (1 << 0); + + if (pinfo->mipi.data_lane1) + lane_en |= (1 << 1); + + if (pinfo->mipi.data_lane2) + lane_en |= (1 << 2); + + if (pinfo->mipi.data_lane3) + lane_en |= (1 << 3); + + if (pinfo->compression_mode == COMPRESSION_DSC) { + dsc = &pinfo->dsc; + panel_width = dsc->pclk_per_line; + } + + final_xres = panel_width; + final_width = panel_width + pinfo->lcdc.xres_pad; + final_yres = pinfo->yres; + final_height = pinfo->yres + pinfo->lcdc.yres_pad; + + ret = mdss_dsi_cmd_mode_config(pinfo, final_width, final_height, + final_xres, final_yres, + pinfo->mipi.dst_format, + ystride, lane_en, + pinfo->mipi.interleave_mode, + pinfo->mipi.ctl_base); + + if (pinfo->mipi.dual_dsi) + ret = mdss_dsi_cmd_mode_config(pinfo, final_width, final_height, + final_xres, final_yres, + pinfo->mipi.dst_format, + ystride, lane_en, + pinfo->mipi.interleave_mode, + pinfo->mipi.sctl_base); + + return ret; +} + + +int dsi_panel_config(void *pdata) +{ + struct msm_panel_info *pinfo = (struct msm_panel_info *)pdata; + struct lcdc_panel_info *plcdc = NULL; + int ret = NO_ERROR; + + if (pinfo == NULL) + return ERROR; + + plcdc = &(pinfo->lcdc); + if (plcdc == NULL) + return ERROR; + + + if (pinfo->mipi.mode == DSI_VIDEO_MODE) + ret = dsi_video_panel_config(pinfo, plcdc); + else + ret = dsi_cmd_panel_config(pinfo, plcdc); + + return ret; +} + +int32_t panel_name_to_id(struct panel_list supp_panels[], + uint32_t supp_panels_size, + const char *panel_name) +{ + uint32_t i; + int32_t panel_id = ERROR; + + if (!panel_name) { + printk(BIOS_ERR, "Invalid panel name\n"); + return panel_id; + } + + for (i = 0; i < supp_panels_size; i++) { + if (!strncmp(panel_name, supp_panels[i].name, + MAX_PANEL_ID_LEN)) { + panel_id = supp_panels[i].id; + break; + } + } + + return panel_id; +} + diff --git a/src/soc/qualcomm/sc7180/display/target_sc7180.c b/src/soc/qualcomm/sc7180/display/target_sc7180.c new file mode 100644 index 0000000..e79c4cb --- /dev/null +++ b/src/soc/qualcomm/sc7180/display/target_sc7180.c @@ -0,0 +1,112 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 Qualcomm Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/mmio.h> +#include <lib.h> +#include <console/console.h> +#include <delay.h> +#include <device/device.h> +#include <edid.h> +#include <stdlib.h> +#include <string.h> +#include <soc/display/panel.h> +#include <soc/display/msm_panel.h> +#include <soc/mdss_6_2_0.h> +#include <soc/display/mipi_dsi.h> +#include <soc/display/panel_display.h> +#include <soc/display/target_sc7180.h> +#include <gpio.h> +#include <soc/gpio.h> + +#define STRENGTH_SIZE_IN_BYTES_SDM845 10 +#define REGULATOR_SIZE_IN_BYTES_SDM845 5 +#define LANE_SIZE_IN_BYTES_SDM845 20 + +int target_dsi_phy_config(struct mdss_dsi_phy_ctrl *phy_db) +{ + memcpy(phy_db->strength, panel_strength_ctrl, + STRENGTH_SIZE_IN_BYTES_SDM845 * sizeof(uint32_t)); + memcpy(phy_db->regulator, panel_regulator_settings, + REGULATOR_SIZE_IN_BYTES_SDM845 * sizeof(uint32_t)); + memcpy(phy_db->laneCfg, panel_lane_config, + LANE_SIZE_IN_BYTES_SDM845); + return NO_ERROR; +} + +int target_backlight_ctrl(uint8_t enable) +{ + + if (enable) { + gpio_configure(GPIO(12), GPIO_FUNC_GPIO, GPIO_NO_PULL, + GPIO_2MA, GPIO_OUTPUT_ENABLE); //BackLight enable GPIO + + gpio_set(GPIO(12), 1); + + } else { + gpio_set(GPIO(12), 1); + + } + return NO_ERROR; +} + +int target_panel_reset(uint8_t enable, struct panel_reset_sequence *resetseq, + struct msm_panel_info *pinfo) +{ + return NO_ERROR; + +} + +int target_set_switch_gpio(int enable) +{ + printk(BIOS_INFO, "%s: Turn bridge gpio's on\n", __func__); + if (enable) { + gpio_configure(GPIO(14), GPIO_FUNC_GPIO, GPIO_NO_PULL, + GPIO_2MA, GPIO_OUTPUT_ENABLE); //Bridge Enable GPIO + + gpio_set(GPIO(14), 1); + + gpio_configure(GPIO(106), GPIO_FUNC_GPIO, GPIO_NO_PULL, + GPIO_8MA, GPIO_OUTPUT_ENABLE); //PP3300 EDP power supply + + gpio_set(GPIO(106), 1); + } else { + gpio_set(GPIO(14), 1); + gpio_set(GPIO(106), 1); + } + return NO_ERROR; +} + +int target_display_pre_on(void) +{ + return NO_ERROR; +} + +int target_display_pre_off(void) +{ + return NO_ERROR; +} +int target_display_post_on(void) +{ + return NO_ERROR; +} +int target_display_post_off(void) +{ + return NO_ERROR; +} +int target_display_get_base_offset(uint32_t base) +{ + return 0; +} + diff --git a/src/soc/qualcomm/sc7180/include/soc/display/mipi_dsi.h b/src/soc/qualcomm/sc7180/include/soc/display/mipi_dsi.h new file mode 100644 index 0000000..b3eebf8 --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/display/mipi_dsi.h @@ -0,0 +1,96 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2018 Qualcomm Technologies + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _PLATFORM_MSM_SHARED_MIPI_DSI_H_ +#define _PLATFORM_MSM_SHARED_MIPI_DSI_H_ + +#include <soc/display/msm_panel.h> + +#define PASS 0 +#define FAIL 1 +#define DSI_VIDEO_MODE_DONE_MASK BIT(17) +#define DSI_VIDEO_MODE_DONE_AK BIT(16) +#define DSI_VIDEO_MODE_DONE_STAT BIT(16) +/********************************************************** + DSI register configuration options + **********************************************************/ +#define MIPI_DSI_MRPS 0x04 /* Maximum Return Packet Size */ +#define MIPI_DSI_REG_LEN 16 /* 4 x 4 bytes register */ +#define TIMING_FLUSH 0x1E4 +#define TIMING_DB_MODE 0x1E8 +#define DSI_HW_REV_241 0x20040001 /* SDM845 */ +#define RDBK_DATA0 0x06C +#define DSI_VIDEO_DST_FORMAT_RGB565 0 +#define DSI_VIDEO_DST_FORMAT_RGB666 1 +#define DSI_VIDEO_DST_FORMAT_RGB666_LOOSE 2 +#define DSI_VIDEO_DST_FORMAT_RGB888 3 +#define DSI_CMD_DST_FORMAT_RGB111 0 +#define DSI_CMD_DST_FORMAT_RGB332 3 +#define DSI_CMD_DST_FORMAT_RGB444 4 +#define DSI_CMD_DST_FORMAT_RGB565 6 +#define DSI_CMD_DST_FORMAT_RGB666 7 +#define DSI_CMD_DST_FORMAT_RGB888 8 + +struct mipi_dsi_cmd { + uint32_t size; + char *payload; + int wait; +}; + +enum { + DSI_VIDEO_MODE, + DSI_CMD_MODE, +}; + +int mdss_dsi_config(struct msm_fb_panel_data *panel); +int mdss_dsi_video_mode_config(struct msm_panel_info *pinfo, + uint16_t disp_width, + uint16_t disp_height, + uint16_t img_width, + uint16_t img_height, + uint16_t hsync_porch0_fp, + uint16_t hsync_porch0_bp, + uint16_t vsync_porch0_fp, + uint16_t vsync_porch0_bp, + uint16_t hsync_width, + uint16_t vsync_width, + uint16_t dst_format, + uint16_t traffic_mode, + uint8_t lane_en, + uint8_t pulse_mode_hsa_he, + uint32_t low_pwr_stop_mode, + uint8_t eof_bllp_pwr, + uint8_t interleav, + uint32_t ctl_base); + +int mdss_dsi_cmd_mode_config(struct msm_panel_info *pinfo, + uint16_t disp_width, + uint16_t disp_height, + uint16_t img_width, + uint16_t img_height, + uint16_t dst_format, + uint8_t ystride, + uint8_t lane_en, + uint8_t interleav, + uint32_t ctl_base); + +int mdss_dsi_cmds_tx(struct mipi_panel_info *mipi, + struct mipi_dsi_cmd *cmds, int count, char dual_dsi); +int mdss_dsi_cmds_rx(struct mipi_panel_info *mipi, uint32_t **rp, int rp_len, + int rdbk_len); +int mdss_dsi_post_on(struct msm_fb_panel_data *panel); + +#endif + diff --git a/src/soc/qualcomm/sc7180/include/soc/display/panel_display.h b/src/soc/qualcomm/sc7180/include/soc/display/panel_display.h new file mode 100644 index 0000000..a36e31b --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/display/panel_display.h @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2018 Qualcomm Technologies + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _PANEL_DISPLAY_H_ +#define _PANEL_DISPLAY_H_ +/*---------------------------------------------------------------------------*/ +/* MACRO definition */ +/*---------------------------------------------------------------------------*/ +#define BPP_16 16 +#define BPP_18 18 +#define BPP_24 24 +#define TIMING_SIZE 48 +#define REGULATOR_SIZE 28 +#define DUAL_DSI_FLAG 0x1 +#define DUAL_PIPE_FLAG 0x2 +#define PIPE_SWAP_FLAG 0x4 +#define SPLIT_DISPLAY_FLAG 0x8 +#define DST_SPLIT_FLAG 0x10 +#define USE_DSI1_PLL_FLAG 0x20 +#define MAX_PANEL_ID_LEN 64 +#include <soc/display/panel.h> +/*---------------------------------------------------------------------------*/ +/* struct definition */ +/*---------------------------------------------------------------------------*/ +struct panel_struct { + struct panel_config *paneldata; + struct panel_resolution *panelres; + struct color_info *color; + struct videopanel_info *videopanel; + struct commandpanel_info *commandpanel; + struct command_state *state; + struct lane_configuration *laneconfig; + struct panel_timing *paneltiminginfo; + struct panel_reset_sequence *panelresetseq; + struct backlight *backlightinfo; + struct topology_config *config; +}; + +struct panel_list { + char name[MAX_PANEL_ID_LEN]; + uint32_t id; +}; + +/*---------------------------------------------------------------------------*/ +/* API */ +/*---------------------------------------------------------------------------*/ +int dsi_panel_init(struct msm_panel_info *pinfo, + struct panel_struct *pstruct); +int dsi_panel_pre_on(void); +int dsi_panel_post_on(void); +int dsi_panel_pre_off(void); +int dsi_panel_post_off(void); +int dsi_panel_rotation(void); +int dsi_panel_config(void *cfg); +int oem_panel_rotation(void); +int oem_panel_on(void); +int oem_panel_off(void); + +/* OEM support API */ +int32_t panel_name_to_id(struct panel_list supp_panels[], + uint32_t supp_panels_size, const char *panel_name); + +int oem_panel_select(const char *panel_name, struct panel_struct *panelstruct, + struct msm_panel_info *pinfo, struct mdss_dsi_phy_ctrl *phy_db); +#endif + diff --git a/src/soc/qualcomm/sc7180/include/soc/display/target_sc7180.h b/src/soc/qualcomm/sc7180/include/soc/display/target_sc7180.h new file mode 100644 index 0000000..1ca9c1d --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/display/target_sc7180.h @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2020 Qualcomm Technologies + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _TARGET_DISPLAY_H +#define _TARGET_DISPLAY_H + +#include <soc/display/panel.h> +#include <soc/display/msm_panel.h> + +/*---------------------------------------------------------------------------*/ +/* Target Physical configuration */ +/*---------------------------------------------------------------------------*/ +static const uint32_t panel_strength_ctrl[] = { + 0x55, 0x03, + 0x55, 0x03, + 0x55, 0x03, + 0x55, 0x03, + 0x55, 0x00 +}; + +static const uint32_t panel_regulator_settings[] = { + 0x1d, 0x1d, 0x1d, 0x1d, 0x1d +}; + +static const char panel_lane_config[] = { + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x80, +}; + +static const char panel_bist_ctrl[] = { }; +static const uint32_t panel_physical_ctrl[] = { }; + +/*---------------------------------------------------------------------------*/ +/* Functions */ +/*---------------------------------------------------------------------------*/ +int target_display_pre_on(void); +int target_display_pre_off(void); +int target_display_post_on(void); +int target_display_post_off(void); +int target_display_get_base_offset(uint32_t base); +int target_backlight_ctrl(uint8_t enable); +int target_set_switch_gpio(int enable_dsi2hdmibridge); +int target_panel_reset(uint8_t enable, struct panel_reset_sequence *resetseq, + struct msm_panel_info *pinfo); +int target_dsi_phy_config(struct mdss_dsi_phy_ctrl *phy_db); +#endif + -- To view, visit https://review.coreboot.org/c/coreboot/+/39614 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie64354ce8bc2a64b891fb9478fbca38d6ec4c321 Gerrit-Change-Number: 39614 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-MessageType: newchange

2 weeks, 5 days

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Change in coreboot[master]: soc/intel/cannonlake: [TEST-ONLY] Enable Audio DSP OSC qualification ...

by Aamir Bohra (Code Review)

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37604 ) Change subject: soc/intel/cannonlake: [TEST-ONLY] Enable Audio DSP OSC qualification for low power idle ...................................................................... soc/intel/cannonlake: [TEST-ONLY] Enable Audio DSP OSC qualification for low power idle Change-Id: I20b793b95483af03ce4ae068ac07864a9e90d39b Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/soc/intel/cannonlake/finalize.c M src/soc/intel/cannonlake/include/soc/pmc.h 2 files changed, 9 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/37604/1 diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c index 115b732..a37ac98 100644 --- a/src/soc/intel/cannonlake/finalize.c +++ b/src/soc/intel/cannonlake/finalize.c @@ -92,11 +92,16 @@ write8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, reg8); } - /* Disable XTAL shutdown qualification for low power idle. */ if (config->s0ix_enable) { + /* Disable XTAL shutdown qualification for low power idle. */ reg32 = read32(pmcbase + CPPMVRIC); reg32 |= XTALSDQDIS; write32(pmcbase + CPPMVRIC, reg32); + + /* Enable Audio DSP OSC qualification for low power idle. */ + reg32 = read32(pmcbase + CPPMVRIC2); + reg32 &= ~ADSPOSCDIS; + write32(pmcbase + CPPMVRIC2, reg32); } pch_handle_sideband(config); diff --git a/src/soc/intel/cannonlake/include/soc/pmc.h b/src/soc/intel/cannonlake/include/soc/pmc.h index 252c719..878271c 100644 --- a/src/soc/intel/cannonlake/include/soc/pmc.h +++ b/src/soc/intel/cannonlake/include/soc/pmc.h @@ -156,6 +156,9 @@ #define CPPMVRIC 0x1B1C #define XTALSDQDIS (1 << 22) +#define CPPMVRIC2 0x1B1C +#define ADSPOSCDIS (1 << 22) + #define IRQ_REG ACTL #define SCI_IRQ_ADJUST 0 #define ACTL 0x1BD8 -- To view, visit https://review.coreboot.org/c/coreboot/+/37604 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20b793b95483af03ce4ae068ac07864a9e90d39b Gerrit-Change-Number: 37604 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

3 weeks, 1 day

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Change in coreboot[master]: util/abuild: Run `make .xcompile` only once

by Nico Huber (Code Review)

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42640 ) Change subject: util/abuild: Run `make .xcompile` only once ...................................................................... util/abuild: Run `make .xcompile` only once If abuild called itself recursively, the file already exists and we can spare us one evaluation of all the makefiles per recursive abuild run. Change-Id: Id3e2239354ec251c24c03c971987586deeb026c5 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M util/abuild/abuild 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/42640/1 diff --git a/util/abuild/abuild b/util/abuild/abuild index 022567d..d41fcd1 100755 --- a/util/abuild/abuild +++ b/util/abuild/abuild @@ -769,8 +769,6 @@ exit 1 fi -$MAKE -C"${ROOT}" .xcompile || exit 1 - customizing=$(echo "$customizing" | cut -c3-) if [ "$customizing" = "" ]; then customizing="default configuration" @@ -780,6 +778,7 @@ PASSED_BOARDS="$(realpath ${TARGET}/passing_boards)" if [ "$recursive" = "false" ]; then + $MAKE -C"${ROOT}" .xcompile || exit 1 rm -f "$FAILED_BOARDS" "$PASSED_BOARDS" fi -- To view, visit https://review.coreboot.org/c/coreboot/+/42640 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id3e2239354ec251c24c03c971987586deeb026c5 Gerrit-Change-Number: 42640 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

3 weeks, 3 days

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Change in coreboot[master]: soc/amd/common: Refactor program_gpios() for overrides

by Kyösti Mälkki (Code Review)

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43050 ) Change subject: soc/amd/common: Refactor program_gpios() for overrides ...................................................................... soc/amd/common: Refactor program_gpios() for overrides Some GPIO listed in override_cfg may not be programmed. Change-Id: Ia8e47b2a278a1887db5406c1f863ddafa6a68675 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/common/block/gpio_banks/gpio.c 1 file changed, 20 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/43050/1 diff --git a/src/soc/amd/common/block/gpio_banks/gpio.c b/src/soc/amd/common/block/gpio_banks/gpio.c index b52d7f1..1019d79 100644 --- a/src/soc/amd/common/block/gpio_banks/gpio.c +++ b/src/soc/amd/common/block/gpio_banks/gpio.c @@ -189,7 +189,16 @@ void program_gpios(const struct soc_amd_gpio *gpio_list_ptr, size_t size) { - size_t i; + return gpio_configure_pads_with_override(gpio_list_ptr, size, NULL, 0); +} + +void gpio_configure_pads_with_override(const struct soc_amd_gpio *base_cfg, + size_t base_num_pads, + const struct soc_amd_gpio *override_cfg, + size_t override_num_pads) +{ + const struct soc_amd_gpio *c; + size_t i, j; /* * Disable blocking wake/interrupt status generation while updating @@ -203,8 +212,16 @@ */ master_switch_clr(GPIO_MASK_STS_EN | GPIO_INTERRUPT_EN); - for (i = 0; i < size; i++) - set_single_gpio(&gpio_list_ptr[i]); + for (i = 0; i < base_num_pads; i++) { + c = &base_cfg[i]; + for (j = 0; override_cfg && j < override_num_pads; j++) { + if (c->gpio == override_cfg[j].gpio) { + c = &override_cfg[j]; + break; + } + } + set_single_gpio(c); + } /* * Re-enable interrupt status generation. @@ -229,36 +246,3 @@ return 0; } - -/* - * This function checks to see if there is an override config present for the - * provided pad_config. If no override config is present, then the input config - * is returned. Else, it returns the override config. - */ -static const struct soc_amd_gpio *gpio_get_config(const struct soc_amd_gpio *c, - const struct soc_amd_gpio *override_cfg_table, - size_t num) -{ - size_t i; - if (override_cfg_table == NULL) - return c; - for (i = 0; i < num; i++) { - if (c->gpio == override_cfg_table[i].gpio) - return override_cfg_table + i; - } - return c; -} -void gpio_configure_pads_with_override(const struct soc_amd_gpio *base_cfg, - size_t base_num_pads, - const struct soc_amd_gpio *override_cfg, - size_t override_num_pads) -{ - size_t i; - const struct soc_amd_gpio *c; - - for (i = 0; i < base_num_pads; i++) { - c = gpio_get_config(base_cfg + i, override_cfg, - override_num_pads); - program_gpios(c, 1); - } -} -- To view, visit https://review.coreboot.org/c/coreboot/+/43050 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8e47b2a278a1887db5406c1f863ddafa6a68675 Gerrit-Change-Number: 43050 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

3 weeks, 5 days

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Change in coreboot[master]: [WIP]arch/arm: Allow program loading of Linux kernels

by Arthur Heymans (Code Review)

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35409 ) Change subject: [WIP]arch/arm: Allow program loading of Linux kernels ...................................................................... [WIP]arch/arm: Allow program loading of Linux kernels On ARM the linux kernel takes 3 arguments: r0 = 0 r1 = machine_type (0xffffffff if using FDT) r2 = &fdt To allow this, a function with a different signature needs to be used when using a FIT payload. Change-Id: Ie0dcc26d647941de71669345911ba288341b834b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/arm/boot.c 1 file changed, 16 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/35409/1 diff --git a/src/arch/arm/boot.c b/src/arch/arm/boot.c index 9d1e4cd..fd7ba68 100644 --- a/src/arch/arm/boot.c +++ b/src/arch/arm/boot.c @@ -11,15 +11,29 @@ * GNU General Public License for more details. */ +#include <cbfs.h> #include <arch/cache.h> #include <program_loading.h> void arch_prog_run(struct prog *prog) { void (*doit)(void *); + void (*doit_3)(void *, void *, void *); + char *program_arg = prog_entry_arg(prog); cache_sync_instructions(); - doit = prog_entry(prog); - doit(prog_entry_arg(prog)); + /* The Linux kernel takes 3 dword's as argument */ + switch (prog_cbfs_type(prog)) { + case CBFS_TYPE_FIT: /* Flattened image tree */ + if (CONFIG(PAYLOAD_FIT_SUPPORT)) { + doit_3 = prog_entry(prog); + doit_3((void *)program_arg, (void *)(program_arg + sizeof(void *)), + (void *)(program_arg + 2 * sizeof(void *))); + break; + } /* else fall-through */ + default: + doit = prog_entry(prog); + doit((void *)program_arg); + } } -- To view, visit https://review.coreboot.org/c/coreboot/+/35409 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie0dcc26d647941de71669345911ba288341b834b Gerrit-Change-Number: 35409 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

1 month

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Change in coreboot[master]: mb/up/squared: set primary GPU in the devicetree

by Maxim Polyakov (Code Review)

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39375 ) Change subject: mb/up/squared: set primary GPU in the devicetree ...................................................................... mb/up/squared: set primary GPU in the devicetree Change-Id: I368fa5d13615dc4ee37db596cb6a5eef993fc220 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/up/squared/devicetree.cb M src/mainboard/up/squared/romstage.c 2 files changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/39375/1 diff --git a/src/mainboard/up/squared/devicetree.cb b/src/mainboard/up/squared/devicetree.cb index d7281a6..6ba3bf4 100644 --- a/src/mainboard/up/squared/devicetree.cb +++ b/src/mainboard/up/squared/devicetree.cb @@ -1,5 +1,8 @@ chip soc/intel/apollolake + # Set IGD as the primary graphics device + register "primary_gpu" = "PRIMARY_IGD" + # Override USB port configuration register "usb_config_override" = "1" # USB 2.0 diff --git a/src/mainboard/up/squared/romstage.c b/src/mainboard/up/squared/romstage.c index 55235a8..fd06559 100644 --- a/src/mainboard/up/squared/romstage.c +++ b/src/mainboard/up/squared/romstage.c @@ -169,7 +169,6 @@ config->RmtCheckRun = 0x3; // 0x0 config->RmtMarginCheckScaleHighThreshold = 0xC8; // 0x0 config->EnhancePort8xhDecoding = 0x0; // 0x1 - config->PrimaryVideoAdaptor = 0x2; // 0x0 config->Ch0_DeviceWidth = 0x1; // 0x0 config->Ch0_Option = 0x3; // 0x0 -- To view, visit https://review.coreboot.org/c/coreboot/+/39375 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I368fa5d13615dc4ee37db596cb6a5eef993fc220 Gerrit-Change-Number: 39375 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

1 month

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