Change in coreboot[master]: mb/lenovo/t440p: update VBT
by DaLao (Code Review)
DaLao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40723 )
Change subject: mb/lenovo/t440p: update VBT
......................................................................
mb/lenovo/t440p: update VBT
Update T440p's VBT from to version 2179. Extracted from the
latest bios update file: T440p's bios image
https://download.lenovo.com/pccbbs/mobiles/gluj42us.iso
Test: boot t440p with both SeaBIOS and Tianocore payloads,
verify dp output and backlight control all works under both
Linux and Windows.
Signed-off-by: dalao <dalao(a)tutanota.com>
Change-Id: If8669b8de6fa0801e261138651b8b2cf50432a70
---
M src/mainboard/lenovo/t440p/data.vbt
1 file changed, 0 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/40723/1
diff --git a/src/mainboard/lenovo/t440p/data.vbt b/src/mainboard/lenovo/t440p/data.vbt
index 1b2cd87..79077cc 100644
--- a/src/mainboard/lenovo/t440p/data.vbt
+++ b/src/mainboard/lenovo/t440p/data.vbt
Binary files differ
--
To view, visit https://review.coreboot.org/c/coreboot/+/40723
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: If8669b8de6fa0801e261138651b8b2cf50432a70
Gerrit-Change-Number: 40723
Gerrit-PatchSet: 1
Gerrit-Owner: DaLao <dalao(a)tutanota.com>
Gerrit-MessageType: newchange
11 hours, 39 minutes
- 4
- 17
Change in ...coreboot[master]: autoport: Add support for Haswell-LynxPoint platform
by Iru Cai (vimacs) (Code Review)
Hello Iru Cai,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/30890
to review the following change.
Change subject: autoport: Add support for Haswell-LynxPoint platform
......................................................................
autoport: Add support for Haswell-LynxPoint platform
It can now generate a buildable source for Clevo W650SZ.
TODO:
- Support Lynx Point LP (GPIO registers differ from non-LP)
- Use PCH HD-Audio in azilia instead of the CPU/Northbridge HD-Audio
Change-Id: I4f6e8c97b5122101de2f36bba8ba9f8ddd5b813a
Signed-off-by: Iru Cai <mytbk920423(a)gmail.com>
---
M util/autoport/azalia.go
A util/autoport/haswell.go
A util/autoport/lynxpoint.go
M util/autoport/main.go
4 files changed, 625 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/30890/1
diff --git a/util/autoport/azalia.go b/util/autoport/azalia.go
index c525189..3090dd0 100644
--- a/util/autoport/azalia.go
+++ b/util/autoport/azalia.go
@@ -62,4 +62,9 @@
RegisterPCI(0x8086, 0x1c20, azalia{})
/* C216/ivybridge */
RegisterPCI(0x8086, 0x1e20, azalia{})
+ /* Haswell */
+ RegisterPCI(0x8086, 0x0c0c, azalia{})
+ /* Lynx Point */
+ RegisterPCI(0x8086, 0x8c20, azalia{})
+ RegisterPCI(0x8086, 0x9c20, azalia{})
}
diff --git a/util/autoport/haswell.go b/util/autoport/haswell.go
new file mode 100644
index 0000000..d3c9d9f
--- /dev/null
+++ b/util/autoport/haswell.go
@@ -0,0 +1,119 @@
+package main
+
+type haswellmc struct {
+ variant string
+}
+
+func (i haswellmc) Scan(ctx Context, addr PCIDevData) {
+ inteltool := ctx.InfoSource.GetInteltool()
+
+ /* FIXME:XX Move this somewhere else. */
+ MainboardIncludes = append(MainboardIncludes, "drivers/intel/gma/int15.h")
+ MainboardEnable += (` /* FIXME: fix those values*/
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+`)
+
+ DevTree = DevTreeNode{
+ Chip: "northbridge/intel/haswell",
+ MissingParent: "northbridge",
+ Comment: "FIXME: check gfx.ndid and gfx.did",
+ Registers: map[string]string{
+ "gpu_dp_b_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 2) & 7),
+ "gpu_dp_c_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 10) & 7),
+ "gpu_dp_d_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 18) & 7),
+ "gpu_panel_port_select": FormatInt32((inteltool.IGD[0xc7208] >> 30) & 3),
+ "gpu_panel_power_up_delay": FormatInt32((inteltool.IGD[0xc7208] >> 16) & 0x1fff),
+ "gpu_panel_power_backlight_on_delay": FormatInt32(inteltool.IGD[0xc7208] & 0x1fff),
+ "gpu_panel_power_down_delay": FormatInt32((inteltool.IGD[0xc720c] >> 16) & 0x1fff),
+ "gpu_panel_power_backlight_off_delay": FormatInt32(inteltool.IGD[0xc720c] & 0x1fff),
+ "gpu_panel_power_cycle_delay": FormatInt32(inteltool.IGD[0xc7210] & 0xff),
+ "gpu_cpu_backlight": FormatHex32(inteltool.IGD[0x48254]),
+ "gpu_pch_backlight": FormatHex32((inteltool.IGD[0xc8254] >> 16) * 0x10001),
+ "gpu_ddi_e_connected": FormatBool(((inteltool.IGD[0x64000] >> 4) & 1) == 0),
+ /* FIXME:XX hardcoded. */
+ "gfx.ndid": "3",
+ "gfx.did": "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }",
+ },
+ Children: []DevTreeNode{
+ {
+ Chip: "cpu_cluster",
+ Dev: 0,
+ Children: []DevTreeNode{
+ {
+ Chip: "cpu/intel/haswell",
+ Children: []DevTreeNode{
+ {
+ Chip: "lapic",
+ Dev: 0,
+ },
+ {
+ Chip: "lapic",
+ Dev: 0xacac,
+ Disabled: true,
+ },
+ },
+ Registers: map[string]string{
+ /* FIXME:XX hardcoded. */
+ "c1_acpower": "1",
+ "c2_acpower": "3",
+ "c3_acpower": "5",
+ "c1_battery": "1",
+ "c2_battery": "3",
+ "c3_battery": "5",
+ },
+ },
+ },
+ },
+
+ {
+ Chip: "domain",
+ Dev: 0,
+ PCIController: true,
+ ChildPCIBus: 0,
+ PCISlots: []PCISlot{
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x0, Func: 0}, writeEmpty: true, additionalComment: "Host bridge"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1, Func: 0}, writeEmpty: true, additionalComment: "PCIe Bridge for discrete graphics"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x2, Func: 0}, writeEmpty: true, additionalComment: "Internal graphics"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x3, Func: 0}, writeEmpty: true, additionalComment: "Mini-HD audio"},
+ },
+ },
+ },
+ }
+
+ PutPCIDev(addr, "Host bridge")
+
+ /* FIXME:XX some configs are unsupported. */
+
+ KconfigBool["CPU_INTEL_HASWELL"] = true
+ KconfigBool["NORTHBRIDGE_INTEL_HASWELL"] = true
+ KconfigBool["INTEL_INT15"] = true
+ KconfigBool["HAVE_ACPI_TABLES"] = true
+ KconfigBool["HAVE_ACPI_RESUME"] = true
+
+ KconfigInt["MAX_CPUS"] = 8
+
+ DSDTIncludes = append(DSDTIncludes, DSDTInclude{
+ File: "cpu/intel/common/acpi/cpu.asl",
+ })
+
+ DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{
+ File: "northbridge/intel/haswell/acpi/haswell.asl",
+ }, DSDTInclude{
+ File: "drivers/intel/gma/acpi/default_brightness_levels.asl",
+ })
+}
+
+func init() {
+ RegisterPCI(0x8086, 0x0c00, haswellmc{variant: "Desktop"})
+ RegisterPCI(0x8086, 0x0c04, haswellmc{variant: "Mobile"})
+ RegisterPCI(0x8086, 0x0a04, haswellmc{variant: "ULT"})
+ RegisterPCI(0x8086, 0x0c08, haswellmc{variant: "Server"})
+ for _, id := range []uint16{
+ 0x0402, 0x0412, 0x0422,
+ 0x0406, 0x0416, 0x0426,
+ 0x0d16, 0x0d26, 0x0d36,
+ 0x0a06, 0x0a16, 0x0a26,
+ } {
+ RegisterPCI(0x8086, id, GenericVGA{GenericPCI{Comment: "VGA controller"}})
+ }
+}
diff --git a/util/autoport/lynxpoint.go b/util/autoport/lynxpoint.go
new file mode 100644
index 0000000..df20c3f
--- /dev/null
+++ b/util/autoport/lynxpoint.go
@@ -0,0 +1,495 @@
+package main
+
+import (
+ "fmt"
+ "os"
+)
+
+type lynxpoint struct {
+ variant string
+ node *DevTreeNode
+}
+
+func (b lynxpoint) writeGPIOSet(ctx Context, sb *os.File,
+ val uint32, set uint, partno int, constraint uint32) {
+
+ max := uint(32)
+ if set == 3 {
+ max = 12
+ }
+
+ bits := [6][2]string{
+ {"GPIO_MODE_NATIVE", "GPIO_MODE_GPIO"},
+ {"GPIO_DIR_OUTPUT", "GPIO_DIR_INPUT"},
+ {"GPIO_LEVEL_LOW", "GPIO_LEVEL_HIGH"},
+ {"GPIO_RESET_PWROK", "GPIO_RESET_RSMRST"},
+ {"GPIO_NO_INVERT", "GPIO_INVERT"},
+ {"GPIO_NO_BLINK", "GPIO_BLINK"},
+ }
+
+ for i := uint(0); i < max; i++ {
+ if ((constraint>>i)&1 == 1) {
+ fmt.Fprintf(sb, " .gpio%d = %s,\n",
+ (set-1)*32+i,
+ bits[partno][(val>>i)&1])
+ }
+ }
+}
+
+func (b lynxpoint) GPIO(ctx Context, inteltool InteltoolData) {
+ var constraint uint32
+ gpio := Create(ctx, "gpio.c")
+ defer gpio.Close()
+
+ AddROMStageFile("gpio.c", "")
+
+ Add_gpl(gpio)
+ gpio.WriteString("#include <southbridge/intel/common/gpio.h>\n\n")
+
+ /* TODO: different in LP PCH */
+ addresses := [3][6]int{
+ {0x00, 0x04, 0x0c, 0x60, 0x2c, 0x18},
+ {0x30, 0x34, 0x38, 0x64, -1, -1},
+ {0x40, 0x44, 0x48, 0x68, -1, -1},
+ }
+
+ for set := 1; set <= 3; set++ {
+ for partno, part := range []string{"mode", "direction", "level", "reset", "invert", "blink"} {
+ addr := addresses[set-1][partno]
+ if addr < 0 {
+ continue
+ }
+ fmt.Fprintf(gpio, "static const struct pch_gpio_set%d pch_gpio_set%d_%s = {\n",
+ set, set, part)
+
+ constraint = 0xffffffff
+ switch part {
+ case "direction":
+ /* Ignored on native mode */
+ constraint = inteltool.GPIO[uint16(addresses[set-1][0])]
+ case "level":
+ /* Level doesn't matter for input */
+ constraint = inteltool.GPIO[uint16(addresses[set-1][0])]
+ constraint &^= inteltool.GPIO[uint16(addresses[set-1][1])]
+ case "reset":
+ /* Only show reset */
+ constraint = inteltool.GPIO[uint16(addresses[set-1][3])]
+ case "invert":
+ /* Only on input and only show inverted GPIO */
+ constraint = inteltool.GPIO[uint16(addresses[set-1][0])]
+ constraint &= inteltool.GPIO[uint16(addresses[set-1][1])]
+ constraint &= inteltool.GPIO[uint16(addresses[set-1][4])]
+ case "blink":
+ /* Only on output and only show blinking GPIO */
+ constraint = inteltool.GPIO[uint16(addresses[set-1][0])]
+ constraint &^= inteltool.GPIO[uint16(addresses[set-1][1])]
+ constraint &= inteltool.GPIO[uint16(addresses[set-1][5])]
+ }
+ b.writeGPIOSet(ctx, gpio, inteltool.GPIO[uint16(addr)], uint(set), partno, constraint)
+ gpio.WriteString("};\n\n")
+ }
+ }
+
+ gpio.WriteString(`const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
+`)
+}
+
+func (b lynxpoint) IsPCIeHotplug(ctx Context, port int) bool {
+ portDev, ok := PCIMap[PCIAddr{Bus: 0, Dev: 0x1c, Func: port}]
+ if !ok {
+ return false
+ }
+ return (portDev.ConfigDump[0xdb] & (1 << 6)) != 0
+}
+
+func (b lynxpoint) GetGPIOHeader() string {
+ return "southbridge/intel/lynxpoint/pch.h"
+}
+
+func (b lynxpoint) EnableGPE(in int) {
+ b.node.Registers[fmt.Sprintf("gpi%d_routing", in)] = "2"
+}
+
+func (b lynxpoint) EncodeGPE(in int) int {
+ return in + 0x10
+}
+
+func (b lynxpoint) DecodeGPE(in int) int {
+ return in - 0x10
+}
+
+func (b lynxpoint) NeedRouteGPIOManually() {
+ b.node.Comment += ", FIXME: set gpiX_routing for EC support"
+}
+
+func (b lynxpoint) Scan(ctx Context, addr PCIDevData) {
+
+ SouthBridge = &b
+
+ inteltool := ctx.InfoSource.GetInteltool()
+ b.GPIO(ctx, inteltool)
+
+ KconfigBool["SOUTHBRIDGE_INTEL_LYNXPOINT"] = true
+ if b.variant == "Lynx Point LP" {
+ KconfigBool["INTEL_LYNXPOINT_LP"] = true
+ }
+ KconfigBool["SERIRQ_CONTINUOUS_MODE"] = true
+ KconfigInt["USBDEBUG_HCD_INDEX"] = 2
+ KconfigComment["USBDEBUG_HCD_INDEX"] = "FIXME: check this"
+ dmi := ctx.InfoSource.GetDMI()
+ if dmi.Vendor == "LENOVO" {
+ KconfigInt["DRAM_RESET_GATE_GPIO"] = 10
+ } else {
+ KconfigInt["DRAM_RESET_GATE_GPIO"] = 60
+ }
+ KconfigComment["DRAM_RESET_GATE_GPIO"] = "FIXME: check this"
+
+ /* Not strictly speaking correct. These subsys/subvendor referer to PCI devices.
+ But most systems don't have any of those. But the config needs to be set
+ nevertheless. So set it to southbridge subsys/subvendor. */
+ KconfigHex["MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID"] = uint32(GetLE16(addr.ConfigDump[0x2c:0x2e]))
+ KconfigHex["MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID"] = uint32(GetLE16(addr.ConfigDump[0x2e:0x30]))
+
+ ich9GetFlashSize(ctx)
+
+ DSDTDefines = append(DSDTDefines,
+ DSDTDefine{
+ Key: "BRIGHTNESS_UP",
+ Value: "\\_SB.PCI0.GFX0.INCB",
+ },
+ DSDTDefine{
+ Key: "BRIGHTNESS_DOWN",
+ Value: "\\_SB.PCI0.GFX0.DECB",
+ },
+ DSDTDefine{
+ Key: "ACPI_VIDEO_DEVICE",
+ Value: "\\_SB.PCI0.GFX0",
+ })
+
+ /* SPI init */
+ MainboardIncludes = append(MainboardIncludes, "southbridge/intel/lynxpoint/pch.h")
+
+ cur := DevTreeNode{
+ Chip: "southbridge/intel/lynxpoint",
+ Comment: "Intel Series 8 Lynx Point PCH",
+
+ Registers: map[string]string{
+ "pirqa_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x60]),
+ "pirqb_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x61]),
+ "pirqc_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x62]),
+ "pirqd_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x63]),
+ "pirqe_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x68]),
+ "pirqf_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x69]),
+ "pirqg_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x6a]),
+ "pirqh_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x6b]),
+ "sata_ahci": "1",
+ "gen1_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x84:0x88]),
+ "gen2_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x88:0x8c]),
+ "gen3_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x8c:0x90]),
+ "gen4_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x90:0x94]),
+ "sata_port_map": fmt.Sprintf("0x%x", PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 2}].ConfigDump[0x92]&0x3f),
+ },
+ PCISlots: []PCISlot{
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x14, Func: 0}, writeEmpty: false, additionalComment: "USB 3.0 Controller"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 0}, writeEmpty: true, additionalComment: "Management Engine Interface 1"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 1}, writeEmpty: true, additionalComment: "Management Engine Interface 2"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 2}, writeEmpty: true, additionalComment: "Management Engine IDE-R"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 3}, writeEmpty: true, additionalComment: "Management Engine KT"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x19, Func: 0}, writeEmpty: true, additionalComment: "Intel Gigabit Ethernet"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1a, Func: 0}, writeEmpty: true, additionalComment: "USB2 EHCI #2"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1b, Func: 0}, writeEmpty: true, additionalComment: "High Definition Audio"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 0}, writeEmpty: true, additionalComment: "PCIe Port #1"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 1}, writeEmpty: true, additionalComment: "PCIe Port #2"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 2}, writeEmpty: true, additionalComment: "PCIe Port #3"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 3}, writeEmpty: true, additionalComment: "PCIe Port #4"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 4}, writeEmpty: true, additionalComment: "PCIe Port #5"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 5}, writeEmpty: true, additionalComment: "PCIe Port #6"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 6}, writeEmpty: true, additionalComment: "PCIe Port #7"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 7}, writeEmpty: true, additionalComment: "PCIe Port #8"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1d, Func: 0}, writeEmpty: true, additionalComment: "USB2 EHCI #1"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1e, Func: 0}, writeEmpty: true, additionalComment: "PCI bridge"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 0}, writeEmpty: true, additionalComment: "LPC bridge"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 2}, writeEmpty: true, additionalComment: "SATA Controller 1"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 3}, writeEmpty: true, additionalComment: "SMBus"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 5}, writeEmpty: true, additionalComment: "SATA Controller 2"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 6}, writeEmpty: true, additionalComment: "Thermal"},
+ },
+ }
+
+ b.node = &cur
+
+ PutPCIChip(addr, cur)
+ PutPCIDevParent(addr, "PCI-LPC bridge", "lpc")
+
+ DSDTIncludes = append(DSDTIncludes, DSDTInclude{
+ File: "southbridge/intel/lynxpoint/acpi/platform.asl",
+ })
+ DSDTIncludes = append(DSDTIncludes, DSDTInclude{
+ File: "southbridge/intel/lynxpoint/acpi/globalnvs.asl",
+ Comment: "global NVS and variables",
+ })
+ DSDTIncludes = append(DSDTIncludes, DSDTInclude{
+ File: "southbridge/intel/lynxpoint/acpi/sleepstates.asl",
+ })
+ DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{
+ File: "southbridge/intel/lynxpoint/acpi/pch.asl",
+ })
+
+ sb := Create(ctx, "romstage.c")
+ defer sb.Close()
+ Add_gpl(sb)
+ sb.WriteString(`#include <stdint.h>
+#include <cpu/intel/romstage.h>
+#include <cpu/intel/haswell/haswell.h>
+#include <northbridge/intel/haswell/haswell.h>
+#include <northbridge/intel/haswell/pei_data.h>
+#include <southbridge/intel/common/gpio.h>
+#include <southbridge/intel/lynxpoint/pch.h>
+
+static const struct rcba_config_instruction rcba_config[] = {
+`)
+ RestoreDIRRoute(sb, "D31IR", uint16(inteltool.RCBA[0x3140]))
+ RestoreDIRRoute(sb, "D29IR", uint16(inteltool.RCBA[0x3144]))
+ RestoreDIRRoute(sb, "D28IR", uint16(inteltool.RCBA[0x3146]))
+ RestoreDIRRoute(sb, "D27IR", uint16(inteltool.RCBA[0x3148]))
+ RestoreDIRRoute(sb, "D26IR", uint16(inteltool.RCBA[0x314c]))
+ RestoreDIRRoute(sb, "D25IR", uint16(inteltool.RCBA[0x3150]))
+ RestoreDIRRoute(sb, "D22IR", uint16(inteltool.RCBA[0x315c]))
+ RestoreDIRRoute(sb, "D20IR", uint16(inteltool.RCBA[0x3160]))
+
+ sb.WriteString(`
+ RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS),
+
+ RCBA_END_CONFIG,
+};`)
+
+ sb.WriteString(`
+
+void mainboard_config_superio(void)
+{
+}
+
+void mainboard_romstage_entry(unsigned long bist)
+{
+ struct pei_data pei_data = {
+ .pei_version = PEI_VERSION,
+ .mchbar = (uintptr_t)DEFAULT_MCHBAR,
+ .dmibar = (uintptr_t)DEFAULT_DMIBAR,
+ .epbar = DEFAULT_EPBAR,
+ .pciexbar = DEFAULT_PCIEXBAR,
+ .smbusbar = SMBUS_IO_BASE,
+ .wdbbar = 0x4000000,
+ .wdbsize = 0x1000,
+ .hpet_address = HPET_ADDR,
+ .rcba = (uintptr_t)DEFAULT_RCBA,
+ .pmbase = DEFAULT_PMBASE,
+ .gpiobase = DEFAULT_GPIOBASE,
+ .temp_mmio_base = 0xfed08000,
+ .system_type = 1, /* desktop/server, FIXME: check this */
+ .tseg_size = CONFIG_SMM_TSEG_SIZE,
+ .spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 }, /* FIXME: check this */
+ .ec_present = 0,
+ .dimm_channel0_disabled = 0, /* FIXME: leave channel 0 enabled */
+ .dimm_channel1_disabled = 0, /* FIXME: leave channel 1 enabled */
+ .max_ddr3_freq = 1600,
+ .usb2_ports = {
+ /* Length, Enable, OCn#, Location */
+`)
+
+ pdo1 := PCIMap[PCIAddr{Bus: 0, Dev: 0x1d, Func: 0}].ConfigDump[0x64]
+ ocmap1 := PCIMap[PCIAddr{Bus: 0, Dev: 0x1d, Func: 0}].ConfigDump[0x74:0x78]
+ pdo2 := PCIMap[PCIAddr{Bus: 0, Dev: 0x1a, Func: 0}].ConfigDump[0x64]
+ ocmap2 := PCIMap[PCIAddr{Bus: 0, Dev: 0x1a, Func: 0}].ConfigDump[0x74:0x78]
+
+ for port := uint(0); port < 14; port++ {
+ var port_oc int = -1
+ var port_pos string
+ var port_disable uint8
+
+ if port < 8 {
+ port_disable = (pdo1 >> port) & 1
+ for oc := 0; oc < 4; oc++ {
+ if ((ocmap1[oc] & (1 << port)) != 0) {
+ port_oc = oc
+ break
+ }
+ }
+ } else {
+ port_disable = (pdo2 >> (port - 8)) & 1
+ for oc := 0; oc < 4; oc++ {
+ if ((ocmap2[oc] & (1 << (port - 8))) != 0) {
+ port_oc = oc + 4
+ break
+ }
+ }
+ }
+ if port_disable == 1 {
+ port_pos = "USB_PORT_SKIP"
+ } else {
+ port_pos = "USB_PORT_BACK_PANEL"
+ }
+ if port_oc == -1 {
+ fmt.Fprintf(sb, " { 0x0040, %d, USB_OC_PIN_SKIP, %s },\n",
+ (port_disable ^ 1), port_pos)
+ } else {
+ fmt.Fprintf(sb, " { 0x0040, %d, %d, %s },\n",
+ (port_disable ^ 1), port_oc, port_pos)
+ }
+ }
+
+ sb.WriteString(` },
+ .usb3_ports = {
+`)
+
+ xpdo := PCIMap[PCIAddr{Bus: 0, Dev: 0x14, Func: 0}].ConfigDump[0xe8]
+ u3ocm := PCIMap[PCIAddr{Bus: 0, Dev: 0x14, Func: 0}].ConfigDump[0xc8:0xd0]
+
+ for port := uint(0); port < 6; port++ {
+ var port_oc int = -1
+ port_disable := (xpdo >> port) & 1
+ for oc := 0; oc < 8; oc++ {
+ if (u3ocm[oc] & (1 << port)) != 0 {
+ port_oc = oc
+ break
+ }
+ }
+ if port_oc == -1 {
+ fmt.Fprintf(sb, " { %d, USB_OC_PIN_SKIP },\n",
+ (port_disable ^ 1))
+ } else {
+ fmt.Fprintf(sb, " { %d, %d },\n",
+ (port_disable ^ 1), port_oc)
+ }
+ }
+
+ sb.WriteString(` },
+ };
+
+ struct romstage_params romstage_params = {
+ .pei_data = &pei_data,
+ .gpio_map = &mainboard_gpio_map,
+ .rcba_config = &rcba_config[0],
+ .bist = bist,
+ };
+
+ romstage_common(&romstage_params);
+}`)
+
+ gnvs := Create(ctx, "acpi_tables.c")
+ defer gnvs.Close()
+
+ Add_gpl(gnvs)
+ gnvs.WriteString(`#include <southbridge/intel/lynxpoint/nvs.h>
+
+/* FIXME: check this function. */
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+ /* Disable USB ports in S3 by default */
+ gnvs->s3u0 = 0;
+ gnvs->s3u1 = 0;
+
+ /* Disable USB ports in S5 by default */
+ gnvs->s5u0 = 0;
+ gnvs->s5u1 = 0;
+
+ // the lid is open by default.
+ gnvs->lids = 1;
+
+ gnvs->tcrt = 100;
+ gnvs->tpsv = 90;
+}
+`)
+
+}
+
+func init() {
+ for _, id := range []uint16 {
+ 0x8c41, 0x8c49, 0x8c4b, 0x8c4f,
+ } {
+ RegisterPCI(0x8086, uint16(id), lynxpoint{variant: "Lynx Point Mobile"})
+ }
+
+ for _, id := range []uint16 {
+ 0x8c42, 0x8c44, 0x8c46, 0x8c4a,
+ 0x8c4c, 0x8c4e, 0x8c50, 0x8c5c,
+ } {
+ RegisterPCI(0x8086, uint16(id), lynxpoint{variant: "Lynx Point Desktop"})
+ }
+
+ for _, id := range []uint16 {
+ 0x8c52, 0x8c54, 0x8c56,
+ } {
+ RegisterPCI(0x8086, uint16(id), lynxpoint{variant: "Lynx Point Server"})
+ }
+
+ for _, id := range []uint16 {
+ 0x9c41, 0x9c43, 0x9c45,
+ } {
+ RegisterPCI(0x8086, uint16(id), lynxpoint{variant: "Lynx Point LP"})
+ }
+
+ /* PCIe bridge */
+ for _, id := range []uint16{
+ 0x8c10, 0x8c12, 0x8c14, 0x8c16, 0x8c18, 0x8c1a, 0x8c1c, 0x8c1e,
+ 0x9c10, 0x9c12, 0x9c14, 0x9c16, 0x9c18, 0x9c1a,
+ } {
+ RegisterPCI(0x8086, id, GenericPCI{})
+ }
+
+ /* SMBus controller */
+ RegisterPCI(0x8086, 0x1c22, GenericPCI{MissingParent: "smbus"})
+ RegisterPCI(0x8086, 0x1e22, GenericPCI{MissingParent: "smbus"})
+ RegisterPCI(0x8086, 0x8c22, GenericPCI{MissingParent: "smbus"})
+ RegisterPCI(0x8086, 0x9c22, GenericPCI{MissingParent: "smbus"})
+
+ /* SATA */
+ for _, id := range []uint16{
+ 0x8c00, 0x8c02, 0x8c04, 0x8c06, 0x8c08, 0x8c0e,
+ 0x8c01, 0x8c03, 0x8c05, 0x8c07, 0x8c09, 0x8c0f,
+ 0x9c03, 0x9c05, 0x9c07, 0x9c0f,
+ } {
+ RegisterPCI(0x8086, id, GenericPCI{})
+ }
+
+ /* EHCI */
+ for _, id := range []uint16{
+ 0x9c26, 0x8c26, 0x8c2d,
+ } {
+ RegisterPCI(0x8086, id, GenericPCI{})
+ }
+
+ /* XHCI */
+ RegisterPCI(0x8086, 0x8c31, GenericPCI{})
+ RegisterPCI(0x8086, 0x9c31, GenericPCI{})
+
+ /* ME and children */
+ for _, id := range []uint16{
+ 0x8c3a, 0x8c3b,
+ } {
+ RegisterPCI(0x8086, id, GenericPCI{})
+ }
+
+ /* Ethernet */
+ RegisterPCI(0x8086, 0x8c33, GenericPCI{})
+}
diff --git a/util/autoport/main.go b/util/autoport/main.go
index 05a829b..c1920a7 100644
--- a/util/autoport/main.go
+++ b/util/autoport/main.go
@@ -236,6 +236,12 @@
pcidev.ConfigDump[addr])
}
+func RestoreDIRRoute(f *os.File, regname string, val uint16) {
+ fmt.Fprintf(f, " RCBA_SET_REG_16(%s, DIR_ROUTE(PIRQ%c, PIRQ%c, PIRQ%c, PIRQ%c)),\n",
+ regname, 'A' + (val & 7), 'A' + ((val >> 4) & 7),
+ 'A' + ((val >> 8) & 7), 'A' + ((val >> 12) & 7))
+}
+
func RestorePCI32Simple(f *os.File, pcidev PCIDevData, addr uint16) {
fmt.Fprintf(f, " pci_write_config32(PCI_DEV(%d, 0x%02x, %d), 0x%02x, 0x%02x%02x%02x%02x);\n",
pcidev.Bus, pcidev.Dev, pcidev.Func, addr,
--
To view, visit https://review.coreboot.org/c/coreboot/+/30890
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I4f6e8c97b5122101de2f36bba8ba9f8ddd5b813a
Gerrit-Change-Number: 30890
Gerrit-PatchSet: 1
Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com>
Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com>
Gerrit-MessageType: newchange
1 day, 1 hour
- 8
- 48
Change in coreboot[master]: cbfstool: Support CONFIG_CBFS_VERIFICATION and master hash anchor
by Julius Werner (Code Review)
Hello Patrick Georgi, Aaron Durbin,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/41121
to review the following change.
Change subject: cbfstool: Support CONFIG_CBFS_VERIFICATION and master hash anchor
......................................................................
cbfstool: Support CONFIG_CBFS_VERIFICATION and master hash anchor
This patch adds support for the new CONFIG_CBFS_VERIFICATION feature to
cbfstool. When CBFS verification is enabled, cbfstool must automatically
add a hash attribute to every CBFS file it adds (with a handful of
exceptions like bootblock and "header" pseudofiles that are never read
by coreboot code itself). It must also automatically update the master
hash that is embedded in the bootblock code. It will automatically find
the master hash by scanning the bootblock for its magic number and use
its presence to auto-detect whether CBFS verification is enabled for an
image (and which hash algorithm to use).
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Change-Id: I61a84add8654f60c683ef213b844a11b145a5cb7
---
M util/cbfstool/Makefile.inc
A util/cbfstool/cbfs_glue.h
M util/cbfstool/cbfs_sections.h
M util/cbfstool/cbfstool.c
4 files changed, 243 insertions(+), 29 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/41121/1
diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc
index 000ceb2..e98b52e 100644
--- a/util/cbfstool/Makefile.inc
+++ b/util/cbfstool/Makefile.inc
@@ -23,10 +23,8 @@
cbfsobj += xdr.o
cbfsobj += partitioned_file.o
# COMMONLIB
-cbfsobj += cbfs.o
+cbfsobj += cbfs_private.o
cbfsobj += fsp_relocate.o
-cbfsobj += mem_pool.o
-cbfsobj += region.o
# FMAP
cbfsobj += fmap.o
cbfsobj += kv_pair.o
@@ -72,10 +70,6 @@
ifitobj += cbfs-mkstage.o
ifitobj += cbfs-mkpayload.o
ifitobj += rmodule.o
-# COMMONLIB
-ifitobj += cbfs.o
-ifitobj += mem_pool.o
-ifitobj += region.o
# FMAP
ifitobj += fmap.o
ifitobj += kv_pair.o
@@ -101,6 +95,7 @@
TOOLCPPFLAGS ?= -D_DEFAULT_SOURCE # memccpy() from string.h
TOOLCPPFLAGS += -D_BSD_SOURCE -D_SVID_SOURCE # _DEFAULT_SOURCE for older glibc
TOOLCPPFLAGS += -D_XOPEN_SOURCE=700 # strdup() from string.h
+TOOLCPPFLAGS += -D_GNU_SOURCE # memmem() from string.h
TOOLCPPFLAGS += -I$(top)/util/cbfstool/flashmap
TOOLCPPFLAGS += -I$(top)/util/cbfstool
TOOLCPPFLAGS += -I$(objutil)/cbfstool
@@ -207,9 +202,7 @@
# Tolerate lzma sdk warnings
$(objutil)/cbfstool/LzmaEnc.o: TOOLCFLAGS += -Wno-sign-compare -Wno-cast-qual
# Tolerate commonlib warnings
-$(objutil)/cbfstool/region.o: TOOLCFLAGS += -Wno-sign-compare -Wno-cast-qual
-$(objutil)/cbfstool/cbfs.o: TOOLCFLAGS += -Wno-sign-compare -Wno-cast-qual
-$(objutil)/cbfstool/mem_pool.o: TOOLCFLAGS += -Wno-sign-compare -Wno-cast-qual
+$(objutil)/cbfstool/cbfs_private.o: TOOLCFLAGS += -Wno-sign-compare
# Tolerate lz4 warnings
$(objutil)/cbfstool/lz4.o: TOOLCFLAGS += -Wno-missing-prototypes
$(objutil)/cbfstool/lz4_wrapper.o: TOOLCFLAGS += -Wno-attributes
diff --git a/util/cbfstool/cbfs_glue.h b/util/cbfstool/cbfs_glue.h
new file mode 100644
index 0000000..11786be
--- /dev/null
+++ b/util/cbfstool/cbfs_glue.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _CBFS_GLUE_H_
+#define _CBFS_GLUE_H_
+
+#include "cbfs_image.h"
+
+#define CBFS_ENABLE_HASHING 1
+
+typedef const struct cbfs_image *cbfs_dev_t;
+
+static inline ssize_t cbfs_dev_read(cbfs_dev_t dev, void *buffer, size_t offset, size_t size)
+{
+ if (buffer_size(&dev->buffer) < offset ||
+ buffer_size(&dev->buffer) - offset < size)
+ return -1;
+
+ memcpy(buffer, buffer_get(&dev->buffer) + offset, size);
+ return size;
+}
+
+static inline size_t cbfs_dev_size(cbfs_dev_t dev)
+{
+ return buffer_size(&dev->buffer);
+}
+
+#endif /* _CBFS_GLUE_H_ */
diff --git a/util/cbfstool/cbfs_sections.h b/util/cbfstool/cbfs_sections.h
index 3526f8d..d444cce 100644
--- a/util/cbfstool/cbfs_sections.h
+++ b/util/cbfstool/cbfs_sections.h
@@ -22,6 +22,7 @@
#define SECTION_NAME_FMAP "FMAP"
#define SECTION_NAME_PRIMARY_CBFS "COREBOOT"
+#define SECTION_NAME_BOOTBLOCK "BOOTBLOCK"
#define SECTION_ANNOTATION_CBFS "CBFS"
diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c
index 6015603..bc07b6f 100644
--- a/util/cbfstool/cbfstool.c
+++ b/util/cbfstool/cbfstool.c
@@ -31,13 +31,13 @@
#include "cbfs_sections.h"
#include "elfparsing.h"
#include "partitioned_file.h"
+#include <commonlib/bsd/cbfs_private.h>
+#include <commonlib/bsd/master_hash.h>
#include <commonlib/fsp.h>
#include <commonlib/endian.h>
#include <commonlib/helpers.h>
#include <vboot_host.h>
-#define SECTION_WITH_FIT_TABLE "BOOTBLOCK"
-
struct command {
const char *name;
const char *optstring;
@@ -104,6 +104,144 @@
.u64val = -1,
};
+struct mh_cache {
+ const char *region;
+ size_t offset;
+ struct vb2_hash cbfs_hash;
+};
+
+static struct mh_cache *get_mh_cache(void)
+{
+ static struct mh_cache mhc;
+
+ if (mhc.region)
+ return &mhc;
+
+ const struct fmap *fmap = partitioned_file_get_fmap(param.image_file);
+ if (!fmap)
+ goto no_master_hash;
+
+ size_t offset, size;
+ struct buffer buffer;
+ if (fmap_find_area(fmap, SECTION_NAME_BOOTBLOCK)) {
+ if (!partitioned_file_read_region(&buffer, param.image_file,
+ SECTION_NAME_BOOTBLOCK))
+ goto no_master_hash;
+ mhc.region = SECTION_NAME_BOOTBLOCK;
+ offset = 0;
+ size = buffer.size;
+ } else {
+ struct cbfs_image cbfs;
+ struct cbfs_file *bootblock;
+ if (!partitioned_file_read_region(&buffer, param.image_file,
+ SECTION_NAME_PRIMARY_CBFS))
+ goto no_master_hash;
+ mhc.region = SECTION_NAME_PRIMARY_CBFS;
+ if (cbfs_image_from_buffer(&cbfs, &buffer, param.headeroffset))
+ goto no_master_hash;
+ bootblock = cbfs_get_entry(&cbfs, "bootblock");
+ if (!bootblock || ntohl(bootblock->type) != CBFS_TYPE_BOOTBLOCK)
+ goto no_master_hash;
+ offset = (void *)bootblock + ntohl(bootblock->offset) -
+ buffer_get(&cbfs.buffer);
+ size = ntohl(bootblock->len);
+ }
+
+ struct master_hash_anchor *anchor = memmem(buffer_get(&buffer) + offset,
+ size, MASTER_HASH_ANCHOR_MAGIC, sizeof(anchor->magic));
+ if (anchor) {
+ if (!vb2_digest_size(anchor->cbfs_hash.algo)) {
+ ERROR("Unknown CBFS master hash type: %d\n",
+ anchor->cbfs_hash.algo);
+ goto no_master_hash;
+ }
+ mhc.cbfs_hash = anchor->cbfs_hash;
+ mhc.offset = (void *)anchor - buffer_get(&buffer);
+ return &mhc;
+ }
+
+no_master_hash:
+ mhc.cbfs_hash.algo = VB2_HASH_INVALID;
+ mhc.region = (void *)-1;
+ return &mhc;
+}
+
+static void update_and_info(const char *name, void *dst, void *src, size_t size)
+{
+ if (!memcmp(dst, src, size))
+ return;
+ char *src_str = bintohex(src, size);
+ char *dst_str = bintohex(dst, size);
+ INFO("Updating %s from %s to %s\n", name, dst_str, src_str);
+ memcpy(dst, src, size);
+ free(src_str);
+ free(dst_str);
+}
+
+static int update_anchor(struct mh_cache *mhc, uint8_t *fmap_hash)
+{
+ struct buffer buffer;
+ if (!partitioned_file_read_region(&buffer, param.image_file,
+ mhc->region))
+ return -1;
+ struct master_hash_anchor *anchor = buffer_get(&buffer) + mhc->offset;
+ if (memcmp(anchor->magic, MASTER_HASH_ANCHOR_MAGIC,
+ sizeof(anchor->magic)) ||
+ anchor->cbfs_hash.algo != mhc->cbfs_hash.algo) {
+ ERROR("Master hash anchor no longer where it used to be!\n");
+ return -1;
+ }
+ update_and_info("CBFS master hash", anchor->cbfs_hash.raw,
+ mhc->cbfs_hash.raw, vb2_digest_size(anchor->cbfs_hash.algo));
+ if (fmap_hash) {
+ update_and_info("FMAP hash",
+ master_hash_anchor_fmap_hash(anchor), fmap_hash,
+ vb2_digest_size(anchor->cbfs_hash.algo));
+ }
+ if (!partitioned_file_write_region(param.image_file, &buffer))
+ return -1;
+ return 0;
+
+}
+
+static int maybe_update_master_hash(struct cbfs_image *cbfs)
+{
+ if (strcmp(param.region_name, SECTION_NAME_PRIMARY_CBFS))
+ return 0; /* Master hash only embedded in primary CBFS. */
+
+ struct mh_cache *mhc = get_mh_cache();
+ if (mhc->cbfs_hash.algo == VB2_HASH_INVALID)
+ return 0;
+
+ cb_err_t err = cbfs_walk(cbfs, NULL, NULL, &mhc->cbfs_hash,
+ CBFS_WALK_WRITEBACK_HASH);
+ if (err != CB_CBFS_NOT_FOUND) {
+ ERROR("Unexpected cbfs_walk() error %d\n", err);
+ return -1;
+ }
+
+ return update_anchor(mhc, NULL);
+}
+
+static int maybe_update_fmap_hash(void)
+{
+ if (strcmp(param.region_name, SECTION_NAME_BOOTBLOCK) &&
+ strcmp(param.region_name, SECTION_NAME_FMAP) &&
+ param.type != CBFS_TYPE_BOOTBLOCK)
+ return 0; /* FMAP and bootblock didn't change. */
+
+ struct mh_cache *mhc = get_mh_cache();
+ if (mhc->cbfs_hash.algo == VB2_HASH_INVALID)
+ return 0;
+
+ uint8_t fmap_hash[VB2_MAX_DIGEST_SIZE];
+ const struct fmap *fmap = partitioned_file_get_fmap(param.image_file);
+ if (!fmap || vb2_digest_buffer((const void *)fmap, fmap_size(fmap),
+ mhc->cbfs_hash.algo, fmap_hash, sizeof(fmap_hash)))
+ return -1;
+ return update_anchor(mhc, fmap_hash);
+}
+
static bool region_is_flashmap(const char *region)
{
return partitioned_file_region_check_magic(param.image_file, region,
@@ -253,13 +391,21 @@
header = cbfs_create_file_header(CBFS_TYPE_RAW,
buffer.size, name);
+
+ enum vb2_hash_algorithm algo = get_mh_cache()->cbfs_hash.algo;
+ if (algo != VB2_HASH_INVALID)
+ if (cbfs_add_file_hash(header, &buffer, algo)) {
+ ERROR("couldn't add hash for '%s'\n", name);
+ goto done;
+ }
+
if (cbfs_add_entry(&image, &buffer, offset, header, 0) != 0) {
ERROR("Failed to add %llu into ROM image as '%s'.\n",
(long long unsigned)u64val, name);
goto done;
}
- ret = 0;
+ ret = maybe_update_master_hash(&image);
done:
free(header);
@@ -366,6 +512,7 @@
h->offset = htonl(offset);
h->architecture = htonl(CBFS_ARCHITECTURE_UNKNOWN);
+ /* Never add a hash attribute to the master header. */
header = cbfs_create_file_header(CBFS_TYPE_CBFSHEADER,
buffer_size(&buffer), name);
if (cbfs_add_entry(&image, &buffer, 0, header, 0) != 0) {
@@ -396,7 +543,7 @@
return 1;
}
- ret = 0;
+ ret = maybe_update_master_hash(&image);
done:
free(header);
@@ -497,18 +644,32 @@
if (convert && convert(&buffer, &offset, header) != 0) {
ERROR("Failed to parse file '%s'.\n", filename);
- buffer_delete(&buffer);
- return 1;
+ goto error;
}
- if (param.hash != VB2_HASH_INVALID)
- if (cbfs_add_file_hash(header, &buffer, param.hash) == -1) {
- ERROR("couldn't add hash for '%s'\n", name);
- free(header);
- buffer_delete(&buffer);
- return 1;
+ /* Bootblock and CBFS header should never have file hashes. When adding
+ the bootblock it is important that we *don't* look up the master hash
+ yet (before it is added) or we'll cache an outdated result. */
+ if (type != CBFS_TYPE_BOOTBLOCK && type != CBFS_TYPE_CBFSHEADER) {
+ enum vb2_hash_algorithm mh_algo = get_mh_cache()->cbfs_hash.algo;
+ if (mh_algo != VB2_HASH_INVALID && param.hash != mh_algo) {
+ if (param.hash == VB2_HASH_INVALID) {
+ param.hash = mh_algo;
+ } else {
+ ERROR("Cannot specify hash %s that's different from master hash algorithm %s\n",
+ vb2_get_hash_algorithm_name(param.hash),
+ vb2_get_hash_algorithm_name(mh_algo));
+ goto error;
+ }
}
+ if (param.hash != VB2_HASH_INVALID &&
+ cbfs_add_file_hash(header, &buffer, param.hash) == -1) {
+ ERROR("couldn't add hash for '%s'\n", name);
+ goto error;
+ }
+ }
+
if (param.autogen_attr) {
/* Add position attribute if assigned */
if (param.baseaddress_assigned || param.stage_xip) {
@@ -573,14 +734,18 @@
-offset);
if (cbfs_add_entry(&image, &buffer, offset, header, len_align) != 0) {
ERROR("Failed to add '%s' into ROM image.\n", filename);
- free(header);
- buffer_delete(&buffer);
- return 1;
+ goto error;
}
free(header);
buffer_delete(&buffer);
- return 0;
+
+ return maybe_update_master_hash(&image) || maybe_update_fmap_hash();
+
+error:
+ free(header);
+ buffer_delete(&buffer);
+ return 1;
}
static int cbfstool_convert_raw(struct buffer *buffer,
@@ -925,7 +1090,7 @@
return 1;
}
- return 0;
+ return maybe_update_master_hash(&image);
}
static int cbfs_create(void)
@@ -1096,6 +1261,33 @@
cbfs_print_directory(&image);
}
+ if (verbose) {
+ struct mh_cache *mhc = get_mh_cache();
+ if (mhc->cbfs_hash.algo == VB2_HASH_INVALID)
+ return 0;
+
+ struct vb2_hash real_hash = { .algo = mhc->cbfs_hash.algo };
+ cb_err_t err = cbfs_walk(&image, NULL, NULL, &real_hash,
+ CBFS_WALK_WRITEBACK_HASH);
+ if (err != CB_CBFS_NOT_FOUND) {
+ ERROR("Unexpected cbfs_walk() error %d\n", err);
+ return 1;
+ }
+ char *hash_str = bintohex(real_hash.raw,
+ vb2_digest_size(real_hash.algo));
+ printf("[MASTER HASH]\t%s:%s",
+ vb2_get_hash_algorithm_name(real_hash.algo), hash_str);
+ if (!strcmp(param.region_name, SECTION_NAME_PRIMARY_CBFS)) {
+ if (!memcmp(mhc->cbfs_hash.raw, real_hash.raw,
+ vb2_digest_size(real_hash.algo)))
+ printf(":valid");
+ else
+ printf(":invalid");
+ }
+ printf("\n");
+ free(hash_str);
+ }
+
return 0;
}
@@ -1194,7 +1386,8 @@
memcpy(param.image_region->data + offset, new_content.data,
new_content.size);
buffer_delete(&new_content);
- return 0;
+
+ return maybe_update_fmap_hash();
}
static int cbfs_read(void)
@@ -1454,7 +1647,7 @@
"Find a place for a file of that size\n"
" layout [-w] "
"List mutable (or, with -w, readable) image regions\n"
- " print [-r image,regions] "
+ " print [-r image,regions] [-k] "
"Show the contents of the ROM\n"
" extract [-r image,regions] [-m ARCH] -n NAME -f FILE [-U] "
"Extracts a file from ROM\n"
--
To view, visit https://review.coreboot.org/c/coreboot/+/41121
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I61a84add8654f60c683ef213b844a11b145a5cb7
Gerrit-Change-Number: 41121
Gerrit-PatchSet: 1
Gerrit-Owner: Julius Werner <jwerner(a)chromium.org>
Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-MessageType: newchange
2 days
- 5
- 36
Change in coreboot[master]: soc/intel/tigerlake: Add code for early tcss
by Brandon Breitenstein (Code Review)
Brandon Breitenstein has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42079 )
Change subject: soc/intel/tigerlake: Add code for early tcss
......................................................................
soc/intel/tigerlake: Add code for early tcss
In order for USB Type-C to be detected prior to loading Kernel
PMC IPC driver is needed to communicate with PMC in order to
correctly set the USB Mux settings. This patch is adding in
support for early detection of both USB and Display Port.
BUG=b:141608957
BRANCH=NONE
TEST: built and booted TGL U RVP
Change-Id: I58e66f21210d565fb8145d140d2fc7febecdd21a
Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com>
---
M src/soc/intel/tigerlake/Kconfig
M src/soc/intel/tigerlake/Makefile.inc
M src/soc/intel/tigerlake/chip.c
A src/soc/intel/tigerlake/early_tcss.c
A src/soc/intel/tigerlake/include/soc/early_tcss.h
5 files changed, 266 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/42079/1
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index fbf56b4..55c06b1 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -208,4 +208,10 @@
config PRERAM_CBMEM_CONSOLE_SIZE
hex
default 0xe00
+
+config EARLY_TCSS
+ bool "Enable early TCSS"
+ help
+ Enable devices to be detected over Type-C ports during boot.
+
endif
diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc
index c4f71c7..5e60114 100644
--- a/src/soc/intel/tigerlake/Makefile.inc
+++ b/src/soc/intel/tigerlake/Makefile.inc
@@ -31,6 +31,7 @@
ramstage-y += acpi.c
ramstage-y += chip.c
ramstage-y += cpu.c
+ramstage-$(CONFIG_EARLY_TCSS) += early_tcss.c
ramstage-y += elog.c
ramstage-y += espi.c
ramstage-y += finalize.c
diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c
index 00db2a4..3da5d9a 100644
--- a/src/soc/intel/tigerlake/chip.c
+++ b/src/soc/intel/tigerlake/chip.c
@@ -10,6 +10,7 @@
#include <intelblocks/itss.h>
#include <intelblocks/xdci.h>
#include <romstage_handoff.h>
+#include <soc/early_tcss.h>
#include <soc/intel/common/vbt.h>
#include <soc/itss.h>
#include <soc/pci_devs.h>
@@ -129,6 +130,10 @@
* default policy that doesn't honor boards' requirements. */
itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
+ /* Check for early TCSS and connect devices */
+ if (CONFIG(EARLY_TCSS))
+ early_tcss_enable();
+
/* Perform silicon specific init. */
fsp_silicon_init(romstage_handoff_is_resume());
diff --git a/src/soc/intel/tigerlake/early_tcss.c b/src/soc/intel/tigerlake/early_tcss.c
new file mode 100644
index 0000000..942d490
--- /dev/null
+++ b/src/soc/intel/tigerlake/early_tcss.c
@@ -0,0 +1,206 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2020 The coreboot project Authors.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include <bootstate.h>
+#include <console/console.h>
+#include <device/pci.h>
+#include <ec/google/chromeec/ec.h>
+#include <intelblocks/pmclib.h>
+#include <soc/early_tcss.h>
+#include <soc/pci_devs.h>
+#include <stdlib.h>
+
+/* send the ipc_command */
+static int send_ipc_command(uint32_t cmd, uint8_t *tcss_req, int req_size,
+ struct pmc_ipc_buffer *rbuf)
+{
+ struct pmc_ipc_buffer *wbuf = malloc(sizeof(*tcss_req));
+
+ /* copy the tcss_req into a buffer for ipc command */
+ memcpy(wbuf, tcss_req, req_size);
+
+ return pmc_send_ipc_cmd(cmd, wbuf, rbuf);
+}
+
+static int send_pmc_connect_request(struct tcss_mux mux_data,
+ struct pmc_ipc_buffer *rbuf)
+{
+ union pmc_ipc_cmd tcss_cmd = { 0 };
+ uint8_t tcss_req[PMC_IPC_CONN_REQ_SIZE] = { 0 };
+
+ tcss_cmd.cmd = PMC_IPC_USBC_CMD_ID;
+ tcss_cmd.subcmd = PMC_IPC_USBC_SUBCMD_ID;
+
+ tcss_req[0] = PMC_IPC_TCSS_CONN_REQ_RES | /* Usage */
+ mux_data.usb3_port << 4;
+ tcss_req[1] = mux_data.usb2_port |
+ mux_data.ufp << 4 | /* 1=UFP/0=DFP */
+ mux_data.polarity << 5 | /* ORI-HSL */
+ mux_data.polarity << 6 | /* ORI-SBU */
+ mux_data.acc << 7;
+ printk(BIOS_DEBUG, "tcss_req[0]-> 0x%x\n"
+ "tcss_req[1]-> 0x%x\n\t", tcss_req[0], tcss_req[1]);
+
+ tcss_cmd.len = PMC_IPC_CONN_REQ_SIZE;
+
+ return send_ipc_command(tcss_cmd.cmd_reg, tcss_req, PMC_IPC_CONN_REQ_SIZE, rbuf);
+}
+
+static int send_pmc_safe_mode_request(struct tcss_mux mux_data,
+ struct pmc_ipc_buffer *rbuf)
+{
+ union pmc_ipc_cmd tcss_cmd = { 0 };
+ uint8_t tcss_req[PMC_IPC_SAFE_REQ_SIZE] = { 0 };
+
+ tcss_cmd.cmd = PMC_IPC_USBC_CMD_ID;
+ tcss_cmd.subcmd = PMC_IPC_USBC_SUBCMD_ID;
+
+ tcss_req[0] = PMC_IPC_TCSS_SAFE_MODE_REQ_RES |
+ mux_data.usb3_port << 4;
+ printk(BIOS_DEBUG, "tcss_req[0]-> 0x%x\n", tcss_req[0]);
+
+ tcss_cmd.cmd.len = PMC_IPC_SAFE_REQ_SIZE;
+
+ return send_ipc_command(tcss_cmd.cmd_reg, tcss_req, PMC_IPC_SAFE_REQ_SIZE, rbuf);
+}
+
+static int send_pmc_alt_mode_request(struct tcss_mux mux_data,
+ struct pmc_ipc_buffer *rbuf)
+{
+ union pmc_ipc_cmd tcss_cmd = { 0 };
+ uint8_t tcss_req[PMC_IPC_ALT_REQ_SIZE] = { 0 };
+
+ tcss_cmd.cmd = PMC_IPC_USBC_CMD_ID;
+ tcss_cmd.subcmd = PMC_IPC_USBC_SUBCMD_ID;
+
+ tcss_req[0] = PMC_IPC_TCSS_ALTMODE_REQ_RES | mux_data.usb3_port << 4;
+ tcss_req[1] |= PMC_IPC_DP_MODE;
+
+ tcss_req[4] = mux_data.polarity << 1 |
+ mux_data.cable << 2 |
+ mux_data.ufp << 3 |
+ mux_data.polarity << 4 |
+ mux_data.polarity << 5;
+
+ if (mux_data.dp_mode <= MODE_DP_PIN_F) {
+ switch (mux_data.dp_mode) {
+ case MODE_DP_PIN_A:
+ tcss_req[5] = 0;
+ break;
+ case MODE_DP_PIN_B:
+ tcss_req[5] = 1;
+ break;
+ case MODE_DP_PIN_C:
+ tcss_req[5] = 2;
+ break;
+ case MODE_DP_PIN_D:
+ tcss_req[5] = 3;
+ break;
+ case MODE_DP_PIN_E:
+ tcss_req[5] = 4;
+ break;
+ case MODE_DP_PIN_F:
+ tcss_req[5] = 5;
+ break;
+ }
+ }
+
+ tcss_req[5] |= mux_data.hpd_lvl << 6;
+ printk(BIOS_DEBUG, "tcss_req[0]-> 0x%x\n"
+ "tcss_req[1]-> 0x%x\n"
+ "tcss_req[4]-> 0x%x\n"
+ "tcss_req[5]-> 0x%x\n\t",
+ tcss_req[0], tcss_req[1], tcss_req[4], tcss_req[5]);
+
+ tcss_cmd.len = PMC_IPC_ALT_REQ_SIZE;
+
+ return send_ipc_command(tcss_cmd.cmd_reg, tcss_req, PMC_IPC_ALT_REQ_SIZE, rbuf);
+}
+
+static void update_tcss_mux(int port, struct tcss_mux mux_data)
+{
+ struct pmc_ipc_buffer *rbuf = malloc(sizeof(*rbuf));
+ int ret = 0;
+
+ /* Check if the mux has a USB device */
+ if (mux_data.usb) {
+ ret = send_pmc_connect_request(mux_data, rbuf);
+ if (ret) {
+ printk(BIOS_ERR, "Port %d connect request failed\n", port);
+ return;
+ }
+ }
+
+ /* check if mux has a DP device */
+ if (mux_data.dp) {
+
+ if (!mux_data.usb) {
+ ret = send_pmc_connect_request(mux_data, rbuf);
+ if (ret) {
+ printk(BIOS_ERR, "Port %d connect request failed\n", port);
+ return;
+ }
+ }
+ ret = send_pmc_safe_mode_request(mux_data, rbuf);
+ if (ret) {
+ printk(BIOS_ERR, "Port %d safe mode request failed\n", port);
+ return;
+ }
+
+ ret = send_pmc_alt_mode_request(mux_data, rbuf);
+ }
+
+ if (ret)
+ printk(BIOS_ERR, "Port %d mux set failed with error %d\n", port, ret);
+}
+
+void early_tcss_enable(void)
+{
+ uint8_t num_ports;
+ int ret, i;
+
+ ret = google_chromeec_get_num_pd_ports(&num_ports);
+ if (ret < 0)
+ return;
+
+ for (i = 0; i < num_ports; i++) {
+ uint8_t port_map, mux_flags;
+ struct tcss_mux mux_data;
+
+ ret = google_chromeec_usb_get_pd_mux_info(i, &mux_flags);
+ if (ret < 0)
+ continue;
+
+ ret = google_chromeec_pd_get_port_info(i, &port_map);
+ if (ret < 0)
+ continue;
+
+ ret = google_chromeec_usb_pd_control(i, &mux_data.ufp, &mux_data.acc,
+ &mux_data.dp_mode);
+ if (ret < 0)
+ continue;
+
+ mux_data.usb = !!(mux_flags & USB_PD_CTRL_USB_ENABLED);
+ mux_data.dp = !!(mux_flags & USB_PD_CTRL_DP_ENABLED);
+ mux_data.cable = !!(mux_flags & USB_PD_MUX_TBT_ACTIVE_CABLE);
+ mux_data.polarity = !!(mux_flags & USB_PD_CTRL_POLARITY_INVERTED);
+ mux_data.hpd_irq = !!(mux_flags & USB_PD_CTRL_HPD_IRQ);
+ mux_data.hpd_lvl = !!(mux_flags & USB_PD_CTRL_HPD_LVL);
+ mux_data.usb2_port = port_map & 0x0F;
+ mux_data.usb3_port = (port_map & 0xF0) >> 4;
+
+ printk(BIOS_DEBUG, "Port %d mux=0x%x\n"
+ "USB2 port = %x\n"
+ "USB3 port = %x\n"
+ "ufp = %d dbg_acc=%d\n",
+ i, (unsigned int)mux_flags, mux_data.usb2_port,
+ mux_data.usb3_port, mux_data.ufp, mux_data.acc);
+
+ update_tcss_mux(i, mux_data);
+ }
+}
diff --git a/src/soc/intel/tigerlake/include/soc/early_tcss.h b/src/soc/intel/tigerlake/include/soc/early_tcss.h
new file mode 100644
index 0000000..29b7cdd
--- /dev/null
+++ b/src/soc/intel/tigerlake/include/soc/early_tcss.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* PMC IPC related offsets and commands */
+#define PMC_IPC_USBC_CMD_ID 0xA7
+#define PMC_IPC_USBC_SUBCMD_ID 0x0
+#define PMC_IPC_CMD 0x0
+#define PMC_IPC_TCSS_CONN_REQ_RES 0x0
+#define PMC_IPC_TCSS_SAFE_MODE_REQ_RES 0x2
+#define PMC_IPC_TCSS_ALTMODE_REQ_RES 0x3
+#define PMC_IPC_CONN_REQ_SIZE 2
+#define PMC_IPC_ALT_REQ_SIZE 8
+#define PMC_IPC_SAFE_REQ_SIZE 1
+#define PMC_IPC_DP_MODE BIT(4)
+
+/* connection modes for pmc */
+enum pmc_ipc_conn_mode {
+ PMC_IPC_TCSS_DISCONNECT_MODE,
+ PMC_IPC_TCSS_USB_MODE,
+ PMC_IPC_TCSS_ALTERNATE_MODE,
+ PMC_IPC_TCSS_SAFE_MODE,
+ PMC_IPC_TCSS_HPD_MODE,
+ PMC_IPC_TCSS_TOTAL_MODES,
+};
+
+/* DP Mode pin definitions */
+#define MODE_DP_PIN_A BIT(0)
+#define MODE_DP_PIN_B BIT(1)
+#define MODE_DP_PIN_C BIT(2)
+#define MODE_DP_PIN_D BIT(3)
+#define MODE_DP_PIN_E BIT(4)
+#define MODE_DP_PIN_F BIT(5)
+
+/* struct to hold all tcss_mux related variables */
+struct tcss_mux {
+ bool dp; /* DP connected */
+ bool usb; /* USB connected */
+ bool cable; /* Activ/Passive Cable */
+ bool polarity; /* polarity of connected device */
+ bool hpd_lvl; /* HPD Level assert */
+ bool hpd_irq; /* HPD IRQ assert */
+ bool ufp;
+ bool acc;
+ uint8_t dp_mode; /* DP Operation Mode */
+ uint8_t usb3_port; /* USB2 Port Number */
+ uint8_t usb2_port; /* USB3 Port Number */
+};
+
+void early_tcss_enable(void);
--
To view, visit https://review.coreboot.org/c/coreboot/+/42079
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I58e66f21210d565fb8145d140d2fc7febecdd21a
Gerrit-Change-Number: 42079
Gerrit-PatchSet: 1
Gerrit-Owner: Brandon Breitenstein <brandon.breitenstein(a)intel.com>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-MessageType: newchange
2 days, 3 hours
- 7
- 64
Change in coreboot[master]: [WIP] AGESA,binaryPI boards: Drop invalid MP table files
by Kyösti Mälkki (Code Review)
Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38313 )
Change subject: [WIP] AGESA,binaryPI boards: Drop invalid MP table files
......................................................................
[WIP] AGESA,binaryPI boards: Drop invalid MP table files
If we spot any error in the file, treat it as untested and
broken copy-paste.
Change-Id: Idd13b8b006fce7383f3f73c3c0a5d51a71c0155b
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/mainboard/amd/bettong/Kconfig
D src/mainboard/amd/bettong/mptable.c
M src/mainboard/amd/db-ft3b-lc/Kconfig
D src/mainboard/amd/db-ft3b-lc/mptable.c
M src/mainboard/amd/gardenia/Kconfig
D src/mainboard/amd/gardenia/mptable.c
M src/mainboard/amd/inagua/Kconfig
D src/mainboard/amd/inagua/mptable.c
M src/mainboard/amd/lamar/Kconfig
D src/mainboard/amd/lamar/mptable.c
M src/mainboard/amd/olivehill/Kconfig
D src/mainboard/amd/olivehill/mptable.c
M src/mainboard/amd/olivehillplus/Kconfig
D src/mainboard/amd/olivehillplus/mptable.c
M src/mainboard/amd/parmer/Kconfig
D src/mainboard/amd/parmer/mptable.c
M src/mainboard/amd/persimmon/Kconfig
D src/mainboard/amd/persimmon/mptable.c
M src/mainboard/amd/south_station/Kconfig
D src/mainboard/amd/south_station/mptable.c
M src/mainboard/amd/thatcher/Kconfig
D src/mainboard/amd/thatcher/mptable.c
M src/mainboard/amd/union_station/Kconfig
D src/mainboard/amd/union_station/mptable.c
M src/mainboard/asrock/e350m1/Kconfig
D src/mainboard/asrock/e350m1/mptable.c
M src/mainboard/asrock/imb-a180/Kconfig
D src/mainboard/asrock/imb-a180/mptable.c
M src/mainboard/asus/am1i-a/Kconfig
D src/mainboard/asus/am1i-a/mptable.c
M src/mainboard/asus/f2a85-m/Kconfig
D src/mainboard/asus/f2a85-m/mptable.c
M src/mainboard/bap/ode_e20XX/Kconfig
D src/mainboard/bap/ode_e20XX/mptable.c
M src/mainboard/bap/ode_e21XX/Kconfig
D src/mainboard/bap/ode_e21XX/mptable.c
M src/mainboard/biostar/a68n_5200/Kconfig
D src/mainboard/biostar/a68n_5200/mptable.c
M src/mainboard/biostar/am1ml/Kconfig
D src/mainboard/biostar/am1ml/mptable.c
M src/mainboard/elmex/pcm205400/Kconfig
D src/mainboard/elmex/pcm205400/mptable.c
M src/mainboard/gizmosphere/gizmo/Kconfig
D src/mainboard/gizmosphere/gizmo/mptable.c
M src/mainboard/gizmosphere/gizmo2/Kconfig
D src/mainboard/gizmosphere/gizmo2/mptable.c
D src/mainboard/google/kahlee/mptable.c
M src/mainboard/hp/abm/Kconfig
D src/mainboard/hp/abm/mptable.c
M src/mainboard/hp/pavilion_m6_1035dx/Kconfig
D src/mainboard/hp/pavilion_m6_1035dx/mptable.c
M src/mainboard/jetway/nf81-t56n-lf/Kconfig
D src/mainboard/jetway/nf81-t56n-lf/mptable.c
M src/mainboard/lenovo/g505s/Kconfig
D src/mainboard/lenovo/g505s/mptable.c
M src/mainboard/lippert/frontrunner-af/Kconfig
D src/mainboard/lippert/frontrunner-af/mptable.c
M src/mainboard/lippert/toucan-af/Kconfig
D src/mainboard/lippert/toucan-af/mptable.c
M src/mainboard/msi/ms7721/Kconfig
D src/mainboard/msi/ms7721/mptable.c
M src/mainboard/pcengines/apu1/Kconfig
D src/mainboard/pcengines/apu1/mptable.c
M src/mainboard/pcengines/apu2/Kconfig
D src/mainboard/pcengines/apu2/mptable.c
65 files changed, 0 insertions(+), 4,840 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/38313/1
diff --git a/src/mainboard/amd/bettong/Kconfig b/src/mainboard/amd/bettong/Kconfig
index 4617360..50140f7 100644
--- a/src/mainboard/amd/bettong/Kconfig
+++ b/src/mainboard/amd/bettong/Kconfig
@@ -28,7 +28,6 @@
select DEFAULT_POST_ON_LPC
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_8192
select GFXUMA
diff --git a/src/mainboard/amd/bettong/mptable.c b/src/mainboard/amd/bettong/mptable.c
deleted file mode 100644
index d9632d5..0000000
--- a/src/mainboard/amd/bettong/mptable.c
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/x86/lapic.h>
-#include <southbridge/amd/pi/hudson/hudson.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-
-static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
-{
- mc->mpc_length += length;
- mc->mpc_entry_count++;
-}
-
-static void my_smp_write_bus(struct mp_config_table *mc,
- unsigned char id, const char *bustype)
-{
- struct mpc_config_bus *mpc;
- mpc = smp_next_mpc_entry(mc);
- memset(mpc, '\0', sizeof(*mpc));
- mpc->mpc_type = MP_BUS;
- mpc->mpc_busid = id;
- memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
- smp_add_mpc_entry(mc, sizeof(*mpc));
-}
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
- memcpy(mc->mpc_oem, "AMD ", 8);
-
- smp_write_processors(mc);
-
- my_smp_write_bus(mc, 0, "PCI ");
- my_smp_write_bus(mc, 1, "PCI ");
- bus_isa = 0x02;
- my_smp_write_bus(mc, bus_isa, "ISA ");
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
-
- /* Internal VGA */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
- /* SMBUS */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
-
- /* HD Audio */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
- /* on board NIC & Slot PCIE. */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0. */
- PCI_INT(bus_pci, 0x5, 0x0, 0x14);
- PCI_INT(bus_pci, 0x5, 0x1, 0x15);
- PCI_INT(bus_pci, 0x5, 0x2, 0x16);
- PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_pci, 0x6, 0x0, 0x15);
- PCI_INT(bus_pci, 0x6, 0x1, 0x16);
- PCI_INT(bus_pci, 0x6, 0x2, 0x17);
- PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_pci, 0x7, 0x0, 0x16);
- PCI_INT(bus_pci, 0x7, 0x1, 0x17);
- PCI_INT(bus_pci, 0x7, 0x2, 0x14);
- PCI_INT(bus_pci, 0x7, 0x3, 0x15);
- }
-
- /* PCIe Lan*/
- PCI_INT(0x0, 0x06, 0x0, 0x13);
-
- /* FCH PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, 0x10);
- /* FCH PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, 0x11);
- /* FCH PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, 0x12);
- /* FCH PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, 0x13);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/amd/db-ft3b-lc/Kconfig b/src/mainboard/amd/db-ft3b-lc/Kconfig
index f17d2d3..7f24015 100644
--- a/src/mainboard/amd/db-ft3b-lc/Kconfig
+++ b/src/mainboard/amd/db-ft3b-lc/Kconfig
@@ -29,7 +29,6 @@
select DEFAULT_POST_ON_LPC
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_8192
select GFXUMA
diff --git a/src/mainboard/amd/db-ft3b-lc/mptable.c b/src/mainboard/amd/db-ft3b-lc/mptable.c
deleted file mode 100644
index 40a75ad..0000000
--- a/src/mainboard/amd/db-ft3b-lc/mptable.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- * Copyright (C) 2014 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <stdint.h>
-#include <cpu/x86/lapic.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /* Initialize the MP_Table */
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- /*
- * Type 0: Processor Entries:
- * LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
- * CPU Signature (Stepping, Model, Family),
- * Feature Flags
- */
- smp_write_processors(mc);
-
- /*
- * Type 1: Bus Entries:
- * Bus ID, Bus Type
- */
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /*
- * Type 2: I/O APICs:
- * APIC ID, Version, APIC Flags:EN, Address
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
- /*
- * Type 3: I/O Interrupt Table Entries:
- * Int Type, Int Polarity, Int Level, Source Bus ID,
- * Source Bus IRQ, Dest APIC ID, Dest PIN#
- */
-
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
-
- /* APU Internal Graphic Device */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]);
-
- /* SMBUS / ACPI */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]);
-
- /* Southbridge HD Audio */
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[PIRQ_EHCI1]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[PIRQ_EHCI2]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[PIRQ_EHCI3]);
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_OHCI4]);
-
- /* SATA */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
-
- /* on board NIC & Slot PCIE */
- PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]);
- PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]);
-
- /* PCIe Lan*/
- PCI_INT(0x0, 0x06, 0x0, intr_data_ptr[PIRQ_D]);
-
- /* FCH PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_A]);
- /* FCH PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_B]);
- /* FCH PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_C]);
- /* FCH PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_D]);
-
- IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
-
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/amd/gardenia/Kconfig b/src/mainboard/amd/gardenia/Kconfig
index e97a3ba..424a47d 100644
--- a/src/mainboard/amd/gardenia/Kconfig
+++ b/src/mainboard/amd/gardenia/Kconfig
@@ -21,7 +21,6 @@
select AMD_APU_STONEYRIDGE
select AMD_APU_PKG_FP4
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_8192
select GFXUMA
diff --git a/src/mainboard/amd/gardenia/mptable.c b/src/mainboard/amd/gardenia/mptable.c
deleted file mode 100644
index 5bb70e9..0000000
--- a/src/mainboard/amd/gardenia/mptable.c
+++ /dev/null
@@ -1,162 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/x86/lapic.h>
-#include <soc/southbridge.h>
-#include <amdblocks/amd_pci_util.h>
-
-static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
-{
- mc->mpc_length += length;
- mc->mpc_entry_count++;
-}
-
-static void my_smp_write_bus(struct mp_config_table *mc,
- unsigned char id, const char *bustype)
-{
- struct mpc_config_bus *mpc;
- mpc = smp_next_mpc_entry(mc);
- memset(mpc, '\0', sizeof(*mpc));
- mpc->mpc_type = MP_BUS;
- mpc->mpc_busid = id;
- memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
- smp_add_mpc_entry(mc, sizeof(*mpc));
-}
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
- memcpy(mc->mpc_oem, "AMD ", 8);
-
- smp_write_processors(mc);
-
- //mptable_write_buses(mc, NULL, &bus_isa);
- my_smp_write_bus(mc, 0, "PCI ");
- my_smp_write_bus(mc, 1, "PCI ");
- bus_isa = 0x02;
- my_smp_write_bus(mc, bus_isa, "ISA ");
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), \
- MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, \
- (intr), (apicid), (pin))
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, \
- MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), \
- (((dev)<<2)|(int_sign)), ioapic_id, (pin))
-
- /* Internal VGA */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
- /* SMBUS */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
-
- /* HD Audio */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
- /* on board NIC & Slot PCIE. */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0. */
- PCI_INT(bus_pci, 0x5, 0x0, 0x14);
- PCI_INT(bus_pci, 0x5, 0x1, 0x15);
- PCI_INT(bus_pci, 0x5, 0x2, 0x16);
- PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_pci, 0x6, 0x0, 0x15);
- PCI_INT(bus_pci, 0x6, 0x1, 0x16);
- PCI_INT(bus_pci, 0x6, 0x2, 0x17);
- PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_pci, 0x7, 0x0, 0x16);
- PCI_INT(bus_pci, 0x7, 0x1, 0x17);
- PCI_INT(bus_pci, 0x7, 0x2, 0x14);
- PCI_INT(bus_pci, 0x7, 0x3, 0x15);
- }
-
- /* PCIe Lan*/
- PCI_INT(0x0, 0x06, 0x0, 0x13);
-
- /* FCH PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, 0x10);
- /* FCH PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, 0x11);
- /* FCH PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, 0x12);
- /* FCH PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, 0x13);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/amd/inagua/Kconfig b/src/mainboard/amd/inagua/Kconfig
index a5ba07e..77f6b8a 100644
--- a/src/mainboard/amd/inagua/Kconfig
+++ b/src/mainboard/amd/inagua/Kconfig
@@ -27,7 +27,6 @@
select SUPERIO_SMSC_KBC1100
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_2048
select GFXUMA
diff --git a/src/mainboard/amd/inagua/mptable.c b/src/mainboard/amd/inagua/mptable.c
deleted file mode 100644
index b8bd0b3..0000000
--- a/src/mainboard/amd/inagua/mptable.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <string.h>
-#include <stdint.h>
-#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
- memcpy(mc->mpc_oem, "AMD ", 8);
-
- smp_write_processors(mc);
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
-
- /* APU Internal Graphic Device*/
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
- //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
- /* Southbridge HD Audio: */
- PCI_INT(0x0, 0x14, 0x2, 0x12);
-
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
- /* on board NIC & Slot PCIE. */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0. */
- PCI_INT(bus_pci, 0x5, 0x0, 0x14);
- PCI_INT(bus_pci, 0x5, 0x1, 0x15);
- PCI_INT(bus_pci, 0x5, 0x2, 0x16);
- PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_pci, 0x6, 0x0, 0x15);
- PCI_INT(bus_pci, 0x6, 0x1, 0x16);
- PCI_INT(bus_pci, 0x6, 0x2, 0x17);
- PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_pci, 0x7, 0x0, 0x16);
- PCI_INT(bus_pci, 0x7, 0x1, 0x17);
- PCI_INT(bus_pci, 0x7, 0x2, 0x14);
- PCI_INT(bus_pci, 0x7, 0x3, 0x15);
- }
-
- /* PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, 0x10);
- /* PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, 0x11);
- /* PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, 0x12);
- /* PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, 0x13);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/amd/lamar/Kconfig b/src/mainboard/amd/lamar/Kconfig
index c856534..2e19c3d 100644
--- a/src/mainboard/amd/lamar/Kconfig
+++ b/src/mainboard/amd/lamar/Kconfig
@@ -29,7 +29,6 @@
select SUPERIO_FINTEK_F81216H
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_8192
select GFXUMA
diff --git a/src/mainboard/amd/lamar/mptable.c b/src/mainboard/amd/lamar/mptable.c
deleted file mode 100644
index 1f2093d..0000000
--- a/src/mainboard/amd/lamar/mptable.c
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 - 2014 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <stdint.h>
-#include <cpu/x86/lapic.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <drivers/generic/ioapic/chip.h>
-#include <southbridge/amd/pi/hudson/amd_pci_int_defs.h>
-#include <northbridge/amd/pi/00630F01/pci_devs.h>
-
-#define NB_APIC_ADDR ((u8 *)0xFEC20000)
-
-#define PCI_INT(bus, dev, fn, apic, pin) \
- if (((pin) != 0x00) && ((pin) != 0x1F)) \
- { \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apic, (pin)); \
- }
-
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /* Initialize the MP_Table */
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- /*
- * Type 0: Processor Entries:
- * LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
- * CPU Signature (Stepping, Model, Family),
- * Feature Flags
- */
- smp_write_processors(mc);
-
- /*
- * Type 1: Bus Entries:
- * Bus ID, Bus Type
- */
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /*
- * Type 2: I/O APICs:
- * APIC ID, Version, APIC Flags:EN, Address
- */
-
- u8 apicid_nb = (io_apic_read(NB_APIC_ADDR, 0x00) >> 24); /* Get the GNB IOAPIC ID */
- u8 apicver_nb = (io_apic_read(NB_APIC_ADDR, 0x01) & 0xFF); /* Get the GNB IOAPIC version */
-
- smp_write_ioapic(mc, apicid_nb, apicver_nb, NB_APIC_ADDR);
-
- u8 apicid_sb = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); /* Get the southbridge IOAPIC ID */
- u8 apicver_sb = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); /* Get the southbridge IOAPIC version */
-
- smp_write_ioapic(mc, apicid_sb, apicver_sb, VIO_APIC_VADDR);
-
- /*
- * Type 3: I/O Interrupt Table Entries:
- * Int Type, Int Polarity, Int Level, Source Bus ID,
- * Source Bus IRQ, Dest APIC ID, Dest PIN#
- */
- mptable_add_isa_interrupts(mc, bus_isa, apicid_nb, 0);
- mptable_add_isa_interrupts(mc, bus_isa, apicid_sb, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-
- /* APU Internal Graphic Device */
- PCI_INT(0x0, 0x01, 0x0, apicid_nb, intr_data_ptr[PIRQ_GFX]);
- PCI_INT(0x0, 0x01, 0x1, apicid_nb, intr_data_ptr[PIRQ_ACTL]);
-
- /* SMBUS / ACPI */
- PCI_INT(0x0, 0x14, 0x0, apicid_sb, intr_data_ptr[PIRQ_SMBUS]);
-
- /* Southbridge HD Audio */
- PCI_INT(0x0, 0x14, 0x2, apicid_sb, intr_data_ptr[PIRQ_HDA]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, apicid_sb, intr_data_ptr[PIRQ_OHCI1]);
- PCI_INT(0x0, 0x12, 0x2, apicid_sb, intr_data_ptr[PIRQ_EHCI1]);
- PCI_INT(0x0, 0x13, 0x0, apicid_sb, intr_data_ptr[PIRQ_OHCI2]);
- PCI_INT(0x0, 0x13, 0x2, apicid_sb, intr_data_ptr[PIRQ_EHCI2]);
- PCI_INT(0x0, 0x16, 0x0, apicid_sb, intr_data_ptr[PIRQ_OHCI3]);
- PCI_INT(0x0, 0x16, 0x2, apicid_sb, intr_data_ptr[PIRQ_EHCI3]);
- PCI_INT(0x0, 0x14, 0x5, apicid_sb, intr_data_ptr[PIRQ_OHCI4]);
-
- /* SATA */
- PCI_INT(0x0, 0x11, 0x0, apicid_sb, intr_data_ptr[PIRQ_SATA]);
-
- /* IDE */
- PCI_INT(0x0, 0x14, 0x1, apicid_sb, intr_data_ptr[PIRQ_IDE]);
-
- /* PCI slots */
- /* NB Gfx PCIe Bridges */
- PCI_INT(0, 0x2, 0x1, apicid_nb, intr_data_ptr[PIRQ_A]);
- PCI_INT(0, 0x2, 0x2, apicid_nb, intr_data_ptr[PIRQ_A]);
-
- /* NB GPP PCIe Bridges */
- PCI_INT(0, 0x3, 0x1, apicid_nb, intr_data_ptr[PIRQ_A]);
- PCI_INT(0, 0x3, 0x2, apicid_nb, intr_data_ptr[PIRQ_A]);
- PCI_INT(0, 0x3, 0x3, apicid_nb, intr_data_ptr[PIRQ_A]);
- PCI_INT(0, 0x3, 0x4, apicid_nb, intr_data_ptr[PIRQ_A]);
- PCI_INT(0, 0x3, 0x5, apicid_nb, intr_data_ptr[PIRQ_A]);
-
- /* PCI slots */
- PCI_INT(0, 0x14, 0x4, apicid_sb, intr_data_ptr[PIRQ_A]);
-
- /* FCH GPP PCIe Bridges */
- PCI_INT(0x0, 0x15, 0x0, apicid_sb, intr_data_ptr[PIRQ_A]);
- /* FCH PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, apicid_sb, intr_data_ptr[PIRQ_A]);
- /* FCH PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, apicid_sb, intr_data_ptr[PIRQ_A]);
- /* FCH PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, apicid_sb, intr_data_ptr[PIRQ_A]);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
-
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/amd/olivehill/Kconfig b/src/mainboard/amd/olivehill/Kconfig
index 78f768f..8810c1d 100644
--- a/src/mainboard/amd/olivehill/Kconfig
+++ b/src/mainboard/amd/olivehill/Kconfig
@@ -27,7 +27,6 @@
select DEFAULT_POST_ON_LPC
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_4096
diff --git a/src/mainboard/amd/olivehill/mptable.c b/src/mainboard/amd/olivehill/mptable.c
deleted file mode 100644
index 7082013..0000000
--- a/src/mainboard/amd/olivehill/mptable.c
+++ /dev/null
@@ -1,158 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/x86/lapic.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <southbridge/amd/agesa/hudson/hudson.h>
-
-static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
-{
- mc->mpc_length += length;
- mc->mpc_entry_count++;
-}
-
-static void my_smp_write_bus(struct mp_config_table *mc,
- unsigned char id, const char *bustype)
-{
- struct mpc_config_bus *mpc;
- mpc = smp_next_mpc_entry(mc);
- memset(mpc, '\0', sizeof(*mpc));
- mpc->mpc_type = MP_BUS;
- mpc->mpc_busid = id;
- memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
- smp_add_mpc_entry(mc, sizeof(*mpc));
-}
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
- memcpy(mc->mpc_oem, "AMD ", 8);
-
- smp_write_processors(mc);
-
- //mptable_write_buses(mc, NULL, &bus_isa);
- my_smp_write_bus(mc, 0, "PCI ");
- my_smp_write_bus(mc, 1, "PCI ");
- bus_isa = 0x02;
- my_smp_write_bus(mc, bus_isa, "ISA ");
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
-
- /* Internal VGA */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
- /* SMBUS */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
-
- /* HD Audio */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
- /* on board NIC & Slot PCIE. */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0. */
- PCI_INT(bus_pci, 0x5, 0x0, 0x14);
- PCI_INT(bus_pci, 0x5, 0x1, 0x15);
- PCI_INT(bus_pci, 0x5, 0x2, 0x16);
- PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_pci, 0x6, 0x0, 0x15);
- PCI_INT(bus_pci, 0x6, 0x1, 0x16);
- PCI_INT(bus_pci, 0x6, 0x2, 0x17);
- PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_pci, 0x7, 0x0, 0x16);
- PCI_INT(bus_pci, 0x7, 0x1, 0x17);
- PCI_INT(bus_pci, 0x7, 0x2, 0x14);
- PCI_INT(bus_pci, 0x7, 0x3, 0x15);
- }
-
- /* PCIe Lan*/
- PCI_INT(0x0, 0x06, 0x0, 0x13);
-
- /* FCH PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, 0x10);
- /* FCH PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, 0x11);
- /* FCH PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, 0x12);
- /* FCH PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, 0x13);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/amd/olivehillplus/Kconfig b/src/mainboard/amd/olivehillplus/Kconfig
index 907de3b..1745969 100644
--- a/src/mainboard/amd/olivehillplus/Kconfig
+++ b/src/mainboard/amd/olivehillplus/Kconfig
@@ -28,7 +28,6 @@
select DEFAULT_POST_ON_LPC
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_8192
select GFXUMA
diff --git a/src/mainboard/amd/olivehillplus/mptable.c b/src/mainboard/amd/olivehillplus/mptable.c
deleted file mode 100644
index 0f6ca81..0000000
--- a/src/mainboard/amd/olivehillplus/mptable.c
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/x86/lapic.h>
-#include <southbridge/amd/pi/hudson/hudson.h>
-
-static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
-{
- mc->mpc_length += length;
- mc->mpc_entry_count++;
-}
-
-static void my_smp_write_bus(struct mp_config_table *mc,
- unsigned char id, const char *bustype)
-{
- struct mpc_config_bus *mpc;
- mpc = smp_next_mpc_entry(mc);
- memset(mpc, '\0', sizeof(*mpc));
- mpc->mpc_type = MP_BUS;
- mpc->mpc_busid = id;
- memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
- smp_add_mpc_entry(mc, sizeof(*mpc));
-}
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
- memcpy(mc->mpc_oem, "AMD ", 8);
-
- smp_write_processors(mc);
-
- //mptable_write_buses(mc, NULL, &bus_isa);
- my_smp_write_bus(mc, 0, "PCI ");
- my_smp_write_bus(mc, 1, "PCI ");
- bus_isa = 0x02;
- my_smp_write_bus(mc, bus_isa, "ISA ");
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
-
- /* Internal VGA */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
- /* SMBUS */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
-
- /* HD Audio */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
- /* on board NIC & Slot PCIE. */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0. */
- PCI_INT(bus_pci, 0x5, 0x0, 0x14);
- PCI_INT(bus_pci, 0x5, 0x1, 0x15);
- PCI_INT(bus_pci, 0x5, 0x2, 0x16);
- PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_pci, 0x6, 0x0, 0x15);
- PCI_INT(bus_pci, 0x6, 0x1, 0x16);
- PCI_INT(bus_pci, 0x6, 0x2, 0x17);
- PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_pci, 0x7, 0x0, 0x16);
- PCI_INT(bus_pci, 0x7, 0x1, 0x17);
- PCI_INT(bus_pci, 0x7, 0x2, 0x14);
- PCI_INT(bus_pci, 0x7, 0x3, 0x15);
- }
-
- /* PCIe Lan*/
- PCI_INT(0x0, 0x06, 0x0, 0x13);
-
- /* FCH PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, 0x10);
- /* FCH PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, 0x11);
- /* FCH PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, 0x12);
- /* FCH PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, 0x13);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/amd/parmer/Kconfig b/src/mainboard/amd/parmer/Kconfig
index ae024dd..94f55ce 100644
--- a/src/mainboard/amd/parmer/Kconfig
+++ b/src/mainboard/amd/parmer/Kconfig
@@ -27,7 +27,6 @@
select DEFAULT_POST_ON_LPC
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_4096
diff --git a/src/mainboard/amd/parmer/mptable.c b/src/mainboard/amd/parmer/mptable.c
deleted file mode 100644
index 3a5540c..0000000
--- a/src/mainboard/amd/parmer/mptable.c
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/x86/lapic.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <southbridge/amd/agesa/hudson/hudson.h>
-
-static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
-{
- mc->mpc_length += length;
- mc->mpc_entry_count++;
-}
-
-static void my_smp_write_bus(struct mp_config_table *mc,
- unsigned char id, const char *bustype)
-{
- struct mpc_config_bus *mpc;
- mpc = smp_next_mpc_entry(mc);
- memset(mpc, '\0', sizeof(*mpc));
- mpc->mpc_type = MP_BUS;
- mpc->mpc_busid = id;
- memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
- smp_add_mpc_entry(mc, sizeof(*mpc));
-}
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
- memcpy(mc->mpc_oem, "AMD ", 8);
-
- smp_write_processors(mc);
-
- //mptable_write_buses(mc, NULL, &bus_isa);
- my_smp_write_bus(mc, 0, "PCI ");
- my_smp_write_bus(mc, 1, "PCI ");
- bus_isa = 0x02;
- my_smp_write_bus(mc, bus_isa, "ISA ");
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
-
- /* Internal VGA */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
- /* SMBUS */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
-
- /* HD Audio */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
- /* on board NIC & Slot PCIE. */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0. */
- PCI_INT(bus_pci, 0x5, 0x0, 0x14);
- PCI_INT(bus_pci, 0x5, 0x1, 0x15);
- PCI_INT(bus_pci, 0x5, 0x2, 0x16);
- PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_pci, 0x6, 0x0, 0x15);
- PCI_INT(bus_pci, 0x6, 0x1, 0x16);
- PCI_INT(bus_pci, 0x6, 0x2, 0x17);
- PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_pci, 0x7, 0x0, 0x16);
- PCI_INT(bus_pci, 0x7, 0x1, 0x17);
- PCI_INT(bus_pci, 0x7, 0x2, 0x14);
- PCI_INT(bus_pci, 0x7, 0x3, 0x15);
- }
-
- /* PCIe Lan*/
- PCI_INT(0x0, 0x06, 0x0, 0x13);
-
- /* FCH PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, 0x10);
- /* FCH PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, 0x11);
- /* FCH PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, 0x12);
- /* FCH PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, 0x13);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/amd/persimmon/Kconfig b/src/mainboard/amd/persimmon/Kconfig
index f243f0f..248e4d4 100644
--- a/src/mainboard/amd/persimmon/Kconfig
+++ b/src/mainboard/amd/persimmon/Kconfig
@@ -27,7 +27,6 @@
select SUPERIO_FINTEK_F81865F
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_4096
diff --git a/src/mainboard/amd/persimmon/mptable.c b/src/mainboard/amd/persimmon/mptable.c
deleted file mode 100644
index bc7a3ac..0000000
--- a/src/mainboard/amd/persimmon/mptable.c
+++ /dev/null
@@ -1,142 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- * Copyright (C) 2014 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <stdint.h>
-#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <drivers/generic/ioapic/chip.h>
-#include <arch/ioapic.h>
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- /* Initialize the MP_Table */
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- /*
- * Type 0: Processor Entries:
- * LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
- * CPU Signature (Stepping, Model, Family),
- * Feature Flags
- */
- smp_write_processors(mc);
-
- /*
- * Type 1: Bus Entries:
- * Bus ID, Bus Type
- */
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /*
- * Type 2: I/O APICs:
- * APIC ID, Version, APIC Flags:EN, Address
- */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /*
- * Type 3: I/O Interrupt Table Entries:
- * Int Type, Int Polarity, Int Level, Source Bus ID,
- * Source Bus IRQ, Dest APIC ID, Dest PIN#
- */
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
-
- /* APU Internal Graphic Device */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]);
-
- /* SMBUS / ACPI */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]);
-
- /* Southbridge HD Audio */
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]);
-
- /* LPC */
- PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
- PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
- PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]);
- PCI_INT(0x0, 0x14, 0x5, intr_data_ptr[PIRQ_OHCI4]);
-
- /* IDE */
- PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_IDE]);
-
- /* SATA */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
-
- /* on board NIC & Slot PCIE */
- PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */
- PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0 */
- PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */
- PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */
- PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */
- PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */
- }
-
- /* PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */
- /* PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */
- /* PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */
- /* PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
- IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/amd/south_station/Kconfig b/src/mainboard/amd/south_station/Kconfig
index 42841cb..0d76d50 100644
--- a/src/mainboard/amd/south_station/Kconfig
+++ b/src/mainboard/amd/south_station/Kconfig
@@ -27,7 +27,6 @@
select SUPERIO_FINTEK_F81865F
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_4096
select GFXUMA
diff --git a/src/mainboard/amd/south_station/mptable.c b/src/mainboard/amd/south_station/mptable.c
deleted file mode 100644
index b8bd0b3..0000000
--- a/src/mainboard/amd/south_station/mptable.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <string.h>
-#include <stdint.h>
-#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
- memcpy(mc->mpc_oem, "AMD ", 8);
-
- smp_write_processors(mc);
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
-
- /* APU Internal Graphic Device*/
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
- //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
- /* Southbridge HD Audio: */
- PCI_INT(0x0, 0x14, 0x2, 0x12);
-
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
- /* on board NIC & Slot PCIE. */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0. */
- PCI_INT(bus_pci, 0x5, 0x0, 0x14);
- PCI_INT(bus_pci, 0x5, 0x1, 0x15);
- PCI_INT(bus_pci, 0x5, 0x2, 0x16);
- PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_pci, 0x6, 0x0, 0x15);
- PCI_INT(bus_pci, 0x6, 0x1, 0x16);
- PCI_INT(bus_pci, 0x6, 0x2, 0x17);
- PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_pci, 0x7, 0x0, 0x16);
- PCI_INT(bus_pci, 0x7, 0x1, 0x17);
- PCI_INT(bus_pci, 0x7, 0x2, 0x14);
- PCI_INT(bus_pci, 0x7, 0x3, 0x15);
- }
-
- /* PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, 0x10);
- /* PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, 0x11);
- /* PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, 0x12);
- /* PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, 0x13);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/amd/thatcher/Kconfig b/src/mainboard/amd/thatcher/Kconfig
index e556592..b79511f 100644
--- a/src/mainboard/amd/thatcher/Kconfig
+++ b/src/mainboard/amd/thatcher/Kconfig
@@ -27,7 +27,6 @@
select DEFAULT_POST_ON_LPC
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select SUPERIO_SMSC_LPC47N217
diff --git a/src/mainboard/amd/thatcher/mptable.c b/src/mainboard/amd/thatcher/mptable.c
deleted file mode 100644
index 05d222a..0000000
--- a/src/mainboard/amd/thatcher/mptable.c
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/x86/lapic.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <southbridge/amd/agesa/hudson/hudson.h>
-
-static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
-{
- mc->mpc_length += length;
- mc->mpc_entry_count++;
-}
-
-static void my_smp_write_bus(struct mp_config_table *mc,
- unsigned char id, const char *bustype)
-{
- struct mpc_config_bus *mpc;
- mpc = smp_next_mpc_entry(mc);
- memset(mpc, '\0', sizeof(*mpc));
- mpc->mpc_type = MP_BUS;
- mpc->mpc_busid = id;
- memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
- smp_add_mpc_entry(mc, sizeof(*mpc));
-}
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
- u8 byte;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
- memcpy(mc->mpc_oem, "AMD ", 8);
-
- smp_write_processors(mc);
-
- //mptable_write_buses(mc, NULL, &bus_isa);
- my_smp_write_bus(mc, 0, "PCI ");
- my_smp_write_bus(mc, 1, "PCI ");
- bus_isa = 0x02;
- my_smp_write_bus(mc, bus_isa, "ISA ");
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
-
- /* Internal VGA */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
- /* SMBUS */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
-
- /* HD Audio */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
- /* on board NIC & Slot PCIE. */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0. */
- PCI_INT(bus_pci, 0x5, 0x0, 0x14);
- PCI_INT(bus_pci, 0x5, 0x1, 0x15);
- PCI_INT(bus_pci, 0x5, 0x2, 0x16);
- PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_pci, 0x6, 0x0, 0x15);
- PCI_INT(bus_pci, 0x6, 0x1, 0x16);
- PCI_INT(bus_pci, 0x6, 0x2, 0x17);
- PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_pci, 0x7, 0x0, 0x16);
- PCI_INT(bus_pci, 0x7, 0x1, 0x17);
- PCI_INT(bus_pci, 0x7, 0x2, 0x14);
- PCI_INT(bus_pci, 0x7, 0x3, 0x15);
- }
-
- /* PCIe Lan*/
- PCI_INT(0x0, 0x06, 0x0, 0x13);
-
- /* FCH PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, 0x10);
- /* FCH PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, 0x11);
- /* FCH PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, 0x12);
- /* FCH PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, 0x13);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/amd/union_station/Kconfig b/src/mainboard/amd/union_station/Kconfig
index 1532d34..2dc82c9 100644
--- a/src/mainboard/amd/union_station/Kconfig
+++ b/src/mainboard/amd/union_station/Kconfig
@@ -26,7 +26,6 @@
select SOUTHBRIDGE_AMD_CIMX_SB800
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_2048
select GFXUMA
diff --git a/src/mainboard/amd/union_station/mptable.c b/src/mainboard/amd/union_station/mptable.c
deleted file mode 100644
index b8bd0b3..0000000
--- a/src/mainboard/amd/union_station/mptable.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <string.h>
-#include <stdint.h>
-#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
- memcpy(mc->mpc_oem, "AMD ", 8);
-
- smp_write_processors(mc);
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
-
- /* APU Internal Graphic Device*/
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
- //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
- /* Southbridge HD Audio: */
- PCI_INT(0x0, 0x14, 0x2, 0x12);
-
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
- /* on board NIC & Slot PCIE. */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0. */
- PCI_INT(bus_pci, 0x5, 0x0, 0x14);
- PCI_INT(bus_pci, 0x5, 0x1, 0x15);
- PCI_INT(bus_pci, 0x5, 0x2, 0x16);
- PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_pci, 0x6, 0x0, 0x15);
- PCI_INT(bus_pci, 0x6, 0x1, 0x16);
- PCI_INT(bus_pci, 0x6, 0x2, 0x17);
- PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_pci, 0x7, 0x0, 0x16);
- PCI_INT(bus_pci, 0x7, 0x1, 0x17);
- PCI_INT(bus_pci, 0x7, 0x2, 0x14);
- PCI_INT(bus_pci, 0x7, 0x3, 0x15);
- }
-
- /* PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, 0x10);
- /* PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, 0x11);
- /* PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, 0x12);
- /* PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, 0x13);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/asrock/e350m1/Kconfig b/src/mainboard/asrock/e350m1/Kconfig
index 3bbc2a5..18058c9 100644
--- a/src/mainboard/asrock/e350m1/Kconfig
+++ b/src/mainboard/asrock/e350m1/Kconfig
@@ -24,7 +24,6 @@
select SB_SUPERIO_HWM
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_4096
diff --git a/src/mainboard/asrock/e350m1/mptable.c b/src/mainboard/asrock/e350m1/mptable.c
deleted file mode 100644
index ce8cfa0..0000000
--- a/src/mainboard/asrock/e350m1/mptable.c
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-
-#include <arch/ioapic.h>
-#include <arch/smp/mpspec.h>
-#include <stdint.h>
-#include <string.h>
-
-#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
- memcpy(mc->mpc_oem, "ASROCK ", 8);
-
- smp_write_processors(mc);
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
-
- /* APU Internal Graphic Device*/
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
- //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
- /* Southbridge HD Audio: */
- PCI_INT(0x0, 0x14, 0x2, 0x12);
-
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
- /* on board NIC & Slot PCIE. */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0. */
- PCI_INT(bus_pci, 0x5, 0x0, 0x14);
- PCI_INT(bus_pci, 0x5, 0x1, 0x15);
- PCI_INT(bus_pci, 0x5, 0x2, 0x16);
- PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_pci, 0x6, 0x0, 0x15);
- PCI_INT(bus_pci, 0x6, 0x1, 0x16);
- PCI_INT(bus_pci, 0x6, 0x2, 0x17);
- PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_pci, 0x7, 0x0, 0x16);
- PCI_INT(bus_pci, 0x7, 0x1, 0x17);
- PCI_INT(bus_pci, 0x7, 0x2, 0x14);
- PCI_INT(bus_pci, 0x7, 0x3, 0x15);
- }
-
- /* PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, 0x10);
- /* PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, 0x11);
- /* PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, 0x12);
- /* PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, 0x13);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/asrock/imb-a180/Kconfig b/src/mainboard/asrock/imb-a180/Kconfig
index 8fca61c..7110c89 100644
--- a/src/mainboard/asrock/imb-a180/Kconfig
+++ b/src/mainboard/asrock/imb-a180/Kconfig
@@ -24,7 +24,6 @@
select SUPERIO_WINBOND_W83627UHG
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_4096
diff --git a/src/mainboard/asrock/imb-a180/mptable.c b/src/mainboard/asrock/imb-a180/mptable.c
deleted file mode 100644
index 7082013..0000000
--- a/src/mainboard/asrock/imb-a180/mptable.c
+++ /dev/null
@@ -1,158 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/x86/lapic.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <southbridge/amd/agesa/hudson/hudson.h>
-
-static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
-{
- mc->mpc_length += length;
- mc->mpc_entry_count++;
-}
-
-static void my_smp_write_bus(struct mp_config_table *mc,
- unsigned char id, const char *bustype)
-{
- struct mpc_config_bus *mpc;
- mpc = smp_next_mpc_entry(mc);
- memset(mpc, '\0', sizeof(*mpc));
- mpc->mpc_type = MP_BUS;
- mpc->mpc_busid = id;
- memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
- smp_add_mpc_entry(mc, sizeof(*mpc));
-}
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
- memcpy(mc->mpc_oem, "AMD ", 8);
-
- smp_write_processors(mc);
-
- //mptable_write_buses(mc, NULL, &bus_isa);
- my_smp_write_bus(mc, 0, "PCI ");
- my_smp_write_bus(mc, 1, "PCI ");
- bus_isa = 0x02;
- my_smp_write_bus(mc, bus_isa, "ISA ");
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
-
- /* Internal VGA */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
- /* SMBUS */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
-
- /* HD Audio */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
- /* on board NIC & Slot PCIE. */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0. */
- PCI_INT(bus_pci, 0x5, 0x0, 0x14);
- PCI_INT(bus_pci, 0x5, 0x1, 0x15);
- PCI_INT(bus_pci, 0x5, 0x2, 0x16);
- PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_pci, 0x6, 0x0, 0x15);
- PCI_INT(bus_pci, 0x6, 0x1, 0x16);
- PCI_INT(bus_pci, 0x6, 0x2, 0x17);
- PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_pci, 0x7, 0x0, 0x16);
- PCI_INT(bus_pci, 0x7, 0x1, 0x17);
- PCI_INT(bus_pci, 0x7, 0x2, 0x14);
- PCI_INT(bus_pci, 0x7, 0x3, 0x15);
- }
-
- /* PCIe Lan*/
- PCI_INT(0x0, 0x06, 0x0, 0x13);
-
- /* FCH PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, 0x10);
- /* FCH PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, 0x11);
- /* FCH PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, 0x12);
- /* FCH PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, 0x13);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/asus/am1i-a/Kconfig b/src/mainboard/asus/am1i-a/Kconfig
index a0dae9f..8a7e7e9 100644
--- a/src/mainboard/asus/am1i-a/Kconfig
+++ b/src/mainboard/asus/am1i-a/Kconfig
@@ -10,7 +10,6 @@
select USE_OPTION_TABLE
select HAVE_CMOS_DEFAULT
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB
diff --git a/src/mainboard/asus/am1i-a/mptable.c b/src/mainboard/asus/am1i-a/mptable.c
deleted file mode 100644
index 9efcab3..0000000
--- a/src/mainboard/asus/am1i-a/mptable.c
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- * Copyright (C) 2018 Gergely Kiss <mail.gery(a)gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <stdint.h>
-#include <cpu/x86/lapic.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <drivers/generic/ioapic/chip.h>
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- /* Initialize the MP_Table */
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- /*
- * Type 0: Processor Entries:
- * LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
- * CPU Signature (Stepping, Model, Family),
- * Feature Flags
- */
- smp_write_processors(mc);
-
- /*
- * Type 1: Bus Entries:
- * Bus ID, Bus Type
- */
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /*
- * Type 2: I/O APICs:
- * APIC ID, Version, APIC Flags:EN, Address
- */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /*
- * Type 3: I/O Interrupt Table Entries:
- * Int Type, Int Polarity, Int Level, Source Bus ID,
- * Source Bus IRQ, Dest APIC ID, Dest PIN#
- */
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
-
- /* APU Internal Graphic Device */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_A]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_B]);
-
- /* GPP Ports */
- PCI_INT(0x0, 0x02, 0x0, intr_data_ptr[PIRQ_A]);
- PCI_INT(0x0, 0x02, 0x1, intr_data_ptr[PIRQ_B]);
- PCI_INT(0x0, 0x02, 0x2, intr_data_ptr[PIRQ_C]);
- PCI_INT(0x0, 0x02, 0x3, intr_data_ptr[PIRQ_D]);
-
- /* SATA */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
-
- /* USB */
- PCI_INT(0x0, 0x10, 0x0, intr_data_ptr[PIRQ_C]); /* XHCI */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[PIRQ_EHCI1]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[PIRQ_EHCI2]);
-
- /* Southbridge HD Audio */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_HDA]);
-
- /* PCIe slot & Onboard NIC */
- PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_A]);
- PCI_INT(0x1, 0x0, 0x1, intr_data_ptr[PIRQ_B]);
- PCI_INT(0x1, 0x0, 0x2, intr_data_ptr[PIRQ_C]);
- PCI_INT(0x1, 0x0, 0x3, intr_data_ptr[PIRQ_D]);
- PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_B]);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
- IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/asus/f2a85-m/Kconfig b/src/mainboard/asus/f2a85-m/Kconfig
index c1dd063..5d5adb4 100644
--- a/src/mainboard/asus/f2a85-m/Kconfig
+++ b/src/mainboard/asus/f2a85-m/Kconfig
@@ -23,7 +23,6 @@
select SOUTHBRIDGE_AMD_AGESA_HUDSON
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select SUPERIO_ITE_IT8728F if BOARD_ASUS_F2A85_M || BOARD_ASUS_F2A85_M_LE
diff --git a/src/mainboard/asus/f2a85-m/mptable.c b/src/mainboard/asus/f2a85-m/mptable.c
deleted file mode 100644
index b5b0433..0000000
--- a/src/mainboard/asus/f2a85-m/mptable.c
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/ioapic.h>
-#include <arch/smp/mpspec.h>
-#include <cpu/x86/lapic.h>
-#include <stdint.h>
-#include <string.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <southbridge/amd/agesa/hudson/hudson.h>
-
-static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
-{
- mc->mpc_length += length;
- mc->mpc_entry_count++;
-}
-
-static void my_smp_write_bus(struct mp_config_table *mc,
- unsigned char id, const char *bustype)
-{
- struct mpc_config_bus *mpc;
- mpc = smp_next_mpc_entry(mc);
- memset(mpc, '\0', sizeof(*mpc));
- mpc->mpc_type = MP_BUS;
- mpc->mpc_busid = id;
- memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
- smp_add_mpc_entry(mc, sizeof(*mpc));
-}
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
- u8 byte;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
- memcpy(mc->mpc_oem, "AMD ", 8);
-
- smp_write_processors(mc);
-
- //mptable_write_buses(mc, NULL, &bus_isa);
- my_smp_write_bus(mc, 0, "PCI ");
- my_smp_write_bus(mc, 1, "PCI ");
- bus_isa = 0x02;
- my_smp_write_bus(mc, bus_isa, "ISA ");
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
-
- /* IOMMU */
- PCI_INT(0x0, 0x0, 0x0, 0x10);
- PCI_INT(0x0, 0x0, 0x1, 0x11);
- PCI_INT(0x0, 0x0, 0x2, 0x12);
- PCI_INT(0x0, 0x0, 0x3, 0x13);
-
- /* Internal VGA */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
- /* SMBUS */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
-
- /* HD Audio */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
- /* on board NIC & Slot PCIE. */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0. */
- PCI_INT(bus_pci, 0x5, 0x0, 0x14);
- PCI_INT(bus_pci, 0x5, 0x1, 0x15);
- PCI_INT(bus_pci, 0x5, 0x2, 0x16);
- PCI_INT(bus_pci, 0x5, 0x3, 0x17);
- }
-
- /* PCIe Lan*/
- PCI_INT(0x0, 0x06, 0x0, 0x13);
-
- /* FCH PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, 0x10);
- /* FCH PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, 0x11);
- /* FCH PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, 0x12);
- /* FCH PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, 0x13);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/bap/ode_e20XX/Kconfig b/src/mainboard/bap/ode_e20XX/Kconfig
index 2a72deb..6d417ed 100644
--- a/src/mainboard/bap/ode_e20XX/Kconfig
+++ b/src/mainboard/bap/ode_e20XX/Kconfig
@@ -28,7 +28,6 @@
select DEFAULT_POST_ON_LPC
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_4096
select GFXUMA
diff --git a/src/mainboard/bap/ode_e20XX/mptable.c b/src/mainboard/bap/ode_e20XX/mptable.c
deleted file mode 100644
index e4edc5f..0000000
--- a/src/mainboard/bap/ode_e20XX/mptable.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <stdint.h>
-#include <cpu/x86/lapic.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <drivers/generic/ioapic/chip.h>
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- /* Initialize the MP_Table */
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- /*
- * Type 0: Processor Entries:
- * LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
- * CPU Signature (Stepping, Model, Family),
- * Feature Flags
- */
- smp_write_processors(mc);
-
- /*
- * Type 1: Bus Entries:
- * Bus ID, Bus Type
- */
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /*
- * Type 2: I/O APICs:
- * APIC ID, Version, APIC Flags:EN, Address
- */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /*
- * Type 3: I/O Interrupt Table Entries:
- * Int Type, Int Polarity, Int Level, Source Bus ID,
- * Source Bus IRQ, Dest APIC ID, Dest PIN#
- */
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
-
- /* APU Internal Graphic Device */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]);
-
- /* SMBUS / ACPI */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]);
-
- /* Southbridge HD Audio */
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]);
-
- /* LPC */
- PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
- PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
- PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]);
- PCI_INT(0x0, 0x16, 0x2, intr_data_ptr[PIRQ_EHCI3]);
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_OHCI4]);
-
- /* SATA */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
-
- /* on board NIC & Slot PCIE */
- PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]);
- PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]);
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0 */
- PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]);
- PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]);
- PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]);
- PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]);
-
- /* PCI_SLOT 1 */
- PCI_INT(bus_pci, 0x6, 0x0, intr_data_ptr[PIRQ_F]);
- PCI_INT(bus_pci, 0x6, 0x1, intr_data_ptr[PIRQ_G]);
- PCI_INT(bus_pci, 0x6, 0x2, intr_data_ptr[PIRQ_H]);
- PCI_INT(bus_pci, 0x6, 0x3, intr_data_ptr[PIRQ_E]);
-
- /* PCI_SLOT 2 */
- PCI_INT(bus_pci, 0x7, 0x0, intr_data_ptr[PIRQ_G]);
- PCI_INT(bus_pci, 0x7, 0x1, intr_data_ptr[PIRQ_H]);
- PCI_INT(bus_pci, 0x7, 0x2, intr_data_ptr[PIRQ_E]);
- PCI_INT(bus_pci, 0x7, 0x3, intr_data_ptr[PIRQ_F]);
-
- PCI_INT(bus_pci, 0x0, 0x0, intr_data_ptr[PIRQ_C]);
- PCI_INT(bus_pci, 0x0, 0x1, intr_data_ptr[PIRQ_D]);
- PCI_INT(bus_pci, 0x0, 0x2, intr_data_ptr[PIRQ_E]);
- }
-
- /* PCIe Lan*/
- PCI_INT(0x0, 0x06, 0x0, intr_data_ptr[PIRQ_D]);
-
- /* FCH PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_A]);
- /* FCH PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_B]);
- /* FCH PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_C]);
- /* FCH PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_D]);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
- IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/bap/ode_e21XX/Kconfig b/src/mainboard/bap/ode_e21XX/Kconfig
index ff71d5b..c1b78c8 100644
--- a/src/mainboard/bap/ode_e21XX/Kconfig
+++ b/src/mainboard/bap/ode_e21XX/Kconfig
@@ -28,7 +28,6 @@
select DEFAULT_POST_ON_LPC
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_8192
select GFXUMA
diff --git a/src/mainboard/bap/ode_e21XX/mptable.c b/src/mainboard/bap/ode_e21XX/mptable.c
deleted file mode 100644
index 0f6ca81..0000000
--- a/src/mainboard/bap/ode_e21XX/mptable.c
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/x86/lapic.h>
-#include <southbridge/amd/pi/hudson/hudson.h>
-
-static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
-{
- mc->mpc_length += length;
- mc->mpc_entry_count++;
-}
-
-static void my_smp_write_bus(struct mp_config_table *mc,
- unsigned char id, const char *bustype)
-{
- struct mpc_config_bus *mpc;
- mpc = smp_next_mpc_entry(mc);
- memset(mpc, '\0', sizeof(*mpc));
- mpc->mpc_type = MP_BUS;
- mpc->mpc_busid = id;
- memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
- smp_add_mpc_entry(mc, sizeof(*mpc));
-}
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
- memcpy(mc->mpc_oem, "AMD ", 8);
-
- smp_write_processors(mc);
-
- //mptable_write_buses(mc, NULL, &bus_isa);
- my_smp_write_bus(mc, 0, "PCI ");
- my_smp_write_bus(mc, 1, "PCI ");
- bus_isa = 0x02;
- my_smp_write_bus(mc, bus_isa, "ISA ");
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
-
- /* Internal VGA */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
- /* SMBUS */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
-
- /* HD Audio */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
- /* on board NIC & Slot PCIE. */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0. */
- PCI_INT(bus_pci, 0x5, 0x0, 0x14);
- PCI_INT(bus_pci, 0x5, 0x1, 0x15);
- PCI_INT(bus_pci, 0x5, 0x2, 0x16);
- PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_pci, 0x6, 0x0, 0x15);
- PCI_INT(bus_pci, 0x6, 0x1, 0x16);
- PCI_INT(bus_pci, 0x6, 0x2, 0x17);
- PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_pci, 0x7, 0x0, 0x16);
- PCI_INT(bus_pci, 0x7, 0x1, 0x17);
- PCI_INT(bus_pci, 0x7, 0x2, 0x14);
- PCI_INT(bus_pci, 0x7, 0x3, 0x15);
- }
-
- /* PCIe Lan*/
- PCI_INT(0x0, 0x06, 0x0, 0x13);
-
- /* FCH PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, 0x10);
- /* FCH PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, 0x11);
- /* FCH PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, 0x12);
- /* FCH PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, 0x13);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/biostar/a68n_5200/Kconfig b/src/mainboard/biostar/a68n_5200/Kconfig
index f608513..c8d8884 100644
--- a/src/mainboard/biostar/a68n_5200/Kconfig
+++ b/src/mainboard/biostar/a68n_5200/Kconfig
@@ -29,7 +29,6 @@
select SUPERIO_ITE_IT8728F
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_4096
select GFXUMA
diff --git a/src/mainboard/biostar/a68n_5200/mptable.c b/src/mainboard/biostar/a68n_5200/mptable.c
deleted file mode 100644
index 7082013..0000000
--- a/src/mainboard/biostar/a68n_5200/mptable.c
+++ /dev/null
@@ -1,158 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/x86/lapic.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <southbridge/amd/agesa/hudson/hudson.h>
-
-static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
-{
- mc->mpc_length += length;
- mc->mpc_entry_count++;
-}
-
-static void my_smp_write_bus(struct mp_config_table *mc,
- unsigned char id, const char *bustype)
-{
- struct mpc_config_bus *mpc;
- mpc = smp_next_mpc_entry(mc);
- memset(mpc, '\0', sizeof(*mpc));
- mpc->mpc_type = MP_BUS;
- mpc->mpc_busid = id;
- memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
- smp_add_mpc_entry(mc, sizeof(*mpc));
-}
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
- memcpy(mc->mpc_oem, "AMD ", 8);
-
- smp_write_processors(mc);
-
- //mptable_write_buses(mc, NULL, &bus_isa);
- my_smp_write_bus(mc, 0, "PCI ");
- my_smp_write_bus(mc, 1, "PCI ");
- bus_isa = 0x02;
- my_smp_write_bus(mc, bus_isa, "ISA ");
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
-
- /* Internal VGA */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
- /* SMBUS */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
-
- /* HD Audio */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
- /* on board NIC & Slot PCIE. */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0. */
- PCI_INT(bus_pci, 0x5, 0x0, 0x14);
- PCI_INT(bus_pci, 0x5, 0x1, 0x15);
- PCI_INT(bus_pci, 0x5, 0x2, 0x16);
- PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_pci, 0x6, 0x0, 0x15);
- PCI_INT(bus_pci, 0x6, 0x1, 0x16);
- PCI_INT(bus_pci, 0x6, 0x2, 0x17);
- PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_pci, 0x7, 0x0, 0x16);
- PCI_INT(bus_pci, 0x7, 0x1, 0x17);
- PCI_INT(bus_pci, 0x7, 0x2, 0x14);
- PCI_INT(bus_pci, 0x7, 0x3, 0x15);
- }
-
- /* PCIe Lan*/
- PCI_INT(0x0, 0x06, 0x0, 0x13);
-
- /* FCH PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, 0x10);
- /* FCH PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, 0x11);
- /* FCH PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, 0x12);
- /* FCH PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, 0x13);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/biostar/am1ml/Kconfig b/src/mainboard/biostar/am1ml/Kconfig
index 9eaa6fb..c9960e3 100644
--- a/src/mainboard/biostar/am1ml/Kconfig
+++ b/src/mainboard/biostar/am1ml/Kconfig
@@ -24,7 +24,6 @@
select GFXUMA
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB
diff --git a/src/mainboard/biostar/am1ml/mptable.c b/src/mainboard/biostar/am1ml/mptable.c
deleted file mode 100644
index 659a141..0000000
--- a/src/mainboard/biostar/am1ml/mptable.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <stdint.h>
-#include <cpu/x86/lapic.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <drivers/generic/ioapic/chip.h>
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- /* Initialize the MP_Table */
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- /*
- * Type 0: Processor Entries:
- * LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
- * CPU Signature (Stepping, Model, Family),
- * Feature Flags
- */
- smp_write_processors(mc);
-
- /*
- * Type 1: Bus Entries:
- * Bus ID, Bus Type
- */
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /*
- * Type 2: I/O APICs:
- * APIC ID, Version, APIC Flags:EN, Address
- */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /*
- * Type 3: I/O Interrupt Table Entries:
- * Int Type, Int Polarity, Int Level, Source Bus ID,
- * Source Bus IRQ, Dest APIC ID, Dest PIN#
- */
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
-
- /* APU Internal Graphic Device */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]);
-
- /* SMBUS / ACPI */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]);
-
- /* Southbridge HD Audio */
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]);
-
- /* LPC */
- PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
- PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
- PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]);
- PCI_INT(0x0, 0x16, 0x2, intr_data_ptr[PIRQ_EHCI3]);
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_OHCI4]);
-
- /* SATA */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
-
- /* on board NIC & Slot PCIE */
- PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]);
- PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]);
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0 */
- PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]);
- PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]);
- PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]);
- PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]);
-
- /* PCI_SLOT 1 */
- PCI_INT(bus_pci, 0x6, 0x0, intr_data_ptr[PIRQ_F]);
- PCI_INT(bus_pci, 0x6, 0x1, intr_data_ptr[PIRQ_G]);
- PCI_INT(bus_pci, 0x6, 0x2, intr_data_ptr[PIRQ_H]);
- PCI_INT(bus_pci, 0x6, 0x3, intr_data_ptr[PIRQ_E]);
-
- /* PCI_SLOT 2 */
- PCI_INT(bus_pci, 0x7, 0x0, intr_data_ptr[PIRQ_G]);
- PCI_INT(bus_pci, 0x7, 0x1, intr_data_ptr[PIRQ_H]);
- PCI_INT(bus_pci, 0x7, 0x2, intr_data_ptr[PIRQ_E]);
- PCI_INT(bus_pci, 0x7, 0x3, intr_data_ptr[PIRQ_F]);
-
- PCI_INT(bus_pci, 0x0, 0x0, intr_data_ptr[PIRQ_C]);
- PCI_INT(bus_pci, 0x0, 0x1, intr_data_ptr[PIRQ_D]);
- PCI_INT(bus_pci, 0x0, 0x2, intr_data_ptr[PIRQ_E]);
- }
-
- /* PCIe Lan*/
- //PCI_INT(0x0, 0x06, 0x0, intr_data_ptr[PIRQ_D]);
-
- /* FCH PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_A]);
- /* FCH PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_B]);
- /* FCH PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_C]);
- /* FCH PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_D]);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
- IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/elmex/pcm205400/Kconfig b/src/mainboard/elmex/pcm205400/Kconfig
index e94a6d8..5892992 100644
--- a/src/mainboard/elmex/pcm205400/Kconfig
+++ b/src/mainboard/elmex/pcm205400/Kconfig
@@ -39,7 +39,6 @@
select SUPERIO_FINTEK_F81865F
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_4096
diff --git a/src/mainboard/elmex/pcm205400/mptable.c b/src/mainboard/elmex/pcm205400/mptable.c
deleted file mode 100644
index bc7a3ac..0000000
--- a/src/mainboard/elmex/pcm205400/mptable.c
+++ /dev/null
@@ -1,142 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- * Copyright (C) 2014 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <stdint.h>
-#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <drivers/generic/ioapic/chip.h>
-#include <arch/ioapic.h>
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- /* Initialize the MP_Table */
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- /*
- * Type 0: Processor Entries:
- * LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
- * CPU Signature (Stepping, Model, Family),
- * Feature Flags
- */
- smp_write_processors(mc);
-
- /*
- * Type 1: Bus Entries:
- * Bus ID, Bus Type
- */
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /*
- * Type 2: I/O APICs:
- * APIC ID, Version, APIC Flags:EN, Address
- */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /*
- * Type 3: I/O Interrupt Table Entries:
- * Int Type, Int Polarity, Int Level, Source Bus ID,
- * Source Bus IRQ, Dest APIC ID, Dest PIN#
- */
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
-
- /* APU Internal Graphic Device */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]);
-
- /* SMBUS / ACPI */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]);
-
- /* Southbridge HD Audio */
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]);
-
- /* LPC */
- PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
- PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
- PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]);
- PCI_INT(0x0, 0x14, 0x5, intr_data_ptr[PIRQ_OHCI4]);
-
- /* IDE */
- PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_IDE]);
-
- /* SATA */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
-
- /* on board NIC & Slot PCIE */
- PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */
- PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0 */
- PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */
- PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */
- PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */
- PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */
- }
-
- /* PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */
- /* PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */
- /* PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */
- /* PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
- IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/gizmosphere/gizmo/Kconfig b/src/mainboard/gizmosphere/gizmo/Kconfig
index e195e8f..30c88c1 100644
--- a/src/mainboard/gizmosphere/gizmo/Kconfig
+++ b/src/mainboard/gizmosphere/gizmo/Kconfig
@@ -23,7 +23,6 @@
select SOUTHBRIDGE_AMD_CIMX_SB800
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_2048
diff --git a/src/mainboard/gizmosphere/gizmo/mptable.c b/src/mainboard/gizmosphere/gizmo/mptable.c
deleted file mode 100644
index a47336c..0000000
--- a/src/mainboard/gizmosphere/gizmo/mptable.c
+++ /dev/null
@@ -1,127 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- * Copyright (C) 2013 Sage Electronic Engineering, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <string.h>
-#include <stdint.h>
-#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
- memcpy(mc->mpc_oem, "AMD ", 8);
-
- smp_write_processors(mc);
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
-
- /* APU Internal Graphic Device*/
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
- //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
- /* Southbridge HD Audio: */
- PCI_INT(0x0, 0x14, 0x2, 0x12);
-
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
- /* on board NIC & Slot PCIE. */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0. */
- PCI_INT(bus_pci, 0x5, 0x0, 0x14);
- PCI_INT(bus_pci, 0x5, 0x1, 0x15);
- PCI_INT(bus_pci, 0x5, 0x2, 0x16);
- PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_pci, 0x6, 0x0, 0x15);
- PCI_INT(bus_pci, 0x6, 0x1, 0x16);
- PCI_INT(bus_pci, 0x6, 0x2, 0x17);
- PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_pci, 0x7, 0x0, 0x16);
- PCI_INT(bus_pci, 0x7, 0x1, 0x17);
- PCI_INT(bus_pci, 0x7, 0x2, 0x14);
- PCI_INT(bus_pci, 0x7, 0x3, 0x15);
- }
-
- /* PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, 0x10);
- /* PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, 0x11);
- /* PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, 0x12);
- /* PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, 0x13);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/gizmosphere/gizmo2/Kconfig b/src/mainboard/gizmosphere/gizmo2/Kconfig
index 685e271..6a8095d 100644
--- a/src/mainboard/gizmosphere/gizmo2/Kconfig
+++ b/src/mainboard/gizmosphere/gizmo2/Kconfig
@@ -28,7 +28,6 @@
select DEFAULT_POST_ON_LPC
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_4096
diff --git a/src/mainboard/gizmosphere/gizmo2/mptable.c b/src/mainboard/gizmosphere/gizmo2/mptable.c
deleted file mode 100644
index e4edc5f..0000000
--- a/src/mainboard/gizmosphere/gizmo2/mptable.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <stdint.h>
-#include <cpu/x86/lapic.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <drivers/generic/ioapic/chip.h>
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- /* Initialize the MP_Table */
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- /*
- * Type 0: Processor Entries:
- * LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
- * CPU Signature (Stepping, Model, Family),
- * Feature Flags
- */
- smp_write_processors(mc);
-
- /*
- * Type 1: Bus Entries:
- * Bus ID, Bus Type
- */
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /*
- * Type 2: I/O APICs:
- * APIC ID, Version, APIC Flags:EN, Address
- */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /*
- * Type 3: I/O Interrupt Table Entries:
- * Int Type, Int Polarity, Int Level, Source Bus ID,
- * Source Bus IRQ, Dest APIC ID, Dest PIN#
- */
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
-
- /* APU Internal Graphic Device */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]);
-
- /* SMBUS / ACPI */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]);
-
- /* Southbridge HD Audio */
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]);
-
- /* LPC */
- PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
- PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
- PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]);
- PCI_INT(0x0, 0x16, 0x2, intr_data_ptr[PIRQ_EHCI3]);
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_OHCI4]);
-
- /* SATA */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
-
- /* on board NIC & Slot PCIE */
- PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]);
- PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]);
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0 */
- PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]);
- PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]);
- PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]);
- PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]);
-
- /* PCI_SLOT 1 */
- PCI_INT(bus_pci, 0x6, 0x0, intr_data_ptr[PIRQ_F]);
- PCI_INT(bus_pci, 0x6, 0x1, intr_data_ptr[PIRQ_G]);
- PCI_INT(bus_pci, 0x6, 0x2, intr_data_ptr[PIRQ_H]);
- PCI_INT(bus_pci, 0x6, 0x3, intr_data_ptr[PIRQ_E]);
-
- /* PCI_SLOT 2 */
- PCI_INT(bus_pci, 0x7, 0x0, intr_data_ptr[PIRQ_G]);
- PCI_INT(bus_pci, 0x7, 0x1, intr_data_ptr[PIRQ_H]);
- PCI_INT(bus_pci, 0x7, 0x2, intr_data_ptr[PIRQ_E]);
- PCI_INT(bus_pci, 0x7, 0x3, intr_data_ptr[PIRQ_F]);
-
- PCI_INT(bus_pci, 0x0, 0x0, intr_data_ptr[PIRQ_C]);
- PCI_INT(bus_pci, 0x0, 0x1, intr_data_ptr[PIRQ_D]);
- PCI_INT(bus_pci, 0x0, 0x2, intr_data_ptr[PIRQ_E]);
- }
-
- /* PCIe Lan*/
- PCI_INT(0x0, 0x06, 0x0, intr_data_ptr[PIRQ_D]);
-
- /* FCH PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_A]);
- /* FCH PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_B]);
- /* FCH PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_C]);
- /* FCH PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_D]);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
- IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/google/kahlee/mptable.c b/src/mainboard/google/kahlee/mptable.c
deleted file mode 100644
index 5bb70e9..0000000
--- a/src/mainboard/google/kahlee/mptable.c
+++ /dev/null
@@ -1,162 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/x86/lapic.h>
-#include <soc/southbridge.h>
-#include <amdblocks/amd_pci_util.h>
-
-static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
-{
- mc->mpc_length += length;
- mc->mpc_entry_count++;
-}
-
-static void my_smp_write_bus(struct mp_config_table *mc,
- unsigned char id, const char *bustype)
-{
- struct mpc_config_bus *mpc;
- mpc = smp_next_mpc_entry(mc);
- memset(mpc, '\0', sizeof(*mpc));
- mpc->mpc_type = MP_BUS;
- mpc->mpc_busid = id;
- memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
- smp_add_mpc_entry(mc, sizeof(*mpc));
-}
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
- memcpy(mc->mpc_oem, "AMD ", 8);
-
- smp_write_processors(mc);
-
- //mptable_write_buses(mc, NULL, &bus_isa);
- my_smp_write_bus(mc, 0, "PCI ");
- my_smp_write_bus(mc, 1, "PCI ");
- bus_isa = 0x02;
- my_smp_write_bus(mc, bus_isa, "ISA ");
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), \
- MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, \
- (intr), (apicid), (pin))
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, \
- MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), \
- (((dev)<<2)|(int_sign)), ioapic_id, (pin))
-
- /* Internal VGA */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
- /* SMBUS */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
-
- /* HD Audio */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
- /* on board NIC & Slot PCIE. */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0. */
- PCI_INT(bus_pci, 0x5, 0x0, 0x14);
- PCI_INT(bus_pci, 0x5, 0x1, 0x15);
- PCI_INT(bus_pci, 0x5, 0x2, 0x16);
- PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_pci, 0x6, 0x0, 0x15);
- PCI_INT(bus_pci, 0x6, 0x1, 0x16);
- PCI_INT(bus_pci, 0x6, 0x2, 0x17);
- PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_pci, 0x7, 0x0, 0x16);
- PCI_INT(bus_pci, 0x7, 0x1, 0x17);
- PCI_INT(bus_pci, 0x7, 0x2, 0x14);
- PCI_INT(bus_pci, 0x7, 0x3, 0x15);
- }
-
- /* PCIe Lan*/
- PCI_INT(0x0, 0x06, 0x0, 0x13);
-
- /* FCH PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, 0x10);
- /* FCH PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, 0x11);
- /* FCH PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, 0x12);
- /* FCH PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, 0x13);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/hp/abm/Kconfig b/src/mainboard/hp/abm/Kconfig
index 907c025..6239086 100644
--- a/src/mainboard/hp/abm/Kconfig
+++ b/src/mainboard/hp/abm/Kconfig
@@ -29,7 +29,6 @@
select SUPERIO_NUVOTON_NCT5104D
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_8192
diff --git a/src/mainboard/hp/abm/mptable.c b/src/mainboard/hp/abm/mptable.c
deleted file mode 100644
index 7082013..0000000
--- a/src/mainboard/hp/abm/mptable.c
+++ /dev/null
@@ -1,158 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/x86/lapic.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <southbridge/amd/agesa/hudson/hudson.h>
-
-static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
-{
- mc->mpc_length += length;
- mc->mpc_entry_count++;
-}
-
-static void my_smp_write_bus(struct mp_config_table *mc,
- unsigned char id, const char *bustype)
-{
- struct mpc_config_bus *mpc;
- mpc = smp_next_mpc_entry(mc);
- memset(mpc, '\0', sizeof(*mpc));
- mpc->mpc_type = MP_BUS;
- mpc->mpc_busid = id;
- memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
- smp_add_mpc_entry(mc, sizeof(*mpc));
-}
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
- memcpy(mc->mpc_oem, "AMD ", 8);
-
- smp_write_processors(mc);
-
- //mptable_write_buses(mc, NULL, &bus_isa);
- my_smp_write_bus(mc, 0, "PCI ");
- my_smp_write_bus(mc, 1, "PCI ");
- bus_isa = 0x02;
- my_smp_write_bus(mc, bus_isa, "ISA ");
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
-
- /* Internal VGA */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
- /* SMBUS */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
-
- /* HD Audio */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
- /* on board NIC & Slot PCIE. */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0. */
- PCI_INT(bus_pci, 0x5, 0x0, 0x14);
- PCI_INT(bus_pci, 0x5, 0x1, 0x15);
- PCI_INT(bus_pci, 0x5, 0x2, 0x16);
- PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_pci, 0x6, 0x0, 0x15);
- PCI_INT(bus_pci, 0x6, 0x1, 0x16);
- PCI_INT(bus_pci, 0x6, 0x2, 0x17);
- PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_pci, 0x7, 0x0, 0x16);
- PCI_INT(bus_pci, 0x7, 0x1, 0x17);
- PCI_INT(bus_pci, 0x7, 0x2, 0x14);
- PCI_INT(bus_pci, 0x7, 0x3, 0x15);
- }
-
- /* PCIe Lan*/
- PCI_INT(0x0, 0x06, 0x0, 0x13);
-
- /* FCH PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, 0x10);
- /* FCH PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, 0x11);
- /* FCH PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, 0x12);
- /* FCH PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, 0x13);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig
index c6c35df..1f17a15 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig
+++ b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig
@@ -25,7 +25,6 @@
select EC_COMPAL_ENE932
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_SMI_HANDLER
select HAVE_ACPI_TABLES
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c b/src/mainboard/hp/pavilion_m6_1035dx/mptable.c
deleted file mode 100644
index ecc57b0..0000000
--- a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c
+++ /dev/null
@@ -1,162 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/ioapic.h>
-#include <arch/smp/mpspec.h>
-#include <cpu/x86/lapic.h>
-#include <stdint.h>
-#include <string.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <southbridge/amd/agesa/hudson/hudson.h>
-
-static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
-{
- mc->mpc_length += length;
- mc->mpc_entry_count++;
-}
-
-static void my_smp_write_bus(struct mp_config_table *mc,
- unsigned char id, const char *bustype)
-{
- struct mpc_config_bus *mpc;
- mpc = smp_next_mpc_entry(mc);
- memset(mpc, '\0', sizeof(*mpc));
- mpc->mpc_type = MP_BUS;
- mpc->mpc_busid = id;
- memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
- smp_add_mpc_entry(mc, sizeof(*mpc));
-}
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
- memcpy(mc->mpc_oem, "AMD ", 8);
-
- smp_write_processors(mc);
-
- //mptable_write_buses(mc, NULL, &bus_isa);
- my_smp_write_bus(mc, 0, "PCI ");
- my_smp_write_bus(mc, 1, "PCI ");
- bus_isa = 0x02;
- my_smp_write_bus(mc, bus_isa, "ISA ");
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
-
- /* IOMMU */
- PCI_INT(0x0, 0x00, 0x0, 0x10);
- PCI_INT(0x0, 0x00, 0x1, 0x11);
- PCI_INT(0x0, 0x00, 0x2, 0x12);
- PCI_INT(0x0, 0x00, 0x3, 0x13);
-
- /* Internal VGA */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
- /* SMBUS */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
-
- /* HD Audio */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
- /* on board NIC & Slot PCIE. */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0. */
- PCI_INT(bus_pci, 0x5, 0x0, 0x14);
- PCI_INT(bus_pci, 0x5, 0x1, 0x15);
- PCI_INT(bus_pci, 0x5, 0x2, 0x16);
- PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_pci, 0x6, 0x0, 0x15);
- PCI_INT(bus_pci, 0x6, 0x1, 0x16);
- PCI_INT(bus_pci, 0x6, 0x2, 0x17);
- PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_pci, 0x7, 0x0, 0x16);
- PCI_INT(bus_pci, 0x7, 0x1, 0x17);
- PCI_INT(bus_pci, 0x7, 0x2, 0x14);
- PCI_INT(bus_pci, 0x7, 0x3, 0x15);
- }
-
- /* PCIe Lan*/
- PCI_INT(0x0, 0x06, 0x0, 0x13);
-
- /* FCH PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, 0x10);
- /* FCH PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, 0x11);
- /* FCH PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, 0x12);
- /* FCH PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, 0x13);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/jetway/nf81-t56n-lf/Kconfig b/src/mainboard/jetway/nf81-t56n-lf/Kconfig
index dfa01b9..dddca36 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/Kconfig
+++ b/src/mainboard/jetway/nf81-t56n-lf/Kconfig
@@ -28,7 +28,6 @@
select SUPERIO_FINTEK_F71869AD
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_2048
diff --git a/src/mainboard/jetway/nf81-t56n-lf/mptable.c b/src/mainboard/jetway/nf81-t56n-lf/mptable.c
deleted file mode 100644
index 9a983b4..0000000
--- a/src/mainboard/jetway/nf81-t56n-lf/mptable.c
+++ /dev/null
@@ -1,143 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- * Copyright (C) 2014 Sage Electronic Engineering, LLC.
- * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/ioapic.h>
-#include <arch/smp/mpspec.h>
-#include <drivers/generic/ioapic/chip.h>
-#include <stdint.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- /* Initialize the MP_Table */
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- /*
- * Type 0: Processor Entries:
- * LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
- * CPU Signature (Stepping, Model, Family),
- * Feature Flags
- */
- smp_write_processors(mc);
-
- /*
- * Type 1: Bus Entries:
- * Bus ID, Bus Type
- */
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /*
- * Type 2: I/O APICs:
- * APIC ID, Version, APIC Flags:EN, Address
- */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /*
- * Type 3: I/O Interrupt Table Entries:
- * Int Type, Int Polarity, Int Level, Source Bus ID,
- * Source Bus IRQ, Dest APIC ID, Dest PIN#
- */
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
-
- /* APU Internal Graphic Device */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]);
-
- /* SMBUS / ACPI */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]);
-
- /* Southbridge HD Audio */
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]);
-
- /* LPC */
- PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
- PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
- PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]);
- PCI_INT(0x0, 0x14, 0x5, intr_data_ptr[PIRQ_OHCI4]);
-
- /* IDE */
- PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_IDE]);
-
- /* SATA */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
-
- /* On-board NIC & Slot PCIE. */
- PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */
- PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0 */
- PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */
- PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */
- PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */
- PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */
- }
-
- /* On-board Realtek NIC 2. (PCIe PortA) */
- PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */
- /* PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */
- /* PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */
- /* PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
- IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/lenovo/g505s/Kconfig b/src/mainboard/lenovo/g505s/Kconfig
index 6ffe508..7f0d7bf 100644
--- a/src/mainboard/lenovo/g505s/Kconfig
+++ b/src/mainboard/lenovo/g505s/Kconfig
@@ -24,7 +24,6 @@
select DEFAULT_POST_ON_LPC
select EC_COMPAL_ENE932
select HAVE_OPTION_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_SMI_HANDLER
select HAVE_ACPI_TABLES
diff --git a/src/mainboard/lenovo/g505s/mptable.c b/src/mainboard/lenovo/g505s/mptable.c
deleted file mode 100644
index ecc57b0..0000000
--- a/src/mainboard/lenovo/g505s/mptable.c
+++ /dev/null
@@ -1,162 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/ioapic.h>
-#include <arch/smp/mpspec.h>
-#include <cpu/x86/lapic.h>
-#include <stdint.h>
-#include <string.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <southbridge/amd/agesa/hudson/hudson.h>
-
-static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
-{
- mc->mpc_length += length;
- mc->mpc_entry_count++;
-}
-
-static void my_smp_write_bus(struct mp_config_table *mc,
- unsigned char id, const char *bustype)
-{
- struct mpc_config_bus *mpc;
- mpc = smp_next_mpc_entry(mc);
- memset(mpc, '\0', sizeof(*mpc));
- mpc->mpc_type = MP_BUS;
- mpc->mpc_busid = id;
- memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
- smp_add_mpc_entry(mc, sizeof(*mpc));
-}
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
- memcpy(mc->mpc_oem, "AMD ", 8);
-
- smp_write_processors(mc);
-
- //mptable_write_buses(mc, NULL, &bus_isa);
- my_smp_write_bus(mc, 0, "PCI ");
- my_smp_write_bus(mc, 1, "PCI ");
- bus_isa = 0x02;
- my_smp_write_bus(mc, bus_isa, "ISA ");
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
-
- /* IOMMU */
- PCI_INT(0x0, 0x00, 0x0, 0x10);
- PCI_INT(0x0, 0x00, 0x1, 0x11);
- PCI_INT(0x0, 0x00, 0x2, 0x12);
- PCI_INT(0x0, 0x00, 0x3, 0x13);
-
- /* Internal VGA */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
- /* SMBUS */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
-
- /* HD Audio */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
- /* on board NIC & Slot PCIE. */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0. */
- PCI_INT(bus_pci, 0x5, 0x0, 0x14);
- PCI_INT(bus_pci, 0x5, 0x1, 0x15);
- PCI_INT(bus_pci, 0x5, 0x2, 0x16);
- PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_pci, 0x6, 0x0, 0x15);
- PCI_INT(bus_pci, 0x6, 0x1, 0x16);
- PCI_INT(bus_pci, 0x6, 0x2, 0x17);
- PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_pci, 0x7, 0x0, 0x16);
- PCI_INT(bus_pci, 0x7, 0x1, 0x17);
- PCI_INT(bus_pci, 0x7, 0x2, 0x14);
- PCI_INT(bus_pci, 0x7, 0x3, 0x15);
- }
-
- /* PCIe Lan*/
- PCI_INT(0x0, 0x06, 0x0, 0x13);
-
- /* FCH PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, 0x10);
- /* FCH PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, 0x11);
- /* FCH PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, 0x12);
- /* FCH PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, 0x13);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/lippert/frontrunner-af/Kconfig b/src/mainboard/lippert/frontrunner-af/Kconfig
index 4a007bf..64a8f14 100644
--- a/src/mainboard/lippert/frontrunner-af/Kconfig
+++ b/src/mainboard/lippert/frontrunner-af/Kconfig
@@ -27,7 +27,6 @@
select SUPERIO_SMSC_SMSCSUPERIO
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
# This erases 28 KB and writes 10 KB register dumps to SPI flash on every
# boot, wasting 3 s and causing wear! Therefore disable S3 for now.
#select HAVE_ACPI_RESUME
diff --git a/src/mainboard/lippert/frontrunner-af/mptable.c b/src/mainboard/lippert/frontrunner-af/mptable.c
deleted file mode 100644
index 78b8ec2..0000000
--- a/src/mainboard/lippert/frontrunner-af/mptable.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <string.h>
-#include <stdint.h>
-#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
- memcpy(mc->mpc_oem, "AMD ", 8);
-
- smp_write_processors(mc);
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
-
- /* APU Internal Graphic Device*/
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
- //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
- /* Southbridge HD Audio: */
- PCI_INT(0x0, 0x14, 0x2, 0x12);
-
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
- /* on board NIC & Slot PCIE. */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0. */
- PCI_INT(bus_pci, 0x5, 0x0, 0x14);
- PCI_INT(bus_pci, 0x5, 0x1, 0x15);
- PCI_INT(bus_pci, 0x5, 0x2, 0x16);
- PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_pci, 0x6, 0x0, 0x15);
- PCI_INT(bus_pci, 0x6, 0x1, 0x16);
- PCI_INT(bus_pci, 0x6, 0x2, 0x17);
- PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_pci, 0x7, 0x0, 0x16);
- PCI_INT(bus_pci, 0x7, 0x1, 0x17);
- PCI_INT(bus_pci, 0x7, 0x2, 0x14);
- PCI_INT(bus_pci, 0x7, 0x3, 0x15);
- }
-
- /* PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, 0x10);
- /* PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, 0x11);
- /* PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, 0x12);
- /* PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, 0x13);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/lippert/toucan-af/Kconfig b/src/mainboard/lippert/toucan-af/Kconfig
index b62da2e..e97099b 100644
--- a/src/mainboard/lippert/toucan-af/Kconfig
+++ b/src/mainboard/lippert/toucan-af/Kconfig
@@ -29,7 +29,6 @@
select SUPERIO_WINBOND_W83627DHG
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
# This erases 28 KB and writes 10 KB register dumps to SPI flash on every
# boot, wasting 3 s and causing wear! Therefore disable S3 for now.
#select HAVE_ACPI_RESUME
diff --git a/src/mainboard/lippert/toucan-af/mptable.c b/src/mainboard/lippert/toucan-af/mptable.c
deleted file mode 100644
index 78b8ec2..0000000
--- a/src/mainboard/lippert/toucan-af/mptable.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <string.h>
-#include <stdint.h>
-#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
- memcpy(mc->mpc_oem, "AMD ", 8);
-
- smp_write_processors(mc);
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
-
- /* APU Internal Graphic Device*/
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
- //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
- /* Southbridge HD Audio: */
- PCI_INT(0x0, 0x14, 0x2, 0x12);
-
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); /* USB */
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
- /* on board NIC & Slot PCIE. */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0. */
- PCI_INT(bus_pci, 0x5, 0x0, 0x14);
- PCI_INT(bus_pci, 0x5, 0x1, 0x15);
- PCI_INT(bus_pci, 0x5, 0x2, 0x16);
- PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_pci, 0x6, 0x0, 0x15);
- PCI_INT(bus_pci, 0x6, 0x1, 0x16);
- PCI_INT(bus_pci, 0x6, 0x2, 0x17);
- PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_pci, 0x7, 0x0, 0x16);
- PCI_INT(bus_pci, 0x7, 0x1, 0x17);
- PCI_INT(bus_pci, 0x7, 0x2, 0x14);
- PCI_INT(bus_pci, 0x7, 0x3, 0x15);
- }
-
- /* PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, 0x10);
- /* PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, 0x11);
- /* PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, 0x12);
- /* PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, 0x13);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/msi/ms7721/Kconfig b/src/mainboard/msi/ms7721/Kconfig
index 1fee747..b57bc48 100644
--- a/src/mainboard/msi/ms7721/Kconfig
+++ b/src/mainboard/msi/ms7721/Kconfig
@@ -25,7 +25,6 @@
select SOUTHBRIDGE_AMD_AGESA_HUDSON
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
select SUPERIO_FINTEK_F71869AD
select BOARD_ROMSIZE_KB_8192
diff --git a/src/mainboard/msi/ms7721/mptable.c b/src/mainboard/msi/ms7721/mptable.c
deleted file mode 100644
index fd55eda..0000000
--- a/src/mainboard/msi/ms7721/mptable.c
+++ /dev/null
@@ -1,150 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/ioapic.h>
-#include <arch/smp/mpspec.h>
-#include <cpu/x86/lapic.h>
-#include <stdint.h>
-#include <string.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <southbridge/amd/agesa/hudson/hudson.h>
-
-static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
-{
- mc->mpc_length += length;
- mc->mpc_entry_count++;
-}
-
-static void my_smp_write_bus(struct mp_config_table *mc,
- unsigned char id, const char *bustype)
-{
- struct mpc_config_bus *mpc;
- mpc = smp_next_mpc_entry(mc);
- memset(mpc, '\0', sizeof(*mpc));
- mpc->mpc_type = MP_BUS;
- mpc->mpc_busid = id;
- memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
- smp_add_mpc_entry(mc, sizeof(*mpc));
-}
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
- memcpy(mc->mpc_oem, "AMD ", 8);
-
- smp_write_processors(mc);
-
- //mptable_write_buses(mc, NULL, &bus_isa);
- my_smp_write_bus(mc, 0, "PCI ");
- my_smp_write_bus(mc, 1, "PCI ");
- bus_isa = 0x02;
- my_smp_write_bus(mc, bus_isa, "ISA ");
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
-
- /* IOMMU */
- PCI_INT(0x0, 0x0, 0x0, 0x10);
- PCI_INT(0x0, 0x0, 0x1, 0x11);
- PCI_INT(0x0, 0x0, 0x2, 0x12);
- PCI_INT(0x0, 0x0, 0x3, 0x13);
-
- /* Internal VGA */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
- /* SMBUS */
- PCI_INT(0x0, 0x14, 0x0, 0x10);
-
- /* HD Audio */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
-
- /* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
- /* on board NIC & Slot PCIE. */
-
- /* PCI slots */
- struct device *dev = pcidev_on_root(0x14, 4);
- if (dev && dev->enabled) {
- u8 bus_pci = dev->link_list->secondary;
- /* PCI_SLOT 0. */
- PCI_INT(bus_pci, 0x5, 0x0, 0x14);
- PCI_INT(bus_pci, 0x5, 0x1, 0x15);
- PCI_INT(bus_pci, 0x5, 0x2, 0x16);
- PCI_INT(bus_pci, 0x5, 0x3, 0x17);
- }
-
- /* PCIe Lan*/
- PCI_INT(0x0, 0x06, 0x0, 0x13);
-
- /* FCH PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, 0x10);
- /* FCH PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, 0x11);
- /* FCH PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, 0x12);
- /* FCH PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, 0x13);
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig
index 3396845..9871051 100644
--- a/src/mainboard/pcengines/apu1/Kconfig
+++ b/src/mainboard/pcengines/apu1/Kconfig
@@ -23,7 +23,6 @@
select SOUTHBRIDGE_AMD_CIMX_SB800
select SUPERIO_NUVOTON_NCT5104D
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select HAVE_OPTION_TABLE
diff --git a/src/mainboard/pcengines/apu1/mptable.c b/src/mainboard/pcengines/apu1/mptable.c
deleted file mode 100644
index 89e5dfc..0000000
--- a/src/mainboard/pcengines/apu1/mptable.c
+++ /dev/null
@@ -1,133 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- * Copyright (C) 2014 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <stdint.h>
-#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <drivers/generic/ioapic/chip.h>
-#include <arch/ioapic.h>
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- /* Initialize the MP_Table */
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- /*
- * Type 0: Processor Entries:
- * LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
- * CPU Signature (Stepping, Model, Family),
- * Feature Flags
- */
- smp_write_processors(mc);
-
- /*
- * Type 1: Bus Entries:
- * Bus ID, Bus Type
- */
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /*
- * Type 2: I/O APICs:
- * APIC ID, Version, APIC Flags:EN, Address
- */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /*
- * Type 3: I/O Interrupt Table Entries:
- * Int Type, Int Polarity, Int Level, Source Bus ID,
- * Source Bus IRQ, Dest APIC ID, Dest PIN#
- */
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
-
- /* APU Internal Graphic Device */
- PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]);
- PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]);
-
- /* SMBUS / ACPI */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]);
-
- /* Southbridge HD Audio */
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]);
-
- /* LPC */
- PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
- PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
- PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]);
- PCI_INT(0x0, 0x14, 0x5, intr_data_ptr[PIRQ_OHCI4]);
-
- /* IDE */
- PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_IDE]);
-
- /* SATA */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
-
- /* on board NIC & Slot PCIE */
- PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */
- PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */
- PCI_INT(0x3, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */
- PCI_INT(0x4, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */
-
- /* PCIe PortA */
- PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */
- /* PCIe PortB */
- PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */
- /* PCIe PortC */
- PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */
- /* PCIe PortD */
- PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */
-
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
- IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig
index 8c713e5..604d490 100644
--- a/src/mainboard/pcengines/apu2/Kconfig
+++ b/src/mainboard/pcengines/apu2/Kconfig
@@ -26,7 +26,6 @@
select DEFAULT_POST_ON_LPC
select SUPERIO_NUVOTON_NCT5104D
select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_8192
select USE_BLOBS
diff --git a/src/mainboard/pcengines/apu2/mptable.c b/src/mainboard/pcengines/apu2/mptable.c
deleted file mode 100644
index 772ee31..0000000
--- a/src/mainboard/pcengines/apu2/mptable.c
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- * Copyright (C) 2014 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <stdint.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- /* Initialize the MP_Table */
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- /*
- * Type 0: Processor Entries:
- * LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
- * CPU Signature (Stepping, Model, Family),
- * Feature Flags
- */
- smp_write_processors(mc);
-
- /*
- * Type 1: Bus Entries:
- * Bus ID, Bus Type
- */
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /*
- * Type 2: I/O APICs:
- * APIC ID, Version, APIC Flags:EN, Address
- */
- u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
- /*
- * Type 3: I/O Interrupt Table Entries:
- * Int Type, Int Polarity, Int Level, Source Bus ID,
- * Source Bus IRQ, Dest APIC ID, Dest PIN#
- */
-
- mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
- /* PCI interrupts are level triggered, and are
- * associated with a specific bus/device/function tuple.
- */
-#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
-
-
- /* SMBUS / ACPI */
- PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]);
-
- /* SD card */
- PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_SD]);
-
- /* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[PIRQ_EHCI1]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[PIRQ_EHCI2]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[PIRQ_EHCI3]);
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_OHCI4]);
-
- /* SATA */
- PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
-
- /* on board NIC & Slot PCIE */
- PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]);
- PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]);
-
-
- /* GPP0 */
- PCI_INT(0x0, 0x2, 0x0, 0x10); // Network 3
- /* GPP1 */
- PCI_INT(0x0, 0x2, 0x1, 0x11); // Network 2
- /* GPP2 */
- PCI_INT(0x0, 0x2, 0x2, 0x12); // Network 1
- /* GPP3 */
- PCI_INT(0x0, 0x2, 0x3, 0x13); // mPCI
- /* GPP4 */
- PCI_INT(0x0, 0x2, 0x4, 0x14); // mPCI
-
- IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
- IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
-
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */
- return (unsigned long)smp_write_config_table(v);
-}
--
To view, visit https://review.coreboot.org/c/coreboot/+/38313
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Idd13b8b006fce7383f3f73c3c0a5d51a71c0155b
Gerrit-Change-Number: 38313
Gerrit-PatchSet: 1
Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Gerrit-MessageType: newchange
2 days, 4 hours
- 4
- 19
Change in coreboot[master]: soc/intel/common: Add romstage common stage file
by Bernardo Perez Priego (Code Review)
Bernardo Perez Priego has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37628 )
Change subject: soc/intel/common: Add romstage common stage file
......................................................................
soc/intel/common: Add romstage common stage file
This patch will ensures all intel soc is using common stage
files to make coreboot design flow align across all socs.
CPU, SA, PCH, MCH programming sequence might be different between
socs but the function call should route from same location across
all soc.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com>
Change-Id: I06d43ac29f5e87ce731a470e5e145adea07ece4c
---
M src/cpu/intel/car/romstage.c
A src/soc/intel/common/basecode/include/intelbasecode/romstage.h
A src/soc/intel/common/basecode/romstage/Makefile.inc
A src/soc/intel/common/basecode/romstage/romstage.c
4 files changed, 162 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/37628/1
diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c
index 1f8eb9a..55d3c9d 100644
--- a/src/cpu/intel/car/romstage.c
+++ b/src/cpu/intel/car/romstage.c
@@ -52,9 +52,6 @@
for (i = 0; i < num_guards; i++)
stack_base[i] = stack_guard;
- if (CONFIG(VBOOT_EARLY_EC_SYNC))
- vboot_sync_ec();
-
mainboard_romstage_entry();
/* Check the stack. */
@@ -64,9 +61,6 @@
printk(BIOS_DEBUG, "Smashed stack detected in romstage!\n");
}
- if (CONFIG(SMM_TSEG))
- smm_list_regions();
-
prepare_and_run_postcar(&early_mtrrs);
/* We do not return here. */
}
diff --git a/src/soc/intel/common/basecode/include/intelbasecode/romstage.h b/src/soc/intel/common/basecode/include/intelbasecode/romstage.h
new file mode 100644
index 0000000..0cebbbf
--- /dev/null
+++ b/src/soc/intel/common/basecode/include/intelbasecode/romstage.h
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOC_INTEL_COMMON_BASECODE_ROMSTAGE_H
+#define SOC_INTEL_COMMON_BASECODE_ROMSTAGE_H
+
+#include <stddef.h>
+#include <stdint.h>
+#include <fsp/soc_binding.h>
+
+struct romstage_ops {
+ void (*soc_early_init)(void);
+ void (*soc_init)(void);
+ void (*pch_early_init)(void);
+ void (*pch_init)(void);
+ void (*cpu_early_init)(void);
+ void (*cpu_init)(void);
+ bool (*is_s3wake)(void);
+ void (*soc_mem_init_params)(FSP_M_CONFIG *mupd);
+};
+
+/* SoC Override function */
+struct romstage_ops *soc_get_ops(void);
+
+#endif
diff --git a/src/soc/intel/common/basecode/romstage/Makefile.inc b/src/soc/intel/common/basecode/romstage/Makefile.inc
new file mode 100644
index 0000000..29763fb
--- /dev/null
+++ b/src/soc/intel/common/basecode/romstage/Makefile.inc
@@ -0,0 +1 @@
+romstage-y += romstage.c
diff --git a/src/soc/intel/common/basecode/romstage/romstage.c b/src/soc/intel/common/basecode/romstage/romstage.c
new file mode 100644
index 0000000..55c4ab5
--- /dev/null
+++ b/src/soc/intel/common/basecode/romstage/romstage.c
@@ -0,0 +1,124 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/early_variables.h>
+#include <romstage_common.h>
+#include <cpu/x86/pae.h>
+#include <intelbasecode/romstage.h>
+#include <intelblocks/systemagent.h>
+#include <soc/iomap.h>
+#include <soc/romstage.h>
+
+static const struct romstage_ops s_romstage_ops;
+
+__weak struct romstage_ops *soc_get_ops(void)
+{
+ return (struct romstage_ops *)&s_romstage_ops;
+}
+
+void romstage_early_init(void)
+{
+ struct romstage_ops *rs_ops = soc_get_ops();
+
+ rs_ops->soc_early_init();
+ rs_ops->pch_early_init();
+ rs_ops->cpu_early_init();
+}
+
+void romstage_init(void)
+{
+ struct romstage_ops *rs_ops = soc_get_ops();
+
+ rs_ops->soc_init();
+ rs_ops->pch_init();
+ rs_ops->cpu_init();
+}
+
+void romstage_cmn_soc_early_init(void)
+{
+ systemagent_early_init();
+ heci_init(HECI1_BASE_ADDRESS);
+}
+
+void romstage_cmn_soc_init(void)
+{
+}
+
+void romstage_cmn_pch_early_init(void)
+{
+}
+
+void romstage_cmn_cpu_early_init(void)
+{
+}
+
+void romstage_cmn_pch_init(void)
+{
+}
+
+void romstage_cmn_cpu_init(void)
+{
+}
+
+bool romstage_cmn_is_s3wake(void)
+{
+ struct chipset_power_state *ps = pmc_get_power_state();
+ return pmc_fill_power_state(ps) == ACPI_S3;
+}
+
+void romstage_cmn_soc_mem_init_param(FSP_M_CONFIG *m_cfg)
+{
+}
+
+static const struct romstage_ops s_romstage_ops = {
+ &romstage_cmn_soc_early_init,
+ &romstage_cmn_soc_init,
+ &romstage_cmn_pch_early_init,
+ &romstage_cmn_pch_init,
+ &romstage_cmn_cpu_early_init,
+ &romstage_cmn_cpu_init,
+ &romstage_cmn_is_s3wake,
+ &romstage_cmn_mb_mem_init_param,
+ &romstage_cmn_soc_mem_init_param
+};
+
+/*
+ Main romstage function
+*/
+asmlinkage void mainboard_romstage_entry(void)
+{
+ if (CONFIG(VBOOT_EARLY_EC_SYNC))
+ vboot_sync_ec(rs_ops->fill_power_state());
+
+ romstage_early_init();
+ romstage_init();
+ fsp_memory_init(rs_ops->is_s3wake());
+
+ if (CONFIG(SMM_TSEG))
+ smm_list_regions();
+}
+
+/*
+ Callback function for FSP memory initialization
+*/
+void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
+{
+ struct romstage_ops *rs_ops = soc_get_ops();
+
+ FSP_M_CONFIG *m_cfg;
+ rs_ops->soc_mem_init_params(m_cfg);
+ mainboard_memory_init_params(m_cfg);
+}
+
--
To view, visit https://review.coreboot.org/c/coreboot/+/37628
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I06d43ac29f5e87ce731a470e5e145adea07ece4c
Gerrit-Change-Number: 37628
Gerrit-PatchSet: 1
Gerrit-Owner: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com>
Gerrit-MessageType: newchange
2 days, 8 hours
- 4
- 12
Change in coreboot[master]: [WIP]security/intel: Add option to eanble SMM flash access only
by Patrick Rudolph (Code Review)
Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40830 )
Change subject: [WIP]security/intel: Add option to eanble SMM flash access only
......................................................................
[WIP]security/intel: Add option to eanble SMM flash access only
On platforms where the boot media can be updated externally, for e.g.
using a BMC, add the possibility to enable writes in SMM only.
This allows to protect the BIOS region even without the use of vboot, but
keeps the SMMSTORE working for the use in payloads.
UNTESTED.
Change-Id: I157db885b5f1d0f74009ede6fb2342b20d9429fa
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/security/lockdown/Kconfig
M src/soc/intel/common/pch/lockdown/lockdown.c
M src/southbridge/intel/bd82x6x/lpc.c
M src/southbridge/intel/common/spi.c
M src/southbridge/intel/common/spi.h
M src/southbridge/intel/ibexpeak/lpc.c
M src/southbridge/intel/lynxpoint/lpc.c
M src/southbridge/intel/lynxpoint/smi.c
8 files changed, 52 insertions(+), 43 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/40830/1
diff --git a/src/security/lockdown/Kconfig b/src/security/lockdown/Kconfig
index d24c5e5..dbe6840 100644
--- a/src/security/lockdown/Kconfig
+++ b/src/security/lockdown/Kconfig
@@ -99,3 +99,13 @@
possible. This option prevents using write protecting facilities in
ramstage, like the MRC cache for example.
Use this option if you don't trust code running after verstage.
+
+config BOOTMEDIA_SMM_BWP
+ bool "Boot media only writable in SMM"
+ depends on ARCH_X86
+ depends on HAVE_SMI_HANDLER
+ select SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE if SOC_INTEL_COMMON_BLOCK
+ help
+ Enable flash writes in SMM only. Select this if you want to secure
+ the SMM_STORE and don't need to update coreboot using the
+ internal controller.
diff --git a/src/soc/intel/common/pch/lockdown/lockdown.c b/src/soc/intel/common/pch/lockdown/lockdown.c
index a00e5c0..768c4cd 100644
--- a/src/soc/intel/common/pch/lockdown/lockdown.c
+++ b/src/soc/intel/common/pch/lockdown/lockdown.c
@@ -62,6 +62,12 @@
/* BIOS Interface Lock */
fast_spi_set_bios_interface_lock_down();
+ /* Only allow writes in SMM */
+ if (CONFIG(BOOTMEDIA_SMM_BWP)) {
+ fast_spi_set_eiss();
+ fast_spi_enable_wp();
+ }
+
/* BIOS Lock */
fast_spi_set_lock_enable();
}
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index 278e90a..78bfb39 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -416,16 +416,6 @@
}
}
-static void pch_disable_smm_only_flashing(struct device *dev)
-{
- u8 reg8;
-
- printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... ");
- reg8 = pci_read_config8(dev, BIOS_CNTL);
- reg8 &= ~(1 << 5);
- pci_write_config8(dev, BIOS_CNTL, reg8);
-}
-
static void pch_fixups(struct device *dev)
{
u8 gen_pmcon_2;
@@ -579,8 +569,6 @@
/* Interrupt 9 should be level triggered (SCI) */
i8259_configure_irq_trigger(9, 1);
- pch_disable_smm_only_flashing(dev);
-
pch_set_acpi_mode();
pch_fixups(dev);
diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c
index 5e967af..253d33f 100644
--- a/src/southbridge/intel/common/spi.c
+++ b/src/southbridge/intel/common/spi.c
@@ -35,6 +35,10 @@
#define HSFC_FCYCLE (0x3 << HSFC_FCYCLE_OFF)
#define HSFC_FDBC_OFF 8 /* 8-13: Flash Data Byte Count */
#define HSFC_FDBC (0x3f << HSFC_FDBC_OFF)
+#define BIOS_CNTL 0xdc
+#define LPC_BC_WE (1 << 0) /* WE */
+#define LPC_BC_LE (1 << 1) /* LE */
+#define LPC_BC_EISS (1 << 5) /* EISS */
static int spi_is_multichip(void);
@@ -293,7 +297,6 @@
void spi_init(void)
{
- uint8_t bios_cntl;
struct ich9_spi_regs *ich9_spi;
struct ich7_spi_regs *ich7_spi;
uint16_t hsfs;
@@ -345,10 +348,7 @@
if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX) || CONFIG(SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9)) {
/* Disable the BIOS write protect so write commands are allowed. */
- bios_cntl = pci_read_config8(dev, 0xdc);
- /* Deassert SMM BIOS Write Protect Disable. */
- bios_cntl &= ~(1 << 5);
- pci_write_config8(dev, 0xdc, bios_cntl | 0x1);
+ spi_smm_only_flashing(0);
}
}
@@ -1108,12 +1108,35 @@
writeb_(spi_config->ops[i].op, &cntlr.opmenu[i]);
}
writew_(optype, cntlr.optype);
+
+ spi_smm_only_flashing(CONFIG(BOOTMEDIA_SMM_BWP));
}
__weak void intel_southbridge_override_spi(struct intel_swseq_spi_config *spi_config)
{
}
+void spi_smm_only_flashing(bool enable)
+{
+ pci_devfn_t dev = PCI_DEV(0, 31, 0);
+ u8 reg8 = pci_read_config8(dev, BIOS_CNTL);
+
+ if (reg8 & LPC_BC_LE)
+ return;
+
+ if (enable) {
+ reg8 |= LPC_BC_EISS;
+ reg8 &= ~LPC_BC_WE;
+ } else {
+ reg8 &= ~LPC_BC_EISS;
+ reg8 |= LPC_BC_WE;
+ }
+ pci_write_config8(dev, BIOS_CNTL, reg8);
+
+ printk(BIOS_SPEW, "BIOS updates outside of SMM %s\n",
+ enable ? "enabled" : "disabled");
+}
+
static const struct spi_ctrlr spi_ctrlr = {
.xfer_vector = xfer_vectors,
.max_xfer_size = member_size(struct ich9_spi_regs, fdata),
diff --git a/src/southbridge/intel/common/spi.h b/src/southbridge/intel/common/spi.h
index 3b8410c..ad1cb27 100644
--- a/src/southbridge/intel/common/spi.h
+++ b/src/southbridge/intel/common/spi.h
@@ -32,6 +32,7 @@
struct intel_spi_op ops[8];
};
+void spi_smm_only_flashing(bool enable);
void spi_finalize_ops(void);
void intel_southbridge_override_spi(struct intel_swseq_spi_config *spi_config);
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c
index 395919e..67c03fa 100644
--- a/src/southbridge/intel/ibexpeak/lpc.c
+++ b/src/southbridge/intel/ibexpeak/lpc.c
@@ -420,16 +420,6 @@
}
}
-static void pch_disable_smm_only_flashing(struct device *dev)
-{
- u8 reg8;
-
- printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... ");
- reg8 = pci_read_config8(dev, BIOS_CNTL);
- reg8 &= ~(1 << 5);
- pci_write_config8(dev, BIOS_CNTL, reg8);
-}
-
static void pch_fixups(struct device *dev)
{
/*
@@ -482,8 +472,6 @@
/* Interrupt 9 should be level triggered (SCI) */
i8259_configure_irq_trigger(9, 1);
- pch_disable_smm_only_flashing(dev);
-
pch_set_acpi_mode();
pch_fixups(dev);
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index d9ef5cc..dafb901 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -481,16 +481,6 @@
}
}
-static void pch_disable_smm_only_flashing(struct device *dev)
-{
- u8 reg8;
-
- printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... ");
- reg8 = pci_read_config8(dev, BIOS_CNTL);
- reg8 &= ~(1 << 5);
- pci_write_config8(dev, BIOS_CNTL, reg8);
-}
-
static void pch_fixups(struct device *dev)
{
u8 gen_pmcon_2;
@@ -549,8 +539,6 @@
/* Interrupt 9 should be level triggered (SCI) */
i8259_configure_irq_trigger(9, 1);
- pch_disable_smm_only_flashing(dev);
-
pch_set_acpi_mode();
pch_fixups(dev);
diff --git a/src/southbridge/intel/lynxpoint/smi.c b/src/southbridge/intel/lynxpoint/smi.c
index 05b5bb5..82e96f3 100644
--- a/src/southbridge/intel/lynxpoint/smi.c
+++ b/src/southbridge/intel/lynxpoint/smi.c
@@ -40,6 +40,8 @@
void smm_southbridge_enable_smi(void)
{
+ u32 mask;
+
printk(BIOS_DEBUG, "Enabling SMIs.\n");
/* Configure events */
enable_pm1(PWRBTN_EN | GBL_EN);
@@ -49,11 +51,14 @@
* - on APMC writes (io 0xb2)
* - on writes to SLP_EN (sleep states)
* - on writes to GBL_RLS (bios commands)
+ * - on TCO events
* No SMIs:
* - on microcontroller writes (io 0x62/0x66)
- * - on TCO events
*/
- enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS);
+ mask = APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS;
+ if (CONFIG(BOOTMEDIA_SMM_BWP))
+ mask |= TCO_EN;
+ enable_smi(mask);
}
static void __unused southbridge_trigger_smi(void)
--
To view, visit https://review.coreboot.org/c/coreboot/+/40830
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I157db885b5f1d0f74009ede6fb2342b20d9429fa
Gerrit-Change-Number: 40830
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Gerrit-MessageType: newchange
3 days, 13 hours
- 3
- 23
Change in coreboot[master]: soc/intel/common/block/smbus: Add config to use ACPI
by Maxim Polyakov (Code Review)
Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44865 )
Change subject: soc/intel/common/block/smbus: Add config to use ACPI
......................................................................
soc/intel/common/block/smbus: Add config to use ACPI
Change-Id: Iafa7d40fc21e62f99dbdc2001ab6525a2a77ff50
Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com>
---
M src/soc/intel/common/block/smbus/Kconfig
1 file changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/44865/1
diff --git a/src/soc/intel/common/block/smbus/Kconfig b/src/soc/intel/common/block/smbus/Kconfig
index fe940cc..818200e 100644
--- a/src/soc/intel/common/block/smbus/Kconfig
+++ b/src/soc/intel/common/block/smbus/Kconfig
@@ -3,6 +3,13 @@
help
Intel Processor common SMBus support
+config SOC_INTEL_COMMON_BLOCK_SMBUS_ACPI_DRIVER
+ bool
+ default n
+ depends on SOC_INTEL_COMMON_BLOCK_SMBUS
+ help
+ Intel Processor SMBus ACPI driver support
+
config SOC_INTEL_COMMON_BLOCK_TCO
bool
help
--
To view, visit https://review.coreboot.org/c/coreboot/+/44865
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Iafa7d40fc21e62f99dbdc2001ab6525a2a77ff50
Gerrit-Change-Number: 44865
Gerrit-PatchSet: 1
Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-MessageType: newchange
3 days, 17 hours
- 4
- 5
Change in coreboot[master]: mb/asus/p8z77-m: New board
by Keith Hui (Code Review)
Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38988 )
Change subject: mb/asus/p8z77-m: New board
......................................................................
mb/asus/p8z77-m: New board
Constructed out of a mix of autoport results, p8z77-m_pro, and
inteltool/superiotool dumps.
Does not yet boot. Submitting for eyeballs and help.
Change-Id: If756e791ddce747cb1706414be8e41e83f88922b
Signed-off-by: Keith Hui <buurin(a)gmail.com>
---
A src/mainboard/asus/p8z77-m/Kconfig
A src/mainboard/asus/p8z77-m/Kconfig.name
A src/mainboard/asus/p8z77-m/Makefile.inc
A src/mainboard/asus/p8z77-m/acpi/ec.asl
A src/mainboard/asus/p8z77-m/acpi/platform.asl
A src/mainboard/asus/p8z77-m/acpi/superio.asl
A src/mainboard/asus/p8z77-m/acpi_tables.c
A src/mainboard/asus/p8z77-m/cmos.default
A src/mainboard/asus/p8z77-m/cmos.layout
A src/mainboard/asus/p8z77-m/data.vbt
A src/mainboard/asus/p8z77-m/devicetree.cb
A src/mainboard/asus/p8z77-m/dsdt.asl
A src/mainboard/asus/p8z77-m/early_init.c
A src/mainboard/asus/p8z77-m/gma-mainboard.ads
A src/mainboard/asus/p8z77-m/gpio.c
A src/mainboard/asus/p8z77-m/hda_verb.c
A src/mainboard/asus/p8z77-m/mainboard.c
17 files changed, 969 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/38988/1
diff --git a/src/mainboard/asus/p8z77-m/Kconfig b/src/mainboard/asus/p8z77-m/Kconfig
new file mode 100644
index 0000000..260597d
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/Kconfig
@@ -0,0 +1,45 @@
+##
+## This file is part of the coreboot project.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+if BOARD_ASUS_P8Z77_M
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select BOARD_ROMSIZE_KB_8192
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select INTEL_INT15
+ select NORTHBRIDGE_INTEL_SANDYBRIDGE
+ select SERIRQ_CONTINUOUS_MODE
+ select SOUTHBRIDGE_INTEL_C216
+ select MAINBOARD_HAS_LPC_TPM
+ select MAINBOARD_HAS_TPM1
+ select HAVE_OPTION_TABLE
+ select HAVE_CMOS_DEFAULT
+ select MAINBOARD_HAS_LIBGFXINIT
+ select INTEL_GMA_HAVE_VBT
+ select SUPERIO_NUVOTON_NCT6779D
+
+config MAINBOARD_DIR
+ string
+ default "asus/p8z77-m"
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "P8Z77-M"
+
+config MAX_CPUS
+ int
+ default 8
+
+endif
diff --git a/src/mainboard/asus/p8z77-m/Kconfig.name b/src/mainboard/asus/p8z77-m/Kconfig.name
new file mode 100644
index 0000000..a797a5b
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/Kconfig.name
@@ -0,0 +1,15 @@
+##
+## This file is part of the coreboot project.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+config BOARD_ASUS_P8Z77_M
+ bool "P8Z77-M"
diff --git a/src/mainboard/asus/p8z77-m/Makefile.inc b/src/mainboard/asus/p8z77-m/Makefile.inc
new file mode 100644
index 0000000..a12efbb
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/Makefile.inc
@@ -0,0 +1,20 @@
+##
+## This file is part of the coreboot project.
+##
+## This program is free software: you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation, either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+bootblock-y += gpio.c
+romstage-y += gpio.c
+
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+bootblock-y += early_init.c
+romstage-y += early_init.c
diff --git a/src/mainboard/asus/p8z77-m/acpi/ec.asl b/src/mainboard/asus/p8z77-m/acpi/ec.asl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/acpi/ec.asl
diff --git a/src/mainboard/asus/p8z77-m/acpi/platform.asl b/src/mainboard/asus/p8z77-m/acpi/platform.asl
new file mode 100644
index 0000000..d2cad26
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/acpi/platform.asl
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* This file is part of the coreboot project. */
+
+Method(_WAK,1)
+{
+ Return(Package(){0,0})
+}
+
+Method(_PTS,1)
+{
+}
diff --git a/src/mainboard/asus/p8z77-m/acpi/superio.asl b/src/mainboard/asus/p8z77-m/acpi/superio.asl
new file mode 100644
index 0000000..f2b35ba
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/acpi/superio.asl
@@ -0,0 +1 @@
+#include <drivers/pc80/pc/ps2_controller.asl>
diff --git a/src/mainboard/asus/p8z77-m/acpi_tables.c b/src/mainboard/asus/p8z77-m/acpi_tables.c
new file mode 100644
index 0000000..9c22f19
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/acpi_tables.c
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Vlado Cibic <vladocb(a)protonmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/bd82x6x/nvs.h>
+
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+ /* critical temp that will shutdown the pc == 95C degrees */
+ gnvs->tcrt = 95;
+
+ /* temp to start throttling the cpu == 85C */
+ gnvs->tpsv = 85;
+}
diff --git a/src/mainboard/asus/p8z77-m/cmos.default b/src/mainboard/asus/p8z77-m/cmos.default
new file mode 100644
index 0000000..725ab98
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/cmos.default
@@ -0,0 +1,24 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2019 Vlado Cibic <vladocb(a)protonmail.com>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+boot_option=Fallback
+debug_level=Debug
+gfx_uma_size=224M
+nmi=Enable
+sata_mode=AHCI
+#usb3_xxxx options are only used with MRC blob, ignored else
+usb3_mode=Enable
+usb3_drv=Enable
+usb3_streams=Enable
diff --git a/src/mainboard/asus/p8z77-m/cmos.layout b/src/mainboard/asus/p8z77-m/cmos.layout
new file mode 100644
index 0000000..da29d1c
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/cmos.layout
@@ -0,0 +1,185 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2019 Vlado Cibic <vladocb(a)protonmail.com>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+# Status Register A
+# -----------------------------------------------------------------
+# Status Register B
+# -----------------------------------------------------------------
+# Status Register C
+#96 4 r 0 status_c_rsvd
+#100 1 r 0 uf_flag
+#101 1 r 0 af_flag
+#102 1 r 0 pf_flag
+#103 1 r 0 irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104 7 r 0 status_d_rsvd
+#111 1 r 0 valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112 8 r 0 diag_rsvd1
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+#120 264 r 0 unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 3 boot_option
+388 4 h 0 reboot_counter
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+#392 3 r 0 unused
+395 4 e 4 debug_level
+#399 1 r 0 unused
+#400 8 r 0 reserved for century byte
+
+# -----------------------------------------------------------------
+# coreboot config options: southbridge
+
+# Non Maskable Interrupt(NMI) support, which is an interrupt that may
+# occur on a RAM or unrecoverable error.
+408 1 e 1 nmi
+
+409 2 e 5 power_on_after_fail
+411 1 e 6 sata_mode
+
+# -----------------------------------------------------------------
+# coreboot config options: northbridge
+
+# gfx_uma_size
+# Quantity of shared video memory the IGP can use
+#
+416 5 e 7 gfx_uma_size
+
+# -----------------------------------------------------------------
+# coreboot config options: usb3
+
+# usb3_mode
+# Controls how the motherboard's USB3 ports act at boot time
+421 2 e 8 usb3_mode
+
+# usb3_drv
+# Load (or not) pre-OS xHCI USB3 bios driver
+#
+423 1 e 1 usb3_drv
+
+# usb3_streams
+# Streams can provide more speed (as they can use 64Kb packets),
+# but they might cause incompatibilities with some devices.
+#
+424 1 e 1 usb3_streams
+
+# -----------------------------------------------------------------
+# Sandy/Ivy Bridge MRC Scrambler Seed values
+# note: MUST NOT be covered by checksum!
+464 32 r 0 mrc_scrambler_seed
+496 32 r 0 mrc_scrambler_seed_s3
+528 16 r 0 mrc_scrambler_seed_chk
+
+# -----------------------------------------------------------------
+# coreboot config options: check sums
+544 16 h 0 check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+#ID value text
+
+# Generic on/off enum
+1 0 Disable
+1 1 Enable
+
+# boot_option
+3 0 Fallback
+3 1 Normal
+
+# debug_level
+4 0 Emergency
+4 1 Alert
+4 2 Critical
+4 3 Error
+4 4 Warning
+4 5 Notice
+4 6 Info
+4 7 Debug
+4 8 Spew
+
+# power_on_after_fail
+5 0 Disable
+5 1 Enable
+5 2 Keep
+
+# sata_mode
+6 0 AHCI
+6 1 Compatible
+
+# gfx_uma_size (Intel IGP Video RAM size)
+7 0 32M
+7 1 64M
+7 2 96M
+7 3 128M
+7 4 160M
+7 5 192M
+7 6 224M
+7 7 256M
+7 8 288M
+7 9 320M
+7 10 352M
+7 11 384M
+7 12 416M
+7 13 448M
+7 14 480M
+7 15 512M
+7 16 544M
+7 17 576M
+7 18 608M
+7 19 640M
+7 20 672M
+7 21 704M
+7 22 736M
+7 23 768M
+7 24 800M
+7 25 832M
+7 26 864M
+7 27 896M
+7 28 928M
+7 29 960M
+7 30 992M
+
+# usb3_mode
+# Disable = Use the port always as USB 2.0 for compatibility
+# Enable = Use the port always as USB 3.0 for speed
+# Auto = Initialize the port as USB 2.0, until the OS loads
+# xHCI USB 3.0 driver
+# SmartAuto = Same as Auto but, if the OS loads the xHCI USB 3.0 driver
+# and the computer is reset, keep the USB 3.0 mode.
+#
+8 0 Disable
+8 1 Enable
+8 2 Auto
+8 3 SmartAuto
+
+# -----------------------------------------------------------------
+# <startBit[must be byte-aligned]> <endBit[must be byte aligned]>
+# <bit where to start storing checksum[must be 16bits-aligned]>
+checksums
+
+checksum 392 431 544
diff --git a/src/mainboard/asus/p8z77-m/data.vbt b/src/mainboard/asus/p8z77-m/data.vbt
new file mode 100644
index 0000000..26ab42d
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/data.vbt
Binary files differ
diff --git a/src/mainboard/asus/p8z77-m/devicetree.cb b/src/mainboard/asus/p8z77-m/devicetree.cb
new file mode 100644
index 0000000..03a20b9
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/devicetree.cb
@@ -0,0 +1,108 @@
+##
+## This file is part of the coreboot project.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did
+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }"
+ register "gfx.ndid" = "3"
+ device cpu_cluster 0x0 on
+ chip cpu/intel/model_206ax
+ register "c1_acpower" = "1"
+ register "c1_battery" = "1"
+ register "c2_acpower" = "3"
+ register "c2_battery" = "3"
+ register "c3_acpower" = "5"
+ register "c3_battery" = "5"
+ device lapic 0x0 on end
+ device lapic 0xacac off end
+ end
+ end
+ device domain 0x0 on
+ subsystemid 0x1043 0x84ca inherit
+ device pci 00.0 on end # Host bridge
+ device pci 01.0 on end # PCIe Bridge for discrete graphics
+ device pci 02.0 on end # Internal graphics VGA controller
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+ register "c2_latency" = "0x0065"
+ register "gen1_dec" = "0x000c0291"
+ register "gen4_dec" = "0x00000000"
+ register "pcie_port_coalesce" = "1"
+ register "sata_interface_speed_support" = "0x3" # 0x3=SATAIII
+ register "sata_port_map" = "0x3f"
+ register "spi_lvscc" = "0x2005"
+ register "spi_uvscc" = "0x2005"
+ register "superspeed_capable_ports" = "0x0000000f"
+ register "xhci_overcurrent_mapping" = "0x00000c03"
+ register "xhci_switchable_ports" = "0x0000000f" # the 4 ports
+
+ device pci 14.0 on end # USB 3.0 Controller
+ device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT
+ device pci 19.0 off end # Intel Gigabit Ethernet
+ device pci 1a.0 on end # USB2 EHCI #2
+ device pci 1b.0 on end # High Definition Audio Audio controller
+ device pci 1c.0 on end # PCIe Port #1
+ device pci 1c.1 off end # PCIe Port #2
+ device pci 1c.2 off end # PCIe Port #3
+ device pci 1c.3 off end # PCIe Port #4
+ device pci 1c.4 off end # PCIe Port #5
+ device pci 1c.5 on end # PCIe Port #6
+ device pci 1c.6 on end # PCIe Port #7
+ device pci 1c.7 off end # PCIe Port #8
+ device pci 1d.0 on end # USB2 EHCI #1
+ device pci 1e.0 off end # PCI bridge
+ device pci 1f.0 on # LPC bridge PCI-LPC bridge
+ chip superio/nuvoton/nct6779d
+ device pnp 2e.1 off end # Parallel
+ device pnp 2e.2 on # UART A
+ io 0x60 = 0x3f8 # COM2 address
+ end
+ device pnp 2e.3 off end # UART B, IR
+ device pnp 2e.5 on # PS2 KBC
+ io 0x60 = 0x0060 # KBC1 base
+ io 0x62 = 0x0064 # KBC2 base
+ irq 0x70 = 1 # Keyboard IRQ
+ irq 0x72 = 12 # Mouse IRQ
+
+ # KBC 12Mhz/A20 speed/sw KBRST
+ drq 0xf0 = 0x82
+ end
+ device pnp 2e.6 off end # CIR
+ device pnp 2e.7 on end # GPIOs 6-8
+ device pnp 2e.8 off end # WDT1 GPIO 0-1
+ device pnp 2e.9 off end # GPIO 1-8
+ device pnp 2e.a on # ACPI
+ drq 0xe4 = 0x10 # Enable 3VSBS to power RAM on S3
+ drq 0xe7 = 0x10 # 0.5s S3 delay for compatibility
+ end
+ device pnp 2e.b off end # HWM, LED
+ device pnp 2e.d off end # WDT1
+ device pnp 2e.e off end # CIR wake-up
+ device pnp 2e.f on # GPIO PP/OD
+ drq 0xe6 = 0x7f # GP7 PP
+ end
+ device pnp 2e.14 on end # Port 80 UART
+ device pnp 2e.16 off end # Deep sleep
+ end
+ chip drivers/pc80/tpm
+ device pnp 4e.0 on end # TPM
+ end
+ end
+ device pci 1f.2 on end # SATA Controller 1
+ device pci 1f.3 on end # SMBus
+ device pci 1f.5 off end # SATA Controller 2
+ device pci 1f.6 off end # Thermal
+ end
+ end
+end
diff --git a/src/mainboard/asus/p8z77-m/dsdt.asl b/src/mainboard/asus/p8z77-m/dsdt.asl
new file mode 100644
index 0000000..62d44ea
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/dsdt.asl
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Vlado Cibic <vladocb(a)protonmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
+
+#include <arch/acpi.h>
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, /* DSDT revision: ACPI 2.0 and up */
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20141018 /* OEM revision */
+)
+{
+ #include "acpi/platform.asl"
+ #include "acpi/superio.asl"
+ #include <cpu/intel/common/acpi/cpu.asl>
+ #include <southbridge/intel/common/acpi/platform.asl>
+
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
+
+ Device (\_SB.PCI0)
+ {
+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
+ }
+}
diff --git a/src/mainboard/asus/p8z77-m/early_init.c b/src/mainboard/asus/p8z77-m/early_init.c
new file mode 100644
index 0000000..52c0e03
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/early_init.c
@@ -0,0 +1,197 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <bootblock_common.h>
+#include <device/pnp_ops.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <arch/io.h>
+#include <device/pnp.h>
+#include <stdint.h>
+
+#include <superio/nuvoton/common/nuvoton.h>
+#include <superio/nuvoton/nct6779d/nct6779d.h>
+
+#include <option.h>
+
+#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <northbridge/intel/sandybridge/raminit.h>
+#include <northbridge/intel/sandybridge/pei_data.h>
+
+#define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1)
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+ /* {enable, current, oc_pin} */
+ { 1, 2, 0 }, /* Port 0: USB3 front internal header, top */
+ { 1, 2, 0 }, /* Port 1: USB3 front internal header, bottom */
+ { 1, 2, 1 }, /* Port 2: USB3 rear, ETH top */
+ { 1, 2, 1 }, /* Port 3: USB3 rear, ETH bottom */
+ { 1, 2, 2 }, /* Port 4: USB2 rear, PS2 top */
+ { 1, 2, 2 }, /* Port 5: USB2 rear, PS2 bottom */
+ { 1, 2, 3 }, /* Port 6: USB2 internal header USB78, top */
+ { 1, 2, 3 }, /* Port 7: USB2 internal header USB78, bottom */
+ { 1, 2, 4 }, /* Port 8: USB2 internal header USB910, top */
+ { 1, 2, 4 }, /* Port 9: USB2 internal header USB910, bottom */
+ { 1, 2, 6 }, /* Port 10: USB2 internal header USB1112, top */
+ { 1, 2, 5 }, /* Port 11: USB2 internal header USB1112, bottom */
+ { 0, 2, 5 }, /* Port 12: Unused. Asus proprietary DEBUG_PORT ??? */
+ { 0, 2, 6 } /* Port 13: Unused. Asus proprietary DEBUG_PORT ??? */
+};
+
+/* Global config register values. */
+static const u8 register_values[] = {
+ /*
+ * Before accessing CR10, CR11, CR13 and CR14, CR26 [Bit4] must be set to logic 1.
+ * - NCT6779D datasheet, page 293
+ */
+ /* reg, value */
+ 0x26, (1 << 4),
+ 0x13, 0xff, /* IRQs 0-15 active low */
+ 0x14, 0xff,
+ 0x1b, 0x60,
+ 0x22, 0xdf, /* Power down UART B */
+ 0x2a, 0x48, /* UART A instead of GPIO8x */
+ 0x2c, 0x00, /* PECI */
+};
+
+void bootblock_mainboard_early_init(void)
+{
+ int max = ARRAY_SIZE(register_values);
+ int i;
+
+ nuvoton_pnp_enter_conf_state(SERIAL_DEV);
+
+ /* Set registers as specified in the register_values[] array. */
+ for (i = 0; i < max; i += 2)
+ pnp_write_config(SERIAL_DEV, register_values[i], register_values[i + 1]);
+
+ pnp_set_logical_device(SERIAL_DEV);
+ pnp_set_enable(SERIAL_DEV, 0);
+ pnp_set_iobase(SERIAL_DEV, PNP_IDX_IO0, CONFIG_TTYS0_BASE);
+ pnp_set_enable(SERIAL_DEV, 1);
+ nuvoton_pnp_exit_conf_state(SERIAL_DEV);
+}
+
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+{
+ read_spd(&spd[0], 0x50, id_only);
+ read_spd(&spd[1], 0x51, id_only);
+ read_spd(&spd[2], 0x52, id_only);
+ read_spd(&spd[3], 0x53, id_only);
+}
+
+int mainboard_should_reset_usb(int s3resume)
+{
+ return !s3resume;
+}
+
+void mainboard_fill_pei_data(struct pei_data *pei_data)
+{
+ /*
+ * USB3 mode:
+ * 0 = Disable: work always as USB 2.0(ehci)
+ * 1 = Enable: work always as USB 3.0(xhci)
+ * 2 = Auto: work as USB2.0(ehci) until OS loads USB3 xhci driver
+ * 3 = Smart Auto : same than Auto, but if OS loads USB3 driver
+ * and reboots, it will keep the USB3.0 speed
+ */
+ int usb3_mode = 1;
+ get_option(&usb3_mode, "usb3_mode");
+ usb3_mode &= 0x3; /* ensure it's 0/1/2/3 only */
+
+ /* Load USB3 pre-OS xHCI driver */
+ int usb3_drv = 1;
+ get_option(&usb3_drv, "usb3_drv");
+ usb3_drv &= 0x1; /* ensure it's 0/1 only */
+
+ /* Use USB3 xHCI streams */
+ int usb3_streams = 1;
+ get_option(&usb3_streams, "usb3_streams");
+ usb3_streams &= 0x1; /* ensure it's 0/1 only */
+
+ struct pei_data pd = {
+ .pei_version = PEI_VERSION,
+ .mchbar = (uintptr_t)DEFAULT_MCHBAR,
+ .dmibar = (uintptr_t)DEFAULT_DMIBAR,
+ .epbar = DEFAULT_EPBAR,
+ .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
+ .smbusbar = SMBUS_IO_BASE,
+ .wdbbar = 0x4000000,
+ .wdbsize = 0x1000,
+ .hpet_address = CONFIG_HPET_ADDRESS,
+ .rcba = (uintptr_t)DEFAULT_RCBABASE,
+ .pmbase = DEFAULT_PMBASE,
+ .gpiobase = DEFAULT_GPIOBASE,
+ .thermalbase = 0xfed08000,
+ .system_type = 1, /* 0=Mobile, 1=Desktop/Server */
+ .tseg_size = CONFIG_SMM_TSEG_SIZE,
+ .spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 }, /* SMBus mul 2 */
+ .ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
+ .ec_present = 0, /* Asus 2203 bios shows XUECA016, but no EC */
+ .gbe_enable = 0, /* Board uses no Intel GbE but a RTL8111F */
+ .dimm_channel0_disabled = 0, /* Both DIMM enabled */
+ .dimm_channel1_disabled = 0, /* Both DIMM enabled */
+ .max_ddr3_freq = 1600, /* 1333=Sandy; 1600=Ivy */
+ .usb_port_config = {
+ /* {enabled, oc_pin, cable len 0x0080=<8inches/20cm} */
+ { 1, 0, 0x0080 }, /* USB3 front internal header */
+ { 1, 0, 0x0080 }, /* USB3 front internal header */
+ { 1, 1, 0x0080 }, /* USB3 ETH top connector */
+ { 1, 1, 0x0080 }, /* USB3 ETH botton connector */
+ { 1, 2, 0x0080 }, /* USB2 PS2 top connector */
+ { 1, 2, 0x0080 }, /* USB2 PS2 botton connector */
+ { 1, 3, 0x0080 }, /* USB2 internal header (USB78) */
+ { 1, 3, 0x0080 }, /* USB2 internal header (USB78) */
+ { 1, 4, 0x0080 }, /* USB2 internal header (USB910) */
+ { 1, 4, 0x0080 }, /* USB2 internal header (USB910) */
+ { 1, 6, 0x0080 }, /* USB2 internal header (USB1112) */
+ { 1, 5, 0x0080 }, /* USB2 internal header (USB1112) */
+ { 0, 5, 0x0080 }, /* Unused. Asus DEBUG_PORT ??? */
+ { 0, 6, 0x0080 } /* Unused. Asus DEBUG_PORT ??? */
+ },
+ .usb3 = {
+ /* 0=Disable; 1=Enable (start at USB3 speed)
+ * 2=Auto (start as USB2 speed until OS loads)
+ * 3=Smart Auto (like Auto but keep speed on reboot)
+ */
+ usb3_mode,
+ /* 4 bit switch mask. 0=not switchable, 1=switchable
+ * Means once it's loaded the OS, it can swap ports
+ * from/to EHCI/xHCI. Z77 has four USB3 ports, so 0xf
+ */
+ 0xf,
+ usb3_drv, /* 1=Load xHCI pre-OS drv */
+ /* 0=Don't use xHCI streams for better compatibility
+ * 1=use xHCI streams for better speed
+ */
+ usb3_streams
+ },
+ /* ASUS P8Z77-M Pro manual says 1.35v DIMMs are supported */
+ .ddr3lv_support = 1,
+ /* PCIe 3.0 support. As we use Ivy Bridge, let's enable it,
+ * but might cause some system instability !
+ */
+ .pcie_init = 1,
+ /* Command Rate. 0=Auto; 1=1N; 2=2N.
+ * Leave it always at Auto for compatibility & stability
+ */
+ .nmode = 0,
+ /* DDR refresh rate. 0=Auto based on DRAM's temperature;
+ * 1=Normal rate for speed; 2=Double rate for stability
+ */
+ .ddr_refresh_rate_config = 0
+ };
+
+ /* copy the data to output PEI */
+ *pei_data = pd;
+}
diff --git a/src/mainboard/asus/p8z77-m/gma-mainboard.ads b/src/mainboard/asus/p8z77-m/gma-mainboard.ads
new file mode 100644
index 0000000..d7afe73
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/gma-mainboard.ads
@@ -0,0 +1,34 @@
+--
+-- This file is part of the coreboot project.
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ -- FIXME: check this
+ ports : constant Port_List :=
+ (DP1,
+ DP2,
+ DP3,
+ HDMI1,
+ HDMI2,
+ HDMI3,
+ Analog,
+ Internal);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/asus/p8z77-m/gpio.c b/src/mainboard/asus/p8z77-m/gpio.c
new file mode 100644
index 0000000..03e1507
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/gpio.c
@@ -0,0 +1,194 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio1 = GPIO_MODE_GPIO,
+ .gpio2 = GPIO_MODE_NATIVE,
+ .gpio3 = GPIO_MODE_NATIVE,
+ .gpio4 = GPIO_MODE_NATIVE,
+ .gpio5 = GPIO_MODE_NATIVE,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_NATIVE,
+ .gpio10 = GPIO_MODE_NATIVE,
+ .gpio11 = GPIO_MODE_NATIVE,
+ .gpio12 = GPIO_MODE_GPIO,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_NATIVE,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio16 = GPIO_MODE_GPIO,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_NATIVE,
+ .gpio19 = GPIO_MODE_NATIVE,
+ .gpio20 = GPIO_MODE_NATIVE,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_NATIVE,
+ .gpio23 = GPIO_MODE_NATIVE,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_NATIVE,
+ .gpio26 = GPIO_MODE_NATIVE,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_GPIO,
+ .gpio30 = GPIO_MODE_NATIVE,
+ .gpio31 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT,
+ .gpio1 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_OUTPUT,
+ .gpio12 = GPIO_DIR_OUTPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_OUTPUT,
+ .gpio16 = GPIO_DIR_INPUT,
+ .gpio17 = GPIO_DIR_INPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_OUTPUT,
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_OUTPUT,
+ .gpio29 = GPIO_DIR_OUTPUT,
+ .gpio31 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio8 = GPIO_LEVEL_HIGH,
+ .gpio12 = GPIO_LEVEL_LOW,
+ .gpio15 = GPIO_LEVEL_LOW,
+ .gpio24 = GPIO_LEVEL_LOW,
+ .gpio28 = GPIO_LEVEL_LOW,
+ .gpio29 = GPIO_LEVEL_HIGH,
+ .gpio31 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio1 = GPIO_INVERT,
+ .gpio13 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_GPIO,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_NATIVE,
+ .gpio36 = GPIO_MODE_NATIVE,
+ .gpio37 = GPIO_MODE_NATIVE,
+ .gpio38 = GPIO_MODE_NATIVE,
+ .gpio39 = GPIO_MODE_NATIVE,
+ .gpio40 = GPIO_MODE_NATIVE,
+ .gpio41 = GPIO_MODE_NATIVE,
+ .gpio42 = GPIO_MODE_NATIVE,
+ .gpio43 = GPIO_MODE_NATIVE,
+ .gpio44 = GPIO_MODE_NATIVE,
+ .gpio45 = GPIO_MODE_GPIO,
+ .gpio46 = GPIO_MODE_GPIO,
+ .gpio47 = GPIO_MODE_NATIVE,
+ .gpio48 = GPIO_MODE_NATIVE,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio50 = GPIO_MODE_NATIVE,
+ .gpio51 = GPIO_MODE_NATIVE,
+ .gpio52 = GPIO_MODE_NATIVE,
+ .gpio53 = GPIO_MODE_NATIVE,
+ .gpio54 = GPIO_MODE_NATIVE,
+ .gpio55 = GPIO_MODE_NATIVE,
+ .gpio56 = GPIO_MODE_NATIVE,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_NATIVE,
+ .gpio60 = GPIO_MODE_NATIVE,
+ .gpio61 = GPIO_MODE_NATIVE,
+ .gpio62 = GPIO_MODE_NATIVE,
+ .gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio32 = GPIO_DIR_OUTPUT,
+ .gpio33 = GPIO_DIR_OUTPUT,
+ .gpio34 = GPIO_DIR_INPUT,
+ .gpio45 = GPIO_DIR_INPUT,
+ .gpio46 = GPIO_DIR_INPUT,
+ .gpio49 = GPIO_DIR_INPUT,
+ .gpio57 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio32 = GPIO_LEVEL_HIGH,
+ .gpio33 = GPIO_LEVEL_HIGH,
+ .gpio57 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_NATIVE,
+ .gpio65 = GPIO_MODE_NATIVE,
+ .gpio66 = GPIO_MODE_NATIVE,
+ .gpio67 = GPIO_MODE_NATIVE,
+ .gpio68 = GPIO_MODE_GPIO,
+ .gpio69 = GPIO_MODE_GPIO,
+ .gpio70 = GPIO_MODE_NATIVE,
+ .gpio71 = GPIO_MODE_NATIVE,
+ .gpio72 = GPIO_MODE_GPIO,
+ .gpio73 = GPIO_MODE_NATIVE,
+ .gpio74 = GPIO_MODE_NATIVE,
+ .gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio68 = GPIO_DIR_INPUT,
+ .gpio69 = GPIO_DIR_INPUT,
+ .gpio72 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/asus/p8z77-m/hda_verb.c b/src/mainboard/asus/p8z77-m/hda_verb.c
new file mode 100644
index 0000000..f240025
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/hda_verb.c
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x10ec0887, /* Codec Vendor / Device ID: Realtek */
+ 0x104384a8, /* Subsystem ID */
+ 15, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(0, 0x104384a8),
+ AZALIA_PIN_CFG(0, 0x11, 0x90430130),
+ AZALIA_PIN_CFG(0, 0x12, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x14, 0x01014410),
+ AZALIA_PIN_CFG(0, 0x15, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x18, 0x01a19c50),
+ AZALIA_PIN_CFG(0, 0x19, 0x02a19c60),
+ AZALIA_PIN_CFG(0, 0x1a, 0x0181345f),
+ AZALIA_PIN_CFG(0, 0x1b, 0x02214c20),
+ AZALIA_PIN_CFG(0, 0x1c, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x1d, 0x4016c629),
+ AZALIA_PIN_CFG(0, 0x1e, 0x01446140),
+ AZALIA_PIN_CFG(0, 0x1f, 0x411111f0),
+
+ 0x80862806, /* Codec Vendor / Device ID: Intel */
+ 0x80860101, /* Subsystem ID */
+ 4, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(3, 0x80860101),
+ AZALIA_PIN_CFG(3, 0x05, 0x58560010),
+ AZALIA_PIN_CFG(3, 0x06, 0x58560020),
+ AZALIA_PIN_CFG(3, 0x07, 0x18560030),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/asus/p8z77-m/mainboard.c b/src/mainboard/asus/p8z77-m/mainboard.c
new file mode 100644
index 0000000..b97b648
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/mainboard.c
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* This file is part of the coreboot project. */
+
+#include <device/device.h>
+#include <drivers/intel/gma/int15.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+static void mainboard_enable(struct device *dev)
+{
+ /* FIXME: fix those values*/
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
+ GMA_INT15_PANEL_FIT_DEFAULT,
+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
--
To view, visit https://review.coreboot.org/c/coreboot/+/38988
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: If756e791ddce747cb1706414be8e41e83f88922b
Gerrit-Change-Number: 38988
Gerrit-PatchSet: 1
Gerrit-Owner: Keith Hui <buurin(a)gmail.com>
Gerrit-MessageType: newchange
4 days, 15 hours
- 6
- 40
Change in coreboot[master]: soc/mediatek/mt8192: Do dramc analog init setting
by CK HU (Code Review)
Hello Duan huayang,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/44727
to review the following change.
Change subject: soc/mediatek/mt8192: Do dramc analog init setting
......................................................................
soc/mediatek/mt8192: Do dramc analog init setting
Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com>
Change-Id: I53b30a2bbed5acb363f85f7cbc7f255fdbc52304
---
M src/soc/mediatek/mt8192/Makefile.inc
A src/soc/mediatek/mt8192/dramc_ana_init_config.c
M src/soc/mediatek/mt8192/dramc_pi_basic_api.c
A src/soc/mediatek/mt8192/dramc_subsys_config.c
M src/soc/mediatek/mt8192/emi.c
5 files changed, 1,411 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/44727/1
diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc
index bfa3316..e3463cd 100644
--- a/src/soc/mediatek/mt8192/Makefile.inc
+++ b/src/soc/mediatek/mt8192/Makefile.inc
@@ -17,6 +17,7 @@
romstage-y += ../common/cbmem.c
romstage-y += dramc_pi_main.c dramc_pi_basic_api.c dramc_pi_calibration_api.c dramc_utility.c dramc_dvfs.c dramc_tracking.c
+romstage-y += dramc_subsys_config.c dramc_ana_init_config.c
romstage-y += emi.c
romstage-y += flash_controller.c
romstage-y += ../common/gpio.c gpio.c
diff --git a/src/soc/mediatek/mt8192/dramc_ana_init_config.c b/src/soc/mediatek/mt8192/dramc_ana_init_config.c
new file mode 100644
index 0000000..0fd3a9a
--- /dev/null
+++ b/src/soc/mediatek/mt8192/dramc_ana_init_config.c
@@ -0,0 +1,1242 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/dramc_pi_api.h>
+#include <soc/dramc_register.h>
+
+static void suspend_on(void)
+{
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_lp_ctrl0,
+ B0_LP_CTRL0_RG_ARDMSUS_10_B0, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_lp_ctrl0,
+ B1_LP_CTRL0_RG_ARDMSUS_10_B1, 0);
+ dramc_set_broadcast(DRAMC_BROADCAST_OFF);
+ for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
+ SET32_BITFIELDS(&ch[chn].phy_ao.ca_lp_ctrl0,
+ CA_LP_CTRL0_RG_ARDMSUS_10_CA, 0);
+ dramc_set_broadcast(DRAMC_BROADCAST_ON);
+}
+
+void resetb_pull_dn(void)
+{
+ SET32_BITFIELDS(&ch[0].phy_ao.ca_cmd11,
+ CA_CMD11_RG_RRESETB_DRVP, 1,
+ CA_CMD11_RG_RRESETB_DRVN, 1,
+ CA_CMD11_RG_TX_RRESETB_DDR3_SEL, 1,
+ CA_CMD11_RG_TX_RRESETB_PULL_DN, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.misc_ctrl1,
+ MISC_CTRL1_R_DMRRESETB_I_OPT, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.misc_ctrl1,
+ MISC_CTRL1_R_DMDA_RRESETB_E, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.ca_cmd11,
+ CA_CMD11_RG_TX_RRESETB_PULL_DN, 0);
+}
+
+static void spm_control(ana_top_config *a_cfg)
+{
+ u8 new_8x_mode = a_cfg->new_8x_mode;
+
+ SET32_BITFIELDS(&ch[0].phy_ao.misc_lp_ctrl,
+ MISC_LP_CTRL_RG_ARDMSUS_10_LP_SEL, 1,
+ MISC_LP_CTRL_RG_RIMP_DMSUS_10_LP_SEL, 1,
+ MISC_LP_CTRL_RG_RRESETB_LP_SEL, 1,
+ MISC_LP_CTRL_RG_RPHYPLL_RESETB_LP_SEL, 1,
+ MISC_LP_CTRL_RG_RPHYPLL_EN_LP_SEL, 1,
+ MISC_LP_CTRL_RG_RCLRPLL_EN_LP_SEL, 1,
+ MISC_LP_CTRL_RG_RPHYPLL_ADA_MCK8X_EN_LP_SEL, 1,
+ MISC_LP_CTRL_RG_RPHYPLL_AD_MCK8X_EN_LP_SEL, 1,
+ MISC_LP_CTRL_RG_RPHYPLL_TOP_REV_0_LP_SEL, 1,
+ MISC_LP_CTRL_RG_SC_ARPI_RESETB_8X_SEQ_LP_SEL, new_8x_mode,
+ MISC_LP_CTRL_RG_ADA_MCK8X_8X_SEQ_LP_SEL, new_8x_mode,
+ MISC_LP_CTRL_RG_AD_MCK8X_8X_SEQ_LP_SEL, new_8x_mode,
+ MISC_LP_CTRL_RG_MIDPI_EN_8X_SEQ_LP_SEL, new_8x_mode,
+ MISC_LP_CTRL_RG_MIDPI_CKDIV4_EN_8X_SEQ_LP_SEL, new_8x_mode,
+ MISC_LP_CTRL_RG_MCK8X_CG_SRC_LP_SEL, new_8x_mode,
+ MISC_LP_CTRL_RG_MCK8X_CG_SRC_AND_LP_SEL, new_8x_mode);
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_lp_ctrl0,
+ B0_LP_CTRL0_RG_ARDMSUS_10_B0_LP_SEL, 1,
+ B0_LP_CTRL0_RG_ARDQ_RESETB_B0_LP_SEL, 1,
+ B0_LP_CTRL0_RG_ARPI_RESETB_B0_LP_SEL, 1,
+ B0_LP_CTRL0_RG_B0_MS_SLV_LP_SEL, 0,
+ B0_LP_CTRL0_RG_ARDLL_PHDET_EN_B0_LP_SEL, 1,
+ B0_LP_CTRL0_RG_RX_ARDQ_BIAS_EN_B0_LP_SEL, 0,
+ B0_LP_CTRL0_DA_ARPI_CG_MCK_B0_LP_SEL, 1,
+ B0_LP_CTRL0_DA_ARPI_CG_MCK_FB2DLL_B0_LP_SEL, 1,
+ B0_LP_CTRL0_DA_ARPI_CG_MCTL_B0_LP_SEL, 1,
+ B0_LP_CTRL0_DA_ARPI_CG_FB_B0_LP_SEL, 1,
+ B0_LP_CTRL0_DA_ARPI_CG_DQ_B0_LP_SEL, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_lp_ctrl0,
+ B0_LP_CTRL0_DA_ARPI_CG_DQM_B0_LP_SEL, 1,
+ B0_LP_CTRL0_DA_ARPI_CG_DQS_B0_LP_SEL, 1,
+ B0_LP_CTRL0_DA_ARPI_CG_DQSIEN_B0_LP_SEL, 1,
+ B0_LP_CTRL0_DA_ARPI_MPDIV_CG_B0_LP_SEL, 1,
+ B0_LP_CTRL0_RG_RX_ARDQ_VREF_EN_B0_LP_SEL, 1,
+ B0_LP_CTRL0_DA_ARPI_MIDPI_EN_B0_LP_SEL, 1,
+ B0_LP_CTRL0_DA_ARPI_MIDPI_CKDIV4_EN_B0_LP_SEL, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_lp_ctrl0,
+ B1_LP_CTRL0_RG_ARDMSUS_10_B1_LP_SEL, 1,
+ B1_LP_CTRL0_RG_ARDQ_RESETB_B1_LP_SEL, 1,
+ B1_LP_CTRL0_RG_ARPI_RESETB_B1_LP_SEL, 1,
+ B1_LP_CTRL0_RG_B1_MS_SLV_LP_SEL, 0,
+ B1_LP_CTRL0_RG_ARDLL_PHDET_EN_B1_LP_SEL, 1,
+ B1_LP_CTRL0_RG_RX_ARDQ_BIAS_EN_B1_LP_SEL, 0,
+ B1_LP_CTRL0_DA_ARPI_CG_MCK_B1_LP_SEL, 1,
+ B1_LP_CTRL0_DA_ARPI_CG_MCK_FB2DLL_B1_LP_SEL, 1,
+ B1_LP_CTRL0_DA_ARPI_CG_MCTL_B1_LP_SEL, 1,
+ B1_LP_CTRL0_DA_ARPI_CG_FB_B1_LP_SEL, 1,
+ B1_LP_CTRL0_DA_ARPI_CG_DQ_B1_LP_SEL, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_lp_ctrl0,
+ B1_LP_CTRL0_DA_ARPI_CG_DQM_B1_LP_SEL, 1,
+ B1_LP_CTRL0_DA_ARPI_CG_DQS_B1_LP_SEL, 1,
+ B1_LP_CTRL0_DA_ARPI_CG_DQSIEN_B1_LP_SEL, 1,
+ B1_LP_CTRL0_DA_ARPI_MPDIV_CG_B1_LP_SEL, 1,
+ B1_LP_CTRL0_RG_RX_ARDQ_VREF_EN_B1_LP_SEL, 1,
+ B1_LP_CTRL0_DA_ARPI_MIDPI_EN_B1_LP_SEL, 1,
+ B1_LP_CTRL0_DA_ARPI_MIDPI_CKDIV4_EN_B1_LP_SEL, 1);
+
+ dramc_set_broadcast(DRAMC_BROADCAST_OFF);
+ for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
+ SET32_BITFIELDS(&ch[chn].phy_ao.ca_lp_ctrl0,
+ CA_LP_CTRL0_RG_ARDMSUS_10_CA_LP_SEL, 1,
+ CA_LP_CTRL0_RG_ARCMD_RESETB_LP_SEL, 1,
+ CA_LP_CTRL0_RG_ARPI_RESETB_CA_LP_SEL, 1,
+ CA_LP_CTRL0_RG_ARDLL_PHDET_EN_CA_LP_SEL, 1,
+ CA_LP_CTRL0_RG_TX_ARCS_PULL_UP_LP_SEL, 1,
+ CA_LP_CTRL0_RG_TX_ARCS_PULL_DN_LP_SEL, 1,
+ CA_LP_CTRL0_RG_TX_ARCA_PULL_UP_LP_SEL, 1,
+ CA_LP_CTRL0_RG_TX_ARCA_PULL_DN_LP_SEL, 1,
+ CA_LP_CTRL0_DA_ARPI_CG_MCK_CA_LP_SEL, 1,
+ CA_LP_CTRL0_DA_ARPI_CG_MCK_FB2DLL_CA_LP_SEL, 1,
+ CA_LP_CTRL0_DA_ARPI_CG_MCTL_CA_LP_SEL, 1,
+ CA_LP_CTRL0_DA_ARPI_CG_FB_CA_LP_SEL, 1);
+ SET32_BITFIELDS(&ch[chn].phy_ao.ca_lp_ctrl0,
+ CA_LP_CTRL0_DA_ARPI_CG_CS_LP_SEL, 1,
+ CA_LP_CTRL0_DA_ARPI_CG_CLK_LP_SEL, 1,
+ CA_LP_CTRL0_DA_ARPI_CG_CMD_LP_SEL, 1,
+ CA_LP_CTRL0_DA_ARPI_CG_CLKIEN_LP_SEL, 1,
+ CA_LP_CTRL0_DA_ARPI_MPDIV_CG_CA_LP_SEL, 1,
+ CA_LP_CTRL0_RG_RX_ARCMD_VREF_EN_LP_SEL, 1,
+ CA_LP_CTRL0_DA_ARPI_MIDPI_EN_CA_LP_SEL, 1,
+ CA_LP_CTRL0_DA_ARPI_MIDPI_CKDIV4_EN_CA_LP_SEL, 1,
+ CA_LP_CTRL0_RG_RX_ARCMD_BIAS_EN_LP_SEL, 0);
+ }
+
+ if (a_cfg->dll_async_en == 1) {
+ for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
+ SET32_BITFIELDS(&ch[chn].phy_ao.ca_lp_ctrl0,
+ CA_LP_CTRL0_RG_CA_MS_SLV_LP_SEL, a_cfg->all_slave_en==0);
+ } else {
+ SET32_BITFIELDS(&ch[0].phy_ao.ca_lp_ctrl0,
+ CA_LP_CTRL0_RG_CA_MS_SLV_LP_SEL, a_cfg->all_slave_en==0);
+ SET32_BITFIELDS(&ch[1].phy_ao.ca_lp_ctrl0,
+ CA_LP_CTRL0_RG_CA_MS_SLV_LP_SEL, 0);
+ }
+ dramc_set_broadcast(DRAMC_BROADCAST_ON);
+
+ SET32_BITFIELDS(&ch[0].phy_ao.misc_cg_ctrl9,
+ MISC_CG_CTRL9_RG_M_CK_OPENLOOP_MODE_EN, 1,
+ MISC_CG_CTRL9_RG_MCK4X_I_OPENLOOP_MODE_EN, 1,
+ MISC_CG_CTRL9_RG_CG_DDR400_MCK4X_I_OFF, 1,
+ MISC_CG_CTRL9_RG_DDR400_MCK4X_I_FORCE_ON, 0,
+ MISC_CG_CTRL9_RG_MCK4X_I_FB_CK_CG_OFF, 1,
+ MISC_CG_CTRL9_RG_MCK4X_Q_OPENLOOP_MODE_EN, 1,
+ MISC_CG_CTRL9_RG_CG_DDR400_MCK4X_Q_OFF, 1,
+ MISC_CG_CTRL9_RG_DDR400_MCK4X_Q_FORCE_ON, 0,
+ MISC_CG_CTRL9_RG_MCK4X_Q_FB_CK_CG_OFF, 1);
+}
+
+static void ana_tx_nonshuffle_config(ana_top_config *a_cfg)
+{
+ SET32_BITFIELDS(&ch[0].phy_ao.ca_cmd6,
+ CA_CMD6_RG_TX_ARCMD_DDR3_SEL, 0,
+ CA_CMD6_RG_TX_ARCMD_DDR4_SEL, 0,
+ CA_CMD6_RG_TX_ARCMD_LP4_SEL, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq6,
+ B0_DQ6_RG_TX_ARDQ_DDR3_SEL_B0, 0,
+ B0_DQ6_RG_TX_ARDQ_DDR4_SEL_B0, !(a_cfg->aphy_comb_en),
+ B0_DQ6_RG_TX_ARDQ_LP4_SEL_B0, a_cfg->aphy_comb_en);
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq6,
+ B1_DQ6_RG_TX_ARDQ_DDR3_SEL_B1, 0,
+ B1_DQ6_RG_TX_ARDQ_DDR4_SEL_B1, !(a_cfg->aphy_comb_en),
+ B1_DQ6_RG_TX_ARDQ_LP4_SEL_B1, a_cfg->aphy_comb_en);
+ dramc_dbg("[CONFIGURE PHASE]: ANA_TX\n");
+ SET32_BITFIELDS(&ch[0].phy_ao.ca_cmd2,
+ CA_CMD2_RG_TX_ARCMD_OE_DIS_CA, 1,
+ CA_CMD2_RG_TX_ARCMD_ODTEN_DIS_CA, 0,
+ CA_CMD2_RG_TX_ARCLK_OE_DIS_CA, 0,
+ CA_CMD2_RG_TX_ARCLK_ODTEN_DIS_CA, 0,
+ CA_CMD2_RG_TX_ARCS_OE_TIE_SEL_CA, 1,
+ CA_CMD2_RG_TX_ARCS_OE_TIE_EN_CA, 1,
+ CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA, 0,
+ CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA, 0xff);
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq2,
+ B0_DQ2_RG_TX_ARDQ_OE_DIS_B0, 0,
+ B0_DQ2_RG_TX_ARDQ_ODTEN_DIS_B0, 0,
+ B0_DQ2_RG_TX_ARDQM0_OE_DIS_B0, 0,
+ B0_DQ2_RG_TX_ARDQM0_ODTEN_DIS_B0, 0,
+ B0_DQ2_RG_TX_ARDQS0_OE_DIS_B0, 0,
+ B0_DQ2_RG_TX_ARDQS0_ODTEN_DIS_B0, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq2,
+ B1_DQ2_RG_TX_ARDQ_OE_DIS_B1, 0,
+ B1_DQ2_RG_TX_ARDQ_ODTEN_DIS_B1, 0,
+ B1_DQ2_RG_TX_ARDQM0_OE_DIS_B1, 0,
+ B1_DQ2_RG_TX_ARDQM0_ODTEN_DIS_B1, 0,
+ B1_DQ2_RG_TX_ARDQS0_OE_DIS_B1, 0,
+ B1_DQ2_RG_TX_ARDQS0_ODTEN_DIS_B1, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.ca_cmd3,
+ CA_CMD3_RG_TX_ARCMD_EN, 1,
+ CA_CMD3_RG_ARCMD_RESETB, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq3,
+ B0_DQ3_RG_ARDQ_RESETB_B0, 1,
+ B0_DQ3_RG_TX_ARDQ_EN_B0, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq3,
+ B1_DQ3_RG_ARDQ_RESETB_B1, 1,
+ B1_DQ3_RG_TX_ARDQ_EN_B1, 1);
+}
+
+static void ana_rx_nonshuffle_config(void)
+{
+ SET32_BITFIELDS(&ch[0].phy_ao.ca_cmd6,
+ CA_CMD6_RG_RX_ARCMD_DDR3_SEL, 0,
+ CA_CMD6_RG_RX_ARCMD_DDR4_SEL, 0,
+ CA_CMD6_RG_RX_ARCMD_BIAS_VREF_SEL, 0,
+ CA_CMD6_RG_RX_ARCMD_RES_BIAS_EN, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq5,
+ B0_DQ5_RG_RX_ARDQ_VREF_EN_B0, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq6,
+ B0_DQ6_RG_RX_ARDQ_DDR3_SEL_B0, 0,
+ B0_DQ6_RG_RX_ARDQ_DDR4_SEL_B0, 1,
+ B0_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B0, 0,
+ B0_DQ6_RG_RX_ARDQ_BIAS_EN_B0, 1,
+ B0_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B0, 0,
+ B0_DQ6_RG_RX_ARDQ_RES_BIAS_EN_B0, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq3,
+ B0_DQ3_RG_RX_ARDQ_STBENCMP_EN_B0, 1,
+ B0_DQ3_RG_RX_ARDQ_SMT_EN_B0, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq5,
+ B1_DQ5_RG_RX_ARDQ_VREF_EN_B1, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq6,
+ B1_DQ6_RG_RX_ARDQ_DDR3_SEL_B1, 0,
+ B1_DQ6_RG_RX_ARDQ_DDR4_SEL_B1, 1,
+ B1_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B1, 0,
+ B1_DQ6_RG_RX_ARDQ_BIAS_EN_B1, 1,
+ B1_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B1, 0,
+ B1_DQ6_RG_RX_ARDQ_RES_BIAS_EN_B1, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq3,
+ B1_DQ3_RG_RX_ARDQ_STBENCMP_EN_B1, 1,
+ B1_DQ3_RG_RX_ARDQ_SMT_EN_B1, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.ca_cmd9,
+ CA_CMD9_RG_RX_ARCMD_STBEN_RESETB, 1,
+ CA_CMD9_RG_RX_ARCLK_STBEN_RESETB, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq9,
+ B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0, 1,
+ B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq9,
+ B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1, 1,
+ B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.ca_cmd8,
+ CA_CMD8_RG_RX_ARCLK_SER_RST_MODE, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq8,
+ B0_DQ8_RG_RX_ARDQS_SER_RST_MODE_B0, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq8,
+ B1_DQ8_RG_RX_ARDQS_SER_RST_MODE_B1, 1);
+}
+
+static void dig_dcm_nonshuffle_config(void)
+{
+ SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rx_cg_ctrl,
+ MISC_SHU_RX_CG_CTRL_RX_DCM_EXT_DLY, 3);
+}
+
+static void ana_imp_configure(void)
+{
+ SET32_BITFIELDS(&ch[0].phy_ao.misc_imp_ctrl1,
+ MISC_IMP_CTRL1_RG_RIMP_DDR3_SEL, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.misc_imp_ctrl1,
+ MISC_IMP_CTRL1_RG_RIMP_DDR4_SEL, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.misc_imp_ctrl1,
+ MISC_IMP_CTRL1_RG_RIMP_BIAS_EN, 0,
+ MISC_IMP_CTRL1_RG_RIMP_ODT_EN, 0,
+ MISC_IMP_CTRL1_RG_RIMP_PRE_EN, 0,
+ MISC_IMP_CTRL1_RG_RIMP_VREF_EN, 0);
+}
+
+static void ana_dll_non_shuffle_config(dram_freq_grp freq_group,
+ ana_top_config *a_cfg)
+{
+ u8 pd_zone = (freq_group >= DDRFREQ_2133) ? 0x2 : 0x3;
+
+ if (a_cfg->dll_idle_mode == 1) {
+ dramc_set_broadcast(DRAMC_BROADCAST_OFF);
+ if (a_cfg->dll_async_en == 1) {
+ for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
+ SET32_BITFIELDS(&ch[chn].phy_ao.ca_dll_arpi5,
+ CA_DLL_ARPI5_RG_ARDLL_IDLE_EN_CA, 0,
+ CA_DLL_ARPI5_RG_ARDLL_PD_ZONE_CA, pd_zone);
+ SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[0].b0_dll_arpi5,
+ B0_DLL_ARPI5_RG_ARDLL_IDLE_EN_B0, 1,
+ B0_DLL_ARPI5_RG_ARDLL_PD_ZONE_B0, pd_zone);
+ SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[1].b0_dll_arpi5,
+ B1_DLL_ARPI5_RG_ARDLL_IDLE_EN_B1, 1,
+ B1_DLL_ARPI5_RG_ARDLL_PD_ZONE_B1, pd_zone);
+ }
+ } else {
+ SET32_BITFIELDS(&ch[0].phy_ao.ca_dll_arpi5,
+ CA_DLL_ARPI5_RG_ARDLL_IDLE_EN_CA, 0,
+ CA_DLL_ARPI5_RG_ARDLL_PD_ZONE_CA, pd_zone);
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dll_arpi5,
+ B0_DLL_ARPI5_RG_ARDLL_IDLE_EN_B0, 1,
+ B0_DLL_ARPI5_RG_ARDLL_PD_ZONE_B0, pd_zone);
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dll_arpi5,
+ B1_DLL_ARPI5_RG_ARDLL_IDLE_EN_B1, 1,
+ B1_DLL_ARPI5_RG_ARDLL_PD_ZONE_B1, pd_zone);
+ SET32_BITFIELDS(&ch[1].phy_ao.ca_dll_arpi5,
+ CA_DLL_ARPI5_RG_ARDLL_IDLE_EN_CA, 1,
+ CA_DLL_ARPI5_RG_ARDLL_PD_ZONE_CA, pd_zone);
+ SET32_BITFIELDS(&ch[1].phy_ao.dvs_b[0].b0_dll_arpi5,
+ B0_DLL_ARPI5_RG_ARDLL_IDLE_EN_B0, 1,
+ B0_DLL_ARPI5_RG_ARDLL_PD_ZONE_B0, pd_zone);
+ SET32_BITFIELDS(&ch[1].phy_ao.dvs_b[1].b0_dll_arpi5,
+ B1_DLL_ARPI5_RG_ARDLL_IDLE_EN_B1, 1,
+ B1_DLL_ARPI5_RG_ARDLL_PD_ZONE_B1, pd_zone);
+ }
+ dramc_set_broadcast(DRAMC_BROADCAST_ON);
+ }
+
+ SET32_BITFIELDS(&ch[0].phy_ao.ca_dll_arpi1,
+ CA_DLL_ARPI1_RG_ARPI_CLKIEN_JUMP_EN, 0,
+ CA_DLL_ARPI1_RG_ARPI_CMD_JUMP_EN, 0,
+ CA_DLL_ARPI1_RG_ARPI_CLK_JUMP_EN, 0,
+ CA_DLL_ARPI1_RG_ARPI_CS_JUMP_EN, 0,
+ CA_DLL_ARPI1_RG_ARPI_FB_JUMP_EN_CA, 0,
+ CA_DLL_ARPI1_RG_ARPI_MCTL_JUMP_EN_CA, 0,
+ CA_DLL_ARPI1_RG_ARPISM_MCK_SEL_CA, 1,
+ CA_DLL_ARPI1_RG_ARPISM_MCK_SEL_CA_REG_OPT, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dll_arpi1,
+ B0_DLL_ARPI1_RG_ARPI_DQSIEN_JUMP_EN_B0, 0,
+ B0_DLL_ARPI1_RG_ARPI_DQ_JUMP_EN_B0, 0,
+ B0_DLL_ARPI1_RG_ARPI_DQM_JUMP_EN_B0, 0,
+ B0_DLL_ARPI1_RG_ARPI_DQS_JUMP_EN_B0, 0,
+ B0_DLL_ARPI1_RG_ARPI_FB_JUMP_EN_B0, 0,
+ B0_DLL_ARPI1_RG_ARPI_MCTL_JUMP_EN_B0, 0,
+ B0_DLL_ARPI1_RG_ARPISM_MCK_SEL_B0, 0,
+ B0_DLL_ARPI1_RG_ARPISM_MCK_SEL_B0_REG_OPT, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dll_arpi1,
+ B1_DLL_ARPI1_RG_ARPI_DQSIEN_JUMP_EN_B1, 0,
+ B1_DLL_ARPI1_RG_ARPI_DQ_JUMP_EN_B1, 0,
+ B1_DLL_ARPI1_RG_ARPI_DQM_JUMP_EN_B1, 0,
+ B1_DLL_ARPI1_RG_ARPI_DQS_JUMP_EN_B1, 0,
+ B1_DLL_ARPI1_RG_ARPI_FB_JUMP_EN_B1, 0,
+ B1_DLL_ARPI1_RG_ARPI_MCTL_JUMP_EN_B1, 0,
+ B1_DLL_ARPI1_RG_ARPISM_MCK_SEL_B1, 0,
+ B1_DLL_ARPI1_RG_ARPISM_MCK_SEL_B1_REG_OPT, 0);
+
+ dramc_set_broadcast(DRAMC_BROADCAST_OFF);
+ for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
+ SET32_BITFIELDS(&ch[chn].phy_ao.ca_dll_arpi5,
+ CA_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_CA, 0,
+ CA_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_SEL_CA, 0,
+ CA_DLL_ARPI5_RG_ARDLL_DIV_DEC_CA, 0,
+ CA_DLL_ARPI5_RG_ARDLL_MON_SEL_CA, 0);
+ SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[0].b0_dll_arpi5,
+ B0_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_B0, 0,
+ B0_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_SEL_B0, 0,
+ B0_DLL_ARPI5_RG_ARDLL_DIV_DEC_B0, 0,
+ B0_DLL_ARPI5_RG_ARDLL_MON_SEL_B0, 0);
+ SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[1].b0_dll_arpi5,
+ B1_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_B1, 0,
+ B1_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_SEL_B1, 0,
+ B1_DLL_ARPI5_RG_ARDLL_DIV_DEC_B1, 0,
+ B1_DLL_ARPI5_RG_ARDLL_MON_SEL_B1, 0);
+ }
+ dramc_set_broadcast(DRAMC_BROADCAST_ON);
+}
+
+static void ana_pll_shuffle_Config(ana_dvfs_core *dvfs_core)
+{
+ u8 prediv = 1;
+ u8 posdiv = 0;
+ u8 fbk_sel = 0;
+ u8 div16_ck_sel = 0;
+ u32 pcw;
+ u32 pll_freq = dvfs_core->pll_freq;
+ u32 xtal_freq = 26;
+
+ if (dvfs_core->dq_ca_open == 1)
+ div16_ck_sel = 1;
+ else
+ fbk_sel = (pll_freq > 3800) ? 1 : 0;
+
+ pcw = (pll_freq/xtal_freq) << (8 + 1 -fbk_sel-prediv - posdiv);
+ dramc_dbg("pll_freq:%d, fbk_sel:%d, pcw = %#x\n", pll_freq, fbk_sel, pcw);
+
+ SET32_BITFIELDS(&ch[0].phy_ao.phypll1,
+ PHYPLL1_RG_RPHYPLL_TST_EN, 0,
+ PHYPLL1_RG_RPHYPLL_TSTOP_EN, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_phypll0,
+ SHU_PHYPLL0_RG_RPHYPLL_RESERVED, 0,
+ SHU_PHYPLL0_RG_RPHYPLL_ICHP, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_clrpll0,
+ SHU_CLRPLL0_RG_RCLRPLL_RESERVED, 0,
+ SHU_CLRPLL0_RG_RCLRPLL_ICHP, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_phypll2,
+ SHU_PHYPLL2_RG_RPHYPLL_PREDIV, prediv,
+ SHU_PHYPLL2_RG_RPHYPLL_POSDIV, posdiv);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_clrpll2,
+ SHU_CLRPLL2_RG_RCLRPLL_PREDIV, prediv,
+ SHU_CLRPLL2_RG_RCLRPLL_POSDIV, posdiv);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_phypll1,
+ SHU_PHYPLL1_RG_RPHYPLL_SDM_PCW, pcw,
+ SHU_PHYPLL1_RG_RPHYPLL_SDM_PCW_CHG, 1,
+ SHU_PHYPLL1_RG_RPHYPLL_SDM_FRA_EN, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_clrpll1,
+ SHU_CLRPLL1_RG_RCLRPLL_SDM_PCW, pcw,
+ SHU_CLRPLL1_RG_RCLRPLL_SDM_PCW_CHG, 1,
+ SHU_CLRPLL1_RG_RCLRPLL_SDM_FRA_EN, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_pll1,
+ SHU_PLL1_RG_RPHYPLLGP_CK_SEL, 1,
+ SHU_PLL1_R_SHU_AUTO_PLL_MUX, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_phypll3,
+ SHU_PHYPLL3_RG_RPHYPLL_LVROD_EN, 0,
+ SHU_PHYPLL3_RG_RPHYPLL_RST_DLY, 1,
+ SHU_PHYPLL3_RG_RPHYPLL_FBKSEL, fbk_sel);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_clrpll3,
+ SHU_CLRPLL3_RG_RCLRPLL_LVROD_EN, 0,
+ SHU_CLRPLL3_RG_RCLRPLL_RST_DLY, 1,
+ SHU_CLRPLL3_RG_RCLRPLL_FBKSEL, fbk_sel);
+ if (dvfs_core->dq_ca_open == 1) {
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_clk_ctrl0,
+ SHU_MISC_CLK_CTRL0_M_CK_OPENLOOP_MODE_SEL,
+ dvfs_core->dq_ca_open);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_phypll3,
+ SHU_PHYPLL3_RG_RPHYPLL_MONCK_EN, 1,
+ SHU_PHYPLL3_RG_RPHYPLL_DIV_CK_SEL, div16_ck_sel);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_clrpll3,
+ SHU_CLRPLL3_RG_RCLRPLL_MONCK_EN, 1,
+ SHU_CLRPLL3_RG_RCLRPLL_DIV_CK_SEL, div16_ck_sel);
+ }
+ dramc_dbg("PLL\n");
+}
+
+static void ana_arpi_shuffle_config(ana_top_config *a_cfg, ana_dvfs_core *tr)
+{
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_dll_arpi3,
+ SHU_CA_DLL_ARPI3_RG_ARPI_CLKIEN_EN, 0,
+ SHU_CA_DLL_ARPI3_RG_ARPI_CMD_EN, !(tr->dq_semi_open),
+ SHU_CA_DLL_ARPI3_RG_ARPI_CS_EN, !(tr->dq_semi_open));
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dll_arpi3,
+ SHU_B0_DLL_ARPI3_RG_ARPI_DQSIEN_EN_B0, !(tr->dq_semi_open),
+ SHU_B0_DLL_ARPI3_RG_ARPI_DQ_EN_B0, !(tr->dq_semi_open),
+ SHU_B0_DLL_ARPI3_RG_ARPI_DQM_EN_B0, !(tr->dq_semi_open),
+ SHU_B0_DLL_ARPI3_RG_ARPI_DQS_EN_B0, !(tr->dq_semi_open),
+ SHU_B0_DLL_ARPI3_RG_ARPI_FB_EN_B0, !(tr->dq_semi_open));
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dll_arpi3,
+ SHU_B0_DLL_ARPI3_RG_ARPI_MCTL_EN_B0,
+ (!(tr->dq_semi_open)) && (a_cfg->rank_mode));
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dll_arpi3,
+ SHU_B1_DLL_ARPI3_RG_ARPI_DQSIEN_EN_B1, !(tr->dq_semi_open),
+ SHU_B1_DLL_ARPI3_RG_ARPI_DQ_EN_B1, !(tr->dq_semi_open),
+ SHU_B1_DLL_ARPI3_RG_ARPI_DQM_EN_B1, !(tr->dq_semi_open),
+ SHU_B1_DLL_ARPI3_RG_ARPI_DQS_EN_B1, !(tr->dq_semi_open),
+ SHU_B1_DLL_ARPI3_RG_ARPI_FB_EN_B1, !(tr->dq_semi_open));
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dll_arpi3,
+ SHU_B1_DLL_ARPI3_RG_ARPI_MCTL_EN_B1,
+ (!(tr->dq_semi_open)) && (a_cfg->rank_mode));
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd2,
+ SHU_CA_CMD2_RG_ARPISM_MCK_SEL_CA_SHU, 1,
+ SHU_CA_CMD2_RG_ARPI_TX_CG_SYNC_DIS_CA, 1,
+ SHU_CA_CMD2_RG_ARPI_TX_CG_CA_EN_CA, 1,
+ SHU_CA_CMD2_RG_ARPI_TX_CG_CLK_EN_CA, 1,
+ SHU_CA_CMD2_RG_ARPI_TX_CG_CS_EN_CA, 1,
+ SHU_CA_CMD2_RG_ARPI_PD_MCTL_SEL_CA, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq2,
+ SHU_B0_DQ2_RG_ARPISM_MCK_SEL_B0_SHU, 1,
+ SHU_B0_DQ2_RG_ARPI_TX_CG_SYNC_DIS_B0, 1,
+ SHU_B0_DQ2_RG_ARPI_TX_CG_DQ_EN_B0, 1,
+ SHU_B0_DQ2_RG_ARPI_TX_CG_DQS_EN_B0, 1,
+ SHU_B0_DQ2_RG_ARPI_TX_CG_DQM_EN_B0, 1,
+ SHU_B0_DQ2_RG_ARPI_PD_MCTL_SEL_B0, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq2,
+ SHU_B1_DQ2_RG_ARPISM_MCK_SEL_B1_SHU, 1,
+ SHU_B1_DQ2_RG_ARPI_TX_CG_SYNC_DIS_B1, 1,
+ SHU_B1_DQ2_RG_ARPI_TX_CG_DQ_EN_B1, 1,
+ SHU_B1_DQ2_RG_ARPI_TX_CG_DQS_EN_B1, 1,
+ SHU_B1_DQ2_RG_ARPI_TX_CG_DQM_EN_B1, 1,
+ SHU_B1_DQ2_RG_ARPI_PD_MCTL_SEL_B1, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq7,
+ SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0, 0,
+ SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0, 0,
+ SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq7,
+ SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1, 0,
+ SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1, 0,
+ SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd7,
+ SHU_CA_CMD7_R_DMTX_ARPI_CG_CS_NEW, 0,
+ SHU_CA_CMD7_R_DMTX_ARPI_CG_CMD_NEW, 0);
+}
+
+static void ana_tx_shuffle_config(ana_top_config *a_cfg)
+{
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd14,
+ SHU_CA_CMD14_RG_TX_ARCA_OE_ODTEN_CG_EN_CA, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd13,
+ SHU_CA_CMD13_RG_TX_ARCLK_OE_ODTEN_CG_EN_CA, 0,
+ SHU_CA_CMD13_RG_TX_ARCS_OE_ODTEN_CG_EN_CA, 0);
+
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq13,
+ SHU_B0_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B0, 1,
+ SHU_B0_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B0, 1,
+ SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_EN_B0, 0,
+ SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B0, 0,
+ SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B0, 0,
+ SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B0, 0,
+ SHU_B0_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B0, a_cfg->tx_odt_dis);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq13,
+ SHU_B1_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B1, 1,
+ SHU_B1_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B1, 1,
+ SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_EN_B1, 0,
+ SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B1, 0,
+ SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B1, 0,
+ SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B1, 0,
+ SHU_B1_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B1, a_cfg->tx_odt_dis);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq14,
+ SHU_B0_DQ14_RG_TX_ARDQ_OE_ODTEN_CG_EN_B0, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq14,
+ SHU_B1_DQ14_RG_TX_ARDQ_OE_ODTEN_CG_EN_B1, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq13,
+ SHU_B0_DQ13_RG_TX_ARDQS_MCKIO_SEL_B0, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq13,
+ SHU_B1_DQ13_RG_TX_ARDQS_MCKIO_SEL_B1, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq14,
+ SHU_B0_DQ14_RG_TX_ARDQ_MCKIO_SEL_B0, 0,
+ SHU_B0_DQ14_RG_TX_ARWCK_MCKIO_SEL_B0, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq14,
+ SHU_B1_DQ14_RG_TX_ARDQ_MCKIO_SEL_B1, 0,
+ SHU_B1_DQ14_RG_TX_ARWCK_MCKIO_SEL_B1, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq13,
+ SHU_B0_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B0, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq13,
+ SHU_B1_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B1, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd13,
+ SHU_CA_CMD13_RG_TX_ARCA_DLY_LAT_EN_CA, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd2,
+ SHU_CA_CMD2_RG_ARPI_OFFSET_LAT_EN_CA, 0,
+ SHU_CA_CMD2_RG_ARPI_OFFSET_ASYNC_EN_CA, 0);
+}
+
+static void dig_phy_shu_misc_cg_ctrl(void)
+{
+ setbits32(&ch[0].phy_ao.misc_shu_cg_ctrl0, 0x33400000);
+}
+
+static void ana_clk_div_config_setting(ana_dvfs_core *tr, ana_top_config *a_cfg)
+{
+ u8 tx_ardq_sermode=0;
+ u8 tx_arcr_sermode=0;
+ u8 ardll_sermode_b=0;
+ u8 ardll_sermode_c=0;
+
+ dramc_dbg("ANA CLOCK DIV configuration\n");
+ switch (tr->dq_p2s_ratio) {
+ case 4 :
+ tx_ardq_sermode = 1;
+ break;
+ case 8 :
+ tx_ardq_sermode = 2;
+ break;
+ case 16:
+ tx_ardq_sermode = 3;
+ break;
+ default: dramc_dbg("ERROR: tr->dq_p2s_ratio= %2d, Not support!!",tr->dq_p2s_ratio);
+ break;
+ }
+
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq14,
+ SHU_B0_DQ14_RG_TX_ARDQ_SER_MODE_B0, tx_ardq_sermode);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq14,
+ SHU_B1_DQ14_RG_TX_ARDQ_SER_MODE_B1, tx_ardq_sermode);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq6,
+ SHU_B0_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B0, tx_ardq_sermode);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq6,
+ SHU_B1_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B1, tx_ardq_sermode);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd11,
+ SHU_CA_CMD11_RG_RX_ARCA_DES_MODE_CA, (tr->dq_p2s_ratio == 16 ) ? 3 : 2);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq11,
+ SHU_B0_DQ11_RG_RX_ARDQ_DES_MODE_B0, (tr->dq_p2s_ratio == 16 ) ? 3 : 2);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq11,
+ SHU_B1_DQ11_RG_RX_ARDQ_DES_MODE_B1, (tr->dq_p2s_ratio == 16 ) ? 3 : 2);
+
+ switch (tr->ca_p2s_ratio) {
+ case 2 :
+ tx_arcr_sermode = (0 + tr->ca_full_rate);
+ break;
+ case 4 :
+ tx_arcr_sermode = (1 + tr->ca_full_rate);
+ break;
+ case 8:
+ tx_arcr_sermode = (2 + tr->ca_full_rate);
+ break;
+ default: dramc_dbg("ERROR: tr->ca_p2s_ratio= %2d, Not support!!",tr->ca_p2s_ratio);
+ break;
+ }
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd14,
+ SHU_CA_CMD14_RG_TX_ARCA_SER_MODE_CA, tx_arcr_sermode);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd6,
+ SHU_CA_CMD6_RG_RX_ARCMD_RANK_SEL_SER_MODE, tx_arcr_sermode);
+
+ switch (tr->dq_aamck_div) {
+ case 2 :
+ ardll_sermode_b = 1;
+ break;
+ case 4 :
+ ardll_sermode_b = 2;
+ break;
+ case 8:
+ ardll_sermode_b = 3;
+ break;
+ default: dramc_dbg("WARN: tr->dq_aamck_div= %2d, Because of dq_semi_open, It's don't care.",tr->dq_aamck_div);
+ break;
+ }
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dll1,
+ SHU_B0_DLL1_RG_ARDLL_SER_MODE_B0, ardll_sermode_b);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dll1,
+ SHU_B1_DLL1_RG_ARDLL_SER_MODE_B1, ardll_sermode_b);
+
+ switch (tr->ca_admck_div) {
+ case 2 :
+ ardll_sermode_c = 1;
+ break;
+ case 4 :
+ ardll_sermode_c = 2;
+ break;
+ case 8:
+ ardll_sermode_c = 3;
+ break;
+ default: dramc_dbg("ERROR: tr->ca_admck_div= %2d, Not support!!",tr->ca_admck_div);
+ break;
+ }
+ dramc_set_broadcast(DRAMC_BROADCAST_OFF);
+ for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
+ SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_dll1,
+ SHU_CA_DLL1_RG_ARDLL_SER_MODE_CA, ardll_sermode_c);
+
+ dramc_set_broadcast(DRAMC_BROADCAST_ON);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq6,
+ SHU_B0_DQ6_RG_ARPI_SOPEN_EN_B0, tr->dq_semi_open,
+ SHU_B0_DQ6_RG_ARPI_OPEN_EN_B0, tr->dq_ca_open);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq6,
+ SHU_B1_DQ6_RG_ARPI_SOPEN_EN_B1, tr->dq_semi_open,
+ SHU_B1_DQ6_RG_ARPI_OPEN_EN_B1, tr->dq_ca_open);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq1,
+ SHU_B0_DQ1_RG_ARPI_MIDPI_EN_B0,
+ !(tr->dq_semi_open) && (!(tr->dq_ckdiv4_en)),
+ SHU_B0_DQ1_RG_ARPI_MIDPI_CKDIV4_EN_B0,
+ !(tr->dq_semi_open) && (tr->dq_ckdiv4_en),
+ SHU_B0_DQ1_RG_ARPI_MIDPI_8PH_DLY_B0, tr->ph8_dly);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq1,
+ SHU_B1_DQ1_RG_ARPI_MIDPI_EN_B1,
+ !(tr->dq_semi_open) && (!(tr->dq_ckdiv4_en)),
+ SHU_B1_DQ1_RG_ARPI_MIDPI_CKDIV4_EN_B1,
+ !(tr->dq_semi_open) && (tr->dq_ckdiv4_en),
+ SHU_B1_DQ1_RG_ARPI_MIDPI_8PH_DLY_B1, tr->ph8_dly);
+
+ if (tr->ca_semi_open == 0) {
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd6,
+ SHU_CA_CMD6_RG_ARPI_SOPEN_EN_CA, 0,
+ SHU_CA_CMD6_RG_ARPI_SOPEN_CKGEN_EN_CA, 0,
+ SHU_CA_CMD6_RG_ARPI_OFFSET_DQSIEN_CA, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_dll_arpi3,
+ SHU_CA_DLL_ARPI3_RG_ARPI_FB_EN_CA, 1,
+ SHU_CA_DLL_ARPI3_RG_ARPI_CLK_EN, 1,
+ SHU_CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA, 1);
+ } else {
+ dramc_set_broadcast(DRAMC_BROADCAST_OFF);
+ for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
+ SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_cmd6,
+ SHU_CA_CMD6_RG_ARPI_SOPEN_EN_CA, 1,
+ SHU_CA_CMD6_RG_ARPI_SOPEN_CKGEN_EN_CA, 1,
+ SHU_CA_CMD6_RG_ARPI_OFFSET_DQSIEN_CA, 16);
+ SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_dll_arpi3,
+ SHU_CA_DLL_ARPI3_RG_ARPI_FB_EN_CA, 1,
+ SHU_CA_DLL_ARPI3_RG_ARPI_CLK_EN, 1);
+ }
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_dll_arpi3,
+ SHU_CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA, 1);
+ SET32_BITFIELDS(&ch[1].phy_ao.shu_ca_dll_arpi3,
+ SHU_CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA, 0);
+ dramc_set_broadcast(DRAMC_BROADCAST_ON);
+ }
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd6,
+ SHU_CA_CMD6_RG_ARPI_OPEN_EN_CA, tr->dq_ca_open);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd13,
+ SHU_CA_CMD13_RG_TX_ARCA_FRATE_EN_CA, tr->ca_full_rate);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd1,
+ SHU_CA_CMD1_RG_ARPI_MIDPI_8PH_DLY_CA, tr->ph8_dly);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd1,
+ SHU_CA_CMD1_RG_ARPI_MIDPI_CKDIV4_PREDIV_EN_CA, tr->ca_prediv_en);
+
+ if (tr->semi_open_ca_pick_mck_ratio == 4)
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd6,
+ SHU_CA_CMD6_RG_ARPI_SOPEN_CKGEN_DIV_CA, 0);
+ else if (tr->semi_open_ca_pick_mck_ratio == 8)
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd6,
+ SHU_CA_CMD6_RG_ARPI_SOPEN_CKGEN_DIV_CA, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dll1,
+ SHU_B0_DLL1_RG_ARDLL_TRACKING_CA_EN_B0, tr->dq_track_ca_en);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dll1,
+ SHU_B1_DLL1_RG_ARDLL_TRACKING_CA_EN_B1, tr->dq_track_ca_en);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_dll_arpi2,
+ SHU_CA_DLL_ARPI2_RG_ARPI_CG_CLKIEN, 1);
+}
+
+static void ana_dll_shuffle_config(dram_freq_grp freq_group, ana_top_config *a_cfg)
+{
+ u8 gain = 0;
+ if (freq_group <= DDRFREQ_1600) {
+ gain = 2;
+ dramc_dbg("Add DLL Gain = %d\n",gain);
+ }
+
+ dramc_dbg("DLL\n");
+ if (a_cfg->dll_async_en == 1) {
+ dramc_set_broadcast(DRAMC_BROADCAST_OFF);
+ for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
+ SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_dll0,
+ SHU_CA_DLL0_RG_ARDLL_GAIN_CA,
+ (a_cfg->all_slave_en == 0) ? 6 : 7,
+ SHU_CA_DLL0_RG_ARDLL_IDLECNT_CA,
+ (a_cfg->all_slave_en == 0) ? 9 : 7,
+ SHU_CA_DLL0_RG_ARDLL_FAST_PSJP_CA,
+ !(a_cfg->all_slave_en),
+ SHU_CA_DLL0_RG_ARDLL_GEAR2_PSJP_CA, 0,
+ SHU_CA_DLL0_RG_ARDLL_FASTPJ_CK_SEL_CA,
+ a_cfg->all_slave_en);
+ SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_dll1,
+ SHU_CA_DLL1_RG_ARDLL_PHDET_OUT_SEL_CA,
+ a_cfg->all_slave_en,
+ SHU_CA_DLL1_RG_ARDLL_PHDET_IN_SWAP_CA,
+ a_cfg->all_slave_en,
+ SHU_CA_DLL1_RG_ARDLL_PGAIN_CA, 0,
+ SHU_CA_DLL1_RG_ARDLL_PSJP_EN_CA, 1,
+ SHU_CA_DLL1_RG_ARDLL_PHDIV_CA, 1,
+ SHU_CA_DLL1_RG_ARDLL_UDIV_EN_CA, 1,
+ SHU_CA_DLL1_RG_ARDLL_PS_EN_CA, 1,
+ SHU_CA_DLL1_RG_ARDLL_PD_CK_SEL_CA,
+ !(a_cfg->all_slave_en));
+ }
+ dramc_set_broadcast(DRAMC_BROADCAST_ON);
+ } else {
+ dramc_set_broadcast(DRAMC_BROADCAST_OFF);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_dll0,
+ SHU_CA_DLL0_RG_ARDLL_GAIN_CA,
+ (a_cfg->all_slave_en == 0) ? 6 + gain : 7 + gain,
+ SHU_CA_DLL0_RG_ARDLL_IDLECNT_CA,
+ (a_cfg->all_slave_en == 0) ? 9 : 7,
+ SHU_CA_DLL0_RG_ARDLL_FAST_PSJP_CA,
+ !(a_cfg->all_slave_en),
+ SHU_CA_DLL0_RG_ARDLL_GEAR2_PSJP_CA, 0,
+ SHU_CA_DLL0_RG_ARDLL_FASTPJ_CK_SEL_CA,
+ a_cfg->all_slave_en);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_dll1,
+ SHU_CA_DLL1_RG_ARDLL_PHDET_OUT_SEL_CA,
+ a_cfg->all_slave_en,
+ SHU_CA_DLL1_RG_ARDLL_PHDET_IN_SWAP_CA,
+ a_cfg->all_slave_en,
+ SHU_CA_DLL1_RG_ARDLL_PGAIN_CA, 0,
+ SHU_CA_DLL1_RG_ARDLL_PSJP_EN_CA, 1,
+ SHU_CA_DLL1_RG_ARDLL_PHDIV_CA, 1,
+ SHU_CA_DLL1_RG_ARDLL_UDIV_EN_CA, 1,
+ SHU_CA_DLL1_RG_ARDLL_PS_EN_CA, 1,
+ SHU_CA_DLL1_RG_ARDLL_PD_CK_SEL_CA,
+ !(a_cfg->all_slave_en));
+ SET32_BITFIELDS(&ch[1].phy_ao.shu_ca_dll0,
+ SHU_CA_DLL0_RG_ARDLL_GAIN_CA, 7+gain,
+ SHU_CA_DLL0_RG_ARDLL_IDLECNT_CA, 7,
+ SHU_CA_DLL0_RG_ARDLL_FAST_PSJP_CA, 0,
+ SHU_CA_DLL0_RG_ARDLL_GEAR2_PSJP_CA, 0,
+ SHU_CA_DLL0_RG_ARDLL_FASTPJ_CK_SEL_CA, 1);
+ SET32_BITFIELDS(&ch[1].phy_ao.shu_ca_dll1,
+ SHU_CA_DLL1_RG_ARDLL_PHDET_OUT_SEL_CA, 1,
+ SHU_CA_DLL1_RG_ARDLL_PHDET_IN_SWAP_CA, 1,
+ SHU_CA_DLL1_RG_ARDLL_PGAIN_CA, 0,
+ SHU_CA_DLL1_RG_ARDLL_PSJP_EN_CA, 1,
+ SHU_CA_DLL1_RG_ARDLL_PHDIV_CA, 1,
+ SHU_CA_DLL1_RG_ARDLL_UDIV_EN_CA, 1,
+ SHU_CA_DLL1_RG_ARDLL_PS_EN_CA, 1,
+ SHU_CA_DLL1_RG_ARDLL_PD_CK_SEL_CA, 0);
+ dramc_set_broadcast(DRAMC_BROADCAST_ON);
+ }
+
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dll0,
+ SHU_B0_DLL0_RG_ARDLL_GAIN_B0, 7+gain,
+ SHU_B0_DLL0_RG_ARDLL_IDLECNT_B0, 7,
+ SHU_B0_DLL0_RG_ARDLL_FAST_PSJP_B0, 0,
+ SHU_B0_DLL0_RG_ARDLL_GEAR2_PSJP_B0, 0,
+ SHU_B0_DLL0_RG_ARDLL_FASTPJ_CK_SEL_B0, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dll1,
+ SHU_B0_DLL1_RG_ARDLL_PHDET_OUT_SEL_B0, 1,
+ SHU_B0_DLL1_RG_ARDLL_PHDET_IN_SWAP_B0, 1,
+ SHU_B0_DLL1_RG_ARDLL_PGAIN_B0, 0,
+ SHU_B0_DLL1_RG_ARDLL_PSJP_EN_B0, 1,
+ SHU_B0_DLL1_RG_ARDLL_PHDIV_B0, 1,
+ SHU_B0_DLL1_RG_ARDLL_UDIV_EN_B0, 1,
+ SHU_B0_DLL1_RG_ARDLL_PS_EN_B0, 1,
+ SHU_B0_DLL1_RG_ARDLL_PD_CK_SEL_B0, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dll0,
+ SHU_B1_DLL0_RG_ARDLL_GAIN_B1, 7+gain,
+ SHU_B1_DLL0_RG_ARDLL_IDLECNT_B1, 7,
+ SHU_B1_DLL0_RG_ARDLL_FAST_PSJP_B1, 0,
+ SHU_B1_DLL0_RG_ARDLL_GEAR2_PSJP_B1, 0,
+ SHU_B1_DLL0_RG_ARDLL_FASTPJ_CK_SEL_B1, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dll1,
+ SHU_B1_DLL1_RG_ARDLL_PHDET_OUT_SEL_B1, 1,
+ SHU_B1_DLL1_RG_ARDLL_PHDET_IN_SWAP_B1, 1,
+ SHU_B1_DLL1_RG_ARDLL_PGAIN_B1, 0,
+ SHU_B1_DLL1_RG_ARDLL_PSJP_EN_B1, 1,
+ SHU_B1_DLL1_RG_ARDLL_PHDIV_B1, 1,
+ SHU_B1_DLL1_RG_ARDLL_UDIV_EN_B1, 1,
+ SHU_B1_DLL1_RG_ARDLL_PS_EN_B1, 1,
+ SHU_B1_DLL1_RG_ARDLL_PD_CK_SEL_B1, 0);
+}
+
+static void ana_rx_shuffle_config(dramc_subsys_config *subsys)
+{
+ u8 rdqs_se_en;
+ u8 dqsien_mode;
+ u8 rank_mode;
+
+ rdqs_se_en = 0;
+ dqsien_mode = subsys->dfs_gp->dqsien_mode;
+ rank_mode = subsys->a_cfg->rank_mode;
+
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq10,
+ SHU_B0_DQ10_RG_RX_ARDQS_SE_EN_B0, rdqs_se_en,
+ SHU_B0_DQ10_RG_RX_ARDQS_DQSIEN_MODE_B0, dqsien_mode,
+ SHU_B0_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B0, 1,
+ SHU_B0_DQ10_RG_RX_ARDQS_RANK_SEL_LAT_EN_B0, rank_mode,
+ SHU_B0_DQ10_RG_RX_ARDQS_DQSIEN_RANK_SEL_LAT_EN_B0, rank_mode);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq11,
+ SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B0, rank_mode,
+ SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B0, rank_mode);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq2,
+ SHU_B0_DQ2_RG_ARPI_OFFSET_LAT_EN_B0, rank_mode,
+ SHU_B0_DQ2_RG_ARPI_OFFSET_ASYNC_EN_B0, rank_mode);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq10,
+ SHU_B1_DQ10_RG_RX_ARDQS_SE_EN_B1, rdqs_se_en,
+ SHU_B1_DQ10_RG_RX_ARDQS_DQSIEN_MODE_B1, dqsien_mode,
+ SHU_B1_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B1, 1,
+ SHU_B1_DQ10_RG_RX_ARDQS_RANK_SEL_LAT_EN_B1, rank_mode,
+ SHU_B1_DQ10_RG_RX_ARDQS_DQSIEN_RANK_SEL_LAT_EN_B1, rank_mode);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq11,
+ SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B1, rank_mode,
+ SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B1, rank_mode);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq2,
+ SHU_B1_DQ2_RG_ARPI_OFFSET_LAT_EN_B1, rank_mode,
+ SHU_B1_DQ2_RG_ARPI_OFFSET_ASYNC_EN_B1, rank_mode);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq10,
+ SHU_B0_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B0, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq2,
+ SHU_B0_DQ2_RG_ARPI_OFFSET_LAT_EN_B0, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq10,
+ SHU_B1_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B1, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq2,
+ SHU_B1_DQ2_RG_ARPI_OFFSET_LAT_EN_B1, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd10,
+ SHU_CA_CMD10_RG_RX_ARCLK_RANK_SEL_LAT_EN_CA, 1,
+ SHU_CA_CMD10_RG_RX_ARCLK_DQSIEN_RANK_SEL_LAT_EN_CA, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd11,
+ SHU_CA_CMD11_RG_RX_ARCA_RANK_SEL_LAT_EN_CA, 1);
+}
+
+static void ana_config_nonshuffle(dram_freq_grp freq_group, ana_top_config *a_cfg)
+{
+ suspend_on();
+ spm_control(a_cfg);
+ ana_tx_nonshuffle_config(a_cfg);
+ ana_rx_nonshuffle_config();
+ dig_dcm_nonshuffle_config();
+ ana_imp_configure();
+ ana_dll_non_shuffle_config(freq_group, a_cfg);
+}
+
+static void ana_config_shuffle(dram_freq_grp freq_group, dramc_subsys_config *subsys)
+{
+ ana_top_config *a_cfg = subsys->a_cfg;
+ ana_dvfs_core *dvfs_core = subsys->dvfs_core;
+
+ ana_pll_shuffle_Config(dvfs_core);
+ ana_arpi_shuffle_config(a_cfg, dvfs_core);
+ ana_tx_shuffle_config(a_cfg);
+ ana_rx_shuffle_config(subsys);
+ dig_phy_shu_misc_cg_ctrl();
+ ana_clk_div_config_setting(dvfs_core, a_cfg);
+ ana_dll_shuffle_config(freq_group, a_cfg);
+}
+
+static void ana_phy_config(dram_freq_grp freq_group, dramc_subsys_config *subsys)
+{
+ ana_top_config *a_cfg = subsys->a_cfg;
+
+ ana_config_nonshuffle(freq_group, a_cfg);
+ ana_config_shuffle(freq_group, subsys);
+}
+
+static void ana_clockoff_sequence(void)
+{
+ SET32_BITFIELDS(&ch[0].phy_ao.misc_cg_ctrl0,
+ MISC_CG_CTRL0_CLK_MEM_SEL, 0,
+ MISC_CG_CTRL0_W_CHG_MEM, 1);
+ udelay(1);
+ SET32_BITFIELDS(&ch[0].phy_ao.misc_cg_ctrl0,
+ MISC_CG_CTRL0_W_CHG_MEM, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dll1,
+ SHU_B0_DLL1_RG_ARDLL_PHDET_EN_B0, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dll1,
+ SHU_B1_DLL1_RG_ARDLL_PHDET_EN_B1, 0);
+ dramc_set_broadcast(DRAMC_BROADCAST_OFF);
+ for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
+ SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_dll1,
+ SHU_CA_DLL1_RG_ARDLL_PHDET_EN_CA, 0);
+
+ dramc_set_broadcast(DRAMC_BROADCAST_ON);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dll_arpi2,
+ SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_B0, 0x1,
+ SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B0, 0x1,
+ SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCTL_B0, 0x1,
+ SHU_B0_DLL_ARPI2_RG_ARPI_CG_FB_B0, 0x1,
+ SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQS_B0, 0x1,
+ SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQM_B0, 0x1,
+ SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQ_B0, 0x1,
+ SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B0, 0x1,
+ SHU_B0_DLL_ARPI2_RG_ARPI_MPDIV_CG_B0, 0x1);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dll_arpi2,
+ SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCK_B1, 0x1,
+ SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B1, 0x1,
+ SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCTL_B1, 0x1,
+ SHU_B1_DLL_ARPI2_RG_ARPI_CG_FB_B1, 0x1,
+ SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQS_B1, 0x1,
+ SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQM_B1, 0x1,
+ SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQ_B1, 0x1,
+ SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B1, 0x1,
+ SHU_B1_DLL_ARPI2_RG_ARPI_MPDIV_CG_B1, 0x1);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_dll_arpi2,
+ SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCK_CA, 0x1,
+ SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_CA, 0x1,
+ SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCTL_CA, 0x1,
+ SHU_CA_DLL_ARPI2_RG_ARPI_CG_FB_CA, 0x1,
+ SHU_CA_DLL_ARPI2_RG_ARPI_CG_CS, 0x1,
+ SHU_CA_DLL_ARPI2_RG_ARPI_CG_CLK, 0x1,
+ SHU_CA_DLL_ARPI2_RG_ARPI_CG_CMD, 0x1,
+ SHU_CA_DLL_ARPI2_RG_ARPI_CG_CLKIEN, 0x1,
+ SHU_CA_DLL_ARPI2_RG_ARPI_MPDIV_CG_CA, 0x1);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_pll2,
+ SHU_PLL2_RG_RPHYPLL_ADA_MCK8X_EN_SHU, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.phypll2,
+ PHYPLL2_RG_RPHYPLL_AD_MCK8X_EN, 0,
+ PHYPLL2_RG_RPHYPLL_ADA_MCK8X_EN, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.phypll0, PHYPLL0_RG_RPHYPLL_EN, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.phypll2, PHYPLL2_RG_RPHYPLL_RESETB, 0);
+}
+
+static void ana_pll_sequence(void)
+{
+ SET32_BITFIELDS(&ch[0].phy_ao.phypll2, PHYPLL2_RG_RPHYPLL_RESETB, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.phypll0, PHYPLL0_RG_RPHYPLL_EN, 1);
+ udelay(20);
+}
+
+static void ana_midpi_sequence(ana_dvfs_core *dvfs_core)
+{
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq1,
+ SHU_B0_DQ1_RG_ARPI_MIDPI_LDO_VREF_SEL_B0, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq1,
+ SHU_B1_DQ1_RG_ARPI_MIDPI_LDO_VREF_SEL_B1, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd1,
+ SHU_CA_CMD1_RG_ARPI_MIDPI_LDO_VREF_SEL_CA, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dll_arpi2,
+ SHU_B0_DLL_ARPI2_RG_ARPI_MPDIV_CG_B0, 1,
+ SHU_B0_DLL_ARPI2_RG_ARPI_CG_FB_B0, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dll_arpi2,
+ SHU_B1_DLL_ARPI2_RG_ARPI_MPDIV_CG_B1, 1,
+ SHU_B1_DLL_ARPI2_RG_ARPI_CG_FB_B1, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_dll_arpi2,
+ SHU_CA_DLL_ARPI2_RG_ARPI_MPDIV_CG_CA, 1,
+ SHU_CA_DLL_ARPI2_RG_ARPI_CG_FB_CA, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dll_arpi2,
+ SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_B0, 0x1,
+ SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B0, 0x1,
+ SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCTL_B0, 0x1,
+ SHU_B0_DLL_ARPI2_RG_ARPI_CG_FB_B0, 0x1,
+ SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQS_B0, 0x1,
+ SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQM_B0, 0x1,
+ SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQ_B0, 0x1,
+ SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B0, 0x1,
+ SHU_B0_DLL_ARPI2_RG_ARPI_MPDIV_CG_B0, 0x1);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dll_arpi2,
+ SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCK_B1, 0x1,
+ SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B1, 0x1,
+ SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCTL_B1, 0x1,
+ SHU_B1_DLL_ARPI2_RG_ARPI_CG_FB_B1, 0x1,
+ SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQS_B1, 0x1,
+ SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQM_B1, 0x1,
+ SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQ_B1, 0x1,
+ SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B1, 0x1,
+ SHU_B1_DLL_ARPI2_RG_ARPI_MPDIV_CG_B1, 0x1);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_dll_arpi2,
+ SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCK_CA, 0x1,
+ SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_CA, 0x1,
+ SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCTL_CA, 0x1,
+ SHU_CA_DLL_ARPI2_RG_ARPI_CG_FB_CA, 0x1,
+ SHU_CA_DLL_ARPI2_RG_ARPI_CG_CS, 0x1,
+ SHU_CA_DLL_ARPI2_RG_ARPI_CG_CLK, 0x1,
+ SHU_CA_DLL_ARPI2_RG_ARPI_CG_CMD, 0x1,
+ SHU_CA_DLL_ARPI2_RG_ARPI_CG_CLKIEN, 0x1,
+ SHU_CA_DLL_ARPI2_RG_ARPI_MPDIV_CG_CA, 0x1);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_pll2,
+ SHU_PLL2_RG_RPHYPLL_ADA_MCK8X_EN_SHU, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.phypll2,
+ PHYPLL2_RG_RPHYPLL_AD_MCK8X_EN, 0,
+ PHYPLL2_RG_RPHYPLL_ADA_MCK8X_EN, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd1,
+ SHU_CA_CMD1_RG_ARPI_MIDPI_EN_CA, !(dvfs_core->ca_ckdiv4_en),
+ SHU_CA_CMD1_RG_ARPI_MIDPI_CKDIV4_EN_CA, dvfs_core->ca_ckdiv4_en);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd1,
+ SHU_CA_CMD1_RG_ARPI_MIDPI_CKDIV4_PREDIV_EN_CA, dvfs_core->ca_prediv_en);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].b0_shu_midpi_ctrl,
+ B0_SHU_MIDPI_CTRL_MIDPI_ENABLE_B0,
+ (!(dvfs_core->dq_semi_open)) && (!(dvfs_core->dq_ckdiv4_en)),
+ B0_SHU_MIDPI_CTRL_MIDPI_DIV4_ENABLE_B0,
+ (!(dvfs_core->dq_semi_open)) && (dvfs_core->dq_ckdiv4_en));
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].b0_shu_midpi_ctrl,
+ B1_SHU_MIDPI_CTRL_MIDPI_ENABLE_B1,
+ (!(dvfs_core->dq_semi_open)) && (!(dvfs_core->dq_ckdiv4_en)),
+ B1_SHU_MIDPI_CTRL_MIDPI_DIV4_ENABLE_B1,
+ (!(dvfs_core->dq_semi_open)) && (dvfs_core->dq_ckdiv4_en));
+ SET32_BITFIELDS(&ch[0].phy_ao.ca_shu_midpi_ctrl,
+ CA_SHU_MIDPI_CTRL_MIDPI_ENABLE_CA, !(dvfs_core->ca_ckdiv4_en),
+ CA_SHU_MIDPI_CTRL_MIDPI_DIV4_ENABLE_CA, dvfs_core->ca_ckdiv4_en);
+ SET32_BITFIELDS(&ch[0].phy_ao.ca_dll_arpi0,
+ CA_DLL_ARPI0_RG_ARPI_RESETB_CA, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dll_arpi0,
+ B0_DLL_ARPI0_RG_ARPI_RESETB_B0, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dll_arpi0,
+ B1_DLL_ARPI0_RG_ARPI_RESETB_B1, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.ca_dll_arpi0,
+ CA_DLL_ARPI0_RG_ARPI_RESETB_CA, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dll_arpi0,
+ B0_DLL_ARPI0_RG_ARPI_RESETB_B0, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dll_arpi0,
+ B1_DLL_ARPI0_RG_ARPI_RESETB_B1, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_pll2,
+ SHU_PLL2_RG_RPHYPLL_ADA_MCK8X_EN_SHU, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.phypll2,
+ PHYPLL2_RG_RPHYPLL_AD_MCK8X_EN, 1,
+ PHYPLL2_RG_RPHYPLL_ADA_MCK8X_EN, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dll_arpi2,
+ SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_B0, 0x0,
+ SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B0, 0x0,
+ SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCTL_B0, 0x0,
+ SHU_B0_DLL_ARPI2_RG_ARPI_CG_FB_B0, 0x0,
+ SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQS_B0, 0x0,
+ SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQM_B0, 0x0,
+ SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQ_B0, 0x0,
+ SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B0, 0x0,
+ SHU_B0_DLL_ARPI2_RG_ARPI_MPDIV_CG_B0, dvfs_core->dq_semi_open);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dll_arpi2,
+ SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCK_B1, 0x0,
+ SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B1, 0x0,
+ SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCTL_B1, 0x0,
+ SHU_B1_DLL_ARPI2_RG_ARPI_CG_FB_B1, 0x0,
+ SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQS_B1, 0x0,
+ SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQM_B1, 0x0,
+ SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQ_B1, 0x0,
+ SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B1, 0x0,
+ SHU_B1_DLL_ARPI2_RG_ARPI_MPDIV_CG_B1, dvfs_core->dq_semi_open);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_dll_arpi2,
+ SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCK_CA, 0x0,
+ SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_CA, 0x0,
+ SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCTL_CA, 0x0,
+ SHU_CA_DLL_ARPI2_RG_ARPI_CG_FB_CA, 0x0,
+ SHU_CA_DLL_ARPI2_RG_ARPI_CG_CS, 0x0,
+ SHU_CA_DLL_ARPI2_RG_ARPI_CG_CLK, 0x0,
+ SHU_CA_DLL_ARPI2_RG_ARPI_CG_CMD, 0x0,
+ SHU_CA_DLL_ARPI2_RG_ARPI_CG_CLKIEN, 0x0,
+ SHU_CA_DLL_ARPI2_RG_ARPI_MPDIV_CG_CA, 0x0);
+}
+
+static void ana_clock_switch(ana_dvfs_core *a_dvfs_cor)
+{
+ if (a_dvfs_cor->dq_ca_open) {
+ SET32_BITFIELDS(&ch[0].phy_ao.misc_cg_ctrl0,
+ MISC_CG_CTRL0_RESERVED_MISC_CG_CTRL0_BIT3_1, 1);
+ udelay(1);
+ SET32_BITFIELDS(&ch[0].phy_ao.misc_cg_ctrl0,
+ MISC_CG_CTRL0_RESERVED_MISC_CG_CTRL0_BIT3_1, 0);
+ }
+ dramc_set_broadcast(DRAMC_BROADCAST_OFF);
+ for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
+ SET32_BITFIELDS(&ch[chn].phy_ao.misc_ckmux_sel,
+ MISC_CKMUX_SEL_R_PHYCTRLDCM, 1,
+ MISC_CKMUX_SEL_R_PHYCTRLMUX, 1);
+
+ dramc_set_broadcast(DRAMC_BROADCAST_ON);
+ SET32_BITFIELDS(&ch[0].phy_ao.misc_cg_ctrl0,
+ MISC_CG_CTRL0_CLK_MEM_SEL, 1,
+ MISC_CG_CTRL0_W_CHG_MEM, 1);
+
+ udelay(1);
+ SET32_BITFIELDS(&ch[0].phy_ao.misc_cg_ctrl0,
+ MISC_CG_CTRL0_W_CHG_MEM, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.misc_cg_ctrl0,
+ MISC_CG_CTRL0_RG_FREERUN_MCK_CG, 1);
+ if (a_dvfs_cor->dq_ca_open)
+ SET32_BITFIELDS(&ch[0].phy_ao.misc_cg_ctrl0,
+ MISC_CG_CTRL0_RESERVED_MISC_CG_CTRL0_BIT7, 1);
+}
+
+static void ana_dll_sequence(ana_dvfs_core *dvfs_core, ana_top_config *a_cfg)
+{
+ u8 dll_async_en;
+ u8 all_slave_en;
+
+ dll_async_en = a_cfg->dll_async_en;
+ all_slave_en = a_cfg->all_slave_en;
+
+ dramc_dbg("[ANA_INIT] DLL >>\n");
+ SET32_BITFIELDS(&ch[0].phy_ao.ca_cmd8,
+ CA_CMD8_RG_ARDLL_RESETB_CA, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq8,
+ B0_DQ8_RG_ARDLL_RESETB_B0, 1);
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq8,
+ B1_DQ8_RG_ARDLL_RESETB_B1, 1);
+ if (all_slave_en == 1) {
+ dramc_set_broadcast(DRAMC_BROADCAST_OFF);
+ for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
+ SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_dll1,
+ SHU_CA_DLL1_RG_ARDLL_PHDET_EN_CA, 1);
+
+ dramc_set_broadcast(DRAMC_BROADCAST_ON);
+ udelay(1);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dll1,
+ SHU_B0_DLL1_RG_ARDLL_PHDET_EN_B0, !(dvfs_core->dq_semi_open));
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dll1,
+ SHU_B1_DLL1_RG_ARDLL_PHDET_EN_B1, !(dvfs_core->dq_semi_open));
+ udelay(1);
+ } else {
+ dramc_set_broadcast(DRAMC_BROADCAST_OFF);
+ if (dll_async_en == 1) {
+ for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
+ SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_dll1,
+ SHU_CA_DLL1_RG_ARDLL_PHDET_EN_CA, 1);
+ udelay(1);
+ } else {
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_dll1,
+ SHU_CA_DLL1_RG_ARDLL_PHDET_EN_CA, 1);
+ udelay(1);
+ SET32_BITFIELDS(&ch[1].phy_ao.shu_ca_dll1,
+ SHU_CA_DLL1_RG_ARDLL_PHDET_EN_CA, 1);
+ udelay(1);
+ }
+ dramc_set_broadcast(DRAMC_BROADCAST_ON);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dll1,
+ SHU_B0_DLL1_RG_ARDLL_PHDET_EN_B0, !(dvfs_core->dq_semi_open));
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dll1,
+ SHU_B1_DLL1_RG_ARDLL_PHDET_EN_B1, !(dvfs_core->dq_semi_open));
+ udelay(1);
+ }
+}
+
+void ana_clk_div_config( ana_dvfs_core *tr, dvfs_group_config *dfs)
+{
+ u32 semi_open_fmin = 300;
+ u32 semi_open_fmax = 500;
+ u32 pi_fmin = 600;
+ u32 dq_pick;
+ u32 ca_pick;
+ u32 ca_mckio;
+ u32 mckio_semi = 0;
+ u16 data_rate = dfs->data_rate;
+ tr->dq_p2s_ratio = dfs->dq_p2s_ratio;
+ tr->ckr = dfs->ckr;
+
+ tr->ca_p2s_ratio = tr->dq_p2s_ratio/tr->ckr;
+ tr->dq_ca_open = ( data_rate < (semi_open_fmin * 2)) ? 1 : 0;
+ tr->dq_semi_open = ( data_rate/2 < pi_fmin) ? (1-tr->dq_ca_open) :
+ ((data_rate <= semi_open_fmax*2) ? (1-tr->dq_ca_open) : 0);
+ tr->ca_semi_open = (( data_rate/(tr->ckr*2) < pi_fmin) ?
+ ((data_rate/(tr->ckr*2) > semi_open_fmax) ? 0 :
+ (((tr->ca_p2s_ratio>2)||(tr->dq_semi_open)) * (1-tr->dq_ca_open))) :
+ tr->dq_semi_open);
+ tr->ca_full_rate = (tr->dq_ca_open == 1) ? ((tr->ckr>1)?1:0) :
+ ((tr->dq_semi_open*tr->ca_semi_open*(tr->ckr>>1)) +
+ (( data_rate/(tr->ckr*2) < pi_fmin) ? (1-tr->ca_semi_open) : 0));
+ tr->dq_ckdiv4_en = ( tr->dq_semi_open == 1) ? 0 :
+ ((( (data_rate/2) < 1200) ? 1 : 0) * (1-tr->dq_ca_open)) ;
+
+ ca_mckio = (data_rate/(tr->ckr*2))*(1+tr->ca_full_rate);
+ dq_pick = (tr->dq_semi_open == 1) ? 0 : (data_rate/2) ;
+ ca_pick = (tr->ca_semi_open == 1) ? ca_mckio*2 : ((ca_mckio>=pi_fmin) ?
+ ca_mckio : (( ca_mckio >= (pi_fmin/2)) ? ca_mckio*2 : ca_mckio *4));
+ tr->ca_ckdiv4_en = ((ca_pick < 1200) ? 1 : 0) * ( 1- tr->dq_ca_open) ;
+ tr->ca_prediv_en = (data_rate >= 4800) ? 1 : 0 ;
+
+ if (data_rate <= 1866)
+ tr->ph8_dly = 0;
+ else if (data_rate <= 2400)
+ tr->ph8_dly = 0x11;
+ else if (data_rate <= 3200)
+ tr->ph8_dly = 0xc;
+ else if (data_rate <= 3733)
+ tr->ph8_dly = 0x9;
+ else
+ tr->ph8_dly = 0x7;
+
+ tr->semi_open_ca_pick_mck_ratio = ( mckio_semi == 0) ?
+ 0 : (ca_pick*tr->dq_p2s_ratio)/data_rate ;
+ tr->dq_aamck_div = (tr->dq_semi_open == 0) ?
+ ((tr->dq_p2s_ratio/2)*(1-tr->dq_semi_open)) : 0;
+ tr->ca_admck_div = ca_pick/(data_rate/tr->dq_p2s_ratio);
+ tr->dq_track_ca_en = 0 ;
+ tr->pll_freq = ((dq_pick * 2 * (tr->dq_ckdiv4_en+1)) > (ca_pick * 2 *(tr->ca_ckdiv4_en + 1))) ?
+ (dq_pick*2*(tr->dq_ckdiv4_en+1)) : (ca_pick*2*(tr->ca_ckdiv4_en+1));
+
+ if (data_rate==2400)
+ tr->pll_freq = 2366;
+ else if (data_rate==1200)
+ tr->pll_freq = 2288;
+ else if (data_rate==3200 || data_rate==1600)
+ tr->pll_freq = 3068;
+ else if (data_rate==800)
+ tr->pll_freq = 3016;
+ else if (data_rate==400)
+ tr->pll_freq = 4000;
+}
+
+static void ana_init_sequence(ana_dvfs_core *dvfs_core, ana_top_config *a_cfg)
+{
+ ana_pll_sequence();
+ ana_midpi_sequence(dvfs_core);
+ ana_clock_switch(dvfs_core);
+ ana_dll_sequence(dvfs_core,a_cfg);
+}
+
+void ana_init(const struct ddr_cali *cali, dramc_subsys_config *subsys)
+{
+ dram_freq_grp freq_group = cali->freq_group;
+
+ dramc_subsys_pre_config(freq_group, subsys);
+ dramc_dbg("ANA_INIT\n");
+
+ SET32_BITFIELDS(&ch[0].phy_ao.ca_cmd2,
+ CA_CMD2_RG_TX_ARCMD_OE_DIS_CA, 1,
+ CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA, 0,
+ CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA, 0xff);
+ ana_clockoff_sequence();
+ ana_phy_config(freq_group, subsys);
+ ana_init_sequence(subsys->dvfs_core, subsys->a_cfg);
+ SET32_BITFIELDS(&ch[0].phy_ao.ca_cmd2,
+ CA_CMD2_RG_TX_ARCMD_OE_DIS_CA, 0,
+ CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA, 1,
+ CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA, 0xff);
+ single_end_dramc_post_config(subsys->lp4_init->lp4y_en);
+}
diff --git a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c
index 1d6b6c2..d32c268 100644
--- a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c
+++ b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c
@@ -3742,6 +3742,12 @@
static void dramc_setting(const struct ddr_cali *cali)
{
+ dramc_subsys_config subsys;
+ ana_top_config ana_top_p;
+ struct gating_config gat_config;
+ static ana_dvfs_core ana_dvfs;
+ static dram_config lp4_config;
+ dvfs_group_config dvfs_config;
dram_freq_grp freq_group = cali->freq_group;
dramc_set_broadcast(DRAMC_BROADCAST_ON);
@@ -3766,6 +3772,13 @@
return;
}
+ resetb_pull_dn();
+ subsys.a_cfg = &ana_top_p;
+ subsys.dvfs_core = &ana_dvfs;
+ subsys.lp4_init = &lp4_config;
+ subsys.dfs_gp = &dvfs_config;
+ subsys.gat_c = &gat_config;
+ ana_init(cali, &subsys);
update_initial_settings(cali);
dramc_set_broadcast(DRAMC_BROADCAST_OFF);
}
diff --git a/src/soc/mediatek/mt8192/dramc_subsys_config.c b/src/soc/mediatek/mt8192/dramc_subsys_config.c
new file mode 100644
index 0000000..146e073
--- /dev/null
+++ b/src/soc/mediatek/mt8192/dramc_subsys_config.c
@@ -0,0 +1,134 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/dramc_pi_api.h>
+#include <soc/dramc_register.h>
+
+static u8 get_dram_RL_WL_mr_field_config(dram_freq_grp freq_group)
+{
+ u8 mr2_rl_wl = 2;
+
+ switch(freq_group) {
+ case DDRFREQ_400:
+ case DDRFREQ_600:
+ case DDRFREQ_800:
+ mr2_rl_wl = 2;
+ break;
+ case DDRFREQ_933:
+ mr2_rl_wl = 3;
+ break;
+ case DDRFREQ_1200:
+ mr2_rl_wl = 4;
+ break;
+ case DDRFREQ_1600:
+ mr2_rl_wl = 5;
+ break;
+ case DDRFREQ_2133:
+ mr2_rl_wl = 7;
+ break;
+ default:
+ dramc_dbg("ERROR: Unexpected freq:0x%x\n", freq_group);
+ break;
+ }
+
+ return mr2_rl_wl;
+}
+
+void dram_configure(dram_freq_grp freq_group, dram_config *tr)
+{
+ tr->mr_wl = get_dram_RL_WL_mr_field_config(freq_group);
+ tr->dbi_wr = 0;
+ tr->dbi_rd = 0;
+ tr->lp4y_en = 0;
+ tr->work_fsp = (freq_group > DDRFREQ_1200) ? 1 : 0;
+}
+
+void dramc_subsys_pre_config(dram_freq_grp freq_group, dramc_subsys_config *subsys)
+{
+ ana_top_config *a_cfg = subsys->a_cfg;
+ dram_config *lp4_init = subsys->lp4_init;
+ dvfs_group_config *dfs_gp = subsys->dfs_gp;
+
+ subsys->freq_group = freq_group;
+ dfs_gp->ckr = 1;
+ dfs_gp->dqsien_mode = 1;
+ lp4_init->ex_row_en[RANK_0] = (get_row_width_from_emi(RANK_0) >= 18) ? 1 : 0;
+ lp4_init->ex_row_en[RANK_1] = (get_row_width_from_emi(RANK_1) >= 18) ? 1 : 0;
+ lp4_init->lp4y_en = 0;
+ a_cfg->new_8x_mode = 1;
+ a_cfg->aphy_comb_en = 1 ;
+ a_cfg->dll_idle_mode = 1;
+ a_cfg->rank_mode = 1;
+ a_cfg->dll_async_en = 0;
+
+ switch (freq_group) {
+ case DDRFREQ_400:
+ dfs_gp->data_rate = 800;
+ dfs_gp->dq_p2s_ratio = 4;
+ break;
+ case DDRFREQ_600:
+ dfs_gp->data_rate = 1200;
+ dfs_gp->dq_p2s_ratio = 8;
+ break;
+ case DDRFREQ_800:
+ dfs_gp->data_rate = 1600;
+ dfs_gp->dq_p2s_ratio = 8;
+ break;
+ case DDRFREQ_933:
+ dfs_gp->data_rate = 1866;
+ dfs_gp->dq_p2s_ratio = 8;
+ break;
+ case DDRFREQ_1200:
+ dfs_gp->data_rate = 2400;
+ dfs_gp->dq_p2s_ratio = 8;
+ break;
+ case DDRFREQ_1600:
+ dfs_gp->data_rate = 3200;
+ dfs_gp->dq_p2s_ratio = 8;
+ break;
+ case DDRFREQ_2133:
+ dfs_gp->data_rate = 4266;
+ dfs_gp->dq_p2s_ratio = 8;
+ break;
+ default:
+ die("Invalid DDR frequency group %u\n", freq_group);
+ return;
+ }
+
+ dram_configure(freq_group, lp4_init);
+
+ a_cfg->all_slave_en = (freq_group <= DDRFREQ_933) ? 1 : 0;
+ a_cfg->tx_odt_dis = (freq_group <= DDRFREQ_1200) ? 1 : 0 ;
+
+ ana_clk_div_config(subsys->dvfs_core, subsys->dfs_gp);
+}
+
+void single_end_dramc_post_config(u8 lp4y_en)
+{
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd13,
+ SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_SEL_CA, lp4y_en,
+ SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_EN_CA, lp4y_en);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq13,
+ SHU_B0_DQ13_RG_TX_ARDQSB_OE_TIE_SEL_B0, lp4y_en,
+ SHU_B0_DQ13_RG_TX_ARDQSB_OE_TIE_EN_B0, lp4y_en);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq13,
+ SHU_B1_DQ13_RG_TX_ARDQSB_OE_TIE_SEL_B1, lp4y_en,
+ SHU_B1_DQ13_RG_TX_ARDQSB_OE_TIE_EN_B1, lp4y_en);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd0,
+ SHU_CA_CMD0_R_LP4Y_WDN_MODE_CLK, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq0,
+ SHU_B0_DQ0_R_LP4Y_WDN_MODE_DQS0, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq0,
+ SHU_B1_DQ0_R_LP4Y_WDN_MODE_DQS1, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd7,
+ SHU_CA_CMD7_R_LP4Y_SDN_MODE_CLK, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq7,
+ SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0, lp4y_en);
+ SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq7,
+ SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1, lp4y_en);
+ SET32_BITFIELDS(&ch[0].phy_ao.ca_cmd7,
+ CA_CMD7_RG_TX_ARCLKB_PULL_DN_LP4Y, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq7,
+ B0_DQ7_RG_TX_ARDQS0B_PULL_DN_B0_LP4Y, 0);
+ SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq7,
+ B1_DQ7_RG_TX_ARDQS0B_PULL_DN_B1_LP4Y, 0);
+}
diff --git a/src/soc/mediatek/mt8192/emi.c b/src/soc/mediatek/mt8192/emi.c
index b587993..acd605f 100644
--- a/src/soc/mediatek/mt8192/emi.c
+++ b/src/soc/mediatek/mt8192/emi.c
@@ -320,6 +320,27 @@
return ma_type;
}
+u32 get_row_width_from_emi(u32 rank)
+{
+ u32 emi_cona;
+ u32 shift_row, shift_ext;
+ int row_width;
+
+ if (rank == 0) {
+ shift_row = 12;
+ shift_ext = 22;
+ } else if (rank == 1) {
+ shift_row = 14;
+ shift_ext = 23;
+ } else
+ return -1;
+
+ emi_cona = read32(&emi_reg->cona);
+ row_width = ((emi_cona >> shift_row) & 0x3) | ((emi_cona >> shift_ext) & 0x4);
+
+ return (row_width + 13);
+}
+
static void emi_sw_setting(void)
{
setbits32(&emi_mpu->mpu_ctrl_d[1], BIT(4));
--
To view, visit https://review.coreboot.org/c/coreboot/+/44727
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I53b30a2bbed5acb363f85f7cbc7f255fdbc52304
Gerrit-Change-Number: 44727
Gerrit-PatchSet: 1
Gerrit-Owner: CK HU <ck.hu(a)mediatek.com>
Gerrit-Reviewer: Duan huayang <huayang.duan(a)mediatek.com>
Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-MessageType: newchange
4 days, 23 hours
- 3
- 46