DaLao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40723 )
Change subject: mb/lenovo/t440p: update VBT
......................................................................
mb/lenovo/t440p: update VBT
Update T440p's VBT from to version 2179. Extracted from the
latest bios update file: T440p's bios image
https://download.lenovo.com/pccbbs/mobiles/gluj42us.iso
Test: boot t440p with both SeaBIOS and Tianocore payloads,
verify dp output and backlight control all works under both
Linux and Windows.
Signed-off-by: dalao <dalao(a)tutanota.com>
Change-Id: If8669b8de6fa0801e261138651b8b2cf50432a70
---
M src/mainboard/lenovo/t440p/data.vbt
1 file changed, 0 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/40723/1
diff --git a/src/mainboard/lenovo/t440p/data.vbt b/src/mainboard/lenovo/t440p/data.vbt
index 1b2cd87..79077cc 100644
--- a/src/mainboard/lenovo/t440p/data.vbt
+++ b/src/mainboard/lenovo/t440p/data.vbt
Binary files differ
--
To view, visit https://review.coreboot.org/c/coreboot/+/40723
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: If8669b8de6fa0801e261138651b8b2cf50432a70
Gerrit-Change-Number: 40723
Gerrit-PatchSet: 1
Gerrit-Owner: DaLao <dalao(a)tutanota.com>
Gerrit-MessageType: newchange
Bernardo Perez Priego has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37628 )
Change subject: soc/intel/common: Add romstage common stage file
......................................................................
soc/intel/common: Add romstage common stage file
This patch will ensures all intel soc is using common stage
files to make coreboot design flow align across all socs.
CPU, SA, PCH, MCH programming sequence might be different between
socs but the function call should route from same location across
all soc.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com>
Change-Id: I06d43ac29f5e87ce731a470e5e145adea07ece4c
---
M src/cpu/intel/car/romstage.c
A src/soc/intel/common/basecode/include/intelbasecode/romstage.h
A src/soc/intel/common/basecode/romstage/Makefile.inc
A src/soc/intel/common/basecode/romstage/romstage.c
4 files changed, 162 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/37628/1
diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c
index 1f8eb9a..55d3c9d 100644
--- a/src/cpu/intel/car/romstage.c
+++ b/src/cpu/intel/car/romstage.c
@@ -52,9 +52,6 @@
for (i = 0; i < num_guards; i++)
stack_base[i] = stack_guard;
- if (CONFIG(VBOOT_EARLY_EC_SYNC))
- vboot_sync_ec();
-
mainboard_romstage_entry();
/* Check the stack. */
@@ -64,9 +61,6 @@
printk(BIOS_DEBUG, "Smashed stack detected in romstage!\n");
}
- if (CONFIG(SMM_TSEG))
- smm_list_regions();
-
prepare_and_run_postcar(&early_mtrrs);
/* We do not return here. */
}
diff --git a/src/soc/intel/common/basecode/include/intelbasecode/romstage.h b/src/soc/intel/common/basecode/include/intelbasecode/romstage.h
new file mode 100644
index 0000000..0cebbbf
--- /dev/null
+++ b/src/soc/intel/common/basecode/include/intelbasecode/romstage.h
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOC_INTEL_COMMON_BASECODE_ROMSTAGE_H
+#define SOC_INTEL_COMMON_BASECODE_ROMSTAGE_H
+
+#include <stddef.h>
+#include <stdint.h>
+#include <fsp/soc_binding.h>
+
+struct romstage_ops {
+ void (*soc_early_init)(void);
+ void (*soc_init)(void);
+ void (*pch_early_init)(void);
+ void (*pch_init)(void);
+ void (*cpu_early_init)(void);
+ void (*cpu_init)(void);
+ bool (*is_s3wake)(void);
+ void (*soc_mem_init_params)(FSP_M_CONFIG *mupd);
+};
+
+/* SoC Override function */
+struct romstage_ops *soc_get_ops(void);
+
+#endif
diff --git a/src/soc/intel/common/basecode/romstage/Makefile.inc b/src/soc/intel/common/basecode/romstage/Makefile.inc
new file mode 100644
index 0000000..29763fb
--- /dev/null
+++ b/src/soc/intel/common/basecode/romstage/Makefile.inc
@@ -0,0 +1 @@
+romstage-y += romstage.c
diff --git a/src/soc/intel/common/basecode/romstage/romstage.c b/src/soc/intel/common/basecode/romstage/romstage.c
new file mode 100644
index 0000000..55c4ab5
--- /dev/null
+++ b/src/soc/intel/common/basecode/romstage/romstage.c
@@ -0,0 +1,124 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/early_variables.h>
+#include <romstage_common.h>
+#include <cpu/x86/pae.h>
+#include <intelbasecode/romstage.h>
+#include <intelblocks/systemagent.h>
+#include <soc/iomap.h>
+#include <soc/romstage.h>
+
+static const struct romstage_ops s_romstage_ops;
+
+__weak struct romstage_ops *soc_get_ops(void)
+{
+ return (struct romstage_ops *)&s_romstage_ops;
+}
+
+void romstage_early_init(void)
+{
+ struct romstage_ops *rs_ops = soc_get_ops();
+
+ rs_ops->soc_early_init();
+ rs_ops->pch_early_init();
+ rs_ops->cpu_early_init();
+}
+
+void romstage_init(void)
+{
+ struct romstage_ops *rs_ops = soc_get_ops();
+
+ rs_ops->soc_init();
+ rs_ops->pch_init();
+ rs_ops->cpu_init();
+}
+
+void romstage_cmn_soc_early_init(void)
+{
+ systemagent_early_init();
+ heci_init(HECI1_BASE_ADDRESS);
+}
+
+void romstage_cmn_soc_init(void)
+{
+}
+
+void romstage_cmn_pch_early_init(void)
+{
+}
+
+void romstage_cmn_cpu_early_init(void)
+{
+}
+
+void romstage_cmn_pch_init(void)
+{
+}
+
+void romstage_cmn_cpu_init(void)
+{
+}
+
+bool romstage_cmn_is_s3wake(void)
+{
+ struct chipset_power_state *ps = pmc_get_power_state();
+ return pmc_fill_power_state(ps) == ACPI_S3;
+}
+
+void romstage_cmn_soc_mem_init_param(FSP_M_CONFIG *m_cfg)
+{
+}
+
+static const struct romstage_ops s_romstage_ops = {
+ &romstage_cmn_soc_early_init,
+ &romstage_cmn_soc_init,
+ &romstage_cmn_pch_early_init,
+ &romstage_cmn_pch_init,
+ &romstage_cmn_cpu_early_init,
+ &romstage_cmn_cpu_init,
+ &romstage_cmn_is_s3wake,
+ &romstage_cmn_mb_mem_init_param,
+ &romstage_cmn_soc_mem_init_param
+};
+
+/*
+ Main romstage function
+*/
+asmlinkage void mainboard_romstage_entry(void)
+{
+ if (CONFIG(VBOOT_EARLY_EC_SYNC))
+ vboot_sync_ec(rs_ops->fill_power_state());
+
+ romstage_early_init();
+ romstage_init();
+ fsp_memory_init(rs_ops->is_s3wake());
+
+ if (CONFIG(SMM_TSEG))
+ smm_list_regions();
+}
+
+/*
+ Callback function for FSP memory initialization
+*/
+void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
+{
+ struct romstage_ops *rs_ops = soc_get_ops();
+
+ FSP_M_CONFIG *m_cfg;
+ rs_ops->soc_mem_init_params(m_cfg);
+ mainboard_memory_init_params(m_cfg);
+}
+
--
To view, visit https://review.coreboot.org/c/coreboot/+/37628
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I06d43ac29f5e87ce731a470e5e145adea07ece4c
Gerrit-Change-Number: 37628
Gerrit-PatchSet: 1
Gerrit-Owner: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com>
Gerrit-MessageType: newchange
Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38988 )
Change subject: mb/asus/p8z77-m: New board
......................................................................
mb/asus/p8z77-m: New board
Constructed out of a mix of autoport results, p8z77-m_pro, and
inteltool/superiotool dumps.
Does not yet boot. Submitting for eyeballs and help.
Change-Id: If756e791ddce747cb1706414be8e41e83f88922b
Signed-off-by: Keith Hui <buurin(a)gmail.com>
---
A src/mainboard/asus/p8z77-m/Kconfig
A src/mainboard/asus/p8z77-m/Kconfig.name
A src/mainboard/asus/p8z77-m/Makefile.inc
A src/mainboard/asus/p8z77-m/acpi/ec.asl
A src/mainboard/asus/p8z77-m/acpi/platform.asl
A src/mainboard/asus/p8z77-m/acpi/superio.asl
A src/mainboard/asus/p8z77-m/acpi_tables.c
A src/mainboard/asus/p8z77-m/cmos.default
A src/mainboard/asus/p8z77-m/cmos.layout
A src/mainboard/asus/p8z77-m/data.vbt
A src/mainboard/asus/p8z77-m/devicetree.cb
A src/mainboard/asus/p8z77-m/dsdt.asl
A src/mainboard/asus/p8z77-m/early_init.c
A src/mainboard/asus/p8z77-m/gma-mainboard.ads
A src/mainboard/asus/p8z77-m/gpio.c
A src/mainboard/asus/p8z77-m/hda_verb.c
A src/mainboard/asus/p8z77-m/mainboard.c
17 files changed, 969 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/38988/1
diff --git a/src/mainboard/asus/p8z77-m/Kconfig b/src/mainboard/asus/p8z77-m/Kconfig
new file mode 100644
index 0000000..260597d
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/Kconfig
@@ -0,0 +1,45 @@
+##
+## This file is part of the coreboot project.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+if BOARD_ASUS_P8Z77_M
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select BOARD_ROMSIZE_KB_8192
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select INTEL_INT15
+ select NORTHBRIDGE_INTEL_SANDYBRIDGE
+ select SERIRQ_CONTINUOUS_MODE
+ select SOUTHBRIDGE_INTEL_C216
+ select MAINBOARD_HAS_LPC_TPM
+ select MAINBOARD_HAS_TPM1
+ select HAVE_OPTION_TABLE
+ select HAVE_CMOS_DEFAULT
+ select MAINBOARD_HAS_LIBGFXINIT
+ select INTEL_GMA_HAVE_VBT
+ select SUPERIO_NUVOTON_NCT6779D
+
+config MAINBOARD_DIR
+ string
+ default "asus/p8z77-m"
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "P8Z77-M"
+
+config MAX_CPUS
+ int
+ default 8
+
+endif
diff --git a/src/mainboard/asus/p8z77-m/Kconfig.name b/src/mainboard/asus/p8z77-m/Kconfig.name
new file mode 100644
index 0000000..a797a5b
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/Kconfig.name
@@ -0,0 +1,15 @@
+##
+## This file is part of the coreboot project.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+config BOARD_ASUS_P8Z77_M
+ bool "P8Z77-M"
diff --git a/src/mainboard/asus/p8z77-m/Makefile.inc b/src/mainboard/asus/p8z77-m/Makefile.inc
new file mode 100644
index 0000000..a12efbb
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/Makefile.inc
@@ -0,0 +1,20 @@
+##
+## This file is part of the coreboot project.
+##
+## This program is free software: you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation, either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+bootblock-y += gpio.c
+romstage-y += gpio.c
+
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+bootblock-y += early_init.c
+romstage-y += early_init.c
diff --git a/src/mainboard/asus/p8z77-m/acpi/ec.asl b/src/mainboard/asus/p8z77-m/acpi/ec.asl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/acpi/ec.asl
diff --git a/src/mainboard/asus/p8z77-m/acpi/platform.asl b/src/mainboard/asus/p8z77-m/acpi/platform.asl
new file mode 100644
index 0000000..d2cad26
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/acpi/platform.asl
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* This file is part of the coreboot project. */
+
+Method(_WAK,1)
+{
+ Return(Package(){0,0})
+}
+
+Method(_PTS,1)
+{
+}
diff --git a/src/mainboard/asus/p8z77-m/acpi/superio.asl b/src/mainboard/asus/p8z77-m/acpi/superio.asl
new file mode 100644
index 0000000..f2b35ba
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/acpi/superio.asl
@@ -0,0 +1 @@
+#include <drivers/pc80/pc/ps2_controller.asl>
diff --git a/src/mainboard/asus/p8z77-m/acpi_tables.c b/src/mainboard/asus/p8z77-m/acpi_tables.c
new file mode 100644
index 0000000..9c22f19
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/acpi_tables.c
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Vlado Cibic <vladocb(a)protonmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/bd82x6x/nvs.h>
+
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+ /* critical temp that will shutdown the pc == 95C degrees */
+ gnvs->tcrt = 95;
+
+ /* temp to start throttling the cpu == 85C */
+ gnvs->tpsv = 85;
+}
diff --git a/src/mainboard/asus/p8z77-m/cmos.default b/src/mainboard/asus/p8z77-m/cmos.default
new file mode 100644
index 0000000..725ab98
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/cmos.default
@@ -0,0 +1,24 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2019 Vlado Cibic <vladocb(a)protonmail.com>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+boot_option=Fallback
+debug_level=Debug
+gfx_uma_size=224M
+nmi=Enable
+sata_mode=AHCI
+#usb3_xxxx options are only used with MRC blob, ignored else
+usb3_mode=Enable
+usb3_drv=Enable
+usb3_streams=Enable
diff --git a/src/mainboard/asus/p8z77-m/cmos.layout b/src/mainboard/asus/p8z77-m/cmos.layout
new file mode 100644
index 0000000..da29d1c
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/cmos.layout
@@ -0,0 +1,185 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2019 Vlado Cibic <vladocb(a)protonmail.com>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+# Status Register A
+# -----------------------------------------------------------------
+# Status Register B
+# -----------------------------------------------------------------
+# Status Register C
+#96 4 r 0 status_c_rsvd
+#100 1 r 0 uf_flag
+#101 1 r 0 af_flag
+#102 1 r 0 pf_flag
+#103 1 r 0 irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104 7 r 0 status_d_rsvd
+#111 1 r 0 valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112 8 r 0 diag_rsvd1
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+#120 264 r 0 unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 3 boot_option
+388 4 h 0 reboot_counter
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+#392 3 r 0 unused
+395 4 e 4 debug_level
+#399 1 r 0 unused
+#400 8 r 0 reserved for century byte
+
+# -----------------------------------------------------------------
+# coreboot config options: southbridge
+
+# Non Maskable Interrupt(NMI) support, which is an interrupt that may
+# occur on a RAM or unrecoverable error.
+408 1 e 1 nmi
+
+409 2 e 5 power_on_after_fail
+411 1 e 6 sata_mode
+
+# -----------------------------------------------------------------
+# coreboot config options: northbridge
+
+# gfx_uma_size
+# Quantity of shared video memory the IGP can use
+#
+416 5 e 7 gfx_uma_size
+
+# -----------------------------------------------------------------
+# coreboot config options: usb3
+
+# usb3_mode
+# Controls how the motherboard's USB3 ports act at boot time
+421 2 e 8 usb3_mode
+
+# usb3_drv
+# Load (or not) pre-OS xHCI USB3 bios driver
+#
+423 1 e 1 usb3_drv
+
+# usb3_streams
+# Streams can provide more speed (as they can use 64Kb packets),
+# but they might cause incompatibilities with some devices.
+#
+424 1 e 1 usb3_streams
+
+# -----------------------------------------------------------------
+# Sandy/Ivy Bridge MRC Scrambler Seed values
+# note: MUST NOT be covered by checksum!
+464 32 r 0 mrc_scrambler_seed
+496 32 r 0 mrc_scrambler_seed_s3
+528 16 r 0 mrc_scrambler_seed_chk
+
+# -----------------------------------------------------------------
+# coreboot config options: check sums
+544 16 h 0 check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+#ID value text
+
+# Generic on/off enum
+1 0 Disable
+1 1 Enable
+
+# boot_option
+3 0 Fallback
+3 1 Normal
+
+# debug_level
+4 0 Emergency
+4 1 Alert
+4 2 Critical
+4 3 Error
+4 4 Warning
+4 5 Notice
+4 6 Info
+4 7 Debug
+4 8 Spew
+
+# power_on_after_fail
+5 0 Disable
+5 1 Enable
+5 2 Keep
+
+# sata_mode
+6 0 AHCI
+6 1 Compatible
+
+# gfx_uma_size (Intel IGP Video RAM size)
+7 0 32M
+7 1 64M
+7 2 96M
+7 3 128M
+7 4 160M
+7 5 192M
+7 6 224M
+7 7 256M
+7 8 288M
+7 9 320M
+7 10 352M
+7 11 384M
+7 12 416M
+7 13 448M
+7 14 480M
+7 15 512M
+7 16 544M
+7 17 576M
+7 18 608M
+7 19 640M
+7 20 672M
+7 21 704M
+7 22 736M
+7 23 768M
+7 24 800M
+7 25 832M
+7 26 864M
+7 27 896M
+7 28 928M
+7 29 960M
+7 30 992M
+
+# usb3_mode
+# Disable = Use the port always as USB 2.0 for compatibility
+# Enable = Use the port always as USB 3.0 for speed
+# Auto = Initialize the port as USB 2.0, until the OS loads
+# xHCI USB 3.0 driver
+# SmartAuto = Same as Auto but, if the OS loads the xHCI USB 3.0 driver
+# and the computer is reset, keep the USB 3.0 mode.
+#
+8 0 Disable
+8 1 Enable
+8 2 Auto
+8 3 SmartAuto
+
+# -----------------------------------------------------------------
+# <startBit[must be byte-aligned]> <endBit[must be byte aligned]>
+# <bit where to start storing checksum[must be 16bits-aligned]>
+checksums
+
+checksum 392 431 544
diff --git a/src/mainboard/asus/p8z77-m/data.vbt b/src/mainboard/asus/p8z77-m/data.vbt
new file mode 100644
index 0000000..26ab42d
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/data.vbt
Binary files differ
diff --git a/src/mainboard/asus/p8z77-m/devicetree.cb b/src/mainboard/asus/p8z77-m/devicetree.cb
new file mode 100644
index 0000000..03a20b9
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/devicetree.cb
@@ -0,0 +1,108 @@
+##
+## This file is part of the coreboot project.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did
+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }"
+ register "gfx.ndid" = "3"
+ device cpu_cluster 0x0 on
+ chip cpu/intel/model_206ax
+ register "c1_acpower" = "1"
+ register "c1_battery" = "1"
+ register "c2_acpower" = "3"
+ register "c2_battery" = "3"
+ register "c3_acpower" = "5"
+ register "c3_battery" = "5"
+ device lapic 0x0 on end
+ device lapic 0xacac off end
+ end
+ end
+ device domain 0x0 on
+ subsystemid 0x1043 0x84ca inherit
+ device pci 00.0 on end # Host bridge
+ device pci 01.0 on end # PCIe Bridge for discrete graphics
+ device pci 02.0 on end # Internal graphics VGA controller
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+ register "c2_latency" = "0x0065"
+ register "gen1_dec" = "0x000c0291"
+ register "gen4_dec" = "0x00000000"
+ register "pcie_port_coalesce" = "1"
+ register "sata_interface_speed_support" = "0x3" # 0x3=SATAIII
+ register "sata_port_map" = "0x3f"
+ register "spi_lvscc" = "0x2005"
+ register "spi_uvscc" = "0x2005"
+ register "superspeed_capable_ports" = "0x0000000f"
+ register "xhci_overcurrent_mapping" = "0x00000c03"
+ register "xhci_switchable_ports" = "0x0000000f" # the 4 ports
+
+ device pci 14.0 on end # USB 3.0 Controller
+ device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT
+ device pci 19.0 off end # Intel Gigabit Ethernet
+ device pci 1a.0 on end # USB2 EHCI #2
+ device pci 1b.0 on end # High Definition Audio Audio controller
+ device pci 1c.0 on end # PCIe Port #1
+ device pci 1c.1 off end # PCIe Port #2
+ device pci 1c.2 off end # PCIe Port #3
+ device pci 1c.3 off end # PCIe Port #4
+ device pci 1c.4 off end # PCIe Port #5
+ device pci 1c.5 on end # PCIe Port #6
+ device pci 1c.6 on end # PCIe Port #7
+ device pci 1c.7 off end # PCIe Port #8
+ device pci 1d.0 on end # USB2 EHCI #1
+ device pci 1e.0 off end # PCI bridge
+ device pci 1f.0 on # LPC bridge PCI-LPC bridge
+ chip superio/nuvoton/nct6779d
+ device pnp 2e.1 off end # Parallel
+ device pnp 2e.2 on # UART A
+ io 0x60 = 0x3f8 # COM2 address
+ end
+ device pnp 2e.3 off end # UART B, IR
+ device pnp 2e.5 on # PS2 KBC
+ io 0x60 = 0x0060 # KBC1 base
+ io 0x62 = 0x0064 # KBC2 base
+ irq 0x70 = 1 # Keyboard IRQ
+ irq 0x72 = 12 # Mouse IRQ
+
+ # KBC 12Mhz/A20 speed/sw KBRST
+ drq 0xf0 = 0x82
+ end
+ device pnp 2e.6 off end # CIR
+ device pnp 2e.7 on end # GPIOs 6-8
+ device pnp 2e.8 off end # WDT1 GPIO 0-1
+ device pnp 2e.9 off end # GPIO 1-8
+ device pnp 2e.a on # ACPI
+ drq 0xe4 = 0x10 # Enable 3VSBS to power RAM on S3
+ drq 0xe7 = 0x10 # 0.5s S3 delay for compatibility
+ end
+ device pnp 2e.b off end # HWM, LED
+ device pnp 2e.d off end # WDT1
+ device pnp 2e.e off end # CIR wake-up
+ device pnp 2e.f on # GPIO PP/OD
+ drq 0xe6 = 0x7f # GP7 PP
+ end
+ device pnp 2e.14 on end # Port 80 UART
+ device pnp 2e.16 off end # Deep sleep
+ end
+ chip drivers/pc80/tpm
+ device pnp 4e.0 on end # TPM
+ end
+ end
+ device pci 1f.2 on end # SATA Controller 1
+ device pci 1f.3 on end # SMBus
+ device pci 1f.5 off end # SATA Controller 2
+ device pci 1f.6 off end # Thermal
+ end
+ end
+end
diff --git a/src/mainboard/asus/p8z77-m/dsdt.asl b/src/mainboard/asus/p8z77-m/dsdt.asl
new file mode 100644
index 0000000..62d44ea
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/dsdt.asl
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Vlado Cibic <vladocb(a)protonmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
+
+#include <arch/acpi.h>
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, /* DSDT revision: ACPI 2.0 and up */
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20141018 /* OEM revision */
+)
+{
+ #include "acpi/platform.asl"
+ #include "acpi/superio.asl"
+ #include <cpu/intel/common/acpi/cpu.asl>
+ #include <southbridge/intel/common/acpi/platform.asl>
+
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
+
+ Device (\_SB.PCI0)
+ {
+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
+ }
+}
diff --git a/src/mainboard/asus/p8z77-m/early_init.c b/src/mainboard/asus/p8z77-m/early_init.c
new file mode 100644
index 0000000..52c0e03
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/early_init.c
@@ -0,0 +1,197 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <bootblock_common.h>
+#include <device/pnp_ops.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <arch/io.h>
+#include <device/pnp.h>
+#include <stdint.h>
+
+#include <superio/nuvoton/common/nuvoton.h>
+#include <superio/nuvoton/nct6779d/nct6779d.h>
+
+#include <option.h>
+
+#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <northbridge/intel/sandybridge/raminit.h>
+#include <northbridge/intel/sandybridge/pei_data.h>
+
+#define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1)
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+ /* {enable, current, oc_pin} */
+ { 1, 2, 0 }, /* Port 0: USB3 front internal header, top */
+ { 1, 2, 0 }, /* Port 1: USB3 front internal header, bottom */
+ { 1, 2, 1 }, /* Port 2: USB3 rear, ETH top */
+ { 1, 2, 1 }, /* Port 3: USB3 rear, ETH bottom */
+ { 1, 2, 2 }, /* Port 4: USB2 rear, PS2 top */
+ { 1, 2, 2 }, /* Port 5: USB2 rear, PS2 bottom */
+ { 1, 2, 3 }, /* Port 6: USB2 internal header USB78, top */
+ { 1, 2, 3 }, /* Port 7: USB2 internal header USB78, bottom */
+ { 1, 2, 4 }, /* Port 8: USB2 internal header USB910, top */
+ { 1, 2, 4 }, /* Port 9: USB2 internal header USB910, bottom */
+ { 1, 2, 6 }, /* Port 10: USB2 internal header USB1112, top */
+ { 1, 2, 5 }, /* Port 11: USB2 internal header USB1112, bottom */
+ { 0, 2, 5 }, /* Port 12: Unused. Asus proprietary DEBUG_PORT ??? */
+ { 0, 2, 6 } /* Port 13: Unused. Asus proprietary DEBUG_PORT ??? */
+};
+
+/* Global config register values. */
+static const u8 register_values[] = {
+ /*
+ * Before accessing CR10, CR11, CR13 and CR14, CR26 [Bit4] must be set to logic 1.
+ * - NCT6779D datasheet, page 293
+ */
+ /* reg, value */
+ 0x26, (1 << 4),
+ 0x13, 0xff, /* IRQs 0-15 active low */
+ 0x14, 0xff,
+ 0x1b, 0x60,
+ 0x22, 0xdf, /* Power down UART B */
+ 0x2a, 0x48, /* UART A instead of GPIO8x */
+ 0x2c, 0x00, /* PECI */
+};
+
+void bootblock_mainboard_early_init(void)
+{
+ int max = ARRAY_SIZE(register_values);
+ int i;
+
+ nuvoton_pnp_enter_conf_state(SERIAL_DEV);
+
+ /* Set registers as specified in the register_values[] array. */
+ for (i = 0; i < max; i += 2)
+ pnp_write_config(SERIAL_DEV, register_values[i], register_values[i + 1]);
+
+ pnp_set_logical_device(SERIAL_DEV);
+ pnp_set_enable(SERIAL_DEV, 0);
+ pnp_set_iobase(SERIAL_DEV, PNP_IDX_IO0, CONFIG_TTYS0_BASE);
+ pnp_set_enable(SERIAL_DEV, 1);
+ nuvoton_pnp_exit_conf_state(SERIAL_DEV);
+}
+
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+{
+ read_spd(&spd[0], 0x50, id_only);
+ read_spd(&spd[1], 0x51, id_only);
+ read_spd(&spd[2], 0x52, id_only);
+ read_spd(&spd[3], 0x53, id_only);
+}
+
+int mainboard_should_reset_usb(int s3resume)
+{
+ return !s3resume;
+}
+
+void mainboard_fill_pei_data(struct pei_data *pei_data)
+{
+ /*
+ * USB3 mode:
+ * 0 = Disable: work always as USB 2.0(ehci)
+ * 1 = Enable: work always as USB 3.0(xhci)
+ * 2 = Auto: work as USB2.0(ehci) until OS loads USB3 xhci driver
+ * 3 = Smart Auto : same than Auto, but if OS loads USB3 driver
+ * and reboots, it will keep the USB3.0 speed
+ */
+ int usb3_mode = 1;
+ get_option(&usb3_mode, "usb3_mode");
+ usb3_mode &= 0x3; /* ensure it's 0/1/2/3 only */
+
+ /* Load USB3 pre-OS xHCI driver */
+ int usb3_drv = 1;
+ get_option(&usb3_drv, "usb3_drv");
+ usb3_drv &= 0x1; /* ensure it's 0/1 only */
+
+ /* Use USB3 xHCI streams */
+ int usb3_streams = 1;
+ get_option(&usb3_streams, "usb3_streams");
+ usb3_streams &= 0x1; /* ensure it's 0/1 only */
+
+ struct pei_data pd = {
+ .pei_version = PEI_VERSION,
+ .mchbar = (uintptr_t)DEFAULT_MCHBAR,
+ .dmibar = (uintptr_t)DEFAULT_DMIBAR,
+ .epbar = DEFAULT_EPBAR,
+ .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
+ .smbusbar = SMBUS_IO_BASE,
+ .wdbbar = 0x4000000,
+ .wdbsize = 0x1000,
+ .hpet_address = CONFIG_HPET_ADDRESS,
+ .rcba = (uintptr_t)DEFAULT_RCBABASE,
+ .pmbase = DEFAULT_PMBASE,
+ .gpiobase = DEFAULT_GPIOBASE,
+ .thermalbase = 0xfed08000,
+ .system_type = 1, /* 0=Mobile, 1=Desktop/Server */
+ .tseg_size = CONFIG_SMM_TSEG_SIZE,
+ .spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 }, /* SMBus mul 2 */
+ .ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
+ .ec_present = 0, /* Asus 2203 bios shows XUECA016, but no EC */
+ .gbe_enable = 0, /* Board uses no Intel GbE but a RTL8111F */
+ .dimm_channel0_disabled = 0, /* Both DIMM enabled */
+ .dimm_channel1_disabled = 0, /* Both DIMM enabled */
+ .max_ddr3_freq = 1600, /* 1333=Sandy; 1600=Ivy */
+ .usb_port_config = {
+ /* {enabled, oc_pin, cable len 0x0080=<8inches/20cm} */
+ { 1, 0, 0x0080 }, /* USB3 front internal header */
+ { 1, 0, 0x0080 }, /* USB3 front internal header */
+ { 1, 1, 0x0080 }, /* USB3 ETH top connector */
+ { 1, 1, 0x0080 }, /* USB3 ETH botton connector */
+ { 1, 2, 0x0080 }, /* USB2 PS2 top connector */
+ { 1, 2, 0x0080 }, /* USB2 PS2 botton connector */
+ { 1, 3, 0x0080 }, /* USB2 internal header (USB78) */
+ { 1, 3, 0x0080 }, /* USB2 internal header (USB78) */
+ { 1, 4, 0x0080 }, /* USB2 internal header (USB910) */
+ { 1, 4, 0x0080 }, /* USB2 internal header (USB910) */
+ { 1, 6, 0x0080 }, /* USB2 internal header (USB1112) */
+ { 1, 5, 0x0080 }, /* USB2 internal header (USB1112) */
+ { 0, 5, 0x0080 }, /* Unused. Asus DEBUG_PORT ??? */
+ { 0, 6, 0x0080 } /* Unused. Asus DEBUG_PORT ??? */
+ },
+ .usb3 = {
+ /* 0=Disable; 1=Enable (start at USB3 speed)
+ * 2=Auto (start as USB2 speed until OS loads)
+ * 3=Smart Auto (like Auto but keep speed on reboot)
+ */
+ usb3_mode,
+ /* 4 bit switch mask. 0=not switchable, 1=switchable
+ * Means once it's loaded the OS, it can swap ports
+ * from/to EHCI/xHCI. Z77 has four USB3 ports, so 0xf
+ */
+ 0xf,
+ usb3_drv, /* 1=Load xHCI pre-OS drv */
+ /* 0=Don't use xHCI streams for better compatibility
+ * 1=use xHCI streams for better speed
+ */
+ usb3_streams
+ },
+ /* ASUS P8Z77-M Pro manual says 1.35v DIMMs are supported */
+ .ddr3lv_support = 1,
+ /* PCIe 3.0 support. As we use Ivy Bridge, let's enable it,
+ * but might cause some system instability !
+ */
+ .pcie_init = 1,
+ /* Command Rate. 0=Auto; 1=1N; 2=2N.
+ * Leave it always at Auto for compatibility & stability
+ */
+ .nmode = 0,
+ /* DDR refresh rate. 0=Auto based on DRAM's temperature;
+ * 1=Normal rate for speed; 2=Double rate for stability
+ */
+ .ddr_refresh_rate_config = 0
+ };
+
+ /* copy the data to output PEI */
+ *pei_data = pd;
+}
diff --git a/src/mainboard/asus/p8z77-m/gma-mainboard.ads b/src/mainboard/asus/p8z77-m/gma-mainboard.ads
new file mode 100644
index 0000000..d7afe73
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/gma-mainboard.ads
@@ -0,0 +1,34 @@
+--
+-- This file is part of the coreboot project.
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ -- FIXME: check this
+ ports : constant Port_List :=
+ (DP1,
+ DP2,
+ DP3,
+ HDMI1,
+ HDMI2,
+ HDMI3,
+ Analog,
+ Internal);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/asus/p8z77-m/gpio.c b/src/mainboard/asus/p8z77-m/gpio.c
new file mode 100644
index 0000000..03e1507
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/gpio.c
@@ -0,0 +1,194 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio1 = GPIO_MODE_GPIO,
+ .gpio2 = GPIO_MODE_NATIVE,
+ .gpio3 = GPIO_MODE_NATIVE,
+ .gpio4 = GPIO_MODE_NATIVE,
+ .gpio5 = GPIO_MODE_NATIVE,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_NATIVE,
+ .gpio10 = GPIO_MODE_NATIVE,
+ .gpio11 = GPIO_MODE_NATIVE,
+ .gpio12 = GPIO_MODE_GPIO,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_NATIVE,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio16 = GPIO_MODE_GPIO,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_NATIVE,
+ .gpio19 = GPIO_MODE_NATIVE,
+ .gpio20 = GPIO_MODE_NATIVE,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_NATIVE,
+ .gpio23 = GPIO_MODE_NATIVE,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_NATIVE,
+ .gpio26 = GPIO_MODE_NATIVE,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_GPIO,
+ .gpio30 = GPIO_MODE_NATIVE,
+ .gpio31 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT,
+ .gpio1 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_OUTPUT,
+ .gpio12 = GPIO_DIR_OUTPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_OUTPUT,
+ .gpio16 = GPIO_DIR_INPUT,
+ .gpio17 = GPIO_DIR_INPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_OUTPUT,
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_OUTPUT,
+ .gpio29 = GPIO_DIR_OUTPUT,
+ .gpio31 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio8 = GPIO_LEVEL_HIGH,
+ .gpio12 = GPIO_LEVEL_LOW,
+ .gpio15 = GPIO_LEVEL_LOW,
+ .gpio24 = GPIO_LEVEL_LOW,
+ .gpio28 = GPIO_LEVEL_LOW,
+ .gpio29 = GPIO_LEVEL_HIGH,
+ .gpio31 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio1 = GPIO_INVERT,
+ .gpio13 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_GPIO,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_NATIVE,
+ .gpio36 = GPIO_MODE_NATIVE,
+ .gpio37 = GPIO_MODE_NATIVE,
+ .gpio38 = GPIO_MODE_NATIVE,
+ .gpio39 = GPIO_MODE_NATIVE,
+ .gpio40 = GPIO_MODE_NATIVE,
+ .gpio41 = GPIO_MODE_NATIVE,
+ .gpio42 = GPIO_MODE_NATIVE,
+ .gpio43 = GPIO_MODE_NATIVE,
+ .gpio44 = GPIO_MODE_NATIVE,
+ .gpio45 = GPIO_MODE_GPIO,
+ .gpio46 = GPIO_MODE_GPIO,
+ .gpio47 = GPIO_MODE_NATIVE,
+ .gpio48 = GPIO_MODE_NATIVE,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio50 = GPIO_MODE_NATIVE,
+ .gpio51 = GPIO_MODE_NATIVE,
+ .gpio52 = GPIO_MODE_NATIVE,
+ .gpio53 = GPIO_MODE_NATIVE,
+ .gpio54 = GPIO_MODE_NATIVE,
+ .gpio55 = GPIO_MODE_NATIVE,
+ .gpio56 = GPIO_MODE_NATIVE,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_NATIVE,
+ .gpio60 = GPIO_MODE_NATIVE,
+ .gpio61 = GPIO_MODE_NATIVE,
+ .gpio62 = GPIO_MODE_NATIVE,
+ .gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio32 = GPIO_DIR_OUTPUT,
+ .gpio33 = GPIO_DIR_OUTPUT,
+ .gpio34 = GPIO_DIR_INPUT,
+ .gpio45 = GPIO_DIR_INPUT,
+ .gpio46 = GPIO_DIR_INPUT,
+ .gpio49 = GPIO_DIR_INPUT,
+ .gpio57 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio32 = GPIO_LEVEL_HIGH,
+ .gpio33 = GPIO_LEVEL_HIGH,
+ .gpio57 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_NATIVE,
+ .gpio65 = GPIO_MODE_NATIVE,
+ .gpio66 = GPIO_MODE_NATIVE,
+ .gpio67 = GPIO_MODE_NATIVE,
+ .gpio68 = GPIO_MODE_GPIO,
+ .gpio69 = GPIO_MODE_GPIO,
+ .gpio70 = GPIO_MODE_NATIVE,
+ .gpio71 = GPIO_MODE_NATIVE,
+ .gpio72 = GPIO_MODE_GPIO,
+ .gpio73 = GPIO_MODE_NATIVE,
+ .gpio74 = GPIO_MODE_NATIVE,
+ .gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio68 = GPIO_DIR_INPUT,
+ .gpio69 = GPIO_DIR_INPUT,
+ .gpio72 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/asus/p8z77-m/hda_verb.c b/src/mainboard/asus/p8z77-m/hda_verb.c
new file mode 100644
index 0000000..f240025
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/hda_verb.c
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x10ec0887, /* Codec Vendor / Device ID: Realtek */
+ 0x104384a8, /* Subsystem ID */
+ 15, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(0, 0x104384a8),
+ AZALIA_PIN_CFG(0, 0x11, 0x90430130),
+ AZALIA_PIN_CFG(0, 0x12, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x14, 0x01014410),
+ AZALIA_PIN_CFG(0, 0x15, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x18, 0x01a19c50),
+ AZALIA_PIN_CFG(0, 0x19, 0x02a19c60),
+ AZALIA_PIN_CFG(0, 0x1a, 0x0181345f),
+ AZALIA_PIN_CFG(0, 0x1b, 0x02214c20),
+ AZALIA_PIN_CFG(0, 0x1c, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x1d, 0x4016c629),
+ AZALIA_PIN_CFG(0, 0x1e, 0x01446140),
+ AZALIA_PIN_CFG(0, 0x1f, 0x411111f0),
+
+ 0x80862806, /* Codec Vendor / Device ID: Intel */
+ 0x80860101, /* Subsystem ID */
+ 4, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(3, 0x80860101),
+ AZALIA_PIN_CFG(3, 0x05, 0x58560010),
+ AZALIA_PIN_CFG(3, 0x06, 0x58560020),
+ AZALIA_PIN_CFG(3, 0x07, 0x18560030),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/asus/p8z77-m/mainboard.c b/src/mainboard/asus/p8z77-m/mainboard.c
new file mode 100644
index 0000000..b97b648
--- /dev/null
+++ b/src/mainboard/asus/p8z77-m/mainboard.c
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* This file is part of the coreboot project. */
+
+#include <device/device.h>
+#include <drivers/intel/gma/int15.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+static void mainboard_enable(struct device *dev)
+{
+ /* FIXME: fix those values*/
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
+ GMA_INT15_PANEL_FIT_DEFAULT,
+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: If756e791ddce747cb1706414be8e41e83f88922b
Gerrit-Change-Number: 38988
Gerrit-PatchSet: 1
Gerrit-Owner: Keith Hui <buurin(a)gmail.com>
Gerrit-MessageType: newchange