Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37321 )
Change subject: cpu/x86/Kconfig: Enable LAPIC remap mitigation on likely affect NB
......................................................................
cpu/x86/Kconfig: Enable LAPIC remap mitigation on likely affect NB
Pre-sandy bridge hardware is likely affected by the sinkhole
vulnerability.
Change-Id: I52cb20e0edac62475597b31696f38d0ffc6080de
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/cpu/x86/Kconfig
1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/37321/1
diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig
index efb5fa9..335463d 100644
--- a/src/cpu/x86/Kconfig
+++ b/src/cpu/x86/Kconfig
@@ -139,9 +139,9 @@
config SMM_LAPIC_REMAP_MITIGATION
bool
- default y if NORTHBRIDGE_INTEL_I945
- default y if NORTHBRIDGE_INTEL_GM45
- default y if NORTHBRIDGE_INTEL_NEHALEM
+ default y if NORTHBRIDGE_INTEL_I945 || NORTHBRIDGE_INTEL_GM45 \
+ || NORTHBRIDGE_INTEL_X4X || NORTHBRIDGE_INTEL_PINEVIEW \
+ || NORTHBRIDGE_INTEL_E7505
default n
config SERIALIZED_SMM_INITIALIZATION
--
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Gerrit-Change-Id: I52cb20e0edac62475597b31696f38d0ffc6080de
Gerrit-Change-Number: 37321
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Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
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Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36674 )
Change subject: arch/x86: Add option to compress postcar stage
......................................................................
arch/x86: Add option to compress postcar stage
The LZ4 decompressor was already linked in romstage.
Change-Id: I89fdc6066027447bf72968c66e6f5eb5fbb630c7
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/Kconfig
M src/arch/x86/Makefile.inc
2 files changed, 19 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/36674/1
diff --git a/src/Kconfig b/src/Kconfig
index 0d56291..17bf545 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -158,6 +158,16 @@
that decompression might slow down booting if the boot flash
is connected through a slow link (i.e. SPI).
+config COMPRESS_POSTCAR
+ bool "Compress postcar with LZ4"
+ depends on POSTCAR_STAGE
+ # Default value set at the end of the file
+ help
+ Compress postcar with LZ4 to save flash space and speed up boot,
+ since the time for reading the image from SPI (and in the vboot
+ case verifying it) is usually much greater than the time spent
+ decompressing.
+
config COMPRESS_PRERAM_STAGES
bool "Compress romstage and verstage with LZ4"
depends on !ARCH_X86 && (HAVE_ROMSTAGE || HAVE_VERSTAGE)
@@ -1203,6 +1213,9 @@
config COMPRESS_RAMSTAGE
default y if !UNCOMPRESSED_RAMSTAGE
+config COMPRESS_POSTCAR
+ default y
+
config COMPRESS_PRERAM_STAGES
depends on !ARCH_X86
default y
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 447fd57..8c35176 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -278,11 +278,16 @@
$(objcbfs)/postcar.elf: $(objcbfs)/postcar.debug.rmod
cp $< $@
+CBFS_POSTCAR_COMPRESS_FLAG := none
+ifeq ($(CONFIG_COMPRESS_POSTCAR),y)
+CBFS_POSTCAR_COMPRESS_FLAG := lz4
+endif
+
# Add postcar to CBFS
cbfs-files-$(CONFIG_POSTCAR_STAGE) += $(CONFIG_CBFS_PREFIX)/postcar
$(CONFIG_CBFS_PREFIX)/postcar-file := $(objcbfs)/postcar.elf
$(CONFIG_CBFS_PREFIX)/postcar-type := stage
-$(CONFIG_CBFS_PREFIX)/postcar-compression := none
+$(CONFIG_CBFS_PREFIX)/postcar-compression := $(CBFS_POSTCAR_COMPRESS_FLAG)
###############################################################################
# ramstage
--
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Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
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Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37196 )
Change subject: [WIP]cpu/x86/cache: CLFLUSH programs to memory before running
......................................................................
[WIP]cpu/x86/cache: CLFLUSH programs to memory before running
When cbmem is initialized in romstage and postcar placed in
the stage cache + cbmem where it is run, the assumption is made
that this are all in UC memory such that calling invd in
postcar is ok.
For performance reasons (e.g. postcar decompression) it is desirable
to cache cbmem and the stage cache during romstage. Another reason
is that AGESA sets up MTRR during romstage to cache all dram, which
is currently worked around by using additional MTRR to make that UC.
TODO be nice to reviewers and spit some parts off.
UNTESTED
Change-Id: I7ff2a57aee620908b71829457ea0f5a0c410ec5b
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/arch/x86/postcar_loader.c
M src/cpu/x86/cache/Makefile.inc
M src/cpu/x86/cache/cache.c
M src/include/cpu/x86/cache.h
4 files changed, 68 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/37196/1
diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c
index b53cbf8..53ab4f9 100644
--- a/src/arch/x86/postcar_loader.c
+++ b/src/arch/x86/postcar_loader.c
@@ -208,6 +208,21 @@
MTRR_TYPE_WRBACK);
}
+/*
+ * POSTCAR will call invd so don't make assumptions on cbmem
+ * and external stage cache being UC.
+ */
+static void postcar_flush_cache(void)
+{
+ uintptr_t stage_cache_base;
+ size_t stage_cache_size;
+ prog_segment_loaded((uintptr_t)cbmem_top(), cbmem_overhead_size(), SEG_FINAL);
+ if (CONFIG(TSEG_STAGE_CACHE)) {
+ stage_cache_external_region((void **)&stage_cache_base, &stage_cache_size);
+ prog_segment_loaded(stage_cache_base, stage_cache_size, SEG_FINAL);
+ }
+}
+
void run_postcar_phase(struct postcar_frame *pcf)
{
struct prog prog =
@@ -222,8 +237,10 @@
parameters between S3 resume and normal boot. On the
platforms where the values are the same it's a nop. */
finalize_load(prog.arg, pcf->stack);
- } else
+ } else {
load_postcar_cbfs(&prog, pcf);
+ postcar_flush_cache();
+ }
/* As postcar exist, it's end of romstage here */
timestamp_add_now(TS_END_ROMSTAGE);
diff --git a/src/cpu/x86/cache/Makefile.inc b/src/cpu/x86/cache/Makefile.inc
index b33b9ee..759488e 100644
--- a/src/cpu/x86/cache/Makefile.inc
+++ b/src/cpu/x86/cache/Makefile.inc
@@ -1 +1,2 @@
+romstage-y += cache.c
ramstage-y += cache.c
diff --git a/src/cpu/x86/cache/cache.c b/src/cpu/x86/cache/cache.c
index 2313c4d..ac2c45b 100644
--- a/src/cpu/x86/cache/cache.c
+++ b/src/cpu/x86/cache/cache.c
@@ -11,8 +11,11 @@
* GNU General Public License for more details.
*/
+#include <cbmem.h>
+#include <program_loading.h>
#include <console/console.h>
#include <cpu/x86/cache.h>
+#include <arch/cpu.h>
void x86_enable_cache(void)
{
@@ -20,3 +23,47 @@
printk(BIOS_INFO, "Enabling cache\n");
enable_cache();
}
+
+int clflush_supported(void)
+{
+ return (cpuid_edx(1) >> 19) & 1;
+}
+
+static void clflush_region(uintptr_t start, size_t size)
+{
+ uintptr_t addr;
+ size_t cl_size = (cpuid_ebx(1) >> 8) & 0xff;
+ if (!clflush_supported())
+ return;
+ for (addr = (start / cl_size) * cl_size; addr < start + size; addr += cl_size)
+ clflush((void *)addr);
+}
+
+static int dram_ready;
+
+/*
+ * For each segment of a program loaded this function is called
+ * to invalidate caches for the addresses of the loaded segment
+ */
+void arch_segment_loaded(uintptr_t start, size_t size, int flags)
+{
+ /* INVD is only called in postcar stage so we only need
+ to make sure that our things hit dram during romstage. */
+ if (!ENV_ROMSTAGE)
+ return;
+ if (flags != SEG_FINAL)
+ return;
+ if (!dram_ready)
+ return;
+
+ if (!clflush_supported())
+ printk(BIOS_DEBUG, "Not flushing cache to ram, CLFLUSH not supported\n");
+ clflush_region(start, size);
+}
+
+static void set_dram_ready(int unused)
+{
+ dram_ready = 1;
+}
+
+ROMSTAGE_CBMEM_INIT_HOOK(set_dram_ready);
diff --git a/src/include/cpu/x86/cache.h b/src/include/cpu/x86/cache.h
index 713ca32..2d2727f 100644
--- a/src/include/cpu/x86/cache.h
+++ b/src/include/cpu/x86/cache.h
@@ -55,6 +55,8 @@
asm volatile ("clflush (%0)"::"r" (addr));
}
+int clflush_supported(void);
+
/* The following functions require the __always_inline due to AMD
* function STOP_CAR_AND_CPU that disables cache as
* RAM, the cache as RAM stack can no longer be used. Called
--
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Gerrit-Change-Number: 37196
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
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Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36613 )
Change subject: Kconfig: Allow x86 to compress pre-ram stages if not run XIP
......................................................................
Kconfig: Allow x86 to compress pre-ram stages if not run XIP
Change-Id: Iac24d243c4bd4cb8c1db14a8e9fc43f508c2cd5d
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/Kconfig
M src/arch/x86/Makefile.inc
2 files changed, 3 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/36613/1
diff --git a/src/Kconfig b/src/Kconfig
index 793927a..df86246 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -160,7 +160,7 @@
config COMPRESS_PRERAM_STAGES
bool "Compress romstage and verstage with LZ4"
- depends on !ARCH_X86 && (HAVE_ROMSTAGE || HAVE_VERSTAGE)
+ depends on HAVE_ROMSTAGE || HAVE_VERSTAGE
# Default value set at the end of the file
help
Compress romstage and (if it exists) verstage with LZ4 to save flash
@@ -1217,7 +1217,7 @@
default y if !UNCOMPRESSED_RAMSTAGE
config COMPRESS_PRERAM_STAGES
- depends on !ARCH_X86
+ depends on NO_XIP_EARLY_STAGES
default y
config INCLUDE_CONFIG_FILE
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 447fd57..db4f054 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -119,6 +119,7 @@
ifeq ($(CONFIG_C_ENVIRONMENT_BOOTBLOCK),y)
bootblock-y += bootblock_crt0.S
+bootblock-y += memmove.c
ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32),y)
$(eval $(call early_x86_stage,bootblock,elf32-i386))
--
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Gerrit-Change-Number: 36613
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Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
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Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37197 )
Change subject: drivers/amd/agesa/romstage: Only mark cbmem as UC if needed
......................................................................
drivers/amd/agesa/romstage: Only mark cbmem as UC if needed
Now cbmem is flushed to dram before calling postcar stage.
UNTESTED.
Change-Id: Iaa0d154e2c5b2052027d07ad26e31f3ff63ae9f3
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/drivers/amd/agesa/mtrr_fixme.c
1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/37197/1
diff --git a/src/drivers/amd/agesa/mtrr_fixme.c b/src/drivers/amd/agesa/mtrr_fixme.c
index bbb9eb0..9e63425 100644
--- a/src/drivers/amd/agesa/mtrr_fixme.c
+++ b/src/drivers/amd/agesa/mtrr_fixme.c
@@ -51,6 +51,10 @@
if (s3resume)
return;
+ /* We worry about cbmem hitting dram later */
+ if (clflush_supported())
+ return;
+
/* For normal path, INIT_POST has returned with all
* memory set WB cacheable. But we need CBMEM as UC
* to make CAR teardown with invalidation without
--
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