February 2025 - coreboot-gerrit

Change in ...coreboot[master]: SeaBIOS - unofficial patches: advanced_bootmenu and multiple_floppies
by mikeb mikeb (Code Review) June 12, 2025

June 12, 2025

Hello Mike Banon, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/32351 to review the following change. Change subject: SeaBIOS - unofficial patches: advanced_bootmenu and multiple_floppies ...................................................................... SeaBIOS - unofficial patches: advanced_bootmenu and multiple_floppies If you'd like to add the useful floppies to your coreboot (read about them at http://dangerousprototypes.com/docs/Lenovo_G505S_hacking#Useful_floppies ), or to use your USB numpad for choosing a SeaBIOS boot entry, then this change is for you! It contains two valuable patches together with a Makefile mod needed to automatically apply these patches to a cloned SeaBIOS before its' compilation. advanced_bootmenu: up to 35 entries (2 pages if >18), numpad support (console) https://mail.coreboot.org/hyperkitty/list/seabios@seabios.org/thread/CKWLNT… [PATCH v2] ramdisk: search for all available floppy images instead of one https://mail.coreboot.org/pipermail/seabios/2018-December/012670.html Patch descriptions are available at these links, and just in case here's a copy: advanced_bootmenu: up to 35 entries (2 pages if >18), numpad support (console) Add support for up to 35 boot menu entries (2 pages if >18). To solve the ">10" problem currently experienced by SeaBIOS users (there are no 11, 12, etc. keys on a keyboard - so impossible to choose the last menu entries if you got >10 entries because of multiple hard drives / secondary payloads / floppies) - the boot menu has been extended to the letter keys. NOTE: TPM menu has been moved from T to M letter: it is at the end of keyboard's 3rd row of letters and "Trusted" is adjective while "Module" is a noun; alternatively could press '-'. Also, add support for a numpad. Small USB numpad could be really convenient for choosing the boot entries at coreboot boards used as (maybe headless) servers. '/' char on numpad could be used to open the boot menu or to exit it. If there are >10 boot menu entries - the numpad console interface will be enabled: press one or two digit keys and then ENTER to confirm your choice, or remove a digit by pressing the '.Del' key. Also you could call TPM with '-' key at any moment, or boot with a single key press of your fullsize keyboard. [PATCH v2] ramdisk: search for all available floppy images instead of one All the floppy images available at CBFS will be found and listed in a boot menu, instead of the first found. Could be highly valuable if you are participating in a hobby OS development - would like to test multiple versions of your floppy at the same coreboot image, to reduce the amount of re-flashes and accelerate the development at bare metal - or simply you would like to access multiple floppies as a coreboot user. For example: KolibriOS (nice assembly OS with GUI and apps), FreeDOS, MichalOS, Snowdrop and memtest (coreboot's memtest version is buggy, e.g. external USB keyboard isn't working at some laptops; floppy is much better) Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: Idf4efba31091a8678b51c2f6541d440c5cc6d37d --- M payloads/external/SeaBIOS/Makefile A payloads/external/SeaBIOS/advanced_bootmenu.patch A payloads/external/SeaBIOS/multiple_floppies.patch 3 files changed, 551 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/32351/1 diff --git a/payloads/external/SeaBIOS/Makefile b/payloads/external/SeaBIOS/Makefile index e505c8c..ae58c8c 100644 --- a/payloads/external/SeaBIOS/Makefile +++ b/payloads/external/SeaBIOS/Makefile @@ -76,7 +76,18 @@ # echo "# CONFIG_SMBIOS is not set" >> seabios/.config $(MAKE) -C seabios olddefconfig OUT=out/ -build: config +patch: + if [ -d seabios ]; then \ + cd seabios; \ + if [ ! -f .patched ]; then \ + echo " PATCH SeaBIOS $(TAG-y)"; \ + patch -p1 < ./../advanced_bootmenu.patch; \ + patch -p1 < ./../multiple_floppies.patch; \ + touch .patched; \ + fi; \ + fi + +build: config patch echo " MAKE SeaBIOS $(TAG-y)" $(MAKE) -C seabios OUT=out/ diff --git a/payloads/external/SeaBIOS/advanced_bootmenu.patch b/payloads/external/SeaBIOS/advanced_bootmenu.patch new file mode 100644 index 0000000..c914588 --- /dev/null +++ b/payloads/external/SeaBIOS/advanced_bootmenu.patch @@ -0,0 +1,332 @@ +diff --git a/src/boot.c b/src/boot.c +index 9f82f3c..f94dd27 100644 +--- a/src/boot.c ++++ b/src/boot.c +@@ -463,6 +463,7 @@ get_keystroke(int msec) + * Boot menu and BCV execution + ****************************************************************/ + ++#define BOOTMENU_PAGE_SIZE 18 + #define DEFAULT_BOOTMENU_WAIT 2500 + + // Show IPL option menu. +@@ -478,59 +479,282 @@ interactive_bootmenu(void) + ; + + char *bootmsg = romfile_loadfile("etc/boot-menu-message", NULL); +- int menukey = romfile_loadint("etc/boot-menu-key", 1); +- printf("%s", bootmsg ?: "\nPress ESC for boot menu.\n\n"); ++ int menukey = romfile_loadint("etc/boot-menu-key", 1); // custom menukey ++ printf("%s", bootmsg ?: "\nPress ESC or \\ / slash for boot menu.\n\n"); + free(bootmsg); + + u32 menutime = romfile_loadint("etc/boot-menu-wait", DEFAULT_BOOTMENU_WAIT); + enable_bootsplash(); + int scan_code = get_keystroke(menutime); + disable_bootsplash(); +- if (scan_code != menukey) ++ if (scan_code != menukey && // custom menukey ++ scan_code != 1 && // ESC ++ scan_code != 43 && // '\' char on keyboard ++ scan_code != 53 && // '/' char on keyboard ++ scan_code != 98) { // '/' char on numpad ++ if (scan_code == -1) ++ printf("No key pressed.\n"); ++ else ++ printf("Not a menukey pressed.\n"); + return; ++ } + + while (get_keystroke(0) >= 0) + ; + +- printf("Select boot device:\n\n"); + wait_threads(); + +- // Show menu items ++ char keyboard_keys[35] = {'1','2','3','4','5','6','7','8','9','0', ++ 'q','w','e','r','t','y','u','i','o','p', ++ 'a','s','d','f','g','h','j','k','l', ++ 'z','x','c','v','b','n'}; /* m = TPM */ ++ int numpad_scancodes[10] = { 82, 79, 80, 81, 75, 76, 77, 71, 72, 73 }; ++ int numpi = 0; // Key index: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9. ++ int digits = 0; // Numerical length of a current choice number. ++ int decode = 0; // Decode the current choice number into a letter? ++ int entry_id = 0; ++ char desc[77]; ++ ++ printf("Select boot device"); ++ ++ // Show menu items after counting them and determining a number of pages. ++ // Only 35 boot menu items (36 if to count a TPM) are supported currently. ++ + int maxmenu = 0; + struct bootentry_s *pos; +- hlist_for_each_entry(pos, &BootList, node) { +- char desc[77]; ++ hlist_for_each_entry(pos, &BootList, node) + maxmenu++; +- printf("%d. %s\n", maxmenu ++ ++ if (maxmenu > 10) { ++ if (maxmenu > 35) ++ maxmenu = 35; ++ if (maxmenu > BOOTMENU_PAGE_SIZE) ++ printf(" - page 1 :"); ++ else ++ printf(": "); ++ printf(" // press ENTER after your numpad input"); ++ if (maxmenu > BOOTMENU_PAGE_SIZE) ++ printf(" - if any -\n " ++ " // - or to switch between the pages...\n"); ++ else ++ printf(" (if any)\n\n"); ++ } else { ++ printf(":\n\n"); ++ } ++ ++ hlist_for_each_entry(pos, &BootList, node) { ++ if (entry_id == BOOTMENU_PAGE_SIZE) // Show only the first page. ++ break; ++ printf("%c. %s\n", keyboard_keys[entry_id] + , strtcpy(desc, pos->description, ARRAY_SIZE(desc))); ++ entry_id++; + } ++ int tpm_cshm = 0; + if (tpm_can_show_menu()) { +- printf("\nt. TPM Configuration\n"); ++ tpm_cshm = 1; ++ printf("\nm-. TPM Configuration"); + } +- +- // Get key press. If the menu key is ESC, do not restart boot unless +- // 1.5 seconds have passed. Otherwise users (trained by years of +- // repeatedly hitting keys to enter the BIOS) will end up hitting ESC +- // multiple times and immediately booting the primary boot device. +- int esc_accepted_time = irqtimer_calc(menukey == 1 ? 1500 : 0); ++ printf("\n> "); ++ ++ // Do not restart boot on menukey press, unless DEFAULT_BOOTMENU_WAIT msecs ++ // have passed. Otherwise users (trained by years of repeatedly hitting keys ++ // to enter the BIOS) will end up hitting menukey multiple times and ++ // immediately booting the primary boot device. ++ int esc_accepted_time = irqtimer_calc(DEFAULT_BOOTMENU_WAIT); ++ int choice = 0, kb_choice = 0; ++ int page_num = 1; ++ int enter = 0; ++ int backspace = 0; ++ int tpm_show_menu = 0; + for (;;) { + scan_code = get_keystroke(1000); +- if (scan_code == 1 && !irqtimer_check(esc_accepted_time)) +- continue; +- if (tpm_can_show_menu() && scan_code == 20 /* t */) { ++ if (scan_code == menukey || // custom menukey ++ scan_code == 1 || // ESC ++ scan_code == 43 || // '\' char on keyboard ++ scan_code == 53 || // '/' char on keyboard ++ scan_code == 98) { // '/' char on numpad ++ if (!irqtimer_check(esc_accepted_time)) ++ continue; ++ if (digits == 2) // Remove the decoded "(*)" ++ printf(" \b\b\b"); ++ /* Remove the existing input before printing a message. */ ++ for (; digits > 0; digits--) ++ printf("\b \b"); ++ printf("Menukey pressed.\n"); ++ return; ++ } ++ kb_choice = 0; ++ /* 4 rows of keyboard_keys: 1 row with numbers, 3 rows with letters. ++ Use any of them to select a boot device (except the TPM 'm-' keys) */ ++ // 1st range: 1-9 and 0 (10) keys <==> 2-11 scan codes <==> 1-10 choice ++ if (scan_code >= 2 && scan_code <= 11) kb_choice = scan_code - 1; ++ // 2nd range: Q-P row of letters <==> 16-25 scan codes <==> 11-20 choice ++ if (scan_code >= 16 && scan_code <= 25) kb_choice = scan_code - 5; ++ // 3rd range: A-L row of letters <==> 30-38 scan codes <==> 21-29 choice ++ if (scan_code >= 30 && scan_code <= 38) kb_choice = scan_code - 9; ++ // 4th range: Z-N row of letters <==> 44-49 scan codes <==> 30-35 choice ++ if (scan_code >= 44 && scan_code <= 49) kb_choice = scan_code - 14; ++ // ENTER: (28) on keyboard, (96) on numpad. ++ if (scan_code == 28 || scan_code == 96) ++ enter = 1; ++ // BCKSPC: '<-'(14) and 'Delete'(111) on keyboard, '.Del'(83) on numpad. ++ if (scan_code == 14 || scan_code == 111 || scan_code == 83) ++ backspace = 1; ++ // TPM keys: 'm'(50) and '-'(12) chars on keyboard, '-'(74) on numpad. ++ if ((scan_code == 50 || scan_code == 12 || scan_code == 74) && tpm_cshm) ++ tpm_show_menu = 1; ++ ++ if (kb_choice != 0 || tpm_show_menu) { ++ if (kb_choice > maxmenu) { ++ if (!tpm_show_menu) ++ continue; ++ } else { ++ choice = kb_choice; ++ } ++ if (digits == 2) // Remove the decoded "(*)" ++ printf(" \b\b\b"); ++ /* Remove the existing input before printing a choice. */ ++ for (; digits > 0; digits--) ++ printf("\b \b"); ++ if (!tpm_show_menu) { ++ // Choice is any of the detected boot devices ==> lets boot! ++ break; ++ } ++ } else { ++ // Internal/USB Numpad console interface. ++ if (digits < 9) { ++ for (numpi = 0; numpi < 10; numpi++) { ++ if (scan_code == numpad_scancodes[numpi]) { ++ if (maxmenu <= 10) { // Console interface is not needed. ++ if ((numpi != 0 && numpi <= maxmenu) || ++ (numpi == 0 && 10 <= maxmenu)) { // 10(0) ++ choice = numpi; ++ enter = 1; // Fake ENTER to boot this entry now. ++ } else { // If no such an entry, don't try to boot. ++ break; ++ } ++ } else { ++ if (digits == 2) { ++ printf(" \b\b\b"); // Remove the decoded "(*)" ++ if (choice == 0) { ++ printf("\b\b \b\b"); // Remove "10". ++ digits = 0; ++ } ++ } ++ choice = 10 * choice + numpi; ++ } ++ if (choice > 0) { ++ printf("%d", numpi); // Print the entered digit. ++ digits++; ++ } else { ++ if (10 <= maxmenu) ++ printf("10(0)\b\b\b"); ++ else ++ printf("10(?)\b\b\b"); ++ digits = 2; ++ } ++ if (choice > 9 && digits == 2) // Decode into a letter. ++ decode = 1; ++ break; ++ } ++ } ++ } ++ if (backspace && digits > 0) { ++ backspace = 0; ++ choice = choice / 10; ++ if (digits == 2) { ++ printf(" \b\b\b"); // Remove the decoded "(*)" ++ // 0 turned into 10: one more Backspace is needed to remove. ++ if (choice == 0) { ++ printf("\b \b"); ++ digits--; ++ } ++ } ++ printf("\b \b"); // Remove the last entered digit. ++ digits--; ++ if (choice > 9 && digits == 2) // Decode into a letter. ++ decode = 1; ++ } ++ if (decode) { // Decode the current choice number into a letter. ++ decode = 0; ++ if (choice <= maxmenu) { ++ printf("(%c)", keyboard_keys[choice-1]); ++ } else { ++ if (tpm_cshm && choice == 36) ++ printf("(m)"); // For TPM. ++ else ++ printf("(?)"); // No matching letter found. ++ } ++ printf("\b\b\b"); // Move a cursor before the "(*)" ++ } ++ } ++ ++ if (enter) { ++ enter = 0; ++ if (choice == 0) { ++ if (digits == 2) { // for 0 that turned into 10 ++ if (10 <= maxmenu) ++ break; ++ else ++ continue; ++ } ++ // If there are two pages - switch between them. ++ if (maxmenu > BOOTMENU_PAGE_SIZE) { ++ entry_id = 0; ++ page_num = 3 - page_num; // 3 - 1 = 2; 3 - 2 = 1. ++ printf("\n\nSelect boot device - page %d :" ++ " // press ENTER after your numpad input" ++ " - if any -\n " ++ " // - or to switch between the pages...\n", ++ page_num); ++ hlist_for_each_entry(pos, &BootList, node) { ++ if ((page_num == 1 && entry_id == BOOTMENU_PAGE_SIZE) || ++ (page_num == 2 && entry_id == 35)) ++ break; ++ if (page_num == 1 || entry_id >= BOOTMENU_PAGE_SIZE) ++ printf("%c. %s\n", keyboard_keys[entry_id], ++ strtcpy(desc, pos->description, ARRAY_SIZE(desc))); ++ entry_id++; ++ } ++ if (tpm_cshm) ++ printf("\nm-. TPM Configuration"); ++ printf("\n> "); ++ } ++ } else { ++ if (choice > maxmenu) { ++ if (tpm_cshm && choice == 36) ++ tpm_show_menu = 1; ++ } else { ++ // Choice is any of the detected boot devices ==> lets boot! ++ break; ++ } ++ } ++ } ++ ++ if (tpm_show_menu) { ++ tpm_show_menu = 0; ++ choice = 0; ++ if (digits == 0) ++ printf("TPM key pressed."); ++ else ++ digits = 0; + printf("\n"); + tpm_menu(); ++ printf("> "); + } +- if (scan_code >= 1 && scan_code <= maxmenu+1) +- break; ++ } ++ ++ if (choice == 0) // 10(0) ++ choice = 10; ++ ++ if (digits == 0 && choice < 36) { ++ printf("%c", keyboard_keys[choice-1]); ++ if (choice > 9) // Decode into a number. ++ printf("(%d)", choice); + } + printf("\n"); +- if (scan_code == 0x01) +- // ESC +- return; + + // Find entry and make top priority. +- int choice = scan_code - 1; + hlist_for_each_entry(pos, &BootList, node) { + if (! --choice) + break; +diff --git a/src/config.h b/src/config.h +index 93c8dbc..f85cc14 100644 +--- a/src/config.h ++++ b/src/config.h +@@ -19,7 +19,7 @@ + // Space to reserve in high-memory for tables + #define BUILD_MAX_HIGHTABLE (256*1024) + // Largest supported externaly facing drive id +-#define BUILD_MAX_EXTDRIVE 16 ++#define BUILD_MAX_EXTDRIVE 36 + // Number of bytes the smbios may be and still live in the f-segment + #define BUILD_MAX_SMBIOS_FSEG 600 + // Maximum number of bytes the mptable may be and still be copied to f-segment diff --git a/payloads/external/SeaBIOS/multiple_floppies.patch b/payloads/external/SeaBIOS/multiple_floppies.patch new file mode 100644 index 0000000..5249394 --- /dev/null +++ b/payloads/external/SeaBIOS/multiple_floppies.patch @@ -0,0 +1,207 @@ +diff --git a/src/block.h b/src/block.h +index f64e880..aaa236f 100644 +--- a/src/block.h ++++ b/src/block.h +@@ -2,7 +2,7 @@ + #define __BLOCK_H + + #include "types.h" // u32 +- ++#include "romfile.h" // struct romfile_s + + /**************************************************************** + * Disk command request +@@ -48,6 +48,7 @@ struct drive_s { + struct drive_s { + u8 type; // Driver type (DTYPE_*) + u8 floppy_type; // Type of floppy (only for floppy drives). ++ struct romfile_s *floppy_file; // Floppy file (only for virtual floppies). + struct chs_s lchs; // Logical CHS + u64 sectors; // Total sectors count + u32 cntl_id; // Unique id for a given driver type. +diff --git a/src/boot.c b/src/boot.c +index 9f82f3c..79f1e7d 100644 +--- a/src/boot.c ++++ b/src/boot.c +@@ -584,7 +584,7 @@ bcv_prepboot(void) + break; + case IPL_TYPE_FLOPPY: + map_floppy_drive(pos->drive); +- add_bev(IPL_TYPE_FLOPPY, 0); ++ add_bev(IPL_TYPE_FLOPPY, (u32)pos->drive); + break; + case IPL_TYPE_HARDDISK: + map_hd_drive(pos->drive); +@@ -733,6 +733,12 @@ do_boot(int seq_nr) + static void + do_boot(int seq_nr) + { ++ ++ int ret; ++ void *pos; ++ struct romfile_s *file; ++ struct drive_s *drive; ++ + if (! CONFIG_BOOT) + panic("Boot support not compiled in.\n"); + +@@ -744,6 +750,16 @@ do_boot(int seq_nr) + switch (ie->type) { + case IPL_TYPE_FLOPPY: + printf("Booting from Floppy...\n"); ++ drive = (struct drive_s *)ie->vector; ++ file = drive->floppy_file; ++ // File is NULL if a floppy is physical. ++ if (file) { ++ // Copy virtual floppy image into ram. ++ pos = (void *)drive->cntl_id; ++ ret = file->copy(file, pos, file->size); ++ if (ret < 0) ++ break; ++ } + boot_disk(0x00, CheckFloppySig); + break; + case IPL_TYPE_HARDDISK: +diff --git a/src/hw/floppy.c b/src/hw/floppy.c +index 9e6647d..5b37c6c 100644 +--- a/src/hw/floppy.c ++++ b/src/hw/floppy.c +@@ -107,7 +107,7 @@ struct floppyinfo_s FloppyInfo[] VARFSEG = { + }; + + struct drive_s * +-init_floppy(int floppyid, int ftype) ++init_floppy(int floppyid, int ftype, struct romfile_s *ffile) + { + if (ftype <= 0 || ftype >= ARRAY_SIZE(FloppyInfo)) { + dprintf(1, "Bad floppy type %d\n", ftype); +@@ -124,6 +124,7 @@ init_floppy(int floppyid, int ftype) + drive->type = DTYPE_FLOPPY; + drive->blksize = DISK_SECTOR_SIZE; + drive->floppy_type = ftype; ++ drive->floppy_file = ffile; + drive->sectors = (u64)-1; + + memcpy(&drive->lchs, &FloppyInfo[ftype].chs +@@ -134,7 +135,7 @@ addFloppy(int floppyid, int ftype) + static void + addFloppy(int floppyid, int ftype) + { +- struct drive_s *drive = init_floppy(floppyid, ftype); ++ struct drive_s *drive = init_floppy(floppyid, ftype, 0); + if (!drive) + return; + char *desc = znprintf(MAXDESCSIZE, "Floppy [drive %c]", 'A' + floppyid); +diff --git a/src/hw/ramdisk.c b/src/hw/ramdisk.c +index b9e9baa..a679385 100644 +--- a/src/hw/ramdisk.c ++++ b/src/hw/ramdisk.c +@@ -23,40 +23,69 @@ ramdisk_setup(void) + if (!CONFIG_FLASH_FLOPPY) + return; + +- // Find image. +- struct romfile_s *file = romfile_findprefix("floppyimg/", NULL); +- if (!file) +- return; +- const char *filename = file->name; +- u32 size = file->size; +- dprintf(3, "Found floppy file %s of size %d\n", filename, size); +- int ftype = find_floppy_type(size); +- if (ftype < 0) { +- dprintf(3, "No floppy type found for ramdisk size\n"); ++ struct romfile_s *file = NULL; ++ char *filename, *desc; ++ u32 size, max_size = 0; ++ int ftype; ++ void *pos; ++ struct drive_s *drive; ++ ++ // Find the max floppy size ++ for (;;) { ++ // Find the next image. ++ file = romfile_findprefix("floppyimg/", file); ++ if (!file) ++ break; ++ filename = file->name; ++ size = file->size; ++ dprintf(3, "Found floppy file %s of size %d\n", filename, size); ++ // Check if this size is valid. ++ ftype = find_floppy_type(size); ++ if (ftype < 0) { ++ dprintf(3, "No floppy type found for ramdisk size\n"); ++ } else { ++ if (size > max_size) ++ max_size = size; ++ } ++ } ++ if (max_size == 0) { ++ dprintf(3, "No floppies found\n"); + return; + } + + // Allocate ram for image. +- void *pos = memalign_tmphigh(PAGE_SIZE, size); ++ pos = memalign_tmphigh(PAGE_SIZE, max_size); + if (!pos) { + warn_noalloc(); + return; + } +- e820_add((u32)pos, size, E820_RESERVED); ++ e820_add((u32)pos, max_size, E820_RESERVED); ++ dprintf(3, "Allocate %u bytes for a floppy\n", max_size); + +- // Copy image into ram. +- int ret = file->copy(file, pos, size); +- if (ret < 0) +- return; +- +- // Setup driver. +- struct drive_s *drive = init_floppy((u32)pos, ftype); +- if (!drive) +- return; +- drive->type = DTYPE_RAMDISK; +- dprintf(1, "Mapping floppy %s to addr %p\n", filename, pos); +- char *desc = znprintf(MAXDESCSIZE, "Ramdisk [%s]", &filename[10]); +- boot_add_floppy(drive, desc, bootprio_find_named_rom(filename, 0)); ++ // Setup the floppy drivers. ++ file = NULL; ++ for (;;) { ++ // Find the next image. ++ file = romfile_findprefix("floppyimg/", file); ++ if (!file) ++ return; ++ filename = file->name; ++ size = file->size; ++ dprintf(3, "Found floppy file %s of size %d\n", filename, size); ++ ftype = find_floppy_type(size); ++ if (ftype < 0) { ++ dprintf(3, "No floppy type found for ramdisk size\n"); ++ } else { ++ // Setup driver. ++ drive = init_floppy((u32)pos, ftype, file); ++ if (!drive) ++ return; ++ drive->type = DTYPE_RAMDISK; ++ dprintf(1, "Mapping floppy %s to addr %p\n", filename, pos); ++ desc = znprintf(MAXDESCSIZE, "Ramdisk [%s]", &filename[10]); ++ boot_add_floppy(drive, desc, bootprio_find_named_rom(filename, 0)); ++ } ++ } + } + + static int +diff --git a/src/util.h b/src/util.h +index 9c06850..ce3a26d 100644 +--- a/src/util.h ++++ b/src/util.h +@@ -147,7 +147,8 @@ void dma_setup(void); + // hw/floppy.c + extern struct floppy_ext_dbt_s diskette_param_table2; + void floppy_setup(void); +-struct drive_s *init_floppy(int floppyid, int ftype); ++extern struct romfile_s *ffile; ++struct drive_s *init_floppy(int floppyid, int ftype, struct romfile_s *ffile); + int find_floppy_type(u32 size); + int floppy_process_op(struct disk_op_s *op); + void floppy_tick(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/32351 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf4efba31091a8678b51c2f6541d440c5cc6d37d Gerrit-Change-Number: 32351 Gerrit-PatchSet: 1 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: pci: Add support for assigning resources to SR-IOV VF BARs
by Name of user not set (Code Review) May 28, 2025

May 28, 2025

stephend(a)silicom-usa.com has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34620 ) Change subject: pci: Add support for assigning resources to SR-IOV VF BARs ...................................................................... pci: Add support for assigning resources to SR-IOV VF BARs This ensures that bridge windows allocate enough space to cover SR-IOV BARs. Without this Linux will print messages like: pci 0000:03:00.0: BAR 7: no space for [mem size 0x00100000 64bit] pci 0000:03:00.0: BAR 7: failed to assign [mem size 0x00100000 64bit] Tested on Camelback Mountain, and Harcuvar. Change-Id: Ib169efe5a6b998a8342a895f1456a280669c719d Signed-off-by: Stephen Douthit <stephend(a)silicom-usa.com> --- M src/device/pci_device.c M src/device/pciexp_device.c M src/include/device/pci_def.h M src/include/device/pciexp.h 4 files changed, 112 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/34620/1 diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 7786043..c96fc8d 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -439,6 +439,11 @@ { pci_read_bases(dev, 6); pci_get_rom_resource(dev, PCI_ROM_ADDRESS); + +#if CONFIG(PCIEXP_PLUGIN_SUPPORT) + /* Check for SR-IOV BARs if we have PCIe support */ + pciexp_dev_read_resources(dev); +#endif } void pci_bus_read_resources(struct device *dev) diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index c209816..8d660b1 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -442,6 +442,82 @@ pciexp_enable_aspm(root, root_cap, dev, cap); } +/* + * Check if this is an SR-IOV capable device and add resources for all VF bars + * + * @param dev Pointer to the dev structure. + */ +void pciexp_dev_read_resources(struct device *dev) +{ + unsigned long sriovpos; + u16 numvfs, i; + + sriovpos = pci_find_capability(dev, PCI_CAP_ID_PCIE); + if (!sriovpos) { + return; + } + + sriovpos = pciexp_find_extended_cap(dev, PCI_EXT_CAP_ID_SRIOV); + if (!sriovpos) { + return; + } + + numvfs = pci_read_config16(dev, sriovpos + PCI_SRIOV_TOT_VFS); + printk(BIOS_DEBUG, "%s: supports %d SR-IOV VFs\n", dev_path(dev), numvfs); + + /* The spec allows this to be 0 for some reason. Nothing to do. */ + if (numvfs == 0) { + return; + } + + for (int off = 0; off < 6; off++) { + unsigned long res_ix = sriovpos + PCI_SRIOV_VFBAR0 + off * 4; + struct resource *resource; + + resource = pci_get_resource(dev, res_ix); + + /* VF BARs aren't necessarily contiguous, skip the unused ones */ + if (resource->size == 0) { + continue; + } + + printk(BIOS_DEBUG, "%s: found %dbit SR-IOV BAR, size 0x%llx @ index %lx\n", + dev_path(dev), (resource->flags & IORESOURCE_PCI64) ? 64 : 32, + resource->size, resource->index); + + if (resource->flags & IORESOURCE_PCI64) { + off++; + } + + /* + * SR-IOV BARs break the resource allocator assumption for PCI + * dev resources that size = gran = alignment. + * + * alignment = gran = pci_get_resource() result, but... + * size is pci_get_resource()->size * numvfs, and there's no + * power of two guarantee on size either since numvfs is just + * an integer. + * + * Rather than add code to handle this as a special case in the + * resource allocator, just round up the size. In practice + * MaxVfs tends to be 2^n or 2^n - 1, so the holes produced + * should only be the size of a single VF BAR + */ + for (i = 1; i < numvfs; i <<= 1) { + resource->size <<= 1; + resource->align += 1; + resource->gran += 1; + } + + if (i != numvfs) { + printk(BIOS_DEBUG, "%s: VFs != 2^n, wasting MMIO space...\n", + dev_path(dev)); + } + } + + compact_resources(dev); +} + void pciexp_scan_bus(struct bus *bus, unsigned int min_devfn, unsigned int max_devfn) { diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index bc5bc79..39a6137 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -453,6 +453,7 @@ #define PCI_EXT_CAP_ID_VC 2 #define PCI_EXT_CAP_ID_DSN 3 #define PCI_EXT_CAP_ID_PWR 4 +#define PCI_EXT_CAP_ID_SRIOV 0x0010 /* Extended Capability lists*/ #define PCIE_EXT_CAP_OFFSET 0x100 @@ -518,6 +519,34 @@ #define PCI_PWR_CAP 12 /* Capability */ #define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */ +/* SR-IOV */ +#define PCI_SRIOV_CAPS 0x04 /* SR-IOV capabilities */ +#define PCI_SRIOV_VF_MIG (1 << 0) /* VF Migration capable */ +#define PCI_SRIOV_ARI_CAP (1 << 1) /* ARI Capable Hierarchy Preserved */ +#define PCI_SRIOV_MIG_INT(x) (((x) >> 21) & 0x7ff) +#define PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */ +#define PCI_SRIOV_VF_EN (1 << 0) +#define PCI_SRIOV_MIG_EN (1 << 1) +#define PCI_SRIOV_MIG_INT_EN (1 << 2) +#define PCI_SRIOV_MSE (1 << 3) +#define PCI_SRIOV_ARI_CAP_EN (1 << 4) +#define PCI_SRIOV_STATUS 0x0A /* SR-IOV Status */ +#define PCI_SRIOV_INIT_VFS 0x0C +#define PCI_SRIOV_TOT_VFS 0x0E +#define PCI_SRIOV_NUM_VFS 0x10 +#define PCI_SRIOV_FN_DEP_LINK 0x12 +#define PCI_SRIOV_VF_OFF 0x14 +#define PCI_SRIOV_VF_STRIDE 0x16 +#define PCI_SRIOV_VF_DEVID 0x1A +#define PCI_SRIOV_SUP_PAGE_SIZE 0x1C +#define PCI_SRIOV_PAGE_SIZE 0x20 +#define PCI_SRIOV_VFBAR0 0x24 +#define PCI_SRIOV_VFBAR1 0x28 +#define PCI_SRIOV_VFBAR2 0x2C +#define PCI_SRIOV_VFBAR3 0x30 +#define PCI_SRIOV_VFBAR4 0x34 +#define PCI_SRIOV_VFBAR5 0x38 +#define PCI_SRIOV_MIG_ARRAY 0x3C /* * The PCI interface treats multi-function devices as independent diff --git a/src/include/device/pciexp.h b/src/include/device/pciexp.h index 3a9825d..94a80bf 100644 --- a/src/include/device/pciexp.h +++ b/src/include/device/pciexp.h @@ -19,6 +19,8 @@ /* Latency tolerance reporting, max snoop latency value 3.14ms */ #define PCIE_LTR_MAX_SNOOP_LATENCY_3146US 0x1003 +void pciexp_dev_read_resources(struct device *dev); + void pciexp_scan_bus(struct bus *bus, unsigned int min_devfn, unsigned int max_devfn); -- To view, visit https://review.coreboot.org/c/coreboot/+/34620 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib169efe5a6b998a8342a895f1456a280669c719d Gerrit-Change-Number: 34620 Gerrit-PatchSet: 1 Gerrit-Owner: stephend(a)silicom-usa.com Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: soc/intel/cmn/block/smbus: Keep TCO WDT timeout flag if ACPI_WDAT_WDT=y
by Matt DeVillier (Code Review) Feb. 28, 2025

Feb. 28, 2025

Attention is currently required from: Filip Brozovic, Intel coreboot Reviewers, Paul Menzel. Matt DeVillier has posted comments on this change by Filip Brozovic. ( https://review.coreboot.org/c/coreboot/+/84875?usp=email ) Change subject: soc/intel/cmn/block/smbus: Keep TCO WDT timeout flag if ACPI_WDAT_WDT=y ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/84875?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2d35a8f8bcbcc3aaaadcc936fab028641dfd6e2c Gerrit-Change-Number: 84875 Gerrit-PatchSet: 4 Gerrit-Owner: Filip Brozovic <fbrozovic(a)gmail.com> Gerrit-Reviewer: Filip Brozovic <fbrozovic(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Filip Brozovic <fbrozovic(a)gmail.com> Gerrit-Comment-Date: Fri, 28 Feb 2025 22:49:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/intel/cmn/acpi: exclude TPM area range if CRB TPM driver is enabled
by Filip Brozovic (Code Review) Feb. 28, 2025

Feb. 28, 2025

Filip Brozovic has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/84874?usp=email ) Change subject: soc/intel/cmn/acpi: exclude TPM area range if CRB TPM driver is enabled ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/84874?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I16f173ebacbd00b5fea26d2136c9c56ba025f55c Gerrit-Change-Number: 84874 Gerrit-PatchSet: 2 Gerrit-Owner: Filip Brozovic <fbrozovic(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: [WIP] soc/amd/glinda/Kconfig: Remove TODOs
by Maximilian Brune (Code Review) Feb. 28, 2025

Feb. 28, 2025

Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86672?usp=email ) Change subject: [WIP] soc/amd/glinda/Kconfig: Remove TODOs ...................................................................... [WIP] soc/amd/glinda/Kconfig: Remove TODOs Remove TODOs after verifying they still all apply. Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: I44bb058a2f3a41bf440261dd840b506829b70fc1 --- M src/soc/amd/glinda/Kconfig 1 file changed, 14 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/86672/1 diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig index 70bdb69..9f64ee7 100644 --- a/src/soc/amd/glinda/Kconfig +++ b/src/soc/amd/glinda/Kconfig @@ -29,7 +29,7 @@ select RTC select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK_ACP_GEN2 # TODO: Check if this is still correct - select SOC_AMD_COMMON_BLOCK_ACPI # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_ACPI select SOC_AMD_COMMON_BLOCK_ACPIMMIO # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_ACPI_ALIB # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_ACPI_CPPC # TODO: Check if this is still correct @@ -37,9 +37,9 @@ select SOC_AMD_COMMON_BLOCK_ACPI_GPIO # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_ACPI_IVRS # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_ACPI_MADT - select SOC_AMD_COMMON_BLOCK_AOAC # TODO: Check if this is still correct - select SOC_AMD_COMMON_BLOCK_APOB # TODO: Check if this is still correct - select SOC_AMD_COMMON_BLOCK_APOB_HASH # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_AOAC + select SOC_AMD_COMMON_BLOCK_APOB + select SOC_AMD_COMMON_BLOCK_APOB_HASH select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH select SOC_AMD_COMMON_BLOCK_DATA_FABRIC @@ -51,29 +51,29 @@ select SOC_AMD_COMMON_BLOCK_GRAPHICS_NO_VGA select SOC_AMD_COMMON_BLOCK_HAS_ESPI # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_HAS_ESPI_ALERT_ENABLE # TODO: Check if this is still correct - select SOC_AMD_COMMON_BLOCK_I2C # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_I2C select SOC_AMD_COMMON_BLOCK_I23C_PAD_CTRL # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_IOMMU # TODO: Check if this is still correct - select SOC_AMD_COMMON_BLOCK_LPC # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_LPC select SOC_AMD_COMMON_BLOCK_MCAX # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_NONCAR # TODO: Check if this is still correct - select SOC_AMD_COMMON_BLOCK_PCI # TODO: Check if this is still correct - select SOC_AMD_COMMON_BLOCK_PCI_MMCONF # TODO: Check if this is still correct - select SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_PCI + select SOC_AMD_COMMON_BLOCK_PCI_MMCONF + select SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER select SOC_AMD_COMMON_BLOCK_PM # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_PSP_GEN2 # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_PSP_SPL select SOC_AMD_COMMON_BLOCK_RESET select SOC_AMD_COMMON_BLOCK_SMBUS # TODO: Check if this is still correct - select SOC_AMD_COMMON_BLOCK_SMI # TODO: Check if this is still correct - select SOC_AMD_COMMON_BLOCK_SMM # TODO: Check if this is still correct - select SOC_AMD_COMMON_BLOCK_SMU # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_SMI + select SOC_AMD_COMMON_BLOCK_SMM + select SOC_AMD_COMMON_BLOCK_SMU select SOC_AMD_COMMON_BLOCK_SMU_SX_ENTRY # TODO: Check if this is still correct - select SOC_AMD_COMMON_BLOCK_SPI # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_SPI select SOC_AMD_COMMON_BLOCK_SVI3 select SOC_AMD_COMMON_BLOCK_TSC - select SOC_AMD_COMMON_BLOCK_UART # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_UART select SOC_AMD_COMMON_BLOCK_UCODE # TODO: Check if this is still correct select SOC_AMD_COMMON_FSP_CCX_CPPC_HOB # TODO: Check if this is still correct select SOC_AMD_COMMON_FSP_DMI_TABLES # TODO: Check if this is still correct -- To view, visit https://review.coreboot.org/c/coreboot/+/86672?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I44bb058a2f3a41bf440261dd840b506829b70fc1 Gerrit-Change-Number: 86672 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com>

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[M] Change in coreboot[main]: soc/amd/cezanne/acpi: Add ACP MSG0 method
by Matt DeVillier (Code Review) Feb. 28, 2025

Feb. 28, 2025

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier. Matt DeVillier has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/86466?usp=email ) Change subject: soc/amd/cezanne/acpi: Add ACP MSG0 method ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86466?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I34f641fbfe40b5df7f0ff2fc173510c5cf2a7f61 Gerrit-Change-Number: 86466 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 28 Feb 2025 21:00:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: soc/amd/cezanne/acpi: Add ACP MSG0 method
by Felix Held (Code Review) Feb. 28, 2025

Feb. 28, 2025

Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier, Matt DeVillier. Felix Held has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/86466?usp=email ) Change subject: soc/amd/cezanne/acpi: Add ACP MSG0 method ...................................................................... Patch Set 4: (1 comment) Patchset: PS1: > not tested yet tested and works as expected -- To view, visit https://review.coreboot.org/c/coreboot/+/86466?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I34f641fbfe40b5df7f0ff2fc173510c5cf2a7f61 Gerrit-Change-Number: 86466 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Fri, 28 Feb 2025 20:57:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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[S] Change in coreboot[main]: soc/amd/cezanne: Add ACPI opregion to root complex
by Felix Held (Code Review) Feb. 28, 2025

Feb. 28, 2025

Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier, Matt DeVillier. Felix Held has posted comments on this change by Matt DeVillier. ( https://review.coreboot.org/c/coreboot/+/77682?usp=email ) Change subject: soc/amd/cezanne: Add ACPI opregion to root complex ...................................................................... Patch Set 6: (1 comment) File src/soc/amd/cezanne/root_complex.c: https://review.coreboot.org/c/coreboot/+/77682/comment/73224e35_50d711a1?us… : PS6, Line 63: Add ACPI device, opregion to host bridge needed for Windows ACP driver. : * : * This provides a mailbox interface for the ACP drivers to notify the PSP : * that the DSP firmware has been loaded, so that the PSP can validate : * the firmware and set the qualifier bit to enable running it. > is this comment still valid? or should we make it more generic? that should probably be reworked a bit. also i'll have to see if CB:86652 should be squashed into it, but still waiting on some test results on that one. i'll try to do the development in upstream, but the testing is done on some out of tree mainboard and right now i need to move there fast, so haven't gotten around to improve the comments and possibly commit messages -- To view, visit https://review.coreboot.org/c/coreboot/+/77682?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4d00c86647e51e5cae621fe788f0a1b06471a443 Gerrit-Change-Number: 77682 Gerrit-PatchSet: 6 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Fri, 28 Feb 2025 20:56:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com>

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[S] Change in coreboot[main]: Documentation/lib/rmodules.md: Update simple binary explanation
by Maximilian Brune (Code Review) Feb. 28, 2025

Feb. 28, 2025

Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86656?usp=email ) Change subject: Documentation/lib/rmodules.md: Update simple binary explanation ...................................................................... Documentation/lib/rmodules.md: Update simple binary explanation Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: I9cf21b4258758b18f0d3c9316c9aa32cc0d9c44f --- M Documentation/lib/rmodules.md 1 file changed, 18 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/86656/1 diff --git a/Documentation/lib/rmodules.md b/Documentation/lib/rmodules.md index 8a707b8..3ac25a7 100644 --- a/Documentation/lib/rmodules.md +++ b/Documentation/lib/rmodules.md @@ -35,8 +35,24 @@ 1. coreboot stages (postcar, ramstage) 2. simple binaries (smm, smmstub, sipi\_vector) -They are actually handled the same by the build system and only differ -in the fact, that they are either coreboot stages or they are not. +They are handled differently in a 1 important fact. The simple binaries +are compiled into rmodules the same as coreboot stages are, but the +simple bianries are always directly linked to a stage. +Since rmodules are ELF files as well, we can easily link them to the +stages in which we need them (usually postcar or ramstage). +So they are not so much as seperate modules anymore, but still retain +the abillity to accept rmodule\_parameters. +Since the simple binaries are usually very small, linking them directly +into the stage (e.g. ramstage or postcar) avoids having to fetch them +from CBFS and running all that code to fetch a few hundred bytes of +code. So the build system handles them as follows: +1. create rmodule (which is an ELF file) from source files +2. removing all the ELF headers and sections that are not loadable using +`objcopy -O binary` +3. from this, create an object file, which usually has the self invented +.manual file extension, which can be linked to the appropriate stage. +4. add the generated .manual file as "source" file to the stage we want +to link it to. In the end the ELF files will have three different ELF sections, which are all created by the rmodtool. -- To view, visit https://review.coreboot.org/c/coreboot/+/86656?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9cf21b4258758b18f0d3c9316c9aa32cc0d9c44f Gerrit-Change-Number: 86656 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com>

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[XL] Change in coreboot[main]: mb/intel/ptlrvp: Add Intel Panther Lake RVP as copy of google/fatcat
by Wonkyu Kim (Code Review) Feb. 28, 2025

Feb. 28, 2025

Attention is currently required from: Bora Guvendik, Cliff Huang, Jamie Ryu, Jérémy Compostella, Paul Menzel, Zhixing Ma. Wonkyu Kim has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/84564?usp=email ) Change subject: mb/intel/ptlrvp: Add Intel Panther Lake RVP as copy of google/fatcat ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84564?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d60 Gerrit-Change-Number: 84564 Gerrit-PatchSet: 7 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 28 Feb 2025 20:50:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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