coreboot-gerrit September 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/razer/blade_stealth_kbl/gpio: Convert configuration to macros

by Maxim Polyakov (Code Review)

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43411 ) Change subject: mb/razer/blade_stealth_kbl/gpio: Convert configuration to macros ...................................................................... mb/razer/blade_stealth_kbl/gpio: Convert configuration to macros Use the intelp2m utility [1,2] to convert the current pad configuration format to the format with the the PAD_CFG() macros (*). $ ./intelp2m -n -t 1 -p snr -file src/mainboard/51nb/x210/gpio.h Unlike the raw DW0 and DW1 registers values from the inteltool dump, is more understandable and makes the code much cleaner. [*] To do this, ignore some bit fields. See Patchset 1 | Change-Id: Ie9da1246b784578c1e29acc5c61a918841de7468 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/razer/blade_stealth_kbl/gpio.h 1 file changed, 152 insertions(+), 152 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/43411/1 diff --git a/src/mainboard/razer/blade_stealth_kbl/gpio.h b/src/mainboard/razer/blade_stealth_kbl/gpio.h index c266dde..f8f5b08 100644 --- a/src/mainboard/razer/blade_stealth_kbl/gpio.h +++ b/src/mainboard/razer/blade_stealth_kbl/gpio.h @@ -10,158 +10,158 @@ /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { - /* RCIN# */ _PAD_CFG_STRUCT(GPP_A0, 0x44000702, 0x0), - /* LAD0 */ _PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x3c00), - /* LAD1 */ _PAD_CFG_STRUCT(GPP_A2, 0x44000702, 0x3c00), - /* LAD2 */ _PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x3c00), - /* LAD3 */ _PAD_CFG_STRUCT(GPP_A4, 0x44000702, 0x3c00), - /* LFRAME# */ _PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x0), - /* SERIRQ */ _PAD_CFG_STRUCT(GPP_A6, 0x44000702, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_A7, 0x84000102, 0x0), - /* CLKRUN# */ _PAD_CFG_STRUCT(GPP_A8, 0x44000702, 0x0), - /* CLKOUT_LPC0 */ _PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x1000), - /* CLKOUT_LPC1 */ _PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x1000), - /* GPIO */ _PAD_CFG_STRUCT(GPP_A11, 0x40100102, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_A12, 0x04000201, 0x0), - /* SUSWARN# */ _PAD_CFG_STRUCT(GPP_A13, 0x44000700, 0x0), - /* SUS_STAT# */ _PAD_CFG_STRUCT(GPP_A14, 0x44000700, 0x0), - /* SUS_ACK# */ _PAD_CFG_STRUCT(GPP_A15, 0x44000700, 0x1000), - /* SD_1P8_SEL */ _PAD_CFG_STRUCT(GPP_A16, 0x44000700, 0x0), - /* SD_PWR_EN# */ _PAD_CFG_STRUCT(GPP_A17, 0x44000700, 0x0), - /* ISH_GP0 */ _PAD_CFG_STRUCT(GPP_A18, 0x44000702, 0x0), - /* ISH_GP1 */ _PAD_CFG_STRUCT(GPP_A19, 0x44000702, 0x0), - /* ISH_GP2 */ _PAD_CFG_STRUCT(GPP_A20, 0x44000702, 0x0), - /* ISH_GP3 */ _PAD_CFG_STRUCT(GPP_A21, 0x44000702, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_A22, 0x44000201, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_A23, 0x40100102, 0x0), - /* CORE_VID0 */ _PAD_CFG_STRUCT(GPP_B0, 0x44000700, 0x0), - /* CORE_VID1 */ _PAD_CFG_STRUCT(GPP_B1, 0x44000700, 0x0), - /* VRALERT# */ _PAD_CFG_STRUCT(GPP_B2, 0x44000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_B3, 0x80100100, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_B4, 0x44000201, 0x0), - /* SRCCLKREQ0# */ _PAD_CFG_STRUCT(GPP_B5, 0x44000700, 0x0), - /* SRCCLKREQ1# */ _PAD_CFG_STRUCT(GPP_B6, 0x44000700, 0x0), - /* SRCCLKREQ2# */ _PAD_CFG_STRUCT(GPP_B7, 0x44000702, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_B8, 0x44000300, 0x0), - /* SRCCLKREQ4# */ _PAD_CFG_STRUCT(GPP_B9, 0x44000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_B10, 0x44000300, 0x0), - /* EXT_PWR_GATE# */ _PAD_CFG_STRUCT(GPP_B11, 0x44000700, 0x0), - /* SLP_S0# */ _PAD_CFG_STRUCT(GPP_B12, 0x44000700, 0x0), - /* PLTRST# */ _PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_B14, 0x44000201, 0x1000), - /* GPIO */ _PAD_CFG_STRUCT(GPP_B15, 0x44000200, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_B16, 0x44000300, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_B17, 0x42880100, 0x1000), - /* GPIO */ _PAD_CFG_STRUCT(GPP_B18, 0x80880102, 0x3000), - /* GPIO */ _PAD_CFG_STRUCT(GPP_B19, 0x44000300, 0x0), - /* GSPI1_CLK */ _PAD_CFG_STRUCT(GPP_B20, 0x44000700, 0x1000), - /* GSPI1_MISO */ _PAD_CFG_STRUCT(GPP_B21, 0x44000700, 0x1000), - /* GSPI1_MOSI */ _PAD_CFG_STRUCT(GPP_B22, 0x44000700, 0x1000), - /* GPIO */ _PAD_CFG_STRUCT(GPP_B23, 0x44000201, 0x1000), - /* SMBCLK */ _PAD_CFG_STRUCT(GPP_C0, 0x44000702, 0x0), - /* SMBDATA */ _PAD_CFG_STRUCT(GPP_C1, 0x44000702, 0x1000), - /* GPIO */ _PAD_CFG_STRUCT(GPP_C2, 0x44000201, 0x1000), - /* SML0CLK */ _PAD_CFG_STRUCT(GPP_C3, 0x44000702, 0x0), - /* SML0DATA */ _PAD_CFG_STRUCT(GPP_C4, 0x44000702, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_C5, 0x40900100, 0x1000), - /* RESERVED */ _PAD_CFG_STRUCT(GPP_C6, 0xffffffff, 0xffffff00), - /* RESERVED */ _PAD_CFG_STRUCT(GPP_C7, 0xffffffff, 0xffffff00), - /* UART0_RXD */ _PAD_CFG_STRUCT(GPP_C8, 0x44000702, 0x0), - /* UART0_TXD */ _PAD_CFG_STRUCT(GPP_C9, 0x44000700, 0x0), - /* UART0_RTS# */ _PAD_CFG_STRUCT(GPP_C10, 0x44000700, 0x0), - /* UART0_CTS# */ _PAD_CFG_STRUCT(GPP_C11, 0x44000700, 0x0), - /* UART1_RXD */ _PAD_CFG_STRUCT(GPP_C12, 0x44000702, 0x0), - /* UART1_TXD */ _PAD_CFG_STRUCT(GPP_C13, 0x44000700, 0x0), - /* UART1_RTS# */ _PAD_CFG_STRUCT(GPP_C14, 0x44000700, 0x0), - /* UART1_CTS# */ _PAD_CFG_STRUCT(GPP_C15, 0x44000702, 0x0), - /* I2C0_SDA */ _PAD_CFG_STRUCT(GPP_C16, 0x44000702, 0x0), - /* I2C0_SCL */ _PAD_CFG_STRUCT(GPP_C17, 0x44000702, 0x0), - /* I2C1_SDA */ _PAD_CFG_STRUCT(GPP_C18, 0x44000702, 0x0), - /* I2C1_SCL */ _PAD_CFG_STRUCT(GPP_C19, 0x44000702, 0x0), - /* UART2_RXD */ _PAD_CFG_STRUCT(GPP_C20, 0x44000702, 0x0), - /* UART2_TXD */ _PAD_CFG_STRUCT(GPP_C21, 0x44000700, 0x0), - /* UART2_RTS# */ _PAD_CFG_STRUCT(GPP_C22, 0x44000700, 0x0), - /* UART2_CTS# */ _PAD_CFG_STRUCT(GPP_C23, 0x44000702, 0x0), - /* SPI1_CS# */ _PAD_CFG_STRUCT(GPP_D0, 0x44000700, 0x0), - /* SPI1_CLK */ _PAD_CFG_STRUCT(GPP_D1, 0x44000700, 0x0), - /* SPI1_MISO */ _PAD_CFG_STRUCT(GPP_D2, 0x44000700, 0x0), - /* SPI1_MOSI */ _PAD_CFG_STRUCT(GPP_D3, 0x44000700, 0x0), - /* FLASHTRIG */ _PAD_CFG_STRUCT(GPP_D4, 0x44000700, 0x0), - /* ISH_I2C0_SDA */ _PAD_CFG_STRUCT(GPP_D5, 0x44000700, 0x0), - /* ISH_I2C0_SCL */ _PAD_CFG_STRUCT(GPP_D6, 0x44000700, 0x0), - /* ISH_I2C1_SDA */ _PAD_CFG_STRUCT(GPP_D7, 0x44000700, 0x0), - /* ISH_I2C1_SCL */ _PAD_CFG_STRUCT(GPP_D8, 0x44000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_D9, 0x40000100, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_D10, 0x40000100, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_D11, 0x40000100, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_D12, 0x40000100, 0x0), - /* ISH_UART0_RXD */ _PAD_CFG_STRUCT(GPP_D13, 0x44000700, 0x0), - /* ISH_UART0_TXD */ _PAD_CFG_STRUCT(GPP_D14, 0x44000700, 0x0), - /* ISH_UART0_RTS# */ _PAD_CFG_STRUCT(GPP_D15, 0x44000700, 0x0), - /* ISH_UART0_CTS# */ _PAD_CFG_STRUCT(GPP_D16, 0x44000700, 0x0), - /* DMIC_CLK1 */ _PAD_CFG_STRUCT(GPP_D17, 0x44000700, 0x0), - /* DMIC_DATA1 */ _PAD_CFG_STRUCT(GPP_D18, 0x44000700, 0x0), - /* DMIC_CLK0 */ _PAD_CFG_STRUCT(GPP_D19, 0x44000700, 0x0), - /* DMIC_DATA0 */ _PAD_CFG_STRUCT(GPP_D20, 0x44000700, 0x0), - /* SPI1_IO2 */ _PAD_CFG_STRUCT(GPP_D21, 0x44000700, 0x0), - /* SPI1_IO3 */ _PAD_CFG_STRUCT(GPP_D22, 0x44000700, 0x0), - /* I2S_MCLK */ _PAD_CFG_STRUCT(GPP_D23, 0x44000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E0, 0x42880100, 0x0), - /* SATAXPCIE1 */ _PAD_CFG_STRUCT(GPP_E1, 0x44000700, 0x0), - /* SATAXPCIE2 */ _PAD_CFG_STRUCT(GPP_E2, 0x44000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E3, 0x40000000, 0x0), - /* SATA_DEVSLP0 */ _PAD_CFG_STRUCT(GPP_E4, 0x04000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E5, 0x82880102, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E6, 0x44000200, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E7, 0x80180102, 0x0), - /* SATALED# */ _PAD_CFG_STRUCT(GPP_E8, 0x44000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E9, 0x44000200, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E10, 0x44000201, 0x1000), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E11, 0x44000201, 0x1000), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E12, 0x44000300, 0x0), - /* DDPB_HPD0 */ _PAD_CFG_STRUCT(GPP_E13, 0x44000702, 0x0), - /* DDPC_HPD1 */ _PAD_CFG_STRUCT(GPP_E14, 0x44000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E15, 0x42840102, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E16, 0x80880102, 0x0), - /* EDP_HPD */ _PAD_CFG_STRUCT(GPP_E17, 0x44000702, 0x0), - /* DDPB_CTRLCLK */ _PAD_CFG_STRUCT(GPP_E18, 0x44000700, 0x0), - /* DDPB_CTRLDATA */ _PAD_CFG_STRUCT(GPP_E19, 0x44000700, 0x1000), - /* DDPC_CTRLCLK */ _PAD_CFG_STRUCT(GPP_E20, 0x44000702, 0x0), - /* DDPC_CTRLDATA */ _PAD_CFG_STRUCT(GPP_E21, 0x44000702, 0x1000), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E22, 0x40900100, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_E23, 0x84000200, 0x1000), - /* I2S2_SCLK */ _PAD_CFG_STRUCT(GPP_F0, 0x44000700, 0x0), - /* I2S2_SFRM */ _PAD_CFG_STRUCT(GPP_F1, 0x44000700, 0x0), - /* I2S2_TXD */ _PAD_CFG_STRUCT(GPP_F2, 0x44000700, 0x0), - /* I2S2_RXD */ _PAD_CFG_STRUCT(GPP_F3, 0x44000700, 0x0), - /* I2C2_SDA */ _PAD_CFG_STRUCT(GPP_F4, 0x44000700, 0x2000000), - /* I2C2_SCL */ _PAD_CFG_STRUCT(GPP_F5, 0x44000702, 0x2000000), - /* I2C3_SDA */ _PAD_CFG_STRUCT(GPP_F6, 0x44000702, 0x2000000), - /* I2C3_SCL */ _PAD_CFG_STRUCT(GPP_F7, 0x44000702, 0x2000000), - /* I2C4_SDA */ _PAD_CFG_STRUCT(GPP_F8, 0x44000702, 0x2000000), - /* I2C4_SCL */ _PAD_CFG_STRUCT(GPP_F9, 0x44000702, 0x2000000), - /* ISH_I2C2_SDA */ _PAD_CFG_STRUCT(GPP_F10, 0x44000b02, 0x2000000), - /* ISH_I2C2_SCL */ _PAD_CFG_STRUCT(GPP_F11, 0x44000b02, 0x2000000), - /* EMMC_CMD */ _PAD_CFG_STRUCT(GPP_F12, 0x44000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_F13, 0x44000102, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_F14, 0x44000102, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_F15, 0x44000100, 0x0), - /* EMMC_DATA3 */ _PAD_CFG_STRUCT(GPP_F16, 0x44000700, 0x0), - /* EMMC_DATA4 */ _PAD_CFG_STRUCT(GPP_F17, 0x44000700, 0x0), - /* EMMC_DATA5 */ _PAD_CFG_STRUCT(GPP_F18, 0x44000700, 0x0), - /* EMMC_DATA6 */ _PAD_CFG_STRUCT(GPP_F19, 0x44000700, 0x0), - /* EMMC_DATA7 */ _PAD_CFG_STRUCT(GPP_F20, 0x44000700, 0x0), - /* EMMC_RCLK */ _PAD_CFG_STRUCT(GPP_F21, 0x44000700, 0x0), - /* EMMC_CLK */ _PAD_CFG_STRUCT(GPP_F22, 0x44000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_F23, 0x40100100, 0x0), - /* SD_CMD */ _PAD_CFG_STRUCT(GPP_G0, 0x44000700, 0x0), - /* SD_DATA0 */ _PAD_CFG_STRUCT(GPP_G1, 0x44000700, 0x0), - /* SD_DATA1 */ _PAD_CFG_STRUCT(GPP_G2, 0x44000700, 0x0), - /* SD_DATA2 */ _PAD_CFG_STRUCT(GPP_G3, 0x44000700, 0x0), - /* SD_DATA3 */ _PAD_CFG_STRUCT(GPP_G4, 0x44000700, 0x0), - /* SD_CD# */ _PAD_CFG_STRUCT(GPP_G5, 0x44000700, 0x0), - /* SD_CLK */ _PAD_CFG_STRUCT(GPP_G6, 0x44000700, 0x0), - /* GPIO */ _PAD_CFG_STRUCT(GPP_G7, 0x44000100, 0x0), +/* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* LAD0 */ PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* LAD1 */ PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* LAD2 */ PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* LAD3 */ PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_A7, NONE, PLTRST, OFF, ACPI), +/* CLKRUN# */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* CLKOUT_LPC0 */ PAD_CFG_NF(GPP_A9, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* CLKOUT_LPC1 */ PAD_CFG_NF(GPP_A10, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPI_APIC(GPP_A11, NONE, DEEP), +/* GPIO */ PAD_CFG_GPO(GPP_A12, 1, PWROK), +/* SUSWARN# */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SUS_STAT# */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SUS_ACK# */ PAD_CFG_NF(GPP_A15, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* ISH_GP0 */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* ISH_GP1 */ PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* ISH_GP2 */ PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* ISH_GP3 */ PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPO(GPP_A22, 1, DEEP), +/* GPIO */ PAD_CFG_GPI_APIC(GPP_A23, NONE, DEEP), +/* CORE_VID0 */ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* CORE_VID1 */ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* VRALERT# */ PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), +/* GPIO */ PAD_CFG_GPO(GPP_B4, 1, DEEP), +/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_NC(GPP_B8, NONE), +/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_NC(GPP_B10, NONE), +/* EXT_PWR_GATE# */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_TERM_GPO(GPP_B14, 1, 20K_PD, DEEP), +/* GPIO */ PAD_CFG_GPO(GPP_B15, 0, DEEP), +/* GPIO */ PAD_NC(GPP_B16, NONE), +/* GPIO */ PAD_CFG_GPI_ACPI_SCI(GPP_B17, 20K_PD, DEEP, INVERT), +/* GPIO */ PAD_CFG_GPI_SCI(GPP_B18, 20K_PU, PLTRST, LEVEL, INVERT), +/* GPIO */ PAD_NC(GPP_B19, NONE), +/* GSPI1_CLK */ PAD_CFG_NF(GPP_B20, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GSPI1_MISO */ PAD_CFG_NF(GPP_B21, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GSPI1_MOSI */ PAD_CFG_NF(GPP_B22, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_TERM_GPO(GPP_B23, 1, 20K_PD, DEEP), +/* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SMBDATA */ PAD_CFG_NF(GPP_C1, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_TERM_GPO(GPP_C2, 1, 20K_PD, DEEP), +/* SML0CLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPI_APIC_INVERT(GPP_C5, 20K_PD, DEEP), +/* RESERVED - GPP_C6 */ +/* RESERVED - GPP_C7 */ +/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* UART0_RTS# */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* UART0_CTS# */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* UART1_RXD */ PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* UART1_TXD */ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* UART1_RTS# */ PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* UART1_CTS# */ PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* UART2_RTS# */ PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* UART2_CTS# */ PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SPI1_CS# */ PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SPI1_CLK */ PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SPI1_MISO */ PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SPI1_MOSI */ PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* FLASHTRIG */ PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* ISH_I2C0_SDA */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* ISH_I2C0_SCL */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* ISH_I2C1_SDA */ PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* ISH_I2C1_SCL */ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D9, NONE, DEEP, LEVEL, ACPI), +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D10, NONE, DEEP, LEVEL, ACPI), +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D11, NONE, DEEP, LEVEL, ACPI), +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D12, NONE, DEEP, LEVEL, ACPI), +/* ISH_UART0_RXD */ PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* ISH_UART0_TXD */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* ISH_UART0_RTS# */ PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* ISH_UART0_CTS# */ PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* DMIC_CLK1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* DMIC_DATA1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SPI1_IO2 */ PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SPI1_IO3 */ PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPI_ACPI_SCI(GPP_E0, NONE, DEEP, INVERT), +/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPIO_BIDIRECT(GPP_E3, 0, NONE, DEEP, LEVEL, ACPI), +/* SATA_DEVSLP0 */ PAD_CFG_NF(GPP_E4, NONE, PWROK, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPI_ACPI_SCI(GPP_E5, NONE, PLTRST, INVERT), +/* GPIO */ PAD_CFG_GPO(GPP_E6, 0, DEEP), +/* GPIO */ PAD_CFG_GPI_DUAL_ROUTE(GPP_E7, NONE, PLTRST, LEVEL, IOAPIC, SCI), +/* SATALED# */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPO(GPP_E9, 0, DEEP), +/* GPIO */ PAD_CFG_TERM_GPO(GPP_E10, 1, 20K_PD, DEEP), +/* GPIO */ PAD_CFG_TERM_GPO(GPP_E11, 1, 20K_PD, DEEP), +/* GPIO */ PAD_NC(GPP_E12, NONE), +/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, INVERT), +/* GPIO */ PAD_CFG_GPI_SCI(GPP_E16, NONE, PLTRST, LEVEL, INVERT), +/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPI_APIC_INVERT(GPP_E22, NONE, DEEP), +/* GPIO */ PAD_CFG_TERM_GPO(GPP_E23, 0, 20K_PD, PLTRST), +/* I2S2_SCLK */ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2S2_SFRM */ PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2S2_TXD */ PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2S2_RXD */ PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2C2_SDA */ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2C2_SCL */ PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2C3_SDA */ PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2C3_SCL */ PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2C4_SDA */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2C4_SCL */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* ISH_I2C2_SDA */ PAD_CFG_NF(GPP_F10, NONE, DEEP, NF2), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* ISH_I2C2_SCL */ PAD_CFG_NF(GPP_F11, NONE, DEEP, NF2), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_F13, NONE, DEEP, OFF, ACPI), +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_F14, NONE, DEEP, OFF, ACPI), +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_F15, NONE, DEEP, OFF, ACPI), +/* EMMC_DATA3 */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* EMMC_DATA4 */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* EMMC_DATA5 */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* EMMC_DATA6 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPI_APIC(GPP_F23, NONE, DEEP), +/* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_G7, NONE, DEEP, OFF, ACPI), }; #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/43411 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9da1246b784578c1e29acc5c61a918841de7468 Gerrit-Change-Number: 43411 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

14 minutes

Change in coreboot[master]: mb/razer/blade_stealth_kbl: Remove comments with pad functions

by Maxim Polyakov (Code Review)

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45370 ) Change subject: mb/razer/blade_stealth_kbl: Remove comments with pad functions ...................................................................... mb/razer/blade_stealth_kbl: Remove comments with pad functions Remove these comments, because it does not contain useful information that helps to understand the circuit, which we do not have. Change-Id: I8a8450493ceebe97ac03b4134adc46b01328a1b6 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/razer/blade_stealth_kbl/gpio.h 1 file changed, 152 insertions(+), 152 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/45370/1 diff --git a/src/mainboard/razer/blade_stealth_kbl/gpio.h b/src/mainboard/razer/blade_stealth_kbl/gpio.h index 495c905..5dc1da4 100644 --- a/src/mainboard/razer/blade_stealth_kbl/gpio.h +++ b/src/mainboard/razer/blade_stealth_kbl/gpio.h @@ -22,158 +22,158 @@ /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { -/* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), -/* LAD0 */ PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), -/* LAD1 */ PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), -/* LAD2 */ PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), -/* LAD3 */ PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), -/* LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), -/* SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), -/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_A7, NONE, PLTRST, OFF, ACPI), -/* CLKRUN# */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), -/* CLKOUT_LPC0 */ PAD_CFG_NF(GPP_A9, 20K_PD, DEEP, NF1), -/* CLKOUT_LPC1 */ PAD_CFG_NF(GPP_A10, 20K_PD, DEEP, NF1), -/* GPIO */ PAD_CFG_GPI_APIC(GPP_A11, NONE, DEEP), -/* GPIO */ PAD_CFG_GPO(GPP_A12, 1, PWROK), -/* SUSWARN# */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), -/* SUS_STAT# */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), -/* SUS_ACK# */ PAD_CFG_NF(GPP_A15, 20K_PD, DEEP, NF1), -/* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), -/* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), -/* ISH_GP0 */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), -/* ISH_GP1 */ PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), -/* ISH_GP2 */ PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), -/* ISH_GP3 */ PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1), -/* GPIO */ PAD_CFG_GPO(GPP_A22, 1, DEEP), -/* GPIO */ PAD_CFG_GPI_APIC(GPP_A23, NONE, DEEP), -/* CORE_VID0 */ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), -/* CORE_VID1 */ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), -/* VRALERT# */ PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), -/* GPIO */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), -/* GPIO */ PAD_CFG_GPO(GPP_B4, 1, DEEP), -/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), -/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), -/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), -/* GPIO */ PAD_NC(GPP_B8, NONE), -/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), -/* GPIO */ PAD_NC(GPP_B10, NONE), -/* EXT_PWR_GATE# */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), -/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), -/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), -/* GPIO */ PAD_CFG_TERM_GPO(GPP_B14, 1, 20K_PD, DEEP), -/* GPIO */ PAD_CFG_GPO(GPP_B15, 0, DEEP), -/* GPIO */ PAD_NC(GPP_B16, NONE), -/* GPIO */ PAD_CFG_GPI_ACPI_SCI(GPP_B17, 20K_PD, DEEP, INVERT), -/* GPIO */ PAD_CFG_GPI_SCI(GPP_B18, 20K_PU, PLTRST, LEVEL, INVERT), -/* GPIO */ PAD_NC(GPP_B19, NONE), -/* GSPI1_CLK */ PAD_CFG_NF(GPP_B20, 20K_PD, DEEP, NF1), -/* GSPI1_MISO */ PAD_CFG_NF(GPP_B21, 20K_PD, DEEP, NF1), -/* GSPI1_MOSI */ PAD_CFG_NF(GPP_B22, 20K_PD, DEEP, NF1), -/* GPIO */ PAD_CFG_TERM_GPO(GPP_B23, 1, 20K_PD, DEEP), -/* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), -/* SMBDATA */ PAD_CFG_NF(GPP_C1, 20K_PD, DEEP, NF1), -/* GPIO */ PAD_CFG_TERM_GPO(GPP_C2, 1, 20K_PD, DEEP), -/* SML0CLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), -/* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), -/* GPIO */ PAD_CFG_GPI_APIC_INVERT(GPP_C5, 20K_PD, DEEP), -/* GPP_C6 - RESERVED */ -/* GPP_C7 - RESERVED */ -/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), -/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), -/* UART0_RTS# */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), -/* UART0_CTS# */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), -/* UART1_RXD */ PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), -/* UART1_TXD */ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), -/* UART1_RTS# */ PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), -/* UART1_CTS# */ PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1), -/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), -/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), -/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), -/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), -/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), -/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), -/* UART2_RTS# */ PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), -/* UART2_CTS# */ PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), -/* SPI1_CS# */ PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1), -/* SPI1_CLK */ PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1), -/* SPI1_MISO */ PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1), -/* SPI1_MOSI */ PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1), -/* FLASHTRIG */ PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), -/* ISH_I2C0_SDA */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), -/* ISH_I2C0_SCL */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), -/* ISH_I2C1_SDA */ PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), -/* ISH_I2C1_SCL */ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), -/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D9, NONE, DEEP, LEVEL, ACPI), -/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D10, NONE, DEEP, LEVEL, ACPI), -/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D11, NONE, DEEP, LEVEL, ACPI), -/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D12, NONE, DEEP, LEVEL, ACPI), -/* ISH_UART0_RXD */ PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), -/* ISH_UART0_TXD */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), -/* ISH_UART0_RTS# */ PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1), -/* ISH_UART0_CTS# */ PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1), -/* DMIC_CLK1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), -/* DMIC_DATA1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), -/* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), -/* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), -/* SPI1_IO2 */ PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), -/* SPI1_IO3 */ PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1), -/* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), -/* GPIO */ PAD_CFG_GPI_ACPI_SCI(GPP_E0, NONE, DEEP, INVERT), -/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), -/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), -/* GPIO */ PAD_CFG_GPIO_BIDIRECT(GPP_E3, 0, NONE, DEEP, LEVEL, ACPI), -/* SATA_DEVSLP0 */ PAD_CFG_NF(GPP_E4, NONE, PWROK, NF1), -/* GPIO */ PAD_CFG_GPI_ACPI_SCI(GPP_E5, NONE, PLTRST, INVERT), -/* GPIO */ PAD_CFG_GPO(GPP_E6, 0, DEEP), -/* GPIO */ PAD_CFG_GPI_DUAL_ROUTE(GPP_E7, NONE, PLTRST, LEVEL, NONE, IOAPIC, SCI), -/* SATALED# */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), -/* GPIO */ PAD_CFG_GPO(GPP_E9, 0, DEEP), -/* GPIO */ PAD_CFG_TERM_GPO(GPP_E10, 1, 20K_PD, DEEP), -/* GPIO */ PAD_CFG_TERM_GPO(GPP_E11, 1, 20K_PD, DEEP), -/* GPIO */ PAD_NC(GPP_E12, NONE), -/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), -/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), -/* GPIO */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, INVERT), -/* GPIO */ PAD_CFG_GPI_SCI(GPP_E16, NONE, PLTRST, LEVEL, INVERT), -/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), -/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), -/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, NF1), -/* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), -/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, 20K_PD, DEEP, NF1), -/* GPIO */ PAD_CFG_GPI_APIC_INVERT(GPP_E22, NONE, DEEP), -/* GPIO */ PAD_CFG_TERM_GPO(GPP_E23, 0, 20K_PD, PLTRST), -/* I2S2_SCLK */ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), -/* I2S2_SFRM */ PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), -/* I2S2_TXD */ PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), -/* I2S2_RXD */ PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1), -/* I2C2_SDA */ PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1), -/* I2C2_SCL */ PAD_CFG_NF_1V8(GPP_F5, NONE, DEEP, NF1), -/* I2C3_SDA */ PAD_CFG_NF_1V8(GPP_F6, NONE, DEEP, NF1), -/* I2C3_SCL */ PAD_CFG_NF_1V8(GPP_F7, NONE, DEEP, NF1), -/* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), -/* I2C4_SCL */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), -/* ISH_I2C2_SDA */ PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP, NF2), -/* ISH_I2C2_SCL */ PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP, NF2), -/* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), -/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_F13, NONE, DEEP, OFF, ACPI), -/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_F14, NONE, DEEP, OFF, ACPI), -/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_F15, NONE, DEEP, OFF, ACPI), -/* EMMC_DATA3 */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), -/* EMMC_DATA4 */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), -/* EMMC_DATA5 */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), -/* EMMC_DATA6 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), -/* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), -/* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), -/* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), -/* GPIO */ PAD_CFG_GPI_APIC(GPP_F23, NONE, DEEP), -/* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), -/* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), -/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), -/* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), -/* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), -/* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), -/* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), -/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_G7, NONE, DEEP, OFF, ACPI), + PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + PAD_CFG_GPI_TRIG_OWN(GPP_A7, NONE, PLTRST, OFF, ACPI), + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A9, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_A10, 20K_PD, DEEP, NF1), + PAD_CFG_GPI_APIC(GPP_A11, NONE, DEEP), + PAD_CFG_GPO(GPP_A12, 1, PWROK), + PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A15, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_A22, 1, DEEP), + PAD_CFG_GPI_APIC(GPP_A23, NONE, DEEP), + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), + PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), + PAD_CFG_GPO(GPP_B4, 1, DEEP), + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), + PAD_NC(GPP_B8, NONE), + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + PAD_NC(GPP_B10, NONE), + PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + PAD_CFG_TERM_GPO(GPP_B14, 1, 20K_PD, DEEP), + PAD_CFG_GPO(GPP_B15, 0, DEEP), + PAD_NC(GPP_B16, NONE), + PAD_CFG_GPI_ACPI_SCI(GPP_B17, 20K_PD, DEEP, INVERT), + PAD_CFG_GPI_SCI(GPP_B18, 20K_PU, PLTRST, LEVEL, INVERT), + PAD_NC(GPP_B19, NONE), + PAD_CFG_NF(GPP_B20, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_B21, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_B22, 20K_PD, DEEP, NF1), + PAD_CFG_TERM_GPO(GPP_B23, 1, 20K_PD, DEEP), + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C1, 20K_PD, DEEP, NF1), + PAD_CFG_TERM_GPO(GPP_C2, 1, 20K_PD, DEEP), + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + PAD_CFG_GPI_APIC_INVERT(GPP_C5, 20K_PD, DEEP), + /* GPP_C6 - RESERVED */ + /* GPP_C7 - RESERVED */ + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + PAD_CFG_GPI_TRIG_OWN(GPP_D9, NONE, DEEP, LEVEL, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D10, NONE, DEEP, LEVEL, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D11, NONE, DEEP, LEVEL, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D12, NONE, DEEP, LEVEL, ACPI), + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), + PAD_CFG_GPI_ACPI_SCI(GPP_E0, NONE, DEEP, INVERT), + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), + PAD_CFG_GPIO_BIDIRECT(GPP_E3, 0, NONE, DEEP, LEVEL, ACPI), + PAD_CFG_NF(GPP_E4, NONE, PWROK, NF1), + PAD_CFG_GPI_ACPI_SCI(GPP_E5, NONE, PLTRST, INVERT), + PAD_CFG_GPO(GPP_E6, 0, DEEP), + PAD_CFG_GPI_DUAL_ROUTE(GPP_E7, NONE, PLTRST, LEVEL, NONE, IOAPIC, SCI), + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_E9, 0, DEEP), + PAD_CFG_TERM_GPO(GPP_E10, 1, 20K_PD, DEEP), + PAD_CFG_TERM_GPO(GPP_E11, 1, 20K_PD, DEEP), + PAD_NC(GPP_E12, NONE), + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, INVERT), + PAD_CFG_GPI_SCI(GPP_E16, NONE, PLTRST, LEVEL, INVERT), + PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E21, 20K_PD, DEEP, NF1), + PAD_CFG_GPI_APIC_INVERT(GPP_E22, NONE, DEEP), + PAD_CFG_TERM_GPO(GPP_E23, 0, 20K_PD, PLTRST), + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1), + PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1), + PAD_CFG_NF_1V8(GPP_F5, NONE, DEEP, NF1), + PAD_CFG_NF_1V8(GPP_F6, NONE, DEEP, NF1), + PAD_CFG_NF_1V8(GPP_F7, NONE, DEEP, NF1), + PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), + PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), + PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP, NF2), + PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), + PAD_CFG_GPI_TRIG_OWN(GPP_F13, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_F14, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_F15, NONE, DEEP, OFF, ACPI), + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + PAD_CFG_GPI_APIC(GPP_F23, NONE, DEEP), + PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), + PAD_CFG_GPI_TRIG_OWN(GPP_G7, NONE, DEEP, OFF, ACPI), }; #endif /* __ACPI__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/45370 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8a8450493ceebe97ac03b4134adc46b01328a1b6 Gerrit-Change-Number: 45370 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

14 minutes

Change in coreboot[master]: mb/ocp/tiogapass/acpi: Move uncore from \_SB scope

by Maxim Polyakov (Code Review)

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45766 ) Change subject: mb/ocp/tiogapass/acpi: Move uncore from \_SB scope ...................................................................... mb/ocp/tiogapass/acpi: Move uncore from \_SB scope Change-Id: I98a8d60b585e2eafd76948baea0f249a029bae09 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/ocp/tiogapass/dsdt.asl 1 file changed, 1 insertion(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/45766/1 diff --git a/src/mainboard/ocp/tiogapass/dsdt.asl b/src/mainboard/ocp/tiogapass/dsdt.asl index bd31251..78475e0 100644 --- a/src/mainboard/ocp/tiogapass/dsdt.asl +++ b/src/mainboard/ocp/tiogapass/dsdt.asl @@ -18,9 +18,5 @@ #include <soc/intel/xeon_sp/skx/acpi/globalnvs.asl> #include <cpu/intel/common/acpi/cpu.asl> - - // Xeon-SP ACPI tables - Scope (\_SB) { - #include <soc/intel/xeon_sp/skx/acpi/uncore.asl> - } + #include <soc/intel/xeon_sp/skx/acpi/uncore.asl> } -- To view, visit https://review.coreboot.org/c/coreboot/+/45766 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I98a8d60b585e2eafd76948baea0f249a029bae09 Gerrit-Change-Number: 45766 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

28 minutes

Change in coreboot[master]: mb/ocp/tiogapass/dsdt: Remove unnecessary comments

by Maxim Polyakov (Code Review)

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45767 ) Change subject: mb/ocp/tiogapass/dsdt: Remove unnecessary comments ...................................................................... mb/ocp/tiogapass/dsdt: Remove unnecessary comments Change-Id: I6a16e2f829219f2eba8acd3ae7f371238c0d8de1 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/ocp/tiogapass/dsdt.asl 1 file changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/45767/1 diff --git a/src/mainboard/ocp/tiogapass/dsdt.asl b/src/mainboard/ocp/tiogapass/dsdt.asl index 78475e0..677d2ca 100644 --- a/src/mainboard/ocp/tiogapass/dsdt.asl +++ b/src/mainboard/ocp/tiogapass/dsdt.asl @@ -11,12 +11,8 @@ 0x20110725 // OEM revision ) { - // platform ACPI tables #include "acpi/platform.asl" - - // global NVS and variables #include <soc/intel/xeon_sp/skx/acpi/globalnvs.asl> - #include <cpu/intel/common/acpi/cpu.asl> #include <soc/intel/xeon_sp/skx/acpi/uncore.asl> } -- To view, visit https://review.coreboot.org/c/coreboot/+/45767 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a16e2f829219f2eba8acd3ae7f371238c0d8de1 Gerrit-Change-Number: 45767 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

28 minutes

Change in coreboot[master]: soc/mediatek/mt8192: Do dram full calibration

by CK HU (Code Review)

Hello Duan huayang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44570 to review the following change. Change subject: soc/mediatek/mt8192: Do dram full calibration ...................................................................... soc/mediatek/mt8192: Do dram full calibration If no correct params was found in flash, do dram full calibration Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> Change-Id: I2d4437a4e4c770de084927018d4dd3f2e8b87fb1 --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/memory.c 2 files changed, 57 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/44570/1 diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 19ab639..dd80beb 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -33,6 +33,16 @@ ramstage-y += ../common/timer.c ramstage-y += ../common/uart.c +MT8192_BLOB_DIR := 3rdparty/blobs/soc/mediatek/mt8192 + +DRAM_CBFS := $(CONFIG_CBFS_PREFIX)/dram +$(DRAM_CBFS)-file := $(MT8192_BLOB_DIR)/dram.elf +$(DRAM_CBFS)-type := stage +$(DRAM_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG) +ifneq ($(wildcard $($(DRAM_CBFS)-file)),) + cbfs-files-y += $(DRAM_CBFS) +endif + CPPFLAGS_common += -Isrc/soc/mediatek/mt8192/include CPPFLAGS_common += -Isrc/soc/mediatek/common/include diff --git a/src/soc/mediatek/mt8192/memory.c b/src/soc/mediatek/mt8192/memory.c index 84c13b7..96a8c91 100644 --- a/src/soc/mediatek/mt8192/memory.c +++ b/src/soc/mediatek/mt8192/memory.c @@ -64,6 +64,39 @@ return DRAMC_ERR_FAST_CALIBRATION; } +static int dram_run_full_calibration(struct dramc_param *dparam) +{ + /* Load and run the provided blob for full-calibration if available */ + struct prog dram = PROG_INIT(PROG_REFCODE, CONFIG_CBFS_PREFIX "/dram"); + + initialize_dramc_param(dparam); + + if (prog_locate(&dram)) + return -1; + + if (cbfs_prog_stage_load(&dram)) + return -2; + + dparam->do_putc = do_putchar; + + prog_set_entry(&dram, prog_entry(&dram), dparam); + prog_run(&dram); + if (dparam->header.status != DRAMC_SUCCESS) { + printk(BIOS_ERR, "Full calibration failed: status = %d\n", + dparam->header.status); + return -3; + } + + if (!(dparam->header.flags & DRAMC_FLAG_HAS_SAVED_DATA)) { + printk(BIOS_ERR, + "Full calibration executed without saving parameters. " + "Please ensure the blob is built properly.\n"); + return -4; + } + + return 0; +} + static void mem_init_set_default_config(struct dramc_param *dparam, u32 ddr_geometry) { @@ -103,6 +136,20 @@ } else { printk(BIOS_WARNING, "Failed to read calibration data from flash\n"); } + + /* Run full calibration */ + printk(BIOS_INFO, "DRAM-K: Full Calibration\n"); + mem_init_set_default_config(dparam, ddr_geometry); + int err = dram_run_full_calibration(dparam); + if (err == 0) { + printk(BIOS_INFO, "Successfully loaded blobs and run DRAM calibration\n"); + + dparam->header.checksum = compute_checksum(dparam); + dparam_ops->write_to_flash(dparam); + printk(BIOS_DEBUG, "Calibration params saved to flash: " + "version=%#x, size=%#x\n", + dparam->header.version, dparam->header.size); + } } static void setup_dramc_voltage_before_calibration(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/44570 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d4437a4e4c770de084927018d4dd3f2e8b87fb1 Gerrit-Change-Number: 44570 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

1 hour

Change in coreboot[master]: soc/mediatek/mt8192: Add dram control register define and bits define

by CK HU (Code Review)

Hello Duan huayang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44699 to review the following change. Change subject: soc/mediatek/mt8192: Add dram control register define and bits define ...................................................................... soc/mediatek/mt8192: Add dram control register define and bits define Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> Change-Id: Ifc64fb6c60d57184c4a2f9febe765b5cb69b39ae --- M src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/dramc_pi_api.h A src/soc/mediatek/mt8192/include/soc/dramc_register.h A src/soc/mediatek/mt8192/include/soc/dramc_register_bits_def.h 4 files changed, 5,002 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/44699/1 diff --git a/src/soc/mediatek/mt8192/include/soc/addressmap.h b/src/soc/mediatek/mt8192/include/soc/addressmap.h index e0cd536..4356d67 100644 --- a/src/soc/mediatek/mt8192/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8192/include/soc/addressmap.h @@ -15,6 +15,7 @@ enum { CKSYS_BASE = IO_PHYS, INFRACFG_AO_BASE = IO_PHYS + 0x00001000, + INFRACFG_AO_MEM_BASE = IO_PHYS + 0x00002000, GPIO_BASE = IO_PHYS + 0x00005000, SPM_BASE = IO_PHYS + 0x00006000, RGU_BASE = IO_PHYS + 0x00007000, @@ -22,6 +23,9 @@ EINT_BASE = IO_PHYS + 0x0000B000, APMIXED_BASE = IO_PHYS + 0x0000C000, PWRAP_BASE = IO_PHYS + 0x0000D000, + EMI_BASE = IO_PHYS + 0x00219000, + EMI_MPU_BASE = IO_PHYS + 0x00226000, + DRAMC_CHA_AO_BASE = IO_PHYS + 0x00230000, UART0_BASE = IO_PHYS + 0x01002000, SPI0_BASE = IO_PHYS + 0x0100A000, SPI1_BASE = IO_PHYS + 0x01010000, diff --git a/src/soc/mediatek/mt8192/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8192/include/soc/dramc_pi_api.h new file mode 100644 index 0000000..c2dec82 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/dramc_pi_api.h @@ -0,0 +1,343 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8192_DRAMC_PI_API_H__ +#define __SOC_MEDIATEK_MT8192_DRAMC_PI_API_H__ + +#include <console/console.h> +#include <delay.h> +#include <device/mmio.h> +#include <stdint.h> +#include <types.h> + +#include <soc/addressmap.h> +#include <soc/dramc_common_mt8192.h> +#include <soc/dramc_register_bits_def.h> +#include <soc/emi.h> + +#define dramc_err(_x_...) printk(BIOS_ERR, _x_) +#define dramc_info(_x_...) printk(BIOS_INFO, _x_) +#if CONFIG(DEBUG_DRAM) +#define dramc_dbg(_x_...) printk(BIOS_INFO, _x_) +#else +#define dramc_dbg(_x_...) +#endif + +#define DRAMC_BROADCAST_ON 0x7f +#define DRAMC_BROADCAST_OFF 0x0 + +#define TX_DQ_UI_TO_PI_TAP 64 +#define TX_PHASE_DQ_UI_TO_PI_TAP 32 +#define LP4_TX_VREF_DATA_NUM 50 +#define LP4_TX_VREF_PASS_CONDITION 0 +#define TX_PASS_WIN_CRITERIA 7 +#define LP4_TX_VREF_BOUNDARY_NOT_READY 0xff +#define REG_SHU_OFFSET_WIDTH 0x700 +#define SHU_OFFSET (REG_SHU_OFFSET_WIDTH / 4) + +typedef enum { + DDRFREQ_400, + DDRFREQ_600, + DDRFREQ_800, + DDRFREQ_933, + DDRFREQ_1200, + DDRFREQ_1600, + DDRFREQ_2133, + DDRFREQ_MAX, +} dram_freq_grp; + +typedef enum { + CALI_SEQ0 = 0, + CALI_SEQ1, + CALI_SEQ2, + CALI_SEQ3, + CALI_SEQ4, + CALI_SEQ5, + CALI_SEQ6, + CALI_SEQ_MAX +} dram_cali_seq; + +typedef enum { + DIV8_MODE = 0, + DIV4_MODE, + UNKNOWN_MODE, +} dram_div_mode; + +typedef enum { + VREF_CALI_OFF = 0, + VREF_CALI_ON, +} vref_cali_mode; + +typedef enum { + DRVP = 0, + DRVN, + ODTP, + ODTN, + IMP_DRV_MAX +} imp_drv_type; + +typedef enum { + RX_WIN_RD_DQC = 0, + RX_WIN_TEST_ENG, +} rx_cali_type; + +typedef enum TX_CAL_TYPE { + TX_DQ_DQS_MOVE_DQ_ONLY, + TX_DQ_DQS_MOVE_DQM_ONLY, + TX_DQ_DQS_MOVE_DQ_DQM, +} tx_cali_type; + +typedef enum { + DCM_OFF = 0, + DCM_ON, +} dcm_state; + +typedef enum { + CBT_LOW_FREQ = 0, + CBT_HIGH_FREQ, + CBT_UNKNOWN_FREQ = 0xff, +} cbt_freq; + +typedef enum { + IN_CBT, + OUT_CBT, +} cbt_state; + +enum { + PHYPLL_MODE = 0, + CLRPLL_MODE, +}; + +enum { + DutyScan_K_DQ, + DutyScan_K_DQM, +}; + +typedef enum { + O1_OFF, + O1_ON, +} o1_state; + +typedef enum +{ + SINGLE_RANK_DDR = 1, + DUAL_RANK_DDR +} ddr_rank_num; + +enum { + DQS_8PH_DEGREE_0 = 0, + DQS_8PH_DEGREE_180, + DQS_8PH_DEGREE_45, + DQS_8PH_DEGREE_MAX, +}; + +struct dram_impedance { + u32 result[ODT_MAX][IMP_DRV_MAX]; +}; + +struct mr_values { + u8 mr01[FSP_MAX]; + u8 mr02[FSP_MAX]; + u8 mr03[FSP_MAX]; + u8 mr04[RANK_MAX]; + u8 mr11[FSP_MAX]; + u8 mr12[CHANNEL_MAX][RANK_MAX][FSP_MAX]; + u8 mr13[RANK_MAX]; + u8 mr14[CHANNEL_MAX][RANK_MAX][FSP_MAX]; + u8 mr18[CHANNEL_MAX][RANK_MAX]; + u8 mr19[CHANNEL_MAX][RANK_MAX]; + u8 mr20[FSP_MAX]; + u8 mr21[FSP_MAX]; + u8 mr22[FSP_MAX]; + u8 mr23[CHANNEL_MAX][RANK_MAX]; + u8 mr26[RANK_MAX]; + u8 mr30[RANK_MAX]; + u8 mr51[FSP_MAX]; +}; + +struct ddr_cali { + u8 chn; + u8 rank; + u8 fsp; + u8 density; + u8 *pll_mode; + u32 frequency; + u32 vcore_voltage; + dram_dfs_shu shu; + ddr_rank_num support_ranks; + dbi_mode w_dbi[FSP_MAX]; + vref_cali_mode vref_cali; + dram_odt_state odt_onoff; + dram_freq_grp freq_group; + dram_div_mode div_mode; + dram_pinmux_type pinmux_type; + dram_cbt_mode cbt_mode[RANK_MAX]; + struct dram_impedance impedance; + struct mr_values *mr_value; + const struct emi_mdl *emi_config; + const struct sdram_params *params; +}; + +struct reg_bak { + u32 *addr; + u32 value; +}; + +typedef struct _ana_top_config { + u8 dll_async_en; + u8 all_slave_en; + u8 rank_mode; + u8 dll_idle_mode; + u8 aphy_comb_en; + u8 tx_odt_dis; + u8 new_8x_mode; +} ana_top_config; + +typedef struct ana_dvfs_core_config { + u8 ckr; + u8 dq_p2s_ratio; + u8 ca_p2s_ratio; + u8 dq_ca_open; + u8 dq_semi_open; + u8 ca_semi_open; + u8 ca_full_rate; + u8 dq_ckdiv4_en; + u8 ca_ckdiv4_en; + u8 ca_prediv_en; + u8 ph8_dly; + u8 semi_open_ca_pick_mck_ratio; + u8 dq_aamck_div; + u8 ca_admck_div; + u8 dq_track_ca_en; + u32 pll_freq; +} ana_dvfs_core; + +typedef struct lp4_dram_config { + u8 ex_row_en[RANK_MAX]; + u8 mr_wl; + u8 dbi_wr; + u8 dbi_rd; + u8 lp4y_en; + u8 work_fsp; +} dram_config; + +typedef struct _dvfs_group_config { + u32 data_rate; + u8 dqsien_mode; + u8 dq_p2s_ratio; + u8 ckr; +} dvfs_group_config; + +struct gating_config { + u8 gat_track_en; + u8 rx_gating_mode; + u8 rx_gating_track_mode; + u8 valid_lat_value; +}; + +typedef struct _dramc_subsys_config { + dram_freq_grp freq_group; + ana_top_config *a_cfg; + ana_dvfs_core *dvfs_core; + dram_config *lp4_init; + dvfs_group_config *dfs_gp; + struct gating_config *gat_c; +} dramc_subsys_config; + +typedef struct _reg_transfer { + u32 *addr; + u8 offset; +} reg_transfer; + +void emi_init2(void); +u32 get_column_num(void); +u32 get_row_width_from_emi(u32 rank); +u8 dramc_mode_reg_read(u8 chn, u8 mr_idx); +u8 dramc_mode_reg_read_by_rank(u8 chn, u8 rank, u8 mr_idx); +void dramc_mode_reg_write_by_rank(const struct ddr_cali *cali, + u8 chn, u8 rank, u8 mr_idx, u8 value); +void after_calib(const struct ddr_cali* cali); +void init_dram(const struct dramc_data *dparam); +void global_option_init(struct ddr_cali *cali); +u32 dramc_get_broadcast(void); +void dramc_set_broadcast(u32 onoff); +void dramc_sw_impedance_cal(dram_odt_state odt, struct dram_impedance *imp); +void dramc_sw_impedance_save_register(const struct ddr_cali *cali); +void dfs_init_for_calibration(const struct ddr_cali *cali); +void dramc_auto_refresh_switch(u8 chn, bool flag); +void dramc_runtime_config(const struct ddr_cali *cali); +void emi_mdl_init(const struct emi_mdl *emi_con); +void cke_fix_onoff(const struct ddr_cali *cali, u8 chn, u8 rank, int option); +void enable_phy_dcm_shuffle(dcm_state enable, u8 shuffle_save); +void enable_phy_dcm_non_shuffle(dcm_state enable); +void dramc_8_phase_cal(const struct ddr_cali *cali); +void dramc_duty_calibration(const struct sdram_params *params); +void dramc_write_leveling(const struct ddr_cali* cali, u8 dqs_final_delay[2][2]); +void dramc_rx_dqs_gating_cal(const struct ddr_cali* cali, u8 *txdly_min, u8 *txdly_max); +void dramc_rx_dqs_gating_post_process(const struct ddr_cali* cali, + u8 txdly_min, u8 txdly_max); +void dramc_rx_datlat_cal(const struct ddr_cali* cali); +void dramc_dual_rank_rx_datlat_cal(const struct ddr_cali* cali); +void dramc_cmd_bus_training(const struct ddr_cali* cali); +void dramc_rx_window_perbit_cal(const struct ddr_cali* cali, rx_cali_type type); +void dramc_tx_window_perbit_cal(const struct ddr_cali* cali, tx_cali_type calType, + const u8 dqs_final_delay[2][2], bool u1VrefScanEnable); +void dramc_tx_oe_calibration(const struct ddr_cali* cali); +dram_freq_grp get_freq_group(const struct ddr_cali *cali); +dram_odt_state get_odt_state(const struct ddr_cali *cali); +u8 get_fsp(const struct ddr_cali *cali); +dram_dfs_shu get_shu(const struct ddr_cali *cali); +dram_freq_grp get_highest_freq_group(void); +dram_cbt_mode get_cbt_mode(const struct ddr_cali *cali); +u32 get_frequency(const struct ddr_cali *cali); +vref_cali_mode get_vref_cali(const struct ddr_cali *cali); +dram_div_mode get_div_mode(const struct ddr_cali *cali); +dbi_mode get_write_dbi(const struct ddr_cali *cali); +dram_dfs_shu get_shu_save_by_k_shu(dram_cali_seq k_shu); +dram_freq_grp get_freq_group_by_shu_save(dram_dfs_shu shu); +dram_pinmux_type get_pinmux_type(const struct ddr_cali *cali); +u32 get_frequency_by_shu(dram_dfs_shu shu); +u32 get_vcore_value(const struct ddr_cali *cali); +void set_cali_datas(struct ddr_cali *cali, const struct dramc_data *dparam, dram_cali_seq k_shu); +u8 get_mck2ui_div_shift(const struct ddr_cali *cali); +void tx_picg_setting(const struct ddr_cali *cali); +void xrtrtr_shu_setting(const struct ddr_cali *cali); +void cbt_switch_freq(const struct ddr_cali *cali, cbt_freq freq); +void enable_dfs_hw_mode_clk(void); +void dramc_dfs_direct_jump_rg_mode(const struct ddr_cali *cali, u8 shu_level); +void dramc_dfs_direct_jump_sram_shu_rg_mode(const struct ddr_cali *cali, + dram_dfs_shu shu_level); +void dramc_save_result_to_shuffle(dram_dfs_shu src, dram_dfs_shu dst); +void dramc_load_shuffle_to_dramc(dram_dfs_shu src, dram_dfs_shu dst); +void dvfs_settings(const struct ddr_cali *cali); +void dramc_dqs_precalculation_preset(const struct ddr_cali* cali); +void freq_jump_ratio_calculation(const struct ddr_cali *cali); +void dramc_hmr4_presetting(const struct ddr_cali* cali); +void dramc_enable_perbank_refresh(bool en); +void dramc_modified_refresh_mode(void); +void dramc_cke_debounce(const struct ddr_cali* cali); +void dramc_hw_dqsosc(const struct ddr_cali* cali, u8 chn); +void xrtwtw_shu_setting(const struct ddr_cali* cali); +void enable_write_DBI_after_calibration(const struct ddr_cali* cali); +void dramc_set_mr13_vrcg_to_normal(const struct ddr_cali* cali); +void ana_init(const struct ddr_cali *cali, dramc_subsys_config *subsys); +void dig_static_setting(const struct ddr_cali *cali, dramc_subsys_config *subsys); +void dig_config_shuf(const struct ddr_cali *cali, dramc_subsys_config *subsys); +void resetb_pull_dn(void); +void dramc_subsys_pre_config(dram_freq_grp freq_group, dramc_subsys_config *subsys); +void single_end_dramc_post_config(u8 lp4y_en); +void dram_configure(dram_freq_grp freq_group, dram_config *tr); +void ana_clk_div_config( ana_dvfs_core *tr,dvfs_group_config *dfs); +void apply_write_dbi_power_improve(bool onoff); +void dramc_write_dbi_onoff(u8 onoff); +void cbt_delay_ca_clk(u8 chn, u8 rank, s32 iDelay); +void dramc_cmd_UI_delay_setting(u8 chn, u8 value); +void dramc_dqsosc_set_mr18_mr19(const struct ddr_cali* cali, + u16 *osc_thrd_inc, u16 *osc_thrd_dec); +void dqsosc_shu_settings(const struct ddr_cali* cali, + u16 *osc_thrd_inc, u16 *osc_thrd_dec); +void shift_dq_ui(const struct ddr_cali* cali, u8 rk, s8 shift_ui); +void shuffle_dfs_to_fsp1(const struct ddr_cali* cali); +u8 get_cbt_vref_pinmux_value(const struct ddr_cali* cali, u8 range, u8 vref_lev); +void o1_path_on_off(const struct ddr_cali* cali, o1_state o1); + +#endif /* __SOC_MEDIATEK_MT8192_DRAMC_PI_API_H__ */ diff --git a/src/soc/mediatek/mt8192/include/soc/dramc_register.h b/src/soc/mediatek/mt8192/include/soc/dramc_register.h new file mode 100644 index 0000000..ae7e169 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/dramc_register.h @@ -0,0 +1,1818 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8192_DRAMC_REGISTER_H__ +#define __SOC_MEDIATEK_MT8192_DRAMC_REGISTER_H__ + +#include <types.h> +#include <soc/addressmap.h> +#include <soc/dpm.h> + +struct dramc_nao_regs { + u32 testmode; + u32 rsvd_0[4]; + u32 rdqc_cmp; + u32 rdqc_dqm_cmp; + u32 rsvd_1[2]; + u32 dmmonitor; + u32 rsvd_2[2]; + u32 initk_pat0; + u32 initk_pat1; + u32 initk_pat2; + u32 initk_pat3; + u32 initk_pat4; + u32 rsvd_3[3]; + u32 spcmdresp3; + u32 cbt_wlev_status2; + u32 rsvd_4[10]; + u32 misc_statusa; + u32 special_status; + u32 spcmdresp; + u32 mrr_status; + u32 mrr_status2; + u32 mrrdata0; + u32 mrrdata1; + u32 mrrdata2; + u32 mrrdata3; + u32 ref_status; + u32 rsvd_5[2]; + u32 wck_status; + u32 rsvd_6[3]; + u32 tcmdo1lat; + u32 cbt_wlev_status1; + u32 cbt_wlev_status; + u32 spcmdresp2; + u32 cbt_wlev_atk_result0; + u32 cbt_wlev_atk_result1; + u32 cbt_wlev_atk_result2; + u32 cbt_wlev_atk_result3; + u32 cbt_wlev_atk_result4; + u32 cbt_wlev_atk_result5; + u32 cbt_wlev_atk_result6; + u32 cbt_wlev_atk_result7; + u32 cbt_wlev_atk_result8; + u32 cbt_wlev_atk_result9; + u32 cbt_wlev_atk_result10; + u32 cbt_wlev_atk_result11; + u32 cbt_wlev_atk_result12; + u32 cbt_wlev_atk_result13; + u32 rsvd_7[1]; + u32 hwmrr_push2pop_cnt; + u32 hwmrr_status; + u32 hw_refrate_mon; + u32 hw_refrate_mon2; + u32 hw_refrate_mon3; + u32 testrpt; + u32 cmp_err; + u32 test_abit_status1; + u32 test_abit_status2; + u32 test_abit_status3; + u32 test_abit_status4; + u32 test_abit_status5; + u32 test_abit_status6; + u32 test_abit_status7; + u32 test_abit_status8; + u32 test_rf_error_flag0; + u32 test_rf_error_flag1; + u32 test_rf_error_cnt1; + u32 test_rf_error_cnt2; + u32 test_rf_error_cnt3; + u32 test_rf_error_cnt4; + u32 test_rf_error_cnt5; + u32 test_rf_error_cnt6; + u32 test_rf_error_cnt7; + u32 test_rf_error_cnt8; + u32 test_loop_cnt; + u32 rsvd_8[3]; + u32 sref_dly_cnt; + u32 rsvd_9[31]; + u32 tx_atk_set0; + u32 tx_atk_set1; + u32 rsvd_10[2]; + u32 tx_atk_result0; + u32 tx_atk_result1; + u32 tx_atk_result2; + u32 tx_atk_result3; + u32 tx_atk_result4; + u32 tx_atk_result5; + u32 tx_atk_result6; + u32 tx_atk_result7; + u32 tx_atk_result8; + u32 rsvd_11[3]; + u32 tx_atk_dbg_bit_status1; + u32 tx_atk_dbg_bit_status2; + u32 tx_atk_dbg_bit_status3; + u32 tx_atk_dbg_bit_status4; + u32 rsvd_12[34]; + u32 lp5_pdx_pde_mon; + u32 lp5_pdx_pde_max_mon; + u32 dram_clk_en_0_old_counter; + u32 aphypi_cg_ck_old_counter; + u32 ckeo_pre_old_counter; + u32 cke1o_pre_old_counter; + u32 dram_clk_en_0_new_counter; + u32 aphypi_cg_ck_new_counter; + u32 ckeo_pre_new_counter; + u32 cke1o_pre_new_counter; + u32 refresh_pop_counter; + u32 freerun_26m_counter; + u32 dramc_idle_counter; + u32 r2r_page_hit_counter; + u32 r2r_page_miss_counter; + u32 r2r_interbank_counter; + u32 r2w_page_hit_counter; + u32 r2w_page_miss_counter; + u32 r2w_interbank_counter; + u32 w2r_page_hit_counter; + u32 w2r_page_miss_counter; + u32 w2r_interbank_counter; + u32 w2w_page_hit_counter; + u32 w2w_page_miss_counter; + u32 w2w_interbank_counter; + u32 rk0_pre_standby_counter; + u32 rk0_pre_powerdown_counter; + u32 rk0_act_standby_counter; + u32 rk0_act_powerdown_counter; + u32 rk1_pre_standby_counter; + u32 rk1_pre_powerdown_counter; + u32 rk1_act_standby_counter; + u32 rk1_act_powerdown_counter; + u32 rk2_pre_standby_counter; + u32 rk2_pre_powerdown_counter; + u32 rk2_act_standby_counter; + u32 rk2_act_powerdown_counter; + u32 dq0_toggle_counter; + u32 dq1_toggle_counter; + u32 dq2_toggle_counter; + u32 dq3_toggle_counter; + u32 dq0_toggle_counter_r; + u32 dq1_toggle_counter_r; + u32 dq2_toggle_counter_r; + u32 dq3_toggle_counter_r; + u32 read_bytes_counter; + u32 write_bytes_counter; + u32 max_sref_req_to_ack_latency_counter; + u32 rsvd_13[2]; + u32 dramc_idle_dcm_counter; + u32 ddrphy_clk_en_counter; + u32 ddrphy_clk_en_comb_counter; + u32 rsvd_14[1]; + u32 ebg_counter_cnt0; + u32 ebg_counter_cnt1; + u32 ebg_counter_cnt2; + u32 rsvd_15[1]; + u32 lat_counter_cmd0; + u32 lat_counter_cmd1; + u32 lat_counter_cmd2; + u32 lat_counter_cmd3; + u32 lat_counter_cmd4; + u32 lat_counter_cmd5; + u32 lat_counter_cmd6; + u32 lat_counter_cmd7; + u32 lat_counter_aver; + u32 lat_counter_num; + u32 lat_counter_block_ale; + u32 rsvd_16[70]; + u32 dramc_loop_bak_adr; + u32 dramc_loop_bak_rk; + u32 rsvd_17[1]; + u32 dramc_loop_bak_wdat0; + u32 dramc_loop_bak_wdat1; + u32 dramc_loop_bak_wdat2; + u32 dramc_loop_bak_wdat3; + u32 dramc_loop_bak_wdat4; + u32 dramc_loop_bak_wdat5; + u32 dramc_loop_bak_wdat6; + u32 dramc_loop_bak_wdat7; + u32 rsvd_18[52]; + u32 rk0_dqsosc_status; + u32 rk0_dqsosc_delta; + u32 rk0_dqsosc_delta2; + u32 rsvd_19[1]; + u32 rk0_current_tx_setting1; + u32 rk0_current_tx_setting2; + u32 rk0_current_tx_setting3; + u32 rk0_current_tx_setting4; + u32 rk0_dummy_rd_data0; + u32 rk0_dummy_rd_data1; + u32 rk0_dummy_rd_data2; + u32 rk0_dummy_rd_data3; + u32 rk0_dummy_rd_data4; + u32 rk0_dummy_rd_data5; + u32 rk0_dummy_rd_data6; + u32 rk0_dummy_rd_data7; + u32 rsvd_20[8]; + u32 rk0_pi_dq_cal; + u32 rsvd_21[1]; + u32 rk0_pi_dqm_cal; + u32 rsvd_22[37]; + u32 rk1_dqsosc_status; + u32 rk1_dqsosc_delta; + u32 rk1_dqsosc_delta2; + u32 rsvd_23[1]; + u32 rk1_current_tx_setting1; + u32 rk1_current_tx_setting2; + u32 rk1_current_tx_setting3; + u32 rk1_current_tx_setting4; + u32 rk1_dummy_rd_data0; + u32 rk1_dummy_rd_data1; + u32 rk1_dummy_rd_data2; + u32 rk1_dummy_rd_data3; + u32 rk1_dummy_rd_data4; + u32 rk1_dummy_rd_data5; + u32 rk1_dummy_rd_data6; + u32 rk1_dummy_rd_data7; + u32 rsvd_24[8]; + u32 rk1_pi_dq_cal; + u32 rsvd_25[1]; + u32 rk1_pi_dqm_cal; + u32 rsvd_26[101]; + u32 mr_backup_00_rk0_fsp0; + u32 mr_backup_01_rk0_fsp0; + u32 mr_backup_02_rk0_fsp0; + u32 mr_backup_03_rk0_fsp0; + u32 mr_backup_04_rk0_fsp0; + u32 mr_backup_05_rk0_fsp0; + u32 mr_backup_06_rk0_fsp0; + u32 mr_backup_07_rk0_fsp0; + u32 mr_backup_08_rk0_fsp0; + u32 mr_backup_09_rk0_fsp0; + u32 rsvd_27[2]; + u32 mr_backup_00_rk0_fsp1; + u32 mr_backup_01_rk0_fsp1; + u32 mr_backup_02_rk0_fsp1; + u32 mr_backup_03_rk0_fsp1; + u32 mr_backup_04_rk0_fsp1; + u32 rsvd_28[7]; + u32 mr_backup_00_rk0_fsp2; + u32 mr_backup_01_rk0_fsp2; + u32 mr_backup_02_rk0_fsp2; + u32 mr_backup_03_rk0_fsp2; + u32 rsvd_29[100]; + u32 mr_backup_00_rk1_fsp0; + u32 mr_backup_01_rk1_fsp0; + u32 mr_backup_02_rk1_fsp0; + u32 mr_backup_03_rk1_fsp0; + u32 mr_backup_04_rk1_fsp0; + u32 mr_backup_05_rk1_fsp0; + u32 mr_backup_06_rk1_fsp0; + u32 mr_backup_07_rk1_fsp0; + u32 mr_backup_08_rk1_fsp0; + u32 mr_backup_09_rk1_fsp0; + u32 rsvd_30[2]; + u32 mr_backup_00_rk1_fsp1; + u32 mr_backup_01_rk1_fsp1; + u32 mr_backup_02_rk1_fsp1; + u32 mr_backup_03_rk1_fsp1; + u32 mr_backup_04_rk1_fsp1; + u32 rsvd_31[7]; + u32 mr_backup_00_rk1_fsp2; + u32 mr_backup_01_rk1_fsp2; + u32 mr_backup_02_rk1_fsp2; + u32 mr_backup_03_rk1_fsp2; +}; + +struct ddrphy_nao_regs { + u32 misc_sta_extlb0; + u32 misc_sta_extlb1; + u32 misc_sta_extlb2; + u32 rsvd_0[1]; + u32 misc_dma_debug0; + u32 misc_dma_debug1; + u32 misc_retry_dbg0; + u32 misc_retry_dbg1; + u32 misc_retry_dbg2; + u32 misc_rdsel_track_dbg; + u32 rsvd_1[22]; + u32 misc_dq_rxdly_trro0; + u32 misc_dq_rxdly_trro1; + u32 misc_dq_rxdly_trro2; + u32 misc_dq_rxdly_trro3; + u32 misc_dq_rxdly_trro4; + u32 misc_dq_rxdly_trro5; + u32 misc_dq_rxdly_trro6; + u32 misc_dq_rxdly_trro7; + u32 misc_dq_rxdly_trro8; + u32 misc_dq_rxdly_trro9; + u32 misc_dq_rxdly_trro10; + u32 misc_dq_rxdly_trro11; + u32 misc_dq_rxdly_trro12; + u32 misc_dq_rxdly_trro13; + u32 misc_dq_rxdly_trro14; + u32 misc_dq_rxdly_trro15; + u32 misc_dq_rxdly_trro16; + u32 misc_dq_rxdly_trro17; + u32 misc_dq_rxdly_trro18; + u32 misc_dq_rxdly_trro19; + u32 misc_dq_rxdly_trro20; + u32 misc_dq_rxdly_trro21; + u32 misc_dq_rxdly_trro22; + u32 misc_dq_rxdly_trro23; + u32 misc_dq_rxdly_trro24; + u32 misc_dq_rxdly_trro25; + u32 misc_dq_rxdly_trro26; + u32 misc_dq_rxdly_trro27; + u32 misc_dq_rxdly_trro28; + u32 misc_dq_rxdly_trro29; + u32 misc_dq_rxdly_trro30; + u32 misc_dq_rxdly_trro31; + u32 rsvd_2[20]; + u32 misc_ca_rxdly_trro20; + u32 misc_ca_rxdly_trro21; + u32 misc_ca_rxdly_trro22; + u32 misc_ca_rxdly_trro23; + u32 misc_ca_rxdly_trro24; + u32 misc_ca_rxdly_trro25; + u32 misc_ca_rxdly_trro26; + u32 misc_ca_rxdly_trro27; + u32 misc_ca_rxdly_trro28; + u32 misc_ca_rxdly_trro29; + u32 misc_ca_rxdly_trro30; + u32 misc_ca_rxdly_trro31; + u32 misc_dqo1; + u32 misc_cao1; + u32 misc_ad_rx_dq_o1; + u32 misc_ad_rx_cmd_o1; + u32 misc_phy_rgs_dq; + u32 misc_phy_rgs_cmd; + u32 misc_phy_rgs_stben_b0; + u32 misc_phy_rgs_stben_b1; + u32 misc_phy_rgs_stben_cmd; + u32 misc_phy_picg_mon_s0; + u32 misc_phy_picg_mon_s1; + u32 misc_phy_picg_mon_s2; + u32 misc_phy_picg_mon_s3; + u32 misc_phy_picg_mon_s4; + u32 misc_phy_picg_mon_s5; + u32 misc_phy_picg_mon_s6; + u32 misc_phy_picg_mon_s7; + u32 misc_phy_picg_mon_s8; + u32 misc_mbist_status; + u32 misc_mbist_status2; + u32 misc_impcal_status1; + u32 misc_impcal_status2; + u32 misc_impcal_status3; + u32 misc_impcal_status4; + u32 misc_impcal_status5; + u32 misc_impcal_status6; + u32 misc_impcal_status7; + u32 misc_impcal_status8; + u32 rsvd_3[1]; + u32 misc_impcal_status9; + u32 misc_sta_toglb0; + u32 misc_sta_toglb1; + u32 rsvd_4[5]; + u32 misc_sta_extlb_dbg0; + u32 misc_sta_extlb_dbg1; + u32 misc_sta_extlb_dbg2; + u32 misc_sta_extlb_dbg3; + u32 misc_duty_toggle_cnt; + u32 misc_duty_dqs0_err_cnt; + u32 misc_duty_dq_err_cnt0; + u32 misc_duty_dqs1_err_cnt; + u32 misc_duty_dq_err_cnt1; + u32 misc_duty_dqs2_err_cnt; + u32 misc_duty_dq_err_cnt2; + u32 misc_duty_dqs3_err_cnt; + u32 misc_duty_dq_err_cnt3; + u32 misc_jmeter_st0; + u32 misc_jmeter_st1; + u32 misc_emi_lpbk0; + u32 misc_emi_lpbk1; + u32 misc_emi_lpbk2; + u32 misc_emi_lpbk3; + u32 misc_emi_lpbk4; + u32 misc_emi_lpbk5; + u32 misc_emi_lpbk6; + u32 misc_emi_lpbk7; + u32 misc_ft_status0; + u32 misc_ft_status1; + u32 misc_ft_status2; + u32 misc_ft_status3; + u32 misc_ft_status4; + u32 misc_sta_toglb2; + u32 misc_sta_toglb3; + u32 misc_sta_extlb3; + u32 misc_sta_extlb4; + u32 misc_sta_extlb5; + u32 rsvd_5[90]; + u32 debug_aphy_rx_ctl; + u32 rsvd_6[3]; + u32 gating_err_infor; + u32 debug_dqsien_b0; + u32 debug_dqsien_b1; + u32 debug_dqsien_ca; + u32 gating_err_latch_dly_b0_rk0; + u32 gating_err_latch_dly_b1_rk0; + u32 gating_err_latch_dly_ca_rk0; + u32 rsvd_7[1]; + u32 gating_err_latch_dly_b0_rk1; + u32 gating_err_latch_dly_b1_rk1; + u32 gating_err_latch_dly_ca_rk1; + u32 rsvd_8[1]; + u32 debug_rodt_ctl; + u32 rsvd_9[47]; + u32 cal_dqsg_cnt_b0; + u32 cal_dqsg_cnt_b1; + u32 cal_dqsg_cnt_ca; + u32 dvfs_status; + u32 rx_autok_status0; + u32 rx_autok_status1; + u32 rx_autok_status2; + u32 rx_autok_status3; + u32 rx_autok_status4; + u32 rx_autok_status5; + u32 rx_autok_status6; + u32 rx_autok_status7; + u32 rx_autok_status8; + u32 rx_autok_status9; + u32 rx_autok_status10; + u32 rx_autok_status11; + u32 rx_autok_status12; + u32 rx_autok_status13; + u32 rx_autok_status14; + u32 rx_autok_status15; + u32 rx_autok_status16; + u32 rx_autok_status17; + u32 rx_autok_status18; + u32 rx_autok_status19; + u32 rx_autok_status20; + u32 rsvd_10[39]; + u32 dqsien_autok_b0_rk0_status0; + u32 dqsien_autok_b0_rk0_status1; + u32 dqsien_autok_b0_rk0_dbg_status0; + u32 dqsien_autok_b0_rk0_dbg_status1; + u32 dqsien_autok_b0_rk0_dbg_status2; + u32 dqsien_autok_b0_rk0_dbg_status3; + u32 dqsien_autok_b0_rk0_dbg_status4; + u32 dqsien_autok_b0_rk0_dbg_status5; + u32 dqsien_autok_b0_rk1_status0; + u32 dqsien_autok_b0_rk1_status1; + u32 dqsien_autok_b0_rk1_dbg_status0; + u32 dqsien_autok_b0_rk1_dbg_status1; + u32 dqsien_autok_b0_rk1_dbg_status2; + u32 dqsien_autok_b0_rk1_dbg_status3; + u32 dqsien_autok_b0_rk1_dbg_status4; + u32 dqsien_autok_b0_rk1_dbg_status5; + u32 dqsien_autok_b1_rk0_status0; + u32 dqsien_autok_b1_rk0_status1; + u32 dqsien_autok_b1_rk0_dbg_status0; + u32 dqsien_autok_b1_rk0_dbg_status1; + u32 dqsien_autok_b1_rk0_dbg_status2; + u32 dqsien_autok_b1_rk0_dbg_status3; + u32 dqsien_autok_b1_rk0_dbg_status4; + u32 dqsien_autok_b1_rk0_dbg_status5; + u32 dqsien_autok_b1_rk1_status0; + u32 dqsien_autok_b1_rk1_status1; + u32 dqsien_autok_b1_rk1_dbg_status0; + u32 dqsien_autok_b1_rk1_dbg_status1; + u32 dqsien_autok_b1_rk1_dbg_status2; + u32 dqsien_autok_b1_rk1_dbg_status3; + u32 dqsien_autok_b1_rk1_dbg_status4; + u32 dqsien_autok_b1_rk1_dbg_status5; + u32 dqsien_autok_ca_rk0_status0; + u32 dqsien_autok_ca_rk0_status1; + u32 dqsien_autok_ca_rk0_dbg_status0; + u32 dqsien_autok_ca_rk0_dbg_status1; + u32 dqsien_autok_ca_rk0_dbg_status2; + u32 dqsien_autok_ca_rk0_dbg_status3; + u32 dqsien_autok_ca_rk0_dbg_status4; + u32 dqsien_autok_ca_rk0_dbg_status5; + u32 rsvd_11[24]; + u32 dqsien_autok_ca_rk1_status0; + u32 dqsien_autok_ca_rk1_status1; + u32 dqsien_autok_ca_rk1_dbg_status0; + u32 dqsien_autok_ca_rk1_dbg_status1; + u32 dqsien_autok_ca_rk1_dbg_status2; + u32 dqsien_autok_ca_rk1_dbg_status3; + u32 dqsien_autok_ca_rk1_dbg_status4; + u32 dqsien_autok_ca_rk1_dbg_status5; + u32 dqsien_autok_ctrl_status; + u32 ad_dline_mon; + u32 dline_mon_track_dbg; + u32 misc_dutycal_status; + u32 misc_dbg_db_imp_message0; + u32 misc_dbg_db_imp_message1; + u32 misc_dbg_db_imp_message2; + u32 misc_dbg_db_imp_message3; + u32 misc_dbg_db_imp_message4; + u32 misc_dbg_db_imp_message5; + u32 misc_dbg_db_imp_message6; + u32 misc_dbg_db_imp_message7; + u32 misc_dbg_db_imp_message8; + u32 misc_dbg_db_imp_message9; + u32 misc_dbg_db_imp_message10; + u32 misc_dbg_db_imp_message11; + u32 rsvd_12[40]; + u32 misc_dma_sram_mbist; + u32 rsvd_13[7]; + u32 misc_aphy_obs0; + u32 misc_aphy_obs1; + u32 misc_aphy_obs2; + u32 misc_aphy_obs3; + u32 misc_aphy_obs4; + u32 misc_aphy_obs5; + u32 misc_aphy_obs6; + u32 misc_aphy_obs7; + u32 misc_aphy_obs8; +}; + +struct dramc_ao_rk { + u32 rk_test2_a1; + u32 rk_dummy_rd_wdata0; + u32 rk_dummy_rd_wdata1; + u32 rk_dummy_rd_wdata2; + u32 rk_dummy_rd_wdata3; + u32 rk_dummy_rd_adr; + u32 rsvd_0[15]; + u32 rk_dummy_rd_adr2; + u32 rsvd_1[4]; + u32 rk_sref_dpd_tck_rk_ctrl; + u32 rsvd_2[9]; + u32 rk_dqsosc; + u32 rsvd_3[91]; +}; + +struct dramc_ao_shu_rk { + u32 shurk_selph_dq0; + u32 shurk_selph_dq1; + u32 shurk_selph_dq2; + u32 shurk_selph_dq3; + u32 shurk_dqs2dq_cal1; + u32 shurk_dqs2dq_cal2; + u32 shurk_dqs2dq_cal3; + u32 shurk_dqs2dq_cal4; + u32 shurk_dqs2dq_cal5; + u32 shurk_pi; + u32 shurk_dqsosc; + u32 shurk_dqsosc_thrd; + u32 shurk_aphy_tx_picg_ctrl; + u32 rsvd_25[3]; + u32 shurk_wck_wr_mck; + u32 shurk_wck_rd_mck; + u32 shurk_wck_fs_mck; + u32 shurk_wck_wr_ui; + u32 shurk_wck_rd_ui; + u32 shurk_wck_fs_ui; + u32 rsvd_26[2]; + u32 shurk_cke_ctrl; + u32 rsvd_27[103]; +}; + +struct dramc_ao_regs { + u32 ddrcommon0; + u32 rsvd_0[2]; + u32 sa_reserve; + u32 rsvd_1[59]; + u32 nonshu_rsv; + u32 test2_a0; + u32 test2_a2; + u32 test2_a3; + u32 test2_a4; + u32 dummy_rd; + u32 dummy_rd_intv; + u32 bus_mon1; + u32 dramc_dbg_sel1; + u32 dramc_dbg_sel2; + u32 swcmd_en; + u32 swcmd_ctrl0; + u32 swcmd_ctrl1; + u32 swcmd_ctrl2; + u32 rddqcgolden1; + u32 rddqcgolden; + u32 rtmrw_ctrl0; + u32 rtmrw_ctrl1; + u32 rtmrw_ctrl2; + u32 rtmrw_ctrl3; + u32 cbt_wlev_ctrl0; + u32 cbt_wlev_ctrl1; + u32 cbt_wlev_ctrl2; + u32 cbt_wlev_ctrl3; + u32 cbt_wlev_ctrl4; + u32 cbt_wlev_atk_ctrl0; + u32 cbt_wlev_atk_ctrl1; + u32 sref_dpd_ctrl; + u32 cfc_ctrl; + u32 dllfrz_ctrl; + u32 mpc_ctrl; + u32 hw_mrr_fun; + u32 scheduler_com; + u32 rsvd_2[4]; + u32 actiming_ctrl; + u32 rsvd_3[3]; + u32 zq_set0; + u32 zq_set1; + u32 rsvd_4[2]; + u32 tx_tracking_set0; + u32 rsvd_5[3]; + u32 tx_retry_set0; + u32 rsvd_6[1]; + u32 mpc_option; + u32 rsvd_7[1]; + u32 mrr_bit_mux1; + u32 mrr_bit_mux2; + u32 mrr_bit_mux3; + u32 mrr_bit_mux4; + u32 rsvd_8[6]; + u32 shuctrl; + u32 dramc_pd_ctrl; + u32 dcm_ctrl0; + u32 ckectrl; + u32 dvfs_ctrl0; + u32 shuctrl1; + u32 dvfs_timing_ctrl1; + u32 shuctrl3; + u32 dvfs_timing_ctrl3; + u32 cmd_dec_ctrl0; + u32 hmr4; + u32 bypass_fspop; + u32 rkcfg; + u32 slp4_testmode; + u32 dq_mux_set0; + u32 dbiwr_protect; + u32 tx_set0; + u32 tx_cg_set0; + u32 rx_set0; + u32 rx_cg_set0; + u32 dqsoscr; + u32 dramctrl; + u32 misctl0; + u32 perfctl0; + u32 arbctl; + u32 datascr; + u32 clkar; + u32 refctrl0; + u32 refctrl1; + u32 ref_bounce1; + u32 ref_bounce2; + u32 rsvd_9[1]; + u32 refpend1; + u32 refpend2; + u32 refque_cnt; + u32 scsmctrl; + u32 scsmctrl_cg; + u32 refctrl2; + u32 tx_freq_ratio_old_mode0; + u32 tx_freq_ratio_old_mode1; + u32 tx_freq_ratio_old_mode2; + u32 wdt_rst; + u32 seda_loop_bak_err_pat_b01; + u32 seda_loop_bak_err_pat_b23; + u32 seda_loop_bak_err_pat_b45; + u32 seda_loop_bak_err_pat_b67; + u32 seda_loop_bak_set; + u32 rsvd_10[3]; + u32 dbg_cmddec_cmdsel0; + u32 dbg_cmddec_cmdsel1; + u32 dbg_cmddec_cmdsel2; + u32 dbg_cmddec_cmdsel3; + u32 dbg_cmddec_cmdsel4; + u32 rtswcmd_cnt; + u32 refctrl3; + u32 rsvd_11[1]; + u32 dramc_irq_en; + u32 dramc_irq_clear; + u32 irq_rsv1; + u32 irq_rsv2; + u32 refcnt_fr_clk1; + u32 refcnt_fr_clk2; + u32 refcnt_fr_clk3; + u32 refcnt_fr_clk4; + u32 refcnt_fr_clk5; + u32 refcnt_fr_clk6; + u32 refcnt_fr_clk7; + u32 rsvd_12[1]; + u32 dcm_sub_ctrl; + u32 rsvd_13[3]; + u32 cbt_wlev_ctrl5; + u32 rsvd_14[3]; + u32 dram_clk_ctrl; + u32 rsvd_15[115]; + struct dramc_ao_rk rk[RANK_MAX]; + u32 rsvd_19[256]; + u32 wdt_dbg_signal; + u32 rsvd_20[1]; + u32 selfref_hwsave_flag; + u32 rsvd_21[125]; + u32 dramc_irq_status1; + u32 dramc_irq_status2; + u32 rsvd_22[2]; + u32 dramc_irq_info1; + u32 dramc_irq_info1a; + u32 rsvd_23[2]; + u32 dramc_irq_info2; + u32 dramc_irq_info3; + u32 dramc_irq_info4; + u32 dramc_irq_info5; + u32 rsvd_24[180]; + struct dramc_ao_shu_rk shu_rk[RANK_MAX]; + u32 shu_matype; + u32 shu_common0; + u32 shu_sref_ctrl; + u32 shu_scheduler; + u32 shu_dcm_ctrl0; + u32 shu_hmr4_dvfs_ctrl0; + u32 shu_selph_ca1; + u32 shu_selph_ca2; + u32 shu_selph_ca3; + u32 shu_selph_ca4; + u32 shu_selph_ca5; + u32 shu_selph_ca6; + u32 shu_selph_ca7; + u32 shu_selph_ca8; + u32 shu_hwset_mr2; + u32 shu_hwset_mr13; + u32 shu_hwset_vrcg; + u32 shu_actim0; + u32 shu_actim1; + u32 shu_actim2; + u32 shu_actim3; + u32 shu_actim4; + u32 shu_actim5; + u32 shu_actim6; + u32 shu_actim_xrt; + u32 shu_ac_time_05t; + u32 shu_ac_derating0; + u32 shu_ac_derating1; + u32 shu_ac_derating_05t; + u32 shu_actiming_conf; + u32 shu_ckectrl; + u32 shu_selph_dqs0; + u32 shu_selph_dqs1; + u32 shu_wodt; + u32 shu_tx_set0; + u32 shu_rx_cg_set0; + u32 shu_dqsosc_set0; + u32 shu_dqsoscr; + u32 shu_tx_rankctl; + u32 shu_zq_set0; + u32 shu_conf0; + u32 shu_misc; + u32 shu_new_xrw2w_ctrl; + u32 shu_aphy_tx_picg_ctrl; + u32 shu_freq_ratio_set0; + u32 shu_freq_ratio_set1; + u32 shu_freq_ratio_set2; + u32 shureg_rsv; + u32 shu_wckctrl; + u32 shu_wckctrl_1; + u32 rsvd_28[2]; + u32 shu_rx_set0; + u32 shu_ref0; + u32 rsvd_29[2]; + u32 shu_lp5_cmd; + u32 shu_lp5_sact; + u32 shu_actim7; +}; + +struct emi_regs { + u32 cona; + u32 conp; + u32 conb; + u32 conq; + u32 conc; + u32 conr; + u32 cond; + u32 conp_2nd; + u32 cone; + u32 conq_2nd; + u32 conf; + u32 conr_2nd; + u32 cong; + u32 conb_3rd; + u32 conh; + u32 conh_2nd; + u32 coni; + u32 conb_4th; + u32 conj; + u32 conb_5th; + u32 conk; + u32 conb_6th; + u32 rsvd_0[1]; + u32 conb_7th; + u32 conm; + u32 conb_8th; + u32 conn; + u32 conc_3rd; + u32 cono; + u32 conc_4th; + u32 mdct; + u32 mdct_2nd; + u32 rsvd_1[1]; + u32 conc_5th; + u32 rsvd_2[1]; + u32 conc_6th; + u32 rsvd_3[1]; + u32 conc_7th; + u32 rsvd_4[1]; + u32 conc_8th; + u32 rsvd_5[9]; + u32 cong_3rd; + u32 cong_4th; + u32 cong_5th; + u32 iocl; + u32 iocl_2nd; + u32 iocm; + u32 iocm_2nd; + u32 rsvd_6[1]; + u32 cong_6th; + u32 testb; + u32 rsvd_7[1]; + u32 testc; + u32 cong_7th; + u32 testd; + u32 rsvd_8[1]; + u32 arba; + u32 rsvd_9[1]; + u32 arbb; + u32 rsvd_10[1]; + u32 arbc; + u32 rsvd_11[1]; + u32 arbd; + u32 rsvd_12[1]; + u32 arbe; + u32 rsvd_13[1]; + u32 arbf; + u32 cong_8th; + u32 arbg; + u32 rsvd_14[1]; + u32 arbh; + u32 conp_3rd; + u32 arbi; + u32 arbi_2nd; + u32 rsvd_15[1]; + u32 arbj_2nd; + u32 arbk; + u32 arbk_2nd; + u32 slct; + u32 rsvd_16[1]; + u32 mpud0_st; + u32 mpud1_st; + u32 mpud2_st; + u32 mpud3_st; + u32 mpud4_st; + u32 mpud5_st; + u32 mpud6_st; + u32 mpud7_st; + u32 mpud8_st; + u32 mpud9_st; + u32 mpud10_st; + u32 mpud11_st; + u32 mpud12_st; + u32 mpud13_st; + u32 mpud14_st; + u32 mpud15_st; + u32 mpud16_st; + u32 mpud17_st; + u32 mpud18_st; + u32 mpud19_st; + u32 mpud20_st; + u32 mpud21_st; + u32 mpud22_st; + u32 mpud23_st; + u32 mpud24_st; + u32 mpud25_st; + u32 mpud26_st; + u32 mpud27_st; + u32 mpud28_st; + u32 mpud29_st; + u32 mpud30_st; + u32 mpud31_st; + u32 conp_4th; + u32 conp_5th; + u32 conp_6th; + u32 rsvd_17[1]; + u32 mpus; + u32 conp_8th; + u32 mput; + u32 mput_2nd; + u32 d0_st2; + u32 d1_st2; + u32 d2_st2; + u32 d3_st2; + u32 d4_st2; + u32 d5_st2; + u32 d6_st2; + u32 d7_st2; + u32 d8_st2; + u32 d9_st2; + u32 d10_st2; + u32 d11_st2; + u32 d12_st2; + u32 d13_st2; + u32 d14_st2; + u32 d15_st2; + u32 d16_st2; + u32 d17_st2; + u32 d18_st2; + u32 d19_st2; + u32 d20_st2; + u32 d21_st2; + u32 d22_st2; + u32 d23_st2; + u32 d24_st2; + u32 d25_st2; + u32 d26_st2; + u32 d27_st2; + u32 d28_st2; + u32 d29_st2; + u32 d30_st2; + u32 d31_st2; + u32 rsvd_18[33]; + u32 prtcl_m0_cyc; + u32 rsvd_19[1]; + u32 prtcl_m0_ctl; + u32 rsvd_20[1]; + u32 prtcl_m0_msk; + u32 rsvd_21[13]; + u32 prtcl_m1_cyc; + u32 rsvd_22[1]; + u32 prtcl_m1_ctl; + u32 rsvd_23[1]; + u32 prtcl_m1_msk; + u32 rsvd_24[13]; + u32 prtcl_m2_cyc; + u32 rsvd_25[1]; + u32 prtcl_m2_ctl; + u32 rsvd_26[1]; + u32 prtcl_m2_msk; + u32 rsvd_27[12]; + u32 prtcl_m3_cyc; + u32 prtcl_m3_ctl; + u32 prtcl_m3_msk; + u32 rsvd_28[6]; + u32 prtcl_m4_cyc; + u32 bmen; + u32 bstp; + u32 bcnt; + u32 prtcl_m4_ctl; + u32 tact; + u32 prtcl_m4_msk; + u32 tsct; + u32 rsvd_29[1]; + u32 wact; + u32 rsvd_30[1]; + u32 wsct; + u32 rsvd_31[1]; + u32 bact; + u32 rsvd_32[1]; + u32 bsct; + u32 rsvd_33[1]; + u32 msel; + u32 rsvd_34[1]; + u32 tsct2; + u32 prtcl_m5_cyc; + u32 tsct3; + u32 prtcl_m5_ctl; + u32 wsct2; + u32 prtcl_m5_msk; + u32 wsct3; + u32 wsct4; + u32 msel2; + u32 rsvd_35[1]; + u32 msel3; + u32 rsvd_36[1]; + u32 msel4; + u32 rsvd_37[1]; + u32 msel5; + u32 rsvd_38[1]; + u32 msel6; + u32 rsvd_39[1]; + u32 msel7; + u32 rsvd_40[1]; + u32 msel8; + u32 prtcl_m6_cyc; + u32 msel9; + u32 prtcl_m6_ctl; + u32 msel10; + u32 prtcl_m6_msk; + u32 bmid0; + u32 bmid1; + u32 bmid2; + u32 bmid3; + u32 bmid4; + u32 bmid5; + u32 bmid6; + u32 bmid7; + u32 bmid8; + u32 bmid9; + u32 bmid10; + u32 rsvd_41[1]; + u32 bmen1; + u32 rsvd_42[1]; + u32 bmen2; + u32 rsvd_43[3]; + u32 bmrw0; + u32 bmrw1; + u32 ttype1; + u32 rsvd_44[1]; + u32 ttype2; + u32 prtcl_m7_cyc; + u32 ttype3; + u32 prtcl_m7_ctl; + u32 ttype4; + u32 prtcl_m7_msk; + u32 ttype5; + u32 rsvd_45[1]; + u32 ttype6; + u32 rsvd_46[1]; + u32 ttype7; + u32 rsvd_47[1]; + u32 ttype8; + u32 rsvd_48[1]; + u32 ttype9; + u32 rsvd_49[1]; + u32 ttype10; + u32 rsvd_50[1]; + u32 ttype11; + u32 rsvd_51[1]; + u32 ttype12; + u32 rsvd_52[1]; + u32 ttype13; + u32 rsvd_53[1]; + u32 ttype14; + u32 rsvd_54[1]; + u32 ttype15; + u32 rsvd_55[1]; + u32 ttype16; + u32 rsvd_56[1]; + u32 ttype17; + u32 rsvd_57[1]; + u32 ttype18; + u32 rsvd_58[1]; + u32 ttype19; + u32 rsvd_59[1]; + u32 ttype20; + u32 rsvd_60[1]; + u32 ttype21; + u32 rsvd_61[3]; + u32 bwct0; + u32 bwct1; + u32 bwct2; + u32 bwct3; + u32 bwct4; + u32 bwst0; + u32 bwst1; + u32 rsvd_62[1]; + u32 ex_con; + u32 ex_st0; + u32 ex_st1; + u32 ex_st2; + u32 wp_adr; + u32 wp_adr_2nd; + u32 wp_ctrl; + u32 rsvd_63[1]; + u32 chker; + u32 chker_type; + u32 chker_adr; + u32 chker_adr_2nd; + u32 rsvd_64[7]; + u32 thro_slv_con0; + u32 rsvd_65[1]; + u32 thro_slv_con1; + u32 mxto0; + u32 mxto1; + u32 rsvd_66[4]; + u32 conq_3rd; + u32 conq_4th; + u32 conq_5th; + u32 conq_6th; + u32 rsvd_67[4]; + u32 conq_7th; + u32 conq_8th; + u32 conr_3rd; + u32 conr_4th; + u32 rsvd_68[9]; + u32 conr_5th; + u32 rsvd_69[2]; + u32 bwct0_2nd; + u32 rsvd_70[25]; + u32 conr_6th; + u32 conr_7th; + u32 shf0; + u32 dvfs_shf_con; + u32 shf1; + u32 clua; + u32 rsvd_71[10]; + u32 conr_8th; + u32 rsvd_72[1]; + u32 ltct0_2nd; + u32 ltct1_2nd; + u32 ltct2_2nd; + u32 ltct3_2nd; + u32 rsvd_73[4]; + u32 bwct0_3rd; + u32 bwlmte_8th; + u32 rsvd_74[1]; + u32 bwlmtf_8th; + u32 bwct0_4th; + u32 bwlmtg_8th; + u32 rsvd_75[1]; + u32 bwlmth_8th; + u32 rsvd_76[5]; + u32 chn_hash0; + u32 rsvd_77[2]; + u32 bwct0_5th; + u32 rsvd_78[5]; + u32 bwct0_6th; + u32 rsvd_79[11]; + u32 snst; + u32 rsvd_80[1]; + u32 slva; + u32 rsvd_81[7]; + u32 thro_os0; + u32 thro_os1; + u32 thro_os2; + u32 thro_os3; + u32 thro_ctrl0; + u32 thro_prd0; + u32 thro_prd1; + u32 thro_lat0; + u32 thro_lat1; + u32 thro_lat2; + u32 thro_lat3; + u32 thro_lat4; + u32 thro_lat5; + u32 thro_lat6; + u32 thro_ctrl1; + u32 thro_prd2; + u32 rsvd_82[5]; + u32 thro_lat7; + u32 thro_lat8; + u32 thro_prd3; + u32 rsvd_83[4]; + u32 bwlmta; + u32 bwlmtb; + u32 rsvd_84[2]; + u32 bwlmte; + u32 bwlmtf; + u32 rsvd_85[2]; + u32 conb_2nd; + u32 conc_2nd; + u32 cong_2nd; + u32 rsvd_86[1]; + u32 thro_lat9; + u32 thro_lat10; + u32 thro_lat11; + u32 thro_lat12; + u32 thro_lat13; + u32 thro_lat14; + u32 rsvd_87[2]; + u32 bwlmte_2nd; + u32 bwlmtf_2nd; + u32 bwlmtg_2nd; + u32 rsvd_88[13]; + u32 bwlmte_4th; + u32 bwlmtf_4th; + u32 rsvd_89[2]; + u32 bwlmte_5th; + u32 bwlmtf_5th; + u32 bwlmtg_5th; + u32 rsvd_90[7]; + u32 bwlmtg_7th; + u32 rsvd_91[12]; + u32 axi_bist_adr0; + u32 axi_bist_adr1; + u32 axi_bist_adr2; + u32 rsvd_92[22]; + u32 thro_lat27; + u32 thro_lat28; + u32 thro_lat29; + u32 thro_lat30; + u32 rsvd_93[64]; + u32 thro_lat31; + u32 thro_lat32; + u32 thro_lat33; + u32 thro_lat34; + u32 thro_lat35; + u32 thro_lat36; + u32 rsvd_94[4]; + u32 thro_lat41; + u32 thro_lat42; + u32 rsvd_95[12]; + u32 thro_lat55; + u32 thro_lat56; + u32 rsvd_96[12]; + u32 thro_lat69; + u32 thro_lat70; + u32 rsvd_97[12]; + u32 thro_lat83; + u32 thro_lat84; + u32 rsvd_98[12]; + u32 thro_lat97; + u32 thro_lat98; + u32 rsvd_99[12]; + u32 thro_lat111; + u32 thro_lat112; + u32 rsvd_100[1]; + u32 thro_prd5; + u32 rsvd_101[12]; + u32 thro_lat113; + u32 thro_lat114; + u32 thro_lat115; + u32 thro_lat116; + u32 thro_lat117; + u32 thro_lat118; + u32 thro_lat119; + u32 thro_lat120; + u32 rsvd_102[4]; + u32 thro_lat125; + u32 thro_lat126; + u32 rsvd_103[16]; + u32 thro_lat139; + u32 thro_lat140; + u32 rsvd_104[1]; + u32 qos_mdr_be0a; + u32 rsvd_105[1]; + u32 qos_mdr_be1a; + u32 rsvd_106[1]; + u32 qos_mdr_shf0; + u32 qos_mdr_shf1; + u32 qos_mdw_be0a; + u32 rsvd_107[1]; + u32 qos_mdw_be1a; + u32 rsvd_108[1]; + u32 qos_mdw_shf0; + u32 qos_mdw_shf1; + u32 qos_apr_be0a; + u32 rsvd_109[1]; + u32 qos_apr_be1a; + u32 rsvd_110[1]; + u32 qos_apr_shf0; + u32 qos_apw_be0a; + u32 rsvd_111[1]; + u32 qos_apw_be1a; + u32 rsvd_112[1]; + u32 qos_mmr_be0a; + u32 rsvd_113[1]; + u32 qos_mmr_be1a; + u32 qos_mmr_be1b; + u32 qos_mmr_be2a; + u32 qos_mmr_be2b; + u32 qos_mmr_shf0; + u32 qos_mmr_shf1; + u32 qos_mmw_be0a; + u32 rsvd_114[1]; + u32 qos_mmw_be1a; + u32 qos_mmw_be1b; + u32 qos_mmw_be2a; + u32 qos_mmw_be2b; + u32 qos_mmw_shf0; + u32 qos_mmw_shf1; + u32 qos_mdhwr_be0a; + u32 rsvd_115[1]; + u32 qos_mdhwr_be1a; + u32 rsvd_116[1]; + u32 qos_mdhwr_shf0; + u32 qos_mdhww_be0a; + u32 rsvd_117[1]; + u32 qos_mdhww_be1a; + u32 rsvd_118[1]; + u32 qos_gpur_be0a; + u32 rsvd_119[1]; + u32 qos_gpur_be1a; + u32 rsvd_120[1]; + u32 qos_gpur_shf0; + u32 qos_gpuw_be0a; + u32 rsvd_121[1]; + u32 qos_gpuw_be1a; + u32 rsvd_122[1]; + u32 qos_arbr_be0a; + u32 rsvd_123[1]; + u32 qos_arbr_be1a; + u32 rsvd_124[1]; + u32 qos_arbr_shf0; + u32 qos_ctrl1; + u32 rsvd_125[3]; + u32 ext_lt_con1_1st; + u32 ext_lt_con2_1st; + u32 ext_lt_con3_1st; + u32 rsvd_126[1]; + u32 ext_lt_con1_2nd; + u32 ext_lt_con2_2nd; + u32 ext_lt_con3_2nd; + u32 rsvd_127[1]; + u32 ext_lt_con1_3rd; + u32 ext_lt_con2_3rd; + u32 ext_lt_con3_3rd; + u32 rsvd_128[1]; + u32 ext_lt_con1_4th; + u32 ext_lt_con2_4th; + u32 ext_lt_con3_4th; +}; + +struct phy_ao_rk { + u32 shu_r0_b0_txdly0; + u32 shu_r0_b0_txdly1; + u32 shu_r0_b0_txdly2; + u32 shu_r0_b0_txdly3; + u32 shu_r0_b0_txdly4; + u32 shu_r0_b0_rxdly0; + u32 shu_r0_b0_rxdly1; + u32 shu_r0_b0_rxdly2; + u32 shu_r0_b0_rxdly3; + u32 shu_r0_b0_rxdly4; + u32 shu_r0_b0_rxdly5; + u32 shu_rk_b0_dq1; + u32 shu_b0_phy_vref_sel; + u32 shu_r0_b0_dq0; + u32 shu_r0_b0_ini_uipi; + u32 shu_r0_b0_next_ini_uipi; + u32 shu_dqsien_mck_ui_dly; + u32 shu_rk_b0_dqsien_pi_dly; + u32 shu_rk_b0_rodten_mck_ui_dly; + u32 shu_rk_b0_dq0; + u32 rsvd_0[4]; + u32 shu_rk_b0_bist_ctrl; + u32 rsvd_1[7]; +}; + +struct phy_ao_shu_byte { + struct phy_ao_rk rk[RANK_MAX]; + u32 shu_b0_dq0; + u32 shu_b0_dq3; + u32 shu_b0_dq4; + u32 shu_b0_dq5; + u32 shu_b0_dq6; + u32 shu_b0_dq1; + u32 shu_b0_dq2; + u32 shu_b0_dq10; + u32 shu_b0_dq11; + u32 shu_b0_dq7; + u32 shu_b0_dq8; + u32 shu_b0_dq9; + u32 shu_b0_dq12; + u32 shu_b0_dll0; + u32 shu_b0_dll1; + u32 shu_b0_dll2; + u32 shu_b0_rank_selph_ui_dly; + u32 shu_b0_dll_arpi2; + u32 shu_b0_dll_arpi3; + u32 shu_b0_txduty; + u32 shu_b0_vref; + u32 shu_b0_dq13; + u32 shu_b0_dq14; + u32 b0_shu_midpi_ctrl; + u32 rsvd_16[8]; +}; + +struct phy_ao_rx_dvs_byte { + struct { + u32 rk_b0_rxdvs0; + u32 rk_b0_rxdvs1; + u32 rk_b0_rxdvs2; + u32 rk_b0_rxdvs3; + u32 rk_b0_rxdvs4; + u32 rsvd[27]; + } rk[RANK_MAX]; + u32 b0_lp_ctrl0; + u32 b0_rxdvs0; + u32 b0_rxdvs1; + u32 b0_dll_arpi0; + u32 b0_dll_arpi1; + u32 b0_dll_arpi4; + u32 b0_dll_arpi5; + u32 b0_dq2; + u32 b0_dq3; + u32 b0_dq4; + u32 b0_dq5; + u32 b0_dq6; + u32 b0_dq7; + u32 b0_dq8; + u32 b0_dq9; + u32 b0_dq10; + u32 b0_dq11; + u32 b0_phy2; + u32 b0_phy3; + u32 b0_tx_mck; + u32 rsvd_3[12]; +}; + +struct phy_ao_ca_rk { + u32 shu_r0_ca_txdly0; + u32 shu_r0_ca_txdly1; + u32 shu_r0_ca_txdly2; + u32 shu_r0_ca_txdly3; + u32 shu_r0_ca_txdly4; + u32 shu_r0_ca_rxdly0; + u32 shu_r0_ca_rxdly1; + u32 shu_r0_ca_rxdly2; + u32 shu_r0_ca_rxdly6; + u32 shu_r0_ca_rxdly3; + u32 shu_r0_ca_rxdly4; + u32 shu_r0_ca_rxdly5; + u32 shu_r0_ca_rxdly7; + u32 shu_r0_ca_cmd0; + u32 shu_r0_ca_ini_uipi; + u32 shu_r0_ca_next_ini_uipi; + u32 shu_rk_ca_dqsien_mck_ui_dly; + u32 shu_rk_ca_dqsien_pi_dly; + u32 shu_rk_ca_rodten_mck_ui_dly; + u32 shu_rk_ca_cmd0; + u32 shu_rk_ca_cmd1; + u32 shu_ca_phy_vref_sel; + u32 rsvd[10]; +}; + +struct phy_ao_misc_rk { + u32 misc_shu_rk_dqsctl; + u32 misc_shu_rk_dqsien_picg_ctrl; + u32 misc_shu_rk_dqscal; + u32 rsvd[29]; +}; + +struct ddrphy_ao_regs { + u32 phypll0; + u32 phypll1; + u32 phypll2; + u32 rsvd_0[5]; + u32 clrpll0; + u32 rsvd_1[15]; + struct phy_ao_rx_dvs_byte dvs_b[BYTE_NUM]; + u32 rk_ca_rxdvs0; + u32 rk_ca_rxdvs1; + u32 rk_ca_rxdvs2; + u32 rk_ca_rxdvs3; + u32 rk_ca_rxdvs4; + u32 rsvd_6[59]; + u32 ca_lp_ctrl0; + u32 ca_rxdvs0; + u32 ca_rxdvs1; + u32 ca_dll_arpi0; + u32 ca_dll_arpi1; + u32 ca_dll_arpi4; + u32 ca_dll_arpi5; + u32 ca_cmd2; + u32 ca_cmd3; + u32 ca_cmd4; + u32 ca_cmd5; + u32 ca_cmd6; + u32 ca_cmd7; + u32 ca_cmd8; + u32 ca_cmd9; + u32 ca_cmd10; + u32 ca_cmd11; + u32 ca_phy2; + u32 ca_phy3; + u32 ca_tx_mck; + u32 rsvd_7[12]; + u32 misc_stbcal; + u32 misc_stbcal1; + u32 misc_stbcal2; + u32 misc_cg_ctrl0; + u32 misc_cg_ctrl1; + u32 misc_cg_ctrl2; + u32 misc_cg_ctrl3; + u32 rsvd_8[1]; + u32 misc_cg_ctrl5; + u32 misc_cg_ctrl7; + u32 misc_cg_ctrl9; + u32 misc_cg_ctrl10; + u32 misc_dvfsctl; + u32 misc_dvfsctl2; + u32 misc_dvfsctl3; + u32 misc_ckmux_sel; + u32 misc_clk_ctrl; + u32 misc_dqsg_retry1; + u32 misc_rdsel_track; + u32 misc_pre_tdqsck1; + u32 misc_cdc_ctrl; + u32 misc_lp_ctrl; + u32 misc_rg_dfs_ctrl; + u32 misc_ddr_reserve; + u32 misc_imp_ctrl1; + u32 misc_impcal; + u32 misc_impcal1; + u32 misc_impedamce_ctrl1; + u32 misc_impedamce_ctrl2; + u32 misc_impedamce_ctrl3; + u32 misc_impedamce_ctrl4; + u32 misc_peripher_ctrl2; + u32 misc_apb; + u32 misc_extlb0; + u32 misc_extlb1; + u32 misc_extlb2; + u32 misc_extlb3; + u32 misc_extlb4; + u32 misc_extlb5; + u32 misc_extlb6; + u32 misc_extlb7; + u32 misc_extlb8; + u32 misc_extlb9; + u32 misc_extlb10; + u32 misc_extlb11; + u32 misc_extlb12; + u32 misc_extlb13; + u32 misc_extlb14; + u32 misc_extlb15; + u32 misc_extlb16; + u32 misc_extlb17; + u32 misc_extlb18; + u32 misc_extlb19; + u32 misc_extlb20; + u32 misc_extlb21; + u32 misc_extlb22; + u32 misc_extlb23; + u32 misc_extlb_rx0; + u32 misc_extlb_rx1; + u32 misc_extlb_rx2; + u32 misc_extlb_rx3; + u32 misc_extlb_rx4; + u32 misc_extlb_rx5; + u32 misc_extlb_rx6; + u32 misc_extlb_rx7; + u32 misc_extlb_rx8; + u32 misc_extlb_rx9; + u32 misc_extlb_rx10; + u32 misc_extlb_rx11; + u32 misc_extlb_rx12; + u32 misc_extlb_rx13; + u32 misc_extlb_rx14; + u32 misc_extlb_rx15; + u32 misc_extlb_rx16; + u32 misc_extlb_rx17; + u32 misc_extlb_rx18; + u32 misc_extlb_rx19; + u32 misc_extlb_rx20; + u32 misc_sram_dma0; + u32 misc_sram_dma1; + u32 misc_sram_dma2; + u32 misc_dutyscan1; + u32 misc_miock_jit_mtr; + u32 misc_jmeter; + u32 misc_dvfs_emi_clk; + u32 misc_rx_in_gate_en_ctrl; + u32 misc_rx_in_buff_en_ctrl; + u32 misc_ctrl0; + u32 misc_ctrl1; + u32 misc_ctrl2; + u32 misc_ctrl3; + u32 misc_ctrl4; + u32 misc_ctrl5; + u32 misc_ctrl6; + u32 misc_vref_ctrl; + u32 misc_shu_opt; + u32 misc_rxdvs0; + u32 misc_rxdvs2; + u32 misc_dqsien_autok_cfg0; + u32 misc_dline_mon_cfg; + u32 misc_rx_autok_cfg0; + u32 misc_rx_autok_cfg1; + u32 rsvd_9[2]; + u32 misc_dbg_irq_ctrl0; + u32 misc_dbg_irq_ctrl1; + u32 misc_dbg_irq_ctrl2; + u32 misc_dbg_irq_ctrl3; + u32 misc_dbg_irq_ctrl4; + u32 misc_dbg_irq_ctrl5; + u32 misc_dbg_irq_ctrl6; + u32 misc_dbg_irq_ctrl7; + u32 misc_dbg_irq_ctrl8; + u32 misc_dbg_irq_ctrl9; + u32 rsvd_10[2]; + u32 misc_dq_se_pinmux_ctrl0; + u32 misc_dq_se_pinmux_ctrl1; + u32 rsvd_11[2]; + u32 misc_bist_lpbk_ctrl0; + u32 rsvd_12[15]; + u32 shu_phypll0; + u32 shu_phypll1; + u32 shu_phypll2; + u32 shu_phypll3; + u32 shu_phypll4; + u32 shu_phypll5; + u32 shu_phypll6; + u32 shu_phypll7; + u32 shu_clrpll0; + u32 shu_clrpll1; + u32 shu_clrpll2; + u32 shu_clrpll3; + u32 shu_clrpll4; + u32 shu_clrpll5; + u32 shu_clrpll6; + u32 shu_clrpll7; + u32 shu_pll0; + u32 shu_pll1; + u32 shu_pll2; + u32 rsvd_13[5]; + struct phy_ao_shu_byte byte[BYTE_NUM]; + struct phy_ao_ca_rk ca_rk[RANK_MAX]; + u32 shu_ca_cmd0; + u32 shu_ca_cmd3; + u32 shu_ca_cmd4; + u32 shu_ca_cmd5; + u32 shu_ca_cmd6; + u32 shu_ca_cmd1; + u32 shu_ca_cmd2; + u32 shu_ca_cmd10; + u32 shu_ca_cmd11; + u32 shu_ca_cmd7; + u32 shu_ca_cmd8; + u32 shu_ca_cmd9; + u32 shu_ca_cmd12; + u32 shu_ca_dll0; + u32 shu_ca_dll1; + u32 shu_ca_dll2; + u32 shu_ca_rank_selph_ui_dly; + u32 shu_ca_dll_arpi2; + u32 shu_ca_dll_arpi3; + u32 shu_ca_txduty; + u32 shu_ca_vref; + u32 shu_ca_cmd13; + u32 shu_ca_cmd14; + u32 ca_shu_midpi_ctrl; + u32 rsvd_21[8]; + struct phy_ao_misc_rk misc_rk[RANK_MAX]; + u32 misc_shu_drving7; + u32 misc_shu_drving8; + u32 misc_shu_impedamce_offset1; + u32 misc_shu_impedamce_offset2; + u32 misc_shu_impedamce_offset3; + u32 misc_shu_impedamce_offset4; + u32 misc_shu_impedamce_offset5; + u32 misc_shu_impedamce_offset6; + u32 misc_shu_impedamce_offset7; + u32 misc_shu_impedamce_offset8; + u32 misc_shu_impedamce_offset9; + u32 misc_shu_impedamce_upd_dis1; + u32 shu_misc_sw_impcal; + u32 misc_shu_stbcal; + u32 misc_shu_stbcal1; + u32 misc_shu_dvfsdll; + u32 misc_shu_rankctl; + u32 misc_shu_phy_rx_ctrl; + u32 misc_shu_odtctrl; + u32 misc_shu_rodtenstb; + u32 misc_shu_rodtenstb1; + u32 misc_shu_dqsg_retry1; + u32 misc_shu_rdat; + u32 misc_shu_rdat1; + u32 shu_misc_clk_ctrl0; + u32 shu_misc_impcal1; + u32 shu_misc_drving1; + u32 shu_misc_drving2; + u32 shu_misc_drving3; + u32 shu_misc_drving4; + u32 shu_misc_drving5; + u32 shu_misc_drving6; + u32 shu_misc_duty_scan; + u32 shu_misc_dma; + u32 shu_misc_rvref; + u32 shu_misc_rx_pipe_ctrl; + u32 shu_misc_tx_pipe_ctrl; + u32 shu_misc_emi_ctrl; + u32 shu_misc_rank_sel_stb; + u32 shu_misc_rdsel_track; + u32 shu_misc_pre_tdqsck; + u32 shu_misc_async_fifo_ctrl; + u32 misc_shu_rx_selph_mode; + u32 misc_shu_rank_sel_lat; + u32 misc_shu_dline_mon_ctrl; + u32 misc_shu_dline_mon_cnt; + u32 misc_shu_midpi_ctrl; + u32 rsvd_23[1]; + u32 misc_shu_rx_cg_ctrl; + u32 misc_shu_cg_ctrl0; + u32 rsvd_24[470]; + u32 misc_stberr_all; + u32 misc_stberr_rk0_r; + u32 misc_stberr_rk0_f; + u32 misc_stberr_rk1_r; + u32 misc_stberr_rk1_f; + u32 rsvd_25[3]; + u32 misc_ddr_reserve_state; + u32 rsvd_26[3]; + u32 misc_irq_status0; + u32 misc_irq_status1; + u32 misc_irq_status2; + u32 rsvd_27[49]; + u32 misc_dbg_db_message0; + u32 misc_dbg_db_message1; + u32 misc_dbg_db_message2; + u32 misc_dbg_db_message3; + u32 misc_dbg_db_message4; + u32 misc_dbg_db_message5; + u32 misc_dbg_db_message6; + u32 misc_dbg_db_message7; +}; + +struct emi_chn_regs { + u32 cona; + u32 rsvd_0[1]; + u32 conb; + u32 rsvd_1[1]; + u32 conc; + u32 rsvd_2[1]; + u32 mdct; + u32 rsvd_3[1]; + u32 ebg_con; + u32 rsvd_4[9]; + u32 testb; + u32 rsvd_5[1]; + u32 testc; + u32 rsvd_6[1]; + u32 testd; + u32 rsvd_7[9]; + u32 md_pre_mask; + u32 rsvd_8[1]; + u32 md_pre_mask_shf; + u32 rsvd_9[1]; + u32 ap_early_cke; + u32 rsvd_10[1]; + u32 dqfr; + u32 rsvd_11[41]; + u32 arbi; + u32 arbi_2nd; + u32 arbj; + u32 arbj_2nd; + u32 arbk; + u32 arbk_2nd; + u32 slct; + u32 arb_rff; + u32 rsvd_12[3]; + u32 drs_mon0; + u32 drs_mon1; + u32 rsvd_13[15]; + u32 rkarb0; + u32 rkarb1; + u32 rkarb2; + u32 rsvd_14[144]; + u32 eco3; + u32 rsvd_15[1]; + u32 md_pre_mask_shf0; + u32 md_pre_mask_shf1; + u32 qos_mdr_shf0; + u32 rsvd_16[192]; + u32 shf0; +}; + +struct emi_mpu_regs { + u32 mpu_ctrl; + u32 rsvd[511]; + u32 mpu_ctrl_d[16]; +}; + +struct infra_ao_mem_regs { + u32 rsvd_0[10]; + u32 emi_dcm_cfg0; + u32 emi_dcm_cfg1; + u32 emi_dcm_cfg2; + u32 emi_dcm_cfg3; + u32 top_ck_anchor_cfg; + u32 rsvd_2[5]; + u32 emi_disph_cfg; + u32 rsvd_3[43]; + u32 emi_idle_bit_en_0; + u32 emi_idle_bit_en_1; + u32 emi_idle_bit_en_2; + u32 emi_idle_bit_en_3; + u32 emi_m0m1_idle_bit_en_0; + u32 emi_m0m1_idle_bit_en_1; + u32 emi_m0m1_idle_bit_en_2; + u32 emi_m0m1_idle_bit_en_3; + u32 emi_m2m5_idle_bit_en_0; + u32 emi_m2m5_idle_bit_en_1; + u32 emi_m2m5_idle_bit_en_2; + u32 emi_m2m5_idle_bit_en_3; + u32 emi_m3_idle_bit_en_0; + u32 emi_m3_idle_bit_en_1; + u32 emi_m3_idle_bit_en_2; + u32 emi_m3_idle_bit_en_3; + u32 emi_m4_idle_bit_en_0; + u32 emi_m4_idle_bit_en_1; + u32 emi_m4_idle_bit_en_2; + u32 emi_m4_idle_bit_en_3; + u32 emi_m6m7_idle_bit_en_0; + u32 emi_m6m7_idle_bit_en_1; + u32 emi_m6m7_idle_bit_en_2; + u32 emi_m6m7_idle_bit_en_3; + u32 emi_sram_idle_bit_en_0; + u32 emi_sram_idle_bit_en_1; + u32 emi_sram_idle_bit_en_2; + u32 emi_sram_idle_bit_en_3; +}; + +struct dramc_channel_regs { + union { + struct dramc_ao_regs ao; + uint8_t raw_ao_regs[0x4000]; + }; + union { + struct dramc_nao_regs nao; + uint8_t raw_nao_regs[0x1000]; + }; + union { + struct emi_chn_regs emi_chn; + uint8_t raw_emi_regs[0x1000]; + }; + union { + struct ddrphy_nao_regs phy_nao; + uint8_t raw_ddrphy_nao_regs[0x2000]; + }; + union { + struct ddrphy_ao_regs phy_ao; + uint8_t raw_ddrphy_ao_regs[0x8000]; + }; +}; + +static struct dramc_channel_regs *const ch = (void *)DRAMC_CHA_AO_BASE; +#endif /* __SOC_MEDIATEK_MT8192_DRAMC_REGISTER_H__ */ diff --git a/src/soc/mediatek/mt8192/include/soc/dramc_register_bits_def.h b/src/soc/mediatek/mt8192/include/soc/dramc_register_bits_def.h new file mode 100644 index 0000000..15d138f --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/dramc_register_bits_def.h @@ -0,0 +1,2837 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8192_DRAMC_MACRO_DEF_H__ +#define __SOC_MEDIATEK_MT8192_DRAMC_MACRO_DEF_H__ + +/* DDRPHY_REG_PHYPLL1 */ +DEFINE_BIT(PHYPLL1_RG_RPHYPLL_TSTOP_EN, 0) +DEFINE_BIT(PHYPLL1_RG_RPHYPLL_TST_EN, 4) + +/* DDRPHY_REG_SHU_PHYPLL0 */ +DEFINE_BITFIELD(SHU_PHYPLL0_RG_RPHYPLL_RESERVED, 15, 0) +DEFINE_BITFIELD(SHU_PHYPLL0_RG_RPHYPLL_ICHP, 25, 24) + +/* DDRPHY_REG_SHU_CLRPLL0 */ +DEFINE_BITFIELD(SHU_CLRPLL0_RG_RCLRPLL_RESERVED, 15, 0) +DEFINE_BITFIELD(SHU_CLRPLL0_RG_RCLRPLL_ICHP, 25, 24) + +/* DDRPHY_REG_SHU_PHYPLL2 */ +DEFINE_BITFIELD(SHU_PHYPLL2_RG_RPHYPLL_POSDIV, 2, 0) +DEFINE_BITFIELD(SHU_PHYPLL2_RG_RPHYPLL_PREDIV, 19, 18) + +/* DDRPHY_REG_SHU_CLRPLL2 */ +DEFINE_BITFIELD(SHU_CLRPLL2_RG_RCLRPLL_POSDIV, 2, 0) +DEFINE_BITFIELD(SHU_CLRPLL2_RG_RCLRPLL_PREDIV, 19, 18) + +/* DDRPHY_REG_SHU_PHYPLL1 */ +DEFINE_BIT(SHU_PHYPLL1_RG_RPHYPLL_SDM_FRA_EN, 0) +DEFINE_BIT(SHU_PHYPLL1_RG_RPHYPLL_SDM_PCW_CHG, 1) +DEFINE_BITFIELD(SHU_PHYPLL1_RG_RPHYPLL_SDM_PCW, 31, 16) + +/* DDRPHY_REG_SHU_CLRPLL1 */ +DEFINE_BIT(SHU_CLRPLL1_RG_RCLRPLL_SDM_FRA_EN, 0) +DEFINE_BIT(SHU_CLRPLL1_RG_RCLRPLL_SDM_PCW_CHG, 1) +DEFINE_BITFIELD(SHU_CLRPLL1_RG_RCLRPLL_SDM_PCW, 31, 16) + +/* DDRPHY_REG_SHU_PLL1 */ +DEFINE_BIT(SHU_PLL1_RG_RPHYPLLGP_CK_SEL, 0) +DEFINE_BIT(SHU_PLL1_R_SHU_AUTO_PLL_MUX, 4) + +/* DDRPHY_REG_SHU_PHYPLL3 */ +DEFINE_BIT(SHU_PHYPLL3_RG_RPHYPLL_DIV_CK_SEL, 0) +DEFINE_BIT(SHU_PHYPLL3_RG_RPHYPLL_FBKSEL, 6) +DEFINE_BITFIELD(SHU_PHYPLL3_RG_RPHYPLL_RST_DLY, 9, 8) +DEFINE_BIT(SHU_PHYPLL3_RG_RPHYPLL_LVROD_EN, 12) +DEFINE_BIT(SHU_PHYPLL3_RG_RPHYPLL_MONCK_EN, 16) + +/* DDRPHY_REG_SHU_CLRPLL3 */ +DEFINE_BIT(SHU_CLRPLL3_RG_RCLRPLL_DIV_CK_SEL, 0) +DEFINE_BIT(SHU_CLRPLL3_RG_RCLRPLL_FBKSEL, 6) +DEFINE_BITFIELD(SHU_CLRPLL3_RG_RCLRPLL_RST_DLY, 9, 8) +DEFINE_BIT(SHU_CLRPLL3_RG_RCLRPLL_LVROD_EN, 12) +DEFINE_BIT(SHU_CLRPLL3_RG_RCLRPLL_MONCK_EN, 16) + +/* DDRPHY_REG_SHU_MISC_CLK_CTRL0 */ +DEFINE_BIT(SHU_MISC_CLK_CTRL0_M_CK_OPENLOOP_MODE_SEL, 4) + +/* DDRPHY_REG_SHU_B0_DQ14 */ +DEFINE_BIT(SHU_B0_DQ14_RG_TX_ARWCK_MCKIO_SEL_B0, 2) +DEFINE_BITFIELD(SHU_B0_DQ14_RG_TX_ARDQ_SER_MODE_B0, 5, 4) +DEFINE_BIT(SHU_B0_DQ14_RG_TX_ARDQ_OE_ODTEN_CG_EN_B0, 11) +DEFINE_BITFIELD(SHU_B0_DQ14_RG_TX_ARDQ_MCKIO_SEL_B0, 23, 16) + +/* DDRPHY_REG_SHU_B1_DQ14 */ +DEFINE_BIT(SHU_B1_DQ14_RG_TX_ARWCK_MCKIO_SEL_B1, 2) +DEFINE_BITFIELD(SHU_B1_DQ14_RG_TX_ARDQ_SER_MODE_B1, 5, 4) +DEFINE_BIT(SHU_B1_DQ14_RG_TX_ARDQ_OE_ODTEN_CG_EN_B1, 11) +DEFINE_BITFIELD(SHU_B1_DQ14_RG_TX_ARDQ_MCKIO_SEL_B1, 23, 16) + +/* DDRPHY_REG_SHU_B0_DQ6 */ +DEFINE_BITFIELD(SHU_B0_DQ6_RG_ARPI_CAP_SEL_B0, 18, 12) +DEFINE_BIT(SHU_B0_DQ6_RG_ARPI_SOPEN_EN_B0, 20) +DEFINE_BIT(SHU_B0_DQ6_RG_ARPI_OPEN_EN_B0, 21) +DEFINE_BITFIELD(SHU_B0_DQ6_RG_ARPI_HYST_SEL_B0, 23, 22) +DEFINE_BIT(SHU_B0_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B0, 29) + +/* DDRPHY_REG_SHU_B1_DQ6 */ +DEFINE_BITFIELD(SHU_B1_DQ6_RG_ARPI_CAP_SEL_B1, 18, 12) +DEFINE_BIT(SHU_B1_DQ6_RG_ARPI_SOPEN_EN_B1, 20) +DEFINE_BIT(SHU_B1_DQ6_RG_ARPI_OPEN_EN_B1, 21) +DEFINE_BITFIELD(SHU_B1_DQ6_RG_ARPI_HYST_SEL_B1, 23, 22) +DEFINE_BIT(SHU_B1_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B1, 29) + +/* DDRPHY_REG_SHU_CA_CMD11 */ +DEFINE_BIT(SHU_CA_CMD11_RG_RX_ARCA_RANK_SEL_SER_EN_CA, 0) +DEFINE_BIT(SHU_CA_CMD11_RG_RX_ARCA_RANK_SEL_LAT_EN_CA, 1) +DEFINE_BIT(SHU_CA_CMD11_RG_RX_ARCA_OFFSETC_LAT_EN_CA, 2) +DEFINE_BITFIELD(SHU_CA_CMD11_RG_RX_ARCA_DES_MODE_CA, 17, 16) +DEFINE_BITFIELD(SHU_CA_CMD11_RG_RX_ARCA_BW_SEL_CA, 19, 18) + +/* DDRPHY_REG_SHU_B0_DQ11 */ +DEFINE_BIT(SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B0, 0) +DEFINE_BIT(SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B0, 1) +DEFINE_BIT(SHU_B0_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B0, 2) +DEFINE_BIT(SHU_B0_DQ11_RG_RX_ARDQ_DVS_EN_B0, 7) +DEFINE_BITFIELD(SHU_B0_DQ11_RG_RX_ARDQ_DES_MODE_B0, 17, 16) +DEFINE_BITFIELD(SHU_B0_DQ11_RG_RX_ARDQ_BW_SEL_B0, 19, 18) + +/* DDRPHY_REG_SHU_B1_DQ11 */ +DEFINE_BIT(SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B1, 0) +DEFINE_BIT(SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B1, 1) +DEFINE_BIT(SHU_B1_DQ11_RG_RX_ARDQ_OFFSETC_LAT_EN_B1, 2) +DEFINE_BIT(SHU_B1_DQ11_RG_RX_ARDQ_DVS_EN_B1, 7) +DEFINE_BITFIELD(SHU_B1_DQ11_RG_RX_ARDQ_DES_MODE_B1, 17, 16) +DEFINE_BITFIELD(SHU_B1_DQ11_RG_RX_ARDQ_BW_SEL_B1, 19, 18) + +/* DDRPHY_REG_SHU_CA_CMD14 */ +DEFINE_BITFIELD(SHU_CA_CMD14_RG_TX_ARCA_SER_MODE_CA, 5, 4) +DEFINE_BIT(SHU_CA_CMD14_RG_TX_ARCA_OE_ODTEN_CG_EN_CA, 11) +DEFINE_BITFIELD(SHU_CA_CMD14_RG_TX_ARCA_MCKIO_SEL_CA, 23, 16) + +/* DDRPHY_REG_SHU_CA_CMD6 */ +DEFINE_BITFIELD(SHU_CA_CMD6_RG_ARPI_OFFSET_DQSIEN_CA, 5, 0) +DEFINE_BITFIELD(SHU_CA_CMD6_RG_ARPI_CAP_SEL_CA, 18, 12) +DEFINE_BIT(SHU_CA_CMD6_RG_ARPI_SOPEN_EN_CA, 20) +DEFINE_BIT(SHU_CA_CMD6_RG_ARPI_OPEN_EN_CA, 21) +DEFINE_BITFIELD(SHU_CA_CMD6_RG_ARPI_HYST_SEL_CA, 23, 22) +DEFINE_BIT(SHU_CA_CMD6_RG_ARPI_SOPEN_CKGEN_EN_CA, 26) +DEFINE_BIT(SHU_CA_CMD6_RG_ARPI_SOPEN_CKGEN_DIV_CA, 27) +DEFINE_BIT(SHU_CA_CMD6_RG_RX_ARCMD_RANK_SEL_SER_MODE, 29) + +/* DDRPHY_REG_SHU_B0_DLL1 */ +DEFINE_BIT(SHU_B0_DLL1_RG_ARDLL_UDIV_EN_B0, 4) +DEFINE_BIT(SHU_B0_DLL1_RG_ARDLL_TRACKING_CA_EN_B0, 6) +DEFINE_BITFIELD(SHU_B0_DLL1_RG_ARDLL_SER_MODE_B0, 9, 8) +DEFINE_BIT(SHU_B0_DLL1_RG_ARDLL_PS_EN_B0, 10) +DEFINE_BIT(SHU_B0_DLL1_RG_ARDLL_PSJP_EN_B0, 11) +DEFINE_BIT(SHU_B0_DLL1_RG_ARDLL_PHDIV_B0, 12) +DEFINE_BIT(SHU_B0_DLL1_RG_ARDLL_PHDET_OUT_SEL_B0, 13) +DEFINE_BIT(SHU_B0_DLL1_RG_ARDLL_PHDET_IN_SWAP_B0, 14) +DEFINE_BIT(SHU_B0_DLL1_RG_ARDLL_PHDET_EN_B0, 16) +DEFINE_BITFIELD(SHU_B0_DLL1_RG_ARDLL_PGAIN_B0, 23, 20) +DEFINE_BIT(SHU_B0_DLL1_RG_ARDLL_PD_CK_SEL_B0, 24) + +/* DDRPHY_REG_SHU_B1_DLL1 */ +DEFINE_BIT(SHU_B1_DLL1_RG_ARDLL_UDIV_EN_B1, 4) +DEFINE_BIT(SHU_B1_DLL1_RG_ARDLL_TRACKING_CA_EN_B1, 6) +DEFINE_BITFIELD(SHU_B1_DLL1_RG_ARDLL_SER_MODE_B1, 9, 8) +DEFINE_BIT(SHU_B1_DLL1_RG_ARDLL_PS_EN_B1, 10) +DEFINE_BIT(SHU_B1_DLL1_RG_ARDLL_PSJP_EN_B1, 11) +DEFINE_BIT(SHU_B1_DLL1_RG_ARDLL_PHDIV_B1, 12) +DEFINE_BIT(SHU_B1_DLL1_RG_ARDLL_PHDET_OUT_SEL_B1, 13) +DEFINE_BIT(SHU_B1_DLL1_RG_ARDLL_PHDET_IN_SWAP_B1, 14) +DEFINE_BIT(SHU_B1_DLL1_RG_ARDLL_PHDET_EN_B1, 16) +DEFINE_BITFIELD(SHU_B1_DLL1_RG_ARDLL_PGAIN_B1, 23, 20) +DEFINE_BIT(SHU_B1_DLL1_RG_ARDLL_PD_CK_SEL_B1, 24) + +/* DDRPHY_REG_SHU_CA_DLL1 */ +DEFINE_BIT(SHU_CA_DLL1_RG_ARDLL_UDIV_EN_CA, 4) +DEFINE_BITFIELD(SHU_CA_DLL1_RG_ARDLL_SER_MODE_CA, 9, 8) +DEFINE_BIT(SHU_CA_DLL1_RG_ARDLL_PS_EN_CA, 10) +DEFINE_BIT(SHU_CA_DLL1_RG_ARDLL_PSJP_EN_CA, 11) +DEFINE_BIT(SHU_CA_DLL1_RG_ARDLL_PHDIV_CA, 12) +DEFINE_BIT(SHU_CA_DLL1_RG_ARDLL_PHDET_OUT_SEL_CA, 13) +DEFINE_BIT(SHU_CA_DLL1_RG_ARDLL_PHDET_IN_SWAP_CA, 14) +DEFINE_BIT(SHU_CA_DLL1_RG_ARDLL_PHDET_EN_CA, 16) +DEFINE_BITFIELD(SHU_CA_DLL1_RG_ARDLL_PGAIN_CA, 23, 20) +DEFINE_BIT(SHU_CA_DLL1_RG_ARDLL_PD_CK_SEL_CA, 24) + +/* DDRPHY_REG_SHU_B0_DQ1 */ +DEFINE_BIT(SHU_B0_DQ1_RG_ARPI_MIDPI_EN_B0, 0) +DEFINE_BIT(SHU_B0_DQ1_RG_ARPI_MIDPI_CKDIV4_EN_B0, 2) +DEFINE_BITFIELD(SHU_B0_DQ1_RG_ARPI_MIDPI_8PH_DLY_B0, 12, 8) +DEFINE_BITFIELD(SHU_B0_DQ1_RG_ARPI_MIDPI_LDO_VREF_SEL_B0, 17, 16) +DEFINE_BIT(SHU_B0_DQ1_RG_ARPI_8PHASE_XLATCH_FORCE_B0, 26) +DEFINE_BIT(SHU_B0_DQ1_RG_ARPI_MIDPI_DUMMY_EN_B0, 27) +DEFINE_BIT(SHU_B0_DQ1_RG_ARPI_MIDPI_BYPASS_EN_B0, 31) + +/* DDRPHY_REG_SHU_B1_DQ1 */ +DEFINE_BIT(SHU_B1_DQ1_RG_ARPI_MIDPI_EN_B1, 0) +DEFINE_BIT(SHU_B1_DQ1_RG_ARPI_MIDPI_CKDIV4_EN_B1, 2) +DEFINE_BITFIELD(SHU_B1_DQ1_RG_ARPI_MIDPI_8PH_DLY_B1, 12, 8) +DEFINE_BITFIELD(SHU_B1_DQ1_RG_ARPI_MIDPI_LDO_VREF_SEL_B1, 17, 16) +DEFINE_BIT(SHU_B1_DQ1_RG_ARPI_8PHASE_XLATCH_FORCE_B1, 26) +DEFINE_BIT(SHU_B1_DQ1_RG_ARPI_MIDPI_DUMMY_EN_B1, 27) +DEFINE_BIT(SHU_B1_DQ1_RG_ARPI_MIDPI_BYPASS_EN_B1, 31) + +/* DDRPHY_REG_SHU_CA_DLL_ARPI3 */ +DEFINE_BIT(SHU_CA_DLL_ARPI3_RG_ARPI_CLKIEN_EN, 11) +DEFINE_BIT(SHU_CA_DLL_ARPI3_RG_ARPI_CMD_EN, 13) +DEFINE_BIT(SHU_CA_DLL_ARPI3_RG_ARPI_CLK_EN, 15) +DEFINE_BIT(SHU_CA_DLL_ARPI3_RG_ARPI_CS_EN, 16) +DEFINE_BIT(SHU_CA_DLL_ARPI3_RG_ARPI_FB_EN_CA, 17) +DEFINE_BIT(SHU_CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA, 19) + +/* DDRPHY_REG_SHU_CA_CMD13 */ +DEFINE_BIT(SHU_CA_CMD13_RG_TX_ARCA_IO_ODT_DIS_CA, 0) +DEFINE_BIT(SHU_CA_CMD13_RG_TX_ARCA_FRATE_EN_CA, 1) +DEFINE_BIT(SHU_CA_CMD13_RG_TX_ARCA_DLY_LAT_EN_CA, 2) +DEFINE_BIT(SHU_CA_CMD13_RG_TX_ARCLK_OE_ODTEN_CG_EN_CA, 7) +DEFINE_BIT(SHU_CA_CMD13_RG_TX_ARCS_OE_ODTEN_CG_EN_CA, 16) +DEFINE_BIT(SHU_CA_CMD13_RG_TX_ARCLKB_READ_BASE_DATA_TIE_EN_CA, 17) +DEFINE_BIT(SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_SEL_CA, 24) +DEFINE_BIT(SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_EN_CA, 25) + +/* DDRPHY_REG_SHU_CA_CMD1 */ +DEFINE_BIT(SHU_CA_CMD1_RG_ARPI_MIDPI_EN_CA, 0) +DEFINE_BIT(SHU_CA_CMD1_RG_ARPI_MIDPI_CKDIV4_PREDIV_EN_CA, 1) +DEFINE_BIT(SHU_CA_CMD1_RG_ARPI_MIDPI_CKDIV4_EN_CA, 2) +DEFINE_BITFIELD(SHU_CA_CMD1_RG_ARPI_MIDPI_8PH_DLY_CA, 12, 8) +DEFINE_BITFIELD(SHU_CA_CMD1_RG_ARPI_MIDPI_LDO_VREF_SEL_CA, 17, 16) +DEFINE_BIT(SHU_CA_CMD1_RG_ARPI_MIDPI_DUMMY_EN_CA, 27) +DEFINE_BIT(SHU_CA_CMD1_RG_ARPI_MIDPI_BYPASS_EN_CA, 31) + +/* DDRPHY_REG_SHU_CA_DLL_ARPI2 */ +DEFINE_BIT(SHU_CA_DLL_ARPI2_RG_ARPI_MPDIV_CG_CA, 10) +DEFINE_BIT(SHU_CA_DLL_ARPI2_RG_ARPI_CG_CLKIEN, 11) +DEFINE_BIT(SHU_CA_DLL_ARPI2_RG_ARPI_CG_CMD, 13) +DEFINE_BIT(SHU_CA_DLL_ARPI2_RG_ARPI_CG_CLK, 15) +DEFINE_BIT(SHU_CA_DLL_ARPI2_RG_ARPI_CG_CS, 16) +DEFINE_BIT(SHU_CA_DLL_ARPI2_RG_ARPI_CG_FB_CA, 17) +DEFINE_BIT(SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCTL_CA, 19) +DEFINE_BIT(SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_CA, 27) +DEFINE_BIT(SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCK_CA, 31) + +/* DDRPHY_REG_CA_DLL_ARPI5 */ +DEFINE_BITFIELD(CA_DLL_ARPI5_RG_ARDLL_MON_SEL_CA, 7, 4) +DEFINE_BIT(CA_DLL_ARPI5_RG_ARDLL_DIV_DEC_CA, 8) +DEFINE_BIT(CA_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_SEL_CA, 25) +DEFINE_BIT(CA_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_CA, 26) +DEFINE_BIT(CA_DLL_ARPI5_RG_ARDLL_IDLE_EN_CA, 28) +DEFINE_BITFIELD(CA_DLL_ARPI5_RG_ARDLL_PD_ZONE_CA, 31, 29) + +/* DDRPHY_REG_B0_DLL_ARPI5 */ +DEFINE_BITFIELD(B0_DLL_ARPI5_RG_ARDLL_MON_SEL_B0, 7, 4) +DEFINE_BIT(B0_DLL_ARPI5_RG_ARDLL_DIV_DEC_B0, 8) +DEFINE_BIT(B0_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_SEL_B0, 25) +DEFINE_BIT(B0_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_B0, 26) +DEFINE_BIT(B0_DLL_ARPI5_RG_ARDLL_IDLE_EN_B0, 28) +DEFINE_BITFIELD(B0_DLL_ARPI5_RG_ARDLL_PD_ZONE_B0, 31, 29) + +/* DDRPHY_REG_B1_DLL_ARPI5 */ +DEFINE_BITFIELD(B1_DLL_ARPI5_RG_ARDLL_MON_SEL_B1, 7, 4) +DEFINE_BIT(B1_DLL_ARPI5_RG_ARDLL_DIV_DEC_B1, 8) +DEFINE_BIT(B1_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_SEL_B1, 25) +DEFINE_BIT(B1_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_B1, 26) +DEFINE_BIT(B1_DLL_ARPI5_RG_ARDLL_IDLE_EN_B1, 28) +DEFINE_BITFIELD(B1_DLL_ARPI5_RG_ARDLL_PD_ZONE_B1, 31, 29) + +/* DDRPHY_REG_CA_DLL_ARPI1 */ +DEFINE_BIT(CA_DLL_ARPI1_RG_ARPI_CLKIEN_JUMP_EN, 11) +DEFINE_BIT(CA_DLL_ARPI1_RG_ARPI_CMD_JUMP_EN, 13) +DEFINE_BIT(CA_DLL_ARPI1_RG_ARPI_CLK_JUMP_EN, 15) +DEFINE_BIT(CA_DLL_ARPI1_RG_ARPI_CS_JUMP_EN, 16) +DEFINE_BIT(CA_DLL_ARPI1_RG_ARPI_FB_JUMP_EN_CA, 17) +DEFINE_BIT(CA_DLL_ARPI1_RG_ARPI_MCTL_JUMP_EN_CA, 19) +DEFINE_BIT(CA_DLL_ARPI1_RG_ARPISM_MCK_SEL_CA_REG_OPT, 20) +DEFINE_BIT(CA_DLL_ARPI1_RG_ARPISM_MCK_SEL_CA, 21) + +/* DDRPHY_REG_B0_DLL_ARPI1 */ +DEFINE_BIT(B0_DLL_ARPI1_RG_ARPI_DQSIEN_JUMP_EN_B0, 11) +DEFINE_BIT(B0_DLL_ARPI1_RG_ARPI_DQ_JUMP_EN_B0, 13) +DEFINE_BIT(B0_DLL_ARPI1_RG_ARPI_DQM_JUMP_EN_B0, 14) +DEFINE_BIT(B0_DLL_ARPI1_RG_ARPI_DQS_JUMP_EN_B0, 15) +DEFINE_BIT(B0_DLL_ARPI1_RG_ARPI_FB_JUMP_EN_B0, 17) +DEFINE_BIT(B0_DLL_ARPI1_RG_ARPI_MCTL_JUMP_EN_B0, 19) +DEFINE_BIT(B0_DLL_ARPI1_RG_ARPISM_MCK_SEL_B0_REG_OPT, 20) +DEFINE_BIT(B0_DLL_ARPI1_RG_ARPISM_MCK_SEL_B0, 21) + +/* DDRPHY_REG_B1_DLL_ARPI1 */ +DEFINE_BIT(B1_DLL_ARPI1_RG_ARPI_DQSIEN_JUMP_EN_B1, 11) +DEFINE_BIT(B1_DLL_ARPI1_RG_ARPI_DQ_JUMP_EN_B1, 13) +DEFINE_BIT(B1_DLL_ARPI1_RG_ARPI_DQM_JUMP_EN_B1, 14) +DEFINE_BIT(B1_DLL_ARPI1_RG_ARPI_DQS_JUMP_EN_B1, 15) +DEFINE_BIT(B1_DLL_ARPI1_RG_ARPI_FB_JUMP_EN_B1, 17) +DEFINE_BIT(B1_DLL_ARPI1_RG_ARPI_MCTL_JUMP_EN_B1, 19) +DEFINE_BIT(B1_DLL_ARPI1_RG_ARPISM_MCK_SEL_B1_REG_OPT, 20) +DEFINE_BIT(B1_DLL_ARPI1_RG_ARPISM_MCK_SEL_B1, 21) + +/* DDRPHY_REG_SHU_CA_DLL0 */ +DEFINE_BITFIELD(SHU_CA_DLL0_RG_ARDLL_IDLECNT_CA, 15, 12) +DEFINE_BITFIELD(SHU_CA_DLL0_RG_ARDLL_GAIN_CA, 23, 20) +DEFINE_BIT(SHU_CA_DLL0_RG_ARDLL_FAST_PSJP_CA, 25) +DEFINE_BIT(SHU_CA_DLL0_RG_ARDLL_FASTPJ_CK_SEL_CA, 26) +DEFINE_BIT(SHU_CA_DLL0_RG_ARDLL_GEAR2_PSJP_CA, 27) + +/* DDRPHY_REG_SHU_B0_DLL0 */ +DEFINE_BITFIELD(SHU_B0_DLL0_RG_ARDLL_IDLECNT_B0, 15, 12) +DEFINE_BITFIELD(SHU_B0_DLL0_RG_ARDLL_GAIN_B0, 23, 20) +DEFINE_BIT(SHU_B0_DLL0_RG_ARDLL_FAST_PSJP_B0, 25) +DEFINE_BIT(SHU_B0_DLL0_RG_ARDLL_FASTPJ_CK_SEL_B0, 26) +DEFINE_BIT(SHU_B0_DLL0_RG_ARDLL_GEAR2_PSJP_B0, 27) + +/* DDRPHY_REG_SHU_B1_DLL0 */ +DEFINE_BITFIELD(SHU_B1_DLL0_RG_ARDLL_IDLECNT_B1, 15, 12) +DEFINE_BITFIELD(SHU_B1_DLL0_RG_ARDLL_GAIN_B1, 23, 20) +DEFINE_BIT(SHU_B1_DLL0_RG_ARDLL_FAST_PSJP_B1, 25) +DEFINE_BIT(SHU_B1_DLL0_RG_ARDLL_FASTPJ_CK_SEL_B1, 26) +DEFINE_BIT(SHU_B1_DLL0_RG_ARDLL_GEAR2_PSJP_B1, 27) + +/* DDRPHY_REG_SHU_B0_DLL_ARPI3 */ +DEFINE_BIT(SHU_B0_DLL_ARPI3_RG_ARPI_DQSIEN_EN_B0, 11) +DEFINE_BIT(SHU_B0_DLL_ARPI3_RG_ARPI_DQ_EN_B0, 13) +DEFINE_BIT(SHU_B0_DLL_ARPI3_RG_ARPI_DQM_EN_B0, 14) +DEFINE_BIT(SHU_B0_DLL_ARPI3_RG_ARPI_DQS_EN_B0, 15) +DEFINE_BIT(SHU_B0_DLL_ARPI3_RG_ARPI_FB_EN_B0, 17) +DEFINE_BIT(SHU_B0_DLL_ARPI3_RG_ARPI_MCTL_EN_B0, 19) + +/* DDRPHY_REG_SHU_B1_DLL_ARPI3 */ +DEFINE_BIT(SHU_B1_DLL_ARPI3_RG_ARPI_DQSIEN_EN_B1, 11) +DEFINE_BIT(SHU_B1_DLL_ARPI3_RG_ARPI_DQ_EN_B1, 13) +DEFINE_BIT(SHU_B1_DLL_ARPI3_RG_ARPI_DQM_EN_B1, 14) +DEFINE_BIT(SHU_B1_DLL_ARPI3_RG_ARPI_DQS_EN_B1, 15) +DEFINE_BIT(SHU_B1_DLL_ARPI3_RG_ARPI_FB_EN_B1, 17) +DEFINE_BIT(SHU_B1_DLL_ARPI3_RG_ARPI_MCTL_EN_B1, 19) + +/* DDRPHY_REG_SHU_CA_CMD2 */ +DEFINE_BIT(SHU_CA_CMD2_RG_ARPI_TX_CG_SYNC_DIS_CA, 0) +DEFINE_BIT(SHU_CA_CMD2_RG_ARPI_TX_CG_CA_EN_CA, 4) +DEFINE_BIT(SHU_CA_CMD2_RG_ARPI_TX_CG_CLK_EN_CA, 5) +DEFINE_BIT(SHU_CA_CMD2_RG_ARPI_TX_CG_CS_EN_CA, 6) +DEFINE_BIT(SHU_CA_CMD2_RG_ARPI_SMT_XLATCH_FORCE_CLK_CA, 8) +DEFINE_BIT(SHU_CA_CMD2_RG_ARPI_SMT_XLATCH_CA_FORCE_CA, 9) +DEFINE_BIT(SHU_CA_CMD2_RG_ARPI_PSMUX_XLATCH_FORCE_CA_CA, 10) +DEFINE_BIT(SHU_CA_CMD2_RG_ARPI_PSMUX_XLATCH_FORCE_CLK_CA, 11) +DEFINE_BIT(SHU_CA_CMD2_RG_ARPISM_MCK_SEL_CA_SHU, 12) +DEFINE_BIT(SHU_CA_CMD2_RG_ARPI_PD_MCTL_SEL_CA, 13) +DEFINE_BIT(SHU_CA_CMD2_RG_ARPI_OFFSET_LAT_EN_CA, 16) +DEFINE_BIT(SHU_CA_CMD2_RG_ARPI_OFFSET_ASYNC_EN_CA, 17) + +/* DDRPHY_REG_SHU_B0_DQ2 */ +DEFINE_BIT(SHU_B0_DQ2_RG_ARPI_TX_CG_SYNC_DIS_B0, 0) +DEFINE_BIT(SHU_B0_DQ2_RG_ARPI_TX_CG_DQ_EN_B0, 4) +DEFINE_BIT(SHU_B0_DQ2_RG_ARPI_TX_CG_DQS_EN_B0, 5) +DEFINE_BIT(SHU_B0_DQ2_RG_ARPI_TX_CG_DQM_EN_B0, 6) +DEFINE_BIT(SHU_B0_DQ2_RG_ARPI_SMT_XLATCH_FORCE_DQS_B0, 8) +DEFINE_BIT(SHU_B0_DQ2_RG_ARPI_SMT_XLATCH_DQ_FORCE_B0, 9) +DEFINE_BIT(SHU_B0_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQ_B0, 10) +DEFINE_BIT(SHU_B0_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQS_B0, 11) +DEFINE_BIT(SHU_B0_DQ2_RG_ARPISM_MCK_SEL_B0_SHU, 12) +DEFINE_BIT(SHU_B0_DQ2_RG_ARPI_PD_MCTL_SEL_B0, 13) +DEFINE_BIT(SHU_B0_DQ2_RG_ARPI_OFFSET_LAT_EN_B0, 16) +DEFINE_BIT(SHU_B0_DQ2_RG_ARPI_OFFSET_ASYNC_EN_B0, 17) + +/* DDRPHY_REG_SHU_B1_DQ2 */ +DEFINE_BIT(SHU_B1_DQ2_RG_ARPI_TX_CG_SYNC_DIS_B1, 0) +DEFINE_BIT(SHU_B1_DQ2_RG_ARPI_TX_CG_DQ_EN_B1, 4) +DEFINE_BIT(SHU_B1_DQ2_RG_ARPI_TX_CG_DQS_EN_B1, 5) +DEFINE_BIT(SHU_B1_DQ2_RG_ARPI_TX_CG_DQM_EN_B1, 6) +DEFINE_BIT(SHU_B1_DQ2_RG_ARPI_SMT_XLATCH_FORCE_DQS_B1, 8) +DEFINE_BIT(SHU_B1_DQ2_RG_ARPI_SMT_XLATCH_DQ_FORCE_B1, 9) +DEFINE_BIT(SHU_B1_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQ_B1, 10) +DEFINE_BIT(SHU_B1_DQ2_RG_ARPI_PSMUX_XLATCH_FORCE_DQS_B1, 11) +DEFINE_BIT(SHU_B1_DQ2_RG_ARPISM_MCK_SEL_B1_SHU, 12) +DEFINE_BIT(SHU_B1_DQ2_RG_ARPI_PD_MCTL_SEL_B1, 13) +DEFINE_BIT(SHU_B1_DQ2_RG_ARPI_OFFSET_LAT_EN_B1, 16) +DEFINE_BIT(SHU_B1_DQ2_RG_ARPI_OFFSET_ASYNC_EN_B1, 17) + +/* DDRPHY_REG_SHU_B0_DQ7 */ +DEFINE_BITFIELD(SHU_B0_DQ7_R_DMRANKRXDVS_B0, 3, 0) +DEFINE_BIT(SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0, 6) +DEFINE_BIT(SHU_B0_DQ7_R_DMDQMDBI_SHU_B0, 7) +DEFINE_BITFIELD(SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0, 11, 8) +DEFINE_BIT(SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0, 12) +DEFINE_BIT(SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0, 13) +DEFINE_BIT(SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0, 14) +DEFINE_BIT(SHU_B0_DQ7_R_DMRODTEN_B0, 15) +DEFINE_BIT(SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0, 16) +DEFINE_BIT(SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0, 17) +DEFINE_BIT(SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0, 18) +DEFINE_BIT(SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0, 19) +DEFINE_BIT(SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0, 20) +DEFINE_BIT(SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0, 24) +DEFINE_BITFIELD(SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0, 27, 25) +DEFINE_BIT(SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0, 28) +DEFINE_BITFIELD(SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0, 31, 29) + +/* DDRPHY_REG_SHU_B1_DQ7 */ +DEFINE_BITFIELD(SHU_B1_DQ7_R_DMRANKRXDVS_B1, 3, 0) +DEFINE_BIT(SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1, 6) +DEFINE_BIT(SHU_B1_DQ7_R_DMDQMDBI_SHU_B1, 7) +DEFINE_BITFIELD(SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1, 11, 8) +DEFINE_BIT(SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1, 12) +DEFINE_BIT(SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1, 13) +DEFINE_BIT(SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1, 14) +DEFINE_BIT(SHU_B1_DQ7_R_DMRODTEN_B1, 15) +DEFINE_BIT(SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1, 16) +DEFINE_BIT(SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1, 17) +DEFINE_BIT(SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1, 18) +DEFINE_BIT(SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1, 19) +DEFINE_BIT(SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1, 20) +DEFINE_BIT(SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1, 24) +DEFINE_BITFIELD(SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1, 27, 25) +DEFINE_BIT(SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1, 28) +DEFINE_BITFIELD(SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1, 31, 29) + +/* DDRPHY_REG_SHU_CA_CMD7 */ +DEFINE_BIT(SHU_CA_CMD7_R_DMTX_ARPI_CG_CMD_NEW, 17) +DEFINE_BIT(SHU_CA_CMD7_R_DMTX_ARPI_CG_CS_NEW, 19) +DEFINE_BIT(SHU_CA_CMD7_R_LP4Y_SDN_MODE_CLK, 20) + +/* DDRPHY_REG_CA_CMD6 */ +DEFINE_BIT(CA_CMD6_RG_RX_ARCMD_RES_BIAS_EN, 6) +DEFINE_BITFIELD(CA_CMD6_RG_RX_ARCMD_BIAS_VREF_SEL, 15, 14) +DEFINE_BIT(CA_CMD6_RG_RX_ARCMD_DDR4_SEL, 16) +DEFINE_BIT(CA_CMD6_RG_TX_ARCMD_DDR4_SEL, 17) +DEFINE_BIT(CA_CMD6_RG_RX_ARCMD_DDR3_SEL, 18) +DEFINE_BIT(CA_CMD6_RG_TX_ARCMD_DDR3_SEL, 19) +DEFINE_BIT(CA_CMD6_RG_TX_ARCMD_LP4_SEL, 21) + +/* DDRPHY_REG_B0_DQ6 */ +DEFINE_BIT(B0_DQ6_RG_RX_ARDQ_RES_BIAS_EN_B0, 6) +DEFINE_BIT(B0_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B0, 7) +DEFINE_BIT(B0_DQ6_RG_RX_ARDQ_O1_SEL_B0, 9) +DEFINE_BIT(B0_DQ6_RG_RX_ARDQ_BIAS_EN_B0, 12) +DEFINE_BITFIELD(B0_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B0, 15, 14) +DEFINE_BIT(B0_DQ6_RG_RX_ARDQ_DDR4_SEL_B0, 16) +DEFINE_BIT(B0_DQ6_RG_TX_ARDQ_DDR4_SEL_B0, 17) +DEFINE_BIT(B0_DQ6_RG_RX_ARDQ_DDR3_SEL_B0, 18) +DEFINE_BIT(B0_DQ6_RG_TX_ARDQ_DDR3_SEL_B0, 19) +DEFINE_BIT(B0_DQ6_RG_TX_ARDQ_LP4_SEL_B0, 21) +DEFINE_BIT(B0_DQ6_RG_RX_ARDQ_EYE_DLY_DQS_BYPASS_B0, 28) +DEFINE_BIT(B0_DQ6_RG_RX_ARDQ_DMRANK_OUTSEL_B0, 31) + +/* DDRPHY_REG_B1_DQ6 */ +DEFINE_BIT(B1_DQ6_RG_RX_ARDQ_RES_BIAS_EN_B1, 6) +DEFINE_BIT(B1_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B1, 7) +DEFINE_BIT(B1_DQ6_RG_RX_ARDQ_O1_SEL_B1, 9) +DEFINE_BIT(B1_DQ6_RG_RX_ARDQ_BIAS_EN_B1, 12) +DEFINE_BITFIELD(B1_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B1, 15, 14) +DEFINE_BIT(B1_DQ6_RG_RX_ARDQ_DDR4_SEL_B1, 16) +DEFINE_BIT(B1_DQ6_RG_TX_ARDQ_DDR4_SEL_B1, 17) +DEFINE_BIT(B1_DQ6_RG_RX_ARDQ_DDR3_SEL_B1, 18) +DEFINE_BIT(B1_DQ6_RG_TX_ARDQ_DDR3_SEL_B1, 19) +DEFINE_BIT(B1_DQ6_RG_TX_ARDQ_LP4_SEL_B1, 21) +DEFINE_BIT(B1_DQ6_RG_RX_ARDQ_EYE_DLY_DQS_BYPASS_B1, 28) +DEFINE_BIT(B1_DQ6_RG_RX_ARDQ_DMRANK_OUTSEL_B1, 31) + +/* DDRPHY_REG_CA_CMD2 */ +DEFINE_BIT(CA_CMD2_RG_TX_ARCLK_ODTEN_DIS_CA, 0) +DEFINE_BIT(CA_CMD2_RG_TX_ARCLK_OE_DIS_CA, 1) +DEFINE_BIT(CA_CMD2_RG_TX_ARCLK_OE_TIE_SEL_CA, 2) +DEFINE_BIT(CA_CMD2_RG_TX_ARCLK_OE_TIE_EN_CA, 3) +DEFINE_BIT(CA_CMD2_RG_TX_ARCS_OE_TIE_SEL_CA, 14) +DEFINE_BIT(CA_CMD2_RG_TX_ARCS_OE_TIE_EN_CA, 15) +DEFINE_BIT(CA_CMD2_RG_TX_ARCMD_ODTEN_DIS_CA, 20) +DEFINE_BIT(CA_CMD2_RG_TX_ARCMD_OE_DIS_CA, 21) +DEFINE_BIT(CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA, 22) +DEFINE_BITFIELD(CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA, 31, 24) + +/* DDRPHY_REG_B0_DQ2 */ +DEFINE_BIT(B0_DQ2_RG_TX_ARDQS0_ODTEN_DIS_B0, 0) +DEFINE_BIT(B0_DQ2_RG_TX_ARDQS0_OE_DIS_B0, 1) +DEFINE_BIT(B0_DQ2_RG_TX_ARDQS_OE_TIE_SEL_B0, 2) +DEFINE_BIT(B0_DQ2_RG_TX_ARDQS_OE_TIE_EN_B0, 3) +DEFINE_BIT(B0_DQ2_RG_TX_ARWCK_OE_TIE_SEL_B0, 8) +DEFINE_BIT(B0_DQ2_RG_TX_ARWCK_OE_TIE_EN_B0, 9) +DEFINE_BIT(B0_DQ2_RG_TX_ARWCKB_OE_TIE_SEL_B0, 10) +DEFINE_BIT(B0_DQ2_RG_TX_ARWCKB_OE_TIE_EN_B0, 11) +DEFINE_BIT(B0_DQ2_RG_TX_ARDQM0_ODTEN_DIS_B0, 12) +DEFINE_BIT(B0_DQ2_RG_TX_ARDQM0_OE_DIS_B0, 13) +DEFINE_BIT(B0_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B0, 14) +DEFINE_BIT(B0_DQ2_RG_TX_ARDQM_OE_TIE_EN_B0, 15) +DEFINE_BIT(B0_DQ2_RG_TX_ARDQ_ODTEN_DIS_B0, 20) +DEFINE_BIT(B0_DQ2_RG_TX_ARDQ_OE_DIS_B0, 21) +DEFINE_BIT(B0_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B0, 22) +DEFINE_BITFIELD(B0_DQ2_RG_TX_ARDQ_OE_TIE_EN_B0, 31, 24) + +/* DDRPHY_REG_B1_DQ2 */ +DEFINE_BIT(B1_DQ2_RG_TX_ARDQS0_ODTEN_DIS_B1, 0) +DEFINE_BIT(B1_DQ2_RG_TX_ARDQS0_OE_DIS_B1, 1) +DEFINE_BIT(B1_DQ2_RG_TX_ARDQS_OE_TIE_SEL_B1, 2) +DEFINE_BIT(B1_DQ2_RG_TX_ARDQS_OE_TIE_EN_B1, 3) +DEFINE_BIT(B1_DQ2_RG_TX_ARWCK_OE_TIE_SEL_B1, 8) +DEFINE_BIT(B1_DQ2_RG_TX_ARWCK_OE_TIE_EN_B1, 9) +DEFINE_BIT(B1_DQ2_RG_TX_ARWCKB_OE_TIE_SEL_B1, 10) +DEFINE_BIT(B1_DQ2_RG_TX_ARWCKB_OE_TIE_EN_B1, 11) +DEFINE_BIT(B1_DQ2_RG_TX_ARDQM0_ODTEN_DIS_B1, 12) +DEFINE_BIT(B1_DQ2_RG_TX_ARDQM0_OE_DIS_B1, 13) +DEFINE_BIT(B1_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B1, 14) +DEFINE_BIT(B1_DQ2_RG_TX_ARDQM_OE_TIE_EN_B1, 15) +DEFINE_BIT(B1_DQ2_RG_TX_ARDQ_ODTEN_DIS_B1, 20) +DEFINE_BIT(B1_DQ2_RG_TX_ARDQ_OE_DIS_B1, 21) +DEFINE_BIT(B1_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B1, 22) +DEFINE_BITFIELD(B1_DQ2_RG_TX_ARDQ_OE_TIE_EN_B1, 31, 24) + +/* DDRPHY_REG_CA_CMD3 */ +DEFINE_BIT(CA_CMD3_RG_TX_ARCMD_EN, 2) +DEFINE_BIT(CA_CMD3_RG_ARCMD_RESETB, 3) + +/* DDRPHY_REG_B0_DQ3 */ +DEFINE_BIT(B0_DQ3_RG_RX_ARDQ_SMT_EN_B0, 1) +DEFINE_BIT(B0_DQ3_RG_TX_ARDQ_EN_B0, 2) +DEFINE_BIT(B0_DQ3_RG_ARDQ_RESETB_B0, 3) +DEFINE_BIT(B0_DQ3_RG_RX_ARDQS0_IN_BUFF_EN_B0, 5) +DEFINE_BIT(B0_DQ3_RG_RX_ARDQ_IN_BUFF_EN_B0, 7) +DEFINE_BIT(B0_DQ3_RG_RX_ARDQ_STBENCMP_EN_B0, 10) + +/* DDRPHY_REG_B1_DQ3 */ +DEFINE_BIT(B1_DQ3_RG_RX_ARDQ_SMT_EN_B1, 1) +DEFINE_BIT(B1_DQ3_RG_TX_ARDQ_EN_B1, 2) +DEFINE_BIT(B1_DQ3_RG_ARDQ_RESETB_B1, 3) +DEFINE_BIT(B1_DQ3_RG_RX_ARDQS0_IN_BUFF_EN_B1, 5) +DEFINE_BIT(B1_DQ3_RG_RX_ARDQ_IN_BUFF_EN_B1, 7) +DEFINE_BIT(B1_DQ3_RG_RX_ARDQ_STBENCMP_EN_B1, 10) + +/* DDRPHY_REG_SHU_B0_DQ13 */ +DEFINE_BIT(SHU_B0_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B0, 0) +DEFINE_BIT(SHU_B0_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B0, 2) +DEFINE_BIT(SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_EN_B0, 3) +DEFINE_BIT(SHU_B0_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B0, 7) +DEFINE_BITFIELD(SHU_B0_DQ13_RG_TX_ARDQS_MCKIO_SEL_B0, 13, 12) +DEFINE_BIT(SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B0, 15) +DEFINE_BIT(SHU_B0_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B0, 16) +DEFINE_BIT(SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B0, 17) +DEFINE_BIT(SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B0, 18) +DEFINE_BIT(SHU_B0_DQ13_RG_TX_ARDQSB_OE_TIE_SEL_B0, 24) +DEFINE_BIT(SHU_B0_DQ13_RG_TX_ARDQSB_OE_TIE_EN_B0, 25) + +/* DDRPHY_REG_SHU_B1_DQ13 */ +DEFINE_BIT(SHU_B1_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B1, 0) +DEFINE_BIT(SHU_B1_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B1, 2) +DEFINE_BIT(SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_EN_B1, 3) +DEFINE_BIT(SHU_B1_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B1, 7) +DEFINE_BITFIELD(SHU_B1_DQ13_RG_TX_ARDQS_MCKIO_SEL_B1, 13, 12) +DEFINE_BIT(SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B1, 15) +DEFINE_BIT(SHU_B1_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B1, 16) +DEFINE_BIT(SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B1, 17) +DEFINE_BIT(SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B1, 18) +DEFINE_BIT(SHU_B1_DQ13_RG_TX_ARDQSB_OE_TIE_SEL_B1, 24) +DEFINE_BIT(SHU_B1_DQ13_RG_TX_ARDQSB_OE_TIE_EN_B1, 25) + +/* DDRPHY_REG_SHU_B0_DQ10 */ +DEFINE_BIT(SHU_B0_DQ10_RG_RX_ARDQS_SE_EN_B0, 0) +DEFINE_BIT(SHU_B0_DQ10_RG_RX_ARDQS_DQSSTB_CG_EN_B0, 1) +DEFINE_BIT(SHU_B0_DQ10_RG_RX_ARDQS_DQSIEN_RANK_SEL_LAT_EN_B0, 2) +DEFINE_BIT(SHU_B0_DQ10_RG_RX_ARDQS_RANK_SEL_LAT_EN_B0, 3) +DEFINE_BIT(SHU_B0_DQ10_RG_RX_ARDQS_DQSSTB_RPST_HS_EN_B0, 4) +DEFINE_BITFIELD(SHU_B0_DQ10_RG_RX_ARDQS_DQSIEN_MODE_B0, 10, 8) +DEFINE_BIT(SHU_B0_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B0, 15) +DEFINE_BITFIELD(SHU_B0_DQ10_RG_RX_ARDQS_BW_SEL_B0, 19, 18) + +/* DDRPHY_REG_SHU_B1_DQ10 */ +DEFINE_BIT(SHU_B1_DQ10_RG_RX_ARDQS_SE_EN_B1, 0) +DEFINE_BIT(SHU_B1_DQ10_RG_RX_ARDQS_DQSSTB_CG_EN_B1, 1) +DEFINE_BIT(SHU_B1_DQ10_RG_RX_ARDQS_DQSIEN_RANK_SEL_LAT_EN_B1, 2) +DEFINE_BIT(SHU_B1_DQ10_RG_RX_ARDQS_RANK_SEL_LAT_EN_B1, 3) +DEFINE_BIT(SHU_B1_DQ10_RG_RX_ARDQS_DQSSTB_RPST_HS_EN_B1, 4) +DEFINE_BITFIELD(SHU_B1_DQ10_RG_RX_ARDQS_DQSIEN_MODE_B1, 10, 8) +DEFINE_BIT(SHU_B1_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B1, 15) +DEFINE_BITFIELD(SHU_B1_DQ10_RG_RX_ARDQS_BW_SEL_B1, 19, 18) + +/* DDRPHY_REG_SHU_CA_CMD10 */ +DEFINE_BIT(SHU_CA_CMD10_RG_RX_ARCLK_DQSIEN_RANK_SEL_LAT_EN_CA, 2) +DEFINE_BIT(SHU_CA_CMD10_RG_RX_ARCLK_RANK_SEL_LAT_EN_CA, 3) +DEFINE_BIT(SHU_CA_CMD10_RG_RX_ARCLK_DLY_LAT_EN_CA, 15) +DEFINE_BITFIELD(SHU_CA_CMD10_RG_RX_ARCLK_BW_SEL_CA, 19, 18) + +/* DDRPHY_REG_B0_DQ5 */ +DEFINE_BITFIELD(B0_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B0, 13, 8) +DEFINE_BIT(B0_DQ5_RG_RX_ARDQ_VREF_EN_B0, 16) +DEFINE_BIT(B0_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B0, 17) +DEFINE_BITFIELD(B0_DQ5_RG_RX_ARDQ_EYE_SEL_B0, 23, 20) +DEFINE_BIT(B0_DQ5_RG_RX_ARDQ_EYE_EN_B0, 24) +DEFINE_BIT(B0_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B0, 25) +DEFINE_BIT(B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0, 31) + +/* DDRPHY_REG_B1_DQ5 */ +DEFINE_BITFIELD(B1_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B1, 13, 8) +DEFINE_BIT(B1_DQ5_RG_RX_ARDQ_VREF_EN_B1, 16) +DEFINE_BIT(B1_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B1, 17) +DEFINE_BITFIELD(B1_DQ5_RG_RX_ARDQ_EYE_SEL_B1, 23, 20) +DEFINE_BIT(B1_DQ5_RG_RX_ARDQ_EYE_EN_B1, 24) +DEFINE_BIT(B1_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B1, 25) +DEFINE_BIT(B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1, 31) + +/* DDRPHY_REG_CA_CMD9 */ +DEFINE_BIT(CA_CMD9_RG_RX_ARCMD_STBEN_RESETB, 0) +DEFINE_BIT(CA_CMD9_RG_RX_ARCLK_STBEN_RESETB, 4) + +/* DDRPHY_REG_B0_DQ9 */ +DEFINE_BIT(B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0, 0) +DEFINE_BIT(B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0, 4) +DEFINE_BIT(B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0, 5) +DEFINE_BIT(B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0, 6) +DEFINE_BIT(B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0, 7) +DEFINE_BITFIELD(B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0, 15, 8) +DEFINE_BITFIELD(B0_DQ9_R_DMDQSIEN_VALID_LAT_B0, 18, 16) +DEFINE_BITFIELD(B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0, 22, 20) +DEFINE_BITFIELD(B0_DQ9_R_DMRXDVS_VALID_LAT_B0, 26, 24) +DEFINE_BITFIELD(B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0, 30, 28) + +/* DDRPHY_REG_B1_DQ9 */ +DEFINE_BIT(B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1, 0) +DEFINE_BIT(B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1, 4) +DEFINE_BIT(B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1, 5) +DEFINE_BIT(B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1, 6) +DEFINE_BIT(B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1, 7) +DEFINE_BITFIELD(B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1, 15, 8) +DEFINE_BITFIELD(B1_DQ9_R_DMDQSIEN_VALID_LAT_B1, 18, 16) +DEFINE_BITFIELD(B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1, 22, 20) +DEFINE_BITFIELD(B1_DQ9_R_DMRXDVS_VALID_LAT_B1, 26, 24) +DEFINE_BITFIELD(B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1, 30, 28) + +/* DDRPHY_REG_CA_CMD8 */ +DEFINE_BIT(CA_CMD8_RG_RX_ARCLK_SER_RST_MODE, 13) +DEFINE_BIT(CA_CMD8_RG_ARDLL_RESETB_CA, 15) + +/* DDRPHY_REG_B0_DQ8 */ +DEFINE_BIT(B0_DQ8_RG_RX_ARDQS_SER_RST_MODE_B0, 13) +DEFINE_BIT(B0_DQ8_RG_ARDLL_RESETB_B0, 15) + +/* DDRPHY_REG_B1_DQ8 */ +DEFINE_BIT(B1_DQ8_RG_RX_ARDQS_SER_RST_MODE_B1, 13) +DEFINE_BIT(B1_DQ8_RG_ARDLL_RESETB_B1, 15) + +/* DDRPHY_REG_CA_CMD11 */ +DEFINE_BITFIELD(CA_CMD11_RG_RRESETB_DRVP, 4, 0) +DEFINE_BITFIELD(CA_CMD11_RG_RRESETB_DRVN, 12, 8) +DEFINE_BIT(CA_CMD11_RG_TX_RRESETB_DDR3_SEL, 19) +DEFINE_BIT(CA_CMD11_RG_TX_RRESETB_PULL_DN, 20) + +/* DDRPHY_REG_MISC_CTRL1 */ +DEFINE_BIT(MISC_CTRL1_R_RK_PINMUXSWAP_EN, 0) +DEFINE_BIT(MISC_CTRL1_R_DMPHYRST, 1) +DEFINE_BIT(MISC_CTRL1_R_DM_TX_ARCLK_OE, 2) +DEFINE_BIT(MISC_CTRL1_R_DM_TX_ARCMD_OE, 3) +DEFINE_BIT(MISC_CTRL1_R_DMARPIDQ_SW, 7) +DEFINE_BITFIELD(MISC_CTRL1_R_DMPINMUX, 9, 8) +DEFINE_BIT(MISC_CTRL1_R_DMRRESETB_I_OPT, 12) +DEFINE_BIT(MISC_CTRL1_R_DMDA_RRESETB_I, 13) +DEFINE_BIT(MISC_CTRL1_R_DMDQSIENCG_EN, 24) +DEFINE_BIT(MISC_CTRL1_R_DMSTBENCMP_RK_OPT, 25) +DEFINE_BIT(MISC_CTRL1_R_DMDA_RRESETB_E, 31) + +/* DDRPHY_REG_B0_LP_CTRL0 */ +DEFINE_BIT(B0_LP_CTRL0_RG_ARDMSUS_10_B0, 0) +DEFINE_BIT(B0_LP_CTRL0_RG_ARDMSUS_10_B0_LP_SEL, 4) +DEFINE_BIT(B0_LP_CTRL0_RG_ARDQ_RESETB_B0_LP_SEL, 8) +DEFINE_BIT(B0_LP_CTRL0_RG_ARPI_RESETB_B0_LP_SEL, 9) +DEFINE_BIT(B0_LP_CTRL0_RG_B0_MS_SLV_LP_SEL, 12) +DEFINE_BIT(B0_LP_CTRL0_RG_ARDLL_PHDET_EN_B0_LP_SEL, 13) +DEFINE_BIT(B0_LP_CTRL0_RG_RX_ARDQ_BIAS_EN_B0_LP_SEL, 16) +DEFINE_BIT(B0_LP_CTRL0_DA_ARPI_CG_MCK_B0_LP_SEL, 17) +DEFINE_BIT(B0_LP_CTRL0_DA_ARPI_CG_MCK_FB2DLL_B0_LP_SEL, 18) +DEFINE_BIT(B0_LP_CTRL0_DA_ARPI_CG_MCTL_B0_LP_SEL, 19) +DEFINE_BIT(B0_LP_CTRL0_DA_ARPI_CG_FB_B0_LP_SEL, 20) +DEFINE_BIT(B0_LP_CTRL0_DA_ARPI_CG_DQ_B0_LP_SEL, 21) +DEFINE_BIT(B0_LP_CTRL0_DA_ARPI_CG_DQM_B0_LP_SEL, 22) +DEFINE_BIT(B0_LP_CTRL0_DA_ARPI_CG_DQS_B0_LP_SEL, 23) +DEFINE_BIT(B0_LP_CTRL0_DA_ARPI_CG_DQSIEN_B0_LP_SEL, 24) +DEFINE_BIT(B0_LP_CTRL0_DA_ARPI_MPDIV_CG_B0_LP_SEL, 25) +DEFINE_BIT(B0_LP_CTRL0_RG_RX_ARDQ_VREF_EN_B0_LP_SEL, 26) +DEFINE_BIT(B0_LP_CTRL0_DA_ARPI_MIDPI_EN_B0_LP_SEL, 27) +DEFINE_BIT(B0_LP_CTRL0_DA_ARPI_MIDPI_CKDIV4_EN_B0_LP_SEL, 28) + +/* DDRPHY_REG_B1_LP_CTRL0 */ +DEFINE_BIT(B1_LP_CTRL0_RG_ARDMSUS_10_B1, 0) +DEFINE_BIT(B1_LP_CTRL0_RG_ARDMSUS_10_B1_LP_SEL, 4) +DEFINE_BIT(B1_LP_CTRL0_RG_ARDQ_RESETB_B1_LP_SEL, 8) +DEFINE_BIT(B1_LP_CTRL0_RG_ARPI_RESETB_B1_LP_SEL, 9) +DEFINE_BIT(B1_LP_CTRL0_RG_B1_MS_SLV_LP_SEL, 12) +DEFINE_BIT(B1_LP_CTRL0_RG_ARDLL_PHDET_EN_B1_LP_SEL, 13) +DEFINE_BIT(B1_LP_CTRL0_RG_RX_ARDQ_BIAS_EN_B1_LP_SEL, 16) +DEFINE_BIT(B1_LP_CTRL0_DA_ARPI_CG_MCK_B1_LP_SEL, 17) +DEFINE_BIT(B1_LP_CTRL0_DA_ARPI_CG_MCK_FB2DLL_B1_LP_SEL, 18) +DEFINE_BIT(B1_LP_CTRL0_DA_ARPI_CG_MCTL_B1_LP_SEL, 19) +DEFINE_BIT(B1_LP_CTRL0_DA_ARPI_CG_FB_B1_LP_SEL, 20) +DEFINE_BIT(B1_LP_CTRL0_DA_ARPI_CG_DQ_B1_LP_SEL, 21) +DEFINE_BIT(B1_LP_CTRL0_DA_ARPI_CG_DQM_B1_LP_SEL, 22) +DEFINE_BIT(B1_LP_CTRL0_DA_ARPI_CG_DQS_B1_LP_SEL, 23) +DEFINE_BIT(B1_LP_CTRL0_DA_ARPI_CG_DQSIEN_B1_LP_SEL, 24) +DEFINE_BIT(B1_LP_CTRL0_DA_ARPI_MPDIV_CG_B1_LP_SEL, 25) +DEFINE_BIT(B1_LP_CTRL0_RG_RX_ARDQ_VREF_EN_B1_LP_SEL, 26) +DEFINE_BIT(B1_LP_CTRL0_DA_ARPI_MIDPI_EN_B1_LP_SEL, 27) +DEFINE_BIT(B1_LP_CTRL0_DA_ARPI_MIDPI_CKDIV4_EN_B1_LP_SEL, 28) + +/* DDRPHY_REG_CA_LP_CTRL0 */ +DEFINE_BIT(CA_LP_CTRL0_RG_ARDMSUS_10_CA, 0) +DEFINE_BIT(CA_LP_CTRL0_RG_TX_ARCA_PULL_DN_LP_SEL, 1) +DEFINE_BIT(CA_LP_CTRL0_RG_TX_ARCA_PULL_UP_LP_SEL, 2) +DEFINE_BIT(CA_LP_CTRL0_RG_TX_ARCS_PULL_DN_LP_SEL, 3) +DEFINE_BIT(CA_LP_CTRL0_RG_ARDMSUS_10_CA_LP_SEL, 4) +DEFINE_BIT(CA_LP_CTRL0_RG_ARCMD_RESETB_LP_SEL, 8) +DEFINE_BIT(CA_LP_CTRL0_RG_ARPI_RESETB_CA_LP_SEL, 9) +DEFINE_BIT(CA_LP_CTRL0_RG_CA_MS_SLV_LP_SEL, 12) +DEFINE_BIT(CA_LP_CTRL0_RG_ARDLL_PHDET_EN_CA_LP_SEL, 13) +DEFINE_BIT(CA_LP_CTRL0_RG_TX_ARCS_PULL_UP_LP_SEL, 15) +DEFINE_BIT(CA_LP_CTRL0_RG_RX_ARCMD_BIAS_EN_LP_SEL, 16) +DEFINE_BIT(CA_LP_CTRL0_DA_ARPI_CG_MCK_CA_LP_SEL, 17) +DEFINE_BIT(CA_LP_CTRL0_DA_ARPI_CG_MCK_FB2DLL_CA_LP_SEL, 18) +DEFINE_BIT(CA_LP_CTRL0_DA_ARPI_CG_MCTL_CA_LP_SEL, 19) +DEFINE_BIT(CA_LP_CTRL0_DA_ARPI_CG_FB_CA_LP_SEL, 20) +DEFINE_BIT(CA_LP_CTRL0_DA_ARPI_CG_CS_LP_SEL, 21) +DEFINE_BIT(CA_LP_CTRL0_DA_ARPI_CG_CLK_LP_SEL, 22) +DEFINE_BIT(CA_LP_CTRL0_DA_ARPI_CG_CMD_LP_SEL, 23) +DEFINE_BIT(CA_LP_CTRL0_DA_ARPI_CG_CLKIEN_LP_SEL, 24) +DEFINE_BIT(CA_LP_CTRL0_DA_ARPI_MPDIV_CG_CA_LP_SEL, 25) +DEFINE_BIT(CA_LP_CTRL0_RG_RX_ARCMD_VREF_EN_LP_SEL, 26) +DEFINE_BIT(CA_LP_CTRL0_DA_ARPI_MIDPI_EN_CA_LP_SEL, 27) +DEFINE_BIT(CA_LP_CTRL0_DA_ARPI_MIDPI_CKDIV4_EN_CA_LP_SEL, 28) + +/* DDRPHY_REG_MISC_LP_CTRL */ +DEFINE_BIT(MISC_LP_CTRL_RG_ARDMSUS_10, 0) +DEFINE_BIT(MISC_LP_CTRL_RG_ARDMSUS_10_LP_SEL, 1) +DEFINE_BIT(MISC_LP_CTRL_RG_RIMP_DMSUS_10, 2) +DEFINE_BIT(MISC_LP_CTRL_RG_RIMP_DMSUS_10_LP_SEL, 3) +DEFINE_BIT(MISC_LP_CTRL_RG_RRESETB_LP_SEL, 4) +DEFINE_BIT(MISC_LP_CTRL_RG_RPHYPLL_RESETB_LP_SEL, 5) +DEFINE_BIT(MISC_LP_CTRL_RG_RPHYPLL_EN_LP_SEL, 6) +DEFINE_BIT(MISC_LP_CTRL_RG_RCLRPLL_EN_LP_SEL, 7) +DEFINE_BIT(MISC_LP_CTRL_RG_RPHYPLL_ADA_MCK8X_EN_LP_SEL, 8) +DEFINE_BIT(MISC_LP_CTRL_RG_RPHYPLL_AD_MCK8X_EN_LP_SEL, 9) +DEFINE_BIT(MISC_LP_CTRL_RG_RPHYPLL_TOP_REV_0_LP_SEL, 10) +DEFINE_BIT(MISC_LP_CTRL_RG_SC_ARPI_RESETB_8X_SEQ_LP_SEL, 11) +DEFINE_BIT(MISC_LP_CTRL_RG_ADA_MCK8X_8X_SEQ_LP_SEL, 12) +DEFINE_BIT(MISC_LP_CTRL_RG_AD_MCK8X_8X_SEQ_LP_SEL, 13) +DEFINE_BIT(MISC_LP_CTRL_RG_MIDPI_EN_8X_SEQ_LP_SEL, 17) +DEFINE_BIT(MISC_LP_CTRL_RG_MIDPI_CKDIV4_EN_8X_SEQ_LP_SEL, 18) +DEFINE_BIT(MISC_LP_CTRL_RG_MCK8X_CG_SRC_LP_SEL, 19) +DEFINE_BIT(MISC_LP_CTRL_RG_MCK8X_CG_SRC_AND_LP_SEL, 20) + +/* DDRPHY_REG_MISC_CG_CTRL9 */ +DEFINE_BIT(MISC_CG_CTRL9_RG_M_CK_OPENLOOP_MODE_EN, 4) +DEFINE_BIT(MISC_CG_CTRL9_RG_MCK4X_I_OPENLOOP_MODE_EN, 8) +DEFINE_BIT(MISC_CG_CTRL9_RG_CG_DDR400_MCK4X_I_OFF, 9) +DEFINE_BIT(MISC_CG_CTRL9_RG_DDR400_MCK4X_I_FORCE_ON, 10) +DEFINE_BIT(MISC_CG_CTRL9_RG_MCK4X_I_FB_CK_CG_OFF, 11) +DEFINE_BIT(MISC_CG_CTRL9_RG_MCK4X_Q_OPENLOOP_MODE_EN, 12) +DEFINE_BIT(MISC_CG_CTRL9_RG_CG_DDR400_MCK4X_Q_OFF, 13) +DEFINE_BIT(MISC_CG_CTRL9_RG_DDR400_MCK4X_Q_FORCE_ON, 14) +DEFINE_BIT(MISC_CG_CTRL9_RG_MCK4X_Q_FB_CK_CG_OFF, 15) +DEFINE_BIT(MISC_CG_CTRL9_RG_MCK4X_O_OPENLOOP_MODE_EN, 16) +DEFINE_BIT(MISC_CG_CTRL9_RG_CG_DDR400_MCK4X_O_OFF, 17) +DEFINE_BIT(MISC_CG_CTRL9_RG_MCK4X_O_FB_CK_CG_OFF, 19) + +/* DDRPHY_REG_MISC_SHU_RX_CG_CTRL */ +DEFINE_BIT(MISC_SHU_RX_CG_CTRL_RX_DCM_OPT, 0) +DEFINE_BIT(MISC_SHU_RX_CG_CTRL_RX_APHY_CTRL_DCM_OPT, 1) +DEFINE_BIT(MISC_SHU_RX_CG_CTRL_RX_RODT_DCM_OPT, 2) +DEFINE_BIT(MISC_SHU_RX_CG_CTRL_RX_DQSIEN_STBCAL_CG_EN, 4) +DEFINE_BIT(MISC_SHU_RX_CG_CTRL_RX_DQSIEN_AUTOK_CG_EN, 5) +DEFINE_BIT(MISC_SHU_RX_CG_CTRL_RX_RDSEL_TRACKING_CG_EN, 8) +DEFINE_BIT(MISC_SHU_RX_CG_CTRL_RX_DQSIEN_RETRY_CG_EN, 9) +DEFINE_BIT(MISC_SHU_RX_CG_CTRL_RX_PRECAL_CG_EN, 10) +DEFINE_BITFIELD(MISC_SHU_RX_CG_CTRL_RX_DCM_EXT_DLY, 19, 16) +DEFINE_BITFIELD(MISC_SHU_RX_CG_CTRL_RX_DCM_WAIT_DLE_EXT_DLY, 23, 20) + +/* DDRPHY_REG_MISC_SHU_CG_CTRL0 */ +DEFINE_BITFIELD(MISC_SHU_CG_CTRL0_R_PHY_MCK_CG_CTRL, 31, 0) + +/* DDRPHY_REG_MISC_IMP_CTRL1 */ +DEFINE_BIT(MISC_IMP_CTRL1_RG_IMP_EN, 1) +DEFINE_BIT(MISC_IMP_CTRL1_RG_RIMP_DDR4_SEL, 2) +DEFINE_BIT(MISC_IMP_CTRL1_RG_RIMP_DDR3_SEL, 3) +DEFINE_BIT(MISC_IMP_CTRL1_RG_RIMP_BIAS_EN, 4) +DEFINE_BIT(MISC_IMP_CTRL1_RG_RIMP_ODT_EN, 5) +DEFINE_BIT(MISC_IMP_CTRL1_RG_RIMP_PRE_EN, 6) +DEFINE_BIT(MISC_IMP_CTRL1_RG_RIMP_VREF_EN, 7) +DEFINE_BIT(MISC_IMP_CTRL1_IMP_ABN_LAT_CLR, 14) +DEFINE_BIT(MISC_IMP_CTRL1_RG_RIMP_SUS_ECO_OPT, 31) + +/* DDRPHY_REG_MISC_CG_CTRL0 */ +DEFINE_BIT(MISC_CG_CTRL0_W_CHG_MEM, 0) +DEFINE_BITFIELD(MISC_CG_CTRL0_RESERVED_MISC_CG_CTRL0_BIT3_1, 3, 1) +DEFINE_BITFIELD(MISC_CG_CTRL0_CLK_MEM_SEL, 5, 4) +DEFINE_BIT(MISC_CG_CTRL0_RESERVED_MISC_CG_CTRL0_BIT7, 7) +DEFINE_BIT(MISC_CG_CTRL0_RG_CG_EMI_OFF_DISABLE, 8) +DEFINE_BIT(MISC_CG_CTRL0_RG_CG_DRAMC_OFF_DISABLE, 9) +DEFINE_BIT(MISC_CG_CTRL0_RG_CG_PHY_OFF_DIABLE, 10) +DEFINE_BIT(MISC_CG_CTRL0_RG_CG_COMB_OFF_DISABLE, 11) +DEFINE_BIT(MISC_CG_CTRL0_RG_CG_CMD_OFF_DISABLE, 12) +DEFINE_BIT(MISC_CG_CTRL0_RG_CG_COMB0_OFF_DISABLE, 13) +DEFINE_BIT(MISC_CG_CTRL0_RG_CG_COMB1_OFF_DISABLE, 14) +DEFINE_BIT(MISC_CG_CTRL0_RG_CG_RX_CMD_OFF_DISABLE, 15) +DEFINE_BIT(MISC_CG_CTRL0_RG_CG_RX_COMB0_OFF_DISABLE, 16) +DEFINE_BIT(MISC_CG_CTRL0_RG_CG_RX_COMB1_OFF_DISABLE, 17) +DEFINE_BIT(MISC_CG_CTRL0_RG_CG_IDLE_SYNC_EN, 18) +DEFINE_BIT(MISC_CG_CTRL0_RG_CG_INFRA_OFF_DISABLE, 19) +DEFINE_BIT(MISC_CG_CTRL0_RG_CG_DRAMC_CK_OFF, 20) +DEFINE_BIT(MISC_CG_CTRL0_RG_CG_NAO_FORCE_OFF, 22) +DEFINE_BIT(MISC_CG_CTRL0_RG_FREERUN_MCK_CG, 29) + +/* DDRPHY_REG_MISC_CKMUX_SEL */ +DEFINE_BIT(MISC_CKMUX_SEL_R_PHYCTRLMUX, 0) +DEFINE_BIT(MISC_CKMUX_SEL_R_PHYCTRLDCM, 1) +DEFINE_BIT(MISC_CKMUX_SEL_RG_52M_104M_SEL, 12) +DEFINE_BITFIELD(MISC_CKMUX_SEL_FMEM_CK_MUX, 19, 18) + +/* DDRPHY_REG_PHYPLL2 */ +DEFINE_BIT(PHYPLL2_RG_RPHYPLL_RESETB, 16) +DEFINE_BIT(PHYPLL2_RG_RPHYPLL_AD_MCK8X_EN, 21) +DEFINE_BIT(PHYPLL2_RG_RPHYPLL_ADA_MCK8X_EN, 22) + +/* DDRPHY_REG_PHYPLL0 */ +DEFINE_BIT(PHYPLL0_RG_RPHYPLL_EN, 31) + +/* DDRPHY_REG_SHU_B0_DLL_ARPI2 */ +DEFINE_BIT(SHU_B0_DLL_ARPI2_RG_ARPI_MPDIV_CG_B0, 10) +DEFINE_BIT(SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B0, 11) +DEFINE_BIT(SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQ_B0, 13) +DEFINE_BIT(SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQM_B0, 14) +DEFINE_BIT(SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQS_B0, 15) +DEFINE_BIT(SHU_B0_DLL_ARPI2_RG_ARPI_CG_FB_B0, 17) +DEFINE_BIT(SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCTL_B0, 19) +DEFINE_BIT(SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B0, 27) +DEFINE_BIT(SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_B0, 31) + +/* DDRPHY_REG_SHU_B1_DLL_ARPI2 */ +DEFINE_BIT(SHU_B1_DLL_ARPI2_RG_ARPI_MPDIV_CG_B1, 10) +DEFINE_BIT(SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B1, 11) +DEFINE_BIT(SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQ_B1, 13) +DEFINE_BIT(SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQM_B1, 14) +DEFINE_BIT(SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQS_B1, 15) +DEFINE_BIT(SHU_B1_DLL_ARPI2_RG_ARPI_CG_FB_B1, 17) +DEFINE_BIT(SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCTL_B1, 19) +DEFINE_BIT(SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B1, 27) +DEFINE_BIT(SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCK_B1, 31) + +/* DDRPHY_REG_SHU_PLL2 */ +DEFINE_BIT(SHU_PLL2_RG_RPHYPLL_ADA_MCK8X_EN_SHU, 0) + +/* DDRPHY_REG_B0_SHU_MIDPI_CTRL */ +DEFINE_BIT(B0_SHU_MIDPI_CTRL_MIDPI_ENABLE_B0, 0) +DEFINE_BIT(B0_SHU_MIDPI_CTRL_MIDPI_DIV4_ENABLE_B0, 1) + +/* DDRPHY_REG_B1_SHU_MIDPI_CTRL */ +DEFINE_BIT(B1_SHU_MIDPI_CTRL_MIDPI_ENABLE_B1, 0) +DEFINE_BIT(B1_SHU_MIDPI_CTRL_MIDPI_DIV4_ENABLE_B1, 1) + +/* DDRPHY_REG_CA_SHU_MIDPI_CTRL */ +DEFINE_BIT(CA_SHU_MIDPI_CTRL_MIDPI_ENABLE_CA, 0) +DEFINE_BIT(CA_SHU_MIDPI_CTRL_MIDPI_DIV4_ENABLE_CA, 1) + +/* DDRPHY_REG_CA_DLL_ARPI0 */ +DEFINE_BIT(CA_DLL_ARPI0_RG_ARPI_RESETB_CA, 3) + +/* DDRPHY_REG_B0_DLL_ARPI0 */ +DEFINE_BIT(B0_DLL_ARPI0_RG_ARPI_RESETB_B0, 3) + +/* DDRPHY_REG_B1_DLL_ARPI0 */ +DEFINE_BIT(B1_DLL_ARPI0_RG_ARPI_RESETB_B1, 3) + +/* DDRPHY_REG_MISC_CG_CTRL2 */ +DEFINE_BIT(MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG, 0) +DEFINE_BITFIELD(MISC_CG_CTRL2_RG_MEM_DCM_APB_SEL, 5, 1) +DEFINE_BIT(MISC_CG_CTRL2_RG_MEM_DCM_FORCE_ON, 6) +DEFINE_BIT(MISC_CG_CTRL2_RG_MEM_DCM_DCM_EN, 7) +DEFINE_BIT(MISC_CG_CTRL2_RG_MEM_DCM_DBC_EN, 8) +DEFINE_BITFIELD(MISC_CG_CTRL2_RG_MEM_DCM_DBC_CNT, 15, 9) +DEFINE_BITFIELD(MISC_CG_CTRL2_RG_MEM_DCM_FSEL, 20, 16) +DEFINE_BITFIELD(MISC_CG_CTRL2_RG_MEM_DCM_IDLE_FSEL, 25, 21) +DEFINE_BIT(MISC_CG_CTRL2_RG_MEM_DCM_FORCE_OFF, 26) +DEFINE_BIT(MISC_CG_CTRL2_RESERVED_MISC_CG_CTRL2_BIT27, 27) +DEFINE_BIT(MISC_CG_CTRL2_RG_PHY_CG_OFF_DISABLE, 28) +DEFINE_BIT(MISC_CG_CTRL2_RG_PIPE0_CG_OFF_DISABLE, 29) +DEFINE_BIT(MISC_CG_CTRL2_RESERVED_MISC_CG_CTRL2_BIT30, 30) +DEFINE_BIT(MISC_CG_CTRL2_RG_MEM_DCM_CG_OFF_DISABLE, 31) + +/* DDRPHY_REG_MISC_CTRL0 */ +DEFINE_BIT(MISC_CTRL0_R_DMDQSIEN_FIFO_EN, 0) +DEFINE_BIT(MISC_CTRL0_R_DMSTBEN_SYNCOPT, 2) +DEFINE_BIT(MISC_CTRL0_R_DMVALID_DLY_OPT, 4) +DEFINE_BIT(MISC_CTRL0_R_DMVALID_NARROW_IG, 5) +DEFINE_BITFIELD(MISC_CTRL0_R_DMVALID_DLY, 10, 8) +DEFINE_BIT(MISC_CTRL0_IMPCAL_CHAB_EN, 12) +DEFINE_BIT(MISC_CTRL0_IMPCAL_TRACK_DISABLE, 13) +DEFINE_BIT(MISC_CTRL0_IMPCAL_LP_ECO_OPT, 18) +DEFINE_BIT(MISC_CTRL0_IMPCAL_CDC_ECO_OPT, 19) +DEFINE_BIT(MISC_CTRL0_IDLE_DCM_CHB_CDC_ECO_OPT, 20) +DEFINE_BIT(MISC_CTRL0_R_DMSHU_PHYDCM_FORCEOFF, 27) +DEFINE_BIT(MISC_CTRL0_R_DQS0IEN_DIV4_CK_CG_CTRL, 28) +DEFINE_BIT(MISC_CTRL0_R_DQS1IEN_DIV4_CK_CG_CTRL, 29) +DEFINE_BIT(MISC_CTRL0_R_CLKIEN_DIV4_CK_CG_CTRL, 30) +DEFINE_BIT(MISC_CTRL0_R_STBENCMP_DIV4CK_EN, 31) + +/* DDRPHY_REG_MISC_RXDVS2 */ +DEFINE_BIT(MISC_RXDVS2_R_DMRXDVS_DEPTH_HALF, 0) +DEFINE_BIT(MISC_RXDVS2_R_DMRXDVS_SHUFFLE_CTRL_CG_IG, 8) +DEFINE_BIT(MISC_RXDVS2_R_DMRXDVS_DBG_MON_EN, 16) +DEFINE_BIT(MISC_RXDVS2_R_DMRXDVS_DBG_MON_CLR, 17) +DEFINE_BIT(MISC_RXDVS2_R_DMRXDVS_DBG_PAUSE_EN, 18) + +/* DDRPHY_REG_MISC_DVFS_EMI_CLK */ +DEFINE_BIT(MISC_DVFS_EMI_CLK_RG_DLL_SHUFFLE_DDRPHY, 24) + +/* DDRPHY_REG_B0_DQ10 */ +DEFINE_BIT(B0_DQ10_ARPI_CG_RK1_SRC_SEL_B0, 0) + +/* DDRPHY_REG_B1_DQ10 */ +DEFINE_BIT(B1_DQ10_ARPI_CG_RK1_SRC_SEL_B1, 0) + +/* DDRPHY_REG_MISC_DVFSCTL */ +DEFINE_BITFIELD(MISC_DVFSCTL_R_DVFS_PICG_MARGIN_NEW, 3, 0) +DEFINE_BITFIELD(MISC_DVFSCTL_R_DVFS_PICG_MARGIN2_NEW, 7, 4) +DEFINE_BITFIELD(MISC_DVFSCTL_R_DVFS_PICG_MARGIN3_NEW, 11, 8) +DEFINE_BITFIELD(MISC_DVFSCTL_R_DVFS_PICG_MARGIN4_NEW, 15, 12) +DEFINE_BIT(MISC_DVFSCTL_R_DMSHUFFLE_CHANGE_FREQ_OPT, 18) +DEFINE_BIT(MISC_DVFSCTL_R_SHUFFLE_PI_RESET_ENABLE, 26) +DEFINE_BIT(MISC_DVFSCTL_R_DVFS_PICG_POSTPONE, 27) +DEFINE_BITFIELD(MISC_DVFSCTL_R_DVFS_MCK8X_MARGIN, 31, 28) + +/* DDRPHY_REG_MISC_STBCAL1 */ +DEFINE_BIT(MISC_STBCAL1_STBCNT_SHU_RST_EN, 0) +DEFINE_BIT(MISC_STBCAL1_DIS_PI_TRACK_AS_NOT_RD, 2) +DEFINE_BIT(MISC_STBCAL1_STBCNT_MODESEL, 4) +DEFINE_BIT(MISC_STBCAL1_DQSIEN_7UI_EN, 5) +DEFINE_BIT(MISC_STBCAL1_STB_SHIFT_DTCOUT_IG, 6) +DEFINE_BIT(MISC_STBCAL1_STB_FLAGCLR_OPT, 8) +DEFINE_BIT(MISC_STBCAL1_STBCNT_SW_RST, 15) +DEFINE_BITFIELD(MISC_STBCAL1_STBCAL_FILTER, 31, 16) + +/* DDRPHY_REG_MISC_STBCAL2 */ +DEFINE_BIT(MISC_STBCAL2_STB_PIDLYCG_IG, 0) +DEFINE_BIT(MISC_STBCAL2_STB_UIDLYCG_IG, 1) +DEFINE_BITFIELD(MISC_STBCAL2_STB_DBG_EN, 7, 4) +DEFINE_BIT(MISC_STBCAL2_STB_DBG_CG_AO, 8) +DEFINE_BIT(MISC_STBCAL2_STB_DBG_UIPI_UPD_OPT, 9) +DEFINE_BIT(MISC_STBCAL2_DQSGCNT_BYP_REF, 10) +DEFINE_BIT(MISC_STBCAL2_STB_PICG_EARLY_1T_EN, 16) +DEFINE_BIT(MISC_STBCAL2_STB_STBENRST_EARLY_1T_EN, 17) +DEFINE_BIT(MISC_STBCAL2_STB_IG_XRANK_CG_RST, 18) +DEFINE_BIT(MISC_STBCAL2_STB_RST_BY_RANK, 19) +DEFINE_BIT(MISC_STBCAL2_DQSIEN_SELPH_BY_RANK_EN, 20) +DEFINE_BIT(MISC_STBCAL2_STB_GERRSTOP, 28) +DEFINE_BIT(MISC_STBCAL2_STB_GERR_RST, 29) +DEFINE_BIT(MISC_STBCAL2_STB_GERR_B01, 30) +DEFINE_BIT(MISC_STBCAL2_STB_GERR_B23, 31) + +/* DDRPHY_REG_MISC_SHU_STBCAL */ +DEFINE_BITFIELD(MISC_SHU_STBCAL_DQSIEN_DQSSTB_MODE, 13, 12) +DEFINE_BIT(MISC_SHU_STBCAL_DQSIEN_BURST_MODE, 14) +DEFINE_BIT(MISC_SHU_STBCAL_STBCALEN, 16) +DEFINE_BIT(MISC_SHU_STBCAL_STB_SELPHCALEN, 17) + +/* DDRPHY_REG_MISC_STBCAL */ +DEFINE_BIT(MISC_STBCAL_PIMASK_RKCHG_OPT, 0) +DEFINE_BIT(MISC_STBCAL_STBDLELAST_OPT, 4) +DEFINE_BITFIELD(MISC_STBCAL_STBDLELAST_PULSE, 11, 8) +DEFINE_BIT(MISC_STBCAL_STBDLELAST_FILTER, 12) +DEFINE_BIT(MISC_STBCAL_STBSTATE_OPT, 15) +DEFINE_BIT(MISC_STBCAL_PHYVALID_IG, 16) +DEFINE_BIT(MISC_STBCAL_SREF_DQSGUPD, 17) +DEFINE_BIT(MISC_STBCAL_RKCHGMASKDIS, 19) +DEFINE_BIT(MISC_STBCAL_PICGEN, 20) +DEFINE_BIT(MISC_STBCAL_REFUICHG, 21) +DEFINE_BIT(MISC_STBCAL_STBCAL2R, 23) +DEFINE_BIT(MISC_STBCAL_PICHGBLOCK_NORD, 26) +DEFINE_BIT(MISC_STBCAL_STB_DQIEN_IG, 27) +DEFINE_BIT(MISC_STBCAL_DQSIENCG_CHG_EN, 28) +DEFINE_BIT(MISC_STBCAL_DQSIENCG_NORMAL_EN, 29) +DEFINE_BIT(MISC_STBCAL_DQSIENMODE, 31) + +/* DDRPHY_REG_B0_PHY2 */ +DEFINE_BITFIELD(B0_PHY2_RG_RX_ARDQS_JM_SEL_B0, 7, 4) +DEFINE_BIT(B0_PHY2_RG_RX_ARDQS_JM_EN_B0, 8) +DEFINE_BITFIELD(B0_PHY2_RG_RX_ARDQS_JM_DLY_B0, 24, 16) +DEFINE_BIT(B0_PHY2_RG_RX_ARDQS_DQSIEN_UI_LEAD_LAG_EN_B0, 28) + +/* DDRPHY_REG_B1_PHY2 */ +DEFINE_BITFIELD(B1_PHY2_RG_RX_ARDQS_JM_SEL_B1, 7, 4) +DEFINE_BIT(B1_PHY2_RG_RX_ARDQS_JM_EN_B1, 8) +DEFINE_BITFIELD(B1_PHY2_RG_RX_ARDQS_JM_DLY_B1, 24, 16) +DEFINE_BIT(B1_PHY2_RG_RX_ARDQS_DQSIEN_UI_LEAD_LAG_EN_B1, 28) + +/* DDRPHY_REG_MISC_RX_IN_GATE_EN_CTRL */ +DEFINE_BIT(MISC_RX_IN_GATE_EN_CTRL_RX_IN_GATE_EN_OPT, 0) +DEFINE_BIT(MISC_RX_IN_GATE_EN_CTRL_RX_IN_GATE_EN_4BYTE_EN, 1) +DEFINE_BITFIELD(MISC_RX_IN_GATE_EN_CTRL_FIX_IN_GATE_EN, 11, 8) +DEFINE_BITFIELD(MISC_RX_IN_GATE_EN_CTRL_DIS_IN_GATE_EN, 15, 12) + +/* DDRPHY_REG_MISC_RX_IN_BUFF_EN_CTRL */ +DEFINE_BIT(MISC_RX_IN_BUFF_EN_CTRL_RX_IN_BUFF_EN_OPT, 0) +DEFINE_BIT(MISC_RX_IN_BUFF_EN_CTRL_RX_IN_BUFF_EN_4BYTE_EN, 1) +DEFINE_BITFIELD(MISC_RX_IN_BUFF_EN_CTRL_FIX_IN_BUFF_EN, 11, 8) +DEFINE_BITFIELD(MISC_RX_IN_BUFF_EN_CTRL_DIS_IN_BUFF_EN, 15, 12) + +/* DDRPHY_REG_B0_RXDVS0 */ +DEFINE_BIT(B0_RXDVS0_R_RX_RANKINSEL_B0, 0) +DEFINE_BITFIELD(B0_RXDVS0_R_RX_RANKINCTL_B0, 7, 4) +DEFINE_BIT(B0_RXDVS0_R_DMRXDVS_DQIENPRE_OPT_B0, 9) +DEFINE_BIT(B0_RXDVS0_R_DMRXDVS_CNTCMP_OPT_B0, 19) +DEFINE_BIT(B0_RXDVS0_R_HWRESTORE_ENA_B0, 22) +DEFINE_BIT(B0_RXDVS0_R_HWSAVE_MODE_ENA_B0, 24) +DEFINE_BIT(B0_RXDVS0_R_RX_DLY_TRACK_CG_EN_B0, 28) +DEFINE_BIT(B0_RXDVS0_R_RX_DLY_TRACK_SPM_CTRL_B0, 29) +DEFINE_BIT(B0_RXDVS0_R_RX_DLY_TRACK_ENA_B0, 31) + +/* DDRPHY_REG_B1_RXDVS0 */ +DEFINE_BIT(B1_RXDVS0_R_RX_RANKINSEL_B1, 0) +DEFINE_BITFIELD(B1_RXDVS0_R_RX_RANKINCTL_B1, 7, 4) +DEFINE_BIT(B1_RXDVS0_R_DMRXDVS_DQIENPRE_OPT_B1, 9) +DEFINE_BIT(B1_RXDVS0_R_DMRXDVS_CNTCMP_OPT_B1, 19) +DEFINE_BIT(B1_RXDVS0_R_HWRESTORE_ENA_B1, 22) +DEFINE_BIT(B1_RXDVS0_R_HWSAVE_MODE_ENA_B1, 24) +DEFINE_BIT(B1_RXDVS0_R_RX_DLY_TRACK_CG_EN_B1, 28) +DEFINE_BIT(B1_RXDVS0_R_RX_DLY_TRACK_SPM_CTRL_B1, 29) +DEFINE_BIT(B1_RXDVS0_R_RX_DLY_TRACK_ENA_B1, 31) + +/* DDRPHY_REG_RK_B0_RXDVS3 */ +DEFINE_BITFIELD(RK_B0_RXDVS3_RG_RK0_ARDQ_MIN_DLY_B0, 7, 0) +DEFINE_BITFIELD(RK_B0_RXDVS3_RG_RK0_ARDQ_MAX_DLY_B0, 15, 8) + +/* DDRPHY_REG_RK_B0_RXDVS4 */ +DEFINE_BITFIELD(RK_B0_RXDVS4_RG_RK0_ARDQS0_MIN_DLY_B0, 8, 0) +DEFINE_BITFIELD(RK_B0_RXDVS4_RG_RK0_ARDQS0_MAX_DLY_B0, 24, 16) + +/* DDRPHY_REG_RK_B0_RXDVS2 */ +DEFINE_BITFIELD(RK_B0_RXDVS2_R_RK0_RX_DLY_FAL_DQS_SCALE_B0, 17, 16) +DEFINE_BITFIELD(RK_B0_RXDVS2_R_RK0_RX_DLY_FAL_DQ_SCALE_B0, 19, 18) +DEFINE_BIT(RK_B0_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B0, 23) +DEFINE_BITFIELD(RK_B0_RXDVS2_R_RK0_RX_DLY_RIS_DQS_SCALE_B0, 25, 24) +DEFINE_BITFIELD(RK_B0_RXDVS2_R_RK0_RX_DLY_RIS_DQ_SCALE_B0, 27, 26) +DEFINE_BIT(RK_B0_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B0, 28) +DEFINE_BIT(RK_B0_RXDVS2_R_RK0_DVS_FDLY_MODE_B0, 29) +DEFINE_BITFIELD(RK_B0_RXDVS2_R_RK0_DVS_MODE_B0, 31, 30) + +/* DDRPHY_REG_RK_B0_RXDVS1 */ +DEFINE_BITFIELD(RK_B0_RXDVS1_R_RK0_B0_DVS_TH_LAG, 15, 0) +DEFINE_BITFIELD(RK_B0_RXDVS1_R_RK0_B0_DVS_TH_LEAD, 31, 16) + +/* DDRPHY_REG_RK_B1_RXDVS3 */ +DEFINE_BITFIELD(RK_B1_RXDVS3_RG_RK0_ARDQ_MIN_DLY_B1, 7, 0) +DEFINE_BITFIELD(RK_B1_RXDVS3_RG_RK0_ARDQ_MAX_DLY_B1, 15, 8) + +/* DDRPHY_REG_RK_B1_RXDVS4 */ +DEFINE_BITFIELD(RK_B1_RXDVS4_RG_RK0_ARDQS0_MIN_DLY_B1, 8, 0) +DEFINE_BITFIELD(RK_B1_RXDVS4_RG_RK0_ARDQS0_MAX_DLY_B1, 24, 16) + +/* DDRPHY_REG_RK_B1_RXDVS2 */ +DEFINE_BITFIELD(RK_B1_RXDVS2_R_RK0_RX_DLY_FAL_DQS_SCALE_B1, 17, 16) +DEFINE_BITFIELD(RK_B1_RXDVS2_R_RK0_RX_DLY_FAL_DQ_SCALE_B1, 19, 18) +DEFINE_BIT(RK_B1_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B1, 23) +DEFINE_BITFIELD(RK_B1_RXDVS2_R_RK0_RX_DLY_RIS_DQS_SCALE_B1, 25, 24) +DEFINE_BITFIELD(RK_B1_RXDVS2_R_RK0_RX_DLY_RIS_DQ_SCALE_B1, 27, 26) +DEFINE_BIT(RK_B1_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B1, 28) +DEFINE_BIT(RK_B1_RXDVS2_R_RK0_DVS_FDLY_MODE_B1, 29) +DEFINE_BITFIELD(RK_B1_RXDVS2_R_RK0_DVS_MODE_B1, 31, 30) + +/* DDRPHY_REG_RK_B1_RXDVS1 */ +DEFINE_BITFIELD(RK_B1_RXDVS1_R_RK0_B1_DVS_TH_LAG, 15, 0) +DEFINE_BITFIELD(RK_B1_RXDVS1_R_RK0_B1_DVS_TH_LEAD, 31, 16) + +/* DDRPHY_REG_MISC_CG_CTRL1 */ +DEFINE_BITFIELD(MISC_CG_CTRL1_R_DVS_DIV4_CG_CTRL, 31, 0) + +/* DDRPHY_REG_B0_RXDVS1 */ +DEFINE_BIT(B0_RXDVS1_F_LEADLAG_TRACK_B0, 15) +DEFINE_BIT(B0_RXDVS1_R_DMRXDVS_UPD_CLR_NORD_B0, 17) + +/* DDRPHY_REG_B1_RXDVS1 */ +DEFINE_BIT(B1_RXDVS1_F_LEADLAG_TRACK_B1, 15) +DEFINE_BIT(B1_RXDVS1_R_DMRXDVS_UPD_CLR_NORD_B1, 17) + +/* DRAMC_REG_DLLFRZ_CTRL */ +DEFINE_BIT(DLLFRZ_CTRL_INPUTRXTRACK_BLOCK, 0) +DEFINE_BIT(DLLFRZ_CTRL_DLLFRZ_MON_PBREF_OPT, 1) +DEFINE_BIT(DLLFRZ_CTRL_DLLFRZ_BLOCKLONG, 2) +DEFINE_BIT(DLLFRZ_CTRL_DLLFRZ, 7) +DEFINE_BIT(DLLFRZ_CTRL_UPDBYWR, 8) + +/* DDRPHY_REG_MISC_RG_DFS_CTRL */ +DEFINE_BIT(MISC_RG_DFS_CTRL_SPM_DVFS_CONTROL_SEL, 0) +DEFINE_BIT(MISC_RG_DFS_CTRL_RG_DPY_RXDLY_TRACK_EN, 2) +DEFINE_BITFIELD(MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL_SRAM, 7, 4) +DEFINE_BIT(MISC_RG_DFS_CTRL_RG_DR_SRAM_RESTORE, 8) +DEFINE_BIT(MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL_SRAM_LATCH, 9) +DEFINE_BIT(MISC_RG_DFS_CTRL_RG_DR_SRAM_LOAD, 10) +DEFINE_BITFIELD(MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL, 17, 16) +DEFINE_BIT(MISC_RG_DFS_CTRL_RG_PHYPLL_SHU_EN, 18) +DEFINE_BIT(MISC_RG_DFS_CTRL_RG_PHYPLL2_SHU_EN, 19) +DEFINE_BIT(MISC_RG_DFS_CTRL_RG_DR_SHU_EN, 23) +DEFINE_BIT(MISC_RG_DFS_CTRL_RG_DDRPHY_FB_CK_EN, 24) + +/* DDRPHY_REG_MISC_CTRL4 */ +DEFINE_BIT(MISC_CTRL4_R_OPT2_MPDIV_CG, 0) +DEFINE_BIT(MISC_CTRL4_R_OPT2_CG_MCK, 1) +DEFINE_BIT(MISC_CTRL4_R_OPT2_CG_DQM, 2) +DEFINE_BIT(MISC_CTRL4_R_OPT2_CG_DQS, 3) +DEFINE_BIT(MISC_CTRL4_R_OPT2_CG_DQ, 4) +DEFINE_BIT(MISC_CTRL4_R_OPT2_CG_DQSIEN, 5) +DEFINE_BIT(MISC_CTRL4_R_OPT2_CG_CMD, 6) +DEFINE_BIT(MISC_CTRL4_R_OPT2_CG_CLK, 7) +DEFINE_BIT(MISC_CTRL4_R_OPT2_CG_CS, 8) + +/* DDRPHY_REG_MISC_CTRL3 */ +DEFINE_BITFIELD(MISC_CTRL3_ARPI_CG_CMD_OPT, 1, 0) +DEFINE_BITFIELD(MISC_CTRL3_ARPI_CG_CLK_OPT, 3, 2) +DEFINE_BIT(MISC_CTRL3_ARPI_MPDIV_CG_CA_OPT, 4) +DEFINE_BIT(MISC_CTRL3_ARPI_CG_MCK_CA_OPT, 5) +DEFINE_BIT(MISC_CTRL3_ARPI_CG_MCTL_CA_OPT, 6) +DEFINE_BITFIELD(MISC_CTRL3_ARPI_CG_DQ_OPT, 17, 16) +DEFINE_BITFIELD(MISC_CTRL3_ARPI_CG_DQS_OPT, 19, 18) +DEFINE_BIT(MISC_CTRL3_ARPI_MPDIV_CG_DQ_OPT, 20) +DEFINE_BIT(MISC_CTRL3_ARPI_CG_MCK_DQ_OPT, 21) +DEFINE_BIT(MISC_CTRL3_ARPI_CG_MCTL_DQ_OPT, 22) +DEFINE_BIT(MISC_CTRL3_R_DDRPHY_COMB_CG_IG, 26) +DEFINE_BIT(MISC_CTRL3_R_DDRPHY_RX_PIPE_CG_IG, 27) + +/* DDRPHY_REG_MISC_CG_CTRL5 */ +DEFINE_BIT(MISC_CG_CTRL5_R_DQ1_DLY_DCM_EN, 16) +DEFINE_BIT(MISC_CG_CTRL5_R_DQ0_DLY_DCM_EN, 17) +DEFINE_BIT(MISC_CG_CTRL5_R_CA_DLY_DCM_EN, 18) +DEFINE_BIT(MISC_CG_CTRL5_R_DQ1_PI_DCM_EN, 20) +DEFINE_BIT(MISC_CG_CTRL5_R_DQ0_PI_DCM_EN, 21) +DEFINE_BIT(MISC_CG_CTRL5_R_CA_PI_DCM_EN, 22) + +/* DRAMC_REG_RX_CG_SET0 */ +DEFINE_BIT(RX_CG_SET0_RDATCKAR, 30) +DEFINE_BIT(RX_CG_SET0_RDYCKAR, 31) + +/* DRAMC_REG_SREF_DPD_CTRL */ +DEFINE_BIT(SREF_DPD_CTRL_LPSM_BYPASS_B, 7) +DEFINE_BIT(SREF_DPD_CTRL_CLR_EN, 9) +DEFINE_BIT(SREF_DPD_CTRL_SELFREF_AUTOSAVE_EN, 10) +DEFINE_BIT(SREF_DPD_CTRL_SREF_PRD_OPT, 11) +DEFINE_BIT(SREF_DPD_CTRL_SREF_CG_OPT, 12) +DEFINE_BIT(SREF_DPD_CTRL_SRFPD_DIS, 13) +DEFINE_BITFIELD(SREF_DPD_CTRL_SREFDLY, 19, 16) +DEFINE_BIT(SREF_DPD_CTRL_SREF_HW_EN, 22) +DEFINE_BIT(SREF_DPD_CTRL_CMDCKAR, 26) +DEFINE_BIT(SREF_DPD_CTRL_GT_SYNC_MASK, 29) +DEFINE_BIT(SREF_DPD_CTRL_DAT_SYNC_MASK, 30) +DEFINE_BIT(SREF_DPD_CTRL_PHY_SYNC_MASK, 31) + +/* DRAMC_REG_DCM_CTRL0 */ +DEFINE_BIT(DCM_CTRL0_BCLKAR, 2) + +/* DRAMC_REG_TX_CG_SET0 */ +DEFINE_BIT(TX_CG_SET0_SELPH_4LCG_DIS, 0) +DEFINE_BIT(TX_CG_SET0_SELPH_CG_DIS, 1) +DEFINE_BIT(TX_CG_SET0_DWCLKRUN, 2) +DEFINE_BIT(TX_CG_SET0_WDATA_CG_DIS, 3) +DEFINE_BIT(TX_CG_SET0_TX_ATK_CLKRUN, 4) +DEFINE_BIT(TX_CG_SET0_PSELAR, 31) + +/* DRAMC_REG_SCSMCTRL_CG */ +DEFINE_BIT(SCSMCTRL_CG_SCARB_SM_CGAR, 30) +DEFINE_BIT(SCSMCTRL_CG_SCSM_CGAR, 31) + +/* DRAMC_REG_TX_TRACKING_SET0 */ +DEFINE_BIT(TX_TRACKING_SET0_TX_TRACKING_OPT, 15) +DEFINE_BIT(TX_TRACKING_SET0_SW_UP_TX_NOW_CASE, 16) +DEFINE_BIT(TX_TRACKING_SET0_TXUIPI_CAL_CGAR, 17) +DEFINE_BIT(TX_TRACKING_SET0_SHU_PRELOAD_TX_START, 18) +DEFINE_BIT(TX_TRACKING_SET0_SHU_PRELOAD_TX_HW, 19) +DEFINE_BIT(TX_TRACKING_SET0_HMRRSEL_CGAR, 21) +DEFINE_BIT(TX_TRACKING_SET0_RDDQSOSC_CGAR, 22) + +/* DRAMC_REG_ZQ_SET0 */ +DEFINE_BITFIELD(ZQ_SET0_ZQCSOP, 7, 0) +DEFINE_BITFIELD(ZQ_SET0_ZQCSAD, 15, 8) +DEFINE_BITFIELD(ZQ_SET0_ZQCS_MASK_SEL, 18, 16) +DEFINE_BIT(ZQ_SET0_ZQCS_MASK_SEL_CGAR, 19) +DEFINE_BIT(ZQ_SET0_ZQMASK_CGAR, 20) +DEFINE_BIT(ZQ_SET0_ZQCSMASK_OPT, 21) +DEFINE_BIT(ZQ_SET0_ZQCSMASK, 29) +DEFINE_BIT(ZQ_SET0_ZQCSDUAL, 30) + +/* DRAMC_REG_ACTIMING_CTRL */ +DEFINE_BIT(ACTIMING_CTRL_SEQCLKRUN3, 0) +DEFINE_BIT(ACTIMING_CTRL_SEQCLKRUN2, 1) +DEFINE_BIT(ACTIMING_CTRL_SEQCLKRUN, 2) +DEFINE_BIT(ACTIMING_CTRL_REFNA_OPT, 6) +DEFINE_BIT(ACTIMING_CTRL_REFBW_FREN, 8) +DEFINE_BIT(ACTIMING_CTRL_CLKWITRFC, 9) +DEFINE_BIT(ACTIMING_CTRL_TMRRICHKDIS, 21) +DEFINE_BIT(ACTIMING_CTRL_TMRRIBYRK_DIS, 22) +DEFINE_BIT(ACTIMING_CTRL_MRRIOPT, 23) +DEFINE_BIT(ACTIMING_CTRL_FASTW2R, 24) + +/* DRAMC_REG_CLKAR */ +DEFINE_BITFIELD(CLKAR_REQQUE_PACG_DIS, 14, 0) +DEFINE_BIT(CLKAR_DCMREF_OPT, 24) +DEFINE_BIT(CLKAR_REQQUECLKRUN, 27) + +/* DRAMC_REG_DRAMC_PD_CTRL */ +DEFINE_BIT(DRAMC_PD_CTRL_DCMEN, 0) +DEFINE_BIT(DRAMC_PD_CTRL_DCMEN2, 1) +DEFINE_BIT(DRAMC_PD_CTRL_DCMENNOTRFC, 2) +DEFINE_BIT(DRAMC_PD_CTRL_PHYGLUECLKRUN, 3) +DEFINE_BIT(DRAMC_PD_CTRL_COMBPHY_CLKENSAME, 5) +DEFINE_BIT(DRAMC_PD_CTRL_MIOCKCTRLOFF, 6) +DEFINE_BIT(DRAMC_PD_CTRL_PG_DCM_OPT, 9) +DEFINE_BIT(DRAMC_PD_CTRL_APHYCKCG_FIXOFF, 12) +DEFINE_BIT(DRAMC_PD_CTRL_TCKFIXON, 13) +DEFINE_BIT(DRAMC_PD_CTRL_PHYCLKDYNGEN, 30) +DEFINE_BIT(DRAMC_PD_CTRL_COMBCLKCTRL, 31) + +/* DRAMC_REG_TEST2_A3 */ +DEFINE_BIT(TEST2_A3_ADRDECEN_TARKMODE, 5) +DEFINE_BIT(TEST2_A3_TESTAUDPAT, 7) +DEFINE_BIT(TEST2_A3_TESTCLKRUN, 8) +DEFINE_BIT(TEST2_A3_PAT_SHIFT_SW_EN, 11) +DEFINE_BIT(TEST2_A3_TEST2_PAT_SHIFT, 15) +DEFINE_BIT(TEST2_A3_TEST_AID_EN, 16) +DEFINE_BIT(TEST2_A3_HFIDPAT, 17) +DEFINE_BIT(TEST2_A3_AUTO_GEN_PAT, 18) +DEFINE_BIT(TEST2_A3_TEST2WREN2_HW_EN, 28) +DEFINE_BIT(TEST2_A3_TEST1, 29) +DEFINE_BIT(TEST2_A3_TEST2R, 30) +DEFINE_BIT(TEST2_A3_TEST2W, 31) + +/* DRAMC_REG_DVFS_CTRL0 */ +DEFINE_BIT(DVFS_CTRL0_R_DRAMC_CHA, 0) +DEFINE_BIT(DVFS_CTRL0_SHU_PHYRST_SEL, 1) +DEFINE_BIT(DVFS_CTRL0_R_DVFS_SREF_OPT, 5) +DEFINE_BIT(DVFS_CTRL0_HWSET_WLRL, 8) +DEFINE_BIT(DVFS_CTRL0_MR13_SHU_EN, 9) +DEFINE_BIT(DVFS_CTRL0_VRCG_EN, 10) +DEFINE_BIT(DVFS_CTRL0_DVFS_RXFIFOST_SKIP, 13) +DEFINE_BIT(DVFS_CTRL0_DVFS_NOQUEFLUSH_EN, 15) +DEFINE_BIT(DVFS_CTRL0_DVFS_CKE_OPT, 16) +DEFINE_BIT(DVFS_CTRL0_DVFS_CG_OPT, 19) +DEFINE_BIT(DVFS_CTRL0_SCARB_PRI_OPT, 20) +DEFINE_BIT(DVFS_CTRL0_R_DMDVFSMRW_EN, 21) +DEFINE_BIT(DVFS_CTRL0_MRWWOPRA, 22) +DEFINE_BIT(DVFS_CTRL0_DVFS_SYNC_MASK, 27) + +/* DDRPHY_REG_MISC_DUTYSCAN1 */ +DEFINE_BIT(MISC_DUTYSCAN1_REG_SW_RST, 0) +DEFINE_BIT(MISC_DUTYSCAN1_RX_EYE_SCAN_EN, 1) +DEFINE_BIT(MISC_DUTYSCAN1_RX_MIOCK_JIT_EN, 2) +DEFINE_BIT(MISC_DUTYSCAN1_RX_EYE_SCAN_CG_EN, 3) +DEFINE_BIT(MISC_DUTYSCAN1_EYESCAN_DQ_SYNC_EN, 8) +DEFINE_BIT(MISC_DUTYSCAN1_EYESCAN_NEW_DQ_SYNC_EN, 9) +DEFINE_BIT(MISC_DUTYSCAN1_EYESCAN_DQS_SYNC_EN, 10) +DEFINE_BIT(MISC_DUTYSCAN1_EYESCAN_DQS_OPT, 11) +DEFINE_BIT(MISC_DUTYSCAN1_DQSERRCNT_DIS, 14) + +/* DDRPHY_REG_SHU_B0_DQ8 */ +DEFINE_BITFIELD(SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0, 14, 0) +DEFINE_BIT(SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0, 15) +DEFINE_BIT(SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0, 19) +DEFINE_BIT(SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0, 20) +DEFINE_BIT(SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0, 21) +DEFINE_BIT(SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0, 22) +DEFINE_BIT(SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0, 23) +DEFINE_BIT(SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0, 24) +DEFINE_BIT(SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0, 26) +DEFINE_BIT(SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0, 27) +DEFINE_BIT(SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0, 28) +DEFINE_BIT(SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0, 29) +DEFINE_BIT(SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0, 30) +DEFINE_BIT(SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0, 31) + +/* DDRPHY_REG_SHU_B1_DQ8 */ +DEFINE_BITFIELD(SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1, 14, 0) +DEFINE_BIT(SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1, 15) +DEFINE_BIT(SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1, 19) +DEFINE_BIT(SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1, 20) +DEFINE_BIT(SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1, 21) +DEFINE_BIT(SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1, 22) +DEFINE_BIT(SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1, 23) +DEFINE_BIT(SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1, 24) +DEFINE_BIT(SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1, 26) +DEFINE_BIT(SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1, 27) +DEFINE_BIT(SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1, 28) +DEFINE_BIT(SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1, 29) +DEFINE_BIT(SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1, 30) +DEFINE_BIT(SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1, 31) + +/* DRAMC_REG_DDRCOMMON0 */ +DEFINE_BIT(DDRCOMMON0_DISSTOP26M, 0) +DEFINE_BIT(DDRCOMMON0_TRCDEARLY, 3) +DEFINE_BIT(DDRCOMMON0_BK8EN, 8) +DEFINE_BIT(DDRCOMMON0_LPDDR4EN, 19) +DEFINE_BIT(DDRCOMMON0_LPDDR5EN, 20) + +/* DRAMC_REG_RX_SET0 */ +DEFINE_BIT(RX_SET0_RDATRST, 0) +DEFINE_BIT(RX_SET0_PRE_DLE_VLD_OPT, 1) +DEFINE_BITFIELD(RX_SET0_DATLAT_PDLE_TH, 4, 2) +DEFINE_BIT(RX_SET0_SMRR_UPD_OLD, 6) +DEFINE_BIT(RX_SET0_DM4TO1MODE, 31) + +/* DRAMC_REG_REFCTRL0 */ +DEFINE_BITFIELD(REFCTRL0_PBREF_BK_REFA_NUM, 2, 0) +DEFINE_BIT(REFCTRL0_PBREF_BK_REFA_ENA, 3) +DEFINE_BIT(REFCTRL0_DMPGVLD_IG, 8) +DEFINE_BIT(REFCTRL0_KEEP_PBREF_OPT, 9) +DEFINE_BIT(REFCTRL0_KEEP_PBREF, 10) +DEFINE_BITFIELD(REFCTRL0_DISBYREFNUM, 14, 12) +DEFINE_BIT(REFCTRL0_PBREF_DISBYREFNUM, 16) +DEFINE_BIT(REFCTRL0_PBREF_DISBYRATE, 17) +DEFINE_BITFIELD(REFCTRL0_REF_PREGATE_CNT, 27, 24) +DEFINE_BIT(REFCTRL0_REFDIS, 29) + +/* DRAMC_REG_REFCTRL1 */ +DEFINE_BIT(REFCTRL1_PB2AB_OPT, 0) +DEFINE_BIT(REFCTRL1_REFPENDINGINT_OPT1, 3) +DEFINE_BIT(REFCTRL1_REF_QUE_AUTOSAVE_EN, 5) +DEFINE_BIT(REFCTRL1_REFPEND_OPT1, 6) +DEFINE_BIT(REFCTRL1_REFPEND_OPT2, 7) +DEFINE_BIT(REFCTRL1_REFPB2AB_IGZQCS, 8) +DEFINE_BIT(REFCTRL1_REFRATE_MON_CLR, 11) +DEFINE_BIT(REFCTRL1_REF_OVERHEAD_PBR2PB_ENA, 13) +DEFINE_BIT(REFCTRL1_REF_OVERHEAD_RATE_REFAL_ENA, 14) +DEFINE_BIT(REFCTRL1_REF_OVERHEAD_RATE_REFPB_ENA, 15) +DEFINE_BIT(REFCTRL1_REF_OVERHEAD_SLOW_REFAL_ENA, 24) +DEFINE_BIT(REFCTRL1_REF_OVERHEAD_SLOW_REFPB_ENA, 25) +DEFINE_BIT(REFCTRL1_REF_OVERHEAD_ALL_REFAL_ENA, 26) +DEFINE_BIT(REFCTRL1_REF_OVERHEAD_ALL_REFPB_ENA, 27) + +/* DRAMC_REG_REFCTRL2 */ +DEFINE_BITFIELD(REFCTRL2_MR4INT_TH, 4, 0) +DEFINE_BITFIELD(REFCTRL2_REF_OVERHEAD_RATE, 31, 16) + +/* DRAMC_REG_DRAMCTRL */ +DEFINE_BIT(DRAMCTRL_CTOREQ_HPRI_OPT, 0) +DEFINE_BIT(DRAMCTRL_ADRDECEN, 2) +DEFINE_BIT(DRAMCTRL_ADRBIT3DEC, 3) +DEFINE_BIT(DRAMCTRL_ALL_BLOCK_CTO_ALE_DBG_EN, 8) +DEFINE_BIT(DRAMCTRL_SELFREF_BLOCK_CTO_ALE_DBG_EN, 9) +DEFINE_BIT(DRAMCTRL_DVFS_BLOCK_CTO_ALE_DBG_EN, 10) +DEFINE_BIT(DRAMCTRL_AG0MWR, 12) +DEFINE_BIT(DRAMCTRL_DYNMWREN, 13) +DEFINE_BIT(DRAMCTRL_PREALL_OPTION, 19) +DEFINE_BIT(DRAMCTRL_REQQUE_THD_EN, 26) +DEFINE_BIT(DRAMCTRL_SHORTQ_OPT, 31) + +/* DRAMC_REG_ARBCTL */ +DEFINE_BITFIELD(ARBCTL_MAXPENDCNT, 7, 0) +DEFINE_BIT(ARBCTL_WDATACNTDIS, 9) + +/* DRAMC_REG_DRAM_CLK_CTRL */ +DEFINE_BIT(DRAM_CLK_CTRL_CLK_EN, 0) + +/* DRAMC_REG_RKCFG */ +DEFINE_BIT(RKCFG_MRS2RK, 10) +DEFINE_BIT(RKCFG_CKE2RANK, 12) + +/* DRAMC_REG_CKECTRL */ +DEFINE_BIT(CKECTRL_CKE2RANK_OPT3, 1) +DEFINE_BIT(CKECTRL_CKE1FIXON, 4) +DEFINE_BIT(CKECTRL_CKE1FIXOFF, 5) +DEFINE_BIT(CKECTRL_CKEFIXON, 6) +DEFINE_BIT(CKECTRL_CKEFIXOFF, 7) +DEFINE_BIT(CKECTRL_CKE2RANK_OPT5, 8) +DEFINE_BIT(CKECTRL_CKE2RANK_OPT6, 9) +DEFINE_BIT(CKECTRL_CKE2RANK_OPT7, 10) +DEFINE_BIT(CKECTRL_CKE2RANK_OPT8, 11) +DEFINE_BIT(CKECTRL_CKETIMER_SEL, 13) +DEFINE_BIT(CKECTRL_FASTWAKE_SEL, 14) +DEFINE_BIT(CKECTRL_CKEWAKE_SEL, 15) +DEFINE_BIT(CKECTRL_CKEPBDIS, 22) +DEFINE_BIT(CKECTRL_CKELCKFIX, 23) +DEFINE_BIT(CKECTRL_CKE2RANK_OPT2, 24) +DEFINE_BIT(CKECTRL_CKE2RANK_OPT, 25) +DEFINE_BIT(CKECTRL_RUNTIMEMRRCKEFIX, 27) +DEFINE_BIT(CKECTRL_RUNTIMEMRRMIODIS, 28) +DEFINE_BIT(CKECTRL_CKEON, 31) + +/* DRAMC_REG_SCHEDULER_COM */ +DEFINE_BIT(SCHEDULER_COM_RWOFOEN, 0) +DEFINE_BIT(SCHEDULER_COM_RWHPRICTL, 4) +DEFINE_BIT(SCHEDULER_COM_RWSPLIT, 5) +DEFINE_BIT(SCHEDULER_COM_MWHPRIEN, 6) +DEFINE_BIT(SCHEDULER_COM_DISRDPHASE1, 8) +DEFINE_BIT(SCHEDULER_COM_PBR2PBR_OPT, 9) + +/* DRAMC_REG_PERFCTL0 */ +DEFINE_BIT(PERFCTL0_EBG_EN, 0) +DEFINE_BIT(PERFCTL0_RWHPRIEN, 8) +DEFINE_BIT(PERFCTL0_RWLLATEN, 9) +DEFINE_BIT(PERFCTL0_RWAGEEN, 10) +DEFINE_BIT(PERFCTL0_EMILLATEN, 11) +DEFINE_BIT(PERFCTL0_WFLUSHEN, 14) +DEFINE_BIT(PERFCTL0_REORDER_MODE, 18) +DEFINE_BIT(PERFCTL0_REORDEREN, 19) + +/* DRAMC_REG_HW_MRR_FUN */ +DEFINE_BIT(HW_MRR_FUN_TMRR_ENA, 0) +DEFINE_BIT(HW_MRR_FUN_TRCDMRR_EN, 1) +DEFINE_BIT(HW_MRR_FUN_TRPMRR_EN, 2) +DEFINE_BIT(HW_MRR_FUN_MANTMRR_EN, 3) +DEFINE_BIT(HW_MRR_FUN_TR2MRR_ENA, 4) +DEFINE_BIT(HW_MRR_FUN_R2MRRHPRICTL, 5) +DEFINE_BIT(HW_MRR_FUN_MRR_HW_HIPRI, 11) + +/* DRAMC_REG_MPC_OPTION */ +DEFINE_BIT(MPC_OPTION_MPCRKEN, 17) + +/* DRAMC_REG_MPC_CTRL */ +DEFINE_BIT(MPC_CTRL_MPC_BLOCKALE_OPT, 0) +DEFINE_BIT(MPC_CTRL_MPC_BLOCKALE_OPT1, 1) +DEFINE_BIT(MPC_CTRL_MPC_BLOCKALE_OPT2, 2) +DEFINE_BIT(MPC_CTRL_ZQ_BLOCKALE_OPT, 3) +DEFINE_BIT(MPC_CTRL_REFR_BLOCKEN, 5) +DEFINE_BIT(MPC_CTRL_RTMRW_HPRI_EN, 6) +DEFINE_BIT(MPC_CTRL_RTSWCMD_HPRI_EN, 7) + +/* DRAMC_REG_HMR4 */ +DEFINE_BIT(HMR4_HMR4_TOG_OPT, 1) +DEFINE_BIT(HMR4_SPDR_MR4_OPT, 2) +DEFINE_BIT(HMR4_HMR4_BYTEMODE_EN, 5) +DEFINE_BIT(HMR4_MR4INT_LIMITEN, 6) +DEFINE_BIT(HMR4_REFR_PERIOD_OPT, 7) +DEFINE_BIT(HMR4_REFRDIS, 8) +DEFINE_BIT(HMR4_REFRCNT_OPT, 9) + +/* DRAMC_REG_RK_TEST2_A1 */ +DEFINE_BITFIELD(RK_TEST2_A1_TEST2_BASE, 31, 3) + +/* DRAMC_REG_TEST2_A2 */ +DEFINE_BITFIELD(TEST2_A2_TEST2_OFF, 31, 4) + +/* DRAMC_REG_TEST2_A4 */ +DEFINE_BITFIELD(TEST2_A4_TESTAUDINC, 4, 0) +DEFINE_BIT(TEST2_A4_TESTSSOPAT, 6) +DEFINE_BIT(TEST2_A4_TESTSSOXTALKPAT, 7) +DEFINE_BITFIELD(TEST2_A4_TESTAUDINIT, 12, 8) +DEFINE_BIT(TEST2_A4_TESTAUDBITINV, 14) +DEFINE_BIT(TEST2_A4_TESTAUDMODE, 15) +DEFINE_BIT(TEST2_A4_TESTXTALKPAT, 16) +DEFINE_BIT(TEST2_A4_TEST_REQ_LEN1, 17) +DEFINE_BITFIELD(TEST2_A4_TESTAGENTRK, 25, 24) +DEFINE_BITFIELD(TEST2_A4_TESTAGENTRKSEL, 30, 28) + +/* DRAMC_REG_CMD_DEC_CTRL0 */ +DEFINE_BIT(CMD_DEC_CTRL0_SELPH_CMD_CG_DIS, 4) +DEFINE_BITFIELD(CMD_DEC_CTRL0_RKMODE, 10, 8) + +/* DRAMC_REG_MISCTL0 */ +DEFINE_BIT(MISCTL0_REFP_ARBMASK_PBR2PBR_ENA, 0) +DEFINE_BIT(MISCTL0_REFP_ARBMASK_PBR2PBR_PA_DIS, 1) +DEFINE_BITFIELD(MISCTL0_PG_WAKEUP_OPT, 15, 14) +DEFINE_BIT(MISCTL0_PAGDIS, 17) +DEFINE_BIT(MISCTL0_REFA_ARB_EN2, 19) +DEFINE_BIT(MISCTL0_PBC_ARB_E1T, 23) +DEFINE_BIT(MISCTL0_PBC_ARB_EN, 24) +DEFINE_BIT(MISCTL0_EMIPREEN, 27) +DEFINE_BIT(MISCTL0_REFP_ARB_EN2, 31) + +/* DRAMC_REG_SCSMCTRL */ +DEFINE_BIT(SCSMCTRL_SC_PG_UPD_OPT, 0) +DEFINE_BIT(SCSMCTRL_SC_PG_MAN_DIS, 1) + +/* DRAMC_REG_SHUCTRL1 */ +DEFINE_BITFIELD(SHUCTRL1_FC_PRDCNT, 7, 0) +DEFINE_BITFIELD(SHUCTRL1_CKFSPE_PRDCNT, 15, 8) +DEFINE_BITFIELD(SHUCTRL1_CKFSPX_PRDCNT, 23, 16) +DEFINE_BITFIELD(SHUCTRL1_VRCGEN_PRDCNT, 31, 24) + +/* DRAMC_REG_DVFS_TIMING_CTRL1 */ +DEFINE_BITFIELD(DVFS_TIMING_CTRL1_SHU_PERIOD_GO_ZERO_CNT, 7, 0) +DEFINE_BITFIELD(DVFS_TIMING_CTRL1_DMSHU_CNT, 21, 16) + +/* DRAMC_REG_REFPEND1 */ +DEFINE_BITFIELD(REFPEND1_MPENDREFCNT_TH0, 3, 0) +DEFINE_BITFIELD(REFPEND1_MPENDREFCNT_TH1, 7, 4) +DEFINE_BITFIELD(REFPEND1_MPENDREFCNT_TH2, 11, 8) +DEFINE_BITFIELD(REFPEND1_MPENDREFCNT_TH3, 15, 12) +DEFINE_BITFIELD(REFPEND1_MPENDREFCNT_TH4, 19, 16) +DEFINE_BITFIELD(REFPEND1_MPENDREFCNT_TH5, 23, 20) +DEFINE_BITFIELD(REFPEND1_MPENDREFCNT_TH6, 27, 24) +DEFINE_BITFIELD(REFPEND1_MPENDREFCNT_TH7, 31, 28) + +/* DRAMC_REG_CBT_WLEV_CTRL1 */ +DEFINE_BITFIELD(CBT_WLEV_CTRL1_CATRAINLAT, 14, 11) +DEFINE_BITFIELD(CBT_WLEV_CTRL1_CATRAIN_INTV, 22, 15) +DEFINE_BITFIELD(CBT_WLEV_CTRL1_TCMDO1LAT, 30, 23) + +/* DRAMC_REG_TX_SET0 */ +DEFINE_BITFIELD(TX_SET0_TXRANK, 1, 0) +DEFINE_BIT(TX_SET0_TXRANKFIX, 2) +DEFINE_BIT(TX_SET0_OE_DOWNGRADE, 6) +DEFINE_BIT(TX_SET0_WPRE2T, 22) +DEFINE_BIT(TX_SET0_DRSCLR_EN, 24) +DEFINE_BIT(TX_SET0_DRSCLR_RK0_EN, 25) +DEFINE_BIT(TX_SET0_RK_SCINPUT_OPT, 30) + +/* DRAMC_REG_DQSOSCR */ +DEFINE_BIT(DQSOSCR_ARUIDQ_SW, 7) +DEFINE_BIT(DQSOSCR_SREF_TXUI_RELOAD_OPT, 23) +DEFINE_BIT(DQSOSCR_DQSOSCRDIS, 24) +DEFINE_BIT(DQSOSCR_R_DMDQS2DQ_FILT_OPT, 26) +DEFINE_BIT(DQSOSCR_SREF_TXPI_RELOAD_OPT, 27) +DEFINE_BIT(DQSOSCR_DQSOSC_CALEN, 31) + +/* DRAMC_REG_DUMMY_RD */ +DEFINE_BIT(DUMMY_RD_DUMMY_RD_SW, 4) +DEFINE_BIT(DUMMY_RD_DMY_WR_DBG, 6) +DEFINE_BIT(DUMMY_RD_DMY_RD_DBG, 7) +DEFINE_BIT(DUMMY_RD_DRS_SELFWAKE_DMYRD_DIS, 15) +DEFINE_BITFIELD(DUMMY_RD_RANK_NUM, 17, 16) +DEFINE_BIT(DUMMY_RD_DUMMY_RD_EN, 20) +DEFINE_BIT(DUMMY_RD_SREF_DMYRD_EN, 21) +DEFINE_BIT(DUMMY_RD_DQSG_DMYRD_EN, 22) +DEFINE_BIT(DUMMY_RD_DQSG_DMYWR_EN, 23) +DEFINE_BIT(DUMMY_RD_DUMMY_RD_PA_OPT, 24) +DEFINE_BIT(DUMMY_RD_DMYRD_REORDER_DIS, 27) + +/* DRAMC_REG_DUMMY_RD_INTV */ +DEFINE_BIT(DUMMY_RD_INTV_DUMMY_RD_CNT0, 0) +DEFINE_BIT(DUMMY_RD_INTV_DUMMY_RD_CNT1, 1) +DEFINE_BIT(DUMMY_RD_INTV_DUMMY_RD_CNT2, 2) +DEFINE_BIT(DUMMY_RD_INTV_DUMMY_RD_CNT3, 3) +DEFINE_BIT(DUMMY_RD_INTV_DUMMY_RD_CNT4, 4) +DEFINE_BIT(DUMMY_RD_INTV_DUMMY_RD_CNT5, 5) +DEFINE_BIT(DUMMY_RD_INTV_DUMMY_RD_CNT6, 6) +DEFINE_BIT(DUMMY_RD_INTV_DUMMY_RD_CNT7, 7) + +/* DRAMC_REG_RK_DQSOSC */ +DEFINE_BIT(RK_DQSOSC_RK0_BYTE_MODE, 29) +DEFINE_BIT(RK_DQSOSC_DQSOSCR_RK0EN, 30) + +/* DRAMC_REG_TX_FREQ_RATIO_OLD_MODE0 */ +DEFINE_BIT(TX_FREQ_RATIO_OLD_MODE0_SHUFFLE_LEVEL_MODE_SELECT, 31) + +/* DRAMC_REG_SWCMD_CTRL1 */ +DEFINE_BIT(SWCMD_CTRL1_RDDQC_LP_ENB, 2) +DEFINE_BIT(SWCMD_CTRL1_WRFIFO_MODE2, 31) + +/* DRAMC_REG_DBG_CMDDEC_CMDSEL0 */ +DEFINE_BIT(DBG_CMDDEC_CMDSEL0_RANK0_10GBEN, 0) +DEFINE_BIT(DBG_CMDDEC_CMDSEL0_RANK1_10GBEN, 1) + +/* DRAMC_REG_DBIWR_PROTECT */ +DEFINE_BIT(DBIWR_PROTECT_DBIWR_IMP_EN, 0) +DEFINE_BIT(DBIWR_PROTECT_DBIWR_PINMUX_EN, 1) +DEFINE_BITFIELD(DBIWR_PROTECT_DBIWR_OPT_B0, 23, 16) +DEFINE_BITFIELD(DBIWR_PROTECT_DBIWR_OPT_B1, 31, 24) + +/* DDRPHY_REG_MISC_SRAM_DMA0 */ +DEFINE_BIT(MISC_SRAM_DMA0_SW_DMA_FIRE, 0) +DEFINE_BIT(MISC_SRAM_DMA0_SW_MODE, 1) +DEFINE_BIT(MISC_SRAM_DMA0_APB_WR_MODE, 2) +DEFINE_BIT(MISC_SRAM_DMA0_SRAM_WR_MODE, 3) +DEFINE_BITFIELD(MISC_SRAM_DMA0_SW_SHU_LEVEL_SRAM, 7, 4) +DEFINE_BITFIELD(MISC_SRAM_DMA0_SW_SHU_LEVEL_APB, 11, 8) +DEFINE_BITFIELD(MISC_SRAM_DMA0_PENABLE_LAT_WR, 15, 14) +DEFINE_BIT(MISC_SRAM_DMA0_KEEP_SRAM_ARB_ENA, 16) +DEFINE_BIT(MISC_SRAM_DMA0_KEEP_APB_ARB_ENA, 17) +DEFINE_BIT(MISC_SRAM_DMA0_DMA_TIMER_EN, 18) +DEFINE_BIT(MISC_SRAM_DMA0_SW_STEP_EN_MODE, 23) +DEFINE_BITFIELD(MISC_SRAM_DMA0_APB_SLV_SEL, 29, 28) + +/* DDRPHY_MD32_REG_SSPM_MCLK_DIV */ +DEFINE_BIT(SSPM_MCLK_DIV_MCLK_DCM_EN, 8) + +/* DDRPHY_REG_CA_CMD7 */ +DEFINE_BIT(CA_CMD7_RG_TX_ARCLKB_PULL_DN, 0) +DEFINE_BIT(CA_CMD7_RG_TX_ARCLKB_PULL_UP, 1) +DEFINE_BIT(CA_CMD7_RG_TX_ARCLK_PULL_DN, 2) +DEFINE_BIT(CA_CMD7_RG_TX_ARCLK_PULL_UP, 3) +DEFINE_BIT(CA_CMD7_RG_TX_ARCS0_PULL_DN, 4) +DEFINE_BIT(CA_CMD7_RG_TX_ARCS0_PULL_UP, 5) +DEFINE_BIT(CA_CMD7_RG_TX_ARCMD_PULL_DN, 6) +DEFINE_BIT(CA_CMD7_RG_TX_ARCMD_PULL_UP, 7) +DEFINE_BIT(CA_CMD7_RG_TX_ARCLKB_PULL_DN_LP4Y, 16) + +/* DDRPHY_REG_B0_DQ7 */ +DEFINE_BIT(B0_DQ7_RG_TX_ARDQS0B_PULL_DN_B0, 0) +DEFINE_BIT(B0_DQ7_RG_TX_ARDQS0B_PULL_UP_B0, 1) +DEFINE_BIT(B0_DQ7_RG_TX_ARDQS0_PULL_DN_B0, 2) +DEFINE_BIT(B0_DQ7_RG_TX_ARDQS0_PULL_UP_B0, 3) +DEFINE_BIT(B0_DQ7_RG_TX_ARDQM0_PULL_DN_B0, 4) +DEFINE_BIT(B0_DQ7_RG_TX_ARDQM0_PULL_UP_B0, 5) +DEFINE_BIT(B0_DQ7_RG_TX_ARDQ_PULL_DN_B0, 6) +DEFINE_BIT(B0_DQ7_RG_TX_ARDQ_PULL_UP_B0, 7) +DEFINE_BIT(B0_DQ7_RG_TX_ARDQS0B_PULL_DN_B0_LP4Y, 16) + +/* DDRPHY_REG_B1_DQ7 */ +DEFINE_BIT(B1_DQ7_RG_TX_ARDQS0B_PULL_DN_B1, 0) +DEFINE_BIT(B1_DQ7_RG_TX_ARDQS0B_PULL_UP_B1, 1) +DEFINE_BIT(B1_DQ7_RG_TX_ARDQS0_PULL_DN_B1, 2) +DEFINE_BIT(B1_DQ7_RG_TX_ARDQS0_PULL_UP_B1, 3) +DEFINE_BIT(B1_DQ7_RG_TX_ARDQM0_PULL_DN_B1, 4) +DEFINE_BIT(B1_DQ7_RG_TX_ARDQM0_PULL_UP_B1, 5) +DEFINE_BIT(B1_DQ7_RG_TX_ARDQ_PULL_DN_B1, 6) +DEFINE_BIT(B1_DQ7_RG_TX_ARDQ_PULL_UP_B1, 7) +DEFINE_BIT(B1_DQ7_RG_TX_ARDQS0B_PULL_DN_B1_LP4Y, 16) + +/* DDRPHY_REG_B0_DQ11 */ +DEFINE_BIT(B0_DQ11_DMY_DQ11_B0, 0) + +/* DDRPHY_REG_B1_DQ11 */ +DEFINE_BIT(B1_DQ11_DMY_DQ11_B1, 0) + +/* DDRPHY_REG_MISC_SRAM_DMA1 */ +DEFINE_BITFIELD(MISC_SRAM_DMA1_SPM_RESTORE_STEP_EN, 16, 0) +DEFINE_BIT(MISC_SRAM_DMA1_R_APB_DMA_DBG_ACCESS, 19) +DEFINE_BITFIELD(MISC_SRAM_DMA1_R_APB_DMA_DBG_LEVEL, 23, 20) + +/* DDRPHY_REG_MISC_CG_CTRL7 */ +DEFINE_BIT(MISC_CG_CTRL7_CK_BFE_DCM_EN, 11) +DEFINE_BIT(MISC_CG_CTRL7_ARMCTL_CK_OUT_CG_SEL, 16) + +/* DDRPHY_REG_MISC_DVFSCTL2 */ +DEFINE_BIT(MISC_DVFSCTL2_RG_TOPCK_FMEM_CK_BLOCK_DURING_DFS, 3) +DEFINE_BIT(MISC_DVFSCTL2_RG_DLL_SHUFFLE, 4) +DEFINE_BIT(MISC_DVFSCTL2_RG_ADA_MCK8X_EN_SHUFFLE, 5) +DEFINE_BIT(MISC_DVFSCTL2_RG_MRW_AFTER_DFS, 8) +DEFINE_BIT(MISC_DVFSCTL2_R_DVFS_CDC_OPTION, 9) +DEFINE_BIT(MISC_DVFSCTL2_R_DVFS_DLL_CHA, 12) +DEFINE_BIT(MISC_DVFSCTL2_R_CDC_MUX_SEL_OPTION, 13) +DEFINE_BIT(MISC_DVFSCTL2_R_DVFS_PARK_N, 14) +DEFINE_BIT(MISC_DVFSCTL2_R_DVFS_OPTION, 15) +DEFINE_BIT(MISC_DVFSCTL2_R_DVFS_CLK_CHG_OK_SEL, 29) +DEFINE_BIT(MISC_DVFSCTL2_R_DVFS_SYNC_MODULE_RST_SEL, 31) + +/* DDRPHY_REG_MISC_DVFSCTL3 */ +DEFINE_BIT(MISC_DVFSCTL3_RG_PHY_ST_DELAY_AFT_CHG_TO_MCLK, 4) +DEFINE_BIT(MISC_DVFSCTL3_RG_PHY_ST_DELAY_BEF_CHG_TO_MCLK, 5) +DEFINE_BIT(MISC_DVFSCTL3_RG_PHY_ST_DELAY_AFT_CHG_TO_BCLK, 6) +DEFINE_BIT(MISC_DVFSCTL3_RG_PHY_ST_DELAY_BEF_CHG_TO_BCLK, 7) +DEFINE_BITFIELD(MISC_DVFSCTL3_RG_DVFS_MEM_CK_SEL_DESTI, 9, 8) +DEFINE_BITFIELD(MISC_DVFSCTL3_RG_DVFS_MEM_CK_SEL_SOURCE, 11, 10) +DEFINE_BITFIELD(MISC_DVFSCTL3_RG_CNT_PHY_ST_DELAY_AFT_CHG_TO_MCLK, 17, 12) +DEFINE_BITFIELD(MISC_DVFSCTL3_RG_CNT_PHY_ST_DELAY_AFT_CHG_TO_BCLK, 27, 22) +DEFINE_BITFIELD(MISC_DVFSCTL3_RG_CNT_PHY_ST_DELAY_BEF_CHG_TO_BCLK, 31, 28) + +/* DDRPHY_REG_MISC_CLK_CTRL */ +DEFINE_BIT(MISC_CLK_CTRL_DVFS_MEM_CK_MUX_UPDATE_EN, 0) +DEFINE_BIT(MISC_CLK_CTRL_DVFS_CLK_MEM_SEL, 1) +DEFINE_BITFIELD(MISC_CLK_CTRL_DVFS_MEM_CK_MUX_SEL, 10, 9) +DEFINE_BITFIELD(MISC_CLK_CTRL_DVFS_MEM_CK_MUX_SEL_MODE, 13, 12) + +/* DDRPHY_REG_MISC_SHU_OPT */ +DEFINE_BIT(MISC_SHU_OPT_R_DQB0_SHU_PHY_GATING_RESETB_SPM_EN, 0) +DEFINE_BITFIELD(MISC_SHU_OPT_R_DQB0_SHU_PHDET_SPM_EN, 3, 2) +DEFINE_BIT(MISC_SHU_OPT_R_DQB1_SHU_PHY_GATING_RESETB_SPM_EN, 8) +DEFINE_BITFIELD(MISC_SHU_OPT_R_DQB1_SHU_PHDET_SPM_EN, 11, 10) +DEFINE_BIT(MISC_SHU_OPT_R_CA_SHU_PHY_GATING_RESETB_SPM_EN, 16) +DEFINE_BITFIELD(MISC_SHU_OPT_R_CA_SHU_PHDET_SPM_EN, 19, 18) + +/* DRAMC_REG_SHU_SELPH_CA1 */ +DEFINE_BITFIELD(SHU_SELPH_CA1_TXDLY_CS, 2, 0) +DEFINE_BITFIELD(SHU_SELPH_CA1_TXDLY_CKE, 6, 4) +DEFINE_BITFIELD(SHU_SELPH_CA1_TXDLY_ODT, 10, 8) +DEFINE_BITFIELD(SHU_SELPH_CA1_TXDLY_RESET, 14, 12) +DEFINE_BITFIELD(SHU_SELPH_CA1_TXDLY_WE, 18, 16) +DEFINE_BITFIELD(SHU_SELPH_CA1_TXDLY_CAS, 22, 20) +DEFINE_BITFIELD(SHU_SELPH_CA1_TXDLY_RAS, 26, 24) +DEFINE_BITFIELD(SHU_SELPH_CA1_TXDLY_CS1, 30, 28) + +/* DRAMC_REG_SHU_SELPH_CA2 */ +DEFINE_BITFIELD(SHU_SELPH_CA2_TXDLY_BA0, 2, 0) +DEFINE_BITFIELD(SHU_SELPH_CA2_TXDLY_BA1, 6, 4) +DEFINE_BITFIELD(SHU_SELPH_CA2_TXDLY_BA2, 10, 8) +DEFINE_BITFIELD(SHU_SELPH_CA2_TXDLY_CKE1, 26, 24) + +/* DRAMC_REG_SHU_SELPH_CA3 */ +DEFINE_BITFIELD(SHU_SELPH_CA3_TXDLY_RA0, 2, 0) +DEFINE_BITFIELD(SHU_SELPH_CA3_TXDLY_RA1, 6, 4) +DEFINE_BITFIELD(SHU_SELPH_CA3_TXDLY_RA2, 10, 8) +DEFINE_BITFIELD(SHU_SELPH_CA3_TXDLY_RA3, 14, 12) +DEFINE_BITFIELD(SHU_SELPH_CA3_TXDLY_RA4, 18, 16) +DEFINE_BITFIELD(SHU_SELPH_CA3_TXDLY_RA5, 22, 20) +DEFINE_BITFIELD(SHU_SELPH_CA3_TXDLY_RA6, 26, 24) +DEFINE_BITFIELD(SHU_SELPH_CA3_TXDLY_RA7, 30, 28) + +/* DRAMC_REG_SHU_SELPH_CA4 */ +DEFINE_BITFIELD(SHU_SELPH_CA4_TXDLY_RA8, 2, 0) +DEFINE_BITFIELD(SHU_SELPH_CA4_TXDLY_RA9, 6, 4) +DEFINE_BITFIELD(SHU_SELPH_CA4_TXDLY_RA10, 10, 8) +DEFINE_BITFIELD(SHU_SELPH_CA4_TXDLY_RA11, 14, 12) +DEFINE_BITFIELD(SHU_SELPH_CA4_TXDLY_RA12, 18, 16) +DEFINE_BITFIELD(SHU_SELPH_CA4_TXDLY_RA13, 22, 20) +DEFINE_BITFIELD(SHU_SELPH_CA4_TXDLY_RA14, 26, 24) +DEFINE_BITFIELD(SHU_SELPH_CA4_TXDLY_RA15, 30, 28) + +/* DRAMC_REG_SHU_SELPH_CA5 */ +DEFINE_BITFIELD(SHU_SELPH_CA5_DLY_CS, 2, 0) +DEFINE_BITFIELD(SHU_SELPH_CA5_DLY_CKE, 6, 4) +DEFINE_BITFIELD(SHU_SELPH_CA5_DLY_ODT, 10, 8) +DEFINE_BITFIELD(SHU_SELPH_CA5_DLY_RESET, 14, 12) +DEFINE_BITFIELD(SHU_SELPH_CA5_DLY_WE, 18, 16) +DEFINE_BITFIELD(SHU_SELPH_CA5_DLY_CAS, 22, 20) +DEFINE_BITFIELD(SHU_SELPH_CA5_DLY_RAS, 26, 24) +DEFINE_BITFIELD(SHU_SELPH_CA5_DLY_CS1, 30, 28) + +/* DRAMC_REG_SHU_SELPH_CA6 */ +DEFINE_BITFIELD(SHU_SELPH_CA6_DLY_BA0, 2, 0) +DEFINE_BITFIELD(SHU_SELPH_CA6_DLY_BA1, 6, 4) +DEFINE_BITFIELD(SHU_SELPH_CA6_DLY_BA2, 10, 8) +DEFINE_BITFIELD(SHU_SELPH_CA6_DLY_CKE1, 26, 24) + +/* DRAMC_REG_SHU_SELPH_CA7 */ +DEFINE_BITFIELD(SHU_SELPH_CA7_DLY_RA0, 2, 0) +DEFINE_BITFIELD(SHU_SELPH_CA7_DLY_RA1, 6, 4) +DEFINE_BITFIELD(SHU_SELPH_CA7_DLY_RA2, 10, 8) +DEFINE_BITFIELD(SHU_SELPH_CA7_DLY_RA3, 14, 12) +DEFINE_BITFIELD(SHU_SELPH_CA7_DLY_RA4, 18, 16) +DEFINE_BITFIELD(SHU_SELPH_CA7_DLY_RA5, 22, 20) +DEFINE_BITFIELD(SHU_SELPH_CA7_DLY_RA6, 26, 24) +DEFINE_BITFIELD(SHU_SELPH_CA7_DLY_RA7, 30, 28) + +/* DRAMC_REG_SHU_SELPH_CA8 */ +DEFINE_BITFIELD(SHU_SELPH_CA8_DLY_RA8, 2, 0) +DEFINE_BITFIELD(SHU_SELPH_CA8_DLY_RA9, 6, 4) +DEFINE_BITFIELD(SHU_SELPH_CA8_DLY_RA10, 10, 8) +DEFINE_BITFIELD(SHU_SELPH_CA8_DLY_RA11, 14, 12) +DEFINE_BITFIELD(SHU_SELPH_CA8_DLY_RA12, 18, 16) +DEFINE_BITFIELD(SHU_SELPH_CA8_DLY_RA13, 22, 20) +DEFINE_BITFIELD(SHU_SELPH_CA8_DLY_RA14, 26, 24) +DEFINE_BITFIELD(SHU_SELPH_CA8_DLY_RA15, 30, 28) + +/* DDRPHY_REG_SHU_MISC_DRVING2 */ +DEFINE_BITFIELD(SHU_MISC_DRVING2_CMDDRVN1, 4, 0) +DEFINE_BITFIELD(SHU_MISC_DRVING2_CMDDRVP1, 9, 5) +DEFINE_BITFIELD(SHU_MISC_DRVING2_CMDDRVN2, 14, 10) +DEFINE_BITFIELD(SHU_MISC_DRVING2_CMDDRVP2, 19, 15) +DEFINE_BITFIELD(SHU_MISC_DRVING2_DQDRVN1, 24, 20) +DEFINE_BITFIELD(SHU_MISC_DRVING2_DQDRVP1, 29, 25) +DEFINE_BIT(SHU_MISC_DRVING2_DIS_IMPCAL_ODT_EN, 31) + +/* DDRPHY_REG_SHU_MISC_IMPCAL1 */ +DEFINE_BITFIELD(SHU_MISC_IMPCAL1_IMPCAL_CHKCYCLE, 2, 0) +DEFINE_BITFIELD(SHU_MISC_IMPCAL1_IMPDRVP, 8, 4) +DEFINE_BITFIELD(SHU_MISC_IMPCAL1_IMPDRVN, 16, 12) +DEFINE_BITFIELD(SHU_MISC_IMPCAL1_IMPCAL_CALEN_CYCLE, 19, 17) +DEFINE_BITFIELD(SHU_MISC_IMPCAL1_IMPCALCNT, 27, 20) +DEFINE_BITFIELD(SHU_MISC_IMPCAL1_IMPCAL_CALICNT, 31, 28) + +/* DDRPHY_REG_SHU_CA_CMD12 */ +DEFINE_BITFIELD(SHU_CA_CMD12_RG_RIMP_REV, 7, 0) +DEFINE_BITFIELD(SHU_CA_CMD12_RG_RIMP_VREF_SEL_ODTN, 14, 8) +DEFINE_BITFIELD(SHU_CA_CMD12_RG_RIMP_VREF_SEL_DRVN, 22, 16) +DEFINE_BIT(SHU_CA_CMD12_RG_RIMP_DRV05, 23) +DEFINE_BITFIELD(SHU_CA_CMD12_RG_RIMP_VREF_SEL_DRVP, 30, 24) +DEFINE_BIT(SHU_CA_CMD12_RG_RIMP_UNTERM_EN, 31) + +/* DDRPHY_REG_MISC_SHU_IMPEDAMCE_UPD_DIS1 */ +DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_DQS_DRVP_UPD_DIS, 0) +DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_DQS_DRVN_UPD_DIS, 1) +DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_DQS_ODTN_UPD_DIS, 2) +DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_DQ_DRVP_UPD_DIS, 4) +DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_DQ_DRVN_UPD_DIS, 5) +DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_DQ_ODTN_UPD_DIS, 6) +DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_DRVP_UPD_DIS, 8) +DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_DRVN_UPD_DIS, 9) +DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_ODTN_UPD_DIS, 10) +DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_CS_DRVP_UPD_DIS, 12) +DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_CS_DRVN_UPD_DIS, 13) +DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_CS_ODTN_UPD_DIS, 14) +DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD1_DRVP_UPD_DIS, 16) +DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD1_DRVN_UPD_DIS, 17) +DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD1_ODTN_UPD_DIS, 18) +DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD2_DRVP_UPD_DIS, 20) +DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD2_DRVN_UPD_DIS, 21) +DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD2_ODTN_UPD_DIS, 22) +DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_DRVP_UPD_DIS, 28) +DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_DRVN_UPD_DIS, 29) +DEFINE_BIT(MISC_SHU_IMPEDAMCE_UPD_DIS1_ODTN_UPD_DIS, 30) + +/* DDRPHY_REG_SHU_MISC_DRVING6 */ +DEFINE_BITFIELD(SHU_MISC_DRVING6_IMP_TXDLY_CMD, 5, 0) + +/* DRAMC_REG_SHU_COMMON0 */ +DEFINE_BIT(SHU_COMMON0_FREQDIV4, 0) +DEFINE_BIT(SHU_COMMON0_FDIV2, 1) +DEFINE_BIT(SHU_COMMON0_DM64BITEN, 4) +DEFINE_BIT(SHU_COMMON0_BL4, 10) +DEFINE_BIT(SHU_COMMON0_BC4OTF, 12) + +/* DRAMC_REG_SHU_ACTIMING_CONF */ +DEFINE_BITFIELD(SHU_ACTIMING_CONF_SCINTV, 5, 0) +DEFINE_BITFIELD(SHU_ACTIMING_CONF_REFBW_FR, 25, 16) +DEFINE_BIT(SHU_ACTIMING_CONF_TREFBWIG, 31) + +/* DRAMC_REG_SHU_DCM_CTRL0 */ +DEFINE_BIT(SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT, 7) +DEFINE_BITFIELD(SHU_DCM_CTRL0_DPHY_CMD_CLKEN_EXTCNT, 10, 8) +DEFINE_BITFIELD(SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL, 15, 12) +DEFINE_BITFIELD(SHU_DCM_CTRL0_APHYPI_CKCGL_CNT, 19, 16) +DEFINE_BITFIELD(SHU_DCM_CTRL0_APHYPI_CKCGH_CNT, 23, 20) +DEFINE_BIT(SHU_DCM_CTRL0_FASTWAKE2, 29) +DEFINE_BIT(SHU_DCM_CTRL0_FASTWAKE, 31) + +/* DRAMC_REG_SHU_CONF0 */ +DEFINE_BITFIELD(SHU_CONF0_DMPGTIM, 6, 0) +DEFINE_BIT(SHU_CONF0_ADVPREEN, 7) +DEFINE_BIT(SHU_CONF0_PBREFEN, 8) +DEFINE_BITFIELD(SHU_CONF0_REFTHD, 15, 12) + +/* DRAMC_REG_SHU_MATYPE */ +DEFINE_BITFIELD(SHU_MATYPE_MATYPE, 1, 0) + +/* DRAMC_REG_SHU_SCHEDULER */ +DEFINE_BIT(SHU_SCHEDULER_DUALSCHEN, 2) + +/* DRAMC_REG_SHU_TX_SET0 */ +DEFINE_BITFIELD(SHU_TX_SET0_DQOE_CNT, 3, 0) +DEFINE_BIT(SHU_TX_SET0_DQOE_OPT, 4) +DEFINE_BITFIELD(SHU_TX_SET0_TXUPD_SEL, 7, 6) +DEFINE_BITFIELD(SHU_TX_SET0_TXUPD_W2R_SEL, 10, 8) +DEFINE_BIT(SHU_TX_SET0_DBIWR, 12) +DEFINE_BIT(SHU_TX_SET0_WDATRGO, 13) +DEFINE_BIT(SHU_TX_SET0_WPST1P5T, 15) +DEFINE_BITFIELD(SHU_TX_SET0_OE_EXT2UI, 24, 22) +DEFINE_BITFIELD(SHU_TX_SET0_DQS2DQ_FILT_PITHRD, 30, 25) + +/* DDRPHY_REG_MISC_SHU_STBCAL1 */ +DEFINE_BIT(MISC_SHU_STBCAL1_STB_UPDMASK_EN, 11) +DEFINE_BITFIELD(MISC_SHU_STBCAL1_STB_UPDMASKCYC, 15, 12) +DEFINE_BIT(MISC_SHU_STBCAL1_DQSINCTL_PRE_SEL, 16) +DEFINE_BITFIELD(MISC_SHU_STBCAL1_STB_PI_TRACKING_RATIO, 25, 20) + +/* DDRPHY_REG_MISC_SHU_STBCAL */ +DEFINE_BITFIELD(MISC_SHU_STBCAL_DMSTBLAT, 3, 0) +DEFINE_BITFIELD(MISC_SHU_STBCAL_PICGLAT, 6, 4) +DEFINE_BIT(MISC_SHU_STBCAL_DQSG_MODE, 8) +DEFINE_BIT(MISC_SHU_STBCAL_DQSIEN_PICG_MODE, 9) + +/* DDRPHY_REG_MISC_SHU_RANKCTL */ +DEFINE_BITFIELD(MISC_SHU_RANKCTL_RANKINCTL_RXDLY, 3, 0) +DEFINE_BIT(MISC_SHU_RANKCTL_RANK_RXDLY_OPT, 4) +DEFINE_BIT(MISC_SHU_RANKCTL_RANKSEL_SELPH_FRUN, 15) +DEFINE_BITFIELD(MISC_SHU_RANKCTL_RANKINCTL_STB, 19, 16) +DEFINE_BITFIELD(MISC_SHU_RANKCTL_RANKINCTL, 23, 20) +DEFINE_BITFIELD(MISC_SHU_RANKCTL_RANKINCTL_ROOT1, 27, 24) +DEFINE_BITFIELD(MISC_SHU_RANKCTL_RANKINCTL_PHY, 31, 28) + +/* DRAMC_REG_SHU_MISC */ +DEFINE_BITFIELD(SHU_MISC_REQQUE_MAXCNT, 3, 0) +DEFINE_BITFIELD(SHU_MISC_DCMDLYREF, 18, 16) +DEFINE_BIT(SHU_MISC_DAREFEN, 30) + +/* DDRPHY_REG_MISC_SHU_RK_DQSIEN_PICG_CTRL */ +DEFINE_BITFIELD(MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_HEAD_EXT_LAT, 2, 0) +DEFINE_BITFIELD(MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_TAIL_EXT_LAT, 6, 4) + +/* DDRPHY_REG_MISC_SHU_RODTENSTB */ +DEFINE_BIT(MISC_SHU_RODTENSTB_RODTENSTB_TRACK_EN, 0) +DEFINE_BIT(MISC_SHU_RODTENSTB_RODTEN_P1_ENABLE, 1) +DEFINE_BIT(MISC_SHU_RODTENSTB_RODTENSTB_TRACK_UDFLWCTRL, 3) +DEFINE_BIT(MISC_SHU_RODTENSTB_RODTENSTB_SELPH_MODE, 4) +DEFINE_BIT(MISC_SHU_RODTENSTB_RODTENSTB_SELPH_BY_BITTIME, 5) +DEFINE_BITFIELD(MISC_SHU_RODTENSTB_RODTENSTB__UI_OFFSET, 11, 8) +DEFINE_BITFIELD(MISC_SHU_RODTENSTB_RODTENSTB_MCK_OFFSET, 15, 12) +DEFINE_BITFIELD(MISC_SHU_RODTENSTB_RODTENSTB_EXT, 31, 16) + +/* DDRPHY_REG_MISC_SHU_RODTENSTB1 */ +DEFINE_BITFIELD(MISC_SHU_RODTENSTB1_RODTENCGEN_HEAD, 5, 4) +DEFINE_BITFIELD(MISC_SHU_RODTENSTB1_RODTENCGEN_TAIL, 7, 6) + +/* DDRPHY_REG_MISC_SHU_RX_SELPH_MODE */ +DEFINE_BITFIELD(MISC_SHU_RX_SELPH_MODE_DQSIEN_SELPH_SERMODE, 1, 0) +DEFINE_BITFIELD(MISC_SHU_RX_SELPH_MODE_RODT_SELPH_SERMODE, 5, 4) +DEFINE_BITFIELD(MISC_SHU_RX_SELPH_MODE_RANK_SELPH_SERMODE, 7, 6) + +/* DDRPHY_REG_MISC_SHU_RDAT1 */ +DEFINE_BIT(MISC_SHU_RDAT1_R_DMRDSEL_DIV2_OPT, 0) +DEFINE_BIT(MISC_SHU_RDAT1_R_DMRDSEL_LOBYTE_OPT, 1) +DEFINE_BIT(MISC_SHU_RDAT1_R_DMRDSEL_HIBYTE_OPT, 2) + +/* DRAMC_REG_SHURK_CKE_CTRL */ +DEFINE_BITFIELD(SHURK_CKE_CTRL_CKE_DBE_CNT, 3, 0) + +/* DDRPHY_REG_MISC_SHU_DQSG_RETRY1 */ +DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_SW_RESET, 0) +DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_SW_EN, 1) +DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_DDR1866_PLUS, 2) +DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_ONCE, 3) +DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_3TIMES, 4) +DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_1RANK, 5) +DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_BY_RANK, 6) +DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_DM4BYTE, 7) +DEFINE_BITFIELD(MISC_SHU_DQSG_RETRY1_RETRY_DQSIENLAT, 11, 8) +DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_STBENCMP_ALLBYTE, 12) +DEFINE_BIT(MISC_SHU_DQSG_RETRY1_XSR_DQSG_RETRY_EN, 13) +DEFINE_BIT(MISC_SHU_DQSG_RETRY1_XSR_RETRY_SPM_MODE, 14) +DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_CMP_DATA, 15) +DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_ALE_BLOCK_MASK, 20) +DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_RDY_SEL_DLE, 21) +DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_USE_NON_EXTEND, 22) +DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_USE_CG_GATING, 23) +DEFINE_BITFIELD(MISC_SHU_DQSG_RETRY1_RETRY_ROUND_NUM, 25, 24) +DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_RANKSEL_FROM_PHY, 28) +DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_PA_DISABLE, 29) +DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_STBEN_RESET_MSK, 30) +DEFINE_BIT(MISC_SHU_DQSG_RETRY1_RETRY_USE_BURST_MODE, 31) + +/* DRAMC_REG_SHU_HWSET_MR13 */ +DEFINE_BITFIELD(SHU_HWSET_MR13_HWSET_MR13_MRSMA, 12, 0) +DEFINE_BITFIELD(SHU_HWSET_MR13_HWSET_MR13_OP, 23, 16) + +/* DRAMC_REG_SHU_HWSET_VRCG */ +DEFINE_BITFIELD(SHU_HWSET_VRCG_HWSET_VRCG_MRSMA, 12, 0) +DEFINE_BITFIELD(SHU_HWSET_VRCG_HWSET_VRCG_OP, 23, 16) +DEFINE_BITFIELD(SHU_HWSET_VRCG_VRCGDIS_PRDCNT, 31, 24) + +/* DRAMC_REG_SHU_HWSET_MR2 */ +DEFINE_BITFIELD(SHU_HWSET_MR2_HWSET_MR2_MRSMA, 12, 0) +DEFINE_BITFIELD(SHU_HWSET_MR2_HWSET_MR2_OP, 23, 16) + +/* DDRPHY_REG_MISC_SHU_DVFSDLL */ +DEFINE_BIT(MISC_SHU_DVFSDLL_R_BYPASS_1ST_DLL, 0) +DEFINE_BIT(MISC_SHU_DVFSDLL_R_BYPASS_2ND_DLL, 1) +DEFINE_BITFIELD(MISC_SHU_DVFSDLL_R_DLL_IDLE, 10, 4) +DEFINE_BITFIELD(MISC_SHU_DVFSDLL_R_2ND_DLL_IDLE, 22, 16) + +/* DDRPHY_REG_SHU_MISC_RX_PIPE_CTRL */ +DEFINE_BIT(SHU_MISC_RX_PIPE_CTRL_RX_PIPE_BYPASS_EN, 0) + +/* DRAMC_REG_SHU_ACTIM1 */ +DEFINE_BITFIELD(SHU_ACTIM1_TRPAB, 3, 0) +DEFINE_BITFIELD(SHU_ACTIM1_TMRWCKEL, 7, 4) +DEFINE_BITFIELD(SHU_ACTIM1_TRP, 11, 8) +DEFINE_BITFIELD(SHU_ACTIM1_TRAS, 21, 16) +DEFINE_BITFIELD(SHU_ACTIM1_TRC, 28, 24) + +/* DRAMC_REG_SHU_ACTIM3 */ +DEFINE_BITFIELD(SHU_ACTIM3_TRFCPB, 7, 0) +DEFINE_BITFIELD(SHU_ACTIM3_MANTMRR, 11, 8) +DEFINE_BITFIELD(SHU_ACTIM3_TR2MRR, 15, 12) +DEFINE_BITFIELD(SHU_ACTIM3_TRFC, 23, 16) +DEFINE_BITFIELD(SHU_ACTIM3_TWTR_L, 29, 24) + +/* DRAMC_REG_SHU_ACTIM2 */ +DEFINE_BITFIELD(SHU_ACTIM2_TXP, 3, 0) +DEFINE_BITFIELD(SHU_ACTIM2_TMRRI, 8, 4) +DEFINE_BITFIELD(SHU_ACTIM2_TRTP, 14, 12) +DEFINE_BITFIELD(SHU_ACTIM2_TR2W, 21, 16) +DEFINE_BITFIELD(SHU_ACTIM2_TFAW, 28, 24) + +/* DRAMC_REG_SHU_ACTIM0 */ +DEFINE_BITFIELD(SHU_ACTIM0_TWTR, 5, 0) +DEFINE_BITFIELD(SHU_ACTIM0_TWR, 15, 8) +DEFINE_BITFIELD(SHU_ACTIM0_TRRD, 18, 16) +DEFINE_BITFIELD(SHU_ACTIM0_TRCD, 27, 24) +DEFINE_BITFIELD(SHU_ACTIM0_CKELCKCNT, 31, 28) + +/* DRAMC_REG_SHU_ACTIM5 */ +DEFINE_BITFIELD(SHU_ACTIM5_TR2PD, 6, 0) +DEFINE_BITFIELD(SHU_ACTIM5_TWTPD, 14, 8) +DEFINE_BITFIELD(SHU_ACTIM5_TPBR2PBR, 23, 16) +DEFINE_BITFIELD(SHU_ACTIM5_TPBR2ACT, 29, 28) + +/* DRAMC_REG_SHU_ACTIM6 */ +DEFINE_BITFIELD(SHU_ACTIM6_TZQLAT2, 4, 0) +DEFINE_BITFIELD(SHU_ACTIM6_TMRD, 11, 8) +DEFINE_BITFIELD(SHU_ACTIM6_TMRW, 15, 12) +DEFINE_BITFIELD(SHU_ACTIM6_TW2MRW, 25, 20) +DEFINE_BITFIELD(SHU_ACTIM6_TR2MRW, 31, 26) + +/* DRAMC_REG_SHU_ACTIM4 */ +DEFINE_BITFIELD(SHU_ACTIM4_TXREFCNT, 9, 0) +DEFINE_BITFIELD(SHU_ACTIM4_TMRR2MRW, 15, 10) +DEFINE_BITFIELD(SHU_ACTIM4_TMRR2W, 21, 16) +DEFINE_BITFIELD(SHU_ACTIM4_TZQCS, 31, 24) + +/* DRAMC_REG_SHU_CKECTRL */ +DEFINE_BIT(SHU_CKECTRL_TPDE_05T, 0) +DEFINE_BIT(SHU_CKECTRL_TPDX_05T, 1) +DEFINE_BITFIELD(SHU_CKECTRL_TPDE, 14, 12) +DEFINE_BITFIELD(SHU_CKECTRL_TPDX, 18, 16) +DEFINE_BITFIELD(SHU_CKECTRL_TCKEPRD, 22, 20) +DEFINE_BITFIELD(SHU_CKECTRL_TCKESRX, 25, 24) + +/* DRAMC_REG_SHU_ACTIM_XRT */ +DEFINE_BITFIELD(SHU_ACTIM_XRT_XRTR2R, 4, 0) +DEFINE_BITFIELD(SHU_ACTIM_XRT_XRTR2W, 13, 8) +DEFINE_BITFIELD(SHU_ACTIM_XRT_XRTW2R, 19, 16) +DEFINE_BITFIELD(SHU_ACTIM_XRT_XRTW2W, 28, 24) + +/* DRAMC_REG_SHU_AC_TIME_05T */ +DEFINE_BIT(SHU_AC_TIME_05T_TRC_05T, 0) +DEFINE_BIT(SHU_AC_TIME_05T_TRFCPB_05T, 1) +DEFINE_BIT(SHU_AC_TIME_05T_TRFC_05T, 2) +DEFINE_BIT(SHU_AC_TIME_05T_TPBR2PBR_05T, 3) +DEFINE_BIT(SHU_AC_TIME_05T_TXP_05T, 4) +DEFINE_BIT(SHU_AC_TIME_05T_TRTP_05T, 5) +DEFINE_BIT(SHU_AC_TIME_05T_TRCD_05T, 6) +DEFINE_BIT(SHU_AC_TIME_05T_TRP_05T, 7) +DEFINE_BIT(SHU_AC_TIME_05T_TRPAB_05T, 8) +DEFINE_BIT(SHU_AC_TIME_05T_TRAS_05T, 9) +DEFINE_BIT(SHU_AC_TIME_05T_TWR_M05T, 10) +DEFINE_BIT(SHU_AC_TIME_05T_TRRD_05T, 12) +DEFINE_BIT(SHU_AC_TIME_05T_TFAW_05T, 13) +DEFINE_BIT(SHU_AC_TIME_05T_TCKEPRD_05T, 14) +DEFINE_BIT(SHU_AC_TIME_05T_TR2PD_05T, 15) +DEFINE_BIT(SHU_AC_TIME_05T_TWTPD_M05T, 16) +DEFINE_BIT(SHU_AC_TIME_05T_TMRRI_05T, 17) +DEFINE_BIT(SHU_AC_TIME_05T_TMRWCKEL_05T, 18) +DEFINE_BIT(SHU_AC_TIME_05T_BGTRRD_05T, 19) +DEFINE_BIT(SHU_AC_TIME_05T_BGTCCD_05T, 20) +DEFINE_BIT(SHU_AC_TIME_05T_BGTWTR_M05T, 21) +DEFINE_BIT(SHU_AC_TIME_05T_TR2W_05T, 22) +DEFINE_BIT(SHU_AC_TIME_05T_TWTR_M05T, 23) +DEFINE_BIT(SHU_AC_TIME_05T_XRTR2W_05T, 24) +DEFINE_BIT(SHU_AC_TIME_05T_TMRD_05T, 25) +DEFINE_BIT(SHU_AC_TIME_05T_TMRW_05T, 26) +DEFINE_BIT(SHU_AC_TIME_05T_TMRR2MRW_05T, 27) +DEFINE_BIT(SHU_AC_TIME_05T_TW2MRW_05T, 28) +DEFINE_BIT(SHU_AC_TIME_05T_TR2MRW_05T, 29) +DEFINE_BIT(SHU_AC_TIME_05T_TPBR2ACT_05T, 30) +DEFINE_BIT(SHU_AC_TIME_05T_XRTW2R_M05T, 31) + +/* DRAMC_REG_SHU_AC_DERATING0 */ +DEFINE_BIT(SHU_AC_DERATING0_ACDERATEEN, 0) +DEFINE_BITFIELD(SHU_AC_DERATING0_TRRD_DERATE, 18, 16) +DEFINE_BITFIELD(SHU_AC_DERATING0_TRCD_DERATE, 27, 24) + +/* DRAMC_REG_SHU_AC_DERATING1 */ +DEFINE_BITFIELD(SHU_AC_DERATING1_TRPAB_DERATE, 3, 0) +DEFINE_BITFIELD(SHU_AC_DERATING1_TRP_DERATE, 11, 8) +DEFINE_BITFIELD(SHU_AC_DERATING1_TRAS_DERATE, 21, 16) +DEFINE_BITFIELD(SHU_AC_DERATING1_TRC_DERATE, 28, 24) + +/* DRAMC_REG_SHU_AC_DERATING_05T */ +DEFINE_BIT(SHU_AC_DERATING_05T_TRC_05T_DERATE, 0) +DEFINE_BIT(SHU_AC_DERATING_05T_TRCD_05T_DERATE, 6) +DEFINE_BIT(SHU_AC_DERATING_05T_TRP_05T_DERATE, 7) +DEFINE_BIT(SHU_AC_DERATING_05T_TRPAB_05T_DERATE, 8) +DEFINE_BIT(SHU_AC_DERATING_05T_TRAS_05T_DERATE, 9) +DEFINE_BIT(SHU_AC_DERATING_05T_TRRD_05T_DERATE, 12) + +/* DRAMC_REG_REFCTRL3 */ +DEFINE_BITFIELD(REFCTRL3_REF_DERATING_EN, 15, 0) + +/* DDRPHY_REG_MISC_SHU_RK_DQSCTL */ +DEFINE_BITFIELD(MISC_SHU_RK_DQSCTL_DQSINCTL, 3, 0) + +/* DDRPHY_REG_MISC_SHU_ODTCTRL */ +DEFINE_BIT(MISC_SHU_ODTCTRL_RODTEN, 0) +DEFINE_BIT(MISC_SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG, 1) +DEFINE_BITFIELD(MISC_SHU_ODTCTRL_RODT_LAT, 7, 4) +DEFINE_BIT(MISC_SHU_ODTCTRL_RODTEN_SELPH_FRUN, 15) +DEFINE_BITFIELD(MISC_SHU_ODTCTRL_RODTDLY_LAT_OPT, 25, 24) +DEFINE_BIT(MISC_SHU_ODTCTRL_FIXRODT, 27) +DEFINE_BIT(MISC_SHU_ODTCTRL_RODTEN_OPT, 29) +DEFINE_BIT(MISC_SHU_ODTCTRL_RODTE2, 30) +DEFINE_BIT(MISC_SHU_ODTCTRL_RODTE, 31) + +/* DDRPHY_REG_SHU_MISC_RANK_SEL_STB */ +DEFINE_BIT(SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN, 0) +DEFINE_BIT(SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN_B23, 1) +DEFINE_BITFIELD(SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_SERMODE, 3, 2) +DEFINE_BIT(SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_TRACK, 4) +DEFINE_BIT(SHU_MISC_RANK_SEL_STB_RANK_SEL_RXDLY_TRACK, 5) +DEFINE_BIT(SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_PHASE_EN, 7) +DEFINE_BITFIELD(SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL, 11, 8) +DEFINE_BITFIELD(SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_PLUS, 19, 16) +DEFINE_BITFIELD(SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_PLUS, 23, 20) +DEFINE_BITFIELD(SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_MINUS, 27, 24) +DEFINE_BITFIELD(SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_MINUS, 31, 28) + +/* DDRPHY_REG_MISC_SHU_RDAT */ +DEFINE_BITFIELD(MISC_SHU_RDAT_DATLAT, 4, 0) +DEFINE_BITFIELD(MISC_SHU_RDAT_DATLAT_DSEL, 12, 8) +DEFINE_BITFIELD(MISC_SHU_RDAT_DATLAT_DSEL_PHY, 20, 16) + +/* DRAMC_REG_SHU_TX_RANKCTL */ +DEFINE_BITFIELD(SHU_TX_RANKCTL_TXRANKINCTL_TXDLY, 3, 0) +DEFINE_BITFIELD(SHU_TX_RANKCTL_TXRANKINCTL, 7, 4) +DEFINE_BITFIELD(SHU_TX_RANKCTL_TXRANKINCTL_ROOT, 11, 8) + +/* DRAMC_REG_BYPASS_FSPOP */ +DEFINE_BIT(BYPASS_FSPOP_BPFSP_OPT, 16) + +/* DDRPHY_MD32_REG_LPIF_FSM_CFG_1 */ +DEFINE_BIT(LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL, 0) +DEFINE_BIT(LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_2ND, 1) +DEFINE_BIT(LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_FOR_PWR, 2) +DEFINE_BIT(LPIF_FSM_CFG_1_LPIF_LEGACY_CONTROL_FOR_PWR_2ND, 3) +DEFINE_BIT(LPIF_FSM_CFG_1_LPIF_OUTPUT_PATH_FROM_SW, 4) +DEFINE_BIT(LPIF_FSM_CFG_1_LPIF_OUTPUT_PATH_FROM_SW_2ND, 5) +DEFINE_BIT(LPIF_FSM_CFG_1_LPIF_POWER_CONTROL_SEL, 6) +DEFINE_BIT(LPIF_FSM_CFG_1_LPIF_POWER_CONTROL_SEL_2ND, 7) + +/* DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0 */ +DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_0_PHYPLL_EN, 3, 2) +DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_0_DPY_DLL_EN, 5, 4) +DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_0_DPY_2ND_DLL_EN, 7, 6) +DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_0_DPY_DLL_CK_EN, 9, 8) +DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_0_DPY_VREF_EN, 11, 10) +DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_0_DDRPHY_FB_CK_EN, 17, 16) +DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_0_PHYPLL_SHU_EN, 21, 20) +DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_0_PHYPLL_MODE_SW, 23, 22) +DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_0_PHYPLL2_SHU_EN, 25, 24) +DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_0_PHYPLL2_MODE_SW, 27, 26) + +/* DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1 */ +DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_1_DMY_EN_MOD_SEL, 13, 12) +DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_1_DMYRD_INTV_SEL, 15, 14) +DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_1_DMYRD_EN, 17, 16) +DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_1_TX_TRACKING_RETRY_EN, 21, 20) +DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_1_DR_SHU_SRAM_LEVEL, 29, 22) + +/* DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_3 */ +DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_3_DPY_MCK8X_EN, 1, 0) +DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_3_DPY_MIDPI_EN, 3, 2) +DEFINE_BITFIELD(LPIF_LOW_POWER_CFG_3_DPY_PI_RESETB_EN, 5, 4) + +/* DDRPHY_MD32_REG_LPIF_FSM_OUT_CTRL_0 */ +DEFINE_BIT(LPIF_FSM_OUT_CTRL_0_LOG_OPT_PHYPLL_EN, 1) +DEFINE_BIT(LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_DLL_EN, 2) +DEFINE_BIT(LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_2ND_DLL_EN, 3) +DEFINE_BIT(LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_DLL_CK_EN, 4) +DEFINE_BIT(LPIF_FSM_OUT_CTRL_0_LOG_OPT_DPY_VREF_EN, 5) +DEFINE_BIT(LPIF_FSM_OUT_CTRL_0_LOG_OPT_PHYPLL_SHU_EN, 10) +DEFINE_BIT(LPIF_FSM_OUT_CTRL_0_LOG_OPT_PHYPLL_MODE_SW, 11) + +/* DDRPHY_REG_CLRPLL0 */ +DEFINE_BIT(CLRPLL0_RG_RCLRPLL_EN, 31) + +/* DDRPHY_MD32_REG_LPIF_DFD_DBUG_0 */ +DEFINE_BIT(LPIF_DFD_DBUG_0_LPIF_DFD_DEBUG_ISO_EN, 0) + +/* DDRPHY_REG_MISC_DMA_DEBUG0 */ +DEFINE_BIT(MISC_DMA_DEBUG0_SRAM_DONE, 16) +DEFINE_BIT(MISC_DMA_DEBUG0_APB_DONE, 17) +DEFINE_BIT(MISC_DMA_DEBUG0_SC_DR_SRAM_LOAD_ACK, 29) +DEFINE_BIT(MISC_DMA_DEBUG0_SC_DR_SRAM_RESTORE_ACK, 30) + +/* DDRPHY_MD32_REG_LPIF_STATUS_4 */ +DEFINE_BITFIELD(LPIF_STATUS_4_SHU_EN_ACK, 15, 14) + +/* DRAMC_REG_MRR_STATUS2 */ +DEFINE_BITFIELD(MRR_STATUS2_DVFS_STATE, 31, 24) + +/* DDRPHY_REG_SHU_MISC_RDSEL_TRACK */ +DEFINE_BITFIELD(SHU_MISC_RDSEL_TRACK_DMDATLAT_I, 4, 0) +DEFINE_BIT(SHU_MISC_RDSEL_TRACK_RDSEL_HWSAVE_MSK, 6) +DEFINE_BIT(SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN, 7) +DEFINE_BITFIELD(SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_NEG, 19, 8) +DEFINE_BITFIELD(SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_POS, 31, 20) + +/* DDRPHY_REG_MISC_SHU_PHY_RX_CTRL */ +DEFINE_BIT(MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPDLAT_EN, 8) +DEFINE_BITFIELD(MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPD_OFFSET, 11, 9) +DEFINE_BITFIELD(MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_PRE_OFFSET, 15, 14) +DEFINE_BITFIELD(MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_HEAD, 18, 16) +DEFINE_BITFIELD(MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_TAIL, 22, 20) +DEFINE_BITFIELD(MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD, 26, 24) +DEFINE_BITFIELD(MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_TAIL, 30, 28) + +/* DDRPHY_REG_MISC_SHU_RANK_SEL_LAT */ +DEFINE_BITFIELD(MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B0, 3, 0) +DEFINE_BITFIELD(MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B1, 7, 4) +DEFINE_BITFIELD(MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_CA, 11, 8) + +/* DDRPHY_REG_SHU_RK_B0_DQSIEN_MCK_UI_DLY */ +DEFINE_BITFIELD(SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0, 3, 0) +DEFINE_BITFIELD(SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0, 7, 4) +DEFINE_BITFIELD(SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0, 19, 16) +DEFINE_BITFIELD(SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0, 23, 20) + +/* DDRPHY_REG_SHU_RK_B0_DQSIEN_PI_DLY */ +DEFINE_BITFIELD(SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0, 6, 0) + +/* DDRPHY_REG_SHU_RK_B1_DQSIEN_MCK_UI_DLY */ +DEFINE_BITFIELD(SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1, 3, 0) +DEFINE_BITFIELD(SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1, 7, 4) +DEFINE_BITFIELD(SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1, 19, 16) +DEFINE_BITFIELD(SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1, 23, 20) + +/* DDRPHY_REG_SHU_RK_B1_DQSIEN_PI_DLY */ +DEFINE_BITFIELD(SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1, 6, 0) + +/* DDRPHY_REG_SHU_RK_B0_RODTEN_MCK_UI_DLY */ +DEFINE_BITFIELD(SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0, 2, 0) +DEFINE_BITFIELD(SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0, 6, 4) +DEFINE_BITFIELD(SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0, 18, 16) +DEFINE_BITFIELD(SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0, 22, 20) + +/* DDRPHY_REG_SHU_RK_B1_RODTEN_MCK_UI_DLY */ +DEFINE_BITFIELD(SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1, 2, 0) +DEFINE_BITFIELD(SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1, 6, 4) +DEFINE_BITFIELD(SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1, 18, 16) +DEFINE_BITFIELD(SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1, 22, 20) + +/* DRAMC_REG_SHU_RX_CG_SET0 */ +DEFINE_BIT(SHU_RX_CG_SET0_DLE_LAST_EXTEND3, 0) +DEFINE_BIT(SHU_RX_CG_SET0_READ_START_EXTEND3, 1) +DEFINE_BIT(SHU_RX_CG_SET0_DLE_LAST_EXTEND2, 2) +DEFINE_BIT(SHU_RX_CG_SET0_READ_START_EXTEND2, 3) +DEFINE_BIT(SHU_RX_CG_SET0_DLE_LAST_EXTEND1, 4) +DEFINE_BIT(SHU_RX_CG_SET0_READ_START_EXTEND1, 5) + +/* DDRPHY_REG_MISC_SHU_RK_DQSCAL */ +DEFINE_BITFIELD(MISC_SHU_RK_DQSCAL_DQSIENLLMT, 6, 0) +DEFINE_BIT(MISC_SHU_RK_DQSCAL_DQSIENLLMTEN, 7) +DEFINE_BITFIELD(MISC_SHU_RK_DQSCAL_DQSIENHLMT, 14, 8) +DEFINE_BIT(MISC_SHU_RK_DQSCAL_DQSIENHLMTEN, 15) + +/* DDRPHY_REG_SHU_R0_B0_INI_UIPI */ +DEFINE_BITFIELD(SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0, 6, 0) +DEFINE_BITFIELD(SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0, 15, 8) + +/* DDRPHY_REG_SHU_R0_B1_INI_UIPI */ +DEFINE_BITFIELD(SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1, 6, 0) +DEFINE_BITFIELD(SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1, 15, 8) + +/* DDRPHY_REG_SHU_R0_B0_NEXT_INI_UIPI */ +DEFINE_BITFIELD(SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0, 6, 0) +DEFINE_BITFIELD(SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0, 15, 8) +DEFINE_BITFIELD(SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0, 31, 24) + +/* DDRPHY_REG_SHU_R0_B1_NEXT_INI_UIPI */ +DEFINE_BITFIELD(SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1, 6, 0) +DEFINE_BITFIELD(SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1, 15, 8) +DEFINE_BITFIELD(SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1, 31, 24) + +/* DDRPHY_REG_SHU_R0_B0_DQ0 */ +DEFINE_BITFIELD(SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY, 2, 0) +DEFINE_BITFIELD(SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY, 6, 4) +DEFINE_BITFIELD(SHU_R0_B0_DQ0_SW_ARPI_DQ_B0, 13, 8) +DEFINE_BITFIELD(SHU_R0_B0_DQ0_SW_ARPI_DQM_B0, 21, 16) +DEFINE_BITFIELD(SHU_R0_B0_DQ0_ARPI_PBYTE_B0, 29, 24) +DEFINE_BIT(SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0, 30) +DEFINE_BIT(SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0, 31) + +/* DDRPHY_REG_SHU_R0_B1_DQ0 */ +DEFINE_BITFIELD(SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY, 2, 0) +DEFINE_BITFIELD(SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY, 6, 4) +DEFINE_BITFIELD(SHU_R0_B1_DQ0_SW_ARPI_DQ_B1, 13, 8) +DEFINE_BITFIELD(SHU_R0_B1_DQ0_SW_ARPI_DQM_B1, 21, 16) +DEFINE_BITFIELD(SHU_R0_B1_DQ0_ARPI_PBYTE_B1, 29, 24) +DEFINE_BIT(SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1, 30) +DEFINE_BIT(SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1, 31) + +/* DRAMC_REG_SHU_APHY_TX_PICG_CTRL */ +DEFINE_BITFIELD(SHU_APHY_TX_PICG_CTRL_TX_PICG_CNT, 3, 0) +DEFINE_BITFIELD(SHU_APHY_TX_PICG_CTRL_TX_DQS_SEL_P1, 6, 4) +DEFINE_BITFIELD(SHU_APHY_TX_PICG_CTRL_TX_DQS_SEL_P0, 10, 8) +DEFINE_BITFIELD(SHU_APHY_TX_PICG_CTRL_DPHY_TX_DCM_EXTCNT, 15, 12) +DEFINE_BIT(SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT, 31) + +/* DRAMC_REG_SHURK_APHY_TX_PICG_CTRL */ +DEFINE_BITFIELD(SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P1, 2, 0) +DEFINE_BITFIELD(SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P0, 6, 4) + +/* DRAMC_REG_SHU_NEW_XRW2W_CTRL */ +DEFINE_BITFIELD(SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B0, 18, 16) +DEFINE_BITFIELD(SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B1, 26, 24) +DEFINE_BIT(SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE, 31) + +/* DRAMC_REG_SHU_SELPH_DQS0 */ +DEFINE_BITFIELD(SHU_SELPH_DQS0_TXDLY_DQS0, 2, 0) +DEFINE_BITFIELD(SHU_SELPH_DQS0_TXDLY_DQS1, 6, 4) +DEFINE_BITFIELD(SHU_SELPH_DQS0_TXDLY_DQS2, 10, 8) +DEFINE_BITFIELD(SHU_SELPH_DQS0_TXDLY_DQS3, 14, 12) +DEFINE_BITFIELD(SHU_SELPH_DQS0_TXDLY_OEN_DQS0, 18, 16) +DEFINE_BITFIELD(SHU_SELPH_DQS0_TXDLY_OEN_DQS1, 22, 20) +DEFINE_BITFIELD(SHU_SELPH_DQS0_TXDLY_OEN_DQS2, 26, 24) +DEFINE_BITFIELD(SHU_SELPH_DQS0_TXDLY_OEN_DQS3, 30, 28) + +/* DRAMC_REG_SHURK_SELPH_DQ0 */ +DEFINE_BITFIELD(SHURK_SELPH_DQ0_TXDLY_DQ0, 2, 0) +DEFINE_BITFIELD(SHURK_SELPH_DQ0_TXDLY_DQ1, 6, 4) +DEFINE_BITFIELD(SHURK_SELPH_DQ0_TXDLY_DQ2, 10, 8) +DEFINE_BITFIELD(SHURK_SELPH_DQ0_TXDLY_DQ3, 14, 12) +DEFINE_BITFIELD(SHURK_SELPH_DQ0_TXDLY_OEN_DQ0, 18, 16) +DEFINE_BITFIELD(SHURK_SELPH_DQ0_TXDLY_OEN_DQ1, 22, 20) +DEFINE_BITFIELD(SHURK_SELPH_DQ0_TXDLY_OEN_DQ2, 26, 24) +DEFINE_BITFIELD(SHURK_SELPH_DQ0_TXDLY_OEN_DQ3, 30, 28) + +/* DRAMC_REG_SHURK_SELPH_DQ1 */ +DEFINE_BITFIELD(SHURK_SELPH_DQ1_TXDLY_DQM0, 2, 0) +DEFINE_BITFIELD(SHURK_SELPH_DQ1_TXDLY_DQM1, 6, 4) +DEFINE_BITFIELD(SHURK_SELPH_DQ1_TXDLY_DQM2, 10, 8) +DEFINE_BITFIELD(SHURK_SELPH_DQ1_TXDLY_DQM3, 14, 12) +DEFINE_BITFIELD(SHURK_SELPH_DQ1_TXDLY_OEN_DQM0, 18, 16) +DEFINE_BITFIELD(SHURK_SELPH_DQ1_TXDLY_OEN_DQM1, 22, 20) +DEFINE_BITFIELD(SHURK_SELPH_DQ1_TXDLY_OEN_DQM2, 26, 24) +DEFINE_BITFIELD(SHURK_SELPH_DQ1_TXDLY_OEN_DQM3, 30, 28) + +/* DRAMC_REG_SHURK_SELPH_DQ2 */ +DEFINE_BITFIELD(SHURK_SELPH_DQ2_DLY_DQ0, 3, 0) +DEFINE_BITFIELD(SHURK_SELPH_DQ2_DLY_DQ1, 7, 4) +DEFINE_BITFIELD(SHURK_SELPH_DQ2_DLY_DQ2, 11, 8) +DEFINE_BITFIELD(SHURK_SELPH_DQ2_DLY_DQ3, 15, 12) +DEFINE_BITFIELD(SHURK_SELPH_DQ2_DLY_OEN_DQ0, 19, 16) +DEFINE_BITFIELD(SHURK_SELPH_DQ2_DLY_OEN_DQ1, 23, 20) +DEFINE_BITFIELD(SHURK_SELPH_DQ2_DLY_OEN_DQ2, 27, 24) +DEFINE_BITFIELD(SHURK_SELPH_DQ2_DLY_OEN_DQ3, 31, 28) + +/* DRAMC_REG_SHURK_SELPH_DQ3 */ +DEFINE_BITFIELD(SHURK_SELPH_DQ3_DLY_DQM0, 3, 0) +DEFINE_BITFIELD(SHURK_SELPH_DQ3_DLY_DQM1, 7, 4) +DEFINE_BITFIELD(SHURK_SELPH_DQ3_DLY_DQM2, 11, 8) +DEFINE_BITFIELD(SHURK_SELPH_DQ3_DLY_DQM3, 15, 12) +DEFINE_BITFIELD(SHURK_SELPH_DQ3_DLY_OEN_DQM0, 19, 16) +DEFINE_BITFIELD(SHURK_SELPH_DQ3_DLY_OEN_DQM1, 23, 20) +DEFINE_BITFIELD(SHURK_SELPH_DQ3_DLY_OEN_DQM2, 27, 24) +DEFINE_BITFIELD(SHURK_SELPH_DQ3_DLY_OEN_DQM3, 31, 28) + +/* DRAMC_REG_SHURK_DQS2DQ_CAL1 */ +DEFINE_BITFIELD(SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0, 10, 0) +DEFINE_BITFIELD(SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1, 26, 16) + +/* DRAMC_REG_SHURK_DQS2DQ_CAL2 */ +DEFINE_BITFIELD(SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0, 10, 0) +DEFINE_BITFIELD(SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1, 26, 16) + +/* DRAMC_REG_SHURK_DQS2DQ_CAL5 */ +DEFINE_BITFIELD(SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0, 10, 0) +DEFINE_BITFIELD(SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1, 26, 16) + +/* DRAMC_REG_SHURK_PI */ +DEFINE_BITFIELD(SHURK_PI_RK0_ARPI_DQ_B1, 5, 0) +DEFINE_BITFIELD(SHURK_PI_RK0_ARPI_DQ_B0, 13, 8) +DEFINE_BITFIELD(SHURK_PI_RK0_ARPI_DQM_B1, 21, 16) +DEFINE_BITFIELD(SHURK_PI_RK0_ARPI_DQM_B0, 29, 24) + +/* DDRPHY_REG_SHU_R0_B0_TXDLY0 */ +DEFINE_BITFIELD(SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0, 7, 0) +DEFINE_BITFIELD(SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0, 15, 8) +DEFINE_BITFIELD(SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0, 23, 16) +DEFINE_BITFIELD(SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0, 31, 24) + +/* DDRPHY_REG_SHU_R0_B0_TXDLY1 */ +DEFINE_BITFIELD(SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0, 7, 0) +DEFINE_BITFIELD(SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0, 15, 8) +DEFINE_BITFIELD(SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0, 23, 16) +DEFINE_BITFIELD(SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0, 31, 24) + +/* DDRPHY_REG_SHU_R0_B0_TXDLY3 */ +DEFINE_BITFIELD(SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0, 7, 0) +DEFINE_BITFIELD(SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0, 23, 16) +DEFINE_BITFIELD(SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0, 31, 24) + +/* DDRPHY_REG_SHU_R0_B1_TXDLY0 */ +DEFINE_BITFIELD(SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1, 7, 0) +DEFINE_BITFIELD(SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1, 15, 8) +DEFINE_BITFIELD(SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1, 23, 16) +DEFINE_BITFIELD(SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1, 31, 24) + +/* DDRPHY_REG_SHU_R0_B1_TXDLY1 */ +DEFINE_BITFIELD(SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1, 7, 0) +DEFINE_BITFIELD(SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1, 15, 8) +DEFINE_BITFIELD(SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1, 23, 16) +DEFINE_BITFIELD(SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1, 31, 24) + +/* DDRPHY_REG_SHU_R0_B1_TXDLY3 */ +DEFINE_BITFIELD(SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1, 7, 0) +DEFINE_BITFIELD(SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1, 23, 16) +DEFINE_BITFIELD(SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1, 31, 24) + +/* DRAMC_REG_SHU_SREF_CTRL */ +DEFINE_BITFIELD(SHU_SREF_CTRL_CKEHCMD, 5, 4) +DEFINE_BITFIELD(SHU_SREF_CTRL_SREF_CK_DLY, 29, 28) + +/* DRAMC_REG_SHU_HMR4_DVFS_CTRL0 */ +DEFINE_BITFIELD(SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT, 15, 8) +DEFINE_BITFIELD(SHU_HMR4_DVFS_CTRL0_REFRCNT, 27, 16) + +/* DDRPHY_REG_SHU_B0_DQ5 */ +DEFINE_BITFIELD(SHU_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0, 5, 0) +DEFINE_BIT(SHU_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0, 6) +DEFINE_BITFIELD(SHU_B0_DQ5_RG_ARPI_FB_B0, 13, 8) +DEFINE_BITFIELD(SHU_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0, 18, 16) +DEFINE_BIT(SHU_B0_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B0, 19) +DEFINE_BITFIELD(SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0, 23, 20) +DEFINE_BITFIELD(SHU_B0_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B0, 31, 29) + +/* DDRPHY_REG_SHU_B1_DQ5 */ +DEFINE_BITFIELD(SHU_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1, 5, 0) +DEFINE_BIT(SHU_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1, 6) +DEFINE_BITFIELD(SHU_B1_DQ5_RG_ARPI_FB_B1, 13, 8) +DEFINE_BITFIELD(SHU_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1, 18, 16) +DEFINE_BIT(SHU_B1_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B1, 19) +DEFINE_BITFIELD(SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1, 23, 20) +DEFINE_BITFIELD(SHU_B1_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B1, 31, 29) + +/* DDRPHY_REG_SHU_R0_B0_RXDLY0 */ +DEFINE_BITFIELD(SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0, 7, 0) +DEFINE_BITFIELD(SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0, 15, 8) +DEFINE_BITFIELD(SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0, 23, 16) +DEFINE_BITFIELD(SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0, 31, 24) + +/* DDRPHY_REG_SHU_R0_B0_RXDLY1 */ +DEFINE_BITFIELD(SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0, 7, 0) +DEFINE_BITFIELD(SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0, 15, 8) +DEFINE_BITFIELD(SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0, 23, 16) +DEFINE_BITFIELD(SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0, 31, 24) + +/* DDRPHY_REG_SHU_R0_B0_RXDLY2 */ +DEFINE_BITFIELD(SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0, 7, 0) +DEFINE_BITFIELD(SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0, 15, 8) +DEFINE_BITFIELD(SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0, 23, 16) +DEFINE_BITFIELD(SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0, 31, 24) + +/* DDRPHY_REG_SHU_R0_B0_RXDLY3 */ +DEFINE_BITFIELD(SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0, 7, 0) +DEFINE_BITFIELD(SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0, 15, 8) +DEFINE_BITFIELD(SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0, 23, 16) +DEFINE_BITFIELD(SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0, 31, 24) + +/* DDRPHY_REG_SHU_R0_B0_RXDLY4 */ +DEFINE_BITFIELD(SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0, 7, 0) +DEFINE_BITFIELD(SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0, 15, 8) + +/* DDRPHY_REG_SHU_R0_B0_RXDLY5 */ +DEFINE_BITFIELD(SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0, 8, 0) +DEFINE_BITFIELD(SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0, 24, 16) + +/* DDRPHY_REG_SHU_R0_B1_RXDLY0 */ +DEFINE_BITFIELD(SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1, 7, 0) +DEFINE_BITFIELD(SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1, 15, 8) +DEFINE_BITFIELD(SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1, 23, 16) +DEFINE_BITFIELD(SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1, 31, 24) + +/* DDRPHY_REG_SHU_R0_B1_RXDLY1 */ +DEFINE_BITFIELD(SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1, 7, 0) +DEFINE_BITFIELD(SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1, 15, 8) +DEFINE_BITFIELD(SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1, 23, 16) +DEFINE_BITFIELD(SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1, 31, 24) + +/* DDRPHY_REG_SHU_R0_B1_RXDLY2 */ +DEFINE_BITFIELD(SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1, 7, 0) +DEFINE_BITFIELD(SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1, 15, 8) +DEFINE_BITFIELD(SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1, 23, 16) +DEFINE_BITFIELD(SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1, 31, 24) + +/* DDRPHY_REG_SHU_R0_B1_RXDLY3 */ +DEFINE_BITFIELD(SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1, 7, 0) +DEFINE_BITFIELD(SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1, 15, 8) +DEFINE_BITFIELD(SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1, 23, 16) +DEFINE_BITFIELD(SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1, 31, 24) + +/* DDRPHY_REG_SHU_R0_B1_RXDLY4 */ +DEFINE_BITFIELD(SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1, 7, 0) +DEFINE_BITFIELD(SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1, 15, 8) + +/* DDRPHY_REG_SHU_R0_B1_RXDLY5 */ +DEFINE_BITFIELD(SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1, 8, 0) +DEFINE_BITFIELD(SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1, 24, 16) + +/* DDRPHY_REG_B0_DQ4 */ +DEFINE_BITFIELD(B0_DQ4_RG_RX_ARDQS_EYE_R_DLY_B0, 6, 0) +DEFINE_BITFIELD(B0_DQ4_RG_RX_ARDQS_EYE_F_DLY_B0, 14, 8) +DEFINE_BITFIELD(B0_DQ4_RG_RX_ARDQ_EYE_R_DLY_B0, 21, 16) +DEFINE_BITFIELD(B0_DQ4_RG_RX_ARDQ_EYE_F_DLY_B0, 29, 24) + +/* DDRPHY_REG_B1_DQ4 */ +DEFINE_BITFIELD(B1_DQ4_RG_RX_ARDQS_EYE_R_DLY_B1, 6, 0) +DEFINE_BITFIELD(B1_DQ4_RG_RX_ARDQS_EYE_F_DLY_B1, 14, 8) +DEFINE_BITFIELD(B1_DQ4_RG_RX_ARDQ_EYE_R_DLY_B1, 21, 16) +DEFINE_BITFIELD(B1_DQ4_RG_RX_ARDQ_EYE_F_DLY_B1, 29, 24) + +/* DDRPHY_REG_SHU_R0_CA_CMD0 */ +DEFINE_BITFIELD(SHU_R0_CA_CMD0_RG_RX_ARCLK_R_DLY_DUTY, 2, 0) +DEFINE_BITFIELD(SHU_R0_CA_CMD0_RG_RX_ARCLK_F_DLY_DUTY, 6, 4) +DEFINE_BITFIELD(SHU_R0_CA_CMD0_RG_ARPI_CS, 13, 8) +DEFINE_BITFIELD(SHU_R0_CA_CMD0_RG_ARPI_CMD, 21, 16) +DEFINE_BITFIELD(SHU_R0_CA_CMD0_RG_ARPI_CLK, 29, 24) +DEFINE_BIT(SHU_R0_CA_CMD0_DA_ARPI_DDR400_0D5UI_RK0_CA, 30) +DEFINE_BIT(SHU_R0_CA_CMD0_DA_RX_ARDQSIEN_0D5UI_RK0_CA, 31) + +/* DRAMC_REG_SHU_SELPH_DQS1 */ +DEFINE_BITFIELD(SHU_SELPH_DQS1_DLY_DQS0, 3, 0) +DEFINE_BITFIELD(SHU_SELPH_DQS1_DLY_DQS1, 7, 4) +DEFINE_BITFIELD(SHU_SELPH_DQS1_DLY_DQS2, 11, 8) +DEFINE_BITFIELD(SHU_SELPH_DQS1_DLY_DQS3, 15, 12) +DEFINE_BITFIELD(SHU_SELPH_DQS1_DLY_OEN_DQS0, 19, 16) +DEFINE_BITFIELD(SHU_SELPH_DQS1_DLY_OEN_DQS1, 23, 20) +DEFINE_BITFIELD(SHU_SELPH_DQS1_DLY_OEN_DQS2, 27, 24) +DEFINE_BITFIELD(SHU_SELPH_DQS1_DLY_OEN_DQS3, 31, 28) + +/* DDRPHY_REG_MISC_RX_AUTOK_CFG0 */ +DEFINE_BIT(MISC_RX_AUTOK_CFG0_RX_CAL_CG_EN, 3) + +/* DDRPHY_REG_SHU_CA_CMD8 */ +DEFINE_BIT(SHU_CA_CMD8_R_RMRODTEN_CG_IG_CA, 20) +DEFINE_BIT(SHU_CA_CMD8_R_RMRX_TOPHY_CG_IG_CA, 21) +DEFINE_BIT(SHU_CA_CMD8_R_DMDQSIEN_FLAG_SYNC_CG_IG_CA, 26) +DEFINE_BIT(SHU_CA_CMD8_R_DMDQSIEN_FLAG_PIPE_CG_IG_CA, 27) +DEFINE_BIT(SHU_CA_CMD8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_CA, 28) +DEFINE_BIT(SHU_CA_CMD8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_CA, 29) +DEFINE_BIT(SHU_CA_CMD8_R_DMRANK_PIPE_CG_IG_CA, 30) +DEFINE_BIT(SHU_CA_CMD8_R_DMRANK_CHG_PIPE_CG_IG_CA, 31) + +/* DRAMC_REG_MRR_BIT_MUX1 */ +DEFINE_BITFIELD(MRR_BIT_MUX1_MRR_BIT0_SEL, 4, 0) +DEFINE_BITFIELD(MRR_BIT_MUX1_MRR_BIT1_SEL, 12, 8) +DEFINE_BITFIELD(MRR_BIT_MUX1_MRR_BIT2_SEL, 20, 16) +DEFINE_BITFIELD(MRR_BIT_MUX1_MRR_BIT3_SEL, 28, 24) + +/* DRAMC_REG_MRR_BIT_MUX2 */ +DEFINE_BITFIELD(MRR_BIT_MUX2_MRR_BIT4_SEL, 4, 0) +DEFINE_BITFIELD(MRR_BIT_MUX2_MRR_BIT5_SEL, 12, 8) +DEFINE_BITFIELD(MRR_BIT_MUX2_MRR_BIT6_SEL, 20, 16) +DEFINE_BITFIELD(MRR_BIT_MUX2_MRR_BIT7_SEL, 28, 24) + +/* DRAMC_REG_MRR_BIT_MUX3 */ +DEFINE_BITFIELD(MRR_BIT_MUX3_MRR_BIT8_SEL, 4, 0) +DEFINE_BITFIELD(MRR_BIT_MUX3_MRR_BIT9_SEL, 12, 8) +DEFINE_BITFIELD(MRR_BIT_MUX3_MRR_BIT10_SEL, 20, 16) +DEFINE_BITFIELD(MRR_BIT_MUX3_MRR_BIT11_SEL, 28, 24) + +/* DRAMC_REG_MRR_BIT_MUX4 */ +DEFINE_BITFIELD(MRR_BIT_MUX4_MRR_BIT12_SEL, 4, 0) +DEFINE_BITFIELD(MRR_BIT_MUX4_MRR_BIT13_SEL, 12, 8) +DEFINE_BITFIELD(MRR_BIT_MUX4_MRR_BIT14_SEL, 20, 16) +DEFINE_BITFIELD(MRR_BIT_MUX4_MRR_BIT15_SEL, 28, 24) + +/* DDRPHY_REG_MISC_DQ_SE_PINMUX_CTRL0 */ +DEFINE_BITFIELD(MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ0, 3, 0) +DEFINE_BITFIELD(MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ1, 7, 4) +DEFINE_BITFIELD(MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ2, 11, 8) +DEFINE_BITFIELD(MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ3, 15, 12) +DEFINE_BITFIELD(MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ4, 19, 16) +DEFINE_BITFIELD(MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ5, 23, 20) +DEFINE_BITFIELD(MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ6, 27, 24) +DEFINE_BITFIELD(MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ7, 31, 28) + +/* DDRPHY_REG_MISC_DQ_SE_PINMUX_CTRL1 */ +DEFINE_BITFIELD(MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ8, 3, 0) +DEFINE_BITFIELD(MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ9, 7, 4) +DEFINE_BITFIELD(MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ10, 11, 8) +DEFINE_BITFIELD(MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ11, 15, 12) +DEFINE_BITFIELD(MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ12, 19, 16) +DEFINE_BITFIELD(MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ13, 23, 20) +DEFINE_BITFIELD(MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ14, 27, 24) +DEFINE_BITFIELD(MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ15, 31, 28) + +/* DRAMC_REG_SA_RESERVE */ +DEFINE_BIT(SA_RESERVE_SINGLE_RANK, 0) +DEFINE_BITFIELD(SA_RESERVE_MODE_RK1, 27, 24) +DEFINE_BITFIELD(SA_RESERVE_MODE_RK0, 31, 28) + +/* DRAMC_REG_SWCMD_CTRL0 */ +DEFINE_BITFIELD(SWCMD_CTRL0_MRSOP, 7, 0) +DEFINE_BITFIELD(SWCMD_CTRL0_MRSMA, 20, 8) +DEFINE_BITFIELD(SWCMD_CTRL0_MRSRK, 25, 24) +DEFINE_BIT(SWCMD_CTRL0_SWTRIG_ZQ_RK, 30) + +/* DRAMC_REG_DRAMC_IRQ_EN */ +DEFINE_BIT(DRAMC_IRQ_EN_MR4INT_EN, 0) +DEFINE_BITFIELD(DRAMC_IRQ_EN_DRAMC_IRQ_EN_RSV, 31, 18) + +/* DDRPHY_REG_CA_TX_MCK */ +DEFINE_BITFIELD(CA_TX_MCK_R_DMRESETB_DRVP_FRPHY, 25, 21) +DEFINE_BITFIELD(CA_TX_MCK_R_DMRESETB_DRVN_FRPHY, 30, 26) +DEFINE_BIT(CA_TX_MCK_R_DMRESET_FRPHY_OPT, 31) + +/* DDRPHY_REG_MISC_IMPCAL */ +DEFINE_BIT(MISC_IMPCAL_DRVCGWREF, 2) +DEFINE_BIT(MISC_IMPCAL_DQDRVSWUPD, 3) +DEFINE_BIT(MISC_IMPCAL_IMPSRCEXT, 4) +DEFINE_BIT(MISC_IMPCAL_IMPBINARY, 5) +DEFINE_BIT(MISC_IMPCAL_DRV_ECO_OPT, 10) +DEFINE_BIT(MISC_IMPCAL_IMPCAL_CHGDRV_ECO_OPT, 11) +DEFINE_BIT(MISC_IMPCAL_IMPCAL_SM_ECO_OPT, 12) +DEFINE_BIT(MISC_IMPCAL_IMPCAL_ECO_OPT, 13) +DEFINE_BIT(MISC_IMPCAL_DIS_SUS_CH1_DRV, 14) +DEFINE_BIT(MISC_IMPCAL_DIS_SUS_CH0_DRV, 15) +DEFINE_BIT(MISC_IMPCAL_IMPCAL_DRVUPDOPT, 17) +DEFINE_BIT(MISC_IMPCAL_IMPCAL_BYPASS_UP_CA_DRV, 19) +DEFINE_BIT(MISC_IMPCAL_IMPCAL_HWSAVE_EN, 20) +DEFINE_BIT(MISC_IMPCAL_IMPCAL_CALI_ENN, 21) +DEFINE_BIT(MISC_IMPCAL_IMPCAL_CALI_ENP, 22) +DEFINE_BIT(MISC_IMPCAL_IMPCAL_CALI_EN, 23) +DEFINE_BIT(MISC_IMPCAL_IMPCAL_IMPPDN, 24) +DEFINE_BIT(MISC_IMPCAL_IMPCAL_IMPPDP, 25) +DEFINE_BIT(MISC_IMPCAL_IMPCAL_NEW_OLD_SL, 26) +DEFINE_BIT(MISC_IMPCAL_IMPCAL_SWVALUE_EN, 29) +DEFINE_BIT(MISC_IMPCAL_IMPCAL_EN, 30) +DEFINE_BIT(MISC_IMPCAL_IMPCAL_HW, 31) + +/* DDRPHY_REG_SHU_B0_DLL2 */ +DEFINE_BITFIELD(SHU_B0_DLL2_RG_ARDQ_REV_B0, 31, 0) + +/* DDRPHY_REG_SHU_B1_DLL2 */ +DEFINE_BITFIELD(SHU_B1_DLL2_RG_ARDQ_REV_B1, 31, 0) + +/* DDRPHY_REG_SHU_CA_DLL2 */ +DEFINE_BITFIELD(SHU_CA_DLL2_RG_ARCMD_REV, 31, 0) + +/* DRAMC_REG_DRAMC_DBG_SEL1 */ +DEFINE_BITFIELD(DRAMC_DBG_SEL1_DEBUG_SEL_0, 15, 0) + +/* DRAMC_REG_SWCMD_CTRL2 */ +DEFINE_BITFIELD(SWCMD_CTRL2_RTSWCMD_AGE, 9, 0) + +/* DRAMC_REG_RTMRW_CTRL0 */ +DEFINE_BITFIELD(RTMRW_CTRL0_RTMRW_AGE, 24, 15) + +/* DRAMC_REG_REF_BOUNCE1 */ +DEFINE_BITFIELD(REF_BOUNCE1_REFRATE_DEBOUNCE_COUNT, 7, 0) +DEFINE_BITFIELD(REF_BOUNCE1_REFRATE_DEBOUNCE_TH, 12, 8) +DEFINE_BIT(REF_BOUNCE1_REFRATE_DEBOUNCE_OPT, 13) +DEFINE_BITFIELD(REF_BOUNCE1_REFRATE_DEBOUNCE_DIS, 31, 16) + +/* DRAMC_REG_REFPEND2 */ +DEFINE_BITFIELD(REFPEND2_MPENDREFCNT_TH8, 3, 0) + +/* DRAMC_REG_RTSWCMD_CNT */ +DEFINE_BITFIELD(RTSWCMD_CNT_RTSWCMD_CNT, 31, 0) + +/* DDRPHY_REG_B0_DLL_ARPI4 */ +DEFINE_BIT(B0_DLL_ARPI4_RG_ARPI_BYPASS_SR_DQ_B0, 8) +DEFINE_BIT(B0_DLL_ARPI4_RG_ARPI_BYPASS_SR_DQS_B0, 9) + +/* DDRPHY_REG_B1_DLL_ARPI4 */ +DEFINE_BIT(B1_DLL_ARPI4_RG_ARPI_BYPASS_SR_DQ_B1, 8) +DEFINE_BIT(B1_DLL_ARPI4_RG_ARPI_BYPASS_SR_DQS_B1, 9) + +/* DDRPHY_REG_CA_DLL_ARPI4 */ +DEFINE_BIT(CA_DLL_ARPI4_RG_ARPI_BYPASS_SR_CA_CA, 8) +DEFINE_BIT(CA_DLL_ARPI4_RG_ARPI_BYPASS_SR_CLK_CA, 9) + +/* DDRPHY_REG_MISC_DDR_RESERVE */ +DEFINE_BITFIELD(MISC_DDR_RESERVE_WDT_CONF_ISO_CNT, 7, 0) +DEFINE_BIT(MISC_DDR_RESERVE_WDT_SM_CLR, 24) +DEFINE_BIT(MISC_DDR_RESERVE_WDT_LITE_EN, 25) + +/* DDRPHY_REG_MISC_CTRL6 */ +DEFINE_BIT(MISC_CTRL6_RG_PHDET_EN_SHU_OPT, 0) +DEFINE_BIT(MISC_CTRL6_RG_ADA_MCK8X_EN_SHU_OPT, 1) + +/* DRAMC_REG_REF_BOUNCE2 */ +DEFINE_BITFIELD(REF_BOUNCE2_PRE_MR4INT_TH, 4, 0) + +/* DRAMC_REG_SHU_REF0 */ +DEFINE_BITFIELD(SHU_REF0_MPENDREF_CNT, 2, 0) + +/* DRAMC_REG_ZQ_SET1 */ +DEFINE_BIT(ZQ_SET1_ZQCALDISB, 30) + +/* DRAMC_REG_TX_RETRY_SET0 */ +DEFINE_BIT(TX_RETRY_SET0_XSR_TX_RETRY_BLOCK_ALE_MASK, 0) +DEFINE_BIT(TX_RETRY_SET0_XSR_TX_RETRY_EN, 2) +DEFINE_BIT(TX_RETRY_SET0_XSR_TX_RETRY_SW_EN, 4) + +/* DRAMC_REG_SPCMDRESP */ +DEFINE_BIT(SPCMDRESP_MRR_RESPONSE, 1) +DEFINE_BIT(SPCMDRESP_RDDQC_RESPONSE, 7) +DEFINE_BIT(SPCMDRESP_TX_RETRY_DONE_RESPONSE, 15) + +/* DDRPHY_REG_SHU_B0_VREF */ +DEFINE_BIT(SHU_B0_VREF_RG_RX_ARDQ_VREF_RANK_SEL_EN_B0, 16) +DEFINE_BIT(SHU_B0_VREF_RG_RX_ARDQ_VREF_UNTERM_EN_B0, 22) + +/* DDRPHY_REG_SHU_B1_VREF */ +DEFINE_BIT(SHU_B1_VREF_RG_RX_ARDQ_VREF_RANK_SEL_EN_B1, 16) +DEFINE_BIT(SHU_B1_VREF_RG_RX_ARDQ_VREF_UNTERM_EN_B1, 22) + +/* DDRPHY_REG_SHU_B0_PHY_VREF_SEL */ +DEFINE_BITFIELD(RG_RX_ARDQ_VREF_SEL_LB_B0, 6, 0) +DEFINE_BITFIELD(RG_RX_ARDQ_VREF_SEL_UB_B0, 14, 8) + +/* DDRPHY_REG_SHU_B1_PHY_VREF_SEL */ +DEFINE_BITFIELD(RG_RX_ARDQ_VREF_SEL_LB_B1, 6, 0) +DEFINE_BITFIELD(RG_RX_ARDQ_VREF_SEL_UB_B1, 14, 8) + +/* DDRPHY_REG_SHU_MISC_DRVING1 */ +DEFINE_BITFIELD(SHU_MISC_DRVING1_DQDRVN2, 4, 0) +DEFINE_BITFIELD(SHU_MISC_DRVING1_DQDRVP2, 9, 5) +DEFINE_BITFIELD(SHU_MISC_DRVING1_DQSDRVN1, 14, 10) +DEFINE_BITFIELD(SHU_MISC_DRVING1_DQSDRVP1, 19, 15) +DEFINE_BITFIELD(SHU_MISC_DRVING1_DQSDRVN2, 24, 20) +DEFINE_BITFIELD(SHU_MISC_DRVING1_DQSDRVP2, 29, 25) +DEFINE_BIT(SHU_MISC_DRVING1_DIS_IMP_ODTN_TRACK, 30) +DEFINE_BIT(SHU_MISC_DRVING1_DIS_IMPCAL_HW, 31) + +/* DRAMC_REG_SHU_ZQ_SET0 */ +DEFINE_BITFIELD(SHU_ZQ_SET0_ZQCSCNT, 15, 0) +DEFINE_BITFIELD(SHU_ZQ_SET0_TZQLAT, 31, 27) + +/* DRAMC_REG_DCM_SUB_CTRL */ +DEFINE_BIT(DCM_SUB_CTRL_SUBCLK_CTRL_TX_TRACKING, 1) +DEFINE_BIT(DCM_SUB_CTRL_SUBCLK_CTRL_TX_AUTOK, 12) + +/* DDRPHY_REG_B0_PHY3 */ +DEFINE_BIT(B0_PHY3_RG_RX_ARDQ_BUFF_EN_SEL_B0, 28) + +/* DDRPHY_REG_B1_PHY3 */ +DEFINE_BIT(B1_PHY3_RG_RX_ARDQ_BUFF_EN_SEL_B1, 28) + +/* DRAMC_REG_CBT_WLEV_CTRL5 */ +DEFINE_BITFIELD(CBT_WLEV_CTRL5_NEW_CBT_PAT_INTV, 11, 4) + +/* DRAMC_REG_CBT_WLEV_CTRL0 */ +DEFINE_BIT(CBT_WLEV_CTRL0_BYTEMODECBTEN, 2) +DEFINE_BIT(CBT_WLEV_CTRL0_WRITE_LEVEL_EN, 3) +DEFINE_BIT(CBT_WLEV_CTRL0_DQSOEAOEN, 4) +DEFINE_BIT(CBT_WLEV_CTRL0_CBT_WLEV_DQS_TRIG, 7) +DEFINE_BITFIELD(CBT_WLEV_CTRL0_CBT_WLEV_DQS_SEL, 11, 8) +DEFINE_BITFIELD(CBT_WLEV_CTRL0_WLEV_DQSPAT_LAT, 19, 12) +DEFINE_BITFIELD(CBT_WLEV_CTRL0_CBT_DQBYTE_OEAO_EN, 29, 26) +DEFINE_BIT(CBT_WLEV_CTRL0_CBT_CMP_BYTEMODE, 30) + +/* DRAMC_REG_SHU_LP5_CMD */ +DEFINE_BIT(SHU_LP5_CMD_LP5_CMD1TO2EN, 0) + +/* DDRPHY_REG_SHU_R0_CA_TXDLY0 */ +DEFINE_BITFIELD(SHU_R0_CA_TXDLY0_TX_ARCA0_DLY, 7, 0) +DEFINE_BITFIELD(SHU_R0_CA_TXDLY0_TX_ARCA1_DLY, 15, 8) +DEFINE_BITFIELD(SHU_R0_CA_TXDLY0_TX_ARCA2_DLY, 23, 16) +DEFINE_BITFIELD(SHU_R0_CA_TXDLY0_TX_ARCA3_DLY, 31, 24) + +/* DDRPHY_REG_SHU_R0_CA_TXDLY1 */ +DEFINE_BITFIELD(SHU_R0_CA_TXDLY1_TX_ARCA4_DLY, 7, 0) +DEFINE_BITFIELD(SHU_R0_CA_TXDLY1_TX_ARCA5_DLY, 15, 8) +DEFINE_BITFIELD(SHU_R0_CA_TXDLY1_TX_ARCA6_DLY, 23, 16) +DEFINE_BITFIELD(SHU_R0_CA_TXDLY1_TX_ARCA7_DLY, 31, 24) + +/* DRAMC_REG_CBT_WLEV_CTRL4 */ +DEFINE_BITFIELD(CBT_WLEV_CTRL4_CBT_TXDQ_B0, 7, 0) +DEFINE_BITFIELD(CBT_WLEV_CTRL4_CBT_TXDQ_B1, 15, 8) + +/* DRAMC_REG_CBT_WLEV_CTRL3 */ +DEFINE_BITFIELD(CBT_WLEV_CTRL3_DQSBX_G, 17, 14) + +/* DRAMC_REG_SWCMD_EN */ +DEFINE_BIT(SWCMD_EN_RDDQCEN, 5) +DEFINE_BIT(SWCMD_EN_MRWEN, 11) +DEFINE_BIT(SWCMD_EN_MRREN, 12) +DEFINE_BIT(SWCMD_EN_ZQCEN_SWTRIG, 16) +DEFINE_BIT(SWCMD_EN_ZQLATEN_SWTRIG, 17) +DEFINE_BIT(SWCMD_EN_WCK2DQI_START_SWTRIG, 18) + +/* DRAMC_REG_SPCMDRESP3 */ +DEFINE_BIT(SPCMDRESP3_ZQC_SWTRIG_RESPONSE, 1) +DEFINE_BIT(SPCMDRESP3_ZQLAT_SWTRIG_RESPONSE, 2) +DEFINE_BIT(SPCMDRESP3_WCK2DQI_START_SWTRIG_RESPONSE, 3) + +/* DDRPHY_REG_SHU_B0_RANK_SELPH_UI_DLY */ +DEFINE_BITFIELD(SHU_B0_RANK_SELPH_UI_DLY_RANKSEL_MCK_DLY_P0_B0, 18, 16) +DEFINE_BITFIELD(SHU_B0_RANK_SELPH_UI_DLY_RANKSEL_MCK_DLY_P1_B0, 22, 20) + +/* DDRPHY_REG_SHU_B1_RANK_SELPH_UI_DLY */ +DEFINE_BITFIELD(SHU_B1_RANK_SELPH_UI_DLY_RANKSEL_MCK_DLY_P0_B1, 18, 16) +DEFINE_BITFIELD(SHU_B1_RANK_SELPH_UI_DLY_RANKSEL_MCK_DLY_P1_B1, 22, 20) + +/* DRAMC_REG_RDDQCGOLDEN */ +DEFINE_BITFIELD(RDDQCGOLDEN_MR20_GOLDEN, 7, 0) +DEFINE_BITFIELD(RDDQCGOLDEN_MR15_GOLDEN, 15, 8) +DEFINE_BITFIELD(RDDQCGOLDEN_MR40_GOLDEN, 23, 16) +DEFINE_BITFIELD(RDDQCGOLDEN_MR32_GOLDEN, 31, 24) + +/* DDRPHY_REG_MISC_JMETER */ +DEFINE_BIT(MISC_JMETER_JMTR_EN, 0) + +/* DDRPHY_REG_MISC_DUTY_TOGGLE_CNT */ +DEFINE_BITFIELD(MISC_DUTY_TOGGLE_CNT_TOGGLE_CNT, 31, 0) + +/* DDRPHY_REG_MISC_DUTY_DQS0_ERR_CNT */ +DEFINE_BITFIELD(MISC_DUTY_DQS0_ERR_CNT_DQS0_ERR_CNT, 31, 0) + +/* DDRPHY_REG_DVFS_STATUS */ +DEFINE_BITFIELD(DVFS_STATUS_OTHER_SHU_GP, 17, 16) + +/* DDRPHY_REG_SHU_MISC_DRVING3 */ +DEFINE_BITFIELD(SHU_MISC_DRVING3_DQODTN2, 4, 0) +DEFINE_BITFIELD(SHU_MISC_DRVING3_DQODTP2, 9, 5) +DEFINE_BITFIELD(SHU_MISC_DRVING3_DQSODTN, 14, 10) +DEFINE_BITFIELD(SHU_MISC_DRVING3_DQSODTP, 19, 15) +DEFINE_BITFIELD(SHU_MISC_DRVING3_DQSODTN2, 24, 20) +DEFINE_BITFIELD(SHU_MISC_DRVING3_DQSODTP2, 29, 25) + +/* DDRPHY_REG_SHU_MISC_DRVING4 */ +DEFINE_BITFIELD(SHU_MISC_DRVING4_CMDODTN1, 4, 0) +DEFINE_BITFIELD(SHU_MISC_DRVING4_CMDODTP1, 9, 5) +DEFINE_BITFIELD(SHU_MISC_DRVING4_CMDODTN2, 14, 10) +DEFINE_BITFIELD(SHU_MISC_DRVING4_CMDODTP2, 19, 15) +DEFINE_BITFIELD(SHU_MISC_DRVING4_DQODTN1, 24, 20) +DEFINE_BITFIELD(SHU_MISC_DRVING4_DQODTP1, 29, 25) + +/* DDRPHY_REG_MISC_SHU_DRVING8 */ +DEFINE_BITFIELD(MISC_SHU_DRVING8_CS_DRVN, 4, 0) +DEFINE_BITFIELD(MISC_SHU_DRVING8_CS_DRVP, 12, 8) + +/* DDRPHY_REG_MISC_PHY_RGS_CMD */ +DEFINE_BIT(MISC_PHY_RGS_CMD_RGS_RIMPCALOUT, 24) + +/* DDRPHY_REG_SHU_CA_TXDUTY */ +DEFINE_BITFIELD(SHU_CA_TXDUTY_DA_TX_ARCLK_DUTY_DLY, 13, 8) + +/* DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_TXDUTY */ +DEFINE_BITFIELD(SHU_B0_TXDUTY_DA_TX_ARDQ_DUTY_DLY_B0, 5, 0) +DEFINE_BITFIELD(SHU_B0_TXDUTY_DA_TX_ARDQS_DUTY_DLY_B0, 13, 8) +DEFINE_BITFIELD(SHU_B0_TXDUTY_DA_TX_ARDQM_DUTY_DLY_B0, 21, 16) +DEFINE_BITFIELD(SHU_B0_TXDUTY_DA_TX_ARWCK_DUTY_DLY_B0, 29, 24) + +/* DRAMC_ADDR_SHIFT_CHN(DRAMC_REG_TEST2_A3 */ +DEFINE_BITFIELD(TEST2_A3_TESTCNT, 3, 0) + +/* DRAMC_REG_SHU_DQSOSC_SET0 */ +DEFINE_BIT(SHU_DQSOSC_SET0_DQSOSCENDIS, 0) +DEFINE_BITFIELD(SHU_DQSOSC_SET0_DQSOSC_PRDCNT, 13, 4) +DEFINE_BITFIELD(SHU_DQSOSC_SET0_DQSOSCENCNT, 31, 16) + +/* DRAMC_REG_SHURK_DQSOSC */ +DEFINE_BITFIELD(SHURK_DQSOSC_DQSOSC_BASE_RK0, 15, 0) +DEFINE_BITFIELD(SHURK_DQSOSC_DQSOSC_BASE_RK0_B1, 31, 16) + +/* DRAMC_REG_SHU_DQSOSCR */ +DEFINE_BITFIELD(SHU_DQSOSCR_DQSOSCRCNT, 7, 0) + +/* DRAMC_REG_SHURK_DQSOSC_THRD */ +DEFINE_BITFIELD(SHURK_DQSOSC_THRD_DQSOSCTHRD_INC, 11, 0) +DEFINE_BITFIELD(SHURK_DQSOSC_THRD_DQSOSCTHRD_DEC, 27, 16) + +/* DRAMC_REG_SHU_FREQ_RATIO_SET0 */ +DEFINE_BITFIELD(SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO3, 7, 0) +DEFINE_BITFIELD(SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO2, 15, 8) +DEFINE_BITFIELD(SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO1, 23, 16) +DEFINE_BITFIELD(SHU_FREQ_RATIO_SET0_TDQSCK_JUMP_RATIO0, 31, 24) + +/* DRAMC_REG_SHU_FREQ_RATIO_SET1 */ +DEFINE_BITFIELD(SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO7, 7, 0) +DEFINE_BITFIELD(SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO6, 15, 8) +DEFINE_BITFIELD(SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO5, 23, 16) +DEFINE_BITFIELD(SHU_FREQ_RATIO_SET1_TDQSCK_JUMP_RATIO4, 31, 24) + +/* DRAMC_REG_SHU_FREQ_RATIO_SET2 */ +DEFINE_BITFIELD(SHU_FREQ_RATIO_SET2_TDQSCK_JUMP_RATIO9, 23, 16) +DEFINE_BITFIELD(SHU_FREQ_RATIO_SET2_TDQSCK_JUMP_RATIO8, 31, 24) + +/* DDRPHY_REG_SHU_MISC_PRE_TDQSCK */ +DEFINE_BIT(SHU_MISC_PRE_TDQSCK_PRECAL_DISABLE, 0) + +/* DDRPHY_REG_MISC_PRE_TDQSCK1 */ +DEFINE_BIT(MISC_PRE_TDQSCK1_TDQSCK_HW_SW_UP_SEL, 22) +DEFINE_BIT(MISC_PRE_TDQSCK1_TDQSCK_REG_DVFS, 25) +DEFINE_BIT(MISC_PRE_TDQSCK1_TDQSCK_PRECAL_HW, 26) + +/* DRAMC_REG_MISC_STATUSA */ +DEFINE_BIT(MISC_STATUSA_REQQ_EMPTY, 2) +DEFINE_BITFIELD(MISC_STATUSA_REFRESH_QUEUE_CNT, 27, 24) + +/* DRAMC_REG_TEST2_A0 */ +DEFINE_BITFIELD(TEST2_A0_TEST2_PAT1, 7, 0) +DEFINE_BITFIELD(TEST2_A0_TEST2_PAT0, 15, 8) +DEFINE_BIT(TEST2_A0_LOOP_NV_END, 16) +DEFINE_BIT(TEST2_A0_ERR_BREAK_EN, 17) +DEFINE_BIT(TEST2_A0_TA2_LOOP_EN, 18) +DEFINE_BITFIELD(TEST2_A0_LOOP_CNT_INDEX, 23, 20) + +/* DRAMC_REG_TESTRPT */ +DEFINE_BITFIELD(TESTRPT_TESTSTAT, 22, 20) + +/* DRAMC_REG_MRR_STATUS */ +DEFINE_BITFIELD(MRR_STATUS_MRR_SW_REG, 31, 16) + +/* DRAMC_REG_SPCMDRESP */ +DEFINE_BIT(SPCMDRESP_MRW_RESPONSE, 0) + +/* DRAMC_REG_MISC_STATUSA */ +DEFINE_BITFIELD(MISC_STATUSA_REFRESH_RATE, 12, 8) + +/* DDRPHY_REG_SHU_CA_CMD0 */ +DEFINE_BIT(SHU_CA_CMD0_R_LP4Y_WDN_MODE_CLK, 31) + +/* DDRPHY_REG_SHU_B0_DQ0 */ +DEFINE_BIT(SHU_B0_DQ0_R_LP4Y_WDN_MODE_DQS0, 31) + +/* DDRPHY_REG_SHU_B1_DQ0 */ +DEFINE_BIT(SHU_B1_DQ0_R_LP4Y_WDN_MODE_DQS1, 31) + +#endif //__SOC_MEDIATEK_MT8192_DRAMC_MACRO_DEF_H__ \ No newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/44699 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc64fb6c60d57184c4a2f9febe765b5cb69b39ae Gerrit-Change-Number: 44699 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

2 hours, 36 minutes

Change in coreboot[master]: [WIP]amdfwtool: Take a config file instead of command line parameters

by Bao Zheng (Code Review)

Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/42859 to review the following change. Change subject: [WIP]amdfwtool: Take a config file instead of command line parameters ...................................................................... [WIP]amdfwtool: Take a config file instead of command line parameters Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M Makefile.inc M src/soc/amd/picasso/Makefile.inc A src/soc/amd/picasso/fw.cfg M util/amdfwtool/Makefile A util/amdfwtool/Makefile.inc M util/amdfwtool/amdfwtool.c A util/amdfwtool/amdfwtool.h A util/amdfwtool/amdfwtool.sh A util/amdfwtool/data_parse.c A util/amdfwtool/sample.txt 10 files changed, 899 insertions(+), 142 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/42859/1 diff --git a/Makefile.inc b/Makefile.inc index bbb6685..0e10136 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -81,7 +81,7 @@ subdirs-y += src/superio subdirs-y += $(wildcard src/drivers/*) $(wildcard src/drivers/*/*) subdirs-y += src/cpu src/vendorcode -subdirs-y += util/cbfstool util/sconfig util/nvramtool util/pgtblgen +subdirs-y += util/cbfstool util/sconfig util/nvramtool util/pgtblgen util/amdfwtool subdirs-y += util/futility util/marvell util/bincfg util/supermicro subdirs-y += $(wildcard src/arch/*) subdirs-y += src/mainboard/$(MAINBOARDDIR) @@ -566,9 +566,9 @@ cp -a $(top)/util/ifdtool/ifdtool $@ AMDFWTOOL:=$(objutil)/amdfwtool/amdfwtool -$(AMDFWTOOL): $(top)/util/amdfwtool/amdfwtool.c - @printf " HOSTCC $(subst $(obj)/,,$(@))\n" - $(HOSTCC) $(HOSTCFLAGS) -DCONFIG_ROM_SIZE=$(CONFIG_ROM_SIZE) -o $@ $< +#$(AMDFWTOOL): $(top)/util/amdfwtool/amdfwtool.c +# @printf " HOSTCC $(subst $(obj)/,,$(@))\n" +# $(HOSTCC) $(HOSTCFLAGS) -DCONFIG_ROM_SIZE=$(CONFIG_ROM_SIZE) -o $@ $< APCB_EDIT_TOOL:=$(top)/util/apcb/apcb_edit.py @@ -666,7 +666,7 @@ include util/crossgcc/Makefile.inc .PHONY: tools -tools: $(objutil)/kconfig/conf $(objutil)/kconfig/toada $(CBFSTOOL) $(objutil)/cbfstool/cbfs-compression-tool $(FMAPTOOL) $(RMODTOOL) $(IFWITOOL) $(objutil)/nvramtool/nvramtool $(objutil)/sconfig/sconfig $(IFDTOOL) $(CBOOTIMAGE) $(AMDFWTOOL) $(AMDCOMPRESS) $(FUTILITY) $(BINCFG) $(IFITTOOL) $(objutil)/supermicro/smcbiosinfo +tools: $(objutil)/kconfig/conf $(objutil)/kconfig/toada $(CBFSTOOL) $(objutil)/cbfstool/cbfs-compression-tool $(FMAPTOOL) $(RMODTOOL) $(IFWITOOL) $(objutil)/nvramtool/nvramtool $(objutil)/sconfig/sconfig $(IFDTOOL) $(CBOOTIMAGE) $(objutil)/amdfwtool/amdfwtool $(AMDCOMPRESS) $(FUTILITY) $(BINCFG) $(IFITTOOL) $(objutil)/supermicro/smcbiosinfo ########################################################################### # Common recipes for all stages @@ -1094,7 +1094,6 @@ endif $(obj)/coreboot.rom: $(obj)/coreboot.pre $(RAMSTAGE) $(CBFSTOOL) $$(INTERMEDIATE) - @printf " CBFS $(subst $(obj)/,,$(@))\n" # The full ROM may be larger than the CBFS part, so create an empty # file (filled with \377 = 0xff) and copy the CBFS image over it. diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 39269e9..20fb5c2 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -378,14 +378,6 @@ rm -f $@ @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" $(AMDFWTOOL) \ - $(OPT_AMD_PUBKEY_FILE) \ - $(OPT_PSPBTLDR_FILE) \ - $(OPT_PSPSCUREOS_FILE) \ - $(OPT_PSP_SEC_DBG_KEY_FILE) \ - $(OPT_SMUFW1_SUB2_FILE) \ - $(OPT_SMUFW2_SUB2_FILE) \ - $(OPT_SMUFW1_SUB1_FILE) \ - $(OPT_SMUFW2_SUB1_FILE) \ $(OPT_PSP_APCB_FILES) \ $(OPT_APOB_ADDR) \ --apob-nv-size $(shell printf "0x%x" \ @@ -398,38 +390,18 @@ $(OPT_PSP_BIOSBIN_DEST) \ $(OPT_PSP_BIOSBIN_SIZE) \ $(OPT_PSP_SOFTFUSE) \ - $(OPT_PSP_PMUI_FILE1) \ - $(OPT_PSP_PMUI_FILE2) \ - $(OPT_PSP_PMUI_FILE3) \ - $(OPT_PSP_PMUI_FILE4) \ - $(OPT_PSP_PMUD_FILE1) \ - $(OPT_PSP_PMUD_FILE2) \ - $(OPT_PSP_PMUD_FILE3) \ - $(OPT_PSP_PMUD_FILE4) \ - $(OPT_MP2CFG_FILE) \ - $(OPT_ABL0_FILE) \ - $(OPT_ABL1_FILE) \ - $(OPT_ABL2_FILE) \ - $(OPT_ABL3_FILE) \ - $(OPT_ABL4_FILE) \ - $(OPT_ABL5_FILE) \ - $(OPT_ABL6_FILE) \ - $(OPT_ABL7_FILE) \ $(OPT_WHITELIST_FILE) \ - $(OPT_SECG1_FILE) \ - $(OPT_SECG2_FILE) \ - $(OPT_MP2FW1_FILE) \ - $(OPT_MP2FW2_FILE) \ - $(OPT_DRIVERS_FILE) \ - $(OPT_PSP_S0I3_FILE) \ - $(OPT_IKEK_FILE) \ $(OPT_SEC_DEBUG_FILE) \ + --config $(FIRMWARE_LOCATE)/fw.cfg \ --combo-capable \ $(OPT_TOKEN_UNLOCK) \ --flashsize $(CONFIG_ROM_SIZE) \ --location $(shell printf "0x%x" $(PICASSO_FWM_POSITION)) \ --output $@ +# --config /home/baozheng/x86/coreboot-gerrit/src/soc/amd/picasso/fw.cfg \ + + $(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS) rm -f $@ @printf " AMDCOMPRS $(subst $(obj)/,,$(@))\n" diff --git a/src/soc/amd/picasso/fw.cfg b/src/soc/amd/picasso/fw.cfg new file mode 100644 index 0000000..f5b9d13 --- /dev/null +++ b/src/soc/amd/picasso/fw.cfg @@ -0,0 +1,46 @@ +# sample PSP fw config file +# Move to amd_blob +# type file +AMD_PUBKEY_FILE AmdPubKeyRV.bin +PSPBTLDR_FILE PspBootLoader_prod_RV.sbin +#PUBSIGNEDKEY_FILE RtmPubSignedRV.key +PSP_SMUFW1_SUB1_FILE SmuFirmwareRV2.csbin +PSP_SMUFW1_SUB2_FILE SmuFirmwarePCO.csbin +PSP_SMUFW2_SUB1_FILE SmuFirmware2RV2.csbin +PSP_SMUFW2_SUB2_FILE SmuFirmware2PCO.csbin +PSPSCUREOS_FILE psp_os_combined_prod_RV.sbin +#PSPTRUSTLETS_FILE dr_ftpm_prod_RV.csbin +#PSP_SEC_DBG_KEY_FILE RavenSecureDebug_PublicKey.bin +PSPSCUREOS_FILE psp_os_combined_prod_RV.sbin +PSP_ABL0_FILE AgesaBootloader0_prod_RV.csbin +PSP_ABL1_FILE AgesaBootloader1_prod_RV.csbin +PSP_ABL2_FILE AgesaBootloader2_prod_RV.csbin +PSP_ABL3_FILE AgesaBootloader3_prod_RV.csbin +PSP_ABL4_FILE AgesaBootloader4_prod_RV.csbin +PSP_ABL5_FILE AgesaBootloader5_prod_RV.csbin +PSP_ABL6_FILE AgesaBootloader6_prod_RV.csbin +PSP_ABL7_FILE AgesaBootloader7_prod_RV.csbin +#PSP_SEC_DEBUG_FILE secure_unlock_prod_RV.sbin +PSP_IKEK_FILE PspIkekRV.bin +PSP_SECG1_FILE security_policy_RV2_FP5_AM4.sbin +PSP_SECG2_FILE security_policy_PCO_FP5_AM4.sbin +#PSP_MP2FW1_FILE MP2I2CFWRV2.sbin +#PSP_MP2FW2_FILE MP2I2CFWPCO.sbin +#PSP_MP2CFG_FILE MP2FWConfig.sbin +PSP_DRIVERS_FILE drv_sys_prod_RV.sbin +#PSP_SOFTFUSE 0x0000000010000001 +#PSP_S0I3_FILE dr_agesa_prod_RV.sbin +#PSP_APOBNV_BASE +#PSP_APOBNV_SIZE +# +## BDT +#PSP_APCB0_FILE apcb.bin +PSP_PMUI_FILE1 Appb_Rv_1D_Ddr4_Udimm_Imem.csbin +PSP_PMUI_FILE2 Appb_Rv_2D_Ddr4_Imem.csbin +PSP_PMUI_FILE3 Appb_Rv2_1D_ddr4_Udimm_Imem.csbin +PSP_PMUI_FILE4 Appb_Rv2_2D_ddr4_Udimm_Imem.csbin +PSP_PMUD_FILE1 Appb_Rv_1D_Ddr4_Udimm_Dmem.csbin +PSP_PMUD_FILE2 Appb_Rv_2D_Ddr4_Dmem.csbin +PSP_PMUD_FILE3 Appb_Rv2_1D_ddr4_Udimm_Dmem.csbin +PSP_PMUD_FILE4 Appb_Rv2_2D_ddr4_Udimm_Dmem.csbin +#PSP_MP2CFG_FILE MP2FWConfig.sbin diff --git a/util/amdfwtool/Makefile b/util/amdfwtool/Makefile index e9fd91b..9f7a01b 100644 --- a/util/amdfwtool/Makefile +++ b/util/amdfwtool/Makefile @@ -2,15 +2,47 @@ # # All rights reserved. # -# SPDX-License-Identifier: BSD-3-Clause - +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# * Neither the name of Advanced Micro Devices, Inc. nor the names of +# its contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# #***************************************************************************** HOSTCC ?= cc -amdfwtool_exe : amdfwtool.c - $(HOSTCC) amdfwtool.c -o amdfwtool +SRC = amdfwtool.c data_parse.c +OBJ = $(SRC:%.c=%.o) +TARGET = amdfwtool +CFLAGS=-O2 -Wall -Wextra -Wshadow -Wno-sign-compare -amdfwtool : amdfwtool_exe + +$(TARGET): $(OBJ) + $(CC) $(OBJ) $(LDFLAGS) -o $@ + +%.o: %.c $(HEADER) + $(CC) $(CFLAGS) -c -o $@ $< + +amdfwtool_exe : $(TARGET) +# $(HOSTCC) amdfwtool.c -o amdfwtool +# +#amdfwtool : amdfwtool_exe clean: - @rm -f amdfwtool.o amdfwtool amdfwtool.exe + rm -f $(TARGET) $(OBJ) diff --git a/util/amdfwtool/Makefile.inc b/util/amdfwtool/Makefile.inc new file mode 100644 index 0000000..36ff207d --- /dev/null +++ b/util/amdfwtool/Makefile.inc @@ -0,0 +1,52 @@ +#***************************************************************************** +# +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# * Neither the name of Advanced Micro Devices, Inc. nor the names of +# its contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +#***************************************************************************** +#HOSTCC ?= cc + +amdfwtoolobj = amdfwtool.o data_parse.o + +#TARGET = $(objutil)/amdfwtool/amdfwtool +AMDFWTOOLCFLAGS=-O2 -Wall -Wextra -Wshadow -Wno-sign-compare + + +#$(TARGET): $(OBJ) +# $(CC) $(OBJ) $(LDFLAGS) -o $@ + +$(objutil)/amdfwtool/%.o: $(top)/util/amdfwtool/%.c # $(HEADER) + printf " AMDFWTOOL\n" + $(HOSTCC) $(AMDFWTOOLCFLAGS) $(HOSTCFLAGS) -c -o $@ $< + +#amdfwtool_exe : $(TARGET) +# $(HOSTCC) amdfwtool.c -o amdfwtool +# +#amdfwtool : amdfwtool_exe + +#clean: +# rm -f $(TARGET) $(OBJ) +$(objutil)/amdfwtool/amdfwtool: $(addprefix $(objutil)/amdfwtool/,$(amdfwtoolobj)) + printf " AMDFWTOOL\n" + $(HOSTCC) $(addprefix $(objutil)/amdfwtool/,$(amdfwtoolobj)) -o $@ diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index a5e5110..eb0cae8 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -56,6 +56,9 @@ #include <string.h> #include <stdlib.h> #include <getopt.h> +#include <libgen.h> + +#include "amdfwtool.h" #ifndef CONFIG_ROM_SIZE #define CONFIG_ROM_SIZE 0x400000 @@ -98,13 +101,6 @@ */ #define PSP_COMBO 0 -#if defined(__GLIBC__) -typedef unsigned long long int uint64_t; -typedef unsigned int uint32_t; -typedef unsigned char uint8_t; -typedef unsigned short uint16_t; -#endif - /* * Creates the OSI Fletcher checksum. See 8473-1, Appendix C, section C.3. * The checksum field of the passed PDU does not need to be reset to zero. @@ -216,92 +212,11 @@ printf("-R | --sharedmem Location of PSP/FW shared memory\n"); printf("-P | --sharedmem-size Maximum size of the PSP/FW shared memory area\n"); printf("-h | --help show this help\n"); + printf("-C | --config config file\n"); } -typedef enum _amd_bios_type { - AMD_BIOS_APCB = 0x60, - AMD_BIOS_APOB = 0x61, - AMD_BIOS_BIN = 0x62, - AMD_BIOS_APOB_NV = 0x63, - AMD_BIOS_PMUI = 0x64, - AMD_BIOS_PMUD = 0x65, - AMD_BIOS_UCODE = 0x66, - AMD_BIOS_APCB_BK = 0x68, - AMD_BIOS_MP2_CFG = 0x6a, - AMD_BIOS_PSP_SHARED_MEM = 0x6b, - AMD_BIOS_L2_PTR = 0x70, - AMD_BIOS_INVALID, -} amd_bios_type; -#define BDT_LVL1 0x1 -#define BDT_LVL2 0x2 -#define BDT_BOTH (BDT_LVL1 | BDT_LVL2) -typedef struct _amd_bios_entry { - amd_bios_type type; - int region_type; - int reset; - int copy; - int ro; - int zlib; - int inst; - int subpr; - uint64_t src; - uint64_t dest; - size_t size; - char *filename; - int level; -} amd_bios_entry; - -typedef enum _amd_fw_type { - AMD_FW_PSP_PUBKEY = 0, - AMD_FW_PSP_BOOTLOADER = 1, - AMD_FW_PSP_SMU_FIRMWARE = 8, - AMD_FW_PSP_RECOVERY = 3, - AMD_FW_PSP_RTM_PUBKEY = 5, - AMD_FW_PSP_SECURED_OS = 2, - AMD_FW_PSP_NVRAM = 4, - AMD_FW_PSP_SECURED_DEBUG = 9, - AMD_FW_PSP_TRUSTLETS = 12, - AMD_FW_PSP_TRUSTLETKEY = 13, - AMD_FW_PSP_SMU_FIRMWARE2 = 18, - AMD_PSP_FUSE_CHAIN = 11, - AMD_FW_PSP_SMUSCS = 95, - AMD_DEBUG_UNLOCK = 0x13, - AMD_WRAPPED_IKEK = 0x21, - AMD_TOKEN_UNLOCK = 0x22, - AMD_SEC_GASKET = 0x24, - AMD_MP2_FW = 0x25, - AMD_DRIVER_ENTRIES = 0x28, - AMD_S0I3_DRIVER = 0x2d, - AMD_ABL0 = 0x30, - AMD_ABL1 = 0x31, - AMD_ABL2 = 0x32, - AMD_ABL3 = 0x33, - AMD_ABL4 = 0x34, - AMD_ABL5 = 0x35, - AMD_ABL6 = 0x36, - AMD_ABL7 = 0x37, - AMD_FW_PSP_WHITELIST = 0x3a, - AMD_FW_L2_PTR = 0x40, - AMD_FW_PSP_VERSTAGE = 0x52, - AMD_FW_IMC, - AMD_FW_GEC, - AMD_FW_XHCI, - AMD_FW_INVALID, -} amd_fw_type; - -#define PSP_LVL1 0x1 -#define PSP_LVL2 0x2 -#define PSP_BOTH (PSP_LVL1 | PSP_LVL2) -typedef struct _amd_fw_entry { - amd_fw_type type; - uint8_t subprog; - char *filename; - int level; - uint64_t other; -} amd_fw_entry; - -static amd_fw_entry amd_psp_fw_table[] = { +/* static */ amd_fw_entry amd_psp_fw_table[] = { { .type = AMD_FW_PSP_PUBKEY, .level = PSP_BOTH }, { .type = AMD_FW_PSP_BOOTLOADER, .level = PSP_BOTH }, { .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 0, .level = PSP_BOTH }, @@ -343,14 +258,14 @@ { .type = AMD_FW_INVALID }, }; -static amd_fw_entry amd_fw_table[] = { +amd_fw_entry amd_fw_table[] = { { .type = AMD_FW_XHCI }, { .type = AMD_FW_IMC }, { .type = AMD_FW_GEC }, { .type = AMD_FW_INVALID }, }; -static amd_bios_entry amd_bios_table[] = { +amd_bios_entry amd_bios_table[] = { { .type = AMD_BIOS_APCB, .inst = 0, .level = BDT_BOTH }, { .type = AMD_BIOS_APCB, .inst = 1, .level = BDT_BOTH }, { .type = AMD_BIOS_APCB, .inst = 2, .level = BDT_BOTH }, @@ -658,6 +573,28 @@ } } +static void dump_psp_firmwares(amd_fw_entry *fw_table) +{ + amd_fw_entry *index; + + for (index = fw_table; index->type != AMD_FW_INVALID; index++) { + printf("type=%x\n", index->type); + if (index->filename) + printf (" filename=%s\n", index->filename); + } +} + +static void dump_bdt_firmwares(amd_bios_entry *fw_table) +{ + amd_bios_entry *index; + + for (index = fw_table; index->type != AMD_BIOS_INVALID; index++) { + printf("type=%x\n", index->type); + if (index->filename) + printf (" filename=%s\n", index->filename); + } +} + static void integrate_psp_firmwares(context *ctx, psp_directory_table *pspdir, psp_directory_table *pspdir2, @@ -1039,7 +976,7 @@ fill_dir_header(biosdir, count, cookie); } // Unused values: CDE -static const char *optstring = "x:i:g:AMS:p:b:s:r:k:c:n:d:t:u:w:m:T:z:J:B:K:L:Y:N:UW:I:a:Q:V:e:v:j:y:G:O:X:F:H:o:f:l:hZ:qR:P:"; +static const char *optstring = "x:i:g:AMS:p:b:s:r:k:c:n:d:t:u:w:m:T:z:J:B:K:L:Y:N:UW:I:a:Q:V:e:v:j:y:G:O:X:F:H:o:f:l:hZ:qR:P:C"; static struct option long_options[] = { {"xhci", required_argument, 0, 'x' }, @@ -1087,6 +1024,7 @@ {"apob-nv-base", required_argument, 0, 'F' }, {"apob-nv-size", required_argument, 0, 'H' }, /* other */ + {"config", required_argument, 0, 'C' }, {"output", required_argument, 0, 'o' }, {"flashsize", required_argument, 0, 'f' }, {"location", required_argument, 0, 'l' }, @@ -1097,7 +1035,7 @@ {NULL, 0, 0, 0 } }; -static void register_fw_fuse(char *str) +void register_fw_fuse(char *str) { int i; @@ -1145,6 +1083,40 @@ } } +static int register_fw_fuses(int fd, char *dir) +{ + struct stat fd_stat; + unsigned char *config_file; + +// fd = open(, O_RDONLY); +// if (fd < 0) { +// printf("Error opening file: %s: %s\n", +// src_file, strerror(errno)); +// return -1; +// } + + if (fstat(fd, &fd_stat)) { + printf("fstat error 1: %s\n", strerror(errno)); + close(fd); + return -2; + } + + //if (fd_stat.st_size > room) { + // printf("Error: %s will not fit. Exiting.\n", src_file); + // close(fd); + // return -3; + //} + + config_file = malloc (fd_stat.st_size+1); + read(fd, config_file, (size_t)fd_stat.st_size); + + config_file[fd_stat.st_size+1] = '\0'; + + process_config(config_file, dir); + printf("fuse written=[%s,%d] %x\n", __func__, __LINE__, amd_psp_fw_table[16].other); +} + + static void register_bdt_data(amd_bios_type type, int sub, int ins, char name[]) { int i; @@ -1188,8 +1160,8 @@ psp_directory_table *pspdir; int comboable = 0; int fuse_defined = 0; - int targetfd; - char *output = NULL; + int targetfd, configfd; + char *output = NULL, *config = NULL; context ctx = { .rom_size = CONFIG_ROM_SIZE, }; @@ -1427,6 +1399,9 @@ sub = instance = 0; break; + case 'C': + config = optarg; + break; case 'h': usage(); return 0; @@ -1434,9 +1409,29 @@ break; } } + #if 1 + if (!config) { + printf("Error: config file is not specified.\n\n"); + retval = 1; + } - if (!fuse_defined) - register_fw_fuse(DEFAULT_SOFT_FUSE_CHAIN); + configfd = open(config, O_RDONLY); + + if (configfd >=0) { + printf("%s opened\n", config); + register_fw_fuses(configfd, dirname(config)); + } else { + printf("open failed\n"); + } + + + dump_psp_firmwares(amd_psp_fw_table); + dump_bdt_firmwares(amd_bios_table); + printf("close config file\n"); + close (configfd); +#endif + //if (!fuse_defined) + // register_fw_fuse(DEFAULT_SOFT_FUSE_CHAIN); if (!output) { printf("Error: Output value is not specified.\n\n"); @@ -1571,6 +1566,7 @@ amd_romsig->bios1_entry = BUFF_TO_RUN(ctx, biosdir); } + /* TODO:Free the filename. */ targetfd = open(output, O_RDWR | O_CREAT | O_TRUNC, 0666); if (targetfd >= 0) { write(targetfd, amd_romsig, ctx.current - romsig_offset); diff --git a/util/amdfwtool/amdfwtool.h b/util/amdfwtool/amdfwtool.h new file mode 100644 index 0000000..fda41b2 --- /dev/null +++ b/util/amdfwtool/amdfwtool.h @@ -0,0 +1,98 @@ +#ifndef _AMD_FW_TOOL_H_ +#define _AMD_FW_TOOL_H_ +#if defined(__GLIBC__) +typedef unsigned long long int uint64_t; +typedef unsigned int uint32_t; +typedef unsigned char uint8_t; +typedef unsigned short uint16_t; +#endif + + +typedef enum _amd_fw_type { + AMD_FW_PSP_PUBKEY = 0, + AMD_FW_PSP_BOOTLOADER = 1, + AMD_FW_PSP_SMU_FIRMWARE = 8, + AMD_FW_PSP_RECOVERY = 3, + AMD_FW_PSP_RTM_PUBKEY = 5, + AMD_FW_PSP_SECURED_OS = 2, + AMD_FW_PSP_NVRAM = 4, + AMD_FW_PSP_SECURED_DEBUG = 9, + AMD_FW_PSP_TRUSTLETS = 12, + AMD_FW_PSP_TRUSTLETKEY = 13, + AMD_FW_PSP_SMU_FIRMWARE2 = 18, + AMD_PSP_FUSE_CHAIN = 11, + AMD_FW_PSP_SMUSCS = 95, + AMD_DEBUG_UNLOCK = 0x13, + AMD_WRAPPED_IKEK = 0x21, + AMD_TOKEN_UNLOCK = 0x22, + AMD_SEC_GASKET = 0x24, + AMD_MP2_FW = 0x25, + AMD_DRIVER_ENTRIES = 0x28, + AMD_S0I3_DRIVER = 0x2d, + AMD_ABL0 = 0x30, + AMD_ABL1 = 0x31, + AMD_ABL2 = 0x32, + AMD_ABL3 = 0x33, + AMD_ABL4 = 0x34, + AMD_ABL5 = 0x35, + AMD_ABL6 = 0x36, + AMD_ABL7 = 0x37, + AMD_FW_PSP_WHITELIST = 0x3a, + AMD_FW_L2_PTR = 0x40, + AMD_FW_PSP_VERSTAGE = 0x52, + AMD_FW_IMC, + AMD_FW_GEC, + AMD_FW_XHCI, + AMD_FW_INVALID, +} amd_fw_type; + +typedef enum _amd_bios_type { + AMD_BIOS_APCB = 0x60, + AMD_BIOS_APOB = 0x61, + AMD_BIOS_BIN = 0x62, + AMD_BIOS_APOB_NV = 0x63, + AMD_BIOS_PMUI = 0x64, + AMD_BIOS_PMUD = 0x65, + AMD_BIOS_UCODE = 0x66, + AMD_BIOS_APCB_BK = 0x68, + AMD_BIOS_MP2_CFG = 0x6a, + AMD_BIOS_PSP_SHARED_MEM = 0x6b, + AMD_BIOS_L2_PTR = 0x70, + AMD_BIOS_INVALID, +} amd_bios_type; + + +#define BDT_LVL1 0x1 +#define BDT_LVL2 0x2 +#define BDT_BOTH (BDT_LVL1 | BDT_LVL2) +typedef struct _amd_bios_entry { + amd_bios_type type; + char *filename; + int subpr; + int region_type; + int reset; + int copy; + int ro; + int zlib; + int inst; + uint64_t src; + uint64_t dest; + size_t size; + int level; +} amd_bios_entry; + + +#define PSP_LVL1 0x1 +#define PSP_LVL2 0x2 +#define PSP_BOTH (PSP_LVL1 | PSP_LVL2) +typedef struct _amd_fw_entry { + amd_fw_type type; + char *filename; + uint8_t subprog; + int level; + uint64_t other; +} amd_fw_entry; + +void register_fw_fuse(char *str); + +#endif diff --git a/util/amdfwtool/amdfwtool.sh b/util/amdfwtool/amdfwtool.sh new file mode 100644 index 0000000..50006f8 --- /dev/null +++ b/util/amdfwtool/amdfwtool.sh @@ -0,0 +1,60 @@ +#!/bin/sh + +# --pubkey ../../3rdparty/blobs/soc/amd/picasso/PSP/AmdPubKeyRV.bin \ +# --bootloader /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//PspBootLoader_prod_RV.sbin \ +# --rtmpubkey /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//RtmPubSignedRV.key \ +# --secureos /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//psp_os_combined_prod_RV.sbin \ +# --securedebug /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//RavenSecureDebug_PublicKey.bin \ + +# --trustlets /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//dr_ftpm_prod_RV.csbin \ +# --subprogram 2 --smufirmware /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//SmuFirmwarePCO.csbin \ +# --subprogram 2 --smufirmware2 /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//SmuFirmware2PCO.csbin \ +# --subprogram 1 --smufirmware /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//SmuFirmwareRV2.csbin \ +# --subprogram 1 --smufirmware2 /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//SmuFirmware2RV2.csbin \ + +# --soft-fuse 0x0000000010000001 \ +# --subprogram 0 --instance 1 --pmu-inst /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//Appb_Rv_1D_Ddr4_Udimm_Imem.csbin \ +# --subprogram 0 --instance 4 --pmu-inst /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//Appb_Rv_2D_Ddr4_Imem.csbin \ +# --subprogram 1 --instance 1 --pmu-inst /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//Appb_Rv2_1D_ddr4_Udimm_Imem.csbin \ +# --subprogram 1 --instance 4 --pmu-inst /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//Appb_Rv2_2D_ddr4_Udimm_Imem.csbin \ +# --subprogram 0 --instance 1 --pmu-data /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//Appb_Rv_1D_Ddr4_Udimm_Dmem.csbin \ +# --subprogram 0 --instance 4 --pmu-data /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//Appb_Rv_2D_Ddr4_Dmem.csbin \ +# --subprogram 1 --instance 1 --pmu-data /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//Appb_Rv2_1D_ddr4_Udimm_Dmem.csbin \ +# --subprogram 1 --instance 4 --pmu-data /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//Appb_Rv2_2D_ddr4_Udimm_Dmem.csbin \ +# --mp2-config /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//MP2FWConfig.sbin \ +# --abl-image /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//AgesaBootloader0_prod_RV.csbin \ +# --abl-image /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//AgesaBootloader1_prod_RV.csbin \ +# --abl-image /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//AgesaBootloader2_prod_RV.csbin \ +# --abl-image /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//AgesaBootloader3_prod_RV.csbin \ +# --abl-image /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//AgesaBootloader4_prod_RV.csbin \ +# --abl-image /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//AgesaBootloader5_prod_RV.csbin \ +# --abl-image /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//AgesaBootloader6_prod_RV.csbin \ +# --abl-image /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//AgesaBootloader7_prod_RV.csbin \ +# --subprog 1 --sec-gasket /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//security_policy_RV2_FP5_AM4.sbin \ +# --subprog 2 --sec-gasket /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//security_policy_PCO_FP5_AM4.sbin \ +# --subprog 1 --mp2-fw /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//MP2I2CFWRV2.sbin \ +# --subprog 2 --mp2-fw /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//MP2I2CFWPCO.sbin \ +# --drv-entry-pts /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//drv_sys_prod_RV.sbin \ +# --ikek /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//PspIkekRV.bin \ +# --secdebug /home/baozheng/x86/coreboot-gerrit/3rdparty/blobs/soc/amd/picasso/PSP//secure_unlock_prod_RV.sbin \ + +./amdfwtool \ + --instance 0 --apcb ../../3rdparty/blobs/mainboard/amd/mandolin/apcb.bin \ + \ + \ + \ + \ + --apob-base 0x9f00000 \ + \ + --apob-nv-size 0x1000 \ + --bios-bin amd_biospsp.img \ + --bios-bin-dest 8078000 \ + --bios-uncomp-size 0x8000 \ + \ + \ + --combo-capable \ + --token-unlock \ + --flashsize 0x00800000 \ + --location 0xff820000 \ + --config sample.txt \ + --output amdfw.rom diff --git a/util/amdfwtool/data_parse.c b/util/amdfwtool/data_parse.c new file mode 100644 index 0000000..03f1a7f --- /dev/null +++ b/util/amdfwtool/data_parse.c @@ -0,0 +1,457 @@ +#include <stdio.h> +#include <regex.h> +#include <string.h> + +#include "amdfwtool.h" + +/* TODO: a empty line does not matched. */ +static const char blank_or_comment_regex[] = + /* a blank line */ + "(^[[:space:]]*$)" "|" /* or ... */ + /* a line consisting of: optional whitespace followed by */ + "(^[[:space:]]*" + /* a '#' character and optionally, additional characters */ + "#.*$)"; +static regex_t blank_or_comment_expr; + +static const char entries_line_regex[] = + /* optional whitespace */ + "^[[:space:]]*" + /* followed by a chunk of nonwhitespace for macro field */ + "([^[:space:]]+)" + /* followed by one or more whitespace characters */ + "[[:space:]]+" + /* followed by a chunk of nonwhitespace for filename field */ + "([^[:space:]]+)" + /* followed by optional whitespace */ + "[[:space:]]*$"; +static regex_t entries_line_expr; + +static const char entries_subprog_line_regex[] = + /* optional whitespace */ + "^[[:space:]]*" + /* followed by a chunk of nonwhitespace for macro field */ + "([^[:space:]]+)" + /* followed by one or more whitespace characters */ + "[[:space:]]+" + /* followed by a chunk of nonwhitespace for filename field */ + "([^[:space:]]+)" + /* followed by one or more whitespace characters */ + "[[:space:]]+" + /* followed by a chunk of nonwhitespace for filename field */ + "([^[:space:]]+)" + /* followed by optional whitespace */ + "[[:space:]]*$"; +static regex_t entries_subprog_line_expr; + +void compile_reg_expr(int cflags, const char *expr, regex_t *reg) +{ + static const size_t ERROR_BUF_SIZE = 256; + char error_msg[ERROR_BUF_SIZE]; + int result; + + if ((result = regcomp(reg, expr, cflags)) != 0) { + regerror(result, reg, error_msg, ERROR_BUF_SIZE); + printf("%s\n", error_msg); + exit(1); + } +} + +extern amd_fw_entry amd_psp_fw_table[]; +extern amd_bios_entry amd_bios_table[]; +void find_register_fw_filename(char *fw_name, char *filename, uint8_t subprog) +{ + unsigned int fw_type, fw_invalid, fw, entry_size; + void *tableptr; + uint8_t /* subprog = 0, */instance = 0; + + printf("fw_name=%s, fn=%s, subprog=%d\n", fw_name, filename, subprog); + if (strcmp(fw_name, "PSPBTLDR_FILE") == 0) { + fw_type = AMD_FW_PSP_BOOTLOADER; + fw_invalid = AMD_FW_INVALID; + subprog = 0; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); +// printf("fw_type=%x, size=%x\n", fw_type, entry_size); + } else if (strcmp(fw_name, "AMD_PUBKEY_FILE") == 0) { + fw_type = AMD_FW_PSP_PUBKEY; + fw_invalid = AMD_FW_INVALID; + subprog = 0; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); +// printf("fw_type=%x, size=%x\n", fw_type, entry_size); + } else if (strcmp(fw_name, "PUBSIGNEDKEY_FILE") == 0) { + fw_type = AMD_FW_PSP_RTM_PUBKEY; + fw_invalid = AMD_FW_INVALID; + subprog = 0; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSP_SMUFW1_SUB1_FILE") == 0) { + fw_type = AMD_FW_PSP_SMU_FIRMWARE; + subprog = 1; + instance = 0; + fw_invalid = AMD_FW_INVALID; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSP_SMUFW1_SUB2_FILE") == 0) { + fw_type = AMD_FW_PSP_SMU_FIRMWARE; + subprog = 2; + instance = 0; + fw_invalid = AMD_FW_INVALID; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSP_SMUFW2_SUB1_FILE") == 0) { + fw_type = AMD_FW_PSP_SMU_FIRMWARE2; + fw_invalid = AMD_FW_INVALID; + subprog = 1; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSP_SMUFW2_SUB2_FILE") == 0) { + fw_type = AMD_FW_PSP_SMU_FIRMWARE2; + fw_invalid = AMD_FW_INVALID; + subprog = 2; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSP_SEC_DBG_KEY_FILE") == 0) { + fw_type = AMD_FW_PSP_SECURED_DEBUG; + fw_invalid = AMD_FW_INVALID; + subprog = 0; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSP_ABL0_FILE") == 0) { + fw_type = AMD_ABL0; + fw_invalid = AMD_FW_INVALID; + subprog = 0; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSP_ABL1_FILE") == 0) { + fw_type = AMD_ABL1; + fw_invalid = AMD_FW_INVALID; + subprog = 0; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSP_ABL2_FILE") == 0) { + fw_type = AMD_ABL2; + fw_invalid = AMD_FW_INVALID; + subprog = 0; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSP_ABL3_FILE") == 0) { + fw_type = AMD_ABL3; + fw_invalid = AMD_FW_INVALID; + subprog = 0; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSP_ABL4_FILE") == 0) { + fw_type = AMD_ABL4; + fw_invalid = AMD_FW_INVALID; + subprog = 0; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSP_ABL5_FILE") == 0) { + fw_type = AMD_ABL5; + fw_invalid = AMD_FW_INVALID; + subprog = 0; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSP_ABL6_FILE") == 0) { + fw_type = AMD_ABL6; + fw_invalid = AMD_FW_INVALID; + subprog = 0; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSP_ABL7_FILE") == 0) { + fw_type = AMD_ABL7; + fw_invalid = AMD_FW_INVALID; + subprog = 0; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSPSCUREOS_FILE") == 0) { + fw_type = AMD_FW_PSP_SECURED_OS; + fw_invalid = AMD_FW_INVALID; + subprog = 0; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSPTRUSTLETS_FILE") == 0) { + fw_type = AMD_FW_PSP_TRUSTLETS; + fw_invalid = AMD_FW_INVALID; + subprog = 0; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSP_SEC_DEBUG_FILE") == 0) { + fw_type = AMD_DEBUG_UNLOCK; + fw_invalid = AMD_FW_INVALID; + subprog = 0; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSP_IKEK_FILE") == 0) { + fw_type = AMD_WRAPPED_IKEK; + fw_invalid = AMD_FW_INVALID; + subprog = 0; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSP_SECG1_FILE") == 0) { + fw_type = AMD_SEC_GASKET; + fw_invalid = AMD_FW_INVALID; + subprog = 1; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSP_SECG2_FILE") == 0) { + fw_type = AMD_SEC_GASKET; + fw_invalid = AMD_FW_INVALID; + subprog = 2; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSP_MP2FW1_FILE") == 0) { + fw_type = AMD_MP2_FW; + fw_invalid = AMD_FW_INVALID; + subprog = 1; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSP_MP2FW2_FILE") == 0) { + fw_type = AMD_MP2_FW; + fw_invalid = AMD_FW_INVALID; + subprog = 2; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSP_DRIVERS_FILE") == 0) { + fw_type = AMD_DRIVER_ENTRIES; + fw_invalid = AMD_FW_INVALID; + subprog = 0; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSP_S0I3_FILE") == 0) { + fw_type = AMD_S0I3_DRIVER; + fw_invalid = AMD_FW_INVALID; + subprog = 0; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else if (strcmp(fw_name, "PSP_WHITELIST_FILE") == 0) { + fw_type = AMD_FW_PSP_WHITELIST; + fw_invalid = AMD_FW_INVALID; + subprog = 0; + instance = 0; + tableptr = (void *)amd_psp_fw_table; + entry_size = sizeof (amd_fw_entry); + } else { + fw_type = AMD_FW_INVALID; +// return ; + /* TODO: Add more */ + } + +// printf("fw_type=%x, size=%x\n", fw_type, entry_size); + printf("Search and fill the filename\n"); + /* Search and fill the filename */ + while (*(unsigned int *)tableptr != fw_invalid) { + if (*(unsigned int *)tableptr == fw_type && + ((amd_bios_entry *)tableptr)->subpr == subprog) { + printf("type=%d,", *(unsigned int *)tableptr); + printf("found, fn=%s\n", filename); + ((amd_fw_entry *)tableptr)->filename = filename; + break; + } else { +// printf("not found type=%d\n", *(unsigned int *)tableptr); + } + tableptr += entry_size; + } + printf("\n"); + printf("Search and fill the filename 2\n\n"); + #if 1 + if (strcmp(fw_name, "PSP_PMUI_FILE1") == 0) { + fw_type = AMD_BIOS_PMUI; + subprog = 0; + instance = 1; + } else if (strcmp(fw_name, "PSP_PMUI_FILE2") == 0) { + fw_type = AMD_BIOS_PMUI; + subprog = 0; + instance = 4; + } else if (strcmp(fw_name, "PSP_PMUI_FILE3") == 0) { + fw_type = AMD_BIOS_PMUI; + subprog = 1; + instance = 1; + } else if (strcmp(fw_name, "PSP_PMUI_FILE4") == 0) { + fw_type = AMD_BIOS_PMUI; + subprog = 1; + instance = 4; + } else if (strcmp(fw_name, "PSP_PMUD_FILE1") == 0) { + fw_type = AMD_BIOS_PMUD; + subprog = 0; + instance = 1; + } else if (strcmp(fw_name, "PSP_PMUD_FILE2") == 0) { + fw_type = AMD_BIOS_PMUD; + subprog = 0; + instance = 4; + } else if (strcmp(fw_name, "PSP_PMUD_FILE3") == 0) { + fw_type = AMD_BIOS_PMUD; + subprog = 1; + instance = 1; + } else if (strcmp(fw_name, "PSP_PMUD_FILE4") == 0) { + fw_type = AMD_BIOS_PMUD; + subprog = 1; + instance = 4; + } else if (strcmp(fw_name, "PSP_MP2CFG_FILE") == 0) { + fw_type = AMD_BIOS_MP2_CFG; + subprog = 0; + instance = 0; + } else { + fw_type = AMD_BIOS_INVALID; + } + tableptr = (void *)amd_bios_table; + if (fw_type != AMD_BIOS_INVALID) { + while (*(unsigned int *)tableptr != AMD_BIOS_INVALID) { + //printf("%x,%x,%x\n", *(unsigned int *)tableptr, ((amd_bios_entry *)tableptr)->subpr, ((amd_bios_entry *)tableptr)->inst); + if (*(unsigned int *)tableptr == fw_type && + ((amd_bios_entry *)tableptr)->subpr == subprog && + ((amd_bios_entry *)tableptr)->inst == instance) { + ((amd_bios_entry *)tableptr)->filename = filename; + //((amd_bios_entry *)tableptr)->subpr = subprog; + //((amd_bios_entry *)tableptr)->inst = instance; + printf("type=%x,", *(unsigned int *)tableptr); + printf("found, fn=%s\n", filename); + break; + } + tableptr += sizeof (amd_bios_entry); + } + } + + printf("Search and fill the filename 3\n\n"); + if (strcmp(fw_name, "PSP_SOFTFUSE") == 0) { + fw_type = AMD_PSP_FUSE_CHAIN; + } else { + fw_type = AMD_BIOS_INVALID; + } + /* char *filename */ + printf("Search and fill the filename 3.1\n\n"); + tableptr = (void *)amd_psp_fw_table; + if (fw_type != AMD_BIOS_INVALID) { + while (*(unsigned int *)tableptr != AMD_BIOS_INVALID) { + printf("%x,%x,%x\n", *(unsigned int *)tableptr, ((amd_bios_entry *)tableptr)->subpr, ((amd_bios_entry *)tableptr)->inst); + if (*(unsigned int *)tableptr == fw_type) { + //((amd_bios_entry *)tableptr)->filename = filename; + //((amd_bios_entry *)tableptr)->subpr = subprog; + ((amd_fw_entry *)tableptr)->other = strtoull(filename, NULL, 16); + printf("type=%x,", *(unsigned int *)tableptr); + printf("found, fuse=%llx\n", ((amd_fw_entry *)tableptr)->other); + break; + } + tableptr += sizeof (amd_fw_entry); + } + } + printf("fuse written=[] %x\n", amd_psp_fw_table[16].other); + + printf("Search and fill the filename 3.9\n\n"); + +#endif + +} + +unsigned int read_line(char **config, char **oneline) +{ + char *ptr = *config; + char *line_start; + int num; + +// printf("read_line %c\n", **config); + if (*ptr == NULL) return -1; + + line_start = ptr; + while (*ptr != '\n' && *ptr != NULL) { + ptr ++; + } + + num = ptr - line_start; + *oneline = malloc(num+1); + + memcpy (*oneline, line_start, num); + *(*oneline + num) = '\0'; + ptr ++; /* skip enter. */ + //*oneline = ptr; +// printf("readline = %s\n", *oneline); + *config = ptr; + return 0; +} +#define N_MATCHES 4 +void process_config(char *config, char *dir) +{ +// char line [ /* LINE_BUF_SIZE */128]; + char *oneline, *current, *path_filename; + regmatch_t match[N_MATCHES]; + uint8_t subprog = 0; + + compile_reg_expr(REG_EXTENDED | REG_NEWLINE, blank_or_comment_regex, &blank_or_comment_expr); + compile_reg_expr(REG_EXTENDED | REG_NEWLINE, entries_line_regex, &entries_line_expr); + compile_reg_expr(REG_EXTENDED | REG_NEWLINE, entries_subprog_line_regex, &entries_subprog_line_expr); + + /* TODO: temp */ + //strcpy (line, "PSPBTLDR_FILE PspBootLoader_prod_RV.sbin\n\0"); +// strcpy (line, "AMD_PUBKEY_FILE AmdPubKeyRV.bin\n\0"); + + /* Get a line */ + current = config; + while (read_line(&current, &oneline) != -1) { + /* get line */ + /* blank comment */ +// printf("%d\n", __LINE__); + if (!regexec(&blank_or_comment_expr, oneline, 0, NULL, 0)){ + printf("skip comment and blank\n"); + continue; + } + +// printf("%d\n", __LINE__); + if (regexec(&entries_line_expr, oneline, 3, match, 0) == 0) { + printf("matched entry\n"); + printf("%d, %d, %d\n", match[0].rm_eo, match[1].rm_eo, match[2].rm_eo); + printf("%d, %d, %d\n", match[0].rm_so, match[1].rm_so, match[2].rm_so); + oneline[match[1].rm_eo] = '\0'; + oneline[match[2].rm_eo] = '\0'; + } else if (regexec(&entries_subprog_line_expr, oneline, 4, match, 0) == 0) { + printf("matched subprog entry\n"); + printf("%d, %d, %d\n", match[0].rm_eo, match[1].rm_eo, match[2].rm_eo, match[3].rm_eo); + printf("%d, %d, %d\n", match[0].rm_so, match[1].rm_so, match[2].rm_so, match[3].rm_so); + oneline[match[1].rm_eo] = '\0'; + oneline[match[2].rm_eo] = '\0'; + oneline[match[3].rm_eo] = '\0'; + subprog = oneline[match[3].rm_so] - '0'; + } else { + printf("no match\n"); + continue; + } +// printf("%d\n", __LINE__); +// printf("%d\n", __LINE__); + +// printf("%s, %s\n", &(oneline[match[1].rm_so]), &(oneline[match[2].rm_so])); + path_filename = malloc(256); + strcpy(path_filename, dir); + strcat(path_filename, "/"); + strcat(path_filename, &(oneline[match[2].rm_so])); + find_register_fw_filename(&(oneline[match[1].rm_so]), path_filename, subprog); + + } + + printf("fuse written=[] %x\n", amd_psp_fw_table[16].other); + +} diff --git a/util/amdfwtool/sample.txt b/util/amdfwtool/sample.txt new file mode 100644 index 0000000..8c3edcc --- /dev/null +++ b/util/amdfwtool/sample.txt @@ -0,0 +1,45 @@ +# sample +# PSP +# type file subprog +AMD_PUBKEY_FILE AmdPubKeyRV.bin +PSPBTLDR_FILE PspBootLoader_prod_RV.sbin +PUBSIGNEDKEY_FILE RtmPubSignedRV.key +PSP_SMUFW1_SUB1_FILE SmuFirmwareRV2.csbin +PSP_SMUFW1_SUB2_FILE SmuFirmwarePCO.csbin +PSP_SMUFW2_SUB1_FILE SmuFirmware2RV2.csbin +PSP_SMUFW2_SUB2_FILE SmuFirmware2PCO.csbin +PSPSCUREOS_FILE psp_os_combined_prod_RV.sbin +PSPTRUSTLETS_FILE dr_ftpm_prod_RV.csbin +PSP_SEC_DBG_KEY_FILE RavenSecureDebug_PublicKey.bin +PSPSCUREOS_FILE psp_os_combined_prod_RV.sbin +PSP_ABL0_FILE AgesaBootloader0_prod_RV.csbin +PSP_ABL1_FILE AgesaBootloader1_prod_RV.csbin +PSP_ABL2_FILE AgesaBootloader2_prod_RV.csbin +PSP_ABL3_FILE AgesaBootloader3_prod_RV.csbin +PSP_ABL4_FILE AgesaBootloader4_prod_RV.csbin +PSP_ABL5_FILE AgesaBootloader5_prod_RV.csbin +PSP_ABL6_FILE AgesaBootloader6_prod_RV.csbin +PSP_ABL7_FILE AgesaBootloader7_prod_RV.csbin +PSP_SEC_DEBUG_FILE secure_unlock_prod_RV.sbin +PSP_IKEK_FILE PspIkekRV.bin +PSP_SECG1_FILE security_policy_RV2_FP5_AM4.sbin +PSP_SECG2_FILE security_policy_PCO_FP5_AM4.sbin +PSP_MP2FW1_FILE MP2I2CFWRV2.sbin +PSP_MP2FW2_FILE MP2I2CFWPCO.sbin +PSP_MP2CFG_FILE MP2FWConfig.sbin +PSP_DRIVERS_FILE drv_sys_prod_RV.sbin +PSP_SOFTFUSE 0x0000000010000001 +PSP_S0I3_FILE dr_agesa_prod_RV.sbin +#PSP_APOBNV_BASE +#PSP_APOBNV_SIZE +# +## BDT +#PSP_APCB0_FILE apcb.bin +PSP_PMUI_FILE1 Appb_Rv_1D_Ddr4_Udimm_Imem.csbin +PSP_PMUI_FILE2 Appb_Rv_2D_Ddr4_Imem.csbin +PSP_PMUI_FILE3 Appb_Rv2_1D_ddr4_Udimm_Imem.csbin +PSP_PMUI_FILE4 Appb_Rv2_2D_ddr4_Udimm_Imem.csbin +PSP_PMUD_FILE1 Appb_Rv_1D_Ddr4_Udimm_Dmem.csbin +PSP_PMUD_FILE2 Appb_Rv_2D_Ddr4_Dmem.csbin +PSP_PMUD_FILE3 Appb_Rv2_1D_ddr4_Udimm_Dmem.csbin +PSP_PMUD_FILE4 Appb_Rv2_2D_ddr4_Udimm_Dmem.csbin -- To view, visit https://review.coreboot.org/c/coreboot/+/42859 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Gerrit-Change-Number: 42859 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-MessageType: newchange

5 hours, 7 minutes

Change in coreboot[master]: soc/mediatek/mt8192: add pmif driver

by CK HU (Code Review)

Hello hsin-hsiung wang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45398 to review the following change. Change subject: soc/mediatek/mt8192: add pmif driver ...................................................................... soc/mediatek/mt8192: add pmif driver MT8192 uses power management interface(PMIF) to access pmics by spmi and spi, so we add pmif driver to control pmics. TEST=Boots correctly on MT8192EVB. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang(a)mediatek.com> Change-Id: I32fc28f72d9522133baa06f9d67c383f814d862c --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/bootblock.c M src/soc/mediatek/mt8192/include/soc/addressmap.h M src/soc/mediatek/mt8192/include/soc/pll.h A src/soc/mediatek/mt8192/include/soc/pmif.h A src/soc/mediatek/mt8192/include/soc/pmif_spi.h A src/soc/mediatek/mt8192/include/soc/pmif_spmi.h A src/soc/mediatek/mt8192/include/soc/pmif_sw.h A src/soc/mediatek/mt8192/include/soc/spmi.h A src/soc/mediatek/mt8192/pmif.c A src/soc/mediatek/mt8192/pmif_clk.c A src/soc/mediatek/mt8192/pmif_spi.c A src/soc/mediatek/mt8192/pmif_spmi.c 13 files changed, 1,550 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/45398/1 diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 533eae2..0fc47c4 100755 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -9,6 +9,7 @@ bootblock-y += ../common/timer.c bootblock-y += ../common/uart.c bootblock-y += ../common/wdt.c +bootblock-y += pmif.c pmif_clk.c pmif_spi.c pmif_spmi.c verstage-y += flash_controller.c verstage-y += ../common/gpio.c gpio.c diff --git a/src/soc/mediatek/mt8192/bootblock.c b/src/soc/mediatek/mt8192/bootblock.c index 8dffe56..0852f0e 100644 --- a/src/soc/mediatek/mt8192/bootblock.c +++ b/src/soc/mediatek/mt8192/bootblock.c @@ -3,6 +3,7 @@ #include <bootblock_common.h> #include <soc/mmu_operations.h> #include <soc/pll.h> +#include <soc/pmif.h> #include <soc/wdt.h> void bootblock_soc_init(void) @@ -10,4 +11,5 @@ mtk_mmu_init(); mtk_wdt_init(); mt_pll_init(); + mtk_pmif_init(); } diff --git a/src/soc/mediatek/mt8192/include/soc/addressmap.h b/src/soc/mediatek/mt8192/include/soc/addressmap.h index e0cd536..e9cb788 100644 --- a/src/soc/mediatek/mt8192/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8192/include/soc/addressmap.h @@ -21,7 +21,11 @@ GPT_BASE = IO_PHYS + 0x00008000, EINT_BASE = IO_PHYS + 0x0000B000, APMIXED_BASE = IO_PHYS + 0x0000C000, - PWRAP_BASE = IO_PHYS + 0x0000D000, + MODEM_TEMP_SHARE_BASE = IO_PHYS + 0x00018000, + PMIF_SPI_BASE = IO_PHYS + 0x00026000, + PMIF_SPMI_BASE = IO_PHYS + 0x00027000, + PMICSPI_MST_BASE = IO_PHYS + 0x00028000, + SPMI_MST_BASE = IO_PHYS + 0x00029000, UART0_BASE = IO_PHYS + 0x01002000, SPI0_BASE = IO_PHYS + 0x0100A000, SPI1_BASE = IO_PHYS + 0x01010000, diff --git a/src/soc/mediatek/mt8192/include/soc/pll.h b/src/soc/mediatek/mt8192/include/soc/pll.h index 442aa30..c83436e 100644 --- a/src/soc/mediatek/mt8192/include/soc/pll.h +++ b/src/soc/mediatek/mt8192/include/soc/pll.h @@ -178,7 +178,11 @@ u32 mfgpll_con2; u32 mfgpll_con3; u32 ap_pllgp1_con2; - u32 reserved2[33]; + u32 reserved2[13]; + u32 ulposc1_con0; + u32 ulposc1_con1; + u32 ulposc1_con2; + u32 reserved3[17]; u32 ap_pllgp2_con0; /* 0x0300 */ u32 ap_pllgp2_con1; u32 univpll_con0; diff --git a/src/soc/mediatek/mt8192/include/soc/pmif.h b/src/soc/mediatek/mt8192/include/soc/pmif.h new file mode 100644 index 0000000..6106a3d --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/pmif.h @@ -0,0 +1,160 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __MT8192_SOC_PMIF_H__ +#define __MT8192_SOC_PMIF_H__ + +#include <types.h> + +enum { + PMIF_CMD_REG_0, + PMIF_CMD_REG, + PMIF_CMD_EXT_REG, + PMIF_CMD_EXT_REG_LONG, +}; + +struct mtk_pmif_regs { + u32 init_done; + u32 reserved1[5]; + u32 inf_busy_sta; + u32 other_busy_sta_0; + u32 other_busy_sta_1; + u32 inf_en; + u32 other_inf_en; + u32 inf_cmd_per_0; + u32 inf_cmd_per_1; + u32 inf_cmd_per_2; + u32 inf_cmd_per_3; + u32 inf_max_bytecnt_per_0; + u32 inf_max_bytecnt_per_1; + u32 inf_max_bytecnt_per_2; + u32 inf_max_bytecnt_per_3; + u32 staupd_ctrl; + u32 reserved2[48]; + u32 int_gps_auxadc_cmd_addr; + u32 int_gps_auxadc_cmd; + u32 int_gps_auxadc_rdata_addr; + u32 reserved3[13]; + u32 arb_en; + u32 reserved4[34]; + u32 lat_cnter_en; + u32 lat_limit_loading; + u32 lat_limit_0; + u32 lat_limit_1; + u32 lat_limit_2; + u32 lat_limit_3; + u32 lat_limit_4; + u32 lat_limit_5; + u32 lat_limit_6; + u32 lat_limit_7; + u32 lat_limit_8; + u32 lat_limit_9; + u32 reserved5[99]; + u32 crc_ctrl; + u32 crc_sta; + u32 sig_mode; + u32 pmic_sig_addr; + u32 pmic_sig_val; + u32 reserved6[2]; + u32 cmdissue_en; + u32 reserved7[10]; + u32 timer_ctrl; + u32 timer_sta; + u32 sleep_protection_ctrl; + u32 reserved8[5]; + u32 spi_mode_ctrl; + u32 reserved9[2]; + u32 pmic_eint_sta_addr; + u32 reserved10[2]; + u32 irq_event_en_0; + u32 irq_flag_raw_0; + u32 irq_flag_0; + u32 irq_clr_0; + u32 reserved11[502]; + u32 swinf_0_acc; + u32 swinf_0_wdata_31_0; + u32 swinf_0_wdata_63_32; + u32 reserved12[2]; + u32 swinf_0_rdata_31_0; + u32 swinf_0_rdata_63_32; + u32 reserved13[2]; + u32 swinf_0_vld_clr; + u32 swinf_0_sta; + u32 reserved14[5]; + u32 swinf_1_acc; + u32 swinf_1_wdata_31_0; + u32 swinf_1_wdata_63_32; + u32 reserved15[2]; + u32 swinf_1_rdata_31_0; + u32 swinf_1_rdata_63_32; + u32 reserved16[2]; + u32 swinf_1_vld_clr; + u32 swinf_1_sta; + u32 reserved17[5]; + u32 swinf_2_acc; + u32 swinf_2_wdata_31_0; + u32 swinf_2_wdata_63_32; + u32 reserved18[2]; + u32 swinf_2_rdata_31_0; + u32 swinf_2_rdata_63_32; + u32 reserved19[2]; + u32 swinf_2_vld_clr; + u32 swinf_2_sta; + u32 reserved20[5]; + u32 swinf_3_acc; + u32 swinf_3_wdata_31_0; + u32 swinf_3_wdata_63_32; + u32 reserved21[2]; + u32 swinf_3_rdata_31_0; + u32 swinf_3_rdata_63_32; + u32 reserved22[2]; + u32 swinf_3_vld_clr; + u32 swinf_3_sta; + u32 reserved23[133]; +}; + +check_member(mtk_pmif_regs, inf_busy_sta, 0x18); +check_member(mtk_pmif_regs, int_gps_auxadc_cmd_addr, 0x110); +check_member(mtk_pmif_regs, arb_en, 0x0150); +check_member(mtk_pmif_regs, lat_cnter_en, 0x1DC); +check_member(mtk_pmif_regs, crc_ctrl, 0x398); +check_member(mtk_pmif_regs, cmdissue_en, 0x3B4); +check_member(mtk_pmif_regs, timer_ctrl, 0x3E0); +check_member(mtk_pmif_regs, spi_mode_ctrl, 0x400); +check_member(mtk_pmif_regs, pmic_eint_sta_addr, 0x40C); +check_member(mtk_pmif_regs, irq_event_en_0, 0x418); +check_member(mtk_pmif_regs, swinf_0_acc, 0xC00); + +struct pmif { + struct mtk_pmif_regs *mtk_pmif; + int swinf_ch_start; + int swinf_no; + int mstid; + int pmifid; + int (*read_cmd)(struct pmif *arb, unsigned int slvid, + unsigned int addr, unsigned int *rdata); + int (*write_cmd)(struct pmif *arb, unsigned int slvid, + unsigned int addr, unsigned int wdata); + int (*is_pmif_init_done)(struct pmif *arb); +}; + +enum { + PMIF_SPI, + PMIF_SPMI, +}; + +enum { + E_IO = 1, /* I/O error */ + E_BUSY, /* Device or resource busy */ + E_NODEV, /* No such device */ + E_INVAL, /* Invalid argument */ + E_OPNOTSUPP, /* Operation not supported on transport endpoint */ + E_TIMEOUT, /* Wait for idle time out */ + E_READ_TEST_FAIL, /* SPI read fail */ + E_SPI_INIT_RESET_SPI, /* reset SPI fail */ + E_SPI_INIT_SIDLY, /* SPI edge calibration fail */ +}; + +/* start external API */ +extern struct pmif *get_pmif_controller(int inf, int mstid); +extern int mtk_pmif_init(void); +#endif /*__MT8192_SOC_PMIF_H__*/ diff --git a/src/soc/mediatek/mt8192/include/soc/pmif_spi.h b/src/soc/mediatek/mt8192/include/soc/pmif_spi.h new file mode 100644 index 0000000..606dbbd --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/pmif_spi.h @@ -0,0 +1,132 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8192_PMIC_WRAP_H__ +#define __SOC_MEDIATEK_MT8192_PMIC_WRAP_H__ + +#include <soc/addressmap.h> +#include <types.h> + +struct mt8192_pmicspi_mst_regs { + u32 reserved1[4]; + u32 other_busy_sta_0; + u32 wrap_en; + u32 reserved2[2]; + u32 man_en; + u32 man_acc; + u32 reserved3[3]; + u32 mux_sel; + u32 reserved4[3]; + u32 dio_en; + u32 rddmy; + u32 cslext_write; + u32 cslext_read; + u32 cshext_write; + u32 cshext_read; + u32 ext_ck_write; + u32 ext_ck_read; + u32 si_sampling_ctrl; +}; + +check_member(mt8192_pmicspi_mst_regs, other_busy_sta_0, 0x10); +check_member(mt8192_pmicspi_mst_regs, man_en, 0x20); +check_member(mt8192_pmicspi_mst_regs, mux_sel, 0x34); +check_member(mt8192_pmicspi_mst_regs, dio_en, 0x44); + +static struct mt8192_pmicspi_mst_regs * const mtk_pmicspi_mst = (void *)PMICSPI_MST_BASE; + +struct mtk_iocfg_tl_regs { + u32 drv_cfg0; + u32 drv_cfg0_set; + u32 drv_cfg0_clr; +}; +check_member(mtk_iocfg_tl_regs, drv_cfg0_set, 0x4); +check_member(mtk_iocfg_tl_regs, drv_cfg0_clr, 0x8); + +#define mtk_iocfg_tl ((struct mtk_iocfg_tl_regs *)IOCFG_TL_BASE) + +struct mtk_modem_temp_share_regs { + u32 ctrl; +}; + +#define mtk_modem_temp_share ((struct mtk_modem_temp_share_regs *)SPM_BASE) + +/* PMIC registers */ +enum { + PMIC_BASE = 0x0000, + PMIC_SMT_CON1 = PMIC_BASE + 0x0032, + PMIC_DRV_CON1 = PMIC_BASE + 0x003a, + PMIC_FILTER_CON0 = PMIC_BASE + 0x0042, + PMIC_GPIO_PULLEN0_CLR = PMIC_BASE + 0x0098, + PMIC_RG_SPI_CON0 = PMIC_BASE + 0x0408, + PMIC_DEW_DIO_EN = PMIC_BASE + 0x040c, + PMIC_DEW_READ_TEST = PMIC_BASE + 0x040e, + PMIC_DEW_WRITE_TEST = PMIC_BASE + 0x0410, + PMIC_DEW_CRC_EN = PMIC_BASE + 0x0414, + PMIC_DEW_CRC_VAL = PMIC_BASE + 0x0416, + PMIC_DEW_RDDMY_NO = PMIC_BASE + 0x0424, + PMIC_RG_SPI_CON2 = PMIC_BASE + 0x0426, + PMIC_SPISLV_KEY = PMIC_BASE + 0x044a, + PMIC_INT_STA = PMIC_BASE + 0x0452, + PMIC_AUXADC_ADC7 = PMIC_BASE + 0x1096, + PMIC_AUXADC_ADC10 = PMIC_BASE + 0x109c, + PMIC_AUXADC_RQST0 = PMIC_BASE + 0x1108, +}; + +#define PMIF_SPI_MD_SWINF_NO 0 +#define PMIF_SPI_AP_SECURE_SWINF_NO 1 +#define PMIF_SPI_AP_SWINF_NO 2 +#define PMIF_SPI_SWINF_0_CHAN_NO 8 +#define PMIF_SPI_MD_SWINF_CHAN_NO BIT(PMIF_SPI_SWINF_0_CHAN_NO + PMIF_SPI_MD_SWINF_NO) +#define PMIF_SPI_AP_SECURE_SWINF_CHAN_NO BIT(PMIF_SPI_SWINF_0_CHAN_NO + PMIF_SPI_AP_SECURE_SWINF_NO) +#define PMIF_SPI_AP_SWINF_CHAN_NO BIT(PMIF_SPI_SWINF_0_CHAN_NO + PMIF_SPI_AP_SWINF_NO) + +#define DEFAULT_SLVID 0 + +#define GET_PMICSPI_BUSY(x) ((x>>9) & 0x00000001) +#define GET_CMDISSUE_BUSY(x) ((x>>2) & 0x00000001) + +enum { + SPI_CLK = 0x1, + SPI_CSN = 0x1 << 1, + SPI_MOSI = 0x1 << 2, + SPI_MISO = 0x1 << 3, + SPI_FILTER = (SPI_CLK | SPI_CSN | SPI_MOSI | SPI_MISO) << 4, + SPI_SMT = (SPI_CLK | SPI_CSN | SPI_MOSI | SPI_MISO), + SPI_PULL_DISABLE = (SPI_CLK | SPI_CSN | SPI_MOSI | SPI_MISO) << 4, +}; + +enum { + IO_4_MA = 0x8, +}; + +enum { + SPI_CLK_SHIFT = 0, + SPI_CSN_SHIFT = 4, + SPI_MOSI_SHIFT = 8, + SPI_MISO_SHIFT = 12, + SPI_DRIVING = (IO_4_MA << SPI_CLK_SHIFT | IO_4_MA << SPI_CSN_SHIFT | + IO_4_MA << SPI_MOSI_SHIFT | IO_4_MA << SPI_MISO_SHIFT), +}; + +enum { + OP_WR = 0x1, + OP_CSH = 0x0, + OP_CSL = 0x1, + OP_OUTS = 0x8, +}; + +enum { + DEFAULT_VALUE_READ_TEST = 0x5aa5, + WRITE_TEST_VALUE = 0xa55a +}; + +enum { + DUMMY_READ_CYCLES = 0X8, +}; + +enum { + E_CLK_EDGE = 1, + E_CLK_LAST_SETTING +}; +extern int pmif_spi_init(struct pmif *arb); +#endif /* __SOC_MEDIATEK_MT8192_PMIC_WRAP_H__ */ diff --git a/src/soc/mediatek/mt8192/include/soc/pmif_spmi.h b/src/soc/mediatek/mt8192/include/soc/pmif_spmi.h new file mode 100644 index 0000000..5f89ddc --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/pmif_spmi.h @@ -0,0 +1,143 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __PMIF_SPMI_H__ +#define __PMIF_SPMI_H__ + +#include <soc/addressmap.h> + +#define DEFAULT_VALUE_READ_TEST (0x5a) +#define DEFAULT_VALUE_WRITE_TEST (0xa5) + +#define GET_REC_CMD(x) (x & 0x00000003) +#define GET_REC_W(x) ((x>>2) & 0x00000001) +#define GET_REC_OP_ST_NACK(x) ((x>>3) & 0x00000001) +#define GET_REC_PMIF_NACK(x) ((x>>4) & 0x00000001) +#define GET_REC_PMIF_PARITY_ERR(x) ((x>>5) & 0x00000001) +#define GET_REC_PMIF_BYTE_ERR(x) ((x>>6) & 0x00000001) +#define GET_REC_PMIF_GRP_RD_ERR(x) ((x>>7) & 0x00000001) +#define GET_REC_SLVID(x) ((x>>8) & 0x0000000f) +#define GET_REC_BYTECNT(x) ((x>>12) & 0x0000000f) +#define GET_REC_ADDR(x) ((x>>16) & 0x0000ffff) + +/* + * GPIO number for IO driving config, + * These can be look up by platform/<mtxxxx>/src/drivers/inc/gpio_cfg.h + * must check by platform + */ +#define SPMI_SCL_GPIO 89 +#define SPMI_SDA_GPIO 90 +#define SPMI_SCL_DRV_SHIFT (3) +#define SPMI_SDA_DRV_SHIFT (6) + +#define SPMIMST_RST_SHIFT 4 +#define WDT_UNLOCK_SHIFT 24 + +#define WDT_UNLOCK_KEY 0x85 + +struct mtk_rgu_regs { + u32 reserved[36]; + u32 wdt_swsysrst2; +}; +check_member(mtk_rgu_regs, wdt_swsysrst2, 0x0090); + +struct mtk_iocfg_bm_regs { + u32 reserved[9]; + u32 drv_cfg2_set; + u32 drv_cfg2_clr; +}; +check_member(mtk_iocfg_bm_regs, drv_cfg2_set, 0x0024); +check_member(mtk_iocfg_bm_regs, drv_cfg2_clr, 0x0028); + +struct mtk_spm_regs { + u32 poweron_config_en; + u32 reserved[263]; + u32 ulposc_con; +}; +check_member(mtk_spm_regs, ulposc_con, 0x0420); + +struct mtk_spmi_mst_reg { + u32 op_st_ctrl; + u32 grp_id_en; + u32 op_st_sta; + u32 mst_sampl; + u32 mst_req_en; + u32 reserved1[11]; + u32 rec_ctrl; + u32 rec0; + u32 rec1; + u32 rec2; + u32 rec3; + u32 rec4; + u32 reserved2[41]; + u32 mst_dbg; +}; + +check_member(mtk_spmi_mst_reg, rec_ctrl, 0x40); +check_member(mtk_spmi_mst_reg, mst_dbg, 0xfc); + +#define mtk_rug ((struct mtk_rgu_regs *)RGU_BASE) +#define mtk_iocfg_bm ((struct mtk_iocfg_bm_regs *)IOCFG_BM_BASE) +#define mtk_spm ((struct mtk_spm_regs *)SPM_BASE) +#define mtk_spmi_mst ((struct mtk_spmi_mst_reg *)SPMI_MST_BASE) + +struct cali { + unsigned int dly; + unsigned int pol; +}; + +enum +{ + SPMI_CK_NO_DLY = 0, + SPMI_CK_DLY_1T +}; + +enum +{ + SPMI_CK_POL_NEG = 0, + SPMI_CK_POL_POS +}; + +enum +{ + SPMI_OP_ST_BUSY = 1, + SPMI_OP_ST_ACK = 0, + SPMI_OP_ST_NACK = 1 +}; + +enum +{ + SPMI_RCS_SR_BIT, + SPMI_RCS_A_BIT +}; + +enum +{ + SPMI_RCS_MST_W = 1, + SPMI_RCS_SLV_W = 3 +}; + +enum +{ + SPMI_RESET = 0, + SPMI_SLEEP, + SPMI_SHUTDOWN, + SPMI_WAKEUP +}; + +enum spmi_regs { + SPMI_OP_ST_CTRL, + SPMI_GRP_ID_EN, + SPMI_OP_ST_STA, + SPMI_MST_SAMPL, + SPMI_MST_REQ_EN, + SPMI_REC_CTRL, + SPMI_REC0, + SPMI_REC1, + SPMI_REC2, + SPMI_REC3, + SPMI_REC4, + SPMI_MST_DBG +}; + +extern int pmif_spmi_init(struct pmif *arb); +#endif /*__PMIF_SPMI_H__*/ diff --git a/src/soc/mediatek/mt8192/include/soc/pmif_sw.h b/src/soc/mediatek/mt8192/include/soc/pmif_sw.h new file mode 100644 index 0000000..1d250bf --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/pmif_sw.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __PMIF_SW_H__ +#define __PMIF_SW_H__ + +/* Read/write byte limitation, by project */ +/* hw bytecnt indicate when we set 0, it can send 1 byte; + * set 1, it can send 2 byte. + */ +#define PMIF_BYTECNT_MAX 1 + +/* macro for SWINF_FSM */ +#define SWINF_FSM_IDLE (0x00) +#define SWINF_FSM_REQ (0x02) +#define SWINF_FSM_WFDLE (0x04) +#define SWINF_FSM_WFVLDCLR (0x06) +#define SWINF_INIT_DONE (0x01) + +/* indicate which number SW channel start, by project */ +#define PMIF_SWINF_0_CHAN_NO 4 + +/* MD: 0, security domain: 1, AP: 2 */ +#define PMIF_AP_SWINF_NO 2 + +#define GET_SWINF_0_FSM(x) ((x >> 1) & 0x7) + +struct pmif_mpu { + unsigned int rgn_slvid; + unsigned short rgn_s_addr; + unsigned short rgn_e_addr; + unsigned int rgn_domain_per; +}; + +enum { + PMIF_READ_US = 1000, + PMIF_WAIT_IDLE_US = 1000, +}; +extern int pmif_clk_init(void); +#endif /*__PMIF_SW_H__*/ diff --git a/src/soc/mediatek/mt8192/include/soc/spmi.h b/src/soc/mediatek/mt8192/include/soc/spmi.h new file mode 100644 index 0000000..61e49b5 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/spmi.h @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SPMI_H__ +#define __SPMI_H__ + +/* enum marco for cmd/channel */ +enum spmi_master +{ + SPMI_MASTER_0, + SPMI_MASTER_1, + SPMI_MASTER_2, + SPMI_MASTER_3 +}; + +enum spmi_slave +{ + SPMI_SLAVE_0, + SPMI_SLAVE_1, + SPMI_SLAVE_2, + SPMI_SLAVE_3, + SPMI_SLAVE_4, + SPMI_SLAVE_5, + SPMI_SLAVE_6, + SPMI_SLAVE_7, + SPMI_SLAVE_8, + SPMI_SLAVE_9, + SPMI_SLAVE_10, + SPMI_SLAVE_11, + SPMI_SLAVE_12, + SPMI_SLAVE_13, + SPMI_SLAVE_14, + SPMI_SLAVE_15 +}; + +enum slv_type +{ + BUCK_CPU, + BUCK_GPU, + BUCK_MD, + BUCK_RF, + MAIN_PMIC, + BUCK_VPU, + SUB_PMIC, + SLV_TYPE_MAX +}; + +enum slv_type_id +{ + BUCK_RF_ID = 1, + BUCK_MD_ID = 3, + MAIN_PMIC_ID = 5, + BUCK_CPU_ID = 6, + BUCK_GPU_ID = 7, + BUCK_VPU_ID, + SUB_PMIC_ID = 10, + SLV_TYPE_ID_MAX +}; + +struct spmi_device { + int slvid; + int grpiden; + enum slv_type type; + enum slv_type_id type_id; +}; +#endif /*__SPMI_H__*/ diff --git a/src/soc/mediatek/mt8192/pmif.c b/src/soc/mediatek/mt8192/pmif.c new file mode 100644 index 0000000..ca42d37 --- /dev/null +++ b/src/soc/mediatek/mt8192/pmif.c @@ -0,0 +1,176 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <console/console.h> +#include <device/mmio.h> +#include <soc/addressmap.h> +#include <soc/pmif.h> +#include <soc/pmif_spi.h> +#include <soc/pmif_spmi.h> +#include <soc/pmif_sw.h> +#include <soc/spmi.h> +#include <string.h> +#include <timer.h> + +static unsigned int pmif_check_idle(struct pmif *arb, unsigned int timeout_us) { + unsigned int reg_rdata; + struct stopwatch sw; + + stopwatch_init_usecs_expire(&sw, timeout_us); + do { + reg_rdata = read32(&arb->mtk_pmif->swinf_0_sta + 0x10 * arb->swinf_no); + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, "[%s] timeout\n", __func__); + return E_TIMEOUT; + } + } while (GET_SWINF_0_FSM(reg_rdata) != SWINF_FSM_IDLE); + + return 0; +} + +static inline unsigned int pmif_check_vldclr(struct pmif *arb, unsigned int timeout_us) { + unsigned int reg_rdata; + struct stopwatch sw; + + stopwatch_init_usecs_expire(&sw, timeout_us); + do { + reg_rdata = read32(&arb->mtk_pmif->swinf_0_sta + 0x10 * arb->swinf_no); + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, "[%s] timeout\n", __func__); + return E_TIMEOUT; + } + } while (GET_SWINF_0_FSM(reg_rdata) != SWINF_FSM_WFVLDCLR); + + return 0; +} + +static int pmif_send_cmd(struct pmif *arb, unsigned int write, + unsigned int opc, unsigned int slvid, unsigned int addr, + unsigned int *rdata, unsigned int wdata, unsigned int len) +{ + unsigned int ret = 0, data = 0; + unsigned int bc = len - 1; + + bc = 0; + /* Wait for Software Interface FSM state to be IDLE. */ + ret = pmif_check_idle(arb, PMIF_WAIT_IDLE_US); + if(ret) + return ret; + + /* Set the write data */ + if (write == 1) { + /* Set the write data. */ + write32(&arb->mtk_pmif->swinf_0_wdata_31_0 + 0x10 * arb->swinf_no, wdata); + } + + /* Send the command. */ + write32(&arb->mtk_pmif->swinf_0_acc + 0x10 * arb->swinf_no, + (opc << 30) | (write << 29) | (slvid << 24) | (bc << 16) | addr); + + if (write == 0) { + /* Wait for Software Interface FSM state to be WFVLDCLR, + * + * read the data and clear the valid flag. + */ + ret = pmif_check_vldclr(arb, PMIF_READ_US); + if(ret) + return ret; + + data = read32(&arb->mtk_pmif->swinf_0_rdata_31_0 + 0x10 * arb->swinf_no); + *rdata = data; + write32(&arb->mtk_pmif->swinf_0_vld_clr + 0x10 * arb->swinf_no, 0x1); + } + + return 0; +} + +static int pmif_spmi_read_cmd(struct pmif *arb,unsigned int slvid, + unsigned int addr, unsigned int *rdata) +{ + + return pmif_send_cmd(arb, 0, PMIF_CMD_EXT_REG_LONG, slvid, addr, rdata, 0, (PMIF_BYTECNT_MAX - 1)); +} + +static int pmif_spmi_write_cmd(struct pmif *arb, unsigned int slvid, + unsigned int addr, unsigned int wdata) +{ + return pmif_send_cmd(arb, 1, PMIF_CMD_EXT_REG_LONG, slvid, addr, NULL, wdata, (PMIF_BYTECNT_MAX - 1)); +} + +static int pmif_spi_read_cmd(struct pmif *arb, unsigned int slvid, + unsigned int addr, unsigned int *rdata) +{ + + return pmif_send_cmd(arb, 0, PMIF_CMD_REG_0, slvid, addr, rdata, 0, (PMIF_BYTECNT_MAX - 1)); +} + +static int pmif_spi_write_cmd(struct pmif *arb, unsigned int slvid, + unsigned int addr, unsigned int wdata) +{ + return pmif_send_cmd(arb, 1, PMIF_CMD_REG_0, slvid, addr, NULL, wdata, (PMIF_BYTECNT_MAX - 1)); +} + +static int is_pmif_init_done(struct pmif *arb) +{ + if ((read32(&arb->mtk_pmif->init_done) & 0x1)) + return 0; + + return -E_NODEV; +} + +static struct pmif pmif_spmi_arb[] = { + { + .mtk_pmif = (struct mtk_pmif_regs *)PMIF_SPMI_BASE, + .swinf_ch_start = PMIF_SWINF_0_CHAN_NO, + .swinf_no = PMIF_AP_SWINF_NO, + .mstid = SPMI_MASTER_0, + .pmifid = PMIF_SPMI, + .write_cmd = pmif_spmi_write_cmd, + .read_cmd = pmif_spmi_read_cmd, + .is_pmif_init_done = is_pmif_init_done, + }, +}; + +static struct pmif pmif_spi_arb[] = { + { + .mtk_pmif = (struct mtk_pmif_regs *)PMIF_SPI_BASE, + .swinf_no = PMIF_AP_SWINF_NO, + .pmifid = PMIF_SPI, + .write_cmd = pmif_spi_write_cmd, + .read_cmd = pmif_spi_read_cmd, + .is_pmif_init_done = is_pmif_init_done, + }, +}; + +struct pmif *get_pmif_controller(int inf, int mstid) +{ + if (inf == PMIF_SPMI) + return &pmif_spmi_arb[mstid]; + else if (inf == PMIF_SPI) + return &pmif_spi_arb[0]; + + return NULL; +} + +int mtk_pmif_init(void) +{ + int ret = 1; + + ret = pmif_clk_init(); + if (ret) + goto FAIL; + + ret = pmif_spmi_init(&pmif_spmi_arb[SPMI_MASTER_0]); + if (ret) + goto FAIL; + + ret = pmif_spi_init(&pmif_spi_arb[0]); + if (ret) + goto FAIL; + + return 0; + +FAIL: + /* assert(0); */ + return ret; +} diff --git a/src/soc/mediatek/mt8192/pmif_clk.c b/src/soc/mediatek/mt8192/pmif_clk.c new file mode 100644 index 0000000..96dfe0e --- /dev/null +++ b/src/soc/mediatek/mt8192/pmif_clk.c @@ -0,0 +1,234 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <delay.h> +#include <device/mmio.h> +#include <soc/infracfg.h> +#include <soc/pll.h> +#include <soc/pll_common.h> +#include <soc/pmif.h> +#include <soc/pmif_sw.h> +#include <soc/pmif_spmi.h> + +#define FREQ_260MHZ 260 +/* calibation miss rate, unit: 0.1% */ +#define CAL_MIS_RATE 40 +/* + * FREQ METER ID + * Ask clkmgr owner to find this information + * at clock table[fmeter]. + */ +#define FREQ_METER_ABIST_AD_OSC_CK 37 +#define CAL_MAX_VAL 0x7f + +static unsigned int mt_get_abist_freq(unsigned int ID) +{ + int output = 0, i = 0; + unsigned int temp, clk26cali_0, clk_dbg_cfg, clk_misc_cfg_0, clk26cali_1; + + clk_dbg_cfg = read32(&mtk_topckgen->clk_dbg_cfg); + /* sel abist_cksw and enable freq meter sel abist */ + write32(&mtk_topckgen->clk_dbg_cfg, (clk_dbg_cfg & 0xFFC0FFFC)|(ID << 16)); + + clk_misc_cfg_0 = read32(&mtk_topckgen->clk_misc_cfg_0); + /* select divider, div 4 */ + write32(&mtk_topckgen->clk_misc_cfg_0, (clk_misc_cfg_0 & 0x00FFFFFF) | (3 << 24)); + + clk26cali_0 = read32(&mtk_topckgen->clk26cali_0); + clk26cali_1 = read32(&mtk_topckgen->clk26cali_1); + write32(&mtk_topckgen->clk26cali_0, 0x1000); + write32(&mtk_topckgen->clk26cali_0, 0x1010); + + /* wait frequency meter finish */ + while (read32(&mtk_topckgen->clk26cali_0) & 0x10) + { + udelay(10); + i++; + if(i > 100) + break; + } + + temp = read32(&mtk_topckgen->clk26cali_1) & 0xFFFF; + output = ((temp * 26000) ) / 1024; /* Khz */ + + write32(&mtk_topckgen->clk_dbg_cfg, clk_dbg_cfg); + write32(&mtk_topckgen->clk_misc_cfg_0, clk_misc_cfg_0); + write32(&mtk_topckgen->clk26cali_0, clk26cali_0); + write32(&mtk_topckgen->clk26cali_1, clk26cali_1); + + return output * 4; +} + +static void pmif_ulposc_config(void) +{ + /* Config ULPOSC_CON0 */ + /* OSC_CP_EN = 0 */ + write32(&mtk_apmixed->ulposc1_con0, read32(&mtk_apmixed->ulposc1_con0) &~(0x1 << 24)); + + /* OSC_DIV = 1110 */ + write32(&mtk_apmixed->ulposc1_con0, read32(&mtk_apmixed->ulposc1_con0) &~(0x3f << 18)); + write32(&mtk_apmixed->ulposc1_con0, read32(&mtk_apmixed->ulposc1_con0) | (0xe << 18)); + + /* OSC_FBAND = 0010 */ + write32(&mtk_apmixed->ulposc1_con0, read32(&mtk_apmixed->ulposc1_con0) &~(0xf << 14)); + write32(&mtk_apmixed->ulposc1_con0, read32(&mtk_apmixed->ulposc1_con0) | (0x2 << 14)); + + /* OSC_IBAND = 1010010 */ + write32(&mtk_apmixed->ulposc1_con0, read32(&mtk_apmixed->ulposc1_con0) &~(0x7f << 7)); + write32(&mtk_apmixed->ulposc1_con0, read32(&mtk_apmixed->ulposc1_con0) | (0x52 << 7)); + + /* OSC_CALI = 1000000 */ + write32(&mtk_apmixed->ulposc1_con0, read32(&mtk_apmixed->ulposc1_con0) &~(0x7f)); + write32(&mtk_apmixed->ulposc1_con0, read32(&mtk_apmixed->ulposc1_con0) | 0x40); + + /* + **** Config ULPOSC_CON1 *** + */ + + /* OSC_DIV2_EN= 1b'0 */ + write32(&mtk_apmixed->ulposc1_con1, read32(&mtk_apmixed->ulposc1_con1) &~(0x1 << 26)); + + /* OSC_MOD = 00 */ + write32(&mtk_apmixed->ulposc1_con1, read32(&mtk_apmixed->ulposc1_con1) &~(0x3 << 24)); + + /* OSC_RSV2= 8b'00000000 */ + write32(&mtk_apmixed->ulposc1_con1, read32(&mtk_apmixed->ulposc1_con1) &~(0xff << 16)); + + /* OSC_RSV1= 8b'00101001 */ + write32(&mtk_apmixed->ulposc1_con1, read32(&mtk_apmixed->ulposc1_con1) &~(0xff << 8)); + write32(&mtk_apmixed->ulposc1_con1, read32(&mtk_apmixed->ulposc1_con1) | (0x29 << 8)); + + /* OSC_32KCALI = 8b'00000000 */ + write32(&mtk_apmixed->ulposc1_con1, read32(&mtk_apmixed->ulposc1_con1) &~(0xff)); + + /* + **** Config ULPOSC_CON2 *** + */ + + /* OSC_BIAS= 8b'01000010 */ + write32(&mtk_apmixed->ulposc1_con2, read32(&mtk_apmixed->ulposc1_con2) &~(0xff)); + write32(&mtk_apmixed->ulposc1_con2, read32(&mtk_apmixed->ulposc1_con2) | (0x40)); + +} + +static u32 pmif_get_ulposc_freq(u32 cali_val) +{ + u32 result = 0; + + /* set calibration value */ + write32(&mtk_apmixed->ulposc1_con0, read32(&mtk_apmixed->ulposc1_con0) &~(0x7f)); + write32(&mtk_apmixed->ulposc1_con0, read32(&mtk_apmixed->ulposc1_con0) | cali_val); + + udelay(50); + + result = mt_get_abist_freq(FREQ_METER_ABIST_AD_OSC_CK); + + return result / 1000; +} + +static int pmif_ulposc_cali(void) +{ + u32 current_val = 0, min = 0, max = CAL_MAX_VAL, middle; + u32 diff_by_min = 0, diff_by_max = 0xffff, cal_result; + int ret = 0; + + do { + middle = (min + max) / 2; + if (middle == min) + break; + + current_val = pmif_get_ulposc_freq(middle); + + if (current_val > FREQ_260MHZ) + max = middle; + else + min = middle; + } while (min <= max); + + current_val = pmif_get_ulposc_freq(min); + if (current_val > FREQ_260MHZ) + diff_by_min = current_val - FREQ_260MHZ; + else + diff_by_min = FREQ_260MHZ - current_val; + + current_val = pmif_get_ulposc_freq(max); + if (current_val > FREQ_260MHZ) + diff_by_max = current_val - FREQ_260MHZ; + else + diff_by_max = FREQ_260MHZ - current_val; + + if (diff_by_min < diff_by_max) { + cal_result = min; + current_val = pmif_get_ulposc_freq(min); + } else { + cal_result = max; + current_val = pmif_get_ulposc_freq(max); + } + + /* check if calibrated value is in the range of target value +- 15% */ + if (current_val < (FREQ_260MHZ * (1000 - CAL_MIS_RATE) / 1000) + || current_val > (FREQ_260MHZ * (1000 + CAL_MIS_RATE) / 1000)) { + printk(BIOS_ERR, "[%s]calibration fail: %dM\n", __func__, current_val); + ret = 1; + } + + return ret; +} + +static int pmif_init_ulposc(void) +{ + int ret = 1; + + /* calibrate ULPOSC1 */ + pmif_ulposc_config(); + + /* enable spm swinf */ + if ((read32(&mtk_spm->poweron_config_en) & 0x1) != 0x1) + write32(&mtk_spm->poweron_config_en, (0xb16 << 16) | 0x1); + + /* turn on ulposc */ + write32(&mtk_spm->ulposc_con, read32(&mtk_spm->ulposc_con) | 0x1); + udelay(100); + write32(&mtk_spm->ulposc_con, read32(&mtk_spm->ulposc_con) | 0x1 << 2); + + ret = pmif_ulposc_cali(); + return ret; +} + +int pmif_clk_init(void) +{ + int ret = 1; + + ret = pmif_init_ulposc(); + if(ret) + return -E_NODEV; + + /* turn off pmic_cg_tmr, cg_ap, cg_md, cg_conn clock */ + write32(&mt8192_infracfg->module_sw_cg_0_set, 0xf); + /* Use MTS: modem_temp_share_cg need to enable + * DRV_WriteReg32(MODULE_SW_CG_2_SET, 0x00000020); + * Use TIA: modem_temp_share_cg not need + */ + write32(&mtk_topckgen->clk_cfg_8_clr, (0x1 << 15) | (0x1 << 12) | (0x7 << 8)); + write32(&mtk_topckgen->clk_cfg_update1, 0x1 << 2); + + /* use ULPOSC1 clock */ + write32(&mt8192_infracfg->pmicw_clock_ctrl_clr, 0xf); + + /* toggle SPMI sw reset */ + write32(&mt8192_infracfg->infra_globalcon_rst2_set, 0x1 << 14); + write32(&mt8192_infracfg->infra_globalcon_rst2_clr, 0x1 << 14); + + /* toggle SPI sw reset */ + write32(&mt8192_infracfg->infra_globalcon_rst2_set, 0x1); + write32(&mt8192_infracfg->infra_globalcon_rst2_clr, 0x1); + + /* turn on pmic_cg_tmr, cg_ap, cg_md, cg_conn clock */ + write32(&mt8192_infracfg->module_sw_cg_0_clr, 0xf); + /* Use MTS: modem_temp_share_cg need to enable + * DRV_WriteReg32(MODULE_SW_CG_2_CLR, 0x00000020); + * Use TIA: modem_temp_share_cg not need + */ + + return 0; +} diff --git a/src/soc/mediatek/mt8192/pmif_spi.c b/src/soc/mediatek/mt8192/pmif_spi.c new file mode 100644 index 0000000..e1d77aa --- /dev/null +++ b/src/soc/mediatek/mt8192/pmif_spi.c @@ -0,0 +1,319 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <delay.h> +#include <device/mmio.h> +#include <soc/infracfg.h> +#include <soc/pll.h> +#include <soc/pmif.h> +#include <soc/pmif_spi.h> +#include <soc/pmif_sw.h> +#include <timer.h> + +/* PMIF, SPI_MODE_CTRL */ +DEFINE_BIT(SPI_MODE_CTRL_VLD_SRCLK_EN_CTRL, 5) +DEFINE_BIT(SPI_MODE_CTRL_PMIF_RDY, 9) +DEFINE_BIT(SPI_MODE_CTRL_SRCLK_EN, 10) +DEFINE_BIT(SPI_MODE_CTRL_SRVOL_EN, 11) + +/* PMIF, SLEEP_PROTECTION_CTRL */ +DEFINE_BITFIELD(SPM_SLEEP_REQ_SEL, 1, 0) +DEFINE_BITFIELD(SCP_SLEEP_REQ_SEL, 10, 9) + +/* PMIF, STAUPD_CTRL */ +DEFINE_BITFIELD(STAUPD_CTRL_PRD, 3, 0) +DEFINE_BIT(STAUPD_CTRL_PMIC0_SIG_STA, 4) +DEFINE_BIT(STAUPD_CTRL_PMIC0_EINT_STA, 6) + +/* SPIMST, Manual_Mode_Access */ +DEFINE_BIT(SPI_RW, 13) +DEFINE_BITFIELD(SPI_OP, 12, 8) + +static void pmif_spi_config(struct pmif *arb) +{ + /* Set srclk_en always valid regardless of ulposc_sel_for_scp */ + SET32_BITFIELDS(&arb->mtk_pmif->spi_mode_ctrl, SPI_MODE_CTRL_VLD_SRCLK_EN_CTRL, 0); + + + /* Set SPI mode controlled by srclk_en and srvol_en instead of pmif_rdy */ + SET32_BITFIELDS(&arb->mtk_pmif->spi_mode_ctrl, SPI_MODE_CTRL_SRCLK_EN, 1, SPI_MODE_CTRL_SRVOL_EN, 1); + SET32_BITFIELDS(&arb->mtk_pmif->spi_mode_ctrl, SPI_MODE_CTRL_PMIF_RDY, 0); + + SET32_BITFIELDS(&arb->mtk_pmif->sleep_protection_ctrl, SPM_SLEEP_REQ_SEL, 0); + SET32_BITFIELDS(&arb->mtk_pmif->sleep_protection_ctrl, SCP_SLEEP_REQ_SEL, 0); + + /* Enable SWINF for AP */ + write32(&arb->mtk_pmif->inf_en, PMIF_SPI_AP_SWINF_CHAN_NO); + + /* Enable arbitration for SWINF for AP */ + write32(&arb->mtk_pmif->arb_en, PMIF_SPI_AP_SWINF_CHAN_NO); + + /* Enable PMIF_SPI Command Issue */ + write32(&arb->mtk_pmif->cmdissue_en, 1); +} + +static signed int reset_spislv(void) +{ + unsigned int pmicspi_mst_dio_en_backup, rdata; + struct stopwatch sw; + + write32(&mtk_pmicspi_mst->wrap_en, 0); + write32(&mtk_pmicspi_mst->mux_sel, 1); + write32(&mtk_pmicspi_mst->man_en, 1); + pmicspi_mst_dio_en_backup = read32(&mtk_pmicspi_mst->dio_en); + write32(&mtk_pmicspi_mst->dio_en, 0); + + SET32_BITFIELDS(&mtk_pmicspi_mst->man_acc, SPI_RW, OP_WR, SPI_OP, OP_CSL); + /* Reset counter */ + SET32_BITFIELDS(&mtk_pmicspi_mst->man_acc, SPI_RW, OP_WR, SPI_OP, OP_OUTS); + SET32_BITFIELDS(&mtk_pmicspi_mst->man_acc, SPI_RW, OP_WR, SPI_OP, OP_CSH); + /* + * In order to pull CSN signal to PMIC, + * PMIC will count it then reset spi slave + */ + SET32_BITFIELDS(&mtk_pmicspi_mst->man_acc, SPI_RW, OP_WR, SPI_OP, OP_OUTS); + SET32_BITFIELDS(&mtk_pmicspi_mst->man_acc, SPI_RW, OP_WR, SPI_OP, OP_OUTS); + SET32_BITFIELDS(&mtk_pmicspi_mst->man_acc, SPI_RW, OP_WR, SPI_OP, OP_OUTS); + SET32_BITFIELDS(&mtk_pmicspi_mst->man_acc, SPI_RW, OP_WR, SPI_OP, OP_OUTS); + + /* Wait for PMIC SPI Master to be idle */ + stopwatch_init_usecs_expire(&sw, PMIF_WAIT_IDLE_US); + do { + rdata = read32(&mtk_pmicspi_mst->other_busy_sta_0); + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, "[%s] timeout\n", __func__); + return E_TIMEOUT; + } + } while (GET_PMICSPI_BUSY(rdata) != 0x0); + + write32(&mtk_pmicspi_mst->man_en, 0); + write32(&mtk_pmicspi_mst->mux_sel, 0); + write32(&mtk_pmicspi_mst->wrap_en, 1); + write32(&mtk_pmicspi_mst->dio_en, pmicspi_mst_dio_en_backup); + + return 0; +} + +static void init_reg_clock(struct pmif *arb) +{ + unsigned int rdata; + + /* Set SoC SPI IO driving strength to 4 mA */ + write32(&mtk_iocfg_tl->drv_cfg0_clr, 0x7 << 21); + write32(&mtk_iocfg_tl->drv_cfg0_set, 0x1 << 21); + + /* Configure SPI protocol */ + write32(&mtk_pmicspi_mst->ext_ck_write, 1); + write32(&mtk_pmicspi_mst->ext_ck_read, 0); + write32(&mtk_pmicspi_mst->cshext_write, 0); + write32(&mtk_pmicspi_mst->cshext_read, 0); + write32(&mtk_pmicspi_mst->cslext_write, 0); + write32(&mtk_pmicspi_mst->cslext_read, 0x100); + + /* Set Read Dummy Cycle Number (Slave Clock is 18MHz) */ + arb->write_cmd(arb, DEFAULT_SLVID, PMIC_DEW_RDDMY_NO, DUMMY_READ_CYCLES); + write32(&mtk_pmicspi_mst->rddmy, DUMMY_READ_CYCLES); + + /* Enable DIO mode */ + arb->write_cmd(arb, DEFAULT_SLVID, PMIC_DEW_DIO_EN, 0x1); + + /* Wait for completion of sending the commands */ + do { + rdata = read32(&arb->mtk_pmif->inf_busy_sta); + } while ((rdata & PMIF_SPI_AP_SWINF_CHAN_NO) != 0x0); + + do { + rdata = read32(&arb->mtk_pmif->other_busy_sta_0); + } while (GET_CMDISSUE_BUSY(rdata) != 0x0); + + do { + rdata = read32(&mtk_pmicspi_mst->other_busy_sta_0); + } while (GET_PMICSPI_BUSY(rdata) != 0x0); + + write32(&mtk_pmicspi_mst->dio_en, 1); +} + +static void init_spislv(struct pmif *arb) +{ + /* Turn on SPI IO filter function */ + arb->write_cmd(arb, DEFAULT_SLVID, PMIC_FILTER_CON0, SPI_FILTER); + /* Turn on SPI IO SMT function to improve noise immunity */ + arb->write_cmd(arb, DEFAULT_SLVID, PMIC_SMT_CON1, SPI_SMT); + /* Turn off SPI IO pull function for power saving */ + arb->write_cmd(arb, DEFAULT_SLVID, PMIC_GPIO_PULLEN0_CLR, SPI_PULL_DISABLE); + /* Enable SPI access in SODI-3.0 and Suspend modes */ + arb->write_cmd(arb, DEFAULT_SLVID, PMIC_RG_SPI_CON0, 0x2); + /* Set SPI IO driving strength to 4 mA */ + arb->write_cmd(arb, DEFAULT_SLVID, PMIC_DRV_CON1, SPI_DRIVING); +} + +static s32 init_sistrobe(struct pmif *arb) +{ + unsigned int rdata = 0; + int si_sample_ctrl; + int test_data[30] = { + 0x6996, 0x9669, 0x6996, 0x9669, 0x6996, 0x9669, 0x6996, + 0x9669, 0x6996, 0x9669, 0x5AA5, 0xA55A, 0x5AA5, 0xA55A, + 0x5AA5, 0xA55A, 0x5AA5, 0xA55A, 0x5AA5, 0xA55A, 0x1B27, + 0x1B27, 0x1B27, 0x1B27, 0x1B27, 0x1B27, 0x1B27, 0x1B27, + 0x1B27, 0x1B27}; + + for (si_sample_ctrl = 0; si_sample_ctrl < 16; si_sample_ctrl++) { + write32(&mtk_pmicspi_mst->si_sampling_ctrl, si_sample_ctrl << 5); + + arb->read_cmd(arb, DEFAULT_SLVID, PMIC_DEW_READ_TEST, &rdata); + if (rdata == DEFAULT_VALUE_READ_TEST) + break; + } + + if (si_sample_ctrl == 16) + return E_CLK_EDGE; + + if (si_sample_ctrl == 15) + return E_CLK_LAST_SETTING; + + /* + * Add the delay time of SPI data from PMIC to align the start boundary + * to current sampling clock edge. + */ + for (int si_dly = 0; si_dly < 10; si_dly++) { + arb->write_cmd(arb, DEFAULT_SLVID, PMIC_RG_SPI_CON2, si_dly); + + int start_boundary_found = 0; + for (size_t i = 0; i < 30; i++) { + arb->write_cmd(arb, DEFAULT_SLVID, PMIC_DEW_WRITE_TEST, test_data[i]); + arb->read_cmd(arb, DEFAULT_SLVID, PMIC_DEW_WRITE_TEST, &rdata); + if ((rdata & 0x7fff) != (test_data[i] & 0x7fff)) { + start_boundary_found = 1; + break; + } + } + if (start_boundary_found == 1) + break; + } + + /* + * Change the sampling clock edge to the next one which is the middle + * of SPI data window. + */ + write32(&mtk_pmicspi_mst->si_sampling_ctrl, ++si_sample_ctrl << 5); + + /* Read Test */ + arb->read_cmd(arb, DEFAULT_SLVID, PMIC_DEW_READ_TEST, &rdata); + if (rdata != DEFAULT_VALUE_READ_TEST) { + printk(BIOS_ERR, "[%s] rdata = %#x, exp = %#x\n", + __func__, rdata, DEFAULT_VALUE_READ_TEST); + return E_READ_TEST_FAIL; + } + + return 0; +} + +static void initstaupd(struct pmif *arb) +{ + unsigned int rdata; + + /* Unlock SPI Slave registers */ + arb->write_cmd(arb, DEFAULT_SLVID, PMIC_SPISLV_KEY, 0xbade); + + /* Enable CRC of PMIC 0 */ + arb->write_cmd(arb, DEFAULT_SLVID, PMIC_DEW_CRC_EN, 0x1); + + /* Wait for completion of sending the commands */ + do { + rdata = read32(&arb->mtk_pmif->inf_busy_sta); + } while ((rdata & PMIF_SPI_AP_SWINF_CHAN_NO) != 0x0); + + do { + rdata = read32(&arb->mtk_pmif->other_busy_sta_0); + } while (GET_CMDISSUE_BUSY(rdata) != 0x0); + + do { + rdata = read32(&mtk_pmicspi_mst->other_busy_sta_0); + } while (GET_PMICSPI_BUSY(rdata) != 0x0); + + /* Configure CRC of PMIC Interface */ + write32(&arb->mtk_pmif->crc_ctrl, 0x1); + write32(&arb->mtk_pmif->sig_mode, 0x0); + + /* Lock SPI Slave registers */ + arb->write_cmd(arb, DEFAULT_SLVID, PMIC_SPISLV_KEY, 0x0); + + /* Setup PMIC Siganature */ + write32(&arb->mtk_pmif->pmic_sig_addr, PMIC_DEW_CRC_VAL); + + /* Setup PMIC EINT */ + write32(&arb->mtk_pmif->pmic_eint_sta_addr, PMIC_INT_STA); + + SET32_BITFIELDS(&arb->mtk_pmif->staupd_ctrl, STAUPD_CTRL_PRD, 5, + STAUPD_CTRL_PMIC0_SIG_STA, 1, STAUPD_CTRL_PMIC0_EINT_STA, 1); +} + +int pmif_spi_init(struct pmif *arb) +{ + int sub_return = 0; + + pmif_spi_config(arb); + + /* Reset spislv */ + sub_return = reset_spislv(); + if (sub_return != 0) + return E_SPI_INIT_RESET_SPI; + + /* Enable WRAP */ + write32(&mtk_pmicspi_mst->wrap_en, 0x1); + + /* SPI Waveform Configuration */ + init_reg_clock(arb); + + /* SPI Slave Configuration */ + init_spislv(arb); + + /* Input data calibration flow; */ + sub_return = init_sistrobe(arb); + if (sub_return != 0) { + printk(BIOS_ERR, "[%s] data calibration fail,ret=%d\n", + __func__, sub_return); + return E_SPI_INIT_SIDLY; + } + + /* Lock SPISLV Registers */ + arb->write_cmd(arb, DEFAULT_SLVID, PMIC_SPISLV_KEY, 0x0); + + /* + * Status update function initialization + * 1. Signature Checking using CRC (CRC 0 only) + * 2. EINT update + * 3. Read back Auxadc thermal data for GPS + */ + initstaupd(arb); + + /* Configure PMIF Timer */ + write32(&arb->mtk_pmif->timer_ctrl, 0x3); + + /* Enable interfaces and arbitration */ + write32(&arb->mtk_pmif->inf_en, 0x307f | + PMIF_SPI_MD_SWINF_CHAN_NO | + PMIF_SPI_AP_SECURE_SWINF_CHAN_NO | + PMIF_SPI_AP_SWINF_CHAN_NO); + + write32(&arb->mtk_pmif->arb_en, 0x707f | + PMIF_SPI_MD_SWINF_CHAN_NO | + PMIF_SPI_AP_SECURE_SWINF_CHAN_NO | + PMIF_SPI_AP_SWINF_CHAN_NO); + + /* Enable GPS AUXADC HW 0 and 1 */ + write32(&arb->mtk_pmif->arb_en, read32(&arb->mtk_pmif->arb_en) | (0x3 << 19)); + write32(&arb->mtk_pmif->other_inf_en, read32(&arb->mtk_pmif->other_inf_en) | (0x3 << 4)); + + /* Set INIT_DONE */ + write32(&arb->mtk_pmif->init_done, 0x1); + + /* Configure MD ADC Interface */ + udelay(100); + + /* write MODEM_TEMP_SHARE_CTRL start */ + write32(&mtk_modem_temp_share->ctrl, 0xf0); + + return 0; +} diff --git a/src/soc/mediatek/mt8192/pmif_spmi.c b/src/soc/mediatek/mt8192/pmif_spmi.c new file mode 100644 index 0000000..4a9af68 --- /dev/null +++ b/src/soc/mediatek/mt8192/pmif_spmi.c @@ -0,0 +1,256 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/pmif.h> +#include <soc/spmi.h> +#include <soc/pmif_sw.h> +#include <soc/pmif_spmi.h> +#include <soc/addressmap.h> +#include <device/mmio.h> +#include <string.h> +#include <console/console.h> +#include <soc/pll.h> +#include <soc/pll_common.h> + +#define PMIF_CMD_PER_3 (0x1 << PMIF_CMD_EXT_REG_LONG) +#define PMIF_CMD_PER_1_3 \ + ((0x1 << PMIF_CMD_REG) | (0x1 << PMIF_CMD_EXT_REG_LONG)) +#define PMIF_CMD_PER_2_3 \ + ((0x1 << PMIF_CMD_EXT_REG) | (0x1 << PMIF_CMD_EXT_REG_LONG)) + +/* spmi master setting */ +struct spmi_device spmi_dev[] = { + { + .slvid = SPMI_SLAVE_6, + .grpiden = 0x800, + .type = BUCK_CPU, + .type_id = BUCK_CPU_ID, + }, { + .slvid = SPMI_SLAVE_7, + .grpiden = 0x800, + .type = BUCK_GPU, + .type_id = BUCK_GPU_ID, + }, +}; + +static int spmi_config_io(void) +{ + /* 0'b010 SPMI_SCL[5:3]; */ + write32(&mtk_iocfg_bm->drv_cfg2_set, 0x2 << SPMI_SCL_DRV_SHIFT); + write32(&mtk_iocfg_bm->drv_cfg2_clr, 0x5 << SPMI_SCL_DRV_SHIFT); + /* 0'b010 SPMI_SDA[6:8] */ + write32(&mtk_iocfg_bm->drv_cfg2_set, 0x2 << SPMI_SDA_DRV_SHIFT); + write32(&mtk_iocfg_bm->drv_cfg2_clr, 0x5 << SPMI_SDA_DRV_SHIFT); + + return 0; +} + +static int spmi_config_master(void) +{ + /* Software reset */ + write32(&mtk_rug->wdt_swsysrst2, + (WDT_UNLOCK_KEY << WDT_UNLOCK_SHIFT) | \ + (0x1 << SPMIMST_RST_SHIFT)); + + write32(&mtk_topckgen->clk_cfg_15_clr, (0x700) | (0x1 << 12) | (0x1 << 15)); + write32(&mtk_topckgen->clk_cfg_update2, (0x1 << 30)); + + /* Software reset */ + write32(&mtk_rug->wdt_swsysrst2, (WDT_UNLOCK_KEY << WDT_UNLOCK_SHIFT)); + + /* Enable SPMI */ + write32(&mtk_spmi_mst->mst_req_en, 1); + + return 0; +} + +static int spmi_read_check(struct pmif *pmif_arb, int slvid) +{ + unsigned int rdata = 0; + + + /* MT6315_PMIC_HWCID_H_ADDR/MT6315_HWCID_H 0x9 */ + pmif_arb->read_cmd(pmif_arb, slvid, 0x9, &rdata); + if (rdata != 0x15) { + printk(BIOS_ERR, "%s next, slvid:%d rdata = 0x%x.\n", + __func__, slvid, rdata); + return -E_IO; + } + + /*MT6315_PMIC_SWCID_H_ADDR/MT6315_SWCID_H 0xb*/ + pmif_arb->read_cmd(pmif_arb, slvid, 0xb, &rdata); + if (rdata != 0x15) { + printk(BIOS_ERR, "%s next, slvid:%d rdata = 0x%x.\n", + __func__, slvid, rdata); + return -E_IO; + } + + return 0; +} + +static int spmi_cali_rd_clock_polarity(struct pmif *pmif_arb, struct spmi_device *dev) +{ + unsigned int i = 0; + struct cali cali_data[] = { + {SPMI_CK_DLY_1T, SPMI_CK_POL_POS}, + {SPMI_CK_NO_DLY, SPMI_CK_POL_POS}, + {SPMI_CK_NO_DLY, SPMI_CK_POL_NEG} + }; + + /* Indicate sampling clock polarity, 1: Positive 0: Negative */ + for (i = 0;i < 3; i++) { + write32(&mtk_spmi_mst->mst_sampl, (cali_data[i].dly << 0x1) | cali_data[i].pol); + if (spmi_read_check(pmif_arb, dev->slvid) == 0) + break; + } + + if (i == 3) { + printk(BIOS_ERR, "FATAL ERROR"); + /* ASSERT(0); */ + } + + return 0; +} + +static int spmi_mst_init(struct pmif *pmif_arb) +{ + int i; + unsigned char spmi_device_cnt; + + if (pmif_arb == NULL) { + printk(BIOS_ERR, "arguments err\n"); + return -E_INVAL; + } + + /* config IOCFG */ + spmi_config_io(); + spmi_config_master(); + + spmi_device_cnt = sizeof(spmi_dev)/sizeof(spmi_dev[0]); + for (i = 0; i < spmi_device_cnt; i++) { + //spmi_dev[i].pmif_arb = pmif_spmi_arb_ctrl[pmif_arb->mstid]; + spmi_cali_rd_clock_polarity(pmif_arb, &spmi_dev[i]); + } + + return 0; +} + +static void pmif_spmi_force_normal_mode(int mstid) +{ + struct pmif *arb = get_pmif_controller(PMIF_SPMI, mstid); + unsigned int value; + + /* listen srclken_0 only for entering normal or sleep mode */ + value = read32(&arb->mtk_pmif->spi_mode_ctrl) & (~(0x1 << 7)); + write32(&arb->mtk_pmif->spi_mode_ctrl, value); + + /* enable srclken_en or srvol_en(VREQ) control */ + value |= ((0x1 << 12) | (0x1 << 13)); + /* disable srclken_rc control */ + value &= (~(0x1 << 11)); + write32(&arb->mtk_pmif->spi_mode_ctrl, value); + + /* enable spm/scp sleep request */ + value = read32(&arb->mtk_pmif->sleep_protection_ctrl); + value &= (~0x3); + value &= (~(0x3 << 9)); + write32(&arb->mtk_pmif->sleep_protection_ctrl, value); +} + +static void pmif_spmi_enable_swinf(int mstid, unsigned int chan_no, + unsigned int swinf_no) +{ + struct pmif *arb = get_pmif_controller(PMIF_SPMI, mstid); + + /* Enable swinf chan_no = 4, swinf_no = 2*/ + write32(&arb->mtk_pmif->inf_en, 0x1 << (chan_no + swinf_no)); + + /* Enable arbitration */ + write32(&arb->mtk_pmif->arb_en, 0x1 << (chan_no + swinf_no)); +} + +static void pmif_spmi_enable_cmdIssue(int mstid, bool en) +{ + struct pmif *arb = get_pmif_controller(PMIF_SPMI, mstid); + + /* Enable cmdIssue */ + write32(&arb->mtk_pmif->cmdissue_en, en); +} + +static void pmif_spmi_enable(int mstid) +{ + struct pmif *arb = get_pmif_controller(PMIF_SPMI, mstid); + unsigned int bytecnt_per = 0, hw_bytecnt = 0; + unsigned int cmd_per = 0; + + /* clear all cmd permission for per channel */ + write32(&arb->mtk_pmif->inf_cmd_per_0, 0); + write32(&arb->mtk_pmif->inf_cmd_per_1, 0); + write32(&arb->mtk_pmif->inf_cmd_per_2, 0); + write32(&arb->mtk_pmif->inf_cmd_per_3, 0); + + /* enable if we need cmd 0~3 permission for per channel */ + cmd_per = PMIF_CMD_PER_3 << 28 | PMIF_CMD_PER_3 << 24 | + PMIF_CMD_PER_3 << 20 | PMIF_CMD_PER_3 << 16 | + PMIF_CMD_PER_3 << 8 | PMIF_CMD_PER_3 << 4 | + PMIF_CMD_PER_1_3 << 0; + write32(&arb->mtk_pmif->inf_cmd_per_0, cmd_per); + cmd_per = PMIF_CMD_PER_3 << 4; + write32(&arb->mtk_pmif->inf_cmd_per_1, cmd_per); + + /* set bytecnt max limitation*/ + write32(&arb->mtk_pmif->inf_max_bytecnt_per_0, 0); + write32(&arb->mtk_pmif->inf_max_bytecnt_per_1, 0); + write32(&arb->mtk_pmif->inf_max_bytecnt_per_2, 0); + write32(&arb->mtk_pmif->inf_max_bytecnt_per_3, 0); + + /* hw bytecnt indicate when we set 0, it can send 1 byte; + * set 1, it can send 2 byte. + */ + hw_bytecnt = PMIF_BYTECNT_MAX -1; + if (hw_bytecnt > 0) { + bytecnt_per = hw_bytecnt << 28 | hw_bytecnt << 24 | + hw_bytecnt << 20 | hw_bytecnt << 16 | + hw_bytecnt << 12 | hw_bytecnt << 8 | + hw_bytecnt << 4 | hw_bytecnt << 0; + } + write32(&arb->mtk_pmif->inf_max_bytecnt_per_0, bytecnt_per); + write32(&arb->mtk_pmif->inf_max_bytecnt_per_1, bytecnt_per); + write32(&arb->mtk_pmif->inf_max_bytecnt_per_2, bytecnt_per); + write32(&arb->mtk_pmif->inf_max_bytecnt_per_3, bytecnt_per); + + /* Add latency limitation */ + write32(&arb->mtk_pmif->lat_cnter_en, 0x2F7); + write32(&arb->mtk_pmif->lat_limit_0, 0); + write32(&arb->mtk_pmif->lat_limit_1, 0x4); + write32(&arb->mtk_pmif->lat_limit_2, 0x8); + write32(&arb->mtk_pmif->lat_limit_4, 0x8); + write32(&arb->mtk_pmif->lat_limit_6, 0x3FF); + write32(&arb->mtk_pmif->lat_limit_9, 0x4); + write32(&arb->mtk_pmif->lat_limit_loading, 0x2F7); + + write32(&arb->mtk_pmif->inf_en, 0x2F7); + write32(&arb->mtk_pmif->arb_en, 0x2F7); + write32(&arb->mtk_pmif->timer_ctrl, 0x3); + write32(&arb->mtk_pmif->init_done, 1); +} + +int pmif_spmi_init(struct pmif *arb) +{ + int ret = 0; + + if (arb->is_pmif_init_done(arb) != 0) { + pmif_spmi_force_normal_mode(arb->mstid); + pmif_spmi_enable_swinf(arb->mstid, PMIF_SWINF_0_CHAN_NO, arb->swinf_no); + pmif_spmi_enable_cmdIssue(arb->mstid, true); + pmif_spmi_enable(arb->mstid); + ret = arb->is_pmif_init_done(arb); + if(ret) + return -E_NODEV; + } + + ret = spmi_mst_init(arb); + if(ret) + return -E_NODEV; + + return 0; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/45398 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32fc28f72d9522133baa06f9d67c383f814d862c Gerrit-Change-Number: 45398 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: hsin-hsiung wang <hsin-hsiung.wang(a)mediatek.com> Gerrit-MessageType: newchange

6 hours, 9 minutes

Change in coreboot[master]: mb/tigerlake: Disable Precision Time Measurement for PCIe RP 9

by Shreesh Chhabbi (Code Review)

Hello Shreesh Chhabbi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44431 to review the following change. Change subject: mb/tigerlake: Disable Precision Time Measurement for PCIe RP 9 ...................................................................... mb/tigerlake: Disable Precision Time Measurement for PCIe RP 9 Change-Id: I72126c2013c4ddac2884b7d40ef043e80d432331 Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/fsp_params.c 4 files changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/44431/1 diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index b4a121a..9ccc5e0 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -63,6 +63,9 @@ register "PcieClkSrcUsage[2]" = "0x3" register "PcieClkSrcUsage[3]" = "0x8" + # PCIe RP PTM + register "PciePtm[8]" = "0x0"; + register "SataSalpSupport" = "1" register "SataPortsEnable[0]" = "1" register "SataPortsEnable[1]" = "1" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index b08cd3c..496f837 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -52,6 +52,9 @@ register "PcieRpLtrEnable[8]" = "1" register "PcieRpLtrEnable[10]" = "1" + # PCIe PTM for Root Port 9 + register "PciePtm[8]" = "0" + # Hybrid storage mode register "HybridStorageMode" = "1" diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 812dbac..3cadcf0 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -174,6 +174,9 @@ /* Probe CLKREQ# signal before enabling CLKREQ# based power management.*/ uint8_t PcieRpClkReqDetect[CONFIG_MAX_ROOT_PORTS]; + /* PCIe Precision Time Measurement for Root Ports */ + uint8_t PciePtm[CONFIG_MAX_ROOT_PORTS]; + /* PCIe RP L1 substate */ enum L1_substates_control { L1_SS_FSP_DEFAULT, diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 885a6f9..8a72573 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -172,6 +172,7 @@ params->PcieRpAdvancedErrorReporting[i] = config->PcieRpAdvancedErrorReporting[i]; params->PcieRpHotPlug[i] = config->PcieRpHotPlug[i]; + params->PciePtm[i] = config->PciePtm[i]; } /* Enable ClkReqDetect for enabled port */ -- To view, visit https://review.coreboot.org/c/coreboot/+/44431 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72126c2013c4ddac2884b7d40ef043e80d432331 Gerrit-Change-Number: 44431 Gerrit-PatchSet: 1 Gerrit-Owner: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Reviewer: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-MessageType: newchange

7 hours, 43 minutes

Change in coreboot[master]: soc/intel: Factor out `select CPU_INTEL_COMMON`

by Angel Pons (Code Review)

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45042 ) Change subject: soc/intel: Factor out `select CPU_INTEL_COMMON` ...................................................................... soc/intel: Factor out `select CPU_INTEL_COMMON` All affected platforms select `SOC_INTEL_COMMON_BLOCK_CPU` already. Change-Id: Iedcd3073b8e0287908eab1d886d2d5efff09088b Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/broadwell/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/common/block/cpu/Kconfig M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/jasperlake/Kconfig M src/soc/intel/skylake/Kconfig M src/soc/intel/tigerlake/Kconfig M src/soc/intel/xeon_sp/Kconfig 10 files changed, 1 insertion(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/45042/1 diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 96808cf..964e7d4 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -28,7 +28,6 @@ select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES # CPU specific options - select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select IOAPIC select PCR_COMMON_IOSF_1_0 diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 156d58a..66030b1 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -15,7 +15,6 @@ select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select MRC_SETTINGS_PROTECT - select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select SUPPORT_CPU_UCODE_IN_CBFS select HAVE_SMI_HANDLER diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index d36e214..52896b9 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -65,7 +65,6 @@ select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS - select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select FSP_COMPRESS_FSP_S_LZMA select FSP_M_XIP diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig index 3c29b24..094cf05 100644 --- a/src/soc/intel/common/block/cpu/Kconfig +++ b/src/soc/intel/common/block/cpu/Kconfig @@ -1,6 +1,7 @@ config SOC_INTEL_COMMON_BLOCK_CPU bool default n + select CPU_INTEL_COMMON help This option selects Intel Common CPU Model support code which provides various CPU related APIs which are common diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index e6d3237..3fce223 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -16,7 +16,6 @@ select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select DEBUG_GPIO - select CPU_INTEL_COMMON select SOC_INTEL_COMMON select SOC_INTEL_COMMON_RESET select PLATFORM_USES_FSP2_0 diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 2aeb6d6..8a98304 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -15,7 +15,6 @@ select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS - select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select FSP_M_XIP select GENERIC_GPIO_LIB diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index fd5648f..d172322 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -15,7 +15,6 @@ select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS - select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select FSP_COMPRESS_FSP_S_LZ4 select FSP_M_XIP diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 9f9cb18..adb43ad 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -26,7 +26,6 @@ select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS - select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_INTEL_COMMON_HYPERTHREADING select FSP_M_XIP diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 8718f97..de92090 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -15,7 +15,6 @@ select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS - select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select FSP_COMPRESS_FSP_S_LZ4 select FSP_M_XIP diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 31d12fc..a4274df 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -31,7 +31,6 @@ select ARCH_VERSTAGE_X86_32 select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES - select CPU_INTEL_COMMON select SOC_INTEL_COMMON select SOC_INTEL_COMMON_RESET select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS -- To view, visit https://review.coreboot.org/c/coreboot/+/45042 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iedcd3073b8e0287908eab1d886d2d5efff09088b Gerrit-Change-Number: 45042 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-MessageType: newchange

9 hours, 34 minutes

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coreboot-gerrit September 2020