September 2020 - coreboot-gerrit

Change in coreboot[master]: [WIP, HACK] broadwell: make uart support build again

by Angel Pons (Code Review)

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37553 ) Change subject: [WIP, HACK] broadwell: make uart support build again ...................................................................... [WIP, HACK] broadwell: make uart support build again @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ @ @ @ DO NOT MERGE AS-IS! @ @ @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ I am fully aware this is an atrociously hideous kludge. Moreover, this change won't be properly build-tested by Mr. Jenkins, and it has not been tested on real hardware either. It only exists for backup purposes. Change-Id: I527024098738700d5fbaf3e27cf4db331a0322bd Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/Makefile.inc M src/soc/intel/broadwell/romstage/uart.c M src/soc/intel/broadwell/serialio.c 3 files changed, 17 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/37553/1 diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index 03aa3fb..61b62c8 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -9,6 +9,7 @@ subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/intel/common +bootblock-y += romstage/uart.c bootblock-y += bootblock/cpu.c bootblock-y += bootblock/pch.c bootblock-y += bootblock/systemagent.c @@ -16,6 +17,9 @@ bootblock-y += ../../../cpu/intel/car/non-evict/cache_as_ram.S bootblock-y += ../../../cpu/x86/early_reset.S +postcar-y += romstage/uart.c +ramstage-y += romstage/uart.c + ramstage-y += acpi.c ramstage-y += adsp.c ramstage-y += chip.c diff --git a/src/soc/intel/broadwell/romstage/uart.c b/src/soc/intel/broadwell/romstage/uart.c index a1a29b6..43c62a9 100644 --- a/src/soc/intel/broadwell/romstage/uart.c +++ b/src/soc/intel/broadwell/romstage/uart.c @@ -14,13 +14,15 @@ */ #include <device/pci_def.h> +#include <console/uart.h> #include <reg_script.h> #include <stdint.h> -#include <uart8250.h> #include <soc/iobp.h> +#include <soc/pci_devs.h> +#include <soc/romstage.h> #include <soc/serialio.h> -const struct reg_script uart_init[] = { +const struct reg_script uart_init_script[] = { /* Set MMIO BAR */ REG_PCI_WRITE32(PCI_BASE_ADDRESS_0, CONFIG_TTYS0_BASE), /* Enable Memory access and Bus Master */ @@ -41,6 +43,11 @@ REG_SCRIPT_END }; +uintptr_t uart_platform_base(int idx) +{ + return CONFIG_TTYS0_BASE; +} + void pch_uart_init(void) { /* Program IOBP CB000154h[12,9:8,4:0] = 1001100011111b */ @@ -72,11 +79,11 @@ pch_iobp_update(0xcb000180, ~0x0000003f, 0x0000003f); /* Initialize chipset uart interface */ - reg_script_run_on_dev(dev, uart_init); + reg_script_run_on_dev(dev, uart_init_script); /* * Perform standard UART initialization * Divisor 1 is 115200 BAUD */ - uart8250_mem_init(CONFIG_TTYS0_BASE, 1); + uart_init(0); } diff --git a/src/soc/intel/broadwell/serialio.c b/src/soc/intel/broadwell/serialio.c index 161c875..50daa3f 100644 --- a/src/soc/intel/broadwell/serialio.c +++ b/src/soc/intel/broadwell/serialio.c @@ -282,7 +282,8 @@ if (serialio_uart_is_debug(dev)) { struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) - uartmem_setbaseaddr(res->base); + printk(BIOS_ERR, "UART base address changed\n"); + //uartmem_setbaseaddr(res->base); } #endif } -- To view, visit https://review.coreboot.org/c/coreboot/+/37553 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I527024098738700d5fbaf3e27cf4db331a0322bd Gerrit-Change-Number: 37553 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP]security/intel: Add option to eanble SMM flash access only

by Patrick Rudolph (Code Review)

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40830 ) Change subject: [WIP]security/intel: Add option to eanble SMM flash access only ...................................................................... [WIP]security/intel: Add option to eanble SMM flash access only On platforms where the boot media can be updated externally, for e.g. using a BMC, add the possibility to enable writes in SMM only. This allows to protect the BIOS region even without the use of vboot, but keeps the SMMSTORE working for the use in payloads. UNTESTED. Change-Id: I157db885b5f1d0f74009ede6fb2342b20d9429fa Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/security/lockdown/Kconfig M src/soc/intel/common/pch/lockdown/lockdown.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/common/spi.c M src/southbridge/intel/common/spi.h M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/smi.c 8 files changed, 52 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/40830/1 diff --git a/src/security/lockdown/Kconfig b/src/security/lockdown/Kconfig index d24c5e5..dbe6840 100644 --- a/src/security/lockdown/Kconfig +++ b/src/security/lockdown/Kconfig @@ -99,3 +99,13 @@ possible. This option prevents using write protecting facilities in ramstage, like the MRC cache for example. Use this option if you don't trust code running after verstage. + +config BOOTMEDIA_SMM_BWP + bool "Boot media only writable in SMM" + depends on ARCH_X86 + depends on HAVE_SMI_HANDLER + select SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE if SOC_INTEL_COMMON_BLOCK + help + Enable flash writes in SMM only. Select this if you want to secure + the SMM_STORE and don't need to update coreboot using the + internal controller. diff --git a/src/soc/intel/common/pch/lockdown/lockdown.c b/src/soc/intel/common/pch/lockdown/lockdown.c index a00e5c0..768c4cd 100644 --- a/src/soc/intel/common/pch/lockdown/lockdown.c +++ b/src/soc/intel/common/pch/lockdown/lockdown.c @@ -62,6 +62,12 @@ /* BIOS Interface Lock */ fast_spi_set_bios_interface_lock_down(); + /* Only allow writes in SMM */ + if (CONFIG(BOOTMEDIA_SMM_BWP)) { + fast_spi_set_eiss(); + fast_spi_enable_wp(); + } + /* BIOS Lock */ fast_spi_set_lock_enable(); } diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 278e90a..78bfb39 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -416,16 +416,6 @@ } } -static void pch_disable_smm_only_flashing(struct device *dev) -{ - u8 reg8; - - printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... "); - reg8 = pci_read_config8(dev, BIOS_CNTL); - reg8 &= ~(1 << 5); - pci_write_config8(dev, BIOS_CNTL, reg8); -} - static void pch_fixups(struct device *dev) { u8 gen_pmcon_2; @@ -579,8 +569,6 @@ /* Interrupt 9 should be level triggered (SCI) */ i8259_configure_irq_trigger(9, 1); - pch_disable_smm_only_flashing(dev); - pch_set_acpi_mode(); pch_fixups(dev); diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 5e967af..253d33f 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -35,6 +35,10 @@ #define HSFC_FCYCLE (0x3 << HSFC_FCYCLE_OFF) #define HSFC_FDBC_OFF 8 /* 8-13: Flash Data Byte Count */ #define HSFC_FDBC (0x3f << HSFC_FDBC_OFF) +#define BIOS_CNTL 0xdc +#define LPC_BC_WE (1 << 0) /* WE */ +#define LPC_BC_LE (1 << 1) /* LE */ +#define LPC_BC_EISS (1 << 5) /* EISS */ static int spi_is_multichip(void); @@ -293,7 +297,6 @@ void spi_init(void) { - uint8_t bios_cntl; struct ich9_spi_regs *ich9_spi; struct ich7_spi_regs *ich7_spi; uint16_t hsfs; @@ -345,10 +348,7 @@ if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX) || CONFIG(SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9)) { /* Disable the BIOS write protect so write commands are allowed. */ - bios_cntl = pci_read_config8(dev, 0xdc); - /* Deassert SMM BIOS Write Protect Disable. */ - bios_cntl &= ~(1 << 5); - pci_write_config8(dev, 0xdc, bios_cntl | 0x1); + spi_smm_only_flashing(0); } } @@ -1108,12 +1108,35 @@ writeb_(spi_config->ops[i].op, &cntlr.opmenu[i]); } writew_(optype, cntlr.optype); + + spi_smm_only_flashing(CONFIG(BOOTMEDIA_SMM_BWP)); } __weak void intel_southbridge_override_spi(struct intel_swseq_spi_config *spi_config) { } +void spi_smm_only_flashing(bool enable) +{ + pci_devfn_t dev = PCI_DEV(0, 31, 0); + u8 reg8 = pci_read_config8(dev, BIOS_CNTL); + + if (reg8 & LPC_BC_LE) + return; + + if (enable) { + reg8 |= LPC_BC_EISS; + reg8 &= ~LPC_BC_WE; + } else { + reg8 &= ~LPC_BC_EISS; + reg8 |= LPC_BC_WE; + } + pci_write_config8(dev, BIOS_CNTL, reg8); + + printk(BIOS_SPEW, "BIOS updates outside of SMM %s\n", + enable ? "enabled" : "disabled"); +} + static const struct spi_ctrlr spi_ctrlr = { .xfer_vector = xfer_vectors, .max_xfer_size = member_size(struct ich9_spi_regs, fdata), diff --git a/src/southbridge/intel/common/spi.h b/src/southbridge/intel/common/spi.h index 3b8410c..ad1cb27 100644 --- a/src/southbridge/intel/common/spi.h +++ b/src/southbridge/intel/common/spi.h @@ -32,6 +32,7 @@ struct intel_spi_op ops[8]; }; +void spi_smm_only_flashing(bool enable); void spi_finalize_ops(void); void intel_southbridge_override_spi(struct intel_swseq_spi_config *spi_config); diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 395919e..67c03fa 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -420,16 +420,6 @@ } } -static void pch_disable_smm_only_flashing(struct device *dev) -{ - u8 reg8; - - printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... "); - reg8 = pci_read_config8(dev, BIOS_CNTL); - reg8 &= ~(1 << 5); - pci_write_config8(dev, BIOS_CNTL, reg8); -} - static void pch_fixups(struct device *dev) { /* @@ -482,8 +472,6 @@ /* Interrupt 9 should be level triggered (SCI) */ i8259_configure_irq_trigger(9, 1); - pch_disable_smm_only_flashing(dev); - pch_set_acpi_mode(); pch_fixups(dev); diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index d9ef5cc..dafb901 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -481,16 +481,6 @@ } } -static void pch_disable_smm_only_flashing(struct device *dev) -{ - u8 reg8; - - printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... "); - reg8 = pci_read_config8(dev, BIOS_CNTL); - reg8 &= ~(1 << 5); - pci_write_config8(dev, BIOS_CNTL, reg8); -} - static void pch_fixups(struct device *dev) { u8 gen_pmcon_2; @@ -549,8 +539,6 @@ /* Interrupt 9 should be level triggered (SCI) */ i8259_configure_irq_trigger(9, 1); - pch_disable_smm_only_flashing(dev); - pch_set_acpi_mode(); pch_fixups(dev); diff --git a/src/southbridge/intel/lynxpoint/smi.c b/src/southbridge/intel/lynxpoint/smi.c index 05b5bb5..82e96f3 100644 --- a/src/southbridge/intel/lynxpoint/smi.c +++ b/src/southbridge/intel/lynxpoint/smi.c @@ -40,6 +40,8 @@ void smm_southbridge_enable_smi(void) { + u32 mask; + printk(BIOS_DEBUG, "Enabling SMIs.\n"); /* Configure events */ enable_pm1(PWRBTN_EN | GBL_EN); @@ -49,11 +51,14 @@ * - on APMC writes (io 0xb2) * - on writes to SLP_EN (sleep states) * - on writes to GBL_RLS (bios commands) + * - on TCO events * No SMIs: * - on microcontroller writes (io 0x62/0x66) - * - on TCO events */ - enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS); + mask = APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS; + if (CONFIG(BOOTMEDIA_SMM_BWP)) + mask |= TCO_EN; + enable_smi(mask); } static void __unused southbridge_trigger_smi(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/40830 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I157db885b5f1d0f74009ede6fb2342b20d9429fa Gerrit-Change-Number: 40830 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/skylake: lock TCO base address on pch finalize

by Michael Niewöhner (Code Review)

Michael Niewöhner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35525 ) Change subject: soc/intel/skylake: lock TCO base address on pch finalize ...................................................................... soc/intel/skylake: lock TCO base address on pch finalize This is a follow-up on I5bd95b3580adc0f4cffa667f8979b7cf08925720 which already locks TCO itself but does not lock the base address. Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Change-Id: Idab9419487e6e4cbdecd2efaa4772ff4960c9055 --- M src/soc/intel/common/block/smbus/tco.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/35525/1 diff --git a/src/soc/intel/common/block/smbus/tco.c b/src/soc/intel/common/block/smbus/tco.c index 1a215eb..a3ebe24 100644 --- a/src/soc/intel/common/block/smbus/tco.c +++ b/src/soc/intel/common/block/smbus/tco.c @@ -34,6 +34,7 @@ #define TCOBASE 0x50 #define TCOCTL 0x54 #define TCO_BASE_EN (1 << 8) +#define TCO_BASE_LOCK (1 << 0) /* Get base address of TCO I/O registers. */ static uint16_t tco_get_bar(void) @@ -61,8 +62,13 @@ void tco_lockdown(void) { + uint32_t reg32; uint16_t tcocnt; + /* TCO base address lockdown */ + reg32 = pci_read_config32(dev, TCOCTL); + pci_write_config32(dev, TCOCTL, reg32 | TCO_BASE_LOCK); + /* TCO Lock down */ tcocnt = tco_read_reg(TCO1_CNT); tcocnt |= TCO_LOCK; -- To view, visit https://review.coreboot.org/c/coreboot/+/35525 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idab9419487e6e4cbdecd2efaa4772ff4960c9055 Gerrit-Change-Number: 35525 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP]acpi: Get rid of boilerplate FADT

by Patrick Rudolph (Code Review)

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40036 ) Change subject: [WIP]acpi: Get rid of boilerplate FADT ...................................................................... [WIP]acpi: Get rid of boilerplate FADT Still not done.... Needs test on windows and Linux on all affected platforms, that is every x86 platform. Change-Id: If58fcf9a1c39c159dfa08339cb931e552d499747 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/arch/x86/acpi.c M src/arch/x86/include/arch/acpi.h M src/soc/intel/apollolake/acpi.c M src/soc/intel/cannonlake/acpi.c M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/skylake/acpi.c M src/soc/intel/xeon_sp/cpx/acpi.c M src/soc/intel/xeon_sp/skx/acpi.c M src/southbridge/amd/cimx/sb800/fadt.c M src/southbridge/amd/pi/hudson/fadt.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/i82371eb/fadt.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/lynxpoint/lpc.c 17 files changed, 407 insertions(+), 1,080 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/40036/1 diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index e4932be..d540721 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -1249,6 +1249,17 @@ fadt->sleep_control_reg.bit_width = 8; fadt->sleep_status_reg.bit_width = 8; + if (CONFIG(ARCH_X86)) { + /* Set x86 defaults. A SoC can still overwrite those. */ + fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->reset_reg.addrl = SYS_RESET; + fadt->reset_reg.addrh = 0x0; + + fadt->reset_value = RST_CPU | SYS_RST; + } acpi_fill_fadt(fadt); header->checksum = @@ -1256,6 +1267,130 @@ } #endif +static void acpi_update_access_size(acpi_addr_t *reg) +{ + switch (DIV_ROUND_UP(reg->bit_width, 8)) { + case 0: + reg->access_size = ACPI_ACCESS_SIZE_UNDEFINED; + default: + case 1: + reg->access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + break; + case 2: + reg->access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; + break; + case 4: + reg->access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + break; + case 8: + reg->access_size = ACPI_ACCESS_SIZE_QDWORD_ACCESS; + break; + } +} + +void acpi_fill_fadt_x86_pm(acpi_fadt_t *fadt, + u32 pm1a_evt_blk, + u32 pm1b_evt_blk, + u32 pm1a_cnt_blk, + u32 pm1b_cnt_blk, + u32 pm2_cnt_blk, + u32 pm_tmr_blk, + u32 gpe0_blk, + u32 gpe1_blk, + u8 pm1_evt_len, + u8 pm1_cnt_len, + u8 pm2_cnt_len, + u8 pm_tmr_len, + u8 gpe0_blk_len, + u8 gpe1_blk_len, + u8 gpe1_base) +{ + fadt->pm1a_evt_blk = pm1a_evt_blk; + fadt->pm1b_evt_blk = pm1b_evt_blk; + fadt->pm1a_cnt_blk = pm1a_cnt_blk; + fadt->pm1b_cnt_blk = pm1b_cnt_blk; + fadt->pm2_cnt_blk = pm2_cnt_blk; + fadt->pm_tmr_blk = pm_tmr_blk; + fadt->gpe0_blk = gpe0_blk; + fadt->gpe1_blk = gpe1_blk; + fadt->gpe1_base = gpe1_base; + + fadt->pm1_evt_len = pm1_evt_len; + fadt->pm1_cnt_len = pm1_cnt_len; + fadt->pm2_cnt_len = pm2_cnt_len; + fadt->pm_tmr_len = pm_tmr_len; + fadt->gpe0_blk_len = gpe0_blk_len; + fadt->gpe1_blk_len = gpe1_blk_len; + + fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; + fadt->x_pm1a_evt_blk.addrl = pm1a_evt_blk; + fadt->x_pm1a_evt_blk.addrh = 0x0; + acpi_update_access_size(&fadt->x_pm1a_evt_blk); + + fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1b_evt_blk.bit_width = pm1_evt_len * 8; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; + fadt->x_pm1b_evt_blk.addrl = pm1b_evt_blk; + fadt->x_pm1b_evt_blk.addrh = 0x0; + acpi_update_access_size(&fadt->x_pm1b_evt_blk); + + fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1a_cnt_blk.bit_width = pm1_cnt_len * 8; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; + fadt->x_pm1a_cnt_blk.addrl = pm1a_cnt_blk; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + acpi_update_access_size(&fadt->x_pm1a_cnt_blk); + + fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1b_cnt_blk.bit_width = pm1_cnt_len * 8; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; + fadt->x_pm1b_cnt_blk.addrl = pm1b_cnt_blk; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + acpi_update_access_size(&fadt->x_pm1b_cnt_blk); + + fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm2_cnt_blk.bit_width = pm2_cnt_len * 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->x_pm2_cnt_blk.addrl = pm2_cnt_blk; + fadt->x_pm2_cnt_blk.addrh = 0x0; + acpi_update_access_size(&fadt->x_pm2_cnt_blk); + + fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm_tmr_blk.bit_width = pm_tmr_len * 8; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_pm_tmr_blk.addrl = pm_tmr_blk; + fadt->x_pm_tmr_blk.addrh = 0x0; + acpi_update_access_size(&fadt->x_pm_tmr_blk); + + /* + * Windows 10 requires x_gpe0_blk to be set starting with FADT revision 5. + * The bit_width field intentionally overflows here. + * The OSPM can instead use the values in `fadt->gpe0_blk{,_len}`, which + * seems to work fine on Linux 5.0 and Windows 10. + */ + fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_gpe0_blk.bit_width = gpe0_blk_len * 8; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->x_gpe0_blk.addrl = gpe0_blk; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_gpe1_blk.bit_width = gpe1_blk_len * 8; + fadt->x_gpe1_blk.bit_offset = gpe1_base * 8; + fadt->x_gpe1_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->x_gpe1_blk.addrl = gpe1_blk; + fadt->x_gpe1_blk.addrh = 0x0; +} + unsigned long __weak fw_cfg_acpi_tables(unsigned long start) { return 0; diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 4351678..107ad86 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -844,6 +844,25 @@ #if CONFIG(COMMON_FADT) void acpi_fill_fadt(acpi_fadt_t *fadt); #endif +/** + * Fill in ACPI FADT fields used by a generic x86 platform. + * That is all PM* and GPE* are located in IO space. + */ +void acpi_fill_fadt_x86_pm(acpi_fadt_t *fadt, + u32 pm1a_evt_blk, + u32 pm1b_evt_blk, + u32 pm1a_cnt_blk, + u32 pm1b_cnt_blk, + u32 pm2_cnt_blk, + u32 pm_tmr_blk, + u32 gpe0_blk, + u32 gpe1_blk, + u8 pm1_evt_len, + u8 pm1_cnt_len, + u8 pm2_cnt_len, + u8 pm_tmr_len, + u8 gpe0_blk_len, + u8 gpe1_blk_len); void update_ssdt(void *ssdt); void update_ssdtx(void *ssdtx, int i); diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index fbfe33f..ef1c01d 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -152,10 +152,9 @@ void soc_fill_fadt(acpi_fadt_t *fadt) { const struct soc_intel_apollolake_config *cfg; + const uint16_t pmbase = ACPI_BASE_ADDRESS; cfg = config_of_soc(); - fadt->pm_tmr_blk = ACPI_BASE_ADDRESS + PM1_TMR; - fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; @@ -164,13 +163,25 @@ fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; - fadt->x_pm_tmr_blk.addrl = ACPI_BASE_ADDRESS + PM1_TMR; - fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - if (cfg->lpss_s0ix_enable) fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0; + + acpi_fill_fadt_x86_pm(fadt, + pmbase + PM1_STS, + 0, + pmbase + PM1_CNT, + 0, + 0, + pmbase + PM1_TMR, + pmbase + GPE0_STS(0), + 0, + 4, + 2, + 0, + 4, + 2 * GPE0_REG_MAX, + 0, + 0); } static unsigned long soc_fill_dmar(unsigned long current) diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index 84659c9..490cabc 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -176,17 +176,25 @@ const struct soc_intel_cannonlake_config *config; config = config_of_soc(); - fadt->pm_tmr_blk = pmbase + PM1_TMR; - fadt->pm_tmr_len = 4; - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; - fadt->x_pm_tmr_blk.addrh = 0x0; - if (config->s0ix_enable) fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0; + + acpi_fill_fadt_x86_pm(fadt, + pmbase + PM1_STS, + 0, + pmbase + PM1_CNT, + 0, + 0, + pmbase + PM1_TMR, + pmbase + GPE0_STS(0), + 0, + 4, + 2, + 0, + 4, + 2 * GPE0_REG_MAX, + 0, + 0); } uint32_t soc_read_sci_irq_select(void) { diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index fe127a2..c729cc8 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -178,6 +178,17 @@ fadt->x_gpe1_blk.space_id = 1; + + fadt->pm1a_evt_blk = pmbase + PM1_STS; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = pmbase + PM1_CNT; + fadt->pm1b_cnt_blk = 0x0; + + fadt->gpe0_blk = pmbase + GPE0_STS(0); + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + soc_fill_fadt(fadt); } diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index d3e2853..fd8b934 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -132,7 +132,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt) { - u16 pmbase = get_pmbase(); + const u16 pmbase = get_pmbase(); /* System Management */ if (!CONFIG(HAVE_SMI_HANDLER)) { @@ -141,17 +141,6 @@ fadt->acpi_disable = 0x00; } - /* Power Control */ - fadt->pm2_cnt_blk = pmbase + PM2_CNT; - fadt->pm_tmr_blk = pmbase + PM1_TMR; - fadt->gpe1_blk = 0; - - /* Control Registers - Length */ - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 8; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; fadt->cst_cnt = 0; fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; @@ -171,75 +160,22 @@ ACPI_FADT_RESET_REGISTER | ACPI_FADT_SLEEP_TYPE | ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; - /* Reset Register */ - fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->reset_reg.addrl = 0xCF9; - fadt->reset_reg.addrh = 0x00; - fadt->reset_value = 6; - - /* PM1 Status & PM1 Enable */ - fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk; - fadt->x_pm1a_evt_blk.addrh = 0x00; - - fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.access_size = 0; - fadt->x_pm1b_evt_blk.addrl = fadt->pm1b_evt_blk; - fadt->x_pm1b_evt_blk.addrh = 0x00; - - /* PM1 Control Registers */ - fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk; - fadt->x_pm1a_cnt_blk.addrh = 0x00; - - fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.access_size = 0; - fadt->x_pm1b_cnt_blk.addrl = fadt->pm1b_cnt_blk; - fadt->x_pm1b_cnt_blk.addrh = 0x00; - - /* PM2 Control Registers */ - fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk; - fadt->x_pm2_cnt_blk.addrh = 0x00; - - /* PM1 Timer Register */ - fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk; - fadt->x_pm_tmr_blk.addrh = 0x00; - - /* General-Purpose Event Registers */ - fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + EventEnable */ - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; - fadt->x_gpe0_blk.addrh = 0x00; - - fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.access_size = 0; - fadt->x_gpe1_blk.addrl = fadt->gpe1_blk; - fadt->x_gpe1_blk.addrh = 0x00; + acpi_fill_fadt_x86_pm(fadt, + pmbase + PM1_STS, + 0, + pmbase + PM1_CNT, + 0, + pmbase + PM2_CNT, + pmbase + PM1_TMR, + pmbase + GPE0_STS(0), + 0, + 4, + 2, + 1, + 4, + 2 * GPE0_REG_MAX * sizeof(uint32_t), + 0, + 0); motherboard_fill_fadt(fadt); } diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 550dd56..9e24017 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -234,8 +234,6 @@ const uint16_t pmbase = ACPI_BASE_ADDRESS; config_t *config = config_of_soc(); - fadt->header.revision = get_acpi_table_revision(FADT); - fadt->sci_int = acpi_sci_irq(); fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; @@ -243,23 +241,6 @@ fadt->s4bios_req = 0x0; fadt->pstate_cnt = 0; - fadt->pm1a_evt_blk = pmbase + PM1_STS; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + PM1_CNT; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + PM2_CNT; - fadt->pm_tmr_blk = pmbase + PM1_TMR; - fadt->gpe0_blk = pmbase + GPE0_STS(0); - fadt->gpe1_blk = 0; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - /* There are 4 GPE0 STS/EN pairs each 32 bits wide. */ - fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; fadt->cst_cnt = 0; fadt->p_lvl2_lat = 1; fadt->p_lvl3_lat = 87; @@ -282,75 +263,22 @@ if (config->s0ix_enable) fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0; - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0; - fadt->reset_value = 6; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.access_size = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.access_size = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_pm2_cnt_blk.addrl = pmbase + PM2_CNT; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; - fadt->x_pm_tmr_blk.addrh = 0x0; - - /* - * Windows 10 requires x_gpe0_blk to be set starting with FADT revision 5. - * The bit_width field intentionally overflows here. - * The OSPM can instead use the values in `fadt->gpe0_blk{,_len}`, which - * seems to work fine on Linux 5.0 and Windows 10. - */ - fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; - fadt->x_gpe0_blk.addrh = 0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.access_size = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; + acpi_fill_fadt_x86_pm(fadt, + pmbase + PM1_STS, + 0, + pmbase + PM1_CNT, + 0, + pmbase + PM2_CNT, + pmbase + PM1_TMR, + pmbase + GPE0_STS(0), + 0, + 4, + 2, + 1, + 4, + 2 * GPE0_REG_MAX * sizeof(uint32_t), + 0, + 0); } static void write_c_state_entries(acpi_cstate_t *map, const int *set, size_t max_c_state) diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/cpx/acpi.c index 48ad374..1688ae3 100644 --- a/src/soc/intel/xeon_sp/cpx/acpi.c +++ b/src/soc/intel/xeon_sp/cpx/acpi.c @@ -108,19 +108,6 @@ fadt->header.revision = get_acpi_table_revision(FADT); fadt->sci_int = SCI_INT_NUM; - fadt->pm1a_evt_blk = pmbase + PM1_STS; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + PM1_CNT; - fadt->pm1b_cnt_blk = 0x0; - - fadt->gpe0_blk = pmbase + GPE0_STS(0); - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - - /* GPE0 STS/EN pairs each 32 bits wide. */ - fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); - fadt->flush_size = 0x400; /* twice of cache size */ fadt->flush_stride = 0x10; /* Cache line width */ fadt->duty_offset = 1; @@ -129,26 +116,6 @@ fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_RESET_REGISTER | ACPI_FADT_PLATFORM_CLOCK; - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.addrl = RST_CNT; - fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->reset_value = RST_CPU | SYS_RST; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; - fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; - - fadt->x_pm1b_evt_blk.space_id = 1; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; - fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; - - fadt->x_pm1b_cnt_blk.space_id = 1; - - fadt->x_gpe1_blk.space_id = 1; - if (CONFIG(HAVE_SMI_HANDLER)) { fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; @@ -165,18 +132,19 @@ fadt->cst_cnt = 0; } - /* General-Purpose Event Registers */ - fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + EventEnable */ - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; - fadt->x_gpe0_blk.addrh = 0; - - fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.access_size = 0; - fadt->x_gpe1_blk.addrl = 0; - fadt->x_gpe1_blk.addrh = 0; + acpi_fill_fadt_x86_pm(fadt, + pmbase + PM1_STS, + 0, + pmbase + PM1_CNT, + 0, + 0, + 0, + pmbase + GPE0_STS(0), + 0, + 4, + 2, + 0, + 0, + 2 * GPE0_REG_MAX * sizeof(uint32_t), + 0); } diff --git a/src/soc/intel/xeon_sp/skx/acpi.c b/src/soc/intel/xeon_sp/skx/acpi.c index e9edc99..aab93b4 100644 --- a/src/soc/intel/xeon_sp/skx/acpi.c +++ b/src/soc/intel/xeon_sp/skx/acpi.c @@ -247,18 +247,6 @@ fadt->acpi_disable = 0x00; } - /* Power Control */ - fadt->pm2_cnt_blk = pmbase + PM2_CNT; - fadt->pm_tmr_blk = pmbase + PM1_TMR; - fadt->gpe1_blk = 0; - - /* Control Registers - Length */ - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - /* There are 4 GPE0 STS/EN pairs each 32 bits wide. */ - fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; fadt->cst_cnt = 0; fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; @@ -278,75 +266,21 @@ ACPI_FADT_RESET_REGISTER | ACPI_FADT_SLEEP_TYPE | ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; - /* Reset Register */ - fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->reset_reg.addrl = 0xCF9; - fadt->reset_reg.addrh = 0x00; - fadt->reset_value = 6; - - /* PM1 Status & PM1 Enable */ - fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk; - fadt->x_pm1a_evt_blk.addrh = 0x00; - - fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.access_size = 0; - fadt->x_pm1b_evt_blk.addrl = fadt->pm1b_evt_blk; - fadt->x_pm1b_evt_blk.addrh = 0x00; - - /* PM1 Control Registers */ - fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk; - fadt->x_pm1a_cnt_blk.addrh = 0x00; - - fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.access_size = 0; - fadt->x_pm1b_cnt_blk.addrl = fadt->pm1b_cnt_blk; - fadt->x_pm1b_cnt_blk.addrh = 0x00; - - /* PM2 Control Registers */ - fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk; - fadt->x_pm2_cnt_blk.addrh = 0x00; - - /* PM1 Timer Register */ - fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk; - fadt->x_pm_tmr_blk.addrh = 0x00; - - /* General-Purpose Event Registers */ - fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + EventEnable */ - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; - fadt->x_gpe0_blk.addrh = 0x00; - - fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.access_size = 0; - fadt->x_gpe1_blk.addrl = fadt->gpe1_blk; - fadt->x_gpe1_blk.addrh = 0x00; + acpi_fill_fadt_x86_pm(fadt, + pmbase + PM1_STS, + 0, + pmbase + PM1_CNT, + 0, + pmbase + PM2_CNT, + pmbase + PM1_TMR, + pmbase + GPE0_STS(0), + 0, + 4, + 2, + 1, + 4, + 2 * GPE0_REG_MAX * sizeof(uint32_t), + 0); motherboard_fill_fadt(fadt); } @@ -355,8 +289,6 @@ { const uint16_t pmbase = ACPI_BASE_ADDRESS; - fadt->header.revision = get_acpi_table_revision(FADT); - fadt->sci_int = acpi_sci_irq(); /* TODO: enabled SMM mode switch when SMM handlers are set up. @@ -370,23 +302,6 @@ fadt->s4bios_req = 0x0; fadt->pstate_cnt = 0; - fadt->pm1a_evt_blk = pmbase + PM1_STS; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + PM1_CNT; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + PM2_CNT; - fadt->pm_tmr_blk = pmbase + PM1_TMR; - fadt->gpe0_blk = pmbase + GPE0_STS(0); - fadt->gpe1_blk = 0; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - /* There are 4 GPE0 STS/EN pairs each 32 bits wide. */ - fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; fadt->cst_cnt = 0; fadt->p_lvl2_lat = 1; fadt->p_lvl3_lat = 87; @@ -406,69 +321,21 @@ ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0; - fadt->reset_value = 6; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.access_size = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.access_size = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_pm2_cnt_blk.addrl = pmbase + PM2_CNT; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; - fadt->x_gpe0_blk.addrh = 0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.access_size = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; + acpi_fill_fadt_x86_pm(fadt, + pmbase + PM1_STS, + 0, + pmbase + PM1_CNT, + 0, + pmbase + PM2_CNT, + pmbase + PM1_TMR, + pmbase + GPE0_STS(0), + 0, + 4, + 2, + 1, + 4, + 2 * GPE0_REG_MAX * sizeof(uint32_t), + 0); soc_fill_fadt(fadt); } diff --git a/src/southbridge/amd/cimx/sb800/fadt.c b/src/southbridge/amd/cimx/sb800/fadt.c index 08fbecb..5b3fee6 100644 --- a/src/southbridge/amd/cimx/sb800/fadt.c +++ b/src/southbridge/amd/cimx/sb800/fadt.c @@ -104,22 +104,6 @@ /* RTC_En_En, TMR_En_En, GBL_EN_EN */ outl(0x1, PM1_CNT_BLK_ADDRESS); /* set SCI_EN */ - fadt->pm1a_evt_blk = PM1_EVT_BLK_ADDRESS; - fadt->pm1b_evt_blk = 0x0000; - fadt->pm1a_cnt_blk = PM1_CNT_BLK_ADDRESS; - fadt->pm1b_cnt_blk = 0x0000; - fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK_ADDRESS; - fadt->pm_tmr_blk = PM1_TMR_BLK_ADDRESS; - fadt->gpe0_blk = GPE0_BLK_ADDRESS; - fadt->gpe1_blk = 0; /* No gpe1 block in hudson1 */ - - fadt->pm1_evt_len = 4; /* 32 bits */ - fadt->pm1_cnt_len = 2; /* 16 bits */ - fadt->pm2_cnt_len = 1; /* 8 bits */ - fadt->pm_tmr_len = 4; /* 32 bits */ - fadt->gpe0_blk_len = 8; /* 64 bits */ - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; fadt->cst_cnt = 0x00; /* unused if SMI_CMD = 0 */ fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; @@ -143,17 +127,6 @@ ACPI_FADT_S4_RTC_VALID | ACPI_FADT_REMOTE_POWER_ON; - /* Format is from 5.2.3.1: Generic Address Structure */ - /* reset_reg: see section 4.7.3.6 ACPI 3.0a spec */ - /* 8 bit write of value 0x06 to 0xCF9 in IO space */ - fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0x0; - fadt->reset_value = 6; - fadt->ARM_boot_arch = 0; /* MUST be 0 ACPI 3.0 */ fadt->FADT_MinorVersion = 0; /* MUST be 0 ACPI 3.0 */ @@ -162,66 +135,22 @@ fadt->x_dsdt_l = ((uintptr_t)dsdt) & 0xffffffff; fadt->x_dsdt_h = ((uint64_t)(uintptr_t)dsdt) >> 32; - fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1a_evt_blk.addrl = PM1_EVT_BLK_ADDRESS; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.access_size = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - - fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = 0; - fadt->x_pm1a_cnt_blk.addrl = PM1_CNT_BLK_ADDRESS; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.access_size = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - - fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm2_cnt_blk.bit_width = 8; /* Hudson 1 Pm2Control is 8 bits */ - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK_ADDRESS; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - - fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm_tmr_blk.addrl = PM1_TMR_BLK_ADDRESS; - fadt->x_pm_tmr_blk.addrh = 0x0; - - - fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + Event Enable */ - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_gpe0_blk.addrl = GPE0_BLK_ADDRESS; - fadt->x_gpe0_blk.addrh = 0x0; - - - fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.access_size = 0; - fadt->x_gpe1_blk.addrl = 0; - fadt->x_gpe1_blk.addrh = 0x0; + acpi_fill_fadt_x86_pm(fadt, + PM1_EVT_BLK_ADDRESS, + 0x0000, + PM1_CNT_BLK_ADDRESS, + 0x0000, + ACPI_PMA_CNT_BLK_ADDRESS, + PM1_TMR_BLK_ADDRESS, + GPE0_BLK_ADDRESS, + 0, + 4, + 2, + 1, + 4, + 2 * sizeof(uint32_t), + 0, + 0); header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t)); diff --git a/src/southbridge/amd/pi/hudson/fadt.c b/src/southbridge/amd/pi/hudson/fadt.c index 8573c8b..b7192f9 100644 --- a/src/southbridge/amd/pi/hudson/fadt.c +++ b/src/southbridge/amd/pi/hudson/fadt.c @@ -77,23 +77,6 @@ fadt->cst_cnt = 0x00; /* unused if SMI_CMD = 0 */ } - fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; - fadt->pm1b_evt_blk = 0x0000; - fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK; - fadt->pm1b_cnt_blk = 0x0000; - fadt->pm2_cnt_blk = 0x0000; - fadt->pm_tmr_blk = ACPI_PM_TMR_BLK; - fadt->gpe0_blk = ACPI_GPE0_BLK; - fadt->gpe1_blk = 0x0000; /* No gpe1 block in hudson */ - - fadt->pm1_evt_len = 4; /* 32 bits */ - fadt->pm1_cnt_len = 2; /* 16 bits */ - fadt->pm2_cnt_len = 0; - fadt->pm_tmr_len = 4; /* 32 bits */ - fadt->gpe0_blk_len = 8; /* 64 bits */ - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; fadt->flush_size = 0; /* set to 0 if WBINVD is 1 in flags */ @@ -116,89 +99,31 @@ ACPI_FADT_S4_RTC_VALID | ACPI_FADT_REMOTE_POWER_ON; - /* Format is from 5.2.3.1: Generic Address Structure */ - /* reset_reg: see section 4.7.3.6 ACPI 3.0a spec */ - /* 8 bit write of value 0x06 to 0xCF9 in IO space */ - fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0x0; - - fadt->reset_value = 6; - - fadt->ARM_boot_arch = 0; /* MUST be 0 ACPI 3.0 */ - fadt->FADT_MinorVersion = 0; /* MUST be 0 ACPI 3.0 */ - fadt->x_firmware_ctl_l = 0; /* set to 0 if firmware_ctrl is used */ fadt->x_firmware_ctl_h = 0; fadt->x_dsdt_l = (u32) dsdt; fadt->x_dsdt_h = 0; - fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.access_size = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - - fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = 0; - fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.access_size = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - /* * Note: Under this current AMD C state implementation, this is no longer * used and should not be reported to OS. */ - fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm2_cnt_blk.bit_width = 0; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_pm2_cnt_blk.addrl = 0; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - - fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK; - fadt->x_pm_tmr_blk.addrh = 0x0; - - - fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + Event Enable */ - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK; - fadt->x_gpe0_blk.addrh = 0x0; - - - fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.access_size = 0; - fadt->x_gpe1_blk.addrl = 0; - fadt->x_gpe1_blk.addrh = 0x0; + acpi_fill_fadt_x86_pm(fadt, + ACPI_PM_EVT_BLK, + 0x0000, + ACPI_PM1_CNT_BLK, + 0x0000, + 0x0000, + ACPI_PM_TMR_BLK, + ACPI_GPE0_BLK, + 0x0000, + 4, + 2, + 0, + 4, + 2 * sizeof(uint32_t), + 0, + 0); header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t)); } diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 46ab5fc..9aec7db 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -717,22 +717,6 @@ fadt->s4bios_req = 0x0; fadt->pstate_cnt = 0; - fadt->pm1a_evt_blk = pmbase; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + 0x4; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + 0x50; - fadt->pm_tmr_blk = pmbase + 0x8; - fadt->gpe0_blk = pmbase + 0x20; - fadt->gpe1_blk = 0; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 16; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; fadt->cst_cnt = 0; c2_latency = chip->c2_latency; if (!c2_latency) { @@ -765,70 +749,22 @@ fadt->flags |= ACPI_FADT_C2_MP_SUPPORTED; } - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0; - - fadt->reset_value = 6; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm1a_evt_blk.addrl = pmbase; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.access_size = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.access_size = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = 128; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_gpe0_blk.addrl = pmbase + 0x20; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.access_size = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; + acpi_fill_fadt_x86_pm(fadt, + pmbase, + 0x0, + pmbase + 0x4, + 0x0, + pmbase + 0x50, + pmbase + 0x8, + pmbase + 0x20, + 0, + 4, + 2, + 1, + 4, + 2 * 2 * sizeof(uint32_t), + 0, + 0); } static const char *lpc_acpi_name(const struct device *dev) diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c index db1071a..4b27b97 100644 --- a/src/southbridge/intel/i82371eb/fadt.c +++ b/src/southbridge/intel/i82371eb/fadt.c @@ -52,25 +52,6 @@ fadt->s4bios_req = 0x0; fadt->pstate_cnt = 0x0; - fadt->pm1a_evt_blk = DEFAULT_PMBASE; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = DEFAULT_PMBASE + PMCNTRL; - fadt->pm1b_cnt_blk = 0x0; - - fadt->pm2_cnt_blk = 0; - fadt->pm_tmr_blk = DEFAULT_PMBASE + PMTMR; - fadt->gpe0_blk = DEFAULT_PMBASE + GPSTS; - fadt->gpe1_blk = 0x0; - fadt->gpe1_base = 0; - fadt->gpe1_blk_len = 0; - - /* *_len define register width in bytes */ - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 0; /* not supported */ - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 4; - fadt->cst_cnt = 0; /* smi command to indicate c state changed notification */ fadt->p_lvl2_lat = 101; /* >100 means c2 not supported */ fadt->p_lvl3_lat = 1001; /* >1000 means c3 not supported */ @@ -141,74 +122,22 @@ */ fadt->flags = 0xa5; - fadt->reset_reg.space_id = 0; - fadt->reset_reg.bit_width = 0; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.access_size = 0; - fadt->reset_reg.addrl = 0x0; - fadt->reset_reg.addrh = 0x0; - fadt->reset_value = 0; - - fadt->x_firmware_ctl_l = (uintptr_t)facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (uintptr_t)dsdt; - fadt->x_dsdt_h = 0; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = fadt->pm1_evt_len * 8; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm1b_evt_blk.addrl = fadt->pm1b_evt_blk; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1b_cnt_blk.addrl = fadt->pm1b_cnt_blk; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = 0; - fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = fadt->gpe1_blk_len * 8; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_gpe1_blk.addrl = fadt->gpe1_blk; - fadt->x_gpe1_blk.addrh = 0x0; + acpi_fill_fadt_x86_pm(fadt, + DEFAULT_PMBASE, + 0, + DEFAULT_PMBASE + PMCNTRL, + 0, + 0, + DEFAULT_PMBASE + PMTMR, + DEFAULT_PMBASE + GPSTS, + 0, + 4, + 2, + 0, + 4, + 2 * sizeof(uint16_t), + 0, + 0); header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); } diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 743dbba..8977228 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -452,87 +452,6 @@ config_t *chip = dev->chip_info; u16 pmbase = lpc_get_pmbase(); - fadt->pm1a_evt_blk = pmbase; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + PM1_CNT; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + PM2_CNT; - fadt->pm_tmr_blk = pmbase + PM1_TMR; - fadt->gpe0_blk = pmbase + GPE0_STS; - fadt->gpe1_blk = 0; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 8; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0; - - fadt->reset_value = 6; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm1a_evt_blk.addrl = pmbase; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 0; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.access_size = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 0; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.access_size = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_pm2_cnt_blk.addrl = pmbase + PM2_CNT; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = 64; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_gpe0_blk.addrl = pmbase + GPE0_STS; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 0; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.access_size = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; fadt->day_alrm = 0xd; fadt->mon_alrm = 0x00; fadt->century = 0x32; @@ -562,6 +481,23 @@ | ACPI_FADT_C2_MP_SUPPORTED); if (chip->docking_supported) fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED; + + acpi_fill_fadt_x86_pm(fadt, + pmbase, + 0, + pmbase + PM1_CNT, + 0, + pmbase + PM2_CNT, + pmbase + PM1_TMR, + pmbase + GPE0_STS, + 0, + 4, + 2, + 1, + 4, + 2 * sizeof(uint32_t), + 0, + 0); } static void i82801gx_lpc_read_resources(struct device *dev) diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index e3fdde7..ae40a42 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -460,86 +460,6 @@ config_t *chip = dev->chip_info; u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; - fadt->pm1a_evt_blk = pmbase; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + 0x4; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + 0x50; - fadt->pm_tmr_blk = pmbase + 0x8; - fadt->gpe0_blk = pmbase + 0x20; - fadt->gpe1_blk = 0; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 16; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0; - fadt->reset_value = 6; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm1a_evt_blk.addrl = pmbase; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 0; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.access_size = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 0; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.access_size = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = 128; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_gpe0_blk.addrl = pmbase + 0x20; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 0; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.access_size = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; fadt->day_alrm = 0xd; fadt->mon_alrm = 0x00; fadt->century = 0x32; @@ -569,6 +489,23 @@ | ACPI_FADT_C2_MP_SUPPORTED); if (chip->docking_supported) fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED; + + acpi_fill_fadt_x86_pm(fadt, + pmbase, + 0, + pmbase + 0x4, + 0, + pmbase + 0x50, + pmbase + 0x8, + pmbase + 0x20, + 0, + 4, + 2, + 1, + 4, + 2 * 2 * sizeof(uint32_t), + 0, + 0); } static void i82801jx_lpc_read_resources(struct device *dev) diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 0062e09..29a263a 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -617,22 +617,6 @@ fadt->s4bios_req = 0x0; fadt->pstate_cnt = 0; - fadt->pm1a_evt_blk = pmbase; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + 0x4; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + 0x50; - fadt->pm_tmr_blk = pmbase + 0x8; - fadt->gpe0_blk = pmbase + 0x20; - fadt->gpe1_blk = 0; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 16; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; fadt->cst_cnt = 0; c2_latency = chip->c2_latency; if (!c2_latency) { @@ -664,70 +648,22 @@ fadt->flags |= ACPI_FADT_C2_MP_SUPPORTED; } - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0; - - fadt->reset_value = 6; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm1a_evt_blk.addrl = pmbase; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.access_size = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.access_size = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = 128; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_gpe0_blk.addrl = pmbase + 0x20; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.access_size = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; + acpi_fill_fadt_x86_pm(fadt, + pmbase, + 0, + pmbase + 0x4, + 0, + pmbase + 0x50, + pmbase + 0x8, + pmbase + 0x20, + 0, + 4, + 2, + 1, + 4, + 2 * 2 * sizeof(uint32_t), + 0, + 0); } static const char *lpc_acpi_name(const struct device *dev) diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 0bfca35..589c4fa 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -767,35 +767,6 @@ fadt->s4bios_req = 0x0; fadt->pstate_cnt = 0; - fadt->pm1a_evt_blk = pmbase + PM1_STS; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + PM1_CNT; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + PM2_CNT; - fadt->pm_tmr_blk = pmbase + PM1_TMR; - if (pch_is_lp()) - fadt->gpe0_blk = pmbase + LP_GPE0_STS_1; - else - fadt->gpe0_blk = pmbase + GPE0_STS; - fadt->gpe1_blk = 0; - - /* - * Some of the lengths here are doubled. This is because they describe - * blocks containing two registers, where the size of each register - * is found by halving the block length. See Table 5-34 and section - * 4.8.3 of the ACPI specification for details. - */ - fadt->pm1_evt_len = 2 * 2; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - if (pch_is_lp()) - fadt->gpe0_blk_len = 2 * 16; - else - fadt->gpe0_blk_len = 2 * 8; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - fadt->cst_cnt = 0; fadt->p_lvl2_lat = 1; fadt->p_lvl3_lat = 87; @@ -820,76 +791,21 @@ if (cfg->docking_supported) fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED; - fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0; - - fadt->reset_value = 6; - - fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1a_evt_blk.bit_width = 2 * 16; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.access_size = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.access_size = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_pm2_cnt_blk.addrl = pmbase + PM2_CNT; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; - fadt->x_pm_tmr_blk.addrh = 0x0; - - /* - * Windows 10 requires x_gpe0_blk to be set starting with FADT revision 5. - * The bit_width field intentionally overflows here. - * The OSPM can instead use the values in `fadt->gpe0_blk{,_len}`, which - * seems to work fine on Linux 5.0 and Windows 10. - */ - fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.access_size = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; + acpi_fill_fadt_x86_pm(fadt, + pmbase + PM1_STS, + 0, + pmbase + PM1_CNT, + 0, + pmbase + PM2_CNT, + pmbase + PM1_TMR, + pch_is_lp() ? (pmbase + LP_GPE0_STS_1) : (pmbase + GPE0_STS), + 0, + 4, + 2, + 1, + 4, + pch_is_lp() ? (2 * 4 * sizeof(uint32_t)) : (2 * 2 * sizeof(uint32_t)), + 0); } static const char *lpc_acpi_name(const struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/40036 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If58fcf9a1c39c159dfa08339cb931e552d499747 Gerrit-Change-Number: 40036 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/lynxpoint: Setup gpio in bootblock

by Arthur Heymans (Code Review)

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36712 ) Change subject: sb/intel/lynxpoint: Setup gpio in bootblock ...................................................................... sb/intel/lynxpoint: Setup gpio in bootblock GPIO setup is needed for verstage. verstage can also still happen after romstage so keep the GPIO init there too. Change-Id: I448ca12f5ddab362983429c508e518b7042ef760 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/asrock/h81m-hds/Makefile.inc M src/mainboard/google/beltino/Makefile.inc M src/mainboard/google/slippy/Makefile.inc M src/mainboard/intel/baskingridge/Makefile.inc M src/mainboard/supermicro/x10slm-f/Makefile.inc M src/southbridge/intel/common/Makefile.inc M src/southbridge/intel/lynxpoint/Makefile.inc M src/southbridge/intel/lynxpoint/bootblock.c M src/southbridge/intel/lynxpoint/early_pch.c M src/southbridge/intel/lynxpoint/pch.h 10 files changed, 22 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/36712/1 diff --git a/src/mainboard/asrock/h81m-hds/Makefile.inc b/src/mainboard/asrock/h81m-hds/Makefile.inc index de18bc5..3fc7ac7 100644 --- a/src/mainboard/asrock/h81m-hds/Makefile.inc +++ b/src/mainboard/asrock/h81m-hds/Makefile.inc @@ -16,4 +16,5 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += gpio.c bootblock-y += bootblock.c diff --git a/src/mainboard/google/beltino/Makefile.inc b/src/mainboard/google/beltino/Makefile.inc index 7535350..0ecb31d 100644 --- a/src/mainboard/google/beltino/Makefile.inc +++ b/src/mainboard/google/beltino/Makefile.inc @@ -23,5 +23,7 @@ romstage-y += variants/$(VARIANT_DIR)/led.c romstage-y += variants/$(VARIANT_DIR)/gpio.c +bootblock-y += variants/$(VARIANT_DIR)/gpio.c + subdirs-y += variants/$(VARIANT_DIR) CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/google/slippy/Makefile.inc b/src/mainboard/google/slippy/Makefile.inc index f80dcab..e35f93e 100644 --- a/src/mainboard/google/slippy/Makefile.inc +++ b/src/mainboard/google/slippy/Makefile.inc @@ -23,6 +23,8 @@ romstage-y += variants/$(VARIANT_DIR)/romstage.c romstage-y += variants/$(VARIANT_DIR)/gpio.c +bootblock-y += variants/$(VARIANT_DIR)/gpio.c + subdirs-y += variants/$(VARIANT_DIR) ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/intel/baskingridge/Makefile.inc b/src/mainboard/intel/baskingridge/Makefile.inc index 91a7963..8f12999 100644 --- a/src/mainboard/intel/baskingridge/Makefile.inc +++ b/src/mainboard/intel/baskingridge/Makefile.inc @@ -17,6 +17,7 @@ ramstage-y += chromeos.c verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += chromeos.c +bootblock-y += gpio.c romstage-y += gpio.c smm-y += mainboard_smi.c diff --git a/src/mainboard/supermicro/x10slm-f/Makefile.inc b/src/mainboard/supermicro/x10slm-f/Makefile.inc index 301070b..0b4f367 100644 --- a/src/mainboard/supermicro/x10slm-f/Makefile.inc +++ b/src/mainboard/supermicro/x10slm-f/Makefile.inc @@ -15,4 +15,5 @@ ## romstage-y += gpio.c +bootblock-y += gpio.c bootblock-y += bootblock.c diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index 5ca7daf..433a310 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -34,6 +34,7 @@ romstage-$(CONFIG_USBDEBUG) += usb_debug.c ramstage-$(CONFIG_USBDEBUG) += usb_debug.c +bootblock-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index e53ed8d..bacaf74 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -50,6 +50,7 @@ romstage-y += rcba.c pmutil.c ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y) +bootblock-y += lp_gpio.c romstage-y += lp_gpio.c ramstage-y += lp_gpio.c smm-y += lp_gpio.c diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c index 39e6925..abcb35b 100644 --- a/src/southbridge/intel/lynxpoint/bootblock.c +++ b/src/southbridge/intel/lynxpoint/bootblock.c @@ -16,6 +16,7 @@ #include <device/pci_ops.h> #include <cpu/intel/car/bootblock.h> #include "pch.h" +#include "lp_gpio.h" /* * Enable Prefetching and Caching. @@ -33,14 +34,6 @@ pci_write_config8(dev, 0xdc, reg8); } - -static void map_rcba(void) -{ - pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); - - pci_write_config32(dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1); -} - static void enable_port80_on_lpc(void) { /* Enable port 80 POST on LPC. The chipset does this by default, @@ -72,7 +65,7 @@ void bootblock_early_southbridge_init(void) { - map_rcba(); + pch_enable_bars(); enable_spi_prefetch(); enable_port80_on_lpc(); set_spi_speed(); @@ -83,3 +76,12 @@ pch_enable_lpc(); mainboard_config_superio(); } + +void bootblock_southbridge_init(void) +{ +#if CONFIG(INTEL_LYNXPOINT_LP) + setup_pch_lp_gpios(mainboard_gpio_map); +#else + setup_pch_gpios(mainboard_gpio_map); +#endif +} diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index b49d3cf..9cf021e 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -45,7 +45,7 @@ return id == PCH_TYPE_LPT_LP; } -static void pch_enable_bars(void) +void pch_enable_bars(void) { /* Setting up Southbridge. In the northbridge code. */ pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1); diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 8802be1..561c5b7 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -184,6 +184,7 @@ int early_pch_init(const struct rcba_config_instruction *rcba_config); void pch_enable_lpc(void); void mainboard_config_superio(void); +void pch_enable_bars(void); #define MAINBOARD_POWER_OFF 0 #define MAINBOARD_POWER_ON 1 -- To view, visit https://review.coreboot.org/c/coreboot/+/36712 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I448ca12f5ddab362983429c508e518b7042ef760 Gerrit-Change-Number: 36712 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: autoport: Add support for Haswell-LynxPoint platform

by Iru Cai (vimacs) (Code Review)

Hello Iru Cai, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/30890 to review the following change. Change subject: autoport: Add support for Haswell-LynxPoint platform ...................................................................... autoport: Add support for Haswell-LynxPoint platform It can now generate a buildable source for Clevo W650SZ. TODO: - Support Lynx Point LP (GPIO registers differ from non-LP) - Use PCH HD-Audio in azilia instead of the CPU/Northbridge HD-Audio Change-Id: I4f6e8c97b5122101de2f36bba8ba9f8ddd5b813a Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- M util/autoport/azalia.go A util/autoport/haswell.go A util/autoport/lynxpoint.go M util/autoport/main.go 4 files changed, 625 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/30890/1 diff --git a/util/autoport/azalia.go b/util/autoport/azalia.go index c525189..3090dd0 100644 --- a/util/autoport/azalia.go +++ b/util/autoport/azalia.go @@ -62,4 +62,9 @@ RegisterPCI(0x8086, 0x1c20, azalia{}) /* C216/ivybridge */ RegisterPCI(0x8086, 0x1e20, azalia{}) + /* Haswell */ + RegisterPCI(0x8086, 0x0c0c, azalia{}) + /* Lynx Point */ + RegisterPCI(0x8086, 0x8c20, azalia{}) + RegisterPCI(0x8086, 0x9c20, azalia{}) } diff --git a/util/autoport/haswell.go b/util/autoport/haswell.go new file mode 100644 index 0000000..d3c9d9f --- /dev/null +++ b/util/autoport/haswell.go @@ -0,0 +1,119 @@ +package main + +type haswellmc struct { + variant string +} + +func (i haswellmc) Scan(ctx Context, addr PCIDevData) { + inteltool := ctx.InfoSource.GetInteltool() + + /* FIXME:XX Move this somewhere else. */ + MainboardIncludes = append(MainboardIncludes, "drivers/intel/gma/int15.h") + MainboardEnable += (` /* FIXME: fix those values*/ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +`) + + DevTree = DevTreeNode{ + Chip: "northbridge/intel/haswell", + MissingParent: "northbridge", + Comment: "FIXME: check gfx.ndid and gfx.did", + Registers: map[string]string{ + "gpu_dp_b_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 2) & 7), + "gpu_dp_c_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 10) & 7), + "gpu_dp_d_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 18) & 7), + "gpu_panel_port_select": FormatInt32((inteltool.IGD[0xc7208] >> 30) & 3), + "gpu_panel_power_up_delay": FormatInt32((inteltool.IGD[0xc7208] >> 16) & 0x1fff), + "gpu_panel_power_backlight_on_delay": FormatInt32(inteltool.IGD[0xc7208] & 0x1fff), + "gpu_panel_power_down_delay": FormatInt32((inteltool.IGD[0xc720c] >> 16) & 0x1fff), + "gpu_panel_power_backlight_off_delay": FormatInt32(inteltool.IGD[0xc720c] & 0x1fff), + "gpu_panel_power_cycle_delay": FormatInt32(inteltool.IGD[0xc7210] & 0xff), + "gpu_cpu_backlight": FormatHex32(inteltool.IGD[0x48254]), + "gpu_pch_backlight": FormatHex32((inteltool.IGD[0xc8254] >> 16) * 0x10001), + "gpu_ddi_e_connected": FormatBool(((inteltool.IGD[0x64000] >> 4) & 1) == 0), + /* FIXME:XX hardcoded. */ + "gfx.ndid": "3", + "gfx.did": "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }", + }, + Children: []DevTreeNode{ + { + Chip: "cpu_cluster", + Dev: 0, + Children: []DevTreeNode{ + { + Chip: "cpu/intel/haswell", + Children: []DevTreeNode{ + { + Chip: "lapic", + Dev: 0, + }, + { + Chip: "lapic", + Dev: 0xacac, + Disabled: true, + }, + }, + Registers: map[string]string{ + /* FIXME:XX hardcoded. */ + "c1_acpower": "1", + "c2_acpower": "3", + "c3_acpower": "5", + "c1_battery": "1", + "c2_battery": "3", + "c3_battery": "5", + }, + }, + }, + }, + + { + Chip: "domain", + Dev: 0, + PCIController: true, + ChildPCIBus: 0, + PCISlots: []PCISlot{ + PCISlot{PCIAddr: PCIAddr{Dev: 0x0, Func: 0}, writeEmpty: true, additionalComment: "Host bridge"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1, Func: 0}, writeEmpty: true, additionalComment: "PCIe Bridge for discrete graphics"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x2, Func: 0}, writeEmpty: true, additionalComment: "Internal graphics"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x3, Func: 0}, writeEmpty: true, additionalComment: "Mini-HD audio"}, + }, + }, + }, + } + + PutPCIDev(addr, "Host bridge") + + /* FIXME:XX some configs are unsupported. */ + + KconfigBool["CPU_INTEL_HASWELL"] = true + KconfigBool["NORTHBRIDGE_INTEL_HASWELL"] = true + KconfigBool["INTEL_INT15"] = true + KconfigBool["HAVE_ACPI_TABLES"] = true + KconfigBool["HAVE_ACPI_RESUME"] = true + + KconfigInt["MAX_CPUS"] = 8 + + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "cpu/intel/common/acpi/cpu.asl", + }) + + DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{ + File: "northbridge/intel/haswell/acpi/haswell.asl", + }, DSDTInclude{ + File: "drivers/intel/gma/acpi/default_brightness_levels.asl", + }) +} + +func init() { + RegisterPCI(0x8086, 0x0c00, haswellmc{variant: "Desktop"}) + RegisterPCI(0x8086, 0x0c04, haswellmc{variant: "Mobile"}) + RegisterPCI(0x8086, 0x0a04, haswellmc{variant: "ULT"}) + RegisterPCI(0x8086, 0x0c08, haswellmc{variant: "Server"}) + for _, id := range []uint16{ + 0x0402, 0x0412, 0x0422, + 0x0406, 0x0416, 0x0426, + 0x0d16, 0x0d26, 0x0d36, + 0x0a06, 0x0a16, 0x0a26, + } { + RegisterPCI(0x8086, id, GenericVGA{GenericPCI{Comment: "VGA controller"}}) + } +} diff --git a/util/autoport/lynxpoint.go b/util/autoport/lynxpoint.go new file mode 100644 index 0000000..df20c3f --- /dev/null +++ b/util/autoport/lynxpoint.go @@ -0,0 +1,495 @@ +package main + +import ( + "fmt" + "os" +) + +type lynxpoint struct { + variant string + node *DevTreeNode +} + +func (b lynxpoint) writeGPIOSet(ctx Context, sb *os.File, + val uint32, set uint, partno int, constraint uint32) { + + max := uint(32) + if set == 3 { + max = 12 + } + + bits := [6][2]string{ + {"GPIO_MODE_NATIVE", "GPIO_MODE_GPIO"}, + {"GPIO_DIR_OUTPUT", "GPIO_DIR_INPUT"}, + {"GPIO_LEVEL_LOW", "GPIO_LEVEL_HIGH"}, + {"GPIO_RESET_PWROK", "GPIO_RESET_RSMRST"}, + {"GPIO_NO_INVERT", "GPIO_INVERT"}, + {"GPIO_NO_BLINK", "GPIO_BLINK"}, + } + + for i := uint(0); i < max; i++ { + if ((constraint>>i)&1 == 1) { + fmt.Fprintf(sb, " .gpio%d = %s,\n", + (set-1)*32+i, + bits[partno][(val>>i)&1]) + } + } +} + +func (b lynxpoint) GPIO(ctx Context, inteltool InteltoolData) { + var constraint uint32 + gpio := Create(ctx, "gpio.c") + defer gpio.Close() + + AddROMStageFile("gpio.c", "") + + Add_gpl(gpio) + gpio.WriteString("#include <southbridge/intel/common/gpio.h>\n\n") + + /* TODO: different in LP PCH */ + addresses := [3][6]int{ + {0x00, 0x04, 0x0c, 0x60, 0x2c, 0x18}, + {0x30, 0x34, 0x38, 0x64, -1, -1}, + {0x40, 0x44, 0x48, 0x68, -1, -1}, + } + + for set := 1; set <= 3; set++ { + for partno, part := range []string{"mode", "direction", "level", "reset", "invert", "blink"} { + addr := addresses[set-1][partno] + if addr < 0 { + continue + } + fmt.Fprintf(gpio, "static const struct pch_gpio_set%d pch_gpio_set%d_%s = {\n", + set, set, part) + + constraint = 0xffffffff + switch part { + case "direction": + /* Ignored on native mode */ + constraint = inteltool.GPIO[uint16(addresses[set-1][0])] + case "level": + /* Level doesn't matter for input */ + constraint = inteltool.GPIO[uint16(addresses[set-1][0])] + constraint &^= inteltool.GPIO[uint16(addresses[set-1][1])] + case "reset": + /* Only show reset */ + constraint = inteltool.GPIO[uint16(addresses[set-1][3])] + case "invert": + /* Only on input and only show inverted GPIO */ + constraint = inteltool.GPIO[uint16(addresses[set-1][0])] + constraint &= inteltool.GPIO[uint16(addresses[set-1][1])] + constraint &= inteltool.GPIO[uint16(addresses[set-1][4])] + case "blink": + /* Only on output and only show blinking GPIO */ + constraint = inteltool.GPIO[uint16(addresses[set-1][0])] + constraint &^= inteltool.GPIO[uint16(addresses[set-1][1])] + constraint &= inteltool.GPIO[uint16(addresses[set-1][5])] + } + b.writeGPIOSet(ctx, gpio, inteltool.GPIO[uint16(addr)], uint(set), partno, constraint) + gpio.WriteString("};\n\n") + } + } + + gpio.WriteString(`const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; +`) +} + +func (b lynxpoint) IsPCIeHotplug(ctx Context, port int) bool { + portDev, ok := PCIMap[PCIAddr{Bus: 0, Dev: 0x1c, Func: port}] + if !ok { + return false + } + return (portDev.ConfigDump[0xdb] & (1 << 6)) != 0 +} + +func (b lynxpoint) GetGPIOHeader() string { + return "southbridge/intel/lynxpoint/pch.h" +} + +func (b lynxpoint) EnableGPE(in int) { + b.node.Registers[fmt.Sprintf("gpi%d_routing", in)] = "2" +} + +func (b lynxpoint) EncodeGPE(in int) int { + return in + 0x10 +} + +func (b lynxpoint) DecodeGPE(in int) int { + return in - 0x10 +} + +func (b lynxpoint) NeedRouteGPIOManually() { + b.node.Comment += ", FIXME: set gpiX_routing for EC support" +} + +func (b lynxpoint) Scan(ctx Context, addr PCIDevData) { + + SouthBridge = &b + + inteltool := ctx.InfoSource.GetInteltool() + b.GPIO(ctx, inteltool) + + KconfigBool["SOUTHBRIDGE_INTEL_LYNXPOINT"] = true + if b.variant == "Lynx Point LP" { + KconfigBool["INTEL_LYNXPOINT_LP"] = true + } + KconfigBool["SERIRQ_CONTINUOUS_MODE"] = true + KconfigInt["USBDEBUG_HCD_INDEX"] = 2 + KconfigComment["USBDEBUG_HCD_INDEX"] = "FIXME: check this" + dmi := ctx.InfoSource.GetDMI() + if dmi.Vendor == "LENOVO" { + KconfigInt["DRAM_RESET_GATE_GPIO"] = 10 + } else { + KconfigInt["DRAM_RESET_GATE_GPIO"] = 60 + } + KconfigComment["DRAM_RESET_GATE_GPIO"] = "FIXME: check this" + + /* Not strictly speaking correct. These subsys/subvendor referer to PCI devices. + But most systems don't have any of those. But the config needs to be set + nevertheless. So set it to southbridge subsys/subvendor. */ + KconfigHex["MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID"] = uint32(GetLE16(addr.ConfigDump[0x2c:0x2e])) + KconfigHex["MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID"] = uint32(GetLE16(addr.ConfigDump[0x2e:0x30])) + + ich9GetFlashSize(ctx) + + DSDTDefines = append(DSDTDefines, + DSDTDefine{ + Key: "BRIGHTNESS_UP", + Value: "\\_SB.PCI0.GFX0.INCB", + }, + DSDTDefine{ + Key: "BRIGHTNESS_DOWN", + Value: "\\_SB.PCI0.GFX0.DECB", + }, + DSDTDefine{ + Key: "ACPI_VIDEO_DEVICE", + Value: "\\_SB.PCI0.GFX0", + }) + + /* SPI init */ + MainboardIncludes = append(MainboardIncludes, "southbridge/intel/lynxpoint/pch.h") + + cur := DevTreeNode{ + Chip: "southbridge/intel/lynxpoint", + Comment: "Intel Series 8 Lynx Point PCH", + + Registers: map[string]string{ + "pirqa_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x60]), + "pirqb_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x61]), + "pirqc_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x62]), + "pirqd_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x63]), + "pirqe_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x68]), + "pirqf_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x69]), + "pirqg_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x6a]), + "pirqh_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x6b]), + "sata_ahci": "1", + "gen1_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x84:0x88]), + "gen2_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x88:0x8c]), + "gen3_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x8c:0x90]), + "gen4_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x90:0x94]), + "sata_port_map": fmt.Sprintf("0x%x", PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 2}].ConfigDump[0x92]&0x3f), + }, + PCISlots: []PCISlot{ + PCISlot{PCIAddr: PCIAddr{Dev: 0x14, Func: 0}, writeEmpty: false, additionalComment: "USB 3.0 Controller"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 0}, writeEmpty: true, additionalComment: "Management Engine Interface 1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 1}, writeEmpty: true, additionalComment: "Management Engine Interface 2"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 2}, writeEmpty: true, additionalComment: "Management Engine IDE-R"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 3}, writeEmpty: true, additionalComment: "Management Engine KT"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x19, Func: 0}, writeEmpty: true, additionalComment: "Intel Gigabit Ethernet"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1a, Func: 0}, writeEmpty: true, additionalComment: "USB2 EHCI #2"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1b, Func: 0}, writeEmpty: true, additionalComment: "High Definition Audio"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 0}, writeEmpty: true, additionalComment: "PCIe Port #1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 1}, writeEmpty: true, additionalComment: "PCIe Port #2"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 2}, writeEmpty: true, additionalComment: "PCIe Port #3"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 3}, writeEmpty: true, additionalComment: "PCIe Port #4"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 4}, writeEmpty: true, additionalComment: "PCIe Port #5"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 5}, writeEmpty: true, additionalComment: "PCIe Port #6"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 6}, writeEmpty: true, additionalComment: "PCIe Port #7"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 7}, writeEmpty: true, additionalComment: "PCIe Port #8"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1d, Func: 0}, writeEmpty: true, additionalComment: "USB2 EHCI #1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1e, Func: 0}, writeEmpty: true, additionalComment: "PCI bridge"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 0}, writeEmpty: true, additionalComment: "LPC bridge"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 2}, writeEmpty: true, additionalComment: "SATA Controller 1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 3}, writeEmpty: true, additionalComment: "SMBus"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 5}, writeEmpty: true, additionalComment: "SATA Controller 2"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 6}, writeEmpty: true, additionalComment: "Thermal"}, + }, + } + + b.node = &cur + + PutPCIChip(addr, cur) + PutPCIDevParent(addr, "PCI-LPC bridge", "lpc") + + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "southbridge/intel/lynxpoint/acpi/platform.asl", + }) + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "southbridge/intel/lynxpoint/acpi/globalnvs.asl", + Comment: "global NVS and variables", + }) + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "southbridge/intel/lynxpoint/acpi/sleepstates.asl", + }) + DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{ + File: "southbridge/intel/lynxpoint/acpi/pch.asl", + }) + + sb := Create(ctx, "romstage.c") + defer sb.Close() + Add_gpl(sb) + sb.WriteString(`#include <stdint.h> +#include <cpu/intel/romstage.h> +#include <cpu/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/pei_data.h> +#include <southbridge/intel/common/gpio.h> +#include <southbridge/intel/lynxpoint/pch.h> + +static const struct rcba_config_instruction rcba_config[] = { +`) + RestoreDIRRoute(sb, "D31IR", uint16(inteltool.RCBA[0x3140])) + RestoreDIRRoute(sb, "D29IR", uint16(inteltool.RCBA[0x3144])) + RestoreDIRRoute(sb, "D28IR", uint16(inteltool.RCBA[0x3146])) + RestoreDIRRoute(sb, "D27IR", uint16(inteltool.RCBA[0x3148])) + RestoreDIRRoute(sb, "D26IR", uint16(inteltool.RCBA[0x314c])) + RestoreDIRRoute(sb, "D25IR", uint16(inteltool.RCBA[0x3150])) + RestoreDIRRoute(sb, "D22IR", uint16(inteltool.RCBA[0x315c])) + RestoreDIRRoute(sb, "D20IR", uint16(inteltool.RCBA[0x3160])) + + sb.WriteString(` + RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS), + + RCBA_END_CONFIG, +};`) + + sb.WriteString(` + +void mainboard_config_superio(void) +{ +} + +void mainboard_romstage_entry(unsigned long bist) +{ + struct pei_data pei_data = { + .pei_version = PEI_VERSION, + .mchbar = (uintptr_t)DEFAULT_MCHBAR, + .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .epbar = DEFAULT_EPBAR, + .pciexbar = DEFAULT_PCIEXBAR, + .smbusbar = SMBUS_IO_BASE, + .wdbbar = 0x4000000, + .wdbsize = 0x1000, + .hpet_address = HPET_ADDR, + .rcba = (uintptr_t)DEFAULT_RCBA, + .pmbase = DEFAULT_PMBASE, + .gpiobase = DEFAULT_GPIOBASE, + .temp_mmio_base = 0xfed08000, + .system_type = 1, /* desktop/server, FIXME: check this */ + .tseg_size = CONFIG_SMM_TSEG_SIZE, + .spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 }, /* FIXME: check this */ + .ec_present = 0, + .dimm_channel0_disabled = 0, /* FIXME: leave channel 0 enabled */ + .dimm_channel1_disabled = 0, /* FIXME: leave channel 1 enabled */ + .max_ddr3_freq = 1600, + .usb2_ports = { + /* Length, Enable, OCn#, Location */ +`) + + pdo1 := PCIMap[PCIAddr{Bus: 0, Dev: 0x1d, Func: 0}].ConfigDump[0x64] + ocmap1 := PCIMap[PCIAddr{Bus: 0, Dev: 0x1d, Func: 0}].ConfigDump[0x74:0x78] + pdo2 := PCIMap[PCIAddr{Bus: 0, Dev: 0x1a, Func: 0}].ConfigDump[0x64] + ocmap2 := PCIMap[PCIAddr{Bus: 0, Dev: 0x1a, Func: 0}].ConfigDump[0x74:0x78] + + for port := uint(0); port < 14; port++ { + var port_oc int = -1 + var port_pos string + var port_disable uint8 + + if port < 8 { + port_disable = (pdo1 >> port) & 1 + for oc := 0; oc < 4; oc++ { + if ((ocmap1[oc] & (1 << port)) != 0) { + port_oc = oc + break + } + } + } else { + port_disable = (pdo2 >> (port - 8)) & 1 + for oc := 0; oc < 4; oc++ { + if ((ocmap2[oc] & (1 << (port - 8))) != 0) { + port_oc = oc + 4 + break + } + } + } + if port_disable == 1 { + port_pos = "USB_PORT_SKIP" + } else { + port_pos = "USB_PORT_BACK_PANEL" + } + if port_oc == -1 { + fmt.Fprintf(sb, " { 0x0040, %d, USB_OC_PIN_SKIP, %s },\n", + (port_disable ^ 1), port_pos) + } else { + fmt.Fprintf(sb, " { 0x0040, %d, %d, %s },\n", + (port_disable ^ 1), port_oc, port_pos) + } + } + + sb.WriteString(` }, + .usb3_ports = { +`) + + xpdo := PCIMap[PCIAddr{Bus: 0, Dev: 0x14, Func: 0}].ConfigDump[0xe8] + u3ocm := PCIMap[PCIAddr{Bus: 0, Dev: 0x14, Func: 0}].ConfigDump[0xc8:0xd0] + + for port := uint(0); port < 6; port++ { + var port_oc int = -1 + port_disable := (xpdo >> port) & 1 + for oc := 0; oc < 8; oc++ { + if (u3ocm[oc] & (1 << port)) != 0 { + port_oc = oc + break + } + } + if port_oc == -1 { + fmt.Fprintf(sb, " { %d, USB_OC_PIN_SKIP },\n", + (port_disable ^ 1)) + } else { + fmt.Fprintf(sb, " { %d, %d },\n", + (port_disable ^ 1), port_oc) + } + } + + sb.WriteString(` }, + }; + + struct romstage_params romstage_params = { + .pei_data = &pei_data, + .gpio_map = &mainboard_gpio_map, + .rcba_config = &rcba_config[0], + .bist = bist, + }; + + romstage_common(&romstage_params); +}`) + + gnvs := Create(ctx, "acpi_tables.c") + defer gnvs.Close() + + Add_gpl(gnvs) + gnvs.WriteString(`#include <southbridge/intel/lynxpoint/nvs.h> + +/* FIXME: check this function. */ +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + // the lid is open by default. + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} +`) + +} + +func init() { + for _, id := range []uint16 { + 0x8c41, 0x8c49, 0x8c4b, 0x8c4f, + } { + RegisterPCI(0x8086, uint16(id), lynxpoint{variant: "Lynx Point Mobile"}) + } + + for _, id := range []uint16 { + 0x8c42, 0x8c44, 0x8c46, 0x8c4a, + 0x8c4c, 0x8c4e, 0x8c50, 0x8c5c, + } { + RegisterPCI(0x8086, uint16(id), lynxpoint{variant: "Lynx Point Desktop"}) + } + + for _, id := range []uint16 { + 0x8c52, 0x8c54, 0x8c56, + } { + RegisterPCI(0x8086, uint16(id), lynxpoint{variant: "Lynx Point Server"}) + } + + for _, id := range []uint16 { + 0x9c41, 0x9c43, 0x9c45, + } { + RegisterPCI(0x8086, uint16(id), lynxpoint{variant: "Lynx Point LP"}) + } + + /* PCIe bridge */ + for _, id := range []uint16{ + 0x8c10, 0x8c12, 0x8c14, 0x8c16, 0x8c18, 0x8c1a, 0x8c1c, 0x8c1e, + 0x9c10, 0x9c12, 0x9c14, 0x9c16, 0x9c18, 0x9c1a, + } { + RegisterPCI(0x8086, id, GenericPCI{}) + } + + /* SMBus controller */ + RegisterPCI(0x8086, 0x1c22, GenericPCI{MissingParent: "smbus"}) + RegisterPCI(0x8086, 0x1e22, GenericPCI{MissingParent: "smbus"}) + RegisterPCI(0x8086, 0x8c22, GenericPCI{MissingParent: "smbus"}) + RegisterPCI(0x8086, 0x9c22, GenericPCI{MissingParent: "smbus"}) + + /* SATA */ + for _, id := range []uint16{ + 0x8c00, 0x8c02, 0x8c04, 0x8c06, 0x8c08, 0x8c0e, + 0x8c01, 0x8c03, 0x8c05, 0x8c07, 0x8c09, 0x8c0f, + 0x9c03, 0x9c05, 0x9c07, 0x9c0f, + } { + RegisterPCI(0x8086, id, GenericPCI{}) + } + + /* EHCI */ + for _, id := range []uint16{ + 0x9c26, 0x8c26, 0x8c2d, + } { + RegisterPCI(0x8086, id, GenericPCI{}) + } + + /* XHCI */ + RegisterPCI(0x8086, 0x8c31, GenericPCI{}) + RegisterPCI(0x8086, 0x9c31, GenericPCI{}) + + /* ME and children */ + for _, id := range []uint16{ + 0x8c3a, 0x8c3b, + } { + RegisterPCI(0x8086, id, GenericPCI{}) + } + + /* Ethernet */ + RegisterPCI(0x8086, 0x8c33, GenericPCI{}) +} diff --git a/util/autoport/main.go b/util/autoport/main.go index 05a829b..c1920a7 100644 --- a/util/autoport/main.go +++ b/util/autoport/main.go @@ -236,6 +236,12 @@ pcidev.ConfigDump[addr]) } +func RestoreDIRRoute(f *os.File, regname string, val uint16) { + fmt.Fprintf(f, " RCBA_SET_REG_16(%s, DIR_ROUTE(PIRQ%c, PIRQ%c, PIRQ%c, PIRQ%c)),\n", + regname, 'A' + (val & 7), 'A' + ((val >> 4) & 7), + 'A' + ((val >> 8) & 7), 'A' + ((val >> 12) & 7)) +} + func RestorePCI32Simple(f *os.File, pcidev PCIDevData, addr uint16) { fmt.Fprintf(f, " pci_write_config32(PCI_DEV(%d, 0x%02x, %d), 0x%02x, 0x%02x%02x%02x%02x);\n", pcidev.Bus, pcidev.Dev, pcidev.Func, addr, -- To view, visit https://review.coreboot.org/c/coreboot/+/30890 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f6e8c97b5122101de2f36bba8ba9f8ddd5b813a Gerrit-Change-Number: 30890 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-MessageType: newchange

2 days, 23 hours

9
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Change in coreboot[master]: [WIP] soc/amd/common: Use configure_scimap()

by Kyösti Mälkki (Code Review)

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43012 ) Change subject: [WIP] soc/amd/common: Use configure_scimap() ...................................................................... [WIP] soc/amd/common: Use configure_scimap() There is little point stashing the SCI trigger register configuration. Remove it to mase SCI and SMI programming more symmetrical. Change-Id: Ie23da79546858282910db65182a6315ade506279 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/common/block/gpio_banks/gpio.c 1 file changed, 12 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/43012/1 diff --git a/src/soc/amd/common/block/gpio_banks/gpio.c b/src/soc/amd/common/block/gpio_banks/gpio.c index 1bcfc8b..141d04f 100644 --- a/src/soc/amd/common/block/gpio_banks/gpio.c +++ b/src/soc/amd/common/block/gpio_banks/gpio.c @@ -40,12 +40,6 @@ configure_gevent_smi(gevent_num, SMI_MODE_SMI, level); } -struct sci_trigger_regs { - uint32_t mask; - uint32_t polarity; - uint32_t level; -}; - /* * For each general purpose event, GPE, the choice of edge/level triggered * event is represented as a single bit in SMI_SCI_LEVEL register. @@ -53,37 +47,24 @@ * In a similar fashion, polarity (rising/falling, hi/lo) of each GPE is * represented as a single bit in SMI_SCI_TRIG register. */ -static void fill_sci_trigger(uint32_t flags, int gpe, struct sci_trigger_regs *regs) +static void program_sci(uint32_t flags, int gevent_num) { - uint32_t mask = 1 << gpe; + struct sci_source sci; - regs->mask |= mask; + sci.scimap = gevent_num; + sci.gpe = gevent_num; if (is_gpio_event_level_triggered(flags)) - regs->level |= mask; + sci.level = SMI_SCI_LVL; else - regs->level &= ~mask; + sci.level = SMI_SCI_EDG; if (is_gpio_event_active_high(flags)) - regs->polarity |= mask; + sci.direction = SMI_SCI_LVL_HIGH; else - regs->polarity &= ~mask; -} + sci.direction = SMI_SCI_LVL_LOW; -/* TODO: See configure_scimap() implementations. */ -static void set_sci_trigger(const struct sci_trigger_regs *regs) -{ - uint32_t value; - - value = smi_read32(SMI_SCI_TRIG); - value &= ~regs->mask; - value |= regs->polarity; - smi_write32(SMI_SCI_TRIG, value); - - value = smi_read32(SMI_SCI_LEVEL); - value &= ~regs->mask; - value |= regs->level; - smi_write32(SMI_SCI_LEVEL, value); + configure_scimap(&sci); } uintptr_t gpio_get_address(gpio_t gpio_num) @@ -175,7 +156,7 @@ __weak void soc_gpio_hook(uint8_t gpio, uint8_t mux) {} -static void set_single_gpio(const struct soc_amd_gpio *g, struct sci_trigger_regs *sci_cfg) +static void set_single_gpio(const struct soc_amd_gpio *g) { static const struct soc_amd_event *gev_tbl; static size_t gev_items; @@ -206,14 +187,12 @@ if (g->flags & GPIO_FLAG_SMI) { program_smi(g->flags, gevent_num); } else if (g->flags & GPIO_FLAG_SCI) { - fill_sci_trigger(g->flags, gevent_num, sci_cfg); - soc_route_sci(gevent_num); + program_sci(g->flags, gevent_num); } } void program_gpios(const struct soc_amd_gpio *gpio_list_ptr, size_t size) { - struct sci_trigger_regs sci_trigger_cfg = { 0 }; size_t i; /* @@ -229,7 +208,7 @@ master_switch_clr(GPIO_MASK_STS_EN | GPIO_INTERRUPT_EN); for (i = 0; i < size; i++) - set_single_gpio(&gpio_list_ptr[i], &sci_trigger_cfg); + set_single_gpio(&gpio_list_ptr[i]); /* * Re-enable interrupt status generation. @@ -239,9 +218,6 @@ * to be missed during boot. */ master_switch_set(GPIO_INTERRUPT_EN); - - /* Set all SCI trigger polarity (high/low) and level (edge/level). */ - set_sci_trigger(&sci_trigger_cfg); } int gpio_interrupt_status(gpio_t gpio) -- To view, visit https://review.coreboot.org/c/coreboot/+/43012 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie23da79546858282910db65182a6315ade506279 Gerrit-Change-Number: 43012 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 days, 19 hours

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Change in coreboot[master]: herobrine : Provide initial mainboard support

by Ravi kumar (Code Review)

Ravi kumar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45206 ) Change subject: herobrine : Provide initial mainboard support ...................................................................... herobrine : Provide initial mainboard support Change-Id: I428cf1a461ee63215f5683abbfed90202d1b2a88 Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org> --- M payloads/libpayload/Kconfig A payloads/libpayload/configs/config.herobrine M payloads/libpayload/drivers/Makefile.inc A payloads/libpayload/drivers/serial/sc7280.c A src/mainboard/google/herobrine/Kconfig A src/mainboard/google/herobrine/Kconfig.name A src/mainboard/google/herobrine/Makefile.inc A src/mainboard/google/herobrine/board.h A src/mainboard/google/herobrine/board_info.txt A src/mainboard/google/herobrine/boardid.c A src/mainboard/google/herobrine/bootblock.c A src/mainboard/google/herobrine/chromeos.c A src/mainboard/google/herobrine/chromeos.fmd A src/mainboard/google/herobrine/devicetree.cb A src/mainboard/google/herobrine/mainboard.c A src/mainboard/google/herobrine/reset.c A src/mainboard/google/herobrine/romstage.c 17 files changed, 319 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/45206/1 diff --git a/payloads/libpayload/Kconfig b/payloads/libpayload/Kconfig index b5dc9a3..43ba6ab 100644 --- a/payloads/libpayload/Kconfig +++ b/payloads/libpayload/Kconfig @@ -256,6 +256,11 @@ depends on SERIAL_CONSOLE default n +config SC7280_SERIAL_CONSOLE + bool "SC7280 SOC compatible serial port driver" + depends on SERIAL_CONSOLE + default n + config QUALCOMM_QUPV3_SERIAL_CONSOLE bool "Qualcomm QUPV3 serial port driver" depends on SERIAL_CONSOLE diff --git a/payloads/libpayload/configs/config.herobrine b/payloads/libpayload/configs/config.herobrine new file mode 100644 index 0000000..a9d576a --- /dev/null +++ b/payloads/libpayload/configs/config.herobrine @@ -0,0 +1,5 @@ +CONFIG_LP_CHROMEOS=y +CONFIG_LP_ARCH_ARM64=y +CONFIG_LP_TIMER_ARM64_ARCH=y +CONFIG_LP_SERIAL_CONSOLE=y +CONFIG_LP_SC7280_SERIAL_CONSOLE=y diff --git a/payloads/libpayload/drivers/Makefile.inc b/payloads/libpayload/drivers/Makefile.inc index c4f7bf6..6c54c49 100644 --- a/payloads/libpayload/drivers/Makefile.inc +++ b/payloads/libpayload/drivers/Makefile.inc @@ -42,6 +42,8 @@ libc-$(CONFIG_LP_PC_MOUSE) += i8042/mouse.c libc-$(CONFIG_LP_PC_I8042) += i8042/i8042.c +libc-$(CONFIG_LP_SC7280_SERIAL_CONSOLE) += serial/sc7280.c serial/serial.c + libc-$(CONFIG_LP_CBMEM_CONSOLE) += cbmem_console.c libc-$(CONFIG_LP_MOUSE_CURSOR) += mouse_cursor.c diff --git a/payloads/libpayload/drivers/serial/sc7280.c b/payloads/libpayload/drivers/serial/sc7280.c new file mode 100644 index 0000000..0d7f5cf --- /dev/null +++ b/payloads/libpayload/drivers/serial/sc7280.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <libpayload.h> + +/* For simplicity sake let's rely on coreboot initalizing the UART. */ +void serial_console_init(void) +{ + +} diff --git a/src/mainboard/google/herobrine/Kconfig b/src/mainboard/google/herobrine/Kconfig new file mode 100644 index 0000000..92f77db --- /dev/null +++ b/src/mainboard/google/herobrine/Kconfig @@ -0,0 +1,55 @@ + +config BOARD_GOOGLE_HEROBRINE_COMMON # Umbrella option to be selected by variants + def_bool n + +if BOARD_GOOGLE_HEROBRINE_COMMON + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select COMMON_CBFS_SPI_WRAPPER + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_RTC + select EC_GOOGLE_CHROMEEC_SPI + select RTC + select SOC_QUALCOMM_SC7280 + select SPI_FLASH + select SPI_FLASH_WINBOND + select MAINBOARD_HAS_CHROMEOS + +config VBOOT + select EC_GOOGLE_CHROMEEC_SWITCHES + select VBOOT_VBNV_FLASH + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select VBOOT_MOCK_SECDATA + +config MAINBOARD_DIR + string + default "google/herobrine" + +config MAINBOARD_VENDOR + string + default "Google" + +config DRIVER_TPM_SPI_BUS + hex + default 0x5 + +config EC_GOOGLE_CHROMEEC_SPI_BUS + hex + default 0xa + +########################################################## +#### Update below when adding a new derivative board. #### +########################################################## + +config MAINBOARD_PART_NUMBER + string + default "Herobrine" if BOARD_GOOGLE_HEROBRINE + +config GBB_HWID + string + depends on CHROMEOS + default "HEROBRINE TEST 1859" if BOARD_GOOGLE_HEROBRINE + +endif # BOARD_GOOGLE_HEROBRINE_COMMON diff --git a/src/mainboard/google/herobrine/Kconfig.name b/src/mainboard/google/herobrine/Kconfig.name new file mode 100644 index 0000000..13dc56a --- /dev/null +++ b/src/mainboard/google/herobrine/Kconfig.name @@ -0,0 +1,4 @@ + +config BOARD_GOOGLE_HEROBRINE + bool "Herobrine" + select BOARD_GOOGLE_HEROBRINE_COMMON diff --git a/src/mainboard/google/herobrine/Makefile.inc b/src/mainboard/google/herobrine/Makefile.inc new file mode 100644 index 0000000..949d775 --- /dev/null +++ b/src/mainboard/google/herobrine/Makefile.inc @@ -0,0 +1,20 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += boardid.c +bootblock-y += chromeos.c +bootblock-y += bootblock.c +bootblock-y += reset.c + +verstage-y += boardid.c +verstage-y += chromeos.c +verstage-y += reset.c + +romstage-y += boardid.c +romstage-y += chromeos.c +romstage-y += romstage.c +romstage-y += reset.c + +ramstage-y += boardid.c +ramstage-y += chromeos.c +ramstage-y += mainboard.c +ramstage-y += reset.c diff --git a/src/mainboard/google/herobrine/board.h b/src/mainboard/google/herobrine/board.h new file mode 100644 index 0000000..c69d5d2 --- /dev/null +++ b/src/mainboard/google/herobrine/board.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _COREBOOT_SRC_MAINBOARD_GOOGLE_TROGDOR_BOARD_H_ +#define _COREBOOT_SRC_MAINBOARD_GOOGLE_TROGDOR_BOARD_H_ + +#include <boardid.h> +#include <gpio.h> +#include <soc/gpio.h> + +#define GPIO_EC_IN_RW GPIO(118) +#define GPIO_AP_EC_INT GPIO(94) +#define GPIO_AP_SUSPEND GPIO(20) +#define GPIO_WP_STATE GPIO(42) +#define GPIO_H1_AP_INT (CONFIG(TROGDOR_REV0) ? GPIO(21) : GPIO(42)) +#define GPIO_SD_CD_L GPIO(69) +#define GPIO_AMP_ENABLE GPIO(23) + +/* Display specific GPIOS */ +#define GPIO_BACKLIGHT_ENABLE GPIO(12) +#define GPIO_EDP_BRIDGE_ENABLE (CONFIG(TROGDOR_REV0) ? GPIO(14) : GPIO(104)) +#define GPIO_EN_PP3300_DX_EDP (CONFIG(TROGDOR_REV0) ? GPIO(106) : GPIO(30)) + +void setup_chromeos_gpios(void); + +#endif /* _COREBOOT_SRC_MAINBOARD_GOOGLE_TROGDOR_BOARD_H_ */ diff --git a/src/mainboard/google/herobrine/board_info.txt b/src/mainboard/google/herobrine/board_info.txt new file mode 100644 index 0000000..a670d6e --- /dev/null +++ b/src/mainboard/google/herobrine/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Herobrine Qualcomm sc7280 reference board +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/herobrine/boardid.c b/src/mainboard/google/herobrine/boardid.c new file mode 100644 index 0000000..7ff648e --- /dev/null +++ b/src/mainboard/google/herobrine/boardid.c @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <boardid.h> +#include <gpio.h> + +uint32_t board_id(void) +{ + static uint32_t id = UNDEFINED_STRAPPING_ID; +#if 0 + /* TODO: update gpios for Herobrine */ + const gpio_t pins[] = {[2] = GPIO(31), [1] = GPIO(93), [0] = GPIO(33)}; + + if (id == UNDEFINED_STRAPPING_ID) + id = gpio_base2_value(pins, ARRAY_SIZE(pins)); +#endif + return id; +} + +uint32_t ram_code(void) +{ + static uint32_t id = UNDEFINED_STRAPPING_ID; +#if 0 + /* TODO: update gpios for Herobrine */ + const gpio_t pins[] = {[2] = GPIO(13), [1] = GPIO(19), [0] = GPIO(29)}; + + if (id == UNDEFINED_STRAPPING_ID) + id = gpio_base2_value(pins, ARRAY_SIZE(pins)); +#endif + return id; +} + +uint32_t sku_id(void) +{ + static uint32_t id = UNDEFINED_STRAPPING_ID; +#if 0 + /* TODO: update gpios for Herobrine */ + const gpio_t pins[] = {[2] = GPIO(20), [1] = GPIO(90), [0] = GPIO(105)}; + + if (id == UNDEFINED_STRAPPING_ID) + id = gpio_base2_value(pins, ARRAY_SIZE(pins)); +#endif + return id; +} diff --git a/src/mainboard/google/herobrine/bootblock.c b/src/mainboard/google/herobrine/bootblock.c new file mode 100644 index 0000000..05e53a6 --- /dev/null +++ b/src/mainboard/google/herobrine/bootblock.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include "board.h" + +void bootblock_mainboard_init(void) +{ + setup_chromeos_gpios(); +} diff --git a/src/mainboard/google/herobrine/chromeos.c b/src/mainboard/google/herobrine/chromeos.c new file mode 100644 index 0000000..dba1c09 --- /dev/null +++ b/src/mainboard/google/herobrine/chromeos.c @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <boot/coreboot_tables.h> +#include <bootmode.h> +#include "board.h" + +int get_write_protect_state(void) +{ +#if 0 + return !gpio_get(GPIO_WP_STATE); +#else + return 0; +#endif +} + +void setup_chromeos_gpios(void) +{ +#if 0 + /* Example of what needs to be done here */ + gpio_input_pullup(GPIO_EC_IN_RW); + gpio_input_pullup(GPIO_AP_EC_INT); + gpio_input_pullup(GPIO_SD_CD_L); + gpio_input_irq(GPIO_H1_AP_INT, IRQ_TYPE_RISING_EDGE, GPIO_PULL_UP); + gpio_output(GPIO_AMP_ENABLE, 0); +#endif +} + +void fill_lb_gpios(struct lb_gpios *gpios) +{ +#if 0 + /* Example of what needs to be done here */ + struct lb_gpio chromeos_gpios[] = { + {GPIO_EC_IN_RW.addr, ACTIVE_LOW, gpio_get(GPIO_EC_IN_RW), + "EC in RW"}, + {GPIO_AP_EC_INT.addr, ACTIVE_LOW, gpio_get(GPIO_AP_EC_INT), + "EC interrupt"}, + {GPIO_H1_AP_INT.addr, ACTIVE_LOW, gpio_get(GPIO_H1_AP_INT), + "TPM interrupt"}, + {GPIO_SD_CD_L.addr, ACTIVE_LOW, gpio_get(GPIO_SD_CD_L), + "SD card detect"}, + {GPIO_AMP_ENABLE.addr, ACTIVE_HIGH, gpio_get(GPIO_AMP_ENABLE), + "speaker enable"}, + }; + + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); +#endif +} diff --git a/src/mainboard/google/herobrine/chromeos.fmd b/src/mainboard/google/herobrine/chromeos.fmd new file mode 100644 index 0000000..a44a638 --- /dev/null +++ b/src/mainboard/google/herobrine/chromeos.fmd @@ -0,0 +1,41 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# TODO: update for Herobrine +FLASH@0x0 8M { + WP_RO 4M { + RO_SECTION 0x3c4000 { + BOOTBLOCK 96K + COREBOOT(CBFS) + FMAP@0x3c0000 0x1000 + GBB 0x2f00 + RO_FRID 0x100 + } + RO_VPD(PRESERVE) 228K + RO_DDR_TRAINING(PRESERVE) 8K + RO_LIMITS_CFG(PRESERVE) 4K + } + + RW_VPD(PRESERVE) 32K + RW_NVRAM(PRESERVE) 16K + RW_DDR_TRAINING(PRESERVE) 8K + RW_LIMITS_CFG(PRESERVE) 4K + RW_ELOG(PRESERVE) 4K + RW_SHARED 4K { + SHARED_DATA + } + + RW_SECTION_A 1280K { + VBLOCK_A 8K + FW_MAIN_A(CBFS) + RW_FWID_A 256 + } + + + RW_SECTION_B 1280K { + VBLOCK_B 8K + FW_MAIN_B(CBFS) + RW_FWID_B 256 + } + + RW_LEGACY(CBFS) +} diff --git a/src/mainboard/google/herobrine/devicetree.cb b/src/mainboard/google/herobrine/devicetree.cb new file mode 100644 index 0000000..e23782f --- /dev/null +++ b/src/mainboard/google/herobrine/devicetree.cb @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip soc/qualcomm/sc7280 + device cpu_cluster 0 on end +end diff --git a/src/mainboard/google/herobrine/mainboard.c b/src/mainboard/google/herobrine/mainboard.c new file mode 100644 index 0000000..31deb77 --- /dev/null +++ b/src/mainboard/google/herobrine/mainboard.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <bootblock_common.h> +#include <arch/mmio.h> +#include <gpio.h> +#include <timestamp.h> + +static void mainboard_init(struct device *dev) +{ + +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = &mainboard_init; +} + +struct chip_operations mainboard_ops = { + .name = CONFIG_MAINBOARD_PART_NUMBER, + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/google/herobrine/reset.c b/src/mainboard/google/herobrine/reset.c new file mode 100644 index 0000000..9b5810f --- /dev/null +++ b/src/mainboard/google/herobrine/reset.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <ec/google/chromeec/ec.h> +#include <reset.h> + +/* Can't do a "real" reset before the PMIC is initialized in QcLib (romstage), + but this works well enough for our purposes. */ +void do_board_reset(void) +{ + google_chromeec_reboot(0, EC_REBOOT_COLD, 0); +} diff --git a/src/mainboard/google/herobrine/romstage.c b/src/mainboard/google/herobrine/romstage.c new file mode 100644 index 0000000..8844f18 --- /dev/null +++ b/src/mainboard/google/herobrine/romstage.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/stages.h> +#include <soc/qclib_common.h> + +void platform_romstage_main(void) +{ + /* QCLib: DDR init & train */ + qclib_load_and_run(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/45206 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I428cf1a461ee63215f5683abbfed90202d1b2a88 Gerrit-Change-Number: 45206 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sc7280: Provide initial SoC support

by Ravi kumar (Code Review)

Hello mturney mturney, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45205 to review the following change. Change subject: sc7280: Provide initial SoC support ...................................................................... sc7280: Provide initial SoC support Change-Id: I1fc841b3113f2bf79b8376cd1ccdb671c53c2084 Signed-off-by: T Michael Turney <mturney(a)codeaurora.org> --- M Documentation/soc/qualcomm/index.md A Documentation/soc/qualcomm/sc7280/index.md A src/soc/qualcomm/sc7280/Kconfig A src/soc/qualcomm/sc7280/Makefile.inc A src/soc/qualcomm/sc7280/bootblock.c A src/soc/qualcomm/sc7280/cbmem.c A src/soc/qualcomm/sc7280/include/soc/addressmap.h A src/soc/qualcomm/sc7280/include/soc/gpio.h A src/soc/qualcomm/sc7280/include/soc/mmu.h A src/soc/qualcomm/sc7280/include/soc/symbols.h A src/soc/qualcomm/sc7280/memlayout.ld A src/soc/qualcomm/sc7280/mmu.c A src/soc/qualcomm/sc7280/qclib.c A src/soc/qualcomm/sc7280/soc.c A src/soc/qualcomm/sc7280/spi.c A src/soc/qualcomm/sc7280/timer.c 16 files changed, 319 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/45205/1 diff --git a/Documentation/soc/qualcomm/index.md b/Documentation/soc/qualcomm/index.md index 5cd7981..d177c0e 100644 --- a/Documentation/soc/qualcomm/index.md +++ b/Documentation/soc/qualcomm/index.md @@ -5,3 +5,4 @@ ## Platforms - [SC7180 series](sc7180/index.md) +- [SC7280 series](sc7280/index.md) diff --git a/Documentation/soc/qualcomm/sc7280/index.md b/Documentation/soc/qualcomm/sc7280/index.md new file mode 100644 index 0000000..9dad39c --- /dev/null +++ b/Documentation/soc/qualcomm/sc7280/index.md @@ -0,0 +1,19 @@ +# Qualcomm SC7280 documentation + +## SOC code + +The SOC folder contains functions for: +* MMU +* CLOCK +* GPIO +* QUPv3 FW (provides a bridge to serial interfaces) +* UART +* SPI-NOR +* AOP FW +* USB + +## Notes about the hardware + +The timer is used from the ARMv8 architecture specific code. + + diff --git a/src/soc/qualcomm/sc7280/Kconfig b/src/soc/qualcomm/sc7280/Kconfig new file mode 100644 index 0000000..fc2f34b --- /dev/null +++ b/src/soc/qualcomm/sc7280/Kconfig @@ -0,0 +1,27 @@ + +config SOC_QUALCOMM_SC7280 + bool + default n + select ARCH_BOOTBLOCK_ARMV8_64 + select ARCH_RAMSTAGE_ARMV8_64 + select ARCH_ROMSTAGE_ARMV8_64 + select ARCH_VERSTAGE_ARMV8_64 + select GENERIC_GPIO_LIB + select GENERIC_UDELAY + select HAVE_MONOTONIC_TIMER + select ARM64_USE_ARCH_TIMER + select SOC_QUALCOMM_COMMON + +if SOC_QUALCOMM_SC7280 + +config MEMLAYOUT_LD_FILE + string + default "src/soc/qualcomm/sc7280/memlayout.ld" + +config VBOOT + select VBOOT_SEPARATE_VERSTAGE + select VBOOT_RETURN_FROM_VERSTAGE + select VBOOT_MUST_REQUEST_DISPLAY + select VBOOT_STARTS_IN_BOOTBLOCK + +endif diff --git a/src/soc/qualcomm/sc7280/Makefile.inc b/src/soc/qualcomm/sc7280/Makefile.inc new file mode 100644 index 0000000..2bed326 --- /dev/null +++ b/src/soc/qualcomm/sc7280/Makefile.inc @@ -0,0 +1,36 @@ + +ifeq ($(CONFIG_SOC_QUALCOMM_SC7280),y) + +################################################################################ +bootblock-y += bootblock.c +bootblock-y += mmu.c +bootblock-y += timer.c +bootblock-y += spi.c + +################################################################################ +verstage-y += timer.c +verstage-y += spi.c + +################################################################################ +romstage-y += cbmem.c +romstage-y += timer.c +romstage-y += ../common/qclib.c +romstage-y += qclib.c +romstage-y += ../common/mmu.c +romstage-y += mmu.c +romstage-y += spi.c + +################################################################################ +ramstage-y += soc.c +ramstage-y += cbmem.c +ramstage-y += timer.c +ramstage-y += spi.c + +################################################################################ + +CPPFLAGS_common += -Isrc/soc/qualcomm/sc7280/include +CPPFLAGS_common += -Isrc/soc/qualcomm/common/include + +################################################################################ + +endif diff --git a/src/soc/qualcomm/sc7280/bootblock.c b/src/soc/qualcomm/sc7280/bootblock.c new file mode 100644 index 0000000..807bb25 --- /dev/null +++ b/src/soc/qualcomm/sc7280/bootblock.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <soc/mmu.h> + +void bootblock_soc_init(void) +{ + sc7280_mmu_init(); +} diff --git a/src/soc/qualcomm/sc7280/cbmem.c b/src/soc/qualcomm/sc7280/cbmem.c new file mode 100644 index 0000000..4b9eb37 --- /dev/null +++ b/src/soc/qualcomm/sc7280/cbmem.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cbmem.h> + +void *cbmem_top_chipset(void) +{ + return (void *)((uintptr_t)4 * GiB); +} diff --git a/src/soc/qualcomm/sc7280/include/soc/addressmap.h b/src/soc/qualcomm/sc7280/include/soc/addressmap.h new file mode 100644 index 0000000..70d17be --- /dev/null +++ b/src/soc/qualcomm/sc7280/include/soc/addressmap.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_QUALCOMM_SC7280_ADDRESS_MAP_H_ +#define _SOC_QUALCOMM_SC7280_ADDRESS_MAP_H_ + +#include <stdint.h> + +#endif /* __SOC_QUALCOMM_SC7280_ADDRESS_MAP_H__ */ diff --git a/src/soc/qualcomm/sc7280/include/soc/gpio.h b/src/soc/qualcomm/sc7280/include/soc/gpio.h new file mode 100644 index 0000000..82a0c39 --- /dev/null +++ b/src/soc/qualcomm/sc7280/include/soc/gpio.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_QUALCOMM_SC7280_GPIO_H_ +#define _SOC_QUALCOMM_SC7280_GPIO_H_ + +#include <types.h> + +typedef struct { + u32 addr; +} gpio_t; + +#endif /* _SOC_QUALCOMM_SC7280_GPIO_H_ */ diff --git a/src/soc/qualcomm/sc7280/include/soc/mmu.h b/src/soc/qualcomm/sc7280/include/soc/mmu.h new file mode 100644 index 0000000..5a2984f --- /dev/null +++ b/src/soc/qualcomm/sc7280/include/soc/mmu.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_QUALCOMM_SC7280_MMU_H_ +#define _SOC_QUALCOMM_SC7280_MMU_H_ + +void sc7280_mmu_init(void); + +#endif /* _SOC_QUALCOMM_SC7280_MMU_H_ */ diff --git a/src/soc/qualcomm/sc7280/include/soc/symbols.h b/src/soc/qualcomm/sc7280/include/soc/symbols.h new file mode 100644 index 0000000..e930638 --- /dev/null +++ b/src/soc/qualcomm/sc7280/include/soc/symbols.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_QUALCOMM_SC7280_SYMBOLS_H_ +#define _SOC_QUALCOMM_SC7280_SYMBOLS_H_ + +#include <symbols.h> + +DECLARE_REGION(ssram) +DECLARE_REGION(bsram) +DECLARE_REGION(dram_aop) +DECLARE_REGION(dram_soc) +DECLARE_REGION(dcb) +DECLARE_REGION(pmic) +DECLARE_REGION(limits_cfg) +DECLARE_REGION(aop) + +#endif /* _SOC_QUALCOMM_SC7280_SYMBOLS_H_ */ diff --git a/src/soc/qualcomm/sc7280/memlayout.ld b/src/soc/qualcomm/sc7280/memlayout.ld new file mode 100644 index 0000000..94300e8 --- /dev/null +++ b/src/soc/qualcomm/sc7280/memlayout.ld @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <memlayout.h> +#include <arch/header.ld> + +/* SYSTEM_IMEM : 0x14680000 - 0x146AE000 */ +#define SSRAM_START(addr) SYMBOL(ssram, addr) +#define SSRAM_END(addr) SYMBOL(essram, addr) + +/* BOOT_IMEM : 0x14800000 - 0x14980000 */ +#define BSRAM_START(addr) SYMBOL(bsram, addr) +#define BSRAM_END(addr) SYMBOL(ebsram, addr) + +/* AOP : 0x0B000000 - 0x0B100000 */ +#define AOPSRAM_START(addr) SYMBOL(aopsram, addr) +#define AOPSRAM_END(addr) SYMBOL(eaopsram, addr) + +SECTIONS +{ + AOPSRAM_START(0x0B000000) + REGION(aop, 0x0B000000, 0x100000, 4096) + AOPSRAM_END(0x0B100000) + + SSRAM_START(0x14680000) + OVERLAP_VERSTAGE_ROMSTAGE(0x14680000, 100K) + REGION(qcsdi, 0x14699000, 52K, 4K) + SSRAM_END(0x146AE000) + + BSRAM_START(0x14800000) + REGION(pbl_timestamps, 0x14800000, 84K, 4K) + BOOTBLOCK(0x14815000, 40K) + PRERAM_CBFS_CACHE(0x1481F000, 70K) + PRERAM_CBMEM_CONSOLE(0x14830800, 32K) + TIMESTAMP(0x14838800, 1K) + TTB(0x14839000, 56K) + STACK(0x14847000, 16K) + VBOOT2_WORK(0x1484B000, 12K) + DMA_COHERENT(0x1484E000, 8K) + REGION(ddr_training, 0x14850000, 8K, 4K) + REGION(qclib_serial_log, 0x14852000, 4K, 4K) + REGION(ddr_information, 0x14853000, 1K, 1K) + FMAP_CACHE(0x14853400, 2K) + REGION(dcb, 0x1485b000, 16K, 4K) + REGION(pmic, 0x1485f000, 44K, 4K) + REGION(limits_cfg, 0x1486a000, 4K, 4K) + REGION(qclib, 0x1486b000, 596K, 4K) + BSRAM_END(0x14900000) + + DRAM_START(0x80000000) + /* Various hardware/software subsystems make use of this area */ + REGION(dram_aop, 0x80800000, 0x040000, 0x1000) + REGION(dram_soc, 0x80900000, 0x200000, 0x1000) + BL31(0x80B00000, 1M) + POSTRAM_CBFS_CACHE(0x9F800000, 16M) + RAMSTAGE(0xA0800000, 16M) +} diff --git a/src/soc/qualcomm/sc7280/mmu.c b/src/soc/qualcomm/sc7280/mmu.c new file mode 100644 index 0000000..9905c29 --- /dev/null +++ b/src/soc/qualcomm/sc7280/mmu.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <symbols.h> +#include <arch/mmu.h> +#include <arch/cache.h> +#include <soc/mmu.h> +#include <soc/mmu_common.h> +#include <soc/symbols.h> + +void sc7280_mmu_init(void) +{ + mmu_init(); + + mmu_config_range((void *)(4 * KiB), ((4UL * GiB) - (4 * KiB)), DEV_MEM); + mmu_config_range((void *)_ssram, REGION_SIZE(ssram), CACHED_RAM); + mmu_config_range((void *)_bsram, REGION_SIZE(bsram), CACHED_RAM); + mmu_config_range((void *)_dma_coherent, REGION_SIZE(dma_coherent), + UNCACHED_RAM); + + mmu_enable(); +} diff --git a/src/soc/qualcomm/sc7280/qclib.c b/src/soc/qualcomm/sc7280/qclib.c new file mode 100644 index 0000000..6affc63 --- /dev/null +++ b/src/soc/qualcomm/sc7280/qclib.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cbfs.h> +#include <fmap.h> +#include <console/console.h> +#include <soc/symbols.h> +#include <soc/qclib_common.h> + +int qclib_soc_blob_load(void) +{ + size_t size; + ssize_t ssize; + + /* Attempt to load PMICCFG Blob */ + size = cbfs_boot_load_file(CONFIG_CBFS_PREFIX "/pmiccfg", + _pmic, REGION_SIZE(pmic), CBFS_TYPE_RAW); + if (!size) + return -1; + qclib_add_if_table_entry(QCLIB_TE_PMIC_SETTINGS, _pmic, size, 0); + + /* Attempt to load DCB Blob */ + size = cbfs_boot_load_file(CONFIG_CBFS_PREFIX "/dcb", + _dcb, REGION_SIZE(dcb), CBFS_TYPE_RAW); + if (!size) + return -1; + qclib_add_if_table_entry(QCLIB_TE_DCB_SETTINGS, _dcb, size, 0); + + /* Attempt to load Limits Config Blob */ + ssize = fmap_read_area(QCLIB_FR_LIMITS_CFG_DATA, _limits_cfg, + REGION_SIZE(limits_cfg)); + if (ssize < 0) + return -1; + qclib_add_if_table_entry(QCLIB_TE_LIMITS_CFG_DATA, + _limits_cfg, ssize, 0); + + return 0; +} diff --git a/src/soc/qualcomm/sc7280/soc.c b/src/soc/qualcomm/sc7280/soc.c new file mode 100644 index 0000000..7233d38 --- /dev/null +++ b/src/soc/qualcomm/sc7280/soc.c @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <symbols.h> +#include <device/device.h> +#include <soc/mmu.h> +#include <soc/mmu_common.h> +#include <soc/symbols.h> + +static void soc_read_resources(struct device *dev) +{ + ram_resource(dev, 0, (uintptr_t)ddr_region->offset / KiB, + ddr_region->size / KiB); + reserved_ram_resource(dev, 1, (uintptr_t)_dram_soc / KiB, + REGION_SIZE(dram_soc) / KiB); +} + +static void soc_init(struct device *dev) +{ +} + +static struct device_operations soc_ops = { + .read_resources = soc_read_resources, + .init = soc_init, +}; + +static void enable_soc_dev(struct device *dev) +{ + dev->ops = &soc_ops; +} + +struct chip_operations soc_qualcomm_sc7280_ops = { + CHIP_NAME("SOC Qualcomm SC7280") + .enable_dev = enable_soc_dev, +}; diff --git a/src/soc/qualcomm/sc7280/spi.c b/src/soc/qualcomm/sc7280/spi.c new file mode 100644 index 0000000..50aa395 --- /dev/null +++ b/src/soc/qualcomm/sc7280/spi.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <spi-generic.h> +#include <spi_flash.h> + +static const struct spi_ctrlr spi_ctrlr; + +const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { + { + .ctrlr = &spi_ctrlr, + .bus_start = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, + .bus_end = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, + }, +}; + +const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); diff --git a/src/soc/qualcomm/sc7280/timer.c b/src/soc/qualcomm/sc7280/timer.c new file mode 100644 index 0000000..19e466a --- /dev/null +++ b/src/soc/qualcomm/sc7280/timer.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <delay.h> +#include <arch/lib_helpers.h> +#include <commonlib/helpers.h> + +void init_timer(void) +{ + raw_write_cntfrq_el0(19200*KHz); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/45205 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fc841b3113f2bf79b8376cd1ccdb671c53c2084 Gerrit-Change-Number: 45205 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/i2c/tas5825m: Add driver for TI TAS5825M amplifier

by Jeremy Soller (Code Review)

Jeremy Soller has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43614 ) Change subject: drivers/i2c/tas5825m: Add driver for TI TAS5825M amplifier ...................................................................... drivers/i2c/tas5825m: Add driver for TI TAS5825M amplifier This adds a driver for the TI TAS5825M, documentation can be found here: https://www.ti.com/product/TAS5825M This driver expects the mainboard using it to define tas5825m_setup, which uses the tas5825m_* functions to set configuration data. Each mainboard may have very different configuration data, depending on its audio hardware. Tested on system76/addw2 and system76/oryp6, which will be added in a future patch. Signed-off-by: Jeremy Soller <jeremy(a)system76.com> Change-Id: I896e8f272f18e64bfc90f406e7d4163010800aaf --- A src/drivers/i2c/tas5825m/Kconfig A src/drivers/i2c/tas5825m/Makefile.inc A src/drivers/i2c/tas5825m/tas5825m.c A src/drivers/i2c/tas5825m/tas5825m.h 4 files changed, 81 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/43614/1 diff --git a/src/drivers/i2c/tas5825m/Kconfig b/src/drivers/i2c/tas5825m/Kconfig new file mode 100644 index 0000000..0deca17 --- /dev/null +++ b/src/drivers/i2c/tas5825m/Kconfig @@ -0,0 +1,5 @@ +config DRIVERS_I2C_TAS5825M + bool + default n + help + Enable support for TI TAS5825M Amplifier. diff --git a/src/drivers/i2c/tas5825m/Makefile.inc b/src/drivers/i2c/tas5825m/Makefile.inc new file mode 100644 index 0000000..909ffdb --- /dev/null +++ b/src/drivers/i2c/tas5825m/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_I2C_TAS5825M) += tas5825m.c diff --git a/src/drivers/i2c/tas5825m/tas5825m.c b/src/drivers/i2c/tas5825m/tas5825m.c new file mode 100644 index 0000000..2970a8ee --- /dev/null +++ b/src/drivers/i2c/tas5825m/tas5825m.c @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <device/smbus.h> +#include <device/pci.h> +#include "tas5825m.h" + +int tas5825m_write_at(struct device *dev, uint8_t addr, uint8_t value) { + return smbus_write_byte(dev, addr, value); +} + +//TODO: use I2C block write for better performance +int tas5825m_write_block_at(struct device *dev, uint8_t addr, const uint8_t * values, uint8_t length) { + int res = 0; + for (uint8_t i = 0; i < length; i++) { + res = smbus_write_byte(dev, addr + i, values[i]); + if (res < 0) return res; + } + return (int)length; +} + +int tas5825m_set_page(struct device *dev, uint8_t page) { + return tas5825m_write_at(dev, 0x00, page); +} + +int tas5825m_set_book(struct device *dev, uint8_t book) { + int res = tas5825m_set_page(dev, 0x00); + if (res < 0) return res; + return tas5825m_write_at(dev, 0x7F, book); +} + +__weak int tas5825m_setup(struct device *dev) { + printk(BIOS_ERR, "tas5825m: setup not implemented\n"); + return -1; +} + +static void tas5825m_init(struct device *dev) { + if (dev->enabled && dev->path.type == DEVICE_PATH_I2C && + ops_smbus_bus(get_pbus_smbus(dev))) { + printk(BIOS_DEBUG, "tas5825m at %s\n", dev_path(dev)); + int res = tas5825m_setup(dev); + if (res) { + printk(BIOS_ERR, "tas5825m init failed: %d\n", res); + } else { + printk(BIOS_DEBUG, "tas5825m init successful\n"); + } + } +} + +static struct device_operations tas5825m_operations = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .init = tas5825m_init, +}; + +static void tas5825m_enable_dev(struct device *dev) { + dev->ops = &tas5825m_operations; +} + +struct chip_operations drivers_i2c_tas5825m_ops = { + CHIP_NAME("TI TAS5825M Amplifier") + .enable_dev = tas5825m_enable_dev, +}; diff --git a/src/drivers/i2c/tas5825m/tas5825m.h b/src/drivers/i2c/tas5825m/tas5825m.h new file mode 100644 index 0000000..c58f86a --- /dev/null +++ b/src/drivers/i2c/tas5825m/tas5825m.h @@ -0,0 +1,12 @@ +#ifndef TAS5825M_H +#define TAS5825M_H + +#include <device/device.h> + +int tas5825m_write_at(struct device *dev, uint8_t addr, uint8_t value); +int tas5825m_write_block_at(struct device *dev, uint8_t addr, const uint8_t * values, uint8_t length); +int tas5825m_set_page(struct device *dev, uint8_t page); +int tas5825m_set_book(struct device *dev, uint8_t book); +int tas5825m_setup(struct device *dev); + +#endif // TAS5825M_H -- To view, visit https://review.coreboot.org/c/coreboot/+/43614 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I896e8f272f18e64bfc90f406e7d4163010800aaf Gerrit-Change-Number: 43614 Gerrit-PatchSet: 1 Gerrit-Owner: Jeremy Soller <jeremy(a)system76.com> Gerrit-MessageType: newchange

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coreboot-gerrit September 2020