coreboot-gerrit September 2020

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Change in coreboot[master]: soc/intel/common/block: Update microcode for each core

by Patrick Rudolph (Code Review)

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35739 ) Change subject: soc/intel/common/block: Update microcode for each core ...................................................................... soc/intel/common/block: Update microcode for each core On Hyper-Threading enabled platform update the microcde only once for each core, not for each thread. Follow Intel Software Developer Guidelines as the added comment also states. Change-Id: I72804753e567a137a5648ca6950009fed332531b Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/common/block/cpu/mp_init.c 1 file changed, 20 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/35739/1 diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index 2c5061f..e7689cf 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -26,6 +26,7 @@ #include <intelblocks/fast_spi.h> #include <intelblocks/mp_init.h> #include <intelblocks/msr.h> +#include <cpu/intel/common/common.h> #include <soc/cpu.h> static const void *microcode_patch; @@ -44,7 +45,24 @@ static void init_one_cpu(struct device *dev) { soc_core_init(dev); - intel_microcode_load_unlocked(microcode_patch); + + /* + * Update just on the first CPU in the core. Other siblings + * get the update automatically according to Document: 253668-060US + * Intel SDM Chapter 9.11.6.3 + * "Update in a System Supporting Intel Hyper-Threading Technology" + * Intel Hyper-Threading Technology has implications on the loading of the + * microcode update. The update must be loaded for each core in a physical + * processor. Thus, for a processor supporting Intel Hyper-Threading + * Technology, only one logical processor per core is required to load the + * microcode update. Each individual logical processor can independently + * load the update. However, MP initialization must provide some mechanism + * (e.g. a software semaphore) to force serialization of microcode update + * loads and to prevent simultaneous load attempts to the same core. + */ + if (!intel_ht_sibling()) { + intel_microcode_load_unlocked(microcode_patch); + } } static struct device_operations cpu_dev_ops = { @@ -141,6 +159,7 @@ if (CONFIG(USE_INTEL_FSP_MP_INIT)) return; + /* Update microcode on BSP */ microcode_patch = intel_microcode_find(); intel_microcode_load_unlocked(microcode_patch); -- To view, visit https://review.coreboot.org/c/coreboot/+/35739 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72804753e567a137a5648ca6950009fed332531b Gerrit-Change-Number: 35739 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

8 hours, 19 minutes

Change in coreboot[master]: nb/intel/pineview: Use new mchbar{8,16,32}_and_or()

by HAOUAS Elyes (Code Review)

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45517 ) Change subject: nb/intel/pineview: Use new mchbar{8,16,32}_and_or() ...................................................................... nb/intel/pineview: Use new mchbar{8,16,32}_and_or() Change-Id: I5fa844a8a13a75d6d802ca48f72c513bfa16d0a5 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- A src/northbridge/intel/common/mchbar_ops.c A src/northbridge/intel/common/mchbar_ops.h M src/northbridge/intel/pineview/Makefile.inc M src/northbridge/intel/pineview/early_init.c M src/northbridge/intel/pineview/pineview.h M src/northbridge/intel/pineview/raminit.c 6 files changed, 417 insertions(+), 344 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/45517/1 diff --git a/src/northbridge/intel/common/mchbar_ops.c b/src/northbridge/intel/common/mchbar_ops.c new file mode 100644 index 0000000..c3fccad --- /dev/null +++ b/src/northbridge/intel/common/mchbar_ops.c @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <stdint.h> +#include "mchbar_ops.h" + +void mchbar8_and_or(int offset, u8 mask, u8 or) +{ + u8 reg8 = MCHBAR8(offset); + + reg8 &= mask; + reg8 |= or; + MCHBAR8(offset) = reg8; +} + +void mchbar16_and_or(int offset, u16 mask, u16 or) +{ + u16 reg16 = MCHBAR32(offset); + + reg16 &= mask; + reg16 |= or; + MCHBAR16(offset) = reg16; +} + +void mchbar32_and_or(int offset, u32 mask, u32 or) +{ + u32 reg32 = MCHBAR32(offset); + + reg32 &= mask; + reg32 |= or; + MCHBAR32(offset) = reg32; +} + +void mchbar8_and(int offset, u8 and) +{ + mchbar8_and_or(offset, and, 0); +} + +void mchbar16_and(int offset, u16 and) +{ + mchbar16_and_or(offset, and, 0); +} + +void mchbar32_and(int offset, u32 and) +{ + mchbar32_and_or(offset, and, 0); +} + +void mchbar8_or(int offset, u8 or) +{ + mchbar8_and_or(offset, 0xff, or); +} + +void mchbar16_or(int offset, u16 or) +{ + mchbar16_and_or(offset, 0xffff, or); +} + +void mchbar32_or(int offset, u32 or) +{ + mchbar32_and_or(offset, 0xffffffff, or); +} diff --git a/src/northbridge/intel/common/mchbar_ops.h b/src/northbridge/intel/common/mchbar_ops.h new file mode 100644 index 0000000..cf39c2b --- /dev/null +++ b/src/northbridge/intel/common/mchbar_ops.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MCHBAR_OPS_H +#define MCHBAR_OPS_H + +#include <stdint.h> +#include <northbridge/intel/pineview/memmap.h> + +#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + x))) +#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + x))) +#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + x))) + +void mchbar8_and_or(int offset, u8 mask, u8 or); +void mchbar16_and_or(int offset, u16 mask, u16 or); +void mchbar32_and_or(int offset, u32 mask, u32 or); +void mchbar8_and(int offset, u8 and); +void mchbar16_and(int offset, u16 and); +void mchbar32_and(int offset, u32 and); +void mchbar8_or(int offset, u8 or); +void mchbar16_or(int offset, u16 or); +void mchbar32_or(int offset, u32 or); + +#endif diff --git a/src/northbridge/intel/pineview/Makefile.inc b/src/northbridge/intel/pineview/Makefile.inc index 08e04f2..4ba902e 100644 --- a/src/northbridge/intel/pineview/Makefile.inc +++ b/src/northbridge/intel/pineview/Makefile.inc @@ -14,6 +14,7 @@ romstage-y += memmap.c romstage-y += raminit.c romstage-y += early_init.c +romstage-y += ../common/mchbar_ops.c postcar-y += memmap.c diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c index 42a68d8..ec7c575 100644 --- a/src/northbridge/intel/pineview/early_init.c +++ b/src/northbridge/intel/pineview/early_init.c @@ -3,6 +3,7 @@ #include <console/console.h> #include <device/pci_ops.h> #include <device/pci_def.h> +#include <northbridge/intel/common/mchbar_ops.h> #include <northbridge/intel/pineview/pineview.h> #include <northbridge/intel/pineview/chip.h> #include <option.h> @@ -67,10 +68,10 @@ if (config->use_crt) { /* Enable VGA */ - MCHBAR32_OR(DACGIOCTRL1, 1 << 15); + mchbar32_or(DACGIOCTRL1, 1 << 15); } else { /* Disable VGA */ - MCHBAR32_AND(DACGIOCTRL1, ~(1 << 15)); + mchbar32_and(DACGIOCTRL1, ~(1 << 15)); } if (config->use_lvds) { @@ -79,17 +80,17 @@ reg32 &= ~0xf1000000; reg32 |= 0x90000000; MCHBAR32(LVDSICR2) = reg32; - MCHBAR32_OR(IOCKTRR1, 1 << 9); + mchbar32_or(IOCKTRR1, 1 << 9); } else { /* Disable LVDS */ - MCHBAR32_OR(DACGIOCTRL1, 3 << 25); + mchbar32_or(DACGIOCTRL1, 3 << 25); } MCHBAR32(CICTRL) = 0xc6db8b5f; MCHBAR16(CISDCTRL) = 0x024f; - MCHBAR32_AND(DACGIOCTRL1, 0xffffff00); - MCHBAR32_OR(DACGIOCTRL1, 1 << 5); + mchbar32_and(DACGIOCTRL1, 0xffffff00); + mchbar32_or(DACGIOCTRL1, 1 << 5); /* Legacy backlight control */ pci_write_config8(GMCH_IGD, 0xf4, 0x4c); diff --git a/src/northbridge/intel/pineview/pineview.h b/src/northbridge/intel/pineview/pineview.h index 03fa318..121c65b 100644 --- a/src/northbridge/intel/pineview/pineview.h +++ b/src/northbridge/intel/pineview/pineview.h @@ -5,6 +5,7 @@ #include <northbridge/intel/pineview/memmap.h> #include <southbridge/intel/i82801gx/i82801gx.h> +#include <northbridge/intel/common/mchbar_ops.h> #define BOOT_PATH_NORMAL 0 #define BOOT_PATH_RESET 1 @@ -36,23 +37,8 @@ /* * MCHBAR + *As there are many registers, define them on a separate file */ - -#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + x))) /* FIXME: causes changes */ -#define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) -#define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) -#define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) -#define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or)) -#define MCHBAR16_OR(x, or) (MCHBAR16(x) = MCHBAR16(x) | (or)) -#define MCHBAR32_OR(x, or) (MCHBAR32(x) = MCHBAR32(x) | (or)) -#define MCHBAR8_AND_OR(x, and, or) (MCHBAR8(x) = (MCHBAR8(x) & (and)) | (or)) -#define MCHBAR16_AND_OR(x, and, or) (MCHBAR16(x) = (MCHBAR16(x) & (and)) | (or)) -#define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) - -/* As there are many registers, define them on a separate file */ - #include "mchbar_regs.h" /* diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index 43149be..b190781 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -8,6 +8,7 @@ #include <console/console.h> #include <delay.h> #include <lib.h> +#include <northbridge/intel/common/mchbar_ops.h> #include "pineview.h" #include "raminit.h" #include <spd.h> @@ -501,7 +502,7 @@ if (s->boot_path == BOOT_PATH_RESET) return; - MCHBAR32_OR(PMSTS, 1); + mchbar32_or(PMSTS, 1); reg32 = (MCHBAR32(CLKCFG) & ~0x70) | (1 << 10); if (s->selected_timings.mem_clock == MEM_CLOCK_800MHz) { @@ -566,7 +567,7 @@ MCHBAR32(HMCCPEXT) = 0; MCHBAR32(HMDCPEXT) = clkcross[fsb_freq][ddr_freq][3]; - MCHBAR32_OR(HMCCMC, 1 << 7); + mchbar32_or(HMCCMC, 1 << 7); if ((fsb_freq == 0) && (ddr_freq == 1)) { MCHBAR8(CLKXSSH2MCBYPPHAS) = 0; @@ -616,8 +617,8 @@ u8 ddr_freq; u16 mpll_ctl; - MCHBAR16_AND(CSHRMISCCTL1, ~(1 << 8)); - MCHBAR8_AND(CSHRMISCCTL1, ~0x3f); + mchbar16_and(CSHRMISCCTL1, (u16)~(1 << 8)); + mchbar8_and(CSHRMISCCTL1, (u8)~0x3f); if (s->selected_timings.mem_clock == MEM_CLOCK_667MHz) { ddr_freq = 0; @@ -627,10 +628,10 @@ mpll_ctl = (1 << 8) | (1 << 5); } if (s->boot_path != BOOT_PATH_RESET) - MCHBAR16_AND_OR(MPLLCTL, ~(0x033f), mpll_ctl); + mchbar16_and_or(MPLLCTL, (u16)~(0x033f), mpll_ctl); MCHBAR32(C0GNT2LNCH1) = 0x58001117; - MCHBAR32_OR(C0STATRDCTRL, 1 << 23); + mchbar32_or(C0STATRDCTRL, 1 << 23); const u32 cas_to_reg[2][4] = { {0x00000000, 0x00030100, 0x0C240201, 0x00000000}, /* DDR = 667 */ @@ -682,7 +683,7 @@ flag = 1; } - MCHBAR8_OR(C0PVCFG, 0x03); + mchbar8_or(C0PVCFG, 0x03); MCHBAR16(C0CYCTRKPCHG) = ((wl + 4 + s->selected_timings.tWR) << 6) | ((2 + MAX(s->selected_timings.tRTP, 2)) << 2) | 1; @@ -699,7 +700,7 @@ /* FIXME: Only applies to DDR2 */ reg16 = (MCHBAR16(C0CYCTRKACT + 2) & 0x0fc0) >> 6; - MCHBAR16_AND_OR(SHCYCTRKCKEL, ~0x1f80, (reg16 << 7)); + mchbar16_and_or(SHCYCTRKCKEL, (u16)~0x1f80, (reg16 << 7)); reg16 = (s->selected_timings.tRCD << 12) | (4 << 8) | (ta2 << 4) | ta4; MCHBAR16(C0CYCTRKWR) = reg16; @@ -714,10 +715,10 @@ MCHBAR8(C0CYCTRKREFR) = (u8) (reg16); MCHBAR8(C0CYCTRKREFR + 1) = (u8) (reg16 >> 8); - MCHBAR16_AND_OR(C0CKECTRL, ~0x03fe, 100 << 1); - MCHBAR8_AND_OR(C0CYCTRKPCHG2, ~0x3f, s->selected_timings.tRAS); + mchbar16_and_or(C0CKECTRL, (u16)~0x03fe, 100 << 1); + mchbar8_and_or(C0CYCTRKPCHG2, (u8)~0x3f, s->selected_timings.tRAS); MCHBAR16(C0ARBCTRL) = 0x2310; - MCHBAR8_AND_OR(C0ADDCSCTRL, ~0x1f, 1); + mchbar8_and_or(C0ADDCSCTRL, (u8)~0x1f, 1); if (s->selected_timings.mem_clock == MEM_CLOCK_667MHz) { reg32 = 3000; @@ -730,7 +731,7 @@ reg2 = 5000; } reg16 = (u16)((((s->selected_timings.CAS + 7) * (reg32)) / reg2) << 8); - MCHBAR16_AND_OR(C0STATRDCTRL, ~0x1f00, reg16); + mchbar16_and_or(C0STATRDCTRL, (u16)~0x1f00, reg16); flag = 0; if (wl > 2) { @@ -739,13 +740,13 @@ reg16 = (u8) (wl - 1 - flag); reg16 |= reg16 << 4; reg16 |= flag << 8; - MCHBAR16_AND_OR(C0WRDATACTRL, ~0x01ff, reg16); + mchbar16_and_or(C0WRDATACTRL, (u16)~0x01ff, reg16); MCHBAR16(C0RDQCTRL) = 0x1585; - MCHBAR8_AND(C0PWLRCTRL, ~0x1f); + mchbar8_and(C0PWLRCTRL, (u8)~0x1f); /* rdmodwr_window[5..0] = CL+4+5 265[13..8] (264[21..16]) */ - MCHBAR16_AND_OR(C0PWLRCTRL, ~0x3f00, (s->selected_timings.CAS + 9) << 8); + mchbar16_and_or(C0PWLRCTRL, (u16)~0x3f00, (s->selected_timings.CAS + 9) << 8); if (s->selected_timings.mem_clock == MEM_CLOCK_667MHz) { reg16 = 0x0514; @@ -754,115 +755,115 @@ reg16 = 0x0618; reg32 = 0x0c30; } - MCHBAR32_AND_OR(C0REFRCTRL2, ~0x0fffff00, (0x3f << 22) | (reg32 << 8)); + mchbar32_and_or(C0REFRCTRL2, (u32)~0x0fffff00, (0x3f << 22) | (reg32 << 8)); /* FIXME: Is this weird access necessary? Reference code does it */ MCHBAR8(C0REFRCTRL + 3) = 0; - MCHBAR16_AND_OR(C0REFCTRL, 0xc000, reg16); + mchbar16_and_or(C0REFCTRL, 0xc000, reg16); /* NPUT Static Mode */ - MCHBAR8_OR(C0DYNRDCTRL, 1); + mchbar8_or(C0DYNRDCTRL, 1); - MCHBAR32_AND_OR(C0STATRDCTRL, ~0x7f000000, 0xb << 25); + mchbar32_and_or(C0STATRDCTRL, (u32)~0x7f000000, 0xb << 25); i = s->selected_timings.mem_clock; j = s->selected_timings.fsb_clock; if (i > j) { - MCHBAR32_OR(C0STATRDCTRL, 1 << 24); + mchbar32_or(C0STATRDCTRL, 1 << 24); } - MCHBAR8_AND(C0RDFIFOCTRL, ~0x3); - MCHBAR16_AND_OR(C0WRDATACTRL, ~0x7c00, (wl + 10) << 10); - MCHBAR32_AND_OR(C0CKECTRL, ~0x070e0000, (3 << 24) | (3 << 17)); + mchbar8_and(C0RDFIFOCTRL, (u8)~0x3); + mchbar16_and_or(C0WRDATACTRL, (u16)~0x7c00, (wl + 10) << 10); + mchbar32_and_or(C0CKECTRL, (u32)~0x070e0000, (3 << 24) | (3 << 17)); reg16 = 0x15 << 6; reg16 |= 0x1f; reg16 |= (0x6 << 12); - MCHBAR16_AND_OR(C0REFRCTRL + 4, ~0x7fff, reg16); + mchbar16_and_or(C0REFRCTRL + 4, (u16)~0x7fff, reg16); reg32 = (0x6 << 27) | (1 << 25); /* FIXME: For DDR3, set BIT26 as well */ - MCHBAR32_AND_OR(C0REFRCTRL2, ~0x30000000, reg32 << 8); - MCHBAR8_AND_OR(C0REFRCTRL + 3, ~0xfa, reg32 >> 24); - MCHBAR8_AND(C0JEDEC, ~(1 << 7)); - MCHBAR8_AND(C0DYNRDCTRL, ~0x6); + mchbar32_and_or(C0REFRCTRL2, (u32)~0x30000000, reg32 << 8); + mchbar8_and_or(C0REFRCTRL + 3, (u8)~0xfa, reg32 >> 24); + mchbar8_and(C0JEDEC, (u8)~(1 << 7)); + mchbar8_and(C0DYNRDCTRL, (u8)~0x6); /* Note: This is a 64-bit register, [34..30] = 0b00110 is split across two writes */ reg32 = ((6 & 3) << 30) | (4 << 25) | (1 << 20) | (8 << 15) | (6 << 10) | (4 << 5) | 1; MCHBAR32(C0WRWMFLSH) = reg32; - MCHBAR16_AND_OR(C0WRWMFLSH + 4, ~0x1ff, (8 << 3) | (6 >> 2)); - MCHBAR16_OR(SHPENDREG, 0x1c00 | (0x1f << 5)); + mchbar16_and_or(C0WRWMFLSH + 4, (u16)~0x1ff, (8 << 3) | (6 >> 2)); + mchbar16_or(SHPENDREG, 0x1c00 | (0x1f << 5)); /* FIXME: Why not do a single word write? */ - MCHBAR8_AND_OR(SHPAGECTRL, ~0xff, 0x40); - MCHBAR8_AND_OR(SHPAGECTRL + 1, ~0x07, 0x05); - MCHBAR8_OR(SHCMPLWRCMD, 0x1f); + mchbar8_and_or(SHPAGECTRL, (u8)~0xff, 0x40); + mchbar8_and_or(SHPAGECTRL + 1, (u8)~0x07, 0x05); + mchbar8_or(SHCMPLWRCMD, 0x1f); reg8 = (3 << 6); reg8 |= (s->dt0mode << 4); reg8 |= 0x0c; - MCHBAR8_AND_OR(SHBONUSREG, ~0xdf, reg8); - MCHBAR8_AND(CSHRWRIOMLNS, ~0x02); - MCHBAR8_AND_OR(C0MISCTM, ~0x07, 0x02); - MCHBAR16_AND_OR(C0BYPCTRL, ~0x3fc, 4 << 2); + mchbar8_and_or(SHBONUSREG, (u8)~0xdf, reg8); + mchbar8_and(CSHRWRIOMLNS, (u8)~0x02); + mchbar8_and_or(C0MISCTM, (u8)~0x07, 0x02); + mchbar16_and_or(C0BYPCTRL, (u16)~0x3fc, 4 << 2); /* [31..29] = 0b010 for kN = 2 (2N) */ reg32 = (2 << 29) | (1 << 28) | (1 << 23); - MCHBAR32_AND_OR(WRWMCONFIG, ~0xffb00000, reg32); + mchbar32_and_or(WRWMCONFIG, (u32)~0xffb00000, reg32); reg8 = (u8) ((MCHBAR16(C0CYCTRKACT) & 0xe000) >> 13); reg8 |= (u8) ((MCHBAR16(C0CYCTRKACT + 2) & 1) << 3); - MCHBAR8_AND_OR(BYPACTSF, ~0xf0, reg8 << 4); + mchbar8_and_or(BYPACTSF, (u8)~0xf0, reg8 << 4); reg8 = (u8) ((MCHBAR32(C0CYCTRKRD) & 0x000f0000) >> 17); - MCHBAR8_AND_OR(BYPACTSF, ~0x0f, reg8); + mchbar8_and_or(BYPACTSF, (u8)~0x0f, reg8); /* FIXME: Why not clear everything at once? */ - MCHBAR8_AND(BYPKNRULE, ~0xfc); - MCHBAR8_AND(BYPKNRULE, ~0x03); - MCHBAR8_AND(SHBONUSREG, ~0x03); - MCHBAR8_OR(C0BYPCTRL, 1); - MCHBAR16_OR(CSHRMISCCTL1, 1 << 9); + mchbar8_and(BYPKNRULE, (u8)~0xfc); + mchbar8_and(BYPKNRULE, (u8)~0x03); + mchbar8_and(SHBONUSREG, (u8)~0x03); + mchbar8_or(C0BYPCTRL, 1); + mchbar16_or(CSHRMISCCTL1, 1 << 9); for (i = 0; i < 8; i++) { /* FIXME: Hardcoded for DDR2 SO-DIMMs */ - MCHBAR32_AND_OR(C0DLLRCVCTLy(i), ~0x3f3f3f3f, 0x0c0c0c0c); + mchbar32_and_or(C0DLLRCVCTLy(i), (u32)~0x3f3f3f3f, 0x0c0c0c0c); } /* RDCS to RCVEN delay: Program coarse common to all bytelanes to default tCL + 1 */ - MCHBAR32_AND_OR(C0STATRDCTRL, ~0x000f0000, (s->selected_timings.CAS + 1) << 16); + mchbar32_and_or(C0STATRDCTRL, (u32)~0x000f0000, (s->selected_timings.CAS + 1) << 16); /* Program RCVEN delay with DLL-safe settings */ for (i = 0; i < 8; i++) { - MCHBAR8_AND(C0RXRCVyDLL(i), ~0x3f); - MCHBAR16_AND(C0RCVMISCCTL2, (u16) ~(3 << (i * 2))); - MCHBAR16_AND(C0RCVMISCCTL1, (u16) ~(3 << (i * 2))); - MCHBAR16_AND(C0COARSEDLY0, (u16) ~(3 << (i * 2))); + mchbar8_and(C0RXRCVyDLL(i), (u8)~0x3f); + mchbar16_and(C0RCVMISCCTL2, (u16)~(3 << (i * 2))); + mchbar16_and(C0RCVMISCCTL1, (u16)~(3 << (i * 2))); + mchbar16_and(C0COARSEDLY0, (u16)~(3 << (i * 2))); } - MCHBAR8_AND(C0DLLPIEN, ~1); /* Power up receiver */ - MCHBAR8_OR(C0DLLPIEN, 2); /* Enable RCVEN DLL */ - MCHBAR8_OR(C0DLLPIEN, 4); /* Enable receiver DQS DLL */ - MCHBAR32_OR(C0COREBONUS, 0x000c0400); - MCHBAR32_OR(C0CMDTX1, 1 << 31); + mchbar8_and(C0DLLPIEN, (u8)~1); /* Power up receiver */ + mchbar8_or(C0DLLPIEN, 2); /* Enable RCVEN DLL */ + mchbar8_or(C0DLLPIEN, 4); /* Enable receiver DQS DLL */ + mchbar32_or(C0COREBONUS, 0x000c0400); + mchbar32_or(C0CMDTX1, 1 << 31); } /* Program clkset0's register for Kcoarse, Tap, PI, DBEn and DBSel */ static void sdram_p_clkset0(const struct pllparam *pll, u8 f, u8 i) { - MCHBAR16_AND_OR(C0CKTX, ~0xc440, + mchbar16_and_or(C0CKTX, (u16)~0xc440, (pll->clkdelay[f][i] << 14) | (pll->dben[f][i] << 10) | (pll->dbsel[f][i] << 6)); - MCHBAR8_AND_OR(C0TXCK0DLL, ~0x3f, pll->pi[f][i]); + mchbar8_and_or(C0TXCK0DLL, (u8)~0x3f, pll->pi[f][i]); } /* Program clkset1's register for Kcoarse, Tap, PI, DBEn and DBSel */ static void sdram_p_clkset1(const struct pllparam *pll, u8 f, u8 i) { /* FIXME: This is actually a dword write! */ - MCHBAR16_AND_OR(C0CKTX, ~0x00030880, + mchbar16_and_or(C0CKTX, (u16)~0x00030880, (pll->clkdelay[f][i] << 16) | (pll->dben[f][i] << 11) | (pll->dbsel[f][i] << 7)); - MCHBAR8_AND_OR(C0TXCK1DLL, ~0x3f, pll->pi[f][i]); + mchbar8_and_or(C0TXCK1DLL, (u8)~0x3f, pll->pi[f][i]); } /* Program CMD0 and CMD1 registers for Kcoarse, Tap, PI, DBEn and DBSel */ @@ -872,14 +873,14 @@ /* Clock Group Index 3 */ reg8 = pll->dbsel[f][i] << 5; reg8 |= pll->dben[f][i] << 6; - MCHBAR8_AND_OR(C0CMDTX1, ~0x60, reg8); + mchbar8_and_or(C0CMDTX1, (u8)~0x60, reg8); reg8 = pll->clkdelay[f][i] << 4; - MCHBAR8_AND_OR(C0CMDTX2, ~0x30, reg8); + mchbar8_and_or(C0CMDTX2, (u8)~0x30, reg8); reg8 = pll->pi[f][i]; - MCHBAR8_AND_OR(C0TXCMD0DLL, ~0x3f, reg8); - MCHBAR8_AND_OR(C0TXCMD1DLL, ~0x3f, reg8); + mchbar8_and_or(C0TXCMD0DLL, (u8)~0x3f, reg8); + mchbar8_and_or(C0TXCMD1DLL, (u8)~0x3f, reg8); } /* Program CTRL registers for Kcoarse, Tap, PI, DBEn and DBSel */ @@ -895,11 +896,11 @@ reg32 |= ((u32) pll->dben[f][i]) << 23; reg32 |= ((u32) pll->clkdelay[f][i]) << 24; reg32 |= ((u32) pll->clkdelay[f][i]) << 27; - MCHBAR32_AND_OR(C0CTLTX2, ~0x01bf0000, reg32); + mchbar32_and_or(C0CTLTX2, (u32)~0x01bf0000, reg32); reg8 = pll->pi[f][i]; - MCHBAR8_AND_OR(C0TXCTL0DLL, ~0x3f, reg8); - MCHBAR8_AND_OR(C0TXCTL1DLL, ~0x3f, reg8); + mchbar8_and_or(C0TXCTL0DLL, (u8)~0x3f, reg8); + mchbar8_and_or(C0TXCTL1DLL, (u8)~0x3f, reg8); /* CTRL2 and CTRL3 */ reg32 = ((u32) pll->dbsel[f][i]) << 12; @@ -908,11 +909,11 @@ reg32 |= ((u32) pll->dben[f][i]) << 9; reg32 |= ((u32) pll->clkdelay[f][i]) << 14; reg32 |= ((u32) pll->clkdelay[f][i]) << 10; - MCHBAR32_AND_OR(C0CMDTX2, ~0xff00, reg32); + mchbar32_and_or(C0CMDTX2, (u32)~0xff00, reg32); reg8 = pll->pi[f][i]; - MCHBAR8_AND_OR(C0TXCTL2DLL, ~0x3f, reg8); - MCHBAR8_AND_OR(C0TXCTL3DLL, ~0x3f, reg8); + mchbar8_and_or(C0TXCTL2DLL, (u8)~0x3f, reg8); + mchbar8_and_or(C0TXCTL3DLL, (u8)~0x3f, reg8); } static void sdram_p_dqs(struct pllparam *pll, u8 f, u8 clk) @@ -934,11 +935,11 @@ & ~((1 << (dqs + 9)) | (1 << dqs))) | reg32; reg32 = ((u32) pll->clkdelay[f][clk]) << ((dqs * 2) + 16); - MCHBAR32_AND_OR(C0DQSDQRyTX3(rank), ~((1 << (dqs * 2 + 17)) | (1 << (dqs * 2 + 16))), + mchbar32_and_or(C0DQSDQRyTX3(rank), ~((1 << (dqs * 2 + 17)) | (1 << (dqs * 2 + 16))), reg32); reg8 = pll->pi[f][clk]; - MCHBAR8_AND_OR(C0TXDQS0R0DLL + j, ~0x3f, reg8); + mchbar8_and_or(C0TXDQS0R0DLL + j, (u8)~0x3f, reg8); } @@ -961,10 +962,10 @@ & ~((1 << (dq + 9)) | (1 << dq))) | reg32; reg32 = ((u32) pll->clkdelay[f][clk]) << (dq*2); - MCHBAR32_AND_OR(C0DQSDQRyTX3(rank), ~((1 << (dq * 2 + 1)) | (1 << (dq * 2))), reg32); + mchbar32_and_or(C0DQSDQRyTX3(rank), ~((1 << (dq * 2 + 1)) | (1 << (dq * 2))), reg32); reg8 = pll->pi[f][clk]; - MCHBAR8_AND_OR(C0TXDQ0R0DLL + j, ~0x3f, reg8); + mchbar8_and_or(C0TXDQ0R0DLL + j, (u8)~0x3f, reg8); } /* WDLL programming: Perform HPLL/MPLL calibration after write levelization */ @@ -1055,8 +1056,8 @@ } /* Disable Dynamic DQS Slave Setting Per Rank */ - MCHBAR8_AND(CSHRDQSCMN, ~(1 << 7)); - MCHBAR16_AND_OR(CSHRPDCTL4, ~0x3fff, 0x1fff); + mchbar8_and(CSHRDQSCMN, (u8)~(1 << 7)); + mchbar16_and_or(CSHRPDCTL4, (u16)~0x3fff, 0x1fff); sdram_p_clkset0(&pll, f, 0); sdram_p_clkset1(&pll, f, 1); @@ -1079,13 +1080,13 @@ s->async = 0; reg8 = 0; - MCHBAR16_OR(CSHRPDCTL, 1 << 15); - MCHBAR8_AND(CSHRPDCTL, ~(1 << 7)); - MCHBAR8_OR(CSHRPDCTL, 1 << 3); - MCHBAR8_OR(CSHRPDCTL, 1 << 2); + mchbar16_or(CSHRPDCTL, 1 << 15); + mchbar8_and(CSHRPDCTL, (u8)~(1 << 7)); + mchbar8_or(CSHRPDCTL, 1 << 3); + mchbar8_or(CSHRPDCTL, 1 << 2); /* Start hardware HMC calibration */ - MCHBAR8_OR(CSHRPDCTL, 1 << 7); + mchbar8_or(CSHRPDCTL, 1 << 7); /* Busy-wait until calibration is done */ while ((MCHBAR8(CSHRPDCTL) & (1 << 2)) == 0) @@ -1110,80 +1111,80 @@ } else { reg32 = 0x00014221; } - MCHBAR32_AND_OR(CSHRMSTRCTL1, ~0x0fffffff, reg32); - MCHBAR32_OR(CSHRMSTRCTL1, 1 << 23); - MCHBAR32_OR(CSHRMSTRCTL1, 1 << 15); - MCHBAR32_AND(CSHRMSTRCTL1, ~(1 << 15)); + mchbar32_and_or(CSHRMSTRCTL1, (u32)~0x0fffffff, reg32); + mchbar32_or(CSHRMSTRCTL1, 1 << 23); + mchbar32_or(CSHRMSTRCTL1, 1 << 15); + mchbar32_and(CSHRMSTRCTL1, (u32)~(1 << 15)); if (s->nodll) { /* Disable the Master DLLs by setting these bits, IN ORDER! */ - MCHBAR16_OR(CSHRMSTRCTL0, 1 << 0); - MCHBAR16_OR(CSHRMSTRCTL0, 1 << 2); - MCHBAR16_OR(CSHRMSTRCTL0, 1 << 4); - MCHBAR16_OR(CSHRMSTRCTL0, 1 << 8); - MCHBAR16_OR(CSHRMSTRCTL0, 1 << 10); - MCHBAR16_OR(CSHRMSTRCTL0, 1 << 12); - MCHBAR16_OR(CSHRMSTRCTL0, 1 << 14); + mchbar16_or(CSHRMSTRCTL0, 1 << 0); + mchbar16_or(CSHRMSTRCTL0, 1 << 2); + mchbar16_or(CSHRMSTRCTL0, 1 << 4); + mchbar16_or(CSHRMSTRCTL0, 1 << 8); + mchbar16_or(CSHRMSTRCTL0, 1 << 10); + mchbar16_or(CSHRMSTRCTL0, 1 << 12); + mchbar16_or(CSHRMSTRCTL0, 1 << 14); } else { /* Enable the Master DLLs by clearing these bits, IN ORDER! */ - MCHBAR16_AND(CSHRMSTRCTL0, ~(1 << 0)); - MCHBAR16_AND(CSHRMSTRCTL0, ~(1 << 2)); - MCHBAR16_AND(CSHRMSTRCTL0, ~(1 << 4)); - MCHBAR16_AND(CSHRMSTRCTL0, ~(1 << 8)); - MCHBAR16_AND(CSHRMSTRCTL0, ~(1 << 10)); - MCHBAR16_AND(CSHRMSTRCTL0, ~(1 << 12)); - MCHBAR16_AND(CSHRMSTRCTL0, ~(1 << 14)); + mchbar16_and(CSHRMSTRCTL0, (u16)~(1 << 0)); + mchbar16_and(CSHRMSTRCTL0, (u16)~(1 << 2)); + mchbar16_and(CSHRMSTRCTL0, (u16)~(1 << 4)); + mchbar16_and(CSHRMSTRCTL0, (u16)~(1 << 8)); + mchbar16_and(CSHRMSTRCTL0, (u16)~(1 << 10)); + mchbar16_and(CSHRMSTRCTL0, (u16)~(1 << 12)); + mchbar16_and(CSHRMSTRCTL0, (u16)~(1 << 14)); } /* Initialize the Transmit DLL PI values in the following sequence. */ if (s->nodll) { - MCHBAR8_AND_OR(CREFPI, ~0x3f, 0x07); + mchbar8_and_or(CREFPI, (u8)~0x3f, 0x07); } else { - MCHBAR8_AND(CREFPI, ~0x3f); + mchbar8_and(CREFPI, (u8)~0x3f); } sdram_calibratepll(s, 0); // XXX check /* Enable all modular Slave DLL */ - MCHBAR16_OR(C0DLLPIEN, 1 << 11); - MCHBAR16_OR(C0DLLPIEN, 1 << 12); + mchbar16_or(C0DLLPIEN, 1 << 11); + mchbar16_or(C0DLLPIEN, 1 << 12); for (i = 0; i < 8; i++) { - MCHBAR16_OR(C0DLLPIEN, (1 << 10) >> i); + mchbar16_or(C0DLLPIEN, (1 << 10) >> i); } /* Enable DQ/DQS output */ - MCHBAR8_OR(C0SLVDLLOUTEN, 1); + mchbar8_or(C0SLVDLLOUTEN, 1); MCHBAR16(CSPDSLVWT) = 0x5005; - MCHBAR16_AND_OR(CSHRPDCTL2, ~0x1f1f, 0x051a); - MCHBAR16_AND_OR(CSHRPDCTL5, ~0xbf3f, 0x9010); + mchbar16_and_or(CSHRPDCTL2, (u16)~0x1f1f, 0x051a); + mchbar16_and_or(CSHRPDCTL5, (u16)~0xbf3f, 0x9010); if (s->nodll) { - MCHBAR8_AND_OR(CSHRPDCTL3, ~0x7f, 0x6b); + mchbar8_and_or(CSHRPDCTL3, (u8)~0x7f, 0x6b); } else { - MCHBAR8_AND_OR(CSHRPDCTL3, ~0x7f, 0x55); + mchbar8_and_or(CSHRPDCTL3, (u8)~0x7f, 0x55); sdram_calibratehwpll(s); } /* Disable Dynamic Diff Amp */ - MCHBAR32_AND(C0STATRDCTRL, ~(1 << 22)); + mchbar32_and(C0STATRDCTRL, (u32)~(1 << 22)); /* Now, start initializing the transmit FIFO */ - MCHBAR8_AND(C0MISCCTL, ~0x02); + mchbar8_and(C0MISCCTL, (u8)~0x02); /* Disable (gate) mdclk and mdclkb */ - MCHBAR8_OR(CSHWRIOBONUS, 0xc0); + mchbar8_or(CSHWRIOBONUS, 0xc0); /* Select mdmclk */ - MCHBAR8_AND(CSHWRIOBONUS, ~(1 << 5)); + mchbar8_and(CSHWRIOBONUS, (u8)~(1 << 5)); /* Ungate mdclk */ - MCHBAR8_AND_OR(CSHWRIOBONUS, ~0xc0, 1 << 6); - MCHBAR8_AND_OR(CSHRFIFOCTL, ~0x3f, 0x1a); + mchbar8_and_or(CSHWRIOBONUS, (u8)~0xc0, 1 << 6); + mchbar8_and_or(CSHRFIFOCTL, (u8)~0x3f, 0x1a); /* Enable the write pointer count */ - MCHBAR8_OR(CSHRFIFOCTL, 1); + mchbar8_or(CSHRFIFOCTL, 1); /* Set the DDR3 Reset Enable bit */ - MCHBAR8_OR(CSHRDDR3CTL, 1); + mchbar8_or(CSHRDDR3CTL, 1); /* Configure DQS-DQ Transmit */ MCHBAR32(CSHRDQSTXPGM) = 0x00551803; @@ -1191,10 +1192,10 @@ reg8 = 0; /* Switch all clocks on anyway */ /* Enable clock groups depending on rank population */ - MCHBAR32_AND_OR(C0CKTX, ~0x3f000000, reg8 << 24); + mchbar32_and_or(C0CKTX, (u32)~0x3f000000, reg8 << 24); /* Enable DDR command output buffers from core */ - MCHBAR8_AND(0x594, ~1); + mchbar8_and(0x594, (u8)~1); reg16 = 0; if (!rank_is_populated(s->dimms, 0, 0)) { @@ -1209,7 +1210,7 @@ if (!rank_is_populated(s->dimms, 0, 3)) { reg16 |= (1 << 11) | (1 << 7) | (1 << 3); } - MCHBAR16_OR(C0CTLTX2, reg16); + mchbar16_or(C0CTLTX2, reg16); } /* Define a shorter name for these to make the lines fit in 96 characters */ @@ -1344,54 +1345,54 @@ FOR_EACH_RCOMP_GROUP(i) { reg8 = rcompupdate[i]; - MCHBAR8_AND_OR(C0RCOMPCTRLx(i), ~1, reg8); - MCHBAR8_AND(C0RCOMPCTRLx(i), ~2); + mchbar8_and_or(C0RCOMPCTRLx(i), (u8)~1, reg8); + mchbar8_and(C0RCOMPCTRLx(i), (u8)~2); reg16 = rcompslew; - MCHBAR16_AND_OR(C0RCOMPCTRLx(i), ~0xf000, reg16 << 12); + mchbar16_and_or(C0RCOMPCTRLx(i), (u16)~0xf000, reg16 << 12); MCHBAR8(C0RCOMPMULTx(i)) = rcompstr[i]; MCHBAR16(C0SCOMPVREFx(i)) = rcompscomp[i]; - MCHBAR8_AND_OR(C0DCOMPx(i), ~0x03, rcompdelay[i]); + mchbar8_and_or(C0DCOMPx(i), (u8)~0x03, rcompdelay[i]); if (i == 2) { /* FIXME: Why are we rewriting this? */ - MCHBAR16_AND_OR(C0RCOMPCTRLx(i), ~0xf000, reg16 << 12); + mchbar16_and_or(C0RCOMPCTRLx(i), (u16)~0xf000, reg16 << 12); MCHBAR8(C0RCOMPMULTx(i)) = rcompstr2[s->dimm_config[0]]; MCHBAR16(C0SCOMPVREFx(i)) = rcompscomp2[s->dimm_config[0]]; - MCHBAR8_AND_OR(C0DCOMPx(i), ~0x03, rcompdelay2[s->dimm_config[0]]); + mchbar8_and_or(C0DCOMPx(i), (u8)~0x03, rcompdelay2[s->dimm_config[0]]); } - MCHBAR16_AND(C0SLEWBASEx(i), ~0x7f7f); + mchbar16_and(C0SLEWBASEx(i), (u16)~0x7f7f); /* FIXME: Why not do a single dword write? */ - MCHBAR16_AND(C0SLEWPULUTx(i), ~0x3f3f); - MCHBAR16_AND(C0SLEWPULUTx(i) + 2, ~0x3f3f); + mchbar16_and(C0SLEWPULUTx(i), (u16)~0x3f3f); + mchbar16_and(C0SLEWPULUTx(i) + 2, (u16)~0x3f3f); /* FIXME: Why not do a single dword write? */ - MCHBAR16_AND(C0SLEWPDLUTx(i), ~0x3f3f); - MCHBAR16_AND(C0SLEWPDLUTx(i) + 2, ~0x3f3f); + mchbar16_and(C0SLEWPDLUTx(i), (u16)~0x3f3f); + mchbar16_and(C0SLEWPDLUTx(i) + 2, (u16)~0x3f3f); } /* FIXME: Hardcoded */ - MCHBAR8_AND_OR(C0ODTRECORDX, ~0x3f, 0x36); - MCHBAR8_AND_OR(C0DQSODTRECORDX, ~0x3f, 0x36); + mchbar8_and_or(C0ODTRECORDX, (u8)~0x3f, 0x36); + mchbar8_and_or(C0DQSODTRECORDX, (u8)~0x3f, 0x36); FOR_EACH_RCOMP_GROUP(i) { - MCHBAR8_AND(C0RCOMPCTRLx(i), ~0x60); - MCHBAR16_AND(C0RCOMPCTRLx(i) + 2, ~0x0706); - MCHBAR16_AND(C0RCOMPOSVx(i), ~0x7f7f); - MCHBAR16_AND(C0SCOMPOFFx(i), ~0x3f3f); - MCHBAR16_AND(C0DCOMPOFFx(i), ~0x1f1f); - MCHBAR8_AND(C0DCOMPOFFx(i) + 2, ~0x1f); + mchbar8_and(C0RCOMPCTRLx(i), (u8)~0x60); + mchbar16_and(C0RCOMPCTRLx(i) + 2, (u16)~0x0706); + mchbar16_and(C0RCOMPOSVx(i), (u16)~0x7f7f); + mchbar16_and(C0SCOMPOFFx(i), (u16)~0x3f3f); + mchbar16_and(C0DCOMPOFFx(i), (u16)~0x1f1f); + mchbar8_and(C0DCOMPOFFx(i) + 2, (u8)~0x1f); } - MCHBAR16_AND(C0ODTRECORDX, ~0xffc0); - MCHBAR16_AND(C0ODTRECORDX + 2, ~0x000f); + mchbar16_and(C0ODTRECORDX, (u16)~0xffc0); + mchbar16_and(C0ODTRECORDX + 2, (u16)~0x000f); /* FIXME: Why not do a single dword write? */ - MCHBAR16_AND(C0DQSODTRECORDX, ~0xffc0); - MCHBAR16_AND(C0DQSODTRECORDX + 2, ~0x000f); + mchbar16_and(C0DQSODTRECORDX, (u16)~0xffc0); + mchbar16_and(C0DQSODTRECORDX + 2, (u16)~0x000f); FOR_EACH_RCOMP_GROUP(i) { MCHBAR16(C0SCOMPOVRx(i)) = rcompf[i]; @@ -1401,33 +1402,33 @@ MCHBAR16(C0DCOMPOVRx(i) + 2) = 0x000C; } - MCHBAR32_AND_OR(DCMEASBUFOVR, ~0x001f1f1f, 0x000c1219); + mchbar32_and_or(DCMEASBUFOVR, (u32)~0x001f1f1f, 0x000c1219); /* FIXME: Why not do a single word write? */ - MCHBAR16_AND_OR(XCOMPSDR0BNS, ~0x1f00, 0x1200); - MCHBAR8_AND_OR(XCOMPSDR0BNS, ~0x1f, 0x12); + mchbar16_and_or(XCOMPSDR0BNS, (u16)~0x1f00, 0x1200); + mchbar8_and_or(XCOMPSDR0BNS, (u8)~0x1f, 0x12); MCHBAR32(COMPCTRL3) = 0x007C9007; MCHBAR32(OFREQDELSEL) = rcomp1; MCHBAR16(XCOMPCMNBNS) = 0x1f7f; MCHBAR32(COMPCTRL2) = rcomp2; - MCHBAR16_AND_OR(XCOMPDFCTRL, ~0x0f, 1); + mchbar16_and_or(XCOMPDFCTRL, (u16)~0x0f, 1); MCHBAR16(ZQCALCTRL) = 0x0134; MCHBAR32(COMPCTRL1) = 0x4C293600; /* FIXME: wtf did these MRC guys smoke */ - MCHBAR8_AND_OR(COMPCTRL1 + 3, ~0x44, (1 << 6) | (1 << 2)); - MCHBAR16_AND(XCOMPSDR0BNS, ~(1 << 13)); - MCHBAR8_AND(XCOMPSDR0BNS, ~(1 << 5)); + mchbar8_and_or(COMPCTRL1 + 3, (u8)~0x44, (1 << 6) | (1 << 2)); + mchbar16_and(XCOMPSDR0BNS, (u16)~(1 << 13)); + mchbar8_and(XCOMPSDR0BNS, (u8)~(1 << 5)); FOR_EACH_RCOMP_GROUP(i) { /* FIXME: This should be an _AND_OR */ - MCHBAR8(C0RCOMPCTRLx(i) + 2) = MCHBAR8(C0RCOMPCTRLx(i)) & ~0x71; + MCHBAR8(C0RCOMPCTRLx(i) + 2) = MCHBAR8(C0RCOMPCTRLx(i)) & (u8)~0x71; } if ((MCHBAR32(COMPCTRL1) & (1 << 30)) == 0) { /* Start COMP */ - MCHBAR8_OR(COMPCTRL1, 1); + mchbar8_or(COMPCTRL1, 1); /* Wait until COMP is done */ while ((MCHBAR8(COMPCTRL1) & 1) != 0) @@ -1443,55 +1444,55 @@ /* FIXME: Why not do a single word write? */ reg16 = (u16)(rcompp - (1 << (srup + 1))) << 8; - MCHBAR16_AND_OR(C0SLEWBASEx(i), ~0x7f00, reg16); + mchbar16_and_or(C0SLEWBASEx(i), (u16)~0x7f00, reg16); reg16 = (u16)(rcompn - (1 << (srun + 1))); - MCHBAR8_AND_OR(C0SLEWBASEx(i), ~0x7f, (u8)reg16); + mchbar8_and_or(C0SLEWBASEx(i), (u8)~0x7f, (u8)reg16); } reg8 = rcompp - (1 << (srup + 1)); for (i = 0, j = reg8; i < 4; i++, j += (1 << srup)) { - MCHBAR8_AND_OR(C0SLEWPULUTx(0) + i, ~0x3f, rcomplut[j][0]); + mchbar8_and_or(C0SLEWPULUTx(0) + i, (u8)~0x3f, rcomplut[j][0]); } for (i = 0, j = reg8; i < 4; i++, j += (1 << srup)) { if (s->dimm_config[0] < 3 || s->dimm_config[0] == 5) { - MCHBAR8_AND_OR(C0SLEWPULUTx(2) + i, ~0x3f, rcomplut[j][10]); + mchbar8_and_or(C0SLEWPULUTx(2) + i, (u8)~0x3f, rcomplut[j][10]); } } for (i = 0, j = reg8; i < 4; i++, j += (1 << srup)) { - MCHBAR8_AND_OR(C0SLEWPULUTx(3) + i, ~0x3f, rcomplut[j][6]); - MCHBAR8_AND_OR(C0SLEWPULUTx(4) + i, ~0x3f, rcomplut[j][6]); + mchbar8_and_or(C0SLEWPULUTx(3) + i, (u8)~0x3f, rcomplut[j][6]); + mchbar8_and_or(C0SLEWPULUTx(4) + i, (u8)~0x3f, rcomplut[j][6]); } for (i = 0, j = reg8; i < 4; i++, j += (1 << srup)) { - MCHBAR8_AND_OR(C0SLEWPULUTx(5) + i, ~0x3f, rcomplut[j][8]); - MCHBAR8_AND_OR(C0SLEWPULUTx(6) + i, ~0x3f, rcomplut[j][8]); + mchbar8_and_or(C0SLEWPULUTx(5) + i, (u8)~0x3f, rcomplut[j][8]); + mchbar8_and_or(C0SLEWPULUTx(6) + i, (u8)~0x3f, rcomplut[j][8]); } reg8 = rcompn - (1 << (srun + 1)); for (i = 0, j = reg8; i < 4; i++, j += (1 << srun)) { - MCHBAR8_AND_OR(C0SLEWPDLUTx(0) + i, ~0x3f, rcomplut[j][1]); + mchbar8_and_or(C0SLEWPDLUTx(0) + i, (u8)~0x3f, rcomplut[j][1]); } for (i = 0, j = reg8; i < 4; i++, j += (1 << srun)) { if (s->dimm_config[0] < 3 || s->dimm_config[0] == 5) { - MCHBAR8_AND_OR(C0SLEWPDLUTx(2) + i, ~0x3f, rcomplut[j][11]); + mchbar8_and_or(C0SLEWPDLUTx(2) + i, (u8)~0x3f, rcomplut[j][11]); } } for (i = 0, j = reg8; i < 4; i++, j += (1 << srun)) { - MCHBAR8_AND_OR(C0SLEWPDLUTx(3) + i, ~0x3f, rcomplut[j][7]); - MCHBAR8_AND_OR(C0SLEWPDLUTx(4) + i, ~0x3f, rcomplut[j][7]); + mchbar8_and_or(C0SLEWPDLUTx(3) + i, (u8)~0x3f, rcomplut[j][7]); + mchbar8_and_or(C0SLEWPDLUTx(4) + i, (u8)~0x3f, rcomplut[j][7]); } for (i = 0, j = reg8; i < 4; i++, j += (1 << srun)) { - MCHBAR8_AND_OR(C0SLEWPDLUTx(5) + i, ~0x3f, rcomplut[j][9]); - MCHBAR8_AND_OR(C0SLEWPDLUTx(6) + i, ~0x3f, rcomplut[j][9]); + mchbar8_and_or(C0SLEWPDLUTx(5) + i, (u8)~0x3f, rcomplut[j][9]); + mchbar8_and_or(C0SLEWPDLUTx(6) + i, (u8)~0x3f, rcomplut[j][9]); } } - MCHBAR8_OR(COMPCTRL1, 1); + mchbar8_or(COMPCTRL1, 1); } /* FIXME: The ODT tables are for DDR2 only! */ @@ -1566,24 +1567,24 @@ if ((s->dimm_config[0] < 3) && rank_is_populated(s->dimms, 0, 0)) { if (s->dimms[0].sides > 1) { // 2R/NC - MCHBAR32_AND_OR(C0CKECTRL, ~1, 0x300001); + mchbar32_and_or(C0CKECTRL, (u32)~1, 0x300001); MCHBAR32(C0DRA01) = 0x00000101; MCHBAR32(C0DRB0) = 0x00040002; MCHBAR32(C0DRB2) = w204[s->dimm_config[0]]; } else { // 1R/NC - MCHBAR32_AND_OR(C0CKECTRL, ~1, 0x100001); + mchbar32_and_or(C0CKECTRL, (u32)~1, 0x100001); MCHBAR32(C0DRA01) = 0x00000001; MCHBAR32(C0DRB0) = 0x00020002; MCHBAR32(C0DRB2) = w204[s->dimm_config[0]]; } } else if ((s->dimm_config[0] == 5) && rank_is_populated(s->dimms, 0, 0)) { - MCHBAR32_AND_OR(C0CKECTRL, ~1, 0x300001); + mchbar32_and_or(C0CKECTRL, (u32)~1, 0x300001); MCHBAR32(C0DRA01) = 0x00000101; MCHBAR32(C0DRB0) = 0x00040002; MCHBAR32(C0DRB2) = 0x00040004; } else { - MCHBAR32_AND_OR(C0CKECTRL, ~1, w260[s->dimm_config[0]]); + mchbar32_and_or(C0CKECTRL, (u32)~1, w260[s->dimm_config[0]]); MCHBAR32(C0DRA01) = w208[s->dimm_config[0]]; MCHBAR32(C0DRB0) = w200[s->dimm_config[0]]; MCHBAR32(C0DRB2) = w204[s->dimm_config[0]]; @@ -1652,10 +1653,10 @@ u32 reg32a, reg32b; ok = 0; - MCHBAR8_AND(XCOMPDFCTRL, ~(1 << 3)); - MCHBAR8_AND(COMPCTRL1, ~(1 << 7)); + mchbar8_and(XCOMPDFCTRL, (u8)~(1 << 3)); + mchbar8_and(COMPCTRL1, (u8)~(1 << 7)); for (i = 0; i < 3; i++) { - MCHBAR8_OR(COMPCTRL1, 1); + mchbar8_or(COMPCTRL1, 1); hpet_udelay(1000); while ((MCHBAR8(COMPCTRL1) & 1) != 0) ; @@ -1668,7 +1669,7 @@ reg32a |= (1 << 31) | (1 << 15); MCHBAR32(RCMEASBUFXOVR) = reg32a; } - MCHBAR8_OR(COMPCTRL1, 1); + mchbar8_or(COMPCTRL1, 1); hpet_udelay(1000); while ((MCHBAR8(COMPCTRL1) & 1) != 0) ; @@ -1681,7 +1682,7 @@ reg32 = jval << 3; reg32 |= rank * (1 << 27); - MCHBAR8_AND_OR(C0JEDEC, ~0x3e, jmode); + mchbar8_and_or(C0JEDEC, (u8)~0x3e, jmode); read32((void *)reg32); barrier(); hpet_udelay(1); // 1us @@ -1690,10 +1691,10 @@ static void sdram_zqcl(struct sysinfo *s) { if (s->boot_path == BOOT_PATH_RESUME) { - MCHBAR32_OR(C0CKECTRL, 1 << 27); - MCHBAR8_AND_OR(C0JEDEC, ~0x0e, NORMAL_OP_CMD); - MCHBAR8_AND(C0JEDEC, ~0x30); - MCHBAR32_AND_OR(C0REFRCTRL2, ~(3 << 30), 3 << 30); + mchbar32_or(C0CKECTRL, 1 << 27); + mchbar8_and_or(C0JEDEC, (u8)~0x0e, NORMAL_OP_CMD); + mchbar8_and(C0JEDEC, (u8)~0x30); + mchbar32_and_or(C0REFRCTRL2, (u32)~(3 << 30), 3 << 30); } } @@ -1759,12 +1760,12 @@ reg32 = 0; reg32 |= (4 << 13); reg32 |= (6 << 8); - MCHBAR32_AND_OR(C0DYNRDCTRL, ~0x3ff00, reg32); - MCHBAR8_AND(C0DYNRDCTRL, ~(1 << 7)); - MCHBAR8_OR(C0REFRCTRL + 3, 1); + mchbar32_and_or(C0DYNRDCTRL, (u32)~0x3ff00, reg32); + mchbar8_and(C0DYNRDCTRL, (u8)~(1 << 7)); + mchbar8_or(C0REFRCTRL + 3, 1); if (s->boot_path != BOOT_PATH_RESUME) { - MCHBAR8_AND_OR(C0JEDEC, ~0x0e, NORMAL_OP_CMD); - MCHBAR8_AND(C0JEDEC, ~0x30); + mchbar8_and_or(C0JEDEC, (u8)~0x0e, NORMAL_OP_CMD); + mchbar8_and(C0JEDEC, (u8)~0x30); } else { sdram_zqcl(s); } @@ -1861,10 +1862,10 @@ reg32 |= (1 << r); } reg8 = (u8)(reg32 << 4) & 0xf0; - MCHBAR8_AND_OR(C0CKECTRL + 2, ~0xf0, reg8); + mchbar8_and_or(C0CKECTRL + 2, (u8)~0xf0, reg8); if (ONLY_DIMMA_IS_POPULATED(s->dimms, 0) || ONLY_DIMMB_IS_POPULATED(s->dimms, 0)) { - MCHBAR8_OR(C0CKECTRL, 1); + mchbar8_or(C0CKECTRL, 1); } addr = C0DRB0; @@ -1885,9 +1886,9 @@ { u8 dqsmatches = 1; while (count--) { - MCHBAR8_AND(C0RSTCTL, ~2); + mchbar8_and(C0RSTCTL, (u8)~2); hpet_udelay(1); - MCHBAR8_OR(C0RSTCTL, 2); + mchbar8_or(C0RSTCTL, 2); hpet_udelay(1); barrier(); read32((void *)strobeaddr); @@ -1906,12 +1907,12 @@ { if (*medium < 3) { (*medium)++; - MCHBAR16_AND_OR(C0RCVMISCCTL2, (u16)~(3 << (lane * 2)), *medium << (lane * 2)); + mchbar16_and_or(C0RCVMISCCTL2, (u16)~(3 << (lane * 2)), *medium << (lane * 2)); } else { *medium = 0; (*coarse)++; - MCHBAR32_AND_OR(C0STATRDCTRL, ~0x000f0000, *coarse << 16); - MCHBAR16_AND_OR(C0RCVMISCCTL2, (u16)(~3 << (lane * 2)), *medium << (lane * 2)); + mchbar32_and_or(C0STATRDCTRL, (u32)~0x000f0000, *coarse << 16); + mchbar16_and_or(C0RCVMISCCTL2, (u16)(~3 << (lane * 2)), *medium << (lane * 2)); } } @@ -1930,8 +1931,8 @@ u32 strobeaddr = 0; u32 dqshighaddr; - MCHBAR8_AND(C0RSTCTL, ~0x0c); - MCHBAR8_AND(CMNDQFIFORST, ~0x80); + mchbar8_and(C0RSTCTL, (u8)~0x0c); + mchbar8_and(CMNDQFIFORST, (u8)~0x80); PRINTK_DEBUG("rcven 0\n"); for (lane = 0; lane < maxlane; lane++) { @@ -1943,10 +1944,10 @@ pi = 0; medium = 0; - MCHBAR32_AND_OR(C0STATRDCTRL, ~0x000f0000, coarse << 16); - MCHBAR16_AND_OR(C0RCVMISCCTL2, (u16)~(3 << (lane * 2)), medium << (lane * 2)); + mchbar32_and_or(C0STATRDCTRL, (u32)~0x000f0000, coarse << 16); + mchbar16_and_or(C0RCVMISCCTL2, (u16)~(3 << (lane * 2)), medium << (lane * 2)); - MCHBAR8_AND(C0RXRCVyDLL(lane), ~0x3f); + mchbar8_and(C0RXRCVyDLL(lane), (u8)~0x3f); savecoarse = coarse; savemedium = medium; @@ -1955,7 +1956,7 @@ PRINTK_DEBUG("rcven 0.1\n"); // XXX comment out - // MCHBAR16_AND_OR(C0RCVMISCCTL1, (u16)~3 << (lane * 2), 1 << (lane * 2)); + // mchbar16_and_or(C0RCVMISCCTL1, (u16)~3 << (lane * 2), 1 << (lane * 2)); while (sampledqs(dqshighaddr, strobeaddr, 0, 3) == 0) { // printk(BIOS_DEBUG, "coarse=%d medium=%d\n", coarse, medium); @@ -1986,8 +1987,8 @@ PRINTK_DEBUG("rcven 0.3\n"); coarse = savecoarse; medium = savemedium; - MCHBAR32_AND_OR(C0STATRDCTRL, ~0x000f0000, coarse << 16); - MCHBAR16_AND_OR(C0RCVMISCCTL2, (u16)~(0x3 << lane * 2), medium << (lane * 2)); + mchbar32_and_or(C0STATRDCTRL, (u32)~0x000f0000, coarse << 16); + mchbar16_and_or(C0RCVMISCCTL2, (u16)~(0x3 << lane * 2), medium << (lane * 2)); while (sampledqs(dqshighaddr, strobeaddr, 1, 3) == 0) { savepi = pi; @@ -1998,12 +1999,12 @@ break; // } } - MCHBAR8_AND_OR(C0RXRCVyDLL(lane), ~0x3f, pi << s->pioffset); + mchbar8_and_or(C0RXRCVyDLL(lane), (u8)~0x3f, pi << s->pioffset); } PRINTK_DEBUG("rcven 0.4\n"); pi = savepi; - MCHBAR8_AND_OR(C0RXRCVyDLL(lane), ~0x3f, pi << s->pioffset); + mchbar8_and_or(C0RXRCVyDLL(lane), (u8)~0x3f, pi << s->pioffset); rcvenclock(&coarse, &medium, lane); if (sampledqs(dqshighaddr, strobeaddr, 1, 1) == 0) { @@ -2013,7 +2014,7 @@ PRINTK_DEBUG("rcven 0.5\n"); while (sampledqs(dqshighaddr, strobeaddr, 0, 3) == 0) { coarse--; - MCHBAR32_AND_OR(C0STATRDCTRL, ~0x000f0000, coarse << 16); + mchbar32_and_or(C0STATRDCTRL, (u32)~0x000f0000, coarse << 16); if (coarse == 0) { PRINTK_DEBUG("Error: DQS did not hit 0\n"); break; @@ -2040,10 +2041,10 @@ do { lane--; offset = lanecoarse[lane] - minlanecoarse; - MCHBAR16_AND_OR(C0COARSEDLY0, (u16)(~(3 << (lane * 2))), offset << (lane * 2)); + mchbar16_and_or(C0COARSEDLY0, (u16)(~(3 << (lane * 2))), offset << (lane * 2)); } while (lane != 0); - MCHBAR32_AND_OR(C0STATRDCTRL, ~0x000f0000, minlanecoarse << 16); + mchbar32_and_or(C0STATRDCTRL, (u32)~0x000f0000, minlanecoarse << 16); s->coarsectrl = minlanecoarse; s->coarsedelay = MCHBAR16(C0COARSEDLY0); @@ -2051,14 +2052,14 @@ s->readptrdelay = MCHBAR16(C0RCVMISCCTL1); PRINTK_DEBUG("rcven 2\n"); - MCHBAR8_AND(C0RSTCTL, ~0x0e); - MCHBAR8_OR(C0RSTCTL, 0x02); - MCHBAR8_OR(C0RSTCTL, 0x04); - MCHBAR8_OR(C0RSTCTL, 0x08); + mchbar8_and(C0RSTCTL, (u8)~0x0e); + mchbar8_or(C0RSTCTL, 0x02); + mchbar8_or(C0RSTCTL, 0x04); + mchbar8_or(C0RSTCTL, 0x08); - MCHBAR8_OR(CMNDQFIFORST, 0x80); - MCHBAR8_AND(CMNDQFIFORST, ~0x80); - MCHBAR8_OR(CMNDQFIFORST, 0x80); + mchbar8_or(CMNDQFIFORST, 0x80); + mchbar8_and(CMNDQFIFORST, (u8)~0x80); + mchbar8_or(CMNDQFIFORST, 0x80); PRINTK_DEBUG("rcven 3\n"); } @@ -2138,20 +2139,20 @@ { u8 reg8, ch, r, fsb_freq, ddr_freq; u32 mask32, reg32; - MCHBAR8_OR(C0ADDCSCTRL, 1); - MCHBAR8_OR(C0REFRCTRL + 3, 1); + mchbar8_or(C0ADDCSCTRL, 1); + mchbar8_or(C0REFRCTRL + 3, 1); mask32 = (0x1f << 15) | (0x1f << 10) | (0x1f << 5) | 0x1f; reg32 = (0x1e << 15) | (0x10 << 10) | (0x1e << 5) | 0x10; - MCHBAR32_AND_OR(WRWMCONFIG, ~mask32, reg32); + mchbar32_and_or(WRWMCONFIG, (u32)~mask32, reg32); MCHBAR8(C0DITCTRL + 1) = 2; MCHBAR16(C0DITCTRL + 2) = 0x0804; MCHBAR16(C0DITCTRL + 4) = 0x2010; MCHBAR8(C0DITCTRL + 6) = 0x40; MCHBAR16(C0DITCTRL + 8) = 0x091c; MCHBAR8(C0DITCTRL + 10) = 0xf2; - MCHBAR8_OR(C0BYPCTRL, 1); - MCHBAR8_OR(C0CWBCTRL, 1); - MCHBAR16_OR(C0ARBSPL, 0x0100); + mchbar8_or(C0BYPCTRL, 1); + mchbar8_or(C0CWBCTRL, 1); + mchbar16_or(C0ARBSPL, 0x0100); pci_or_config8(HOST_BRIDGE, 0xf0, 1); MCHBAR32(SBCTL) = 0x00000002; @@ -2162,7 +2163,7 @@ MCHBAR32(HIT2) = 0x07000000; MCHBAR32(HIT3) = 0x01014010; MCHBAR32(HIT4) = 0x0f038000; - pci_and_config8(HOST_BRIDGE, 0xf0, ~1); + pci_and_config8(HOST_BRIDGE, 0xf0, (u8)~1); u32 nranks, curranksize, maxranksize, dra; u8 rankmismatch; @@ -2209,14 +2210,14 @@ die("Invalid number of ranks found, halt\n"); break; } - MCHBAR8_AND_OR(CHDECMISC, ~0xfc, reg8 & 0xfc); - MCHBAR32_AND(NOACFGBUSCTL, ~0x80000000); + mchbar8_and_or(CHDECMISC, (u8)~0xfc, reg8 & 0xfc); + mchbar32_and(NOACFGBUSCTL, (u32)~0x80000000); MCHBAR32(HTBONUS0) = 0x0000000f; - MCHBAR8_OR(C0COREBONUS + 4, 1); + mchbar8_or(C0COREBONUS + 4, 1); - MCHBAR32_AND(HIT3, ~0x0e000000); - MCHBAR32_AND_OR(HIT4, ~0x000c0000, 0x00040000); + mchbar32_and(HIT3, (u32)~0x0e000000); + mchbar32_and_or(HIT4, (u32)~0x000c0000, 0x00040000); u32 clkcx[2][2][3] = { { @@ -2236,20 +2237,20 @@ MCHBAR32(CLKXSSH2X2MD + 4) = clkcx[fsb_freq][ddr_freq][1]; MCHBAR32(CLKXSSH2MCBYP + 4) = clkcx[fsb_freq][ddr_freq][2]; - MCHBAR8_AND(HIT4, ~0x02); + mchbar8_and(HIT4, (u8)~0x02); } static void sdram_periodic_rcomp(void) { - MCHBAR8_AND(COMPCTRL1, ~0x02); + mchbar8_and(COMPCTRL1, (u8)~0x02); while ((MCHBAR32(COMPCTRL1) & 0x80000000) > 0) { ; } - MCHBAR16_AND(CSHRMISCCTL, ~0x3000); - MCHBAR8_OR(CMNDQFIFORST, 0x80); - MCHBAR16_AND_OR(XCOMPDFCTRL, ~0x0f, 0x09); + mchbar16_and(CSHRMISCCTL, (u16)~0x3000); + mchbar8_or(CMNDQFIFORST, 0x80); + mchbar16_and_or(XCOMPDFCTRL, (u16)~0x0f, 0x09); - MCHBAR8_OR(COMPCTRL1, 0x82); + mchbar8_or(COMPCTRL1, 0x82); } static void sdram_new_trd(struct sysinfo *s) @@ -2337,7 +2338,7 @@ } } - MCHBAR16_AND_OR(C0STATRDCTRL, ~0x1f00, trd << 8); + mchbar16_and_or(C0STATRDCTRL, (u16)~0x1f00, trd << 8); } static void sdram_powersettings(struct sysinfo *s) @@ -2347,26 +2348,26 @@ /* Thermal sensor */ MCHBAR8(TSC1) = 0x9b; - MCHBAR32_AND_OR(TSTTP, ~0x00ffffff, 0x1d00); + mchbar32_and_or(TSTTP, (u32)~0x00ffffff, 0x1d00); MCHBAR8(THERM1) = 0x08; MCHBAR8(TSC3) = 0x00; - MCHBAR8_AND_OR(TSC2, ~0x0f, 0x04); - MCHBAR8_AND_OR(THERM1, ~1, 1); - MCHBAR8_AND_OR(TCO, ~0x80, 0x80); + mchbar8_and_or(TSC2, (u8)~0x0f, 0x04); + mchbar8_and_or(THERM1, (u8)~1, 1); + mchbar8_and_or(TCO, (u8)~0x80, 0x80); /* Clock gating */ - MCHBAR32_AND(PMMISC, ~0x00040001); - MCHBAR8_AND(SBCTL3 + 3, ~0x80); - MCHBAR8_AND(CISDCTRL + 3, ~0x80); - MCHBAR16_AND(CICGDIS, ~0x1fff); - MCHBAR32_AND(SBCLKGATECTRL, ~0x0001ffff); - MCHBAR16_AND(HICLKGTCTL, ~0x03ff & 0x06); - MCHBAR32_AND_OR(HTCLKGTCTL, ~0xffffffff, 0x20); - MCHBAR8_AND(TSMISC, ~1); + mchbar32_and(PMMISC, (u32)~0x00040001); + mchbar8_and(SBCTL3 + 3, (u8)~0x80); + mchbar8_and(CISDCTRL + 3, (u8)~0x80); + mchbar16_and(CICGDIS, (u16)~0x1fff); + mchbar32_and(SBCLKGATECTRL, (u32)~0x0001ffff); + mchbar16_and(HICLKGTCTL, (u16)~0x03ff & 0x06); + mchbar32_and_or(HTCLKGTCTL, (u32)~0xffffffff, 0x20); + mchbar8_and(TSMISC, (u8)~1); MCHBAR8(C0WRDPYN) = s->selected_timings.CAS - 1 + 0x15; - MCHBAR16_AND_OR(CLOCKGATINGI, ~0x07fc, 0x0040); - MCHBAR16_AND_OR(CLOCKGATINGII, ~0x0fff, 0x0d00); - MCHBAR16_AND(CLOCKGATINGIII, ~0x0d80); + mchbar16_and_or(CLOCKGATINGI, (u16)~0x07fc, 0x0040); + mchbar16_and_or(CLOCKGATINGII, (u16)~0x0fff, 0x0d00); + mchbar16_and(CLOCKGATINGIII, (u16)~0x0d80); MCHBAR16(GTDPCGC + 2) = 0xffff; /* Sequencing */ @@ -2379,15 +2380,15 @@ MCHBAR32(PMDSLFRC) = (MCHBAR32(PMDSLFRC) & ~0x0001bff7) | 0x00000078; if (s->selected_timings.fsb_clock == FSB_CLOCK_667MHz) - MCHBAR16_AND_OR(PMMSPMRES, ~0x03ff, 0x00c8); + mchbar16_and_or(PMMSPMRES, (u16)~0x03ff, 0x00c8); else - MCHBAR16_AND_OR(PMMSPMRES, ~0x03ff, 0x0100); + mchbar16_and_or(PMMSPMRES, (u16)~0x03ff, 0x0100); j = (s->selected_timings.mem_clock == MEM_CLOCK_667MHz) ? 0 : 1; - MCHBAR32_AND_OR(PMCLKRC, ~0x01fff37f, 0x10810700); - MCHBAR8_AND_OR(PMPXPRC, ~0x07, 1); - MCHBAR8_AND(PMBAK, ~0x02); + mchbar32_and_or(PMCLKRC, (u32)~0x01fff37f, 0x10810700); + mchbar8_and_or(PMPXPRC, (u8)~0x07, 1); + mchbar8_and(PMBAK, (u8)~0x02); static const u16 ddr2lut[2][4][2] = { { @@ -2407,8 +2408,8 @@ MCHBAR16(C0C2REG) = 0x7a89; MCHBAR8(SHC2REGII) = 0xaa; MCHBAR16(SHC2REGII + 1) = ddr2lut[j][s->selected_timings.CAS - 3][1]; - MCHBAR16_AND_OR(SHC2REGI, ~0x7fff, ddr2lut[j][s->selected_timings.CAS - 3][0]); - MCHBAR16_AND_OR(CLOCKGATINGIII, ~0xf000, 0xf000); + mchbar16_and_or(SHC2REGI, (u16)~0x7fff, ddr2lut[j][s->selected_timings.CAS - 3][0]); + mchbar16_and_or(CLOCKGATINGIII, (u16)~0xf000, 0xf000); MCHBAR8(CSHWRIOBONUSX) = (MCHBAR8(CSHWRIOBONUSX) & ~0x77) | (4 << 4 | 4); reg32 = s->nodll ? 0x30000000 : 0; @@ -2416,72 +2417,72 @@ /* FIXME: Compacting this results in changes to the binary */ MCHBAR32(C0COREBONUS) = (MCHBAR32(C0COREBONUS) & ~0x0f000000) | 0x20000000 | reg32; - MCHBAR32_AND_OR(CLOCKGATINGI, ~0x00f00000, 0x00f00000); - MCHBAR32_AND_OR(CLOCKGATINGII - 1, ~0x001ff000, 0xbf << 20); - MCHBAR16_AND_OR(SHC3C4REG2, ~0x1f7f, (0x0b << 8) | (7 << 4) | 0x0b); + mchbar32_and_or(CLOCKGATINGI, (u32)~0x00f00000, 0x00f00000); + mchbar32_and_or(CLOCKGATINGII - 1, (u32)~0x001ff000, 0xbf << 20); + mchbar16_and_or(SHC3C4REG2, (u16)~0x1f7f, (0x0b << 8) | (7 << 4) | 0x0b); MCHBAR16(SHC3C4REG3) = 0x3264; - MCHBAR16_AND_OR(SHC3C4REG4, ~0x3f3f, (0x14 << 8) | 0x0a); + mchbar16_and_or(SHC3C4REG4, (u16)~0x3f3f, (0x14 << 8) | 0x0a); - MCHBAR32_OR(C1COREBONUS, 0x80002000); + mchbar32_or(C1COREBONUS, 0x80002000); } static void sdram_programddr(void) { - MCHBAR16_AND_OR(CLOCKGATINGII, ~0x03ff, 0x0100); - MCHBAR16_AND_OR(CLOCKGATINGIII, ~0x003f, 0x0010); - MCHBAR16_AND_OR(CLOCKGATINGI, ~0x7000, 0x2000); + mchbar16_and_or(CLOCKGATINGII, (u16)~0x03ff, 0x0100); + mchbar16_and_or(CLOCKGATINGIII, (u16)~0x003f, 0x0010); + mchbar16_and_or(CLOCKGATINGI, (u16)~0x7000, 0x2000); - MCHBAR8_AND(CSHRPDCTL, ~0x0e); - MCHBAR8_AND(CSHRWRIOMLNS, ~0x0c); - MCHBAR8_AND(C0MISCCTLy(0), ~0x0e); - MCHBAR8_AND(C0MISCCTLy(1), ~0x0e); - MCHBAR8_AND(C0MISCCTLy(2), ~0x0e); - MCHBAR8_AND(C0MISCCTLy(3), ~0x0e); - MCHBAR8_AND(C0MISCCTLy(4), ~0x0e); - MCHBAR8_AND(C0MISCCTLy(5), ~0x0e); - MCHBAR8_AND(C0MISCCTLy(6), ~0x0e); - MCHBAR8_AND(C0MISCCTLy(7), ~0x0e); - MCHBAR8_AND(CSHRWRIOMLNS, ~0x02); + mchbar8_and(CSHRPDCTL, (u8)~0x0e); + mchbar8_and(CSHRWRIOMLNS, (u8)~0x0c); + mchbar8_and(C0MISCCTLy(0), (u8)~0x0e); + mchbar8_and(C0MISCCTLy(1), (u8)~0x0e); + mchbar8_and(C0MISCCTLy(2), (u8)~0x0e); + mchbar8_and(C0MISCCTLy(3), (u8)~0x0e); + mchbar8_and(C0MISCCTLy(4), (u8)~0x0e); + mchbar8_and(C0MISCCTLy(5), (u8)~0x0e); + mchbar8_and(C0MISCCTLy(6), (u8)~0x0e); + mchbar8_and(C0MISCCTLy(7), (u8)~0x0e); + mchbar8_and(CSHRWRIOMLNS, (u8)~0x02); - MCHBAR16_AND(CSHRMISCCTL, ~0x0400); - MCHBAR16_AND(CLOCKGATINGIII, ~0x0dc0); - MCHBAR8_AND(C0WRDPYN, ~0x80); - MCHBAR32_AND(C0COREBONUS, ~(1 << 22)); - MCHBAR16_AND(CLOCKGATINGI, ~0x80fc); - MCHBAR16_AND(CLOCKGATINGII, ~0x0c00); + mchbar16_and(CSHRMISCCTL, (u16)~0x0400); + mchbar16_and(CLOCKGATINGIII, (u16)~0x0dc0); + mchbar8_and(C0WRDPYN, (u8)~0x80); + mchbar32_and(C0COREBONUS, (u32)~(1 << 22)); + mchbar16_and(CLOCKGATINGI, (u16)~0x80fc); + mchbar16_and(CLOCKGATINGII, (u16)~0x0c00); - MCHBAR8_AND(CSHRPDCTL, ~0x0d); - MCHBAR8_AND(C0MISCCTLy(0), ~1); - MCHBAR8_AND(C0MISCCTLy(1), ~1); - MCHBAR8_AND(C0MISCCTLy(2), ~1); - MCHBAR8_AND(C0MISCCTLy(3), ~1); - MCHBAR8_AND(C0MISCCTLy(4), ~1); - MCHBAR8_AND(C0MISCCTLy(5), ~1); - MCHBAR8_AND(C0MISCCTLy(6), ~1); - MCHBAR8_AND(C0MISCCTLy(7), ~1); + mchbar8_and(CSHRPDCTL, (u8)~0x0d); + mchbar8_and(C0MISCCTLy(0), (u8)~1); + mchbar8_and(C0MISCCTLy(1), (u8)~1); + mchbar8_and(C0MISCCTLy(2), (u8)~1); + mchbar8_and(C0MISCCTLy(3), (u8)~1); + mchbar8_and(C0MISCCTLy(4), (u8)~1); + mchbar8_and(C0MISCCTLy(5), (u8)~1); + mchbar8_and(C0MISCCTLy(6), (u8)~1); + mchbar8_and(C0MISCCTLy(7), (u8)~1); - MCHBAR32_AND_OR(C0STATRDCTRL, ~0x00700000, 3 << 20); - MCHBAR32_AND(C0COREBONUS, ~0x00100000); - MCHBAR8_OR(C0DYNSLVDLLEN, 0x1e); - MCHBAR8_OR(C0DYNSLVDLLEN2, 0x03); - MCHBAR32_AND_OR(SHCYCTRKCKEL, ~0x0c000000, 0x04000000); - MCHBAR16_OR(C0STATRDCTRL, 0x6000); - MCHBAR32_OR(C0CKECTRL, 0x00010000); - MCHBAR8_OR(C0COREBONUS, 0x10); - MCHBAR32_OR(CLOCKGATINGI - 1, 0xf << 24); - MCHBAR8_OR(CSHWRIOBONUS, 0x07); - MCHBAR8_OR(C0DYNSLVDLLEN, 0xc0); - MCHBAR8_OR(SHC2REGIII, 7); - MCHBAR16_AND_OR(SHC2MINTM, ~0xffff, 0x0080); - MCHBAR8_AND_OR(SHC2IDLETM, ~0xff, 0x10); - MCHBAR16_OR(C0COREBONUS, 0x01e0); - MCHBAR8_OR(CSHWRIOBONUS, 0x18); - MCHBAR8_OR(CSHRMSTDYNDLLENB, 0x0d); - MCHBAR16_OR(SHC3C4REG1, 0x0a3f); - MCHBAR8_OR(C0STATRDCTRL, 3); - MCHBAR8_AND_OR(C0REFRCTRL2, ~0xff, 0x4a); - MCHBAR8_AND(C0COREBONUS + 4, ~0x60); - MCHBAR16_OR(C0DYNSLVDLLEN, 0x0321); + mchbar32_and_or(C0STATRDCTRL, (u32)~0x00700000, 3 << 20); + mchbar32_and(C0COREBONUS, (u32)~0x00100000); + mchbar8_or(C0DYNSLVDLLEN, 0x1e); + mchbar8_or(C0DYNSLVDLLEN2, 0x03); + mchbar32_and_or(SHCYCTRKCKEL, (u32)~0x0c000000, 0x04000000); + mchbar16_or(C0STATRDCTRL, 0x6000); + mchbar32_or(C0CKECTRL, 0x00010000); + mchbar8_or(C0COREBONUS, 0x10); + mchbar32_or(CLOCKGATINGI - 1, 0xf << 24); + mchbar8_or(CSHWRIOBONUS, 0x07); + mchbar8_or(C0DYNSLVDLLEN, 0xc0); + mchbar8_or(SHC2REGIII, 7); + mchbar16_and_or(SHC2MINTM, (u16)~0xffff, 0x0080); + mchbar8_and_or(SHC2IDLETM, (u8)~0xff, 0x10); + mchbar16_or(C0COREBONUS, 0x01e0); + mchbar8_or(CSHWRIOBONUS, 0x18); + mchbar8_or(CSHRMSTDYNDLLENB, 0x0d); + mchbar16_or(SHC3C4REG1, 0x0a3f); + mchbar8_or(C0STATRDCTRL, 3); + mchbar8_and_or(C0REFRCTRL2, (u8)~0xff, 0x4a); + mchbar8_and(C0COREBONUS + 4, (u8)~0x60); + mchbar16_or(C0DYNSLVDLLEN, 0x0321); } static void sdram_programdqdqs(struct sysinfo *s) @@ -2541,13 +2542,13 @@ if ((tmaxunmask >= reg32) && tmaxpi >= dqdqs_delay) { if (repeat == 2) { - MCHBAR32_AND(C0COREBONUS, ~(1 << 23)); + mchbar32_and(C0COREBONUS, (u32)~(1 << 23)); } feature = 1; repeat = 0; } else { repeat--; - MCHBAR32_OR(C0COREBONUS, 1 << 23); + mchbar32_or(C0COREBONUS, 1 << 23); cwb = 2 * mdclk; } } @@ -2556,10 +2557,10 @@ MCHBAR8(CLOCKGATINGI) = MCHBAR8(CLOCKGATINGI) & ~0x3; return; } - MCHBAR8_OR(CLOCKGATINGI, 3); - MCHBAR16_AND_OR(CLOCKGATINGIII, ~0xf000, pimdclk << 12); - MCHBAR8_AND_OR(CSHWRIOBONUSX, ~0x77, (push << 4) | push); - MCHBAR32_AND_OR(C0COREBONUS, ~0x0f000000, 0x03000000); + mchbar8_or(CLOCKGATINGI, 3); + mchbar16_and_or(CLOCKGATINGIII, (u16)~0xf000, pimdclk << 12); + mchbar8_and_or(CSHWRIOBONUSX, (u8)~0x77, (push << 4) | push); + mchbar32_and_or(C0COREBONUS, (u32)~0x0f000000, 0x03000000); } /** @@ -2592,7 +2593,7 @@ /* Enable HPET */ enable_hpet(); - MCHBAR16_OR(CPCTL, 1 << 15); + mchbar16_or(CPCTL, 1 << 15); sdram_clk_crossing(&si); @@ -2627,16 +2628,16 @@ PRINTK_DEBUG("Done mmap\n"); /* Enable DDR IO buffer */ - MCHBAR8_AND_OR(C0IOBUFACTCTL, ~0x3f, 0x08); - MCHBAR8_OR(C0RSTCTL, 1); + mchbar8_and_or(C0IOBUFACTCTL, (u8)~0x3f, 0x08); + mchbar8_or(C0RSTCTL, 1); sdram_rcompupdate(&si); PRINTK_DEBUG("Done RCOMP update\n"); - MCHBAR8_OR(HIT4, 2); + mchbar8_or(HIT4, 2); if (si.boot_path != BOOT_PATH_RESUME) { - MCHBAR32_OR(C0CKECTRL, 1 << 27); + mchbar32_or(C0CKECTRL, 1 << 27); sdram_jedecinit(&si); PRINTK_DEBUG("Done MRS\n"); @@ -2649,7 +2650,7 @@ PRINTK_DEBUG("Done zqcl\n"); if (si.boot_path != BOOT_PATH_RESUME) { - MCHBAR32_OR(C0REFRCTRL2, 3 << 30); + mchbar32_or(C0REFRCTRL2, 3 << 30); } sdram_dradrb(&si); @@ -2680,7 +2681,7 @@ PRINTK_DEBUG("Done periodic RCOMP\n"); /* Set init done */ - MCHBAR32_OR(C0REFRCTRL2, 1 << 30); + mchbar32_or(C0REFRCTRL2, 1 << 30); /* Tell ICH7 that we're done */ pci_and_config8(PCI_DEV(0, 0x1f, 0), 0xa2, (u8)~(1 << 7)); -- To view, visit https://review.coreboot.org/c/coreboot/+/45517 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5fa844a8a13a75d6d802ca48f72c513bfa16d0a5 Gerrit-Change-Number: 45517 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

11 hours, 21 minutes

Change in coreboot[master]: [WIP] cpu/x86/mpinit: Serialize microcode updates for HT threads

by Patrick Rudolph (Code Review)

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44904 ) Change subject: [WIP] cpu/x86/mpinit: Serialize microcode updates for HT threads ...................................................................... [WIP] cpu/x86/mpinit: Serialize microcode updates for HT threads Update microcode using a core specific semaphore. The SDM and most of the BWGs suggest doing this. Change-Id: I89a01f6ff94e7d35f1feded3ddb0c43caf7c6c5d Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/x86/mp_init.c M src/cpu/x86/sipi_vector.S 2 files changed, 74 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/44904/1 diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 5807831..4c4de09 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -25,6 +25,7 @@ #include <symbols.h> #include <timer.h> #include <thread.h> +#include <lib.h> #include <security/intel/stm/SmmStm.h> @@ -97,6 +98,9 @@ uint32_t msr_count; uint32_t c_handler; atomic_t ap_count; + uint32_t microcode_lock_ht; /* 1 special microcode locking for Intel HT CPUs */ + uint32_t apic_core_id_mask; + uint32_t hyperthreading_lock[CONFIG_MAX_CPUS/2]; } __packed; /* This also needs to match the assembly code for saved MSR encoding. */ @@ -216,6 +220,31 @@ sp->stack_top = ALIGN_DOWN((uintptr_t)&_estack, CONFIG_STACK_SIZE); /* Adjust the stack top to take into account cpu_info. */ sp->stack_top -= sizeof(struct cpu_info); + sp->microcode_lock_ht = !!(cpuid_edx(1) & CPUID_FEAURE_HTT); + if (sp->microcode_lock_ht) { + struct cpuid_result result; + unsigned int core_ids, apic_ids, threads; + + apic_ids = 1; + if (cpuid_eax(0) >= 1) + apic_ids = (cpuid_ebx(1) >> 16) & 0xff; + if (apic_ids == 0) + apic_ids = 1; + + core_ids = 1; + if (cpuid_eax(0) >= 4) { + result = cpuid_ext(4, 0); + core_ids += (result.eax >> 26) & 0x3f; + } + + threads = (apic_ids / core_ids); + + sp->apic_core_id_mask = 1UL << log2_ceil(core_ids); + sp->apic_core_id_mask <<= log2_ceil(threads); + } else { + sp->apic_core_id_mask = 0; + } + memset(sp->hyperthreading_lock, 0, sizeof(sp->hyperthreading_lock)); } #define NUM_FIXED_MTRRS 11 diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S index ba1ecb7..abf0549 100644 --- a/src/cpu/x86/sipi_vector.S +++ b/src/cpu/x86/sipi_vector.S @@ -3,6 +3,7 @@ #include <cpu/x86/cr.h> #include <cpu/amd/mtrr.h> #include <cpu/x86/msr.h> +#include <cpu/x86/lapic_def.h> #include <arch/ram_segs.h> /* The SIPI vector is responsible for initializing the APs in the system. It @@ -33,6 +34,12 @@ .long 0 ap_count: .long 0 +apic_core_id_mask: +.long 0 +hyperthreading_lock: +.space CONFIG_MAX_CPUS/2 +microcode_lock_ht: +.long 0 #define CR0_CLEAR_FLAGS_CACHE_ENABLE (CR0_CD | CR0_NW) #define CR0_SET_FLAGS (CR0_CLEAR_FLAGS_CACHE_ENABLE | CR0_PE) @@ -115,6 +122,35 @@ test %edx, %edx jnz microcode_done + /* Determine if Hyper-Threading semaphore should be used */ + cmpl $0, microcode_lock_ht + je load_microcode + + /* Get this CPU's LAPIC ID */ + movl $(LOCAL_APIC_ADDR | LAPIC_ID), %esi + movl (%esi), %ecx + shr $24, %ecx + + movl apic_core_id_mask, %eax + andl %eax, %ecx +1: + bt $0, %eax + jc 1f + shr $1, %eax + shr $1, %ecx + jmp 1b +1: + /* ecx now contains the core ID */ + movl $(hyperthreading_lock), %ebx + shl $2, %ecx + addl %ecx, %ebx + +lock_ht_semaphore: + /* Lock the core specific semaphore */ + lock bts $0, (%ebx) + jc lock_ht_semaphore + jmp load_microcode + /* Determine if parallel microcode loading is allowed. */ cmpl $0xffffffff, microcode_lock je load_microcode @@ -136,6 +172,15 @@ wrmsr popa + /* Determine if Hyper-Threading semaphore should be used */ + cmpl $0, microcode_lock_ht + jne 1f + + xor %eax, %eax + mov %eax, (%ebx) + je microcode_done + +1: /* Unconditionally unlock microcode loading. */ cmpl $0xffffffff, microcode_lock je microcode_done -- To view, visit https://review.coreboot.org/c/coreboot/+/44904 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I89a01f6ff94e7d35f1feded3ddb0c43caf7c6c5d Gerrit-Change-Number: 44904 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

11 hours, 28 minutes

Change in coreboot[master]: util/kconfig: Uprev to Linux 5.3's kconfig

by Patrick Georgi (Code Review)

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37152 ) Change subject: util/kconfig: Uprev to Linux 5.3's kconfig ...................................................................... util/kconfig: Uprev to Linux 5.3's kconfig This was originally several commits that had to be squashed into one because the intermediate states weren't able to build coreboot: - one to remove everything that wasn't our own code, leaving only regex.[ch], toada.c, description.md and Makefile.inc - one to copy in Linux 5.3's scripts/kconfig and adapt Makefile.inc to make the original Makefile work again. TODO: - more commits that bring back our modifications, both directly in the code and as a diff in a patches/ subdirectory. Change-Id: Ia0e8fe4e9022b278f34ab113a433ef4d45e5c355 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M util/kconfig/Makefile M util/kconfig/Makefile.inc D util/kconfig/POTFILES.in D util/kconfig/check.sh M util/kconfig/conf.c M util/kconfig/confdata.c M util/kconfig/expr.c M util/kconfig/expr.h A util/kconfig/gconf-cfg.sh M util/kconfig/gconf.c M util/kconfig/images.c A util/kconfig/images.h D util/kconfig/kxgettext.c A util/kconfig/lexer.l M util/kconfig/list.h M util/kconfig/lkc.h M util/kconfig/lkc_proto.h D util/kconfig/lxdialog/.gitignore M util/kconfig/lxdialog/BIG.FAT.WARNING D util/kconfig/lxdialog/check-lxdialog.sh M util/kconfig/lxdialog/checklist.c M util/kconfig/lxdialog/dialog.h M util/kconfig/lxdialog/inputbox.c M util/kconfig/lxdialog/menubox.c M util/kconfig/lxdialog/textbox.c M util/kconfig/lxdialog/util.c M util/kconfig/lxdialog/yesno.c A util/kconfig/mconf-cfg.sh M util/kconfig/mconf.c M util/kconfig/menu.c A util/kconfig/merge_config.sh A util/kconfig/nconf-cfg.sh M util/kconfig/nconf.c M util/kconfig/nconf.gui.c M util/kconfig/nconf.h R util/kconfig/parser.y A util/kconfig/preprocess.c A util/kconfig/qconf-cfg.sh M util/kconfig/qconf.cc M util/kconfig/qconf.h A util/kconfig/streamline_config.pl M util/kconfig/symbol.c M util/kconfig/util.c D util/kconfig/zconf.gperf D util/kconfig/zconf.hash.c_shipped D util/kconfig/zconf.l D util/kconfig/zconf.lex.c_shipped D util/kconfig/zconf.tab.c_shipped 48 files changed, 4,250 insertions(+), 8,203 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/37152/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/37152 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia0e8fe4e9022b278f34ab113a433ef4d45e5c355 Gerrit-Change-Number: 37152 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

11 hours, 59 minutes

Change in ...coreboot[master]: soc/intel/denverton_ns: Rewrite pmutil using pmclib

by Patrick Georgi (Code Review)

Hello Julien Viard de Galbert, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31072 to review the following change. Change subject: soc/intel/denverton_ns: Rewrite pmutil using pmclib ...................................................................... soc/intel/denverton_ns: Rewrite pmutil using pmclib Change-Id: I13ab94e7440886f77e3091b16e50e48b17151751 Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net> --- M src/soc/intel/denverton_ns/include/soc/pm.h M src/soc/intel/denverton_ns/pmutil.c M src/soc/intel/denverton_ns/smihandler.c M src/soc/intel/denverton_ns/smm.c 4 files changed, 33 insertions(+), 184 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/31072/1 diff --git a/src/soc/intel/denverton_ns/include/soc/pm.h b/src/soc/intel/denverton_ns/include/soc/pm.h index 09ce158..0aab0e2 100644 --- a/src/soc/intel/denverton_ns/include/soc/pm.h +++ b/src/soc/intel/denverton_ns/include/soc/pm.h @@ -47,18 +47,6 @@ struct chipset_power_state *fill_power_state(void); /* Power Management Utility Functions. */ -uint32_t clear_smi_status(void); -uint16_t clear_pm1_status(void); -uint32_t clear_tco_status(void); -uint32_t clear_gpe_status(void); void clear_pmc_status(void); -void enable_smi(uint32_t mask); -void disable_smi(uint32_t mask); -void enable_pm1(uint16_t events); -void enable_pm1_control(uint32_t mask); -void disable_pm1_control(uint32_t mask); -void enable_gpe(uint32_t mask); -void disable_gpe(uint32_t mask); -void disable_all_gpe(void); #endif /* _DENVERTON_NS_PM_H_ */ diff --git a/src/soc/intel/denverton_ns/pmutil.c b/src/soc/intel/denverton_ns/pmutil.c index ccf0d95..344f8b9 100644 --- a/src/soc/intel/denverton_ns/pmutil.c +++ b/src/soc/intel/denverton_ns/pmutil.c @@ -19,29 +19,12 @@ #include <arch/io.h> #include <console/console.h> +#include <intelblocks/pmclib.h> #include <soc/iomap.h> #include <soc/soc_util.h> #include <soc/pm.h> -static void print_num_status_bits(int num_bits, uint32_t status, - const char *const bit_names[]) -{ - int i; - - if (!status) - return; - - for (i = num_bits - 1; i >= 0; i--) { - if (status & (1 << i)) { - if (bit_names[i]) - printk(BIOS_DEBUG, "%s ", bit_names[i]); - else - printk(BIOS_DEBUG, "BIT%d ", i); - } - } -} - -static uint32_t print_smi_status(uint32_t smi_sts) +const char *const *soc_smi_sts_array(size_t *a) { static const char *const smi_sts_bits[] = { [2] = "BIOS", @@ -67,93 +50,11 @@ [31] = "LEGACY_USB3", }; - if (!smi_sts) - return 0; - - printk(BIOS_DEBUG, "SMI_STS: "); - print_num_status_bits(ARRAY_SIZE(smi_sts_bits), smi_sts, smi_sts_bits); - printk(BIOS_DEBUG, "\n"); - - return smi_sts; + *a = ARRAY_SIZE(smi_sts_bits); + return smi_sts_bits; } -static uint32_t reset_smi_status(void) -{ - uint16_t pmbase = get_pmbase(); - uint32_t smi_sts = inl((uint16_t)(pmbase + SMI_STS)); - outl(smi_sts, (uint16_t)(pmbase + SMI_STS)); - return smi_sts; -} - -uint32_t clear_smi_status(void) { return print_smi_status(reset_smi_status()); } - -void enable_smi(uint32_t mask) -{ - uint16_t pmbase = get_pmbase(); - uint32_t smi_en = inl((uint16_t)(pmbase + SMI_EN)); - smi_en |= mask; - outl(smi_en, (uint16_t)(pmbase + SMI_EN)); -} - -void disable_smi(uint32_t mask) -{ - uint16_t pmbase = get_pmbase(); - uint32_t smi_en = inl((uint16_t)(pmbase + SMI_EN)); - smi_en &= ~mask; - outl(smi_en, (uint16_t)(pmbase + SMI_EN)); -} - -void enable_pm1_control(uint32_t mask) -{ - uint16_t pmbase = get_pmbase(); - uint32_t pm1_cnt = inl((uint16_t)(pmbase + PM1_CNT)); - pm1_cnt |= mask; - outl(pm1_cnt, (uint16_t)(pmbase + PM1_CNT)); -} - -void disable_pm1_control(uint32_t mask) -{ - uint16_t pmbase = get_pmbase(); - uint32_t pm1_cnt = inl((uint16_t)(pmbase + PM1_CNT)); - pm1_cnt &= ~mask; - outl(pm1_cnt, (uint16_t)(pmbase + PM1_CNT)); -} - -static uint16_t reset_pm1_status(void) -{ - uint16_t pmbase = get_pmbase(); - uint16_t pm1_sts = inw((uint16_t)(pmbase + PM1_STS)); - outw(pm1_sts, (uint16_t)(pmbase + PM1_STS)); - return pm1_sts; -} - -static uint16_t print_pm1_status(uint16_t pm1_sts) -{ - static const char *const pm1_sts_bits[] = { - [0] = "TMROF", [4] = "BM", [5] = "GBL", - [8] = "PWRBTN", [10] = "RTC", [11] = "PRBTNOR", - [15] = "WAK", - }; - - if (!pm1_sts) - return 0; - - printk(BIOS_SPEW, "PM1_STS: "); - print_num_status_bits(ARRAY_SIZE(pm1_sts_bits), pm1_sts, pm1_sts_bits); - printk(BIOS_SPEW, "\n"); - - return pm1_sts; -} - -uint16_t clear_pm1_status(void) { return print_pm1_status(reset_pm1_status()); } - -void enable_pm1(uint16_t events) -{ - uint16_t pmbase = get_pmbase(); - outw(events, (uint16_t)(pmbase + PM1_EN)); -} - -static uint32_t print_tco_status(uint32_t tco_sts) +const char *const *soc_tco_sts_array(size_t *a) { static const char *const tco_sts_bits[] = { [0] = "NMI2SMI", [1] = "OS_TCO_SMI", @@ -164,17 +65,11 @@ [17] = "SECOND_TO", [20] = "SMLINK_SLV_SMI", }; - if (!tco_sts) - return 0; - - printk(BIOS_DEBUG, "TCO_STS: "); - print_num_status_bits(ARRAY_SIZE(tco_sts_bits), tco_sts, tco_sts_bits); - printk(BIOS_DEBUG, "\n"); - - return tco_sts; + *a = ARRAY_SIZE(tco_sts_bits); + return tco_sts_bits; } -static uint32_t reset_tco_status(void) +uint32_t soc_reset_tco_status(void) { uint16_t tcobase = get_tcobase(); uint32_t tco_sts = inl((uint16_t)(tcobase + TCO1_STS)); @@ -184,35 +79,7 @@ return tco_sts & tco_en; } -uint32_t clear_tco_status(void) { return print_tco_status(reset_tco_status()); } - -void enable_gpe(uint32_t mask) -{ - uint16_t pmbase = get_pmbase(); - uint32_t gpe0_en = inl((uint16_t)(pmbase + GPE0_EN(GPE_STD))); - gpe0_en |= mask; - outl(gpe0_en, (uint16_t)(pmbase + GPE0_EN(GPE_STD))); -} - -void disable_gpe(uint32_t mask) -{ - uint16_t pmbase = get_pmbase(); - uint32_t gpe0_en = inl((uint16_t)(pmbase + GPE0_EN(GPE_STD))); - gpe0_en &= ~mask; - outl(gpe0_en, (uint16_t)(pmbase + GPE0_EN(GPE_STD))); -} - -void disable_all_gpe(void) { disable_gpe(~0); } - -static uint32_t reset_gpe_status(void) -{ - uint16_t pmbase = get_pmbase(); - uint32_t gpe_sts = inl((uint16_t)(pmbase + GPE0_STS(GPE_STD))); - outl(gpe_sts, (uint16_t)(pmbase + GPE0_STS(GPE_STD))); - return gpe_sts; -} - -static uint32_t print_gpe_sts(uint32_t gpe_sts) +const char *const *soc_std_gpe_sts_array(size_t *a) { static const char *const gpe_sts_bits[] = { [0] = "GPIO_0", [1] = "GPIO_1", @@ -233,16 +100,8 @@ [30] = "GPIO_30", [31] = "GPIO_31", }; - if (!gpe_sts) - return gpe_sts; - - printk(BIOS_DEBUG, "GPE0a_STS: "); - print_num_status_bits(ARRAY_SIZE(gpe_sts_bits), gpe_sts, gpe_sts_bits); - printk(BIOS_DEBUG, "\n"); - - return gpe_sts; + *a = ARRAY_SIZE(gpe_sts_bits); + return gpe_sts_bits; } -uint32_t clear_gpe_status(void) { return print_gpe_sts(reset_gpe_status()); } - void clear_pmc_status(void) { /* TODO */ } diff --git a/src/soc/intel/denverton_ns/smihandler.c b/src/soc/intel/denverton_ns/smihandler.c index 85f99d7..e1e7bc4 100644 --- a/src/soc/intel/denverton_ns/smihandler.c +++ b/src/soc/intel/denverton_ns/smihandler.c @@ -25,6 +25,7 @@ #include <device/pci_def.h> #include <elog.h> #include <intelblocks/fast_spi.h> +#include <intelblocks/pmclib.h> #include <spi-generic.h> #include <soc/iomap.h> #include <soc/soc_util.h> @@ -52,7 +53,7 @@ return 0; } -void southbridge_smi_set_eos(void) { enable_smi(EOS); } +void southbridge_smi_set_eos(void) { pmc_enable_smi(EOS); } global_nvs_t *smm_get_gnvs(void) { return gnvs; } @@ -98,7 +99,7 @@ uint16_t pmbase = get_pmbase(); /* First, disable further SMIs */ - disable_smi(SLP_SMI_EN); + pmc_disable_smi(SLP_SMI_EN); /* Figure out SLP_TYP */ reg32 = inl((uint16_t)(pmbase + PM1_CNT)); @@ -131,7 +132,7 @@ printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n"); /* Disable all GPE */ - disable_all_gpe(); + pmc_disable_all_gpe(); /* also iterates over all bridges on bus 0 */ busmaster_disable_on_bus(0); @@ -145,7 +146,7 @@ * event again. We need to set BIT13 (SLP_EN) though to make the * sleep happen. */ - enable_pm1_control(SLP_EN); + pmc_enable_pm1_control(SLP_EN); /* Make sure to stop executing code here for S3/S4/S5 */ if (slp_typ > 1) @@ -158,7 +159,7 @@ reg32 = inl((uint16_t)(pmbase + PM1_CNT)); if (reg32 & SCI_EN) { /* The OS is not an ACPI OS, so we set the state to S0 */ - disable_pm1_control(SLP_EN | SLP_TYP); + pmc_disable_pm1_control(SLP_EN | SLP_TYP); } } @@ -237,11 +238,11 @@ printk(BIOS_DEBUG, "P-state control\n"); break; case APM_CNT_ACPI_DISABLE: - disable_pm1_control(SCI_EN); + pmc_disable_pm1_control(SCI_EN); printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n"); break; case APM_CNT_ACPI_ENABLE: - enable_pm1_control(SCI_EN); + pmc_enable_pm1_control(SCI_EN); printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); break; case APM_CNT_FINALIZE: @@ -268,23 +269,23 @@ static void southbridge_smi_pm1(void) { - uint16_t pm1_sts = clear_pm1_status(); + uint16_t pm1_sts = pmc_clear_pm1_status(); /* While OSPM is not active, poweroff immediately * on a power button event. */ if (pm1_sts & PWRBTN_STS) { // power button pressed - disable_pm1_control(-1UL); - enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT)); + pmc_disable_pm1_control(-1UL); + pmc_enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT)); } } -static void southbridge_smi_gpe0(void) { clear_gpe_status(); } +static void southbridge_smi_gpe0(void) { pmc_clear_all_gpe_status(); } static void southbridge_smi_tco(void) { - uint32_t tco_sts = clear_tco_status(); + uint32_t tco_sts = pmc_clear_tco_status(); /* Any TCO event? */ if (!tco_sts) @@ -354,7 +355,7 @@ /* We need to clear the SMI status registers, or we won't see what's * happening in the following calls. */ - smi_sts = clear_smi_status(); + smi_sts = pmc_clear_smi_status(); /* Call SMI sub handler for each of the status bits */ for (i = 0; i < ARRAY_SIZE(southbridge_smi); i++) { diff --git a/src/soc/intel/denverton_ns/smm.c b/src/soc/intel/denverton_ns/smm.c index 9d3fa75..65d2499 100644 --- a/src/soc/intel/denverton_ns/smm.c +++ b/src/soc/intel/denverton_ns/smm.c @@ -23,6 +23,7 @@ #include <cpu/x86/smm.h> #include <string.h> +#include <intelblocks/pmclib.h> #include <soc/iomap.h> #include <soc/soc_util.h> #include <soc/pm.h> @@ -48,10 +49,10 @@ } /* Dump and clear status registers */ - clear_smi_status(); - clear_pm1_status(); - clear_tco_status(); - clear_gpe_status(); + pmc_clear_smi_status(); + pmc_clear_pm1_status(); + pmc_clear_tco_status(); + pmc_clear_all_gpe_status(); clear_pmc_status(); } @@ -60,8 +61,8 @@ printk(BIOS_DEBUG, "Enabling SMIs.\n"); /* Configure events Disable pcie wake. */ - enable_pm1(PWRBTN_EN | GBL_EN | PCIEXPWAK_DIS); - disable_gpe(PME_B0_EN); + pmc_enable_pm1(PWRBTN_EN | GBL_EN | PCIEXPWAK_DIS); + pmc_disable_std_gpe(PME_B0_EN); /* Enable SMI generation: * - on APMC writes (io 0xb2) @@ -71,7 +72,7 @@ * - on TCO events * - on microcontroller writes (io 0x62/0x66) */ - enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS); + pmc_enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS); } void smm_setup_structures(void *gnvs, void *tcg, void *smi1) -- To view, visit https://review.coreboot.org/c/coreboot/+/31072 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I13ab94e7440886f77e3091b16e50e48b17151751 Gerrit-Change-Number: 31072 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-MessageType: newchange

12 hours

Change in coreboot[master]: Documentation: Add documentation on jenkins builders

by Martin Roth (Code Review)

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43984 ) Change subject: Documentation: Add documentation on jenkins builders ...................................................................... Documentation: Add documentation on jenkins builders Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: I54a0204e7525a25f2fd717a73007b304aac67396 --- A Documentation/community/builders.md 1 file changed, 391 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/43984/1 diff --git a/Documentation/community/builders.md b/Documentation/community/builders.md new file mode 100644 index 0000000..bc35bcc --- /dev/null +++ b/Documentation/community/builders.md @@ -0,0 +1,391 @@ +# Jenkins builder setup and configuration + +## How to set up a new jenkins builder + +### Contact a jenkins admin + +Let a jenkins admin know that you’re interested in setting up a jenkins +build system. + +For a permanent build system, this should generally be a dedicated +machine that is not generally being used for other purposes. The +coreboot builds are very intensive. + +It's also best to be aware that although we don't know of any security +issues, the jenkins-node image is run with the privileged flag which +gives the container root access to the build machine. See +[this article](https://blog.trendmicro.com/trendlabs-security-intelligence/why-ru… +about why this is discouraged. + +It's recommended that you give an admin root access on your machine so +that they can reset it in case of a failure. This is not a requirement, +as the system can just be disabled until someone is available to fix any +issues. + +Currently active Jenkins admins: +* Patrick Georgi: + * Email: [patrick@georgi-clan.de](mailto:patrick@georgi-clan.de) + * IRC: pgeorgi + + +### Build Machine requirements + +For a builder, we need a fast system with lots of threads and plenty of +RAM. The builder builds and stores the git repos and output in tmpfs +along with the ccache save area, so if there isn't enough memory, the +builds will slow down because of smaller ccache areas and can run into +"out of storage space" errors. + +#### Current Build Machines + +To give an idea of what a suitable build machine might be, currently the +coreboot project has 3 active jenkins build machines. + +* Congenialbuilder - 128 threads, 256GiB RAM + * Fastest Passing coreboot gerrit build: 4 min, 30 sec + * Slowest Passing coreboot gerrit build: 9 min, 56 sec + + +* Gleeful builder - 64 thread, 64GiB RAM + * Fastest Passing coreboot gerrit build: 6 min, 6 sec + * Slowest Passing coreboot gerrit build, 34 min + + +* Ultron (9elements) - 48 threads, 128GiB RAM + * Fastest Passing coreboot gerrit build: 6 min, 32 sec + * Slowest Passing coreboot gerrit build: 44 min + + +### Jenkins Builds + +There are a number of builds handled by the coreboot jenkins builders, +for a number of different projects - coreboot, flashrom, memtest86+, +em100, etc. Many of these have builders for their current master branch +as well as gerrit and coverity builds. + +You can see all the builds here: +[https://qa.coreboot.org/](https://qa.coreboot.org/) + +Most of the time on the builders is taken up by the coreboot master and +gerrit builds. + +* [coreboot gerrit build](https://qa.coreboot.org/job/coreboot-gerrit/) +([Time trend](https://qa.coreboot.org/job/coreboot-gerrit/buildTimeTrend)) + + +* [coreboot master build](https://qa.coreboot.org/job/coreboot/) + ([Time trend](https://qa.coreboot.org/job/coreboot/buildTimeTrend)) + + +### Stress test the machine + +Test the machine to make sure that building won't stress the hardware +too much. Install stress-ng, then run the stress test for at least an +hour. + +On a system with 32 cores, it was tested with this command: + +``` +$ stress-ng --cpu 20 --io 6 --vm 6 --vm-bytes 1G --verify --metrics-brief -t 60m +``` + +You can watch the temperature with the sensors package or with ‘acpi -t’ +if your machine supports that. + +You can check for thermal throttling by running this command and seeing +if the values go down on any of the cores after it's been running for a +while. + +``` +$ while [ true ]; do clear; cat /proc/cpuinfo | grep 'cpu MHz' ; sleep 1; done +``` + +If the machine throttles or resets, you probably need to upgrade the +cooling system. + + +## jenkins-server docker installation + + +### Manual Installation + +If you’ve met all the above requirements, and an admin has agreed to set +up the builder in jenkins, you’re ready to go on to the next steps. + + +### Set up your network so jenkins can talk to the container + +Expose a local port through any firewalls you might have on your router. +This would generally be in the port forwarding section, and you'd just +forward a port (typically 49151) from the internet directly to the +builder’s IP address. + +You might also want to set up a port to forward to port 22 on your +machine and set up openssh so you can manage the machine remotely. + + +### Install and set up docker + +Install docker by following the directions on the docker site. These +instructions keep changing, so just check the latest information. + +[https://docs.docker.com/engine/install/](https://docs.docker.com/engine/install/) + + +#### Set up environment variables + +To make configuration and the later commands easier, these should go in +your shell's .rc file. Note that you only need to set them if you're +using something other than the default. + +``` +# Set the port used on your machine to connect to jenkins. +export COREBOOT_JENKINS_PORT=49151 + +# Set the revision of the container from docker hub +export DOCKER_COMMIT=65718760fa + +# Set the location of where the jenkins cache directory will be. +export COREBOOT_JENKINS_CACHE_DIR="/srv/docker/coreboot-builder/cache" + +# Set the name of the container +export COREBOOT_JENKINS_CONTAINER="coreboot_jenkins" +``` + +Make sure any variables needed are set in your environment before +continuing to the next step. + + +### Using the Makefile for docker installation + +From the coreboot directory, run + +``` +make -C util/docker help +``` + +This will show you the available targets and variables needed: + +``` +Commands for working with docker images: + coreboot-sdk - Build coreboot-sdk container + upload-coreboot-sdk - Upload coreboot-sdk to hub.docker.com + coreboot-jenkins-node - Build coreboot-jenkins-node container + upload-coreboot-jenkins-node - Upload coreboot-jenkins-node to hub.docker.com + doc.coreboot.org - Build doc.coreboot.org container + clean-coreboot-containers - Remove all docker coreboot containers + clean-coreboot-images - Remove all docker coreboot images + docker-clean - Remove docker coreboot containers & images + +Commands for using docker images + docker-build-coreboot - Build coreboot under coreboot-sdk + <BUILD_CMD=target> + docker-abuild - Run abuild under coreboot-sdk + <ABUILD_ARGS='-a -B'> + docker-what-jenkins-does - Run 'what-jenkins-does' target + docker-shell - Bash prompt in coreboot-jenkins-node + <USER=root or USER=coreboot> + docker-jenkins-server - Run coreboot-jenkins-node image (for server) + docker-jenkins-attach - Open shell in running jenkins server + docker-build-docs - Build the documentation + docker-livehtml-docs - Run sphinx-autobuild + +Variables: + COREBOOT_JENKINS_PORT=49151 + COREBOOT_JENKINS_CACHE_DIR=/srv/docker/coreboot-builder/cache + COREBOOT_JENKINS_CONTAINER=coreboot_jenkins + COREBOOT_IMAGE_TAG=f2741aa632f + DOCKER_COMMIT=65718760fa +``` + +### Set up the system for the jenkins builder + +As a regular user - *Not root*, run: + +``` +sudo mkdir -p ${COREBOOT_JENKINS_CACHE_DIR} +sudo mkdir -p ${COREBOOT_JENKINS_CCACHE_DIR} +sudo chown $(whoami):$(whoami) ${COREBOOT_JENKINS_CCACHE_DIR} +sudo chown $(whoami):$(whoami) ${COREBOOT_JENKINS_CACHE_DIR} +wget http://www.dediprog.com/save/78.rar/to/EM100Pro.rar +mv EM100Pro.rar ${COREBOOT_JENKINS_CACHE_DIR} +``` + +### Install the coreboot jenkins builder + +``` +make -C util/docker docker-jenkins-server +``` + +Your installation is complete on your side. + +### Tell the Admins that the machine is set up +Let the admins know that the builder is set up so they can set up the +machine profile on qa.coreboot.org. + +They need to know: +* Your external IP address or domain name. If you don’t have a static +IP, make sure you have a dynamic dns hostname configured. +* The port on your machine and firewall that’s exposed for jenkins: +`$COREBOOT_JENKINS_PORT` +* The core count of the machine. +* How much memory is available on the machine. This helps determine +the amount of memory used for ccache. + + +### First build +On the first build after a machine is reset, it will frequently take +20-25 minutes to do the entire what-jenkins-does build while the ccache +is getting filled up and the entire coreboot repo gets downloaded. As +the ccache gets populated, the build time will drop. + + +## Additional Information + + +### How to log in to the docker instance for debugging +``` + $ make -C util/docker docker-jenkins-attach + $ su coreboot + $ cd ~/slave-root/workspace + $ bash +``` + + +WARNING: This should not be used to make changes to the build system, +but just to debug issues. Changes to the build system are highly +discouraged as it leads to situations where patches can pass the build +testing on one builder and fail on another builder. Any changes that are +made in the image will be lost on the next update, so if you +accidentally change something, you can remove the containers and images +and update to get a fresh installation. + + +### How to download containers/images for a fresh installation and remove old containers + +To delete the old containers & images: + +``` +$ docker stop $COREBOOT_JENKINS_CONTAINER +$ docker rm $COREBOOT_JENKINS_CONTAINER +$ docker images # lists all existing images +$ docker rmi XXXX # Use the image ID found in the above command. +``` + +To get and run the new coreboot-jenkins image, change the value in the +`DOCKER_COMMIT` variable to the new image value. + +``` +$ make -C util/docker docker-jenkins-server +``` + +#### Getting ready to push the docker images + +Set up an account on hub.docker.com + +Get an admin to add the account to the coreboot team on hub.docker.com + +[https://hub.docker.com/u/coreboot/dashboard/teams/?team=owners](https://hub.docker.com/u/coreboot/dashboard/teams/?team=owners) + +Make sure your credentials are configured on your host machine by +running + +``` +$ docker login +``` + +This will prompt you for your docker username, password, and your email +address, and write out to ~/.docker/config.json. Without this file, you +won’t be able to push the images. + +#### Updating the Dockerfiles: + +The coreboot-sdk Dockerfile will need to be updated when any additional +dependencies are added. Both the coreboot-sdk and the +coreboot-jenkins-node Dockerfiles will need to be updated to the new +version number and git commit id anytime the toolchain is updated. Both +files are stored in the coreboot repo under coreboot/util/docker. + +Read the [dockerfile best practices](https://docs.docker.com/v1.8/articles/dockerfile_best-practices/) +page before updating the files. + +#### Rebuilding the coreboot-sdk docker image to update the toolchain: + +``` +$ make -C util/docker coreboot-sdk +``` + +This takes a relatively long time. + +#### Test the coreboot-sdk docker image: + +There are two methods of running the docker image - interactively as a +shell, or doing the build directly. Running interactively as a shell is +useful for early testing, because it allows you to update the image +(without any changes getting saved) and re-test builds. This saves the +time of having to rebuild the image for every issue you find. + +#### Running the docker image interactively: + +Run: + +``` +$ make -C util/docker docker-jenkins-server +$ make -C util/docker docker-jenkins-attach +``` + +#### Running the build directly: + +From the coreboot directory: + +``` +$ make -C util/docker docker-build-coreboot +``` + +You’ll also want to test building the other projects and payloads: +ChromeEC, flashrom, memtest86+, em100, Grub2, SeaBIOS, iPXE, coreinfo, +nvramcui, tint... + +#### Pushing the coreboot-sdk image to hub.docker.com for use: + +When you’re satisfied with the testing, push the coreboot-sdk image to +the hub.docker.com + +``` +$ make -C util/docker upload-coreboot-sdk +``` + +#### Building and pushing the coreboot-jenkins-node docker image: + +This docker image is pretty simple, so there’s not really any testing +that needs to be done. + +``` +$ make -C util/docker coreboot-jenkins-node +$ make -C util/docker upload-coreboot-jenkins-node +``` + +### Coverity Setup + +To run coverity jobs, the builder needs to have the tools available, and +to be marked as a coverity builder. + + +#### Set up the Coverity tools + +Download the Linux-64 coverity build tool and decompress it into your +cache directory as defined by the `$COREBOOT_JENKINS_CACHE_DIR` variable + +[https://scan.coverity.com/download](https://scan.coverity.com/download) + +Rename the directory from its original name +(cov-analysis-linux64-7.7.0.4) to ‘coverity’, or better, create a +symlink: + +``` +ln -s cov-analysis-linux64-7.7.0.4 coverity +``` + + +Let the admins know that the ‘coverity’ label can be added to the +builder. -- To view, visit https://review.coreboot.org/c/coreboot/+/43984 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54a0204e7525a25f2fd717a73007b304aac67396 Gerrit-Change-Number: 43984 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

14 hours, 44 minutes

Change in coreboot[master]: nb/intel/i945/acpi: COnvert igd.asl to ASL+ Syntax

by HAOUAS Elyes (Code Review)

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45273 ) Change subject: nb/intel/i945/acpi: COnvert igd.asl to ASL+ Syntax ...................................................................... nb/intel/i945/acpi: COnvert igd.asl to ASL+ Syntax Change-Id: Id0c3063b5a448fee4bcf283e56e7dc2008edcf7c Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/acpi/igd.asl 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/45273/1 diff --git a/src/northbridge/intel/i945/acpi/igd.asl b/src/northbridge/intel/i945/acpi/igd.asl index 5258c52..43662d1 100644 --- a/src/northbridge/intel/i945/acpi/igd.asl +++ b/src/northbridge/intel/i945/acpi/igd.asl @@ -28,7 +28,7 @@ Method (XBCM, 1, NotSerialized) { - Store (Or(ShiftLeft (Arg0, 4), 0xf), ^^DSPC.BRTC) + ^^DSPC.BRTC = ((Arg0 << 0x04) | 0x0F) #ifdef SMI_SAVE_CMOS Trap(SMI_SAVE_CMOS) #endif @@ -36,8 +36,8 @@ Method (XBQC, 0, NotSerialized) { - Store (^^DSPC.BRTC, Local0) - ShiftRight (Local0, 4, Local0) + Local0 = ^^DSPC.BRTC + Local0 >>= 4 Return (Local0) } #include <drivers/intel/gma/acpi/common.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/45273 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id0c3063b5a448fee4bcf283e56e7dc2008edcf7c Gerrit-Change-Number: 45273 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

16 hours, 37 minutes

Change in coreboot[master]: soc/mediatek/mt8192: Do dramc analog init setting

by CK HU (Code Review)

Hello Duan huayang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44727 to review the following change. Change subject: soc/mediatek/mt8192: Do dramc analog init setting ...................................................................... soc/mediatek/mt8192: Do dramc analog init setting Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> Change-Id: I53b30a2bbed5acb363f85f7cbc7f255fdbc52304 --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/dramc_ana_init_config.c M src/soc/mediatek/mt8192/dramc_pi_basic_api.c A src/soc/mediatek/mt8192/dramc_subsys_config.c M src/soc/mediatek/mt8192/emi.c 5 files changed, 1,411 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/44727/1 diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index bfa3316..e3463cd 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -17,6 +17,7 @@ romstage-y += ../common/cbmem.c romstage-y += dramc_pi_main.c dramc_pi_basic_api.c dramc_pi_calibration_api.c dramc_utility.c dramc_dvfs.c dramc_tracking.c +romstage-y += dramc_subsys_config.c dramc_ana_init_config.c romstage-y += emi.c romstage-y += flash_controller.c romstage-y += ../common/gpio.c gpio.c diff --git a/src/soc/mediatek/mt8192/dramc_ana_init_config.c b/src/soc/mediatek/mt8192/dramc_ana_init_config.c new file mode 100644 index 0000000..0fd3a9a --- /dev/null +++ b/src/soc/mediatek/mt8192/dramc_ana_init_config.c @@ -0,0 +1,1242 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/dramc_pi_api.h> +#include <soc/dramc_register.h> + +static void suspend_on(void) +{ + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_lp_ctrl0, + B0_LP_CTRL0_RG_ARDMSUS_10_B0, 0); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_lp_ctrl0, + B1_LP_CTRL0_RG_ARDMSUS_10_B1, 0); + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.ca_lp_ctrl0, + CA_LP_CTRL0_RG_ARDMSUS_10_CA, 0); + dramc_set_broadcast(DRAMC_BROADCAST_ON); +} + +void resetb_pull_dn(void) +{ + SET32_BITFIELDS(&ch[0].phy_ao.ca_cmd11, + CA_CMD11_RG_RRESETB_DRVP, 1, + CA_CMD11_RG_RRESETB_DRVN, 1, + CA_CMD11_RG_TX_RRESETB_DDR3_SEL, 1, + CA_CMD11_RG_TX_RRESETB_PULL_DN, 1); + SET32_BITFIELDS(&ch[0].phy_ao.misc_ctrl1, + MISC_CTRL1_R_DMRRESETB_I_OPT, 1); + SET32_BITFIELDS(&ch[0].phy_ao.misc_ctrl1, + MISC_CTRL1_R_DMDA_RRESETB_E, 1); + SET32_BITFIELDS(&ch[0].phy_ao.ca_cmd11, + CA_CMD11_RG_TX_RRESETB_PULL_DN, 0); +} + +static void spm_control(ana_top_config *a_cfg) +{ + u8 new_8x_mode = a_cfg->new_8x_mode; + + SET32_BITFIELDS(&ch[0].phy_ao.misc_lp_ctrl, + MISC_LP_CTRL_RG_ARDMSUS_10_LP_SEL, 1, + MISC_LP_CTRL_RG_RIMP_DMSUS_10_LP_SEL, 1, + MISC_LP_CTRL_RG_RRESETB_LP_SEL, 1, + MISC_LP_CTRL_RG_RPHYPLL_RESETB_LP_SEL, 1, + MISC_LP_CTRL_RG_RPHYPLL_EN_LP_SEL, 1, + MISC_LP_CTRL_RG_RCLRPLL_EN_LP_SEL, 1, + MISC_LP_CTRL_RG_RPHYPLL_ADA_MCK8X_EN_LP_SEL, 1, + MISC_LP_CTRL_RG_RPHYPLL_AD_MCK8X_EN_LP_SEL, 1, + MISC_LP_CTRL_RG_RPHYPLL_TOP_REV_0_LP_SEL, 1, + MISC_LP_CTRL_RG_SC_ARPI_RESETB_8X_SEQ_LP_SEL, new_8x_mode, + MISC_LP_CTRL_RG_ADA_MCK8X_8X_SEQ_LP_SEL, new_8x_mode, + MISC_LP_CTRL_RG_AD_MCK8X_8X_SEQ_LP_SEL, new_8x_mode, + MISC_LP_CTRL_RG_MIDPI_EN_8X_SEQ_LP_SEL, new_8x_mode, + MISC_LP_CTRL_RG_MIDPI_CKDIV4_EN_8X_SEQ_LP_SEL, new_8x_mode, + MISC_LP_CTRL_RG_MCK8X_CG_SRC_LP_SEL, new_8x_mode, + MISC_LP_CTRL_RG_MCK8X_CG_SRC_AND_LP_SEL, new_8x_mode); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_lp_ctrl0, + B0_LP_CTRL0_RG_ARDMSUS_10_B0_LP_SEL, 1, + B0_LP_CTRL0_RG_ARDQ_RESETB_B0_LP_SEL, 1, + B0_LP_CTRL0_RG_ARPI_RESETB_B0_LP_SEL, 1, + B0_LP_CTRL0_RG_B0_MS_SLV_LP_SEL, 0, + B0_LP_CTRL0_RG_ARDLL_PHDET_EN_B0_LP_SEL, 1, + B0_LP_CTRL0_RG_RX_ARDQ_BIAS_EN_B0_LP_SEL, 0, + B0_LP_CTRL0_DA_ARPI_CG_MCK_B0_LP_SEL, 1, + B0_LP_CTRL0_DA_ARPI_CG_MCK_FB2DLL_B0_LP_SEL, 1, + B0_LP_CTRL0_DA_ARPI_CG_MCTL_B0_LP_SEL, 1, + B0_LP_CTRL0_DA_ARPI_CG_FB_B0_LP_SEL, 1, + B0_LP_CTRL0_DA_ARPI_CG_DQ_B0_LP_SEL, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_lp_ctrl0, + B0_LP_CTRL0_DA_ARPI_CG_DQM_B0_LP_SEL, 1, + B0_LP_CTRL0_DA_ARPI_CG_DQS_B0_LP_SEL, 1, + B0_LP_CTRL0_DA_ARPI_CG_DQSIEN_B0_LP_SEL, 1, + B0_LP_CTRL0_DA_ARPI_MPDIV_CG_B0_LP_SEL, 1, + B0_LP_CTRL0_RG_RX_ARDQ_VREF_EN_B0_LP_SEL, 1, + B0_LP_CTRL0_DA_ARPI_MIDPI_EN_B0_LP_SEL, 1, + B0_LP_CTRL0_DA_ARPI_MIDPI_CKDIV4_EN_B0_LP_SEL, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_lp_ctrl0, + B1_LP_CTRL0_RG_ARDMSUS_10_B1_LP_SEL, 1, + B1_LP_CTRL0_RG_ARDQ_RESETB_B1_LP_SEL, 1, + B1_LP_CTRL0_RG_ARPI_RESETB_B1_LP_SEL, 1, + B1_LP_CTRL0_RG_B1_MS_SLV_LP_SEL, 0, + B1_LP_CTRL0_RG_ARDLL_PHDET_EN_B1_LP_SEL, 1, + B1_LP_CTRL0_RG_RX_ARDQ_BIAS_EN_B1_LP_SEL, 0, + B1_LP_CTRL0_DA_ARPI_CG_MCK_B1_LP_SEL, 1, + B1_LP_CTRL0_DA_ARPI_CG_MCK_FB2DLL_B1_LP_SEL, 1, + B1_LP_CTRL0_DA_ARPI_CG_MCTL_B1_LP_SEL, 1, + B1_LP_CTRL0_DA_ARPI_CG_FB_B1_LP_SEL, 1, + B1_LP_CTRL0_DA_ARPI_CG_DQ_B1_LP_SEL, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_lp_ctrl0, + B1_LP_CTRL0_DA_ARPI_CG_DQM_B1_LP_SEL, 1, + B1_LP_CTRL0_DA_ARPI_CG_DQS_B1_LP_SEL, 1, + B1_LP_CTRL0_DA_ARPI_CG_DQSIEN_B1_LP_SEL, 1, + B1_LP_CTRL0_DA_ARPI_MPDIV_CG_B1_LP_SEL, 1, + B1_LP_CTRL0_RG_RX_ARDQ_VREF_EN_B1_LP_SEL, 1, + B1_LP_CTRL0_DA_ARPI_MIDPI_EN_B1_LP_SEL, 1, + B1_LP_CTRL0_DA_ARPI_MIDPI_CKDIV4_EN_B1_LP_SEL, 1); + + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.ca_lp_ctrl0, + CA_LP_CTRL0_RG_ARDMSUS_10_CA_LP_SEL, 1, + CA_LP_CTRL0_RG_ARCMD_RESETB_LP_SEL, 1, + CA_LP_CTRL0_RG_ARPI_RESETB_CA_LP_SEL, 1, + CA_LP_CTRL0_RG_ARDLL_PHDET_EN_CA_LP_SEL, 1, + CA_LP_CTRL0_RG_TX_ARCS_PULL_UP_LP_SEL, 1, + CA_LP_CTRL0_RG_TX_ARCS_PULL_DN_LP_SEL, 1, + CA_LP_CTRL0_RG_TX_ARCA_PULL_UP_LP_SEL, 1, + CA_LP_CTRL0_RG_TX_ARCA_PULL_DN_LP_SEL, 1, + CA_LP_CTRL0_DA_ARPI_CG_MCK_CA_LP_SEL, 1, + CA_LP_CTRL0_DA_ARPI_CG_MCK_FB2DLL_CA_LP_SEL, 1, + CA_LP_CTRL0_DA_ARPI_CG_MCTL_CA_LP_SEL, 1, + CA_LP_CTRL0_DA_ARPI_CG_FB_CA_LP_SEL, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.ca_lp_ctrl0, + CA_LP_CTRL0_DA_ARPI_CG_CS_LP_SEL, 1, + CA_LP_CTRL0_DA_ARPI_CG_CLK_LP_SEL, 1, + CA_LP_CTRL0_DA_ARPI_CG_CMD_LP_SEL, 1, + CA_LP_CTRL0_DA_ARPI_CG_CLKIEN_LP_SEL, 1, + CA_LP_CTRL0_DA_ARPI_MPDIV_CG_CA_LP_SEL, 1, + CA_LP_CTRL0_RG_RX_ARCMD_VREF_EN_LP_SEL, 1, + CA_LP_CTRL0_DA_ARPI_MIDPI_EN_CA_LP_SEL, 1, + CA_LP_CTRL0_DA_ARPI_MIDPI_CKDIV4_EN_CA_LP_SEL, 1, + CA_LP_CTRL0_RG_RX_ARCMD_BIAS_EN_LP_SEL, 0); + } + + if (a_cfg->dll_async_en == 1) { + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.ca_lp_ctrl0, + CA_LP_CTRL0_RG_CA_MS_SLV_LP_SEL, a_cfg->all_slave_en==0); + } else { + SET32_BITFIELDS(&ch[0].phy_ao.ca_lp_ctrl0, + CA_LP_CTRL0_RG_CA_MS_SLV_LP_SEL, a_cfg->all_slave_en==0); + SET32_BITFIELDS(&ch[1].phy_ao.ca_lp_ctrl0, + CA_LP_CTRL0_RG_CA_MS_SLV_LP_SEL, 0); + } + dramc_set_broadcast(DRAMC_BROADCAST_ON); + + SET32_BITFIELDS(&ch[0].phy_ao.misc_cg_ctrl9, + MISC_CG_CTRL9_RG_M_CK_OPENLOOP_MODE_EN, 1, + MISC_CG_CTRL9_RG_MCK4X_I_OPENLOOP_MODE_EN, 1, + MISC_CG_CTRL9_RG_CG_DDR400_MCK4X_I_OFF, 1, + MISC_CG_CTRL9_RG_DDR400_MCK4X_I_FORCE_ON, 0, + MISC_CG_CTRL9_RG_MCK4X_I_FB_CK_CG_OFF, 1, + MISC_CG_CTRL9_RG_MCK4X_Q_OPENLOOP_MODE_EN, 1, + MISC_CG_CTRL9_RG_CG_DDR400_MCK4X_Q_OFF, 1, + MISC_CG_CTRL9_RG_DDR400_MCK4X_Q_FORCE_ON, 0, + MISC_CG_CTRL9_RG_MCK4X_Q_FB_CK_CG_OFF, 1); +} + +static void ana_tx_nonshuffle_config(ana_top_config *a_cfg) +{ + SET32_BITFIELDS(&ch[0].phy_ao.ca_cmd6, + CA_CMD6_RG_TX_ARCMD_DDR3_SEL, 0, + CA_CMD6_RG_TX_ARCMD_DDR4_SEL, 0, + CA_CMD6_RG_TX_ARCMD_LP4_SEL, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq6, + B0_DQ6_RG_TX_ARDQ_DDR3_SEL_B0, 0, + B0_DQ6_RG_TX_ARDQ_DDR4_SEL_B0, !(a_cfg->aphy_comb_en), + B0_DQ6_RG_TX_ARDQ_LP4_SEL_B0, a_cfg->aphy_comb_en); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq6, + B1_DQ6_RG_TX_ARDQ_DDR3_SEL_B1, 0, + B1_DQ6_RG_TX_ARDQ_DDR4_SEL_B1, !(a_cfg->aphy_comb_en), + B1_DQ6_RG_TX_ARDQ_LP4_SEL_B1, a_cfg->aphy_comb_en); + dramc_dbg("[CONFIGURE PHASE]: ANA_TX\n"); + SET32_BITFIELDS(&ch[0].phy_ao.ca_cmd2, + CA_CMD2_RG_TX_ARCMD_OE_DIS_CA, 1, + CA_CMD2_RG_TX_ARCMD_ODTEN_DIS_CA, 0, + CA_CMD2_RG_TX_ARCLK_OE_DIS_CA, 0, + CA_CMD2_RG_TX_ARCLK_ODTEN_DIS_CA, 0, + CA_CMD2_RG_TX_ARCS_OE_TIE_SEL_CA, 1, + CA_CMD2_RG_TX_ARCS_OE_TIE_EN_CA, 1, + CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA, 0, + CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA, 0xff); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq2, + B0_DQ2_RG_TX_ARDQ_OE_DIS_B0, 0, + B0_DQ2_RG_TX_ARDQ_ODTEN_DIS_B0, 0, + B0_DQ2_RG_TX_ARDQM0_OE_DIS_B0, 0, + B0_DQ2_RG_TX_ARDQM0_ODTEN_DIS_B0, 0, + B0_DQ2_RG_TX_ARDQS0_OE_DIS_B0, 0, + B0_DQ2_RG_TX_ARDQS0_ODTEN_DIS_B0, 0); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq2, + B1_DQ2_RG_TX_ARDQ_OE_DIS_B1, 0, + B1_DQ2_RG_TX_ARDQ_ODTEN_DIS_B1, 0, + B1_DQ2_RG_TX_ARDQM0_OE_DIS_B1, 0, + B1_DQ2_RG_TX_ARDQM0_ODTEN_DIS_B1, 0, + B1_DQ2_RG_TX_ARDQS0_OE_DIS_B1, 0, + B1_DQ2_RG_TX_ARDQS0_ODTEN_DIS_B1, 0); + SET32_BITFIELDS(&ch[0].phy_ao.ca_cmd3, + CA_CMD3_RG_TX_ARCMD_EN, 1, + CA_CMD3_RG_ARCMD_RESETB, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq3, + B0_DQ3_RG_ARDQ_RESETB_B0, 1, + B0_DQ3_RG_TX_ARDQ_EN_B0, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq3, + B1_DQ3_RG_ARDQ_RESETB_B1, 1, + B1_DQ3_RG_TX_ARDQ_EN_B1, 1); +} + +static void ana_rx_nonshuffle_config(void) +{ + SET32_BITFIELDS(&ch[0].phy_ao.ca_cmd6, + CA_CMD6_RG_RX_ARCMD_DDR3_SEL, 0, + CA_CMD6_RG_RX_ARCMD_DDR4_SEL, 0, + CA_CMD6_RG_RX_ARCMD_BIAS_VREF_SEL, 0, + CA_CMD6_RG_RX_ARCMD_RES_BIAS_EN, 0); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq5, + B0_DQ5_RG_RX_ARDQ_VREF_EN_B0, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq6, + B0_DQ6_RG_RX_ARDQ_DDR3_SEL_B0, 0, + B0_DQ6_RG_RX_ARDQ_DDR4_SEL_B0, 1, + B0_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B0, 0, + B0_DQ6_RG_RX_ARDQ_BIAS_EN_B0, 1, + B0_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B0, 0, + B0_DQ6_RG_RX_ARDQ_RES_BIAS_EN_B0, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq3, + B0_DQ3_RG_RX_ARDQ_STBENCMP_EN_B0, 1, + B0_DQ3_RG_RX_ARDQ_SMT_EN_B0, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq5, + B1_DQ5_RG_RX_ARDQ_VREF_EN_B1, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq6, + B1_DQ6_RG_RX_ARDQ_DDR3_SEL_B1, 0, + B1_DQ6_RG_RX_ARDQ_DDR4_SEL_B1, 1, + B1_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B1, 0, + B1_DQ6_RG_RX_ARDQ_BIAS_EN_B1, 1, + B1_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B1, 0, + B1_DQ6_RG_RX_ARDQ_RES_BIAS_EN_B1, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq3, + B1_DQ3_RG_RX_ARDQ_STBENCMP_EN_B1, 1, + B1_DQ3_RG_RX_ARDQ_SMT_EN_B1, 1); + SET32_BITFIELDS(&ch[0].phy_ao.ca_cmd9, + CA_CMD9_RG_RX_ARCMD_STBEN_RESETB, 1, + CA_CMD9_RG_RX_ARCLK_STBEN_RESETB, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq9, + B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0, 1, + B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq9, + B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1, 1, + B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1, 1); + SET32_BITFIELDS(&ch[0].phy_ao.ca_cmd8, + CA_CMD8_RG_RX_ARCLK_SER_RST_MODE, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq8, + B0_DQ8_RG_RX_ARDQS_SER_RST_MODE_B0, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq8, + B1_DQ8_RG_RX_ARDQS_SER_RST_MODE_B1, 1); +} + +static void dig_dcm_nonshuffle_config(void) +{ + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rx_cg_ctrl, + MISC_SHU_RX_CG_CTRL_RX_DCM_EXT_DLY, 3); +} + +static void ana_imp_configure(void) +{ + SET32_BITFIELDS(&ch[0].phy_ao.misc_imp_ctrl1, + MISC_IMP_CTRL1_RG_RIMP_DDR3_SEL, 0); + SET32_BITFIELDS(&ch[0].phy_ao.misc_imp_ctrl1, + MISC_IMP_CTRL1_RG_RIMP_DDR4_SEL, 1); + SET32_BITFIELDS(&ch[0].phy_ao.misc_imp_ctrl1, + MISC_IMP_CTRL1_RG_RIMP_BIAS_EN, 0, + MISC_IMP_CTRL1_RG_RIMP_ODT_EN, 0, + MISC_IMP_CTRL1_RG_RIMP_PRE_EN, 0, + MISC_IMP_CTRL1_RG_RIMP_VREF_EN, 0); +} + +static void ana_dll_non_shuffle_config(dram_freq_grp freq_group, + ana_top_config *a_cfg) +{ + u8 pd_zone = (freq_group >= DDRFREQ_2133) ? 0x2 : 0x3; + + if (a_cfg->dll_idle_mode == 1) { + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + if (a_cfg->dll_async_en == 1) { + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.ca_dll_arpi5, + CA_DLL_ARPI5_RG_ARDLL_IDLE_EN_CA, 0, + CA_DLL_ARPI5_RG_ARDLL_PD_ZONE_CA, pd_zone); + SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[0].b0_dll_arpi5, + B0_DLL_ARPI5_RG_ARDLL_IDLE_EN_B0, 1, + B0_DLL_ARPI5_RG_ARDLL_PD_ZONE_B0, pd_zone); + SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[1].b0_dll_arpi5, + B1_DLL_ARPI5_RG_ARDLL_IDLE_EN_B1, 1, + B1_DLL_ARPI5_RG_ARDLL_PD_ZONE_B1, pd_zone); + } + } else { + SET32_BITFIELDS(&ch[0].phy_ao.ca_dll_arpi5, + CA_DLL_ARPI5_RG_ARDLL_IDLE_EN_CA, 0, + CA_DLL_ARPI5_RG_ARDLL_PD_ZONE_CA, pd_zone); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dll_arpi5, + B0_DLL_ARPI5_RG_ARDLL_IDLE_EN_B0, 1, + B0_DLL_ARPI5_RG_ARDLL_PD_ZONE_B0, pd_zone); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dll_arpi5, + B1_DLL_ARPI5_RG_ARDLL_IDLE_EN_B1, 1, + B1_DLL_ARPI5_RG_ARDLL_PD_ZONE_B1, pd_zone); + SET32_BITFIELDS(&ch[1].phy_ao.ca_dll_arpi5, + CA_DLL_ARPI5_RG_ARDLL_IDLE_EN_CA, 1, + CA_DLL_ARPI5_RG_ARDLL_PD_ZONE_CA, pd_zone); + SET32_BITFIELDS(&ch[1].phy_ao.dvs_b[0].b0_dll_arpi5, + B0_DLL_ARPI5_RG_ARDLL_IDLE_EN_B0, 1, + B0_DLL_ARPI5_RG_ARDLL_PD_ZONE_B0, pd_zone); + SET32_BITFIELDS(&ch[1].phy_ao.dvs_b[1].b0_dll_arpi5, + B1_DLL_ARPI5_RG_ARDLL_IDLE_EN_B1, 1, + B1_DLL_ARPI5_RG_ARDLL_PD_ZONE_B1, pd_zone); + } + dramc_set_broadcast(DRAMC_BROADCAST_ON); + } + + SET32_BITFIELDS(&ch[0].phy_ao.ca_dll_arpi1, + CA_DLL_ARPI1_RG_ARPI_CLKIEN_JUMP_EN, 0, + CA_DLL_ARPI1_RG_ARPI_CMD_JUMP_EN, 0, + CA_DLL_ARPI1_RG_ARPI_CLK_JUMP_EN, 0, + CA_DLL_ARPI1_RG_ARPI_CS_JUMP_EN, 0, + CA_DLL_ARPI1_RG_ARPI_FB_JUMP_EN_CA, 0, + CA_DLL_ARPI1_RG_ARPI_MCTL_JUMP_EN_CA, 0, + CA_DLL_ARPI1_RG_ARPISM_MCK_SEL_CA, 1, + CA_DLL_ARPI1_RG_ARPISM_MCK_SEL_CA_REG_OPT, 0); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dll_arpi1, + B0_DLL_ARPI1_RG_ARPI_DQSIEN_JUMP_EN_B0, 0, + B0_DLL_ARPI1_RG_ARPI_DQ_JUMP_EN_B0, 0, + B0_DLL_ARPI1_RG_ARPI_DQM_JUMP_EN_B0, 0, + B0_DLL_ARPI1_RG_ARPI_DQS_JUMP_EN_B0, 0, + B0_DLL_ARPI1_RG_ARPI_FB_JUMP_EN_B0, 0, + B0_DLL_ARPI1_RG_ARPI_MCTL_JUMP_EN_B0, 0, + B0_DLL_ARPI1_RG_ARPISM_MCK_SEL_B0, 0, + B0_DLL_ARPI1_RG_ARPISM_MCK_SEL_B0_REG_OPT, 0); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dll_arpi1, + B1_DLL_ARPI1_RG_ARPI_DQSIEN_JUMP_EN_B1, 0, + B1_DLL_ARPI1_RG_ARPI_DQ_JUMP_EN_B1, 0, + B1_DLL_ARPI1_RG_ARPI_DQM_JUMP_EN_B1, 0, + B1_DLL_ARPI1_RG_ARPI_DQS_JUMP_EN_B1, 0, + B1_DLL_ARPI1_RG_ARPI_FB_JUMP_EN_B1, 0, + B1_DLL_ARPI1_RG_ARPI_MCTL_JUMP_EN_B1, 0, + B1_DLL_ARPI1_RG_ARPISM_MCK_SEL_B1, 0, + B1_DLL_ARPI1_RG_ARPISM_MCK_SEL_B1_REG_OPT, 0); + + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.ca_dll_arpi5, + CA_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_CA, 0, + CA_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_SEL_CA, 0, + CA_DLL_ARPI5_RG_ARDLL_DIV_DEC_CA, 0, + CA_DLL_ARPI5_RG_ARDLL_MON_SEL_CA, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[0].b0_dll_arpi5, + B0_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_B0, 0, + B0_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_SEL_B0, 0, + B0_DLL_ARPI5_RG_ARDLL_DIV_DEC_B0, 0, + B0_DLL_ARPI5_RG_ARDLL_MON_SEL_B0, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[1].b0_dll_arpi5, + B1_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_B1, 0, + B1_DLL_ARPI5_RG_ARDLL_FJ_OUT_MODE_SEL_B1, 0, + B1_DLL_ARPI5_RG_ARDLL_DIV_DEC_B1, 0, + B1_DLL_ARPI5_RG_ARDLL_MON_SEL_B1, 0); + } + dramc_set_broadcast(DRAMC_BROADCAST_ON); +} + +static void ana_pll_shuffle_Config(ana_dvfs_core *dvfs_core) +{ + u8 prediv = 1; + u8 posdiv = 0; + u8 fbk_sel = 0; + u8 div16_ck_sel = 0; + u32 pcw; + u32 pll_freq = dvfs_core->pll_freq; + u32 xtal_freq = 26; + + if (dvfs_core->dq_ca_open == 1) + div16_ck_sel = 1; + else + fbk_sel = (pll_freq > 3800) ? 1 : 0; + + pcw = (pll_freq/xtal_freq) << (8 + 1 -fbk_sel-prediv - posdiv); + dramc_dbg("pll_freq:%d, fbk_sel:%d, pcw = %#x\n", pll_freq, fbk_sel, pcw); + + SET32_BITFIELDS(&ch[0].phy_ao.phypll1, + PHYPLL1_RG_RPHYPLL_TST_EN, 0, + PHYPLL1_RG_RPHYPLL_TSTOP_EN, 0); + SET32_BITFIELDS(&ch[0].phy_ao.shu_phypll0, + SHU_PHYPLL0_RG_RPHYPLL_RESERVED, 0, + SHU_PHYPLL0_RG_RPHYPLL_ICHP, 0); + SET32_BITFIELDS(&ch[0].phy_ao.shu_clrpll0, + SHU_CLRPLL0_RG_RCLRPLL_RESERVED, 0, + SHU_CLRPLL0_RG_RCLRPLL_ICHP, 0); + SET32_BITFIELDS(&ch[0].phy_ao.shu_phypll2, + SHU_PHYPLL2_RG_RPHYPLL_PREDIV, prediv, + SHU_PHYPLL2_RG_RPHYPLL_POSDIV, posdiv); + SET32_BITFIELDS(&ch[0].phy_ao.shu_clrpll2, + SHU_CLRPLL2_RG_RCLRPLL_PREDIV, prediv, + SHU_CLRPLL2_RG_RCLRPLL_POSDIV, posdiv); + SET32_BITFIELDS(&ch[0].phy_ao.shu_phypll1, + SHU_PHYPLL1_RG_RPHYPLL_SDM_PCW, pcw, + SHU_PHYPLL1_RG_RPHYPLL_SDM_PCW_CHG, 1, + SHU_PHYPLL1_RG_RPHYPLL_SDM_FRA_EN, 0); + SET32_BITFIELDS(&ch[0].phy_ao.shu_clrpll1, + SHU_CLRPLL1_RG_RCLRPLL_SDM_PCW, pcw, + SHU_CLRPLL1_RG_RCLRPLL_SDM_PCW_CHG, 1, + SHU_CLRPLL1_RG_RCLRPLL_SDM_FRA_EN, 0); + SET32_BITFIELDS(&ch[0].phy_ao.shu_pll1, + SHU_PLL1_RG_RPHYPLLGP_CK_SEL, 1, + SHU_PLL1_R_SHU_AUTO_PLL_MUX, 1); + SET32_BITFIELDS(&ch[0].phy_ao.shu_phypll3, + SHU_PHYPLL3_RG_RPHYPLL_LVROD_EN, 0, + SHU_PHYPLL3_RG_RPHYPLL_RST_DLY, 1, + SHU_PHYPLL3_RG_RPHYPLL_FBKSEL, fbk_sel); + SET32_BITFIELDS(&ch[0].phy_ao.shu_clrpll3, + SHU_CLRPLL3_RG_RCLRPLL_LVROD_EN, 0, + SHU_CLRPLL3_RG_RCLRPLL_RST_DLY, 1, + SHU_CLRPLL3_RG_RCLRPLL_FBKSEL, fbk_sel); + if (dvfs_core->dq_ca_open == 1) { + SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_clk_ctrl0, + SHU_MISC_CLK_CTRL0_M_CK_OPENLOOP_MODE_SEL, + dvfs_core->dq_ca_open); + SET32_BITFIELDS(&ch[0].phy_ao.shu_phypll3, + SHU_PHYPLL3_RG_RPHYPLL_MONCK_EN, 1, + SHU_PHYPLL3_RG_RPHYPLL_DIV_CK_SEL, div16_ck_sel); + SET32_BITFIELDS(&ch[0].phy_ao.shu_clrpll3, + SHU_CLRPLL3_RG_RCLRPLL_MONCK_EN, 1, + SHU_CLRPLL3_RG_RCLRPLL_DIV_CK_SEL, div16_ck_sel); + } + dramc_dbg("PLL\n"); +} + +static void ana_arpi_shuffle_config(ana_top_config *a_cfg, ana_dvfs_core *tr) +{ + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_dll_arpi3, + SHU_CA_DLL_ARPI3_RG_ARPI_CLKIEN_EN, 0, + SHU_CA_DLL_ARPI3_RG_ARPI_CMD_EN, !(tr->dq_semi_open), + SHU_CA_DLL_ARPI3_RG_ARPI_CS_EN, !(tr->dq_semi_open)); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dll_arpi3, + SHU_B0_DLL_ARPI3_RG_ARPI_DQSIEN_EN_B0, !(tr->dq_semi_open), + SHU_B0_DLL_ARPI3_RG_ARPI_DQ_EN_B0, !(tr->dq_semi_open), + SHU_B0_DLL_ARPI3_RG_ARPI_DQM_EN_B0, !(tr->dq_semi_open), + SHU_B0_DLL_ARPI3_RG_ARPI_DQS_EN_B0, !(tr->dq_semi_open), + SHU_B0_DLL_ARPI3_RG_ARPI_FB_EN_B0, !(tr->dq_semi_open)); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dll_arpi3, + SHU_B0_DLL_ARPI3_RG_ARPI_MCTL_EN_B0, + (!(tr->dq_semi_open)) && (a_cfg->rank_mode)); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dll_arpi3, + SHU_B1_DLL_ARPI3_RG_ARPI_DQSIEN_EN_B1, !(tr->dq_semi_open), + SHU_B1_DLL_ARPI3_RG_ARPI_DQ_EN_B1, !(tr->dq_semi_open), + SHU_B1_DLL_ARPI3_RG_ARPI_DQM_EN_B1, !(tr->dq_semi_open), + SHU_B1_DLL_ARPI3_RG_ARPI_DQS_EN_B1, !(tr->dq_semi_open), + SHU_B1_DLL_ARPI3_RG_ARPI_FB_EN_B1, !(tr->dq_semi_open)); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dll_arpi3, + SHU_B1_DLL_ARPI3_RG_ARPI_MCTL_EN_B1, + (!(tr->dq_semi_open)) && (a_cfg->rank_mode)); + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd2, + SHU_CA_CMD2_RG_ARPISM_MCK_SEL_CA_SHU, 1, + SHU_CA_CMD2_RG_ARPI_TX_CG_SYNC_DIS_CA, 1, + SHU_CA_CMD2_RG_ARPI_TX_CG_CA_EN_CA, 1, + SHU_CA_CMD2_RG_ARPI_TX_CG_CLK_EN_CA, 1, + SHU_CA_CMD2_RG_ARPI_TX_CG_CS_EN_CA, 1, + SHU_CA_CMD2_RG_ARPI_PD_MCTL_SEL_CA, 0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq2, + SHU_B0_DQ2_RG_ARPISM_MCK_SEL_B0_SHU, 1, + SHU_B0_DQ2_RG_ARPI_TX_CG_SYNC_DIS_B0, 1, + SHU_B0_DQ2_RG_ARPI_TX_CG_DQ_EN_B0, 1, + SHU_B0_DQ2_RG_ARPI_TX_CG_DQS_EN_B0, 1, + SHU_B0_DQ2_RG_ARPI_TX_CG_DQM_EN_B0, 1, + SHU_B0_DQ2_RG_ARPI_PD_MCTL_SEL_B0, 1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq2, + SHU_B1_DQ2_RG_ARPISM_MCK_SEL_B1_SHU, 1, + SHU_B1_DQ2_RG_ARPI_TX_CG_SYNC_DIS_B1, 1, + SHU_B1_DQ2_RG_ARPI_TX_CG_DQ_EN_B1, 1, + SHU_B1_DQ2_RG_ARPI_TX_CG_DQS_EN_B1, 1, + SHU_B1_DQ2_RG_ARPI_TX_CG_DQM_EN_B1, 1, + SHU_B1_DQ2_RG_ARPI_PD_MCTL_SEL_B1, 1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq7, + SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0, 0, + SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0, 0, + SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0, 0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq7, + SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1, 0, + SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1, 0, + SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1, 0); + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd7, + SHU_CA_CMD7_R_DMTX_ARPI_CG_CS_NEW, 0, + SHU_CA_CMD7_R_DMTX_ARPI_CG_CMD_NEW, 0); +} + +static void ana_tx_shuffle_config(ana_top_config *a_cfg) +{ + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd14, + SHU_CA_CMD14_RG_TX_ARCA_OE_ODTEN_CG_EN_CA, 0); + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd13, + SHU_CA_CMD13_RG_TX_ARCLK_OE_ODTEN_CG_EN_CA, 0, + SHU_CA_CMD13_RG_TX_ARCS_OE_ODTEN_CG_EN_CA, 0); + + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq13, + SHU_B0_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B0, 1, + SHU_B0_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B0, 1, + SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_EN_B0, 0, + SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B0, 0, + SHU_B0_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B0, 0, + SHU_B0_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B0, 0, + SHU_B0_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B0, a_cfg->tx_odt_dis); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq13, + SHU_B1_DQ13_RG_TX_ARDQS_OE_ODTEN_CG_EN_B1, 1, + SHU_B1_DQ13_RG_TX_ARDQM_OE_ODTEN_CG_EN_B1, 1, + SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_EN_B1, 0, + SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_EN_B1, 0, + SHU_B1_DQ13_RG_TX_ARDQS_READ_BASE_DATA_TIE_EN_B1, 0, + SHU_B1_DQ13_RG_TX_ARDQSB_READ_BASE_DATA_TIE_EN_B1, 0, + SHU_B1_DQ13_RG_TX_ARDQ_IO_ODT_DIS_B1, a_cfg->tx_odt_dis); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq14, + SHU_B0_DQ14_RG_TX_ARDQ_OE_ODTEN_CG_EN_B0, 1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq14, + SHU_B1_DQ14_RG_TX_ARDQ_OE_ODTEN_CG_EN_B1, 1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq13, + SHU_B0_DQ13_RG_TX_ARDQS_MCKIO_SEL_B0, 0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq13, + SHU_B1_DQ13_RG_TX_ARDQS_MCKIO_SEL_B1, 0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq14, + SHU_B0_DQ14_RG_TX_ARDQ_MCKIO_SEL_B0, 0, + SHU_B0_DQ14_RG_TX_ARWCK_MCKIO_SEL_B0, 0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq14, + SHU_B1_DQ14_RG_TX_ARDQ_MCKIO_SEL_B1, 0, + SHU_B1_DQ14_RG_TX_ARWCK_MCKIO_SEL_B1, 0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq13, + SHU_B0_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B0, 0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq13, + SHU_B1_DQ13_RG_TX_ARDQ_DLY_LAT_EN_B1, 0); + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd13, + SHU_CA_CMD13_RG_TX_ARCA_DLY_LAT_EN_CA, 0); + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd2, + SHU_CA_CMD2_RG_ARPI_OFFSET_LAT_EN_CA, 0, + SHU_CA_CMD2_RG_ARPI_OFFSET_ASYNC_EN_CA, 0); +} + +static void dig_phy_shu_misc_cg_ctrl(void) +{ + setbits32(&ch[0].phy_ao.misc_shu_cg_ctrl0, 0x33400000); +} + +static void ana_clk_div_config_setting(ana_dvfs_core *tr, ana_top_config *a_cfg) +{ + u8 tx_ardq_sermode=0; + u8 tx_arcr_sermode=0; + u8 ardll_sermode_b=0; + u8 ardll_sermode_c=0; + + dramc_dbg("ANA CLOCK DIV configuration\n"); + switch (tr->dq_p2s_ratio) { + case 4 : + tx_ardq_sermode = 1; + break; + case 8 : + tx_ardq_sermode = 2; + break; + case 16: + tx_ardq_sermode = 3; + break; + default: dramc_dbg("ERROR: tr->dq_p2s_ratio= %2d, Not support!!",tr->dq_p2s_ratio); + break; + } + + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq14, + SHU_B0_DQ14_RG_TX_ARDQ_SER_MODE_B0, tx_ardq_sermode); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq14, + SHU_B1_DQ14_RG_TX_ARDQ_SER_MODE_B1, tx_ardq_sermode); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq6, + SHU_B0_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B0, tx_ardq_sermode); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq6, + SHU_B1_DQ6_RG_RX_ARDQ_RANK_SEL_SER_MODE_B1, tx_ardq_sermode); + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd11, + SHU_CA_CMD11_RG_RX_ARCA_DES_MODE_CA, (tr->dq_p2s_ratio == 16 ) ? 3 : 2); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq11, + SHU_B0_DQ11_RG_RX_ARDQ_DES_MODE_B0, (tr->dq_p2s_ratio == 16 ) ? 3 : 2); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq11, + SHU_B1_DQ11_RG_RX_ARDQ_DES_MODE_B1, (tr->dq_p2s_ratio == 16 ) ? 3 : 2); + + switch (tr->ca_p2s_ratio) { + case 2 : + tx_arcr_sermode = (0 + tr->ca_full_rate); + break; + case 4 : + tx_arcr_sermode = (1 + tr->ca_full_rate); + break; + case 8: + tx_arcr_sermode = (2 + tr->ca_full_rate); + break; + default: dramc_dbg("ERROR: tr->ca_p2s_ratio= %2d, Not support!!",tr->ca_p2s_ratio); + break; + } + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd14, + SHU_CA_CMD14_RG_TX_ARCA_SER_MODE_CA, tx_arcr_sermode); + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd6, + SHU_CA_CMD6_RG_RX_ARCMD_RANK_SEL_SER_MODE, tx_arcr_sermode); + + switch (tr->dq_aamck_div) { + case 2 : + ardll_sermode_b = 1; + break; + case 4 : + ardll_sermode_b = 2; + break; + case 8: + ardll_sermode_b = 3; + break; + default: dramc_dbg("WARN: tr->dq_aamck_div= %2d, Because of dq_semi_open, It's don't care.",tr->dq_aamck_div); + break; + } + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dll1, + SHU_B0_DLL1_RG_ARDLL_SER_MODE_B0, ardll_sermode_b); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dll1, + SHU_B1_DLL1_RG_ARDLL_SER_MODE_B1, ardll_sermode_b); + + switch (tr->ca_admck_div) { + case 2 : + ardll_sermode_c = 1; + break; + case 4 : + ardll_sermode_c = 2; + break; + case 8: + ardll_sermode_c = 3; + break; + default: dramc_dbg("ERROR: tr->ca_admck_div= %2d, Not support!!",tr->ca_admck_div); + break; + } + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_dll1, + SHU_CA_DLL1_RG_ARDLL_SER_MODE_CA, ardll_sermode_c); + + dramc_set_broadcast(DRAMC_BROADCAST_ON); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq6, + SHU_B0_DQ6_RG_ARPI_SOPEN_EN_B0, tr->dq_semi_open, + SHU_B0_DQ6_RG_ARPI_OPEN_EN_B0, tr->dq_ca_open); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq6, + SHU_B1_DQ6_RG_ARPI_SOPEN_EN_B1, tr->dq_semi_open, + SHU_B1_DQ6_RG_ARPI_OPEN_EN_B1, tr->dq_ca_open); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq1, + SHU_B0_DQ1_RG_ARPI_MIDPI_EN_B0, + !(tr->dq_semi_open) && (!(tr->dq_ckdiv4_en)), + SHU_B0_DQ1_RG_ARPI_MIDPI_CKDIV4_EN_B0, + !(tr->dq_semi_open) && (tr->dq_ckdiv4_en), + SHU_B0_DQ1_RG_ARPI_MIDPI_8PH_DLY_B0, tr->ph8_dly); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq1, + SHU_B1_DQ1_RG_ARPI_MIDPI_EN_B1, + !(tr->dq_semi_open) && (!(tr->dq_ckdiv4_en)), + SHU_B1_DQ1_RG_ARPI_MIDPI_CKDIV4_EN_B1, + !(tr->dq_semi_open) && (tr->dq_ckdiv4_en), + SHU_B1_DQ1_RG_ARPI_MIDPI_8PH_DLY_B1, tr->ph8_dly); + + if (tr->ca_semi_open == 0) { + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd6, + SHU_CA_CMD6_RG_ARPI_SOPEN_EN_CA, 0, + SHU_CA_CMD6_RG_ARPI_SOPEN_CKGEN_EN_CA, 0, + SHU_CA_CMD6_RG_ARPI_OFFSET_DQSIEN_CA, 0); + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_dll_arpi3, + SHU_CA_DLL_ARPI3_RG_ARPI_FB_EN_CA, 1, + SHU_CA_DLL_ARPI3_RG_ARPI_CLK_EN, 1, + SHU_CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA, 1); + } else { + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_cmd6, + SHU_CA_CMD6_RG_ARPI_SOPEN_EN_CA, 1, + SHU_CA_CMD6_RG_ARPI_SOPEN_CKGEN_EN_CA, 1, + SHU_CA_CMD6_RG_ARPI_OFFSET_DQSIEN_CA, 16); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_dll_arpi3, + SHU_CA_DLL_ARPI3_RG_ARPI_FB_EN_CA, 1, + SHU_CA_DLL_ARPI3_RG_ARPI_CLK_EN, 1); + } + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_dll_arpi3, + SHU_CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA, 1); + SET32_BITFIELDS(&ch[1].phy_ao.shu_ca_dll_arpi3, + SHU_CA_DLL_ARPI3_RG_ARPI_MCTL_EN_CA, 0); + dramc_set_broadcast(DRAMC_BROADCAST_ON); + } + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd6, + SHU_CA_CMD6_RG_ARPI_OPEN_EN_CA, tr->dq_ca_open); + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd13, + SHU_CA_CMD13_RG_TX_ARCA_FRATE_EN_CA, tr->ca_full_rate); + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd1, + SHU_CA_CMD1_RG_ARPI_MIDPI_8PH_DLY_CA, tr->ph8_dly); + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd1, + SHU_CA_CMD1_RG_ARPI_MIDPI_CKDIV4_PREDIV_EN_CA, tr->ca_prediv_en); + + if (tr->semi_open_ca_pick_mck_ratio == 4) + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd6, + SHU_CA_CMD6_RG_ARPI_SOPEN_CKGEN_DIV_CA, 0); + else if (tr->semi_open_ca_pick_mck_ratio == 8) + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd6, + SHU_CA_CMD6_RG_ARPI_SOPEN_CKGEN_DIV_CA, 1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dll1, + SHU_B0_DLL1_RG_ARDLL_TRACKING_CA_EN_B0, tr->dq_track_ca_en); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dll1, + SHU_B1_DLL1_RG_ARDLL_TRACKING_CA_EN_B1, tr->dq_track_ca_en); + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_dll_arpi2, + SHU_CA_DLL_ARPI2_RG_ARPI_CG_CLKIEN, 1); +} + +static void ana_dll_shuffle_config(dram_freq_grp freq_group, ana_top_config *a_cfg) +{ + u8 gain = 0; + if (freq_group <= DDRFREQ_1600) { + gain = 2; + dramc_dbg("Add DLL Gain = %d\n",gain); + } + + dramc_dbg("DLL\n"); + if (a_cfg->dll_async_en == 1) { + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_dll0, + SHU_CA_DLL0_RG_ARDLL_GAIN_CA, + (a_cfg->all_slave_en == 0) ? 6 : 7, + SHU_CA_DLL0_RG_ARDLL_IDLECNT_CA, + (a_cfg->all_slave_en == 0) ? 9 : 7, + SHU_CA_DLL0_RG_ARDLL_FAST_PSJP_CA, + !(a_cfg->all_slave_en), + SHU_CA_DLL0_RG_ARDLL_GEAR2_PSJP_CA, 0, + SHU_CA_DLL0_RG_ARDLL_FASTPJ_CK_SEL_CA, + a_cfg->all_slave_en); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_dll1, + SHU_CA_DLL1_RG_ARDLL_PHDET_OUT_SEL_CA, + a_cfg->all_slave_en, + SHU_CA_DLL1_RG_ARDLL_PHDET_IN_SWAP_CA, + a_cfg->all_slave_en, + SHU_CA_DLL1_RG_ARDLL_PGAIN_CA, 0, + SHU_CA_DLL1_RG_ARDLL_PSJP_EN_CA, 1, + SHU_CA_DLL1_RG_ARDLL_PHDIV_CA, 1, + SHU_CA_DLL1_RG_ARDLL_UDIV_EN_CA, 1, + SHU_CA_DLL1_RG_ARDLL_PS_EN_CA, 1, + SHU_CA_DLL1_RG_ARDLL_PD_CK_SEL_CA, + !(a_cfg->all_slave_en)); + } + dramc_set_broadcast(DRAMC_BROADCAST_ON); + } else { + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_dll0, + SHU_CA_DLL0_RG_ARDLL_GAIN_CA, + (a_cfg->all_slave_en == 0) ? 6 + gain : 7 + gain, + SHU_CA_DLL0_RG_ARDLL_IDLECNT_CA, + (a_cfg->all_slave_en == 0) ? 9 : 7, + SHU_CA_DLL0_RG_ARDLL_FAST_PSJP_CA, + !(a_cfg->all_slave_en), + SHU_CA_DLL0_RG_ARDLL_GEAR2_PSJP_CA, 0, + SHU_CA_DLL0_RG_ARDLL_FASTPJ_CK_SEL_CA, + a_cfg->all_slave_en); + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_dll1, + SHU_CA_DLL1_RG_ARDLL_PHDET_OUT_SEL_CA, + a_cfg->all_slave_en, + SHU_CA_DLL1_RG_ARDLL_PHDET_IN_SWAP_CA, + a_cfg->all_slave_en, + SHU_CA_DLL1_RG_ARDLL_PGAIN_CA, 0, + SHU_CA_DLL1_RG_ARDLL_PSJP_EN_CA, 1, + SHU_CA_DLL1_RG_ARDLL_PHDIV_CA, 1, + SHU_CA_DLL1_RG_ARDLL_UDIV_EN_CA, 1, + SHU_CA_DLL1_RG_ARDLL_PS_EN_CA, 1, + SHU_CA_DLL1_RG_ARDLL_PD_CK_SEL_CA, + !(a_cfg->all_slave_en)); + SET32_BITFIELDS(&ch[1].phy_ao.shu_ca_dll0, + SHU_CA_DLL0_RG_ARDLL_GAIN_CA, 7+gain, + SHU_CA_DLL0_RG_ARDLL_IDLECNT_CA, 7, + SHU_CA_DLL0_RG_ARDLL_FAST_PSJP_CA, 0, + SHU_CA_DLL0_RG_ARDLL_GEAR2_PSJP_CA, 0, + SHU_CA_DLL0_RG_ARDLL_FASTPJ_CK_SEL_CA, 1); + SET32_BITFIELDS(&ch[1].phy_ao.shu_ca_dll1, + SHU_CA_DLL1_RG_ARDLL_PHDET_OUT_SEL_CA, 1, + SHU_CA_DLL1_RG_ARDLL_PHDET_IN_SWAP_CA, 1, + SHU_CA_DLL1_RG_ARDLL_PGAIN_CA, 0, + SHU_CA_DLL1_RG_ARDLL_PSJP_EN_CA, 1, + SHU_CA_DLL1_RG_ARDLL_PHDIV_CA, 1, + SHU_CA_DLL1_RG_ARDLL_UDIV_EN_CA, 1, + SHU_CA_DLL1_RG_ARDLL_PS_EN_CA, 1, + SHU_CA_DLL1_RG_ARDLL_PD_CK_SEL_CA, 0); + dramc_set_broadcast(DRAMC_BROADCAST_ON); + } + + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dll0, + SHU_B0_DLL0_RG_ARDLL_GAIN_B0, 7+gain, + SHU_B0_DLL0_RG_ARDLL_IDLECNT_B0, 7, + SHU_B0_DLL0_RG_ARDLL_FAST_PSJP_B0, 0, + SHU_B0_DLL0_RG_ARDLL_GEAR2_PSJP_B0, 0, + SHU_B0_DLL0_RG_ARDLL_FASTPJ_CK_SEL_B0, 1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dll1, + SHU_B0_DLL1_RG_ARDLL_PHDET_OUT_SEL_B0, 1, + SHU_B0_DLL1_RG_ARDLL_PHDET_IN_SWAP_B0, 1, + SHU_B0_DLL1_RG_ARDLL_PGAIN_B0, 0, + SHU_B0_DLL1_RG_ARDLL_PSJP_EN_B0, 1, + SHU_B0_DLL1_RG_ARDLL_PHDIV_B0, 1, + SHU_B0_DLL1_RG_ARDLL_UDIV_EN_B0, 1, + SHU_B0_DLL1_RG_ARDLL_PS_EN_B0, 1, + SHU_B0_DLL1_RG_ARDLL_PD_CK_SEL_B0, 0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dll0, + SHU_B1_DLL0_RG_ARDLL_GAIN_B1, 7+gain, + SHU_B1_DLL0_RG_ARDLL_IDLECNT_B1, 7, + SHU_B1_DLL0_RG_ARDLL_FAST_PSJP_B1, 0, + SHU_B1_DLL0_RG_ARDLL_GEAR2_PSJP_B1, 0, + SHU_B1_DLL0_RG_ARDLL_FASTPJ_CK_SEL_B1, 1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dll1, + SHU_B1_DLL1_RG_ARDLL_PHDET_OUT_SEL_B1, 1, + SHU_B1_DLL1_RG_ARDLL_PHDET_IN_SWAP_B1, 1, + SHU_B1_DLL1_RG_ARDLL_PGAIN_B1, 0, + SHU_B1_DLL1_RG_ARDLL_PSJP_EN_B1, 1, + SHU_B1_DLL1_RG_ARDLL_PHDIV_B1, 1, + SHU_B1_DLL1_RG_ARDLL_UDIV_EN_B1, 1, + SHU_B1_DLL1_RG_ARDLL_PS_EN_B1, 1, + SHU_B1_DLL1_RG_ARDLL_PD_CK_SEL_B1, 0); +} + +static void ana_rx_shuffle_config(dramc_subsys_config *subsys) +{ + u8 rdqs_se_en; + u8 dqsien_mode; + u8 rank_mode; + + rdqs_se_en = 0; + dqsien_mode = subsys->dfs_gp->dqsien_mode; + rank_mode = subsys->a_cfg->rank_mode; + + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq10, + SHU_B0_DQ10_RG_RX_ARDQS_SE_EN_B0, rdqs_se_en, + SHU_B0_DQ10_RG_RX_ARDQS_DQSIEN_MODE_B0, dqsien_mode, + SHU_B0_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B0, 1, + SHU_B0_DQ10_RG_RX_ARDQS_RANK_SEL_LAT_EN_B0, rank_mode, + SHU_B0_DQ10_RG_RX_ARDQS_DQSIEN_RANK_SEL_LAT_EN_B0, rank_mode); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq11, + SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B0, rank_mode, + SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B0, rank_mode); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq2, + SHU_B0_DQ2_RG_ARPI_OFFSET_LAT_EN_B0, rank_mode, + SHU_B0_DQ2_RG_ARPI_OFFSET_ASYNC_EN_B0, rank_mode); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq10, + SHU_B1_DQ10_RG_RX_ARDQS_SE_EN_B1, rdqs_se_en, + SHU_B1_DQ10_RG_RX_ARDQS_DQSIEN_MODE_B1, dqsien_mode, + SHU_B1_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B1, 1, + SHU_B1_DQ10_RG_RX_ARDQS_RANK_SEL_LAT_EN_B1, rank_mode, + SHU_B1_DQ10_RG_RX_ARDQS_DQSIEN_RANK_SEL_LAT_EN_B1, rank_mode); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq11, + SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B1, rank_mode, + SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_LAT_EN_B1, rank_mode); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq2, + SHU_B1_DQ2_RG_ARPI_OFFSET_LAT_EN_B1, rank_mode, + SHU_B1_DQ2_RG_ARPI_OFFSET_ASYNC_EN_B1, rank_mode); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq10, + SHU_B0_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B0, 0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq2, + SHU_B0_DQ2_RG_ARPI_OFFSET_LAT_EN_B0, 0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq10, + SHU_B1_DQ10_RG_RX_ARDQS_DLY_LAT_EN_B1, 0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq2, + SHU_B1_DQ2_RG_ARPI_OFFSET_LAT_EN_B1, 0); + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd10, + SHU_CA_CMD10_RG_RX_ARCLK_RANK_SEL_LAT_EN_CA, 1, + SHU_CA_CMD10_RG_RX_ARCLK_DQSIEN_RANK_SEL_LAT_EN_CA, 1); + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd11, + SHU_CA_CMD11_RG_RX_ARCA_RANK_SEL_LAT_EN_CA, 1); +} + +static void ana_config_nonshuffle(dram_freq_grp freq_group, ana_top_config *a_cfg) +{ + suspend_on(); + spm_control(a_cfg); + ana_tx_nonshuffle_config(a_cfg); + ana_rx_nonshuffle_config(); + dig_dcm_nonshuffle_config(); + ana_imp_configure(); + ana_dll_non_shuffle_config(freq_group, a_cfg); +} + +static void ana_config_shuffle(dram_freq_grp freq_group, dramc_subsys_config *subsys) +{ + ana_top_config *a_cfg = subsys->a_cfg; + ana_dvfs_core *dvfs_core = subsys->dvfs_core; + + ana_pll_shuffle_Config(dvfs_core); + ana_arpi_shuffle_config(a_cfg, dvfs_core); + ana_tx_shuffle_config(a_cfg); + ana_rx_shuffle_config(subsys); + dig_phy_shu_misc_cg_ctrl(); + ana_clk_div_config_setting(dvfs_core, a_cfg); + ana_dll_shuffle_config(freq_group, a_cfg); +} + +static void ana_phy_config(dram_freq_grp freq_group, dramc_subsys_config *subsys) +{ + ana_top_config *a_cfg = subsys->a_cfg; + + ana_config_nonshuffle(freq_group, a_cfg); + ana_config_shuffle(freq_group, subsys); +} + +static void ana_clockoff_sequence(void) +{ + SET32_BITFIELDS(&ch[0].phy_ao.misc_cg_ctrl0, + MISC_CG_CTRL0_CLK_MEM_SEL, 0, + MISC_CG_CTRL0_W_CHG_MEM, 1); + udelay(1); + SET32_BITFIELDS(&ch[0].phy_ao.misc_cg_ctrl0, + MISC_CG_CTRL0_W_CHG_MEM, 0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dll1, + SHU_B0_DLL1_RG_ARDLL_PHDET_EN_B0, 0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dll1, + SHU_B1_DLL1_RG_ARDLL_PHDET_EN_B1, 0); + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_dll1, + SHU_CA_DLL1_RG_ARDLL_PHDET_EN_CA, 0); + + dramc_set_broadcast(DRAMC_BROADCAST_ON); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dll_arpi2, + SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_B0, 0x1, + SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B0, 0x1, + SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCTL_B0, 0x1, + SHU_B0_DLL_ARPI2_RG_ARPI_CG_FB_B0, 0x1, + SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQS_B0, 0x1, + SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQM_B0, 0x1, + SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQ_B0, 0x1, + SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B0, 0x1, + SHU_B0_DLL_ARPI2_RG_ARPI_MPDIV_CG_B0, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dll_arpi2, + SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCK_B1, 0x1, + SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B1, 0x1, + SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCTL_B1, 0x1, + SHU_B1_DLL_ARPI2_RG_ARPI_CG_FB_B1, 0x1, + SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQS_B1, 0x1, + SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQM_B1, 0x1, + SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQ_B1, 0x1, + SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B1, 0x1, + SHU_B1_DLL_ARPI2_RG_ARPI_MPDIV_CG_B1, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_dll_arpi2, + SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCK_CA, 0x1, + SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_CA, 0x1, + SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCTL_CA, 0x1, + SHU_CA_DLL_ARPI2_RG_ARPI_CG_FB_CA, 0x1, + SHU_CA_DLL_ARPI2_RG_ARPI_CG_CS, 0x1, + SHU_CA_DLL_ARPI2_RG_ARPI_CG_CLK, 0x1, + SHU_CA_DLL_ARPI2_RG_ARPI_CG_CMD, 0x1, + SHU_CA_DLL_ARPI2_RG_ARPI_CG_CLKIEN, 0x1, + SHU_CA_DLL_ARPI2_RG_ARPI_MPDIV_CG_CA, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.shu_pll2, + SHU_PLL2_RG_RPHYPLL_ADA_MCK8X_EN_SHU, 0); + SET32_BITFIELDS(&ch[0].phy_ao.phypll2, + PHYPLL2_RG_RPHYPLL_AD_MCK8X_EN, 0, + PHYPLL2_RG_RPHYPLL_ADA_MCK8X_EN, 0); + SET32_BITFIELDS(&ch[0].phy_ao.phypll0, PHYPLL0_RG_RPHYPLL_EN, 0); + SET32_BITFIELDS(&ch[0].phy_ao.phypll2, PHYPLL2_RG_RPHYPLL_RESETB, 0); +} + +static void ana_pll_sequence(void) +{ + SET32_BITFIELDS(&ch[0].phy_ao.phypll2, PHYPLL2_RG_RPHYPLL_RESETB, 1); + SET32_BITFIELDS(&ch[0].phy_ao.phypll0, PHYPLL0_RG_RPHYPLL_EN, 1); + udelay(20); +} + +static void ana_midpi_sequence(ana_dvfs_core *dvfs_core) +{ + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq1, + SHU_B0_DQ1_RG_ARPI_MIDPI_LDO_VREF_SEL_B0, 1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq1, + SHU_B1_DQ1_RG_ARPI_MIDPI_LDO_VREF_SEL_B1, 1); + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd1, + SHU_CA_CMD1_RG_ARPI_MIDPI_LDO_VREF_SEL_CA, 1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dll_arpi2, + SHU_B0_DLL_ARPI2_RG_ARPI_MPDIV_CG_B0, 1, + SHU_B0_DLL_ARPI2_RG_ARPI_CG_FB_B0, 1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dll_arpi2, + SHU_B1_DLL_ARPI2_RG_ARPI_MPDIV_CG_B1, 1, + SHU_B1_DLL_ARPI2_RG_ARPI_CG_FB_B1, 1); + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_dll_arpi2, + SHU_CA_DLL_ARPI2_RG_ARPI_MPDIV_CG_CA, 1, + SHU_CA_DLL_ARPI2_RG_ARPI_CG_FB_CA, 1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dll_arpi2, + SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_B0, 0x1, + SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B0, 0x1, + SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCTL_B0, 0x1, + SHU_B0_DLL_ARPI2_RG_ARPI_CG_FB_B0, 0x1, + SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQS_B0, 0x1, + SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQM_B0, 0x1, + SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQ_B0, 0x1, + SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B0, 0x1, + SHU_B0_DLL_ARPI2_RG_ARPI_MPDIV_CG_B0, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dll_arpi2, + SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCK_B1, 0x1, + SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B1, 0x1, + SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCTL_B1, 0x1, + SHU_B1_DLL_ARPI2_RG_ARPI_CG_FB_B1, 0x1, + SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQS_B1, 0x1, + SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQM_B1, 0x1, + SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQ_B1, 0x1, + SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B1, 0x1, + SHU_B1_DLL_ARPI2_RG_ARPI_MPDIV_CG_B1, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_dll_arpi2, + SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCK_CA, 0x1, + SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_CA, 0x1, + SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCTL_CA, 0x1, + SHU_CA_DLL_ARPI2_RG_ARPI_CG_FB_CA, 0x1, + SHU_CA_DLL_ARPI2_RG_ARPI_CG_CS, 0x1, + SHU_CA_DLL_ARPI2_RG_ARPI_CG_CLK, 0x1, + SHU_CA_DLL_ARPI2_RG_ARPI_CG_CMD, 0x1, + SHU_CA_DLL_ARPI2_RG_ARPI_CG_CLKIEN, 0x1, + SHU_CA_DLL_ARPI2_RG_ARPI_MPDIV_CG_CA, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.shu_pll2, + SHU_PLL2_RG_RPHYPLL_ADA_MCK8X_EN_SHU, 0); + SET32_BITFIELDS(&ch[0].phy_ao.phypll2, + PHYPLL2_RG_RPHYPLL_AD_MCK8X_EN, 0, + PHYPLL2_RG_RPHYPLL_ADA_MCK8X_EN, 0); + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd1, + SHU_CA_CMD1_RG_ARPI_MIDPI_EN_CA, !(dvfs_core->ca_ckdiv4_en), + SHU_CA_CMD1_RG_ARPI_MIDPI_CKDIV4_EN_CA, dvfs_core->ca_ckdiv4_en); + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd1, + SHU_CA_CMD1_RG_ARPI_MIDPI_CKDIV4_PREDIV_EN_CA, dvfs_core->ca_prediv_en); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].b0_shu_midpi_ctrl, + B0_SHU_MIDPI_CTRL_MIDPI_ENABLE_B0, + (!(dvfs_core->dq_semi_open)) && (!(dvfs_core->dq_ckdiv4_en)), + B0_SHU_MIDPI_CTRL_MIDPI_DIV4_ENABLE_B0, + (!(dvfs_core->dq_semi_open)) && (dvfs_core->dq_ckdiv4_en)); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].b0_shu_midpi_ctrl, + B1_SHU_MIDPI_CTRL_MIDPI_ENABLE_B1, + (!(dvfs_core->dq_semi_open)) && (!(dvfs_core->dq_ckdiv4_en)), + B1_SHU_MIDPI_CTRL_MIDPI_DIV4_ENABLE_B1, + (!(dvfs_core->dq_semi_open)) && (dvfs_core->dq_ckdiv4_en)); + SET32_BITFIELDS(&ch[0].phy_ao.ca_shu_midpi_ctrl, + CA_SHU_MIDPI_CTRL_MIDPI_ENABLE_CA, !(dvfs_core->ca_ckdiv4_en), + CA_SHU_MIDPI_CTRL_MIDPI_DIV4_ENABLE_CA, dvfs_core->ca_ckdiv4_en); + SET32_BITFIELDS(&ch[0].phy_ao.ca_dll_arpi0, + CA_DLL_ARPI0_RG_ARPI_RESETB_CA, 0); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dll_arpi0, + B0_DLL_ARPI0_RG_ARPI_RESETB_B0, 0); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dll_arpi0, + B1_DLL_ARPI0_RG_ARPI_RESETB_B1, 0); + SET32_BITFIELDS(&ch[0].phy_ao.ca_dll_arpi0, + CA_DLL_ARPI0_RG_ARPI_RESETB_CA, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dll_arpi0, + B0_DLL_ARPI0_RG_ARPI_RESETB_B0, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dll_arpi0, + B1_DLL_ARPI0_RG_ARPI_RESETB_B1, 1); + SET32_BITFIELDS(&ch[0].phy_ao.shu_pll2, + SHU_PLL2_RG_RPHYPLL_ADA_MCK8X_EN_SHU, 1); + SET32_BITFIELDS(&ch[0].phy_ao.phypll2, + PHYPLL2_RG_RPHYPLL_AD_MCK8X_EN, 1, + PHYPLL2_RG_RPHYPLL_ADA_MCK8X_EN, 1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dll_arpi2, + SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_B0, 0x0, + SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B0, 0x0, + SHU_B0_DLL_ARPI2_RG_ARPI_CG_MCTL_B0, 0x0, + SHU_B0_DLL_ARPI2_RG_ARPI_CG_FB_B0, 0x0, + SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQS_B0, 0x0, + SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQM_B0, 0x0, + SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQ_B0, 0x0, + SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B0, 0x0, + SHU_B0_DLL_ARPI2_RG_ARPI_MPDIV_CG_B0, dvfs_core->dq_semi_open); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dll_arpi2, + SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCK_B1, 0x0, + SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_B1, 0x0, + SHU_B1_DLL_ARPI2_RG_ARPI_CG_MCTL_B1, 0x0, + SHU_B1_DLL_ARPI2_RG_ARPI_CG_FB_B1, 0x0, + SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQS_B1, 0x0, + SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQM_B1, 0x0, + SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQ_B1, 0x0, + SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B1, 0x0, + SHU_B1_DLL_ARPI2_RG_ARPI_MPDIV_CG_B1, dvfs_core->dq_semi_open); + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_dll_arpi2, + SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCK_CA, 0x0, + SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCK_FB2DLL_CA, 0x0, + SHU_CA_DLL_ARPI2_RG_ARPI_CG_MCTL_CA, 0x0, + SHU_CA_DLL_ARPI2_RG_ARPI_CG_FB_CA, 0x0, + SHU_CA_DLL_ARPI2_RG_ARPI_CG_CS, 0x0, + SHU_CA_DLL_ARPI2_RG_ARPI_CG_CLK, 0x0, + SHU_CA_DLL_ARPI2_RG_ARPI_CG_CMD, 0x0, + SHU_CA_DLL_ARPI2_RG_ARPI_CG_CLKIEN, 0x0, + SHU_CA_DLL_ARPI2_RG_ARPI_MPDIV_CG_CA, 0x0); +} + +static void ana_clock_switch(ana_dvfs_core *a_dvfs_cor) +{ + if (a_dvfs_cor->dq_ca_open) { + SET32_BITFIELDS(&ch[0].phy_ao.misc_cg_ctrl0, + MISC_CG_CTRL0_RESERVED_MISC_CG_CTRL0_BIT3_1, 1); + udelay(1); + SET32_BITFIELDS(&ch[0].phy_ao.misc_cg_ctrl0, + MISC_CG_CTRL0_RESERVED_MISC_CG_CTRL0_BIT3_1, 0); + } + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.misc_ckmux_sel, + MISC_CKMUX_SEL_R_PHYCTRLDCM, 1, + MISC_CKMUX_SEL_R_PHYCTRLMUX, 1); + + dramc_set_broadcast(DRAMC_BROADCAST_ON); + SET32_BITFIELDS(&ch[0].phy_ao.misc_cg_ctrl0, + MISC_CG_CTRL0_CLK_MEM_SEL, 1, + MISC_CG_CTRL0_W_CHG_MEM, 1); + + udelay(1); + SET32_BITFIELDS(&ch[0].phy_ao.misc_cg_ctrl0, + MISC_CG_CTRL0_W_CHG_MEM, 0); + SET32_BITFIELDS(&ch[0].phy_ao.misc_cg_ctrl0, + MISC_CG_CTRL0_RG_FREERUN_MCK_CG, 1); + if (a_dvfs_cor->dq_ca_open) + SET32_BITFIELDS(&ch[0].phy_ao.misc_cg_ctrl0, + MISC_CG_CTRL0_RESERVED_MISC_CG_CTRL0_BIT7, 1); +} + +static void ana_dll_sequence(ana_dvfs_core *dvfs_core, ana_top_config *a_cfg) +{ + u8 dll_async_en; + u8 all_slave_en; + + dll_async_en = a_cfg->dll_async_en; + all_slave_en = a_cfg->all_slave_en; + + dramc_dbg("[ANA_INIT] DLL >>\n"); + SET32_BITFIELDS(&ch[0].phy_ao.ca_cmd8, + CA_CMD8_RG_ARDLL_RESETB_CA, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq8, + B0_DQ8_RG_ARDLL_RESETB_B0, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq8, + B1_DQ8_RG_ARDLL_RESETB_B1, 1); + if (all_slave_en == 1) { + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_dll1, + SHU_CA_DLL1_RG_ARDLL_PHDET_EN_CA, 1); + + dramc_set_broadcast(DRAMC_BROADCAST_ON); + udelay(1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dll1, + SHU_B0_DLL1_RG_ARDLL_PHDET_EN_B0, !(dvfs_core->dq_semi_open)); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dll1, + SHU_B1_DLL1_RG_ARDLL_PHDET_EN_B1, !(dvfs_core->dq_semi_open)); + udelay(1); + } else { + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + if (dll_async_en == 1) { + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_dll1, + SHU_CA_DLL1_RG_ARDLL_PHDET_EN_CA, 1); + udelay(1); + } else { + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_dll1, + SHU_CA_DLL1_RG_ARDLL_PHDET_EN_CA, 1); + udelay(1); + SET32_BITFIELDS(&ch[1].phy_ao.shu_ca_dll1, + SHU_CA_DLL1_RG_ARDLL_PHDET_EN_CA, 1); + udelay(1); + } + dramc_set_broadcast(DRAMC_BROADCAST_ON); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dll1, + SHU_B0_DLL1_RG_ARDLL_PHDET_EN_B0, !(dvfs_core->dq_semi_open)); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dll1, + SHU_B1_DLL1_RG_ARDLL_PHDET_EN_B1, !(dvfs_core->dq_semi_open)); + udelay(1); + } +} + +void ana_clk_div_config( ana_dvfs_core *tr, dvfs_group_config *dfs) +{ + u32 semi_open_fmin = 300; + u32 semi_open_fmax = 500; + u32 pi_fmin = 600; + u32 dq_pick; + u32 ca_pick; + u32 ca_mckio; + u32 mckio_semi = 0; + u16 data_rate = dfs->data_rate; + tr->dq_p2s_ratio = dfs->dq_p2s_ratio; + tr->ckr = dfs->ckr; + + tr->ca_p2s_ratio = tr->dq_p2s_ratio/tr->ckr; + tr->dq_ca_open = ( data_rate < (semi_open_fmin * 2)) ? 1 : 0; + tr->dq_semi_open = ( data_rate/2 < pi_fmin) ? (1-tr->dq_ca_open) : + ((data_rate <= semi_open_fmax*2) ? (1-tr->dq_ca_open) : 0); + tr->ca_semi_open = (( data_rate/(tr->ckr*2) < pi_fmin) ? + ((data_rate/(tr->ckr*2) > semi_open_fmax) ? 0 : + (((tr->ca_p2s_ratio>2)||(tr->dq_semi_open)) * (1-tr->dq_ca_open))) : + tr->dq_semi_open); + tr->ca_full_rate = (tr->dq_ca_open == 1) ? ((tr->ckr>1)?1:0) : + ((tr->dq_semi_open*tr->ca_semi_open*(tr->ckr>>1)) + + (( data_rate/(tr->ckr*2) < pi_fmin) ? (1-tr->ca_semi_open) : 0)); + tr->dq_ckdiv4_en = ( tr->dq_semi_open == 1) ? 0 : + ((( (data_rate/2) < 1200) ? 1 : 0) * (1-tr->dq_ca_open)) ; + + ca_mckio = (data_rate/(tr->ckr*2))*(1+tr->ca_full_rate); + dq_pick = (tr->dq_semi_open == 1) ? 0 : (data_rate/2) ; + ca_pick = (tr->ca_semi_open == 1) ? ca_mckio*2 : ((ca_mckio>=pi_fmin) ? + ca_mckio : (( ca_mckio >= (pi_fmin/2)) ? ca_mckio*2 : ca_mckio *4)); + tr->ca_ckdiv4_en = ((ca_pick < 1200) ? 1 : 0) * ( 1- tr->dq_ca_open) ; + tr->ca_prediv_en = (data_rate >= 4800) ? 1 : 0 ; + + if (data_rate <= 1866) + tr->ph8_dly = 0; + else if (data_rate <= 2400) + tr->ph8_dly = 0x11; + else if (data_rate <= 3200) + tr->ph8_dly = 0xc; + else if (data_rate <= 3733) + tr->ph8_dly = 0x9; + else + tr->ph8_dly = 0x7; + + tr->semi_open_ca_pick_mck_ratio = ( mckio_semi == 0) ? + 0 : (ca_pick*tr->dq_p2s_ratio)/data_rate ; + tr->dq_aamck_div = (tr->dq_semi_open == 0) ? + ((tr->dq_p2s_ratio/2)*(1-tr->dq_semi_open)) : 0; + tr->ca_admck_div = ca_pick/(data_rate/tr->dq_p2s_ratio); + tr->dq_track_ca_en = 0 ; + tr->pll_freq = ((dq_pick * 2 * (tr->dq_ckdiv4_en+1)) > (ca_pick * 2 *(tr->ca_ckdiv4_en + 1))) ? + (dq_pick*2*(tr->dq_ckdiv4_en+1)) : (ca_pick*2*(tr->ca_ckdiv4_en+1)); + + if (data_rate==2400) + tr->pll_freq = 2366; + else if (data_rate==1200) + tr->pll_freq = 2288; + else if (data_rate==3200 || data_rate==1600) + tr->pll_freq = 3068; + else if (data_rate==800) + tr->pll_freq = 3016; + else if (data_rate==400) + tr->pll_freq = 4000; +} + +static void ana_init_sequence(ana_dvfs_core *dvfs_core, ana_top_config *a_cfg) +{ + ana_pll_sequence(); + ana_midpi_sequence(dvfs_core); + ana_clock_switch(dvfs_core); + ana_dll_sequence(dvfs_core,a_cfg); +} + +void ana_init(const struct ddr_cali *cali, dramc_subsys_config *subsys) +{ + dram_freq_grp freq_group = cali->freq_group; + + dramc_subsys_pre_config(freq_group, subsys); + dramc_dbg("ANA_INIT\n"); + + SET32_BITFIELDS(&ch[0].phy_ao.ca_cmd2, + CA_CMD2_RG_TX_ARCMD_OE_DIS_CA, 1, + CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA, 0, + CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA, 0xff); + ana_clockoff_sequence(); + ana_phy_config(freq_group, subsys); + ana_init_sequence(subsys->dvfs_core, subsys->a_cfg); + SET32_BITFIELDS(&ch[0].phy_ao.ca_cmd2, + CA_CMD2_RG_TX_ARCMD_OE_DIS_CA, 0, + CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA, 1, + CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA, 0xff); + single_end_dramc_post_config(subsys->lp4_init->lp4y_en); +} diff --git a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c index 1d6b6c2..d32c268 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c @@ -3742,6 +3742,12 @@ static void dramc_setting(const struct ddr_cali *cali) { + dramc_subsys_config subsys; + ana_top_config ana_top_p; + struct gating_config gat_config; + static ana_dvfs_core ana_dvfs; + static dram_config lp4_config; + dvfs_group_config dvfs_config; dram_freq_grp freq_group = cali->freq_group; dramc_set_broadcast(DRAMC_BROADCAST_ON); @@ -3766,6 +3772,13 @@ return; } + resetb_pull_dn(); + subsys.a_cfg = &ana_top_p; + subsys.dvfs_core = &ana_dvfs; + subsys.lp4_init = &lp4_config; + subsys.dfs_gp = &dvfs_config; + subsys.gat_c = &gat_config; + ana_init(cali, &subsys); update_initial_settings(cali); dramc_set_broadcast(DRAMC_BROADCAST_OFF); } diff --git a/src/soc/mediatek/mt8192/dramc_subsys_config.c b/src/soc/mediatek/mt8192/dramc_subsys_config.c new file mode 100644 index 0000000..146e073 --- /dev/null +++ b/src/soc/mediatek/mt8192/dramc_subsys_config.c @@ -0,0 +1,134 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/dramc_pi_api.h> +#include <soc/dramc_register.h> + +static u8 get_dram_RL_WL_mr_field_config(dram_freq_grp freq_group) +{ + u8 mr2_rl_wl = 2; + + switch(freq_group) { + case DDRFREQ_400: + case DDRFREQ_600: + case DDRFREQ_800: + mr2_rl_wl = 2; + break; + case DDRFREQ_933: + mr2_rl_wl = 3; + break; + case DDRFREQ_1200: + mr2_rl_wl = 4; + break; + case DDRFREQ_1600: + mr2_rl_wl = 5; + break; + case DDRFREQ_2133: + mr2_rl_wl = 7; + break; + default: + dramc_dbg("ERROR: Unexpected freq:0x%x\n", freq_group); + break; + } + + return mr2_rl_wl; +} + +void dram_configure(dram_freq_grp freq_group, dram_config *tr) +{ + tr->mr_wl = get_dram_RL_WL_mr_field_config(freq_group); + tr->dbi_wr = 0; + tr->dbi_rd = 0; + tr->lp4y_en = 0; + tr->work_fsp = (freq_group > DDRFREQ_1200) ? 1 : 0; +} + +void dramc_subsys_pre_config(dram_freq_grp freq_group, dramc_subsys_config *subsys) +{ + ana_top_config *a_cfg = subsys->a_cfg; + dram_config *lp4_init = subsys->lp4_init; + dvfs_group_config *dfs_gp = subsys->dfs_gp; + + subsys->freq_group = freq_group; + dfs_gp->ckr = 1; + dfs_gp->dqsien_mode = 1; + lp4_init->ex_row_en[RANK_0] = (get_row_width_from_emi(RANK_0) >= 18) ? 1 : 0; + lp4_init->ex_row_en[RANK_1] = (get_row_width_from_emi(RANK_1) >= 18) ? 1 : 0; + lp4_init->lp4y_en = 0; + a_cfg->new_8x_mode = 1; + a_cfg->aphy_comb_en = 1 ; + a_cfg->dll_idle_mode = 1; + a_cfg->rank_mode = 1; + a_cfg->dll_async_en = 0; + + switch (freq_group) { + case DDRFREQ_400: + dfs_gp->data_rate = 800; + dfs_gp->dq_p2s_ratio = 4; + break; + case DDRFREQ_600: + dfs_gp->data_rate = 1200; + dfs_gp->dq_p2s_ratio = 8; + break; + case DDRFREQ_800: + dfs_gp->data_rate = 1600; + dfs_gp->dq_p2s_ratio = 8; + break; + case DDRFREQ_933: + dfs_gp->data_rate = 1866; + dfs_gp->dq_p2s_ratio = 8; + break; + case DDRFREQ_1200: + dfs_gp->data_rate = 2400; + dfs_gp->dq_p2s_ratio = 8; + break; + case DDRFREQ_1600: + dfs_gp->data_rate = 3200; + dfs_gp->dq_p2s_ratio = 8; + break; + case DDRFREQ_2133: + dfs_gp->data_rate = 4266; + dfs_gp->dq_p2s_ratio = 8; + break; + default: + die("Invalid DDR frequency group %u\n", freq_group); + return; + } + + dram_configure(freq_group, lp4_init); + + a_cfg->all_slave_en = (freq_group <= DDRFREQ_933) ? 1 : 0; + a_cfg->tx_odt_dis = (freq_group <= DDRFREQ_1200) ? 1 : 0 ; + + ana_clk_div_config(subsys->dvfs_core, subsys->dfs_gp); +} + +void single_end_dramc_post_config(u8 lp4y_en) +{ + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd13, + SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_SEL_CA, lp4y_en, + SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_EN_CA, lp4y_en); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq13, + SHU_B0_DQ13_RG_TX_ARDQSB_OE_TIE_SEL_B0, lp4y_en, + SHU_B0_DQ13_RG_TX_ARDQSB_OE_TIE_EN_B0, lp4y_en); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq13, + SHU_B1_DQ13_RG_TX_ARDQSB_OE_TIE_SEL_B1, lp4y_en, + SHU_B1_DQ13_RG_TX_ARDQSB_OE_TIE_EN_B1, lp4y_en); + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd0, + SHU_CA_CMD0_R_LP4Y_WDN_MODE_CLK, 0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq0, + SHU_B0_DQ0_R_LP4Y_WDN_MODE_DQS0, 0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq0, + SHU_B1_DQ0_R_LP4Y_WDN_MODE_DQS1, 0); + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd7, + SHU_CA_CMD7_R_LP4Y_SDN_MODE_CLK, 0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq7, + SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0, lp4y_en); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq7, + SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1, lp4y_en); + SET32_BITFIELDS(&ch[0].phy_ao.ca_cmd7, + CA_CMD7_RG_TX_ARCLKB_PULL_DN_LP4Y, 0); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq7, + B0_DQ7_RG_TX_ARDQS0B_PULL_DN_B0_LP4Y, 0); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq7, + B1_DQ7_RG_TX_ARDQS0B_PULL_DN_B1_LP4Y, 0); +} diff --git a/src/soc/mediatek/mt8192/emi.c b/src/soc/mediatek/mt8192/emi.c index b587993..acd605f 100644 --- a/src/soc/mediatek/mt8192/emi.c +++ b/src/soc/mediatek/mt8192/emi.c @@ -320,6 +320,27 @@ return ma_type; } +u32 get_row_width_from_emi(u32 rank) +{ + u32 emi_cona; + u32 shift_row, shift_ext; + int row_width; + + if (rank == 0) { + shift_row = 12; + shift_ext = 22; + } else if (rank == 1) { + shift_row = 14; + shift_ext = 23; + } else + return -1; + + emi_cona = read32(&emi_reg->cona); + row_width = ((emi_cona >> shift_row) & 0x3) | ((emi_cona >> shift_ext) & 0x4); + + return (row_width + 13); +} + static void emi_sw_setting(void) { setbits32(&emi_mpu->mpu_ctrl_d[1], BIT(4)); -- To view, visit https://review.coreboot.org/c/coreboot/+/44727 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53b30a2bbed5acb363f85f7cbc7f255fdbc52304 Gerrit-Change-Number: 44727 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

21 hours, 43 minutes

Change in coreboot[master]: rivers/spi/spi_flash.c: Remove unused <boot_device.h>

by HAOUAS Elyes (Code Review)

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45817 ) Change subject: rivers/spi/spi_flash.c: Remove unused <boot_device.h> ...................................................................... rivers/spi/spi_flash.c: Remove unused <boot_device.h> Change-Id: I7f6a5df455dff8bfdd9940b10bdbfd73454bc881 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/drivers/spi/spi_flash.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/45817/1 diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index f2610a1..66804ec 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <assert.h> -#include <boot_device.h> #include <boot/coreboot_tables.h> #include <console/console.h> #include <string.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/45817 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f6a5df455dff8bfdd9940b10bdbfd73454bc881 Gerrit-Change-Number: 45817 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 days, 9 hours

Change in coreboot[master]: WIP: soc/amd/picasso/acpi: Add power resources for UART0

by Raul Rangel (Code Review)

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42474 ) Change subject: WIP: soc/amd/picasso/acpi: Add power resources for UART0 ...................................................................... WIP: soc/amd/picasso/acpi: Add power resources for UART0 BUG=b:153001807 TEST=suspend and resume with trembyle Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I73c4c7325f1c31238174795b7400eb244cdf8aec --- M src/soc/amd/picasso/acpi/aoac.asl M src/soc/amd/picasso/acpi/sb_fch.asl 2 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/42474/1 diff --git a/src/soc/amd/picasso/acpi/aoac.asl b/src/soc/amd/picasso/acpi/aoac.asl index 6577cfc..036ebc0 100644 --- a/src/soc/amd/picasso/acpi/aoac.asl +++ b/src/soc/amd/picasso/acpi/aoac.asl @@ -140,6 +140,7 @@ AOAC_DEVICE(I2C2, 7, 0) AOAC_DEVICE(I2C3, 8, 0) AOAC_DEVICE(I2C4, 9, 5) + AOAC_DEVICE(FUR0, 11, 0) AOAC_DEVICE(FUR1, 12, 0) AOAC_DEVICE(FUR2, 16, 0) AOAC_DEVICE(FUR3, 26, 0) diff --git a/src/soc/amd/picasso/acpi/sb_fch.asl b/src/soc/amd/picasso/acpi/sb_fch.asl index 00774fd..cb186c4 100644 --- a/src/soc/amd/picasso/acpi/sb_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_fch.asl @@ -122,6 +122,17 @@ Return (Local0) } } + Name (_PR0, Package () { \_SB.AOAC.FUR0 }) + Name (_PR2, Package () { \_SB.AOAC.FUR0 }) + Name (_PR3, Package () { \_SB.AOAC.FUR0 }) + Method (_PS0, 0, Serialized) { + Printf("FUR0._PS0") + \_SB.AOAC.FUR0.TDS = 1 + } + Method (_PS3, 0, Serialized) { + Printf("FUR0._PS3") + \_SB.AOAC.FUR0.TDS = 3 + } } Device (FUR1) { -- To view, visit https://review.coreboot.org/c/coreboot/+/42474 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I73c4c7325f1c31238174795b7400eb244cdf8aec Gerrit-Change-Number: 42474 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

3 days, 6 hours

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coreboot-gerrit September 2020