coreboot-gerrit September 2013

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 89020dd qemu: q35: avoid address conflict
by Ronald G. Minnich 30 Sep '13

30 Sep '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3938 -gerrit commit 89020dd4f7deeb5f2ddc829c3af1731819686ebe Author: Gerd Hoffmann <kraxel(a)redhat.com> Date: Tue Sep 17 09:49:02 2013 +0200 qemu: q35: avoid address conflict Qemu has the fw_cfg interface at 0x510, which conflicts with power management base address in coreboot. Move the pmbase to a non-conflicting address. No need to worry about speedstep, it is not supported by qemu and isn't enabled in the qemu config. Change-Id: I3e87d8301988028ca0ea7d96c08b4e26ac15a7c2 Signed-off-by: Gerd Hoffmann <kraxel(a)redhat.com> --- src/southbridge/intel/i82801ix/i82801ix.h | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h index ca28107..d84af3a 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.h +++ b/src/southbridge/intel/i82801ix/i82801ix.h @@ -29,7 +29,16 @@ #define DEFAULT_TBAR 0xfed1b000 #define DEFAULT_RCBA 0xfed1c000 -#define DEFAULT_PMBASE 0x00000500 /* Speedstep code has this hardcoded, too. */ +#ifdef CONFIG_BOARD_EMULATION_QEMU_X86_Q35 +/* + * Qemu has the fw_cfg interface at 0x510. Move the pmbase to a + * non-conflicting address. No need to worry about speedstep, it + * is not supported by qemu and isn't enabled in the qemu config. + */ +# define DEFAULT_PMBASE 0x00000600 +#else +# define DEFAULT_PMBASE 0x00000500 /* Speedstep code has this hardcoded, too. */ +#endif #define DEFAULT_TCOBASE (DEFAULT_PMBASE + 0x60) #define DEFAULT_GPIOBASE 0x00000580

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Patch set updated for coreboot: 69e0d06 vendorcode/amd/agesa/f16kb: Update Kabini PI from v0.0.1.0 to v1.0.0.7
by Paul Menzel 30 Sep '13

30 Sep '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3935 -gerrit commit 69e0d06f76d740b66ad9d88d3efeaeb855010657 Author: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Date: Wed Jul 31 16:55:26 2013 +0800 vendorcode/amd/agesa/f16kb: Update Kabini PI from v0.0.1.0 to v1.0.0.7 The platform initialization code v1.0.0.7 for Kabini has some enhancements like ECC DIMM support, new CPU microcode rev 0700010B, FCH bug fix (RTC) and so on. Use the name Kabini instead of Kerala everywhere. Change-Id: I186de1aef222cd35ea69efa93967a3ffb8da7248 Signed-off-by: WANG Siyuan <SiYuan.Wang(a)amd.com> Signed-off-by: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> --- src/cpu/amd/agesa/family16kb/Makefile.inc | 3 +- src/vendorcode/amd/agesa/f16kb/AGESA.h | 1 + .../amd/agesa/f16kb/Include/KabiniFt3Install.h | 144 + .../amd/agesa/f16kb/Include/KeralaInstall.h | 143 - .../agesa/f16kb/Include/OptionFamily16hInstall.h | 24 +- .../amd/agesa/f16kb/Include/OptionFchInstall.h | 10 + .../amd/agesa/f16kb/Include/OptionMemoryInstall.h | 48 +- .../amd/agesa/f16kb/Include/PlatformInstall.h | 6 +- .../f16kb/Legacy/PlatformMemoryConfiguration.inc | 2 +- src/vendorcode/amd/agesa/f16kb/Legacy/agesa.inc | 1 + .../Proc/CPU/Family/0x16/KB/F16KbCoreAfterReset.c | 37 +- .../agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbDmi.c | 2 +- .../CPU/Family/0x16/KB/F16KbId7001MicrocodePatch.c | 3567 +++++++++++++++ .../Proc/CPU/Family/0x16/KB/F16KbInitEarlyTable.c | 32 + .../0x16/KB/F16KbMicrocodePatch0700002A_Enc.c | 3539 --------------- .../0x16/KB/F16KbMicrocodePatch07000106_Enc.c | 3539 --------------- .../f16kb/Proc/CPU/Family/0x16/KB/F16KbPciTables.c | 19 +- src/vendorcode/amd/agesa/f16kb/Proc/CPU/cahalt.asm | 367 -- .../amd/agesa/f16kb/Proc/CPU/cahalt64.asm | 173 - .../amd/agesa/f16kb/Proc/Fch/Common/FchCommonCfg.h | 13 +- .../amd/agesa/f16kb/Proc/Fch/Common/FchDef.h | 3 +- src/vendorcode/amd/agesa/f16kb/Proc/Fch/Fch.h | 7 +- .../Family/Yangtze/YangtzeHwAcpiEnvService.c | 13 +- .../Fch/HwAcpi/Family/Yangtze/YangtzeSSService.c | 1 + .../amd/agesa/f16kb/Proc/Fch/HwAcpi/HwAcpiReset.c | 35 +- .../amd/agesa/f16kb/Proc/Fch/Imc/ImcLib.c | 37 + .../Sata/Family/Yangtze/YangtzeSataEnvService.c | 6 +- .../Fch/Sata/Family/Yangtze/YangtzeSataService.c | 23 +- .../Fch/Sd/Family/Yangtze/YangtzeSdEnvService.c | 12 +- .../Spi/Family/Yangtze/YangtzeLpcResetService.c | 36 +- .../Fch/Usb/Family/Yangtze/YangtzeEhciMidService.c | 17 +- .../Fch/Usb/Family/Yangtze/YangtzeXhciEnvService.c | 42 +- .../agesa/f16kb/Proc/GNB/Common/GnbRegistersKB.h | 24 +- .../f16kb/Proc/GNB/Modules/GnbInitKB/AlibSsdtKB.h | 4612 ++++++++------------ .../Modules/GnbInitKB/GfxIntegratedInfoTableKB.c | 5 +- .../Proc/GNB/Modules/GnbInitKB/GfxMidInitKB.c | 2 +- .../f16kb/Proc/GNB/Modules/GnbInitKB/GfxTablesKB.c | 5 +- .../Proc/GNB/Modules/GnbInitKB/GnbSmuFirmwareKB.h | 4388 +++++++++---------- .../f16kb/Proc/GNB/Modules/GnbInitKB/GnbTablesKB.c | 2 +- .../Proc/GNB/Modules/GnbInitKB/PcieEarlyInitKB.c | 6 +- .../Proc/GNB/Modules/GnbInitKB/PcieMidInitKB.c | 86 +- .../amd/agesa/f16kb/Proc/Mem/Feat/DMI/mfDMI.c | 4 +- .../amd/agesa/f16kb/Proc/Mem/Main/mmMemRestore.c | 9 + .../amd/agesa/f16kb/Proc/Mem/NB/KB/mnkb.c | 1 + .../amd/agesa/f16kb/Proc/Mem/NB/KB/mnphykb.c | 8 +- .../amd/agesa/f16kb/Proc/Mem/NB/KB/mns3kb.c | 106 +- src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mndct.c | 1 + src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mnphy.c | 40 +- .../amd/agesa/f16kb/Proc/Mem/Ps/KB/FT3/mpSkbft3.c | 77 +- .../amd/agesa/f16kb/Proc/Mem/Ps/KB/mpSkb3.c | 30 +- .../amd/agesa/f16kb/Proc/Mem/Ps/KB/mpUkb3.c | 106 +- src/vendorcode/amd/agesa/f16kb/Proc/Mem/mn.h | 19 +- src/vendorcode/amd/agesa/f16kb/cpcarmac.inc | 476 -- 53 files changed, 8467 insertions(+), 13442 deletions(-) diff --git a/src/cpu/amd/agesa/family16kb/Makefile.inc b/src/cpu/amd/agesa/family16kb/Makefile.inc index f21459a..f5f204e 100644 --- a/src/cpu/amd/agesa/family16kb/Makefile.inc +++ b/src/cpu/amd/agesa/family16kb/Makefile.inc @@ -76,8 +76,7 @@ agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x16/KB/F16KbHtc.c agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x16/KB/F16KbInitEarlyTable.c agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x16/KB/F16KbIoCstate.c agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x16/KB/F16KbLogicalIdTables.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x16/KB/F16KbMicrocodePatch0700002A_Enc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x16/KB/F16KbMicrocodePatch07000106_Enc.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x16/KB/F16KbId7001MicrocodePatch.c agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x16/KB/F16KbMicrocodePatchTables.c agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x16/KB/F16KbMsrTables.c agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x16/KB/F16KbNbAfterReset.c diff --git a/src/vendorcode/amd/agesa/f16kb/AGESA.h b/src/vendorcode/amd/agesa/f16kb/AGESA.h index d71250c..3e58d23 100644 --- a/src/vendorcode/amd/agesa/f16kb/AGESA.h +++ b/src/vendorcode/amd/agesa/f16kb/AGESA.h @@ -2882,6 +2882,7 @@ typedef struct { IN SCI_MAP_CONTROL *CfgFchSciMapControl; ///< FCH SCI Mapping Control IN SATA_PHY_CONTROL *CfgFchSataPhyControl; ///< FCH SATA PHY Control IN GPIO_CONTROL *CfgFchGpioControl; ///< FCH GPIO Control + IN BOOLEAN CfgFchRtcWorkAround; ///< FCH RTC Workaround } FCH_PLATFORM_POLICY; diff --git a/src/vendorcode/amd/agesa/f16kb/Include/KabiniFt3Install.h b/src/vendorcode/amd/agesa/f16kb/Include/KabiniFt3Install.h new file mode 100644 index 0000000..a28dd5e --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Include/KabiniFt3Install.h @@ -0,0 +1,144 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Install of build options for a Kabini platform solution + * + * This file generates the defaults tables for the "Kabini" platform solution + * set of processors. The documented build options are imported from a user + * controlled file for processing. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Core + * @e \$Revision: 69377 $ @e \$Date: 2012-05-08 03:52:23 -0500 (Tue, 08 May 2012) $ + */ +/***************************************************************************** + * + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "AdvancedApi.h" +#include "heapManager.h" +#include "CreateStruct.h" +#include "cpuFeatures.h" +#include "Table.h" +#include "CommonReturns.h" +#include "cpuEarlyInit.h" +#include "cpuLateInit.h" +#include "GnbInterface.h" + +/***************************************************************************** + * Define the RELEASE VERSION string + * + * The Release Version string should identify the next planned release. + * When a branch is made in preparation for a release, the release manager + * should change/confirm that the branch version of this file contains the + * string matching the desired version for the release. The trunk version of + * the file should always contain a trailing 'X'. This will make sure that a + * development build from trunk will not be confused for a released version. + * The release manager will need to remove the trailing 'X' and update the + * version string as appropriate for the release. The trunk copy of this file + * should also be updated/incremented for the next expected version, + trailing 'X' + ****************************************************************************/ + // This is the delivery package title, "KabiniPI " + // This string MUST be exactly 16 characters long +#define AGESA_PACKAGE_STRING {'K', 'a', 'b', 'i', 'n', 'i', 'P', 'I', ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' '} + + // This is the release version number of the AGESA component + // This string MUST be exactly 12 characters long +#define AGESA_VERSION_STRING {'V', '1', '.', '0', '.', '0', '.', '7', ' ', ' ', ' ', ' '} + + +// The Kabini FT3 solution is defined to be family 0x16 models 0x00 - 0x0F in the FT3 sockets. +#define INSTALL_FT3_SOCKET_SUPPORT TRUE +#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE + +#ifdef BLDOPT_REMOVE_FT3_SOCKET_SUPPORT + #if BLDOPT_REMOVE_FT3_SOCKET_SUPPORT == TRUE + #undef INSTALL_FT3_SOCKET_SUPPORT + #define INSTALL_FT3_SOCKET_SUPPORT FALSE + #endif +#endif + + +// The following definitions specify the default values for various parameters in which there are +// no clearly defined defaults to be used in the common file. The values below are based on product +// and BKDG content, please consult the AGESA Memory team for consultation. +#define DFLT_SCRUB_DRAM_RATE (0) +#define DFLT_SCRUB_L2_RATE (0) +#define DFLT_SCRUB_L3_RATE (0) +#define DFLT_SCRUB_IC_RATE (0) +#define DFLT_SCRUB_DC_RATE (0) +#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define DFLT_VRM_SLEW_RATE (5000) + + +#define DFLT_SMBUS0_BASE_ADDRESS 0xB00 +#define DFLT_SMBUS1_BASE_ADDRESS 0xB20 +#define DFLT_SIO_PME_BASE_ADDRESS 0xE00 +#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400 +#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404 +#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x408 +#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410 +#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x420 +#define DFLT_SPI_BASE_ADDRESS 0xFEC10000ul +#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0ul +#define DFLT_HPET_BASE_ADDRESS 0xFED00000ul +#define DFLT_SMI_CMD_PORT 0xB0 +#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 +#define DFLT_GEC_BASE_ADDRESS 0xFED61000ul +#define DFLT_AZALIA_SSID 0x780D1022ul +#define DFLT_SMBUS_SSID 0x780B1022ul +#define DFLT_IDE_SSID 0x780C1022ul +#define DFLT_SATA_AHCI_SSID 0x78011022ul +#define DFLT_SATA_IDE_SSID 0x78001022ul +#define DFLT_SATA_RAID5_SSID 0x78031022ul +#define DFLT_SATA_RAID_SSID 0x78021022ul +#define DFLT_EHCI_SSID 0x78081022ul +#define DFLT_OHCI_SSID 0x78071022ul +#define DFLT_LPC_SSID 0x780E1022ul +#define DFLT_SD_SSID 0x78061022ul +#define DFLT_XHCI_SSID 0x78121022ul +#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE +#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE +#define DFLT_FCH_GPP_LINK_CONFIG PortA4 +#define DFLT_FCH_GPP_PORT0_PRESENT FALSE +#define DFLT_FCH_GPP_PORT1_PRESENT FALSE +#define DFLT_FCH_GPP_PORT2_PRESENT FALSE +#define DFLT_FCH_GPP_PORT3_PRESENT FALSE +#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE +#define OPTION_MICROSERVER TRUE +// Instantiate all solution relevant data. +#include "PlatformInstall.h" + diff --git a/src/vendorcode/amd/agesa/f16kb/Include/KeralaInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/KeralaInstall.h deleted file mode 100644 index 6b16a6c..0000000 --- a/src/vendorcode/amd/agesa/f16kb/Include/KeralaInstall.h +++ /dev/null @@ -1,143 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build options for a Kerala platform solution - * - * This file generates the defaults tables for the "Kerala" platform solution - * set of processors. The documented build options are imported from a user - * controlled file for processing. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 69377 $ @e \$Date: 2012-05-08 03:52:23 -0500 (Tue, 08 May 2012) $ - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#include "cpuRegisters.h" -#include "cpuFamRegisters.h" -#include "cpuFamilyTranslation.h" -#include "AdvancedApi.h" -#include "heapManager.h" -#include "CreateStruct.h" -#include "cpuFeatures.h" -#include "Table.h" -#include "CommonReturns.h" -#include "cpuEarlyInit.h" -#include "cpuLateInit.h" -#include "GnbInterface.h" - -/***************************************************************************** - * Define the RELEASE VERSION string - * - * The Release Version string should identify the next planned release. - * When a branch is made in preparation for a release, the release manager - * should change/confirm that the branch version of this file contains the - * string matching the desired version for the release. The trunk version of - * the file should always contain a trailing 'X'. This will make sure that a - * development build from trunk will not be confused for a released version. - * The release manager will need to remove the trailing 'X' and update the - * version string as appropriate for the release. The trunk copy of this file - * should also be updated/incremented for the next expected version, + trailing 'X' - ****************************************************************************/ - // This is the delivery package title, "KabiniPI " - // This string MUST be exactly 8 characters long -#define AGESA_PACKAGE_STRING {'K', 'a', 'b', 'i', 'n', 'i', 'P', 'I'} - - // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long -#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '1', '.', '0', ' ', ' ', ' ', ' '} - - -// The Kerala solution is defined to be family 0x16 models 0x00 - 0x0F in the FT3 sockets. -#define INSTALL_FT3_SOCKET_SUPPORT TRUE -#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE - -#ifdef BLDOPT_REMOVE_FT3_SOCKET_SUPPORT - #if BLDOPT_REMOVE_FT3_SOCKET_SUPPORT == TRUE - #undef INSTALL_FT3_SOCKET_SUPPORT - #define INSTALL_FT3_SOCKET_SUPPORT FALSE - #endif -#endif - - -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. -#define DFLT_SCRUB_DRAM_RATE (0) -#define DFLT_SCRUB_L2_RATE (0) -#define DFLT_SCRUB_L3_RATE (0) -#define DFLT_SCRUB_IC_RATE (0) -#define DFLT_SCRUB_DC_RATE (0) -#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define DFLT_VRM_SLEW_RATE (5000) - - -#define DFLT_SMBUS0_BASE_ADDRESS 0xB00 -#define DFLT_SMBUS1_BASE_ADDRESS 0xB20 -#define DFLT_SIO_PME_BASE_ADDRESS 0xE00 -#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400 -#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404 -#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x408 -#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410 -#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x420 -#define DFLT_SPI_BASE_ADDRESS 0xFEC10000ul -#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0ul -#define DFLT_HPET_BASE_ADDRESS 0xFED00000ul -#define DFLT_SMI_CMD_PORT 0xB0 -#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 -#define DFLT_GEC_BASE_ADDRESS 0xFED61000ul -#define DFLT_AZALIA_SSID 0x780D1022ul -#define DFLT_SMBUS_SSID 0x780B1022ul -#define DFLT_IDE_SSID 0x780C1022ul -#define DFLT_SATA_AHCI_SSID 0x78011022ul -#define DFLT_SATA_IDE_SSID 0x78001022ul -#define DFLT_SATA_RAID5_SSID 0x78031022ul -#define DFLT_SATA_RAID_SSID 0x78021022ul -#define DFLT_EHCI_SSID 0x78081022ul -#define DFLT_OHCI_SSID 0x78071022ul -#define DFLT_LPC_SSID 0x780E1022ul -#define DFLT_SD_SSID 0x78061022ul -#define DFLT_XHCI_SSID 0x78121022ul -#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE -#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE -#define DFLT_FCH_GPP_LINK_CONFIG PortA4 -#define DFLT_FCH_GPP_PORT0_PRESENT FALSE -#define DFLT_FCH_GPP_PORT1_PRESENT FALSE -#define DFLT_FCH_GPP_PORT2_PRESENT FALSE -#define DFLT_FCH_GPP_PORT3_PRESENT FALSE -#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE -// Instantiate all solution relevant data. -#include "PlatformInstall.h" - diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionFamily16hInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionFamily16hInstall.h index 92dae54..ae9e3ad 100644 --- a/src/vendorcode/amd/agesa/f16kb/Include/OptionFamily16hInstall.h +++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionFamily16hInstall.h @@ -127,6 +127,7 @@ extern F_PERFORM_EARLY_INIT_ON_CORE F16SetBrandIdRegistersAtEarly; extern F_PERFORM_EARLY_INIT_ON_CORE LocalApicInitializationAtEarly; extern F_PERFORM_EARLY_INIT_ON_CORE LoadMicrocodePatchAtEarly; + extern F_PERFORM_EARLY_INIT_ON_CORE F16KbLoadMicrocodePatchAtEarly; CONST S_PERFORM_EARLY_INIT_ON_CORE ROMDATA F16KbEarlyInitBeforeApLaunchOnCoreTable[] = { @@ -143,7 +144,7 @@ {SetRegistersFromTablesAfterApLaunch, PERFORM_EARLY_ANY_CONDITION}, {F16SetBrandIdRegistersAtEarly, PERFORM_EARLY_ANY_CONDITION}, #if OPTION_EARLY_SAMPLES == FALSE - {LoadMicrocodePatchAtEarly, PERFORM_EARLY_ANY_CONDITION}, + {F16KbLoadMicrocodePatchAtEarly, PERFORM_EARLY_ANY_CONDITION}, #endif {NULL, 0} }; @@ -208,25 +209,24 @@ #endif #if (AGESA_ENTRY_INIT_RECOVERY == TRUE) || (AGESA_ENTRY_INIT_EARLY == TRUE) - #define F16_KB_UCODE_002A - #define F16_KB_UCODE_0106 + #define F16_KB_UCODE_7000 + #define F16_KB_UCODE_7001 #if AGESA_ENTRY_INIT_EARLY == TRUE #if OPTION_EARLY_SAMPLES == TRUE + extern CONST UINT8 ROMDATA CpuF16KbId7000MicrocodePatch[]; + #undef F16_KB_UCODE_7000 + #define F16_KB_UCODE_7000 CpuF16KbId7000MicrocodePatch, #endif - extern CONST UINT8 ROMDATA arr1[]; - #undef F16_KB_UCODE_002A - #define F16_KB_UCODE_002A arr1, - - extern CONST UINT8 ROMDATA arr2[]; - #undef F16_KB_UCODE_0106 - #define F16_KB_UCODE_0106 arr2, + extern CONST UINT8 ROMDATA CpuF16KbId7001MicrocodePatch[]; + #undef F16_KB_UCODE_7001 + #define F16_KB_UCODE_7001 CpuF16KbId7001MicrocodePatch, #endif CONST UINT8 ROMDATA *CpuF16KbMicroCodePatchArray[] = { - F16_KB_UCODE_0106 - F16_KB_UCODE_002A + F16_KB_UCODE_7001 + F16_KB_UCODE_7000 NULL }; diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionFchInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionFchInstall.h index 4c927af..4725504 100644 --- a/src/vendorcode/amd/agesa/f16kb/Include/OptionFchInstall.h +++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionFchInstall.h @@ -241,6 +241,7 @@ #define FCH_NO_GPP_SUPPORT TRUE #define FCH_NO_PCIB_SUPPORT TRUE #define FCH_NO_PCIE_SUPPORT TRUE + #define BLDOPT_RTC_WORKAROUND TRUE #else #error FCH_SUPPORT: No chip type selected. #endif @@ -929,6 +930,7 @@ InstallFchInitLatePcie, InstallFchInitLatePcib, InstallFchInitLateSpi, + InstallFchInitMidUsbEhci, InstallFchInitLateUsb, InstallFchInitLateUsbEhci, InstallFchInitLateUsbOhci, @@ -1011,6 +1013,14 @@ #endif +#define DFLT_RTC_WORKAROUND FALSE +#ifdef BLDOPT_RTC_WORKAROUND + #undef CFG_FCH_RTC_WORKAROUND + #define CFG_FCH_RTC_WORKAROUND BLDOPT_RTC_WORKAROUND +#else + #undef CFG_FCH_RTC_WORKAROUND + #define CFG_FCH_RTC_WORKAROUND DFLT_RTC_WORKAROUND +#endif CONST BLDOPT_FCH_FUNCTION ROMDATA BldoptFchFunction = { FP_FCH_INIT_RESET, diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionMemoryInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionMemoryInstall.h index 07becd2..1aaa027 100644 --- a/src/vendorcode/amd/agesa/f16kb/Include/OptionMemoryInstall.h +++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionMemoryInstall.h @@ -1263,16 +1263,34 @@ BOOLEAN MemFS3DefConstructorRet ( #define PSC_TBL_KB_ODT_TRI_FT3 &KBSODdr3ODTTriEntFT3, extern PSC_TBL_ENTRY KBSODdr3CSTriEntFT3; #define PSC_TBL_KB_CS_TRI_FT3 &KBSODdr3CSTriEntFT3, + #undef PSC_TBL_KB_UDIMM3_S2D_FT3 + #ifndef extern_S2DTblEntUFT3 + #define extern_S2DTblEntUFT3 + extern PSC_TBL_ENTRY S2DTblEntUFT3; + #endif + #define PSC_TBL_KB_UDIMM3_S2D_FT3 &S2DTblEntUFT3, #endif #if OPTION_UDIMMS - extern PSC_TBL_ENTRY KBMaxFreqTblEntU; - #define PSC_TBL_KB_UDIMM3_MAX_FREQ &KBMaxFreqTblEntU, - extern PSC_TBL_ENTRY KBDramTermTblEntU; - #define PSC_TBL_KB_UDIMM3_DRAM_TERM &KBDramTermTblEntU, - extern PSC_TBL_ENTRY KBSAOTblEntU3; - #define PSC_TBL_KB_UDIMM3_SAO &KBSAOTblEntU3, + #if (OPTION_MICROSERVER == TRUE) + extern PSC_TBL_ENTRY KBMaxFreqTblEntMicroSrvU6L; + #define PSC_TBL_KB_UDIMM3_MAX_FREQ_6L &KBMaxFreqTblEntMicroSrvU6L, + #else + extern PSC_TBL_ENTRY KBMaxFreqTblEntU6L; + #define PSC_TBL_KB_UDIMM3_MAX_FREQ_6L &KBMaxFreqTblEntU6L, + #endif + extern PSC_TBL_ENTRY KBMaxFreqTblEntU4L; + #define PSC_TBL_KB_UDIMM3_MAX_FREQ_4L &KBMaxFreqTblEntU4L, + #if OPTION_FT3_SOCKET_SUPPORT + extern PSC_TBL_ENTRY KBDramTermTblEntUFT3; + #define PSC_TBL_KB_UDIMM3_DRAM_TERM_FT3 &KBDramTermTblEntUFT3, + extern PSC_TBL_ENTRY KBSAOTblEntU3FT3; + #define PSC_TBL_KB_UDIMM3_SAO_FT3 &KBSAOTblEntU3FT3, + #endif #undef PSC_TBL_KB_UDIMM3_S2D_FT3 - extern PSC_TBL_ENTRY S2DTblEntUFT3; + #ifndef extern_S2DTblEntUFT3 + #define extern_S2DTblEntUFT3 + extern PSC_TBL_ENTRY S2DTblEntUFT3; + #endif #define PSC_TBL_KB_UDIMM3_S2D_FT3 &S2DTblEntUFT3, #endif #if OPTION_SODIMMS @@ -1299,10 +1317,6 @@ BOOLEAN MemFS3DefConstructorRet ( #define PSC_TBL_KB_SODWN_PLUS_SODIMM3_MAX_FREQ_4L &KBMaxFreqTblEntSoDwnPlusSODIMM6L, extern PSC_TBL_ENTRY KBMaxFreqTblEntSoDwn; #define PSC_TBL_KB_SODWN_MAX_FREQ &KBMaxFreqTblEntSoDwn, - extern PSC_TBL_ENTRY KBMaxFreqTblEntU6L; - #define PSC_TBL_KB_UDIMM3_MAX_FREQ_6L &KBMaxFreqTblEntU6L, - extern PSC_TBL_ENTRY KBMaxFreqTblEntU4L; - #define PSC_TBL_KB_UDIMM3_MAX_FREQ_4L &KBMaxFreqTblEntU4L, #undef PSC_TBL_KB_SODIMM3_S2D_FT3 #define PSC_TBL_KB_SODIMM3_S2D_FT3 #endif @@ -1334,8 +1348,8 @@ BOOLEAN MemFS3DefConstructorRet ( #ifndef PSC_TBL_KB_UDIMM3_MAX_FREQ_4L #define PSC_TBL_KB_UDIMM3_MAX_FREQ_4L #endif - #ifndef PSC_TBL_KB_UDIMM3_DRAM_TERM - #define PSC_TBL_KB_UDIMM3_DRAM_TERM + #ifndef PSC_TBL_KB_UDIMM3_DRAM_TERM_FT3 + #define PSC_TBL_KB_UDIMM3_DRAM_TERM_FT3 #endif #ifndef PSC_TBL_KB_SODIMM3_DRAM_TERM #define PSC_TBL_KB_SODIMM3_DRAM_TERM @@ -1355,8 +1369,8 @@ BOOLEAN MemFS3DefConstructorRet ( #ifndef PSC_TBL_KB_SODWN_SAO #define PSC_TBL_KB_SODWN_SAO #endif - #ifndef PSC_TBL_KB_UDIMM3_SAO - #define PSC_TBL_KB_UDIMM3_SAO + #ifndef PSC_TBL_KB_UDIMM3_SAO_FT3 + #define PSC_TBL_KB_UDIMM3_SAO_FT3 #endif #ifndef PSC_TBL_KB_CLK_DIS_FT3 #define PSC_TBL_KB_CLK_DIS_FT3 @@ -1384,7 +1398,7 @@ BOOLEAN MemFS3DefConstructorRet ( }; PSC_TBL_ENTRY* memPSCTblDramTermArrayKB[] = { - PSC_TBL_KB_UDIMM3_DRAM_TERM + PSC_TBL_KB_UDIMM3_DRAM_TERM_FT3 PSC_TBL_KB_SODIMM3_DRAM_TERM PSC_TBL_KB_SODWN_PLUS_SODIMM3_DRAM_TERM PSC_TBL_KB_SODWN_DRAM_TERM @@ -1401,7 +1415,7 @@ BOOLEAN MemFS3DefConstructorRet ( PSC_TBL_KB_SODIMM3_SAO PSC_TBL_KB_SODWN_PLUS_SODIMM3_SAO PSC_TBL_KB_SODWN_SAO - PSC_TBL_KB_UDIMM3_SAO + PSC_TBL_KB_UDIMM3_SAO_FT3 PSC_TBL_END }; diff --git a/src/vendorcode/amd/agesa/f16kb/Include/PlatformInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/PlatformInstall.h index 136b0f4..1295888 100644 --- a/src/vendorcode/amd/agesa/f16kb/Include/PlatformInstall.h +++ b/src/vendorcode/amd/agesa/f16kb/Include/PlatformInstall.h @@ -360,6 +360,9 @@ VOLATILE AMD_MODULE_HEADER mCpuModuleID = { #define OPTION_MEM_RESTORE TRUE #undef OPTION_DIMM_EXCLUDE #define OPTION_DIMM_EXCLUDE TRUE + #ifndef OPTION_MICROSERVER + #define OPTION_MICROSERVER FALSE + #endif #endif #endif @@ -1811,7 +1814,8 @@ FCH_PLATFORM_POLICY FchUserOptions = { CFG_FCH_SD_CLOCK_CONTROL, // CfgFchSdClockControl CFG_FCH_SCI_MAP_LIST, // *CfgFchSciMapControl CFG_FCH_SATA_PHY_LIST, // *CfgFchSataPhyControl - CFG_FCH_GPIO_CONTROL_LIST // *CfgFchGpioControl + CFG_FCH_GPIO_CONTROL_LIST, // *CfgFchGpioControl + CFG_FCH_RTC_WORKAROUND // CfgFchRtcWorkaround }; BUILD_OPT_CFG UserOptions = { diff --git a/src/vendorcode/amd/agesa/f16kb/Legacy/PlatformMemoryConfiguration.inc b/src/vendorcode/amd/agesa/f16kb/Legacy/PlatformMemoryConfiguration.inc index d75d04f..872f973 100644 --- a/src/vendorcode/amd/agesa/f16kb/Legacy/PlatformMemoryConfiguration.inc +++ b/src/vendorcode/amd/agesa/f16kb/Legacy/PlatformMemoryConfiguration.inc @@ -444,7 +444,7 @@ MEMORY_POWER_POLICY_OVERRIDE MACRO PowerPolicy:REQ DB PowerPolicy ENDM -MOTHER_RBOARD_LAYERS MACRO Layers:REQ +MOTHER_BOARD_LAYERS MACRO Layers:REQ DB PSO_MOTHER_BOARD_LAYERS DB 1 DB Layers diff --git a/src/vendorcode/amd/agesa/f16kb/Legacy/agesa.inc b/src/vendorcode/amd/agesa/f16kb/Legacy/agesa.inc index 010db87..7683b15 100644 --- a/src/vendorcode/amd/agesa/f16kb/Legacy/agesa.inc +++ b/src/vendorcode/amd/agesa/f16kb/Legacy/agesa.inc @@ -2453,6 +2453,7 @@ FCH_PLATFORM_POLICY STRUCT CfgFchSciMapControl POINTER ? ; FCH SCI Mapping Control CfgFchSataPhyControl POINTER ? ; FCH SATA PHY Control CfgFchGpioControl POINTER ? ; FCH GPIO Control + CfgFchRtcWorkaround BOOLEAN ? ; FCH RTC Workaround FCH_PLATFORM_POLICY ENDS diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCoreAfterReset.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCoreAfterReset.c index 0ae46c6..5ed8b60 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCoreAfterReset.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCoreAfterReset.c @@ -139,13 +139,13 @@ F16KbPmCoreAfterReset ( LibAmdPciRead (AccessWidth32, PciAddress, &HwPsMaxVal, StdHeader); HwPsMaxVal = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &HwPsMaxVal)->HwPstateMaxVal; - // Launch each local core to perform steps 1 through 3. + // Launch each local core to perform steps 1 through 4. TaskPtr.FuncAddress.PfApTask = F16KbPmCoreAfterResetPhase1OnCore; TaskPtr.DataTransfer.DataSizeInDwords = 0; TaskPtr.ExeFlags = WAIT_FOR_CORE; ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr); - // Launch each local core to perform steps 4 through 6. + // Launch each local core to perform steps 5 through 7. TaskPtr.FuncAddress.PfApTaskI = F16KbPmCoreAfterResetPhase2OnCore; TaskPtr.DataTransfer.DataSizeInDwords = 1; TaskPtr.DataTransfer.DataPtr = &HwPsMaxVal; @@ -176,25 +176,36 @@ F16KbPmCoreAfterResetPhase1OnCore ( IN AMD_CONFIG_PARAMS *StdHeader ) { - UINT64 CofvidSts; - UINT64 LocalMsrRegister; - UINT64 PstateCtrl; + BOOLEAN SkipStep3; + UINT64 CofvidSts; + UINT64 LocalMsrRegister; + UINT64 PstateCtrl; IDS_HDT_CONSOLE (CPU_TRACE, " F16KbPmCoreAfterResetPhase1OnCore\n"); - // 1. Write 0 to MSRC001_0062[PstateCmd] on all cores in the processor. + // 1. If MSRC001_0071[CurPstate] = MSRC001_0071[CurPstateLimit], then skip step 3 for that core + LibAmdMsrRead (MSR_COFVID_STS, &CofvidSts, StdHeader); + if (((COFVID_STS_MSR *) &CofvidSts)->CurPstate == ((COFVID_STS_MSR *) &CofvidSts)->CurPstateLimit) { + SkipStep3 = TRUE; + } else { + SkipStep3 = FALSE; + } + + // 2. Write 0 to MSRC001_0062[PstateCmd] on all cores in the processor. PstateCtrl = 0; LibAmdMsrWrite (MSR_PSTATE_CTL, &PstateCtrl, StdHeader); - // 2. Wait for MSRC001_0071[CurCpuFid, CurCpuDid] = [CpuFid, CpuDid] from + // 3. Wait for MSRC001_0071[CurCpuFid, CurCpuDid] = [CpuFid, CpuDid] from // MSRC001_00[6B:64] indexed by MSRC001_0071[CurPstateLimit]. - do { - LibAmdMsrRead (MSR_COFVID_STS, &CofvidSts, StdHeader); - LibAmdMsrRead ((UINT32) (MSR_PSTATE_0 + (UINT32) (((COFVID_STS_MSR *) &CofvidSts)->CurPstateLimit)), &LocalMsrRegister, StdHeader); - } while ((((COFVID_STS_MSR *) &CofvidSts)->CurCpuFid != ((PSTATE_MSR *) &LocalMsrRegister)->CpuFid) || - (((COFVID_STS_MSR *) &CofvidSts)->CurCpuDid != ((PSTATE_MSR *) &LocalMsrRegister)->CpuDid)); + if (!SkipStep3) { + do { + LibAmdMsrRead (MSR_COFVID_STS, &CofvidSts, StdHeader); + LibAmdMsrRead ((UINT32) (MSR_PSTATE_0 + (UINT32) (((COFVID_STS_MSR *) &CofvidSts)->CurPstateLimit)), &LocalMsrRegister, StdHeader); + } while ((((COFVID_STS_MSR *) &CofvidSts)->CurCpuFid != ((PSTATE_MSR *) &LocalMsrRegister)->CpuFid) || + (((COFVID_STS_MSR *) &CofvidSts)->CurCpuDid != ((PSTATE_MSR *) &LocalMsrRegister)->CpuDid)); + } - // 3. Write MSRC001_0061[PstateMaxVal] to MSRC001_0062[PstateCmd] on all + // 4. Write MSRC001_0061[PstateMaxVal] to MSRC001_0062[PstateCmd] on all // cores in the processor. LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &LocalMsrRegister, StdHeader); ((PSTATE_CTRL_MSR *) &PstateCtrl)->PstateCmd = ((PSTATE_CURLIM_MSR *) &LocalMsrRegister)->PstateMaxVal; diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbDmi.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbDmi.c index 37d0aa0..45b1b8f 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbDmi.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbDmi.c @@ -344,7 +344,7 @@ DmiF16KbGetExtClock ( IN AMD_CONFIG_PARAMS *StdHeader ) { - return (EXTERNAL_CLOCK_DFLT); + return (EXTERNAL_CLOCK_100MHZ); } /* -----------------------------------------------------------------------------*/ diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbId7001MicrocodePatch.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbId7001MicrocodePatch.c new file mode 100644 index 0000000..33596c4 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbId7001MicrocodePatch.c @@ -0,0 +1,3567 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD F16Kb Microcode patch. + * + * F16Kb Microcode Patch rev 0700010B for 7001 or equivalent. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x16/KB + * @e \$Revision: 267923 $ @e \$Date: 2013-07-15 16:49:48 -0400 (Mon, 15 Jul 2013) $ + */ +/***************************************************************************** + * + * Copyright 2008 - 2013 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + * + ***************************************************************************/ + + + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "cpuRegisters.h" +#include "cpuEarlyInit.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +UCODE_VS_FLAG (0700010B) + +// Encrypt Patch code 0700010B for 7001 and equivalent + +CONST UINT8 ROMDATA CpuF16KbId7001MicrocodePatch [IDS_PAD_4K] = +{ + 0x13, + 0x20, + 0x09, + 0x07, + 0x0b, + 0x01, + 0x00, + 0x07, + 0x03, + 0x80, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x01, + 0x70, + 0x00, + 0x00, + 0x00, + 0xaa, + 0xaa, + 0xaa, + 0x1c, + 0x8a, + 0x19, + 0x02, + 0x24, + 0xb6, + 0x41, + 0xb0, + 0x60, + 0x6a, + 0x6e, + 0xc3, + 0xdb, + 0xae, + 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0xff, + 0x81, + 0x7f, + 0x00, + 0xe1, + 0x1f, + 0xc0, + 0xbf, + 0xff, + 0xbf, + 0x07, + 0x00, + 0xff, + 0x81, + 0x7f, + 0x00, + 0xe1, + 0x1f, + 0xc0, + 0xbf, + 0xff, + 0x81, + 0x7f, + 0x00, + 0xe1, + 0x1f, + 0xc0, + 0xbf, + 0xff, + 0xbf, + 0x07, + 0x00, + 0xff, + 0x81, + 0x7f, + 0x00, + 0xe1, + 0x1f, + 0xc0, + 0xbf, + 0xff, + 0x81, + 0x7f, + 0x00, + 0xe1, + 0x1f, + 0xc0, + 0xbf, + 0xff, + 0xbf, + 0x07, + 0x00, + 0xff, + 0x81, + 0x7f, + 0x00, + 0xe1, + 0x1f, + 0xc0, + 0xbf, + 0xff, + 0x81, + 0x7f, + 0x00, + 0xe1, + 0x1f, + 0xc0, + 0xbf, + 0xff, + 0xbf, + 0x07, + 0x00, + 0xc6, + 0x9c, + 0xc0, + 0x30, + 0x51, + 0x9c, + 0x16, + 0x99, + 0xb1, + 0x07, + 0xa3, + 0x18, + 0xeb, + 0x9c, + 0xf3, + 0x3e, + 0x48, + 0xcf, + 0x1f, + 0xc7, + 0xba, + 0x80, + 0xa7, + 0x9c, + 0x01, + 0x99, + 0xe3, + 0xd8, + 0xa3, + 0xb5, + 0xef, + 0xca, + 0x0e, + 0x43, + 0x9c, + 0xc4, + 0x4c, + 0xa5, + 0x9d, + 0xa0, + 0x33, + 0x4e, + 0xdd, + 0xdf, + 0x14, + 0x59, + 0x8d, + 0x04, + 0xfc, + 0x03, + 0x71, + 0xc7, + 0xd2, + 0x99, + 0xb6, + 0x9d, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, +}; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ \ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbInitEarlyTable.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbInitEarlyTable.c index 9c0e54b..1e1b23d 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbInitEarlyTable.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbInitEarlyTable.c @@ -52,6 +52,7 @@ #include "cpuFamilyTranslation.h" #include "Filecode.h" #include "cpuEarlyInit.h" +#include "cpuFeatures.h" CODE_GROUP (G2_PEI) RDATA_GROUP (G2_PEI) #define FILECODE PROC_CPU_FAMILY_0X16_KB_F16KBINITEARLYTABLE_FILECODE @@ -88,6 +89,13 @@ GetF16KbEarlyInitAfterApLaunchOnCoreTable ( IN AMD_CPU_EARLY_PARAMS *EarlyParams, IN AMD_CONFIG_PARAMS *StdHeader ); + +VOID +F16KbLoadMicrocodePatchAtEarly ( + IN CPU_SPECIFIC_SERVICES *FamilyServices, + IN AMD_CPU_EARLY_PARAMS *EarlyParams, + IN AMD_CONFIG_PARAMS *StdHeader + ); /*---------------------------------------------------------------------------------------- * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- @@ -141,3 +149,27 @@ GetF16KbEarlyInitAfterApLaunchOnCoreTable ( *Table = F16KbEarlyInitAfterApLaunchOnCoreTable; } +/*---------------------------------------------------------------------------------------*/ +/** + * Update microcode patch in current processor for Family16h KB. + * + * This function acts as a wrapper for calling the LoadMicrocodePatch + * routine at AmdInitEarly. + * + * @param[in] FamilyServices The current Family Specific Services. + * @param[in] EarlyParams Service parameters. + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +F16KbLoadMicrocodePatchAtEarly ( + IN CPU_SPECIFIC_SERVICES *FamilyServices, + IN AMD_CPU_EARLY_PARAMS *EarlyParams, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + if (!IsFeatureEnabled (C6Cstate, &EarlyParams->PlatformConfig, StdHeader)) { + AGESA_TESTPOINT (TpProcCpuLoadUcode, StdHeader); + LoadMicrocodePatch (StdHeader); + } +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbMicrocodePatch0700002A_Enc.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbMicrocodePatch0700002A_Enc.c deleted file mode 100644 index 5a010ae..0000000 --- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbMicrocodePatch0700002A_Enc.c +++ /dev/null @@ -1,3539 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD F16Kb Microcode patch. - * - * F16Kb Microcode Patch rev 0700002A for 7000 or equivalent. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x16/KB - * @e \$Revision: 84798 $ @e \$Date: 2012-12-19 21:26:23 -0600 (Wed, 19 Dec 2012) $ - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - - - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuEarlyInit.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -// Encrypt Patch code 0700002A for 7000 and equivalent - -CONST UINT8 ROMDATA arr1 [IDS_PAD_4K] = -{ - 0x12, - 0x20, - 0x18, - 0x12, - 0x2a, - 0x00, - 0x00, - 0x07, - 0x03, - 0x80, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x70, - 0x00, - 0x00, - 0x00, - 0xaa, - 0xaa, - 0xaa, - 0x49, - 0x98, - 0x47, - 0x92, - 0x9e, - 0x94, - 0x1c, - 0x90, - 0x43, - 0x82, - 0xfb, - 0x61, - 0x5c, - 0xc3, - 0x8a, - 0xb1, - 0xd7, - 0x77, - 0xc5, - 0x2f, - 0xe2, - 0x32, - 0x8e, - 0xa2, - 0xfe, - 0x17, - 0x86, - 0x8b, - 0xea, - 0xf8, - 0x9c, - 0x9a, - 0xdb, - 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0xe7, - 0xff, - 0x81, - 0x7f, - 0x2d, - 0xe1, - 0x1f, - 0xe0, - 0xe7, - 0x11, - 0x20, - 0x06, - 0x00, - 0x17, - 0xfc, - 0xbf, - 0x2d, - 0xe0, - 0x1f, - 0xe0, - 0xe7, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xcf, - 0xbf, - 0x11, - 0x80, - 0x06, - 0x00, - 0xfc, - 0xff, - 0xff, - 0x2b, - 0xe1, - 0x1f, - 0xe0, - 0xe7, - 0xff, - 0x81, - 0x7f, - 0x00, - 0xe1, - 0x1f, - 0xc0, - 0xbf, - 0xff, - 0xbf, - 0x07, - 0x00, - 0xe3, - 0xff, - 0xff, - 0x2b, - 0xe1, - 0x1f, - 0xe0, - 0xe7, - 0xee, - 0xff, - 0xff, - 0x2d, - 0xe1, - 0x1f, - 0xe0, - 0xe7, - 0x11, - 0x20, - 0x06, - 0x00, - 0xff, - 0xff, - 0xbf, - 0x2d, - 0xe0, - 0x1f, - 0xe0, - 0xe7, - 0xff, - 0xff, - 0xef, - 0xff, - 0xaa, - 0xff, - 0xcf, - 0xbf, - 0x11, - 0x80, - 0x06, - 0x00, - 0xf1, - 0xff, - 0xff, - 0x2b, - 0xe1, - 0x1f, - 0xe0, - 0xe7, - 0xff, - 0x81, - 0x7f, - 0x00, - 0xe1, - 0x1f, - 0xc0, - 0xbf, - 0xff, - 0xbf, - 0x07, - 0x00, - 0xff, - 0xff, - 0xbf, - 0x2d, - 0xe0, - 0x1f, - 0xe0, - 0xe7, - 0xff, - 0xff, - 0x9f, - 0xef, - 0xd5, - 0xfe, - 0xcf, - 0xbf, - 0x11, - 0x80, - 0x06, - 0x00, - 0xf0, - 0xff, - 0xff, - 0x2b, - 0xe1, - 0x1f, - 0xe0, - 0xe7, - 0xff, - 0x81, - 0x7f, - 0x00, - 0xe1, - 0x1f, - 0xc0, - 0xbf, - 0xff, - 0xbf, - 0x07, - 0x00, - 0xff, - 0x81, - 0x7f, - 0x2b, - 0xe1, - 0x1f, - 0xe0, - 0xe7, - 0xfe, - 0xff, - 0xff, - 0x2d, - 0xe1, - 0x1f, - 0xe0, - 0xe7, - 0x11, - 0x20, - 0x06, - 0x00, - 0xff, - 0x81, - 0x7f, - 0x00, - 0xe1, - 0x1f, - 0xc0, - 0xbf, - 0xff, - 0x81, - 0x7f, - 0x00, - 0xe1, - 0x1f, - 0xc0, - 0xbf, - 0x56, - 0x5f, - 0x06, - 0x00, - 0x0a, - 0x02, - 0xff, - 0x2e, - 0xe0, - 0x1f, - 0xe0, - 0xe7, - 0xe7, - 0xff, - 0xff, - 0x2e, - 0xe0, - 0x9f, - 0xeb, - 0xfa, - 0xff, - 0xbf, - 0x07, - 0x00, - 0xe0, - 0xff, - 0xff, - 0x29, - 0xe1, - 0x1f, - 0xe0, - 0xac, - 0xdf, - 0xfb, - 0xff, - 0x2c, - 0xe1, - 0x1f, - 0xe0, - 0xe7, - 0xff, - 0xbf, - 0x07, - 0x00, - 0xff, - 0xd7, - 0x7f, - 0x2b, - 0xe1, - 0x5f, - 0xaa, - 0xff, - 0xf7, - 0xdb, - 0x3a, - 0x2c, - 0xa0, - 0x9f, - 0xcb, - 0xe7, - 0xfb, - 0xbf, - 0x07, - 0x00, - 0xff, - 0xd7, - 0x7a, - 0x2c, - 0xa0, - 0x9f, - 0xcb, - 0xe7, - 0xff, - 0x81, - 0x7f, - 0x00, - 0xe1, - 0x1f, - 0xc0, - 0xbf, - 0xff, - 0xbf, - 0x07, - 0x00, - 0xdb, - 0xf7, - 0xff, - 0x3e, - 0xe0, - 0x1f, - 0x2b, - 0xfb, - 0xff, - 0x81, - 0x7f, - 0x00, - 0xe1, - 0x1f, - 0xc0, - 0xbf, - 0xe6, - 0x58, - 0x06, - 0x00, - 0xff, - 0xd1, - 0x7f, - 0x28, - 0xe0, - 0x1f, - 0x6b, - 0xf1, - 0x67, - 0xd1, - 0x3a, - 0x00, - 0xa0, - 0x9f, - 0xcb, - 0xe7, - 0x46, - 0xa1, - 0x06, - 0x00, - 0xff, - 0x81, - 0x7f, - 0x00, - 0xe1, - 0x1f, - 0xc0, - 0xbf, - 0xff, - 0x81, - 0x7f, - 0x00, - 0xe1, - 0x1f, - 0xc0, - 0xbf, - 0x45, - 0xa1, - 0x06, - 0x00, - 0xf8, - 0xff, - 0xff, - 0x00, - 0xe1, - 0x9d, - 0x0b, - 0xf9, - 0xfe, - 0xff, - 0xff, - 0x00, - 0xe1, - 0xcf, - 0x43, - 0xd7, - 0xff, - 0xbf, - 0x07, - 0x00, - 0x2b, - 0xce, - 0x38, - 0x00, - 0xa0, - 0x1f, - 0xc0, - 0xe7, - 0xff, - 0x81, - 0x7f, - 0x00, - 0xe1, - 0x1f, - 0xc0, - 0xbf, - 0x97, - 0x5b, - 0x02, - 0x00, - 0x57, - 0xdc, - 0x38, - 0x00, - 0xc0, - 0xdf, - 0xdb, - 0xeb, - 0xff, - 0x81, - 0x7f, - 0x00, - 0xe1, - 0x1f, - 0xc0, - 0xbf, - 0x9b, - 0x5b, - 0x06, - 0x00, - 0xff, - 0x81, - 0x7f, - 0x00, - 0xe1, - 0x1f, - 0xc0, - 0xbf, - 0xff, - 0x81, - 0x7f, - 0x00, - 0xe1, - 0x1f, - 0xc0, - 0xbf, - 0xff, - 0xbf, - 0x07, - 0x00, - 0xff, - 0x81, - 0x7f, - 0x00, - 0xe1, - 0x1f, - 0xc0, - 0xbf, - 0xff, - 0x81, - 0x7f, - 0x00, - 0xe1, - 0x1f, - 0xc0, - 0xbf, - 0xff, - 0xbf, - 0x07, - 0x00, - 0xff, - 0x81, - 0x7f, - 0x00, - 0xe1, - 0x1f, - 0xc0, - 0xbf, - 0xff, - 0x81, - 0x7f, - 0x00, - 0xe1, - 0x1f, - 0xc0, - 0xbf, - 0xff, - 0xbf, - 0x07, - 0x00, - 0xff, - 0x81, - 0x7f, - 0x00, - 0xe1, - 0x1f, - 0xc0, - 0xbf, - 0xff, - 0x81, - 0x7f, - 0x00, - 0xe1, - 0x1f, - 0xc0, - 0xbf, - 0xff, - 0xbf, - 0x07, - 0x00, - 0xff, - 0x81, - 0x7f, - 0x00, - 0xe1, - 0x1f, - 0xc0, - 0xbf, - 0xff, - 0x81, - 0x7f, - 0x00, - 0xe1, - 0x1f, - 0xc0, - 0xbf, - 0xff, - 0xbf, - 0x07, - 0x00, - 0xff, - 0x81, - 0x7f, - 0x00, - 0xe1, - 0x1f, - 0xc0, - 0xbf, - 0xff, - 0x81, - 0x7f, - 0x00, - 0xe1, - 0x1f, - 0xc0, - 0xbf, - 0xff, - 0xbf, - 0x07, - 0x00, - 0xff, - 0x81, - 0x7f, - 0x00, - 0xe1, - 0x1f, - 0xc0, - 0xbf, - 0xff, - 0x81, - 0x7f, - 0x00, - 0xe1, - 0x1f, - 0xc0, - 0xbf, - 0xff, - 0xbf, - 0x07, - 0x00, - 0xff, - 0x81, - 0x7f, - 0x00, - 0xe1, - 0x1f, - 0xc0, - 0xbf, - 0xff, - 0x81, - 0x7f, - 0x00, - 0xe1, - 0x1f, - 0xc0, - 0xbf, - 0xff, - 0xbf, - 0x07, - 0x00, - 0xbc, - 0xa8, - 0x3e, - 0x11, - 0x69, - 0xce, - 0x06, - 0x3f, - 0xb9, - 0x87, - 0xd7, - 0xdd, - 0xc6, - 0x12, - 0xb6, - 0xe2, - 0xc2, - 0x53, - 0x20, - 0xfb, - 0xea, - 0x71, - 0x72, - 0xb5, - 0xe1, - 0xa6, - 0xd8, - 0xee, - 0x9d, - 0x97, - 0xe6, - 0x72, - 0x3f, - 0x73, - 0x88, - 0xed, - 0x14, - 0x8c, - 0xdf, - 0x5d, - 0x8f, - 0x0d, - 0xd0, - 0x70, - 0x64, - 0x1c, - 0x06, - 0x7f, - 0x59, - 0x93, - 0x32, - 0x55, - 0x2a, - 0x10, - 0x61, - 0xde, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, -}; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbMicrocodePatch07000106_Enc.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbMicrocodePatch07000106_Enc.c deleted file mode 100644 index 85bdc4e..0000000 --- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbMicrocodePatch07000106_Enc.c +++ /dev/null @@ -1,3539 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD F16Kb Microcode patch. - * - * F16Kb Microcode Patch rev 07000106 for 7001 or equivalent. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x16/KB - * @e \$Revision: 86822 $ @e \$Date: 2013-01-28 00:17:14 -0500 (Mon, 28 Jan 2013) $ - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - - - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuEarlyInit.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -// Encrypt Patch code 07000106 for 7001 and equivalent - -CONST UINT8 ROMDATA arr2 [IDS_PAD_4K] = -{ - 0x13, - 0x20, - 0x22, - 0x01, - 0x06, - 0x01, - 0x00, - 0x07, - 0x03, - 0x80, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x01, - 0x70, - 0x00, - 0x00, - 0x00, - 0xaa, - 0xaa, - 0xaa, - 0x49, - 0x66, - 0xa8, - 0x8e, - 0x7a, - 0x20, - 0xc7, - 0xae, - 0xe4, - 0xf4, - 0xb4, - 0x4a, - 0x32, - 0x58, - 0xbb, - 0x8b, - 0x60, - 0x57, - 0x0e, - 0x35, - 0x36, - 0xda, - 0x53, - 0x69, - 0xb7, - 0xaf, - 0x84, - 0xe0, - 0x66, - 0x54, - 0x71, - 0x2a, - 0xef, - 0x0f, - 0xf0, - 0x0e, - 0x9d, - 0x5a, - 0xbe, - 0xbe, - 0x19, - 0x2a, - 0xe1, - 0x53, - 0xdf, - 0x30, - 0x15, - 0xe9, - 0x9e, - 0xa2, - 0xb4, - 0x74, - 0x0f, - 0xfa, - 0x38, - 0x6e, - 0x5c, - 0x08, - 0xa5, - 0xe5, - 0xd7, - 0xc3, - 0x24, - 0x04, - 0x5c, - 0x6e, - 0xf5, - 0x57, - 0xb6, - 0x2e, - 0x41, - 0x1d, - 0x5d, - 0xa2, - 0x62, - 0x9c, - 0xce, - 0x79, - 0xfb, - 0xd8, - 0xda, - 0x01, - 0x36, - 0xfe, - 0xcf, - 0x18, - 0x78, - 0xcd, - 0x8b, - 0x49, - 0x92, - 0x0a, - 0x59, - 0x40, - 0x8f, - 0xc9, - 0x3e, - 0xf6, - 0xd7, - 0xea, - 0x78, - 0x89, - 0xc1, - 0xea, - 0xf8, - 0x2e, - 0x35, - 0xf8, - 0xfb, - 0x15, - 0x48, - 0x8f, - 0x07, - 0xd4, - 0x3f, - 0x1f, - 0x85, - 0x38, - 0x87, - 0x17, - 0x38, - 0x23, - 0x9b, - 0xcc, - 0x4a, - 0xea, - 0xfd, - 0x49, - 0x5a, - 0xfe, - 0xb6, - 0x11, - 0x21, - 0xa6, - 0x5d, - 0x26, - 0x5a, - 0x2e, - 0xc9, - 0x49, - 0x4a, - 0x2a, - 0x5b, - 0xc7, - 0x8f, - 0xde, - 0x65, - 0x27, - 0xfd, - 0x9d, - 0x59, - 0x02, - 0xf9, - 0xad, - 0x13, - 0x4a, - 0x19, - 0xb9, - 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0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, -}; - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPciTables.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPciTables.c index 4cd445e..253d518 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPciTables.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPciTables.c @@ -710,23 +710,6 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F16KbPciRegistersAfterApLaunch[] = 0x08000000, // RegMask }} }, -// D18F3x200 - Performance Mode Control Register -// bits[3] EnMcqPrbPickThrottle = 0x1 -// bits[2] EnDctOddToNcLnkDatXfr = 0x1 -// bits[1] EnDctEvnToNcLnkDatXfr = 0x1 - { - PciRegister, - { - AMD_FAMILY_16, // CpuFamily - AMD_F16_KB_ALL // CpuRevision - }, - {AMD_PF_ALL}, // PlatformFeatures - {{ - MAKE_SBDFO (0, 0, 24, FUNC_3, 0x200), // Address - 0x0000000E, // RegData - 0x0000000E, // RegMask - }} - }, // D18F4x118 - C-state Control 1 // bits[23:21] ClkDivisorCstAct1 = 0x0 // bits[19:18] CacheFlushTmrSelCstAct1 = 0x2 @@ -828,7 +811,7 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F16KbPciRegistersAfterApLaunch[] = }} }, // D18F5x8C -// bits[15] = 0x1 +// bits[15] EnSrqAllocGt31 = 0x1 { PciRegister, { diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cahalt.asm b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cahalt.asm deleted file mode 100644 index a6ca517..0000000 --- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cahalt.asm +++ /dev/null @@ -1,367 +0,0 @@ -;/** -; * @file -; * -; * Agesa pre-memory miscellaneous support, including ap halt loop. -; * -; * @xrefitem bom "File Content Label" "Release Content" -; * @e project: AGESA -; * @e sub-project: CPU -; * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ -; */ -;***************************************************************************** -; - * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;***************************************************************************** - - .XLIST - INCLUDE agesa.inc - INCLUDE cpcarmac.inc - .LIST - - .586P - -;=============================================== -;=============================================== -;== -;== M E M O R Y A B S E N T S E G M E N T -;== -;=============================================== -;=============================================== - .MODEL flat - .CODE -;====================================================================== -; ExecuteFinalHltInstruction: Disables the stack and performs -; a hlt instruction on an AP. -; -; In: -; None -; -; Out: -; None -; -; Destroyed: -; eax, ebx, ecx, edx, esp -; -;====================================================================== -PUBLIC ExecuteFinalHltInstruction -ExecuteFinalHltInstruction PROC NEAR C USES ESI EDI HaltFlags:DWORD, ApMtrrSettingList:PTR, StandardHeader:PTR - - mov esi, StandardHeader ; The code must reference all parameters to avoid a build warning - mov esi, HaltFlags - mov edi, ApMtrrSettingList - ; Do these special steps in case if the core is part of a compute unit - ; Note: The following bits are family specific flags, that gets set during build time, - ; and indicates things like "family cache control methodology", etc. - ; esi bit0 = 0 -> not a Primary core - ; esi bit0 = 1 -> Primary core - ; esi bit1 = 0 -> Cache disable - ; esi bit1 = 1 -> Cache enable - .if (esi & 2h) - AMD_CPUID CPUID_MODEL - shr eax, 20 ; AL = cpu extended family - cmp al, 05h ; Is this family 15h? - jne not_fam15_skip_combineCr0Cd ; Branch if not family15h - - ; Set CombineCr0Cd bit - mov ecx, CU_CFG3 - _RDMSR - bts edx, (COMBINE_CR0_CD - 32) - _WRMSR - -not_fam15_skip_combineCr0Cd: - ; Clear the CR0.CD bit - mov eax, CR0 ; Make sure cache is enabled for all APs - btr eax, CR0_CD - btr eax, CR0_NW - mov CR0, eax ; Write back to CR0 - .else - mov eax, CR0 ; Make sure cache is disabled for all APs - bts eax, CR0_CD ; Disable cache - bts eax, CR0_NW - mov CR0, eax ; Write back to CR0 - .endif - - .if (esi & 1h) - ; This core is a primary core and needs to do all the MTRRs, including shared MTRRs. - mov esi, edi ; Get ApMtrrSettingList - - ; Configure the MTRRs on the AP so - ; when it runs remote code it will execute - ; out of RAM instead of ROM. - - ; Disable MTRRs and turn on modification enable bit - mov ecx, MTRR_SYS_CFG - _RDMSR - btr eax, MTRR_VAR_DRAM_EN ; Disable - bts eax, MTRR_FIX_DRAM_MOD_EN ; Enable - btr eax, MTRR_FIX_DRAM_EN ; Disable - _WRMSR - - ; Setup default values for Fixed-Sized MTRRs - ; Set 7FFFh-00000h as WB - mov ecx, AMD_AP_MTRR_FIX64k_00000 - mov eax, 1E1E1E1Eh - mov edx, eax - _WRMSR - - ; Set 9FFFFh-80000h also as WB - mov ecx, AMD_AP_MTRR_FIX16k_80000 - _WRMSR - - ; Set BFFFFh-A0000h as Uncacheable Memory-mapped IO - mov ecx, AMD_AP_MTRR_FIX16k_A0000 - xor eax, eax - xor edx, edx - _WRMSR - - ; Set DFFFFh-C0000h as Uncacheable Memory-mapped IO - xor eax, eax - xor edx, edx - mov ecx, AMD_AP_MTRR_FIX4k_C0000 - -CDLoop: - _WRMSR - inc ecx - cmp ecx, AMD_AP_MTRR_FIX4k_D8000 - jbe CDLoop - - ; Set FFFFFh-E0000h as Uncacheable Memory - mov eax, 18181818h - mov edx, eax - - mov ecx, AMD_AP_MTRR_FIX4k_E0000 - -EFLoop: - _WRMSR - inc ecx - cmp ecx, AMD_AP_MTRR_FIX4k_F8000 - jbe EFLoop - - ; If IBV provided settings for Fixed-Sized MTRRs, - ; overwrite the default settings. - .if ((esi != 0) && (esi != 0FFFFFFFFh)) - mov ecx, (AP_MTRR_SETTINGS ptr [esi]).MsrAddr - ; While we are not at the end of the list - .while (ecx != CPU_LIST_TERMINAL) - ; Ensure that the MSR address is valid for Fixed-Sized MTRRs - .if ( ((ecx >= AMD_AP_MTRR_FIX4k_C0000) && (ecx <= AMD_AP_MTRR_FIX4k_F8000)) || \ - (ecx == AMD_AP_MTRR_FIX64k_00000) || (ecx == AMD_AP_MTRR_FIX16k_80000 ) || (ecx == AMD_AP_MTRR_FIX16k_A0000)) - mov eax, dword ptr (AP_MTRR_SETTINGS ptr [esi]).MsrData - mov edx, dword ptr (AP_MTRR_SETTINGS ptr [esi+4]).MsrData - _WRMSR - .endif - add esi, sizeof (AP_MTRR_SETTINGS) - mov ecx, (AP_MTRR_SETTINGS ptr [esi]).MsrAddr - .endw - .endif - - ; Enable fixed-range and variable-range MTRRs - mov ecx, AMD_MTRR_DEFTYPE - _RDMSR - bts eax, MTRR_DEF_TYPE_EN ; MtrrDefTypeEn - bts eax, MTRR_DEF_TYPE_FIX_EN ; MtrrDefTypeFixEn - _WRMSR - - ; Enable Top-of-Memory setting - ; Enable use of RdMem/WrMem bits attributes - mov ecx, MTRR_SYS_CFG - _RDMSR - bts eax, MTRR_VAR_DRAM_EN ; Enable - btr eax, MTRR_FIX_DRAM_MOD_EN ; Disable - bts eax, MTRR_FIX_DRAM_EN ; Enable - _WRMSR - - mov esi, (1 SHL FLAG_IS_PRIMARY) - .else ; end if primary core - xor esi, esi - .endif - ; Make sure not to touch any Shared MSR from this point on - - AMD_DISABLE_STACK_FAMILY_HOOK - - bt esi, FLAG_IS_PRIMARY - .if (carry?) - ; restore variable MTRR6 and MTRR7 to default states - mov ecx, AMD_MTRR_VARIABLE_MASK7 ; clear MTRRPhysBase6 MTRRPhysMask6 - xor eax, eax ; and MTRRPhysBase7 MTRRPhysMask7 - xor edx, edx - .while (cx >= AMD_MTRR_VARIABLE_BASE6) - _WRMSR - dec cx - .endw - .endif - -@@: - cli - hlt - jmp @B ;ExecuteHltInstruction - ret -ExecuteFinalHltInstruction ENDP - -;====================================================================== -; ExecuteHltInstruction: Performs a hlt instruction. -; -; In: -; None -; -; Out: -; None -; -; Destroyed: -; eax, ebx, ecx, edx, esp -; -;====================================================================== -PUBLIC ExecuteHltInstruction -ExecuteHltInstruction PROC NEAR C - cli - hlt - ret -ExecuteHltInstruction ENDP - -;====================================================================== -; NmiHandler: Simply performs an IRET. -; -; In: -; None -; -; Out: -; None -; -; Destroyed: -; None -; -;====================================================================== -PUBLIC NmiHandler -NmiHandler PROC NEAR C - iretd -NmiHandler ENDP - -;====================================================================== -; GetCsSelector: Returns the current protected mode CS selector. -; -; In: -; None -; -; Out: -; None -; -; Destroyed: -; None -; -;====================================================================== -PUBLIC GetCsSelector -GetCsSelector PROC NEAR C, CsSelector:PTR - push ax - push ebx - - call FarCallGetCs - mov ebx, CsSelector - mov [ebx], ax - pop ebx - pop ax - ret -GetCsSelector ENDP - -;====================================================================== -; FarCallGetCs: -; -; In: -; None -; -; Out: -; None -; -; Destroyed: -; none -; -;====================================================================== -FarCallGetCs PROC FAR PRIVATE - - mov ax, ss:[esp + 4] - retf - -FarCallGetCs ENDP - -;====================================================================== -; SetIdtr: -; -; In: -; @param[in] IdtPtr Points to IDT table -; -; Out: -; None -; -; Destroyed: -; none -; -;====================================================================== -PUBLIC SetIdtr -SetIdtr PROC NEAR C USES EBX, IdtPtr:PTR - mov ebx, IdtPtr - lidt fword ptr ss:[ebx] - ret -SetIdtr ENDP - -;====================================================================== -; GetIdtr: -; -; In: -; @param[in] IdtPtr Points to IDT table -; -; Out: -; None -; -; Destroyed: -; none -; -;====================================================================== -PUBLIC GetIdtr -GetIdtr PROC NEAR C USES EBX, IdtPtr:PTR - mov ebx, IdtPtr - sidt fword ptr ss:[ebx] - ret -GetIdtr ENDP - -;====================================================================== -; ExecuteWbinvdInstruction: Performs a wbinvd instruction. -; -; In: -; None -; -; Out: -; None -; -; Destroyed: -; None -; -;====================================================================== -PUBLIC ExecuteWbinvdInstruction -ExecuteWbinvdInstruction PROC NEAR C - wbinvd ; Write back the cache tag RAMs - ret -ExecuteWbinvdInstruction ENDP - -END diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cahalt64.asm b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cahalt64.asm deleted file mode 100644 index f7a8e3e..0000000 --- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cahalt64.asm +++ /dev/null @@ -1,173 +0,0 @@ -;/** -; * @file -; * -; * Agesa pre-memory miscellaneous support, including ap halt loop. -; * -; * @xrefitem bom "File Content Label" "Release Content" -; * @e project: AGESA -; * @e sub-project: CPU -; * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ -; */ -;***************************************************************************** -; - * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;***************************************************************************** - - text SEGMENT - - -;====================================================================== -; ExecuteFinalHltInstruction: Performs a hlt instruction. -; -; In: -; None -; -; Out: -; None -; -; Destroyed: -; eax, ebx, ecx, edx, esp -; -;====================================================================== -ExecuteFinalHltInstruction PROC PUBLIC -@@: - cli - hlt - jmp @B ;ExecuteHltInstruction -ExecuteFinalHltInstruction ENDP - -;====================================================================== -; ExecuteHltInstruction: Performs a hlt instruction. -; -; In: -; None -; -; Out: -; None -; -; Destroyed: -; eax, ebx, ecx, edx, esp -; -;====================================================================== -ExecuteHltInstruction PROC PUBLIC - cli - hlt - ret -ExecuteHltInstruction ENDP - -;====================================================================== -; NmiHandler: Simply performs an IRET. -; -; In: -; None -; -; Out: -; None -; -; Destroyed: -; None -; -;====================================================================== -NmiHandler PROC PUBLIC - iretq -NmiHandler ENDP - -;====================================================================== -; GetCsSelector: Returns the current protected mode CS selector. -; -; In: -; None -; -; Out: -; None -; -; Destroyed: -; None -; -;====================================================================== -GetCsSelector PROC PUBLIC - ; This stub function is here to avoid compilation errors. - ; At this time, there is no need to provide a 64 bit function. - ret -GetCsSelector ENDP - -;====================================================================== -; SetIdtr: -; -; In: -; @param[in] IdtPtr Points to IDT table -; -; Out: -; None -; -; Destroyed: -; none -; -;====================================================================== -SetIdtr PROC PUBLIC - ; This stub function is here to avoid compilation errors. - ; At this time, there is no need to provide a 64 bit function. - ret -SetIdtr ENDP - -;====================================================================== -; GetIdtr: -; -; In: -; @param[in] IdtPtr Points to IDT table -; -; Out: -; None -; -; Destroyed: -; none -; -;====================================================================== -GetIdtr PROC PUBLIC - ; This stub function is here to avoid compilation errors. - ; At this time, there is no need to provide a 64 bit function. - ret -GetIdtr ENDP - -;====================================================================== -; ExecuteWbinvdInstruction: Performs a wbinvd instruction. -; -; In: -; None -; -; Out: -; None -; -; Destroyed: -; None -; -;====================================================================== -ExecuteWbinvdInstruction PROC PUBLIC - wbinvd ; Write back the cache tag RAMs - ret -ExecuteWbinvdInstruction ENDP - -END diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/FchCommonCfg.h b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/FchCommonCfg.h index 7376a96..9009f6b 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/FchCommonCfg.h +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/FchCommonCfg.h @@ -370,11 +370,15 @@ typedef struct _SATA_ST { /// @li 0 - disable /// @li 1 - enable /// - BOOLEAN IdeEnable; ///< IdeEnable - Ide Controller Mode + BOOLEAN IdeEnable; ///< IdeEnable - Hidden IDE /// @par - /// Sata IDE Controller set to Combined Mode - /// @li 0 - disable - /// @li 1 - enable + /// Sata IDE Controller Combined Mode + /// Enable - SATA controller has control over Port0 through Port3, + /// IDE controller has control over Port4 and Port7. + /// Disable - SATA controller has full control of all 8 Ports + /// when operating in non-IDE mode. + /// @li 0 - enable + /// @li 1 - disable /// UINT8 SataClkMode; /// SataClkMode - Reserved } SATA_ST; @@ -843,6 +847,7 @@ typedef struct { TIMER_SMI LongTimer; ///< Long Timer SMI TIMER_SMI ShortTimer; ///< Short Timer SMI UINT32 FchCpuId; ///< Saving CpuId for FCH Module. + BOOLEAN NoneSioKbcSupport; ///< NoneSioKbcSupport - No KBC/SIO controller ( Turn on Inchip KBC emulation function ) } FCH_MISC; diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/FchDef.h b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/FchDef.h index 1d717e4..42a9bef 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/FchDef.h +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/FchDef.h @@ -245,6 +245,7 @@ VOID ImcWakeup (IN VOID *FchDataPtr); VOID ImcIdle (IN VOID *FchDataPtr); BOOLEAN ValidateImcFirmware (IN VOID *FchDataPtr); VOID SoftwareToggleImcStrapping (IN VOID *FchDataPtr); +VOID SoftwareDisableImc (IN VOID *FchDataPtr); /// @@ -355,7 +356,7 @@ VOID FchXhciInitBeforePciInit (IN FCH_DATA_BLOCK* FchDataPtr); VOID FchXhciInitIndirectReg (IN FCH_DATA_BLOCK* FchDataPtr); VOID FchInitLateUsbXhciProgram (IN VOID *FchDataPtr); VOID FchXhciUsbPhyCalibrated (IN FCH_DATA_BLOCK* FchDataPtr); - +UINT8 FchUsbCommonPhyCalibration (IN FCH_DATA_BLOCK* FchDataPtr); /// /// Fch Sd Routines diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Fch.h b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Fch.h index a67439a..c370d4c 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Fch.h +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Fch.h @@ -1617,8 +1617,13 @@ FCH_MISC_REGF0 EQU 0F0h #define KABINI_OSC_OUT_CLOCK_SEL_48MHz 0x02 #define KABINI_OSC_OUT_CLOCK_SEL_25MHz 0x01 +#define RTC_WORKAROUND_SECOND 0x00 +#define RTC_VALID_SECOND_VALUE 0x59 +#define RTC_SECOND_RESET_VALUE 0x30 +#define RTC_SECOND_LOWER_NIBBLE 0x0F +#define RTC_VALID_SECOND_VALUE_LN 0x09 + #ifndef FCH_DEADLOOP #define FCH_DEADLOOP() { volatile UINTN __i; __i = 1; while (__i); } #endif - diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/Family/Yangtze/YangtzeHwAcpiEnvService.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/Family/Yangtze/YangtzeHwAcpiEnvService.c index a035a72..57ca222 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/Family/Yangtze/YangtzeHwAcpiEnvService.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/Family/Yangtze/YangtzeHwAcpiEnvService.c @@ -77,21 +77,19 @@ ACPI_REG_WRITE FchYangtzeInitEnvHwAcpiMmioTable[] = // // HPET workaround // - {PMIO_BASE >> 8, FCH_PMIOA_REG54 + 2, 0x7F, BIT7}, - {PMIO_BASE >> 8, FCH_PMIOA_REG54 + 2, 0x7F, 0x00}, + {PMIO_BASE >> 8, FCH_PMIOA_REG54 + 2, 0x7F, BIT7}, + {PMIO_BASE >> 8, FCH_PMIOA_REG54 + 2, 0x7F, 0x00}, {PMIO_BASE >> 8, FCH_PMIOA_REGC4, (UINT8)~BIT2, BIT2}, {PMIO_BASE >> 8, FCH_PMIOA_REGC0, 0, 0x3D}, {PMIO_BASE >> 8, FCH_PMIOA_REGC0 + 1, 0x0, 0x04}, {PMIO_BASE >> 8, FCH_PMIOA_REGC2, 0x20, 0x58}, {PMIO_BASE >> 8, FCH_PMIOA_REGC2 + 1, 0, 0x40}, {PMIO_BASE >> 8, FCH_PMIOA_REGC2, (UINT8)~(BIT4), BIT4}, - {PMIO_BASE >> 8, FCH_PMIOA_REGCC, 0xF8, 0x07}, + {PMIO_BASE >> 8, FCH_PMIOA_REGCC, 0xF8, 0x03}, {PMIO_BASE >> 8, FCH_PMIOA_REG74, 0x00, BIT0 + BIT1 + BIT2 + BIT4}, {PMIO_BASE >> 8, 0x74 + 3, (UINT8)~BIT5, 0}, {PMIO_BASE >> 8, FCH_PMIOA_REGBA, (UINT8)~BIT3, BIT3}, - {PMIO_BASE >> 8, FCH_PMIOA_REGBA + 1, (UINT8)~BIT6, BIT6}, {PMIO_BASE >> 8, FCH_PMIOA_REGBC, (UINT8)~BIT1, BIT1}, - {PMIO_BASE >> 8, FCH_PMIOA_REGED, (UINT8)~(BIT0 + BIT1), 0}, {PMIO_BASE >> 8, 0xDC, 0x7C, BIT1}, {SMI_BASE >> 8, FCH_SMI_Gevent1, 0, 1}, @@ -190,6 +188,11 @@ ProgramFchEnvHwAcpiPciReg ( if ( LocalCfgPtr->Smbus.SmbusSsid != 0 ) { RwPci ((SMBUS_BUS_DEV_FUN << 16) + FCH_CFG_REG2C, AccessWidth32, 0x00, LocalCfgPtr->Smbus.SmbusSsid, StdHeader); } + if ( LocalCfgPtr->Misc.NoneSioKbcSupport ) { + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGED, AccessWidth8, ~(UINT32) ( BIT2 + BIT1), BIT2 + BIT1); + } else { + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGED, AccessWidth8, ~(UINT32) ( BIT2 + BIT1), BIT2); + } ProgramPcieNativeMode (FchDataPtr); } diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/Family/Yangtze/YangtzeSSService.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/Family/Yangtze/YangtzeSSService.c index 3db2cbe..68c9be7 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/Family/Yangtze/YangtzeSSService.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/Family/Yangtze/YangtzeSSService.c @@ -116,6 +116,7 @@ ProgramFchHwAcpiResetP ( LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr; StdHeader = &((AMD_RESET_PARAMS *)FchDataPtr)->StdHeader; + RwPmio (FCH_PMIOA_REGC8, AccessWidth8, 0xEF, 0x0, StdHeader); RwPmio (FCH_PMIOA_REGD3, AccessWidth8, (UINT32)~BIT4, 0, StdHeader); RwPmio (FCH_PMIOA_REGD3, AccessWidth8, (UINT32)~BIT4, BIT4, StdHeader); RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGC8 + 3, AccessWidth8, 0x7F, BIT7, StdHeader); diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/HwAcpiReset.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/HwAcpiReset.c index 5a3833e..c9b5ffc 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/HwAcpiReset.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/HwAcpiReset.c @@ -135,7 +135,18 @@ FchInitResetHwAcpi ( if (UserOptions.FchBldCfg->CfgFchSataPhyControl != NULL) { ProgramFchSataPhyTbl ((UserOptions.FchBldCfg->CfgFchSataPhyControl), LocalCfgPtr); } - + // + // RTC Workaround for Daylight saving time enable bit + // + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG5E, AccessWidth8, 0, 0); + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG5F, AccessWidth8, 0xFE, BIT0 ); // Enable DltSavEnable + Value = 0x0B; + LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REG70, &Value, StdHeader); + LibAmdIoRead (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader); + Value &= 0xFE; + LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader); + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG5E, AccessWidth8, 0, 0); + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG5F, AccessWidth8, 0xFE, 0 ); // Disable DltSavEnable // // Prevent RTC error // @@ -148,6 +159,7 @@ FchInitResetHwAcpi ( Value = 0x08; LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC00, &Value, StdHeader); LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGC01, &Value, StdHeader); + if ( !LocalCfgPtr->EcKbd ) { // // Route SIO IRQ1/IRQ12 to USB IRQ1/IRQ12 input @@ -156,6 +168,23 @@ FchInitResetHwAcpi ( } LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC01, &Value, StdHeader); + if ( UserOptions.FchBldCfg->CfgFchRtcWorkAround ) { + Value = RTC_WORKAROUND_SECOND; + LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REG70, &Value, StdHeader); + LibAmdIoRead (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader); + if ( Value > RTC_VALID_SECOND_VALUE ) { + Value = RTC_SECOND_RESET_VALUE; + LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader); + } + LibAmdIoRead (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader); + Value &= RTC_SECOND_LOWER_NIBBLE; + if ( Value > RTC_VALID_SECOND_VALUE_LN ) { + LibAmdIoRead (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader); + Value = RTC_SECOND_RESET_VALUE; + LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader); + } + } + Value = 0x09; LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC00, &Value, StdHeader); LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGC01, &Value, StdHeader); @@ -189,14 +218,14 @@ FchInitResetHwAcpi ( // // PciExpWakeStatus workaround // + ReadMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG60, AccessWidth16, &AsfPort); + AsfPort++; ReadMem (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REG04, AccessWidth32, &GeventEnableBits); ReadMem (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REG00, AccessWidth32, &GeventValue); if ( (GeventValue & GeventEnableBits) != 0 ) { Value = 0x40; LibAmdIoWrite (AccessWidth8, AsfPort, &Value, StdHeader); } - ReadMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG60, AccessWidth16, &AsfPort); - AsfPort++; LibAmdIoRead (AccessWidth8, AsfPort, &Value, StdHeader); if ((Value & (BIT2 + BIT0)) != 0) { Value = 0x40; diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Imc/ImcLib.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Imc/ImcLib.c index 44fe2cd..05f5727 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Imc/ImcLib.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Imc/ImcLib.c @@ -176,6 +176,43 @@ ImcSleep ( WaitForEcLDN9MailboxCmdAck (StdHeader); } +/** + * SoftwareDisableImc - Software disable IMC strap + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +VOID +SoftwareDisableImc ( + IN VOID *FchDataPtr + ) +{ + UINT8 ValueByte; + UINT8 PortStatusByte; + UINT32 AbValue; + UINT32 ABStrapOverrideReg; + AMD_CONFIG_PARAMS *StdHeader; + + StdHeader = ((FCH_DATA_BLOCK *) FchDataPtr)->StdHeader; + GetChipSysMode (&PortStatusByte, StdHeader); + + RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGC8 + 3, AccessWidth8, 0x7F, BIT7, StdHeader); + ReadPmio (0xBF, AccessWidth8, &ValueByte, StdHeader); + + ReadMem ((ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG80), AccessWidth32, &AbValue); + ABStrapOverrideReg = AbValue; + ABStrapOverrideReg &= ~BIT2; // bit2=0 EcEnableStrap + WriteMem ((ACPI_MMIO_BASE + MISC_BASE + 0x84), AccessWidth32, &ABStrapOverrideReg); + + ReadPmio (FCH_PMIOA_REGD7, AccessWidth8, &ValueByte, StdHeader); + ValueByte |= BIT1; + WritePmio (FCH_PMIOA_REGD7, AccessWidth8, &ValueByte, StdHeader); + + ValueByte = 06; + LibAmdIoWrite (AccessWidth8, 0xcf9, &ValueByte, StdHeader); + FchStall (0xffffffff, StdHeader); +} /** * ImcEnableSurebootTimer - IMC Enable Sureboot Timer. diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataEnvService.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataEnvService.c index 8abcac0..0ae0993 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataEnvService.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataEnvService.c @@ -210,12 +210,12 @@ FchProgramSataPhy ( SquelchValue[0] = (0x07 << 9); SquelchValue[1] = (0x07 << 9); for (PortNum = 0; PortNum < 2; PortNum ++) { - RwPci ((SATA_BUS_DEV_FUN << 16) + 0x080, AccessWidth16, 0x00, ( 0x130 + PortNum), StdHeader); + RwPci ((SATA_BUS_DEV_FUN << 16) + 0x080, AccessWidth16, 0x00, ( 0x30 + PortNum), StdHeader); RwPci ((SATA_BUS_DEV_FUN << 16) + 0x09C, AccessWidth32, (UINT32) (~(0x7 << 9)), SquelchValue[PortNum], StdHeader); RwPci ((SATA_BUS_DEV_FUN << 16) + 0x09C, AccessWidth32, (UINT32) (~(0x7 << 13)), (UINT32) (0x0 << 13), StdHeader); - RwPci ((SATA_BUS_DEV_FUN << 16) + 0x080, AccessWidth16, 0x00, ( 0x120 + PortNum), StdHeader); + RwPci ((SATA_BUS_DEV_FUN << 16) + 0x080, AccessWidth16, 0x00, ( 0x20 + PortNum), StdHeader); RwPci ((SATA_BUS_DEV_FUN << 16) + 0x09C, AccessWidth32, (UINT32) (~(0x7 << 9)), SquelchValue[PortNum], StdHeader); - RwPci ((SATA_BUS_DEV_FUN << 16) + 0x080, AccessWidth16, 0x00, ( 0x110 + PortNum), StdHeader); + RwPci ((SATA_BUS_DEV_FUN << 16) + 0x080, AccessWidth16, 0x00, ( 0x10 + PortNum), StdHeader); RwPci ((SATA_BUS_DEV_FUN << 16) + 0x09C, AccessWidth32, (UINT32) (~(0x7 << 9)), SquelchValue[PortNum], StdHeader); RwPci ((SATA_BUS_DEV_FUN << 16) + 0x080, AccessWidth16, 0x00, 0x010, StdHeader); } diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataService.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataService.c index ab3bbab..9f526d8 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataService.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataService.c @@ -165,13 +165,22 @@ FchInitMidProgramSataRegs ( FchSataMsiCapability = 0; } // + // Disable SATA FLR Capability + // + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x070 + 1), AccessWidth8, 0, 0, StdHeader); + // // Enabled SATA MSI capability // SATA MSI and D3 Power State Capability MMC 0x2 // - if ( !FchSataMsiCapability ) { - RwPci (((SATA_BUS_DEV_FUN << 16) + 0x70 + 1), AccessWidth8, 0, 0, StdHeader); + if ( FchSataMsiCapability ) { + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x060 + 1), AccessWidth8, 0, 0x70, StdHeader); + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x070 + 1), AccessWidth8, 0, 0x50, StdHeader); + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x050 + 2), AccessWidth8, 0xF1, 0x06, StdHeader); + } else { + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x060 + 1), AccessWidth8, 0, 0x70, StdHeader); + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x070 + 1), AccessWidth8, 0, 0x00, StdHeader); + RwPci (((SATA_BUS_DEV_FUN << 16) + 0x050 + 2), AccessWidth8, 0xF1, 0x00, StdHeader); } - // // Sata Target Support 8 devices function // @@ -286,8 +295,8 @@ FchInitLateProgramSataRegs ( RwMem ((Bar5 + 0x110 + (PortNumByte * 0x80)), AccessWidth32, 0xFFFFFFFF, 0x00); } if ( LocalCfgPtr->Sata.SataDevSlpPort0 ) { - RwMem (ACPI_MMIO_BASE + GPIO_BASE + FCH_GPIO_REG55, AccessWidth8, 0, 0x3E); - RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GPIO_REG55, AccessWidth8, 0, 0x01); + RwMem (ACPI_MMIO_BASE + GPIO_BASE + FCH_GPIO_REG55, AccessWidth8, 0, 0x0E); + RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GPIO_REG55, AccessWidth8, 0, 0x02); RwMem ((Bar5 + 0x0F4), AccessWidth32, 0xFFFFFEEF, BIT4 + BIT8); } else { RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GPIO_REG55, AccessWidth8, 0, 0x00); @@ -297,8 +306,8 @@ FchInitLateProgramSataRegs ( } } if ( LocalCfgPtr->Sata.SataDevSlpPort1 ) { - RwMem (ACPI_MMIO_BASE + GPIO_BASE + FCH_GPIO_REG59, AccessWidth8, 0, 0x3E); - RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GPIO_REG59, AccessWidth8, 0, 0x01); + RwMem (ACPI_MMIO_BASE + GPIO_BASE + FCH_GPIO_REG59, AccessWidth8, 0, 0x0E); + RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GPIO_REG59, AccessWidth8, 0, 0x02); RwMem ((Bar5 + 0x0F4), AccessWidth32, 0xFFFFFDEF, BIT4 + BIT9); } else { RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GPIO_REG59, AccessWidth8, 0, 0x00); diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sd/Family/Yangtze/YangtzeSdEnvService.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sd/Family/Yangtze/YangtzeSdEnvService.c index e9ded68..577d8cf 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sd/Family/Yangtze/YangtzeSdEnvService.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sd/Family/Yangtze/YangtzeSdEnvService.c @@ -71,6 +71,7 @@ FchInitEnvSdProgram ( // SD Configuration // if ( LocalCfgPtr->Sd.SdConfig != SdDisable) { + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGD3, AccessWidth8, 0xBF, 0x40); RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGE8, AccessWidth8, 0xFE, BIT0); Sd30Control = 0; SdData32 = 0x30FE00B2; @@ -83,8 +84,7 @@ FchInitEnvSdProgram ( } else if ( LocalCfgPtr->Sd.SdConfig == SdPio) { SdData32 &= ~(BIT20 + BIT22 + BIT19); ///PIO } - SdData32 |= (LocalCfgPtr->Sd.SdSpeed << 21) + (LocalCfgPtr->Sd.SdBitWidth << 28); - SdData32 |= BIT24; + SdData32 |= BIT24 + BIT21; if ( LocalCfgPtr->Sd.SdHostControllerVersion == 1) { SdData32 |= 0x3200; if ( (ApuStepping & 0x0F) == 0) { @@ -109,12 +109,13 @@ FchInitEnvSdProgram ( Sd30Control |= (BIT16 + BIT17); } Sd30Control &= ~(BIT0 + BIT1); - Sd30Control |= LocalCfgPtr->Sd.SdrCapabilities; + // Sd30Control |= LocalCfgPtr->Sd.SdrCapabilities; Sd30Control |= LocalCfgPtr->Sd.SdReTuningMode << 14; if ( LocalCfgPtr->Sd.SdHostControllerVersion == 2) { Sd30Control &= 0xFFFF00FF; - Sd30Control |= ( BIT4 + BIT5 + BIT6 + BIT8 + BIT10 + BIT13 ); + Sd30Control |= ( BIT0 + BIT1 + BIT8 + BIT10 + BIT13 ); } + Sd30Control |= ( BIT4 + BIT5 + BIT6 ); RwPci ((SD_BUS_DEV_FUN << 16) + SD_PCI_REGD0 + 1, AccessWidth8, 0xFD, BIT1, StdHeader); RwPci ((SD_BUS_DEV_FUN << 16) + SD_PCI_REGA8, AccessWidth32, 0x3FFC, Sd30Control, StdHeader); RwPci ((SD_BUS_DEV_FUN << 16) + SD_PCI_REGB0 + 3, AccessWidth8, 0, LocalCfgPtr->Sd.SdHostControllerVersion, StdHeader); @@ -124,6 +125,7 @@ FchInitEnvSdProgram ( RwPci ((SD_BUS_DEV_FUN << 16) + SD_PCI_REGF8, AccessWidth32, 0, 0x00010002, StdHeader); RwPci ((SD_BUS_DEV_FUN << 16) + SD_PCI_REGFC, AccessWidth32, 0, 0x00014000, StdHeader); } else { - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGD3, AccessWidth8, 0xBF, 0x00); + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGD3, AccessWidth8, 0xBF, 0x00); + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGE8, AccessWidth8, 0xFE, 0x00); } } diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/Family/Yangtze/YangtzeLpcResetService.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/Family/Yangtze/YangtzeLpcResetService.c index eb0f54f..1a02218 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/Family/Yangtze/YangtzeLpcResetService.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/Family/Yangtze/YangtzeLpcResetService.c @@ -471,7 +471,7 @@ FchInitResetSpi ( SpiModeByte = LocalCfgPtr->Mode; if (LocalCfgPtr->Mode) { - if ((SpiModeByte == FCH_SPI_MODE_QUAL_114) || (SpiModeByte == FCH_SPI_MODE_QUAL_144)) { + if ((SpiModeByte == FCH_SPI_MODE_QUAL_114) || (SpiModeByte == FCH_SPI_MODE_QUAL_144) || (SpiModeByte == FCH_SPI_MODE_QUAL_112) || (SpiModeByte == FCH_SPI_MODE_QUAL_122) || (SpiModeByte == FCH_SPI_MODE_FAST)) { if (FchPlatformSpiQe (FchDataPtr)) { FchSetQualMode (SpiModeByte, StdHeader); } @@ -671,6 +671,7 @@ FchConfigureSpiDeviceDummyCycle ( { UINT16 Mode16; UINT16 Value16; + UINT8 Value8; UINT16 DummyValue16; UINT16 CurrentDummyValue16; UINT16 CurrentMode16; @@ -681,7 +682,8 @@ FchConfigureSpiDeviceDummyCycle ( DummyValue16 = 8; switch (DeviceID) { - case 0x17BA20: + case 0x17BA20://N25Q064 + case 0x16BA20://N25Q032 FchSpiTransfer ( 0, //IN UINT8 PrefixCode, @@ -740,8 +742,34 @@ FchConfigureSpiDeviceDummyCycle ( TRUE,//IN BOOLEAN DataFlag, TRUE //IN BOOLEAN FinishedFlag ); - FchStall (1000, StdHeader); - WriteIo8 ((UINT16) (0xCF9), 0x0E); + + FchSpiTransfer ( + 0, //IN UINT8 PrefixCode, + 0x85,//IN UINT8 Opcode, + (UINT8 *)(&Value8),//IN OUT UINT8 *DataPtr, + NULL,//IN UINT8 *AddressPtr, + 0,//IN UINT8 Length, + FALSE,//IN BOOLEAN WriteFlag, + FALSE,//IN BOOLEAN AddressFlag, + TRUE,//IN BOOLEAN DataFlag, + FALSE //IN BOOLEAN FinishedFlag + ); + + Value8 &= ~ (0xf << 4); + Value8 |= (UINT8) (DummyValue16 << 4); + FchSpiTransfer ( + 0x06, //IN UINT8 PrefixCode, + 0x81,//IN UINT8 Opcode, + (UINT8 *)(&Value8),//IN OUT UINT8 *DataPtr, + NULL,//IN UINT8 *AddressPtr, + 0,//IN UINT8 Length, + TRUE,//IN BOOLEAN WriteFlag, + FALSE,//IN BOOLEAN AddressFlag, + TRUE,//IN BOOLEAN DataFlag, + TRUE //IN BOOLEAN FinishedFlag + ); + // FchStall (1000, StdHeader); +// WriteIo8 ((UINT16) (0xCF9), 0x0E); } return TRUE; default: diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/Family/Yangtze/YangtzeEhciMidService.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/Family/Yangtze/YangtzeEhciMidService.c index 977ee0e..8959420 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/Family/Yangtze/YangtzeEhciMidService.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/Family/Yangtze/YangtzeEhciMidService.c @@ -66,6 +66,8 @@ FchEhciInitAfterPciInit ( AMD_CONFIG_PARAMS *StdHeader; UINT32 PortNum; UINT32 DrivingStrength; + UINT8 RetEfuseValue; + UINT32 UsbFuseCommonCalibrationValue; LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; StdHeader = LocalCfgPtr->StdHeader; @@ -122,8 +124,13 @@ FchEhciInitAfterPciInit ( RwMem (BarAddress + FCH_EHCI_BAR_REGD4, AccessWidth32, ~((UINT32) (0x02)), (UINT32) (0x02)); FchStall (400, StdHeader); RwMem (BarAddress + FCH_EHCI_BAR_REGD4, AccessWidth32, ~((UINT32) (0x02)), (UINT32) (0x0)); - RwMem (BarAddress + FCH_EHCI_BAR_REGC0, AccessWidth32, (UINT32) (~ 0x00010000), BIT16); - + RetEfuseValue = FchUsbCommonPhyCalibration ( FchDataPtr ); + if ( RetEfuseValue == 0 ) { + RwMem (BarAddress + FCH_EHCI_BAR_REGC0, AccessWidth32, (UINT32) (~ 0x00030000), BIT16); + } else { + UsbFuseCommonCalibrationValue = RetEfuseValue << 11; + RwMem (BarAddress + FCH_EHCI_BAR_REGC0, AccessWidth32, (UINT32) (~ 0x0003FF00), UsbFuseCommonCalibrationValue); + } RwPci ((UINT32) Value + 0x50, AccessWidth32, ~ ((UINT32) (0x01 << 6)), (UINT32) (0x01 << 6), StdHeader); RwPci ((UINT32) Value + 0x50, AccessWidth32, ~ ((UINT32) (0x0F << 8)), (UINT32) (0x01 << 8), StdHeader); RwPci ((UINT32) Value + 0x50, AccessWidth32, ~ ((UINT32) (0x0F << 12)), (UINT32) (0x01 << 12), StdHeader); @@ -170,12 +177,6 @@ FchEhciInitAfterPciInit ( RwMem (BarAddress + FCH_EHCI_BAR_REGB4, AccessWidth32, ~((UINT32) (1 << 12)), 0); RwMem (BarAddress + FCH_EHCI_BAR_REGB4, AccessWidth32, ~((UINT32) (1 << 12)), (UINT32) (0x1 << 12)); } - } else { - BarAddress = FCH_FAKE_USB_BAR_ADDRESS; - WritePci ((UINT32) Value + FCH_EHCI_REG10, AccessWidth32, &BarAddress, StdHeader); - RwPci ((UINT32) Value + FCH_EHCI_REG04, AccessWidth8, 0, BIT1, StdHeader); - RwMem (BarAddress + FCH_EHCI_BAR_REGBC, AccessWidth32, (UINT32)~( BIT12 + BIT14), BIT12 + BIT14); - RwPci ((UINT32) Value + FCH_EHCI_REG04, AccessWidth8, 0, 0, StdHeader); } ReadPmio (FCH_PMIOA_REGF0, AccessWidth8, &UsbS3WakeResumeOnlyDisable, StdHeader); diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/Family/Yangtze/YangtzeXhciEnvService.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/Family/Yangtze/YangtzeXhciEnvService.c index 67fcaf6..c34a280 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/Family/Yangtze/YangtzeXhciEnvService.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/Family/Yangtze/YangtzeXhciEnvService.c @@ -47,8 +47,36 @@ // Declaration of local functions // +#define PRODUCT_INFO_REG1 0x1FC // Product Information Register 1 +#define AMD_CPU_DEV_FUN ((0x18 << 3) + 3) + /** + * FchUsbCommonPhyCalibration - Config USB Common PHY + * Calibration + * + * + * + * @param[in] FchDataPtr Fch configuration structure pointer. + * + */ +UINT8 +FchUsbCommonPhyCalibration ( + IN FCH_DATA_BLOCK *FchDataPtr + ) +{ + UINT8 RetEfuseValue; + FCH_DATA_BLOCK *LocalCfgPtr; + AMD_CONFIG_PARAMS *StdHeader; + + LocalCfgPtr = (FCH_DATA_BLOCK *)FchDataPtr; + StdHeader = LocalCfgPtr->StdHeader; + + ReadPci ((AMD_CPU_DEV_FUN << 16) + PRODUCT_INFO_REG1, AccessWidth8, &RetEfuseValue, StdHeader); + RetEfuseValue = ((RetEfuseValue & 0x1E) >> 1); + return RetEfuseValue; +} +/** * FchXhciUsbPhyCalibrated - Config XHCI Phy * * @@ -133,11 +161,15 @@ FchXhciInitIndirectReg ( UINT32 RegValue; FCH_DATA_BLOCK *LocalCfgPtr; AMD_CONFIG_PARAMS *StdHeader; + UINT8 RetEfuseValue; + UINT32 UsbFuseCommonCalibrationValue; LocalCfgPtr = (FCH_DATA_BLOCK *)FchDataPtr; StdHeader = LocalCfgPtr->StdHeader; DrivingStrength = 0; + FchXhciUsbPhyCalibrated (LocalCfgPtr); + RwXhci0IndReg ( FCH_XHCI_IND_REG94, 0xFFFFFC00, 0x00000021, StdHeader); RwXhci0IndReg ( FCH_XHCI_IND_REGD4, 0xFFFFFC00, 0x00000021, StdHeader); @@ -150,10 +182,16 @@ FchXhciInitIndirectReg ( } - RwXhci0IndReg ( FCH_XHCI_IND60_REG50, ~ ((UINT32) (0x0f)), ((UINT32) (0x07)), StdHeader); + RwXhci0IndReg ( FCH_XHCI_IND60_REG50, ~ ((UINT32) (0x0f)), ((UINT32) (0x06)), StdHeader); RwXhci0IndReg ( FCH_XHCI_IND60_REG0C, ~ ((UINT32) (0x0f << 4)), ((UINT32) (0x02 << 4)), StdHeader); RwXhci0IndReg ( FCH_XHCI_IND60_REG0C, ~ ((UINT32) (0x0f << 8)), ((UINT32) (0x02 << 8)), StdHeader); - RwXhci0IndReg ( FCH_XHCI_IND60_REG08, 0x80FC00FF, 0, StdHeader); // For BTS + RetEfuseValue = FchUsbCommonPhyCalibration ( FchDataPtr ); + if ( RetEfuseValue == 0) { + RwXhci0IndReg ( FCH_XHCI_IND60_REG08, 0x80FD00FF, (UINT32) BIT16 , StdHeader); + } else { + UsbFuseCommonCalibrationValue = RetEfuseValue << 11; + RwXhci0IndReg ( FCH_XHCI_IND60_REG08, 0x80FC00FF, UsbFuseCommonCalibrationValue , StdHeader); + } for (Port = 0; Port < 2; Port ++) { DrivingStrength = 0x1E4; diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbRegistersKB.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbRegistersKB.h index a469eb3..3ac61d8 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbRegistersKB.h +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbRegistersKB.h @@ -3269,9 +3269,21 @@ typedef union { #define DxFxxE4_xA0_LcL1ImmediateAck_OFFSET 23 #define DxFxxE4_xA0_LcL1ImmediateAck_WIDTH 1 #define DxFxxE4_xA0_LcL1ImmediateAck_MASK 0x800000 -#define DxFxxE4_xA0_Reserved_31_24_OFFSET 24 -#define DxFxxE4_xA0_Reserved_31_24_WIDTH 8 -#define DxFxxE4_xA0_Reserved_31_24_MASK 0xFF000000 +#define DxFxxE4_xA0_Reserved_24_24_OFFSET 24 +#define DxFxxE4_xA0_Reserved_24_24_WIDTH 1 +#define DxFxxE4_xA0_Reserved_24_24_MASK 0x01000000 +#define DxFxxE4_xA0_Reserved_26_25_OFFSET 25 +#define DxFxxE4_xA0_Reserved_26_25_WIDTH 2 +#define DxFxxE4_xA0_Reserved_26_25_MASK 0x06000000 +#define DxFxxE4_xA0_Reserved_27_27_OFFSET 27 +#define DxFxxE4_xA0_Reserved_27_27_WIDTH 1 +#define DxFxxE4_xA0_Reserved_27_27_MASK 0x08000000 +#define DxFxxE4_xA0_Reserved_28_28_OFFSET 28 +#define DxFxxE4_xA0_Reserved_28_28_WIDTH 1 +#define DxFxxE4_xA0_Reserved_28_28_MASK 0x10000000 +#define DxFxxE4_xA0_Reserved_31_29_OFFSET 29 +#define DxFxxE4_xA0_Reserved_31_29_WIDTH 3 +#define DxFxxE4_xA0_Reserved_31_29_MASK 0xE0000000 /// DxFxxE4_xA0 typedef union { @@ -3282,7 +3294,11 @@ typedef union { UINT32 LcL1Inactivity:4; ///< UINT32 Reserved_22_16:7; ///< UINT32 LcL1ImmediateAck:1; ///< - UINT32 Reserved_31_24:8; ///< + UINT32 Reserved_24_24:1; ///< + UINT32 Reserved_26_25:2; ///< + UINT32 Reserved_27_27:1; ///< + UINT32 Reserved_28_28:1; ///< + UINT32 Reserved_31_29:3; ///< } Field; diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/AlibSsdtKB.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/AlibSsdtKB.h index eb3c21f..879e1fd 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/AlibSsdtKB.h +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/AlibSsdtKB.h @@ -46,11 +46,11 @@ #define _ALIBSSDTKB_H_ UINT8 AlibSsdtKB[] = { - 0x53, 0x53, 0x44, 0x54, 0x52, 0x63, 0x00, 0x00, - 0x02, 0x82, 0x41, 0x4D, 0x44, 0x00, 0x00, 0x00, + 0x53, 0x53, 0x44, 0x54, 0xD1, 0x46, 0x00, 0x00, + 0x02, 0xF4, 0x41, 0x4D, 0x44, 0x00, 0x00, 0x00, 0x41, 0x4C, 0x49, 0x42, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x4D, 0x53, 0x46, 0x54, - 0x00, 0x00, 0x00, 0x04, 0x10, 0x8D, 0x32, 0x06, + 0x00, 0x00, 0x00, 0x04, 0x10, 0x8C, 0x6A, 0x04, 0x5C, 0x5F, 0x53, 0x42, 0x5F, 0x08, 0x41, 0x47, 0x52, 0x42, 0x0C, 0xFF, 0xFF, 0xFF, 0xFF, 0x08, 0x41, 0x44, 0x42, 0x47, 0x11, 0x04, 0x0B, 0x00, @@ -119,7 +119,7 @@ UINT8 AlibSsdtKB[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x14, 0x41, 0x17, 0x41, + 0x00, 0x00, 0x00, 0x00, 0x14, 0x46, 0x13, 0x41, 0x4C, 0x49, 0x42, 0x02, 0xA0, 0x40, 0x09, 0x93, 0x68, 0x0A, 0x00, 0x70, 0x11, 0x04, 0x0B, 0x00, 0x01, 0x60, 0x8B, 0x60, 0x0A, 0x00, 0x41, 0x30, @@ -155,642 +155,793 @@ UINT8 AlibSsdtKB[] = { 0x1C, 0x93, 0x68, 0x0A, 0x06, 0x70, 0x83, 0x88, 0x69, 0x0A, 0x04, 0x00, 0x60, 0x70, 0x83, 0x88, 0x69, 0x0A, 0x02, 0x00, 0x61, 0xA4, 0x41, 0x30, - 0x33, 0x33, 0x60, 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0xA1, 0x0D, 0x7B, + 0x41, 0x30, 0x38, 0x36, 0x80, 0x60, 0x00, 0x41, + 0x30, 0x38, 0x36, 0x5B, 0x82, 0x43, 0xA4, 0x41, + 0x42, 0x52, 0x31, 0x08, 0x5F, 0x48, 0x49, 0x44, 0x0C, 0x41, 0xD0, 0x0C, 0x02, 0x08, 0x5F, 0x55, - 0x49, 0x44, 0x0A, 0x80, 0x08, 0x41, 0x42, 0x31, - 0x32, 0x0A, 0x20, 0x08, 0x41, 0x42, 0x30, 0x30, + 0x49, 0x44, 0x0A, 0x81, 0x08, 0x41, 0x42, 0x31, + 0x32, 0x0A, 0x34, 0x08, 0x41, 0x42, 0x30, 0x30, 0x0A, 0x00, 0x08, 0x41, 0x42, 0x30, 0x31, 0x0A, 0x00, 0x08, 0x41, 0x42, 0x30, 0x45, 0x0A, 0x00, 0x08, 0x41, 0x42, 0x30, 0x32, 0x0A, 0x00, 0x08, @@ -804,7 +955,7 @@ UINT8 AlibSsdtKB[] = { 0x41, 0x42, 0x30, 0x42, 0x0A, 0x00, 0x08, 0x41, 0x42, 0x30, 0x43, 0x0A, 0x00, 0x08, 0x41, 0x42, 0x30, 0x44, 0x0A, 0x00, 0x5B, 0x80, 0x41, 0x30, - 0x38, 0x33, 0x00, 0x72, 0x41, 0x47, 0x52, 0x42, + 0x38, 0x31, 0x00, 0x72, 0x41, 0x47, 0x52, 0x42, 0x7D, 0x79, 0x83, 0x88, 0x5C, 0x2E, 0x5F, 0x53, 0x42, 0x5F, 0x41, 0x44, 0x41, 0x54, 0x72, 0x41, 0x42, 0x31, 0x32, 0x0A, 0x0D, 0x00, 0x00, 0x0A, @@ -812,45 +963,45 @@ UINT8 AlibSsdtKB[] = { 0x53, 0x42, 0x5F, 0x41, 0x44, 0x41, 0x54, 0x72, 0x41, 0x42, 0x31, 0x32, 0x0A, 0x0E, 0x00, 0x00, 0x0A, 0x0C, 0x00, 0x00, 0x00, 0x0B, 0x00, 0x10, - 0x5B, 0x81, 0x45, 0x04, 0x41, 0x30, 0x38, 0x33, + 0x5B, 0x81, 0x45, 0x04, 0x41, 0x30, 0x38, 0x31, 0x01, 0x00, 0x40, 0x0C, 0x00, 0x08, 0x41, 0x30, - 0x37, 0x34, 0x08, 0x41, 0x30, 0x37, 0x35, 0x08, - 0x00, 0x48, 0x26, 0x41, 0x30, 0x37, 0x30, 0x02, - 0x00, 0x03, 0x41, 0x30, 0x37, 0x31, 0x01, 0x00, - 0x0A, 0x00, 0x0B, 0x41, 0x30, 0x37, 0x32, 0x01, - 0x00, 0x44, 0x0E, 0x41, 0x30, 0x38, 0x32, 0x04, - 0x00, 0x01, 0x41, 0x30, 0x37, 0x39, 0x01, 0x00, - 0x4A, 0x2B, 0x41, 0x30, 0x38, 0x34, 0x20, 0x5B, - 0x87, 0x16, 0x41, 0x30, 0x38, 0x33, 0x41, 0x30, - 0x38, 0x34, 0x0A, 0xA1, 0x03, 0x00, 0x40, 0x72, - 0x00, 0x0C, 0x41, 0x30, 0x36, 0x36, 0x01, 0x5B, - 0x87, 0x16, 0x41, 0x30, 0x38, 0x33, 0x41, 0x30, - 0x38, 0x34, 0x0A, 0xA2, 0x03, 0x00, 0x40, 0x72, - 0x00, 0x0D, 0x41, 0x30, 0x38, 0x31, 0x01, 0x5B, - 0x87, 0x27, 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0x5F, 0x53, 0x42, 0x5F, 0x41, 0x44, 0x41, 0x54, 0x0A, 0x00, 0x00, 0x0A, - 0x01, 0x41, 0x30, 0x33, 0x38, 0x70, 0x41, 0x30, - 0x36, 0x39, 0x41, 0x30, 0x37, 0x30, 0xA4, 0x62, - 0x14, 0x46, 0x05, 0x41, 0x30, 0x39, 0x32, 0x01, + 0x01, 0x41, 0x30, 0x33, 0x37, 0x70, 0x41, 0x30, + 0x36, 0x37, 0x41, 0x30, 0x36, 0x38, 0xA4, 0x62, + 0x14, 0x46, 0x05, 0x41, 0x30, 0x39, 0x30, 0x01, 0xA0, 0x14, 0x94, 0x41, 0x42, 0x30, 0x36, 0x41, 0x42, 0x30, 0x37, 0x74, 0x41, 0x42, 0x30, 0x36, 0x41, 0x42, 0x30, 0x37, 0x60, 0xA1, 0x0B, 0x74, @@ -3091,140 +2249,70 @@ UINT8 AlibSsdtKB[] = { 0x60, 0x75, 0x60, 0x79, 0x0A, 0x01, 0x60, 0x60, 0x76, 0x60, 0x79, 0x60, 0x41, 0x42, 0x30, 0x38, 0x60, 0xA0, 0x0F, 0x93, 0x68, 0x0A, 0x01, 0x7D, - 0x41, 0x30, 0x38, 0x38, 0x60, 0x41, 0x30, 0x38, - 0x38, 0xA1, 0x0D, 0x7B, 0x41, 0x30, 0x38, 0x38, - 0x80, 0x60, 0x00, 0x41, 0x30, 0x38, 0x38, 0x08, + 0x41, 0x30, 0x38, 0x36, 0x60, 0x41, 0x30, 0x38, + 0x36, 0xA1, 0x0D, 0x7B, 0x41, 0x30, 0x38, 0x36, + 0x80, 0x60, 0x00, 0x41, 0x30, 0x38, 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b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxIntegratedInfoTableKB.c @@ -461,10 +461,7 @@ GfxIntInfoTableInitKB ( SystemInfoTableV3.sIntegratedSysInfo.ulDDR_DLL_PowerUpTime = 4940; SystemInfoTableV3.sIntegratedSysInfo.ulDDR_PLL_PowerUpTime = 2000; - SystemInfoTableV3.sIntegratedSysInfo.ulGPUCapInfo = - GPUCAPINFO_TMDS_HDMI_USE_SINGLE_PLL_MODE | - GPUCAPINFO_DP_USE_SINGLE_PLL_MODE | - GPUCAPINFO_DFS_BYPASS_DISABLE; + SystemInfoTableV3.sIntegratedSysInfo.ulGPUCapInfo = GPUCAPINFO_DFS_BYPASS_DISABLE; // GPUCAPINFO_DFS_BYPASS_ENABLE should be enabled by default for MOBILE systems if ((Gfx->AmdPlatformType & AMD_PLATFORM_MOBILE) != 0) { diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxMidInitKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxMidInitKB.c index b6cfe66..476c7845 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxMidInitKB.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxMidInitKB.c @@ -133,7 +133,7 @@ GfxMidInterfaceKB ( Status = GfxGmcInitKB (Gfx); AGESA_STATUS_UPDATE (Status, AgesaStatus); - //Status = GfxSamuInit (Gfx); + Status = GfxSamuInit (Gfx); AGESA_STATUS_UPDATE (Status, AgesaStatus); Status = GfxInitSsid (Gfx); diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxTablesKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxTablesKB.c index 99e7f93..9d37c4c 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxTablesKB.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxTablesKB.c @@ -434,10 +434,13 @@ GNB_TABLE ROMDATA GfxGmcInitTableKB [] = { GNB_ENTRY_WR (0x12, 0x3750, 0x18201015), GNB_ENTRY_WR (0x12, 0x3754, 0x18201015), GNB_ENTRY_WR (0x12, 0x253C, 0x000000B4), - GNB_ENTRY_WR (0x12, 0x2550, 0x000000A3), + GNB_ENTRY_WR (0x12, 0x2550, 0x000000B3), GNB_ENTRY_WR (0x12, 0x2558, 0x00002077), GNB_ENTRY_WR (0x12, 0x2558, 0x000020B7), GNB_ENTRY_WR (0x12, 0x2558, 0x00002A3D), + GNB_ENTRY_WR (0x12, 0x2558, 0x00002010), + GNB_ENTRY_WR (0x12, 0x2558, 0x00002A20), + GNB_ENTRY_WR (0x12, 0x2544, 0x00040108), GNB_ENTRY_WR (0x12, 0x287C, 0x0c000911), diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbSmuFirmwareKB.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbSmuFirmwareKB.h index 62736a3..1baece9 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbSmuFirmwareKB.h +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbSmuFirmwareKB.h @@ -51,7 +51,7 @@ UINT32 FirmwareKBHeader [] = { 0x0001F984, 0x00002000, 0x00010000, - 0xECE28940, + 0x64C7232B, 0x0000424B, 0x00000000, 0x00000000, @@ -61,18 +61,18 @@ UINT32 FirmwareKBHeader [] = { }; UINT32 FirmwareKB[] = { - 0x63c00f17, - 0xb9cfd803, - 0x196410db, - 0x8c378d8b, - 0xa8f232ce, - 0x000c0d00, + 0x88b67705, + 0x432a07e8, + 0xe1e6cc0b, + 0x7471790d, + 0xc101174a, + 0x000c1200, 0x00000100, 0x00000000, 0x00020100, - 0x00019900, + 0x00019d08, 0x0001f954, - 0x000398d8, + 0x00039ce0, 0x0003f900, 0x0003f000, 0x00000000, @@ -80,8 +80,8 @@ UINT32 FirmwareKB[] = { 0x00000000, 0x00000000, 0x00000000, - 0x00038c00, - 0x00038fa8, + 0x00039008, + 0x000393b0, 0x00000000, 0x00000000, 0x00000000, @@ -137,7 +137,7 @@ UINT32 FirmwareKB[] = { 0x5b9d0074, 0xf8000059, 0x34010001, - 0xf8002e56, + 0xf8002eb3, 0xe000009a, 0x34000000, 0x34000000, @@ -145,7 +145,7 @@ UINT32 FirmwareKB[] = { 0x5b9d0074, 0xf8000051, 0x34010002, - 0xf8002e4e, + 0xf8002eab, 0x2b980060, 0x2b990064, 0xe000006f, @@ -153,7 +153,7 @@ UINT32 FirmwareKB[] = { 0x5b9d0074, 0xf8000049, 0x34010003, - 0xf8002e46, + 0xf8002ea3, 0xe000008a, 0x34000000, 0x34000000, @@ -161,7 +161,7 @@ UINT32 FirmwareKB[] = { 0x5b9d0074, 0xf8000041, 0x34010004, - 0xf8002e3e, + 0xf8002e9b, 0x2b980060, 0x2b990064, 0xe000005f, @@ -169,7 +169,7 @@ UINT32 FirmwareKB[] = { 0x5b9d0074, 0xf8000039, 0x34010005, - 0xf8002e36, + 0xf8002e93, 0x2b980060, 0x2b990064, 0xe0000057, @@ -330,11 +330,11 @@ UINT32 FirmwareKB[] = { 0x781c0003, 0x3b9ceffc, 0x781a0004, - 0x3b5a0da0, + 0x3b5a11b0, 0x78010003, - 0x38218db0, + 0x382191b8, 0x78030003, - 0x38638e70, + 0x38639278, 0x44230004, 0x58200000, 0x34210004, @@ -348,16 +348,16 @@ UINT32 FirmwareKB[] = { 0x5b9d0078, 0xfbffff63, 0x78010003, - 0x382198d8, + 0x38219ce0, 0x28230004, 0x28220000, 0x34630001, 0x585c0000, 0x58230004, 0xf800008b, - 0xf80048d4, + 0xf80049cc, 0x78010003, - 0x382198d8, + 0x38219ce0, 0x28230004, 0x28220000, 0x3463ffff, @@ -371,7 +371,7 @@ UINT32 FirmwareKB[] = { 0xb81df000, 0xfbffff4c, 0x78010003, - 0x382198d8, + 0x38219ce0, 0x28230004, 0x28220000, 0x34630001, @@ -380,7 +380,7 @@ UINT32 FirmwareKB[] = { 0xe3ffffea, 0x379cfffc, 0x5b9d0004, - 0xf80049d9, + 0xf8004ad1, 0xe0000000, 0x99084000, 0x39080001, @@ -451,9 +451,9 @@ UINT32 FirmwareKB[] = { 0x5b9d0004, 0x34020000, 0x78010003, - 0x38218e94, - 0xf8004941, - 0xf8002804, + 0x3821929c, + 0xf8004a39, + 0xf8002859, 0x7c210000, 0x33010078, 0x43010078, @@ -463,35 +463,35 @@ UINT32 FirmwareKB[] = { 0x5b9d0004, 0x78010003, 0x34020000, - 0x38218ea0, - 0xf8004935, + 0x382192a8, + 0xf8004a2d, 0xf80010bd, 0xe3fffffb, 0x379cfffc, 0x5b9d0004, 0x78010003, - 0x38218f30, + 0x38219338, 0x34020000, 0x58220024, 0x58220020, 0x78010003, 0x34020000, - 0x38218e88, - 0xf8004928, - 0xf800382a, + 0x38219290, + 0xf8004a20, + 0xf80038f7, 0xe3fffffb, 0x379cfffc, 0x5b9d0004, 0x78010003, - 0x38218f58, + 0x38219360, 0x34020000, 0x58220024, 0x58220020, 0x78010003, 0x34020000, - 0x38218e7c, - 0xf800491b, - 0xf800395a, + 0x38219284, + 0xf8004a13, + 0xf8003a27, 0xe3fffffb, 0x379cfff8, 0x5b8b0008, @@ -530,7 +530,7 @@ UINT32 FirmwareKB[] = { 0x38210100, 0x78050003, 0x58410000, - 0x38a58e70, + 0x38a59278, 0x7804e000, 0x38843094, 0x34a5ffff, @@ -602,7 +602,7 @@ UINT32 FirmwareKB[] = { 0x00460010, 0x00270018, 0x781b0003, - 0x3b7b8c00, + 0x3b7b9008, 0x33630001, 0x33680007, 0x33610000, @@ -1302,7 +1302,7 @@ UINT32 FirmwareKB[] = { 0x5b8b000c, 0x5b8c0008, 0x5b9d0004, - 0xf8004681, + 0xf8004779, 0x780b0003, 0x34040000, 0x396beffc, @@ -1311,35 +1311,35 @@ UINT32 FirmwareKB[] = { 0xb8802800, 0xb8803000, 0x34020003, - 0x38218ee0, - 0xf800464f, + 0x382192e8, + 0xf8004747, 0x356bfbfc, 0x78010003, 0x78050002, - 0x3563ff00, + 0x3563fe00, 0xb9602000, 0x34020007, 0x34060000, - 0x38218eb8, + 0x382192c0, 0x38a5052c, 0x780cc00c, - 0xf8004644, + 0xf800473c, 0x398c0000, 0x29820000, 0x78010100, 0x38210000, 0xa0411000, 0x00460018, - 0x356bfefc, + 0x356bfdfc, 0x5cc0000a, 0x78010003, 0x78050003, 0x3563fc00, 0xb9602000, - 0x38218f80, - 0x38a57214, + 0x38219388, + 0x38a575f4, 0x34020006, - 0xf8004634, + 0xf800472c, 0x356bfbfc, 0x78010003, 0x78050002, @@ -1348,8 +1348,8 @@ UINT32 FirmwareKB[] = { 0x38a50608, 0x34020004, 0x34060000, - 0x38218f08, - 0xf800462a, + 0x38219310, + 0xf8004722, 0x356bfdfc, 0x78010003, 0x78050002, @@ -1358,23 +1358,23 @@ UINT32 FirmwareKB[] = { 0x38a50658, 0x34020002, 0x34060000, - 0x38218f30, - 0xf8004620, + 0x38219338, + 0xf8004718, 0x356bfdfc, 0x78010003, 0x78050002, 0x34020001, 0x3563fe00, - 0x38218f58, + 0x38219360, 0xb9602000, 0x38a5068c, 0x34060000, - 0xf8004616, + 0xf800470e, 0x29830000, 0x78020003, 0x78010003, - 0x384298d8, - 0x38218ee0, + 0x38429ce0, + 0x382192e8, 0x58410000, 0x20630002, 0x5c60000a, @@ -1409,7 +1409,7 @@ UINT32 FirmwareKB[] = { 0x28410000, 0xa0230800, 0x58410000, - 0xf800467d, + 0xf8004775, 0xf8000334, 0xf8001b4b, 0x7803c020, @@ -1427,7 +1427,7 @@ UINT32 FirmwareKB[] = { 0xb8203000, 0xb8203800, 0x34040037, - 0xf80046e0, + 0xf80047d8, 0x34010000, 0xb8202800, 0xb8203000, @@ -1435,7 +1435,7 @@ UINT32 FirmwareKB[] = { 0xb8201000, 0xb8201800, 0x34040037, - 0xf8004719, + 0xf8004811, 0x78010003, 0x3821f900, 0x28230000, @@ -1445,7 +1445,7 @@ UINT32 FirmwareKB[] = { 0x34030064, 0x34420032, 0x8c431000, - 0xf800467f, + 0xf8004777, 0x2b8b000c, 0x2b8c0008, 0x2b9d0004, @@ -1485,7 +1485,7 @@ UINT32 FirmwareKB[] = { 0x5b8b0008, 0x5b9d0004, 0x78180003, - 0x3b188fa8, + 0x3b1893b0, 0xfbfffc3e, 0x780b0003, 0xb9601000, @@ -1504,12 +1504,12 @@ UINT32 FirmwareKB[] = { 0xa0411000, 0x00420018, 0x5c400002, - 0xf800571c, + 0xf8005814, 0x78010003, 0x78020003, 0x3821ec00, 0x3842edfc, - 0xf8003130, + 0xf80031fd, 0x34010004, 0xd0210000, 0x34010001, @@ -1534,7 +1534,7 @@ UINT32 FirmwareKB[] = { 0x90002800, 0x34010000, 0xd0010000, - 0x386398d8, + 0x38639ce0, 0x28620034, 0x34010001, 0xbc240800, @@ -1545,7 +1545,7 @@ UINT32 FirmwareKB[] = { 0x90002800, 0x34010000, 0xd0010000, - 0x386398d8, + 0x38639ce0, 0x28620038, 0x34010001, 0xbc240800, @@ -1556,7 +1556,7 @@ UINT32 FirmwareKB[] = { 0x34010000, 0xd0010000, 0x78020003, - 0x384298d8, + 0x38429ce0, 0x28440000, 0x28410034, 0x38c68000, @@ -1581,7 +1581,7 @@ UINT32 FirmwareKB[] = { 0xd0010000, 0x34010001, 0xbc220800, - 0x386398d8, + 0x38639ce0, 0x28620034, 0xa4200800, 0xa0411000, @@ -1593,7 +1593,7 @@ UINT32 FirmwareKB[] = { 0xd0010000, 0x34010001, 0xbc220800, - 0x386398d8, + 0x38639ce0, 0x28620038, 0xa4200800, 0xa0411000, @@ -1603,7 +1603,7 @@ UINT32 FirmwareKB[] = { 0x34010000, 0xd0010000, 0x78020003, - 0x384298d8, + 0x38429ce0, 0x28440000, 0x28410034, 0x38c68000, @@ -1621,7 +1621,7 @@ UINT32 FirmwareKB[] = { 0x34010000, 0xd0010000, 0x78020003, - 0x384298d8, + 0x38429ce0, 0x34030000, 0x28440000, 0x78018000, @@ -1642,7 +1642,7 @@ UINT32 FirmwareKB[] = { 0xd0020000, 0x28240000, 0x78020003, - 0x384298d8, + 0x38429ce0, 0x58440034, 0x28210004, 0x58410038, @@ -1657,7 +1657,7 @@ UINT32 FirmwareKB[] = { 0x90002800, 0x34010000, 0xd0010000, - 0x386398d8, + 0x38639ce0, 0x28630000, 0x34020001, 0xbc441000, @@ -1669,7 +1669,7 @@ UINT32 FirmwareKB[] = { 0x90002800, 0x34010000, 0xd0010000, - 0x386398d8, + 0x38639ce0, 0x28630000, 0x34020001, 0xbc441000, @@ -1681,7 +1681,7 @@ UINT32 FirmwareKB[] = { 0x34010000, 0xd0010000, 0x78020003, - 0x384298d8, + 0x38429ce0, 0x28440000, 0x28410034, 0x38c68000, @@ -1704,7 +1704,7 @@ UINT32 FirmwareKB[] = { 0x90002800, 0x34010000, 0xd0010000, - 0x386398d8, + 0x38639ce0, 0x28630000, 0x34010001, 0xbc220800, @@ -1717,7 +1717,7 @@ UINT32 FirmwareKB[] = { 0x90002800, 0x34010000, 0xd0010000, - 0x386398d8, + 0x38639ce0, 0x28630000, 0x34010001, 0xbc220800, @@ -1730,7 +1730,7 @@ UINT32 FirmwareKB[] = { 0x34010000, 0xd0010000, 0x78020003, - 0x384298d8, + 0x38429ce0, 0x28440000, 0x28410034, 0x38c68000, @@ -1747,9 +1747,9 @@ UINT32 FirmwareKB[] = { 0x379cfffc, 0x5b9d0004, 0x78010003, - 0x38218ea0, - 0xf80043fa, - 0xf80043a6, + 0x382192a8, + 0xf80044f2, + 0xf800449e, 0x2b9d0004, 0x379c0004, 0xc3a00000, @@ -1775,24 +1775,24 @@ UINT32 FirmwareKB[] = { 0x33040074, 0x78010003, 0x33030075, - 0x38218e94, - 0xf80043de, + 0x3821929c, + 0xf80044d6, 0x2b9d0004, 0x379c0004, 0xc3a00000, 0x379cfffc, 0x5b9d0004, 0x78010003, - 0x38218e88, - 0xf80043d6, + 0x38219290, + 0xf80044ce, 0x2b9d0004, 0x379c0004, 0xc3a00000, 0x379cfffc, 0x5b9d0004, 0x78010003, - 0x38218e7c, - 0xf80043ce, + 0x38219284, + 0xf80044c6, 0x2b9d0004, 0x379c0004, 0xc3a00000, @@ -1810,9 +1810,9 @@ UINT32 FirmwareKB[] = { 0x004b0013, 0x65610001, 0x44200051, - 0xf80046b9, + 0xf80047b1, 0xb8206000, - 0xf80046ce, + 0xf80047c6, 0x01810011, 0x34030000, 0x20210001, @@ -1821,14 +1821,14 @@ UINT32 FirmwareKB[] = { 0xb8606800, 0x5c230006, 0x78010003, - 0x38218de0, + 0x382191e8, 0x302b0012, 0xb9606800, 0xb9602000, 0x21814000, 0x4420000b, 0x78010003, - 0x38218de0, + 0x382191e8, 0x78020003, 0x302b0010, 0x3842f320, @@ -1840,7 +1840,7 @@ UINT32 FirmwareKB[] = { 0x21812000, 0x4420000d, 0x78010003, - 0x38218de0, + 0x382191e8, 0x34020000, 0x78030003, 0x30220010, @@ -1864,11 +1864,11 @@ UINT32 FirmwareKB[] = { 0x58220000, 0x44600004, 0x78010003, - 0x38218eac, - 0xf8004385, + 0x382192b4, + 0xf800447d, 0x45a0000f, 0x78030003, - 0x38638de0, + 0x386391e8, 0x40610015, 0x4420000b, 0x40620010, @@ -1879,8 +1879,8 @@ UINT32 FirmwareKB[] = { 0x30610015, 0x44410004, 0x78010003, - 0x38218eac, - 0xf8004376, + 0x382192b4, + 0xf800446e, 0x34010001, 0x3301007b, 0x3c21001a, @@ -1889,7 +1889,7 @@ UINT32 FirmwareKB[] = { 0x58410050, 0x34010000, 0x34022800, - 0xf80045d2, + 0xf80046ca, 0x2b8b0010, 0x2b8c000c, 0x2b8d0008, @@ -1909,7 +1909,7 @@ UINT32 FirmwareKB[] = { 0x004b0014, 0x65610001, 0x4420004f, - 0xf8004662, + 0xf800475a, 0xb8201800, 0x00210011, 0x34040000, @@ -1919,14 +1919,14 @@ UINT32 FirmwareKB[] = { 0xb8806000, 0x5c240006, 0x78010003, - 0x38218de0, + 0x382191e8, 0x302b0012, 0xb9606000, 0xb9602800, 0x20614000, 0x4420000b, 0x78010003, - 0x38218de0, + 0x382191e8, 0x78020003, 0x302b0010, 0x3842f320, @@ -1938,7 +1938,7 @@ UINT32 FirmwareKB[] = { 0x20612000, 0x4420000d, 0x78010003, - 0x38218de0, + 0x382191e8, 0x34020000, 0x78030003, 0x30220010, @@ -1962,11 +1962,11 @@ UINT32 FirmwareKB[] = { 0x58220000, 0x44800004, 0x78010003, - 0x38218eac, - 0xf8004323, + 0x382192b4, + 0xf800441b, 0x4580000f, 0x78030003, - 0x38638de0, + 0x386391e8, 0x40610015, 0x4420000b, 0x40620010, @@ -1977,8 +1977,8 @@ UINT32 FirmwareKB[] = { 0x30610015, 0x44410004, 0x78010003, - 0x38218eac, - 0xf8004314, + 0x382192b4, + 0xf800440c, 0x34010001, 0x78028000, 0x3c240019, @@ -1986,7 +1986,7 @@ UINT32 FirmwareKB[] = { 0x3301007b, 0x58440050, 0x34022800, - 0xf8004588, + 0xf8004680, 0x2b8b000c, 0x2b8c0008, 0x2b9d0004, @@ -1995,7 +1995,7 @@ UINT32 FirmwareKB[] = { 0x379cfffc, 0x5b9d0004, 0x78030003, - 0x38638de0, + 0x386391e8, 0x40620016, 0x34050001, 0x34040000, @@ -2005,8 +2005,8 @@ UINT32 FirmwareKB[] = { 0x3065000f, 0xfbfffe4f, 0x78010003, - 0x38218eac, - 0xf80042f8, + 0x382192b4, + 0xf80043f0, 0x2b9d0004, 0x379c0004, 0xc3a00000, @@ -2025,8 +2025,8 @@ UINT32 FirmwareKB[] = { 0x33020008, 0x78010003, 0x33030009, - 0x38218e94, - 0xf80042e4, + 0x3821929c, + 0xf80043dc, 0x2b9d0004, 0x379c0004, 0xc3a00000, @@ -2045,8 +2045,8 @@ UINT32 FirmwareKB[] = { 0x33020014, 0x78010003, 0x33030015, - 0x38218e94, - 0xf80042d0, + 0x3821929c, + 0xf80043c8, 0x2b9d0004, 0x379c0004, 0xc3a00000, @@ -2065,8 +2065,8 @@ UINT32 FirmwareKB[] = { 0x33020020, 0x78010003, 0x33030021, - 0x38218e94, - 0xf80042bc, + 0x3821929c, + 0xf80043b4, 0x2b9d0004, 0x379c0004, 0xc3a00000, @@ -2085,8 +2085,8 @@ UINT32 FirmwareKB[] = { 0x3302002c, 0x78010003, 0x3303002d, - 0x38218e94, - 0xf80042a8, + 0x3821929c, + 0xf80043a0, 0x2b9d0004, 0x379c0004, 0xc3a00000, @@ -2105,8 +2105,8 @@ UINT32 FirmwareKB[] = { 0x33020038, 0x78010003, 0x33030039, - 0x38218e94, - 0xf8004294, + 0x3821929c, + 0xf800438c, 0x2b9d0004, 0x379c0004, 0xc3a00000, @@ -2125,8 +2125,8 @@ UINT32 FirmwareKB[] = { 0x33020044, 0x78010003, 0x33030045, - 0x38218e94, - 0xf8004280, + 0x3821929c, + 0xf8004378, 0x2b9d0004, 0x379c0004, 0xc3a00000, @@ -2145,8 +2145,8 @@ UINT32 FirmwareKB[] = { 0x33020050, 0x78010003, 0x33030051, - 0x38218e94, - 0xf800426c, + 0x3821929c, + 0xf8004364, 0x2b9d0004, 0x379c0004, 0xc3a00000, @@ -2165,8 +2165,8 @@ UINT32 FirmwareKB[] = { 0x3302005c, 0x78010003, 0x3303005d, - 0x38218e94, - 0xf8004258, + 0x3821929c, + 0xf8004350, 0x2b9d0004, 0x379c0004, 0xc3a00000, @@ -2183,8 +2183,8 @@ UINT32 FirmwareKB[] = { 0x78010003, 0x5b020064, 0x33030068, - 0x38218e94, - 0xf8004246, + 0x3821929c, + 0xf800433e, 0x2b9d0004, 0x379c0004, 0xc3a00000, @@ -2206,7 +2206,7 @@ UINT32 FirmwareKB[] = { 0x582b0000, 0x3d630002, 0x78020003, - 0x384289cc, + 0x38428dd0, 0x34010000, 0xb4621800, 0x3301007b, @@ -2237,7 +2237,7 @@ UINT32 FirmwareKB[] = { 0x5b9d0004, 0x780d0003, 0xb9a01000, - 0x3842899c, + 0x38428da0, 0x10410000, 0x340b0000, 0x6421ffff, @@ -2245,7 +2245,7 @@ UINT32 FirmwareKB[] = { 0xb8406000, 0xb9a00800, 0xb56b1800, - 0x3821899c, + 0x38218da0, 0xb4611800, 0x10610000, 0x78028000, @@ -2282,9 +2282,9 @@ UINT32 FirmwareKB[] = { 0xb5a20800, 0x3421ffff, 0x8c220800, - 0xf80041c1, + 0xf80042b9, 0xe000001f, - 0xf800435d, + 0xf8004455, 0xb9604800, 0x3929f900, 0x29250000, @@ -2308,8 +2308,8 @@ UINT32 FirmwareKB[] = { 0x00430001, 0xb4230800, 0x8c220800, - 0xf80041a7, - 0xf8004344, + 0xf800429f, + 0xf800443c, 0xb8201800, 0x5563fffe, 0x5d630002, @@ -2329,7 +2329,7 @@ UINT32 FirmwareKB[] = { 0x34020064, 0x34210032, 0x8c220800, - 0xf8004340, + 0xf8004438, 0x2b9d0004, 0x379c0004, 0xc3a00000, @@ -2350,9 +2350,9 @@ UINT32 FirmwareKB[] = { 0xc3a00000, 0x379cfffc, 0x5b9d0004, - 0xf800431b, + 0xf8004413, 0x78050003, - 0x38a58db0, + 0x38a591b8, 0x58a20000, 0x2b9d0004, 0x379c0004, @@ -2361,12 +2361,12 @@ UINT32 FirmwareKB[] = { 0x5b8b0008, 0x5b9d0004, 0x780b0003, - 0x396b8db0, + 0x396b91b8, 0x29610000, 0x780241c6, 0x38424e6d, 0x3783000c, - 0xf8003931, + 0xf8003a29, 0x2b810010, 0x34213039, 0x59610000, @@ -2388,7 +2388,7 @@ UINT32 FirmwareKB[] = { 0xb56b0800, 0x34210001, 0x3c210010, - 0xf800391b, + 0xf8003a13, 0x2b820010, 0xc98b0800, 0xb4220800, @@ -2644,7 +2644,7 @@ UINT32 FirmwareKB[] = { 0x3842f9f0, 0x78040003, 0x58460000, - 0x38848b20, + 0x38848f28, 0x78010003, 0x28830000, 0x3821fa04, @@ -2945,7 +2945,7 @@ UINT32 FirmwareKB[] = { 0x5d600046, 0x78020003, 0xb8406800, - 0x38428db6, + 0x384291be, 0x2c410000, 0x5c200036, 0xfbffff67, @@ -2953,7 +2953,7 @@ UINT32 FirmwareKB[] = { 0xb0401000, 0x5c220006, 0x78010003, - 0x38218db4, + 0x382191bc, 0x34020007, 0x30220000, 0xe0000008, @@ -2962,11 +2962,11 @@ UINT32 FirmwareKB[] = { 0xb0401000, 0x5c220004, 0x78010003, - 0x38218db4, + 0x382191bc, 0x302b0000, 0x78030003, 0xb8600800, - 0x38218db4, + 0x382191bc, 0x40220000, 0x7c410007, 0x5c20000a, @@ -2988,10 +2988,10 @@ UINT32 FirmwareKB[] = { 0xb44c1000, 0x40410014, 0x330106ec, - 0x38638db4, + 0x386391bc, 0x40610000, 0xb9a05800, - 0x396b8db6, + 0x396b91be, 0x5b0106d8, 0x2f010728, 0x2f02072a, @@ -3015,7 +3015,7 @@ UINT32 FirmwareKB[] = { 0x7d610001, 0x5c200005, 0x78010003, - 0x38218db6, + 0x382191be, 0x34020000, 0x0c220000, 0x2b8b0010, @@ -3052,24 +3052,24 @@ UINT32 FirmwareKB[] = { 0x78028000, 0x5c80000d, 0x78010003, - 0x38218dc0, - 0x38638db8, + 0x382191c8, + 0x386391c0, 0x58240000, 0x58640000, 0x3842014c, 0x28420000, - 0x38a58dbc, + 0x38a591c4, 0x34010001, 0x58a20000, 0x33010736, 0xe0000036, 0xb8606800, - 0x39ad8db8, + 0x39ad91c0, 0xb8407000, 0x29a30000, 0x39ce014c, 0xb8a07800, - 0x39ef8dbc, + 0x39ef91c4, 0x29c20000, 0x29e10000, 0x34630001, @@ -3083,7 +3083,7 @@ UINT32 FirmwareKB[] = { 0x8c431000, 0x780c0003, 0xb9805800, - 0x396b8dc0, + 0x396b91c8, 0x29610000, 0x430306fc, 0x206300ff, @@ -3110,7 +3110,7 @@ UINT32 FirmwareKB[] = { 0xe0000008, 0x38a5f000, 0x2ca102f6, - 0x398c8dc0, + 0x398c91c8, 0x29820000, 0x3c210008, 0x50410003, @@ -3139,7 +3139,7 @@ UINT32 FirmwareKB[] = { 0x78020002, 0x7805c020, 0x38630008, - 0x38848b24, + 0x38848f2c, 0x38423e94, 0x38a50024, 0x202100ff, @@ -3233,7 +3233,7 @@ UINT32 FirmwareKB[] = { 0x33020760, 0x78010003, 0x330206ef, - 0x38218ba8, + 0x38218fb0, 0x7805c020, 0x30220019, 0x30220000, @@ -3243,7 +3243,7 @@ UINT32 FirmwareKB[] = { 0x78020002, 0x3401ffef, 0xa0812000, - 0x38638b24, + 0x38638f2c, 0x38424a68, 0x58620000, 0x58a40000, @@ -3252,7 +3252,7 @@ UINT32 FirmwareKB[] = { 0x78060003, 0x44200007, 0x78010002, - 0x38c68b24, + 0x38c68f2c, 0x38213dc8, 0x58c10000, 0x330206ef, @@ -3265,7 +3265,7 @@ UINT32 FirmwareKB[] = { 0x78030002, 0x7804c020, 0x28410000, - 0x38c68b24, + 0x38c68f2c, 0x38633e94, 0x38210030, 0x58410000, @@ -3279,7 +3279,7 @@ UINT32 FirmwareKB[] = { 0x78020003, 0x78010002, 0x330306ea, - 0x38428b24, + 0x38428f2c, 0x38213e94, 0x58410000, 0x34010000, @@ -3381,7 +3381,7 @@ UINT32 FirmwareKB[] = { 0x33020760, 0x78010003, 0x330206ef, - 0x38218ba8, + 0x38218fb0, 0x7805c020, 0x30220019, 0x30220000, @@ -3391,7 +3391,7 @@ UINT32 FirmwareKB[] = { 0x78020002, 0x3401ffef, 0xa0812000, - 0x38638b24, + 0x38638f2c, 0x38424a68, 0x58620000, 0x58a40000, @@ -3400,7 +3400,7 @@ UINT32 FirmwareKB[] = { 0x78060003, 0x44200007, 0x78010002, - 0x38c68b24, + 0x38c68f2c, 0x38213dc8, 0x58c10000, 0x330206ef, @@ -3413,7 +3413,7 @@ UINT32 FirmwareKB[] = { 0x78030002, 0x7804c020, 0x28410000, - 0x38c68b24, + 0x38c68f2c, 0x38633e94, 0x38210030, 0x58410000, @@ -3427,7 +3427,7 @@ UINT32 FirmwareKB[] = { 0x78020003, 0x78010002, 0x330306ea, - 0x38428b24, + 0x38428f2c, 0x38213e94, 0x58410000, 0x34010000, @@ -3495,7 +3495,7 @@ UINT32 FirmwareKB[] = { 0x33010918, 0xe0000016, 0x33020918, - 0xf8002453, + 0xf80024be, 0x4181000f, 0x396b00cc, 0x7802c050, @@ -3517,7 +3517,7 @@ UINT32 FirmwareKB[] = { 0x58810000, 0x29820004, 0x78010003, - 0x38218b88, + 0x38218f90, 0x58220000, 0x41820016, 0x7806c020, @@ -3561,7 +3561,7 @@ UINT32 FirmwareKB[] = { 0x5b8f0008, 0x5b9d0004, 0x780b0003, - 0x396b8b88, + 0x396b8f90, 0x29610000, 0xf80011d1, 0xb8206000, @@ -3580,7 +3580,7 @@ UINT32 FirmwareKB[] = { 0x5c20000a, 0x78020003, 0x78010002, - 0x38428b24, + 0x38428f2c, 0x382132b0, 0x58410000, 0xfbffff6d, @@ -3612,7 +3612,7 @@ UINT32 FirmwareKB[] = { 0xf8001283, 0x78020003, 0x78010002, - 0x38428b24, + 0x38428f2c, 0x382137b0, 0x58410000, 0x34030001, @@ -3645,7 +3645,7 @@ UINT32 FirmwareKB[] = { 0xe000000c, 0x78030003, 0x78020002, - 0x38638b24, + 0x38638f2c, 0x384232b0, 0x4d800002, 0x34040001, @@ -3718,7 +3718,7 @@ UINT32 FirmwareKB[] = { 0xa0250800, 0x58410000, 0x4181000d, - 0x38c68b88, + 0x38c68f90, 0x3301077f, 0x4181000e, 0x33010781, @@ -3767,7 +3767,7 @@ UINT32 FirmwareKB[] = { 0x33010918, 0xe0000016, 0x33020918, - 0xf8002343, + 0xf80023ae, 0x4181000f, 0x396b00cc, 0x7802c050, @@ -3826,7 +3826,7 @@ UINT32 FirmwareKB[] = { 0x5c20000a, 0x78020003, 0x78010002, - 0x38428b24, + 0x38428f2c, 0x382130a4, 0x58410000, 0xfbffff5c, @@ -3858,7 +3858,7 @@ UINT32 FirmwareKB[] = { 0xf800118d, 0x78020003, 0x78010002, - 0x38428b24, + 0x38428f2c, 0x382143c8, 0x58410000, 0x34030001, @@ -3884,7 +3884,7 @@ UINT32 FirmwareKB[] = { 0x780d0003, 0x78010002, 0x38213b88, - 0x39ad8b24, + 0x39ad8f2c, 0x59a10000, 0x430106f0, 0x44200004, @@ -3913,7 +3913,7 @@ UINT32 FirmwareKB[] = { 0x330206ef, 0x78010003, 0x33020760, - 0x38218ba8, + 0x38218fb0, 0x30220019, 0x30220000, 0x38840004, @@ -3959,7 +3959,7 @@ UINT32 FirmwareKB[] = { 0x3c210002, 0xb42e0800, 0x28210000, - 0xf8001b18, + 0xf8001b6d, 0x34060000, 0x330606ed, 0x2f02073c, @@ -4023,7 +4023,7 @@ UINT32 FirmwareKB[] = { 0x202300ff, 0x78020002, 0x7c610001, - 0x38848b24, + 0x38848f2c, 0x38423000, 0xb8a04000, 0x5c250005, @@ -4038,7 +4038,7 @@ UINT32 FirmwareKB[] = { 0x7806c020, 0x34070001, 0x38630008, - 0x38a58b24, + 0x38a58f2c, 0x38843e94, 0x38c60024, 0x202200ff, @@ -4084,7 +4084,7 @@ UINT32 FirmwareKB[] = { 0x78010002, 0x330306e9, 0x330406f9, - 0x38428b24, + 0x38428f2c, 0x38213000, 0x58410000, 0xe0000007, @@ -4097,7 +4097,7 @@ UINT32 FirmwareKB[] = { 0x34010000, 0xe000012b, 0x78010003, - 0x38218b88, + 0x38218f90, 0x28220000, 0x2b0106f4, 0x5041000c, @@ -4327,7 +4327,7 @@ UINT32 FirmwareKB[] = { 0x3c210002, 0xb42c0800, 0x28210000, - 0xf80019a8, + 0xf80019fd, 0x2f02073c, 0x2f010748, 0x5422001d, @@ -4419,7 +4419,7 @@ UINT32 FirmwareKB[] = { 0xe000000c, 0x78030003, 0x78020002, - 0x38638b24, + 0x38638f2c, 0x384230a4, 0x4d800002, 0x34040001, @@ -4525,10 +4525,10 @@ UINT32 FirmwareKB[] = { 0x78040002, 0x78010003, 0x78020003, - 0x38218ba8, - 0x38638b24, - 0x3884e6e0, - 0x38422680, + 0x38218fb0, + 0x38638f2c, + 0x3884ea14, + 0x38422a60, 0x58620058, 0x302b0016, 0x30250000, @@ -4605,7 +4605,7 @@ UINT32 FirmwareKB[] = { 0x78050003, 0x38a5f818, 0x78010003, - 0x38218ba8, + 0x38218fb0, 0x30220000, 0x30220019, 0x302b0016, @@ -4618,9 +4618,9 @@ UINT32 FirmwareKB[] = { 0xb82b0800, 0x58a10000, 0x78020003, - 0x38638b24, - 0x3884e6e0, - 0x38422680, + 0x38638f2c, + 0x3884ea14, + 0x38422a60, 0x34010000, 0x58620058, 0x5864002c, @@ -4764,7 +4764,7 @@ UINT32 FirmwareKB[] = { 0x58410000, 0xfbfffed3, 0x78010003, - 0x38218ba8, + 0x38218fb0, 0xb5815800, 0x41630000, 0x44600013, @@ -4781,7 +4781,7 @@ UINT32 FirmwareKB[] = { 0xfbfffeb9, 0x3d810002, 0x78020003, - 0x38428b24, + 0x38428f2c, 0xb4220800, 0x28210000, 0xd8200000, @@ -4796,19 +4796,19 @@ UINT32 FirmwareKB[] = { 0x43010831, 0x7c210010, 0x5c200003, - 0xf8003518, + 0xf8003610, 0xe000000c, 0x43010831, 0x4420000a, 0x43010831, 0x7c210001, 0x5c200003, - 0xf800347f, + 0xf8003577, 0xe0000005, 0x43010831, 0x7c210002, 0x5c200002, - 0xf800348a, + 0xf8003582, 0x3401001f, 0xfbfffe99, 0xb9a00800, @@ -4852,8 +4852,8 @@ UINT32 FirmwareKB[] = { 0x78030003, 0x78020002, 0x78010003, - 0x38218ba8, - 0x38638b24, + 0x38218fb0, + 0x38638f2c, 0x38424a68, 0x30240006, 0x3024001f, @@ -4908,7 +4908,7 @@ UINT32 FirmwareKB[] = { 0x4381000f, 0x330106e6, 0x78010003, - 0x38218b20, + 0x38218f28, 0x28210000, 0x402100d3, 0x44200004, @@ -4959,19 +4959,19 @@ UINT32 FirmwareKB[] = { 0xb8621800, 0x58a30000, 0x330606e6, - 0x38848b24, + 0x38848f2c, 0x38214aac, 0x58810018, 0x34020001, 0x78010003, 0x33020813, - 0x38218b20, + 0x38218f28, 0x28220000, 0x78040003, 0x3884f820, 0x2c4100d4, 0x78030003, - 0x38638ba8, + 0x38638fb0, 0x0f010804, 0x2c4100d6, 0x0f010806, @@ -5007,7 +5007,7 @@ UINT32 FirmwareKB[] = { 0x379c0004, 0xc3a00000, 0x78010003, - 0x38218b20, + 0x38218f28, 0x430207b0, 0x28230000, 0xb0401000, @@ -5030,7 +5030,7 @@ UINT32 FirmwareKB[] = { 0xe3fffffc, 0xc3a00000, 0x78010003, - 0x38218b20, + 0x38218f28, 0x28240000, 0x430107b0, 0x288300c4, @@ -5061,7 +5061,7 @@ UINT32 FirmwareKB[] = { 0x5d60002a, 0x78020003, 0xb8406000, - 0x38428dc5, + 0x384291cd, 0x40410000, 0x5c20001f, 0xfbffffc6, @@ -5069,7 +5069,7 @@ UINT32 FirmwareKB[] = { 0xb0401000, 0x5c220006, 0x78010003, - 0x38218dc4, + 0x382191cc, 0x34020007, 0x30220000, 0xe0000008, @@ -5078,17 +5078,17 @@ UINT32 FirmwareKB[] = { 0xb0401000, 0x5c220004, 0x78010003, - 0x38218dc4, + 0x382191cc, 0x302b0000, 0x2f0107f0, 0xb9805800, - 0x396b8dc5, + 0x396b91cd, 0x2f0207f2, 0x2021ffff, 0x2042ffff, 0xfbfff568, 0x78020003, - 0x38428dc4, + 0x384291cc, 0x40420000, 0x3421ffff, 0x31610000, @@ -5103,7 +5103,7 @@ UINT32 FirmwareKB[] = { 0x7d610001, 0x5c200005, 0x78010003, - 0x38218dc5, + 0x382191cd, 0x34020000, 0x30220000, 0x2b8b000c, @@ -5187,7 +5187,7 @@ UINT32 FirmwareKB[] = { 0x202100ff, 0x780b0003, 0x7c230001, - 0x396b8b20, + 0x396b8f28, 0x3702078c, 0x5c200009, 0x29610000, @@ -5206,7 +5206,7 @@ UINT32 FirmwareKB[] = { 0x379c0008, 0xc3a00000, 0x78010003, - 0x38218b20, + 0x38218f28, 0x430207b0, 0x28230000, 0xb0401000, @@ -5234,7 +5234,7 @@ UINT32 FirmwareKB[] = { 0x5b8c0008, 0x5b9d0004, 0x78010003, - 0x38218b20, + 0x38218f28, 0x282c0000, 0x7802c050, 0x384200d8, @@ -5249,7 +5249,7 @@ UINT32 FirmwareKB[] = { 0xfbfffe5b, 0x430207b1, 0x78030003, - 0x38638b88, + 0x38638f90, 0xb0401000, 0x3c410002, 0x7808c020, @@ -5270,7 +5270,7 @@ UINT32 FirmwareKB[] = { 0x78040002, 0xb0401000, 0x3c410002, - 0x38a58b24, + 0x38a58f2c, 0xb4220800, 0x3c210002, 0x388456c0, @@ -5294,7 +5294,7 @@ UINT32 FirmwareKB[] = { 0x379cfffc, 0x5b9d0004, 0x78010003, - 0x38218b20, + 0x38218f28, 0x28260000, 0x7802c050, 0x384200d8, @@ -5302,7 +5302,7 @@ UINT32 FirmwareKB[] = { 0x4420ffff, 0x430207b1, 0x78030003, - 0x38638b88, + 0x38638f90, 0xb0401000, 0x3c410002, 0x7805c020, @@ -5346,8 +5346,8 @@ UINT32 FirmwareKB[] = { 0x78020002, 0x78010003, 0x33040761, - 0x38218ba8, - 0x38638b24, + 0x38218fb0, + 0x38638f2c, 0x38424a68, 0x58620004, 0x3024001a, @@ -5359,7 +5359,7 @@ UINT32 FirmwareKB[] = { 0x44200009, 0x78010002, 0x38630114, - 0x38a58b24, + 0x38a58f2c, 0x38215e24, 0x58a10004, 0x58640000, @@ -5370,7 +5370,7 @@ UINT32 FirmwareKB[] = { 0x58620000, 0x78010002, 0x330207b7, - 0x38a58b24, + 0x38a58f2c, 0x382156c0, 0x58a10004, 0xe000000c, @@ -5382,7 +5382,7 @@ UINT32 FirmwareKB[] = { 0xfbfffdd6, 0x78020003, 0x78010002, - 0x38428b24, + 0x38428f2c, 0x382156c0, 0x58410004, 0x34010000, @@ -5393,7 +5393,7 @@ UINT32 FirmwareKB[] = { 0x3c220002, 0x78030003, 0xb4411000, - 0x38638b20, + 0x38638f28, 0x28610000, 0x3c420002, 0xb4411000, @@ -5417,7 +5417,7 @@ UINT32 FirmwareKB[] = { 0x780d0003, 0x78010002, 0x38215380, - 0x39ad8b24, + 0x39ad8f2c, 0x59a10004, 0x430107b8, 0x44200004, @@ -5425,7 +5425,7 @@ UINT32 FirmwareKB[] = { 0x330107b1, 0xe0000028, 0x780c0003, - 0x398c8b20, + 0x398c8f28, 0x29810000, 0x402b00ca, 0x216100ff, @@ -5446,7 +5446,7 @@ UINT32 FirmwareKB[] = { 0x78020002, 0x78010003, 0x33030761, - 0x38218ba8, + 0x38218fb0, 0x38424a68, 0x59a20004, 0x3023001a, @@ -5471,7 +5471,7 @@ UINT32 FirmwareKB[] = { 0xfbfffd7d, 0x430207b1, 0x780e0003, - 0x39ce8b20, + 0x39ce8f28, 0xb0401000, 0x3c410002, 0x29c30000, @@ -5483,7 +5483,7 @@ UINT32 FirmwareKB[] = { 0x340b0000, 0x780dc050, 0x2021ffff, - 0xf8001524, + 0xf8001579, 0x330b07b5, 0x330b07b3, 0x330b07b4, @@ -5506,7 +5506,7 @@ UINT32 FirmwareKB[] = { 0xfbfffd5a, 0x78020003, 0x78010002, - 0x38428b24, + 0x38428f2c, 0x382151b8, 0x58410004, 0x430207b1, @@ -5581,7 +5581,7 @@ UINT32 FirmwareKB[] = { 0x33060919, 0xe0000018, 0x330b0919, - 0xf8001c2d, + 0xf8001c98, 0x430207b1, 0x29c30000, 0xb9802800, @@ -5623,7 +5623,7 @@ UINT32 FirmwareKB[] = { 0x5b9d0004, 0x780d0003, 0xb9a00800, - 0x38218b20, + 0x38218f28, 0x282c0000, 0xb9a07000, 0x430107b6, @@ -5725,7 +5725,7 @@ UINT32 FirmwareKB[] = { 0x330107ae, 0x430307b0, 0xb9c01000, - 0x38428b20, + 0x38428f28, 0xb0601800, 0x3c610002, 0x28420000, @@ -5748,7 +5748,7 @@ UINT32 FirmwareKB[] = { 0x330107b1, 0x430207b0, 0x780d0003, - 0x39ad8b20, + 0x39ad8f28, 0xb0401000, 0x3c410002, 0x29a30000, @@ -5785,7 +5785,7 @@ UINT32 FirmwareKB[] = { 0x78010002, 0xb8822000, 0x382150c0, - 0x38638b24, + 0x38638f2c, 0x58a40000, 0x58610004, 0x430207b1, @@ -5858,7 +5858,7 @@ UINT32 FirmwareKB[] = { 0x330f0919, 0xe0000018, 0x33100919, - 0xf8001b18, + 0xf8001b83, 0x430207b1, 0x29a30000, 0xb9602800, @@ -5891,7 +5891,7 @@ UINT32 FirmwareKB[] = { 0x5022009d, 0x430107b3, 0xb9a07800, - 0x39ef8b20, + 0x39ef8f28, 0x34210001, 0x330107b3, 0xfbfffc9f, @@ -5925,7 +5925,7 @@ UINT32 FirmwareKB[] = { 0xb4240800, 0x28210004, 0x2021ffff, - 0xf800136a, + 0xf80013bf, 0x7801c020, 0x38210130, 0x34020004, @@ -5947,7 +5947,7 @@ UINT32 FirmwareKB[] = { 0x78010002, 0xb8822000, 0x382151b8, - 0x38638b24, + 0x38638f2c, 0x58a40000, 0x58610004, 0x430207b1, @@ -6018,7 +6018,7 @@ UINT32 FirmwareKB[] = { 0x330d0919, 0xe0000018, 0x33010919, - 0xf8001a78, + 0xf8001ae3, 0x430207b1, 0x29e30000, 0xb9602800, @@ -6051,7 +6051,7 @@ UINT32 FirmwareKB[] = { 0x5441001c, 0x430107b5, 0x78050003, - 0x38a58b20, + 0x38a58f28, 0x34210001, 0x330107b5, 0x430207b0, @@ -6094,7 +6094,7 @@ UINT32 FirmwareKB[] = { 0x78020002, 0x38a50114, 0x34060001, - 0x38848b24, + 0x38848f2c, 0x384256c0, 0x202100ff, 0x34030000, @@ -6117,7 +6117,7 @@ UINT32 FirmwareKB[] = { 0x379cfffc, 0x5b9d0004, 0x78010003, - 0x38218b20, + 0x38218f28, 0x28210000, 0x402100c8, 0x44200010, @@ -6132,7 +6132,7 @@ UINT32 FirmwareKB[] = { 0x3821f820, 0x28220000, 0x78010003, - 0x38218ba8, + 0x38218fb0, 0x30220001, 0x3022001a, 0xe0000002, @@ -6157,12 +6157,12 @@ UINT32 FirmwareKB[] = { 0x78030003, 0x3863f818, 0x78010003, - 0x38218ba8, + 0x38218fb0, 0x30220001, 0x3022001a, 0x28620000, 0x78010003, - 0x38218b20, + 0x38218f28, 0x28210000, 0x38420004, 0x58620000, @@ -6388,7 +6388,7 @@ UINT32 FirmwareKB[] = { 0x3301091b, 0xe0000017, 0x3302091b, - 0xf8001906, + 0xf8001971, 0x4181000a, 0x396b00a4, 0x7802c050, @@ -6452,7 +6452,7 @@ UINT32 FirmwareKB[] = { 0x3301091c, 0xe0000017, 0x3302091c, - 0xf80018c6, + 0xf8001931, 0x4181000b, 0x396b009c, 0x7802c050, @@ -6475,7 +6475,7 @@ UINT32 FirmwareKB[] = { 0x58810000, 0x29820000, 0x78010003, - 0x38218b88, + 0x38218f90, 0x58220008, 0x298c0004, 0x582c000c, @@ -6501,7 +6501,7 @@ UINT32 FirmwareKB[] = { 0x78020003, 0x78010002, 0x3303008a, - 0x38428b24, + 0x38428f2c, 0x38216788, 0x58410030, 0x43020089, @@ -6554,10 +6554,10 @@ UINT32 FirmwareKB[] = { 0xb4220800, 0x2c210008, 0x34020006, - 0xf80010f5, + 0xf800114a, 0x78020003, 0x78010002, - 0x38428b24, + 0x38428f2c, 0x3821645c, 0x58410030, 0xfbffffb4, @@ -6819,13 +6819,13 @@ UINT32 FirmwareKB[] = { 0x78050003, 0x78040002, 0x78030003, - 0x38c68ba8, + 0x38c68fb0, 0x38e7f000, - 0x38a58b24, + 0x38a58f2c, 0x38846788, 0x34080001, 0x34020000, - 0x38638b88, + 0x38638f90, 0x20210010, 0x4422000c, 0x40e702ec, @@ -6862,12 +6862,12 @@ UINT32 FirmwareKB[] = { 0x38a5009c, 0x386301c8, 0x38c60118, - 0x39298ba8, + 0x39298fb0, 0x398cf000, - 0x396b8b24, + 0x396b8f2c, 0x394a6788, 0x340e0001, - 0x38e78b88, + 0x38e78f90, 0x3908f818, 0x39adf900, 0x202200ff, @@ -7069,7 +7069,7 @@ UINT32 FirmwareKB[] = { 0x33010921, 0xe0000018, 0x33010921, - 0xf800165d, + 0xf80016c8, 0x41810006, 0x396b00e4, 0x7802c050, @@ -7093,7 +7093,7 @@ UINT32 FirmwareKB[] = { 0x58610000, 0x298c0000, 0x78010003, - 0x38218b88, + 0x38218f90, 0x582c0010, 0x2b8b000c, 0x2b8c0008, @@ -7119,7 +7119,7 @@ UINT32 FirmwareKB[] = { 0x78020003, 0x78010002, 0x330300f9, - 0x38428b24, + 0x38428f2c, 0x3821714c, 0x5841003c, 0x430200f8, @@ -7179,10 +7179,10 @@ UINT32 FirmwareKB[] = { 0x33010769, 0x2c610004, 0x34020009, - 0xf8000e84, + 0xf8000ed9, 0x78020003, 0x78010002, - 0x38428b24, + 0x38428f2c, 0x38216dfc, 0x5841003c, 0xfbffffab, @@ -7398,13 +7398,13 @@ UINT32 FirmwareKB[] = { 0x78050003, 0x78040002, 0x78030003, - 0x38c68ba8, + 0x38c68fb0, 0x38e7f000, - 0x38a58b24, + 0x38a58f2c, 0x3884714c, 0x34080001, 0x34020000, - 0x38638b88, + 0x38638f90, 0x20210080, 0x4422000b, 0x40e702ef, @@ -7440,12 +7440,12 @@ UINT32 FirmwareKB[] = { 0x394a01c8, 0x39080000, 0x396b0118, - 0x38848ba8, + 0x38848fb0, 0x39adf000, - 0x39298b24, + 0x39298f2c, 0x38a5714c, 0x340e0001, - 0x38c68b88, + 0x38c68f90, 0x3863f818, 0x398cf900, 0x202200ff, @@ -7537,7 +7537,7 @@ UINT32 FirmwareKB[] = { 0x3301091a, 0xe0000017, 0x3301091a, - 0xf8001489, + 0xf80014f4, 0x41810006, 0x396b00ac, 0x7802c050, @@ -7560,7 +7560,7 @@ UINT32 FirmwareKB[] = { 0x58810000, 0x298c0000, 0x78010003, - 0x38218b88, + 0x38218f90, 0x582c0018, 0x2b8b000c, 0x2b8c0008, @@ -7586,7 +7586,7 @@ UINT32 FirmwareKB[] = { 0x78020003, 0x78010002, 0x330300a7, - 0x38428b24, + 0x38428f2c, 0x382179d0, 0x58410034, 0x430100a5, @@ -7633,10 +7633,10 @@ UINT32 FirmwareKB[] = { 0x33010767, 0x2c610004, 0x34020007, - 0xf8000cbe, + 0xf8000d13, 0x78020003, 0x78010002, - 0x38428b24, + 0x38428f2c, 0x38217548, 0x58410034, 0xfbffffb8, @@ -7769,7 +7769,7 @@ UINT32 FirmwareKB[] = { 0x442b0017, 0x78010003, 0x330b00aa, - 0x38218b88, + 0x38218f90, 0x28220018, 0x2b0100b8, 0x5c410011, @@ -7792,7 +7792,7 @@ UINT32 FirmwareKB[] = { 0x430100ab, 0x5c20000c, 0x78010003, - 0x38218b88, + 0x38218f90, 0x28220018, 0x2b0100b8, 0x4441002e, @@ -7936,12 +7936,12 @@ UINT32 FirmwareKB[] = { 0x78020002, 0x78070003, 0x38c6f000, - 0x38a58ba8, - 0x38848b24, + 0x38a58fb0, + 0x38848f2c, 0x384279d0, 0x34030001, 0x34080000, - 0x38e78b88, + 0x38e78f90, 0x20210020, 0x44280011, 0x40c102ed, @@ -7981,11 +7981,11 @@ UINT32 FirmwareKB[] = { 0x39290118, 0x394a00ac, 0x3884f000, - 0x38428ba8, - 0x38e78b24, + 0x38428fb0, + 0x38e78f2c, 0x38a579d0, 0x340d0001, - 0x396b8b88, + 0x396b8f90, 0x3908f818, 0x398cf900, 0x202300ff, @@ -8401,8 +8401,8 @@ UINT32 FirmwareKB[] = { 0x78010003, 0x78040003, 0x34020003, - 0x38848e34, - 0x38218e30, + 0x3884923c, + 0x38219238, 0x7803c020, 0x58820000, 0x58220000, @@ -8436,42 +8436,42 @@ UINT32 FirmwareKB[] = { 0x58240000, 0xb8406000, 0x38a5fa04, - 0x5c60035c, + 0x5c60036c, 0x3c810002, 0x78020003, - 0x38427df4, + 0x384281d4, 0xb4220800, 0x28210000, 0xc0200000, 0x34030000, - 0xe0000357, + 0xe0000367, 0x340300fe, - 0xe0000355, + 0xe0000365, 0x340300fe, - 0xe0000353, + 0xe0000363, 0x340300fe, - 0xe0000351, + 0xe0000361, 0x340300fe, - 0xe000034f, + 0xe000035f, 0x340300fe, - 0xe000034d, + 0xe000035d, 0x340300fe, - 0xe000034b, + 0xe000035b, 0x340300fe, - 0xe0000349, + 0xe0000359, 0x340300fe, - 0xe0000347, + 0xe0000357, 0x340300fe, - 0xe0000345, + 0xe0000355, 0x340300fe, - 0xe0000343, + 0xe0000353, 0x340300fe, - 0xe0000341, + 0xe0000351, 0x340300fe, - 0xe000033f, + 0xe000034f, 0x430106ee, 0x340300ff, - 0x4420033c, + 0x4420034c, 0x34010000, 0x78030003, 0x330106f0, @@ -8482,57 +8482,57 @@ UINT32 FirmwareKB[] = { 0xa0411000, 0x58620000, 0x34030000, - 0xe0000331, + 0xe0000341, 0x340300fe, - 0xe000032f, + 0xe000033f, 0x340300fe, - 0xe000032d, - 0xf8001005, + 0xe000033d, + 0xf8001062, 0x34030000, - 0xe000032a, - 0xf800101a, + 0xe000033a, + 0xf8001077, 0x34030000, - 0xe0000327, + 0xe0000337, 0x78030003, - 0x38638c00, + 0x38639008, 0x2ca20002, 0x2c61003e, 0x48220003, 0x406100ab, - 0x5c20031f, - 0xf8000c7a, - 0xe000031d, + 0x5c20032f, + 0xf8000cd7, + 0xe000032d, 0x78030003, - 0x38638c00, + 0x38639008, 0x2ca20002, 0x2c61003e, 0x48220003, 0x406100ab, - 0x5c200316, - 0xf8000bc0, - 0xe0000314, + 0x5c200326, + 0xf8000c1d, + 0xe0000324, 0x340300fe, - 0xe0000313, + 0xe0000323, 0x340300fe, - 0xe0000311, + 0xe0000321, 0x340300fe, - 0xe000030f, + 0xe000031f, 0x340300fe, - 0xe000030d, + 0xe000031d, 0x34010001, 0xe0000002, 0x34010000, 0x33010114, - 0xe0000307, + 0xe0000317, 0x5b0c0118, - 0xe0000305, + 0xe0000315, 0x34010000, 0xe0000002, 0x34010001, 0x33010079, - 0xe0000300, - 0xf8001dd7, - 0xe00002fe, + 0xe0000310, + 0xf8001e9a, + 0xe000030e, 0x90005800, 0x34010000, 0xd0010000, @@ -8541,16 +8541,24 @@ UINT32 FirmwareKB[] = { 0x7801c201, 0x33020774, 0x3821c588, - 0xf800161a, + 0xf80016e7, 0x38220003, 0x7801c201, 0x3821c588, - 0xf80015fc, - 0xf8001d74, + 0xf80016c9, + 0x7801c201, + 0x3821c52c, + 0xf80016e0, + 0x78020003, + 0x38428ed0, + 0x6c230000, + 0x5841003c, + 0x4460fff9, + 0xf8001e2f, 0xd00b0000, - 0xe00002ee, - 0xf8001e3d, - 0xe00002ec, + 0xe00002f6, + 0xf8001ef8, + 0xe00002f4, 0x90005800, 0x34010000, 0xd0010000, @@ -8559,49 +8567,57 @@ UINT32 FirmwareKB[] = { 0x7801c201, 0x33020774, 0x3821c588, - 0xf8001608, + 0xf80016cd, 0x38220003, 0x7801c201, 0x3821c588, - 0xf80015ea, - 0xf8001df1, + 0xf80016af, + 0x7801c201, + 0x3821c52c, + 0xf80016c6, + 0x78020003, + 0x38428ed0, + 0x6c230000, + 0x5841003c, + 0x4460fff9, + 0xf8001ea4, 0xd00b0000, 0xe00002dc, - 0xf8001d32, + 0xf8001de5, 0xe00002da, 0x90005800, 0x34010000, 0xd0010000, - 0xf8001cf1, + 0xf8001da4, 0xd00b0000, 0xe00002d4, - 0xf8001e65, + 0xf8001f18, 0xe00002d2, - 0xf8001e54, + 0xf8001f07, 0xe00002d0, 0x90005800, 0x34010000, 0xd0010000, - 0xf8001e70, + 0xf8001f23, 0xd00b0000, 0xe00002ca, 0x90005800, 0x34010000, 0xd0010000, - 0xf8001e69, + 0xf8001f1c, 0xd00b0000, 0xe00002c4, 0x90005800, 0x34010000, 0xd0010000, 0x34010001, - 0xf8001018, + 0xf8001065, 0xd00b0000, 0xe00002bd, 0x90005800, 0x34010000, 0xd0010000, - 0xf8001012, + 0xf800105f, 0xd00b0000, 0x34030000, 0xe00002b7, @@ -8691,19 +8707,19 @@ UINT32 FirmwareKB[] = { 0x7d810000, 0x33010760, 0xe0000260, - 0xfbffe739, - 0xfbffe9dc, - 0xfbfff202, - 0xfbfff81e, - 0xfbfffa8e, - 0xfbfffcae, + 0xfbffe729, + 0xfbffe9cc, + 0xfbfff1f2, + 0xfbfff80e, + 0xfbfffa7e, + 0xfbfffc9e, 0x34030001, 0xe0000259, - 0xfbffe966, - 0xfbfff180, - 0xfbfff81e, - 0xfbfffa8e, - 0xfbfffcae, + 0xfbffe956, + 0xfbfff170, + 0xfbfff80e, + 0xfbfffa7e, + 0xfbfffc9e, 0x34030001, 0xe0000252, 0x34010001, @@ -8712,7 +8728,7 @@ UINT32 FirmwareKB[] = { 0x34000000, 0x34000000, 0x34000000, - 0xfbffef8e, + 0xfbffef7e, 0x34030000, 0xe0000249, 0x90005800, @@ -8724,7 +8740,7 @@ UINT32 FirmwareKB[] = { 0x34000000, 0x34000000, 0x34000000, - 0xfbffefab, + 0xfbffef9b, 0xd00b0000, 0x34030000, 0xe000023c, @@ -8737,7 +8753,7 @@ UINT32 FirmwareKB[] = { 0x34000000, 0x34000000, 0x34000000, - 0xfbffeff4, + 0xfbffefe4, 0xd00b0000, 0x34030000, 0xe000022f, @@ -8750,7 +8766,7 @@ UINT32 FirmwareKB[] = { 0x34000000, 0x34000000, 0x34000000, - 0xfbfff5b4, + 0xfbfff5a4, 0xd00b0000, 0x34030000, 0xe0000222, @@ -8763,7 +8779,7 @@ UINT32 FirmwareKB[] = { 0x34000000, 0x34000000, 0x34000000, - 0xfbfff5c1, + 0xfbfff5b1, 0xd00b0000, 0x34030000, 0xe0000215, @@ -8776,7 +8792,7 @@ UINT32 FirmwareKB[] = { 0x34000000, 0x34000000, 0x34000000, - 0xfbfff5e8, + 0xfbfff5d8, 0xd00b0000, 0x34030000, 0xe0000208, @@ -8784,7 +8800,7 @@ UINT32 FirmwareKB[] = { 0x34010000, 0xd0010000, 0x78030003, - 0x38638b20, + 0x38638f28, 0x28610000, 0x34070001, 0x282200c4, @@ -8825,7 +8841,7 @@ UINT32 FirmwareKB[] = { 0xb8e01800, 0xe00001dc, 0x78010003, - 0x38218b20, + 0x38218f28, 0x28210000, 0x34050000, 0xb8a02000, @@ -8931,7 +8947,7 @@ UINT32 FirmwareKB[] = { 0x34000000, 0x34000000, 0x34000000, - 0xfbfff7b8, + 0xfbfff7a8, 0xd00b0000, 0x34030000, 0xe000016d, @@ -8944,7 +8960,7 @@ UINT32 FirmwareKB[] = { 0x34000000, 0x34000000, 0x34000000, - 0xfbfff7c9, + 0xfbfff7b9, 0xd00b0000, 0x34030000, 0xe0000160, @@ -8957,7 +8973,7 @@ UINT32 FirmwareKB[] = { 0x34000000, 0x34000000, 0x34000000, - 0xfbfff806, + 0xfbfff7f6, 0xd00b0000, 0x34030000, 0xe0000153, @@ -9005,7 +9021,7 @@ UINT32 FirmwareKB[] = { 0x34000000, 0x34000000, 0x34000000, - 0xfbfff9b1, + 0xfbfff9a1, 0xd00b0000, 0x34030000, 0xe0000123, @@ -9018,7 +9034,7 @@ UINT32 FirmwareKB[] = { 0x34000000, 0x34000000, 0x34000000, - 0xfbfff9c1, + 0xfbfff9b1, 0xd00b0000, 0x34030000, 0xe0000116, @@ -9031,7 +9047,7 @@ UINT32 FirmwareKB[] = { 0x34000000, 0x34000000, 0x34000000, - 0xfbfff9f2, + 0xfbfff9e2, 0xd00b0000, 0x34030000, 0xe0000109, @@ -9079,7 +9095,7 @@ UINT32 FirmwareKB[] = { 0x34000000, 0x34000000, 0x34000000, - 0xfbfffb80, + 0xfbfffb70, 0xd00b0000, 0x34030000, 0xe00000d9, @@ -9092,7 +9108,7 @@ UINT32 FirmwareKB[] = { 0x34000000, 0x34000000, 0x34000000, - 0xfbfffb96, + 0xfbfffb86, 0xd00b0000, 0x34030000, 0xe00000cc, @@ -9105,7 +9121,7 @@ UINT32 FirmwareKB[] = { 0x34000000, 0x34000000, 0x34000000, - 0xfbfffbc6, + 0xfbfffbb6, 0xd00b0000, 0x34030000, 0xe00000bf, @@ -9150,7 +9166,7 @@ UINT32 FirmwareKB[] = { 0x340300ff, 0x44200097, 0x218100ff, - 0xfbffe75d, + 0xfbffe74d, 0x340300ff, 0x44200093, 0x34010001, @@ -9193,7 +9209,7 @@ UINT32 FirmwareKB[] = { 0x38210000, 0x34020000, 0x58410000, - 0xfbffe268, + 0xfbffe258, 0x78018000, 0x38218000, 0x3402ffff, @@ -9226,16 +9242,16 @@ UINT32 FirmwareKB[] = { 0xe000004c, 0x340300fe, 0xe000004a, - 0xf8001875, + 0xf8001928, 0xe0000047, - 0xf80018d2, + 0xf8001985, 0xe0000045, 0x90005800, 0x34010000, 0xd0010000, 0x43010789, 0x5c200002, - 0xf8001553, + 0xf8001610, 0xd00b0000, 0xe000003d, 0x90005800, @@ -9244,7 +9260,7 @@ UINT32 FirmwareKB[] = { 0x4301078a, 0x7c210001, 0x5c200002, - 0xf80015a6, + 0xf8001663, 0xd00b0000, 0xe0000034, 0x43010789, @@ -9269,29 +9285,29 @@ UINT32 FirmwareKB[] = { 0x33010787, 0xb8201800, 0xe000001f, - 0xf8002212, + 0xf80022fa, 0xe000001c, - 0xf800224c, + 0xf8002334, 0xe000001a, - 0xf800225a, + 0xf8002342, 0xe0000018, - 0xf800228d, + 0xf8002375, 0xe0000016, - 0xf800243d, + 0xf8002525, 0xe0000014, - 0xf8002445, + 0xf800252d, 0xe0000012, 0x218100ff, - 0xf8000e2f, + 0xf8000e9a, 0xe000000f, - 0xf8000e4d, + 0xf8000eb8, 0xe000000d, 0x218100ff, - 0xf8000e64, + 0xf8000edb, 0xe000000a, - 0xf8000e82, + 0xf8000ef9, 0xe0000008, - 0xf80018ef, + 0xf80019a2, 0xe0000006, 0x34010001, 0x33010735, @@ -9467,7 +9483,7 @@ UINT32 FirmwareKB[] = { 0xe000001b, 0x430307b0, 0x78020003, - 0x38428b20, + 0x38428f28, 0xb0601800, 0x3c610002, 0x28420000, @@ -9507,7 +9523,7 @@ UINT32 FirmwareKB[] = { 0x0f0300cc, 0xe0000007, 0x78010003, - 0x38218408, + 0x382187e8, 0xb4421000, 0xb4411000, 0x2c41ff00, @@ -9541,7 +9557,7 @@ UINT32 FirmwareKB[] = { 0x340200ff, 0x7c210001, 0x5c20002d, - 0xfbfffa21, + 0xfbfffa11, 0x5b0106f4, 0xe0000021, 0x43010088, @@ -9580,7 +9596,7 @@ UINT32 FirmwareKB[] = { 0xe0000008, 0x340200fe, 0xe0000006, - 0xf80026cf, + 0xf80027b7, 0x78028000, 0x38420074, 0x58410000, @@ -9598,7 +9614,7 @@ UINT32 FirmwareKB[] = { 0x5c200010, 0xe0000007, 0x78010003, - 0x38218b88, + 0x38218f90, 0x28210000, 0x5441000b, 0xb8601000, @@ -9650,13 +9666,13 @@ UINT32 FirmwareKB[] = { 0x340200ff, 0x7c210001, 0x5c200048, - 0xfbfff9b4, + 0xfbfff9a4, 0x5b0106f4, 0xe0000008, 0x5b0200b0, 0xe0000006, 0xb8400800, - 0xfbfff882, + 0xfbfff872, 0xb8201800, 0x55610004, 0x5b0b00b8, @@ -9668,11 +9684,11 @@ UINT32 FirmwareKB[] = { 0x340200ff, 0xe0000037, 0x78010003, - 0x38218b88, + 0x38218f90, 0x28220000, 0xe0000004, 0x78010003, - 0x38218b88, + 0x38218f90, 0x28220018, 0x78018000, 0x38210078, @@ -9738,17 +9754,17 @@ UINT32 FirmwareKB[] = { 0x5c20000c, 0xe0000012, 0x78010003, - 0x38218b88, + 0x38218f90, 0x28210000, 0xf4411000, 0xc8621000, 0xe000000d, 0x78010003, - 0x38218b88, + 0x38218f90, 0x28210000, 0xe0000004, 0x78010003, - 0x38218b88, + 0x38218f90, 0x28210018, 0xf4411000, 0x34010001, @@ -9764,10 +9780,10 @@ UINT32 FirmwareKB[] = { 0xb8402000, 0x74610006, 0x340200fe, - 0x5c200048, + 0x5c200050, 0x3c610002, 0x78020003, - 0x38428418, + 0x384287f8, 0xb4220800, 0x28210000, 0xc0200000, @@ -9775,11 +9791,11 @@ UINT32 FirmwareKB[] = { 0x3821007c, 0x34820001, 0x58220000, - 0xe000003c, + 0xe0000044, 0x90005800, 0x34010000, 0xd0010000, - 0xf8001826, + 0xf80018d9, 0x43010824, 0x7c210001, 0x5c200008, @@ -9793,26 +9809,34 @@ UINT32 FirmwareKB[] = { 0x34010000, 0x33010779, 0xd00b0000, - 0xe000002a, + 0xe0000032, 0x90005800, 0x34010000, 0xd0010000, 0x43010824, 0x202200ff, 0x7c410001, - 0x5c20000d, + 0x5c200015, 0x43010826, - 0x5c20000b, + 0x5c200013, 0x33020826, 0x3302082c, 0x7801c201, 0x33020774, 0x3821c588, - 0xf8001127, + 0xf80011e4, 0x38220003, 0x7801c201, 0x3821c588, - 0xf8001109, + 0xf80011c6, + 0x7801c201, + 0x3821c52c, + 0xf80011dd, + 0x78020003, + 0x38428ed0, + 0x6c230000, + 0x5841003c, + 0x4460fff9, 0x34010001, 0x33010779, 0x4301077b, @@ -9825,16 +9849,16 @@ UINT32 FirmwareKB[] = { 0x90005800, 0x34010000, 0xd0010000, - 0xf80017dd, + 0xf8001888, 0xd00b0000, 0xe0000008, 0x90005800, 0x34010000, 0xd0010000, - 0xf80017f2, + 0xf800189d, 0xd00b0000, 0xe0000002, - 0xf80006ae, + 0xf80006f3, 0x34020001, 0xb8400800, 0x2b8b0008, @@ -9891,11 +9915,11 @@ UINT32 FirmwareKB[] = { 0x5b020104, 0xe000002c, 0x78010003, - 0x38218b88, + 0x38218f90, 0x28220000, 0xe0000004, 0x78010003, - 0x38218b88, + 0x38218f90, 0x28220010, 0x78018000, 0x38210084, @@ -9937,7 +9961,7 @@ UINT32 FirmwareKB[] = { 0xe0000008, 0x340200fe, 0xe0000006, - 0xf800256a, + 0xf800264a, 0x78028000, 0x38420084, 0x58410000, @@ -9959,13 +9983,13 @@ UINT32 FirmwareKB[] = { 0x5c200019, 0xe000000e, 0x78010003, - 0x38218b88, + 0x38218f90, 0x28210000, 0xf4411000, 0xc8621000, 0xe0000013, 0x78010003, - 0x38218b88, + 0x38218f90, 0x28210010, 0xf4411000, 0x34010001, @@ -9988,95 +10012,156 @@ UINT32 FirmwareKB[] = { 0x5b8b000c, 0x5b8c0008, 0x5b9d0004, - 0x3423ffff, - 0x78040003, - 0x74610059, + 0x3424ffff, + 0x78050003, + 0x78030003, + 0x74810062, 0xb8406000, - 0x3884fa04, - 0x5c200195, - 0x3c610002, + 0x38a5fa04, + 0x3863fa80, + 0x5c2001d0, + 0x3c810002, 0x78020003, - 0x38428434, + 0x38428814, 0xb4220800, 0x28210000, 0xc0200000, - 0xfbfff9d0, - 0xe000018f, + 0xfbfff9b6, + 0xe00001ca, 0x90005800, 0x34010000, 0xd0010000, - 0xf8001e51, + 0xf8001f2f, 0xd00b0000, - 0xe0000189, + 0xe00001c4, 0x90005800, 0x34010000, 0xd0010000, - 0xf8001e72, + 0xf8001f50, 0xd00b0000, - 0xe0000183, + 0xe00001be, 0x78010003, - 0x38218c00, + 0x38219008, 0x402100ab, - 0x5c20017f, + 0x5c2001ba, 0x34010001, 0xe0000005, 0x78010003, - 0x38218c00, + 0x38219008, 0x402100ab, - 0x5c200179, + 0x5c2001b4, 0x3301069b, - 0xf80014ac, - 0xe0000176, + 0xf800155d, + 0xe00001b1, 0x78010003, - 0x38218c00, + 0x38219008, 0x402100ab, - 0x5c200172, - 0xf8001415, - 0xe0000170, + 0x5c2001ad, + 0xf80014c8, + 0xe00001ab, 0x78030003, - 0x38638c00, - 0x2c820002, + 0x38639008, + 0x2ca20002, 0x2c61003e, 0x48220003, 0x406100ab, - 0x5c200169, + 0x5c2001a4, 0x34010001, - 0xf8001326, - 0xe0000166, + 0xf80013d9, + 0xe00001a1, 0x90005800, 0x34010000, 0xd0010000, - 0xf8001a93, + 0xf8001b71, 0xd00b0000, - 0xe0000160, + 0xe000019b, 0x90005800, 0x34010000, 0xd0010000, - 0xf8001aaf, + 0xf8001b8d, 0xd00b0000, - 0xe000015a, + 0xe0000195, 0x35810068, 0x3c210007, 0x78020003, 0x5b01081c, - 0x38428c00, + 0x38429008, 0x40410029, 0x2b02081c, 0x3c210007, 0xc8411000, 0x5b020820, + 0xe000018a, + 0x78010003, + 0x38219008, + 0x302c00c4, + 0x7801c201, + 0x306c00c4, + 0x3821c45c, + 0xf80010d2, + 0x21840007, + 0x3c840002, + 0x3402ffe3, + 0xa0221000, + 0x78030003, + 0xb8441000, + 0x38638ed0, + 0x7801c201, + 0x58620044, + 0x3821c45c, + 0xf80010ad, + 0xe0000177, + 0x78010003, + 0x38219008, + 0x0c2c00c6, + 0x0c6c00c6, + 0xe0000172, + 0x78010003, + 0x38219008, + 0x302c00ab, + 0x306c00ab, + 0xe000016d, + 0x78010003, + 0x38219008, + 0x0c2c0036, + 0x0c6c0036, + 0xe0000168, + 0x78010003, + 0x38219008, + 0x0c2c0032, + 0x0c6c0032, + 0xe0000163, + 0x78010003, + 0x38219008, + 0x302c00b4, + 0x306c00b4, + 0xe000015e, + 0x78010003, + 0x38219008, + 0x302c00b5, + 0x306c00b5, + 0xe0000159, + 0x78010003, + 0x38219008, + 0x302c00b6, + 0x306c00b6, + 0xe0000154, + 0x78010003, + 0x38219008, + 0x0c2c00c0, + 0x0c6c00c0, 0xe000014f, 0x78030003, - 0x38638c00, - 0x2c820002, + 0x38639008, + 0x2ca20002, 0x2c61003e, 0x4822001e, 0x406100ab, 0x5c200148, 0xe000001b, 0x78030003, - 0x38638c00, - 0x2c820002, + 0x38639008, + 0x2ca20002, 0x2c61003e, 0x48220003, 0x406100ab, @@ -10089,8 +10174,8 @@ UINT32 FirmwareKB[] = { 0xb8201800, 0xe000013a, 0x78030003, - 0x38638c00, - 0x2c820002, + 0x38639008, + 0x2ca20002, 0x2c61003e, 0x48220003, 0x406100ab, @@ -10102,7 +10187,7 @@ UINT32 FirmwareKB[] = { 0x44400005, 0x43010158, 0x5c20012b, - 0xf800167a, + 0xf80016e8, 0xe0000129, 0x43010158, 0x7c210001, @@ -10156,7 +10241,7 @@ UINT32 FirmwareKB[] = { 0x34000000, 0x34000000, 0x34000000, - 0xfbfff036, + 0xfbffefe1, 0xe00000c6, 0x34010001, 0xd0810000, @@ -10164,7 +10249,7 @@ UINT32 FirmwareKB[] = { 0x34000000, 0x34000000, 0x34000000, - 0xfbfff048, + 0xfbffeff3, 0xe00000be, 0x34010001, 0xd0810000, @@ -10172,13 +10257,13 @@ UINT32 FirmwareKB[] = { 0x34000000, 0x34000000, 0x34000000, - 0xfbfff074, + 0xfbfff01f, 0xe00000b6, 0x430107b6, 0x340300ff, 0x442000e1, 0x218100ff, - 0xfbffed4b, + 0xfbffecf6, 0x340300ff, 0x442000dd, 0x34010001, @@ -10210,7 +10295,7 @@ UINT32 FirmwareKB[] = { 0xe0000094, 0x78040003, 0xb8800800, - 0x38218b20, + 0x38218f28, 0x28210000, 0x34070003, 0x340300ff, @@ -10224,7 +10309,7 @@ UINT32 FirmwareKB[] = { 0x34010000, 0xd0010000, 0xb8801000, - 0x38428b20, + 0x38428f28, 0x28410000, 0x34040000, 0x282100c4, @@ -10264,7 +10349,7 @@ UINT32 FirmwareKB[] = { 0x34000000, 0x34000000, 0x34000000, - 0xf80002f0, + 0xf80002f8, 0xd00b0000, 0xe0000086, 0x90005800, @@ -10276,7 +10361,7 @@ UINT32 FirmwareKB[] = { 0x34000000, 0x34000000, 0x34000000, - 0xf8000305, + 0xf800030d, 0xd00b0000, 0xe000007a, 0x90005800, @@ -10302,7 +10387,7 @@ UINT32 FirmwareKB[] = { 0x34000000, 0x34000000, 0x34000000, - 0xfbffeb11, + 0xfbffeabc, 0xd00b0000, 0xe0000033, 0xd00b0000, @@ -10319,7 +10404,7 @@ UINT32 FirmwareKB[] = { 0x34000000, 0x34000000, 0x34000000, - 0xfbffeb2a, + 0xfbffead5, 0xd00b0000, 0xe0000022, 0xd00b0000, @@ -10328,40 +10413,40 @@ UINT32 FirmwareKB[] = { 0x34010000, 0xd0010000, 0x3401001e, - 0xfbffdd9d, + 0xfbffdd48, 0xd00b0000, 0xe0000046, 0x90005800, 0x34010000, 0xd0010000, 0x3401001e, - 0xfbffddc3, + 0xfbffdd6e, 0xd00b0000, 0xe000003f, 0x78010003, - 0x38218c00, + 0x38219008, 0x402100ab, 0x5c20003b, 0x34010001, 0x33010174, - 0xf8002126, + 0xf80021c9, 0xe0000037, 0x78010003, - 0x38218c00, + 0x38219008, 0x402100ab, 0x5c200033, - 0xf8002157, + 0xf80021fa, 0xe0000031, - 0xf8000a75, + 0xf8000aa7, 0xe000002f, - 0xf8000a8d, + 0xf8000abf, 0x34030000, 0xe000002d, 0x90005800, 0x34010000, 0xd0010000, 0xb9800800, - 0xf8001b46, + 0xf8001be9, 0x5c200005, 0x7801c210, 0x3821003c, @@ -10372,20 +10457,20 @@ UINT32 FirmwareKB[] = { 0x90005800, 0x34010000, 0xd0010000, - 0xf80019d2, + 0xf8001a75, 0xd00b0000, 0xe000001a, 0x90005800, 0x34010000, 0xd0010000, - 0xf80019da, + 0xf8001a7d, 0xd00b0000, 0xe0000014, - 0xf80032ac, + 0xf800334f, 0xe0000012, - 0xf8001be9, + 0xf8001c8c, 0x34010000, - 0xfbffe0cd, + 0xfbffe078, 0xe000000e, 0x7801c00c, 0x38210000, @@ -10393,10 +10478,10 @@ UINT32 FirmwareKB[] = { 0x20210002, 0x5c200009, 0x34010001, - 0xfbffe0c5, - 0xf8001c57, + 0xfbffe070, + 0xf8001cfa, 0xe0000005, - 0xf8001d07, + 0xf8001daa, 0xe0000003, 0x340300fe, 0xe0000002, @@ -10470,7 +10555,7 @@ UINT32 FirmwareKB[] = { 0xe000002e, 0x430307b0, 0x78020003, - 0x38428b20, + 0x38428f28, 0xb0601800, 0x3c610002, 0x28420000, @@ -10557,14 +10642,14 @@ UINT32 FirmwareKB[] = { 0xd00c0000, 0xe0000025, 0x204100ff, - 0xf8000934, + 0xf800095a, 0xe0000022, - 0xf8000952, + 0xf8000978, 0xe0000020, 0x204100ff, - 0xf8000969, + 0xf800099b, 0xe000001d, - 0xf8000987, + 0xf80009b9, 0xe000001b, 0x90006000, 0x34010000, @@ -10575,13 +10660,13 @@ UINT32 FirmwareKB[] = { 0x3401005d, 0xb9601000, 0x34030001, - 0xfbffe8cf, + 0xfbffe87a, 0x330b092c, 0xe000000b, 0x34020000, 0x3401005d, 0xb8401800, - 0xfbffe8c9, + 0xfbffe874, 0x44200004, 0x34010000, 0x3301092b, @@ -10626,7 +10711,7 @@ UINT32 FirmwareKB[] = { 0xb42c0800, 0x3c210002, 0xb8601000, - 0x38428fa8, + 0x384293b0, 0xb4225800, 0x90002000, 0x34010000, @@ -10636,7 +10721,7 @@ UINT32 FirmwareKB[] = { 0xd0040000, 0xe000003a, 0x5d800007, - 0x38638fa8, + 0x386393b0, 0x40610015, 0x7c210001, 0x5c20000d, @@ -10645,7 +10730,7 @@ UINT32 FirmwareKB[] = { 0x7d810001, 0x5c200009, 0x78010003, - 0x38218fa8, + 0x382193b0, 0x40210009, 0x7c210001, 0x5c200004, @@ -10662,10 +10747,10 @@ UINT32 FirmwareKB[] = { 0x3d820002, 0x44200004, 0x78010003, - 0x38217dcc, + 0x382181ac, 0xe0000003, 0x78010003, - 0x38217da4, + 0x38218184, 0xb4410800, 0x28230000, 0xb8c01000, @@ -10676,7 +10761,7 @@ UINT32 FirmwareKB[] = { 0x44600013, 0x78010003, 0x3d820002, - 0x38217d7c, + 0x3821815c, 0xb4411000, 0x28410000, 0x34020000, @@ -10686,11 +10771,11 @@ UINT32 FirmwareKB[] = { 0x31620009, 0x5c220007, 0x78020003, - 0x38428e70, + 0x38429278, 0x28410000, 0x44200003, 0xb8400800, - 0xf800210c, + 0xf80021af, 0x34010000, 0x2b8b000c, 0x2b8c0008, @@ -10738,7 +10823,7 @@ UINT32 FirmwareKB[] = { 0x38210134, 0x206300ff, 0x34020100, - 0xfbffe8e7, + 0xfbffe892, 0x43020744, 0x7803c020, 0x38630134, @@ -10807,10 +10892,10 @@ UINT32 FirmwareKB[] = { 0x38210054, 0x28230000, 0x78010003, - 0x38218e70, + 0x38219278, 0xb8601000, 0x5c60fff5, - 0xf80020cb, + 0xf800216e, 0xe3fffff3, 0x7804c020, 0x38840090, @@ -10833,10 +10918,10 @@ UINT32 FirmwareKB[] = { 0x38210054, 0x28230000, 0x78010003, - 0x38218e70, + 0x38219278, 0xb8601000, 0x5c600002, - 0xf80020b1, + 0xf8002154, 0xb9600800, 0x38210094, 0x28210000, @@ -10848,7 +10933,7 @@ UINT32 FirmwareKB[] = { 0x34050000, 0x78020003, 0x202600ff, - 0x38428c00, + 0x38429008, 0xb8a01800, 0x34630001, 0x404100a0, @@ -10934,7 +11019,7 @@ UINT32 FirmwareKB[] = { 0x78020003, 0x78010002, 0x38214a68, - 0x38428b24, + 0x38428f2c, 0x58410040, 0x37010758, 0x3404000b, @@ -10944,11 +11029,11 @@ UINT32 FirmwareKB[] = { 0x34210001, 0x4c82fffc, 0x78010003, - 0x38218ba8, + 0x38218fb0, 0x30220010, 0x30220029, 0x3302076f, - 0xe000003c, + 0xe0000044, 0x34010000, 0x0f01073e, 0x43010765, @@ -10974,7 +11059,7 @@ UINT32 FirmwareKB[] = { 0x34630002, 0x44c0fff4, 0x7ce10000, - 0x44200022, + 0x4420002a, 0x2f02073e, 0x2f01073c, 0x44220007, @@ -10986,7 +11071,7 @@ UINT32 FirmwareKB[] = { 0x0f01073c, 0x4301082c, 0x7c210001, - 0x5c200014, + 0x5c20001c, 0x340b0000, 0x330b082c, 0x2f01073e, @@ -10995,17 +11080,25 @@ UINT32 FirmwareKB[] = { 0xfbffff7c, 0x43010774, 0x7c210001, - 0x5c2b000b, + 0x5c2b0013, 0x7801c201, 0x330b0774, 0x3821c588, - 0xf8000c80, + 0xf8000cf8, 0x3402fffc, 0xa0221000, 0x7801c201, 0x3821c588, 0x38420002, - 0xf8000c60, + 0xf8000cd8, + 0x7801c201, + 0x3821c52c, + 0xf8000cef, + 0x78020003, + 0x38428ed0, + 0x6c230000, + 0x5841003c, + 0x4460fff9, 0x34010001, 0x3301076f, 0x34010000, @@ -11020,8 +11113,8 @@ UINT32 FirmwareKB[] = { 0x5b9d0004, 0x78020003, 0x78010002, - 0x38428b24, - 0x3821a9b4, + 0x38428f2c, + 0x3821ab08, 0x58410040, 0x34020001, 0x78010003, @@ -11029,7 +11122,7 @@ UINT32 FirmwareKB[] = { 0x3821f820, 0x28230000, 0x78020003, - 0x38428ba8, + 0x38428fb0, 0x780100ff, 0x38210000, 0xa0611800, @@ -11038,7 +11131,7 @@ UINT32 FirmwareKB[] = { 0x30430010, 0x30430029, 0x3821c57c, - 0xf8000c59, + 0xf8000cc9, 0x202100ff, 0x78020003, 0x0f010740, @@ -11064,23 +11157,23 @@ UINT32 FirmwareKB[] = { 0xb8205800, 0x7801c201, 0x3821c574, - 0xf8000c3f, + 0xf8000caf, 0x78040003, 0xb8801000, - 0x38428acc, + 0x38428ed0, 0x58410038, 0x7d6b0000, 0x78010003, 0x78050003, 0x5d600006, - 0x38218c00, + 0x38219008, 0x4023000c, 0xe0000005, 0x40830008, 0xe0000022, - 0x38218c00, + 0x38219008, 0x40230011, - 0x38848acc, + 0x38848ed0, 0x28810038, 0x38a5fe14, 0x34060000, @@ -11091,7 +11184,7 @@ UINT32 FirmwareKB[] = { 0x20210080, 0xb8221000, 0x58a20000, - 0x38848c00, + 0x38849008, 0x34c60001, 0x408500a0, 0x68c70004, @@ -11177,7 +11270,7 @@ UINT32 FirmwareKB[] = { 0x5b8b0008, 0x5b9d0004, 0x78010003, - 0x38218b88, + 0x38218f90, 0x282b0000, 0xfbfffff7, 0x096b0492, @@ -11214,11 +11307,11 @@ UINT32 FirmwareKB[] = { 0xb8c06800, 0xfbffffd9, 0x78030003, - 0x38638c00, + 0x38639008, 0xb8209800, 0x40620017, 0x78010003, - 0x382185e0, + 0x382189e4, 0xb4411000, 0x10410000, 0x40630015, @@ -11319,7 +11412,7 @@ UINT32 FirmwareKB[] = { 0x88431000, 0x34030064, 0x8c431000, - 0xf800166b, + 0xf8001706, 0x2b9d0004, 0x379c000c, 0xc3a00000, @@ -11346,7 +11439,7 @@ UINT32 FirmwareKB[] = { 0x21810004, 0x5c2b000f, 0x78010003, - 0x38218b88, + 0x38218f90, 0x2822000c, 0x2b040274, 0x28210008, @@ -11362,7 +11455,7 @@ UINT32 FirmwareKB[] = { 0x21810002, 0x5c20000a, 0x78010003, - 0x38218b88, + 0x38218f90, 0x28210018, 0x2b020278, 0x00210003, @@ -11373,7 +11466,7 @@ UINT32 FirmwareKB[] = { 0x21810008, 0x5c20000a, 0x78010003, - 0x38218b88, + 0x38218f90, 0x28210010, 0x2b02027c, 0x00210003, @@ -11384,7 +11477,7 @@ UINT32 FirmwareKB[] = { 0x21810001, 0x5c20000a, 0x78010003, - 0x38218b88, + 0x38218f90, 0x28210014, 0x2b020284, 0x00210003, @@ -11394,7 +11487,7 @@ UINT32 FirmwareKB[] = { 0xb5625800, 0x430107b0, 0x78020003, - 0x38428b88, + 0x38428f90, 0xb0200800, 0x3c210002, 0x28420004, @@ -11418,15 +11511,15 @@ UINT32 FirmwareKB[] = { 0xb58c6800, 0x78010003, 0x5d800004, - 0x38218c00, + 0x38219008, 0x2c21009c, 0xe0000003, - 0x38218c00, + 0x38219008, 0x2c21009e, 0x5b81001c, 0xb9800800, 0xfbfffe91, - 0xfbffdd52, + 0xfbffdcf5, 0x3c21000f, 0x34020fa0, 0x8c222800, @@ -11489,7 +11582,7 @@ UINT32 FirmwareKB[] = { 0x5b82000c, 0x2b0202ac, 0x37810008, - 0xf80015c1, + 0xf800165c, 0x00210008, 0x2b9d0004, 0x379c000c, @@ -11521,7 +11614,7 @@ UINT32 FirmwareKB[] = { 0x34010000, 0xd0010000, 0x78010003, - 0x38218ba8, + 0x38218fb0, 0x34020000, 0x78040003, 0x30220005, @@ -11532,7 +11625,7 @@ UINT32 FirmwareKB[] = { 0x38217fff, 0xa0611800, 0x78020003, - 0x38428b24, + 0x38428f2c, 0x34010000, 0x58410014, 0x58830000, @@ -11562,13 +11655,13 @@ UINT32 FirmwareKB[] = { 0x780f0003, 0x3dae0002, 0xb9e00800, - 0x38217cec, + 0x382180cc, 0xb5c10800, 0x40210001, 0x340c0000, 0x51810014, 0xb9e05800, - 0x396b7cec, + 0x396b80cc, 0xb5cb5800, 0x41610002, 0x41620000, @@ -11582,7 +11675,7 @@ UINT32 FirmwareKB[] = { 0x38210001, 0x58610000, 0x34010001, - 0xfbffdbd2, + 0xfbffdb75, 0x41610001, 0x358c0001, 0xe3ffffed, @@ -11610,7 +11703,7 @@ UINT32 FirmwareKB[] = { 0x38420d50, 0xb9a00800, 0x58440000, - 0x38217cec, + 0x382180cc, 0x4022008d, 0x7803c040, 0x38630d58, @@ -11621,7 +11714,7 @@ UINT32 FirmwareKB[] = { 0xb8806000, 0x5082001d, 0xb9a05800, - 0x396b7cec, + 0x396b80cc, 0x4162008e, 0x4161008c, 0x3d840016, @@ -11643,7 +11736,7 @@ UINT32 FirmwareKB[] = { 0x38210d54, 0x58220000, 0x34010001, - 0xfbffdb95, + 0xfbffdb38, 0x4161008d, 0x358c0001, 0x51810002, @@ -11659,13 +11752,13 @@ UINT32 FirmwareKB[] = { 0x780f0003, 0x3dae0002, 0xb9e00800, - 0x38217cec, + 0x382180cc, 0xb5c10800, 0x40210021, 0x340c0000, 0x51810014, 0xb9e05800, - 0x396b7cec, + 0x396b80cc, 0xb5cb5800, 0x41610022, 0x41620020, @@ -11679,7 +11772,7 @@ UINT32 FirmwareKB[] = { 0x38210001, 0x58610000, 0x34010001, - 0xfbffdb71, + 0xfbffdb14, 0x41610021, 0x358c0001, 0xe3ffffed, @@ -11943,14 +12036,14 @@ UINT32 FirmwareKB[] = { 0x90006000, 0xd00d0000, 0x780b0003, - 0x396b8c00, + 0x396b9008, 0x41610080, 0x39ceffff, - 0xfbffdb4a, + 0xfbffdaed, 0x00210002, 0x0f01022a, 0x41610081, - 0xfbffdb46, + 0xfbffdae9, 0x78020003, 0x3842f900, 0x28480000, @@ -11966,7 +12059,7 @@ UINT32 FirmwareKB[] = { 0x78060003, 0x2084ffff, 0x28210000, - 0x38c68ba8, + 0x38c68fb0, 0x34090001, 0xa02e0800, 0x00210010, @@ -11975,10 +12068,10 @@ UINT32 FirmwareKB[] = { 0x7805ffff, 0x38a57fff, 0x78030003, - 0x38638b24, + 0x38638f2c, 0x8c882000, 0x78020002, - 0x3842b2a4, + 0x3842b418, 0x88240800, 0x5b0102ac, 0x330a02b4, @@ -12241,8 +12334,8 @@ UINT32 FirmwareKB[] = { 0x28c30004, 0x78020003, 0x78010002, - 0x3821c154, - 0x38428b24, + 0x3821c2c8, + 0x38428f2c, 0x0f030752, 0x58410044, 0x40c1000d, @@ -12254,7 +12347,7 @@ UINT32 FirmwareKB[] = { 0x430106ac, 0x7c210004, 0x5c200033, - 0xfbffdb4c, + 0xfbffdaef, 0xb0200800, 0x3c220003, 0x7805c020, @@ -12298,15 +12391,15 @@ UINT32 FirmwareKB[] = { 0x28c30004, 0x78020003, 0x78010002, - 0x38428b24, - 0x3821c154, + 0x38428f2c, + 0x3821c2c8, 0x0f030752, 0x58410044, 0x34030001, 0xe0000018, 0x430206ae, 0x78010003, - 0x38218ba8, + 0x38218fb0, 0x330206ac, 0x34020000, 0x7804c020, @@ -12316,7 +12409,7 @@ UINT32 FirmwareKB[] = { 0x28830000, 0x78020003, 0x78010002, - 0x38428b24, + 0x38428f2c, 0x38214a68, 0x58410044, 0x430206ad, @@ -12357,7 +12450,7 @@ UINT32 FirmwareKB[] = { 0x5c20004d, 0x3c410002, 0x78020003, - 0x3842859c, + 0x384289a0, 0xb4220800, 0x28210000, 0xc0200000, @@ -12420,17 +12513,17 @@ UINT32 FirmwareKB[] = { 0x34010001, 0x330106f8, 0x78010003, - 0x38218ba8, + 0x38218fb0, 0x34040001, 0x78030003, 0x78020002, - 0x38638b24, - 0x3842bd64, + 0x38638f2c, + 0x3842bed8, 0x3024002a, 0x30240011, 0x58620044, 0x34010020, - 0xfbffd567, + 0xfbffd50a, 0x2b9d0004, 0x379c0004, 0xc3a00000, @@ -12457,7 +12550,7 @@ UINT32 FirmwareKB[] = { 0x78050003, 0x28810000, 0xa0621800, - 0x38a598d8, + 0x38a59ce0, 0x2021000f, 0x3c210004, 0xb8611800, @@ -12466,15 +12559,15 @@ UINT32 FirmwareKB[] = { 0x5b0106a4, 0x28a10038, 0x5b0106a8, - 0xfbffd59f, + 0xfbffd542, 0x3401000e, - 0xfbffd541, + 0xfbffd4e4, 0x34010012, - 0xfbffd53f, + 0xfbffd4e2, 0x34010006, - 0xfbffd53d, + 0xfbffd4e0, 0x3401000a, - 0xfbffd53b, + 0xfbffd4de, 0xe0000054, 0x370c06b0, 0x2f01073c, @@ -12484,7 +12577,7 @@ UINT32 FirmwareKB[] = { 0x43010746, 0x202b00ff, 0x5d60004a, - 0xfbffda66, + 0xfbffda09, 0x780dc020, 0xb9a02800, 0x330106e9, @@ -12513,13 +12606,13 @@ UINT32 FirmwareKB[] = { 0x4420ffff, 0x29820008, 0x78010003, - 0x38218b88, + 0x38218f90, 0x58220000, 0x4181000f, 0x330106f2, 0x430106f2, 0x202100ff, - 0xfbffdb6c, + 0xfbffdb0f, 0x41830010, 0x7804c020, 0x38840088, @@ -12555,13 +12648,13 @@ UINT32 FirmwareKB[] = { 0x3c420004, 0xb8822000, 0x58a40000, - 0xfbffd55a, + 0xfbffd4fd, 0xe0000003, 0x34010001, 0xe0000018, 0x430206ae, 0x78010003, - 0x38218ba8, + 0x38218fb0, 0x330206ac, 0x34020000, 0x7804c020, @@ -12571,7 +12664,7 @@ UINT32 FirmwareKB[] = { 0x28830000, 0x78020003, 0x78010002, - 0x38428b24, + 0x38428f2c, 0x38214a68, 0x58410044, 0x430206ad, @@ -12596,9 +12689,9 @@ UINT32 FirmwareKB[] = { 0x78070003, 0x78060002, 0x78040003, - 0x38848ba8, - 0x38e78b24, - 0x38c6bd64, + 0x38848fb0, + 0x38e78f2c, + 0x38c6bed8, 0x34050001, 0x34010020, 0x44400002, @@ -12606,7 +12699,7 @@ UINT32 FirmwareKB[] = { 0x58e60044, 0x3085002a, 0x30850011, - 0xfbffd4b7, + 0xfbffd45a, 0x3401000a, 0xfbfffe56, 0x2b9d0004, @@ -12620,9 +12713,9 @@ UINT32 FirmwareKB[] = { 0x78070003, 0x78060002, 0x78040003, - 0x38848ba8, - 0x38e78b24, - 0x38c6bd64, + 0x38848fb0, + 0x38e78f2c, + 0x38c6bed8, 0x34050001, 0x34010020, 0x44400002, @@ -12630,7 +12723,7 @@ UINT32 FirmwareKB[] = { 0x58e60044, 0x3085002a, 0x30850011, - 0xfbffd49f, + 0xfbffd442, 0x34010004, 0xfbfffe3e, 0x2b9d0004, @@ -12725,7 +12818,7 @@ UINT32 FirmwareKB[] = { 0x33030826, 0x2f01073c, 0x2021ffff, - 0xfbfff8b7, + 0xfbfff8af, 0x2b9d0004, 0x379c0004, 0xc3a00000, @@ -12740,12 +12833,12 @@ UINT32 FirmwareKB[] = { 0xb9800800, 0x38420020, 0x59620000, - 0xf8001a95, + 0xf8001b30, 0x29620000, 0xb9800800, 0x38420001, 0x59620000, - 0xf8001a90, + 0xf8001b2b, 0x34010000, 0x33010926, 0x2b8b000c, @@ -12757,8 +12850,22 @@ UINT32 FirmwareKB[] = { 0x5b8b000c, 0x5b8c0008, 0x5b9d0004, - 0x43010927, - 0x5c20000b, + 0x780cc050, + 0xb9800800, + 0x38210170, + 0x28210000, + 0x780b0200, + 0xb9601000, + 0x38420000, + 0xa0220800, + 0x00210019, + 0x44200007, + 0x34010014, + 0xf8001b14, + 0xb9800800, + 0x38210170, + 0x28210000, + 0xe3fffff6, 0x7804c050, 0x38840170, 0x28830000, @@ -12767,10 +12874,10 @@ UINT32 FirmwareKB[] = { 0x78022000, 0xa0611800, 0x38420000, - 0xb8621800, - 0x58830000, 0x780cc050, + 0xb8621800, 0xb9800800, + 0x58830000, 0x38210194, 0x28210000, 0x780b0080, @@ -12782,7 +12889,7 @@ UINT32 FirmwareKB[] = { 0x64210001, 0x5c200007, 0x34010014, - 0xf8001a6b, + 0xf8001af8, 0xb9800800, 0x38210194, 0x28210000, @@ -12794,67 +12901,81 @@ UINT32 FirmwareKB[] = { 0x2b9d0004, 0x379c000c, 0xc3a00000, - 0x379cfff4, - 0x5b8b000c, - 0x5b8c0008, + 0x379cfff0, + 0x5b8b0010, + 0x5b8c000c, + 0x5b8d0008, 0x5b9d0004, 0x43010928, - 0x780cc050, - 0xb9805800, 0x7c210001, - 0x396b0080, - 0x5c20002b, - 0x29620000, - 0x34010014, - 0x20420001, - 0x7c420001, - 0x5c40001d, - 0x43020927, - 0x7805c050, - 0x7804dfff, - 0x78032000, - 0x38a50170, - 0x3884ffff, - 0x38630000, - 0x5c400005, - 0x28a20000, - 0xa0441000, - 0xb8431000, - 0x58a20000, - 0x29620000, + 0x5c200023, + 0x780dc050, + 0xb9a02000, + 0x38840080, + 0x28820000, 0x3403fffe, - 0xa0431000, - 0x59620000, - 0xf8001a40, - 0x29620000, - 0x34010014, - 0x38420040, - 0x59620000, - 0xf8001a3b, - 0x29620000, - 0x3403ffbf, 0x34010014, 0xa0431000, - 0x59620000, - 0xf8001a35, - 0xfbffffac, - 0xb9801000, + 0x58820000, + 0xf8001adc, + 0x780cc050, + 0xb9800800, + 0x38210170, + 0x28210000, + 0x780b0200, + 0xb9601000, + 0x38420000, + 0xa0220800, + 0x00210019, + 0x44200007, + 0x34010014, + 0xf8001ad0, + 0xb9800800, + 0x38210170, + 0x28210000, + 0xe3fffff6, + 0xfbffffa8, + 0xb9a01000, 0x38420080, 0x28430000, 0x3404ffdf, 0x34010014, 0xa0641800, 0x58430000, - 0xf8001a2c, - 0x2b8b000c, - 0x2b8c0008, + 0xf8001ac3, + 0x2b8b0010, + 0x2b8c000c, + 0x2b8d0008, 0x2b9d0004, - 0x379c000c, + 0x379c0010, 0xc3a00000, - 0x379cfffc, + 0x379cfff0, + 0x5b8b0010, + 0x5b8c000c, + 0x5b8d0008, 0x5b9d0004, - 0x43010927, - 0x5c20000b, + 0x780bc050, + 0xb9600800, + 0x38210080, + 0x28210000, + 0x20210001, + 0x5c20001b, + 0x780dc050, + 0xb9a00800, + 0x38210170, + 0x28210000, + 0x780c0200, + 0xb9801000, + 0x38420000, + 0xa0220800, + 0x00210019, + 0x44200007, + 0x34010014, + 0xf8001aa6, + 0xb9a00800, + 0x38210170, + 0x28210000, + 0xe3fffff6, 0x7804c050, 0x38840170, 0x28830000, @@ -12868,14 +12989,13 @@ UINT32 FirmwareKB[] = { 0x7801c050, 0x38210194, 0x28220000, + 0x396b0080, 0x78010080, 0x38210000, 0xa0411000, 0x00420017, - 0x7801c050, 0x33020926, - 0x38210080, - 0x28220000, + 0x29620000, 0x43010918, 0x20420001, 0x7c210001, @@ -12905,13 +13025,16 @@ UINT32 FirmwareKB[] = { 0x7c410000, 0x33030924, 0x5c200005, - 0xfbffff50, + 0xfbffff35, 0xe0000003, 0x34010000, 0x33010924, 0x34010000, + 0x2b8b0010, + 0x2b8c000c, + 0x2b8d0008, 0x2b9d0004, - 0x379c0004, + 0x379c0010, 0xc3a00000, 0x202100ff, 0x90005000, @@ -12952,20 +13075,32 @@ UINT32 FirmwareKB[] = { 0x34010000, 0xd0010000, 0x3301091e, - 0xfbffff62, + 0xfbffff52, + 0x7804c050, + 0x388401c8, + 0x28810000, + 0x78030003, + 0x38638000, + 0xa0230800, + 0x0021000f, + 0x28820000, + 0x20210003, + 0x3c21000f, + 0x7805fffc, + 0x38a57fff, + 0xa0230800, + 0xa0451000, + 0xb8411000, 0x7803c050, + 0x58820000, 0x38630118, 0x28610000, 0x3402ffdf, - 0x7804c050, 0xa0220800, 0x58610000, - 0x388401c8, - 0x28820000, - 0x7801fffc, - 0x38217fff, - 0xa0411000, - 0x58820000, + 0x28810000, + 0xa0250800, + 0x58810000, 0xd00b0000, 0x2b8b0008, 0x2b9d0004, @@ -13010,7 +13145,7 @@ UINT32 FirmwareKB[] = { 0x34010000, 0xd0010000, 0x3301091d, - 0xfbffff28, + 0xfbffff0c, 0x7804c050, 0x388401c8, 0x28820000, @@ -13035,7 +13170,7 @@ UINT32 FirmwareKB[] = { 0x34020001, 0x78010003, 0x33020928, - 0x38218ba8, + 0x38218fb0, 0x78050003, 0x30220018, 0x30220031, @@ -13049,8 +13184,8 @@ UINT32 FirmwareKB[] = { 0x78030003, 0x78010002, 0xb8822000, - 0x38638b24, - 0x3821c7d8, + 0x38638f2c, + 0x3821c960, 0x58610060, 0x58a40000, 0xd0060000, @@ -13061,7 +13196,7 @@ UINT32 FirmwareKB[] = { 0x34020000, 0x78010003, 0x33020928, - 0x38218ba8, + 0x38218fb0, 0x78050003, 0x30220031, 0x30220018, @@ -13072,7 +13207,7 @@ UINT32 FirmwareKB[] = { 0x78030003, 0x78020002, 0xa0812000, - 0x38638b24, + 0x38638f2c, 0x38424a68, 0x58620060, 0x58a40000, @@ -13087,7 +13222,7 @@ UINT32 FirmwareKB[] = { 0x340c0000, 0x3d8b0002, 0x78010003, - 0x382185c0, + 0x382189c4, 0xb5610800, 0x28250000, 0x340400d0, @@ -13095,13 +13230,13 @@ UINT32 FirmwareKB[] = { 0x34010000, 0xb8201000, 0xb8201800, - 0xf8002af9, + 0xf8002b6a, 0x34010000, 0xb8201000, 0xb8201800, 0x340400d4, 0x3405000f, - 0xf8002b2a, + 0xf8002b9b, 0x358c0001, 0xb56d5800, 0x75820006, @@ -13122,7 +13257,7 @@ UINT32 FirmwareKB[] = { 0x340c0000, 0x3d8b0002, 0x78010003, - 0x382185c0, + 0x382189c4, 0xb5610800, 0x28250000, 0x340400d0, @@ -13130,7 +13265,7 @@ UINT32 FirmwareKB[] = { 0x34010000, 0xb8201000, 0xb8201800, - 0xf8002ad6, + 0xf8002b47, 0xb56d5800, 0x29650000, 0x34010000, @@ -13138,7 +13273,7 @@ UINT32 FirmwareKB[] = { 0xb8201800, 0x340400d4, 0x3406000f, - 0xf8002ace, + 0xf8002b3f, 0x358c0001, 0x75810006, 0x4420ffeb, @@ -13154,7 +13289,7 @@ UINT32 FirmwareKB[] = { 0x38210000, 0x28210010, 0x00210017, - 0xf80018f7, + 0xf8001968, 0x2b9d0004, 0x379c0004, 0xc3a00000, @@ -13814,48 +13949,61 @@ UINT32 FirmwareKB[] = { 0x2b8d0004, 0x379c000c, 0xc3a00000, - 0x379cffec, - 0x5b8b0014, - 0x5b8c0010, - 0x5b8d000c, - 0x5b8e0008, + 0x379cffe8, + 0x5b8b0018, + 0x5b8c0014, + 0x5b8d0010, + 0x5b8e000c, + 0x5b8f0008, 0x5b9d0004, - 0x780cc000, - 0x398c0000, - 0x298d0014, - 0x7802c00c, - 0x38420000, - 0x29810010, - 0x7805c050, - 0x38a50118, - 0x298b0000, - 0x7801fff7, - 0x3821ffff, - 0x284e0000, - 0xa1615800, - 0x7803ffdf, - 0x28a10000, - 0x7802ffef, + 0x780dc000, + 0x39ad0000, + 0x29ae0014, + 0x7801c00c, + 0x38210000, + 0x29a20010, + 0x7804c050, + 0x38840118, + 0x29ab0000, + 0x7806c050, + 0x38c601c8, + 0x282f0000, + 0x7805fffc, + 0x7802fff7, + 0x28810000, + 0x38a57fff, 0x3842ffff, 0x38210020, - 0x58a10000, - 0xa1625800, + 0x58810000, + 0x28810000, + 0xa1625800, + 0x7803ffef, + 0x38210040, + 0x58810000, + 0x28c10000, 0x3863ffff, - 0x7801f7ff, - 0x28a40000, + 0x7802ffdf, + 0xa0250800, + 0x58c10000, 0xa1635800, + 0x3842ffff, + 0x7801f7ff, + 0x28c40000, + 0xa1625800, 0x3821ffff, 0xa1615800, - 0x7802efff, + 0x7802ffe3, + 0x7803efff, 0x3842ffff, + 0x3863ffff, 0x7801fffe, - 0xa1625800, + 0xa0822000, + 0xa1635800, 0x3821ffff, - 0x38840040, + 0x58c40000, 0xa1615800, - 0x58a40000, - 0x598b0000, - 0xfbfffd3d, + 0x59ab0000, + 0xfbfffd30, 0x78010008, 0x38210000, 0x78020010, @@ -13865,30 +14013,52 @@ UINT32 FirmwareKB[] = { 0x78010020, 0x38210000, 0x78020800, - 0xb9615800, 0x38420000, + 0xb9615800, + 0x78031000, 0xb9625800, - 0x01ad001e, - 0x78011000, + 0x38630000, + 0x78010001, + 0xb9635800, 0x38210000, - 0x78020001, 0xb9615800, - 0x38420000, - 0x21ad0001, - 0x01ce0004, - 0xb9625800, - 0x65ad0000, - 0x598b0000, + 0x780c0003, + 0x59ab0000, + 0x398cf900, + 0x29810000, + 0x340b0064, + 0x01ce001e, + 0x082103e8, 0x21ce0001, - 0x5da00003, - 0x5dc00002, - 0xfbffff04, - 0x2b8b0014, - 0x2b8c0010, - 0x2b8d000c, - 0x2b8e0008, + 0x01ef0004, + 0x34210032, + 0x8c2b0800, + 0x65ce0000, + 0x21ef0001, + 0xf800167e, + 0x2b210e60, + 0x38210002, + 0x5b210e60, + 0x29820000, + 0x3c410002, + 0xb4220800, + 0x34210032, + 0x8c2b0800, + 0xf8001675, + 0x2b220e60, + 0x3401fffd, + 0xa0411000, + 0x5b220e60, + 0x5dc00003, + 0x5de00002, + 0xfbfffee2, + 0x2b8b0018, + 0x2b8c0014, + 0x2b8d0010, + 0x2b8e000c, + 0x2b8f0008, 0x2b9d0004, - 0x379c0014, + 0x379c0018, 0xc3a00000, 0x379cfff8, 0x5b8b0008, @@ -13903,9 +14073,9 @@ UINT32 FirmwareKB[] = { 0x5b212f4c, 0x34010004, 0x5b2120ac, - 0xf8000d84, - 0xfbffffa6, - 0xf8000dbf, + 0xf8000dd2, + 0xfbffff83, + 0xf8000e0d, 0x2b212f4c, 0x3402fffe, 0xa0220800, @@ -13920,93 +14090,128 @@ UINT32 FirmwareKB[] = { 0x2b9d0004, 0x379c0008, 0xc3a00000, - 0x379cffec, - 0x5b8b0014, - 0x5b8c0010, - 0x5b8d000c, - 0x5b8e0008, + 0x379cffe8, + 0x5b8b0018, + 0x5b8c0014, + 0x5b8d0010, + 0x5b8e000c, + 0x5b8f0008, 0x5b9d0004, - 0x780cc000, - 0x398c0000, - 0x29820010, - 0x7806c050, - 0x38c60118, - 0x298b0000, + 0x780dc000, + 0x39ad0000, + 0x29a20010, + 0x7803c050, + 0x38630118, + 0x29ac0000, 0x7802c00c, 0x38420000, - 0x284e0000, - 0x7803ffef, + 0x284f0000, + 0x7808c050, + 0x7807fff7, + 0x28620000, + 0x390801c8, + 0x38e7ffff, + 0x38420020, + 0x58620000, + 0x28620000, + 0x7805ffef, + 0xa1876000, + 0x38420040, + 0x58620000, + 0x29060000, + 0x38a5ffff, + 0x7803ffdf, + 0xa1856000, 0x3863ffff, - 0x7802fff7, - 0x3842ffff, - 0x28c50000, - 0xa1625800, - 0x7804ffdf, - 0xa1635800, - 0x3884ffff, + 0x7804fffc, 0x7802f7ff, - 0xa1645800, + 0x38847fff, + 0xa1836000, 0x3842ffff, - 0x38a50020, - 0xa1625800, + 0xa0c43000, + 0xa1826000, 0x7803efff, - 0x58c50000, + 0x59060000, 0x3863ffff, 0x7802fffe, - 0x28c40000, - 0xa1635800, + 0x29050000, + 0xa1836000, 0x3842ffff, - 0xa1625800, - 0x3402ffdf, - 0x7803fffd, - 0xa1625800, - 0x38840040, + 0xa1826000, + 0x7803ffe3, 0x3863ffff, - 0xa1635800, - 0x58c40000, - 0x598b0000, - 0x202d00ff, - 0xfbfffcce, - 0x396b0020, - 0x598b0000, - 0x45a00002, - 0xfbfffd15, + 0x3402ffdf, + 0x7804fffd, + 0xa0a32800, + 0xa1826000, + 0x3884ffff, + 0xa1846000, + 0x59050000, + 0x59ac0000, + 0x202e00ff, + 0xfbfffc9e, + 0x398c0020, + 0x59ac0000, + 0x45c00002, + 0xfbfffce5, 0x78010008, 0x38210000, 0x78020010, - 0xb9615800, + 0xb9816000, 0x38420000, - 0xb9625800, + 0xb9826000, 0x78010020, 0x38210000, 0x78020800, - 0xb9615800, 0x38420000, + 0xb9816000, 0x78031000, - 0xb9625800, 0x38630000, + 0xb9826000, 0x78010001, - 0xb9635800, + 0xb9836000, 0x38210000, - 0x01c20004, - 0xb9615800, - 0x7da30000, - 0xa4401000, + 0xb9816000, 0x78010002, - 0xa0431000, 0x38210000, - 0x396b8000, - 0xb9615800, - 0x64420000, - 0x598b0000, - 0x5c400002, - 0xfbfffe8e, - 0x2b8b0014, - 0x2b8c0010, - 0x2b8d000c, - 0x2b8e0008, + 0x398c8000, + 0xb9816000, + 0x780b0003, + 0x59ac0000, + 0x396bf900, + 0x29610000, + 0x340c0064, + 0x082103e8, + 0x34210032, + 0x8c2c0800, + 0xf80015e9, + 0x2b210e60, + 0x38210002, + 0x5b210e60, + 0x29620000, + 0x3c410002, + 0xb4220800, + 0x34210032, + 0x8c2c0800, + 0xf80015e0, + 0x01e10004, + 0x7dc20000, + 0x2b230e60, + 0xa4200800, + 0xa0220800, + 0x3402fffd, + 0xa0621800, + 0x64210000, + 0x5b230e60, + 0x5c200002, + 0xfbfffe49, + 0x2b8b0018, + 0x2b8c0014, + 0x2b8d0010, + 0x2b8e000c, + 0x2b8f0008, 0x2b9d0004, - 0x379c0014, + 0x379c0018, 0xc3a00000, 0x379cffc8, 0x5b8b0018, @@ -14039,20 +14244,20 @@ UINT32 FirmwareKB[] = { 0x5b212f4c, 0x34010004, 0x5b2120ac, - 0xf8000cfc, + 0xf8000d27, 0xb9c00800, - 0xfbfffc3d, + 0xfbfffbf7, 0x21810001, 0x64220000, 0x5dab0005, 0x5c400002, 0x34010001, - 0xfbffff81, + 0xfbffff5e, 0xe0000002, - 0xfbffff15, - 0xf8000d2e, + 0xfbfffecf, + 0xf8000d59, 0xb9c00800, - 0xfbfffc55, + 0xfbfffc0f, 0x2b212f4c, 0x3402fffe, 0xb9e01800, @@ -14090,7 +14295,7 @@ UINT32 FirmwareKB[] = { 0x4c400002, 0xe0000002, 0xb8600800, - 0xfbffff56, + 0xfbffff33, 0xb9600800, 0x3821302c, 0x28220000, @@ -14107,8 +14312,8 @@ UINT32 FirmwareKB[] = { 0x78030003, 0x78040003, 0x58a20004, - 0x38638dc8, - 0x38848dcc, + 0x386391d0, + 0x388491d4, 0x58610000, 0x58820000, 0xc3a00000, @@ -14145,8 +14350,8 @@ UINT32 FirmwareKB[] = { 0x50a20010, 0x78070003, 0x78060003, - 0x38e78dcc, - 0x38c68dc8, + 0x38e791d4, + 0x38c691d0, 0xb8201800, 0x28610000, 0x34a50001, @@ -14287,7 +14492,7 @@ UINT32 FirmwareKB[] = { 0x780b0003, 0x00230016, 0xb9601000, - 0x38428acc, + 0x38428ed0, 0x58410038, 0x20630001, 0x5c60000a, @@ -14296,12 +14501,12 @@ UINT32 FirmwareKB[] = { 0xfbffffa2, 0x00220016, 0xb9601800, - 0x38638acc, + 0x38638ed0, 0x58610038, 0x20420001, 0x4440fff8, 0x78040003, - 0x38848acc, + 0x38848ed0, 0x28820034, 0x21810003, 0x3403ff3f, @@ -14336,7 +14541,7 @@ UINT32 FirmwareKB[] = { 0x780b0003, 0x00230015, 0xb9601000, - 0x38428acc, + 0x38428ed0, 0x58410038, 0x20630002, 0x4460000a, @@ -14345,12 +14550,12 @@ UINT32 FirmwareKB[] = { 0xfbffff71, 0x00220015, 0xb9601800, - 0x38638acc, + 0x38638ed0, 0x58610038, 0x20420002, 0x5c40fff8, 0x78040003, - 0x38848acc, + 0x38848ed0, 0x28820034, 0x21810003, 0x3403ffe7, @@ -14380,13 +14585,13 @@ UINT32 FirmwareKB[] = { 0xb8601000, 0x33030778, 0x38210130, - 0xfbffdaad, + 0xfbffd9e0, 0x780ec020, 0xb9c00800, 0x38210004, 0x282f0000, 0x780b0003, - 0x396b8acc, + 0x396b8ed0, 0x7801c201, 0x3821c574, 0xfbffff42, @@ -14425,7 +14630,7 @@ UINT32 FirmwareKB[] = { 0x34020001, 0xb8801800, 0x33040778, - 0xfbffda80, + 0xfbffd9b3, 0x2b8b0018, 0x2b8c0014, 0x2b8d0010, @@ -14440,7 +14645,7 @@ UINT32 FirmwareKB[] = { 0x5b9d0004, 0x780c0003, 0xb9800800, - 0x38218b1c, + 0x38218f24, 0x43030779, 0x28220000, 0x206400ff, @@ -14451,7 +14656,7 @@ UINT32 FirmwareKB[] = { 0x44400002, 0x34030000, 0xb9800800, - 0x38218b1c, + 0x38218f24, 0x28210000, 0x40210006, 0x5c200004, @@ -14461,7 +14666,7 @@ UINT32 FirmwareKB[] = { 0x7c610000, 0x4420002f, 0xb9801000, - 0x38428b1c, + 0x38428f24, 0x28410000, 0x40210007, 0x3301077c, @@ -14475,12 +14680,12 @@ UINT32 FirmwareKB[] = { 0x40210004, 0x4420000b, 0x78030003, - 0x38638acc, - 0x2862003c, + 0x38638ed0, + 0x28620040, 0x3404ffdf, 0x7801c201, 0xa0441000, - 0x5862003c, + 0x58620040, 0x3821c588, 0xfbfffecb, 0x330b0782, @@ -14491,7 +14696,7 @@ UINT32 FirmwareKB[] = { 0x43010787, 0x202b00ff, 0x5d600046, - 0x398c8b1c, + 0x398c8f24, 0x29810000, 0x40220001, 0x40210000, @@ -14499,8 +14704,8 @@ UINT32 FirmwareKB[] = { 0x78020003, 0x78010002, 0x330b0784, - 0x38428b24, - 0x3821e2a4, + 0x38428f2c, + 0x3821e5d8, 0x58410028, 0x330b0783, 0x330b0786, @@ -14513,7 +14718,7 @@ UINT32 FirmwareKB[] = { 0x5d60001b, 0x4301077b, 0x5c200009, - 0x398c8b1c, + 0x398c8f24, 0x29810000, 0x40220003, 0x40210002, @@ -14521,7 +14726,7 @@ UINT32 FirmwareKB[] = { 0x34010001, 0x33010784, 0xe0000007, - 0x398c8b1c, + 0x398c8f24, 0x29810000, 0x40220001, 0x40210000, @@ -14529,8 +14734,8 @@ UINT32 FirmwareKB[] = { 0x330b0784, 0x78010003, 0x78020002, - 0x38218b24, - 0x3842e2a4, + 0x38218f2c, + 0x3842e5d8, 0x58220028, 0x34010000, 0x33010783, @@ -14545,17 +14750,17 @@ UINT32 FirmwareKB[] = { 0x4301077c, 0x202b00ff, 0x5d600010, - 0x398c8b1c, + 0x398c8f24, 0x29810000, 0x40210004, 0x4420000b, 0x78030003, - 0x38638acc, - 0x2862003c, + 0x38638ed0, + 0x28620040, 0x7801c201, 0x3821c588, 0x38420020, - 0x5862003c, + 0x58620040, 0xfbfffe81, 0x34010001, 0x33010782, @@ -14580,7 +14785,7 @@ UINT32 FirmwareKB[] = { 0x780c0003, 0x780b0002, 0x4420000b, - 0x38428b1c, + 0x38428f24, 0x28410000, 0x40220001, 0x40210000, @@ -14590,7 +14795,7 @@ UINT32 FirmwareKB[] = { 0x34010001, 0x33010786, 0xe0000009, - 0x38428b1c, + 0x38428f24, 0x28410000, 0x40220003, 0x40210002, @@ -14598,15 +14803,15 @@ UINT32 FirmwareKB[] = { 0x34010001, 0x33010784, 0x33010788, - 0x398c8b24, - 0x396be094, + 0x398c8f2c, + 0x396be3c8, 0x598b0028, 0x34010005, 0x33010783, 0xe0000055, 0x78060003, 0xb8c00800, - 0x38218b1c, + 0x38218f24, 0x43030779, 0x28220000, 0x206500ff, @@ -14617,7 +14822,7 @@ UINT32 FirmwareKB[] = { 0x44400002, 0xb8801800, 0xb8c00800, - 0x38218b1c, + 0x38218f24, 0x28210000, 0x40210006, 0x5c200005, @@ -14627,7 +14832,7 @@ UINT32 FirmwareKB[] = { 0xe0000022, 0x44600021, 0xb8c06000, - 0x398c8b1c, + 0x398c8f24, 0x29810000, 0x40210007, 0x3301077c, @@ -14641,12 +14846,12 @@ UINT32 FirmwareKB[] = { 0x40210004, 0x4420000b, 0x78030003, - 0x38638acc, - 0x2862003c, + 0x38638ed0, + 0x28620040, 0x3404ffdf, 0x7801c201, 0xa0441000, - 0x5862003c, + 0x58620040, 0x3821c588, 0xfbfffe25, 0x330b0782, @@ -14668,17 +14873,17 @@ UINT32 FirmwareKB[] = { 0x5c200017, 0xb8c05800, 0x3301077b, - 0x396b8b1c, + 0x396b8f24, 0x29610000, 0x40210004, 0x4420000b, 0x78030003, - 0x38638acc, - 0x2862003c, + 0x38638ed0, + 0x28620040, 0x7801c201, 0x3821c588, 0x38420020, - 0x5862003c, + 0x58620040, 0xfbfffe06, 0x34010001, 0x33010782, @@ -14713,15 +14918,15 @@ UINT32 FirmwareKB[] = { 0x78040003, 0x78030002, 0x004c0005, - 0x39ad8b1c, + 0x39ad8f24, 0x340b0000, 0x3821c570, - 0x39ce8acc, + 0x39ce8ed0, 0x38e7f824, - 0x38a58ba8, + 0x38a58fb0, 0x38c60004, - 0x38848b24, - 0x3863e2a4, + 0x38848f2c, + 0x3863e5d8, 0x444b0039, 0x330c0789, 0x330c0779, @@ -14758,7 +14963,7 @@ UINT32 FirmwareKB[] = { 0x3821c588, 0xfbfffdd3, 0x29a30000, - 0x59c1003c, + 0x59c10040, 0x3402ffdf, 0xa0222000, 0x40630004, @@ -14766,7 +14971,7 @@ UINT32 FirmwareKB[] = { 0x3821c588, 0xb8801000, 0x44600004, - 0x59c4003c, + 0x59c40040, 0xfbfffdae, 0x330b0782, 0x29a10000, @@ -14793,20 +14998,20 @@ UINT32 FirmwareKB[] = { 0x4301078a, 0x780c0003, 0x340b0000, - 0x398c8b1c, + 0x398c8f24, 0x442b0026, 0x330b0789, 0x29820000, 0x78040003, 0x7801c201, 0x40420004, - 0x38848acc, + 0x38848ed0, 0x3821c588, 0x444b0007, - 0x2882003c, + 0x28820040, 0x3403ffdf, 0xa0431000, - 0x5882003c, + 0x58820040, 0xfbfffd86, 0x330b0782, 0x29810000, @@ -14817,7 +15022,7 @@ UINT32 FirmwareKB[] = { 0x3301077b, 0x78010003, 0x330b0784, - 0x38218ba8, + 0x38218fb0, 0x78050003, 0x302b000a, 0x302b0023, @@ -14827,7 +15032,7 @@ UINT32 FirmwareKB[] = { 0x78020002, 0x3401fbff, 0xa0812000, - 0x38638b24, + 0x38638f2c, 0x38424a68, 0x58620028, 0x58a40000, @@ -14870,7 +15075,7 @@ UINT32 FirmwareKB[] = { 0x58620000, 0x780b0003, 0xfbfffd62, - 0x396b8acc, + 0x396b8ed0, 0x59610018, 0x7801c200, 0x3821c5e0, @@ -14880,13 +15085,13 @@ UINT32 FirmwareKB[] = { 0x34010000, 0x78040003, 0x5b010150, - 0x38848c00, + 0x38849008, 0x0063001d, 0x40820018, 0xb4641800, 0x78010003, 0x40630000, - 0x382185dc, + 0x382189e0, 0xb4411000, 0x10410000, 0x08630019, @@ -14964,14 +15169,14 @@ UINT32 FirmwareKB[] = { 0x3821c450, 0xfbfffd05, 0x78020003, - 0x38428acc, + 0x38428ed0, 0x58410014, 0x78038000, 0x38638000, 0x34010010, 0x58610054, 0x34010001, - 0xf8001194, + 0xf80011bf, 0x78010003, 0x78030003, 0x3821f830, @@ -14983,9 +15188,9 @@ UINT32 FirmwareKB[] = { 0x34030064, 0x34420032, 0x8c431000, - 0xf800119d, + 0xf80011c8, 0x34010024, - 0xfbffcb6c, + 0xfbffca9f, 0x78020003, 0x3842f818, 0x28410000, @@ -14996,9 +15201,9 @@ UINT32 FirmwareKB[] = { 0x38218000, 0x58220054, 0x34010024, - 0xfbffcb8e, + 0xfbffcac1, 0x34010001, - 0xf8001184, + 0xf80011af, 0x78020003, 0x3842f818, 0x28410000, @@ -15024,13 +15229,13 @@ UINT32 FirmwareKB[] = { 0x7801c200, 0x3821c5c4, 0x780b0003, - 0x396b8acc, + 0x396b8ed0, 0xfbfffcc6, 0x59610000, 0xd00c0000, 0x78100003, 0xba001800, - 0x38638acc, + 0x38638ed0, 0x40610000, 0x44200082, 0x2861000c, @@ -15051,7 +15256,7 @@ UINT32 FirmwareKB[] = { 0x5c200002, 0xb9801800, 0xba005800, - 0x396b8acc, + 0x396b8ed0, 0x41650000, 0x2b0102cc, 0x780d0003, @@ -15060,7 +15265,7 @@ UINT32 FirmwareKB[] = { 0xb9a01800, 0xc84c6000, 0x6d810000, - 0x38638c00, + 0x38639008, 0xc8010800, 0xa1816000, 0x3d8c0007, @@ -15078,7 +15283,7 @@ UINT32 FirmwareKB[] = { 0x2f0302b0, 0x2042ffff, 0x2063ffff, - 0xfbffce3f, + 0xfbffcd72, 0x0f0106a0, 0x2b020198, 0x7801c201, @@ -15114,14 +15319,14 @@ UINT32 FirmwareKB[] = { 0x5c20001e, 0x34010000, 0x4c23001f, - 0x39ad8c00, + 0x39ad9008, 0x41a30045, 0x78010003, - 0x38218bf8, + 0x38219000, 0xb4611800, 0x40640000, 0xba002800, - 0x38a58acc, + 0x38a58ed0, 0x28a20000, 0xb9e01800, 0x3863ffff, @@ -15173,33 +15378,24 @@ UINT32 FirmwareKB[] = { 0x379c001c, 0xc3a00000, 0xc3a00000, - 0x379cfff4, - 0x5b8b000c, - 0x5b8c0008, + 0x379cfff8, + 0x5b8b0008, 0x5b9d0004, - 0x78010003, - 0x38218c00, - 0x40220099, - 0xb8205800, - 0x5c400003, - 0x780b0003, - 0x396bfa80, 0x7801c210, 0x38210034, 0x28220000, - 0x780c0003, - 0xb9801800, - 0x3863fa64, - 0x28610000, + 0x780b0003, + 0x396bfa64, + 0x29610000, 0x20420001, 0x64420000, 0x38210001, - 0x58610000, + 0x59610000, 0x34060000, 0x44460016, 0x7801c200, 0x3821c5f0, - 0xfbfffc18, + 0xfbfffc21, 0x00220001, 0x00230003, 0x00240005, @@ -15215,18 +15411,16 @@ UINT32 FirmwareKB[] = { 0x64a50000, 0x78020003, 0xb4c43000, - 0x38428acc, - 0x5841004c, + 0x38428ed0, + 0x58410050, 0xb4c53000, - 0xb9802000, - 0x3884fa64, - 0x28820000, + 0x29620000, 0x7801ffe1, 0x3821ffff, 0x3cc30011, 0xa0411000, 0xb8431000, - 0x58820000, + 0x59620000, 0x2b02017c, 0x3cc30004, 0x2b010178, @@ -15257,16 +15451,21 @@ UINT32 FirmwareKB[] = { 0x4301019f, 0x2b02017c, 0x202100ff, - 0x50410003, - 0x416100b5, - 0xe0000008, + 0x50410005, + 0x78010003, + 0x38219008, + 0x402100b5, + 0xe000000b, 0x430101a0, + 0x78030003, 0x2b02017c, 0x202100ff, - 0x50410003, - 0x416100b6, - 0xe0000002, - 0x416100b4, + 0x50410004, + 0x38639008, + 0x406100b6, + 0xe0000003, + 0x38639008, + 0x406100b4, 0x5b010190, 0x4301019d, 0x2b020180, @@ -15276,16 +15475,21 @@ UINT32 FirmwareKB[] = { 0x430101a2, 0x2b020184, 0x202100ff, - 0x50220003, - 0x416100b4, - 0xe0000008, + 0x50220005, + 0x78010003, + 0x38219008, + 0x402100b4, + 0xe000000b, 0x430101a1, + 0x78030003, 0x2b020184, 0x202100ff, - 0x50220003, - 0x416100b6, - 0xe0000002, - 0x416100b5, + 0x50220004, + 0x38639008, + 0x406100b6, + 0xe0000003, + 0x38639008, + 0x406100b5, 0x5b010194, 0x2b020190, 0x2b010194, @@ -15312,10 +15516,9 @@ UINT32 FirmwareKB[] = { 0x2b010198, 0x00210007, 0x5b010198, - 0x2b8b000c, - 0x2b8c0008, + 0x2b8b0008, 0x2b9d0004, - 0x379c000c, + 0x379c0008, 0xc3a00000, 0x379cffe0, 0x5b8b0020, @@ -15326,19 +15529,14 @@ UINT32 FirmwareKB[] = { 0x5b90000c, 0x5b910008, 0x5b9d0004, - 0x78020003, - 0x38428c00, - 0x40430099, - 0x202b00ff, - 0x5c600003, - 0x78020003, - 0x3842fa80, - 0x2c410032, - 0x780d0003, 0x780c0003, - 0x3c210008, + 0x398c9008, + 0x2d830032, + 0x202b00ff, 0x340203e8, - 0xf80022a1, + 0x3c610008, + 0x780d0003, + 0xf80022d3, 0x0f0102ee, 0x34010001, 0x5b01069c, @@ -15346,16 +15544,16 @@ UINT32 FirmwareKB[] = { 0x78100003, 0x780f8000, 0x78110003, - 0x4560005c, + 0x4560005a, 0x7801c201, 0x3821c2b4, - 0xfbfffb82, + 0xfbfffb89, 0x78020200, 0x38420000, 0xb8221000, 0x7801c201, 0x3821c2b4, - 0xfbfffb62, + 0xfbfffb69, 0x78010003, 0x340b0000, 0x3821f9b0, @@ -15376,38 +15574,36 @@ UINT32 FirmwareKB[] = { 0x7801c201, 0x0f0b02fe, 0x3821c40c, - 0xfbfffb67, - 0xb9a01800, - 0x38638c00, - 0x406200b7, - 0x398c8acc, - 0x5981000c, + 0xfbfffb6e, + 0x418200b7, + 0x39ad8ed0, + 0x59a1000c, 0x3302019c, - 0x406100b8, - 0x78050003, - 0x38a5f82c, + 0x418100b8, + 0x78040003, + 0x3884f82c, 0x3301019d, - 0x406100b9, - 0xba003000, - 0x38c68ba8, + 0x418100b9, + 0xba002800, + 0x38a58fb0, 0x3301019e, - 0x406100ba, - 0x78040002, - 0x3884e994, + 0x418100ba, + 0x78030002, + 0x3863ecc8, 0x3301019f, - 0x406100bb, - 0x39ce8b24, + 0x418100bb, + 0x39ce8f2c, 0x39ef8000, 0x330101a0, - 0x406200bc, + 0x418200bc, 0x34010002, 0x330201a1, - 0x406200bd, + 0x418200bd, 0x330201a2, - 0x406200be, + 0x418200be, 0x330201a3, - 0x2c6200c0, - 0x59c40024, + 0x2d8200c0, + 0x59c30024, 0x0f0201a4, 0x5b0b0178, 0x5b0b017c, @@ -15415,12 +15611,12 @@ UINT32 FirmwareKB[] = { 0x5b0b0184, 0x5b0b0188, 0x5b0b018c, - 0x28a20000, - 0x30c20009, - 0x30c20022, + 0x28820000, + 0x30a20009, + 0x30a20022, 0x34020100, 0x59e20054, - 0xf8000fd3, + 0xf8001007, 0x78010003, 0x3821f900, 0x28220000, @@ -15429,29 +15625,28 @@ UINT32 FirmwareKB[] = { 0x34010002, 0x34420032, 0x8c431000, - 0xf8000fdf, + 0xf8001013, 0x34010028, - 0xfbffc9ae, + 0xfbffc8ea, 0xba201000, 0x3842f818, 0x28410000, 0x38210100, 0x58410000, - 0xe0000028, - 0x39ad8c00, - 0x41ad00aa, - 0xb9801000, - 0x38428acc, - 0x304d000d, + 0xe0000027, + 0x418c00aa, + 0xb9a01000, + 0x38428ed0, + 0x304c000d, 0x2842000c, 0x7801c201, 0x3821c40c, - 0xfbfffb07, + 0xfbfffb11, 0x78010002, 0x38214a68, - 0x39ce8b24, + 0x39ce8f2c, 0xba001000, - 0x38428ba8, + 0x38428fb0, 0x59c10024, 0x304b0009, 0x304b0022, @@ -15459,9 +15654,9 @@ UINT32 FirmwareKB[] = { 0x39ef8000, 0x59e10054, 0x34010028, - 0xfbffc9bf, + 0xfbffc8fc, 0x34010002, - 0xf8000fb5, + 0xf8000fea, 0xba202000, 0x3884f818, 0x28820000, @@ -15470,13 +15665,13 @@ UINT32 FirmwareKB[] = { 0xa0431000, 0x58820000, 0x3821c2b4, - 0xfbfffb09, + 0xfbfffb13, 0x7802fdff, 0x3842ffff, 0xa0221000, 0x7801c201, 0x3821c2b4, - 0xfbfffae9, + 0xfbfffaf3, 0x2b8b0020, 0x2b8c001c, 0x2b8d0018, @@ -15504,16 +15699,16 @@ UINT32 FirmwareKB[] = { 0x5b0c007c, 0x3821c45c, 0x780b0003, - 0xfbfffae7, - 0x396b8acc, - 0x59610040, + 0xfbfffaf1, + 0x396b8ed0, + 0x59610044, 0xb8201800, 0x43010698, 0x3402fffc, 0xa0621800, 0x20210003, 0xb8611800, - 0x59630040, + 0x59630044, 0x43020699, 0x3401ff7f, 0xa0611800, @@ -15522,12 +15717,12 @@ UINT32 FirmwareKB[] = { 0x7801c201, 0xb8621800, 0xb8601000, - 0x59630040, + 0x59630044, 0x3821c45c, - 0xfbfffab9, + 0xfbfffac3, 0x7801c201, 0x3821c570, - 0xfbfffad0, + 0xfbfffada, 0x59610034, 0x4303069a, 0xb8201000, @@ -15539,7 +15734,7 @@ UINT32 FirmwareKB[] = { 0x7801c201, 0x59620034, 0x3821c570, - 0xfbfffaaa, + 0xfbfffab4, 0x78010003, 0x3821f900, 0x28230000, @@ -15549,16 +15744,16 @@ UINT32 FirmwareKB[] = { 0x34030064, 0x34420032, 0x8c431000, - 0xf8000f67, + 0xf8000f9c, 0x2b010080, 0x20218000, 0x442c0002, - 0xfbfff0ed, + 0xfbfff087, 0x2b010080, 0x20211000, 0x44200003, 0xb9a00800, - 0xfbfffd99, + 0xfbfffda3, 0x2b010080, 0x20214000, 0x44200002, @@ -15567,13 +15762,13 @@ UINT32 FirmwareKB[] = { 0x20210100, 0x44200003, 0xb9a00800, - 0xfbffff06, + 0xfbffff0e, 0x2b010080, 0x00210017, 0x20210001, 0x64210000, 0x5c200002, - 0xf8000cb9, + 0xf8000cee, 0xd00e0000, 0x2b8b0014, 0x2b8c0010, @@ -15597,28 +15792,28 @@ UINT32 FirmwareKB[] = { 0x5b02007c, 0x3821c45c, 0x780b0003, - 0xfbfffa8a, - 0x396b8acc, - 0x59610040, + 0xfbfffa94, + 0x396b8ed0, + 0x59610044, 0x20210003, 0x33010698, - 0x29620040, + 0x29620044, 0x7801c201, 0x3821c45c, 0x00420007, 0x20420001, 0x33020699, - 0x29630040, + 0x29630044, 0x3402fffc, 0xa0621800, 0x3402ff7f, 0xa0621800, 0xb8601000, - 0x59630040, - 0xfbfffa5e, + 0x59630044, + 0xfbfffa68, 0x7801c201, 0x3821c570, - 0xfbfffa75, + 0xfbfffa7f, 0x00220009, 0x59610034, 0x20420007, @@ -15629,7 +15824,7 @@ UINT32 FirmwareKB[] = { 0xa0431000, 0x3821c570, 0x59620034, - 0xfbfffa50, + 0xfbfffa5a, 0x78010003, 0x3821f818, 0x28210000, @@ -15639,12 +15834,12 @@ UINT32 FirmwareKB[] = { 0x20210001, 0x64210000, 0x5c200002, - 0xf8000cae, + 0xf8000ce3, 0x2b010080, 0x20210100, 0x44200003, 0xb9800800, - 0xfbfffeb9, + 0xfbfffec1, 0x2b010080, 0x20214000, 0x44200002, @@ -15653,11 +15848,11 @@ UINT32 FirmwareKB[] = { 0x20211000, 0x44200003, 0xb9800800, - 0xfbfffd3a, + 0xfbfffd44, 0x2b010080, 0x20218000, 0x44200002, - 0xfbffefd4, + 0xfbffef6e, 0x78010003, 0x3821f900, 0x28220000, @@ -15666,7 +15861,7 @@ UINT32 FirmwareKB[] = { 0xb9800800, 0x34420032, 0x8c431000, - 0xf8000ef2, + 0xf8000f27, 0xd00d0000, 0x2b8b0010, 0x2b8c000c, @@ -15685,7 +15880,7 @@ UINT32 FirmwareKB[] = { 0x5c200020, 0x3c410002, 0x78020003, - 0x384285e8, + 0x384289ec, 0xb4220800, 0x28210000, 0xc0200000, @@ -15726,8 +15921,8 @@ UINT32 FirmwareKB[] = { 0x78030002, 0x78020003, 0x34010000, - 0x38428ba8, - 0x38848b24, + 0x38428fb0, + 0x38848f2c, 0x38634a68, 0x58830010, 0x30410004, @@ -15740,9 +15935,9 @@ UINT32 FirmwareKB[] = { 0x330b06e5, 0x38210134, 0x34020020, - 0xfbffd55d, + 0xfbffd49a, 0x78010003, - 0x38218acc, + 0x38218ed0, 0x7802c201, 0x582b0020, 0x3842c43c, @@ -15777,13 +15972,13 @@ UINT32 FirmwareKB[] = { 0xd0030000, 0x2f01015c, 0x780b0003, - 0x396b8c00, + 0x396b9008, 0x2f02015a, 0x41630044, 0x34040008, 0x2042ffff, 0x2021ffff, - 0xfbffcb7e, + 0xfbffcabb, 0x0f01015a, 0x2f020244, 0x378c0010, @@ -15804,7 +15999,7 @@ UINT32 FirmwareKB[] = { 0x2f02015e, 0x2021ffff, 0x2042ffff, - 0xfbffcb69, + 0xfbffcaa6, 0x0f01015e, 0x43010158, 0xb9802800, @@ -15824,7 +16019,7 @@ UINT32 FirmwareKB[] = { 0x2f030166, 0x2042ffff, 0x2063ffff, - 0xfbffcbd6, + 0xfbffcb13, 0x43810010, 0xb9802800, 0x33010154, @@ -15843,7 +16038,7 @@ UINT32 FirmwareKB[] = { 0x2f030168, 0x2042ffff, 0x2063ffff, - 0xfbffcbe8, + 0xfbffcb25, 0x43810010, 0x33010156, 0x43810011, @@ -15864,7 +16059,7 @@ UINT32 FirmwareKB[] = { 0x3821c43c, 0x28230000, 0x78020003, - 0x38428acc, + 0x38428ed0, 0x38630001, 0x78010003, 0x58430020, @@ -15877,15 +16072,15 @@ UINT32 FirmwareKB[] = { 0xa0a12800, 0x00a50010, 0x78010003, - 0x38218ba8, - 0x3863f540, - 0x38848b24, + 0x38218fb0, + 0x3863f84c, + 0x38848f2c, 0x780b0003, 0x780c0003, 0x58830010, 0x30250004, 0x3025001d, - 0x398c8c00, + 0x398c9008, 0x396bfa04, 0x2d610002, 0x2d83003e, @@ -15896,7 +16091,7 @@ UINT32 FirmwareKB[] = { 0x2f010162, 0x2021ffff, 0x3c210008, - 0xf8002073, + 0xf80020a8, 0x0f010162, 0x2d610000, 0x2d830040, @@ -15907,7 +16102,7 @@ UINT32 FirmwareKB[] = { 0x2f010164, 0x2021ffff, 0x3c210008, - 0xf8002068, + 0xf800209d, 0x0f010164, 0x2f010162, 0x41820042, @@ -15942,7 +16137,7 @@ UINT32 FirmwareKB[] = { 0x382100b4, 0x28210000, 0x78020003, - 0x38428dd0, + 0x384291d8, 0x20217f00, 0x00210008, 0x34030001, @@ -15966,7 +16161,7 @@ UINT32 FirmwareKB[] = { 0x402102f4, 0x4420000e, 0x78010003, - 0x38218dd0, + 0x382191d8, 0x28220000, 0x7803c050, 0x386300d0, @@ -16375,24 +16570,77 @@ UINT32 FirmwareKB[] = { 0xc3a00000, 0xc3a00000, 0xc3a00000, - 0x34010000, - 0xc3a00000, - 0x34010000, - 0xc3a00000, - 0x34010000, - 0xc3a00000, - 0x379cffe8, - 0x5b8b0018, - 0x5b8c0014, - 0x5b8d0010, - 0x5b8e000c, - 0x5b8f0008, - 0x5b900004, - 0x204affff, - 0x2026ffff, - 0xb8606000, - 0xb8806800, - 0xb9400800, + 0x3801c798, + 0x3803ff9f, + 0xb7210800, + 0x58230000, + 0x3802c770, + 0xb7220800, + 0x28210000, + 0x3404f0ff, + 0xb7221000, + 0xa0240800, + 0x38210700, + 0x58410000, + 0x3801c79c, + 0xb7210800, + 0x58230000, + 0x3802c774, + 0xb7220800, + 0x28210000, + 0xb7221000, + 0x3805b51c, + 0xa0240800, + 0x38210700, + 0x58410000, + 0xb7250800, + 0x28220000, + 0x7803ffff, + 0x38630000, + 0xa0431000, + 0x38420003, + 0x58220000, + 0x3804b01c, + 0xb7240800, + 0x28210000, + 0xb7241000, + 0x3805b11c, + 0xa0230800, + 0x38210003, + 0x58410000, + 0xb7250800, + 0x28220000, + 0x3803c450, + 0x3401ffc0, + 0xa0411000, + 0xb7250800, + 0x58220000, + 0xb7230800, + 0x28210000, + 0x3402ff00, + 0xb7231800, + 0xa0220800, + 0x38210001, + 0x58610000, + 0xc3a00000, + 0x34010000, + 0xc3a00000, + 0x34010000, + 0xc3a00000, + 0x34010000, + 0xc3a00000, + 0x379cffe8, + 0x5b8b0018, + 0x5b8c0014, + 0x5b8d0010, + 0x5b8e000c, + 0x5b8f0008, + 0x5b900004, + 0x204affff, + 0x2026ffff, + 0xb8606000, + 0xb8806800, + 0xb9400800, 0x45400049, 0x3545ffff, 0xb4ca0800, @@ -16804,19 +17052,19 @@ UINT32 FirmwareKB[] = { 0x29620004, 0x202107ff, 0x204207ff, - 0xfbffc84b, + 0xfbffc753, 0x0f01080e, 0x29610008, 0x2f02080e, 0x202107ff, 0x2042ffff, - 0xfbffc845, + 0xfbffc74d, 0x0f01080e, 0x2961000c, 0x2f02080e, 0x202107ff, 0x2042ffff, - 0xfbffc83f, + 0xfbffc747, 0x0f01080e, 0x2f01080e, 0x2021ffff, @@ -16826,7 +17074,7 @@ UINT32 FirmwareKB[] = { 0x4843000c, 0x29810000, 0x78020003, - 0x38428c00, + 0x38429008, 0x20210001, 0x5c20000f, 0x4041002a, @@ -16850,7 +17098,7 @@ UINT32 FirmwareKB[] = { 0x379c000c, 0xc3a00000, 0x78050003, - 0x38a58c00, + 0x38a59008, 0x40a1004b, 0x78060003, 0x78070003, @@ -16858,10 +17106,10 @@ UINT32 FirmwareKB[] = { 0x78040003, 0x78030003, 0x38c6f82c, - 0x38e78ba8, + 0x38e78fb0, 0x3908f818, - 0x38848b24, - 0x3863056c, + 0x38848f2c, + 0x3863094c, 0x44200014, 0x28c10000, 0x40a2002b, @@ -16887,9 +17135,9 @@ UINT32 FirmwareKB[] = { 0x78030002, 0x38634a68, 0x78020003, - 0x38848b24, + 0x38848f2c, 0x34010000, - 0x38428ba8, + 0x38428fb0, 0x58830050, 0x3041002d, 0x30410014, @@ -16972,7 +17220,7 @@ UINT32 FirmwareKB[] = { 0x7ca50001, 0x34030050, 0x5ca00002, - 0xfbfff51b, + 0xfbfff4f0, 0x34010000, 0x2b8b0018, 0x2b8c0014, @@ -16986,22 +17234,22 @@ UINT32 FirmwareKB[] = { 0x3884fa5c, 0x40810001, 0x78020003, - 0x38428ba8, + 0x38428fb0, 0x30410017, 0x40840001, 0x78030003, 0x78010003, - 0x38638b24, - 0x38210720, + 0x38638f2c, + 0x38210b00, 0x30440030, 0x5861005c, 0xc3a00000, 0x78030003, 0x78020002, 0x78010003, - 0x38218ba8, + 0x38218fb0, 0x34040000, - 0x38638b24, + 0x38638f2c, 0x38424a68, 0x5862005c, 0x30240030, @@ -17171,7 +17419,7 @@ UINT32 FirmwareKB[] = { 0x780e0003, 0xb9c06800, 0xb8205800, - 0x39ad8e38, + 0x39ad9240, 0x340c0007, 0xb9600800, 0xf8001a52, @@ -17195,7 +17443,7 @@ UINT32 FirmwareKB[] = { 0x35ad0004, 0x4d80ffec, 0xb9c03000, - 0x38c68e38, + 0x38c69240, 0x2cc50014, 0x2cc20016, 0x34010000, @@ -17238,7 +17486,7 @@ UINT32 FirmwareKB[] = { 0x59620000, 0x2d610000, 0x78040003, - 0x38848c00, + 0x38849008, 0x2021ffff, 0x202200ff, 0x3c420008, @@ -17305,7 +17553,7 @@ UINT32 FirmwareKB[] = { 0x5b8e0008, 0x5b9d0004, 0x78020003, - 0x38428e38, + 0x38429240, 0x40420019, 0xb8206000, 0x370e01c4, @@ -17384,7 +17632,7 @@ UINT32 FirmwareKB[] = { 0x34010009, 0xfbfffda8, 0x78020003, - 0x38428e58, + 0x38429260, 0x34019f9f, 0x7803000f, 0x3863ffff, @@ -17402,7 +17650,7 @@ UINT32 FirmwareKB[] = { 0x34010009, 0xfbfffd96, 0x780b0003, - 0x396b8e60, + 0x396b9268, 0x34011000, 0x340c0008, 0x59610000, @@ -17445,7 +17693,7 @@ UINT32 FirmwareKB[] = { 0x34010009, 0xfbfffd6b, 0x78020003, - 0x38428e58, + 0x38429260, 0x34019f9f, 0x7803000f, 0x3863ffff, @@ -17463,7 +17711,7 @@ UINT32 FirmwareKB[] = { 0x34010009, 0xfbfffd59, 0x780b0003, - 0x396b8e60, + 0x396b9268, 0x34011000, 0x340c0008, 0x59610000, @@ -17504,7 +17752,7 @@ UINT32 FirmwareKB[] = { 0x34010009, 0xfbfffd30, 0x78020003, - 0x38428e58, + 0x38429260, 0x3401ffff, 0x7803000c, 0x3863020f, @@ -17566,7 +17814,7 @@ UINT32 FirmwareKB[] = { 0x780e0003, 0xfbfffcf2, 0xb9c05800, - 0x396b8e60, + 0x396b9268, 0x3401008e, 0x340c0008, 0x59610000, @@ -17602,16 +17850,16 @@ UINT32 FirmwareKB[] = { 0x20210002, 0x44200005, 0x7801a0f8, - 0x38428e58, + 0x38429260, 0x38211405, 0xe0000004, 0x7801a0f8, - 0x38428e58, + 0x38429260, 0x38217465, 0x58410000, 0x78020003, 0x38630001, - 0x38428e58, + 0x38429260, 0x58430004, 0x34010034, 0xfbfffcae, @@ -17625,7 +17873,7 @@ UINT32 FirmwareKB[] = { 0x34010009, 0xfbfffcb7, 0xb9c05800, - 0x396b8e60, + 0x396b9268, 0x3401008e, 0x340c0008, 0x59610000, @@ -17669,7 +17917,7 @@ UINT32 FirmwareKB[] = { 0xfbfffc8c, 0x78020003, 0x7801a0f8, - 0x38428e58, + 0x38429260, 0x38217465, 0x78030008, 0x38630001, @@ -17687,7 +17935,7 @@ UINT32 FirmwareKB[] = { 0x34010009, 0x780b0003, 0x780e0100, - 0x396b8e60, + 0x396b9268, 0x340c0008, 0xfbfffc75, 0x39ce02ae, @@ -17784,8 +18032,8 @@ UINT32 FirmwareKB[] = { 0x50620002, 0xe0000012, 0x296b0000, - 0xfbffd2d5, - 0xfbffd2c0, + 0xfbffd1dd, + 0xfbffd1c8, 0xb9800800, 0x34020001, 0xf8000628, @@ -17799,7 +18047,7 @@ UINT32 FirmwareKB[] = { 0xb9600800, 0x34020007, 0x504b0002, - 0xfbffd2b2, + 0xfbffd1ba, 0x2b8b000c, 0x2b8c0008, 0x2b9d0004, @@ -18012,7 +18260,7 @@ UINT32 FirmwareKB[] = { 0x7802003c, 0x3821c51c, 0x38420000, - 0xfbfff101, + 0xfbfff0d6, 0x34020058, 0x5b02083c, 0x34010ace, @@ -18046,7 +18294,7 @@ UINT32 FirmwareKB[] = { 0x5b020840, 0x34020100, 0x58820050, - 0xfbffbf77, + 0xfbffbe7f, 0x2b8b0008, 0x2b9d0004, 0x379c0008, @@ -18054,7 +18302,7 @@ UINT32 FirmwareKB[] = { 0x379cfffc, 0x5b9d0004, 0x34010008, - 0xfbffbf9c, + 0xfbffbea4, 0x34010000, 0x33010830, 0x2b010838, @@ -18088,7 +18336,7 @@ UINT32 FirmwareKB[] = { 0x7802003c, 0x3821c51c, 0x38420000, - 0xfbfff0b5, + 0xfbfff08a, 0x34020018, 0x5b02083c, 0x34010ace, @@ -18393,7 +18641,7 @@ UINT32 FirmwareKB[] = { 0x2f01080c, 0x2b020868, 0x2021ffff, - 0xfbffc211, + 0xfbffc119, 0x5b010868, 0x2f01080c, 0x2b02086c, @@ -18403,7 +18651,7 @@ UINT32 FirmwareKB[] = { 0x2f01080e, 0x2b020870, 0x2021ffff, - 0xfbffc207, + 0xfbffc10f, 0x5b010870, 0x2f01080e, 0x2b020874, @@ -18418,7 +18666,7 @@ UINT32 FirmwareKB[] = { 0x2b010888, 0x2f0202b2, 0x2042ffff, - 0xfbffc1f8, + 0xfbffc100, 0x5b010888, 0x2f0102b2, 0x2b02088c, @@ -18432,7 +18680,7 @@ UINT32 FirmwareKB[] = { 0x2b010894, 0x2f0206a0, 0x2042ffff, - 0xfbffc1ea, + 0xfbffc0f2, 0x5b010894, 0x2f0102c4, 0x2b020898, @@ -18442,7 +18690,7 @@ UINT32 FirmwareKB[] = { 0x2b01089c, 0x2f02015e, 0x2042ffff, - 0xfbffc1e0, + 0xfbffc0e8, 0x5b01089c, 0x2f01015e, 0x2b0208a0, @@ -18452,7 +18700,7 @@ UINT32 FirmwareKB[] = { 0x2b0108a4, 0x2f02015a, 0x2042ffff, - 0xfbffc1d6, + 0xfbffc0de, 0x5b0108a4, 0x2f02015a, 0x78040003, @@ -18528,7 +18776,7 @@ UINT32 FirmwareKB[] = { 0x2f01016e, 0x2b020908, 0x2021ffff, - 0xfbffc18a, + 0xfbffc092, 0x5b010908, 0x2f01016e, 0x2b02090c, @@ -18577,7 +18825,7 @@ UINT32 FirmwareKB[] = { 0x78020003, 0x59010000, 0x2b010868, - 0x38428c00, + 0x38429008, 0x2c430082, 0x3421fe78, 0x3c210005, @@ -18779,7 +19027,7 @@ UINT32 FirmwareKB[] = { 0xb4380800, 0x2c210240, 0x780c0003, - 0x398c8c00, + 0x398c9008, 0xb4411000, 0x0f02016c, 0x2f01016c, @@ -18788,7 +19036,7 @@ UINT32 FirmwareKB[] = { 0x2f02016e, 0x2021ffff, 0x2042ffff, - 0xfbffbfc1, + 0xfbffbec9, 0x0f01016e, 0x2f02016e, 0x2f010170, @@ -18823,7 +19071,7 @@ UINT32 FirmwareKB[] = { 0x340203e8, 0xf8001506, 0x0f0102ee, - 0xfbffc071, + 0xfbffbf79, 0x34010000, 0x2b8b000c, 0x2b8c0008, @@ -18837,7 +19085,7 @@ UINT32 FirmwareKB[] = { 0x34010000, 0xd0010000, 0x78040003, - 0x38848c00, + 0x38849008, 0x2c830082, 0x2c8100c6, 0x340203e8, @@ -18862,7 +19110,7 @@ UINT32 FirmwareKB[] = { 0xa0411000, 0x00420010, 0x78010003, - 0x38218ba8, + 0x38218fb0, 0x78050003, 0x30220015, 0x3022002e, @@ -18876,8 +19124,8 @@ UINT32 FirmwareKB[] = { 0x78030003, 0x78010003, 0xb8822000, - 0x38638b24, - 0x38212438, + 0x38638f2c, + 0x38212818, 0x58610054, 0x58a40000, 0xd00b0000, @@ -18892,7 +19140,7 @@ UINT32 FirmwareKB[] = { 0x330202bc, 0x78010003, 0x330206e4, - 0x38218ba8, + 0x38218fb0, 0x78050003, 0x3022002e, 0x30220015, @@ -18903,7 +19151,7 @@ UINT32 FirmwareKB[] = { 0x78030003, 0x78020002, 0xa0812000, - 0x38638b24, + 0x38638f2c, 0x38424a68, 0x58620054, 0x58a40000, @@ -18915,7 +19163,7 @@ UINT32 FirmwareKB[] = { 0x430202b8, 0x78050003, 0x7801c201, - 0x38a58acc, + 0x38a58ed0, 0x3821c43c, 0x204200ff, 0x340b0000, @@ -18943,7 +19191,7 @@ UINT32 FirmwareKB[] = { 0xb8441000, 0x38420001, 0x58a20020, - 0xfbffed5e, + 0xfbffed33, 0x34010000, 0x330b02bf, 0x2b8b0008, @@ -18988,7 +19236,7 @@ UINT32 FirmwareKB[] = { 0xc3a00000, 0x78030003, 0xb8201000, - 0x3863861c, + 0x38638a20, 0x34040000, 0x2021000f, 0x5c240003, @@ -19003,7 +19251,7 @@ UINT32 FirmwareKB[] = { 0x5b8b0008, 0x5b9d0004, 0x780b0003, - 0x396b98d8, + 0x396b9ce0, 0x29610008, 0x5c200019, 0x2961000c, @@ -19038,7 +19286,7 @@ UINT32 FirmwareKB[] = { 0x34010000, 0xd0010000, 0x78020003, - 0x384298d8, + 0x38429ce0, 0x28410008, 0x34210001, 0x58410008, @@ -19051,19 +19299,19 @@ UINT32 FirmwareKB[] = { 0xd0010000, 0x78050003, 0xb8a01800, - 0x386398d8, + 0x38639ce0, 0x28610008, 0x3422ffff, 0x44200002, 0x58620008, 0xd0040000, 0xb8a01000, - 0x384298d8, + 0x38429ce0, 0x28410008, 0x5c200004, 0x28410004, 0x5c200002, - 0xfbffb6f6, + 0xfbffb5fe, 0x2b9d0004, 0x379c0004, 0xc3a00000, @@ -19073,7 +19321,7 @@ UINT32 FirmwareKB[] = { 0x5b8d0004, 0x780c0003, 0xb9805800, - 0x396b98d8, + 0x396b9ce0, 0x34080000, 0x340d0001, 0x35690014, @@ -19089,7 +19337,7 @@ UINT32 FirmwareKB[] = { 0x44800016, 0x2881000c, 0xb9803000, - 0x38c698d8, + 0x38c69ce0, 0x3423ffff, 0xa4a03800, 0x5883000c, @@ -19119,7 +19367,7 @@ UINT32 FirmwareKB[] = { 0x5b9d0004, 0x78050003, 0xb8a02000, - 0x388498d8, + 0x38849ce0, 0x28820004, 0xb8201800, 0x3401ffff, @@ -19130,7 +19378,7 @@ UINT32 FirmwareKB[] = { 0x5823000c, 0x90003800, 0xd0020000, - 0x38a598d8, + 0x38a59ce0, 0x28a60000, 0x28a30010, 0x34020001, @@ -19145,7 +19393,7 @@ UINT32 FirmwareKB[] = { 0xa0822000, 0x58a4000c, 0xd0070000, - 0xfbffb6a4, + 0xfbffb5ac, 0x34010000, 0x2b9d0004, 0x379c0004, @@ -19164,7 +19412,7 @@ UINT32 FirmwareKB[] = { 0xbc412800, 0x78030003, 0x3c220002, - 0x386398d8, + 0x38639ce0, 0x74210007, 0xa4a02000, 0xb4431000, @@ -19185,10 +19433,10 @@ UINT32 FirmwareKB[] = { 0x5861000c, 0xd00c0000, 0x78010003, - 0x382198d8, + 0x38219ce0, 0x28210004, 0x5c20000c, - 0xfbffb679, + 0xfbffb581, 0xe000000a, 0x29610004, 0x29620008, @@ -19210,7 +19458,7 @@ UINT32 FirmwareKB[] = { 0x5b9d0004, 0x780b0003, 0xb9601800, - 0x386398d8, + 0x38639ce0, 0x28640004, 0xb8202800, 0xb8404000, @@ -19220,7 +19468,7 @@ UINT32 FirmwareKB[] = { 0xd0040000, 0x28a10004, 0xb9602000, - 0x388498d8, + 0x38849ce0, 0x34070001, 0x3422ffff, 0x44200005, @@ -19249,8 +19497,8 @@ UINT32 FirmwareKB[] = { 0xb8220800, 0x58810010, 0xd0060000, - 0xfbffb63c, - 0x396b98d8, + 0xfbffb544, + 0x396b9ce0, 0x29610000, 0x2821001c, 0x7c210000, @@ -19288,7 +19536,7 @@ UINT32 FirmwareKB[] = { 0x379cfffc, 0x5b9d0004, 0x78010003, - 0x382198d8, + 0x38219ce0, 0x28220000, 0x28410018, 0x28420014, @@ -19297,7 +19545,7 @@ UINT32 FirmwareKB[] = { 0x34010000, 0xd0010000, 0x78020003, - 0x384298d8, + 0x38429ce0, 0x28410000, 0x2843000c, 0x28240008, @@ -19307,7 +19555,7 @@ UINT32 FirmwareKB[] = { 0xa0611800, 0x5843000c, 0xd0050000, - 0xfbffb602, + 0xfbffb50a, 0x2b9d0004, 0x379c0004, 0xc3a00000, @@ -19319,7 +19567,7 @@ UINT32 FirmwareKB[] = { 0xb8404800, 0x34020001, 0x780b0003, - 0x396b98d8, + 0x396b9ce0, 0xbc496000, 0xb4eb3800, 0x28e20014, @@ -19699,10 +19947,10 @@ UINT32 FirmwareKB[] = { 0x5b8c0004, 0x780a0003, 0xb9402800, - 0x38a58dd4, + 0x38a591dc, 0x28a60000, 0x78080003, - 0x39088dae, + 0x390891b6, 0x34c60001, 0x20c6ffff, 0x41070000, @@ -19721,7 +19969,7 @@ UINT32 FirmwareKB[] = { 0x34010000, 0x31010000, 0xb9400800, - 0x38218dd4, + 0x382191dc, 0x78028002, 0x38428000, 0x28240000, @@ -19749,7 +19997,7 @@ UINT32 FirmwareKB[] = { 0x68810007, 0x58430010, 0x4420fff9, - 0x394a8dd4, + 0x394a91dc, 0x29410000, 0x2b8b0008, 0x2b8c0004, @@ -19757,8 +20005,8 @@ UINT32 FirmwareKB[] = { 0xc3a00000, 0x78020003, 0x78040003, - 0x38428de0, - 0x38848e28, + 0x384291e8, + 0x38849230, 0x34030001, 0x3043000f, 0x58810000, @@ -19772,15 +20020,15 @@ UINT32 FirmwareKB[] = { 0x7801c201, 0x3821c530, 0x34020026, - 0xfbffea21, + 0xfbffe9f6, 0x7801c201, 0xb9601000, 0x3821c534, - 0xfbffea1d, + 0xfbffe9f2, 0x7801c201, 0x3821c538, 0xb9801000, - 0xfbffea19, + 0xfbffe9ee, 0x2b8b000c, 0x2b8c0008, 0x2b9d0004, @@ -19843,7 +20091,7 @@ UINT32 FirmwareKB[] = { 0x5c2c0022, 0x3c410002, 0x78020003, - 0x3842862c, + 0x38428a30, 0xb4220800, 0x28210000, 0xc0200000, @@ -19889,11 +20137,11 @@ UINT32 FirmwareKB[] = { 0x64810000, 0x5c200009, 0x78020003, - 0x38428de0, + 0x384291e8, 0x34030001, 0x78010003, 0x3043000d, - 0x38218eac, + 0x382192b4, 0xfbfffd18, 0x340d0000, 0x45800005, @@ -19920,10 +20168,10 @@ UINT32 FirmwareKB[] = { 0x7801c201, 0x34020065, 0x3821c530, - 0xfbffe98d, + 0xfbffe962, 0x7801c201, 0x3821c534, - 0xfbffe9a4, + 0xfbffe979, 0x2b9d0004, 0x379c0004, 0xc3a00000, @@ -19941,16 +20189,16 @@ UINT32 FirmwareKB[] = { 0x379cfffc, 0x5b9d0004, 0x78030003, - 0x38638acc, - 0x28620048, + 0x38638ed0, + 0x2862004c, 0x78010001, 0x38210000, 0xb8411000, 0x38420001, 0x7801c201, - 0x58620048, + 0x5862004c, 0x3821c50c, - 0xfbffe96f, + 0xfbffe944, 0x2b9d0004, 0x379c0004, 0xc3a00000, @@ -20061,7 +20309,7 @@ UINT32 FirmwareKB[] = { 0x5b8f0008, 0x5b9d0004, 0x78060003, - 0x38c68dd8, + 0x38c691e0, 0x28c70000, 0x780c8002, 0x398c8000, @@ -20286,7 +20534,7 @@ UINT32 FirmwareKB[] = { 0x5b910008, 0x5b9d0004, 0x78060003, - 0x38c68de0, + 0x38c691e8, 0x40c4000c, 0xb8202800, 0xb8404000, @@ -20314,7 +20562,7 @@ UINT32 FirmwareKB[] = { 0x78110003, 0xba204000, 0x20a5ffff, - 0x39088de0, + 0x390891e8, 0x3df00002, 0x00260018, 0x3ca30008, @@ -20330,7 +20578,7 @@ UINT32 FirmwareKB[] = { 0xe000003f, 0x44e00038, 0xba206000, - 0x398c8de0, + 0x398c91e8, 0xb60c0800, 0x282b0038, 0x282d0040, @@ -20372,7 +20620,7 @@ UINT32 FirmwareKB[] = { 0x20210001, 0x64210000, 0x5c20fffd, - 0x3a318de0, + 0x3a3191e8, 0xb6111000, 0x28410038, 0x28430040, @@ -20385,7 +20633,7 @@ UINT32 FirmwareKB[] = { 0x34040003, 0xfbfffdbb, 0x78010003, - 0x38218de0, + 0x382191e8, 0xb5e10800, 0x34020000, 0x3022001c, @@ -20569,10 +20817,10 @@ UINT32 FirmwareKB[] = { 0x78040003, 0x34050000, 0x5c250004, - 0x38848de0, + 0x388491e8, 0x30830018, 0xe0000003, - 0x38848de0, + 0x388491e8, 0x30850018, 0xa0c20800, 0x34030000, @@ -20580,10 +20828,10 @@ UINT32 FirmwareKB[] = { 0x34020001, 0x78040003, 0x5c230004, - 0x38848de0, + 0x388491e8, 0x30830017, 0xc3a00000, - 0x38848de0, + 0x388491e8, 0x30820017, 0xc3a00000, 0x379cff8c, @@ -20604,7 +20852,7 @@ UINT32 FirmwareKB[] = { 0x5b9d0004, 0x78100003, 0xba000800, - 0x38218de0, + 0x382191e8, 0x40210001, 0x5b81004c, 0x2b82004c, @@ -20691,7 +20939,7 @@ UINT32 FirmwareKB[] = { 0xba003800, 0x38c60000, 0xa1663000, - 0x38e78de0, + 0x38e791e8, 0x204200ff, 0x34010000, 0x78030800, @@ -20742,7 +20990,7 @@ UINT32 FirmwareKB[] = { 0x5c200027, 0x78010003, 0x3da20002, - 0x38218640, + 0x38218a44, 0xb4411000, 0x28410000, 0x78030003, @@ -20809,7 +21057,7 @@ UINT32 FirmwareKB[] = { 0x5c200101, 0x3da10002, 0x78020003, - 0x38428674, + 0x38428a78, 0xb4220800, 0x28210000, 0xc0200000, @@ -20820,7 +21068,7 @@ UINT32 FirmwareKB[] = { 0x38630000, 0xb8230800, 0xb9e01000, - 0xfbffe609, + 0xfbffe5de, 0xe0000018, 0x2b810054, 0x78028008, @@ -20831,10 +21079,10 @@ UINT32 FirmwareKB[] = { 0x78030003, 0xb4220800, 0x582f0000, - 0x3a108de0, + 0x3a1091e8, 0x34010001, - 0x38845250, - 0x38638e28, + 0x38845630, + 0x38639230, 0x3201000f, 0xe0000087, 0x78020003, @@ -20847,7 +21095,7 @@ UINT32 FirmwareKB[] = { 0xfbfffeaf, 0x78030003, 0x78020003, - 0x38635250, + 0x38635630, 0xe0000010, 0x78020003, 0x3842f540, @@ -20863,9 +21111,9 @@ UINT32 FirmwareKB[] = { 0xfbfffd66, 0x78030003, 0x78020003, - 0x38634fc8, - 0x3a108de0, - 0x38428e28, + 0x386353a8, + 0x3a1091e8, + 0x38429230, 0x34010001, 0x3201000f, 0x58430000, @@ -20945,7 +21193,7 @@ UINT32 FirmwareKB[] = { 0xfbfffd66, 0x4420000b, 0xba000800, - 0x38218de0, + 0x382191e8, 0x28220028, 0x2821002c, 0x5b810050, @@ -20966,10 +21214,10 @@ UINT32 FirmwareKB[] = { 0x78020003, 0x78040003, 0x78030003, - 0x38428de0, + 0x384291e8, 0x34010001, - 0x38845314, - 0x38638e28, + 0x388456f4, + 0x38639230, 0x3041000f, 0x58640000, 0xe000005b, @@ -21057,9 +21305,9 @@ UINT32 FirmwareKB[] = { 0x384203a0, 0xb4a20800, 0x58270000, - 0x38845530, - 0x3a108de0, - 0x38c68e28, + 0x38845910, + 0x3a1091e8, + 0x38c69230, 0x34010001, 0x3201000f, 0x58c40000, @@ -21070,7 +21318,7 @@ UINT32 FirmwareKB[] = { 0x2b81004c, 0xfbfffdf5, 0x78010003, - 0x38218eac, + 0x382192b4, 0xfbfff87f, 0x2b8b003c, 0x2b8c0038, @@ -21097,7 +21345,7 @@ UINT32 FirmwareKB[] = { 0xb8206000, 0x78060003, 0x780100ff, - 0x38c68ddc, + 0x38c691e4, 0x3821ffff, 0x28c50000, 0x3c840018, @@ -21148,7 +21396,7 @@ UINT32 FirmwareKB[] = { 0x5b9d0004, 0x78110003, 0xba200800, - 0x38218de0, + 0x382191e8, 0x40320001, 0x78020003, 0x3842f008, @@ -21247,14 +21495,14 @@ UINT32 FirmwareKB[] = { 0x206300ff, 0x208d00ff, 0x5c400004, - 0x3a318de0, + 0x3a3191e8, 0x34010000, 0x32210019, 0x7461000c, 0x5c20007e, 0x3c610002, 0x78020003, - 0x384286a8, + 0x38428aac, 0xb4220800, 0x28210000, 0x780b0003, @@ -21266,7 +21514,7 @@ UINT32 FirmwareKB[] = { 0xa0220800, 0x38630000, 0xb8230800, - 0xfbffe465, + 0xfbffe43a, 0xe0000019, 0x2b82002c, 0x78048008, @@ -21277,11 +21525,11 @@ UINT32 FirmwareKB[] = { 0xb9c01800, 0xb4441000, 0x28420000, - 0x396b8de0, - 0x398c8e28, + 0x396b91e8, + 0x398c9230, 0xfbfffc91, 0x78010003, - 0x382159c8, + 0x38215da8, 0x34020001, 0x3162000f, 0x59810000, @@ -21297,7 +21545,7 @@ UINT32 FirmwareKB[] = { 0xb9c01800, 0xfbfffc81, 0x78020003, - 0x384259c8, + 0x38425da8, 0xe000000d, 0x78020003, 0x3842f540, @@ -21310,16 +21558,16 @@ UINT32 FirmwareKB[] = { 0xfbfffb77, 0xfbfffcf9, 0x78020003, - 0x38425074, - 0x396b8de0, - 0x398c8e28, + 0x38425454, + 0x396b91e8, + 0x398c9230, 0x34010001, 0x3161000f, 0x59820000, 0xe000003d, 0x2b82002c, 0x2b810028, - 0x396b8de0, + 0x396b91e8, 0x31620000, 0x34030000, 0xfbfffbea, @@ -21337,8 +21585,8 @@ UINT32 FirmwareKB[] = { 0xfbffff0b, 0x78010003, 0x78020003, - 0x382157e4, - 0x38428e28, + 0x38215bc4, + 0x38429230, 0x34040001, 0x65e30000, 0x58410000, @@ -21371,16 +21619,16 @@ UINT32 FirmwareKB[] = { 0x78030003, 0x78040003, 0x58460000, - 0x38a55484, - 0x38638de0, - 0x38848e28, + 0x38a55864, + 0x386391e8, + 0x38849230, 0x34010001, 0x3061000f, 0x58850000, 0xba400800, 0xfbfffcbf, 0x78010003, - 0x38218eac, + 0x382192b4, 0xfbfff749, 0x2b8b0024, 0x2b8c0020, @@ -21440,7 +21688,7 @@ UINT32 FirmwareKB[] = { 0x5b8b0008, 0x5b9d0004, 0x780b0003, - 0x396b8de0, + 0x396b91e8, 0x41630018, 0x78020003, 0x3842f304, @@ -21463,7 +21711,7 @@ UINT32 FirmwareKB[] = { 0x5b8b0008, 0x5b9d0004, 0x780b0003, - 0x396b8de0, + 0x396b91e8, 0x41630018, 0x78020003, 0x3842f30c, @@ -21486,7 +21734,7 @@ UINT32 FirmwareKB[] = { 0x5b8b0008, 0x5b9d0004, 0x780b0003, - 0x396b8de0, + 0x396b91e8, 0x41630013, 0x34010000, 0x34020002, @@ -21504,20 +21752,20 @@ UINT32 FirmwareKB[] = { 0x41610017, 0x78050003, 0x78040003, - 0x38a56938, + 0x38a56d18, 0x34060001, - 0x388440b4, + 0x38844494, 0x78020003, 0x44200005, - 0x38428e28, + 0x38429230, 0x3166000f, 0x58450000, 0xe0000004, - 0x38428e28, + 0x38429230, 0x3166000f, 0x58440000, 0x78010003, - 0x38218eac, + 0x382192b4, 0xfbfff6c0, 0x2b8b0008, 0x2b9d0004, @@ -21529,7 +21777,7 @@ UINT32 FirmwareKB[] = { 0x3842f30c, 0x28430000, 0x78040003, - 0x38848de0, + 0x388491e8, 0x7802e000, 0x38420000, 0xa0621800, @@ -21555,7 +21803,7 @@ UINT32 FirmwareKB[] = { 0x5b8b0008, 0x5b9d0004, 0x780b0003, - 0x396b8de0, + 0x396b91e8, 0x41610001, 0xfbffffde, 0x41630013, @@ -21575,20 +21823,20 @@ UINT32 FirmwareKB[] = { 0x41610017, 0x78050003, 0x78040003, - 0x38a56938, + 0x38a56d18, 0x34060001, - 0x388440b4, + 0x38844494, 0x78020003, 0x44200005, - 0x38428e28, + 0x38429230, 0x3166000f, 0x58450000, 0xe0000004, - 0x38428e28, + 0x38429230, 0x3166000f, 0x58440000, 0x78010003, - 0x38218eac, + 0x382192b4, 0xfbfff679, 0x2b8b0008, 0x2b9d0004, @@ -21612,7 +21860,7 @@ UINT32 FirmwareKB[] = { 0x38210000, 0xa0411000, 0xba000800, - 0x38218de0, + 0x382191e8, 0x004d0018, 0x402e0001, 0x65ab0000, @@ -21668,7 +21916,7 @@ UINT32 FirmwareKB[] = { 0x3402ffef, 0xba005800, 0xa0220800, - 0x396b8de0, + 0x396b91e8, 0x58610000, 0x41610013, 0x44200006, @@ -21687,16 +21935,16 @@ UINT32 FirmwareKB[] = { 0x41610017, 0x78020003, 0x78030003, - 0x38426938, + 0x38426d18, 0x5c200003, 0x78020003, - 0x384240b4, + 0x38424494, 0x34010001, 0x3161000f, - 0x38638e28, + 0x38639230, 0x78010003, 0x58620000, - 0x38218eac, + 0x382192b4, 0xfbfff60d, 0xe0000006, 0x5c40ffaf, @@ -21717,7 +21965,7 @@ UINT32 FirmwareKB[] = { 0x5b8b0008, 0x5b9d0004, 0x780b0003, - 0x396b8de0, + 0x396b91e8, 0x41610001, 0xfbffff3c, 0x78040003, @@ -21743,20 +21991,20 @@ UINT32 FirmwareKB[] = { 0x41610017, 0x78050003, 0x78040003, - 0x38a56938, + 0x38a56d18, 0x34060001, - 0x388440b4, + 0x38844494, 0x78020003, 0x44200005, - 0x38428e28, + 0x38429230, 0x3166000f, 0x58450000, 0xe0000004, - 0x38428e28, + 0x38429230, 0x3166000f, 0x58440000, 0x78010003, - 0x38218eac, + 0x382192b4, 0xfbfff5d1, 0x2b8b0008, 0x2b9d0004, @@ -21804,7 +22052,7 @@ UINT32 FirmwareKB[] = { 0x64210000, 0x5c200028, 0x780b0003, - 0x396b8de0, + 0x396b91e8, 0x41610001, 0xfbfffee5, 0x78020003, @@ -21830,16 +22078,16 @@ UINT32 FirmwareKB[] = { 0x41610017, 0x78020003, 0x78030003, - 0x38426938, + 0x38426d18, 0x5c200003, 0x78020003, - 0x384240b4, + 0x38424494, 0x34010001, 0x3161000f, - 0x38638e28, + 0x38639230, 0x78010003, 0x58620000, - 0x38218eac, + 0x382192b4, 0xfbfff57e, 0xe0000006, 0x5c40ffc0, @@ -21858,7 +22106,7 @@ UINT32 FirmwareKB[] = { 0x5b8b0008, 0x5b9d0004, 0x780b0003, - 0x396b8de0, + 0x396b91e8, 0x41610001, 0xfbfffe58, 0x41630013, @@ -21878,20 +22126,20 @@ UINT32 FirmwareKB[] = { 0x41610017, 0x78050003, 0x78040003, - 0x38a56938, + 0x38a56d18, 0x34060001, - 0x388440b4, + 0x38844494, 0x78020003, 0x44200005, - 0x38428e28, + 0x38429230, 0x3166000f, 0x58450000, 0xe0000004, - 0x38428e28, + 0x38429230, 0x3166000f, 0x58440000, 0x78010003, - 0x38218eac, + 0x382192b4, 0xfbfff54a, 0x2b8b0008, 0x2b9d0004, @@ -21908,7 +22156,7 @@ UINT32 FirmwareKB[] = { 0x5b9d0004, 0x780e0003, 0xb9c00800, - 0x38218de0, + 0x382191e8, 0x40210001, 0x78100003, 0x340d0000, @@ -21994,7 +22242,7 @@ UINT32 FirmwareKB[] = { 0xba205800, 0xa0220800, 0x58610000, - 0x396b8de0, + 0x396b91e8, 0x41610013, 0x442c0005, 0xb9800800, @@ -22010,12 +22258,12 @@ UINT32 FirmwareKB[] = { 0x41610017, 0x78020003, 0x78030003, - 0x38426938, + 0x38426d18, 0x5c200003, 0x78020003, - 0x384240b4, + 0x38424494, 0x34010001, - 0x38638e28, + 0x38639230, 0x3161000f, 0xe000001c, 0x45670020, @@ -22023,7 +22271,7 @@ UINT32 FirmwareKB[] = { 0xb8205800, 0x5c20001d, 0xb9c06000, - 0x398c8de0, + 0x398c91e8, 0x41820013, 0x44400004, 0x34020002, @@ -22038,16 +22286,16 @@ UINT32 FirmwareKB[] = { 0x41810017, 0x78020003, 0x78030003, - 0x38426938, + 0x38426d18, 0x5c200003, 0x78020003, - 0x384240b4, + 0x38424494, 0x34010001, - 0x38638e28, + 0x38639230, 0x3181000f, 0x78010003, 0x58620000, - 0x38218eac, + 0x382192b4, 0xfbfff4ae, 0xe000000b, 0xe5af1000, @@ -22079,7 +22327,7 @@ UINT32 FirmwareKB[] = { 0x5b9d0004, 0x780f0003, 0xb9e00800, - 0x38218de0, + 0x382191e8, 0x40210001, 0x780e0003, 0x340c0000, @@ -22118,7 +22366,7 @@ UINT32 FirmwareKB[] = { 0x7c2100ff, 0x5c20003e, 0xb9e05800, - 0x396b8de0, + 0x396b91e8, 0x41630000, 0x78018002, 0x34020040, @@ -22166,16 +22414,16 @@ UINT32 FirmwareKB[] = { 0x41610017, 0x78020003, 0x78030003, - 0x38426938, + 0x38426d18, 0x5c200003, 0x78020003, - 0x384240b4, + 0x38424494, 0x34010001, 0x3161000f, - 0x38638e28, + 0x38639230, 0x78010003, 0x58620000, - 0x38218eac, + 0x382192b4, 0xfbfff42e, 0xe0000006, 0x5c40ffaa, @@ -22195,7 +22443,7 @@ UINT32 FirmwareKB[] = { 0x5b8b0008, 0x5b9d0004, 0x780b0003, - 0x396b8de0, + 0x396b91e8, 0x41610001, 0xfbfffd07, 0x78040003, @@ -22221,20 +22469,20 @@ UINT32 FirmwareKB[] = { 0x41610017, 0x78050003, 0x78040003, - 0x38a56938, + 0x38a56d18, 0x34060001, - 0x388440b4, + 0x38844494, 0x78020003, 0x44200005, - 0x38428e28, + 0x38429230, 0x3166000f, 0x58450000, 0xe0000004, - 0x38428e28, + 0x38429230, 0x3166000f, 0x58440000, 0x78010003, - 0x38218eac, + 0x382192b4, 0xfbfff3f3, 0x2b8b0008, 0x2b9d0004, @@ -22250,7 +22498,7 @@ UINT32 FirmwareKB[] = { 0x5c270055, 0x3c810002, 0x78020003, - 0x384286dc, + 0x38428ae0, 0xb4220800, 0x28210000, 0xc0200000, @@ -22359,7 +22607,7 @@ UINT32 FirmwareKB[] = { 0x5b9d0004, 0x780e0003, 0xb9c00800, - 0x38218de0, + 0x382191e8, 0x40240001, 0x78030003, 0x3863f000, @@ -22520,14 +22768,14 @@ UINT32 FirmwareKB[] = { 0xfbfff7bb, 0x78020003, 0x78030003, - 0x38426938, - 0x38638e28, + 0x38426d18, + 0x38639230, 0x34040001, - 0x39ce8de0, + 0x39ce91e8, 0x78010003, 0x31c4000f, 0x58620000, - 0x38218eac, + 0x382192b4, 0xfbfff2ce, 0x2b8b0020, 0x2b8c001c, @@ -22553,7 +22801,7 @@ UINT32 FirmwareKB[] = { 0x5b9d0004, 0x78110003, 0xba208000, - 0x3a108de0, + 0x3a1091e8, 0x42130001, 0x78010003, 0x3821f008, @@ -22580,10 +22828,10 @@ UINT32 FirmwareKB[] = { 0x7801c201, 0x34020065, 0x3821c530, - 0xfbffdf29, + 0xfbffdefe, 0x7801c201, 0x3821c534, - 0xfbffdf40, + 0xfbffdf15, 0x00220008, 0x00210004, 0x20420100, @@ -22613,8 +22861,8 @@ UINT32 FirmwareKB[] = { 0x4422000a, 0x78020003, 0x78030003, - 0x38426938, - 0x38638e28, + 0x38426d18, + 0x38639230, 0x34040001, 0x78010003, 0x3204000f, @@ -22654,7 +22902,7 @@ UINT32 FirmwareKB[] = { 0x3421ffff, 0x202100ff, 0x34230034, - 0x3a318de0, + 0x3a3191e8, 0xba802000, 0x32230001, 0x3884f320, @@ -22669,7 +22917,7 @@ UINT32 FirmwareKB[] = { 0x21610100, 0x44200007, 0x78020003, - 0x38428de0, + 0x384291e8, 0x34030001, 0x78010003, 0x3043000e, @@ -22700,14 +22948,14 @@ UINT32 FirmwareKB[] = { 0x78050003, 0x78020003, 0x78030003, - 0x38a56938, - 0x38428de0, - 0x38638e28, + 0x38a56d18, + 0x384291e8, + 0x38639230, 0x34040001, 0x78010003, 0x3044000f, 0x58650000, - 0x38218eac, + 0x382192b4, 0xfbfff21a, 0x2b8b002c, 0x2b8c0028, @@ -22726,7 +22974,7 @@ UINT32 FirmwareKB[] = { 0x5b9d0004, 0x78080003, 0xb9000800, - 0x38218de0, + 0x382191e8, 0x40220001, 0x78050003, 0x78030030, @@ -22814,14 +23062,14 @@ UINT32 FirmwareKB[] = { 0xb8250800, 0x58610000, 0x78020003, - 0x38846938, - 0x39088de0, - 0x38428e28, + 0x38846d18, + 0x390891e8, + 0x38429230, 0x34030001, 0x78010003, 0x3103000f, 0x58440000, - 0x38218eac, + 0x382192b4, 0xfbfff1a8, 0x2b9d0004, 0x379c0004, @@ -22867,7 +23115,7 @@ UINT32 FirmwareKB[] = { 0xbd655800, 0x78020003, 0x34030001, - 0x38428de0, + 0x384291e8, 0x3043001a, 0x584b0004, 0x34010007, @@ -22883,7 +23131,7 @@ UINT32 FirmwareKB[] = { 0x38428000, 0x58410054, 0x3401003c, - 0xfbffac92, + 0xfbffab9a, 0x2b8b0008, 0x2b9d0004, 0x379c0008, @@ -22892,11 +23140,11 @@ UINT32 FirmwareKB[] = { 0x5b9d0004, 0x78010003, 0x34030000, - 0x38218de0, + 0x382191e8, 0x58230004, 0x3023001a, 0x3401003c, - 0xfbffacb2, + 0xfbffabba, 0x34010007, 0xfbfff2a8, 0x34010001, @@ -22913,7 +23161,7 @@ UINT32 FirmwareKB[] = { 0x78060003, 0xbc221800, 0x3884f320, - 0x38c68de0, + 0x38c691e8, 0x34050000, 0x3409001f, 0x3408ffdf, @@ -22945,7 +23193,7 @@ UINT32 FirmwareKB[] = { 0x5b9d0004, 0x780d0003, 0xb9a02800, - 0x38a58de0, + 0x38a591e8, 0x40a80001, 0x78010003, 0x3821f00c, @@ -22970,21 +23218,21 @@ UINT32 FirmwareKB[] = { 0xe0000010, 0x78020003, 0x78010003, - 0x38428e28, - 0x38216214, + 0x38429230, + 0x382165f4, 0xe000000a, 0x78020003, 0x78010003, - 0x38428e28, - 0x38215c3c, + 0x38429230, + 0x3821601c, 0xe0000005, 0x78020003, 0x78010003, - 0x38428e28, - 0x38215f38, + 0x38429230, + 0x38216318, 0x58410000, 0xb8e01000, - 0x38428de0, + 0x384291e8, 0x34030001, 0x78010003, 0x3043000f, @@ -23101,7 +23349,7 @@ UINT32 FirmwareKB[] = { 0x20890001, 0xb9a01800, 0x34020000, - 0x38638de0, + 0x386391e8, 0x7d210001, 0x30620017, 0xb8406000, @@ -23111,7 +23359,7 @@ UINT32 FirmwareKB[] = { 0xb9000800, 0xfbfffee5, 0xb9a00800, - 0x38218de0, + 0x382191e8, 0x34030000, 0x34020001, 0x30230014, @@ -23122,7 +23370,7 @@ UINT32 FirmwareKB[] = { 0x3062001a, 0x58620004, 0x3401003c, - 0xfbffabd0, + 0xfbffaad8, 0x34010007, 0xfbfff1c6, 0x34010001, @@ -23133,7 +23381,7 @@ UINT32 FirmwareKB[] = { 0x90005800, 0xd00c0000, 0xb9a01000, - 0x38428de0, + 0x384291e8, 0x40430012, 0x44600006, 0x34010000, @@ -23146,11 +23394,11 @@ UINT32 FirmwareKB[] = { 0xb8606000, 0xd00b0000, 0x34010000, - 0x39ad8de0, + 0x39ad91e8, 0x31a10012, 0x78040003, 0xb8801000, - 0x38428de0, + 0x384291e8, 0x34010000, 0x30410011, 0x7dc30001, @@ -23158,19 +23406,19 @@ UINT32 FirmwareKB[] = { 0x78020003, 0x5c610005, 0x78010003, - 0x38428e28, - 0x382140b4, + 0x38429230, + 0x38214494, 0xe0000004, 0x78010003, - 0x38428e28, - 0x3821494c, + 0x38429230, + 0x38214d2c, 0x58410000, 0x5ca00007, - 0x38848de0, + 0x388491e8, 0x34020001, 0x78010003, 0x3082000f, - 0x38218eac, + 0x382192b4, 0xfbfff04b, 0x2b8b0014, 0x2b8c0010, @@ -23184,7 +23432,7 @@ UINT32 FirmwareKB[] = { 0x5b8c0008, 0x5b9d0004, 0x780b0003, - 0x396b8de0, + 0x396b91e8, 0x416c0001, 0x3581ffcc, 0x202100ff, @@ -23331,7 +23579,7 @@ UINT32 FirmwareKB[] = { 0x6901001f, 0x4420ffb5, 0x78010003, - 0x38218de0, + 0x382191e8, 0x78020003, 0x582a0008, 0x3842f318, @@ -23385,8 +23633,8 @@ UINT32 FirmwareKB[] = { 0x78010003, 0xfd686000, 0xfce83000, - 0x38638de0, - 0x38218eac, + 0x386391e8, + 0x382192b4, 0x20a500ff, 0x78040003, 0x78020003, @@ -23397,16 +23645,16 @@ UINT32 FirmwareKB[] = { 0x78010003, 0x38a5f320, 0x34030000, - 0x38218eac, + 0x382192b4, 0x5cc30008, - 0x38428de0, + 0x384291e8, 0x30470010, 0x28a20000, 0x38420040, 0x58a20000, 0xfbffef62, 0xe0000007, - 0x38428de0, + 0x384291e8, 0x30430010, 0x28a10000, 0x3402ffbf, @@ -23414,11 +23662,11 @@ UINT32 FirmwareKB[] = { 0x58a10000, 0x78020003, 0x78010003, - 0x38428de0, + 0x384291e8, 0x5d800005, 0x304b001b, 0x304b000e, - 0x38218eac, + 0x382192b4, 0xfbffef53, 0xd00d0000, 0x2b8b0010, @@ -23435,7 +23683,7 @@ UINT32 FirmwareKB[] = { 0x5b8f0008, 0x5b9d0004, 0x3401003c, - 0xfbffaa97, + 0xfbffa99f, 0x34010007, 0xfbfff08d, 0x340d0001, @@ -23445,15 +23693,15 @@ UINT32 FirmwareKB[] = { 0x780c0003, 0x59610054, 0x340e0000, - 0x398c8de0, + 0x398c91e8, 0x3401001a, 0x598e0004, 0x318e001a, - 0xfbffaa89, + 0xfbffa991, 0x3da2001a, 0x34010019, 0x59620050, - 0xfbffaa85, + 0xfbffa98d, 0x3da10019, 0x78040003, 0x59610050, @@ -23506,7 +23754,7 @@ UINT32 FirmwareKB[] = { 0x38210000, 0xa0411000, 0x00420010, - 0x38a58de0, + 0x38a591e8, 0x78010003, 0x58a20030, 0x3821f314, @@ -23620,7 +23868,7 @@ UINT32 FirmwareKB[] = { 0x3821c001, 0x358c0034, 0x780e0003, - 0x39ce8de0, + 0x39ce91e8, 0x58410000, 0x218300ff, 0xb9a02000, @@ -23634,25 +23882,25 @@ UINT32 FirmwareKB[] = { 0xb8431000, 0x78030003, 0x58820000, - 0x38638acc, - 0x28620048, + 0x38638ed0, + 0x2862004c, 0x7801fffe, 0x3821ffff, 0xa0411000, 0x38420001, 0x7801c201, - 0x58620048, + 0x5862004c, 0x3821c50c, - 0xfbffdb02, + 0xfbffdad7, 0x3401001a, - 0xfbffa998, + 0xfbffa8a0, 0x340d0001, 0x3da1001a, 0x780b8000, 0x396b8000, 0x59610050, 0x34010019, - 0xfbffa991, + 0xfbffa899, 0x3da10019, 0x34040000, 0x59610050, @@ -23696,7 +23944,7 @@ UINT32 FirmwareKB[] = { 0x5b8c0008, 0x5b9d0004, 0x3401003c, - 0xfbffa992, + 0xfbffa89a, 0x340c0001, 0x3d81001c, 0x780b8000, @@ -23705,11 +23953,11 @@ UINT32 FirmwareKB[] = { 0x34010007, 0xfbffef83, 0x3401001a, - 0xfbffa989, + 0xfbffa891, 0x3d82001a, 0x34010019, 0x59620050, - 0xfbffa985, + 0xfbffa88d, 0x3d810019, 0x7803c210, 0x59610050, @@ -23717,7 +23965,7 @@ UINT32 FirmwareKB[] = { 0x38630008, 0x78010003, 0x58620000, - 0x38218de0, + 0x382191e8, 0x78050003, 0x302c0011, 0x3022000c, @@ -23751,14 +23999,14 @@ UINT32 FirmwareKB[] = { 0x5b9d0004, 0x78010003, 0x34020000, - 0x38218eac, + 0x382192b4, 0xfbffee3d, 0x90002000, 0x34010000, 0xd0010000, 0x780b0003, 0xb9601000, - 0x38428de0, + 0x384291e8, 0x4043000d, 0x3041000d, 0xd0040000, @@ -23768,7 +24016,7 @@ UINT32 FirmwareKB[] = { 0x90002000, 0xd0030000, 0xb9601000, - 0x38428de0, + 0x384291e8, 0x4043000e, 0x34010000, 0x3041000e, @@ -23777,28 +24025,28 @@ UINT32 FirmwareKB[] = { 0xfbfffea5, 0x78030003, 0x78020003, - 0x396b8de0, - 0x38638e28, - 0x38426570, + 0x396b91e8, + 0x38639230, + 0x38426950, 0x34040001, 0x4420ffe0, 0x78010003, 0x58620000, 0x3164000f, - 0x38218eac, + 0x382192b4, 0xfbffede4, 0xe3ffffda, 0x90002000, 0xd0030000, 0xb9600800, - 0x38218de0, + 0x382191e8, 0x4023000f, 0x34020000, 0x3022000f, 0xd0040000, 0x78010003, - 0x38218e28, - 0x396b8de0, + 0x38219230, + 0x396b91e8, 0x4462ffce, 0x28210000, 0x3162000f, @@ -23833,7 +24081,7 @@ UINT32 FirmwareKB[] = { 0x58a10000, 0x28a20000, 0x78010003, - 0x38218de0, + 0x382191e8, 0x38420008, 0x58a20000, 0x28a20000, @@ -24228,7 +24476,7 @@ UINT32 FirmwareKB[] = { 0x34020004, 0x780b0003, 0xf8000025, - 0x396b871c, + 0x396b8b20, 0xb42b0800, 0xb42c0800, 0x40220000, @@ -24266,7 +24514,7 @@ UINT32 FirmwareKB[] = { 0xe3fffff2, 0x2042001f, 0x78030003, - 0x3863881c, + 0x38638c20, 0xb4421000, 0xb4421000, 0xb4621800, @@ -24306,7 +24554,7 @@ UINT32 FirmwareKB[] = { 0xc3a00000, 0x2042001f, 0x78030003, - 0x3863889c, + 0x38638ca0, 0xb4421000, 0xb4421000, 0xb4621800, @@ -24346,7 +24594,7 @@ UINT32 FirmwareKB[] = { 0xc3a00000, 0x2042001f, 0x78030003, - 0x3863891c, + 0x38638d20, 0xb4421000, 0xb4421000, 0xb4621800, @@ -24486,107 +24734,107 @@ UINT32 FirmwareKB[] = { 0x80000064, 0x80000124, 0xc2100004, - 0x00029070, - 0x00029070, - 0x000293b8, - 0x000294e0, - 0x00029704, - 0x000298d0, - 0x0002a4e4, - 0x00029a74, - 0x0002a4a4, - 0x0002a1a8, + 0x000290b0, + 0x000290b0, + 0x000293f8, + 0x00029520, + 0x00029744, + 0x00029930, + 0x0002a638, + 0x00029ad4, + 0x0002a5f8, + 0x0002a2fc, 0x000282ac, 0x000282ac, - 0x00029364, - 0x000293c0, - 0x00029544, - 0x00029780, - 0x0002a4e4, - 0x00029908, - 0x0002a35c, - 0x00029b0c, + 0x000293a4, + 0x00029400, + 0x00029584, + 0x000297c0, + 0x0002a638, + 0x00029968, + 0x0002a4b0, + 0x00029b6c, 0x000282f8, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, 0x00028300, 0x00028308, 0x00028310, 0x00028318, 0x00028320, 0x00028328, - 0x0002904c, - 0x0002904c, + 0x0002908c, + 0x0002908c, 0x00028330, 0x00028338, 0x00028340, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, 0x00028348, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, 0x00028350, 0x00028358, 0x00028360, 0x00028398, 0x000283a0, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, 0x000283a8, 0x000283b4, 0x000283c0, @@ -24597,29 +24845,21 @@ UINT32 FirmwareKB[] = { 0x00028420, 0x00028428, 0x00028430, - 0x0002904c, - 0x0002904c, + 0x0002908c, + 0x0002908c, 0x00028444, 0x0002844c, - 0x0002904c, + 0x0002908c, 0x00028458, 0x00028460, - 0x00028548, - 0x00028564, - 0x00028580, 0x00028588, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x00028590, - 0x00028598, - 0x000285a0, - 0x000285a8, - 0x000285b0, - 0x000285b8, + 0x000285a4, 0x000285c0, 0x000285c8, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, 0x000285d0, 0x000285d8, 0x000285e0, @@ -24635,376 +24875,393 @@ UINT32 FirmwareKB[] = { 0x00028630, 0x00028638, 0x00028640, - 0x0002864c, + 0x00028648, + 0x00028650, + 0x00028658, + 0x00028660, 0x00028668, 0x00028670, 0x00028678, 0x00028680, - 0x00028688, - 0x0002904c, - 0x0002904c, - 0x00028690, - 0x00028698, - 0x000286a0, + 0x0002868c, 0x000286a8, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, 0x000286b0, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, 0x000286b8, - 0x000286cc, - 0x00028714, - 0x00028dec, - 0x00028df4, - 0x00028e4c, - 0x00028e54, - 0x00028e5c, - 0x00028e64, - 0x0002904c, - 0x0002904c, - 0x00028ea0, - 0x0002904c, - 0x0002904c, - 0x000284a0, - 0x000284a8, - 0x00028ee4, - 0x00028eec, - 0x00028ef4, - 0x00028efc, - 0x00028f04, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x00028f0c, - 0x00028f14, - 0x00028f1c, + 0x000286c0, + 0x000286c8, + 0x0002908c, + 0x0002908c, + 0x000286d0, + 0x000286d8, + 0x000286e0, + 0x000286e8, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x000286f0, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x000286f8, + 0x0002870c, + 0x00028754, + 0x00028e2c, + 0x00028e34, + 0x00028e8c, + 0x00028e94, + 0x00028e9c, + 0x00028ea4, + 0x0002908c, + 0x0002908c, + 0x00028ee0, + 0x0002908c, + 0x0002908c, + 0x000284c0, + 0x000284c8, 0x00028f24, 0x00028f2c, 0x00028f34, 0x00028f3c, - 0x0002904c, - 0x0002904c, - 0x000287a0, - 0x00028e6c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x00028a74, - 0x00028cc4, - 0x0002904c, - 0x00028b9c, - 0x00028b10, - 0x00028d60, - 0x0002904c, - 0x00028c38, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002843c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x000284e8, - 0x000284f0, - 0x00028508, - 0x00028510, - 0x0002904c, - 0x00028518, - 0x00028530, 0x00028f44, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x00028f4c, + 0x00028f54, + 0x00028f5c, 0x00028f64, - 0x00028f88, + 0x00028f6c, + 0x00028f74, + 0x00028f7c, + 0x0002908c, + 0x0002908c, + 0x000287e0, + 0x00028eac, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x00028ab4, + 0x00028d04, + 0x0002908c, + 0x00028bdc, + 0x00028b50, + 0x00028da0, + 0x0002908c, + 0x00028c78, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002843c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x00028528, + 0x00028530, + 0x00028548, + 0x00028550, + 0x0002908c, + 0x00028558, + 0x00028570, + 0x00028f84, 0x00028fa4, - 0x00028fc0, - 0x00028954, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x00029054, - 0x00029054, - 0x00028738, - 0x0002876c, - 0x0002904c, - 0x0002904c, - 0x000287d4, - 0x00028808, - 0x00028aa8, - 0x00028adc, - 0x00028bd0, - 0x00028c04, - 0x0002904c, - 0x0002904c, - 0x00028cf8, - 0x00028d2c, - 0x0002883c, - 0x00028a14, + 0x00028fc8, + 0x00028fe4, + 0x00029000, + 0x00028994, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x00029094, + 0x00029094, + 0x00028778, + 0x000287ac, + 0x0002908c, + 0x0002908c, + 0x00028814, + 0x00028848, + 0x00028ae8, + 0x00028b1c, + 0x00028c10, + 0x00028c44, + 0x0002908c, + 0x0002908c, + 0x00028d38, + 0x00028d6c, + 0x0002887c, + 0x00028a54, + 0x00028a7c, + 0x0002908c, + 0x0002908c, + 0x0002892c, 0x00028a3c, - 0x0002904c, - 0x0002904c, - 0x000288ec, - 0x000289fc, - 0x00028b70, - 0x00028c98, - 0x0002904c, - 0x00028dc0, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x00029010, - 0x0002901c, - 0x00029024, + 0x00028bb0, + 0x00028cd8, + 0x0002908c, + 0x00028e00, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x00029050, + 0x0002905c, + 0x00029064, + 0x00029070, + 0x00029040, + 0x00029048, + 0x00028aa0, + 0x0002908c, + 0x00028980, + 0x00028bc8, + 0x00028cf0, + 0x0002908c, + 0x00028e18, + 0x0002908c, + 0x00028718, + 0x00028738, + 0x00029078, + 0x00029020, + 0x00029028, 0x00029030, - 0x00029000, - 0x00029008, - 0x00028a60, - 0x0002904c, - 0x00028940, - 0x00028b88, - 0x00028cb0, - 0x0002904c, - 0x00028dd8, - 0x0002904c, - 0x000286d8, - 0x000286f8, 0x00029038, - 0x00028fe0, - 0x00028fe8, - 0x00028ff0, - 0x00028ff8, - 0x0002904c, - 0x0002904c, - 0x0002904c, - 0x00029040, + 0x0002908c, + 0x0002908c, + 0x0002908c, + 0x00029080, 0x00800092, 0x00a300b6, 0x00c800da, 0x00ec0100, - 0x00029884, - 0x0002989c, - 0x000297b8, - 0x000298b8, - 0x000297cc, - 0x00029814, - 0x000298b4, - 0x00029b4c, - 0x0002a184, - 0x0002a184, - 0x0002a184, - 0x0002a184, - 0x0002a184, - 0x0002a184, - 0x0002a184, - 0x00029da4, - 0x0002a184, - 0x0002a184, - 0x00029bd0, - 0x0002a184, - 0x00029cac, - 0x0002a184, - 0x0002a184, - 0x0002a184, - 0x0002a184, - 0x0002a184, - 0x0002a184, - 0x0002a184, - 0x0002a18c, - 0x0002a184, - 0x0002a184, - 0x00029b54, - 0x00029bb8, - 0x00029b6c, - 0x00029e04, - 0x00029e58, - 0x00029dc4, - 0x00029de4, - 0x0002a184, - 0x0002a184, - 0x0002a184, - 0x0002a184, - 0x0002a140, - 0x0002a18c, - 0x0002a18c, - 0x0002a18c, - 0x0002a18c, - 0x0002a184, - 0x0002a184, - 0x0002a184, - 0x0002a184, - 0x0002a184, - 0x00029c54, - 0x00029c74, - 0x00029b84, - 0x00029b9c, - 0x0002a184, - 0x0002a184, - 0x0002a184, - 0x0002a184, - 0x0002a184, - 0x0002a184, - 0x00029fd8, - 0x0002a018, - 0x00029fa8, - 0x00029f48, - 0x00029f78, - 0x0002a184, - 0x0002a184, - 0x0002a184, - 0x0002a184, - 0x0002a184, - 0x0002a184, - 0x0002a18c, - 0x0002a05c, - 0x0002a078, - 0x00029bf8, - 0x00029c10, - 0x0002a184, - 0x0002a184, - 0x0002a110, - 0x0002a128, - 0x00029e8c, - 0x0002a184, - 0x0002a184, - 0x0002a184, - 0x0002a0e0, - 0x0002a094, - 0x0002a0b4, + 0x000298e4, + 0x000298fc, + 0x000297f8, + 0x00029918, + 0x0002980c, + 0x00029854, + 0x00029914, + 0x00029bb4, + 0x0002a2d8, + 0x0002a2d8, + 0x0002a2d8, + 0x0002a2d8, + 0x0002a2d8, + 0x0002a2d8, + 0x0002a2d8, + 0x00029ef8, + 0x0002a2d8, + 0x0002a2d8, + 0x00029c38, + 0x0002a2d8, + 0x00029e00, + 0x0002a2d8, + 0x0002a2d8, + 0x0002a2d8, + 0x0002a2d8, + 0x0002a2d8, + 0x0002a2d8, + 0x0002a2d8, + 0x0002a2e0, + 0x0002a2d8, + 0x0002a2d8, + 0x00029bbc, + 0x00029c20, + 0x00029bd4, + 0x00029f58, + 0x00029fac, + 0x00029f18, + 0x00029f38, + 0x0002a2d8, + 0x0002a2d8, + 0x0002a2d8, + 0x0002a2d8, + 0x0002a294, + 0x0002a2e0, + 0x0002a2e0, + 0x0002a2e0, + 0x0002a2e0, + 0x0002a2d8, + 0x0002a2d8, + 0x0002a2d8, + 0x0002a2d8, + 0x0002a2d8, + 0x00029da8, + 0x00029dc8, + 0x00029bec, + 0x00029c04, + 0x0002a2d8, + 0x0002a2d8, + 0x0002a2d8, + 0x0002a2d8, + 0x0002a2d8, + 0x0002a2d8, + 0x0002a12c, + 0x0002a16c, + 0x0002a0fc, + 0x0002a09c, 0x0002a0cc, - 0x0002a0d4, - 0x0002a148, - 0x0002a158, - 0x0002a17c, - 0x00029d04, - 0x00029d90, - 0x00029c28, - 0x0002c058, - 0x0002c148, - 0x0002c084, - 0x0002c148, - 0x0002c0b0, - 0x0002c148, - 0x0002c0dc, - 0x0002c148, - 0x0002c030, + 0x0002a2d8, + 0x0002a2d8, + 0x0002a2d8, + 0x0002a2d8, + 0x0002a2d8, + 0x0002a2d8, + 0x0002a2e0, + 0x0002a1b0, + 0x0002a1cc, + 0x00029c60, + 0x00029c78, + 0x0002a2d8, + 0x0002a2d8, + 0x0002a264, + 0x0002a27c, + 0x00029fe0, + 0x0002a2d8, + 0x0002a2d8, + 0x0002a2d8, + 0x0002a234, + 0x0002a1e8, + 0x0002a208, + 0x0002a220, + 0x0002a228, + 0x0002a29c, + 0x0002a2ac, + 0x0002a2d0, + 0x00029e58, + 0x00029ee4, + 0x00029c90, + 0x00029cbc, + 0x00029d08, + 0x00029d1c, + 0x00029d30, + 0x00029d44, + 0x00029d58, + 0x00029d6c, + 0x00029d80, + 0x00029d94, + 0x0002c1cc, + 0x0002c2bc, + 0x0002c1f8, + 0x0002c2bc, + 0x0002c224, + 0x0002c2bc, + 0x0002c250, + 0x0002c2bc, + 0x0002c1a4, 0x013014ab, 0x013014b6, 0x013014ac, @@ -25015,83 +25272,83 @@ UINT32 FirmwareKB[] = { 0x00e70019, 0xf6fcfe00, 0x02040608, - 0x0002f430, - 0x0002f438, - 0x0002f440, - 0x0002f448, - 0x0002f450, - 0x0002f458, - 0x0002f460, - 0x0002f468, - 0x0002f470, - 0x0002f478, - 0x0002f480, - 0x0002f488, - 0x0002f490, + 0x0002f73c, + 0x0002f744, + 0x0002f74c, + 0x0002f754, + 0x0002f75c, + 0x0002f764, + 0x0002f76c, + 0x0002f774, + 0x0002f77c, + 0x0002f784, + 0x0002f78c, + 0x0002f794, + 0x0002f79c, 0xff000100, 0x02000100, 0x03000100, 0x02000100, - 0x00033528, - 0x00033554, - 0x00033568, - 0x00033578, - 0x00033584, - 0x0003433c, - 0x0003433c, - 0x0003433c, - 0x0003433c, - 0x0003433c, - 0x0003433c, - 0x0003433c, - 0x0003433c, - 0x00034360, - 0x00034360, - 0x00034360, - 0x00034360, - 0x00034390, - 0x00034440, - 0x00034464, - 0x000344a0, - 0x000344d0, - 0x000344dc, - 0x000344dc, - 0x000344dc, - 0x000344dc, - 0x00034524, - 0x00034524, - 0x00034524, - 0x00034524, - 0x000346c0, - 0x00034b3c, - 0x00034b5c, - 0x00034ba4, - 0x00034bd8, - 0x00034be4, - 0x00034be4, - 0x00034be4, - 0x00034be4, - 0x00034c20, - 0x00034c20, - 0x00034c20, - 0x00034c20, - 0x00034c94, - 0x00035ac4, - 0x00035ac4, - 0x00035acc, - 0x00035ad4, - 0x00035adc, - 0x00035ae4, - 0x00035aec, - 0x00035ac4, - 0x00035af8, - 0x00035b20, - 0x00035b38, - 0x00035b4c, - 0x00035b78, - 0x00035bc8, - 0x00035be0, - 0x00035bec, + 0x00033908, + 0x00033934, + 0x00033948, + 0x00033958, + 0x00033964, + 0x0003471c, + 0x0003471c, + 0x0003471c, + 0x0003471c, + 0x0003471c, + 0x0003471c, + 0x0003471c, + 0x0003471c, + 0x00034740, + 0x00034740, + 0x00034740, + 0x00034740, + 0x00034770, + 0x00034820, + 0x00034844, + 0x00034880, + 0x000348b0, + 0x000348bc, + 0x000348bc, + 0x000348bc, + 0x000348bc, + 0x00034904, + 0x00034904, + 0x00034904, + 0x00034904, + 0x00034aa0, + 0x00034f1c, + 0x00034f3c, + 0x00034f84, + 0x00034fb8, + 0x00034fc4, + 0x00034fc4, + 0x00034fc4, + 0x00034fc4, + 0x00035000, + 0x00035000, + 0x00035000, + 0x00035000, + 0x00035074, + 0x00035ea4, + 0x00035ea4, + 0x00035eac, + 0x00035eb4, + 0x00035ebc, + 0x00035ec4, + 0x00035ecc, + 0x00035ea4, + 0x00035ed8, + 0x00035f00, + 0x00035f18, + 0x00035f2c, + 0x00035f58, + 0x00035fa8, + 0x00035fc0, + 0x00035fcc, 0x00000000, 0x00000000, 0x00000000, @@ -25156,102 +25413,102 @@ UINT32 FirmwareKB[] = { 0x03030202, 0x01010101, 0x01010101, - 0x00037ac8, - 0x00037ac4, - 0x00037ac0, - 0x00037abc, - 0x00037ab8, - 0x00037ab4, - 0x00037ab0, - 0x00037aac, - 0x00037aa8, - 0x00037aa4, - 0x00037aa0, - 0x00037a9c, - 0x00037a98, - 0x00037a94, - 0x00037a90, - 0x00037a8c, - 0x00037a88, - 0x00037a84, - 0x00037a80, - 0x00037a7c, - 0x00037a78, - 0x00037a74, - 0x00037a70, - 0x00037a6c, - 0x00037a68, - 0x00037a64, - 0x00037a60, - 0x00037a5c, - 0x00037a58, - 0x00037a54, - 0x00037a50, - 0x00037a4c, - 0x00037b68, - 0x00037b64, - 0x00037b60, - 0x00037b5c, - 0x00037b58, - 0x00037b54, - 0x00037b50, - 0x00037b4c, - 0x00037b48, - 0x00037b44, - 0x00037b40, - 0x00037b3c, - 0x00037b38, - 0x00037b34, - 0x00037b30, - 0x00037b2c, - 0x00037b28, - 0x00037b24, - 0x00037b20, - 0x00037b1c, - 0x00037b18, - 0x00037b14, - 0x00037b10, - 0x00037b0c, - 0x00037b08, - 0x00037b04, - 0x00037b00, - 0x00037afc, - 0x00037af8, - 0x00037af4, - 0x00037af0, - 0x00037aec, - 0x00037c08, - 0x00037c04, - 0x00037c00, - 0x00037bfc, - 0x00037bf8, - 0x00037bf4, - 0x00037bf0, - 0x00037bec, - 0x00037be8, - 0x00037be4, - 0x00037be0, - 0x00037bdc, - 0x00037bd8, - 0x00037bd4, - 0x00037bd0, - 0x00037bcc, - 0x00037bc8, - 0x00037bc4, - 0x00037bc0, - 0x00037bbc, - 0x00037bb8, - 0x00037bb4, - 0x00037bb0, - 0x00037bac, - 0x00037ba8, - 0x00037ba4, - 0x00037ba0, - 0x00037b9c, - 0x00037b98, - 0x00037b94, - 0x00037b90, - 0x00037b8c, + 0x00037ea8, + 0x00037ea4, + 0x00037ea0, + 0x00037e9c, + 0x00037e98, + 0x00037e94, + 0x00037e90, + 0x00037e8c, + 0x00037e88, + 0x00037e84, + 0x00037e80, + 0x00037e7c, + 0x00037e78, + 0x00037e74, + 0x00037e70, + 0x00037e6c, + 0x00037e68, + 0x00037e64, + 0x00037e60, + 0x00037e5c, + 0x00037e58, + 0x00037e54, + 0x00037e50, + 0x00037e4c, + 0x00037e48, + 0x00037e44, + 0x00037e40, + 0x00037e3c, + 0x00037e38, + 0x00037e34, + 0x00037e30, + 0x00037e2c, + 0x00037f48, + 0x00037f44, + 0x00037f40, + 0x00037f3c, + 0x00037f38, + 0x00037f34, + 0x00037f30, + 0x00037f2c, + 0x00037f28, + 0x00037f24, + 0x00037f20, + 0x00037f1c, + 0x00037f18, + 0x00037f14, + 0x00037f10, + 0x00037f0c, + 0x00037f08, + 0x00037f04, + 0x00037f00, + 0x00037efc, + 0x00037ef8, + 0x00037ef4, + 0x00037ef0, + 0x00037eec, + 0x00037ee8, + 0x00037ee4, + 0x00037ee0, + 0x00037edc, + 0x00037ed8, + 0x00037ed4, + 0x00037ed0, + 0x00037ecc, + 0x00037fe8, + 0x00037fe4, + 0x00037fe0, + 0x00037fdc, + 0x00037fd8, + 0x00037fd4, + 0x00037fd0, + 0x00037fcc, + 0x00037fc8, + 0x00037fc4, + 0x00037fc0, + 0x00037fbc, + 0x00037fb8, + 0x00037fb4, + 0x00037fb0, + 0x00037fac, + 0x00037fa8, + 0x00037fa4, + 0x00037fa0, + 0x00037f9c, + 0x00037f98, + 0x00037f94, + 0x00037f90, + 0x00037f8c, + 0x00037f88, + 0x00037f84, + 0x00037f80, + 0x00037f7c, + 0x00037f78, + 0x00037f74, + 0x00037f70, + 0x00037f6c, 0x24002800, 0x3c002001, 0x12010e01, @@ -25272,22 +25529,22 @@ UINT32 FirmwareKB[] = { 0x00000000, 0x00021e74, 0x00021ec4, - 0x00031e20, + 0x00032200, 0x00000000, 0x00021a70, - 0x0002daf0, - 0x0002cd24, + 0x0002de24, + 0x0002cf40, 0x00000000, - 0x0002c47c, + 0x0002c5f0, 0x00000000, 0x00000000, - 0x0002cca4, - 0x0002bfc0, - 0x0002d9ec, + 0x0002cec0, + 0x0002c134, + 0x0002dd20, 0x00000000, 0x00000000, 0x00000000, - 0x0002d814, + 0x0002dabc, 0x00000000, 0x00021cac, 0x00021b1c, @@ -25348,6 +25605,7 @@ UINT32 FirmwareKB[] = { 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x0003f9e8, 0x0003fd00, 0x00024a68, @@ -31549,264 +31807,6 @@ UINT32 FirmwareKB[] = { 0x00000000, 0x00000000, 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, 0x000003ff, 0xfffffc00, 0x00000003, diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbTablesKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbTablesKB.c index 5c1fef2..2b8534b 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbTablesKB.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbTablesKB.c @@ -475,7 +475,7 @@ GNB_TABLE ROMDATA GnbMidInitTableKB [] = { 0x7 | 0x8 | 0xfff0, - ( 5 << 0) | + ( 4 << 0) | ( 0 << 3) | ( 0xF << 4) ), diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieEarlyInitKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieEarlyInitKB.c index 2199796..f0624d4 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieEarlyInitKB.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieEarlyInitKB.c @@ -244,7 +244,7 @@ PciePhyIsolationKB ( ); PhyRxIsoDis = GnbBuildOptions.CfgPciePhyIsolationEnable ? 0 : 3; - ActiveLaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE, 0, Wrapper); + ActiveLaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE, 0, Wrapper); if ((ActiveLaneBitmap & 0xF0) != 0) { PhyRxIsoDis = 3; } @@ -256,7 +256,7 @@ PciePhyIsolationKB ( WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8013_ADDRESS), Pcie ); - D0F0xE4_WRAP_8013.Field.PhyRxIsoDis = 3; + D0F0xE4_WRAP_8013.Field.PhyRxIsoDis = PhyRxIsoDis; PcieRegisterWrite ( Wrapper, WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8013_ADDRESS), @@ -264,7 +264,7 @@ PciePhyIsolationKB ( FALSE, Pcie ); - + IDS_HDT_CONSOLE (GNB_TRACE, " ActiveLaneBitmap = 0x%x, PhyRxIsoDis = %d\n", ActiveLaneBitmap, PhyRxIsoDis); IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyIsolationKB Exit\n"); } diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieMidInitKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieMidInitKB.c index ef07647..d1c39d3 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieMidInitKB.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieMidInitKB.c @@ -110,21 +110,77 @@ PcieMidPortInitCallbackKB ( PciePortProgramRegisterTable (PortInitMidTableKB.Table, PortInitMidTableKB.Length, Engine, TRUE, Pcie); if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS) || Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled) { PcieEnableSlotPowerLimitV5 (Engine, Pcie); + + // If StartLane == 4/7 and EndLane == 7/4, this is GFX port + if (!(((Engine->EngineData.StartLane == 4) && (Engine->EngineData.EndLane == 7)) || + ((Engine->EngineData.StartLane == 7) && (Engine->EngineData.EndLane == 4)))) { + // Only count active Gpp ports + *(UINT8 *)Buffer += 1; + } } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Callback to init ASPM on all active ports + * + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in, out] Buffer PortCount + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +STATIC +PcieMidAspmInitCallbackKB ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + + IDS_HDT_CONSOLE (GNB_TRACE, "PcieMidAspmInitCallbackKB Enter\n"); + + IDS_HDT_CONSOLE (GNB_TRACE, " PortCount = %02x\n", *(UINT8 *)Buffer); + // If StartLane == 4/7 and EndLane == 7/4, this is GFX port if (!(((Engine->EngineData.StartLane == 4) && (Engine->EngineData.EndLane == 7)) || ((Engine->EngineData.StartLane == 7) && (Engine->EngineData.EndLane == 4)))) { - // For GPP ports only set STRAP_MED_yTSx_COUNT=2 - PciePortRegisterRMW ( - Engine, - 0xC0, - 0x30, - 0x2 << 4, - TRUE, - Pcie - ); + // For GPP ports only set STRAP_MED_yTSx_COUNT=2, but only if active ports is > 2 + switch (*(UINT8 *)Buffer) { + case 0: + case 1: + break; + case 2: + PciePortRegisterRMW ( + Engine, + DxFxxE4_xA0_ADDRESS, + DxFxxE4_xA0_Reserved_26_25_MASK | + DxFxxE4_xA0_Reserved_28_28_MASK, + (0 << DxFxxE4_xA0_Reserved_26_25_OFFSET) | + (1 << DxFxxE4_xA0_Reserved_28_28_OFFSET), + TRUE, + Pcie + ); + break; + default: + PciePortRegisterRMW ( + Engine, + 0xC0, + 0x30, + 0x2 << 4, + TRUE, + Pcie + ); + break; + } } PcieEnableAspm (Engine, Pcie); + + IDS_HDT_CONSOLE (GNB_TRACE, "PcieMidAspmInitCallbackKB Exit\n"); } /*----------------------------------------------------------------------------------------*/ @@ -147,12 +203,22 @@ PcieMidPortInitKB ( { AGESA_STATUS Status; PCIE_LINK_SPEED_CAP GlobalSpeedCap; + UINT8 PortCount; + Status = AGESA_SUCCESS; + PortCount = 0; PcieConfigRunProcForAllEngines ( DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, PcieMidPortInitCallbackKB, - NULL, + &PortCount, + Pcie + ); + + PcieConfigRunProcForAllEngines ( + DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, + PcieMidAspmInitCallbackKB, + &PortCount, Pcie ); diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/DMI/mfDMI.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/DMI/mfDMI.c index af7bdaf..57cc491 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/DMI/mfDMI.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/DMI/mfDMI.c @@ -392,8 +392,8 @@ MemFDMISupport3 ( FormFactor = (UINT8) SpdDataStructure->Data[3]; if (((FormFactor & 0x0F) == 0x01) || ((FormFactor & 0x0F) == 0x02) || ((FormFactor & 0x0F) == 0x0B)) { DmiPhysicalDimmInfoTable->FormFactor = 0x09; // RDIMM or UDIMM or LRDIMM - } else if ((FormFactor & 0x0F) == 0x03) { - DmiPhysicalDimmInfoTable->FormFactor = 0x0D; // SO-DIMM + } else if (((FormFactor & 0x0F) == 0x03) || ((FormFactor & 0x0F) == 0x08) || ((FormFactor & 0x0F) == 0x09) || ((FormFactor & 0x0F) == 0x0A)) { + DmiPhysicalDimmInfoTable->FormFactor = 0x0D; // SO-DIMM, SO-UDIMM, SO-RDIMM and SO-CDIMM } else { DmiPhysicalDimmInfoTable->FormFactor = 0x02; // UNKNOWN } diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmMemRestore.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmMemRestore.c index 2cba133..3d80baf 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmMemRestore.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmMemRestore.c @@ -59,6 +59,7 @@ #include "S3.h" #include "mfs3.h" #include "heapManager.h" +#include "cpuFeatures.h" #include "cpuRegisters.h" #include "cpuPostInit.h" #include "cpuApicUtilities.h" @@ -491,6 +492,14 @@ MemMContextRestore ( MemFeatMain.MemClr (MemMainPtr); } } + // Set LockDramCfg, which must be done after Memory Clear + for (Node = 0; Node < MemMainPtr->DieCount; Node ++) { + if (IsFeatureEnabled (C6Cstate, MemMainPtr->MemPtr->PlatFormConfig, &(MemMainPtr->MemPtr->StdHeader))) { + IDS_SKIP_HOOK (IDS_LOCK_DRAM_CFG, &NBArray[Node], &MemMainPtr->MemPtr->StdHeader) { + NBArray[Node].SetBitField (&NBArray[Node], BFLockDramCfg, 1); + } + } + } } else { RefPtr->MemRestoreCtl = FALSE; } diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnkb.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnkb.c index dbc2de3..b76d9e8 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnkb.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnkb.c @@ -451,6 +451,7 @@ MemNInitNBDataKB ( NBPtr->FamilySpecificHook[DisableMemHoleMapping] = MemNDisableMemHoleMappingKB; NBPtr->FamilySpecificHook[RestoreMemHoleMapping] = MemNRestoreMemHoleMappingKB; NBPtr->FamilySpecificHook[PhyInitVref] = MemNPhyInitVrefKB; + NBPtr->FamilySpecificHook[IntermediateMemclkFreqVal] = MemNIntermediateMemclkFreqValUnb; IEM_INSERT_CODE (IEM_NBBLOCK_INIT, IemInitNBDataOverrideKB, (NBPtr)); } diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnphykb.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnphykb.c index 17a3779..be956bc 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnphykb.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnphykb.c @@ -938,6 +938,8 @@ MemNPhyPowerSavingMPstateKB ( UINT8 WrDqDqsEarly; UINT8 i; UINT8 j; + UINT16 MemClkSpeed; + MemClkSpeed = ( (NBPtr->MemPstate == MEMORY_PSTATE0) ? NBPtr->DCTPtr->Timings.Speed : MemNGetMemClkFreqUnb (NBPtr, (UINT8) MemNGetBitFieldNb (NBPtr, BFM1MemClkFreq)) ); // 3. Program D18F2x9C_x0D0F_0[F,8:0]30_dct[0][PwrDn] to disable the ECC lane if // D18F2x90_dct[0][DimmEccEn]==0. @@ -966,11 +968,11 @@ MemNPhyPowerSavingMPstateKB ( } // 11. Program D18F2x9C_x0D0F_0[F,7:0][50,10]_dct[1:0][EnRxPadStandby] = IF // (D18F2x94_dct[1:0][MemClkFreq] <= 800 MHz) THEN 1 ELSE 0 ENDIF. - MemNSetBitFieldNb (NBPtr, BFEnRxPadStandby, (NBPtr->DCTPtr->Timings.Speed <= DDR1600_FREQUENCY) ? 0x1000 : 0); + MemNSetBitFieldNb (NBPtr, BFEnRxPadStandby, (MemClkSpeed <= DDR1600_FREQUENCY) ? 0x1000 : 0); // 12. Program D18F2x9C_x0000_000D_dct[1:0]_mp[1:0] as follows: // If (DDR rate < = 1600) TxMaxDurDllNoLock = RxMaxDurDllNoLock = 8h // else TxMaxDurDllNoLock = RxMaxDurDllNoLock = 7h. - if (NBPtr->DCTPtr->Timings.Speed <= DDR1600_FREQUENCY) { + if (MemClkSpeed <= DDR1600_FREQUENCY) { MemNSetBitFieldNb (NBPtr, BFRxMaxDurDllNoLock, 8); MemNSetBitFieldNb (NBPtr, BFTxMaxDurDllNoLock, 8); } else { @@ -994,7 +996,7 @@ MemNPhyPowerSavingMPstateKB ( DllPower[i] = 0x8080; } // 13. If (DDR rate > = 1866) DllWakeTime = 1, Else DllWakeTime = 0. - DllWakeTime = (NBPtr->DCTPtr->Timings.Speed >= DDR1866_FREQUENCY) ? 1 : 0; + DllWakeTime = (MemClkSpeed >= DDR1866_FREQUENCY) ? 1 : 0; // Let MaxRxStggrDly = ((Tcl-1)*2) + MIN(DqsRcvEnGrossDelay for all byte lanes (see D18F2x9C_x0000_00[2A:10]_dct[1:0]_mp[1:0])) - 6. MinRcvEnGrossDly = NBPtr->TechPtr->GetMinMaxGrossDly (NBPtr->TechPtr, AccessRcvEnDly, FALSE); Tcl = (UINT8) MemNGetBitFieldNb (NBPtr, BFTcl); diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mns3kb.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mns3kb.c index 7c433ad..6ca3859 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mns3kb.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mns3kb.c @@ -185,6 +185,14 @@ MemS3ResumeConstructNBBlockKB ( IN UINT8 NodeID ); +VOID +MemNS3SetMemClkFreqValKB ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN OUT VOID *Value, + IN OUT VOID *ConfigPtr + ); + /*---------------------------------------------------------------------------- * DEFINITIONS AND MACROS * @@ -201,7 +209,7 @@ PCI_SPECIAL_CASE PciSpecialCaseFuncKB[] = { {MemNS3SaveNBRegisterUnb, MemNS3RestoreNBRegisterUnb}, {MemNS3GetBitFieldNb, MemNS3SetPreDriverCalUnb}, { (VOID (*) (ACCESS_WIDTH, PCI_ADDR, VOID *, VOID *)) memDefRet, MemNS3SetPhyStatusRegKB}, - { (VOID (*) (ACCESS_WIDTH, PCI_ADDR, VOID *, VOID *)) memDefRet, MemNS3SetMemClkFreqValUnb}, + { (VOID (*) (ACCESS_WIDTH, PCI_ADDR, VOID *, VOID *)) memDefRet, MemNS3SetMemClkFreqValKB}, {MemNS3ChangeMemPStateContextNb, MemNS3ChangeMemPStateContextNb}, {MemNS3GetBitFieldNb, MemNS3SetPhyFenceKB}, { (VOID (*) (ACCESS_WIDTH, PCI_ADDR, VOID *, VOID *)) memDefRet, MemNS3ReleaseNBPSUnb}, @@ -218,8 +226,8 @@ PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorKB[] = { {{0, 0, 0}, FUNC_1, 0x40, 0xFFFF0703}, {{0, 0, 0}, FUNC_1, 0x44, 0xFFFF0707}, {{0, 0, 0}, FUNC_1, 0xF0, 0xFF00FF83}, - {{0, 0, 0}, FUNC_1, 0x120, 0x00001FFF}, - {{0, 0, 0}, FUNC_1, 0x124, 0x00001FFF}, + {{0, 0, 0}, FUNC_1, 0x120, 0x001FFFFF}, + {{0, 0, 0}, FUNC_1, 0x124, 0x001FFFFF}, {{0, 0, 0}, FUNC_1, 0x200, 0x00FFF87B}, {{0, 0, 0}, FUNC_1, 0x204, 0x00FFF800}, {{0, 0, 0}, FUNC_2, 0x114, 0x00000200}, @@ -229,11 +237,7 @@ PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorKB[] = { {{0, 0, 0}, FUNC_2, 0x1B0, 0xFFD3FF3F}, {{0, 0, 0}, FUNC_2, 0x1B4, 0xFC7FFFFF}, {{0, 0, 0}, FUNC_2, 0x1BC, 0xFFFFFFFF}, - {{0, 0, 0}, FUNC_2, 0xA4, 0x00F07900}, - {{0, 0, 0}, FUNC_5, 0x240, 0xFFFFFFC1}, - {{0, 0, 0}, FUNC_5, 0x244, 0x0000FFFF}, - {{0, 0, 0}, FUNC_5, 0x248, 0xFFFFFFC0}, - {{0, 0, 0}, FUNC_5, 0x24C, 0x0000FFFF} + {{0, 0, 0}, FUNC_2, 0xA4, 0x00F07900} }; CONST PCI_REGISTER_BLOCK_HEADER ROMDATA S3PciPreSelfRefKB = { @@ -421,12 +425,16 @@ CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorKB[] = { {{1, 2, 1}, DCT0, BFRxDqInsDly, 0, DCT0_MASK, ANY_DIMM_MASK}, {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x10), 0x03FF03FF, DCT0_MASK, 0x01}, {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x11), 0x03FF03FF, DCT0_MASK, 0x01}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x12), 0x000003FF, DCT0_MASK, 0x01}, {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x13), 0x03FF03FF, DCT0_MASK, 0x04}, {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x14), 0x03FF03FF, DCT0_MASK, 0x04}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x15), 0x000003FF, DCT0_MASK, 0x04}, {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x16), 0x03FF03FF, DCT0_MASK, 0x10}, {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x17), 0x03FF03FF, DCT0_MASK, 0x10}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x18), 0x000003FF, DCT0_MASK, 0x10}, {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x19), 0x03FF03FF, DCT0_MASK, 0x40}, {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1A), 0x03FF03FF, DCT0_MASK, 0x40}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1B), 0x000003FF, DCT0_MASK, 0x40}, {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x20), 0x03FF03FF, DCT0_MASK, 0x01}, {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x21), 0x03FF03FF, DCT0_MASK, 0x01}, {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x23), 0x03FF03FF, DCT0_MASK, 0x04}, @@ -437,12 +445,16 @@ CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorKB[] = { {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x2A), 0x03FF03FF, DCT0_MASK, 0x40}, {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x01), 0xFFFFFFFF, DCT0_MASK, 0x01}, {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x02), 0xFFFFFFFF, DCT0_MASK, 0x01}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x03), 0x000000FF, DCT0_MASK, 0x01}, {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x101), 0xFFFFFFFF, DCT0_MASK, 0x04}, {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x102), 0xFFFFFFFF, DCT0_MASK, 0x04}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x103), 0x000000FF, DCT0_MASK, 0x04}, {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x201), 0xFFFFFFFF, DCT0_MASK, 0x10}, {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x202), 0xFFFFFFFF, DCT0_MASK, 0x10}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x203), 0x000000FF, DCT0_MASK, 0x10}, {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x301), 0xFFFFFFFF, DCT0_MASK, 0x40}, {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x302), 0xFFFFFFFF, DCT0_MASK, 0x40}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x303), 0x000000FF, DCT0_MASK, 0x40}, {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x05), 0x3E3E3E3E, DCT0_MASK, 0x01}, {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x06), 0x3E3E3E3E, DCT0_MASK, 0x01}, {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x105), 0x3E3E3E3E, DCT0_MASK, 0x04}, @@ -453,12 +465,16 @@ CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorKB[] = { {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x306), 0x3E3E3E3E, DCT0_MASK, 0x40}, {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x30), 0x00FF00FF, DCT0_MASK, 0x01}, {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x31), 0x00FF00FF, DCT0_MASK, 0x01}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x32), 0x000000FF, DCT0_MASK, 0x01}, {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x33), 0x00FF00FF, DCT0_MASK, 0x04}, {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x34), 0x00FF00FF, DCT0_MASK, 0x04}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x35), 0x000000FF, DCT0_MASK, 0x04}, {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x36), 0x00FF00FF, DCT0_MASK, 0x10}, {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x37), 0x00FF00FF, DCT0_MASK, 0x10}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x38), 0x000000FF, DCT0_MASK, 0x10}, {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x39), 0x00FF00FF, DCT0_MASK, 0x40}, {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3A), 0x00FF00FF, DCT0_MASK, 0x40}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3B), 0x000000FF, DCT0_MASK, 0x40}, {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x40), 0x00FF00FF, DCT0_MASK, 0x01}, {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x41), 0x00FF00FF, DCT0_MASK, 0x01}, {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x43), 0x00FF00FF, DCT0_MASK, 0x04}, @@ -493,12 +509,16 @@ CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorKB[] = { {{1, 2, 1}, DCT0, BFRxDqInsDly, 0, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x10), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x01}, {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x11), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x01}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x12), 0x000003FF, DCT0_MEMPSTATE_MASK, 0x01}, {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x13), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x04}, {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x14), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x04}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x15), 0x000003FF, DCT0_MEMPSTATE_MASK, 0x04}, {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x16), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x10}, {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x17), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x10}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x18), 0x000003FF, DCT0_MEMPSTATE_MASK, 0x10}, {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x19), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x40}, {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1A), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x40}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1B), 0x000003FF, DCT0_MEMPSTATE_MASK, 0x40}, {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x20), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x01}, {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x21), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x01}, {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x23), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x04}, @@ -509,12 +529,16 @@ CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorKB[] = { {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x2A), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x40}, {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x01), 0xFFFFFFFF, DCT0_MEMPSTATE_MASK, 0x01}, {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x02), 0xFFFFFFFF, DCT0_MEMPSTATE_MASK, 0x01}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x03), 0x000000FF, DCT0_MEMPSTATE_MASK, 0x01}, {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x101), 0xFFFFFFFF, DCT0_MEMPSTATE_MASK, 0x04}, {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x102), 0xFFFFFFFF, DCT0_MEMPSTATE_MASK, 0x04}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x103), 0x000000FF, DCT0_MEMPSTATE_MASK, 0x04}, {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x201), 0xFFFFFFFF, DCT0_MEMPSTATE_MASK, 0x10}, {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x202), 0xFFFFFFFF, DCT0_MEMPSTATE_MASK, 0x10}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x203), 0x000000FF, DCT0_MEMPSTATE_MASK, 0x10}, {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x301), 0xFFFFFFFF, DCT0_MEMPSTATE_MASK, 0x40}, {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x302), 0xFFFFFFFF, DCT0_MEMPSTATE_MASK, 0x40}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x303), 0x000000FF, DCT0_MEMPSTATE_MASK, 0x40}, {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x05), 0x3E3E3E3E, DCT0_MEMPSTATE_MASK, 0x01}, {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x06), 0x3E3E3E3E, DCT0_MEMPSTATE_MASK, 0x01}, {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x105), 0x3E3E3E3E, DCT0_MEMPSTATE_MASK, 0x04}, @@ -525,12 +549,16 @@ CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorKB[] = { {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x306), 0x3E3E3E3E, DCT0_MEMPSTATE_MASK, 0x40}, {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x30), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x01}, {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x31), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x01}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x32), 0x000000FF, DCT0_MEMPSTATE_MASK, 0x01}, {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x33), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x04}, {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x34), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x04}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x35), 0x000000FF, DCT0_MEMPSTATE_MASK, 0x04}, {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x36), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x10}, {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x37), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x10}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x38), 0x000000FF, DCT0_MEMPSTATE_MASK, 0x10}, {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x39), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x40}, {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3A), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x40}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3B), 0x000000FF, DCT0_MEMPSTATE_MASK, 0x40}, {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x40), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x01}, {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x41), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x01}, {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x43), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x04}, @@ -562,6 +590,10 @@ CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorKB[] = { {{1, 1, 1}, DCT0, BFVrefSel, 0x00000007, DCT0_MASK, ANY_DIMM_MASK}, {{1, 2, 1}, DCT0, BFVrefDAC, 0x000001F8, DCT0_MASK, ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_5, 0x240, 0xFFFFFFC1, ANY_DIMM_MASK, ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_5, 0x244, 0x0000FFFF, ANY_DIMM_MASK, ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_5, 0x248, 0xFFFFFFC0, ANY_DIMM_MASK, ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_5, 0x24C, 0x0000FFFF, ANY_DIMM_MASK, ANY_DIMM_MASK}, {{0, 0, 0}, FUNC_2, 0x1B4, 0x08000000, ANY_DIMM_MASK, ANY_DIMM_MASK}, {{0, 0, 0}, FUNC_3, 0x180, 0x02000000, ANY_DIMM_MASK, ANY_DIMM_MASK}, {{0, 0, 0}, FUNC_3, 0x58, 0x0000001F, ANY_DIMM_MASK, ANY_DIMM_MASK}, @@ -569,7 +601,7 @@ CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorKB[] = { {{0, 0, 0}, FUNC_3, 0x44, 0x00400004, ANY_DIMM_MASK, ANY_DIMM_MASK}, {{0, 0, 0}, FUNC_2, 0x118, 0x00040000, ANY_DIMM_MASK, ANY_DIMM_MASK}, - {{0, 0, 0}, FUNC_2, 0x118, 0x00080000, ANY_DIMM_MASK, ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x118, 0x00080000, ANY_DIMM_MASK, ANY_DIMM_MASK, S3_RESUME_MODE}, {{13, 3, 1}, DO_NOT_CARE, 0, DO_NOT_CARE, ANY_DIMM_MASK, ANY_DIMM_MASK} }; @@ -1256,3 +1288,59 @@ MemNS3SetPhyFenceKB ( MemNSetBitFieldNb (NBPtr, BFFence2, Fence2Reg); } } + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sets MemClkFreqVal bit, adding an intermediate frequency hop + * to 333Mhz before changing to the target DDR rate. This sequence is + * intended to mimic the initial boot frequency ramp. + * + * @param[in] AccessWidth - Access width of the register. + * @param[in] Address - address in PCI_ADDR format. + * @param[in, out] *Value - Pointer to the value to be written. + * @param[in, out] *ConfigPtr - Pointer to Config handle. + * @return none + */ +VOID +MemNS3SetMemClkFreqValKB ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN OUT VOID *Value, + IN OUT VOID *ConfigPtr + ) +{ + UINT32 TempValue; + UINT32 TempMemClk; + + // 1. Save the current MemClkFreq + MemNS3SaveNBRegisterUnb (AccessWidth, Address, &TempValue, ConfigPtr); + TempMemClk = TempValue; + + // 2. Program MemClkFreq = 200MHz, MemClkFreqVal = 1; + TempValue &= 0xFFFFFF00; + TempValue |= 0x82; + MemNS3RestoreNBRegisterUnb (AccessWidth, Address, &TempValue, ConfigPtr); + + // 3. Wait for FreqChgInPrg == 0 + MemNS3SaveNBRegisterUnb (AccessWidth, Address, &TempValue, ConfigPtr); + while ((TempValue & 0x200000) != 0) { + MemNS3SaveNBRegisterUnb (AccessWidth, Address, &TempValue, ConfigPtr); + } + + // 4. Program MemClkFreqVal = 0, Restore MemClkFreq + TempValue &= 0xFFFFFFEF; + MemNS3RestoreNBRegisterUnb (AccessWidth, Address, &TempMemClk, ConfigPtr); + + // 5. Program MemClkFreqVal = 1 + MemNS3SaveNBRegisterUnb (AccessWidth, Address, &TempValue, ConfigPtr); + TempValue |= 0x80; + MemNS3RestoreNBRegisterUnb (AccessWidth, Address, &TempValue, ConfigPtr); + + // 6. Wait for FreqChgInPrg = 0 + MemNS3SaveNBRegisterUnb (AccessWidth, Address, &TempValue, ConfigPtr); + while ((TempValue & 0x200000) != 0) { + MemNS3SaveNBRegisterUnb (AccessWidth, Address, &TempValue, ConfigPtr); + } +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mndct.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mndct.c index cefa8db..9499278 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mndct.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mndct.c @@ -367,6 +367,7 @@ MemNStartupDCTUnb ( for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { MemNSwitchDCTNb (NBPtr, Dct); if ((NBPtr->DCTPtr->Timings.DctMemSize != 0)) { + NBPtr->FamilySpecificHook[IntermediateMemclkFreqVal] (NBPtr, NULL); MemNSetBitFieldNb (NBPtr, BFMemClkFreqVal, 1); MemNPollBitFieldNb (NBPtr, BFFreqChgInProg, 0, PCI_ACCESS_TIMEOUT, FALSE); } diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mnphy.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mnphy.c index 773e7b2..356d4e3 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mnphy.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mnphy.c @@ -1152,6 +1152,8 @@ MemNPhyPowerSavingMPstateUnb ( UINT8 MaxTxStggrDly; UINT8 Tcwl; UINT8 i; + UINT16 MemClkSpeed; + MemClkSpeed = ( (NBPtr->MemPstate == MEMORY_PSTATE0) ? NBPtr->DCTPtr->Timings.Speed : MemNGetMemClkFreqUnb (NBPtr, (UINT8) MemNGetBitFieldNb (NBPtr, BFM1MemClkFreq)) ); IDS_HDT_CONSOLE (MEM_FLOW, "Start Phy power saving setting for memory Pstate %d\n", NBPtr->MemPstate); // 4. Program D18F2x9C_x0D0F_0[F,8:0]13_dct[1:0][DllDisEarlyU] = 1b. @@ -1172,11 +1174,11 @@ MemNPhyPowerSavingMPstateUnb ( } // 10. Program D18F2x9C_x0D0F_0[F,7:0][50,10]_dct[1:0][EnRxPadStandby] = IF // (D18F2x94_dct[1:0][MemClkFreq] <= 800 MHz) THEN 1 ELSE 0 ENDIF. - MemNSetBitFieldNb (NBPtr, BFEnRxPadStandby, (NBPtr->DCTPtr->Timings.Speed <= DDR1600_FREQUENCY) ? 0x1000 : 0); + MemNSetBitFieldNb (NBPtr, BFEnRxPadStandby, (MemClkSpeed <= DDR1600_FREQUENCY) ? 0x1000 : 0); // 11. Program D18F2x9C_x0000_000D_dct[1:0]_mp[1:0] as follows: // If (DDR rate < = 1600) TxMaxDurDllNoLock = RxMaxDurDllNoLock = 8h // else TxMaxDurDllNoLock = RxMaxDurDllNoLock = 7h. - if (NBPtr->DCTPtr->Timings.Speed <= DDR1600_FREQUENCY) { + if (MemClkSpeed <= DDR1600_FREQUENCY) { MemNSetBitFieldNb (NBPtr, BFTxMaxDurDllNoLock, 8); MemNSetBitFieldNb (NBPtr, BFRxMaxDurDllNoLock, 8); } else { @@ -1199,7 +1201,7 @@ MemNPhyPowerSavingMPstateUnb ( DllPower[i] = 0x8080; } // If (DDR rate > = 1866) DllWakeTime = 1, Else DllWakeTime = 0. - DllWakeTime = (NBPtr->DCTPtr->Timings.Speed >= DDR1866_FREQUENCY) ? 1 : 0; + DllWakeTime = (MemClkSpeed >= DDR1866_FREQUENCY) ? 1 : 0; // Let MaxRxStggrDly = (Tcl*2) + MIN(DqsRcvEnGrossDelay for all byte lanes (see D18F2x9C_x0000_00[2A:10]_dct[1:0]_mp[1:0])) - 4. MinRcvEnGrossDly = NBPtr->TechPtr->GetMinMaxGrossDly (NBPtr->TechPtr, AccessRcvEnDly, FALSE); ASSERT ((NBPtr->DCTPtr->Timings.CasL * 2 + MinRcvEnGrossDly) >= 4); @@ -1343,3 +1345,35 @@ MemN2DRdDQSEyeRimSearchUnb ( { return MemT2DRdDQSEyeRimSearch (NBPtr->TechPtr); } + +/*----------------------------------------------------------------------------- + * + * + * Hook for some families which need an intermediate Mem Clk Frequency Valid + * before changing to the initial startup training frequency. + * + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] *OptParam - Optional parameter + * + * @return TRUE - always + * ---------------------------------------------------------------------------- + */ +BOOLEAN +MemNIntermediateMemclkFreqValUnb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT VOID *OptParam + ) +{ + // 1. Program MemClkFreq = 200MHz + MemNSetBitFieldNb (NBPtr, BFMemClkFreq, MemNGetMemClkFreqIdUnb (NBPtr, DDR400_FREQUENCY)); + // 2. MemClkFreqVal = 1; + MemNSetBitFieldNb (NBPtr, BFMemClkFreqVal, 1); + // 3. Wait for FreqChgInPrg == 0 + MemNPollBitFieldNb (NBPtr, BFFreqChgInProg, 0, PCI_ACCESS_TIMEOUT, FALSE); + // 4. Program MemClkFreqVal = 0 + MemNSetBitFieldNb (NBPtr, BFMemClkFreqVal, 0); + // 5. Retore MemClkFreq to startup value. + MemNSetBitFieldNb (NBPtr, BFMemClkFreq, MemNGetMemClkFreqIdUnb (NBPtr, NBPtr->DCTPtr->Timings.Speed)); + return TRUE; +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/FT3/mpSkbft3.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/FT3/mpSkbft3.c index f04c4a3..7503417 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/FT3/mpSkbft3.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/FT3/mpSkbft3.c @@ -66,7 +66,6 @@ RDATA_GROUP (G2_PEI) *---------------------------------------------------------------------------- */ #define SOCKET_FT3_KB 0 - /*---------------------------------------------------------------------------- * TYPEDEFS AND STRUCTURES * @@ -84,12 +83,80 @@ RDATA_GROUP (G2_PEI) * *----------------------------------------------------------------------------- */ +// Slow mode, POdtOff, Address timing and Output drive compensation for FT3 +// Format : +// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, SlowMode, AddTmgCtl, ODC, POdtOff +// +STATIC CONST PSCFG_SAO_ENTRY KBUDdr3SAOFT3[] = { + {_1DIMM, DDR667 + DDR800, V1_5 + V1_35, DIMM_SR + DIMM_DR, NP, NP, 0, 0x00000000, 0x00002222, 0}, + {_1DIMM, DDR1066, V1_5 + V1_35, DIMM_SR, NP, NP, 0, 0x003D3D3D, 0x10002222, 0}, + {_1DIMM, DDR1066, V1_5 + V1_35, DIMM_DR, NP, NP, 0, 0x00000000, 0x10002222, 0}, + {_1DIMM, DDR1333, V1_5 + V1_35, DIMM_SR, NP, NP, 0, 0x003D3D3D, 0x20112222, 0}, + {_1DIMM, DDR1333, V1_5 + V1_35, DIMM_DR, NP, NP, 0, 0x00003D3D, 0x20112222, 0}, + {_1DIMM, DDR1600, V1_5 + V1_35, DIMM_SR, NP, NP, 0, 0x003C3C3C, 0x30332222, 0}, + {_1DIMM, DDR1600, V1_5 + V1_35, DIMM_DR, NP, NP, 1, 0x00003C3C, 0x30332222, 0}, + {_1DIMM, DDR1866, V1_5, DIMM_SR, NP, NP, 0, 0x003C3C3C, 0x30332222, 0}, + {_1DIMM, DDR1866, V1_5, DIMM_DR, NP, NP, 1, 0x00003C3C, 0x30332222, 0}, + {_2DIMM, DDR667 + DDR800, V1_5 + V1_35, NP, DIMM_SR + DIMM_DR, NP, 0, 0x00000000, 0x00002222, 0}, + {_2DIMM, DDR667, V1_5 + V1_35, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 1, 0x00000000, 0x10222323, 0}, + {_2DIMM, DDR800, V1_5 + V1_35, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 1, 0x00000000, 0x20222323, 0}, + {_2DIMM, DDR1066, V1_5 + V1_35, NP, DIMM_SR, NP, 0, 0x003D3D3D, 0x10002222, 0}, + {_2DIMM, DDR1066, V1_5 + V1_35, NP, DIMM_DR, NP, 0, 0x00000000, 0x10002222, 0}, + {_2DIMM, DDR1066 + DDR1333, V1_5 + V1_35, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 1, 0x00000000, 0x30222323, 0}, + {_2DIMM, DDR1333, V1_5 + V1_35, NP, DIMM_SR, NP, 0, 0x003D3D3D, 0x20112222, 0}, + {_2DIMM, DDR1333, V1_5 + V1_35, NP, DIMM_DR, NP, 0, 0x00003D3D, 0x20112222, 0}, + {_2DIMM, DDR1600, V1_5 + V1_35, NP, DIMM_SR, NP, 0, 0x003C3C3C, 0x30332222, 0}, + {_2DIMM, DDR1600, V1_5 + V1_35, NP, DIMM_DR, NP, 1, 0x00003C3C, 0x30332222, 0}, + {_2DIMM, DDR1600, V1_5, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 1, 0x00000000, 0x30222323, 0}, + {_2DIMM, DDR1600, V1_35, DIMM_SR, DIMM_SR, NP, 1, 0x00000000, 0x30222323, 0}, + {_2DIMM, DDR1866, V1_5, NP, DIMM_SR, NP, 0, 0x003C3C3C, 0x30332222, 0}, + {_2DIMM, DDR1866, V1_5, NP, DIMM_DR, NP, 1, 0x00003C3C, 0x30332222, 0}, +}; +CONST PSC_TBL_ENTRY KBSAOTblEntU3FT3 = { + {PSCFG_SAO, UDIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_16_KB, AMD_F16_ALL}, KB_SOCKET_FT3, DDR3_TECHNOLOGY}, + sizeof (KBUDdr3SAOFT3) / sizeof (PSCFG_SAO_ENTRY), + (VOID *)&KBUDdr3SAOFT3 +}; + +// Dram Term and Dynamic Dram Term for FT3 +// Format : +// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, Dimm, Rank, RttNom, RttWr +// +// RttNom: +// 0 On die termination disabled +// 1 60ohms +// 2 120ohms +// 3 40ohms +// 4 20ohms +// 5 30ohms +// RttWr: +// 0 Dynamic termination for writes disabled. +// 1 60ohms +// 2 120ohms +STATIC CONST PSCFG_RTT_ENTRY DramTermKBUDIMMFT3[] = { + {_1DIMM, DDR667 + DDR800 + DDR1066, V1_5 + V1_35, DIMM_SR + DIMM_DR, NP, NP, DIMM_SR + DIMM_DR, R0 + R1, 2, 0}, + {_1DIMM, DDR1333 + DDR1600, V1_5 + V1_35, DIMM_SR + DIMM_DR, NP, NP, DIMM_SR + DIMM_DR, R0 + R1, 1, 0}, + {_1DIMM, DDR1866, V1_5, DIMM_SR + DIMM_DR, NP, NP, DIMM_SR + DIMM_DR, R0 + R1, 1, 0}, + {_2DIMM, DDR667 + DDR800 + DDR1066, V1_5 + V1_35, NP, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 2, 0}, + {_2DIMM, DDR667 + DDR800, V1_5 + V1_35, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 3, 2}, + {_2DIMM, DDR1066 + DDR1333, V1_5 + V1_35, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 5, 2}, + {_2DIMM, DDR1333 + DDR1600, V1_5 + V1_35, NP, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 1, 0}, + {_2DIMM, DDR1600, V1_5, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 4, 1}, + {_2DIMM, DDR1600, V1_35, DIMM_SR, DIMM_SR, NP, DIMM_SR + DIMM_DR, R0 + R1, 4, 1}, + {_2DIMM, DDR1866, V1_5, NP, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 1, 0}, +}; +CONST PSC_TBL_ENTRY KBDramTermTblEntUFT3 = { + {PSCFG_RTT, UDIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_16_KB, AMD_F16_ALL}, KB_SOCKET_FT3, DDR3_TECHNOLOGY}, + sizeof (DramTermKBUDIMMFT3) / sizeof (PSCFG_RTT_ENTRY), + (VOID *)&DramTermKBUDIMMFT3 +}; + // // MemClkDis // STATIC CONST UINT8 ROMDATA KBSODdr3CLKDisFT3[] = {0xFF, 0xFF, 0x00 , 0x00, 0x00, 0x00, 0x00, 0x00}; CONST PSC_TBL_ENTRY KBClkDisMapEntSOFT3 = { - {PSCFG_CLKDIS, SODIMM_TYPE + UDIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_16_KB, AMD_F16_ALL}, SOCKET_FT3_KB, DDR3_TECHNOLOGY}, + {PSCFG_CLKDIS, SODIMM_TYPE + UDIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_16_KB, AMD_F16_ALL}, KB_SOCKET_FT3, DDR3_TECHNOLOGY}, sizeof (KBSODdr3CLKDisFT3) / sizeof (UINT8), (VOID *)&KBSODdr3CLKDisFT3 }; @@ -99,7 +166,7 @@ CONST PSC_TBL_ENTRY KBClkDisMapEntSOFT3 = { // STATIC CONST UINT8 ROMDATA KBSODdr3ODTTriFT3[] = {0xFF, 0xFF, 0x00, 0x00}; CONST PSC_TBL_ENTRY KBSODdr3ODTTriEntFT3 = { - {PSCFG_ODTTRI, SODIMM_TYPE + UDIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_16_KB, AMD_F16_ALL}, SOCKET_FT3_KB, DDR3_TECHNOLOGY}, + {PSCFG_ODTTRI, SODIMM_TYPE + UDIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_16_KB, AMD_F16_ALL}, KB_SOCKET_FT3, DDR3_TECHNOLOGY}, sizeof (KBSODdr3ODTTriFT3) / sizeof (UINT8), (VOID *)&KBSODdr3ODTTriFT3 }; @@ -109,7 +176,7 @@ CONST PSC_TBL_ENTRY KBSODdr3ODTTriEntFT3 = { // STATIC CONST UINT8 ROMDATA KBSODdr3CSTriFT3[] = {0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; CONST PSC_TBL_ENTRY KBSODdr3CSTriEntFT3 = { - {PSCFG_CSTRI, SODIMM_TYPE + UDIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_16_KB, AMD_F16_ALL}, SOCKET_FT3_KB, DDR3_TECHNOLOGY}, + {PSCFG_CSTRI, SODIMM_TYPE + UDIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_16_KB, AMD_F16_ALL}, KB_SOCKET_FT3, DDR3_TECHNOLOGY}, sizeof (KBSODdr3CSTriFT3) / sizeof (UINT8), (VOID *)&KBSODdr3CSTriFT3 }; @@ -124,7 +191,7 @@ STATIC CONST PSCFG_S2D_ENTRY KBUDdr3S2DFT3[] = { {2, ANY_SPEED, VOLT_ALL, NP + DIMM_SR + DIMM_DR, NP + DIMM_SR + DIMM_DR, NP, 1} }; CONST PSC_TBL_ENTRY S2DTblEntUFT3 = { - {PSCFG_S2D, UDIMM_TYPE + SODIMM_TYPE + SODWN_SODIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_16_KB, AMD_F16_ALL}, SOCKET_FT3_KB, DDR3_TECHNOLOGY}, + {PSCFG_S2D, UDIMM_TYPE + SODIMM_TYPE + SODWN_SODIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_16_KB, AMD_F16_ALL}, KB_SOCKET_FT3, DDR3_TECHNOLOGY}, sizeof (KBUDdr3S2DFT3) / sizeof (PSCFG_S2D_ENTRY), (VOID *)&KBUDdr3S2DFT3 }; diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/mpSkb3.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/mpSkb3.c index 76b85e5..9074629 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/mpSkb3.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/mpSkb3.c @@ -95,24 +95,18 @@ STATIC CONST PSCFG_SAO_ENTRY KBSODdr3SAO[] = { {_1DIMM, DDR1333, VOLT_ALL, DIMM_DR, NP, NP, 0, 0x00003D3D, 0x20112222, 0}, {_1DIMM, DDR1600, V1_5 + V1_35, DIMM_SR, NP, NP, 0, 0x003C3C3C, 0x30332222, 0}, {_1DIMM, DDR1600, V1_5 + V1_35, DIMM_DR, NP, NP, 1, 0x00003C3C, 0x30332222, 0}, - {_1DIMM, DDR1866, V1_5, DIMM_SR, NP, NP, 0, 0x003C3C3C, 0x30332222, 0}, - {_1DIMM, DDR1866, V1_5, DIMM_DR, NP, NP, 1, 0x00003C3C, 0x30332222, 0}, {_2DIMM, DDR667 + DDR800, VOLT_ALL, NP, DIMM_SR + DIMM_DR, NP, 0, 0x00000000, 0x00002222, 0}, {_2DIMM, DDR667, VOLT_ALL, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 1, 0x00000000, 0x10222323, 0}, {_2DIMM, DDR800, VOLT_ALL, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 1, 0x00000000, 0x20222323, 0}, {_2DIMM, DDR1066, VOLT_ALL, NP, DIMM_SR, NP, 0, 0x003D3D3D, 0x10002222, 0}, {_2DIMM, DDR1066, VOLT_ALL, NP, DIMM_DR, NP, 0, 0x00000000, 0x10002222, 0}, - {_2DIMM, DDR1066, VOLT_ALL, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 1, 0x00000000, 0x30222323, 0}, + {_2DIMM, DDR1066 + DDR1333, VOLT_ALL, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 1, 0x00000000, 0x30222323, 0}, {_2DIMM, DDR1333, VOLT_ALL, NP, DIMM_SR, NP, 0, 0x003D3D3D, 0x20112222, 0}, {_2DIMM, DDR1333, VOLT_ALL, NP, DIMM_DR, NP, 0, 0x00003D3D, 0x20112222, 0}, - {_2DIMM, DDR1333, V1_5 + V1_35, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 1, 0x00000000, 0x30222323, 0}, - {_2DIMM, DDR1333, V1_25, DIMM_SR, DIMM_SR, NP, 1, 0x00000000, 0x30222323, 0}, {_2DIMM, DDR1600, V1_5 + V1_35, NP, DIMM_SR, NP, 0, 0x003C3C3C, 0x30332222, 0}, {_2DIMM, DDR1600, V1_5 + V1_35, NP, DIMM_DR, NP, 1, 0x00003C3C, 0x30332222, 0}, {_2DIMM, DDR1600, V1_5, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 1, 0x00000000, 0x30222323, 0}, {_2DIMM, DDR1600, V1_35, DIMM_SR, DIMM_SR, NP, 1, 0x00000000, 0x30222323, 0}, - {_2DIMM, DDR1866, V1_5, NP, DIMM_SR, NP, 0, 0x003C3C3C, 0x30332222, 0}, - {_2DIMM, DDR1866, V1_5, NP, DIMM_DR, NP, 1, 0x00003C3C, 0x30332222, 0}, }; CONST PSC_TBL_ENTRY KBSAOTblEntSO3 = { {PSCFG_SAO, SODIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_16_KB, AMD_F16_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY}, @@ -155,8 +149,6 @@ STATIC CONST PSCFG_SAO_ENTRY KBSoDwnDdr3SAO[] = { {_DIMM_NONE, DDR1333, VOLT_ALL, DIMM_DR, NP, NP, 0, 0x00003D3D, 0x20110000, 0}, {_DIMM_NONE, DDR1600, V1_5 + V1_35, DIMM_SR, NP, NP, 0, 0x003C3C3C, 0x30110000, 0}, {_DIMM_NONE, DDR1600, V1_5 + V1_35, DIMM_DR, NP, NP, 1, 0x00003C3C, 0x30110000, 0}, - {_DIMM_NONE, DDR1866, V1_5, DIMM_SR, NP, NP, 0, 0x003C3C3C, 0x30110000, 0}, - {_DIMM_NONE, DDR1866, V1_5, DIMM_DR, NP, NP, 1, 0x00003C3C, 0x30110000, 0}, }; CONST PSC_TBL_ENTRY KBSAOTblEntSoDwn3 = { {PSCFG_SAO, SODWN_SODIMM_TYPE, _DIMM_NONE, {AMD_FAMILY_16_KB, AMD_F16_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY}, @@ -186,14 +178,11 @@ STATIC CONST PSCFG_RTT_ENTRY KBDramTermSODIMM3[] = { {_1DIMM, DDR1866, V1_5, DIMM_SR + DIMM_DR, NP, NP, DIMM_SR + DIMM_DR, R0 + R1, 1, 0}, {_2DIMM, DDR667 + DDR800 + DDR1066, VOLT_ALL, NP, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 2, 0}, {_2DIMM, DDR667 + DDR800, VOLT_ALL, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 3, 2}, - {_2DIMM, DDR1066, VOLT_ALL, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 5, 2}, + {_2DIMM, DDR1066 + DDR1333, VOLT_ALL, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 5, 2}, {_2DIMM, DDR1333, VOLT_ALL, NP, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 1, 0}, - {_2DIMM, DDR1333, V1_5 + V1_35, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 5, 2}, - {_2DIMM, DDR1333, V1_25, DIMM_SR, DIMM_SR, NP, DIMM_SR + DIMM_DR, R0 + R1, 5, 2}, {_2DIMM, DDR1600, V1_5 + V1_35, NP, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 1, 0}, {_2DIMM, DDR1600, V1_5, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 4, 1}, {_2DIMM, DDR1600, V1_35, DIMM_SR, DIMM_SR, NP, DIMM_SR + DIMM_DR, R0 + R1, 4, 1}, - {_2DIMM, DDR1866, V1_5, NP, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 1, 0}, }; CONST PSC_TBL_ENTRY KBDramTermTblEntSO3 = { {PSCFG_RTT, SODIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_16_KB, AMD_F16_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY}, @@ -250,7 +239,6 @@ STATIC CONST PSCFG_RTT_ENTRY KBDramTermSoDwn3[] = { {_DIMM_NONE, DDR800 + DDR1066, VOLT_ALL, DIMM_SR + DIMM_DR, NP, NP, DIMM_SR + DIMM_DR, R0 + R1, 2, 0}, {_DIMM_NONE, DDR1333, VOLT_ALL, DIMM_SR + DIMM_DR, NP, NP, DIMM_SR + DIMM_DR, R0 + R1, 1, 0}, {_DIMM_NONE, DDR1600, V1_5 + V1_35, DIMM_SR + DIMM_DR, NP, NP, DIMM_SR + DIMM_DR, R0 + R1, 1, 0}, - {_DIMM_NONE, DDR1866, V1_5, DIMM_SR + DIMM_DR, NP, NP, DIMM_SR + DIMM_DR, R0 + R1, 1, 0}, }; CONST PSC_TBL_ENTRY KBDramTermTblEntSoDwn3 = { {PSCFG_RTT, SODWN_SODIMM_TYPE, _DIMM_NONE, {AMD_FAMILY_16_KB, AMD_F16_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY}, @@ -267,9 +255,9 @@ STATIC CONST PSCFG_MAXFREQ_ENTRY ROMDATA KBMaxFreqSODIMM6L[] = { {{_1DIMM, 1, 0, 1, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, DDR1333_FREQUENCY}}, {{_2DIMM, 1, 1, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, DDR1333_FREQUENCY}}, {{_2DIMM, 1, 0, 1, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, DDR1333_FREQUENCY}}, - {{_2DIMM, 2, 2, 0, 0, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}}, - {{_2DIMM, 2, 1, 1, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, DDR1066_FREQUENCY}}, - {{_2DIMM, 2, 0, 2, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, DDR1066_FREQUENCY}}, + {{_2DIMM, 2, 2, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, DDR1333_FREQUENCY}}, + {{_2DIMM, 2, 1, 1, 0, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}}, + {{_2DIMM, 2, 0, 2, 0, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}}, }; CONST PSC_TBL_ENTRY KBMaxFreqTblEntSO6L = { {PSCFG_MAXFREQ, SODIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_16_KB, AMD_F16_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY}, @@ -304,8 +292,8 @@ STATIC CONST PSCFG_MAXFREQ_ENTRY ROMDATA KBMaxFreqSoDwnPlusSODIMM6L[] = { {{_1DIMM, 1, 1, 0, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, DDR1066_FREQUENCY}}, {{_1DIMM, 1, 0, 1, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, DDR1066_FREQUENCY}}, {{_1DIMM, 2, 2, 0, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, DDR1066_FREQUENCY}}, - {{_1DIMM, 2, 1, 1, 0, DDR1066_FREQUENCY, DDR1066_FREQUENCY, DDR1066_FREQUENCY}}, - {{_1DIMM, 2, 0, 2, 0, DDR1066_FREQUENCY, DDR1066_FREQUENCY, DDR1066_FREQUENCY}}, + {{_1DIMM, 2, 1, 1, 0, DDR1333_FREQUENCY, DDR1066_FREQUENCY, DDR1066_FREQUENCY}}, + {{_1DIMM, 2, 0, 2, 0, DDR1333_FREQUENCY, DDR1066_FREQUENCY, DDR1066_FREQUENCY}}, }; CONST PSC_TBL_ENTRY KBMaxFreqTblEntSoDwnPlusSODIMM6L = { {PSCFG_MAXFREQ, SODWN_SODIMM_TYPE, _1DIMM, {AMD_FAMILY_16_KB, AMD_F16_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY}, @@ -335,8 +323,8 @@ CONST PSC_TBL_ENTRY KBMaxFreqTblEntSoDwnPlusSODIMM4L = { // DimmPerCh, Dimms, SR, DR, QR, Speed1_5V, Speed1_35V, Speed1_25V // STATIC CONST PSCFG_MAXFREQ_ENTRY ROMDATA KBMaxFreqSoDwn[] = { - {{_DIMM_NONE, 1, 1, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, DDR1066_FREQUENCY}}, - {{_DIMM_NONE, 1, 0, 1, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, DDR1066_FREQUENCY}}, + {{_DIMM_NONE, 1, 1, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, DDR1333_FREQUENCY}}, + {{_DIMM_NONE, 1, 0, 1, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, DDR1333_FREQUENCY}}, }; CONST PSC_TBL_ENTRY KBMaxFreqTblEntSoDwn = { {PSCFG_MAXFREQ, SODWN_SODIMM_TYPE, _DIMM_NONE, {AMD_FAMILY_16_KB, AMD_F16_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY}, diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/mpUkb3.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/mpUkb3.c index c18af0a..7e9b64e 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/mpUkb3.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/mpUkb3.c @@ -82,77 +82,18 @@ RDATA_GROUP (G2_PEI) * *----------------------------------------------------------------------------- */ -// Slow mode, POdtOff, Address timing and Output drive compensation -// Format : -// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, SlowMode, AddTmgCtl, ODC, POdtOff -// -STATIC CONST PSCFG_SAO_ENTRY KBUDdr3SAO[] = { - {_1DIMM, DDR667 + DDR800, V1_5, DIMM_SR + DIMM_DR, NP, NP, 0, 0x00000000, 0x00002222, 0}, - {_1DIMM, DDR1066, V1_5, DIMM_SR, NP, NP, 0, 0x003D3D3D, 0x10002222, 0}, - {_1DIMM, DDR1066, V1_5, DIMM_DR, NP, NP, 0, 0x00000000, 0x10002222, 0}, - {_1DIMM, DDR1333, V1_5, DIMM_SR, NP, NP, 0, 0x003D3D3D, 0x20112222, 0}, - {_1DIMM, DDR1333, V1_5, DIMM_DR, NP, NP, 0, 0x00003D3D, 0x20112222, 0}, - {_1DIMM, DDR1600 + DDR1866, V1_5, DIMM_SR, NP, NP, 0, 0x003C3C3C, 0x30332222, 0}, - {_1DIMM, DDR1600 + DDR1866, V1_5, DIMM_DR, NP, NP, 1, 0x00003C3C, 0x30332222, 0}, - {_2DIMM, DDR667 + DDR800, V1_5, NP, DIMM_SR + DIMM_DR, NP, 0, 0x00000000, 0x00002222, 0}, - {_2DIMM, DDR667, V1_5, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 1, 0x00000000, 0x10222323, 0}, - {_2DIMM, DDR800, V1_5, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 1, 0x00000000, 0x20222323, 0}, - {_2DIMM, DDR1066, V1_5, NP, DIMM_SR, NP, 0, 0x003D3D3D, 0x10002222, 0}, - {_2DIMM, DDR1066, V1_5, NP, DIMM_DR, NP, 0, 0x00000000, 0x10002222, 0}, - {_2DIMM, DDR1066 + DDR1333 + DDR1600, V1_5, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 1, 0x00000000, 0x30222323, 0}, - {_2DIMM, DDR1333, V1_5, NP, DIMM_SR, NP, 0, 0x003D3D3D, 0x20112222, 0}, - {_2DIMM, DDR1333, V1_5, NP, DIMM_DR, NP, 0, 0x00003D3D, 0x20112222, 0}, - {_2DIMM, DDR1600 + DDR1866, V1_5, NP, DIMM_SR, NP, 0, 0x003C3C3C, 0x30332222, 0}, - {_2DIMM, DDR1600 + DDR1866, V1_5, NP, DIMM_DR, NP, 1, 0x00003C3C, 0x30332222, 0}, -}; -CONST PSC_TBL_ENTRY KBSAOTblEntU3 = { - {PSCFG_SAO, UDIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_16_KB, AMD_F16_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY}, - sizeof (KBUDdr3SAO) / sizeof (PSCFG_SAO_ENTRY), - (VOID *)&KBUDdr3SAO -}; - -// Dram Term and Dynamic Dram Term -// Format : -// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, Dimm, Rank, RttNom, RttWr -// -// RttNom: -// 0 On die termination disabled -// 1 60ohms -// 2 120ohms -// 3 40ohms -// 4 20ohms -// 5 30ohms -// RttWr: -// 0 Dynamic termination for writes disabled. -// 1 60ohms -// 2 120ohms -STATIC CONST PSCFG_RTT_ENTRY DramTermKBUDIMM[] = { - {_1DIMM, DDR667 + DDR800 + DDR1066, V1_5, DIMM_SR + DIMM_DR, NP, NP, DIMM_SR + DIMM_DR, R0 + R1, 2, 0}, - {_1DIMM, DDR1333 + DDR1600 + DDR1866, V1_5, DIMM_SR + DIMM_DR, NP, NP, DIMM_SR + DIMM_DR, R0 + R1, 1, 0}, - {_2DIMM, DDR667 + DDR800 + DDR1066, V1_5, NP, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 2, 0}, - {_2DIMM, DDR667 + DDR800, V1_5, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 3, 2}, - {_2DIMM, DDR1066 + DDR1333, V1_5, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 5, 2}, - {_2DIMM, DDR1333 + DDR1600 + DDR1866, V1_5, NP, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 1, 0}, - {_2DIMM, DDR1600, V1_5, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 4, 1}, -}; -CONST PSC_TBL_ENTRY KBDramTermTblEntU = { - {PSCFG_RTT, UDIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_16_KB, AMD_F16_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY}, - sizeof (DramTermKBUDIMM) / sizeof (PSCFG_RTT_ENTRY), - (VOID *)&DramTermKBUDIMM -}; - // Max Freq. for UDIMM <6-layer Motherboard Design> configuration // Format : // DimmPerCh, Dimms, SR, DR, QR, Speed1_5V, Speed1_35V, Speed1_25V // STATIC CONST PSCFG_MAXFREQ_ENTRY ROMDATA MaxFreqKBUDIMM6L[] = { - {{_1DIMM, 1, 1, 0, 0, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, - {{_1DIMM, 1, 0, 1, 0, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, - {{_2DIMM, 1, 1, 0, 0, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, - {{_2DIMM, 1, 0, 1, 0, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, - {{_2DIMM, 2, 2, 0, 0, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, - {{_2DIMM, 2, 1, 1, 0, DDR1333_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, - {{_2DIMM, 2, 0, 2, 0, DDR1333_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, + {{_1DIMM, 1, 1, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, + {{_1DIMM, 1, 0, 1, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, + {{_2DIMM, 1, 1, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, + {{_2DIMM, 1, 0, 1, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, + {{_2DIMM, 2, 2, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, + {{_2DIMM, 2, 1, 1, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, + {{_2DIMM, 2, 0, 2, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, }; CONST PSC_TBL_ENTRY KBMaxFreqTblEntU6L = { {PSCFG_MAXFREQ, UDIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_16_KB, AMD_F16_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY}, @@ -160,18 +101,37 @@ CONST PSC_TBL_ENTRY KBMaxFreqTblEntU6L = { (VOID *)&MaxFreqKBUDIMM6L }; +// Max Freq. for UDIMM <6-layer Motherboard Design> configuration for microserver +// Format : +// DimmPerCh, Dimms, SR, DR, QR, Speed1_5V, Speed1_35V, Speed1_25V +// +STATIC CONST PSCFG_MAXFREQ_ENTRY ROMDATA MaxFreqKBMicroSrvUDIMM6L[] = { + {{_1DIMM, 1, 1, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, + {{_1DIMM, 1, 0, 1, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, + {{_2DIMM, 1, 1, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, + {{_2DIMM, 1, 0, 1, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, + {{_2DIMM, 2, 2, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, + {{_2DIMM, 2, 1, 1, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, + {{_2DIMM, 2, 0, 2, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, +}; +CONST PSC_TBL_ENTRY KBMaxFreqTblEntMicroSrvU6L = { + {PSCFG_MAXFREQ, UDIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_16_KB, AMD_F16_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY}, + sizeof (MaxFreqKBMicroSrvUDIMM6L) / sizeof (PSCFG_MAXFREQ_ENTRY), + (VOID *)&MaxFreqKBMicroSrvUDIMM6L +}; + // Max Freq. for UDIMM <4-layer Motherboard Design> configuration // Format : // DimmPerCh, Dimms, SR, DR, QR, Speed1_5V, Speed1_35V, Speed1_25V // STATIC CONST PSCFG_MAXFREQ_ENTRY ROMDATA MaxFreqKBUDIMM4L[] = { - {{_1DIMM, 1, 1, 0, 0, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, - {{_1DIMM, 1, 0, 1, 0, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, - {{_2DIMM, 1, 1, 0, 0, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, - {{_2DIMM, 1, 0, 1, 0, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, - {{_2DIMM, 2, 2, 0, 0, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, - {{_2DIMM, 2, 1, 1, 0, DDR1333_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, - {{_2DIMM, 2, 0, 2, 0, DDR1333_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, + {{_1DIMM, 1, 1, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, + {{_1DIMM, 1, 0, 1, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, + {{_2DIMM, 1, 1, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, + {{_2DIMM, 1, 0, 1, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, + {{_2DIMM, 2, 2, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, + {{_2DIMM, 2, 1, 1, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, + {{_2DIMM, 2, 0, 2, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, }; CONST PSC_TBL_ENTRY KBMaxFreqTblEntU4L = { {PSCFG_MAXFREQ, UDIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_16_KB, AMD_F16_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY}, diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/mn.h b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/mn.h index 4783cd3..feddf9f 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/mn.h +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/mn.h @@ -364,6 +364,8 @@ typedef struct _MEM_PS_BLOCK { UINT8 NumOfDimmSlots; ///< See enum type NOD_SUPPORTED UINT8 DimmType; ///< See enum type DIMM_TYPE UINT16 RankType; ///< Rank type of all populated DIMMs. See MemPGetPsRankType. + UINT8 MotherboardLayer; ///< See enum type MB_LAYER_TYPE + UINT8 MotherboardPower; ///< See enum type MB_POWER_TYPE } MEM_PS_BLOCK; /// Structure parameters needed in frequency change of client NB. @@ -445,7 +447,8 @@ typedef enum { AMPIsEnabled, ///< Check to detemine if AMP is exactly enabled. ScrubberEn, ///< Check to determine if DRAM scrubber is already enabled SwitchRdDqsDlyForMaxRdLatency, ///< Use the different RdDqsDly value for MaxRdLatency calculation before/after DQS training - + SelectMotherboardLayer, ///< Check to determine if multiple motherboard layer design applies + SelectMotherboardPower, ///< Check to determine if multiple motherboard power design applies EnumSize ///< Size of list } NB_SUPPORTED; @@ -548,6 +551,7 @@ typedef enum { DisableMemHoleMapping, ///< Disable Memory Hole Settings RestoreMemHoleMapping, ///< Enable Memory Hole Settings PhyInitVref, ///< Program VrefSel during phy init + IntermediateMemclkFreqVal, ///< Workaround for some families needing intermediate frequency valid NumberOfHooks ///< Size of list } FAMILY_SPECIFIC_FUNC_INDEX; @@ -629,6 +633,7 @@ typedef struct _MEM_NB_BLOCK { BOOLEAN OrigDisAutoRefreshState; ///< Original state of Dis Auto Refresh BOOLEAN Execute1dMaxRdLatTraining; ///< Indicates if 1D training should be executed BOOLEAN Override2DTraining; ///< 2D training has been overriden + UINT8 PmuFirmwareImage; ///< PMU firmware image to be use. MEM_DCT_CACHE DctCache[MAX_CHANNELS_PER_SOCKET]; ///< Allocate space for MCT_DCT_CACHE. MEM_DCT_CACHE *DctCachePtr; ///< pointer to current Node's Node struct @@ -1575,5 +1580,17 @@ VOID MemNSetEccExclusionRangeUnb ( IN OUT MEM_NB_BLOCK *NBPtr ); + +UINT32 +MemNGetNbClkFreqByPstateUnb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 NBPstate + ); + +BOOLEAN +MemNIntermediateMemclkFreqValUnb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT VOID *OptParam + ); #endif /* _MN_H_ */ diff --git a/src/vendorcode/amd/agesa/f16kb/cpcarmac.inc b/src/vendorcode/amd/agesa/f16kb/cpcarmac.inc deleted file mode 100644 index b29ea8c..0000000 --- a/src/vendorcode/amd/agesa/f16kb/cpcarmac.inc +++ /dev/null @@ -1,476 +0,0 @@ -;***************************************************************************** -; AMD Generic Encapsulated Software Architecture -; -; Workfile: cpcarmac.inc $Revision:: 84150 $ $Date:: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ -; -; Description: Code to setup and break down cache-as-stack -; -;***************************************************************************** -; - * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;***************************************************************************** - - .XLIST - INCLUDE cpcar.inc - .LIST - .586P - .mmx - -STACK_AT_TOP EQU 0 ; Stack is at the top of CAR -STACK_AT_BOTTOM EQU 1 ; Stack is at the bottom of CAR - -;====================================================================== -; AMD_ENABLE_STACK: Setup a stack -; -; In: -; EBX = Return address (preserved) -; -; Out: -; SS:ESP - Our new private stack location -; -; EAX = AGESA_STATUS -; EDX = Return status code if EAX contains a return code of higher -; severity than AGESA_SUCCESS -; ECX = Stack size in bytes -; -; Requirements: -; * This routine presently is limited to a max of 64 processor cores -; Preserved: -; ebx ebp -; Destroyed: -; eax, ecx, edx, edi, esi, ds, es, ss, esp -; mmx0, mmx1, mmx5 -; Input Parameter: -; STACK_AT_TOP (default) -; Indicate stack is on the top of cache as RAM. -; STACK_AT_BOTTOM -; Indicate stack is at the bottom of cache as RAM. -; -; Description: -; Fixed MTRR address allocation to cores: -; The BSP gets 64K of stack, Core0 of each node gets 16K of stack, all other cores get 4K. -; There is a max of 1 BSP, 7 core0s and 56 other cores. -; Although each core has it's own cache storage, they share the address space. Each core must -; be assigned a private and unique address space for its stack. To support legacy systems, -; the stack needs to be within the legacy address space (1st 1Meg). Room must also be reserved -; for the other legacy elements (Interrupt vectors, BIOS ROM, video buffer, etc.) -; -; 80000h 40000h 00000h -; +----------+----------+----------+----------+----------+----------+----------+----------+ -; 64K | | | | | | | | | 64K ea -; ea +----------+----------+----------+----------+----------+----------+----------+----------+ -; | MTRR 0000_0250 MTRRfix64K_00000 | -; +----------+----------+----------+----------+----------+----------+----------+----------+ -; | 3 | 2 | 1 | 0 | 0 | | | | <-node -; | 15..1 | 15..1 | 15..1 | 15..1 | 0 | | | | <-core -; +----------+----------+----------+----------+----------+----------+----------+----------+ -; -; C0000h B0000h A0000h 90000h 80000h -; +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+ -;16K | | | | | | | | | | | | | | | | | -; ea +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+ -; | MTRR 0259 MTRRfix16K_A0000 | MTRR 0258 MTRRfix16K_80000 | -; +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+ -; | > Dis|play B|uffer | < | | | | | | | | | | 3 | 2 | 1 | <-node -; | > T| e m |p o r |a r y | B u |f f e |r A |r e a<| | | | | | 0 | 0 | 0 | <-core -; +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+ -; -; E0000h D0000h C0000h -; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ -; 4K | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 4K ea -; ea +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ -; | 026B MTRRfix4K_D8000 | 026A MTRRfix4K_D0000 | 0269 MTRRfix4K_C8000 | 0268 MTRRfix4K_C0000 | -; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ -; | | | | | | | | | | | | | | | | | >| V| I| D| E| O| |B |I |O |S | |A |r |e |a<| -; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ -; -; 100000h F0000h E0000h -; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ -; | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 4K ea -; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ -; | 026F MTRRfix4K_F8000 | 026E MTRRfix4K_F0000 | 026D MTRRfix4K_E8000 | 026C MTRRfix4K_E0000 | -; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ -; | >|MA|IN| B|IO|S |RA|NG|E | | | | | | |< | >|EX|TE|ND|ED| B|IO|S |ZO|NE| | | | | |< | -; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ -;====================================================================== -AMD_ENABLE_STACK MACRO StackPosition - local AmdEnableStackExit - -; Note that SS:ESP will be default stack. Note that this stack -; routine will not be used after memory has been initialized. Because -; of its limited lifetime, it will not conflict with typical PCI devices. - movd mm0, ebx ; Put return address in a safe place - movd mm1, ebp ; Save some other user registers - - ; get node id and core id of current executing core - GET_NODE_ID_CORE_ID ; Sets ESI[15,8]= Node#; ESI[7,0]= core# (relative to node) - ; Note: ESI[31:24] are used for flags: Unrecognized Family, Is_Primary core, Stack already established - - ; If we detected an unknown processor family or core combination, return AGESA_FATAL. - .if (esi & (1 SHL FLAG_UNKNOWN_FAMILY)) - mov edx, CPU_EVENT_UNKNOWN_PROCESSOR_FAMILY - mov eax, AGESA_FATAL - jmp AmdEnableStackExit - .elseif (esi & (1 SHL FLAG_CORE_NOT_IDENTIFIED)) - mov edx, CPU_EVENT_CORE_NOT_IDENTIFIED - mov eax, AGESA_FATAL - jmp AmdEnableStackExit - .endif - - ; determine if stack is already enabled. We are using the DefType MSR for this determination. - ; It is =0 after reset; CAR setup sets it to enable the MTRRs - mov eax, cr0 ; Is cache enabled? (CD or NW bit set) - CR0_MASK TEXTEQU %((1 SHL CR0_CD) OR (1 SHL CR0_NW)) - .if (!(eax & CR0_MASK)) - mov ecx, AMD_MTRR_DEFTYPE ; MSR:0000_02FF - _RDMSR ; Are either of the default types enabled? (MTRR_DEF_TYPE_EN + MTRR_DEF_TYPE_FIX_EN) - MSR_MASK TEXTEQU %((1 SHL MTRR_DEF_TYPE_EN)+(1 SHL MTRR_DEF_TYPE_FIX_EN)) - .if (eax & MSR_MASK) - bts esi, FLAG_STACK_REENTRY ; indicate stack has already been initialized - .endif - .endif - - ; Set node to map the first 16MB to node 0; 0000_0000 to 00FF_FFFF as DRAM - mov ebx, esi ; Get my Node/Core info - xor bl, bl - shl bh, 3 ; Isolate my node#, match alignment for PCI Dev# - mov eax, 8000C144h ; D18F1x44:DRAM Base/Limit; N is Base, N+4 is Limit - add ah, bh - mov ebx, eax ; Save PCI address for Base/Limit pair - - mov dx, 0CF8h - out dx, eax - add dx, 4 - xor eax, eax ; Least Significant bit is AD24 so 0 sets mask of 00FF_FFFF (16MB) - out dx, eax ; DRAM Limit = node0, no interleave - - mov eax, ebx - sub eax, 4 ; Now point to the Base register - mov dx, 0CF8h - out dx, eax - add dx, 4 - mov eax, 00000003h ; Set the read and write enable bits - out dx, eax ; DRAM Base = 0x0000, R/W - - AMD_ENABLE_STACK_FAMILY_HOOK - - ; Init CPU MSRs for our init routines - mov ecx, MTRR_SYS_CFG ; SYS_CFG - _RDMSR - bts eax, MTRR_FIX_DRAM_MOD_EN ; Turn on modification enable bit - _WRMSR - - mov eax, esi - bt eax, FLAG_STACK_REENTRY ; Is this a 2nd entry? - .if (!carry?) ; On a re-entry, do not clear MTRRs or reset TOM; just reset the stack SS:ESP - bt eax, FLAG_IS_PRIMARY ; Is this core the primary in a compute unit? - .if (carry?) ; Families using shared groups do not need to clear the MTRRs since that is done at power-on reset - ; Note: Relying on MSRs to be cleared to 0's at reset for families w/shared cores - ; Clear all variable and Fixed MTRRs for non-shared cores - mov ecx, AMD_MTRR_VARIABLE_BASE0 - xor eax, eax - xor edx, edx - .while (cl != 10h) ; Variable MTRRphysBase[n] and MTRRphysMask[n] - _WRMSR - inc cl - .endw - mov cx, AMD_MTRR_FIX64k_00000 ; MSR:0000_0250 - _WRMSR - mov cx, AMD_MTRR_FIX16k_80000 ; MSR:0000_0258 - _WRMSR - mov cx, AMD_MTRR_FIX16k_A0000 ; MSR:0000_0259 - _WRMSR - mov cx, AMD_MTRR_FIX4k_C0000 ; Fixed 4Ks: MTRRfix4K_C0000 to MTRRfix4K_F8000 - .while (cl != 70h) - _WRMSR - inc cl - .endw - - ; Set TOP_MEM (C001_001A) for non-shared cores to 16M. This will be increased at heap init. - ; - not strictly needed since the FixedMTRRs take presedence. - mov eax, (16 * 1024 * 1024) - mov ecx, TOP_MEM ; MSR:C001_001A - _WRMSR - .endif ; End Is_Primary - .endif ; End Stack_ReEntry - - ; Clear IORRs (C001_0016-19) and TOM2(C001_001D) for all cores - xor eax, eax - xor edx, edx - mov ecx, IORR_BASE ; MSR:C001_0016 - 0019 - .while (cl != 1Ah) - _WRMSR - inc cl - .endw - mov ecx, TOP_MEM2 ; MSR:C001_001D - _WRMSR - - ; setup MTTRs for stacks - ; A speculative read can be generated by a speculative fetch mis-aligned in a code zone - ; or due to a data zone being interpreted as code. When a speculative read occurs outside a - ; controlled region (intentionally used by software), it could cause an unwanted cache eviction. - ; To prevent speculative reads from causing an eviction, the unused cache ranges are set - ; to UC type. Only the actively used regions (stack, heap) are reflected in the MTRRs. - ; Note: some core stack regions will share an MTRR since the control granularity is much - ; larger than the allocated stack zone. The allocation algorithm must account for this 'extra' - ; space covered by the MTRR when parseling out cache space for the various uses. In some cases - ; this could reduce the amount of EXE cache available to a core. see cpuCacheInit.c - ; - ; Outcome of this block is that: (Note the MTRR map at the top of the file) - ; ebp - start address of stack block - ; ebx - [31:16] - MTRR MSR address - ; - [15:8] - slot# in MTRR register - ; - [7:0] - block size in #4K blocks - ; review: ESI[31:24]=Flags; SI[15,8]= Node#; SI[7,0]= core# (relative to node) - ; - - mov eax, esi ; Load Flags, node, core - .if (al == 0) ; Is a core 0? - .if (ah == 0) ; Is Node 0? (BSP) - ; Is BSP, assign a 64K stack; for F10/F12, foce to a 32K stack - mov ebx, ((AMD_MTRR_FIX64k_00000 SHL 16) + (3 SHL 8) + (BSP_STACK_SIZE_64K / 1000h)) - bt eax, FLAG_FORCE_32K_STACK - .if (carry?) - mov ebx, ((AMD_MTRR_FIX64k_00000 SHL 16) + (3 SHL 8) + (BSP_STACK_SIZE_32K / 1000h)) - .endif - mov ebp, BSP_STACK_BASE_ADDR - .else ; node 1 to 7, core0 - ; Is a Core0 of secondary node, assign 16K stacks - mov bx, AMD_MTRR_FIX16k_80000 - shl ebx, 16 ; - dec ah ; index from 0 - mov bh, ah ; Node# is used as slot# - mov bl, (CORE0_STACK_SIZE / 1000h) - mov al, ah ; Base = (Node# * Size); - mul bl ; - movzx eax, ax ; - shl eax, 12 ; Expand back to full byte count (* 4K) - add eax, CORE0_STACK_BASE_ADDR - mov ebp, eax - .endif - .else ;core 1 thru core 15 - ; Is core 1-15 of any node, assign 4K stacks - mov al, 16 ; CoreIndex = ( (Node# * 16) ... - mul ah ; - mov bx, si ; - dec bl ; account for core 0 on P1, etc - add al, bl ; ... + Core#); - - mov bx, AMD_MTRR_FIX64k_00000 - shl ebx, 16 ; - mov bh, al ; Slot# = (CoreIndex / 16) + 4; - shr bh, 4 ; - add bh, 4 ; - mov bl, (CORE1_STACK_SIZE / 1000h) - - mul bl ; Base = ( (CoreIndex * Size) ... - movzx eax, ax ; - shl eax, 12 ; Expand back to full byte count (* 4K) - add eax, CORE1_STACK_BASE_ADDR ; ... + Base_Addr); - mov ebp, eax - .endif - - ; Now set the MTRR. Add this to already existing settings (don't clear any MTRR) - mov edi, WB_DRAM_TYPE ; Load Cache type in 1st slot - mov cl, bh ; ShiftCount = ((slot# ... - and cl, 03h ; ... % 4) ... - shl cl, 3 ; ... * 8); - shl edi, cl ; Cache type is now in correct position - ror ebx, 16 ; Get the MTRR address - movzx ecx, bx ; - rol ebx, 16 ; Put slot# & size back in BX - _RDMSR ; Read-modify-write the MSR - .if (bh < 4) ; Is value in lower or upper half of MSR? - or eax, edi ; - .else ; - or edx, edi ; - .endif ; - _WRMSR ; - - ; Enable MTRR defaults as UC type - mov ecx, AMD_MTRR_DEFTYPE ; MSR:0000_02FF - _RDMSR ; Read-modify-write the MSR - bts eax, MTRR_DEF_TYPE_EN ; MtrrDefTypeEn - bts eax, MTRR_DEF_TYPE_FIX_EN ; MtrrDefTypeFixEn - _WRMSR - - ; Close the modification window on the Fixed MTRRs - mov ecx, MTRR_SYS_CFG ; MSR:0C001_0010 - _RDMSR - bts eax, MTRR_FIX_DRAM_EN ; MtrrFixDramEn - bts eax, MTRR_VAR_DRAM_EN ; variable MTRR enable bit - btr eax, MTRR_FIX_DRAM_MOD_EN ; Turn off modification enable bit - _WRMSR - - ; Enable caching in CR0 - mov eax, CR0 ; Enable WT/WB cache - btr eax, CR0_PG ; Make sure paging is disabled - btr eax, CR0_CD ; Clear CR0 NW and CD - btr eax, CR0_NW - mov CR0, eax - - ; Use the Stack Base & size to calculate SS and ESP values - ; review: - ; esi[31:24]=Flags; esi[15,8]= Node#; esi[7,0]= core# (relative to node) - ; ebp - start address of stack block - ; ebx - [31:16] - MTRR MSR address - ; - [15:8] - slot# in MTRR register - ; - [7:0] - block size in #4K blocks - ; - mov esp, ebp ; Initialize the stack pointer - mov edi, esp ; Copy the stack start to edi - movzx bx, bl - movzx ebx, bx ; Clear upper ebx, don't need MSR addr anymore - shl ebx, 12 ; Make size full byte count (* 4K) - IFNB <StackPosition> - IF (StackPosition EQ STACK_AT_BOTTOM) - shr ebx, 1 ; If stack is at the bottom of CAR, divide size by 2 - ENDIF - ENDIF - add esp, ebx ; Set the Stack Pointer as full linear address - sub esp, 4 - ; - ; review: - ; esi[31:24]=Flags; esi[15,8]= Node#; esi[7,0]= core# (relative to node) - ; edi - 32b start address of stack block - ; ebx - size of stack block - ; esp - 32b linear stack pointer - ; - - ; Determine mode for SS base; - mov ecx, CR0 ; Check for 32-bit protect mode - bt ecx, CR0_PE ; - .if (!carry?) ; PE=0 means real mode - mov cx, cs ; - .if (cx >= 0D000h) ; If CS >= D000, it's a real mode segment. PM selector would be 08-> 1000 - ; alter SS:ESP for 16b Real Mode: - mov eax, edi ; - shr eax, 4 ; Create a Real Mode segment for ss, ds, es - mov ss, ax ; - mov ds, ax ; - mov es, ax ; - shl eax, 4 ; - sub edi, eax ; Adjust the clearing pointer for Seg:Offset mode - mov esp, ebx ; Make SP an offset from SS - sub esp, 4 ; - .endif ; endif - ; else - ; Default is to use Protected 32b Mode - .endif - IFNB <StackPosition> - IF (StackPosition EQ STACK_AT_BOTTOM) - shl ebx, 1 ; restore the size of CAR - ENDIF - ENDIF - ; - ; Clear The Stack - ; Now that we have set the location and the MTRRs, initialize the cache by - ; reading then writing to zero all of the stack area. - ; review: - ; ss - Stack base - ; esp - stack pointer - ; ebx - size of stack block - ; esi[31:24]=Flags; esi[15,8]= Node#; esi[7,0]= core# (relative to node) - ; edi - address of start of stack block - ; - shr ebx, 2 ; - mov cx, bx ; set cx for size count of DWORDS - ; Check our flags - Don't clear an existing stack - .if ( !(esi & (1 SHL FLAG_STACK_REENTRY)) ) - cld - mov esi, edi - rep lods DWORD PTR [esi] ; Pre-load the range - xor eax, eax - mov cx, bx - mov esi, edi ; Preserve base for push on stack - rep stos DWORD PTR [edi] ; Clear the range - mov DWORD PTR [esp], 0ABCDDCBAh ; Put marker in top stack dword - shl ebx, 2 ; Put stack size and base - push ebx ; in top of stack - push esi - - mov ecx, ebx ; Return size of stack in bytes - mov eax, AGESA_SUCCESS ; eax = AGESA_SUCCESS : no error return code - .else - movzx ecx, cx - shl ecx, 2 ; Return size of stack, in bytes - mov edx, CPU_EVENT_STACK_REENTRY - mov eax, AGESA_WARNING ; eax = AGESA_WARNING (Stack has already been set up) - .endif - -AmdEnableStackExit: - movd ebx, mm0 ; Restore return address - movd ebp, mm1 -ENDM - -;====================================================================== -; AMD_DISABLE_STACK: Destroy the stack inside the cache. This routine -; should only be executed on the BSP -; -; In: -; none -; -; Out: -; EAX = AGESA_SUCCESS -; -; Preserved: -; ebx -; Destroyed: -; eax, ecx, edx, esp, mmx5 -;====================================================================== -AMD_DISABLE_STACK MACRO - - mov esp, ebx ; Save return address - - ; get node/core/flags of current executing core - GET_NODE_ID_CORE_ID ; Sets ESI[15,8]= Node#; ESI[7,0]= core# (relative to node) - - ; Turn on modification enable bit - mov ecx, MTRR_SYS_CFG ; MSR:C001_0010 - _RDMSR - bts eax, MTRR_FIX_DRAM_MOD_EN ; Enable modifications - _WRMSR - - ; Set lower 640K MTRRs for Write-Back memory caching - mov ecx, AMD_MTRR_FIX64k_00000 - mov eax, 1E1E1E1Eh - mov edx, eax - _WRMSR ; 0 - 512K = WB Mem - mov ecx, AMD_MTRR_FIX16k_80000 - _WRMSR ; 512K - 640K = WB Mem - - ; Turn off modification enable bit - mov ecx, MTRR_SYS_CFG ; MSR:C001_0010 - _RDMSR - btr eax, MTRR_FIX_DRAM_MOD_EN ; Disable modification - _WRMSR - - AMD_DISABLE_STACK_FAMILY_HOOK ; Re-Enable 'normal' cache operations - - mov ebx, esp ; restore return address (ebx) - xor eax, eax - -ENDM

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Patch merged into coreboot/master: c371442 libpayload: Switch xHCI shared ports back to EHCI on shutdown
by gerrit＠coreboot.org 30 Sep '13

30 Sep '13

the following patch was just integrated into master: commit c371442a2925e9bfc9ddc045bfd446db53f0a145 Author: Nico Huber <nico.huber(a)secunet.com> Date: Fri Jul 19 14:03:47 2013 +0200 libpayload: Switch xHCI shared ports back to EHCI on shutdown On Intel's Panther Point the xHCI ports are shared with an EHCI controller. Our xHCI driver switches them to xHCI, naturally. But we forgot to switch them back on shutdown, which left them unusable by a non-xHCI aware operating system. Change-Id: I70ef08655a603b42ee939935d50cf77ea97878a3 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-on: http://review.coreboot.org/3791 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/3791 for details. -gerrit

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New patch to review for coreboot: 4ad8b3e Kratos-X1: Initial support for Micro Passion Kratos-X1
by David Robinson 29 Sep '13

29 Sep '13

David Robinson (info(a)micropassion.co.uk) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3951 -gerrit commit 4ad8b3e9ace2704c16f69a08950120223ed1026f Author: David Robinson <info(a)micropassion.co.uk> Date: Sun Sep 29 21:26:19 2013 +0100 Kratos-X1: Initial support for Micro Passion Kratos-X1 Initial support for Micro Passion Kratos-X1 PICO ITX single board computer featuring an AMD G-Series SOC (FT3). The configuration includes an example of soldered down DDR3 (No SPD) Change-Id: I2cbe3ec26002e248e440531cef3b8b53e6d08148 Signed-off-by: David Robinson <info(a)micropassion.co.uk> --- src/mainboard/Kconfig | 3 + src/mainboard/micropassion/Kconfig | 16 + src/mainboard/micropassion/kratosx1/BiosCallOuts.c | 172 +++++ src/mainboard/micropassion/kratosx1/BiosCallOuts.h | 33 + src/mainboard/micropassion/kratosx1/Kconfig | 100 +++ src/mainboard/micropassion/kratosx1/Makefile.inc | 28 + src/mainboard/micropassion/kratosx1/OptionsIds.h | 67 ++ .../micropassion/kratosx1/PlatformGnbPcie.c | 154 ++++ .../micropassion/kratosx1/PlatformGnbPcieComplex.h | 32 + .../micropassion/kratosx1/acpi/AmdImc.asl | 114 +++ src/mainboard/micropassion/kratosx1/acpi/gpe.asl | 78 +++ src/mainboard/micropassion/kratosx1/acpi/ide.asl | 250 +++++++ .../micropassion/kratosx1/acpi/mainboard.asl | 34 + .../micropassion/kratosx1/acpi/routing.asl | 198 ++++++ src/mainboard/micropassion/kratosx1/acpi/sata.asl | 150 ++++ src/mainboard/micropassion/kratosx1/acpi/si.asl | 27 + src/mainboard/micropassion/kratosx1/acpi/sleep.asl | 89 +++ .../micropassion/kratosx1/acpi/superio.asl | 20 + .../micropassion/kratosx1/acpi/thermal.asl | 20 + .../micropassion/kratosx1/acpi/usb_oc.asl | 132 ++++ src/mainboard/micropassion/kratosx1/acpi_tables.c | 333 +++++++++ src/mainboard/micropassion/kratosx1/agesawrapper.c | 771 +++++++++++++++++++++ src/mainboard/micropassion/kratosx1/agesawrapper.h | 97 +++ src/mainboard/micropassion/kratosx1/buildOpts.c | 504 ++++++++++++++ src/mainboard/micropassion/kratosx1/cmos.layout | 114 +++ src/mainboard/micropassion/kratosx1/devicetree.cb | 64 ++ src/mainboard/micropassion/kratosx1/dsdt.asl | 84 +++ src/mainboard/micropassion/kratosx1/get_bus_conf.c | 184 +++++ src/mainboard/micropassion/kratosx1/irq_tables.c | 112 +++ src/mainboard/micropassion/kratosx1/mainboard.c | 53 ++ src/mainboard/micropassion/kratosx1/mptable.c | 245 +++++++ src/mainboard/micropassion/kratosx1/romstage.c | 199 ++++++ 32 files changed, 4477 insertions(+) diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index fdb0eac..40c1f19 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -88,6 +88,8 @@ config VENDOR_LENOVO bool "Lenovo" config VENDOR_LIPPERT bool "LiPPERT" +config VENDOR_MICROPASSION + bool "Micro Passion" config VENDOR_MITAC bool "Mitac" config VENDOR_MSI @@ -181,6 +183,7 @@ source "src/mainboard/kontron/Kconfig" source "src/mainboard/lanner/Kconfig" source "src/mainboard/lenovo/Kconfig" source "src/mainboard/lippert/Kconfig" +source "src/mainboard/micropassion/Kconfig" source "src/mainboard/mitac/Kconfig" source "src/mainboard/msi/Kconfig" source "src/mainboard/nec/Kconfig" diff --git a/src/mainboard/micropassion/Kconfig b/src/mainboard/micropassion/Kconfig new file mode 100755 index 0000000..7045161 --- /dev/null +++ b/src/mainboard/micropassion/Kconfig @@ -0,0 +1,16 @@ +if VENDOR_MICROPASSION + +choice + prompt "Mainboard model" + +config BOARD_MICROPASSION_KRATOSX1 + bool "KRATOS-X1" +endchoice + +source "src/mainboard/micropassion/kratosx1/Kconfig" + +config MAINBOARD_VENDOR + string + default "Micro Passion Ltd" + +endif # VENDOR_MICROPASSION diff --git a/src/mainboard/micropassion/kratosx1/BiosCallOuts.c b/src/mainboard/micropassion/kratosx1/BiosCallOuts.c new file mode 100755 index 0000000..6b62e0d --- /dev/null +++ b/src/mainboard/micropassion/kratosx1/BiosCallOuts.c @@ -0,0 +1,172 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Micro Passion Ltd + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "agesawrapper.h" +#include "amdlib.h" +#include "BiosCallOuts.h" +#include "Ids.h" +#include "OptionsIds.h" +#include "heapManager.h" +#include "FchPlatform.h" +#include "cbfs.h" +#include <arch/io.h> +#include <console/console.h> +#include <console/loglevel.h> +#include <string.h> + +STATIC CONST BIOS_CALLOUT_STRUCT BiosCallouts[] = +{ + {AGESA_ALLOCATE_BUFFER, fam16kb_AllocateBuffer }, + {AGESA_DEALLOCATE_BUFFER, fam16kb_DeallocateBuffer }, + {AGESA_DO_RESET, fam16kb_Reset }, + {AGESA_LOCATE_BUFFER, fam16kb_LocateBuffer }, + {AGESA_READ_SPD, BiosReadSpd}, + {AGESA_READ_SPD_RECOVERY, fam16kb_DefaultRet }, + {AGESA_RUNFUNC_ONAP, fam16kb_RunFuncOnAp }, + {AGESA_GET_IDS_INIT_DATA, fam16kb_GetIdsInitData }, + {AGESA_HOOKBEFORE_DQS_TRAINING, fam16kb_HookBeforeDQSTraining }, + {AGESA_HOOKBEFORE_EXIT_SELF_REF, fam16kb_HookBeforeExitSelfRefresh }, + {AGESA_FCH_OEM_CALLOUT, Fch_Oem_config }, + {AGESA_GNB_GFX_GET_VBIOS_IMAGE, fam16kb_HookGfxGetVbiosImage } +}; + +AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + UINTN i; + AGESA_STATUS CalloutStatus; + UINTN CallOutCount = sizeof (BiosCallouts) / sizeof (BiosCallouts [0]); + + for (i = 0; i < CallOutCount; i++) + { + if (BiosCallouts[i].CalloutName == Func) + break; + } + + if(i >= CallOutCount) + return AGESA_UNSUPPORTED; + + CalloutStatus = BiosCallouts[i].CalloutPtr (Func, Data, ConfigPtr); + + return CalloutStatus; +} + +/** + * AMD Kratos-X1 Pico ITX Platform ALC272 Verb Table + */ +static const CODEC_ENTRY kratosx1_Alc272_VerbTbl[] = { + {0x11, 0x411111F0}, // - SPDIF_OUT2 + {0x12, 0x411111F0}, // - DMIC_1/2 + {0x13, 0x411111F0}, // - DMIC_3/4 + {0x14, 0x411111F0}, // Port D - LOUT1 + {0x15, 0x411111F0}, // Port A - LOUT2 + {0x16, 0x411111F0}, // + {0x17, 0x411111F0}, // Port H - MONO + {0x18, 0x01a19840}, // Port B - MIC1 + {0x19, 0x411111F0}, // Port F - MIC2 + {0x1a, 0x01813030}, // Port C - LINE1 + {0x1b, 0x411111F0}, // Port E - LINE2 + {0x1d, 0x40130605}, // - PCBEEP + {0x1e, 0x411111F0}, + {0x21, 0x01211010}, + {0xff, 0xffffffff} +}; + +static const CODEC_TBL_LIST kratosx1CodecTableList[] = +{ + {0x10ec0272, (CODEC_ENTRY*)&kratosx1_Alc272_VerbTbl[0]}, + {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL} +}; + +const unsigned char SPD_2GB_1R8_1333 [] = { +0x92,0x10,0x0B,0x03,0x03,0x19,0x00,0x01,0x03,0x52,0x01,0x08,0x0c,0x00,0x7e,0x00, +0x69,0x78,0x69,0x30,0x69,0x11,0x20,0x89,0x00,0x05,0x3C,0x3C,0x00,0xF0,0x83,0x81, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x2F,0x11,0x61,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 +}; + +AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status; +#ifdef __PRE_RAM__ + AGESA_READ_SPD_PARAMS * Params = (AGESA_READ_SPD_PARAMS *) ConfigPtr; + + printk(BIOS_DEBUG, "BiosReadSpd: %d %d %d\n", Params->SocketId, Params->MemChannelId, Params->DimmId); + + memcpy(Params->Buffer, SPD_2GB_1R8_1333, 256); + + Status = AGESA_SUCCESS; +#else + Status = AGESA_UNSUPPORTED; +#endif + + return Status; +} + +/** + * Fch Oem setting callback + * + * Configure platform specific Hudson device, + * such Azalia, SATA, IMC etc. + */ +AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) +{ + FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *)FchData; + + if (FchParams->StdHeader->Func == AMD_INIT_RESET) { + //FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *) FchData; + printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); + //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ + } else if (FchParams->StdHeader->Func == AMD_INIT_ENV) { + FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; + printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); + + /* Azalia Controller OEM Codec Table Pointer */ + FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&kratosx1CodecTableList[0]); + /* Azalia Controller Front Panel OEM Table Pointer */ + + /* Fan Control */ + //oem_fan_control(FchParams_env); + + /* XHCI configuration */ +#if CONFIG_HUDSON_XHCI_ENABLE + FchParams_env->Usb.Xhci0Enable = TRUE; +#else + FchParams_env->Usb.Xhci0Enable = FALSE; +#endif + FchParams_env->Usb.Xhci1Enable = FALSE; + + /* sata configuration */ + } + printk(BIOS_DEBUG, "Done\n"); + + return AGESA_SUCCESS; +} diff --git a/src/mainboard/micropassion/kratosx1/BiosCallOuts.h b/src/mainboard/micropassion/kratosx1/BiosCallOuts.h new file mode 100755 index 0000000..778eae0 --- /dev/null +++ b/src/mainboard/micropassion/kratosx1/BiosCallOuts.h @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _BIOS_CALLOUT_H_ +#define _BIOS_CALLOUT_H_ + +#include <northbridge/amd/agesa/family16kb/fam16kb_callouts.h> + +/* CALLOUT Initialization */ +AGESA_STATUS GetBiosCallout(UINT32 Func, UINT32 Data, VOID *ConfigPtr); + +/* AGESA ADVANCED CALLOUTS - MEMORY */ +AGESA_STATUS BiosReadSpd (UINT32 Func,UINT32 Data,VOID *ConfigPtr); +/* FCH OEM Config*/ +AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr); + +#endif //_BIOS_CALLOUT_H_ diff --git a/src/mainboard/micropassion/kratosx1/Kconfig b/src/mainboard/micropassion/kratosx1/Kconfig new file mode 100755 index 0000000..4f63f3c --- /dev/null +++ b/src/mainboard/micropassion/kratosx1/Kconfig @@ -0,0 +1,100 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +if BOARD_MICROPASSION_KRATOSX1 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_AMD_AGESA_FAMILY16_KB + select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB + select SOUTHBRIDGE_AMD_AGESA_YANGTZE + select HAVE_OPTION_TABLE + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select HAVE_ACPI_RESUME + select SB_HT_CHAIN_UNITID_OFFSET_ONLY + select LIFT_BSP_APIC_ID + select SERIAL_CPU_INIT + select AMDMCT + select HAVE_ACPI_TABLES + select BOARD_ROMSIZE_KB_2048 + select GFXUMA + +config MAINBOARD_DIR + string + default micropassion/kratosx1 + +config APIC_ID_OFFSET + hex + default 0x0 + +config MAINBOARD_PART_NUMBER + string + default "KRATOS-X1" + +config HW_MEM_HOLE_SIZEK + hex + default 0x200000 + +config MAX_CPUS + int + default 4 + +config MAX_PHYSICAL_CPUS + int + default 1 + +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n + +config MEM_TRAIN_SEQ + int + default 2 + +config IRQ_SLOT_COUNT + int + default 11 + +config RAMTOP + hex + default 0x1000000 + +config HEAP_SIZE + hex + default 0xc0000 + +config ACPI_SSDTX_NUM + int + default 0 + +config RAMBASE + hex + default 0x200000 + +config ONBOARD_VGA_IS_PRIMARY + bool + default y + +config HUDSON_LEGACY_FREE + bool + default y + +endif # BOARD_MICROPASSION_KRATOSX1 diff --git a/src/mainboard/micropassion/kratosx1/Makefile.inc b/src/mainboard/micropassion/kratosx1/Makefile.inc new file mode 100755 index 0000000..a83297a --- /dev/null +++ b/src/mainboard/micropassion/kratosx1/Makefile.inc @@ -0,0 +1,28 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +romstage-y += buildOpts.c +romstage-y += agesawrapper.c +romstage-y += BiosCallOuts.c +romstage-y += PlatformGnbPcie.c + +ramstage-y += buildOpts.c +ramstage-y += agesawrapper.c +ramstage-y += BiosCallOuts.c +ramstage-y += PlatformGnbPcie.c diff --git a/src/mainboard/micropassion/kratosx1/OptionsIds.h b/src/mainboard/micropassion/kratosx1/OptionsIds.h new file mode 100755 index 0000000..0a1d328 --- /dev/null +++ b/src/mainboard/micropassion/kratosx1/OptionsIds.h @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/** + * @file + * + * IDS Option File + * + * This file is used to switch on/off IDS features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Core + * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ + */ +#ifndef _OPTION_IDS_H_ +#define _OPTION_IDS_H_ + +/** + * + * This file generates the defaults tables for the Integrated Debug Support + * Module. The documented build options are imported from a user controlled + * file for processing. The build options for the Integrated Debug Support + * Module are listed below: + * + * IDSOPT_IDS_ENABLED + * IDSOPT_ERROR_TRAP_ENABLED + * IDSOPT_CONTROL_ENABLED + * IDSOPT_TRACING_ENABLED + * IDSOPT_PERF_ANALYSIS + * IDSOPT_ASSERT_ENABLED + * IDS_DEBUG_PORT + * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED + * + **/ + +#define IDSOPT_IDS_ENABLED TRUE +//#define IDSOPT_CONTROL_ENABLED TRUE +//#define IDSOPT_TRACING_ENABLED TRUE +#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE +//#define IDSOPT_PERF_ANALYSIS TRUE +#define IDSOPT_ASSERT_ENABLED TRUE +//#undef IDSOPT_DEBUG_ENABLED +//#define IDSOPT_DEBUG_ENABLED FALSE +//#undef IDSOPT_HOST_SIMNOW +//#define IDSOPT_HOST_SIMNOW FALSE +//#undef IDSOPT_HOST_HDT +//#define IDSOPT_HOST_HDT FALSE +//#define IDS_DEBUG_PORT 0x80 + +#endif diff --git a/src/mainboard/micropassion/kratosx1/PlatformGnbPcie.c b/src/mainboard/micropassion/kratosx1/PlatformGnbPcie.c new file mode 100755 index 0000000..ed6746f --- /dev/null +++ b/src/mainboard/micropassion/kratosx1/PlatformGnbPcie.c @@ -0,0 +1,154 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "heapManager.h" +#include "PlatformGnbPcieComplex.h" +#include "Filecode.h" + +#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE + +static const PCIe_PORT_DESCRIPTOR PortList [] = { + { + 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 3, 3), + PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 5, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x01, 0) + }, + /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */ + { + 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 2), + PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 4, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x02, 0) + }, + /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */ + { + 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 1, 1), + PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 3, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x03, 0) + }, + /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 0), + PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 2, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x04, 0) + }, + /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */ + { + DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7), + PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x05, 0) + } +}; + +static const PCIe_DDI_DESCRIPTOR DdiList [] = { + /* DP0 to LVDS */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeLvds, Aux1, Hdp1) + }, + /* DP1 to DVI */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeSingleLinkDVI, Aux2, Hdp2) + }, + /* DP2 to VGA */ + { + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 16, 19), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeCrt, Aux2, Hdp2) + }, +}; + +static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { + .Flags = DESCRIPTOR_TERMINATE_LIST, + .SocketId = 0, + .PciePortList = PortList, + .DdiLinkList = DdiList +}; + +/*---------------------------------------------------------------------------------------*/ +/** + * OemCustomizeInitEarly + * + * Description: + * This is the stub function will call the host environment through the binary block + * interface (call-out port) to provide a user hook opportunity + * + * Parameters: + * @param[in] **PeiServices + * @param[in] *InitEarly + * + * @retval VOID + * + **/ +/*---------------------------------------------------------------------------------------*/ +VOID +OemCustomizeInitEarly ( + IN OUT AMD_EARLY_PARAMS *InitEarly + ) +{ + AGESA_STATUS Status; + PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr; + + ALLOCATE_HEAP_PARAMS AllocHeapParams; + + /* GNB PCIe topology Porting */ + + /* */ + /* Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR */ + /* */ + AllocHeapParams.RequestedBufferSize = sizeof(PcieComplex); + + AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; + AllocHeapParams.Persist = HEAP_LOCAL_CACHE; + Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader); + if ( Status!= AGESA_SUCCESS) { + /* Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR */ + ASSERT(FALSE); + return; + } + + PcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; + LibAmdMemCopy (PcieComplexListPtr, &PcieComplex, sizeof(PcieComplex), &InitEarly->StdHeader); + InitEarly->GnbConfig.PcieComplexList = PcieComplexListPtr; +} diff --git a/src/mainboard/micropassion/kratosx1/PlatformGnbPcieComplex.h b/src/mainboard/micropassion/kratosx1/PlatformGnbPcieComplex.h new file mode 100755 index 0000000..1db8b2d --- /dev/null +++ b/src/mainboard/micropassion/kratosx1/PlatformGnbPcieComplex.h @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H +#define _PLATFORM_GNB_PCIE_COMPLEX_H + +#include "Porting.h" +#include "AGESA.h" +#include "amdlib.h" + +VOID +OemCustomizeInitEarly ( + IN OUT AMD_EARLY_PARAMS *InitEarly + ); + +#endif //_PLATFORM_GNB_PCIE_COMPLEX_H diff --git a/src/mainboard/micropassion/kratosx1/acpi/AmdImc.asl b/src/mainboard/micropassion/kratosx1/acpi/AmdImc.asl new file mode 100755 index 0000000..074dd7c --- /dev/null +++ b/src/mainboard/micropassion/kratosx1/acpi/AmdImc.asl @@ -0,0 +1,114 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +//BTDC Due to IMC Fan, ACPI control codes +OperationRegion(IMIO, SystemIO, 0x3E, 0x02) +Field(IMIO , ByteAcc, NoLock, Preserve) { + IMCX,8, + IMCA,8 +} + +IndexField(IMCX, IMCA, ByteAcc, NoLock, Preserve) { + Offset(0x80), + MSTI, 8, + MITS, 8, + MRG0, 8, + MRG1, 8, + MRG2, 8, + MRG3, 8, +} + +Method(WACK, 0) +{ + Store(0, Local0) + While (LNotEqual(Local0, 0xFA)) { + Store(MRG0, Local0) + Sleep(10) + } +} + +//Init +Method (ITZE, 0) +{ + Store(0, MRG0) + Store(0xB5, MRG1) + Store(0, MRG2) + Store(0x96, MSTI) + WACK() + + Store(0, MRG0) + Store(0, MRG1) + Store(0, MRG2) + Store(0x80, MSTI) + WACK() + + Or(MRG2, 0x01, Local0) + + Store(0, MRG0) + Store(0, MRG1) + Store(Local0, MRG2) + Store(0x81, MSTI) + WACK() +} + +//Sleep +Method (IMSP, 0) +{ + Store(0, MRG0) + Store(0xB5, MRG1) + Store(0, MRG2) + Store(0x96, MSTI) + WACK() + + Store(0, MRG0) + Store(1, MRG1) + Store(0, MRG2) + Store(0x98, MSTI) + WACK() + + Store(0, MRG0) + Store(0xB4, MRG1) + Store(0, MRG2) + Store(0x96, MSTI) + WACK() +} + +//Wake +Method (IMWK, 0) +{ + Store(0, MRG0) + Store(0xB5, MRG1) + Store(0, MRG2) + Store(0x96, MSTI) + WACK() + + Store(0, MRG0) + Store(0, MRG1) + Store(0, MRG2) + Store(0x80, MSTI) + WACK() + + Or(MRG2, 0x01, Local0) + + Store(0, MRG0) + Store(0, MRG1) + Store(Local0, MRG2) + Store(0x81, MSTI) + WACK() +} diff --git a/src/mainboard/micropassion/kratosx1/acpi/gpe.asl b/src/mainboard/micropassion/kratosx1/acpi/gpe.asl new file mode 100755 index 0000000..f294502 --- /dev/null +++ b/src/mainboard/micropassion/kratosx1/acpi/gpe.asl @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +Scope(\_GPE) { /* Start Scope GPE */ + + /* General event 3 */ + Method(_L03) { + /* DBGO("\\_GPE\\_L00\n") */ + Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Legacy PM event */ + Method(_L08) { + /* DBGO("\\_GPE\\_L08\n") */ + } + + /* Temp warning (TWarn) event */ + Method(_L09) { + /* DBGO("\\_GPE\\_L09\n") */ + /* Notify (\_TZ.TZ00, 0x80) */ + } + + /* USB controller PME# */ + Method(_L0B) { + /* DBGO("\\_GPE\\_L0B\n") */ + Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* ExtEvent0 SCI event */ + Method(_L10) { + /* DBGO("\\_GPE\\_L10\n") */ + } + + /* ExtEvent1 SCI event */ + Method(_L11) { + /* DBGO("\\_GPE\\_L11\n") */ + } + + /* GPIO0 or GEvent8 event */ + Method(_L18) { + /* DBGO("\\_GPE\\_L18\n") */ + Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Azalia SCI event */ + Method(_L1B) { + /* DBGO("\\_GPE\\_L1B\n") */ + Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } +} /* End Scope GPE */ diff --git a/src/mainboard/micropassion/kratosx1/acpi/ide.asl b/src/mainboard/micropassion/kratosx1/acpi/ide.asl new file mode 100755 index 0000000..853dc13 --- /dev/null +++ b/src/mainboard/micropassion/kratosx1/acpi/ide.asl @@ -0,0 +1,250 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012-2013 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* No IDE functionality */ + +#if 0 +/* +Scope (_SB) { + Device(PCI0) { + Device(IDEC) { + Name(_ADR, 0x00140001) + #include "ide.asl" + } + } +} +*/ + +/* Some timing tables */ +Name(UDTT, Package(){ /* Udma timing table */ + 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */ +}) + +Name(MDTT, Package(){ /* MWDma timing table */ + 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */ +}) + +Name(POTT, Package(){ /* Pio timing table */ + 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */ +}) + +/* Some timing register value tables */ +Name(MDRT, Package(){ /* MWDma timing register table */ + 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */ +}) + +Name(PORT, Package(){ + 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */ +}) + +OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */ + Field(ICRG, AnyAcc, NoLock, Preserve) +{ + PPTS, 8, /* Primary PIO Slave Timing */ + PPTM, 8, /* Primary PIO Master Timing */ + OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */ + PMTM, 8, /* Primary MWDMA Master Timing */ + OFFSET(0x08), PPCR, 8, /* Primary PIO Control */ + OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */ + PPSM, 4, /* Primary PIO slave Mode */ + OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */ + OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */ + PDSM, 4, /* Primary UltraDMA Mode */ +} + +Method(GTTM, 1) /* get total time*/ +{ + Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ + Increment(Local0) + Store(ShiftRight(Arg0, 4), Local1) /* Command Width */ + Increment(Local1) + Return(Multiply(30, Add(Local0, Local1))) +} + +Device(PRID) +{ + Name (_ADR, Zero) + Method(_GTM, 0) + { + NAME(OTBF, Buffer(20) { /* out buffer */ + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 + }) + + CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */ + CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */ + CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */ + CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */ + CreateDwordField(OTBF, 16, BFFG) /* buffer flags */ + + /* Just return if the channel is disabled */ + If(And(PPCR, 0x01)) { /* primary PIO control */ + Return(OTBF) + } + + /* Always tell them independent timing available and IOChannelReady used on both drives */ + Or(BFFG, 0x1A, BFFG) + + /* save total time of primary PIO master timing to PIO spd0 */ + Store(GTTM(PPTM), PSD0) + /* save total time of primary PIO slave Timing to PIO spd1 */ + Store(GTTM(PPTS), PSD1) + + If(And(PDCR, 0x01)) { /* It's under UDMA mode */ + Or(BFFG, 0x01, BFFG) + Store(DerefOf(Index(UDTT, PDMM)), DSD0) + } + Else { + Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */ + } + + If(And(PDCR, 0x02)) { /* It's under UDMA mode */ + Or(BFFG, 0x04, BFFG) + Store(DerefOf(Index(UDTT, PDSM)), DSD1) + } + Else { + Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */ + } + + Return(OTBF) /* out buffer */ + } /* End Method(_GTM) */ + + Method(_STM, 3, NotSerialized) + { + NAME(INBF, Buffer(20) { /* in buffer */ + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 + }) + + CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */ + CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */ + CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */ + CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */ + CreateDwordField(INBF, 16, BFFG) /*buffer flag */ + + Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0) + Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ + Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1) + Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */ + + Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */ + Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */ + + If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ + Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0) + Divide(Local0, 7, PDMM,) + Or(PDCR, 0x01, PDCR) + } + Else { + If(LNotEqual(DSD0, 0xFFFFFFFF)) { + Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0) + Store(DerefOf(Index(MDRT, Local0)), PMTM) + } + } + + If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ + Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0) + Divide(Local0, 7, PDSM,) + Or(PDCR, 0x02, PDCR) + } + Else { + If(LNotEqual(DSD1, 0xFFFFFFFF)) { + Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0) + Store(DerefOf(Index(MDRT, Local0)), PMTS) + } + } + /* Return(INBF) */ + } /*End Method(_STM) */ + Device(MST) + { + Name(_ADR, 0) + Method(_GTF) { + Name(CMBF, Buffer(21) { + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 + }) + CreateByteField(CMBF, 1, POMD) + CreateByteField(CMBF, 8, DMMD) + CreateByteField(CMBF, 5, CMDA) + CreateByteField(CMBF, 12, CMDB) + CreateByteField(CMBF, 19, CMDC) + + Store(0xA0, CMDA) + Store(0xA0, CMDB) + Store(0xA0, CMDC) + + Or(PPMM, 0x08, POMD) + + If(And(PDCR, 0x01)) { + Or(PDMM, 0x40, DMMD) + } + Else { + Store(Match + (MDTT, MLE, GTTM(PMTM), + MTR, 0, 0), Local0) + If(LLess(Local0, 3)) { + Or(0x20, Local0, DMMD) + } + } + Return(CMBF) + } + } /* End Device(MST) */ + + Device(SLAV) + { + Name(_ADR, 1) + Method(_GTF) { + Name(CMBF, Buffer(21) { + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 + }) + CreateByteField(CMBF, 1, POMD) + CreateByteField(CMBF, 8, DMMD) + CreateByteField(CMBF, 5, CMDA) + CreateByteField(CMBF, 12, CMDB) + CreateByteField(CMBF, 19, CMDC) + + Store(0xB0, CMDA) + Store(0xB0, CMDB) + Store(0xB0, CMDC) + + Or(PPSM, 0x08, POMD) + + If(And(PDCR, 0x02)) { + Or(PDSM, 0x40, DMMD) + } + Else { + Store(Match + (MDTT, MLE, GTTM(PMTS), + MTR, 0, 0), Local0) + If(LLess(Local0, 3)) { + Or(0x20, Local0, DMMD) + } + } + Return(CMBF) + } + } /* End Device(SLAV) */ +} +#endif diff --git a/src/mainboard/micropassion/kratosx1/acpi/mainboard.asl b/src/mainboard/micropassion/kratosx1/acpi/mainboard.asl new file mode 100755 index 0000000..5487b79 --- /dev/null +++ b/src/mainboard/micropassion/kratosx1/acpi/mainboard.asl @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Memory related values */ +Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ +Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ +Name(PBLN, 0x0) /* Length of BIOS area */ + +Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ +Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */ +Name(HPBA, 0xFED00000) /* Base address of HPET table */ + +Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ + +/* Some global data */ +Name(OSTP, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ +Name(OSV, Ones) /* Assume nothing */ +Name(PMOD, One) /* Assume APIC */ diff --git a/src/mainboard/micropassion/kratosx1/acpi/routing.asl b/src/mainboard/micropassion/kratosx1/acpi/routing.asl new file mode 100755 index 0000000..0b924a3 --- /dev/null +++ b/src/mainboard/micropassion/kratosx1/acpi/routing.asl @@ -0,0 +1,198 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 + ) + { + #include "routing.asl" + } +*/ + +/* Routing is in System Bus scope */ +Name(PR0, Package(){ + /* NB devices */ + /* Bus 0, Dev 0 - F16 Host Controller */ + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ + /* Bus 0, Dev 1, Func 1 - HDMI Audio Controller */ + Package(){0x0001FFFF, 0, INTB, 0 }, + Package(){0x0001FFFF, 1, INTC, 0 }, + + + /* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */ + Package(){0x0002FFFF, 0, INTC, 0 }, + Package(){0x0002FFFF, 1, INTD, 0 }, + Package(){0x0002FFFF, 2, INTA, 0 }, + Package(){0x0002FFFF, 3, INTB, 0 }, + + /* FCH devices */ + /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */ + Package(){0x0014FFFF, 0, INTA, 0 }, + Package(){0x0014FFFF, 1, INTB, 0 }, + Package(){0x0014FFFF, 2, INTC, 0 }, + Package(){0x0014FFFF, 3, INTD, 0 }, + + /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */ + /* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */ + Package(){0x0012FFFF, 0, INTC, 0 }, + Package(){0x0012FFFF, 1, INTB, 0 }, + + Package(){0x0013FFFF, 0, INTC, 0 }, + Package(){0x0013FFFF, 1, INTB, 0 }, + + Package(){0x0016FFFF, 0, INTC, 0 }, + Package(){0x0016FFFF, 1, INTB, 0 }, + + /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */ + Package(){0x0010FFFF, 0, INTC, 0 }, + Package(){0x0010FFFF, 1, INTB, 0 }, + + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, INTD, 0 }, + +}) + +Name(APR0, Package(){ + /* NB devices in APIC mode */ + /* Bus 0, Dev 0 - F15 Host Controller */ + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ + Package(){0x0001FFFF, 0, 0, 44 }, + Package(){0x0001FFFF, 1, 0, 45 }, + + /* Bus 0, Dev 2 - PCIe Bridges */ + Package(){0x0002FFFF, 0, 0, 18 }, + Package(){0x0002FFFF, 1, 0, 19 }, + Package(){0x0002FFFF, 2, 0, 16 }, + Package(){0x0002FFFF, 3, 0, 17 }, + + + /* SB devices in APIC mode */ + /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */ + Package(){0x0014FFFF, 0, 0, 16 }, + Package(){0x0014FFFF, 1, 0, 17 }, + Package(){0x0014FFFF, 2, 0, 18 }, + Package(){0x0014FFFF, 3, 0, 19 }, + + /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */ + /* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */ + Package(){0x0012FFFF, 0, 0, 18 }, + Package(){0x0012FFFF, 1, 0, 17 }, + + Package(){0x0013FFFF, 0, 0, 18 }, + Package(){0x0013FFFF, 1, 0, 17 }, + + Package(){0x0016FFFF, 0, 0, 18 }, + Package(){0x0016FFFF, 1, 0, 17 }, + + /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */ + Package(){0x0010FFFF, 0, 0, 0x12}, + Package(){0x0010FFFF, 1, 0, 0x11}, + + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, 0, 19 }, + +}) + +Name(PS2, Package(){ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, +}) +Name(APS2, Package(){ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, +}) + +/* GFX */ +Name(PS4, Package(){ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, +}) +Name(APS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, +}) + +/* GPP 0 */ +Name(PS5, Package(){ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, +}) +Name(APS5, Package(){ + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, +}) + +/* GPP 1 */ +Name(PS6, Package(){ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, +}) +Name(APS6, Package(){ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, +}) + +/* GPP 2 */ +Name(PS7, Package(){ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, +}) +Name(APS7, Package(){ + Package(){0x0000FFFF, 0, 0, 19 }, + Package(){0x0000FFFF, 1, 0, 16 }, + Package(){0x0000FFFF, 2, 0, 17 }, + Package(){0x0000FFFF, 3, 0, 18 }, +}) + +/* GPP 3 */ +Name(PS8, Package(){ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, +}) +Name(APS8, Package(){ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 18 }, +}) + diff --git a/src/mainboard/micropassion/kratosx1/acpi/sata.asl b/src/mainboard/micropassion/kratosx1/acpi/sata.asl new file mode 100755 index 0000000..3d19222 --- /dev/null +++ b/src/mainboard/micropassion/kratosx1/acpi/sata.asl @@ -0,0 +1,150 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012-2013 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* No SATA functionality */ + +#if 0 +/* +Scope (_SB) { + Device(PCI0) { + Device(SATA) { + Name(_ADR, 0x00110000) + #include "sata.asl" + } + } +} +*/ + +Name(STTM, Buffer(20) { + 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, + 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, + 0x1f, 0x00, 0x00, 0x00 +}) + +/* Start by clearing the PhyRdyChg bits */ +Method(_INI) { + \_GPE._L1F() +} + +Device(PMRY) +{ + Name(_ADR, 0) + Method(_GTM, 0x0, NotSerialized) { + Return(STTM) + } + Method(_STM, 0x3, NotSerialized) {} + + Device(PMST) { + Name(_ADR, 0) + Method(_STA,0) { + if (LGreater(P0IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + }/* end of PMST */ + + Device(PSLA) + { + Name(_ADR, 1) + Method(_STA,0) { + if (LGreater(P1IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of PSLA */ +} /* end of PMRY */ + +Device(SEDY) +{ + Name(_ADR, 1) /* IDE Scondary Channel */ + Method(_GTM, 0x0, NotSerialized) { + Return(STTM) + } + Method(_STM, 0x3, NotSerialized) {} + + Device(SMST) + { + Name(_ADR, 0) + Method(_STA,0) { + if (LGreater(P2IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of SMST */ + + Device(SSLA) + { + Name(_ADR, 1) + Method(_STA,0) { + if (LGreater(P3IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of SSLA */ +} /* end of SEDY */ + +/* SATA Hot Plug Support */ +Scope(\_GPE) { + Method(_L1F,0x0,NotSerialized) { + if (\_SB.P0PR) { + if (LGreater(\_SB.P0IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P0PR) + } + + if (\_SB.P1PR) { + if (LGreater(\_SB.P1IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P1PR) + } + + if (\_SB.P2PR) { + if (LGreater(\_SB.P2IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P2PR) + } + + if (\_SB.P3PR) { + if (LGreater(\_SB.P3IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P3PR) + } + } +} +#endif diff --git a/src/mainboard/micropassion/kratosx1/acpi/si.asl b/src/mainboard/micropassion/kratosx1/acpi/si.asl new file mode 100755 index 0000000..3cc2170 --- /dev/null +++ b/src/mainboard/micropassion/kratosx1/acpi/si.asl @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +Scope(\_SI) { + Method(_SST, 1) { + /* DBGO("\\_SI\\_SST\n") */ + /* DBGO(" New Indicator state: ") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + } +} /* End Scope SI */ diff --git a/src/mainboard/micropassion/kratosx1/acpi/sleep.asl b/src/mainboard/micropassion/kratosx1/acpi/sleep.asl new file mode 100755 index 0000000..dd0d9a4 --- /dev/null +++ b/src/mainboard/micropassion/kratosx1/acpi/sleep.asl @@ -0,0 +1,89 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Wake status package */ +Name(WKST,Package(){Zero, Zero}) + +/* +* \_PTS - Prepare to Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2, etc +* +* Exit: +* -none- +* +* The _PTS control method is executed at the beginning of the sleep process +* for S1-S5. The sleeping value is passed to the _PTS control method. This +* control method may be executed a relatively long time before entering the +* sleep state and the OS may abort the operation without notification to +* the ACPI driver. This method cannot modify the configuration or power +* state of any device in the system. +*/ +Method(_PTS, 1) { + /* DBGO("\\_PTS\n") */ + /* DBGO("From S0 to S") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + + /* Clear wake status structure. */ + Store(0, Index(WKST,0)) + Store(0, Index(WKST,1)) + Store(7, UPWS) +} /* End Method(\_PTS) */ + +/* +* \_BFS OEM Back From Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* -none- +*/ +Method(\_BFS, 1) { + /* DBGO("\\_BFS\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ +} + +/* +* \_WAK System Wake method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* Return package of 2 DWords +* Dword 1 - Status +* 0x00000000 wake succeeded +* 0x00000001 Wake was signaled but failed due to lack of power +* 0x00000002 Wake was signaled but failed due to thermal condition +* Dword 2 - Power Supply state +* if non-zero the effective S-state the power supply entered +*/ +Method(\_WAK, 1) { + /* DBGO("\\_WAK\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + + Return(WKST) +} /* End Method(\_WAK) */ diff --git a/src/mainboard/micropassion/kratosx1/acpi/superio.asl b/src/mainboard/micropassion/kratosx1/acpi/superio.asl new file mode 100755 index 0000000..ec72e36 --- /dev/null +++ b/src/mainboard/micropassion/kratosx1/acpi/superio.asl @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* No Super I/O device or functionality yet */ diff --git a/src/mainboard/micropassion/kratosx1/acpi/thermal.asl b/src/mainboard/micropassion/kratosx1/acpi/thermal.asl new file mode 100755 index 0000000..0466a1b --- /dev/null +++ b/src/mainboard/micropassion/kratosx1/acpi/thermal.asl @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* No thermal zone functionality */ diff --git a/src/mainboard/micropassion/kratosx1/acpi/usb_oc.asl b/src/mainboard/micropassion/kratosx1/acpi/usb_oc.asl new file mode 100755 index 0000000..e0a9143 --- /dev/null +++ b/src/mainboard/micropassion/kratosx1/acpi/usb_oc.asl @@ -0,0 +1,132 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* simple name description */ +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 + ) + { + #include "usb.asl" + } +*/ + +/* USB overcurrent mapping pins. */ +Name(UOM0, 0) +Name(UOM1, 2) +Name(UOM2, 0) +Name(UOM3, 7) +Name(UOM4, 2) +Name(UOM5, 2) +Name(UOM6, 6) +Name(UOM7, 2) +Name(UOM8, 6) +Name(UOM9, 6) + +/* USB Overcurrent GPEs */ + +#if 0 /* TODO: Update for Olivehill */ +Method(UCOC, 0) { + Sleep(20) + Store(0x13,CMTI) + Store(0,GPSL) +} + +/* USB Port 0 overcurrent uses Gpm 0 */ +If(LLessEqual(UOM0,9)) { + Scope (\_GPE) { + Method (_L13) { + } + } +} + +/* USB Port 1 overcurrent uses Gpm 1 */ +If (LLessEqual(UOM1,9)) { + Scope (\_GPE) { + Method (_L14) { + } + } +} + +/* USB Port 2 overcurrent uses Gpm 2 */ +If (LLessEqual(UOM2,9)) { + Scope (\_GPE) { + Method (_L15) { + } + } +} + +/* USB Port 3 overcurrent uses Gpm 3 */ +If (LLessEqual(UOM3,9)) { + Scope (\_GPE) { + Method (_L16) { + } + } +} + +/* USB Port 4 overcurrent uses Gpm 4 */ +If (LLessEqual(UOM4,9)) { + Scope (\_GPE) { + Method (_L19) { + } + } +} + +/* USB Port 5 overcurrent uses Gpm 5 */ +If (LLessEqual(UOM5,9)) { + Scope (\_GPE) { + Method (_L1A) { + } + } +} + +/* USB Port 6 overcurrent uses Gpm 6 */ +If (LLessEqual(UOM6,9)) { + Scope (\_GPE) { + /* Method (_L1C) { */ + Method (_L06) { + } + } +} + +/* USB Port 7 overcurrent uses Gpm 7 */ +If (LLessEqual(UOM7,9)) { + Scope (\_GPE) { + /* Method (_L1D) { */ + Method (_L07) { + } + } +} + +/* USB Port 8 overcurrent uses Gpm 8 */ +If (LLessEqual(UOM8,9)) { + Scope (\_GPE) { + Method (_L17) { + } + } +} + +/* USB Port 9 overcurrent uses Gpm 9 */ +If (LLessEqual(UOM9,9)) { + Scope (\_GPE) { + Method (_L0E) { + } + } +} +#endif diff --git a/src/mainboard/micropassion/kratosx1/acpi_tables.c b/src/mainboard/micropassion/kratosx1/acpi_tables.c new file mode 100755 index 0000000..b5ae758 --- /dev/null +++ b/src/mainboard/micropassion/kratosx1/acpi_tables.c @@ -0,0 +1,333 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <string.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <arch/ioapic.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/x86/msr.h> +#include "agesawrapper.h" +#include <cpu/amd/mtrr.h> +#include <cpu/amd/amdfam16.h> + +#include "agesawrapper.h" + +#define DUMP_ACPI_TABLES 0 + +#if DUMP_ACPI_TABLES == 1 + +static void dump_mem(u32 start, u32 end) +{ + u32 i; + print_debug("dump_mem:"); + for (i = start; i < end; i++) { + if ((i & 0xf) == 0) { + printk(BIOS_DEBUG, "\n%08x:", i); + } + printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i)); + } + print_debug("\n"); +} +#endif + +extern const unsigned char AmlCode[]; + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + /* Just a dummy */ + return current; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + /* Write SB800 IOAPIC, only one */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, + IO_APIC_ADDR, 0); + + /* TODO: Remove the hardcode */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS+1, + 0xFEC20000, 24); + + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, 0xF); + /* 0: mean bus 0--->ISA */ + /* 0: PIC 0 */ + /* 2: APIC 2 */ + /* 5 mean: 0101 --> Edige-triggered, Active high */ + + /* create all subtables for processors */ + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1); + /* 1: LINT1 connect to NMI */ + + return current; +} + +unsigned long acpi_fill_hest(acpi_hest_t *hest) +{ + void *addr, *current; + + /* Skip the HEST header. */ + current = (void *)(hest + 1); + + addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); + if (addr != NULL) + current += acpi_create_hest_error_source(hest, current, 0, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + + addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); + if (addr != NULL) + current += acpi_create_hest_error_source(hest, current, 1, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + + return (unsigned long)current; +} + +unsigned long acpi_fill_slit(unsigned long current) +{ + /* Not implemented */ + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + /* No NUMA, no SRAT */ + return current; +} + +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) +{ + int lens; + msr_t msr; + char pscope[] = "\\_SB.PCI0"; + + lens = acpigen_write_scope(pscope); + msr = rdmsr(TOP_MEM); + lens += acpigen_write_name_dword("TOM1", msr.lo); + msr = rdmsr(TOP_MEM2); + /* + * Since XP only implements parts of ACPI 2.0, we can't use a qword + * here. + * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt + * slide 22ff. + * Shift value right by 20 bit to make it fit into 32bit, + * giving us 1MB granularity and a limit of almost 4Exabyte of memory. + */ + lens += acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20); + acpigen_patch_len(lens - 1); + return (unsigned long) (acpigen_get_current()); +} + +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + acpi_rsdp_t *rsdp; + acpi_rsdt_t *rsdt; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_srat_t *srat; + acpi_slit_t *slit; + acpi_fadt_t *fadt; + acpi_facs_t *facs; + acpi_header_t *dsdt; + acpi_header_t *ssdt; + acpi_header_t *alib; + acpi_header_t *ivrs; + acpi_hest_t *hest; + + get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ + + /* Align ACPI tables to 16 bytes */ + start = ALIGN(start, 16); + current = start; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + + /* clear all table memory */ + memset((void *)start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, NULL); + acpi_write_rsdt(rsdt); + + /* DSDT */ + current = ALIGN(current, 8); + printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); + dsdt = (acpi_header_t *)current; /* it will used by fadt */ + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); + + /* FACS */ /* it needs 64 bit alignment */ + current = ALIGN(current, 8); + printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); + facs = (acpi_facs_t *) current; /* it will be used by fadt */ + current += sizeof(acpi_facs_t); + acpi_create_facs(facs); + + /* FADT */ + current = ALIGN(current, 8); + printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + + /* + * We explicitly add these tables later on: + */ + current = ALIGN(current, 8); + printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); + hpet = (acpi_hpet_t *) current; + current += sizeof(acpi_hpet_t); + acpi_create_hpet(hpet); + acpi_add_table(rsdp, hpet); + + /* If we want to use HPET Timers Linux wants an MADT */ + current = ALIGN(current, 8); + printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + acpi_add_table(rsdp, madt); + + /* HEST */ + current = ALIGN(current, 8); + hest = (acpi_hest_t *)current; + acpi_write_hest((void *)current); + acpi_add_table(rsdp, (void *)current); + current += ((acpi_header_t *)current)->length; + + current = ALIGN(current, 8); + printk(BIOS_DEBUG, "ACPI: * IVRS at %lx\n", current); + ivrs = agesawrapper_getlateinitptr(PICK_IVRS); + if (ivrs != NULL) { + memcpy((void *)current, ivrs, ivrs->length); + ivrs = (acpi_header_t *) current; + current += ivrs->length; + acpi_add_table(rsdp, ivrs); + } else { + printk(BIOS_DEBUG, " AGESA IVRS table NULL. Skipping.\n"); + } + + /* SRAT */ + current = ALIGN(current, 8); + printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); + srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); + if (srat != NULL) { + memcpy((void *)current, srat, srat->header.length); + srat = (acpi_srat_t *) current; + current += srat->header.length; + acpi_add_table(rsdp, srat); + } else { + printk(BIOS_DEBUG, " AGESA SRAT table NULL. Skipping.\n"); + } + + /* SLIT */ + current = ALIGN(current, 8); + printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); + slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); + if (slit != NULL) { + memcpy((void *)current, slit, slit->header.length); + slit = (acpi_slit_t *) current; + current += slit->header.length; + acpi_add_table(rsdp, slit); + } else { + printk(BIOS_DEBUG, " AGESA SLIT table NULL. Skipping.\n"); + } + + /* ALIB */ + current = ALIGN(current, 16); + printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); + alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); + if (alib != NULL) { + memcpy((void *)current, alib, alib->length); + alib = (acpi_header_t *) current; + current += alib->length; + acpi_add_table(rsdp, (void *)alib); + } + else { + printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); + } + + /* this pstate ssdt may cause Blue Screen: Fixed: Keep this comment for a while. */ + /* SSDT */ + current = ALIGN(current, 16); + printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); + ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); + if (ssdt != NULL) { + memcpy((void *)current, ssdt, ssdt->length); + ssdt = (acpi_header_t *) current; + current += ssdt->length; + } + else { + printk(BIOS_DEBUG, " AGESA PState table NULL. Skipping.\n"); + } + acpi_add_table(rsdp,ssdt); + + printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); + + printk(BIOS_DEBUG, "ACPI: * SSDT\n"); + ssdt = (acpi_header_t *)current; + + acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + +#if DUMP_ACPI_TABLES == 1 + printk(BIOS_DEBUG, "rsdp\n"); + dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t)); + + printk(BIOS_DEBUG, "rsdt\n"); + dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t)); + + printk(BIOS_DEBUG, "madt\n"); + dump_mem(madt, ((void *)madt) + madt->header.length); + + printk(BIOS_DEBUG, "srat\n"); + dump_mem(srat, ((void *)srat) + srat->header.length); + + printk(BIOS_DEBUG, "slit\n"); + dump_mem(slit, ((void *)slit) + slit->header.length); + + printk(BIOS_DEBUG, "ssdt\n"); + dump_mem(ssdt, ((void *)ssdt) + ssdt->length); + + printk(BIOS_DEBUG, "fadt\n"); + dump_mem(fadt, ((void *)fadt) + fadt->header.length); + + printk(BIOS_DEBUG, "hest\n"); + dump_mem(hest, ((void *)hest) + hest->header.length); +#endif + + printk(BIOS_INFO, "ACPI: done.\n"); + return current; +} diff --git a/src/mainboard/micropassion/kratosx1/agesawrapper.c b/src/mainboard/micropassion/kratosx1/agesawrapper.c new file mode 100755 index 0000000..06405ad --- /dev/null +++ b/src/mainboard/micropassion/kratosx1/agesawrapper.c @@ -0,0 +1,771 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include <stdint.h> +#include <string.h> +#include "agesawrapper.h" +#include "BiosCallOuts.h" +#include "cpuRegisters.h" +#include "cpuCacheInit.h" +#include "cpuApicUtilities.h" +#include "cpuEarlyInit.h" +#include "cpuLateInit.h" +#include "Dispatcher.h" +#include "cpuCacheInit.h" +#include "amdlib.h" +#include "PlatformGnbPcieComplex.h" +#include "Filecode.h" +#include "heapManager.h" +#include "FchPlatform.h" +#include "Fch.h" +#include <cpu/amd/agesa/s3_resume.h> +#include <cbmem.h> +#include <arch/acpi.h> +#include <arch/io.h> + +VOID FchInitS3LateRestore (IN FCH_DATA_BLOCK *FchDataPtr); +VOID FchInitS3EarlyRestore (IN FCH_DATA_BLOCK *FchDataPtr); + +#define FILECODE UNASSIGNED_FILE_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/* ACPI table pointers returned by AmdInitLate */ +VOID *DmiTable = NULL; +VOID *AcpiPstate = NULL; +VOID *AcpiSrat = NULL; +VOID *AcpiSlit = NULL; + +VOID *AcpiWheaMce = NULL; +VOID *AcpiWheaCmc = NULL; +VOID *AcpiAlib = NULL; +VOID *AcpiIvrs = NULL; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ +UINT32 +agesawrapper_amdinitcpuio ( + VOID + ) +{ + AGESA_STATUS Status; + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; + + /* Enable legacy video routing: D18F1xF4 VGA Enable */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4); + PciData = 1; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* The platform BIOS needs to ensure the memory ranges of SB800 legacy + * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are + * set to non-posted regions. + */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84); + PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */ + PciData |= 1 << 7; /* set NP (non-posted) bit */ + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80); + PciData = (0xFED00000 >> 8) | 3; /* lowest NP address is HPET at FED00000 */ + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Map the remaining PCI hole as posted MMIO */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C); + PciData = 0x00FECF00; /* last address before non-posted range */ + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); + MsrReg = (MsrReg >> 8) | 3; + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88); + PciData = (UINT32)MsrReg; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Send all IO (0000-FFFF) to southbridge. */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4); + PciData = 0x0000F000; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0); + PciData = 0x00000003; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + Status = AGESA_SUCCESS; + return (UINT32)Status; +} + +UINT32 +agesawrapper_amdinitmmio ( + VOID + ) +{ + AGESA_STATUS Status; + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; + + /* + Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base + Address MSR register. + */ + MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; + LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); + + /* + Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. + */ + LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader); + MsrReg = MsrReg | 0x0000400000000000; + LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); + + /* For serial port */ + PciData = 0xFF03FFD5; + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44); + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Set ROM cache onto WP to decrease post time */ + MsrReg = (0x0100000000ull - CONFIG_ROM_SIZE) | 5ull; + LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); + MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800ull; + LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); + + Status = AGESA_SUCCESS; + return (UINT32)Status; +} + +UINT32 +agesawrapper_amdinitreset ( + VOID + ) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_RESET_PARAMS AmdResetParams; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + LibAmdMemFill (&AmdResetParams, + 0, + sizeof (AMD_RESET_PARAMS), + &(AmdResetParams.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; + AmdParamStruct.AllocationMethod = ByHost; + AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS); + AmdParamStruct.NewStructPtr = &AmdResetParams; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + AmdResetParams.HtConfig.Depth = 0; +#if !CONFIG_HUDSON_XHCI_ENABLE + AmdResetParams.FchInterface.Xhci0Enable = FALSE; +#endif + AmdResetParams.FchInterface.Xhci1Enable = FALSE; + + status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AmdReleaseStruct (&AmdParamStruct); + return (UINT32)status; +} + +UINT32 +agesawrapper_amdinitearly ( + VOID + ) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_EARLY_PARAMS *AmdEarlyParamsPtr; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + + AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr; + OemCustomizeInitEarly (AmdEarlyParamsPtr); + + status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AmdReleaseStruct (&AmdParamStruct); + + return (UINT32)status; +} + +UINT32 GetHeapBase( + AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 heap; + +#if CONFIG_HAVE_ACPI_RESUME + /* Both romstage and ramstage has this S3 detect. */ + if (acpi_get_sleep_type() == 3) + heap = (UINT32)cbmem_find(CBMEM_ID_RESUME_SCRATCH) + (CONFIG_HIGH_SCRATCH_MEMORY_SIZE - BIOS_HEAP_SIZE); /* base + high_stack_size */ + else +#endif + heap = BIOS_HEAP_START_ADDRESS; /* Low mem */ + + return heap; +} + +UINT32 +agesawrapper_amdinitpost ( + VOID + ) +{ + AGESA_STATUS status; + UINT16 i; + UINT32 *HeadPtr; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_POST_PARAMS *PostParams; + BIOS_HEAP_MANAGER *BiosManagerPtr; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + AmdCreateStruct (&AmdParamStruct); + PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr; + status = AmdInitPost (PostParams); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(PostParams->StdHeader.HeapStatus); + AmdReleaseStruct (&AmdParamStruct); + /* Initialize heap space */ + BiosManagerPtr = (BIOS_HEAP_MANAGER *)GetHeapBase(&AmdParamStruct.StdHeader); + + HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER)); + for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++) + { + *HeadPtr = 0x00000000; + HeadPtr++; + } + BiosManagerPtr->StartOfAllocatedNodes = 0; + BiosManagerPtr->StartOfFreedNodes = 0; + + return (UINT32)status; +} + +UINT32 +agesawrapper_amdinitenv ( + VOID + ) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_ENV_PARAMS *EnvParam; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + status = AmdCreateStruct (&AmdParamStruct); + EnvParam = (AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr; + + status = AmdInitEnv (EnvParam); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(EnvParam->StdHeader.HeapStatus); + /* Initialize Subordinate Bus Number and Secondary Bus Number + * In platform BIOS this address is allocated by PCI enumeration code + Modify D1F0x18 + */ + + return (UINT32)status; +} + +VOID * +agesawrapper_getlateinitptr ( + int pick + ) +{ + switch (pick) { + case PICK_DMI: + return DmiTable; + case PICK_PSTATE: + return AcpiPstate; + case PICK_SRAT: + return AcpiSrat; + case PICK_SLIT: + return AcpiSlit; + case PICK_WHEA_MCE: + return AcpiWheaMce; + case PICK_WHEA_CMC: + return AcpiWheaCmc; + case PICK_ALIB: + return AcpiAlib; + case PICK_IVRS: + return AcpiIvrs; + default: + return NULL; + } +} + +UINT32 +agesawrapper_amdinitmid ( + VOID + ) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + + /* Enable MMIO on AMD CPU Address Map Controller */ + agesawrapper_amdinitcpuio (); + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + AmdCreateStruct (&AmdParamStruct); + + ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr)->GnbMidConfiguration.iGpuVgaMode = 0;/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ + status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AmdReleaseStruct (&AmdParamStruct); + + return (UINT32)status; +} + +UINT32 +agesawrapper_amdinitlate ( + VOID + ) +{ + AGESA_STATUS Status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_LATE_PARAMS *AmdLateParams; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + /* NOTE: if not call amdcreatestruct, the initializer(AmdInitLateInitializer) would not be called */ + AmdCreateStruct(&AmdParamStruct); + AmdLateParams = (AMD_LATE_PARAMS *)AmdParamStruct.NewStructPtr; + Status = AmdInitLate(AmdLateParams); + /* CDIT table is not created. */ + if (Status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(AmdLateParams->StdHeader.HeapStatus); + ASSERT(Status == AGESA_SUCCESS); + } + + DmiTable = AmdLateParams->DmiTable; + AcpiPstate = AmdLateParams->AcpiPState; + AcpiSrat = AmdLateParams->AcpiSrat; + AcpiSlit = AmdLateParams->AcpiSlit; + + AcpiWheaMce = AmdLateParams->AcpiWheaMce; + AcpiWheaCmc = AmdLateParams->AcpiWheaCmc; + AcpiAlib = AmdLateParams->AcpiAlib; + AcpiIvrs = AmdLateParams->AcpiIvrs; + + printk(BIOS_DEBUG, "DmiTable:%x, AcpiPstatein: %x, AcpiSrat:%x," + "AcpiSlit:%x, Mce:%x, Cmc:%x," + "Alib:%x, AcpiIvrs:%x in %s\n", + (unsigned int)DmiTable, (unsigned int)AcpiPstate, (unsigned int)AcpiSrat, + (unsigned int)AcpiSlit, (unsigned int)AcpiWheaMce, (unsigned int)AcpiWheaCmc, + (unsigned int)AcpiAlib, (unsigned int)AcpiIvrs, __func__); + + /* AmdReleaseStruct (&AmdParamStruct); */ + return (UINT32)Status; +} + +UINT32 +agesawrapper_amdlaterunaptask ( + UINT32 Func, + UINT32 Data, + VOID *ConfigPtr + ) +{ + AGESA_STATUS Status; + AP_EXE_PARAMS ApExeParams; + + LibAmdMemFill (&ApExeParams, + 0, + sizeof (AP_EXE_PARAMS), + &(ApExeParams.StdHeader)); + + ApExeParams.StdHeader.AltImageBasePtr = 0; + ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + ApExeParams.StdHeader.Func = 0; + ApExeParams.StdHeader.ImageBasePtr = 0; + ApExeParams.FunctionNumber = Func; + ApExeParams.RelatedDataBlock = ConfigPtr; + + Status = AmdLateRunApTask (&ApExeParams); + if (Status != AGESA_SUCCESS) { + /* agesawrapper_amdreadeventlog(); */ + ASSERT(Status == AGESA_SUCCESS); + } + + return (UINT32)Status; +} + +#if CONFIG_HAVE_ACPI_RESUME + +UINT32 agesawrapper_amdinitresume(VOID) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_RESUME_PARAMS *AmdResumeParamsPtr; + S3_DATA_TYPE S3DataType; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + + AmdResumeParamsPtr = (AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr; + + AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0; + AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0; + S3DataType = S3DataTypeNonVolatile; + OemAgesaGetS3Info (S3DataType, + (u32 *) &AmdResumeParamsPtr->S3DataBlock.NvStorageSize, + (void **) &AmdResumeParamsPtr->S3DataBlock.NvStorage); + + status = AmdInitResume ((AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr); + + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AmdReleaseStruct (&AmdParamStruct); + + return (UINT32)status; +} + +#ifndef __PRE_RAM__ + +extern FCH_DATA_BLOCK InitEnvCfgDefault; +STATIC VOID s3_resume_init_data(FCH_DATA_BLOCK *FchParams) +{ + FchParams->Gpp.GppLinkConfig = UserOptions.FchBldCfg->CfgFchGppLinkConfig; + FchParams->Gpp.PortCfg[0].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort0Present; + FchParams->Gpp.PortCfg[1].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort1Present; + FchParams->Gpp.PortCfg[2].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort2Present; + FchParams->Gpp.PortCfg[3].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort3Present; + FchParams->Gpp.PortCfg[0].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort0HotPlug; + FchParams->Gpp.PortCfg[1].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort1HotPlug; + FchParams->Gpp.PortCfg[2].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort2HotPlug; + FchParams->Gpp.PortCfg[3].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort3HotPlug; + FchParams->Gpp.GppFunctionEnable = TRUE; /* GppEnable */ + FchParams->Gpp.GppPhyPllPowerDown = TRUE; + FchParams->Gpp.GppDynamicPowerSaving = TRUE; + FchParams->Gpp.UmiPhyPllPowerDown = TRUE; + FchParams->Gpp.NewGppAlgorithm = TRUE; + FchParams->Gpp.GppPortMinPollingTime = 40; + + FchParams->Spi.SpiSpeed = 2; + FchParams->Ir.IrConfig = 3; + + FchParams->HwAcpi.Smbus0BaseAddress = UserOptions.FchBldCfg->CfgSmbus0BaseAddress; + FchParams->HwAcpi.Smbus1BaseAddress = UserOptions.FchBldCfg->CfgSmbus1BaseAddress; + FchParams->HwAcpi.SioPmeBaseAddress = UserOptions.FchBldCfg->CfgSioPmeBaseAddress; + FchParams->HwAcpi.AcpiPm1EvtBlkAddr = UserOptions.FchBldCfg->CfgAcpiPm1EvtBlkAddr; + FchParams->HwAcpi.AcpiPm1CntBlkAddr = UserOptions.FchBldCfg->CfgAcpiPm1CntBlkAddr; + FchParams->HwAcpi.AcpiPmTmrBlkAddr = UserOptions.FchBldCfg->CfgAcpiPmTmrBlkAddr; + FchParams->HwAcpi.CpuControlBlkAddr = UserOptions.FchBldCfg->CfgCpuControlBlkAddr; + FchParams->HwAcpi.AcpiGpe0BlkAddr = UserOptions.FchBldCfg->CfgAcpiGpe0BlkAddr; + FchParams->HwAcpi.SmiCmdPortAddr = UserOptions.FchBldCfg->CfgSmiCmdPortAddr; + FchParams->HwAcpi.AcpiPmaCntBlkAddr = UserOptions.FchBldCfg->CfgAcpiPmaCntBlkAddr; + FchParams->HwAcpi.WatchDogTimerBase = UserOptions.FchBldCfg->CfgWatchDogTimerBase; + FchParams->Sata.SataRaid5Ssid = UserOptions.FchBldCfg->CfgSataRaid5Ssid; + FchParams->Sata.SataRaidSsid = UserOptions.FchBldCfg->CfgSataRaidSsid; + FchParams->Sata.SataAhciSsid = UserOptions.FchBldCfg->CfgSataAhciSsid; + FchParams->Sata.SataIdeSsid = UserOptions.FchBldCfg->CfgSataIdeSsid; + FchParams->Spi.RomBaseAddress = UserOptions.FchBldCfg->CfgSpiRomBaseAddress; + FchParams->Sd.SdSsid = UserOptions.FchBldCfg->CfgSdSsid; + FchParams->Spi.LpcSsid = UserOptions.FchBldCfg->CfgLpcSsid; + FchParams->Hpet.HpetBase = UserOptions.FchBldCfg->CfgHpetBaseAddress; + FchParams->Azalia.AzaliaSsid = UserOptions.FchBldCfg->CfgAzaliaSsid; + FchParams->Smbus.SmbusSsid = UserOptions.FchBldCfg->CfgSmbusSsid; + FchParams->Ide.IdeSsid = UserOptions.FchBldCfg->CfgIdeSsid; + FchParams->Usb.EhciSsid = UserOptions.FchBldCfg->CfgEhciSsid; + FchParams->Usb.OhciSsid = UserOptions.FchBldCfg->CfgOhciSsid; + FchParams->Usb.XhciSsid = UserOptions.FchBldCfg->CfgXhciSsid; + FchParams->Ir.IrPinControl = UserOptions.FchBldCfg->CfgFchIrPinControl; + FchParams->Sd.SdClockControl = UserOptions.FchBldCfg->CfgFchSdClockControl; +} + +UINT32 agesawrapper_fchs3earlyrestore (VOID) +{ + AGESA_STATUS status = AGESA_SUCCESS; + + FCH_DATA_BLOCK FchParams; + AMD_CONFIG_PARAMS StdHeader; + + StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10; + StdHeader.AltImageBasePtr = 0; + StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + StdHeader.Func = 0; + StdHeader.ImageBasePtr = 0; + + FchParams = InitEnvCfgDefault; + FchParams.StdHeader = &StdHeader; + s3_resume_init_data(&FchParams); + + FchInitS3EarlyRestore(&FchParams); + + return status; +} +#endif + +UINT32 agesawrapper_amds3laterestore (VOID) +{ + AGESA_STATUS Status; + AMD_INTERFACE_PARAMS AmdInterfaceParams; + AMD_S3LATE_PARAMS AmdS3LateParams; + AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; + S3_DATA_TYPE S3DataType; + + agesawrapper_amdinitcpuio(); + LibAmdMemFill (&AmdS3LateParams, + 0, + sizeof (AMD_S3LATE_PARAMS), + &(AmdS3LateParams.StdHeader)); + AmdInterfaceParams.StdHeader.ImageBasePtr = 0; + AmdInterfaceParams.AllocationMethod = ByHost; + AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; + AmdInterfaceParams.NewStructPtr = &AmdS3LateParams; + AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdS3LateParamsPtr = &AmdS3LateParams; + AmdInterfaceParams.NewStructSize = sizeof (AMD_S3LATE_PARAMS); + + AmdCreateStruct (&AmdInterfaceParams); + + AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0; + S3DataType = S3DataTypeVolatile; + + OemAgesaGetS3Info (S3DataType, + (u32 *) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize, + (void **) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); + + Status = AmdS3LateRestore (AmdS3LateParamsPtr); + if (Status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(AmdInterfaceParams.StdHeader.HeapStatus); + ASSERT(Status == AGESA_SUCCESS); + } + + return (UINT32)Status; +} + +#ifndef __PRE_RAM__ + +extern UINT8 picr_data[0x54], intr_data[0x54]; + +UINT32 agesawrapper_fchs3laterestore (VOID) +{ + AGESA_STATUS status = AGESA_SUCCESS; + + FCH_DATA_BLOCK FchParams; + AMD_CONFIG_PARAMS StdHeader; + UINT8 byte; + + StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10; + StdHeader.AltImageBasePtr = 0; + StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + StdHeader.Func = 0; + StdHeader.ImageBasePtr = 0; + + FchParams = InitEnvCfgDefault; + FchParams.StdHeader = &StdHeader; + s3_resume_init_data(&FchParams); + FchInitS3LateRestore(&FchParams); + /* PIC IRQ routine */ + for (byte = 0x0; byte < sizeof(picr_data); byte ++) { + outb(byte, 0xC00); + outb(picr_data[byte], 0xC01); + } + + /* APIC IRQ routine */ + for (byte = 0x0; byte < sizeof(intr_data); byte ++) { + outb(byte | 0x80, 0xC00); + outb(intr_data[byte], 0xC01); + } + + return status; +} +#endif + +#ifndef __PRE_RAM__ + +UINT32 agesawrapper_amdS3Save(VOID) +{ + AGESA_STATUS Status; + AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; + AMD_INTERFACE_PARAMS AmdInterfaceParams; + S3_DATA_TYPE S3DataType; + + LibAmdMemFill (&AmdInterfaceParams, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdInterfaceParams.StdHeader)); + + AmdInterfaceParams.StdHeader.ImageBasePtr = 0; + AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdInterfaceParams.AllocationMethod = PostMemDram; + AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE; + AmdInterfaceParams.StdHeader.AltImageBasePtr = 0; + AmdInterfaceParams.StdHeader.Func = 0; + + AmdCreateStruct(&AmdInterfaceParams); + AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *)AmdInterfaceParams.NewStructPtr; + AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; + + Status = AmdS3Save(AmdS3SaveParamsPtr); + if (Status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(AmdInterfaceParams.StdHeader.HeapStatus); + ASSERT(Status == AGESA_SUCCESS); + } + + S3DataType = S3DataTypeNonVolatile; + printk(BIOS_DEBUG, "NvStorageSize=%x, NvStorage=%x\n", + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorage); + + Status = OemAgesaSaveS3Info ( + S3DataType, + AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, + AmdS3SaveParamsPtr->S3DataBlock.NvStorage); + + printk(BIOS_DEBUG, "VolatileStorageSize=%x, VolatileStorage=%x\n", + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); + + if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) { + S3DataType = S3DataTypeVolatile; + + Status = OemAgesaSaveS3Info ( + S3DataType, + AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, + AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); + } + OemAgesaSaveMtrr(); + + AmdReleaseStruct (&AmdInterfaceParams); + + return (UINT32)Status; +} + +#endif /* #ifndef __PRE_RAM__ */ +#endif /* CONFIG_HAVE_ACPI_RESUME */ + +UINT32 +agesawrapper_amdreadeventlog ( + UINT8 HeapStatus + ) +{ + AGESA_STATUS Status; + EVENT_PARAMS AmdEventParams; + + LibAmdMemFill (&AmdEventParams, + 0, + sizeof (EVENT_PARAMS), + &(AmdEventParams.StdHeader)); + + AmdEventParams.StdHeader.AltImageBasePtr = 0; + AmdEventParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdEventParams.StdHeader.Func = 0; + AmdEventParams.StdHeader.ImageBasePtr = 0; + AmdEventParams.StdHeader.HeapStatus = HeapStatus; + Status = AmdReadEventLog (&AmdEventParams); + while (AmdEventParams.EventClass != 0) { + printk(BIOS_DEBUG,"\nEventLog: EventClass = %x, EventInfo = %x.\n", (unsigned int)AmdEventParams.EventClass,(unsigned int)AmdEventParams.EventInfo); + printk(BIOS_DEBUG," Param1 = %x, Param2 = %x.\n",(unsigned int)AmdEventParams.DataParam1, (unsigned int)AmdEventParams.DataParam2); + printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n",(unsigned int)AmdEventParams.DataParam3, (unsigned int)AmdEventParams.DataParam4); + Status = AmdReadEventLog (&AmdEventParams); + } + + return (UINT32)Status; +} diff --git a/src/mainboard/micropassion/kratosx1/agesawrapper.h b/src/mainboard/micropassion/kratosx1/agesawrapper.h new file mode 100755 index 0000000..db893cd --- /dev/null +++ b/src/mainboard/micropassion/kratosx1/agesawrapper.h @@ -0,0 +1,97 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#ifndef _AGESAWRAPPER_H_ +#define _AGESAWRAPPER_H_ + +#include <stdint.h> +#include "Porting.h" +#include "AGESA.h" + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +/* Define AMD Ontario APPU SSID/SVID */ +#define AMD_APU_SVID 0x1022 +#define AMD_APU_SSID 0x1234 +#define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS + +enum { + PICK_DMI, /* DMI Interface */ + PICK_PSTATE, /* Acpi Pstate SSDT Table */ + PICK_SRAT, /* SRAT Table */ + PICK_SLIT, /* SLIT Table */ + PICK_WHEA_MCE, /* WHEA MCE table */ + PICK_WHEA_CMC, /* WHEA CMV table */ + PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ + PICK_IVRS, /* IOMMU ACPI IVRS(I/O Virtualization Reporting Structure) table */ +}; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +typedef struct { + UINT32 CalloutName; + AGESA_STATUS (*CalloutPtr) (UINT32 Func, UINT32 Data, VOID* ConfigPtr); +} BIOS_CALLOUT_STRUCT; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ + +UINT32 agesawrapper_amdinitreset (void); +UINT32 agesawrapper_amdinitearly (void); +UINT32 agesawrapper_amdinitenv (void); +UINT32 agesawrapper_amdinitlate (void); +UINT32 agesawrapper_amdinitpost (void); +UINT32 agesawrapper_amdinitmid (void); +UINT32 agesawrapper_amdreadeventlog (UINT8 HeapStatus); +UINT32 agesawrapper_amdinitmmio (void); +UINT32 agesawrapper_amdinitcpuio (void); +void *agesawrapper_getlateinitptr (int pick); +UINT32 agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, void *ConfigPtr); +UINT32 agesawrapper_amdS3Save(VOID); +UINT32 agesawrapper_amdinitresume(VOID); +UINT32 agesawrapper_amds3laterestore (VOID); + +UINT32 agesawrapper_fchs3earlyrestore (VOID); +UINT32 agesawrapper_fchs3laterestore (VOID); + +UINT32 GetHeapBase(AMD_CONFIG_PARAMS *StdHeader); + +#endif diff --git a/src/mainboard/micropassion/kratosx1/buildOpts.c b/src/mainboard/micropassion/kratosx1/buildOpts.c new file mode 100755 index 0000000..9b16c84 --- /dev/null +++ b/src/mainboard/micropassion/kratosx1/buildOpts.c @@ -0,0 +1,504 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/** + * @file + * + * AMD User options selection for a Brazos platform solution system + * + * This file is placed in the user's platform directory and contains the + * build option selections desired for that platform. + * + * For Information about this file, see @ref platforminstall. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Core + * @e \$Revision: 23714 $ @e \$Date: 2009-12-09 17:28:37 -0600 (Wed, 09 Dec 2009) $ + */ + +#include "AGESA.h" +//#include "CommonReturns.h" +#include "Filecode.h" +#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE + +#define INSTALL_FT3_SOCKET_SUPPORT TRUE +#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE + +#define INSTALL_G34_SOCKET_SUPPORT FALSE +#define INSTALL_C32_SOCKET_SUPPORT FALSE +#define INSTALL_S1G3_SOCKET_SUPPORT FALSE +#define INSTALL_S1G4_SOCKET_SUPPORT FALSE +#define INSTALL_ASB2_SOCKET_SUPPORT FALSE +#define INSTALL_FS1_SOCKET_SUPPORT FALSE +#define INSTALL_FM1_SOCKET_SUPPORT FALSE +#define INSTALL_FP2_SOCKET_SUPPORT FALSE +#define INSTALL_FT1_SOCKET_SUPPORT FALSE +#define INSTALL_AM3_SOCKET_SUPPORT FALSE +#define INSTALL_FM2_SOCKET_SUPPORT FALSE + + +#ifdef BLDOPT_REMOVE_FT3_SOCKET_SUPPORT + #if BLDOPT_REMOVE_FT3_SOCKET_SUPPORT == TRUE + #undef INSTALL_FT3_SOCKET_SUPPORT + #define INSTALL_FT3_SOCKET_SUPPORT FALSE + #endif +#endif + +#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_ECC_SUPPORT TRUE +#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE +#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE +#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE +#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE +#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE +//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE +#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE +//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE +#define BLDOPT_REMOVE_SRAT FALSE //TRUE +#define BLDOPT_REMOVE_SLIT FALSE //TRUE +#define BLDOPT_REMOVE_WHEA FALSE //TRUE +#define BLDOPT_REMOVE_CRAT TRUE +//#define BLDOPT_REMOVE_DMI FALSE //TRUE +//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE + +//This element selects whether P-States should be forced to be independent, +// as reported by the ACPI _PSD object. For single-link processors, +// setting TRUE for OS to support this feature. + +//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE + +#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS +#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER +/* Build configuration values here. + */ +#define BLDCFG_VRM_CURRENT_LIMIT 15000 +#define BLDCFG_VRM_NB_CURRENT_LIMIT 13000 +#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 21000 +#define BLDCFG_VRM_SVI_OCP_LEVEL BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT +#define BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT 17000 +#define BLDCFG_VRM_NB_SVI_OCP_LEVEL BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT +#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0 +#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 0 +#define BLDCFG_VRM_SLEW_RATE 10000 +#define BLDCFG_VRM_NB_SLEW_RATE BLDCFG_VRM_SLEW_RATE +#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE + +#define BLDCFG_PLAT_NUM_IO_APICS 3 +#define BLDCFG_GNB_IOAPIC_ADDRESS 0xFEC20000 +#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST +#define BLDCFG_MEM_INIT_PSTATE 0 +#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 // Specifies the IO addresses trapped by the + // core for C-state entry requests. A value + // of 0 in this field specifies that the core + // does not trap any IO addresses for C-state entry. + // Values greater than 0xFFF8 results in undefined behavior. +#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770 + +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE + +#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY +#define BLDCFG_MEMORY_MODE_UNGANGED TRUE +#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE +#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE +#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE +#define BLDCFG_MEMORY_POWER_DOWN TRUE +#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT +#define BLDCFG_ONLINE_SPARE FALSE +#define BLDCFG_BANK_SWIZZLE TRUE +#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO +#define BLDCFG_MEMORY_CLOCK_SELECT DDR1866_FREQUENCY +#define BLDCFG_DQS_TRAINING_CONTROL TRUE +#define BLDCFG_IGNORE_SPD_CHECKSUM TRUE +#define BLDCFG_USE_BURST_MODE FALSE +#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE +#define BLDCFG_ENABLE_ECC_FEATURE FALSE +#define BLDCFG_ECC_REDIRECTION FALSE +#define BLDCFG_SCRUB_DRAM_RATE 0 +#define BLDCFG_SCRUB_L2_RATE 0 +#define BLDCFG_SCRUB_L3_RATE 0 +#define BLDCFG_SCRUB_IC_RATE 0 +#define BLDCFG_SCRUB_DC_RATE 0 +#define BLDCFG_ECC_SYNC_FLOOD TRUE +#define BLDCFG_ECC_SYMBOL_SIZE 4 +#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000ul +#define BLDCFG_1GB_ALIGN FALSE +#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED +#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO +#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 +#define BLDCFG_IOMMU_SUPPORT FALSE +#define OPTION_GFX_INIT_SVIEW FALSE +#define BLDCFG_PLATFORM_POWER_POLICY_MODE BatteryLife + +//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL OEM_LCD_BACK_LIGHT_CONTROL +#define BLDCFG_CFG_ABM_SUPPORT TRUE + +#define BLDCFG_CFG_GNB_HD_AUDIO FALSE +//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID +//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID +//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID + +#ifdef PCIEX_BASE_ADDRESS +#define BLDCFG_PCI_MMIO_BASE PCIEX_BASE_ADDRESS +#define BLDCFG_PCI_MMIO_SIZE (PCIEX_LENGTH >> 20) +#endif + +#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P' +#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' +#define BLDCFG_PCIE_TRAINING_ALGORITHM PcieTrainingDistributed + +/* Process the options... + * This file include MUST occur AFTER the user option selection settings + */ +#define AGESA_ENTRY_INIT_RESET TRUE +#define AGESA_ENTRY_INIT_RECOVERY FALSE +#define AGESA_ENTRY_INIT_EARLY TRUE +#define AGESA_ENTRY_INIT_POST TRUE +#define AGESA_ENTRY_INIT_ENV TRUE +#define AGESA_ENTRY_INIT_MID TRUE +#define AGESA_ENTRY_INIT_LATE TRUE +#define AGESA_ENTRY_INIT_S3SAVE TRUE +#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE +#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE +#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE +/* + * Customized OEM build configurations for FCH component + */ +// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00 +// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20 +// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00 +// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400 +// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404 +// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408 +// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410 +// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420 +// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000 +// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000 +// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000 +// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0 +// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00 +// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000 +// #define BLDCFG_AZALIA_SSID 0x780D1022 +// #define BLDCFG_SMBUS_SSID 0x780B1022 +// #define BLDCFG_IDE_SSID 0x780C1022 +// #define BLDCFG_SATA_AHCI_SSID 0x78011022 +// #define BLDCFG_SATA_IDE_SSID 0x78001022 +// #define BLDCFG_SATA_RAID5_SSID 0x78031022 +// #define BLDCFG_SATA_RAID_SSID 0x78021022 +// #define BLDCFG_EHCI_SSID 0x78081022 +// #define BLDCFG_OHCI_SSID 0x78071022 +// #define BLDCFG_LPC_SSID 0x780E1022 +// #define BLDCFG_SD_SSID 0x78061022 +// #define BLDCFG_XHCI_SSID 0x78121022 +// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE +// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE +// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4 +// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE +// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE +// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE +// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE +// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE +// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE +// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE +// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE + +CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = +{ + { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E }, + { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E }, + { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 }, + { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 }, + { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 }, + { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 }, + { CPU_LIST_TERMINAL } +}; + +#define BLDCFG_AP_MTRR_SETTINGS_LIST &KabiniApMtrrSettingsList + +//#include "KeralaInstall.h" + +/* Include the files that instantiate the configuration definitions. */ +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "AdvancedApi.h" +#include "heapManager.h" +#include "CreateStruct.h" +#include "cpuFeatures.h" +#include "Table.h" +#include "CommonReturns.h" +#include "cpuEarlyInit.h" +#include "cpuLateInit.h" +#include "GnbInterface.h" + + // This is the delivery package title, "BrazosPI" + // This string MUST be exactly 8 characters long +#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} + + // This is the release version number of the AGESA component + // This string MUST be exactly 12 characters long +#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} + +/* MEMORY_BUS_SPEED */ +//#define DDR400_FREQUENCY 200 ///< DDR 400 +//#define DDR533_FREQUENCY 266 ///< DDR 533 +//#define DDR667_FREQUENCY 333 ///< DDR 667 +//#define DDR800_FREQUENCY 400 ///< DDR 800 +//#define DDR1066_FREQUENCY 533 ///< DDR 1066 +//#define DDR1333_FREQUENCY 667 ///< DDR 1333 +//#define DDR1600_FREQUENCY 800 ///< DDR 1600 +//#define DDR1866_FREQUENCY 933 ///< DDR 1866 +//#define DDR2100_FREQUENCY 1050 ///< DDR 2100 +//#define DDR2133_FREQUENCY 1066 ///< DDR 2133 +//#define DDR2400_FREQUENCY 1200 ///< DDR 2400 +//#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency +// +///* QUANDRANK_TYPE*/ +//#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM +//#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM +// +///* USER_MEMORY_TIMING_MODE */ +//#define TIMING_MODE_AUTO 0 ///< Use best rate possible +//#define TIMING_MODE_LIMITED 1 ///< Set user top limit +//#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed +// +///* POWER_DOWN_MODE */ +//#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode +//#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode + +/* + * Agesa optional capabilities selection. + * Uncomment and mark FALSE those features you wish to include in the build. + * Comment out or mark TRUE those features you want to REMOVE from the build. + */ + +#define DFLT_SMBUS0_BASE_ADDRESS 0xB00 +#define DFLT_SMBUS1_BASE_ADDRESS 0xB20 +#define DFLT_SIO_PME_BASE_ADDRESS 0xE00 +#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800 +#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804 +#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808 +#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810 +#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820 +#define DFLT_SPI_BASE_ADDRESS 0xFEC10000 +#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 +#define DFLT_HPET_BASE_ADDRESS 0xFED00000 +#define DFLT_SMI_CMD_PORT 0xB0 +#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 +#define DFLT_GEC_BASE_ADDRESS 0xFED61000 +#define DFLT_AZALIA_SSID 0x780D1022 +#define DFLT_SMBUS_SSID 0x780B1022 +#define DFLT_IDE_SSID 0x780C1022 +#define DFLT_SATA_AHCI_SSID 0x78011022 +#define DFLT_SATA_IDE_SSID 0x78001022 +#define DFLT_SATA_RAID5_SSID 0x78031022 +#define DFLT_SATA_RAID_SSID 0x78021022 +#define DFLT_EHCI_SSID 0x78081022 +#define DFLT_OHCI_SSID 0x78071022 +#define DFLT_LPC_SSID 0x780E1022 +#define DFLT_SD_SSID 0x78061022 +#define DFLT_XHCI_SSID 0x78121022 +#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE +#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE +#define DFLT_FCH_GPP_LINK_CONFIG PortA4 +#define DFLT_FCH_GPP_PORT0_PRESENT FALSE +#define DFLT_FCH_GPP_PORT1_PRESENT FALSE +#define DFLT_FCH_GPP_PORT2_PRESENT FALSE +#define DFLT_FCH_GPP_PORT3_PRESENT FALSE +#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE +//#define BLDCFG_IR_PIN_CONTROL 0x33 + +GPIO_CONTROL kratosx1_gpio[] = { + {183, Function1, GpioIn | GpioOutEnB | PullUpB}, + {-1} +}; +//#define BLDCFG_FCH_GPIO_CONTROL_LIST (&kratosx1_gpio[0]) + +// The following definitions specify the default values for various parameters in which there are +// no clearly defined defaults to be used in the common file. The values below are based on product +// and BKDG content, please consult the AGESA Memory team for consultation. +#define DFLT_SCRUB_DRAM_RATE (0) +#define DFLT_SCRUB_L2_RATE (0) +#define DFLT_SCRUB_L3_RATE (0) +#define DFLT_SCRUB_IC_RATE (0) +#define DFLT_SCRUB_DC_RATE (0) +#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define DFLT_VRM_SLEW_RATE (5000) + +#include "PlatformInstall.h" + +/*---------------------------------------------------------------------------------------- + * CUSTOMER OVERIDES MEMORY TABLE + *---------------------------------------------------------------------------------------- + */ + +/* + * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA + * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable + * is populated, AGESA will base its settings on the data from the table. Otherwise, it will + * use its default conservative settings. + */ +CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { + // + // The following macros are supported (use comma to separate macros): + // + // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap) + // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. + // AGESA will base on this value to disable unused MemClk to save power. + // Example: + // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: + // Bit AM3/S1g3 pin name + // 0 M[B,A]_CLK_H/L[0] + // 1 M[B,A]_CLK_H/L[1] + // 2 M[B,A]_CLK_H/L[2] + // 3 M[B,A]_CLK_H/L[3] + // 4 M[B,A]_CLK_H/L[4] + // 5 M[B,A]_CLK_H/L[5] + // 6 M[B,A]_CLK_H/L[6] + // 7 M[B,A]_CLK_H/L[7] + // And platform has the following routing: + // CS0 M[B,A]_CLK_H/L[4] + // CS1 M[B,A]_CLK_H/L[2] + // CS2 M[B,A]_CLK_H/L[3] + // CS3 M[B,A]_CLK_H/L[5] + // Then platform can specify the following macro: + // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00) + // + // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap) + // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap. + // AGESA will base on this value to tristate unused CKE to save power. + // + // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap) + // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap. + // AGESA will base on this value to tristate unused ODT pins to save power. + // + // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap) + // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap. + // AGESA will base on this value to tristate unused Chip select to save power. + // + // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) + // Specifies the number of DIMM slots per channel. + // + // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) + // Specifies the number of Chip selects per channel. + // + // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) + // Specifies the number of channels per socket. + // + // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED) + // Specifies DDR bus speed of channel ChannelID on socket SocketID. + // + // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE) + // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...) + // + // WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, + // Byte6Seed, Byte7Seed, ByteEccSeed) + // Specifies the write leveling seed for a channel of a socket. + // + // HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, + // Byte6Seed, Byte7Seed, ByteEccSeed) + // Speicifes the HW RXEN training seed for a channel of a socket + // + #define SEED_A 0x12 + HW_RXEN_SEED( + ANY_SOCKET, CHANNEL_A, ALL_DIMMS, + SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, + SEED_A), + + NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1), + NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), + + MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), + CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00), /* TODO: bit2map, bit3map */ + ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00), + CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), + + PSO_END +}; + +/* + * These tables are optional and may be used to adjust memory timing settings + */ +#include "mm.h" +#include "mn.h" + +// Customer table +UINT8 AGESA_MEM_TABLE_TN[][sizeof (MEM_TABLE_ALIAS)] = +{ + // Hardcoded Memory Training Values + + // The following macro should be used to override training values for your platform + // + // DQSACCESS(MTAfterDqsRwPosTrn, MTNodes, MTDcts, MTDIMMs, BFRdDqsDly, MTOverride, 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c, 0x20), + // + // NOTE: + // The following training hardcode values are example values that were taken from a tilapia motherboard + // with a particular DIMM configuration. To hardcode your own values, uncomment the appropriate line in + // the table and replace the byte lane values with your own. + // + // ------------------ BYTE LANES ---------------------- + // BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC + // Write Data Timing + // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM0, BFWrDatDly, MTOverride, 0x1D, 0x20, 0x26, 0x2B, 0x37, 0x3A, 0x3e, 0x3F, 0x30),// DCT0, DIMM0 + // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM1, BFWrDatDly, MTOverride, 0x1D, 0x00, 0x06, 0x0B, 0x17, 0x1A, 0x1E, 0x1F, 0x10),// DCT0, DIMM1 + // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM0, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x27, 0x2B, 0x3B, 0x3B, 0x3E, 0x3E, 0x30),// DCT1, DIMM0 + // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM1, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x1C, 0x0B, 0x17, 0x1A, 0x1D, 0x1C, 0x10),// DCT1, DIMM1 + + // DQS Receiver Enable + // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0 + // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM1, BFRcvEnDly, MTOverride, 0x7C, 0x7D, 0x7E, 0x81, 0x88, 0x8F, 0x96, 0x9F, 0x84),// DCT0, DIMM1 + // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT1, DIMM0 + // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM1, BFRcvEnDly, MTOverride, 0x1C, 0x1D, 0x1E, 0x01, 0x08, 0x0F, 0x16, 0x1F, 0x04),// DCT1, DIMM1 + + // Write DQS Delays + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFWrDqsDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFWrDqsDly, MTOverride, 0x06, 0x0D, 0x12, 0x1A, 0x25, 0x28, 0x2C, 0x2C, 0x44),// DCT0, DIMM1 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFWrDqsDly, MTOverride, 0x07, 0x0E, 0x14, 0x1B, 0x24, 0x29, 0x2B, 0x2C, 0x1F),// DCT1, DIMM0 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFWrDqsDly, MTOverride, 0x07, 0x0C, 0x14, 0x19, 0x25, 0x28, 0x2B, 0x2B, 0x1A),// DCT1, DIMM1 + + // Read DQS Delays + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x0E, 0x10),// DCT0, DIMM0 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT0, DIMM1 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM0 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM1 + //-------------------------------------------------------------------------------------------------------------------------------------------------- + // TABLE END + NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table +}; +UINT8 SizeOfTableTN = sizeof (AGESA_MEM_TABLE_TN) / sizeof (AGESA_MEM_TABLE_TN[0]); diff --git a/src/mainboard/micropassion/kratosx1/cmos.layout b/src/mainboard/micropassion/kratosx1/cmos.layout new file mode 100755 index 0000000..f6b5806 --- /dev/null +++ b/src/mainboard/micropassion/kratosx1/cmos.layout @@ -0,0 +1,114 @@ +#***************************************************************************** +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +#***************************************************************************** + +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 diff --git a/src/mainboard/micropassion/kratosx1/devicetree.cb b/src/mainboard/micropassion/kratosx1/devicetree.cb new file mode 100755 index 0000000..451d290 --- /dev/null +++ b/src/mainboard/micropassion/kratosx1/devicetree.cb @@ -0,0 +1,64 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2013 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# +chip northbridge/amd/agesa/family16kb/root_complex + device cpu_cluster 0 on + chip cpu/amd/agesa/family16kb + device lapic 0 on end + end + end + + device domain 0 on + subsystemid 0x1022 0x1410 inherit + chip northbridge/amd/agesa/family16kb # CPU side of HT root complex + + chip northbridge/amd/agesa/family16kb # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end # PCIe Host Bridge + device pci 2.1 on end # x4 PCIe slot + device pci 2.2 on end # mPCIe slot + device pci 2.3 on end # Realtek NIC + device pci 2.4 on end # Edge Connector + device pci 2.5 on end # Edge Connector + end #chip northbridge/amd/agesa/family16kb + + chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus + device pci 10.0 on end # XHCI HC0 + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on end # SM + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on end # LPC 0x439d + device pci 14.7 on end # SD + end #chip southbridge/amd/hudson + + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + + end #chip northbridge/amd/agesa/family16kb # CPU side of HT root complex + end #domain +end #northbridge/amd/agesa/family16kb/root_complex diff --git a/src/mainboard/micropassion/kratosx1/dsdt.asl b/src/mainboard/micropassion/kratosx1/dsdt.asl new file mode 100755 index 0000000..78d9bca --- /dev/null +++ b/src/mainboard/micropassion/kratosx1/dsdt.asl @@ -0,0 +1,84 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* DefinitionBlock Statement */ +DefinitionBlock ( + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "AMD ", /* OEMID */ + "COREBOOT", /* TABLE ID */ + 0x00010001 /* OEM Revision */ + ) +{ /* Start of ASL file */ + /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ + + /* Globals for the platform */ + #include "acpi/mainboard.asl" + + /* Describe the USB Overcurrent pins */ + #include "acpi/usb_oc.asl" + + /* PCI IRQ mapping for the Southbridge */ + #include <southbridge/amd/agesa/hudson/acpi/pcie.asl> + + /* Describe the processor tree (\_PR) */ + #include <cpu/amd/agesa/family16kb/acpi/cpu.asl> + + /* Contains the supported sleep states for this chipset */ + #include <southbridge/amd/agesa/hudson/acpi/sleepstates.asl> + + /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */ + #include "acpi/sleep.asl" + + /* System Bus */ + Scope(\_SB) { /* Start \_SB scope */ + /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> + + /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ + #include "acpi/routing.asl" + + Device(PCI0) { + /* Describe the AMD Northbridge */ + #include <northbridge/amd/agesa/family16kb/acpi/northbridge.asl> + + /* Describe the AMD Fusion Controller Hub Southbridge */ + #include <southbridge/amd/agesa/hudson/acpi/fch.asl> + } + + /* Describe PCI INT[A-H] for the Southbridge */ + #include <southbridge/amd/agesa/hudson/acpi/pci_int.asl> + + } /* End \_SB scope */ + + /* Describe SMBUS for the Southbridge */ + #include <southbridge/amd/agesa/hudson/acpi/smbus.asl> + + /* Define the General Purpose Events for the platform */ + #include "acpi/gpe.asl" + + /* Define the Thermal zones and methods for the platform */ + #include "acpi/thermal.asl" + + /* Define the System Indicators for the platform */ + #include "acpi/si.asl" +} +/* End of ASL file */ diff --git a/src/mainboard/micropassion/kratosx1/get_bus_conf.c b/src/mainboard/micropassion/kratosx1/get_bus_conf.c new file mode 100755 index 0000000..5413986 --- /dev/null +++ b/src/mainboard/micropassion/kratosx1/get_bus_conf.c @@ -0,0 +1,184 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Micro Passion Ltd + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include <string.h> +#include <stdint.h> +#include <stdlib.h> +#include <cpu/amd/amdfam14.h> +#include "agesawrapper.h" + +#define ACPI_MMIO_BASE 0xFED80000 + +/* Global variables for MB layouts and these will be shared by irqtable mptable + * and acpi_tables busnum is default. + */ +u8 bus_isa; +u8 bus_yangtze[3]; +u32 apicid_yangtze; + +/* + * Here you only need to set value in pci1234 for HT-IO that could be installed or not + * You may need to preset pci1234 for HTIO board, + * please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail + */ +u32 pci1234x[] = { + 0x0000ff0, +}; + +u32 bus_type[256]; +u32 sbdn_yangtze; + +static u32 get_bus_conf_done = 0; + +#if CONFIG_HAVE_ACPI_RESUME +extern u8 acpi_slp_type; +#endif +void get_bus_conf(void) +{ + u32 apicid_base; + u32 status; + device_t pcidev; + u16 temp; + u32 * Ptr32; + u32 value; + + device_t dev; + int i, j; + + if (get_bus_conf_done == 1) + return; /* do it only once */ + + get_bus_conf_done = 1; + + /* + * This is the call to AmdInitLate. It is really in the wrong place, conceptually, + * but functionally within the coreboot model, this is the best place to make the + * call. The logically correct place to call AmdInitLate is after PCI scan is done, + * after the decision about S3 resume is made, and before the system tables are + * written into RAM. The routine that is responsible for writing the tables is + * "write_tables", called near the end of "hardwaremain". There is no platform + * specific entry point between the S3 resume decision point and the call to + * "write_tables", and the next platform specific entry points are the calls to + * the ACPI table write functions. The first of ose would seem to be the right + * place, but other table write functions, e.g. the PIRQ table write function, are + * called before the ACPI tables are written. This routine is called at the beginning + * of each of the write functions called prior to the ACPI write functions, so this + * becomes the best place for this call. + */ +#if CONFIG_HAVE_ACPI_RESUME + if (acpi_slp_type != 3) { + status = agesawrapper_amdinitlate(); + if(status) { + printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); + } + status = agesawrapper_amdS3Save(); + if (status) { + printk(BIOS_DEBUG, "agesawrapper_amds3save failed: %x \n", status); + } + } +#else + status = agesawrapper_amdinitlate(); + if (status) + printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); +#endif + dev = dev_find_slot(0, PCI_DEVFN(0, 0)); /* clear IoapicSbFeatureEn */ + pci_write_config32(dev, 0xF8, 0); + pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */ + + + /* disable No Snoop */ + dev = dev_find_slot(0, PCI_DEVFN(1, 1)); + value = pci_read_config32(dev, 0x60); + value &= ~(1 << 11); + pci_write_config32(dev, 0x60, value); + + sbdn_yangtze = 0; + + for (i = 0; i < 3; i++) { + bus_yangtze[i] = 0; + } + + for (i = 0; i < 256; i++) { + bus_type[i] = 0; /* default ISA bus. */ + } + + bus_type[0] = 1; /* pci */ + + // bus_yangtze[0] = (sysconf.pci1234[0] >> 16) & 0xff; + bus_yangtze[0] = (pci1234x[0] >> 16) & 0xff; + + /* yangtze */ + dev = dev_find_slot(bus_yangtze[0], PCI_DEVFN(sbdn_yangtze + 0x14, 4)); + + if (dev) { + bus_yangtze[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); + + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; + for (j = bus_yangtze[1]; j < bus_isa; j++) + bus_type[j] = 1; + } + + for (i = 0; i < 4; i++) { + dev = dev_find_slot(bus_yangtze[0], PCI_DEVFN(sbdn_yangtze + 0x14, i)); + if (dev) { + bus_yangtze[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; + } + } + for (j = bus_yangtze[2]; j < bus_isa; j++) + bus_type[j] = 1; + + /* I/O APICs: APIC ID Version State Address */ + bus_isa = 10; + apicid_base = CONFIG_MAX_CPUS; + apicid_yangtze = apicid_base; + + + //Setup Ethernet LED Configuration + pcidev = dev_find_device(0x10EC, 0x8168, 0); + if (pcidev) + { + temp = pci_read_config16(pcidev, 0x10); + temp &= 0xFFFE; + printk(BIOS_DEBUG, "Found Realtek Ethernet controller with IO address: %x\n", temp); + outw (0xFF, (temp + 0x18)); + } + + Ptr32 = (u32 *) (ACPI_MMIO_BASE + 0xE00 + 0x00); //GPPClkCntrl + *Ptr32 &= ~0x0000; + *Ptr32 |= 0x430F; //Setup PCIe clocks based on clk_req lines + + //Setup PSI_L VID threshold + pcidev = dev_find_slot(0, PCI_DEVFN(0x18, 3)); + if (pcidev) + { + temp = pci_read_config16(pcidev, 0xA0); + temp &= 0xFF00; + temp |= 0xE2; + pci_write_config16(pcidev, 0xA0, temp); + } + +} diff --git a/src/mainboard/micropassion/kratosx1/irq_tables.c b/src/mainboard/micropassion/kratosx1/irq_tables.c new file mode 100755 index 0000000..9779153 --- /dev/null +++ b/src/mainboard/micropassion/kratosx1/irq_tables.c @@ -0,0 +1,112 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> +#include <arch/pirq_routing.h> +#include <cpu/amd/amdfam16.h> + +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, + u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, + u8 slot, u8 rfu) +{ + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; +} + +extern u8 bus_isa; +extern u8 bus_yangtze[2]; +extern unsigned long sbdn_yangtze; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + struct irq_routing_table *pirq; + struct irq_info *pirq_info; + u32 slot_num; + u8 *v; + + u8 sum = 0; + int i; + + get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */ + + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15; + + /* This table must be betweeen 0xf0000 & 0x100000 */ + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); + + pirq = (void *)(addr); + v = (u8 *) (addr); + + pirq->signature = PIRQ_SIGNATURE; + pirq->version = PIRQ_VERSION; + + pirq->rtr_bus = bus_yangtze[0]; + pirq->rtr_devfn = ((sbdn_yangtze + 0x14) << 3) | 4; + + pirq->exclusive_irqs = 0; + + pirq->rtr_vendor = 0x1002; + pirq->rtr_device = 0x4384; + + pirq->miniport_data = 0; + + memset(pirq->rfu, 0, sizeof(pirq->rfu)); + + pirq_info = (void *)(&pirq->checksum + 1); + slot_num = 0; + + /* pci bridge */ + write_pirq_info(pirq_info, bus_yangtze[0], ((sbdn_yangtze + 0x14) << 3) | 4, + 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, + 0); + pirq_info++; + + slot_num++; + + pirq->size = 32 + 16 * slot_num; + + for (i = 0; i < pirq->size; i++) + sum += v[i]; + + sum = pirq->checksum - sum; + + if (sum != pirq->checksum) { + pirq->checksum = sum; + } + + printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + + return (unsigned long)pirq_info; +} diff --git a/src/mainboard/micropassion/kratosx1/mainboard.c b/src/mainboard/micropassion/kratosx1/mainboard.c new file mode 100755 index 0000000..50a4872 --- /dev/null +++ b/src/mainboard/micropassion/kratosx1/mainboard.c @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <arch/io.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/mtrr.h> +#include <device/pci_def.h> +#include <arch/acpi.h> +#include "BiosCallOuts.h" +#include <cpu/amd/agesa/s3_resume.h> +#include "agesawrapper.h" + +/********************************************** + * enable the dedicated function in mainboard. + **********************************************/ +static void mainboard_enable(device_t dev) +{ + printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + /* + * The mainboard is the first place that we get control in ramstage. Check + * for S3 resume and call the approriate AGESA/CIMx resume functions. + */ +#if CONFIG_HAVE_ACPI_RESUME + acpi_slp_type = acpi_get_sleep_type(); + if (acpi_slp_type == 3) + agesawrapper_fchs3earlyrestore(); +#endif + + +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/micropassion/kratosx1/mptable.c b/src/mainboard/micropassion/kratosx1/mptable.c new file mode 100755 index 0000000..118f860 --- /dev/null +++ b/src/mainboard/micropassion/kratosx1/mptable.c @@ -0,0 +1,245 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <arch/smp/mpspec.h> +#include <device/pci.h> +#include <arch/io.h> +#include <string.h> +#include <stdint.h> +#include <cpu/amd/amdfam15.h> +#include <arch/cpu.h> +#include <cpu/x86/lapic.h> +#include "southbridge/amd/agesa/hudson/hudson.h" /* pm_ioread() */ + +//-#define IO_APIC_ID CONFIG_MAX_PHYSICAL_CPUS + 1 +#define IO_APIC_ID CONFIG_MAX_CPUS +extern u8 bus_yangtze[3]; + +extern u32 bus_type[256]; +extern u32 sbdn_yangtze; +extern u32 apicid_yangtze; + +u8 picr_data[0x54] = { + 0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + 0x1F,0x1F,0x1F,0x03,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x05,0x04,0x05,0x04,0x04,0x05,0x04,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x04,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x03,0x04,0x05,0x07 +}; +u8 intr_data[0x54] = { + 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x10,0x11,0x12,0x13 +}; + +static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length) +{ + mc->mpc_length += length; + mc->mpc_entry_count++; +} + +static void my_smp_write_bus(struct mp_config_table *mc, + unsigned char id, const char *bustype) +{ + struct mpc_config_bus *mpc; + mpc = smp_next_mpc_entry(mc); + memset(mpc, '\0', sizeof(*mpc)); + mpc->mpc_type = MP_BUS; + mpc->mpc_busid = id; + memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); + smp_add_mpc_entry(mc, sizeof(*mpc)); +} + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + int bus_isa; + u32 dword; + u8 byte; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LOCAL_APIC_ADDR); + memcpy(mc->mpc_oem, "AMD ", 8); + + smp_write_processors(mc); + + get_bus_conf(); + + //mptable_write_buses(mc, NULL, &bus_isa); + my_smp_write_bus(mc, 0, "PCI "); + my_smp_write_bus(mc, 1, "PCI "); + bus_isa = 0x02; + my_smp_write_bus(mc, bus_isa, "ISA "); + + /* I/O APICs: APIC ID Version State Address */ + + dword = 0; + dword = pm_ioread(0x34) & 0xF0; + dword |= (pm_ioread(0x35) & 0xFF) << 8; + dword |= (pm_ioread(0x36) & 0xFF) << 16; + dword |= (pm_ioread(0x37) & 0xFF) << 24; + /* Set IO APIC ID onto IO_APIC_ID */ + write32 (dword, 0x00); + write32 (dword + 0x10, IO_APIC_ID << 24); + apicid_yangtze = IO_APIC_ID; + smp_write_ioapic(mc, apicid_yangtze, 0x21, dword); + + smp_write_ioapic(mc, apicid_yangtze+1, 0x21, 0xFEC20000); + /* PIC IRQ routine */ + for (byte = 0x0; byte < sizeof(picr_data); byte ++) { + outb(byte, 0xC00); + outb(picr_data[byte], 0xC01); + } + + /* APIC IRQ routine */ + for (byte = 0x0; byte < sizeof(intr_data); byte ++) { + outb(byte | 0x80, 0xC00); + outb(intr_data[byte], 0xC01); + } +#if 0 + outb(0x0B, 0xCD6); + outb(0x02, 0xCD7); + + outb(0x50, 0xCD6); + outb(0x1F, 0xCD7); + + outb(0x48, 0xCD6); + outb(0xF2, 0xCD7); + + //outb(0xBE, 0xCD6); + //outb(0x52, 0xCD7); + + outb(0xED, 0xCD6); + outb(0x17, 0xCD7); + + *(volatile u8 *) (0xFED80D00 + 0x31) = 2; + *(volatile u8 *) (0xFED80D00 + 0x32) = 2; + *(volatile u8 *) (0xFED80D00 + 0x33) = 2; + *(volatile u8 *) (0xFED80D00 + 0x34) = 2; + + *(volatile u8 *) (0xFED80100 + 0x31) = 0xc8; + *(volatile u8 *) (0xFED80100 + 0x32) = 0xc8; + *(volatile u8 *) (0xFED80100 + 0x33) = 0xc8; + *(volatile u8 *) (0xFED80100 + 0x34) = 0xa0; + + *(volatile u8 *) (0xFED80D00 + 0x6c) = 1; + *(volatile u8 *) (0xFED80D00 + 0x6E) = 2; + *(volatile u8 *) (0xFED80D00 + 0x6f) = 2; + + *(volatile u8 *) (0xFED80100 + 0x6c) = 0xa0; + *(volatile u8 *) (0xFED80100 + 0x6E) = 0xa8; + *(volatile u8 *) (0xFED80100 + 0x6f) = 0xa0; + + *(volatile u8 *) (0xFED80D00 + 0xA6) = 2; + *(volatile u8 *) (0xFED80100 + 0xA6) = 0; + + *(volatile u8 *) (0xFED80100 + 0x40) = 0xC8; +#endif + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ +#define IO_LOCAL_INT(type, intr, apicid, pin) \ + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + mptable_add_isa_interrupts(mc, bus_isa, apicid_yangtze, 0); + + /* PCI interrupts are level triggered, and are + * associated with a specific bus/device/function tuple. + */ +#define PCI_INT(bus, dev, int_sign, pin) \ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_yangtze, (pin)) + + /* Internal VGA */ + PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); + PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); + + /* SMBUS */ + PCI_INT(0x0, 0x14, 0x0, 0x10); + + /* HD Audio */ + PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]); + + /* USB */ + PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); + PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); + PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); + PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); + PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); + PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); + PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]); + + /* sata */ + PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]); + PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); + + /* on board NIC & Slot PCIE. */ + + /* PCI slots */ + /* PCI_SLOT 0. */ + PCI_INT(bus_yangtze[1], 0x5, 0x0, 0x14); + PCI_INT(bus_yangtze[1], 0x5, 0x1, 0x15); + PCI_INT(bus_yangtze[1], 0x5, 0x2, 0x16); + PCI_INT(bus_yangtze[1], 0x5, 0x3, 0x17); + + /* PCI_SLOT 1. */ + PCI_INT(bus_yangtze[1], 0x6, 0x0, 0x15); + PCI_INT(bus_yangtze[1], 0x6, 0x1, 0x16); + PCI_INT(bus_yangtze[1], 0x6, 0x2, 0x17); + PCI_INT(bus_yangtze[1], 0x6, 0x3, 0x14); + + /* PCI_SLOT 2. */ + PCI_INT(bus_yangtze[1], 0x7, 0x0, 0x16); + PCI_INT(bus_yangtze[1], 0x7, 0x1, 0x17); + PCI_INT(bus_yangtze[1], 0x7, 0x2, 0x14); + PCI_INT(bus_yangtze[1], 0x7, 0x3, 0x15); + + PCI_INT(bus_yangtze[2], 0x0, 0x0, 0x12); + PCI_INT(bus_yangtze[2], 0x0, 0x1, 0x13); + PCI_INT(bus_yangtze[2], 0x0, 0x2, 0x14); + + /* PCIe Lan*/ + PCI_INT(0x0, 0x06, 0x0, 0x13); + + /* FCH PCIe PortA */ + PCI_INT(0x0, 0x15, 0x0, 0x10); + /* FCH PCIe PortB */ + PCI_INT(0x0, 0x15, 0x1, 0x11); + /* FCH PCIe PortC */ + PCI_INT(0x0, 0x15, 0x2, 0x12); + /* FCH PCIe PortD */ + PCI_INT(0x0, 0x15, 0x3, 0x13); + + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); + IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); + /* There is no extension information... */ + + /* Compute the checksums */ + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/micropassion/kratosx1/romstage.c b/src/mainboard/micropassion/kratosx1/romstage.c new file mode 100755 index 0000000..51b6e86 --- /dev/null +++ b/src/mainboard/micropassion/kratosx1/romstage.c @@ -0,0 +1,199 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Micro Passion Ltd + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <string.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include <arch/stages.h> +#include <device/pnp_def.h> +#include <arch/cpu.h> +#include <cpu/x86/lapic.h> +#include <console/console.h> +#include "superio/smsc/sio1007/early_serial.c" +#include <console/loglevel.h> +#include "agesawrapper.h" +#include "cpu/x86/bist.h" +#include "cpu/x86/lapic.h" +#include "southbridge/amd/agesa/hudson/hudson.h" +#include "cpu/amd/agesa/s3_resume.h" +#include "src/drivers/pc80/i8254.c" +#include "src/drivers/pc80/i8259.c" +#include "cbmem.h" + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); +void disable_cache_as_ram(void); + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + u32 val; + device_t dev; + u32 dword; +#if CONFIG_HAVE_ACPI_RESUME + void *resume_backup_memory; +#endif + + /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for + * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA + * even though the register is not documented in the Kabini BKDG. + * Otherwise the serial output is bad code. + */ + outb(0xD2, 0xcd6); + outb(0x00, 0xcd7); + + val = agesawrapper_amdinitmmio(); + + hudson_lpc_port80(); + + if (!cpu_init_detectedx && boot_cpu()) { + __writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5); + __writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800); + + dev = PCI_DEV(0, 0x14, 0x03); + /* LPC Bridge 0:20:3:48h. + * BIT0: Port Enable for SuperIO 0x2E-0x2F + * BIT1: Port Enable for SuperIO 0x4E-0x4F + * BIT4: Port Enable for LPC ROM Address Arrage2 (0x68-0x6C) + * BIT6: Port Enable for RTC IO 0x70-0x73 + * BIT21: Port Enable for Port 0x80 + */ + dword = pci_io_read_config32(dev, 0x48); + dword |= (1<<0);// | (1<<1) | (1<<4) | (1<<6) | (1<<21) ; + pci_io_write_config32(dev, 0x48, dword); + + dword = pci_io_read_config32(dev, 0x44); + dword |= 0xFFFFFFFF; + pci_io_write_config32(dev, 0x44, dword); + sio1007_enable_uart_at(0x2e); + post_code(0x30); + + post_code(0x31); + console_init(); + } + + /* Halt if there was a built in self test failure */ + post_code(0x34); + report_bist_failure(bist); + + /* Load MPB */ + val = cpuid_eax(1); + printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + + /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */ + int i; + for(i = 0; i < 200000; i++) + val = inb(0xcd6); + + post_code(0x37); + val = agesawrapper_amdinitreset(); + if(val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val); + } + + post_code(0x38); + printk(BIOS_DEBUG, "Got past yangtze_early_setup\n"); + + post_code(0x39); + + val = agesawrapper_amdinitearly (); + if(val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val); + } + printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n"); + +#if CONFIG_HAVE_ACPI_RESUME + if (!acpi_is_wakeup_early()) { /* Check for S3 resume */ +#endif + post_code(0x40); + val = agesawrapper_amdinitpost (); + if(val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val); + } + printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n"); + + post_code(0x41); + val = agesawrapper_amdinitenv (); + if(val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val); + } + printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n"); + /* TODO: Disable cache is not ok. */ + disable_cache_as_ram(); +#if CONFIG_HAVE_ACPI_RESUME + } else { /* S3 detect */ + printk(BIOS_INFO, "S3 detected\n"); + + post_code(0x60); + printk(BIOS_DEBUG, "agesawrapper_amdinitresume "); + val = agesawrapper_amdinitresume(); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); + + printk(BIOS_DEBUG, "agesawrapper_amds3laterestore "); + val = agesawrapper_amds3laterestore (); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); + + post_code(0x61); + printk(BIOS_DEBUG, "Find resume memory location\n"); + resume_backup_memory = (void *)backup_resume(); + + post_code(0x62); + printk(BIOS_DEBUG, "Move CAR stack.\n"); + move_stack_high_mem(); + printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE)); + + post_code(0x63); + disable_cache_as_ram(); + printk(BIOS_DEBUG, "CAR disabled.\n"); + set_resume_cache(); + + /* + * Copy the system memory that is in the ramstage area to the + * reserved area. + */ + if (resume_backup_memory) + memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE); + + printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n"); + } +#endif + + outb(0xEA, 0xCD6); + outb(0x1, 0xcd7); + /* Initialize i8259 pic */ + post_code(0x41); + setup_i8259 (); + + /* Initialize i8254 timers */ + post_code(0x42); + setup_i8254 (); + + post_code(0x50); + copy_and_run(); + + post_code(0x54); /* Should never see this post code. */ +}

1 0

Patch merged into coreboot/master: 681d17e exynos5420: Fix build warning
by gerrit＠coreboot.org 28 Sep '13

28 Sep '13

the following patch was just integrated into master: commit 681d17e0bf00a889f3c931d69b9af205c4ab674d Author: Allen Martin <amartin(a)nvidia.com> Date: Thu Sep 26 11:13:01 2013 -0700 exynos5420: Fix build warning Fix "set but not used" variable warning with gcc 4.7.3 Change-Id: Ia27291ecb4f993c4ba6f29b134167dc23a449bf5 Signed-off-by: Allen Martin <amartin(a)nvidia.com> Reviewed-on: http://review.coreboot.org/3949 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Gabe Black <gabeblack(a)chromium.org> See http://review.coreboot.org/3949 for details. -gerrit

1 0

New patch to review for coreboot: 4b0d7b7 Delay cbfs-file tmpfile generation
by Patrick Georgi 28 Sep '13

28 Sep '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3950 -gerrit commit 4b0d7b713fb601e2e95cee7ba04f79da2e1b9fa1 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat Sep 28 20:55:52 2013 +0200 Delay cbfs-file tmpfile generation For some file processing in the build process we use temporary files. Generate them lazily, so "make printall" doesn't lead to their creation. Change-Id: I27c2c96bab1420cde774e15d2d6fdcb689ec50b3 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile.inc b/Makefile.inc index 69ad3a1..6a39427 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -173,7 +173,7 @@ cbfs-files-handler= \ )) \ $(if $(tmp-cbfs-method), \ $(eval tmp-old-cbfs-file:=$(tmp-cbfs-file)) \ - $(eval tmp-cbfs-file:=$(shell mkdir -p $(obj)/mainboard/$(MAINBOARDDIR); mktemp $(obj)/mainboard/$(MAINBOARDDIR)/cbfs-file.XXXXXX).out) \ + $(eval tmp-cbfs-file:=$$(shell mkdir -p $(obj)/mainboard/$(MAINBOARDDIR); mktemp $(obj)/mainboard/$(MAINBOARDDIR)/cbfs-file.XXXXXX).out) \ $(call cbfs-files-processor-$(tmp-cbfs-method),$(tmp-old-cbfs-file),$(tmp-cbfs-file))) \ $(eval cbfs-files += $(tmp-cbfs-file)|$(2)|$($(2)-type)|$($(2)-compression)|$($(2)-position)) \ $(eval $(2)-name:=) \

1 0

Patch merged into coreboot/master: 616e6fb ASRock IMB_A180: fix Windows 7 HDMI audio issue
by gerrit＠coreboot.org 27 Sep '13

27 Sep '13

the following patch was just integrated into master: commit 616e6fb2521e639eebb95c572f38db1a8bc26894 Author: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Date: Mon Sep 23 15:11:11 2013 +0800 ASRock IMB_A180: fix Windows 7 HDMI audio issue Windows 7 cannot find HDMI audio device because of acpi setting. I have tested on Windows 7. I can play music. Change-Id: I53177ce00b676824a903a3397d69338e8c1a38af Signed-off-by: WANG Siyuan <SiYuan.Wang(a)amd.com> Signed-off-by: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Reviewed-on: http://review.coreboot.org/3936 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/3936 for details. -gerrit

1 0

Patch merged into coreboot/master: 1bfe374 lint: Use temporary build directory
by gerrit＠coreboot.org 27 Sep '13

27 Sep '13

the following patch was just integrated into master: commit 1bfe37470e8300152b0f6f335a59f88096577bcf Author: Nico Huber <nico.huber(a)secunet.com> Date: Tue Jul 2 16:39:28 2013 +0200 lint: Use temporary build directory `util/lint/lint-stable-002-build-dir-handling` always overwrites your current `config.h` and `auto.conf` when the pre-commit hook is run. It can be very confusing when your configuration is suddenly broken. So fix it by not using the default build directory. Change-Id: If2bbc97ac2f12a8203a3769d813386a023f93dd6 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-on: http://review.coreboot.org/3593 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/3593 for details. -gerrit

1 0

Patch set updated for coreboot: ed87352 lint: Use temporary build directory
by Nico Huber 27 Sep '13

27 Sep '13

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3593 -gerrit commit ed8735201907a2dc7439a8d2698651c61412cefa Author: Nico Huber <nico.huber(a)secunet.com> Date: Tue Jul 2 16:39:28 2013 +0200 lint: Use temporary build directory `util/lint/lint-stable-002-build-dir-handling` always overwrites your current `config.h` and `auto.conf` when the pre-commit hook is run. It can be very confusing when your configuration is suddenly broken. So fix it by not using the default build directory. Change-Id: If2bbc97ac2f12a8203a3769d813386a023f93dd6 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- util/lint/lint-stable-002-build-dir-handling | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/util/lint/lint-stable-002-build-dir-handling b/util/lint/lint-stable-002-build-dir-handling index 2dad8a6..03f0b62 100755 --- a/util/lint/lint-stable-002-build-dir-handling +++ b/util/lint/lint-stable-002-build-dir-handling @@ -53,9 +53,12 @@ if [ "$MAKE" = "" ]; then fi # prepare a config to use +TMPOBJ=`mktemp .tmpobj.XXXXXX` +rm $TMPOBJ +mkdir -p ${TMPOBJ} TMPCONFIG=`mktemp .tmpconfig.XXXXXX` rm -f $TMPCONFIG -$MAKE DOTCONFIG=$TMPCONFIG allyesconfig >/dev/null +$MAKE obj=$TMPOBJ DOTCONFIG=$TMPCONFIG allyesconfig >/dev/null # look up parent directory CURRENTDIR=`pwd -P` @@ -66,5 +69,5 @@ compare_output "`run_printall ../obj`" "$PARENTDIR/obj/.../static.c $PARENTDIR/o compare_output "`run_printall /tmp`" "/tmp/.../static.c /tmp/.../static.c /tmp/.../static.romstage.o" compare_output "`run_printall /../tmp`" "/tmp/.../static.c /tmp/.../static.c /tmp/.../static.romstage.o" -rm -f $TMPCONFIG +rm -rf $TMPCONFIG $TMPOBJ

1 0

Patch set updated for coreboot: 8682b13 vendorcode/amd/agesa/f16kb: Update Kabini PI from v0.0.1.0 to v1.0.0.7
by Paul Menzel 27 Sep '13

27 Sep '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3935 -gerrit commit 8682b13c5f407d36d72eb25e802fdc89aaaf0025 Author: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Date: Wed Jul 31 16:55:26 2013 +0800 vendorcode/amd/agesa/f16kb: Update Kabini PI from v0.0.1.0 to v1.0.0.7 The platform initialization code v1.0.0.7 for Kabini has some enhancements like ECC DIMM support, new CPU microcode rev 0700010B, FCH bug fix (RTC) and so on. In some places, the name Kerala was still used and it is now replaced by or renamed to Kabini. Change-Id: I186de1aef222cd35ea69efa93967a3ffb8da7248 Signed-off-by: WANG Siyuan <SiYuan.Wang(a)amd.com> Signed-off-by: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> --- src/cpu/amd/agesa/family16kb/Makefile.inc | 3 +- src/vendorcode/amd/agesa/f16kb/AGESA.h | 1 + .../amd/agesa/f16kb/Include/KabiniFt3Install.h | 144 + .../amd/agesa/f16kb/Include/KeralaInstall.h | 143 - .../agesa/f16kb/Include/OptionFamily16hInstall.h | 24 +- .../amd/agesa/f16kb/Include/OptionFchInstall.h | 10 + .../amd/agesa/f16kb/Include/OptionMemoryInstall.h | 48 +- .../amd/agesa/f16kb/Include/PlatformInstall.h | 6 +- .../f16kb/Legacy/PlatformMemoryConfiguration.inc | 2 +- src/vendorcode/amd/agesa/f16kb/Legacy/agesa.inc | 1 + .../Proc/CPU/Family/0x16/KB/F16KbCoreAfterReset.c | 37 +- .../agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbDmi.c | 2 +- .../CPU/Family/0x16/KB/F16KbId7001MicrocodePatch.c | 3540 +++++++++++++++ .../Proc/CPU/Family/0x16/KB/F16KbInitEarlyTable.c | 32 + .../0x16/KB/F16KbMicrocodePatch0700002A_Enc.c | 3539 --------------- .../0x16/KB/F16KbMicrocodePatch07000106_Enc.c | 3539 --------------- .../f16kb/Proc/CPU/Family/0x16/KB/F16KbPciTables.c | 19 +- src/vendorcode/amd/agesa/f16kb/Proc/CPU/cahalt.asm | 367 -- .../amd/agesa/f16kb/Proc/CPU/cahalt64.asm | 173 - .../amd/agesa/f16kb/Proc/Fch/Common/FchCommonCfg.h | 13 +- .../amd/agesa/f16kb/Proc/Fch/Common/FchDef.h | 3 +- src/vendorcode/amd/agesa/f16kb/Proc/Fch/Fch.h | 7 +- .../Family/Yangtze/YangtzeHwAcpiEnvService.c | 13 +- .../Fch/HwAcpi/Family/Yangtze/YangtzeSSService.c | 1 + .../amd/agesa/f16kb/Proc/Fch/HwAcpi/HwAcpiReset.c | 35 +- .../amd/agesa/f16kb/Proc/Fch/Imc/ImcLib.c | 37 + .../Sata/Family/Yangtze/YangtzeSataEnvService.c | 6 +- .../Fch/Sata/Family/Yangtze/YangtzeSataService.c | 23 +- .../Fch/Sd/Family/Yangtze/YangtzeSdEnvService.c | 12 +- .../Spi/Family/Yangtze/YangtzeLpcResetService.c | 36 +- .../Fch/Usb/Family/Yangtze/YangtzeEhciMidService.c | 17 +- .../Fch/Usb/Family/Yangtze/YangtzeXhciEnvService.c | 42 +- .../agesa/f16kb/Proc/GNB/Common/GnbRegistersKB.h | 24 +- .../f16kb/Proc/GNB/Modules/GnbInitKB/AlibSsdtKB.h | 4612 ++++++++------------ .../Modules/GnbInitKB/GfxIntegratedInfoTableKB.c | 5 +- .../Proc/GNB/Modules/GnbInitKB/GfxMidInitKB.c | 2 +- .../f16kb/Proc/GNB/Modules/GnbInitKB/GfxTablesKB.c | 5 +- .../Proc/GNB/Modules/GnbInitKB/GnbSmuFirmwareKB.h | 4388 +++++++++---------- .../f16kb/Proc/GNB/Modules/GnbInitKB/GnbTablesKB.c | 2 +- .../Proc/GNB/Modules/GnbInitKB/PcieEarlyInitKB.c | 6 +- .../Proc/GNB/Modules/GnbInitKB/PcieMidInitKB.c | 86 +- .../amd/agesa/f16kb/Proc/Mem/Feat/DMI/mfDMI.c | 4 +- .../amd/agesa/f16kb/Proc/Mem/Main/mmMemRestore.c | 9 + .../amd/agesa/f16kb/Proc/Mem/NB/KB/mnkb.c | 1 + .../amd/agesa/f16kb/Proc/Mem/NB/KB/mnphykb.c | 8 +- .../amd/agesa/f16kb/Proc/Mem/NB/KB/mns3kb.c | 106 +- src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mndct.c | 1 + src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mnphy.c | 40 +- .../amd/agesa/f16kb/Proc/Mem/Ps/KB/FT3/mpSkbft3.c | 77 +- .../amd/agesa/f16kb/Proc/Mem/Ps/KB/mpSkb3.c | 30 +- .../amd/agesa/f16kb/Proc/Mem/Ps/KB/mpUkb3.c | 106 +- src/vendorcode/amd/agesa/f16kb/Proc/Mem/mn.h | 19 +- src/vendorcode/amd/agesa/f16kb/cpcarmac.inc | 476 -- 53 files changed, 8440 insertions(+), 13442 deletions(-) diff --git a/src/cpu/amd/agesa/family16kb/Makefile.inc b/src/cpu/amd/agesa/family16kb/Makefile.inc index f21459a..f5f204e 100644 --- a/src/cpu/amd/agesa/family16kb/Makefile.inc +++ b/src/cpu/amd/agesa/family16kb/Makefile.inc @@ -76,8 +76,7 @@ agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x16/KB/F16KbHtc.c agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x16/KB/F16KbInitEarlyTable.c agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x16/KB/F16KbIoCstate.c agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x16/KB/F16KbLogicalIdTables.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x16/KB/F16KbMicrocodePatch0700002A_Enc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x16/KB/F16KbMicrocodePatch07000106_Enc.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x16/KB/F16KbId7001MicrocodePatch.c agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x16/KB/F16KbMicrocodePatchTables.c agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x16/KB/F16KbMsrTables.c agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x16/KB/F16KbNbAfterReset.c diff --git a/src/vendorcode/amd/agesa/f16kb/AGESA.h b/src/vendorcode/amd/agesa/f16kb/AGESA.h index d71250c..3e58d23 100644 --- a/src/vendorcode/amd/agesa/f16kb/AGESA.h +++ b/src/vendorcode/amd/agesa/f16kb/AGESA.h @@ -2882,6 +2882,7 @@ typedef struct { IN SCI_MAP_CONTROL *CfgFchSciMapControl; ///< FCH SCI Mapping Control IN SATA_PHY_CONTROL *CfgFchSataPhyControl; ///< FCH SATA PHY Control IN GPIO_CONTROL *CfgFchGpioControl; ///< FCH GPIO Control + IN BOOLEAN CfgFchRtcWorkAround; ///< FCH RTC Workaround } FCH_PLATFORM_POLICY; diff --git a/src/vendorcode/amd/agesa/f16kb/Include/KabiniFt3Install.h b/src/vendorcode/amd/agesa/f16kb/Include/KabiniFt3Install.h new file mode 100644 index 0000000..36153e1 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Include/KabiniFt3Install.h @@ -0,0 +1,144 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Install of build options for a Kerala platform solution + * + * This file generates the defaults tables for the "Kerala" platform solution + * set of processors. The documented build options are imported from a user + * controlled file for processing. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Core + * @e \$Revision: 69377 $ @e \$Date: 2012-05-08 03:52:23 -0500 (Tue, 08 May 2012) $ + */ +/***************************************************************************** + * + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "AdvancedApi.h" +#include "heapManager.h" +#include "CreateStruct.h" +#include "cpuFeatures.h" +#include "Table.h" +#include "CommonReturns.h" +#include "cpuEarlyInit.h" +#include "cpuLateInit.h" +#include "GnbInterface.h" + +/***************************************************************************** + * Define the RELEASE VERSION string + * + * The Release Version string should identify the next planned release. + * When a branch is made in preparation for a release, the release manager + * should change/confirm that the branch version of this file contains the + * string matching the desired version for the release. The trunk version of + * the file should always contain a trailing 'X'. This will make sure that a + * development build from trunk will not be confused for a released version. + * The release manager will need to remove the trailing 'X' and update the + * version string as appropriate for the release. The trunk copy of this file + * should also be updated/incremented for the next expected version, + trailing 'X' + ****************************************************************************/ + // This is the delivery package title, "KabiniPI " + // This string MUST be exactly 16 characters long +#define AGESA_PACKAGE_STRING {'K', 'a', 'b', 'i', 'n', 'i', 'P', 'I', ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' '} + + // This is the release version number of the AGESA component + // This string MUST be exactly 12 characters long +#define AGESA_VERSION_STRING {'V', '1', '.', '0', '.', '0', '.', '7', ' ', ' ', ' ', ' '} + + +// The Kabini FT3 solution is defined to be family 0x16 models 0x00 - 0x0F in the FT3 sockets. +#define INSTALL_FT3_SOCKET_SUPPORT TRUE +#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE + +#ifdef BLDOPT_REMOVE_FT3_SOCKET_SUPPORT + #if BLDOPT_REMOVE_FT3_SOCKET_SUPPORT == TRUE + #undef INSTALL_FT3_SOCKET_SUPPORT + #define INSTALL_FT3_SOCKET_SUPPORT FALSE + #endif +#endif + + +// The following definitions specify the default values for various parameters in which there are +// no clearly defined defaults to be used in the common file. The values below are based on product +// and BKDG content, please consult the AGESA Memory team for consultation. +#define DFLT_SCRUB_DRAM_RATE (0) +#define DFLT_SCRUB_L2_RATE (0) +#define DFLT_SCRUB_L3_RATE (0) +#define DFLT_SCRUB_IC_RATE (0) +#define DFLT_SCRUB_DC_RATE (0) +#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define DFLT_VRM_SLEW_RATE (5000) + + +#define DFLT_SMBUS0_BASE_ADDRESS 0xB00 +#define DFLT_SMBUS1_BASE_ADDRESS 0xB20 +#define DFLT_SIO_PME_BASE_ADDRESS 0xE00 +#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400 +#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404 +#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x408 +#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410 +#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x420 +#define DFLT_SPI_BASE_ADDRESS 0xFEC10000ul +#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0ul +#define DFLT_HPET_BASE_ADDRESS 0xFED00000ul +#define DFLT_SMI_CMD_PORT 0xB0 +#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 +#define DFLT_GEC_BASE_ADDRESS 0xFED61000ul +#define DFLT_AZALIA_SSID 0x780D1022ul +#define DFLT_SMBUS_SSID 0x780B1022ul +#define DFLT_IDE_SSID 0x780C1022ul +#define DFLT_SATA_AHCI_SSID 0x78011022ul +#define DFLT_SATA_IDE_SSID 0x78001022ul +#define DFLT_SATA_RAID5_SSID 0x78031022ul +#define DFLT_SATA_RAID_SSID 0x78021022ul +#define DFLT_EHCI_SSID 0x78081022ul +#define DFLT_OHCI_SSID 0x78071022ul +#define DFLT_LPC_SSID 0x780E1022ul +#define DFLT_SD_SSID 0x78061022ul +#define DFLT_XHCI_SSID 0x78121022ul +#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE +#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE +#define DFLT_FCH_GPP_LINK_CONFIG PortA4 +#define DFLT_FCH_GPP_PORT0_PRESENT FALSE +#define DFLT_FCH_GPP_PORT1_PRESENT FALSE +#define DFLT_FCH_GPP_PORT2_PRESENT FALSE +#define DFLT_FCH_GPP_PORT3_PRESENT FALSE +#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE +#define OPTION_MICROSERVER TRUE +// Instantiate all solution relevant data. +#include "PlatformInstall.h" + diff --git a/src/vendorcode/amd/agesa/f16kb/Include/KeralaInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/KeralaInstall.h deleted file mode 100644 index 6b16a6c..0000000 --- a/src/vendorcode/amd/agesa/f16kb/Include/KeralaInstall.h +++ /dev/null @@ -1,143 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build options for a Kerala platform solution - * - * This file generates the defaults tables for the "Kerala" platform solution - * set of processors. The documented build options are imported from a user - * controlled file for processing. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 69377 $ @e \$Date: 2012-05-08 03:52:23 -0500 (Tue, 08 May 2012) $ - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#include "cpuRegisters.h" -#include "cpuFamRegisters.h" -#include "cpuFamilyTranslation.h" -#include "AdvancedApi.h" -#include "heapManager.h" -#include "CreateStruct.h" -#include "cpuFeatures.h" -#include "Table.h" -#include "CommonReturns.h" -#include "cpuEarlyInit.h" -#include "cpuLateInit.h" -#include "GnbInterface.h" - -/***************************************************************************** - * Define the RELEASE VERSION string - * - * The Release Version string should identify the next planned release. - * When a branch is made in preparation for a release, the release manager - * should change/confirm that the branch version of this file contains the - * string matching the desired version for the release. The trunk version of - * the file should always contain a trailing 'X'. This will make sure that a - * development build from trunk will not be confused for a released version. - * The release manager will need to remove the trailing 'X' and update the - * version string as appropriate for the release. The trunk copy of this file - * should also be updated/incremented for the next expected version, + trailing 'X' - ****************************************************************************/ - // This is the delivery package title, "KabiniPI " - // This string MUST be exactly 8 characters long -#define AGESA_PACKAGE_STRING {'K', 'a', 'b', 'i', 'n', 'i', 'P', 'I'} - - // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long -#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '1', '.', '0', ' ', ' ', ' ', ' '} - - -// The Kerala solution is defined to be family 0x16 models 0x00 - 0x0F in the FT3 sockets. -#define INSTALL_FT3_SOCKET_SUPPORT TRUE -#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE - -#ifdef BLDOPT_REMOVE_FT3_SOCKET_SUPPORT - #if BLDOPT_REMOVE_FT3_SOCKET_SUPPORT == TRUE - #undef INSTALL_FT3_SOCKET_SUPPORT - #define INSTALL_FT3_SOCKET_SUPPORT FALSE - #endif -#endif - - -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. -#define DFLT_SCRUB_DRAM_RATE (0) -#define DFLT_SCRUB_L2_RATE (0) -#define DFLT_SCRUB_L3_RATE (0) -#define DFLT_SCRUB_IC_RATE (0) -#define DFLT_SCRUB_DC_RATE (0) -#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define DFLT_VRM_SLEW_RATE (5000) - - -#define DFLT_SMBUS0_BASE_ADDRESS 0xB00 -#define DFLT_SMBUS1_BASE_ADDRESS 0xB20 -#define DFLT_SIO_PME_BASE_ADDRESS 0xE00 -#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400 -#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404 -#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x408 -#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410 -#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x420 -#define DFLT_SPI_BASE_ADDRESS 0xFEC10000ul -#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0ul -#define DFLT_HPET_BASE_ADDRESS 0xFED00000ul -#define DFLT_SMI_CMD_PORT 0xB0 -#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 -#define DFLT_GEC_BASE_ADDRESS 0xFED61000ul -#define DFLT_AZALIA_SSID 0x780D1022ul -#define DFLT_SMBUS_SSID 0x780B1022ul -#define DFLT_IDE_SSID 0x780C1022ul -#define DFLT_SATA_AHCI_SSID 0x78011022ul -#define DFLT_SATA_IDE_SSID 0x78001022ul -#define DFLT_SATA_RAID5_SSID 0x78031022ul -#define DFLT_SATA_RAID_SSID 0x78021022ul -#define DFLT_EHCI_SSID 0x78081022ul -#define DFLT_OHCI_SSID 0x78071022ul -#define DFLT_LPC_SSID 0x780E1022ul -#define DFLT_SD_SSID 0x78061022ul -#define DFLT_XHCI_SSID 0x78121022ul -#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE -#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE -#define DFLT_FCH_GPP_LINK_CONFIG PortA4 -#define DFLT_FCH_GPP_PORT0_PRESENT FALSE -#define DFLT_FCH_GPP_PORT1_PRESENT FALSE -#define DFLT_FCH_GPP_PORT2_PRESENT FALSE -#define DFLT_FCH_GPP_PORT3_PRESENT FALSE -#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE -// Instantiate all solution relevant data. -#include "PlatformInstall.h" - diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionFamily16hInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionFamily16hInstall.h index 92dae54..ae9e3ad 100644 --- a/src/vendorcode/amd/agesa/f16kb/Include/OptionFamily16hInstall.h +++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionFamily16hInstall.h @@ -127,6 +127,7 @@ extern F_PERFORM_EARLY_INIT_ON_CORE F16SetBrandIdRegistersAtEarly; extern F_PERFORM_EARLY_INIT_ON_CORE LocalApicInitializationAtEarly; extern F_PERFORM_EARLY_INIT_ON_CORE LoadMicrocodePatchAtEarly; + extern F_PERFORM_EARLY_INIT_ON_CORE F16KbLoadMicrocodePatchAtEarly; CONST S_PERFORM_EARLY_INIT_ON_CORE ROMDATA F16KbEarlyInitBeforeApLaunchOnCoreTable[] = { @@ -143,7 +144,7 @@ {SetRegistersFromTablesAfterApLaunch, PERFORM_EARLY_ANY_CONDITION}, {F16SetBrandIdRegistersAtEarly, PERFORM_EARLY_ANY_CONDITION}, #if OPTION_EARLY_SAMPLES == FALSE - {LoadMicrocodePatchAtEarly, PERFORM_EARLY_ANY_CONDITION}, + {F16KbLoadMicrocodePatchAtEarly, PERFORM_EARLY_ANY_CONDITION}, #endif {NULL, 0} }; @@ -208,25 +209,24 @@ #endif #if (AGESA_ENTRY_INIT_RECOVERY == TRUE) || (AGESA_ENTRY_INIT_EARLY == TRUE) - #define F16_KB_UCODE_002A - #define F16_KB_UCODE_0106 + #define F16_KB_UCODE_7000 + #define F16_KB_UCODE_7001 #if AGESA_ENTRY_INIT_EARLY == TRUE #if OPTION_EARLY_SAMPLES == TRUE + extern CONST UINT8 ROMDATA CpuF16KbId7000MicrocodePatch[]; + #undef F16_KB_UCODE_7000 + #define F16_KB_UCODE_7000 CpuF16KbId7000MicrocodePatch, #endif - extern CONST UINT8 ROMDATA arr1[]; - #undef F16_KB_UCODE_002A - #define F16_KB_UCODE_002A arr1, - - extern CONST UINT8 ROMDATA arr2[]; - #undef F16_KB_UCODE_0106 - #define F16_KB_UCODE_0106 arr2, + extern CONST UINT8 ROMDATA CpuF16KbId7001MicrocodePatch[]; + #undef F16_KB_UCODE_7001 + #define F16_KB_UCODE_7001 CpuF16KbId7001MicrocodePatch, #endif CONST UINT8 ROMDATA *CpuF16KbMicroCodePatchArray[] = { - F16_KB_UCODE_0106 - F16_KB_UCODE_002A + F16_KB_UCODE_7001 + F16_KB_UCODE_7000 NULL }; diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionFchInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionFchInstall.h index 4c927af..4725504 100644 --- a/src/vendorcode/amd/agesa/f16kb/Include/OptionFchInstall.h +++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionFchInstall.h @@ -241,6 +241,7 @@ #define FCH_NO_GPP_SUPPORT TRUE #define FCH_NO_PCIB_SUPPORT TRUE #define FCH_NO_PCIE_SUPPORT TRUE + #define BLDOPT_RTC_WORKAROUND TRUE #else #error FCH_SUPPORT: No chip type selected. #endif @@ -929,6 +930,7 @@ InstallFchInitLatePcie, InstallFchInitLatePcib, InstallFchInitLateSpi, + InstallFchInitMidUsbEhci, InstallFchInitLateUsb, InstallFchInitLateUsbEhci, InstallFchInitLateUsbOhci, @@ -1011,6 +1013,14 @@ #endif +#define DFLT_RTC_WORKAROUND FALSE +#ifdef BLDOPT_RTC_WORKAROUND + #undef CFG_FCH_RTC_WORKAROUND + #define CFG_FCH_RTC_WORKAROUND BLDOPT_RTC_WORKAROUND +#else + #undef CFG_FCH_RTC_WORKAROUND + #define CFG_FCH_RTC_WORKAROUND DFLT_RTC_WORKAROUND +#endif CONST BLDOPT_FCH_FUNCTION ROMDATA BldoptFchFunction = { FP_FCH_INIT_RESET, diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionMemoryInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionMemoryInstall.h index 07becd2..1aaa027 100644 --- a/src/vendorcode/amd/agesa/f16kb/Include/OptionMemoryInstall.h +++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionMemoryInstall.h @@ -1263,16 +1263,34 @@ BOOLEAN MemFS3DefConstructorRet ( #define PSC_TBL_KB_ODT_TRI_FT3 &KBSODdr3ODTTriEntFT3, extern PSC_TBL_ENTRY KBSODdr3CSTriEntFT3; #define PSC_TBL_KB_CS_TRI_FT3 &KBSODdr3CSTriEntFT3, + #undef PSC_TBL_KB_UDIMM3_S2D_FT3 + #ifndef extern_S2DTblEntUFT3 + #define extern_S2DTblEntUFT3 + extern PSC_TBL_ENTRY S2DTblEntUFT3; + #endif + #define PSC_TBL_KB_UDIMM3_S2D_FT3 &S2DTblEntUFT3, #endif #if OPTION_UDIMMS - extern PSC_TBL_ENTRY KBMaxFreqTblEntU; - #define PSC_TBL_KB_UDIMM3_MAX_FREQ &KBMaxFreqTblEntU, - extern PSC_TBL_ENTRY KBDramTermTblEntU; - #define PSC_TBL_KB_UDIMM3_DRAM_TERM &KBDramTermTblEntU, - extern PSC_TBL_ENTRY KBSAOTblEntU3; - #define PSC_TBL_KB_UDIMM3_SAO &KBSAOTblEntU3, + #if (OPTION_MICROSERVER == TRUE) + extern PSC_TBL_ENTRY KBMaxFreqTblEntMicroSrvU6L; + #define PSC_TBL_KB_UDIMM3_MAX_FREQ_6L &KBMaxFreqTblEntMicroSrvU6L, + #else + extern PSC_TBL_ENTRY KBMaxFreqTblEntU6L; + #define PSC_TBL_KB_UDIMM3_MAX_FREQ_6L &KBMaxFreqTblEntU6L, + #endif + extern PSC_TBL_ENTRY KBMaxFreqTblEntU4L; + #define PSC_TBL_KB_UDIMM3_MAX_FREQ_4L &KBMaxFreqTblEntU4L, + #if OPTION_FT3_SOCKET_SUPPORT + extern PSC_TBL_ENTRY KBDramTermTblEntUFT3; + #define PSC_TBL_KB_UDIMM3_DRAM_TERM_FT3 &KBDramTermTblEntUFT3, + extern PSC_TBL_ENTRY KBSAOTblEntU3FT3; + #define PSC_TBL_KB_UDIMM3_SAO_FT3 &KBSAOTblEntU3FT3, + #endif #undef PSC_TBL_KB_UDIMM3_S2D_FT3 - extern PSC_TBL_ENTRY S2DTblEntUFT3; + #ifndef extern_S2DTblEntUFT3 + #define extern_S2DTblEntUFT3 + extern PSC_TBL_ENTRY S2DTblEntUFT3; + #endif #define PSC_TBL_KB_UDIMM3_S2D_FT3 &S2DTblEntUFT3, #endif #if OPTION_SODIMMS @@ -1299,10 +1317,6 @@ BOOLEAN MemFS3DefConstructorRet ( #define PSC_TBL_KB_SODWN_PLUS_SODIMM3_MAX_FREQ_4L &KBMaxFreqTblEntSoDwnPlusSODIMM6L, extern PSC_TBL_ENTRY KBMaxFreqTblEntSoDwn; #define PSC_TBL_KB_SODWN_MAX_FREQ &KBMaxFreqTblEntSoDwn, - extern PSC_TBL_ENTRY KBMaxFreqTblEntU6L; - #define PSC_TBL_KB_UDIMM3_MAX_FREQ_6L &KBMaxFreqTblEntU6L, - extern PSC_TBL_ENTRY KBMaxFreqTblEntU4L; - #define PSC_TBL_KB_UDIMM3_MAX_FREQ_4L &KBMaxFreqTblEntU4L, #undef PSC_TBL_KB_SODIMM3_S2D_FT3 #define PSC_TBL_KB_SODIMM3_S2D_FT3 #endif @@ -1334,8 +1348,8 @@ BOOLEAN MemFS3DefConstructorRet ( #ifndef PSC_TBL_KB_UDIMM3_MAX_FREQ_4L #define PSC_TBL_KB_UDIMM3_MAX_FREQ_4L #endif - #ifndef PSC_TBL_KB_UDIMM3_DRAM_TERM - #define PSC_TBL_KB_UDIMM3_DRAM_TERM + #ifndef PSC_TBL_KB_UDIMM3_DRAM_TERM_FT3 + #define PSC_TBL_KB_UDIMM3_DRAM_TERM_FT3 #endif #ifndef PSC_TBL_KB_SODIMM3_DRAM_TERM #define PSC_TBL_KB_SODIMM3_DRAM_TERM @@ -1355,8 +1369,8 @@ BOOLEAN MemFS3DefConstructorRet ( #ifndef PSC_TBL_KB_SODWN_SAO #define PSC_TBL_KB_SODWN_SAO #endif - #ifndef PSC_TBL_KB_UDIMM3_SAO - #define PSC_TBL_KB_UDIMM3_SAO + #ifndef PSC_TBL_KB_UDIMM3_SAO_FT3 + #define PSC_TBL_KB_UDIMM3_SAO_FT3 #endif #ifndef PSC_TBL_KB_CLK_DIS_FT3 #define PSC_TBL_KB_CLK_DIS_FT3 @@ -1384,7 +1398,7 @@ BOOLEAN MemFS3DefConstructorRet ( }; PSC_TBL_ENTRY* memPSCTblDramTermArrayKB[] = { - PSC_TBL_KB_UDIMM3_DRAM_TERM + PSC_TBL_KB_UDIMM3_DRAM_TERM_FT3 PSC_TBL_KB_SODIMM3_DRAM_TERM PSC_TBL_KB_SODWN_PLUS_SODIMM3_DRAM_TERM PSC_TBL_KB_SODWN_DRAM_TERM @@ -1401,7 +1415,7 @@ BOOLEAN MemFS3DefConstructorRet ( PSC_TBL_KB_SODIMM3_SAO PSC_TBL_KB_SODWN_PLUS_SODIMM3_SAO PSC_TBL_KB_SODWN_SAO - PSC_TBL_KB_UDIMM3_SAO + PSC_TBL_KB_UDIMM3_SAO_FT3 PSC_TBL_END }; diff --git a/src/vendorcode/amd/agesa/f16kb/Include/PlatformInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/PlatformInstall.h index 136b0f4..1295888 100644 --- a/src/vendorcode/amd/agesa/f16kb/Include/PlatformInstall.h +++ b/src/vendorcode/amd/agesa/f16kb/Include/PlatformInstall.h @@ -360,6 +360,9 @@ VOLATILE AMD_MODULE_HEADER mCpuModuleID = { #define OPTION_MEM_RESTORE TRUE #undef OPTION_DIMM_EXCLUDE #define OPTION_DIMM_EXCLUDE TRUE + #ifndef OPTION_MICROSERVER + #define OPTION_MICROSERVER FALSE + #endif #endif #endif @@ -1811,7 +1814,8 @@ FCH_PLATFORM_POLICY FchUserOptions = { CFG_FCH_SD_CLOCK_CONTROL, // CfgFchSdClockControl CFG_FCH_SCI_MAP_LIST, // *CfgFchSciMapControl CFG_FCH_SATA_PHY_LIST, // *CfgFchSataPhyControl - CFG_FCH_GPIO_CONTROL_LIST // *CfgFchGpioControl + CFG_FCH_GPIO_CONTROL_LIST, // *CfgFchGpioControl + CFG_FCH_RTC_WORKAROUND // CfgFchRtcWorkaround }; BUILD_OPT_CFG UserOptions = { diff --git a/src/vendorcode/amd/agesa/f16kb/Legacy/PlatformMemoryConfiguration.inc b/src/vendorcode/amd/agesa/f16kb/Legacy/PlatformMemoryConfiguration.inc index d75d04f..872f973 100644 --- a/src/vendorcode/amd/agesa/f16kb/Legacy/PlatformMemoryConfiguration.inc +++ b/src/vendorcode/amd/agesa/f16kb/Legacy/PlatformMemoryConfiguration.inc @@ -444,7 +444,7 @@ MEMORY_POWER_POLICY_OVERRIDE MACRO PowerPolicy:REQ DB PowerPolicy ENDM -MOTHER_RBOARD_LAYERS MACRO Layers:REQ +MOTHER_BOARD_LAYERS MACRO Layers:REQ DB PSO_MOTHER_BOARD_LAYERS DB 1 DB Layers diff --git a/src/vendorcode/amd/agesa/f16kb/Legacy/agesa.inc b/src/vendorcode/amd/agesa/f16kb/Legacy/agesa.inc index 010db87..7683b15 100644 --- a/src/vendorcode/amd/agesa/f16kb/Legacy/agesa.inc +++ b/src/vendorcode/amd/agesa/f16kb/Legacy/agesa.inc @@ -2453,6 +2453,7 @@ FCH_PLATFORM_POLICY STRUCT CfgFchSciMapControl POINTER ? ; FCH SCI Mapping Control CfgFchSataPhyControl POINTER ? ; FCH SATA PHY Control CfgFchGpioControl POINTER ? ; FCH GPIO Control + CfgFchRtcWorkaround BOOLEAN ? ; FCH RTC Workaround FCH_PLATFORM_POLICY ENDS diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCoreAfterReset.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCoreAfterReset.c index 0ae46c6..5ed8b60 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCoreAfterReset.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCoreAfterReset.c @@ -139,13 +139,13 @@ F16KbPmCoreAfterReset ( LibAmdPciRead (AccessWidth32, PciAddress, &HwPsMaxVal, StdHeader); HwPsMaxVal = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &HwPsMaxVal)->HwPstateMaxVal; - // Launch each local core to perform steps 1 through 3. + // Launch each local core to perform steps 1 through 4. TaskPtr.FuncAddress.PfApTask = F16KbPmCoreAfterResetPhase1OnCore; TaskPtr.DataTransfer.DataSizeInDwords = 0; TaskPtr.ExeFlags = WAIT_FOR_CORE; ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr); - // Launch each local core to perform steps 4 through 6. + // Launch each local core to perform steps 5 through 7. TaskPtr.FuncAddress.PfApTaskI = F16KbPmCoreAfterResetPhase2OnCore; TaskPtr.DataTransfer.DataSizeInDwords = 1; TaskPtr.DataTransfer.DataPtr = &HwPsMaxVal; @@ -176,25 +176,36 @@ F16KbPmCoreAfterResetPhase1OnCore ( IN AMD_CONFIG_PARAMS *StdHeader ) { - UINT64 CofvidSts; - UINT64 LocalMsrRegister; - UINT64 PstateCtrl; + BOOLEAN SkipStep3; + UINT64 CofvidSts; + UINT64 LocalMsrRegister; + UINT64 PstateCtrl; IDS_HDT_CONSOLE (CPU_TRACE, " F16KbPmCoreAfterResetPhase1OnCore\n"); - // 1. Write 0 to MSRC001_0062[PstateCmd] on all cores in the processor. + // 1. If MSRC001_0071[CurPstate] = MSRC001_0071[CurPstateLimit], then skip step 3 for that core + LibAmdMsrRead (MSR_COFVID_STS, &CofvidSts, StdHeader); + if (((COFVID_STS_MSR *) &CofvidSts)->CurPstate == ((COFVID_STS_MSR *) &CofvidSts)->CurPstateLimit) { + SkipStep3 = TRUE; + } else { + SkipStep3 = FALSE; + } + + // 2. Write 0 to MSRC001_0062[PstateCmd] on all cores in the processor. PstateCtrl = 0; LibAmdMsrWrite (MSR_PSTATE_CTL, &PstateCtrl, StdHeader); - // 2. Wait for MSRC001_0071[CurCpuFid, CurCpuDid] = [CpuFid, CpuDid] from + // 3. Wait for MSRC001_0071[CurCpuFid, CurCpuDid] = [CpuFid, CpuDid] from // MSRC001_00[6B:64] indexed by MSRC001_0071[CurPstateLimit]. - do { - LibAmdMsrRead (MSR_COFVID_STS, &CofvidSts, StdHeader); - LibAmdMsrRead ((UINT32) (MSR_PSTATE_0 + (UINT32) (((COFVID_STS_MSR *) &CofvidSts)->CurPstateLimit)), &LocalMsrRegister, StdHeader); - } while ((((COFVID_STS_MSR *) &CofvidSts)->CurCpuFid != ((PSTATE_MSR *) &LocalMsrRegister)->CpuFid) || - (((COFVID_STS_MSR *) &CofvidSts)->CurCpuDid != ((PSTATE_MSR *) &LocalMsrRegister)->CpuDid)); + if (!SkipStep3) { + do { + LibAmdMsrRead (MSR_COFVID_STS, &CofvidSts, StdHeader); + LibAmdMsrRead ((UINT32) (MSR_PSTATE_0 + (UINT32) (((COFVID_STS_MSR *) &CofvidSts)->CurPstateLimit)), &LocalMsrRegister, StdHeader); + } while ((((COFVID_STS_MSR *) &CofvidSts)->CurCpuFid != ((PSTATE_MSR *) &LocalMsrRegister)->CpuFid) || + (((COFVID_STS_MSR *) &CofvidSts)->CurCpuDid != ((PSTATE_MSR *) &LocalMsrRegister)->CpuDid)); + } - // 3. Write MSRC001_0061[PstateMaxVal] to MSRC001_0062[PstateCmd] on all + // 4. Write MSRC001_0061[PstateMaxVal] to MSRC001_0062[PstateCmd] on all // cores in the processor. LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &LocalMsrRegister, StdHeader); ((PSTATE_CTRL_MSR *) &PstateCtrl)->PstateCmd = ((PSTATE_CURLIM_MSR *) &LocalMsrRegister)->PstateMaxVal; diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbDmi.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbDmi.c index 37d0aa0..45b1b8f 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbDmi.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbDmi.c @@ -344,7 +344,7 @@ DmiF16KbGetExtClock ( IN AMD_CONFIG_PARAMS *StdHeader ) { - return (EXTERNAL_CLOCK_DFLT); + return (EXTERNAL_CLOCK_100MHZ); } /* -----------------------------------------------------------------------------*/ diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbId7001MicrocodePatch.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbId7001MicrocodePatch.c new file mode 100644 index 0000000..14fbfb2 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbId7001MicrocodePatch.c @@ -0,0 +1,3540 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD F16Kb Microcode patch. + * + * F16Kb Microcode Patch rev 0700010B for 7001 or equivalent. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x16/KB + * @e \$Revision: 267923 $ @e \$Date: 2013-07-15 16:49:48 -0400 (Mon, 15 Jul 2013) $ + */ +/***************************************************************************** + * + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************** + */ + + + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "cpuRegisters.h" +#include "cpuEarlyInit.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +UCODE_VS_FLAG (0700010B) + +// Encrypt Patch code 0700010B for 7001 and equivalent + +CONST UINT8 ROMDATA CpuF16KbId7001MicrocodePatch [IDS_PAD_4K] = +{ + 0x13, + 0x20, + 0x09, + 0x07, + 0x0b, + 0x01, + 0x00, + 0x07, + 0x03, + 0x80, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x01, + 0x70, + 0x00, + 0x00, + 0x00, + 0xaa, + 0xaa, + 0xaa, + 0x1c, + 0x8a, + 0x19, + 0x02, + 0x24, + 0xb6, + 0x41, + 0xb0, + 0x60, + 0x6a, + 0x6e, + 0xc3, + 0xdb, + 0xae, + 0xd9, + 0xa3, + 0x9e, + 0x4c, + 0x89, + 0xd2, + 0xe6, + 0xb8, + 0xb1, + 0x81, + 0x30, + 0xbd, + 0x57, + 0x94, + 0x81, + 0xa3, + 0xbc, + 0x81, + 0x95, + 0x47, + 0xb5, + 0x93, + 0x5f, + 0x8a, + 0xf6, + 0x82, + 0xcd, + 0x0e, + 0x4d, + 0xd3, + 0x26, + 0xd8, + 0xa8, + 0x35, + 0xb7, + 0x64, + 0xba, + 0x32, + 0x33, + 0x09, + 0xfd, + 0x93, + 0xc6, + 0x49, + 0x19, + 0xe3, + 0x53, + 0xc1, + 0xb5, + 0xcc, + 0x2f, + 0xf3, + 0x52, + 0xaa, + 0xe3, + 0x9c, + 0x79, + 0x52, + 0x10, + 0x5f, + 0xff, + 0x90, + 0x29, + 0x0b, + 0xf1, + 0x7f, + 0xfa, + 0x0c, + 0x10, + 0x75, + 0x84, + 0x74, + 0x81, + 0x8b, + 0x63, + 0xb3, + 0x71, + 0x20, + 0x25, + 0xc8, + 0x16, + 0x6d, + 0xc2, + 0xcc, + 0xf7, + 0x78, + 0x30, + 0xb6, + 0x2d, + 0x81, + 0x2b, + 0xdd, + 0xc4, + 0x6b, + 0xab, + 0x31, + 0x90, + 0xa8, + 0x6d, + 0xd7, + 0x6c, + 0xae, + 0x66, + 0xe5, + 0xdf, + 0xd6, + 0x65, + 0xd4, + 0x95, + 0xe5, + 0x68, + 0xae, + 0x26, + 0xa5, + 0x48, + 0xe6, + 0xf5, + 0xf3, + 0x22, + 0x67, + 0xb9, + 0x4d, + 0x22, + 0x38, + 0x32, + 0x51, + 0x4b, + 0x8a, + 0x6b, + 0xc1, + 0x9c, + 0xd2, + 0xc3, + 0x91, + 0xb5, + 0x43, + 0xe9, + 0xcc, + 0x73, + 0x49, + 0x07, + 0x7c, + 0x7d, + 0xe8, + 0xc8, + 0x5e, + 0x56, + 0x7a, + 0x22, + 0x80, + 0xcc, + 0xbd, + 0x21, + 0x1b, + 0x32, + 0x0d, + 0xd4, + 0x92, + 0x62, + 0x37, + 0xaf, + 0xf6, + 0x18, + 0xfa, + 0x9f, + 0x9f, + 0x12, + 0x6b, + 0x4b, + 0x4f, + 0x1d, + 0x5a, + 0xca, + 0x3c, + 0x7d, + 0x7d, + 0x38, + 0x66, + 0x00, + 0x90, + 0xc5, + 0x7e, + 0x44, + 0xf3, + 0xa8, + 0x65, + 0xc3, + 0x1b, + 0x41, + 0x1d, + 0xef, + 0xb3, + 0xd4, + 0x43, + 0xb5, + 0x02, + 0x1a, + 0x0d, + 0x08, + 0x44, + 0xa5, + 0x57, + 0xa7, + 0x65, + 0x90, + 0xdc, + 0xdc, + 0x1e, + 0xdf, + 0x45, + 0x5f, + 0x88, + 0xdc, + 0x7c, + 0xd6, + 0x09, + 0x57, + 0x01, + 0x33, + 0xfc, + 0x47, + 0xad, + 0xa0, + 0x49, + 0x0c, + 0x55, + 0xc4, + 0xfd, + 0xf1, + 0x68, + 0xd2, + 0x67, + 0x0c, + 0xf1, + 0x92, + 0xa4, + 0x9b, + 0x50, + 0x34, + 0x5d, + 0xea, + 0x58, + 0x5b, + 0x2a, + 0x58, + 0x44, + 0x53, + 0xdf, + 0x59, + 0xbc, + 0x14, + 0xe3, + 0x7f, + 0xd6, + 0x4a, + 0xd6, + 0x98, + 0x59, + 0x8c, + 0xbb, + 0xce, + 0xe6, + 0x86, + 0xdb, + 0x66, + 0xbd, + 0xeb, + 0x51, + 0xf1, + 0xce, + 0x80, + 0x0f, + 0xd9, + 0x83, + 0x86, + 0x17, + 0xed, + 0x78, + 0x3e, + 0x5d, + 0xac, + 0xd1, + 0x13, + 0xfa, + 0x01, + 0x58, + 0x35, + 0xe9, + 0x66, + 0x16, + 0x5d, + 0xa8, + 0x70, + 0x08, + 0x0e, + 0xa3, + 0xab, + 0x3b, + 0xd1, + 0x75, + 0xbf, + 0x2f, + 0xb2, + 0x9a, + 0x7c, + 0xd8, + 0x84, + 0x66, + 0x1a, + 0x07, + 0x00, + 0xe0, + 0x04, + 0xbf, + 0x0e, + 0x04, + 0xaa, + 0x0e, + 0x91, + 0x6f, + 0xb4, + 0xb8, + 0xff, + 0xfa, + 0xad, + 0xb0, + 0xd8, + 0x41, + 0x65, + 0xf5, + 0xd5, + 0x0d, + 0x12, + 0x15, + 0xbf, + 0x40, + 0x5b, + 0xed, + 0xeb, + 0x81, + 0x2a, + 0x1f, + 0x48, + 0x00, + 0x5b, + 0xf7, + 0x08, + 0x35, + 0x86, + 0x8d, + 0xe4, + 0x15, + 0x52, + 0x40, + 0x1b, + 0x88, + 0x5a, + 0x8f, + 0xd0, + 0x4f, + 0xb5, + 0xbc, + 0xdb, + 0x45, + 0x30, + 0xc5, + 0x89, + 0x32, + 0x98, + 0xf9, + 0xa7, + 0x18, + 0x27, + 0xf1, + 0x0b, + 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0xbb, + 0xe7, + 0x52, + 0xbe, + 0xc5, + 0xeb, + 0xc8, + 0x2b, + 0xb9, + 0x40, + 0x7d, + 0x5a, + 0xf8, + 0x4c, + 0x8e, + 0x84, + 0x64, + 0xb9, + 0x32, + 0x38, + 0x3d, + 0xf8, + 0x4e, + 0xe5, + 0x82, + 0x87, + 0xbe, + 0x69, + 0x3a, + 0x66, + 0xd0, + 0x3c, + 0x1e, + 0x40, + 0x14, + 0xc0, + 0x71, + 0x12, + 0x8b, + 0xee, + 0x1f, + 0x2b, + 0x5f, + 0xe9, + 0x80, + 0x1e, + 0x10, + 0x48, + 0x1e, + 0xcb, + 0xba, + 0x10, + 0x22, + 0x45, + 0x67, + 0xf3, + 0xbd, + 0x3f, + 0x97, + 0x86, + 0x7d, + 0x3f, + 0x01, + 0x00, + 0x00, + 0x00, + 0x0b, + 0x01, + 0x00, + 0x07, + 0xe2, + 0x13, + 0xe7, + 0x13, + 0x93, + 0x07, + 0x66, + 0x04, + 0x60, + 0x04, + 0xd7, + 0x19, + 0x04, + 0x07, + 0xda, + 0x09, + 0x4f, + 0x15, + 0x2e, + 0x07, + 0xe3, + 0x16, + 0xf0, + 0x0c, + 0xf0, + 0x0c, + 0xf0, + 0x0c, + 0xf0, + 0x0c, + 0xf0, + 0x0c, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 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0x99, + 0xb6, + 0x9d, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, +}; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbInitEarlyTable.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbInitEarlyTable.c index 9c0e54b..1e1b23d 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbInitEarlyTable.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbInitEarlyTable.c @@ -52,6 +52,7 @@ #include "cpuFamilyTranslation.h" #include "Filecode.h" #include "cpuEarlyInit.h" +#include "cpuFeatures.h" CODE_GROUP (G2_PEI) RDATA_GROUP (G2_PEI) #define FILECODE PROC_CPU_FAMILY_0X16_KB_F16KBINITEARLYTABLE_FILECODE @@ -88,6 +89,13 @@ GetF16KbEarlyInitAfterApLaunchOnCoreTable ( IN AMD_CPU_EARLY_PARAMS *EarlyParams, IN AMD_CONFIG_PARAMS *StdHeader ); + +VOID +F16KbLoadMicrocodePatchAtEarly ( + IN CPU_SPECIFIC_SERVICES *FamilyServices, + IN AMD_CPU_EARLY_PARAMS *EarlyParams, + IN AMD_CONFIG_PARAMS *StdHeader + ); /*---------------------------------------------------------------------------------------- * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- @@ -141,3 +149,27 @@ GetF16KbEarlyInitAfterApLaunchOnCoreTable ( *Table = F16KbEarlyInitAfterApLaunchOnCoreTable; } +/*---------------------------------------------------------------------------------------*/ +/** + * Update microcode patch in current processor for Family16h KB. + * + * This function acts as a wrapper for calling the LoadMicrocodePatch + * routine at AmdInitEarly. + * + * @param[in] FamilyServices The current Family Specific Services. + * @param[in] EarlyParams Service parameters. + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +F16KbLoadMicrocodePatchAtEarly ( + IN CPU_SPECIFIC_SERVICES *FamilyServices, + IN AMD_CPU_EARLY_PARAMS *EarlyParams, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + if (!IsFeatureEnabled (C6Cstate, &EarlyParams->PlatformConfig, StdHeader)) { + AGESA_TESTPOINT (TpProcCpuLoadUcode, StdHeader); + LoadMicrocodePatch (StdHeader); + } +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbMicrocodePatch0700002A_Enc.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbMicrocodePatch0700002A_Enc.c deleted file mode 100644 index 5a010ae..0000000 --- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbMicrocodePatch0700002A_Enc.c +++ /dev/null @@ -1,3539 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD F16Kb Microcode patch. - * - * F16Kb Microcode Patch rev 0700002A for 7000 or equivalent. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x16/KB - * @e \$Revision: 84798 $ @e \$Date: 2012-12-19 21:26:23 -0600 (Wed, 19 Dec 2012) $ - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - - - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuEarlyInit.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -// Encrypt Patch code 0700002A for 7000 and equivalent - -CONST UINT8 ROMDATA arr1 [IDS_PAD_4K] = -{ - 0x12, - 0x20, - 0x18, - 0x12, - 0x2a, - 0x00, - 0x00, - 0x07, - 0x03, - 0x80, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x70, - 0x00, - 0x00, - 0x00, - 0xaa, - 0xaa, - 0xaa, - 0x49, - 0x98, - 0x47, - 0x92, - 0x9e, - 0x94, - 0x1c, - 0x90, - 0x43, - 0x82, - 0xfb, - 0x61, - 0x5c, - 0xc3, - 0x8a, - 0xb1, - 0xd7, - 0x77, - 0xc5, - 0x2f, - 0xe2, - 0x32, - 0x8e, - 0xa2, - 0xfe, - 0x17, - 0x86, - 0x8b, - 0xea, - 0xf8, - 0x9c, - 0x9a, - 0xdb, - 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