Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35739 )
Change subject: soc/intel/common/block: Update microcode for each core
......................................................................
soc/intel/common/block: Update microcode for each core
On Hyper-Threading enabled platform update the microcde only once
for each core, not for each thread.
Follow Intel Software Developer Guidelines as the added comment
also states.
Change-Id: I72804753e567a137a5648ca6950009fed332531b
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/soc/intel/common/block/cpu/mp_init.c
1 file changed, 20 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/35739/1
diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c
index 2c5061f..e7689cf 100644
--- a/src/soc/intel/common/block/cpu/mp_init.c
+++ b/src/soc/intel/common/block/cpu/mp_init.c
@@ -26,6 +26,7 @@
#include <intelblocks/fast_spi.h>
#include <intelblocks/mp_init.h>
#include <intelblocks/msr.h>
+#include <cpu/intel/common/common.h>
#include <soc/cpu.h>
static const void *microcode_patch;
@@ -44,7 +45,24 @@
static void init_one_cpu(struct device *dev)
{
soc_core_init(dev);
- intel_microcode_load_unlocked(microcode_patch);
+
+ /*
+ * Update just on the first CPU in the core. Other siblings
+ * get the update automatically according to Document: 253668-060US
+ * Intel SDM Chapter 9.11.6.3
+ * "Update in a System Supporting Intel Hyper-Threading Technology"
+ * Intel Hyper-Threading Technology has implications on the loading of the
+ * microcode update. The update must be loaded for each core in a physical
+ * processor. Thus, for a processor supporting Intel Hyper-Threading
+ * Technology, only one logical processor per core is required to load the
+ * microcode update. Each individual logical processor can independently
+ * load the update. However, MP initialization must provide some mechanism
+ * (e.g. a software semaphore) to force serialization of microcode update
+ * loads and to prevent simultaneous load attempts to the same core.
+ */
+ if (!intel_ht_sibling()) {
+ intel_microcode_load_unlocked(microcode_patch);
+ }
}
static struct device_operations cpu_dev_ops = {
@@ -141,6 +159,7 @@
if (CONFIG(USE_INTEL_FSP_MP_INIT))
return;
+ /* Update microcode on BSP */
microcode_patch = intel_microcode_find();
intel_microcode_load_unlocked(microcode_patch);
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I72804753e567a137a5648ca6950009fed332531b
Gerrit-Change-Number: 35739
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Gerrit-MessageType: newchange
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37368 )
Change subject: arch/x86/car: Remove runtime stack alignment enforcing
......................................................................
arch/x86/car: Remove runtime stack alignment enforcing
This is now checked at buildtime.
Change-Id: Ice687b1a4de53de4799e90238c98cfef19a81136
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/cpu/intel/car/core2/cache_as_ram.S
M src/cpu/intel/car/non-evict/cache_as_ram.S
M src/cpu/intel/car/p3/cache_as_ram.S
M src/cpu/intel/car/p4-netburst/cache_as_ram.S
M src/cpu/qemu-x86/cache_as_ram_bootblock.S
M src/soc/intel/common/block/cpu/car/cache_as_ram.S
6 files changed, 0 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/37368/1
diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S
index 73618d9..be96633 100644
--- a/src/cpu/intel/car/core2/cache_as_ram.S
+++ b/src/cpu/intel/car/core2/cache_as_ram.S
@@ -173,7 +173,6 @@
/* Need to align stack to 16 bytes at call instruction. Account for
the pushes below. */
- andl $0xfffffff0, %esp
subl $4, %esp
/* push TSC and BIST to stack */
diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S
index 5a668c4..6c78ddb 100644
--- a/src/cpu/intel/car/non-evict/cache_as_ram.S
+++ b/src/cpu/intel/car/non-evict/cache_as_ram.S
@@ -219,7 +219,6 @@
/* Need to align stack to 16 bytes at call instruction. Account for
the pushes below. */
- andl $0xfffffff0, %esp
subl $4, %esp
/* push TSC and BIST to stack */
diff --git a/src/cpu/intel/car/p3/cache_as_ram.S b/src/cpu/intel/car/p3/cache_as_ram.S
index 5262b18..8c3009a 100644
--- a/src/cpu/intel/car/p3/cache_as_ram.S
+++ b/src/cpu/intel/car/p3/cache_as_ram.S
@@ -161,7 +161,6 @@
/* Need to align stack to 16 bytes at call instruction. Account for
the pushes below. */
- andl $0xfffffff0, %esp
subl $4, %esp
/* push TSC and BIST to stack */
diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
index fdeb0af..8fd240d 100644
--- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S
+++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
@@ -372,7 +372,6 @@
/* Need to align stack to 16 bytes at call instruction. Account for
the pushes below. */
- andl $0xfffffff0, %esp
subl $4, %esp
/* push TSC and BIST to stack */
diff --git a/src/cpu/qemu-x86/cache_as_ram_bootblock.S b/src/cpu/qemu-x86/cache_as_ram_bootblock.S
index 1fa0018..c1fe52d 100644
--- a/src/cpu/qemu-x86/cache_as_ram_bootblock.S
+++ b/src/cpu/qemu-x86/cache_as_ram_bootblock.S
@@ -37,8 +37,6 @@
movl $_ecar_stack, %esp
/* Align the stack and keep aligned for call to bootblock_c_entry() */
- and $0xfffffff0, %esp
-
/* Restore the BIST result and timestamps. */
#if defined(__x86_64__)
movd %mm1, %rdi
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
index 0992d85..5d7eafa 100644
--- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S
+++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
@@ -174,7 +174,6 @@
/* Need to align stack to 16 bytes at call instruction. Account for
the two pushes below. */
- andl $0xfffffff0, %esp
sub $8, %esp
/* push TSC value to stack */
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ice687b1a4de53de4799e90238c98cfef19a81136
Gerrit-Change-Number: 37368
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-MessageType: newchange
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37367 )
Change subject: arch/x86/car.ld: Assert at buildtime that _ecar_stack is aligned
......................................................................
arch/x86/car.ld: Assert at buildtime that _ecar_stack is aligned
This can be used to avoid aligning the stack at runtime.
Change-Id: I3aa068d947b6b6110fd7d002522f28a13e725cf7
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/arch/x86/car.ld
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/37367/1
diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld
index 483a908..2d1723e 100644
--- a/src/arch/x86/car.ld
+++ b/src/arch/x86/car.ld
@@ -124,3 +124,4 @@
#if !CONFIG(ROMCC_BOOTBLOCK)
_bogus3 = ASSERT(CONFIG_DCACHE_BSP_STACK_SIZE > 0x0, "BSP stack size not configured");
#endif
+_bogus4 = ASSERT(_ecar_stack == ((_ecar_stack + 0xf) & ~0xf), "_ecar_stack must be 16 aligned");
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I3aa068d947b6b6110fd7d002522f28a13e725cf7
Gerrit-Change-Number: 37367
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-MessageType: newchange
Idwer Vollering has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37968 )
Change subject: romcc: cleanup leftovers
......................................................................
romcc: cleanup leftovers
Change-Id: I5112e0ce66e3bcd8c1f020089278766d2f27edb8
Signed-off-by: Idwer Vollering <vidwer(a)gmail.com>
---
M .gitignore
M util/README.md
M util/abuild/abuild.1
M util/lint/check_lint_tests
M util/lint/lint-000-license-headers
M util/lint/lint-014-qualified-types
M util/lint/lint-extended-015-final-newlines
M util/lint/lint-stable-010-asm-syntax
8 files changed, 2 insertions(+), 31 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/37968/1
diff --git a/.gitignore b/.gitignore
index 0cc6ae2..86ddd19 100644
--- a/.gitignore
+++ b/.gitignore
@@ -115,7 +115,6 @@
util/nvramtool/nvramtool
util/optionlist/Options.wiki
util/pmh7tool/pmh7tool
-util/romcc/build
util/runfw/googlesnow
util/superiotool/superiotool
util/vgabios/testbios
diff --git a/util/README.md b/util/README.md
index 55bcaab..66438a9 100644
--- a/util/README.md
+++ b/util/README.md
@@ -86,8 +86,6 @@
* _sifive-gpt.py_ - Wraps the bootblock in a GPT partition for
SiFive's bootrom. `Python3`
* __rockchip__ - Generate Rockchip idblock bootloader. `Python2`
-* __romcc__ - Compile a C source file generating a binary that does not
-implicitly use RAM. `C`
* __sconfig__ - coreboot device tree compiler `Lex` `Yacc`
* __scripts__
* _config_ - Manipulate options in a .config file from the
diff --git a/util/abuild/abuild.1 b/util/abuild/abuild.1
index 2eee84b..ccdfff6 100644
--- a/util/abuild/abuild.1
+++ b/util/abuild/abuild.1
@@ -78,7 +78,6 @@
.B abuild
is covered by the GNU General Public License (GPL), version 2 or later.
.SH SEE ALSO
-.BR romcc (1),
.BR flashrom (1).
.SH COPYRIGHT
2004 Stefan Reinauer
diff --git a/util/lint/check_lint_tests b/util/lint/check_lint_tests
index 6b1860f..20d49a7 100755
--- a/util/lint/check_lint_tests
+++ b/util/lint/check_lint_tests
@@ -35,11 +35,6 @@
sed -i "s/for more details./for more details.\n \* You${SPACE}should${SPACE}have received a copy of the GNU General Public License\n \* along with this program; if not, write to the Free Software\n \* Foundation, Inc./" ${TESTFILE009}
git add ${TESTFILE009}
-#lint-stable-010-asm-syntax
-TESTFILE010=src/arch/x86/bootblock_romcc.S
-sed -i "1s/^/.att${UNDERSCORE}syntax noprefix\n/" ${TESTFILE010}
-git add ${TESTFILE010}
-
#lint-stable-012-executable-bit
TESTFILE012=src/lib/libgcc.c
chmod +x ${TESTFILE012}
diff --git a/util/lint/lint-000-license-headers b/util/lint/lint-000-license-headers
index 9b3553b..5adbc7c 100755
--- a/util/lint/lint-000-license-headers
+++ b/util/lint/lint-000-license-headers
@@ -24,8 +24,6 @@
^util/amdtools/example_input/|\
^util/cbfstool/lzma/|\
^util/kconfig/|\
-^util/romcc/tests|\
-^util/romcc/results|\
Kconfig|\
\<COPYING\>|\
\<LICENSE\>|\
diff --git a/util/lint/lint-014-qualified-types b/util/lint/lint-014-qualified-types
index 98679ea..976748f 100755
--- a/util/lint/lint-014-qualified-types
+++ b/util/lint/lint-014-qualified-types
@@ -17,7 +17,7 @@
LC_ALL=C export LC_ALL
INCLUDED_DIRS='^src/\|^util/\|payloads/libpayload\|payloads/coreinfo'
-EXCLUDED_DIRS='^src/vendorcode\|^util/romcc\|cbfstool/lzma\|cbfstool/lz4'
+EXCLUDED_DIRS='^src/vendorcode\|^util/cbfstool/lzma\|cbfstool/lz4'
INCLUDED_FILES='\.[ch]:'
# Use git grep if the code is in a git repo, otherwise use grep.
diff --git a/util/lint/lint-extended-015-final-newlines b/util/lint/lint-extended-015-final-newlines
index b5a503f..15462d6 100755
--- a/util/lint/lint-extended-015-final-newlines
+++ b/util/lint/lint-extended-015-final-newlines
@@ -18,7 +18,7 @@
PIDS=""
INCLUDED_DIRS_AND_FILES='util/* src/* payloads/* configs/* Makefile *.inc'
-EXCLUDED_DIRS='src/vendorcode/\|util/romcc/\|cbfstool/lzma/\|cbfstool/lz4/\|Documentation/\|build/\|3rdparty/\|\.git/\|coreboot-builds/\|util/nvidia/cbootimage/'
+EXCLUDED_DIRS='src/vendorcode/\|util/cbfstool/lzma/\|cbfstool/lz4/\|Documentation/\|build/\|3rdparty/\|\.git/\|coreboot-builds/\|util/nvidia/cbootimage/'
EXCLUDED_FILES='\.jpg$\|\.cksum$\|\.bin$\|\.vbt$\|\.hex$\|\.ico$\|\.o$\|\.bz2$\|\.xz$\|^.tmpconfig\|\.pyc$\|_shipped$\|sha256$\|\.png$\|\.patch$'
# Use git ls-files if the code is in a git repo, otherwise use find.
diff --git a/util/lint/lint-stable-010-asm-syntax b/util/lint/lint-stable-010-asm-syntax
index a102a77..e69de29 100755
--- a/util/lint/lint-stable-010-asm-syntax
+++ b/util/lint/lint-stable-010-asm-syntax
@@ -1,18 +0,0 @@
-#!/bin/sh
-# This file is part of the coreboot project.
-#
-# Copyright 2016 Google Inc.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# DESCR: Check that we use a single assembler syntax
-
-LC_ALL=C export LC_ALL
-git grep -n "\.\(att\|intel\)_syntax\>" | grep -v '\.patch:'
--
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Gerrit-Branch: master
Gerrit-Change-Id: I5112e0ce66e3bcd8c1f020089278766d2f27edb8
Gerrit-Change-Number: 37968
Gerrit-PatchSet: 1
Gerrit-Owner: Idwer Vollering <vidwer(a)gmail.com>
Gerrit-MessageType: newchange
Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30957
Change subject: superio/ite: Add and use it8528e
......................................................................
superio/ite: Add and use it8528e
* Add SuperIO ITE8528E
* Use ITE8528E to configure serial on wedge100s
TODO: Add support for accessing EC space.
Tested on wedge100s. The serial works without CONFIG_CONSOLE_SERIAL.
Change-Id: I72aa756e123d6f99d9ef4fe955c4b7f1be25d547
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/mainboard/ocp/wedge100s/Kconfig
M src/mainboard/ocp/wedge100s/devicetree.cb
M src/superio/ite/Makefile.inc
A src/superio/ite/it8528e/Kconfig
A src/superio/ite/it8528e/Makefile.inc
A src/superio/ite/it8528e/chip.h
A src/superio/ite/it8528e/it8528e.h
A src/superio/ite/it8528e/superio.c
8 files changed, 226 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/30957/1
diff --git a/src/mainboard/ocp/wedge100s/Kconfig b/src/mainboard/ocp/wedge100s/Kconfig
index ce9c097..6224340 100644
--- a/src/mainboard/ocp/wedge100s/Kconfig
+++ b/src/mainboard/ocp/wedge100s/Kconfig
@@ -16,6 +16,7 @@
select MAINBOARD_HAS_LPC_TPM
select MAINBOARD_HAS_TPM1
select DRIVERS_UART_8250IO
+ select SUPERIO_ITE_IT8528E
config VBOOT
select VBOOT_VBNV_CMOS
diff --git a/src/mainboard/ocp/wedge100s/devicetree.cb b/src/mainboard/ocp/wedge100s/devicetree.cb
index 3d66d0d..fc6dccc 100644
--- a/src/mainboard/ocp/wedge100s/devicetree.cb
+++ b/src/mainboard/ocp/wedge100s/devicetree.cb
@@ -11,6 +11,58 @@
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
+ chip superio/ite/it8528e
+ # COM1, routed to COM-e header
+ device pnp 6e.1 on
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ # COM2, routed to COM-e header
+ device pnp 6e.2 on
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 6e.4 off end
+ device pnp 6e.5 off end
+ device pnp 6e.6 off end
+ device pnp 6e.a off end
+ device pnp 6e.f off end
+ device pnp 6e.10 off
+ io 0x60 = 0x70
+ io 0x62 = 0x72
+ irq 0x70 = 8
+ end
+ device pnp 6e.11 off
+ io 0x60 = 0x620
+ io 0x62 = 0x660
+ irq 0x70 = 1
+ end
+ device pnp 6e.12 off
+ io 0x60 = 0x680
+ io 0x62 = 0x6c0
+ irq 0x70 = 1
+ end
+ device pnp 6e.13 off
+ io 0x60 = 0x300
+ irq 0x70 = 2
+ end
+ device pnp 6e.14 off end
+ device pnp 6e.17 off
+ io 0x60 = 0x6a0
+ io 0x62 = 0x6e0
+ irq 0x70 = 1
+ end
+ device pnp 6e.18 off
+ io 0x60 = 0x740
+ io 0x62 = 0x780
+ irq 0x70 = 1
+ end
+ device pnp 6e.19 off
+ io 0x60 = 0x7a0
+ io 0x62 = 0x7c0
+ irq 0x70 = 1
+ end
+ end #superio/ite/it8528e
end # LPC Bridge
device pci 1f.2 on end # SATA Controller
device pci 1f.3 on end # SMBus Controller
diff --git a/src/superio/ite/Makefile.inc b/src/superio/ite/Makefile.inc
index e73fd71..551abe9 100644
--- a/src/superio/ite/Makefile.inc
+++ b/src/superio/ite/Makefile.inc
@@ -20,6 +20,7 @@
## include generic ite environment controller driver
ramstage-$(CONFIG_SUPERIO_ITE_ENV_CTRL) += common/env_ctrl.c
+subdirs-y += it8528e
subdirs-y += it8623e
subdirs-y += it8671f
subdirs-y += it8712f
diff --git a/src/superio/ite/it8528e/Kconfig b/src/superio/ite/it8528e/Kconfig
new file mode 100644
index 0000000..3815c28
--- /dev/null
+++ b/src/superio/ite/it8528e/Kconfig
@@ -0,0 +1,18 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2019 Patrick Rudolph <patrick.rudolph(a)9elements.com>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+config SUPERIO_ITE_IT8528E
+ bool
+ select SUPERIO_ITE_COMMON_PRE_RAM
diff --git a/src/superio/ite/it8528e/Makefile.inc b/src/superio/ite/it8528e/Makefile.inc
new file mode 100644
index 0000000..def04e5
--- /dev/null
+++ b/src/superio/ite/it8528e/Makefile.inc
@@ -0,0 +1,17 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2019 Patrick Rudolph <patrick.rudolph(a)9elements.com>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+ramstage-$(CONFIG_SUPERIO_ITE_IT8528E) += superio.c
diff --git a/src/superio/ite/it8528e/chip.h b/src/superio/ite/it8528e/chip.h
new file mode 100644
index 0000000..ef7e14f
--- /dev/null
+++ b/src/superio/ite/it8528e/chip.h
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Patrick Rudolph <patrick.rudolph(a)9elements.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SUPERIO_ITE_IT8528E_CHIP_H
+#define SUPERIO_ITE_IT8528E_CHIP_H
+
+#include <superio/ite/common/env_ctrl_chip.h>
+
+struct superio_ite_it8528e_config {
+ // FIXME: Add support for EC
+};
+
+#endif /* SUPERIO_ITE_IT8528E_CHIP_H */
diff --git a/src/superio/ite/it8528e/it8528e.h b/src/superio/ite/it8528e/it8528e.h
new file mode 100644
index 0000000..7b19349
--- /dev/null
+++ b/src/superio/ite/it8528e/it8528e.h
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Patrick Rudolph <patrick.rudolph(a)9elements.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SUPERIO_ITE_IT8528E_H
+#define SUPERIO_ITE_IT8528E_H
+
+#define IT8528E_SP1 0x01 /* Com1 */
+#define IT8528E_SP2 0x02 /* Com2 */
+#define IT8528E_SWUC 0x04 /* System Wake-Up */
+#define IT8528E_KBCM 0x05 /* PS/2 mouse */
+#define IT8528E_KBCK 0x06 /* PS/2 keyboard */
+#define IT8528E_IR 0x0a /* Consumer IR */
+#define IT8528E_SMFI 0x0f /* Shared Memory/Flash Interface */
+#define IT8528E_RTCT 0x10 /* RTC-like Timer */
+#define IT8528E_PMC1 0x11 /* Power Management Channel 1 */
+#define IT8528E_PMC2 0x12 /* Power Management Channel 2 */
+#define IT8528E_SSPI 0x13 /* Serial Periphial Interface */
+#define IT8528E_PECI 0x14 /* Platform EC Interface */
+#define IT8528E_PMC3 0x17 /* Power Management Channel 3 */
+#define IT8528E_PMC4 0x18 /* Power Management Channel 4 */
+#define IT8528E_PMC5 0x19 /* Power Management Channel 5 */
+
+
+#endif /* SUPERIO_ITE_IT8528E_H */
diff --git a/src/superio/ite/it8528e/superio.c b/src/superio/ite/it8528e/superio.c
new file mode 100644
index 0000000..ae2a8e9
--- /dev/null
+++ b/src/superio/ite/it8528e/superio.c
@@ -0,0 +1,74 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de>
+ * Copyright (C) 2007 Philipp Degler <pdegler(a)rumms.uni-mannheim.de>
+ * Copyright (C) 2017 Gergely Kiss <mail.gery(a)gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/device.h>
+#include <device/pnp.h>
+#include <arch/io.h>
+#include <stdlib.h>
+#include <superio/conf_mode.h>
+
+#include "chip.h"
+#include "it8528e.h"
+
+static void it8528e_init(struct device *dev)
+{
+ // FIXME: Init EC
+}
+
+static struct device_operations ops = {
+ .read_resources = pnp_read_resources,
+ .set_resources = pnp_set_resources,
+ .enable_resources = pnp_enable_resources,
+ .enable = pnp_alt_enable,
+ .init = it8528e_init,
+ .ops_pnp_mode = &pnp_conf_mode_870155_aa,
+};
+
+static struct pnp_info pnp_dev_info[] = {
+ { NULL, IT8528E_SP1, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
+ { NULL, IT8528E_SP2, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
+ { NULL, IT8528E_SWUC, PNP_IO0 | PNP_IRQ0, 0xfff0, },
+ { NULL, IT8528E_KBCM, PNP_IRQ0, },
+ /* Documentation: Programm io0 = 0x60 and io1 = 0x64 */
+ { NULL, IT8528E_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff, },
+ { NULL, IT8528E_IR, PNP_IO0 | PNP_IRQ0, 0xfff8, },
+ { NULL, IT8528E_SMFI, PNP_IO0 | PNP_IRQ0, 0xfff0, },
+ /* Documentation: Programm io0 = 0x70 and io1 = 0x272 */
+ { NULL, IT8528E_RTCT, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IO3 | PNP_IRQ0,
+ 0xfffe, 0xfffe, 0xfffe, 0xfffe},
+ /* Documentation: Programm io0 = 0x62 and io1 = 0x66 */
+ { NULL, IT8528E_PMC1, PNP_IO0 | PNP_IO1 | PNP_IRQ0 , 0x07ff, 0x07ff },
+ { NULL, IT8528E_PMC2, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IRQ0 , 0x07fc,
+ 0x07fc, 0xfff0 },
+ /* Documentation is unclear if PMC3-5 have LPC I/O decoding support */
+ { NULL, IT8528E_PMC3, PNP_IO0 | PNP_IO1 | PNP_IRQ0 , 0x07ff, 0x07ff },
+ { NULL, IT8528E_PMC4, PNP_IO0 | PNP_IO1 | PNP_IRQ0 , 0x07ff, 0x07ff },
+ { NULL, IT8528E_PMC5, PNP_IO0 | PNP_IO1 | PNP_IRQ0 , 0x07ff, 0x07ff },
+ { NULL, IT8528E_SSPI, PNP_IO0 | PNP_IRQ0, 0xfff8 },
+ { NULL, IT8528E_PECI, PNP_IO0 , 0xfff8 },
+};
+
+static void enable_dev(struct device *dev)
+{
+ pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
+}
+
+struct chip_operations superio_ite_it8528e_ops = {
+ CHIP_NAME("ITE IT8528E Super I/O")
+ .enable_dev = enable_dev,
+};
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I72aa756e123d6f99d9ef4fe955c4b7f1be25d547
Gerrit-Change-Number: 30957
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Gerrit-MessageType: newchange
Daniel Maslowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36071 )
Change subject: superio: IT8587E (WIP)
......................................................................
superio: IT8587E (WIP)
Change-Id: I1e541daa2b3d48a4f5a0e7b7fa88a2c2f8a1b0c5
Signed-off-by: Daniel Maslowski <info(a)orangecms.org>
---
A src/superio/ite/it8587e/Kconfig
A src/superio/ite/it8587e/Makefile.inc
A src/superio/ite/it8587e/it8587e.h
A src/superio/ite/it8587e/superio.c
4 files changed, 137 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/36071/1
diff --git a/src/superio/ite/it8587e/Kconfig b/src/superio/ite/it8587e/Kconfig
new file mode 100644
index 0000000..438bd3e
--- /dev/null
+++ b/src/superio/ite/it8587e/Kconfig
@@ -0,0 +1,16 @@
+##
+## This file is part of the coreboot project.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+config SUPERIO_ITE_IT8587E
+ bool
+ select SUPERIO_ITE_COMMON_PRE_RAM
diff --git a/src/superio/ite/it8587e/Makefile.inc b/src/superio/ite/it8587e/Makefile.inc
new file mode 100644
index 0000000..dbde0b7
--- /dev/null
+++ b/src/superio/ite/it8587e/Makefile.inc
@@ -0,0 +1,15 @@
+##
+## This file is part of the coreboot project.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+ramstage-$(CONFIG_SUPERIO_ITE_IT8587E) += superio.c
diff --git a/src/superio/ite/it8587e/it8587e.h b/src/superio/ite/it8587e/it8587e.h
new file mode 100644
index 0000000..eab3527
--- /dev/null
+++ b/src/superio/ite/it8587e/it8587e.h
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SUPERIO_ITE_IT8587E_H
+#define SUPERIO_ITE_IT8587E_H
+
+#define IT8528E_SP1 0x01 /* Com1 */
+#define IT8528E_SP2 0x02 /* Com2 */
+#define IT8587E_SWUC 0x04 /* System Wake-Up */
+#define IT8587E_KBCM 0x05 /* PS/2 mouse */
+#define IT8587E_KBCK 0x06 /* PS/2 keyboard */
+#define IT8587E_SMFI 0x0f /* Shared Memory/Flash Interface */
+#define IT8587E_RTCT 0x10 /* RTC-like Timer */
+#define IT8587E_PMC1 0x11 /* Power Management Channel 1 */
+#define IT8587E_PMC2 0x12 /* Power Management Channel 2 */
+#define IT8587E_SSPI 0x13 /* Serial Periphial Interface */
+#define IT8587E_PECI 0x14 /* Platform EC Interface */
+#define IT8587E_PMC3 0x17 /* Power Management Channel 3 */
+#define IT8587E_PMC4 0x18 /* Power Management Channel 4 */
+#define IT8587E_PMC5 0x19 /* Power Management Channel 5 */
+
+
+#endif /* SUPERIO_ITE_IT8587E_H */
diff --git a/src/superio/ite/it8587e/superio.c b/src/superio/ite/it8587e/superio.c
new file mode 100644
index 0000000..cdb97e6
--- /dev/null
+++ b/src/superio/ite/it8587e/superio.c
@@ -0,0 +1,72 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de>
+ * Copyright (C) 2007 Philipp Degler <pdegler(a)rumms.uni-mannheim.de>
+ * Copyright (C) 2017 Gergely Kiss <mail.gery(a)gmail.com>
+ * Copyright (C) 2019 9Elements GmbH <patrick.rudolph(a)9elements.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/device.h>
+#include <device/pnp.h>
+#include <stdlib.h>
+#include <superio/conf_mode.h>
+
+#include "it8587e.h"
+
+static void it8587e_init(struct device *dev)
+{
+}
+
+static struct device_operations ops = {
+ .read_resources = pnp_read_resources,
+ .set_resources = pnp_set_resources,
+ .enable_resources = pnp_enable_resources,
+ .enable = pnp_alt_enable,
+ .init = it8587e_init,
+ .ops_pnp_mode = &pnp_conf_mode_870155_aa,
+};
+
+static struct pnp_info pnp_dev_info[] = {
+ { NULL, IT8587E_SP1, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
+ { NULL, IT8587E_SP2, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
+ { NULL, IT8587E_SWUC, PNP_IO0 | PNP_IRQ0, 0xfff0, },
+ /* Documentation: Unused */
+ { NULL, IT8587E_KBCM, PNP_IRQ0, },
+ /* Documentation: Program io0 = 0x60 and io1 = 0x64 */
+ { NULL, IT8587E_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff, },
+ { NULL, IT8587E_SMFI, PNP_IO0 | PNP_IRQ0, 0xfff0, },
+ /* Documentation: Program io0 = 0x70-0x73 */
+ { NULL, IT8587E_RTCT, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IO3 | PNP_IRQ0,
+ 0xfffe, 0xfffe, 0xfffe, 0xfffe},
+ /* Documentation: Program io0 = 0x62 and io1 = 0x66 */
+ { NULL, IT8587E_PMC1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff },
+ /* Documentation: Program io0 = 0x68 and io1 = 0x6c */
+ { NULL, IT8587E_PMC2, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07fc, 0x07fc },
+ /* Documentation: Program io0 = 0x6a and io1 = 0x6e */
+ { NULL, IT8587E_PMC3, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff },
+ { NULL, IT8587E_PMC4, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff },
+ { NULL, IT8587E_PMC5, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff },
+ { NULL, IT8587E_SSPI, PNP_IO0 | PNP_IRQ0, 0xfff8 },
+ { NULL, IT8528E_PECI, PNP_IO0, 0xfff8 },
+};
+
+static void enable_dev(struct device *dev)
+{
+ pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
+}
+
+struct chip_operations superio_ite_it8587e_ops = {
+ CHIP_NAME("ITE IT8587E Super I/O")
+ .enable_dev = enable_dev,
+};
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I1e541daa2b3d48a4f5a0e7b7fa88a2c2f8a1b0c5
Gerrit-Change-Number: 36071
Gerrit-PatchSet: 1
Gerrit-Owner: Daniel Maslowski <info(a)orangecms.org>
Gerrit-Reviewer: Daniel Maslowski <info(a)orangecms.org>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-MessageType: newchange
Daniel Maslowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36010 )
Change subject: Documentation: add Gigabyte P34G v2
......................................................................
Documentation: add Gigabyte P34G v2
Change-Id: Ie8025f7bf4e7b40810c97a0b5fa80fd7c41e97eb
Signed-off-by: Daniel Maslowski <info(a)orangecms.org>
---
A Documentation/mainboard/gigabyte/p34g-v2.md
A Documentation/mainboard/gigabyte/p34g-v2_tpm_socket_spi_chip.jpg
M Documentation/mainboard/index.md
3 files changed, 89 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/36010/1
diff --git a/Documentation/mainboard/gigabyte/p34g-v2.md b/Documentation/mainboard/gigabyte/p34g-v2.md
new file mode 100644
index 0000000..4dfcf79
--- /dev/null
+++ b/Documentation/mainboard/gigabyte/p34g-v2.md
@@ -0,0 +1,88 @@
+# Gigabyte P34G v2
+
+This page describes how to run coreboot on the [Gigabyte P34G v2 gaming
+laptop](https://www.gigabyte.com/Laptop/P34G-v2).
+
+Original board name: GA-R3456R
+
+Rebrands:
+- Schenker XMG C404
+
+## Technology
+
+```eval_rst
++------------------+----------------------------------------------+
+| Northbridge | :doc:`../../northbridge/intel/haswell/index` |
++------------------+----------------------------------------------+
+| Southbridge | Lynx Point |
++------------------+----------------------------------------------+
+| CPU | i7-4710HQ |
++------------------+----------------------------------------------+
+| EC / SuperIO | ITE IT8587E |
++------------------+----------------------------------------------+
+| Coprocessor | Intel ME, `me_cleaner` untested |
++------------------+----------------------------------------------+
+| TPM | None, but socket exists (see photo below) |
++------------------+----------------------------------------------+
+```
+
+## Required proprietary blobs
+
+```eval_rst
+Please see :doc:`../../northbridge/intel/haswell/mrc.bin`.
+```
+
+## Flash chip
+
+
+
+```eval_rst
++---------------------+------------+
+| Type | Value |
++=====================+============+
+| Socketed flash | No |
++---------------------+------------+
+| Model | MX25L6406E |
++---------------------+------------+
+| Size | 8 MiB |
++---------------------+------------+
+| In circuit flashing | Yes |
++---------------------+------------+
+| Package | SOIC-8 |
++---------------------+------------+
+| Write protection | No |
++---------------------+------------+
+| Internal flashing | Untested |
++---------------------+------------+
+```
+
+## Flash layout
+
+```txt
+00000000:00000fff fd
+00400000:007fffff bios
+00001000:003fffff me
+```
+
+## EC firmware
+
+There is an additional 128KiB EC firmware blob within the BIOS region at
+`0x700000`. The EC has its own internal EPROM though, for which Gigabyte offers
+updates in a bundle with the UEFI firmware updates based on AMI Aptio. The EC
+firmware can be updated via AFU. An unmodified EC firmware version F005 seems
+to work fine with coreboot even without the extra 128KiB part. It could be
+extracted from a firmware update through `dd` etc and reinserted though. Other
+version have not been tested.
+
+## Known issues
+
+- EC / ACPI
+ * no suspend on LID close
+ * eject, sleep, backlight up/down, external screen buttons do not work
+ * Bluetooth LED shows inverted state, does not turn on on first press
+ * battery state can not be queried
+- CPU overheats on high load leading to force poweroff
+
+```eval_rst
+Please also see :doc:`../../northbridge/intel/haswell/known-issues`.
+```
diff --git a/Documentation/mainboard/gigabyte/p34g-v2_tpm_socket_spi_chip.jpg b/Documentation/mainboard/gigabyte/p34g-v2_tpm_socket_spi_chip.jpg
new file mode 100644
index 0000000..9835a8a
--- /dev/null
+++ b/Documentation/mainboard/gigabyte/p34g-v2_tpm_socket_spi_chip.jpg
Binary files differ
diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
index 83189757..f0f8f8e 100644
--- a/Documentation/mainboard/index.md
+++ b/Documentation/mainboard/index.md
@@ -40,6 +40,7 @@
## Gigabyte
- [GA-H61M-S2PV](gigabyte/ga-h61m-s2pv.md)
+- [P34G v2](gigabyte/p34g-v2.md)
## Google
--
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