coreboot-gerrit January 2022

coreboot-gerrit@coreboot.org

1 participants
6084 discussions

Change in coreboot[master]: Herobrine T32 scripts working in standalone environment
by Ravi kumar (Code Review) 26 Sep '22

26 Sep '22

Hello mturney mturney, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/47365 to review the following change. Change subject: Herobrine T32 scripts working in standalone environment ...................................................................... Herobrine T32 scripts working in standalone environment Change-Id: I451344d887c7b6c0983594e4dea4ca2b030d65f1 --- M util/qualcomm/scripts/cmm/debug_cb_common.cmm A util/qualcomm/scripts/cmm/debug_cb_herobrine.cmm 2 files changed, 123 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/47365/1 diff --git a/util/qualcomm/scripts/cmm/debug_cb_common.cmm b/util/qualcomm/scripts/cmm/debug_cb_common.cmm index cbcb004..a722864 100644 --- a/util/qualcomm/scripts/cmm/debug_cb_common.cmm +++ b/util/qualcomm/scripts/cmm/debug_cb_common.cmm @@ -126,6 +126,11 @@ else d.load.elf &imgpath /strippart "coreboot" /sourcepath &srcpath /nocode + print "Hacking DDR ranges..." + B::D.S MD:0x1485B000 %LE %Long 0x80000000 + B::D.S MD:0x1485B004 %LE %Long 0 + B::D.S MD:0x1485B008 %LE %Long 0x80000000 + print %String "Now the control is in ROMStage, press enter after debugging to go to next stage" print %String "Press enter to go to next stage" enter diff --git a/util/qualcomm/scripts/cmm/debug_cb_herobrine.cmm b/util/qualcomm/scripts/cmm/debug_cb_herobrine.cmm new file mode 100644 index 0000000..8693a5f --- /dev/null +++ b/util/qualcomm/scripts/cmm/debug_cb_herobrine.cmm @@ -0,0 +1,118 @@ +;============================================================================ +;## SPDX-License-Identifier: GPL-2.0-only +;============================================================================ +; Name: +; debug_cb_trogdor.cmm +; +; Description: +; Debug coreboot trogdor front-end +;============================================================================ + +;============================================================================ +; CMM script variables +;============================================================================ + +LOCAL &TargetPkg + +GLOBAL &BBEntryAddr // Bootblock Entry +GLOBAL &BBExitAddr // Bootblock Exit to Xbl-Sec +GLOBAL &VEREntryAddr // Verstage Entry +GLOBAL &ROMEntryAddr // Romstage Entry +GLOBAL &QCLEntryAddr // QCLstage Entry +GLOBAL &RAMEntryAddr // Ramstage Entry +GLOBAL &BL31EntryAddr // BL31 Entry +GLOBAL &DCEntryAddr // Depthcharge Entry + +GLOBAL &PreRamConsoleAddr +GLOBAL &RamConsoleAddr +GLOBAL &PreRamCbfsCache +GLOBAL &VBoot2Work +GLOBAL &Stack +GLOBAL &Ttb +GLOBAL &Timestamp +GLOBAL &CbmemTop +GLOBAL &PostRamCbfsCache + +GLOBAL &CBTablePtr + +;============================================================================ + +;--------------------------------------------------- +; Entry point +;--------------------------------------------------- +ENTRY &ImageName &RegAddress + + // Later these can be parameterized + &TargetPkg="herobrinePkg" + + // These settings come from .../src/soc/qualcomm/sc7280/memlayout.ld + &BBEntryAddr=0x14819000 + &VEREntryAddr=0x14680000 + &ROMEntryAddr=0x14680000 + &QCLEntryAddr=0x1486c950 + &RAMEntryAddr=0xA0800000 + &BL31EntryAddr=0x80C00000 + &DCEntryAddr=0xF1000000 + &KernelEntryAddr=0xD0000000 + + &PreRamConsoleAddr=0x14834800 + &VBoot2Work=0x1484F000 + &Stack=0x1484B000 + &Ttb=0x1483D000 + &Timestamp=0x1483C800 + &PreRamCbfsCache=0x14823000 + &CbmemTop=0x280000000 + &PostRamCbfsCache=0x9F800000 + // End of memlayout.ld settings + + // Common commands irrespective of &Mode + PATH + &CwDir=os.pwd() + PATH + &CwDir + + // position at top of coreboot tree + // find depth count for source loading + cd ..\..\..\.. + &srcpath=os.pwd() + + +;--------------------------------------------------- +; Setup area and log +;--------------------------------------------------- + area.clear + area.reset + area.create CB_Logs 1000. 8192. + area.select CB_Logs + + area.view CB_Logs + + PRINT %String "Source Path: &srcpath" + + symbol.sourcepath.setbasedir &srcpath\src + + // Make parsing simple, upper-case parameters + &ImageName=STRING.UPR("&ImageName") + if (STR.CP("&ImageName","0X*")) + ( + &RegAddress=&ImageName + &ImageName="" + ) + &RegAddress=STRING.UPR("&RegAddress") + + PRINT %String "ImageName: &ImageName" + PRINT %String "RegAddress: &RegAddress" + + ;sys.d + ;sys.up + b.d + y.reset + + if (STR.CP("&RegAddress","0X*")) + D.S EZAXI:&RegAddress %LE %Long 0x80000000 + + go &BBEntryAddr + wait !run() + + DO debug_cb_common.cmm &TargetPkg &srcpath &xblsrcpath &ImageName + + enddo -- To view, visit https://review.coreboot.org/c/coreboot/+/47365 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I451344d887c7b6c0983594e4dea4ca2b030d65f1 Gerrit-Change-Number: 47365 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newchange

5 40

Change in coreboot[master]: AMD good IRQs: scripts for applying the unofficial (not-merged-yet) p...
by Mike Banon (Code Review) 23 Sep '22

23 Sep '22

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48427 ) Change subject: AMD good IRQs: scripts for applying the unofficial (not-merged-yet) patches ...................................................................... AMD good IRQs: scripts for applying the unofficial (not-merged-yet) patches These scripts will help you to securely and conveniently apply seven changes for improving the IRQ routing on these AMD boards: 1) CB:48161, CB:48162, CB:48163, CB:48179 - for AMD Lenovo G505S; 2) CB:48424, CB:48425, CB:48426 - for ASUS A88XM-E; 3) Not ready yet - for ASUS AM1I-A. Save to ./coreboot/ then run ./get_irq_patches.sh , ./check... and ./apply... Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I04869ae24185eef5399c3fd9b8d4965ec4e33a19 --- A apply_irq_patches.sh A check_irq_patches.sh A get_irq_patches.sh A sha256sums_irq_correct.txt 4 files changed, 113 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/48427/1 diff --git a/apply_irq_patches.sh b/apply_irq_patches.sh new file mode 100755 index 0000000..8fc5318 --- /dev/null +++ b/apply_irq_patches.sh @@ -0,0 +1,37 @@ +#!/bin/sh +### +### https://review.coreboot.org/c/coreboot/+/48161 +### lenovo/g505s: properly program the IRQ tables +### +patch -p1 < "./cd096f9.diff" +### +### https://review.coreboot.org/c/coreboot/+/48162 +### lenovo/g505s: update the ACPI routing to match the new IRQ routing +### +patch -p1 < "./42aeed4.diff" +### +### https://review.coreboot.org/c/coreboot/+/48163 +### lenovo/g505s: add the PIRQ routing table +### +patch -p1 < "./c6ab05e.diff" +### +### https://review.coreboot.org/c/coreboot/+/48179 +### lenovo/g505s: enable the webcam [WIP] +### +patch -p1 < "./8517e5a.diff" +### +### https://review.coreboot.org/c/coreboot/+/48424 +### asus/a88xm-e: properly program the IRQ tables +### +patch -p1 < "./cfc8288.diff" +### +### https://review.coreboot.org/c/coreboot/+/48425 +### asus/a88xm-e: update the ACPI routing to match the new IRQ routing +### +patch -p1 < "./489e510.diff" +### +### https://review.coreboot.org/c/coreboot/+/48426 +### asus/a88xm-e: add the PIRQ routing table +### +patch -p1 < "./08638df.diff" +### diff --git a/check_irq_patches.sh b/check_irq_patches.sh new file mode 100755 index 0000000..3a2bb16 --- /dev/null +++ b/check_irq_patches.sh @@ -0,0 +1,18 @@ +#!/bin/sh +rm -f "./sha256sums_irq_my.txt" +sha256sum "./cd096f9.diff" > "./sha256sums_irq_my.txt" +sha256sum "./42aeed4.diff" >> "./sha256sums_irq_my.txt" +sha256sum "./c6ab05e.diff" >> "./sha256sums_irq_my.txt" +sha256sum "./8517e5a.diff" >> "./sha256sums_irq_my.txt" +sha256sum "./cfc8288.diff" >> "./sha256sums_irq_my.txt" +sha256sum "./489e510.diff" >> "./sha256sums_irq_my.txt" +sha256sum "./08638df.diff" >> "./sha256sums_irq_my.txt" +if cmp -s "./sha256sums_irq_my.txt" "./sha256sums_irq_correct.txt" +then + echo "SHA256 checksums are correct, please run ./apply_irq_patches.sh" + exit 0 +else + echo "! MISMATCH ! See ./sha256sums_irq_my.txt and ./sha256sums_irq_correct.txt" + exit 1 +fi +# diff --git a/get_irq_patches.sh b/get_irq_patches.sh new file mode 100755 index 0000000..97da6b5 --- /dev/null +++ b/get_irq_patches.sh @@ -0,0 +1,51 @@ +#!/bin/sh +### +### https://review.coreboot.org/c/coreboot/+/48161 +### lenovo/g505s: properly program the IRQ tables +### +rm -f "./cd096f9.diff" +wget "https://review.coreboot.org/changes/48161/revisions/1/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./cd096f9.diff" +### +### https://review.coreboot.org/c/coreboot/+/48162 +### lenovo/g505s: update the ACPI routing to match the new IRQ routing +### +rm -f "./42aeed4.diff" +wget "https://review.coreboot.org/changes/48162/revisions/1/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./42aeed4.diff" +### +### https://review.coreboot.org/c/coreboot/+/48163 +### lenovo/g505s: add the PIRQ routing table +### +rm -f "./c6ab05e.diff" +wget "https://review.coreboot.org/changes/48163/revisions/3/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./c6ab05e.diff" +### +### https://review.coreboot.org/c/coreboot/+/48179 +### lenovo/g505s: enable the webcam [WIP] +### +rm -f "./8517e5a.diff" +wget "https://review.coreboot.org/changes/48179/revisions/1/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./8517e5a.diff" +### +### https://review.coreboot.org/c/coreboot/+/48424 +### asus/a88xm-e: properly program the IRQ tables +### +rm -f "./cfc8288.diff" +wget "https://review.coreboot.org/changes/48424/revisions/1/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./cfc8288.diff" +### +### https://review.coreboot.org/c/coreboot/+/48425 +### asus/a88xm-e: update the ACPI routing to match the new IRQ routing +### +rm -f "./489e510.diff" +wget "https://review.coreboot.org/changes/48425/revisions/1/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./489e510.diff" +### +### https://review.coreboot.org/c/coreboot/+/48426 +### asus/a88xm-e: add the PIRQ routing table +### +rm -f "./08638df.diff" +wget "https://review.coreboot.org/changes/48426/revisions/1/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./08638df.diff" +### diff --git a/sha256sums_irq_correct.txt b/sha256sums_irq_correct.txt new file mode 100755 index 0000000..a06b640 --- /dev/null +++ b/sha256sums_irq_correct.txt @@ -0,0 +1,7 @@ +9fd4cca063bb6e6c9063f00f4c972c019d616560883b9bda76177a462817ae8e ./cd096f9.diff +357a1e1e9f250149127fa8f7aac089e481a39f96b313ae1a0310c7e5d22faa72 ./42aeed4.diff +e350591056f1a10b5922cc7180a07e1142f14fe8af41f6c545317a37c12880ed ./c6ab05e.diff +ab0b347af164e5c50c580f036e7ed55757e90158ad3cb04fc2f8154b5392f804 ./8517e5a.diff +358c3a5fcce7085ca49154370c21cd95396fa8fa9d0b30e1de8625fe1db0f36d ./cfc8288.diff +669bd10d74229f3e2200a9e206fad49326928348a6ad3f261f14ebe920b63c56 ./489e510.diff +fab791e93eb63b880d2692eff527979051dadcf504018f58346c6f0c4c6173b6 ./08638df.diff -- To view, visit https://review.coreboot.org/c/coreboot/+/48427 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I04869ae24185eef5399c3fd9b8d4965ec4e33a19 Gerrit-Change-Number: 48427 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

2 10

Change in coreboot[master]: arch/x86: Don't use .bss from car.ld if not running XIP
by Arthur Heymans (Code Review) 21 Sep '22

21 Sep '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48156 ) Change subject: arch/x86: Don't use .bss from car.ld if not running XIP ...................................................................... arch/x86: Don't use .bss from car.ld if not running XIP Some platform run early stages like romstage and verstage from CAR instead of XIP. This allows to link them like other arch inside the _program region. Change-Id: I6cf51f943dde5f642d75ba4c5d3be520dc56370a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/assembly_entry.S M src/arch/x86/car.ld M src/include/rules.h M src/lib/program.ld 4 files changed, 12 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/48156/1 diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S index 31670c2..7d7d3fc 100644 --- a/src/arch/x86/assembly_entry.S +++ b/src/arch/x86/assembly_entry.S @@ -36,6 +36,7 @@ mov $_STACK_TOP, %esp /* clear .bss section as it is not shared */ +#if ENV_STAGE_XIP cld xor %eax, %eax movl $(_ebss), %ecx @@ -43,6 +44,7 @@ sub %edi, %ecx shrl $2, %ecx rep stosl +#endif #if ((ENV_SEPARATE_VERSTAGE && CONFIG(VERSTAGE_DEBUG_SPINLOOP)) \ || (ENV_ROMSTAGE && CONFIG(ROMSTAGE_DEBUG_SPINLOOP))) diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index c291efb..38128d1 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -62,6 +62,7 @@ * cbmem console. This is useful for clearing this area on a per-stage * basis when more than one stage uses cache-as-ram. */ +#if ENV_STAGE_HAS_CAR_XIP_BSS . = ALIGN(ARCH_POINTER_ALIGN_SIZE); _bss = .; /* Allow global uninitialized variables for stages without CAR teardown. */ @@ -71,6 +72,7 @@ *(.sbss.*) . = ALIGN(ARCH_POINTER_ALIGN_SIZE); _ebss = .; +#endif #if ENV_ROMSTAGE && CONFIG(ASAN_IN_ROMSTAGE) _shadow_size = (_ebss - _car_region_start) >> 3; diff --git a/src/include/rules.h b/src/include/rules.h index 6ebb37e..f503914 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -261,14 +261,21 @@ #if ENV_X86 /* Indicates memory layout is determined with arch/x86/car.ld. */ #define ENV_CACHE_AS_RAM (ENV_ROMSTAGE_OR_BEFORE && !CONFIG(RESET_VECTOR_IN_RAM)) +/* Indicates if the stage runs XIP. */ +#define ENV_STAGE_XIP (ENV_CACHE_AS_RAM && \ + !((ENV_ROMSTAGE || ENV_SEPARATE_VERSTAGE) && CONFIG(NO_XIP_EARLY_STAGES))) /* No .data sections with execute-in-place from ROM. */ #define ENV_STAGE_HAS_DATA_SECTION !ENV_CACHE_AS_RAM #else /* Both .data and .bss, sometimes SRAM not DRAM. */ #define ENV_STAGE_HAS_DATA_SECTION 1 #define ENV_CACHE_AS_RAM 0 +#define ENV_STAGE_XIP 0 #endif +/* Indicates if the stages uses the _bss region defined in arch/x86/car.ld */ +#define ENV_STAGE_HAS_CAR_XIP_BSS ENV_STAGE_XIP + /* Currently rmodules, ramstage and smm have heap. */ #define ENV_STAGE_HAS_HEAP_SECTION (ENV_RMODULE || ENV_RAMSTAGE || ENV_SMM) diff --git a/src/lib/program.ld b/src/lib/program.ld index 3b6aa2e..ff3c672 100644 --- a/src/lib/program.ld +++ b/src/lib/program.ld @@ -103,7 +103,7 @@ } #endif -#if !ENV_CACHE_AS_RAM +#if !ENV_STAGE_HAS_CAR_XIP_BSS .bss . : { . = ALIGN(ARCH_POINTER_ALIGN_SIZE); _bss = .; -- To view, visit https://review.coreboot.org/c/coreboot/+/48156 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cf51f943dde5f642d75ba4c5d3be520dc56370a Gerrit-Change-Number: 48156 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

6 28

Change in coreboot[master]: include/rules.h: Allow .data section on non-XIP stages
by Arthur Heymans (Code Review) 21 Sep '22

21 Sep '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48157 ) Change subject: include/rules.h: Allow .data section on non-XIP stages ...................................................................... include/rules.h: Allow .data section on non-XIP stages This allows platform that don't run stage XIP to have a .data section. Change-Id: I40a651398dff374bf6ba75471b07662de96fb434 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/include/rules.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/48157/1 diff --git a/src/include/rules.h b/src/include/rules.h index f503914..a7fc77f 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -265,7 +265,7 @@ #define ENV_STAGE_XIP (ENV_CACHE_AS_RAM && \ !((ENV_ROMSTAGE || ENV_SEPARATE_VERSTAGE) && CONFIG(NO_XIP_EARLY_STAGES))) /* No .data sections with execute-in-place from ROM. */ -#define ENV_STAGE_HAS_DATA_SECTION !ENV_CACHE_AS_RAM +#define ENV_STAGE_HAS_DATA_SECTION !ENV_STAGE_XIP #else /* Both .data and .bss, sometimes SRAM not DRAM. */ #define ENV_STAGE_HAS_DATA_SECTION 1 -- To view, visit https://review.coreboot.org/c/coreboot/+/48157 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40a651398dff374bf6ba75471b07662de96fb434 Gerrit-Change-Number: 48157 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: Kconfig: Allow x86 to compress pre-ram stages if not run XIP
by Arthur Heymans (Code Review) 20 Sep '22

20 Sep '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36613 ) Change subject: Kconfig: Allow x86 to compress pre-ram stages if not run XIP ...................................................................... Kconfig: Allow x86 to compress pre-ram stages if not run XIP Change-Id: Iac24d243c4bd4cb8c1db14a8e9fc43f508c2cd5d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/Kconfig M src/arch/x86/Makefile.inc 2 files changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/36613/1 diff --git a/src/Kconfig b/src/Kconfig index 793927a..df86246 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -160,7 +160,7 @@ config COMPRESS_PRERAM_STAGES bool "Compress romstage and verstage with LZ4" - depends on !ARCH_X86 && (HAVE_ROMSTAGE || HAVE_VERSTAGE) + depends on HAVE_ROMSTAGE || HAVE_VERSTAGE # Default value set at the end of the file help Compress romstage and (if it exists) verstage with LZ4 to save flash @@ -1217,7 +1217,7 @@ default y if !UNCOMPRESSED_RAMSTAGE config COMPRESS_PRERAM_STAGES - depends on !ARCH_X86 + depends on NO_XIP_EARLY_STAGES default y config INCLUDE_CONFIG_FILE diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 447fd57..db4f054 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -119,6 +119,7 @@ ifeq ($(CONFIG_C_ENVIRONMENT_BOOTBLOCK),y) bootblock-y += bootblock_crt0.S +bootblock-y += memmove.c ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32),y) $(eval $(call early_x86_stage,bootblock,elf32-i386)) -- To view, visit https://review.coreboot.org/c/coreboot/+/36613 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac24d243c4bd4cb8c1db14a8e9fc43f508c2cd5d Gerrit-Change-Number: 36613 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

8 21

Change in coreboot[master]: soc/intel/apollolake: LZ4 Compress FSP-M
by Arthur Heymans (Code Review) 20 Sep '22

20 Sep '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48158 ) Change subject: soc/intel/apollolake: LZ4 Compress FSP-M ...................................................................... soc/intel/apollolake: LZ4 Compress FSP-M FSP-M is not run XIP so it can be compressed. This more than halves the binary size. 364544 bytes -> 168616 bytes. On the up/squared this also results in a 83ms speedup. TESTED: up/squared boots. Change-Id: Ic76b51f0f3007b59ccb9f76b6a57bb9265dab833 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/apollolake/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/48158/1 diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 4f762a9..bf7cd0b 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -46,6 +46,7 @@ select MRC_SETTINGS_PROTECT select MRC_SETTINGS_VARIABLE_DATA select NO_XIP_EARLY_STAGES + select FSP_COMPRESS_FSP_M_LZ4 select PARALLEL_MP select PARALLEL_MP_AP_WORK select PCIEXP_ASPM -- To view, visit https://review.coreboot.org/c/coreboot/+/48158 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic76b51f0f3007b59ccb9f76b6a57bb9265dab833 Gerrit-Change-Number: 48158 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

8 12

Change in coreboot[master]: arch/x86: Add option to compress postcar stage
by Arthur Heymans (Code Review) 19 Sep '22

19 Sep '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36674 ) Change subject: arch/x86: Add option to compress postcar stage ...................................................................... arch/x86: Add option to compress postcar stage The LZ4 decompressor was already linked in romstage. Change-Id: I89fdc6066027447bf72968c66e6f5eb5fbb630c7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/Kconfig M src/arch/x86/Makefile.inc 2 files changed, 19 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/36674/1 diff --git a/src/Kconfig b/src/Kconfig index 0d56291..17bf545 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -158,6 +158,16 @@ that decompression might slow down booting if the boot flash is connected through a slow link (i.e. SPI). +config COMPRESS_POSTCAR + bool "Compress postcar with LZ4" + depends on POSTCAR_STAGE + # Default value set at the end of the file + help + Compress postcar with LZ4 to save flash space and speed up boot, + since the time for reading the image from SPI (and in the vboot + case verifying it) is usually much greater than the time spent + decompressing. + config COMPRESS_PRERAM_STAGES bool "Compress romstage and verstage with LZ4" depends on !ARCH_X86 && (HAVE_ROMSTAGE || HAVE_VERSTAGE) @@ -1203,6 +1213,9 @@ config COMPRESS_RAMSTAGE default y if !UNCOMPRESSED_RAMSTAGE +config COMPRESS_POSTCAR + default y + config COMPRESS_PRERAM_STAGES depends on !ARCH_X86 default y diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 447fd57..8c35176 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -278,11 +278,16 @@ $(objcbfs)/postcar.elf: $(objcbfs)/postcar.debug.rmod cp $< $@ +CBFS_POSTCAR_COMPRESS_FLAG := none +ifeq ($(CONFIG_COMPRESS_POSTCAR),y) +CBFS_POSTCAR_COMPRESS_FLAG := lz4 +endif + # Add postcar to CBFS cbfs-files-$(CONFIG_POSTCAR_STAGE) += $(CONFIG_CBFS_PREFIX)/postcar $(CONFIG_CBFS_PREFIX)/postcar-file := $(objcbfs)/postcar.elf $(CONFIG_CBFS_PREFIX)/postcar-type := stage -$(CONFIG_CBFS_PREFIX)/postcar-compression := none +$(CONFIG_CBFS_PREFIX)/postcar-compression := $(CBFS_POSTCAR_COMPRESS_FLAG) ############################################################################### # ramstage -- To view, visit https://review.coreboot.org/c/coreboot/+/36674 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I89fdc6066027447bf72968c66e6f5eb5fbb630c7 Gerrit-Change-Number: 36674 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

8 20

Change in coreboot[master]: [WIP]cpu/x86/cache: CLFLUSH programs to memory before running
by Arthur Heymans (Code Review) 19 Sep '22

19 Sep '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37196 ) Change subject: [WIP]cpu/x86/cache: CLFLUSH programs to memory before running ...................................................................... [WIP]cpu/x86/cache: CLFLUSH programs to memory before running When cbmem is initialized in romstage and postcar placed in the stage cache + cbmem where it is run, the assumption is made that this are all in UC memory such that calling invd in postcar is ok. For performance reasons (e.g. postcar decompression) it is desirable to cache cbmem and the stage cache during romstage. Another reason is that AGESA sets up MTRR during romstage to cache all dram, which is currently worked around by using additional MTRR to make that UC. TODO be nice to reviewers and spit some parts off. UNTESTED Change-Id: I7ff2a57aee620908b71829457ea0f5a0c410ec5b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/postcar_loader.c M src/cpu/x86/cache/Makefile.inc M src/cpu/x86/cache/cache.c M src/include/cpu/x86/cache.h 4 files changed, 68 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/37196/1 diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index b53cbf8..53ab4f9 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -208,6 +208,21 @@ MTRR_TYPE_WRBACK); } +/* + * POSTCAR will call invd so don't make assumptions on cbmem + * and external stage cache being UC. + */ +static void postcar_flush_cache(void) +{ + uintptr_t stage_cache_base; + size_t stage_cache_size; + prog_segment_loaded((uintptr_t)cbmem_top(), cbmem_overhead_size(), SEG_FINAL); + if (CONFIG(TSEG_STAGE_CACHE)) { + stage_cache_external_region((void **)&stage_cache_base, &stage_cache_size); + prog_segment_loaded(stage_cache_base, stage_cache_size, SEG_FINAL); + } +} + void run_postcar_phase(struct postcar_frame *pcf) { struct prog prog = @@ -222,8 +237,10 @@ parameters between S3 resume and normal boot. On the platforms where the values are the same it's a nop. */ finalize_load(prog.arg, pcf->stack); - } else + } else { load_postcar_cbfs(&prog, pcf); + postcar_flush_cache(); + } /* As postcar exist, it's end of romstage here */ timestamp_add_now(TS_END_ROMSTAGE); diff --git a/src/cpu/x86/cache/Makefile.inc b/src/cpu/x86/cache/Makefile.inc index b33b9ee..759488e 100644 --- a/src/cpu/x86/cache/Makefile.inc +++ b/src/cpu/x86/cache/Makefile.inc @@ -1 +1,2 @@ +romstage-y += cache.c ramstage-y += cache.c diff --git a/src/cpu/x86/cache/cache.c b/src/cpu/x86/cache/cache.c index 2313c4d..ac2c45b 100644 --- a/src/cpu/x86/cache/cache.c +++ b/src/cpu/x86/cache/cache.c @@ -11,8 +11,11 @@ * GNU General Public License for more details. */ +#include <cbmem.h> +#include <program_loading.h> #include <console/console.h> #include <cpu/x86/cache.h> +#include <arch/cpu.h> void x86_enable_cache(void) { @@ -20,3 +23,47 @@ printk(BIOS_INFO, "Enabling cache\n"); enable_cache(); } + +int clflush_supported(void) +{ + return (cpuid_edx(1) >> 19) & 1; +} + +static void clflush_region(uintptr_t start, size_t size) +{ + uintptr_t addr; + size_t cl_size = (cpuid_ebx(1) >> 8) & 0xff; + if (!clflush_supported()) + return; + for (addr = (start / cl_size) * cl_size; addr < start + size; addr += cl_size) + clflush((void *)addr); +} + +static int dram_ready; + +/* + * For each segment of a program loaded this function is called + * to invalidate caches for the addresses of the loaded segment + */ +void arch_segment_loaded(uintptr_t start, size_t size, int flags) +{ + /* INVD is only called in postcar stage so we only need + to make sure that our things hit dram during romstage. */ + if (!ENV_ROMSTAGE) + return; + if (flags != SEG_FINAL) + return; + if (!dram_ready) + return; + + if (!clflush_supported()) + printk(BIOS_DEBUG, "Not flushing cache to ram, CLFLUSH not supported\n"); + clflush_region(start, size); +} + +static void set_dram_ready(int unused) +{ + dram_ready = 1; +} + +ROMSTAGE_CBMEM_INIT_HOOK(set_dram_ready); diff --git a/src/include/cpu/x86/cache.h b/src/include/cpu/x86/cache.h index 713ca32..2d2727f 100644 --- a/src/include/cpu/x86/cache.h +++ b/src/include/cpu/x86/cache.h @@ -55,6 +55,8 @@ asm volatile ("clflush (%0)"::"r" (addr)); } +int clflush_supported(void); + /* The following functions require the __always_inline due to AMD * function STOP_CAR_AND_CPU that disables cache as * RAM, the cache as RAM stack can no longer be used. Called -- To view, visit https://review.coreboot.org/c/coreboot/+/37196 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ff2a57aee620908b71829457ea0f5a0c410ec5b Gerrit-Change-Number: 37196 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

6 22

Change in coreboot[master]: cpu/intel/haswell: add Crystal Well CPU IDs
by Iru Cai (vimacs) (Code Review) 11 Sep '22

11 Sep '22

Hello Iru Cai, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44066 to review the following change. Change subject: cpu/intel/haswell: add Crystal Well CPU IDs ...................................................................... cpu/intel/haswell: add Crystal Well CPU IDs Change-Id: Ife4ae71fd977d32d7b11ee7e2a1a7e2ec3eec52f Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- M src/cpu/intel/haswell/haswell_init.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/44066/1 diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index e621638..5f3debb 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -778,6 +778,8 @@ { X86_VENDOR_INTEL, 0x306c3 }, /* Intel Haswell C0 */ { X86_VENDOR_INTEL, 0x40650 }, /* Intel Haswell ULT B0 */ { X86_VENDOR_INTEL, 0x40651 }, /* Intel Haswell ULT B1 */ + { X86_VENDOR_INTEL, 0x40660 }, /* Intel Crystal Well C0 */ + { X86_VENDOR_INTEL, 0x40661 }, /* Intel Crystal Well C1 */ { 0, 0 }, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/44066 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife4ae71fd977d32d7b11ee7e2a1a7e2ec3eec52f Gerrit-Change-Number: 44066 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: cpu/intel/haswell: Add Broadwell CPUIDs and microcode
by Angel Pons (Code Review) 11 Sep '22

11 Sep '22

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46942 ) Change subject: cpu/intel/haswell: Add Broadwell CPUIDs and microcode ...................................................................... cpu/intel/haswell: Add Broadwell CPUIDs and microcode Broadwell can now use the Haswell CPU driver. Change-Id: I36138cab72b1e3ad0ff7f6434996f5ce00de9d0d Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/haswell/Makefile.inc M src/cpu/intel/haswell/haswell_init.c 2 files changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/46942/1 diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index b93b911..3c4db4f 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -23,3 +23,7 @@ cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-3c-*) cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-45-*) + +ifeq ($(CONFIG_SOC_INTEL_BROADWELL),y) +cpu_microcode_bins += 3rdparty/blobs/soc/intel/broadwell/microcode.bin +endif diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 04f5802..577061c 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -728,6 +728,10 @@ { X86_VENDOR_INTEL, CPUID_HASWELL_ULT_C0 }, { X86_VENDOR_INTEL, CPUID_CRYSTALWELL_B0 }, { X86_VENDOR_INTEL, CPUID_CRYSTALWELL_C0 }, + { X86_VENDOR_INTEL, CPUID_BROADWELL_C0 }, + { X86_VENDOR_INTEL, CPUID_BROADWELL_ULT_C0 }, + { X86_VENDOR_INTEL, CPUID_BROADWELL_ULT_D0 }, + { X86_VENDOR_INTEL, CPUID_BROADWELL_ULT_E0 }, { 0, 0 }, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/46942 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36138cab72b1e3ad0ff7f6434996f5ce00de9d0d Gerrit-Change-Number: 46942 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 6

Jump to page:

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit January 2022