coreboot-gerrit January 2022

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Change in coreboot[master]: [UNTESTED]drivers/amd/agesa/s3_mtrr.c: Use a struct over pointer arit...

by Arthur Heymans (Code Review)

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44293 ) Change subject: [UNTESTED]drivers/amd/agesa/s3_mtrr.c: Use a struct over pointer aritmetic ...................................................................... [UNTESTED]drivers/amd/agesa/s3_mtrr.c: Use a struct over pointer aritmetic The size of the data used is fixed in this function so there is no need for this aritmetic. The function signature will be changed in a followup commit. Change-Id: I3c6df8951d39695cddd4635360d6407d4d001b0a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/amd/agesa/s3_mtrr.c 1 file changed, 53 insertions(+), 85 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/44293/1 diff --git a/src/drivers/amd/agesa/s3_mtrr.c b/src/drivers/amd/agesa/s3_mtrr.c index 6c7ba5f..672eb20 100644 --- a/src/drivers/amd/agesa/s3_mtrr.c +++ b/src/drivers/amd/agesa/s3_mtrr.c @@ -8,114 +8,82 @@ #include <string.h> #include <northbridge/amd/agesa/agesa_helper.h> -static void write_mtrr(u8 **p_nvram_pos, unsigned int idx) -{ - msr_t msr_data; - msr_data = rdmsr(idx); - - memcpy(*p_nvram_pos, &msr_data, sizeof(msr_data)); - *p_nvram_pos += sizeof(msr_data); -} +struct mtrr_backup { + msr_t mtrr_fix_64k_00000; + msr_t mtrr_fix_16k_80000; + msr_t mtrr_fix_16k_a0000; + msr_t mtrr_fix_4k_xx000[8]; /* 4K_C0000 -- 4K_F8000 */ + msr_t mtrr_phys_base[8]; + msr_t mtrr_phys_mask[8]; + msr_t syscfg; + msr_t top_mem; + msr_t top_mem2; +}; void backup_mtrr(void *mtrr_store, u32 *mtrr_store_size) { - u8 *nvram_pos = mtrr_store; - msr_t msr_data; - u32 i; + msr_t syscfg_msr; + struct mtrr_backup *mtrr_save = (struct mtrr_backup *)mtrr_store; + uint32_t i; /* Enable access to AMD RdDram and WrDram extension bits */ - msr_data = rdmsr(SYSCFG_MSR); - msr_data.lo |= SYSCFG_MSR_MtrrFixDramModEn; - wrmsr(SYSCFG_MSR, msr_data); + syscfg_msr = rdmsr(SYSCFG_MSR); + syscfg_msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYSCFG_MSR, syscfg_msr); - /* Fixed MTRRs */ - write_mtrr(&nvram_pos, MTRR_FIX_64K_00000); - write_mtrr(&nvram_pos, MTRR_FIX_16K_80000); - write_mtrr(&nvram_pos, MTRR_FIX_16K_A0000); + mtrr_save->mtrr_fix_64k_00000 = rdmsr(MTRR_FIX_64K_00000); + mtrr_save->mtrr_fix_16k_80000 = rdmsr(MTRR_FIX_16K_80000); + mtrr_save->mtrr_fix_16k_a0000 = rdmsr(MTRR_FIX_16K_A0000); - for (i = MTRR_FIX_4K_C0000; i <= MTRR_FIX_4K_F8000; i++) - write_mtrr(&nvram_pos, i); + for (i = 0; i < 8; i++) + mtrr_save->mtrr_fix_4k_xx000[i] = rdmsr(MTRR_FIX_4K_C0000 + i); /* Disable access to AMD RdDram and WrDram extension bits */ - msr_data = rdmsr(SYSCFG_MSR); - msr_data.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; - wrmsr(SYSCFG_MSR, msr_data); + syscfg_msr = rdmsr(SYSCFG_MSR); + syscfg_msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYSCFG_MSR, syscfg_msr); - /* Variable MTRRs */ - for (i = MTRR_PHYS_BASE(0); i < MTRR_PHYS_BASE(8); i++) - write_mtrr(&nvram_pos, i); + for (i = 0; i < 8; i++) { + mtrr_save->mtrr_phys_mask[i] = rdmsr(MTRR_PHYS_BASE(i)); + mtrr_save->mtrr_phys_base[i] = rdmsr(MTRR_PHYS_BASE(i)); + } - /* SYSCFG_MSR */ - write_mtrr(&nvram_pos, SYSCFG_MSR); - /* TOM */ - write_mtrr(&nvram_pos, TOP_MEM); - /* TOM2 */ - write_mtrr(&nvram_pos, TOP_MEM2); + mtrr_save->syscfg = rdmsr(SYSCFG_MSR); + mtrr_save->top_mem = rdmsr(TOP_MEM); + mtrr_save->top_mem2 = rdmsr(TOP_MEM2); - *mtrr_store_size = nvram_pos - (u8*) mtrr_store; + *mtrr_store_size = sizeof(struct mtrr_backup); } void restore_mtrr(void) { - volatile u32 *msrPtr = (u32 *) OemS3Saved_MTRR_Storage(); - u32 msr; - msr_t msr_data; - - if (!msrPtr) - return; - - disable_cache(); + msr_t syscfg_msr; + struct mtrr_backup *mtrr_save = (struct mtrr_backup *)OemS3Saved_MTRR_Storage(); + uint32_t i; /* Enable access to AMD RdDram and WrDram extension bits */ - msr_data = rdmsr(SYSCFG_MSR); - msr_data.lo |= SYSCFG_MSR_MtrrFixDramModEn; - wrmsr(SYSCFG_MSR, msr_data); + syscfg_msr = rdmsr(SYSCFG_MSR); + syscfg_msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYSCFG_MSR, syscfg_msr); - /* Now restore the Fixed MTRRs */ - msr_data.lo = *msrPtr; - msrPtr ++; - msr_data.hi = *msrPtr; - msrPtr ++; - wrmsr(MTRR_FIX_64K_00000, msr_data); + wrmsr(MTRR_FIX_64K_00000, mtrr_save->mtrr_fix_64k_00000); + wrmsr(MTRR_FIX_16K_80000, mtrr_save->mtrr_fix_16k_80000); + wrmsr(MTRR_FIX_16K_A0000, mtrr_save->mtrr_fix_16k_a0000); - msr_data.lo = *msrPtr; - msrPtr ++; - msr_data.hi = *msrPtr; - msrPtr ++; - wrmsr(MTRR_FIX_16K_80000, msr_data); - - msr_data.lo = *msrPtr; - msrPtr ++; - msr_data.hi = *msrPtr; - msrPtr ++; - wrmsr(MTRR_FIX_16K_A0000, msr_data); - - for (msr = MTRR_FIX_4K_C0000; msr <= MTRR_FIX_4K_F8000; msr++) { - msr_data.lo = *msrPtr; - msrPtr ++; - msr_data.hi = *msrPtr; - msrPtr ++; - wrmsr(msr, msr_data); - } + for (i = 0; i < 8; i++) + wrmsr(MTRR_FIX_4K_C0000 + i, mtrr_save->mtrr_fix_4k_xx000[i]); /* Disable access to AMD RdDram and WrDram extension bits */ - msr_data = rdmsr(SYSCFG_MSR); - msr_data.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; - wrmsr(SYSCFG_MSR, msr_data); + syscfg_msr = rdmsr(SYSCFG_MSR); + syscfg_msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYSCFG_MSR, syscfg_msr); - /* Restore the Variable MTRRs */ - for (msr = MTRR_PHYS_BASE(0); msr <= MTRR_PHYS_MASK(7); msr++) { - msr_data.lo = *msrPtr; - msrPtr ++; - msr_data.hi = *msrPtr; - msrPtr ++; - wrmsr(msr, msr_data); + for (i = 0; i < 8; i++) { + wrmsr(MTRR_PHYS_BASE(i), mtrr_save->mtrr_phys_mask[i]); + wrmsr(MTRR_PHYS_BASE(i), mtrr_save->mtrr_phys_base[i]); } - /* Restore SYSCFG MTRR */ - msr_data.lo = *msrPtr; - msrPtr ++; - msr_data.hi = *msrPtr; - msrPtr ++; - wrmsr(SYSCFG_MSR, msr_data); + wrmsr(SYSCFG_MSR, mtrr_save->syscfg); + wrmsr(TOP_MEM, mtrr_save->top_mem); + wrmsr(TOP_MEM2, mtrr_save->top_mem2); } -- To view, visit https://review.coreboot.org/c/coreboot/+/44293 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3c6df8951d39695cddd4635360d6407d4d001b0a Gerrit-Change-Number: 44293 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 days

Change in coreboot[master]: [UNTESTED]cpu/amd/agesa: Use common MRC_CACHE code to save S3 data

by Arthur Heymans (Code Review)

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44295 ) Change subject: [UNTESTED]cpu/amd/agesa: Use common MRC_CACHE code to save S3 data ...................................................................... [UNTESTED]cpu/amd/agesa: Use common MRC_CACHE code to save S3 data Most of the code is copied from soc/amd/common/block/s3/s3_resume.c The current default MRC_CACHE FMAP region is 64K instead of 8K. One could make this configurable in the future. Change-Id: I0f4f36dcead52a6c550fb5e606772e0a99029872 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/amd/agesa/Kconfig M src/cpu/amd/agesa/Makefile.inc M src/drivers/amd/agesa/oem_s3.c 3 files changed, 38 insertions(+), 81 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/44295/1 diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 499cc5b..f407139 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -18,6 +18,7 @@ select SMM_ASEG select SSE2 select ACPI_NO_SMI_GNVS + select CACHE_MRC_SETTINGS if CPU_AMD_AGESA @@ -53,14 +54,6 @@ Try to restore memory training results from non-volatile memory. -config S3_DATA_POS - hex - default 0xFFFF0000 - -config S3_DATA_SIZE - int - default 8192 - endif # CPU_AMD_AGESA source "src/cpu/amd/agesa/family14/Kconfig" diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc index 14067e1..1f9cca5 100644 --- a/src/cpu/amd/agesa/Makefile.inc +++ b/src/cpu/amd/agesa/Makefile.inc @@ -3,18 +3,3 @@ subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += family14 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) += family15tn subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) += family16kb - -ifeq ($(CONFIG_HAVE_ACPI_RESUME), y) - -$(obj)/coreboot_s3nv.rom: $(obj)/config.h - echo " S3 NVRAM $(CONFIG_S3_DATA_POS) (S3 storage area)" - # force C locale, so cygwin awk doesn't try to interpret the 0xff below as UTF-8 (or worse) - printf %d $(CONFIG_S3_DATA_SIZE) | LC_ALL=C awk '{for (i=0; i<$$1; i++) {printf "%c", 255}}' > $@.tmp - mv $@.tmp $@ - -cbfs-files-y += s3nv -s3nv-file := $(obj)/coreboot_s3nv.rom -s3nv-position := $(CONFIG_S3_DATA_POS) -s3nv-type := raw - -endif # CONFIG_HAVE_ACPI_RESUME == y diff --git a/src/drivers/amd/agesa/oem_s3.c b/src/drivers/amd/agesa/oem_s3.c index 0b37d3e..8d32bae 100644 --- a/src/drivers/amd/agesa/oem_s3.c +++ b/src/drivers/amd/agesa/oem_s3.c @@ -1,41 +1,53 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <spi-generic.h> -#include <spi_flash.h> #include <string.h> +#include <device/mmio.h> #include <cbmem.h> #include <console/console.h> +#include <mrc_cache.h> +#include <reset.h> #include <northbridge/amd/agesa/state_machine.h> #include <AGESA.h> #include <northbridge/amd/agesa/agesa_helper.h> -/* The size needs to be 4k aligned, which is the sector size of most flashes. */ -#define S3_DATA_NONVOLATILE_SIZE 0x1000 +/* Training data versioning is not supported or tracked. */ +#define DEFAULT_MRC_VERSION 0 -#if CONFIG(HAVE_ACPI_RESUME) && S3_DATA_NONVOLATILE_SIZE > CONFIG_S3_DATA_SIZE -#error "Please increase the value of S3_DATA_SIZE" -#endif - -static void get_s3nv_data(uintptr_t *pos, uintptr_t *len) +static void __noreturn reboot_from_resume(const char *message) { - /* FIXME: Find file from CBFS. */ - *pos = CONFIG_S3_DATA_POS; - *len= S3_DATA_NONVOLATILE_SIZE; + printk(BIOS_ERR, "%s", message); +// set_pm1cnt_s5(); TODO?? + board_reset(); } AGESA_STATUS OemInitResume(AMD_S3_PARAMS *dataBlock) { - uintptr_t pos, size; - get_s3nv_data(&pos, &size); + void *base; + size_t size; + int i; + uint32_t erased = 0xffffffff; + struct region_device rdev; - u32 len = *(u32*)pos; + if (mrc_cache_get_current(MRC_TRAINING_DATA, DEFAULT_MRC_VERSION, + &rdev)) + reboot_from_resume("mrc_cache_get_current error, rebooting.\n"); - /* Test for uninitialized s3nv data in SPI. */ - if (len == 0 || len == (u32)-1ULL) - return AGESA_FATAL; + base = rdev_mmap_full(&rdev); + size = region_device_sz(&rdev); + if (!base || !size) + reboot_from_resume("Error: S3 NV data not found, rebooting.\n"); - dataBlock->NvStorageSize = len; - dataBlock->NvStorage = (void *) (pos + sizeof(u32)); + /* Read 16 bytes to infer if the NV has been erased from flash. */ + for (i = 0; i < 4; i++) + erased &= read32((uint32_t *)base + i); + if (erased == 0xffffffff) + reboot_from_resume("Error: S3 NV data invalid, rebooting.\n"); + + dataBlock->NvStorage = base; + dataBlock->NvStorageSize = size; + printk(BIOS_SPEW, "S3 NV data @%p, 0x%0zx bytes\n", + dataBlock->NvStorage, (size_t)dataBlock->NvStorageSize); + return AGESA_SUCCESS; } @@ -56,44 +68,13 @@ return AGESA_SUCCESS; } -#if ENV_RAMSTAGE - -static int spi_SaveS3info(u32 pos, u32 size, u8 *buf, u32 len) -{ -#if CONFIG(SPI_FLASH) - struct spi_flash flash; - - spi_init(); - if (spi_flash_probe(0, 0, &flash)) - return -1; - - spi_flash_volatile_group_begin(&flash); - - spi_flash_erase(&flash, pos, size); - spi_flash_write(&flash, pos, sizeof(len), &len); - spi_flash_write(&flash, pos + sizeof(len), len, buf); - - spi_flash_volatile_group_end(&flash); - return 0; -#else - return -1; -#endif -} - AGESA_STATUS OemS3Save(AMD_S3_PARAMS *dataBlock) { - uintptr_t pos, size; - - /* To be consumed in AmdInitResume. */ - get_s3nv_data(&pos, &size); - if (size && dataBlock->NvStorageSize) - spi_SaveS3info(pos, size, dataBlock->NvStorage, - dataBlock->NvStorageSize); - else - printk(BIOS_EMERG, - "Error: Cannot store memory training results in SPI.\n" - "Error: S3 resume will not be possible.\n" - ); + if (mrc_cache_stash_data(MRC_TRAINING_DATA, DEFAULT_MRC_VERSION, + dataBlock->NvStorage, dataBlock->NvStorageSize) < 0) { + printk(BIOS_ERR, "Failed to stash MRC data\n"); + return AGESA_CRITICAL; + } /* To be consumed in AmdS3LateRestore. */ char *heap = cbmem_add(CBMEM_ID_RESUME_SCRATCH, HIGH_MEMORY_SCRATCH); @@ -107,5 +88,3 @@ return AGESA_SUCCESS; } - -#endif /* ENV_RAMSTAGE */ -- To view, visit https://review.coreboot.org/c/coreboot/+/44295 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f4f36dcead52a6c550fb5e606772e0a99029872 Gerrit-Change-Number: 44295 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 days, 1 hour

Change in coreboot[master]: [UNTESTED]drivers/amd/agesa: Don't save regular boot MTRR to flash

by Arthur Heymans (Code Review)

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44294 ) Change subject: [UNTESTED]drivers/amd/agesa: Don't save regular boot MTRR to flash ...................................................................... [UNTESTED]drivers/amd/agesa: Don't save regular boot MTRR to flash Save the regular boot MTRR's that are restored on the S3 path during the CPU init with cbmem instead of storing them to the SPI flash. Change-Id: Ia58e7cd1afb785ba0c379ba75ef6090b56cb9dc6 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/commonlib/include/commonlib/cbmem_id.h M src/drivers/amd/agesa/oem_s3.c M src/drivers/amd/agesa/s3_mtrr.c M src/northbridge/amd/agesa/agesa_helper.h 4 files changed, 21 insertions(+), 52 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/44294/1 diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h index ac271a0..058a9d4 100644 --- a/src/commonlib/include/commonlib/cbmem_id.h +++ b/src/commonlib/include/commonlib/cbmem_id.h @@ -8,6 +8,7 @@ #define CBMEM_ID_ACPI_UCSI 0x55435349 #define CBMEM_ID_AFTER_CAR 0xc4787a93 #define CBMEM_ID_AGESA_RUNTIME 0x41474553 +#define CBMEM_ID_AGESA_MTRR 0xf08b4b9d #define CBMEM_ID_AMDMCT_MEMINFO 0x494D454E #define CBMEM_ID_CAR_GLOBALS 0xcac4e6a3 #define CBMEM_ID_CBTABLE 0x43425442 @@ -74,6 +75,7 @@ { CBMEM_ID_ACPI_GNVS, "ACPI GNVS " }, \ { CBMEM_ID_ACPI_UCSI, "ACPI UCSI " }, \ { CBMEM_ID_AGESA_RUNTIME, "AGESA RSVD " }, \ + { CBMEM_ID_AGESA_MTRR, "AGESA MTRR " }, \ { CBMEM_ID_AFTER_CAR, "AFTER CAR " }, \ { CBMEM_ID_AMDMCT_MEMINFO, "AMDMEM INFO" }, \ { CBMEM_ID_CAR_GLOBALS, "CAR GLOBALS" }, \ diff --git a/src/drivers/amd/agesa/oem_s3.c b/src/drivers/amd/agesa/oem_s3.c index e47daf3..0b37d3e 100644 --- a/src/drivers/amd/agesa/oem_s3.c +++ b/src/drivers/amd/agesa/oem_s3.c @@ -9,45 +9,24 @@ #include <AGESA.h> #include <northbridge/amd/agesa/agesa_helper.h> -typedef enum { - S3DataTypeNonVolatile = 0, ///< NonVolatile Data Type - S3DataTypeMTRR ///< MTRR storage -} S3_DATA_TYPE; - /* The size needs to be 4k aligned, which is the sector size of most flashes. */ -#define S3_DATA_MTRR_SIZE 0x1000 #define S3_DATA_NONVOLATILE_SIZE 0x1000 -#if CONFIG(HAVE_ACPI_RESUME) && \ - (S3_DATA_MTRR_SIZE + S3_DATA_NONVOLATILE_SIZE) > CONFIG_S3_DATA_SIZE +#if CONFIG(HAVE_ACPI_RESUME) && S3_DATA_NONVOLATILE_SIZE > CONFIG_S3_DATA_SIZE #error "Please increase the value of S3_DATA_SIZE" #endif -static void get_s3nv_data(S3_DATA_TYPE S3DataType, uintptr_t *pos, uintptr_t *len) +static void get_s3nv_data(uintptr_t *pos, uintptr_t *len) { /* FIXME: Find file from CBFS. */ - u32 s3_data = CONFIG_S3_DATA_POS; - - switch (S3DataType) { - case S3DataTypeMTRR: - *pos = s3_data; - *len = S3_DATA_MTRR_SIZE; - break; - case S3DataTypeNonVolatile: - *pos = s3_data + S3_DATA_MTRR_SIZE; - *len = S3_DATA_NONVOLATILE_SIZE; - break; - default: - *pos = 0; - *len = 0; - break; - } + *pos = CONFIG_S3_DATA_POS; + *len= S3_DATA_NONVOLATILE_SIZE; } AGESA_STATUS OemInitResume(AMD_S3_PARAMS *dataBlock) { uintptr_t pos, size; - get_s3nv_data(S3DataTypeNonVolatile, &pos, &size); + get_s3nv_data(&pos, &size); u32 len = *(u32*)pos; @@ -101,15 +80,12 @@ #endif } -static u8 MTRRStorage[S3_DATA_MTRR_SIZE]; - AGESA_STATUS OemS3Save(AMD_S3_PARAMS *dataBlock) { - u32 MTRRStorageSize = 0; uintptr_t pos, size; /* To be consumed in AmdInitResume. */ - get_s3nv_data(S3DataTypeNonVolatile, &pos, &size); + get_s3nv_data(&pos, &size); if (size && dataBlock->NvStorageSize) spi_SaveS3info(pos, size, dataBlock->NvStorage, dataBlock->NvStorageSize); @@ -127,24 +103,9 @@ } /* Collect MTRR setup. */ - backup_mtrr(MTRRStorage, &MTRRStorageSize); - - /* To be consumed in restore_mtrr, CPU enumeration in ramstage. */ - get_s3nv_data(S3DataTypeMTRR, &pos, &size); - if (size && MTRRStorageSize) - spi_SaveS3info(pos, size, MTRRStorage, MTRRStorageSize); + backup_mtrr(); return AGESA_SUCCESS; } #endif /* ENV_RAMSTAGE */ - -const void *OemS3Saved_MTRR_Storage(void) -{ - uintptr_t pos, size; - get_s3nv_data(S3DataTypeMTRR, &pos, &size); - if (!size) - return NULL; - - return (void *)(pos + sizeof(UINT32)); -} diff --git a/src/drivers/amd/agesa/s3_mtrr.c b/src/drivers/amd/agesa/s3_mtrr.c index 672eb20..be38327 100644 --- a/src/drivers/amd/agesa/s3_mtrr.c +++ b/src/drivers/amd/agesa/s3_mtrr.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <stdint.h> +#include <cbmem.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <cpu/amd/mtrr.h> @@ -20,12 +21,16 @@ msr_t top_mem2; }; -void backup_mtrr(void *mtrr_store, u32 *mtrr_store_size) +void backup_mtrr(void) { msr_t syscfg_msr; - struct mtrr_backup *mtrr_save = (struct mtrr_backup *)mtrr_store; + struct mtrr_backup *mtrr_save; uint32_t i; + mtrr_save = cbmem_add(CBMEM_ID_AGESA_MTRR, sizeof(struct mtrr_backup)); + if (!mtrr_save) + return; + /* Enable access to AMD RdDram and WrDram extension bits */ syscfg_msr = rdmsr(SYSCFG_MSR); syscfg_msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; @@ -51,16 +56,17 @@ mtrr_save->syscfg = rdmsr(SYSCFG_MSR); mtrr_save->top_mem = rdmsr(TOP_MEM); mtrr_save->top_mem2 = rdmsr(TOP_MEM2); - - *mtrr_store_size = sizeof(struct mtrr_backup); } void restore_mtrr(void) { msr_t syscfg_msr; - struct mtrr_backup *mtrr_save = (struct mtrr_backup *)OemS3Saved_MTRR_Storage(); + struct mtrr_backup *mtrr_save = cbmem_find(CBMEM_ID_AGESA_MTRR); uint32_t i; + if (!mtrr_save) + return; + /* Enable access to AMD RdDram and WrDram extension bits */ syscfg_msr = rdmsr(SYSCFG_MSR); syscfg_msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; diff --git a/src/northbridge/amd/agesa/agesa_helper.h b/src/northbridge/amd/agesa/agesa_helper.h index 120e74a..ef6085f 100644 --- a/src/northbridge/amd/agesa/agesa_helper.h +++ b/src/northbridge/amd/agesa/agesa_helper.h @@ -39,7 +39,7 @@ void recover_postcar_frame(struct postcar_frame *pcf, int s3resume); void restore_mtrr(void); -void backup_mtrr(void *mtrr_store, u32 *mtrr_store_size); +void backup_mtrr(void); const void *OemS3Saved_MTRR_Storage(void); #endif /* _AGESA_HELPER_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/44294 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia58e7cd1afb785ba0c379ba75ef6090b56cb9dc6 Gerrit-Change-Number: 44294 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 days, 3 hours

Change in coreboot[master]: mb/lenovo/t60: Add support for ThinkLight

by Stefan Ott (Code Review)

Stefan Ott has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40678 ) Change subject: mb/lenovo/t60: Add support for ThinkLight ...................................................................... mb/lenovo/t60: Add support for ThinkLight With this patch, the ThinkLight on the ThinkPad T60 can be controlled through the OS. This was initially done for the X201 in f63fbdb6: mb/lenovo/x201: Add support for ThinkLight. After applying this patch, the light can be controlled like this: echo on >/proc/acpi/ibm/light echo off >/proc/acpi/ibm/light Or through sysfs at /sys/class/leds/tpacpi::thinklight Unfortunately I do not own a T60 to test this. Change-Id: I47f878533d36857d002d2e2605cc8bc7e1d960c9 Signed-off-by: Stefan Ott <stefan(a)ott.net> --- M src/mainboard/lenovo/t60/dsdt.asl 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/40678/1 diff --git a/src/mainboard/lenovo/t60/dsdt.asl b/src/mainboard/lenovo/t60/dsdt.asl index 51ff336..cab3ddb 100644 --- a/src/mainboard/lenovo/t60/dsdt.asl +++ b/src/mainboard/lenovo/t60/dsdt.asl @@ -48,4 +48,6 @@ // Dock support code #include "acpi/dock.asl" + + #include <ec/lenovo/h8/acpi/thinklight.asl> } -- To view, visit https://review.coreboot.org/c/coreboot/+/40678 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47f878533d36857d002d2e2605cc8bc7e1d960c9 Gerrit-Change-Number: 40678 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Ott <coreboot(a)desire.ch> Gerrit-MessageType: newchange

4 days, 1 hour

Change in coreboot[master]: WIP: riscv/mb/qemu: fix DRAM probing

by Philipp Hug (Code Review)

Philipp Hug has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36486 ) Change subject: WIP: riscv/mb/qemu: fix DRAM probing ...................................................................... WIP: riscv/mb/qemu: fix DRAM probing Current version of qemu raise an exception when accessing invalid memory. Modify the probing code to temporary redirect the exception handler like on ARM platform. TEST=qemu detects RAM size correctly Change-Id: I25860f688c7546714f6fdbce8c8f96da6400813c Signed-off-by: Philipp Hug <philipp(a)hug.cx> --- M src/arch/riscv/Makefile.inc M src/arch/riscv/include/arch/exception.h A src/arch/riscv/ramdetect.c M src/arch/riscv/trap_handler.c M src/arch/riscv/trap_util.S M src/lib/ramdetect.c 6 files changed, 57 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/36486/1 diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index 0039fab..7465a8f 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -101,6 +101,7 @@ romstage-y += stages.c romstage-y += misc.c romstage-$(ARCH_RISCV_PMP) += pmp.c +romstage-y += ramdetect.c romstage-y += smp.c romstage-y += \ $(top)/src/lib/memchr.c \ @@ -142,6 +143,7 @@ ramstage-y += virtual_memory.c ramstage-y += stages.c ramstage-y += misc.c +ramstage-y += ramdetect.c ramstage-y += smp.c ramstage-y += boot.c ramstage-y += tables.c diff --git a/src/arch/riscv/include/arch/exception.h b/src/arch/riscv/include/arch/exception.h index 6fbbdf0..cdca582 100644 --- a/src/arch/riscv/include/arch/exception.h +++ b/src/arch/riscv/include/arch/exception.h @@ -53,7 +53,7 @@ } void redirect_trap(void); -void trap_handler(trapframe *tf); +void default_trap_handler(trapframe *tf); void handle_supervisor_call(trapframe *tf); void handle_misaligned(trapframe *tf); diff --git a/src/arch/riscv/ramdetect.c b/src/arch/riscv/ramdetect.c new file mode 100644 index 0000000..47153ab --- /dev/null +++ b/src/arch/riscv/ramdetect.c @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include <arch/exception.h> +#include <types.h> +#include <console/console.h> +#include <device/mmio.h> +#include <ramdetect.h> +#include <arch/smp/spinlock.h> + +static enum { + ABORT_CHECKER_NOT_TRIGGERED, + ABORT_CHECKER_TRIGGERED, +} abort_state = ABORT_CHECKER_NOT_TRIGGERED; + +extern void(*trap_handler)(trapframe *tf); + +#define insn_size 4 +static void ramcheck_trap_handler(trapframe *tf) +{ + printk(BIOS_DEBUG, "TRAP 0x%lx!!!\n", tf->epc); + abort_state = ABORT_CHECKER_TRIGGERED; + + /* + * skip read instruction. + * currenctly hardcoded to 32bit instruction size + */ + write_csr(mepc, read_csr(mepc) + insn_size); +} + +int probe_mb(const uintptr_t dram_start, const uintptr_t size) +{ + uintptr_t addr = dram_start + (size * MiB) - sizeof(uint32_t); + void *ptr = (void *)addr; + + abort_state = ABORT_CHECKER_NOT_TRIGGERED; + trap_handler = ramcheck_trap_handler; + barrier(); + read32(ptr); + trap_handler = default_trap_handler; + barrier(); + return abort_state == ABORT_CHECKER_NOT_TRIGGERED; +} diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c index 6b39fab..1d51268 100644 --- a/src/arch/riscv/trap_handler.c +++ b/src/arch/riscv/trap_handler.c @@ -118,7 +118,10 @@ break; } } -void trap_handler(trapframe *tf) + +void(*trap_handler)(trapframe *tf) = default_trap_handler; + +void default_trap_handler(trapframe *tf) { write_csr(mscratch, tf); if (tf->cause & 0x8000000000000000ULL) { diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S index 67e917c..93f5afd 100644 --- a/src/arch/riscv/trap_util.S +++ b/src/arch/riscv/trap_util.S @@ -120,7 +120,8 @@ save_tf mv a0, sp - jal trap_handler + ld t0, trap_handler + jalr t0 restore_regs addi sp, sp, MENTRY_FRAME_SIZE diff --git a/src/lib/ramdetect.c b/src/lib/ramdetect.c index 2c83092..eaf6190 100644 --- a/src/lib/ramdetect.c +++ b/src/lib/ramdetect.c @@ -58,6 +58,8 @@ if (saved_result) return saved_result; + printk(BIOS_DEBUG, "RAMDETECT: Starting\n"); + /* Find the MSB + 1. */ size_t tmp = probe_size; do { -- To view, visit https://review.coreboot.org/c/coreboot/+/36486 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25860f688c7546714f6fdbce8c8f96da6400813c Gerrit-Change-Number: 36486 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-MessageType: newchange

1 week, 1 day

Change in coreboot[master]: Herobrine T32 scripts working in standalone environment

by Ravi kumar (Code Review)

Hello mturney mturney, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/47365 to review the following change. Change subject: Herobrine T32 scripts working in standalone environment ...................................................................... Herobrine T32 scripts working in standalone environment Change-Id: I451344d887c7b6c0983594e4dea4ca2b030d65f1 --- M util/qualcomm/scripts/cmm/debug_cb_common.cmm A util/qualcomm/scripts/cmm/debug_cb_herobrine.cmm 2 files changed, 123 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/47365/1 diff --git a/util/qualcomm/scripts/cmm/debug_cb_common.cmm b/util/qualcomm/scripts/cmm/debug_cb_common.cmm index cbcb004..a722864 100644 --- a/util/qualcomm/scripts/cmm/debug_cb_common.cmm +++ b/util/qualcomm/scripts/cmm/debug_cb_common.cmm @@ -126,6 +126,11 @@ else d.load.elf &imgpath /strippart "coreboot" /sourcepath &srcpath /nocode + print "Hacking DDR ranges..." + B::D.S MD:0x1485B000 %LE %Long 0x80000000 + B::D.S MD:0x1485B004 %LE %Long 0 + B::D.S MD:0x1485B008 %LE %Long 0x80000000 + print %String "Now the control is in ROMStage, press enter after debugging to go to next stage" print %String "Press enter to go to next stage" enter diff --git a/util/qualcomm/scripts/cmm/debug_cb_herobrine.cmm b/util/qualcomm/scripts/cmm/debug_cb_herobrine.cmm new file mode 100644 index 0000000..8693a5f --- /dev/null +++ b/util/qualcomm/scripts/cmm/debug_cb_herobrine.cmm @@ -0,0 +1,118 @@ +;============================================================================ +;## SPDX-License-Identifier: GPL-2.0-only +;============================================================================ +; Name: +; debug_cb_trogdor.cmm +; +; Description: +; Debug coreboot trogdor front-end +;============================================================================ + +;============================================================================ +; CMM script variables +;============================================================================ + +LOCAL &TargetPkg + +GLOBAL &BBEntryAddr // Bootblock Entry +GLOBAL &BBExitAddr // Bootblock Exit to Xbl-Sec +GLOBAL &VEREntryAddr // Verstage Entry +GLOBAL &ROMEntryAddr // Romstage Entry +GLOBAL &QCLEntryAddr // QCLstage Entry +GLOBAL &RAMEntryAddr // Ramstage Entry +GLOBAL &BL31EntryAddr // BL31 Entry +GLOBAL &DCEntryAddr // Depthcharge Entry + +GLOBAL &PreRamConsoleAddr +GLOBAL &RamConsoleAddr +GLOBAL &PreRamCbfsCache +GLOBAL &VBoot2Work +GLOBAL &Stack +GLOBAL &Ttb +GLOBAL &Timestamp +GLOBAL &CbmemTop +GLOBAL &PostRamCbfsCache + +GLOBAL &CBTablePtr + +;============================================================================ + +;--------------------------------------------------- +; Entry point +;--------------------------------------------------- +ENTRY &ImageName &RegAddress + + // Later these can be parameterized + &TargetPkg="herobrinePkg" + + // These settings come from .../src/soc/qualcomm/sc7280/memlayout.ld + &BBEntryAddr=0x14819000 + &VEREntryAddr=0x14680000 + &ROMEntryAddr=0x14680000 + &QCLEntryAddr=0x1486c950 + &RAMEntryAddr=0xA0800000 + &BL31EntryAddr=0x80C00000 + &DCEntryAddr=0xF1000000 + &KernelEntryAddr=0xD0000000 + + &PreRamConsoleAddr=0x14834800 + &VBoot2Work=0x1484F000 + &Stack=0x1484B000 + &Ttb=0x1483D000 + &Timestamp=0x1483C800 + &PreRamCbfsCache=0x14823000 + &CbmemTop=0x280000000 + &PostRamCbfsCache=0x9F800000 + // End of memlayout.ld settings + + // Common commands irrespective of &Mode + PATH + &CwDir=os.pwd() + PATH + &CwDir + + // position at top of coreboot tree + // find depth count for source loading + cd ..\..\..\.. + &srcpath=os.pwd() + + +;--------------------------------------------------- +; Setup area and log +;--------------------------------------------------- + area.clear + area.reset + area.create CB_Logs 1000. 8192. + area.select CB_Logs + + area.view CB_Logs + + PRINT %String "Source Path: &srcpath" + + symbol.sourcepath.setbasedir &srcpath\src + + // Make parsing simple, upper-case parameters + &ImageName=STRING.UPR("&ImageName") + if (STR.CP("&ImageName","0X*")) + ( + &RegAddress=&ImageName + &ImageName="" + ) + &RegAddress=STRING.UPR("&RegAddress") + + PRINT %String "ImageName: &ImageName" + PRINT %String "RegAddress: &RegAddress" + + ;sys.d + ;sys.up + b.d + y.reset + + if (STR.CP("&RegAddress","0X*")) + D.S EZAXI:&RegAddress %LE %Long 0x80000000 + + go &BBEntryAddr + wait !run() + + DO debug_cb_common.cmm &TargetPkg &srcpath &xblsrcpath &ImageName + + enddo -- To view, visit https://review.coreboot.org/c/coreboot/+/47365 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I451344d887c7b6c0983594e4dea4ca2b030d65f1 Gerrit-Change-Number: 47365 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newchange

1 week, 3 days

Change in coreboot[master]: arch,cpu,lib: Use thin archives instead of partial linking

by Jacob Garber (Code Review)

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40812 ) Change subject: arch,cpu,lib: Use thin archives instead of partial linking ...................................................................... arch,cpu,lib: Use thin archives instead of partial linking x86 ramstage and smm compilation currently use partial linking, which is not supported by link-time optimization. Collect the object files into thin archives instead, and link them all at once at the very end. Change-Id: I122a4542d1e98d89545897d5177c93ee463d0cdb Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> --- M src/arch/x86/Makefile.inc M src/cpu/x86/smm/Makefile.inc M src/lib/Makefile.inc 3 files changed, 17 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/40812/1 diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index af52f70..1615e75 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -307,18 +307,20 @@ endif -$(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(call src-to-obj,ramstage,src/arch/x86/memlayout.ld) - @printf " CC $(subst $(obj)/,,$(@))\n" - $(LD_ramstage) $(CPPFLAGS) $(LDFLAGS_ramstage) -o $@ -L$(obj) $< -T $(call src-to-obj,ramstage,src/arch/x86/memlayout.ld) - -$(objgenerated)/ramstage.o: $$(ramstage-objs) $(COMPILER_RT_ramstage) $$(ramstage-libs) - @printf " CC $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) - $(LD_ramstage) -Wl,-m,elf_i386 -r -o $@ $(COMPILER_RT_FLAGS_ramstage) -Wl,--whole-archive,--start-group $(filter-out %.ld,$(ramstage-objs)) $(ramstage-libs) -Wl,--no-whole-archive $(COMPILER_RT_ramstage) -Wl,--end-group +LDFLAGS_ramstage += -Wl,-m,elf_i386 else - $(LD_ramstage) -Wl,-m,elf_x86_64 -r -o $@ $(COMPILER_RT_FLAGS_ramstage) -Wl,--whole-archive,--start-group $(filter-out %.ld,$(ramstage-objs)) $(ramstage-libs) -Wl,--no-whole-archive $(COMPILER_RT_ramstage) -Wl,--end-group +LDFLAGS_ramstage += -Wl,-m,elf_x86_64 endif +$(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.a $(call src-to-obj,ramstage,src/arch/x86/memlayout.ld) + @printf " CC $(subst $(obj)/,,$(@))\n" + $(LD_ramstage) $(CPPFLAGS) $(LDFLAGS_ramstage) $(COMPILER_RT_FLAGS_ramstage) -o $@ -L$(obj) -Wl,--whole-archive,--start-group $< -Wl,--no-whole-archive $(COMPILER_RT_ramstage) -Wl,--end-group -T $(call src-to-obj,ramstage,src/arch/x86/memlayout.ld) + +$(objgenerated)/ramstage.a: $$(ramstage-objs) $$(ramstage-libs) + @printf " AR $(subst $(obj)/,,$(@))\n" + $(AR_ramstage) rcT $@ $(filter-out %.ld,$(ramstage-objs)) $(ramstage-libs) + endif # CONFIG_ARCH_RAMSTAGE_X86_32 / CONFIG_ARCH_RAMSTAGE_X86_64 smm-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index 2e63fb3..4899370 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -25,8 +25,8 @@ smm-generic-ccopts += -D__SMM__ smm-c-deps:=$$(OPTION_TABLE_H) -$(obj)/smm/smm.o: $$(smm-objs) $(COMPILER_RT_smm) - $(LD_smm) -nostdlib -r -o $@ $(COMPILER_RT_FLAGS_smm) -Wl,--whole-archive,--start-group $(smm-objs) -Wl,--no-whole-archive $(COMPILER_RT_smm) -Wl,--end-group +$(obj)/smm/smm.a: $$(smm-objs) + $(AR_smm) rcT $@ $^ # change to the target path because objcopy will use the path name in its # ELF symbol names. @@ -72,9 +72,9 @@ # C-based SMM handler. ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) -$(eval $(call rmodule_link,$(obj)/smm/smm.elf, $(obj)/smm/smm.o, $(CONFIG_SMM_MODULE_HEAP_SIZE),x86_32)) +$(eval $(call rmodule_link,$(obj)/smm/smm.elf, $(obj)/smm/smm.a, $(CONFIG_SMM_MODULE_HEAP_SIZE),x86_32)) else -$(eval $(call rmodule_link,$(obj)/smm/smm.elf, $(obj)/smm/smm.o, $(CONFIG_SMM_MODULE_HEAP_SIZE),x86_64)) +$(eval $(call rmodule_link,$(obj)/smm/smm.elf, $(obj)/smm/smm.a, $(CONFIG_SMM_MODULE_HEAP_SIZE),x86_64)) endif $(obj)/smm/smm: $(obj)/smm/smm.elf.rmod @@ -82,8 +82,8 @@ else # CONFIG_SMM_TSEG -$(obj)/smm/smm: $(obj)/smm/smm.o $(src)/cpu/x86/smm/smm.ld - $(LD_smm) $(LDFLAGS_smm) -o $(obj)/smm/smm.elf -T $(src)/cpu/x86/smm/smm.ld $(obj)/smm/smm.o +$(obj)/smm/smm: $(obj)/smm/smm.a $(src)/cpu/x86/smm/smm.ld + $(LD_smm) $(LDFLAGS_smm) $(COMPILER_RT_FLAGS_smm) -o $(obj)/smm/smm.elf -T $(src)/cpu/x86/smm/smm.ld -Wl,--whole-archive,--start-group $(obj)/smm/smm.a -Wl,--no-whole-archive $(COMPILER_RT_smm) -Wl,--end-group $(NM_smm) -n $(obj)/smm/smm.elf | sort > $(obj)/smm/smm.map $(OBJCOPY_smm) -O binary $(obj)/smm/smm.elf $@ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index adcd16a..768331b 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -290,7 +290,7 @@ # rmdoule is named $(1).rmod define rmodule_link $(strip $(1)): $(strip $(2)) $$(COMPILER_RT_rmodules_$(4)) $(call src-to-obj,rmodules_$(4),src/lib/rmodule.ld) | $$(RMODTOOL) - $$(LD_rmodules_$(4)) $$(LDFLAGS_rmodules_$(4)) $(RMODULE_LDFLAGS) -T $(call src-to-obj,rmodules_$(4),src/lib/rmodule.ld) -Wl,--defsym=__heap_size=$(strip $(3)) -o $$@ -Wl,--whole-archive,--start-group $(filter-out %.ld,$(2)) -Wl,--end-group + $$(LD_rmodules_$(4)) $$(LDFLAGS_rmodules_$(4)) $$(COMPILER_RT_FLAGS_rmodules_$(4)) $(RMODULE_LDFLAGS) -T $(call src-to-obj,rmodules_$(4),src/lib/rmodule.ld) -Wl,--defsym=__heap_size=$(strip $(3)) -o $$@ -Wl,--whole-archive,--start-group $(filter-out %.ld,$(2)) -Wl,--no-whole-archive $$(COMPILER_RT_rmodules_$(4)) -Wl,--end-group $$(NM_rmodules_$(4)) -n $$@ > $$(basename $$(a)).map endef -- To view, visit https://review.coreboot.org/c/coreboot/+/40812 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I122a4542d1e98d89545897d5177c93ee463d0cdb Gerrit-Change-Number: 40812 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

1 week, 4 days

Change in coreboot[master]: nb/intel/haswell: Add RMRR for USB devices

by Angel Pons (Code Review)

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43807 ) Change subject: nb/intel/haswell: Add RMRR for USB devices ...................................................................... nb/intel/haswell: Add RMRR for USB devices FIXME: Figure out which address the RMRR corresponds to. VT-d checklist verifies that there's a RMRR entry for USB devices. If said devices are enabled, add the RMRR entry. Tested on Asrock B85M Pro4, verify VT-d check about USB RMRR passes. Change-Id: I800d6d1847f457827d64b39c5b7bbfc9cb04f230 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/acpi.c M src/southbridge/intel/lynxpoint/acpi.c M src/southbridge/intel/lynxpoint/pch.h 3 files changed, 36 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/43807/1 diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c index 6a6a124..5e28c82 100644 --- a/src/northbridge/intel/haswell/acpi.c +++ b/src/northbridge/intel/haswell/acpi.c @@ -87,7 +87,7 @@ acpi_dmar_drhd_fixup(tmp, current); } - return current; + return acpi_create_usb_rmrr(current); } unsigned long northbridge_write_acpi_tables(const struct device *const dev, diff --git a/src/southbridge/intel/lynxpoint/acpi.c b/src/southbridge/intel/lynxpoint/acpi.c index 8fee16b..6a2103b 100644 --- a/src/southbridge/intel/lynxpoint/acpi.c +++ b/src/southbridge/intel/lynxpoint/acpi.c @@ -77,3 +77,36 @@ ssdt->length = current - (unsigned long)ssdt; ssdt->checksum = acpi_checksum((void *)ssdt, ssdt->length); } + +unsigned long acpi_create_usb_rmrr(const unsigned long tmp) +{ + unsigned long current = tmp; + + struct device *const ehc1_dev = pcidev_on_root(0x1d, 0); + struct device *const ehc2_dev = pcidev_on_root(0x1a, 0); + struct device *const xhci_dev = pcidev_on_root(0x14, 0); + + const bool ehc1_enabled = ehc1_dev && ehc1_dev->enabled; + const bool ehc2_enabled = ehc2_dev && ehc2_dev->enabled; + const bool xhci_enabled = xhci_dev && xhci_dev->enabled; + + /* If no USB devices are enabled, do not generate the RMRR entry */ + if (!ehc1_enabled && !ehc2_enabled && !xhci_enabled) + return current; + + /* FIXME: This should be the address of the runtime register space instead! */ + current += acpi_create_dmar_rmrr(current, 0, 0x3e2e0000, 0x3e300000 - 1); + + if (ehc1_enabled) + current += acpi_create_dmar_ds_pci(current, 0, 0x1d, 0); + + if (ehc2_enabled) + current += acpi_create_dmar_ds_pci(current, 0, 0x1a, 0); + + if (xhci_enabled) + current += acpi_create_dmar_ds_pci(current, 0, 0x14, 0); + + acpi_dmar_rmrr_fixup(tmp, current); + + return current; +} diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 9946944..79d9dbc 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -122,6 +122,8 @@ void acpi_create_intel_hpet(acpi_hpet_t * hpet); void acpi_create_serialio_ssdt(acpi_header_t *ssdt); +unsigned long acpi_create_usb_rmrr(const unsigned long tmp); + void enable_usb_bar(void); int early_pch_init(void); void pch_enable_lpc(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/43807 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I800d6d1847f457827d64b39c5b7bbfc9cb04f230 Gerrit-Change-Number: 43807 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 weeks, 4 days

Change in coreboot[master]: haswell: Report only one HPET timer device

by Angel Pons (Code Review)

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43806 ) Change subject: haswell: Report only one HPET timer device ...................................................................... haswell: Report only one HPET timer device VT-d checklist fails if there are multiple devices for a single HPET timer block, and if the bus/dev/fn differs between HPET devices. Tested on Asrock B85M Pro4, verify VT-d check about HPET is successful. Change-Id: I68fd074f5440c634ff3ed28c5d423835c81d33b9 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/acpi.c M src/southbridge/intel/lynxpoint/lpc.c 2 files changed, 4 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/43806/1 diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c index 1df66bc..6a6a124 100644 --- a/src/northbridge/intel/haswell/acpi.c +++ b/src/northbridge/intel/haswell/acpi.c @@ -82,10 +82,8 @@ current += acpi_create_dmar_ds_ioapic(current, 2, PCH_IOAPIC_PCI_BUS, PCH_IOAPIC_PCI_SLOT, 0); - size_t i; - for (i = 0; i < 8; ++i) - current += acpi_create_dmar_ds_msi_hpet(current, 0, PCH_HPET_PCI_BUS, - PCH_HPET_PCI_SLOT, i); + current += acpi_create_dmar_ds_msi_hpet(current, 0, PCH_HPET_PCI_BUS, + PCH_HPET_PCI_SLOT, 0); acpi_dmar_drhd_fixup(tmp, current); } diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 85fab4d..93b45d0 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -370,10 +370,10 @@ u32 reg32; size_t i; - /* Assign unique bus/dev/fn for each HPET */ + /* Assign the same bus/dev/fn for each HPET */ for (i = 0; i < 8; ++i) pci_write_config16(dev, LPC_HnBDF(i), - PCH_HPET_PCI_BUS << 8 | PCH_HPET_PCI_SLOT << 3 | i); + PCH_HPET_PCI_BUS << 8 | PCH_HPET_PCI_SLOT << 3 | 0); /* Move HPET to default address 0xfed00000 and enable it */ reg32 = RCBA32(HPTC); -- To view, visit https://review.coreboot.org/c/coreboot/+/43806 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I68fd074f5440c634ff3ed28c5d423835c81d33b9 Gerrit-Change-Number: 43806 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 weeks, 4 days

Change in coreboot[master]: mb/lenovo/{t420,t420s}: Convert to variant board

by Peter Lemenkov (Code Review)

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40381 ) Change subject: mb/lenovo/{t420,t420s}: Convert to variant board ...................................................................... mb/lenovo/{t420,t420s}: Convert to variant board Change-Id: If117c48cf8e6131b3d25112346d4ddd1ff366009 Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/t420/Kconfig M src/mainboard/lenovo/t420/Kconfig.name M src/mainboard/lenovo/t420/Makefile.inc M src/mainboard/lenovo/t420/board_info.txt M src/mainboard/lenovo/t420/devicetree.cb M src/mainboard/lenovo/t420/early_init.c M src/mainboard/lenovo/t420/gma-mainboard.ads M src/mainboard/lenovo/t420/hda_verb.c A src/mainboard/lenovo/t420/variants/t420/board_info.txt R src/mainboard/lenovo/t420/variants/t420/data.vbt A src/mainboard/lenovo/t420/variants/t420/early_init.c R src/mainboard/lenovo/t420/variants/t420/gpio.c A src/mainboard/lenovo/t420/variants/t420/hda_verb.c A src/mainboard/lenovo/t420/variants/t420/overridetree.cb R src/mainboard/lenovo/t420/variants/t420s/board_info.txt R src/mainboard/lenovo/t420/variants/t420s/data.vbt A src/mainboard/lenovo/t420/variants/t420s/early_init.c R src/mainboard/lenovo/t420/variants/t420s/gpio.c R src/mainboard/lenovo/t420/variants/t420s/hda_verb.c A src/mainboard/lenovo/t420/variants/t420s/overridetree.cb D src/mainboard/lenovo/t420s/Kconfig D src/mainboard/lenovo/t420s/Kconfig.name D src/mainboard/lenovo/t420s/Makefile.inc D src/mainboard/lenovo/t420s/acpi/ec.asl D src/mainboard/lenovo/t420s/acpi/platform.asl D src/mainboard/lenovo/t420s/acpi/superio.asl D src/mainboard/lenovo/t420s/acpi_tables.c D src/mainboard/lenovo/t420s/cmos.default D src/mainboard/lenovo/t420s/cmos.layout D src/mainboard/lenovo/t420s/devicetree.cb D src/mainboard/lenovo/t420s/dsdt.asl D src/mainboard/lenovo/t420s/early_init.c D src/mainboard/lenovo/t420s/gma-mainboard.ads D src/mainboard/lenovo/t420s/mainboard.c D src/mainboard/lenovo/t420s/smihandler.c D src/mainboard/lenovo/t420s/vboot-ro-me_clean.fmd D src/mainboard/lenovo/t420s/vboot-ro.fmd D src/mainboard/lenovo/t420s/vboot-rwa.fmd 38 files changed, 150 insertions(+), 853 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/40381/1 diff --git a/src/mainboard/lenovo/t420/Kconfig b/src/mainboard/lenovo/t420/Kconfig index dfc8ed1..b0523f6 100644 --- a/src/mainboard/lenovo/t420/Kconfig +++ b/src/mainboard/lenovo/t420/Kconfig @@ -1,4 +1,4 @@ -if BOARD_LENOVO_T420 +if BOARD_LENOVO_T420 || BOARD_LENOVO_T420S config BOARD_SPECIFIC_OPTIONS def_bool y @@ -16,7 +16,7 @@ select HAVE_CMOS_DEFAULT select HAVE_ACPI_RESUME select INTEL_INT15 - select DRIVERS_RICOH_RCE822 + select DRIVERS_RICOH_RCE822 if BOARD_LENOVO_T420 select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 select MAINBOARD_HAS_LIBGFXINIT @@ -51,9 +51,19 @@ string default "lenovo/t420" +config VARIANT_DIR + string + default "t420" if BOARD_LENOVO_T420 + default "t420s" if BOARD_LENOVO_T420S + +config OVERRIDE_DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" + config MAINBOARD_PART_NUMBER string - default "ThinkPad T420" + default "ThinkPad T420" if BOARD_LENOVO_T420 + default "ThinkPad T420s" if BOARD_LENOVO_T420S config MAX_CPUS int @@ -81,4 +91,4 @@ config PS2M_EISAID default "LEN0015" -endif # BOARD_LENOVO_T420 +endif # BOARD_LENOVO_T420 || BOARD_LENOVO_T420S diff --git a/src/mainboard/lenovo/t420/Kconfig.name b/src/mainboard/lenovo/t420/Kconfig.name index 75570ad..c43ec9d 100644 --- a/src/mainboard/lenovo/t420/Kconfig.name +++ b/src/mainboard/lenovo/t420/Kconfig.name @@ -1,2 +1,5 @@ config BOARD_LENOVO_T420 bool "ThinkPad T420" + +config BOARD_LENOVO_T420S + bool "ThinkPad T420s" diff --git a/src/mainboard/lenovo/t420/Makefile.inc b/src/mainboard/lenovo/t420/Makefile.inc index 05befdd..df5ca02 100644 --- a/src/mainboard/lenovo/t420/Makefile.inc +++ b/src/mainboard/lenovo/t420/Makefile.inc @@ -15,7 +15,9 @@ smm-y += smihandler.c bootblock-y += gpio.c romstage-y += gpio.c - +ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += variants/$(VARIANT_DIR)/early_init.c bootblock-y += early_init.c +romstage-y += variants/$(VARIANT_DIR)/early_init.c romstage-y += early_init.c diff --git a/src/mainboard/lenovo/t420/board_info.txt b/src/mainboard/lenovo/t420/board_info.txt index c0f04ca..05146ff 100644 --- a/src/mainboard/lenovo/t420/board_info.txt +++ b/src/mainboard/lenovo/t420/board_info.txt @@ -1,3 +1,5 @@ +Vendor name: Lenovo +Board name: ThinkPad T420 baseboard Category: laptop ROM package: SOIC-8 / WSON-8 ROM protocol: SPI diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb index 5ac9cf5..ec4a57a 100644 --- a/src/mainboard/lenovo/t420/devicetree.cb +++ b/src/mainboard/lenovo/t420/devicetree.cb @@ -82,13 +82,7 @@ device pci 1c.3 on smbios_slot_desc "7" "3" "ExpressCard Slot" "8" end # PCIe Port #4 ExpressCard - device pci 1c.4 on - chip drivers/ricoh/rce822 - register "sdwppol" = "1" - register "disable_mask" = "0x87" - device pci 00.0 on end - end - end # PCIe Port #5 (Ricoh SD & FW) + device pci 1c.4 on end # PCIe Port #5 device pci 1c.5 off end # PCIe Port #6 Intel Gigabit Ethernet PHY (not PCIe) device pci 1c.6 off end # PCIe Port #7 device pci 1c.7 off end # PCIe Port #8 diff --git a/src/mainboard/lenovo/t420/early_init.c b/src/mainboard/lenovo/t420/early_init.c index 6c189f4..7a06bf0 100644 --- a/src/mainboard/lenovo/t420/early_init.c +++ b/src/mainboard/lenovo/t420/early_init.c @@ -34,24 +34,6 @@ pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); } -// OC3 set in BIOS to port 2-7, OC7 set in BIOS to port 10-13 -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 1, 0 }, /* P0: system port 4, OC0 */ - { 1, 1, 1 }, /* P1: system port 2 (EHCI debug), OC 1 */ - { 1, 1, -1 }, /* P2: HALF MINICARD (WLAN) no oc */ - { 1, 0, -1 }, /* P3: WWAN, no OC */ - { 1, 0, -1 }, /* P4: smartcard, no OC */ - { 1, 1, -1 }, /* P5: ExpressCard, no OC */ - { 0, 0, -1 }, /* P6: empty */ - { 0, 0, -1 }, /* P7: empty */ - { 1, 1, 4 }, /* P8: system port 3, OC4*/ - { 1, 1, 5 }, /* P9: system port 1 (EHCI debug), OC 5 */ - { 1, 0, -1 }, /* P10: fingerprint reader, no OC */ - { 1, 0, -1 }, /* P11: bluetooth, no OC. */ - { 1, 1, -1 }, /* P12: docking, no OC */ - { 1, 1, -1 }, /* P13: camera (LCD), no OC */ -}; - void mainboard_get_spd(spd_raw_data *spd, bool id_only) { read_spd(&spd[0], 0x50, id_only); diff --git a/src/mainboard/lenovo/t420/gma-mainboard.ads b/src/mainboard/lenovo/t420/gma-mainboard.ads index a26b993..fae3544 100644 --- a/src/mainboard/lenovo/t420/gma-mainboard.ads +++ b/src/mainboard/lenovo/t420/gma-mainboard.ads @@ -1,4 +1,4 @@ --- SPDX-License-Identifier: GPL-2.0-only +-- SPDX-License-Identifier: GPL-2.0-or-later -- This file is part of the coreboot project. with HW.GFX.GMA; diff --git a/src/mainboard/lenovo/t420/hda_verb.c b/src/mainboard/lenovo/t420/hda_verb.c index 690c936..2997587 100644 --- a/src/mainboard/lenovo/t420/hda_verb.c +++ b/src/mainboard/lenovo/t420/hda_verb.c @@ -1,45 +1 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -/* Bits 31:28 - Codec Address */ -/* Bits 27:20 - NID */ -/* Bits 19:8 - Verb ID */ -/* Bits 7:0 - Payload */ - -#include <device/azalia_device.h> - -const u32 cim_verb_data[] = { - 0x14f1506e, /* Codec VID / DID: Conexant CX20590 - schematic shows CX20672 */ - 0x17aa21ce, /* Subsystem ID */ - 13, /* Number of 4 dword sets */ - AZALIA_SUBVENDOR(0, 0x17aa21d2), - AZALIA_PIN_CFG(0, 0x12, 0x90a60140), - AZALIA_PIN_CFG(0, 0x14, 0x90170110), - AZALIA_PIN_CFG(0, 0x15, 0x03211020), - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), - AZALIA_PIN_CFG(0, 0x18, 0x03a11830), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1d, 0x40138205), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), - - /* Misc entries */ - 0x00b707C0, /* Enable PortB as Output with HP amp */ - 0x00d70740, /* Enable PortD as Output */ - 0x0017a200, /* Disable ClkEn of PortSenseTst */ - 0x0017c621, /* Slave Port - Port A used as microphone input for - combo Jack - Master Port - Port B used for Jack Presence Detect - Enable Combo Jack Detection */ - 0x0017a208, /* Enable ClkEn of PortSenseTst */ - 0x00170500, /* Set power state to D0 */ - 0x00170500, /* Padding */ - 0x00170500, /* Padding */ -}; - -const u32 pc_beep_verbs[] = { - 0x02177a00, /* Digital PCBEEP Gain: 0h=-9db, 1h=-6db ... 4h=+3db, 5h=+6db */ -}; - -AZALIA_ARRAY_SIZES; +/* dummy */ diff --git a/src/mainboard/lenovo/t420/variants/t420/board_info.txt b/src/mainboard/lenovo/t420/variants/t420/board_info.txt new file mode 100644 index 0000000..c0f04ca --- /dev/null +++ b/src/mainboard/lenovo/t420/variants/t420/board_info.txt @@ -0,0 +1,6 @@ +Category: laptop +ROM package: SOIC-8 / WSON-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: n +Release year: 2011 diff --git a/src/mainboard/lenovo/t420/data.vbt b/src/mainboard/lenovo/t420/variants/t420/data.vbt similarity index 100% rename from src/mainboard/lenovo/t420/data.vbt rename to src/mainboard/lenovo/t420/variants/t420/data.vbt Binary files differ diff --git a/src/mainboard/lenovo/t420/variants/t420/early_init.c b/src/mainboard/lenovo/t420/variants/t420/early_init.c new file mode 100644 index 0000000..4b71060 --- /dev/null +++ b/src/mainboard/lenovo/t420/variants/t420/early_init.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <southbridge/intel/bd82x6x/pch.h> + +// OC3 set in BIOS to port 2-7, OC7 set in BIOS to port 10-13 +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, /* P0: system port 4, OC0 */ + { 1, 1, 1 }, /* P1: system port 2 (EHCI debug), OC 1 */ + { 1, 1, -1 }, /* P2: HALF MINICARD (WLAN) no oc */ + { 1, 0, -1 }, /* P3: WWAN, no OC */ + { 1, 0, -1 }, /* P4: smartcard, no OC */ + { 1, 1, -1 }, /* P5: ExpressCard, no OC */ + { 0, 0, -1 }, /* P6: empty */ + { 0, 0, -1 }, /* P7: empty */ + { 1, 1, 4 }, /* P8: system port 3, OC4*/ + { 1, 1, 5 }, /* P9: system port 1 (EHCI debug), OC 5 */ + { 1, 0, -1 }, /* P10: fingerprint reader, no OC */ + { 1, 0, -1 }, /* P11: bluetooth, no OC. */ + { 1, 1, -1 }, /* P12: docking, no OC */ + { 1, 1, -1 }, /* P13: camera (LCD), no OC */ +}; diff --git a/src/mainboard/lenovo/t420/gpio.c b/src/mainboard/lenovo/t420/variants/t420/gpio.c similarity index 100% rename from src/mainboard/lenovo/t420/gpio.c rename to src/mainboard/lenovo/t420/variants/t420/gpio.c diff --git a/src/mainboard/lenovo/t420/variants/t420/hda_verb.c b/src/mainboard/lenovo/t420/variants/t420/hda_verb.c new file mode 100644 index 0000000..690c936 --- /dev/null +++ b/src/mainboard/lenovo/t420/variants/t420/hda_verb.c @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +/* Bits 31:28 - Codec Address */ +/* Bits 27:20 - NID */ +/* Bits 19:8 - Verb ID */ +/* Bits 7:0 - Payload */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x14f1506e, /* Codec VID / DID: Conexant CX20590 - schematic shows CX20672 */ + 0x17aa21ce, /* Subsystem ID */ + 13, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x17aa21d2), + AZALIA_PIN_CFG(0, 0x12, 0x90a60140), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x15, 0x03211020), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x03a11830), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40138205), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + + /* Misc entries */ + 0x00b707C0, /* Enable PortB as Output with HP amp */ + 0x00d70740, /* Enable PortD as Output */ + 0x0017a200, /* Disable ClkEn of PortSenseTst */ + 0x0017c621, /* Slave Port - Port A used as microphone input for + combo Jack + Master Port - Port B used for Jack Presence Detect + Enable Combo Jack Detection */ + 0x0017a208, /* Enable ClkEn of PortSenseTst */ + 0x00170500, /* Set power state to D0 */ + 0x00170500, /* Padding */ + 0x00170500, /* Padding */ +}; + +const u32 pc_beep_verbs[] = { + 0x02177a00, /* Digital PCBEEP Gain: 0h=-9db, 1h=-6db ... 4h=+3db, 5h=+6db */ +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/lenovo/t420/variants/t420/overridetree.cb b/src/mainboard/lenovo/t420/variants/t420/overridetree.cb new file mode 100644 index 0000000..c0b503c --- /dev/null +++ b/src/mainboard/lenovo/t420/variants/t420/overridetree.cb @@ -0,0 +1,13 @@ +chip northbridge/intel/sandybridge + device domain 0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + device pci 1c.4 on + chip drivers/ricoh/rce822 + register "sdwppol" = "1" + register "disable_mask" = "0x87" + device pci 00.0 on end + end + end # PCIe Port #5 (Ricoh SD & FW) + end + end +end diff --git a/src/mainboard/lenovo/t420s/board_info.txt b/src/mainboard/lenovo/t420/variants/t420s/board_info.txt similarity index 100% rename from src/mainboard/lenovo/t420s/board_info.txt rename to src/mainboard/lenovo/t420/variants/t420s/board_info.txt diff --git a/src/mainboard/lenovo/t420s/data.vbt b/src/mainboard/lenovo/t420/variants/t420s/data.vbt similarity index 100% rename from src/mainboard/lenovo/t420s/data.vbt rename to src/mainboard/lenovo/t420/variants/t420s/data.vbt Binary files differ diff --git a/src/mainboard/lenovo/t420/variants/t420s/early_init.c b/src/mainboard/lenovo/t420/variants/t420s/early_init.c new file mode 100644 index 0000000..3066da5 --- /dev/null +++ b/src/mainboard/lenovo/t420/variants/t420s/early_init.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <southbridge/intel/bd82x6x/pch.h> + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 0, 1, -1 }, /* P0: empty */ + { 1, 1, 1 }, /* P1: system port 2 (To system port) (EHCI debug), OC 1 */ + { 1, 1, -1 }, /* P2: HALF MINICARD (WLAN) no oc */ + { 1, 0, -1 }, /* P3: WWAN, no OC */ + { 1, 1, -1 }, /* P4: smartcard, no OC */ + { 1, 1, -1 }, /* P5: ExpressCard, no OC */ + { 0, 0, -1 }, /* P6: empty */ + { 0, 0, -1 }, /* P7: empty */ + { 0, 1, -1 }, /* P8: empty (touch panel) */ + { 1, 0, 5 }, /* P9: system port 1 (To USBAO) (EHCI debug), OC 5 */ + { 1, 0, -1 }, /* P10: fingerprint reader, no OC */ + { 1, 1, -1 }, /* P11: bluetooth, no OC. */ + { 1, 1, -1 }, /* P12: docking, no OC */ + { 1, 1, -1 }, /* P13: camera (LCD), no OC */ +}; diff --git a/src/mainboard/lenovo/t420s/gpio.c b/src/mainboard/lenovo/t420/variants/t420s/gpio.c similarity index 100% rename from src/mainboard/lenovo/t420s/gpio.c rename to src/mainboard/lenovo/t420/variants/t420s/gpio.c diff --git a/src/mainboard/lenovo/t420s/hda_verb.c b/src/mainboard/lenovo/t420/variants/t420s/hda_verb.c similarity index 100% rename from src/mainboard/lenovo/t420s/hda_verb.c rename to src/mainboard/lenovo/t420/variants/t420s/hda_verb.c diff --git a/src/mainboard/lenovo/t420/variants/t420s/overridetree.cb b/src/mainboard/lenovo/t420/variants/t420s/overridetree.cb new file mode 100644 index 0000000..e12d7ea --- /dev/null +++ b/src/mainboard/lenovo/t420/variants/t420s/overridetree.cb @@ -0,0 +1,18 @@ +chip northbridge/intel/sandybridge + device domain 0 on + subsystemid 0x17aa 0x21d2 inherit + + device pci 02.0 on + subsystemid 0x17aa 0x21d3 + end # Integrated Graphics Controller + + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + # Enable SATA ports 0 (HDD bay) & 1 (ODD bay) & 2 (mSATA) & 4 (dock) + register "sata_port_map" = "0x17" + + device pci 19.0 on + subsystemid 0x17aa 0x21ce + end # Intel Gigabit Ethernet + end + end +end diff --git a/src/mainboard/lenovo/t420s/Kconfig b/src/mainboard/lenovo/t420s/Kconfig deleted file mode 100644 index e2fd824..0000000 --- a/src/mainboard/lenovo/t420s/Kconfig +++ /dev/null @@ -1,83 +0,0 @@ -if BOARD_LENOVO_T420S - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select SYSTEM_TYPE_LAPTOP - select NORTHBRIDGE_INTEL_SANDYBRIDGE - select USE_NATIVE_RAMINIT - select SOUTHBRIDGE_INTEL_BD82X6X - select EC_LENOVO_PMH7 - select EC_LENOVO_H8 - select H8_HAS_BAT_TRESHOLDS_IMPL - select NO_UART_ON_SUPERIO - select BOARD_ROMSIZE_KB_8192 - select HAVE_ACPI_TABLES - select HAVE_OPTION_TABLE - select HAVE_CMOS_DEFAULT - select HAVE_ACPI_RESUME - select INTEL_INT15 - select MAINBOARD_HAS_LPC_TPM - select MAINBOARD_HAS_TPM1 - select MAINBOARD_HAS_LIBGFXINIT - select GFX_GMA_PANEL_1_ON_LVDS - select DRIVERS_LENOVO_HYBRID_GRAPHICS - select INTEL_GMA_HAVE_VBT - select MAINBOARD_USES_IFD_GBE_REGION - - # Workaround for EC/KBC IRQ1. - select SERIRQ_CONTINUOUS_MODE - -config VBOOT - select VBOOT_VBNV_CMOS - select GBB_FLAG_DISABLE_LID_SHUTDOWN - select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC - select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC - select GBB_FLAG_DISABLE_FWMP - select HAS_RECOVERY_MRC_CACHE - -config VBOOT_SLOTS_RW_A - default y - -config VBOOT_VBNV_OFFSET - hex - default 0x2a - -config FMDFILE - string - default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT - -config MAINBOARD_DIR - string - default "lenovo/t420s" - -config MAINBOARD_PART_NUMBER - string - default "ThinkPad T420s" - -config MAX_CPUS - int - default 8 - -config USBDEBUG_HCD_INDEX - int - default 2 - -config DRAM_RESET_GATE_GPIO - int - default 10 - -config VGA_BIOS_FILE - string - default "pci8086,0126.rom" - -config VGA_BIOS_ID - string - default "8086,0126" - -config PS2K_EISAID - default "PNP0303" - -config PS2M_EISAID - default "LEN0015" - -endif # BOARD_LENOVO_T420S diff --git a/src/mainboard/lenovo/t420s/Kconfig.name b/src/mainboard/lenovo/t420s/Kconfig.name deleted file mode 100644 index 648688b..0000000 --- a/src/mainboard/lenovo/t420s/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_LENOVO_T420S - bool "ThinkPad T420s" diff --git a/src/mainboard/lenovo/t420s/Makefile.inc b/src/mainboard/lenovo/t420s/Makefile.inc deleted file mode 100644 index 05befdd..0000000 --- a/src/mainboard/lenovo/t420s/Makefile.inc +++ /dev/null @@ -1,21 +0,0 @@ -## -## This file is part of the coreboot project. -## -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -smm-y += smihandler.c -bootblock-y += gpio.c -romstage-y += gpio.c - -ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads -bootblock-y += early_init.c -romstage-y += early_init.c diff --git a/src/mainboard/lenovo/t420s/acpi/ec.asl b/src/mainboard/lenovo/t420s/acpi/ec.asl deleted file mode 100644 index 2dda5ec..0000000 --- a/src/mainboard/lenovo/t420s/acpi/ec.asl +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -#include <ec/lenovo/h8/acpi/ec.asl> - -Scope(\_SB.PCI0.LPCB.EC) -{ -} - -#include <ec/lenovo/h8/acpi/thinkpad_bat_thresholds_b0.asl> diff --git a/src/mainboard/lenovo/t420s/acpi/platform.asl b/src/mainboard/lenovo/t420s/acpi/platform.asl deleted file mode 100644 index dc46182..0000000 --- a/src/mainboard/lenovo/t420s/acpi/platform.asl +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -/* The _PTS method (Prepare To Sleep) is called before the OS is - * entering a sleep state. The sleep state number is passed in Arg0 - */ - -Method(_PTS,1) -{ - \_SB.PCI0.LPCB.EC.MUTE(1) - \_SB.PCI0.LPCB.EC.USBP(0) - \_SB.PCI0.LPCB.EC.RADI(0) -} - -/* The _WAK method is called on system wakeup */ - -Method(_WAK,1) -{ - /* ME may not be up yet. */ - Store (0, \_TZ.MEB1) - Store (0, \_TZ.MEB2) - - /* Wake the HKEY to init BT/WWAN */ - \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) - - /* Not implemented. */ - Return(Package(){0,0}) -} diff --git a/src/mainboard/lenovo/t420s/acpi/superio.asl b/src/mainboard/lenovo/t420s/acpi/superio.asl deleted file mode 100644 index f2b35ba..0000000 --- a/src/mainboard/lenovo/t420s/acpi/superio.asl +++ /dev/null @@ -1 +0,0 @@ -#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/lenovo/t420s/acpi_tables.c b/src/mainboard/lenovo/t420s/acpi_tables.c deleted file mode 100644 index 65c6019..0000000 --- a/src/mainboard/lenovo/t420s/acpi_tables.c +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -#include <southbridge/intel/bd82x6x/nvs.h> - -void acpi_create_gnvs(global_nvs_t *gnvs) -{ - /* The lid is open by default */ - gnvs->lids = 1; - - /* Temperature at which OS will shutdown */ - gnvs->tcrt = 100; - /* Temperature at which OS will throttle CPU */ - gnvs->tpsv = 90; -} diff --git a/src/mainboard/lenovo/t420s/cmos.default b/src/mainboard/lenovo/t420s/cmos.default deleted file mode 100644 index 467f965..0000000 --- a/src/mainboard/lenovo/t420s/cmos.default +++ /dev/null @@ -1,16 +0,0 @@ -boot_option=Fallback -debug_level=Debug -power_on_after_fail=Disable -nmi=Enable -volume=0x3 -first_battery=Primary -bluetooth=Enable -wwan=Enable -wlan=Enable -touchpad=Enable -sata_mode=AHCI -fn_ctrl_swap=Disable -sticky_fn=Disable -trackpoint=Enable -hybrid_graphics_mode=Integrated Only -usb_always_on=Disable diff --git a/src/mainboard/lenovo/t420s/cmos.layout b/src/mainboard/lenovo/t420s/cmos.layout deleted file mode 100644 index 26e6300..0000000 --- a/src/mainboard/lenovo/t420s/cmos.layout +++ /dev/null @@ -1,141 +0,0 @@ -## -## This file is part of the coreboot project. -## -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -# ----------------------------------------------------------------- -entries - -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused - -# ----------------------------------------------------------------- -# RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? - -# ----------------------------------------------------------------- -# coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused - -#400 8 r 0 reserved for century byte - -# coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail - -# coreboot config options: EC -411 1 e 8 first_battery -412 1 e 1 bluetooth -413 1 e 1 wwan -414 1 e 1 touchpad -415 1 e 1 wlan -416 1 e 1 trackpoint -417 1 e 1 fn_ctrl_swap -418 1 e 1 sticky_fn -419 1 e 1 power_management_beeps -421 1 e 9 sata_mode -422 2 e 13 usb_always_on - -# coreboot config options: cpu -#424 8 r 0 unused - -# coreboot config options: northbridge -432 3 e 11 gfx_uma_size -435 2 e 12 hybrid_graphics_mode -#437 3 r 0 unused - -440 8 h 0 volume - -# VBOOT -448 128 r 0 vbnv - -# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 -960 16 r 0 mrc_scrambler_seed_chk - -# coreboot config options: check sums -984 16 h 0 check_sum - -# ----------------------------------------------------------------- - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 Secondary -8 1 Primary -9 0 AHCI -9 1 Compatible -10 0 Both -10 1 Keyboard only -10 2 Thinklight only -10 3 None -11 0 32M -11 1 64M -11 2 96M -11 3 128M -11 4 160M -11 5 192M -11 6 224M -12 0 Integrated Only -12 1 Discrete Only -12 2 Dual Graphics -13 0 Disable -13 1 AC and battery -13 2 AC only - -# ----------------------------------------------------------------- -checksums - -checksum 392 447 984 diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb deleted file mode 100644 index b3399c3..0000000 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ /dev/null @@ -1,175 +0,0 @@ -chip northbridge/intel/sandybridge - # IGD Displays - register "gfx" = "GMA_STATIC_DISPLAYS(1)" - - # Enable DisplayPort Hotplug with 6ms pulse - register "gpu_dp_d_hotplug" = "0x06" - - # Enable Panel as LVDS and configure power delays - register "gpu_panel_port_select" = "0" # LVDS - register "gpu_panel_power_cycle_delay" = "1" - register "gpu_panel_power_up_delay" = "300" # T1+T2: 30ms - register "gpu_panel_power_down_delay" = "300" # T5+T6: 30ms - register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms - register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms - register "gpu_cpu_backlight" = "0x1155" - register "gpu_pch_backlight" = "0x06100610" - - device cpu_cluster 0 on - chip cpu/intel/model_206ax - # Magic APIC ID to locate this chip - device lapic 0x0 on end - device lapic 0xacac off end - - register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) - - register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) - end - end - - register "pci_mmio_size" = "2048" - - device domain 0 on - subsystemid 0x17aa 0x21d2 inherit - - device pci 00.0 on end # host bridge - device pci 01.0 on end # NVIDIA Corporation GF119M [NVS 4200M] - device pci 02.0 on - subsystemid 0x17aa 0x21d3 - end # Integrated Graphics Controller - - chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - # GPI routing - # 0 No effect (default) - # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) - # 2 SCI (if corresponding GPIO_EN bit is also set) - register "alt_gp_smi_en" = "0x0000" - register "gpi1_routing" = "2" - register "gpi13_routing" = "2" - - # Enable SATA ports 0 (HDD bay) & 1 (ODD bay) & 2 (mSATA) & 4 (dock) - register "sata_port_map" = "0x17" - # Set max SATA speed to 6.0 Gb/s - register "sata_interface_speed_support" = "0x3" - - register "gen1_dec" = "0x7c1601" - register "gen2_dec" = "0x0c15e1" - register "gen4_dec" = "0x0c06a1" - - register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" - - # Enable zero-based linear PCIe root port functions - register "pcie_port_coalesce" = "1" - - register "c2_latency" = "101" # c2 not supported - - # device specific SPI configuration - register "spi_uvscc" = "0x2005" - register "spi_lvscc" = "0x2005" - - device pci 16.0 off end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 on - subsystemid 0x17aa 0x21ce - end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB Enhanced Host Controller #2 - device pci 1b.0 on end # High Definition Audio Controller - device pci 1c.0 off end # PCIe Port #1 - device pci 1c.1 on end # PCIe Port #2 Integrated Wireless LAN - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 on - smbios_slot_desc "7" "3" "ExpressCard Slot" "8" - end # PCIe Port #4 ExpressCard - device pci 1c.4 on end # PCIe Port #5 NEC Corporation uPD720200A USB 3.0 Host Controller - device pci 1c.5 off end # PCIe Port #6 Intel Gigabit Ethernet PHY (not PCIe) - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB Enhanced Host Controller #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on - chip ec/lenovo/pmh7 - device pnp ff.1 on end # dummy - register "backlight_enable" = "0x01" - register "dock_event_enable" = "0x01" - end - - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - - chip ec/lenovo/h8 - device pnp ff.2 on # dummy - io 0x60 = 0x62 - io 0x62 = 0x66 - io 0x64 = 0x1600 - io 0x66 = 0x1604 - end - - register "config0" = "0xa7" - register "config1" = "0x01" - register "config2" = "0xa0" - register "config3" = "0xe2" - - register "has_keyboard_backlight" = "0" - - register "beepmask0" = "0x02" - register "beepmask1" = "0x86" - register "has_power_management_beeps" = "1" - register "event2_enable" = "0xff" - register "event3_enable" = "0xff" - register "event4_enable" = "0xf0" - register "event5_enable" = "0x3c" - register "event6_enable" = "0x00" - register "event7_enable" = "0xa1" - register "event8_enable" = "0x7b" - register "event9_enable" = "0xff" - register "eventa_enable" = "0x00" - register "eventb_enable" = "0x00" - register "eventc_enable" = "0xff" - register "eventd_enable" = "0xff" - register "evente_enable" = "0x0d" - - register "has_bdc_detection" = "1" - register "bdc_gpio_num" = "54" - register "bdc_gpio_lvl" = "0" - end - chip drivers/lenovo/hybrid_graphics - device pnp ff.f on end # dummy - - register "detect_gpio" = "21" - - register "has_panel_hybrid_gpio" = "1" - register "panel_hybrid_gpio" = "52" - register "panel_integrated_lvl" = "1" - - register "has_backlight_gpio" = "0" - register "has_dgpu_power_gpio" = "0" - - register "has_thinker1" = "1" - end - end # LPC Controller - device pci 1f.2 on end # 6 port SATA AHCI Controller - device pci 1f.3 on - # eeprom, 8 virtual devices, same chip - chip drivers/i2c/at24rf08c - device i2c 54 on end - device i2c 55 on end - device i2c 56 on end - device i2c 57 on end - device i2c 5c on end - device i2c 5d on end - device i2c 5e on end - device i2c 5f on end - end - end # SMBus Controller - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 on end # Thermal - end - end -end diff --git a/src/mainboard/lenovo/t420s/dsdt.asl b/src/mainboard/lenovo/t420s/dsdt.asl deleted file mode 100644 index a03b252..0000000 --- a/src/mainboard/lenovo/t420s/dsdt.asl +++ /dev/null @@ -1,40 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -#define THINKPAD_EC_GPE 17 -#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB -#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 -#define EC_LENOVO_H8_ME_WORKAROUND 1 - -#include <arch/acpi.h> -DefinitionBlock( - "dsdt.aml", - "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up - OEM_ID, - ACPI_TABLE_CREATOR, - 0x20110725 // OEM revision -) -{ - #include <southbridge/intel/common/acpi/platform.asl> - - #include "acpi/platform.asl" - - // global NVS and variables - #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> - - #include <cpu/intel/common/acpi/cpu.asl> - - Scope (\_SB) { - Device (PCI0) - { - #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> - #include <southbridge/intel/bd82x6x/acpi/pch.asl> - - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> - } - } - - #include <southbridge/intel/common/acpi/sleepstates.asl> -} diff --git a/src/mainboard/lenovo/t420s/early_init.c b/src/mainboard/lenovo/t420s/early_init.c deleted file mode 100644 index 4f5f69d..0000000 --- a/src/mainboard/lenovo/t420s/early_init.c +++ /dev/null @@ -1,63 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -#include <device/pci_ops.h> -#include <northbridge/intel/sandybridge/raminit_native.h> -#include <southbridge/intel/bd82x6x/pch.h> -#include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h> -#include <northbridge/intel/sandybridge/sandybridge.h> -#include <device/device.h> - -static void hybrid_graphics_init(void) -{ - bool peg, igd; - u32 reg32; - - early_hybrid_graphics(&igd, &peg); - - if (peg && igd) - return; - - /* Hide disabled devices */ - reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); - reg32 &= ~(DEVEN_PEG10 | DEVEN_IGD); - - if (peg) - reg32 |= DEVEN_PEG10; - - if (igd) - reg32 |= DEVEN_IGD; - else - /* Disable IGD VGA decode, no GTT or GFX stolen */ - pci_write_config16(PCI_DEV(0, 0, 0), GGC, 2); - - pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); -} - -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 0, 1, -1 }, /* P0: empty */ - { 1, 1, 1 }, /* P1: system port 2 (To system port) (EHCI debug), OC 1 */ - { 1, 1, -1 }, /* P2: HALF MINICARD (WLAN) no oc */ - { 1, 0, -1 }, /* P3: WWAN, no OC */ - { 1, 1, -1 }, /* P4: smartcard, no OC */ - { 1, 1, -1 }, /* P5: ExpressCard, no OC */ - { 0, 0, -1 }, /* P6: empty */ - { 0, 0, -1 }, /* P7: empty */ - { 0, 1, -1 }, /* P8: empty (touch panel) */ - { 1, 0, 5 }, /* P9: system port 1 (To USBAO) (EHCI debug), OC 5 */ - { 1, 0, -1 }, /* P10: fingerprint reader, no OC */ - { 1, 1, -1 }, /* P11: bluetooth, no OC. */ - { 1, 1, -1 }, /* P12: docking, no OC */ - { 1, 1, -1 }, /* P13: camera (LCD), no OC */ -}; - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x51, id_only); -} - -void mainboard_early_init(int s3resume) -{ - hybrid_graphics_init(); -} diff --git a/src/mainboard/lenovo/t420s/gma-mainboard.ads b/src/mainboard/lenovo/t420s/gma-mainboard.ads deleted file mode 100644 index fae3544..0000000 --- a/src/mainboard/lenovo/t420s/gma-mainboard.ads +++ /dev/null @@ -1,23 +0,0 @@ --- SPDX-License-Identifier: GPL-2.0-or-later --- This file is part of the coreboot project. - -with HW.GFX.GMA; -with HW.GFX.GMA.Display_Probing; - -use HW.GFX.GMA; -use HW.GFX.GMA.Display_Probing; - -private package GMA.Mainboard is - - ports : constant Port_List := - (DP1, - DP2, - DP3, - HDMI1, - HDMI2, - HDMI3, - Analog, - LVDS, - others => Disabled); - -end GMA.Mainboard; diff --git a/src/mainboard/lenovo/t420s/mainboard.c b/src/mainboard/lenovo/t420s/mainboard.c deleted file mode 100644 index 0890151..0000000 --- a/src/mainboard/lenovo/t420s/mainboard.c +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -#include <device/device.h> -#include <drivers/intel/gma/int15.h> -#include <ec/lenovo/h8/h8.h> - -static void mainboard_enable(struct device *dev) -{ - install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, - GMA_INT15_PANEL_FIT_DEFAULT, - GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/lenovo/t420s/smihandler.c b/src/mainboard/lenovo/t420s/smihandler.c deleted file mode 100644 index 4432995..0000000 --- a/src/mainboard/lenovo/t420s/smihandler.c +++ /dev/null @@ -1,69 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -#include <arch/io.h> -#include <console/console.h> -#include <cpu/x86/smm.h> -#include <ec/acpi/ec.h> -#include <ec/lenovo/h8/h8.h> -#include <southbridge/intel/bd82x6x/pch.h> -#include <southbridge/intel/common/pmutil.h> - -#define GPE_EC_SCI 1 -#define GPE_EC_WAKE 13 - -static void mainboard_smi_handle_ec_sci(void) -{ - u8 status = inb(EC_SC); - u8 event; - - if (!(status & EC_SCI_EVT)) - return; - - event = ec_query(); - printk(BIOS_DEBUG, "EC event %02x\n", event); -} - -void mainboard_smi_gpi(u32 gpi_sts) -{ - if (gpi_sts & (1 << GPE_EC_SCI)) - mainboard_smi_handle_ec_sci(); -} - -int mainboard_smi_apmc(u8 data) -{ - switch (data) { - case APM_CNT_ACPI_ENABLE: - /* use 0x1600/0x1604 to prevent races with userspace */ - ec_set_ports(0x1604, 0x1600); - /* route EC_SCI to SCI */ - gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI); - /* discard all events, and enable attention */ - ec_write(0x80, 0x01); - break; - case APM_CNT_ACPI_DISABLE: - /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't - provide a EC query function */ - ec_set_ports(0x66, 0x62); - /* route EC_SCI to SMI */ - gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI); - /* discard all events, and enable attention */ - ec_write(0x80, 0x01); - break; - default: - break; - } - return 0; -} - -void mainboard_smi_sleep(u8 slp_typ) -{ - if (slp_typ == 3) { - u8 ec_wake = ec_read(0x32); - /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ - if (ec_wake & 0x14) { - /* Redirect EC WAKE GPE to SCI. */ - gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI); - } - } -} diff --git a/src/mainboard/lenovo/t420s/vboot-ro-me_clean.fmd b/src/mainboard/lenovo/t420s/vboot-ro-me_clean.fmd deleted file mode 100644 index d1cbff7..0000000 --- a/src/mainboard/lenovo/t420s/vboot-ro-me_clean.fmd +++ /dev/null @@ -1,22 +0,0 @@ -FLASH@0xff800000 0x800000 { - SI_ALL 0x20000 { - SI_DESC 0x1000 - SI_GBE 0x2000 - SI_ME - } - SI_BIOS 0x7e0000 { - UNIFIED_MRC_CACHE 0x20000 { - RECOVERY_MRC_CACHE 0x10000 - RW_MRC_CACHE 0x10000 - } - - WP_RO { - FMAP 0x800 - RO_FRID 0x40 - RO_PADDING 0x7c0 - RO_VPD(PRESERVE) 0x1000 - GBB 0x1e000 - COREBOOT(CBFS) - } - } -} diff --git a/src/mainboard/lenovo/t420s/vboot-ro.fmd b/src/mainboard/lenovo/t420s/vboot-ro.fmd deleted file mode 100644 index 51df8a5..0000000 --- a/src/mainboard/lenovo/t420s/vboot-ro.fmd +++ /dev/null @@ -1,22 +0,0 @@ -FLASH@0xff800000 0x800000 { - SI_ALL 0x500000 { - SI_DESC 0x1000 - SI_GBE 0x2000 - SI_ME 0x4ed000 - } - SI_BIOS 0x300000 { - UNIFIED_MRC_CACHE 0x20000 { - RECOVERY_MRC_CACHE 0x10000 - RW_MRC_CACHE 0x10000 - } - - WP_RO { - FMAP 0x800 - RO_FRID 0x40 - RO_PADDING 0x7c0 - RO_VPD(PRESERVE) 0x1000 - GBB 0x1e000 - COREBOOT(CBFS) - } - } -} diff --git a/src/mainboard/lenovo/t420s/vboot-rwa.fmd b/src/mainboard/lenovo/t420s/vboot-rwa.fmd deleted file mode 100644 index 8a4cd3b..0000000 --- a/src/mainboard/lenovo/t420s/vboot-rwa.fmd +++ /dev/null @@ -1,29 +0,0 @@ -FLASH@0xff800000 0x800000 { - SI_ALL@0x0 0x500000 { - SI_DESC@0x0 0x1000 - SI_GBE@0x1000 0x2000 - SI_ME@0x3000 0x4ed000 - } - SI_BIOS@0x500000 0x300000 { - RW_SECTION_A@0x00000 0x180000 { - VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x16ffc0 - RW_FWID_A@0x17ffc0 0x40 - } - UNIFIED_MRC_CACHE@0x180000 0x20000 { - RECOVERY_MRC_CACHE@0x0 0x10000 - RW_MRC_CACHE@0x10000 0x10000 - } - RW_VPD(PRESERVE)@0x1a0000 0x1000 - SMMSTORE(PRESERVE)@0x1a1000 0x40000 - - WP_RO@0x1e1000 0x11f000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_PADDING@0x840 0x7c0 - RO_VPD(PRESERVE)@0x1000 0x1000 - GBB@0x2000 0x1e000 - COREBOOT(CBFS)@0x20000 0xff000 - } - } -} -- To view, visit https://review.coreboot.org/c/coreboot/+/40381 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If117c48cf8e6131b3d25112346d4ddd1ff366009 Gerrit-Change-Number: 40381 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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coreboot-gerrit January 2022