Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47429 )
Change subject: nb/intel/sandybridge: Clarify RAM overclock options
......................................................................
nb/intel/sandybridge: Clarify RAM overclock options
Rewrite them to more accurately describe what they are about.
Change-Id: Icb0ac1e592b662bbb81da431ff97af1a00f952c0
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M src/northbridge/intel/sandybridge/Kconfig
1 file changed, 7 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/47429/1
diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig
index ef6dc3d..b4834cd 100644
--- a/src/northbridge/intel/sandybridge/Kconfig
+++ b/src/northbridge/intel/sandybridge/Kconfig
@@ -44,19 +44,19 @@
System Agent/MRC.bin. You should answer Y.
config NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES
- bool "Ignore vendor programmed fuses that limit max. DRAM frequency"
+ bool "[OVERCLOCKING] Ignore CAPID fuses that limit max. DRAM frequency"
default n
depends on USE_NATIVE_RAMINIT
help
- Ignore the mainboard's vendor programmed fuses that might limit the
- maximum DRAM frequency. By selecting this option the fuses will be
- ignored and the only limits on DRAM frequency are set by RAM's SPD and
- hard fuses in southbridge's clockgen.
- Disabled by default as it might causes system instability.
+ Ignore the CAPID fuses and devicetree settings that might limit the
+ maximum DRAM frequency on overclocking-capable parts. By selecting
+ this option, the fuse values will be ignored and the only limits on
+ DRAM frequency are determined by SPD values and hard limits in the
+ northbridge's MPLL. Disabled by default as it can cause instability.
Handle with care!
config NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS
- bool "Ignore XMP profile max DIMMs per channel"
+ bool "[OVERCLOCKING] Ignore XMP profile max DIMMs per channel"
default n
depends on USE_NATIVE_RAMINIT
help
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Icb0ac1e592b662bbb81da431ff97af1a00f952c0
Gerrit-Change-Number: 47429
Gerrit-PatchSet: 1
Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com>
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Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42806 )
Change subject: bootsplash: Allow bootsplash compression
......................................................................
bootsplash: Allow bootsplash compression
TEST=include BMP bootsplash and select the compression, boot Protectli
FW6 with SeaBIOS and observe the bootsplash on the screen
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Change-Id: Id9abc6f72e3f82ce60cd06376cdc4f49f0198823
---
M Makefile.inc
M src/Kconfig
2 files changed, 16 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/42806/1
diff --git a/Makefile.inc b/Makefile.inc
index 7f61a5e..af931f7 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -1218,9 +1218,16 @@
revision-type := raw
BOOTSPLASH_SUFFIX=$(suffix $(call strip_quotes,$(CONFIG_BOOTSPLASH_FILE)))
+ifeq ($(CONFIG_COMPRESS_BOOTSPLASH),)
cbfs-files-$(CONFIG_BOOTSPLASH_IMAGE) += bootsplash$(BOOTSPLASH_SUFFIX)
bootsplash$(BOOTSPLASH_SUFFIX)-file := $(call strip_quotes,$(CONFIG_BOOTSPLASH_FILE))
bootsplash$(BOOTSPLASH_SUFFIX)-type := bootsplash
+else
+cbfs-files-$(CONFIG_BOOTSPLASH_IMAGE) += bootsplash$(BOOTSPLASH_SUFFIX).lzma
+bootsplash$(BOOTSPLASH_SUFFIX).lzma-file := $(call strip_quotes,$(CONFIG_BOOTSPLASH_FILE))
+bootsplash$(BOOTSPLASH_SUFFIX).lzma-compression := $(CBFS_COMPRESS_FLAG)
+bootsplash$(BOOTSPLASH_SUFFIX).lzma-type := bootsplash
+endif
# Ensure that no payload segment overlaps with memory regions used by ramstage
# (not for x86 since it can relocate itself in that case)
diff --git a/src/Kconfig b/src/Kconfig
index 1b49e2b..ec3a274 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -315,6 +315,15 @@
This will only add the image to the ROM. To actually run it check
options under 'Display' section.
+config COMPRESS_BOOTSPLASH
+ bool "Compress bootsplash image"
+ depends on PAYLOAD_SEABIOS
+ help
+ The bootsplash image can be compressed with LZMA. This is especially
+ useful when BMP bootsplash is used and occupies too much SPI flash
+ space. The bootsplash CBFS file name will be compressed and suffixed
+ with lzma extension to indicate SeaBIOS to decompress it when loaded.
+
config BOOTSPLASH_FILE
string "Bootsplash path and filename"
depends on BOOTSPLASH_IMAGE
--
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Gerrit-Project: coreboot
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Gerrit-Change-Id: Id9abc6f72e3f82ce60cd06376cdc4f49f0198823
Gerrit-Change-Number: 42806
Gerrit-PatchSet: 1
Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Gerrit-MessageType: newchange
Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47148 )
Change subject: drivers/intel/dptf: Generate ACPI identifiers only for enabled devices
......................................................................
drivers/intel/dptf: Generate ACPI identifiers only for enabled devices
DPTF configuration can be applied based on firmware configuration. Hence
generate ACPI identifiers only for enabled devices.
BUG=b:170229672
TEST=Build and boot to OS in Drawlat and Drawcia. Ensure that the ACPI
identifier is enabled only for enabled devices.
Change-Id: Ib042bec7e8c68b38fafa60a8e965d781bddcd1f0
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
---
M src/drivers/intel/dptf/dptf.c
1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/47148/1
diff --git a/src/drivers/intel/dptf/dptf.c b/src/drivers/intel/dptf/dptf.c
index 0f1cc9c..e0e2202 100644
--- a/src/drivers/intel/dptf/dptf.c
+++ b/src/drivers/intel/dptf/dptf.c
@@ -232,6 +232,9 @@
{
struct drivers_intel_dptf_config *config = config_of(dev);
+ if (!dev->enabled)
+ return;
+
write_device_definitions(dev);
write_policies(config);
write_controls(config);
--
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Gerrit-Change-Id: Ib042bec7e8c68b38fafa60a8e965d781bddcd1f0
Gerrit-Change-Number: 47148
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Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
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Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35739 )
Change subject: soc/intel/common/block: Update microcode for each core
......................................................................
soc/intel/common/block: Update microcode for each core
On Hyper-Threading enabled platform update the microcde only once
for each core, not for each thread.
Follow Intel Software Developer Guidelines as the added comment
also states.
Change-Id: I72804753e567a137a5648ca6950009fed332531b
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/soc/intel/common/block/cpu/mp_init.c
1 file changed, 20 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/35739/1
diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c
index 2c5061f..e7689cf 100644
--- a/src/soc/intel/common/block/cpu/mp_init.c
+++ b/src/soc/intel/common/block/cpu/mp_init.c
@@ -26,6 +26,7 @@
#include <intelblocks/fast_spi.h>
#include <intelblocks/mp_init.h>
#include <intelblocks/msr.h>
+#include <cpu/intel/common/common.h>
#include <soc/cpu.h>
static const void *microcode_patch;
@@ -44,7 +45,24 @@
static void init_one_cpu(struct device *dev)
{
soc_core_init(dev);
- intel_microcode_load_unlocked(microcode_patch);
+
+ /*
+ * Update just on the first CPU in the core. Other siblings
+ * get the update automatically according to Document: 253668-060US
+ * Intel SDM Chapter 9.11.6.3
+ * "Update in a System Supporting Intel Hyper-Threading Technology"
+ * Intel Hyper-Threading Technology has implications on the loading of the
+ * microcode update. The update must be loaded for each core in a physical
+ * processor. Thus, for a processor supporting Intel Hyper-Threading
+ * Technology, only one logical processor per core is required to load the
+ * microcode update. Each individual logical processor can independently
+ * load the update. However, MP initialization must provide some mechanism
+ * (e.g. a software semaphore) to force serialization of microcode update
+ * loads and to prevent simultaneous load attempts to the same core.
+ */
+ if (!intel_ht_sibling()) {
+ intel_microcode_load_unlocked(microcode_patch);
+ }
}
static struct device_operations cpu_dev_ops = {
@@ -141,6 +159,7 @@
if (CONFIG(USE_INTEL_FSP_MP_INIT))
return;
+ /* Update microcode on BSP */
microcode_patch = intel_microcode_find();
intel_microcode_load_unlocked(microcode_patch);
--
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