November 2019 - coreboot-gerrit

Change in coreboot[master]: trogdor: QCSDI loading depends on VB2_GBB_FLAG_FAFT_KEY_OVERIDE setting

by mturney mturney (Code Review)

Hello ashk(a)codeaurora.org, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/36518 to review the following change. Change subject: trogdor: QCSDI loading depends on VB2_GBB_FLAG_FAFT_KEY_OVERIDE setting ...................................................................... trogdor: QCSDI loading depends on VB2_GBB_FLAG_FAFT_KEY_OVERIDE setting Change-Id: I63f35c94bc6c60934ace5fe0fd9176443059b354 Signed-off-by: Ashwin Kumar <ashk(a)codeaurora.org> --- M src/soc/qualcomm/common/qclib.c M src/soc/qualcomm/sc7180/Makefile.inc 2 files changed, 15 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/36518/1 diff --git a/src/soc/qualcomm/common/qclib.c b/src/soc/qualcomm/common/qclib.c index ac80a76..7f3dfa8 100644 --- a/src/soc/qualcomm/common/qclib.c +++ b/src/soc/qualcomm/common/qclib.c @@ -26,6 +26,7 @@ #include <soc/mmu_common.h> #include <soc/qclib_common.h> #include <soc/symbols_common.h> +#include <security/vboot/gbb.h> struct qclib_cb_if_table qclib_cb_if_table = { .magic = QCLIB_MAGIC_NUMBER, @@ -158,19 +159,22 @@ QCLIB_GA_ENABLE_UART_LOGGING; if (CONFIG(QC_SDI_ENABLE)) { - struct prog qcsdi = - PROG_INIT(PROG_REFCODE, CONFIG_CBFS_PREFIX "/qcsdi"); + if(!(gbb_is_flag_set(VB2_GBB_FLAG_FAFT_KEY_OVERIDE))) { + struct prog qcsdi = + PROG_INIT(PROG_REFCODE, + CONFIG_CBFS_PREFIX "/qcsdi"); - /* Attempt to load QCSDI elf */ - if (prog_locate(&qcsdi)) - goto fail; + /* Attempt to load QCSDI elf */ + if (prog_locate(&qcsdi)) + goto fail; - if (cbfs_prog_stage_load(&qcsdi)) - goto fail; + if (cbfs_prog_stage_load(&qcsdi)) + goto fail; - qclib_add_if_table_entry(QCLIB_TE_QCSDI, prog_entry(&qcsdi), - prog_size(&qcsdi), 0); - printk(BIOS_INFO, "qcsdi.entry[%p]\n", qcsdi.entry); + qclib_add_if_table_entry(QCLIB_TE_QCSDI, + prog_entry(&qcsdi), prog_size(&qcsdi), 0); + printk(BIOS_INFO, "qcsdi.entry[%p]\n", qcsdi.entry); + } } dump_te_table(); diff --git a/src/soc/qualcomm/sc7180/Makefile.inc b/src/soc/qualcomm/sc7180/Makefile.inc index 66cb35c..695ab88 100644 --- a/src/soc/qualcomm/sc7180/Makefile.inc +++ b/src/soc/qualcomm/sc7180/Makefile.inc @@ -40,6 +40,7 @@ romstage-y += qcom_qup_se.c romstage-$(CONFIG_DRIVERS_UART) += uart.c romstage-$(CONFIG_SC7180_QSPI) += qspi.c +romstage-$(CONFIG_QC_SDI_ENABLE) += ../../../security/vboot/gbb.c ################################################################################ ramstage-y += soc.c -- To view, visit https://review.coreboot.org/c/coreboot/+/36518 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I63f35c94bc6c60934ace5fe0fd9176443059b354 Gerrit-Change-Number: 36518 Gerrit-PatchSet: 1 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: ashk(a)codeaurora.org Gerrit-MessageType: newchange

3 hours, 20 minutes

3
29
0 0

Change in coreboot[master]: trogdor: Add T32 scripts for full boot chain

by mturney mturney (Code Review)

Hello ashk(a)codeaurora.org, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/35505 to review the following change. Change subject: trogdor: Add T32 scripts for full boot chain ...................................................................... trogdor: Add T32 scripts for full boot chain Change-Id: I4ec1d4f722523f240fa293dd79235ab4e32e4489 Signed-off-by: ashk <ashk(a)codeaurora.org> --- M util/qualcomm/scripts/cmm/debug_cb_common.cmm A util/qualcomm/scripts/cmm/debug_cb_trogdor.cmm A util/qualcomm/scripts/cmm/pbl_to_depthcharge.cmm 3 files changed, 229 insertions(+), 51 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/35505/1 diff --git a/util/qualcomm/scripts/cmm/debug_cb_common.cmm b/util/qualcomm/scripts/cmm/debug_cb_common.cmm index 5959ee1..cc3dd38 100644 --- a/util/qualcomm/scripts/cmm/debug_cb_common.cmm +++ b/util/qualcomm/scripts/cmm/debug_cb_common.cmm @@ -163,22 +163,28 @@ enter ) + +;;;; START OF COMMENTED OUT CODE TO SKIP QCLIB DEBUG + ; go &QCLEntryAddr ; wait !run() -; + ; if &QCLStage ; ( -; &imgpath="3rdparty\blobs\soc\qualcomm\sdm845\QcLib.elf" + ; if (&RAMLoad) -; d.load.elf &imgpath /strippart "coreboot" /sourcepath &srcpath /noclear -; else -; d.load.elf &imgpath /strippart "coreboot" /sourcepath &srcpath /nocode /noclear -; +; d.load \\snowcone\builds792\PROD\BOOT.XF.3.1-00315-SC7180LCB-1\boot_images\Build\Rennell_qclib\DEBUG_CLANG60LINUX\AARCH64\QcomPkg\QCLib\QcLibCommon\DEBUG\QcLib.dll +; else +; d.load \\snowcone\builds792\PROD\BOOT.XF.3.1-00315-SC7180LCB-1\boot_images\Build\Rennell_qclib\DEBUG_CLANG60LINUX\AARCH64\QcomPkg\QCLib\QcLibCommon\DEBUG\QcLib.dll + + ; print %String "Now the control is in QCLStage, press enter after debugging to go to next stage" ; print %String "Press enter to go to next stage" ; enter ; ) +;;;; END OF QCLIB COMMENTED OUT CODE + go &RAMEntryAddr wait !run() @@ -193,26 +199,6 @@ print %String "Press enter to go to next stage" enter ) - -; BL31 disabled for now -; Next block of code commented out -; go &BL31EntryAddr -; wait !run() -; -; if &BL31Stage -; ( -; &imgpath="build\bl31.elf" -; if (&RAMLoad) -; d.load.elf &imgpath /strippart "coreboot" /sourcepath &srcpath -; else -; d.load.elf &imgpath /strippart "coreboot" /sourcepath &srcpath /nocode -; y.spath.srd 3rdparty/arm-trusted-firmware -; print %String "Now the control is in BL31, press enter after debugging to go to next stage" -; print %String "Press enter to go to next stage" -; enter -; ) -; End of commented out code block: bl31 - go &DCEntryAddr wait !run() @@ -220,36 +206,17 @@ ( &imgpath="payloads\external\depthcharge\depthcharge\build\depthcharge.elf" symbol.sourcepath.setbasedir &srcpath\payloads + y.spath.srd payloads\external\depthcharge\depthcharge\src if (&RAMLoad) d.load.elf &imgpath /strippart "payloads" /sourcepath &srcpath else d.load.elf &imgpath /strippart "payloads" /sourcepath &srcpath /nocode - b.d /all - b.set main - b.set halt - b.set &KernelEntryAddr ; kernel entry point - y.spath.srd + payloads/external/depthcharge/depthcharge - y.spath.srd + 3rdparty\vboot_reference - d.dump &RamConsoleAddr /spotlight - &CBTablePtr=Register(X0) - Data.SAVE.Binary CBTablePtr.bin &CBTablePtr++0x400 - print %String "Now the control is in Depthcharge, press enter after debugging to run free" - ;print %String "Use this command to load kernel symbols: d.load.elf vmlinux /nocode /strippart kernel" - print %String "Press enter when done debugging Depthcharge" - enter + print %String "Now the control is in depthcharge, end of script" + d.l + b.s main + ;Execute this command in T32 if you start debugging vboot code, e.g. vboot_select_and_load_kernel() + ;y.spath.srd 3rdparty\vboot\firmware ) -; go &KernelEntryAddr -; wait !run() -; -; if &KernelSyms -; ( -; print %String "Kernel Symbols are being loaded, this requires two files in coreboot root tree:" -; print %String "vmlinux needs to be copied from ChromiumOS build tree" -; print %String "msm-4.4 needs to be symbolic link to kernel source tree" -; d.load.elf vmlinux /strippart "msm-4.4" /nocode -; y.spath.srd msm-4.4 -; print %String "This script now concludes at kernel entry point" -; ) enddo diff --git a/util/qualcomm/scripts/cmm/debug_cb_trogdor.cmm b/util/qualcomm/scripts/cmm/debug_cb_trogdor.cmm new file mode 100644 index 0000000..276bf45 --- /dev/null +++ b/util/qualcomm/scripts/cmm/debug_cb_trogdor.cmm @@ -0,0 +1,158 @@ +;============================================================================ +;## +;## This file is part of the coreboot project. +;## +;## Copyright (C) 2019, The Linux Foundation. All rights reserved. +;## +;## This program is free software; you can redistribute it and/or modify +;## it under the terms of the GNU General Public License version 2 and +;## only version 2 as published by the Free Software Foundation. +;## +;## This program is distributed in the hope that it will be useful, +;## but WITHOUT ANY WARRANTY; without even the implied warranty of +;## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;## GNU General Public License for more details. +;## +;============================================================================ +; Name: +; debug_cb_trogdor.cmm +; +; Description: +; Debug coreboot trogdor front-end +;============================================================================ + +;============================================================================ +; CMM script variables +;============================================================================ + +LOCAL &TargetPkg + +GLOBAL &BBEntryAddr // Bootblock Entry +GLOBAL &BBExitAddr // Bootblock Exit to Xbl-Sec +GLOBAL &VEREntryAddr // Verstage Entry +GLOBAL &ROMEntryAddr // Romstage Entry +GLOBAL &QCLEntryAddr // QCLstage Entry +GLOBAL &RAMEntryAddr // Ramstage Entry +GLOBAL &BL31EntryAddr // BL31 Entry +GLOBAL &DCEntryAddr // Depthcharge Entry +GLOBAL &KernelEntryAddr // Kernel Entry + +GLOBAL &PreRamConsoleAddr +GLOBAL &RamConsoleAddr +GLOBAL &PreRamCbfsCache +GLOBAL &VBoot2Work +GLOBAL &Stack +GLOBAL &Ttb +GLOBAL &Timestamp +GLOBAL &CbmemTop +GLOBAL &PostRamCbfsCache + +GLOBAL &CBTablePtr +GLOBAL &debug +;============================================================================ + +;--------------------------------------------------- +; Entry point +;--------------------------------------------------- +ENTRY &ImageName + + // Later these can be parameterized + &TargetPkg="trogdorPkg" + + // These settings come from .../src/soc/qualcomm/sc7180/include/soc/memlayout.ld + &BBEntryAddr=0x14815000 + &VEREntryAddr=0x14680000 + &ROMEntryAddr=0x14680000 + &QCLEntryAddr=0x14881950 + &RAMEntryAddr=0x9F860000 + &BL31EntryAddr=0x06820000 + &DCEntryAddr=0xF1000000 + &KernelEntryAddr=0xD0000000 + + &PreRamConsoleAddr=0x14830800 + &VBoot2Work=0x1482E000 + &Stack=0x14847000 + &Ttb=0x14839000 + &Timestamp=0x14838800 + &PreRamCbfsCache=0x1481F000 + &CbmemTop=0x280000000 + &PostRamCbfsCache=0x9F800000 + // End of memlayout.ld settings + + // Common commands irrespective of &Mode + PATH + &CwDir=os.pwd() + PATH + &CwDir + + // position at top of coreboot tree + // find depth count for source loading + cd ..\..\..\.. + &srcpath=os.pwd() + + +;--------------------------------------------------- +; Setup area and log +;--------------------------------------------------- + area.clear + area.reset + area.create CB_Logs 1000. 8192. + area.select CB_Logs + + area.view CB_Logs + + PRINT %String "Source Path: &srcpath" + + symbol.sourcepath.setbasedir &srcpath\src + + // Make parsing simple, upper-case parameters + &ImageName=STRING.UPR("&ImageName") + IF (STR.CP("&ImageName","DEBUG,*")) + ( + &debug="DEBUG" + ) + ELSE + ( + &debug="" + ) + &ImageName=STR.CUT("&ImageName",6) + IF "&debug"=="" + ( + PRINT "SPI_RAM LOAD" + &ImageName=STRING.UPR("&ImageName") + IF "&ImageName"=="" + ( + &ImageName="RAM,BB" //for RAM load Bootblock only and jump till DC + ) + PRINT "&ImageName" + ) + ELSE + ( + if (STR.CP("&debug","DEBUG")) + ( + PRINT "DEBUG" + &ImageName=STRING.UPR("&ImageName") + IF "&ImageName"=="" + ( + &ImageName="RAM,ALL" //for RAM loading all the images + ) + PRINT "&ImageName" + ) + ) + + sys.d + sys.up + b.d + y.reset + D.S EZAXI:0xC260208 %LE %Long 0x80000000 + + b.s 0x148e7000 /o + go + WAIT !STATE.RUN() + + b.s 0x14815000 /o + go + WAIT !STATE.RUN() + + DO debug_cb_common.cmm &TargetPkg &srcpath &xblsrcpath &ImageName + + enddo diff --git a/util/qualcomm/scripts/cmm/pbl_to_depthcharge.cmm b/util/qualcomm/scripts/cmm/pbl_to_depthcharge.cmm new file mode 100644 index 0000000..9205d67 --- /dev/null +++ b/util/qualcomm/scripts/cmm/pbl_to_depthcharge.cmm @@ -0,0 +1,53 @@ +sys.d +sys.up +b.d +y.reset + +d.load.elf \\ashk-linux\workspace\ashk\pbl_script\FBC_validation\APPS_PBL.elf + +b.s sec_ctrl_drv_ioctl\273+0xC /P /CMD "r.s x6 0x12345678" /resume +b.s pbl_recoverable_error_handler /o +b.s pbl_non_recoverable_error_handler /o + +snoop.PC on + +b.s 0x148e7000 /o +go +WAIT !STATE.RUN() + +b.s 0x14815000 /o +go +WAIT !STATE.RUN() + +b.d +b.s 0x14680000 /o +go +WAIT !STATE.RUN() + +b.d +b.s 0x14680000 /o +go +WAIT !STATE.RUN() + +b.d +b.s 0x14881950 /o +go +WAIT !STATE.RUN() + +d.load \\ashk-linux\workspace\ashk\test_qclib_8_7\boot.xf.3.1.test_qclib_8_7\boot_images\Build\Rennell_qclib\DEBUG_CLANG60LINUX\AARCH64\QcomPkg\QCLib\QcLibCommon\DEBUG\QcLib.dll +do \\ashk-linux\workspace\ashk\test_qclib_8_7\boot.xf.3.1.test_qclib_8_7\boot_images\QcomPkg\Tools\qclib\qclib_rennell_only_stub_coreboot.cmm + +b.d +b.s 0x9f860000 /o +go +WAIT !STATE.RUN() + +b.d +b.s 0x80c00000 /o +go +WAIT !STATE.RUN() + +b.d +b.s 0xF1000000 /o +go +WAIT !STATE.RUN() -- To view, visit https://review.coreboot.org/c/coreboot/+/35505 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ec1d4f722523f240fa293dd79235ab4e32e4489 Gerrit-Change-Number: 35505 Gerrit-PatchSet: 1 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: ashk(a)codeaurora.org Gerrit-MessageType: newchange

3 hours, 22 minutes

5
9
0 0

Change in coreboot[master]: sc7180: enable bl31

by mturney mturney (Code Review)

Hello ashk(a)codeaurora.org, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/35504 to review the following change. Change subject: sc7180: enable bl31 ...................................................................... sc7180: enable bl31 Developer/Reviewer, be aware of this patch from Napali: https://review.coreboot.org/c/coreboot/+/28014/44 Change-Id: Ia961ee0e30478e21fd786ce464655977449df510 Signed-off-by: ashk <ashk(a)codeaurora.org> --- M src/soc/qualcomm/sc7180/Kconfig M src/soc/qualcomm/sc7180/include/soc/memlayout.ld 2 files changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/35504/1 diff --git a/src/soc/qualcomm/sc7180/Kconfig b/src/soc/qualcomm/sc7180/Kconfig index df5d116..28f7522 100644 --- a/src/soc/qualcomm/sc7180/Kconfig +++ b/src/soc/qualcomm/sc7180/Kconfig @@ -6,6 +6,7 @@ select ARCH_RAMSTAGE_ARMV8_64 select ARCH_ROMSTAGE_ARMV8_64 select ARCH_VERSTAGE_ARMV8_64 + select ARM64_USE_ARM_TRUSTED_FIRMWARE select GENERIC_GPIO_LIB select GENERIC_UDELAY select HAVE_MONOTONIC_TIMER diff --git a/src/soc/qualcomm/sc7180/include/soc/memlayout.ld b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld index f4e6f05..e47f881 100644 --- a/src/soc/qualcomm/sc7180/include/soc/memlayout.ld +++ b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld @@ -72,7 +72,7 @@ REGION(dram_reserved1, 0x80820000, 0x20000, 0x1000) REGION(dram_reserved, 0x80900000, 0x200000, 0x1000) /* Various hardware/software subsystems make use of this area */ - BL31(0x85000000, 0x1A800000) + BL31(0x80C00000, 0x1A800000) POSTRAM_CBFS_CACHE(0x9F800000, 384K) RAMSTAGE(0x9F860000, 2M) } -- To view, visit https://review.coreboot.org/c/coreboot/+/35504 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia961ee0e30478e21fd786ce464655977449df510 Gerrit-Change-Number: 35504 Gerrit-PatchSet: 1 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: ashk(a)codeaurora.org Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newchange

3 hours, 22 minutes

2
4
0 0

Change in coreboot[master]: trogdor: mainboard reference QUPv3 FW driver

by mturney mturney (Code Review)

mturney mturney has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37306 ) Change subject: trogdor: mainboard reference QUPv3 FW driver ...................................................................... trogdor: mainboard reference QUPv3 FW driver Change-Id: I8ff5dd63fac28ffa558aec71e79a6de87d7885e0 Signed-off-by: T Michael Turney <mturney(a)codeaurora.org> --- M src/mainboard/google/trogdor/mainboard.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/37306/1 diff --git a/src/mainboard/google/trogdor/mainboard.c b/src/mainboard/google/trogdor/mainboard.c index 1cf2b96..8849911 100644 --- a/src/mainboard/google/trogdor/mainboard.c +++ b/src/mainboard/google/trogdor/mainboard.c @@ -19,6 +19,7 @@ #include <gpio.h> #include <timestamp.h> #include <soc/usb.h> +#include <soc/qupv3_fw_config.h> static struct usb_board_data usb0_board_data = { .pll_bias_control_2 = 0x22, @@ -34,6 +35,7 @@ static void mainboard_init(struct device *dev) { setup_usb(); + qupv3_fw_init(); } static void mainboard_enable(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/37306 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ff5dd63fac28ffa558aec71e79a6de87d7885e0 Gerrit-Change-Number: 37306 Gerrit-PatchSet: 1 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newchange

3 hours, 23 minutes

2
3
0 0

Change in coreboot[master]: sc7180: Add SPI QUP driver

by mturney mturney (Code Review)

mturney mturney has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36517 ) Change subject: sc7180: Add SPI QUP driver ...................................................................... sc7180: Add SPI QUP driver This implements the SPI driver for the QUP core. Change-Id: I86f4fcff6f9537373f70a43711130d7f28bd5e09 Signed-off-by: Roja Rani Yarubandi <rojay(a)codeaurora.org> --- M src/mainboard/google/trogdor/bootblock.c M src/soc/qualcomm/sc7180/Makefile.inc A src/soc/qualcomm/sc7180/include/soc/spi_qup_qcom.h M src/soc/qualcomm/sc7180/qcom_qup_se.c M src/soc/qualcomm/sc7180/spi.c A src/soc/qualcomm/sc7180/spi_qup.c 6 files changed, 310 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/36517/1 diff --git a/src/mainboard/google/trogdor/bootblock.c b/src/mainboard/google/trogdor/bootblock.c index c658093..a109a08 100644 --- a/src/mainboard/google/trogdor/bootblock.c +++ b/src/mainboard/google/trogdor/bootblock.c @@ -15,8 +15,12 @@ #include <bootblock_common.h> #include "board.h" +#include <soc/qcom_qup_se.h> +#include <soc/spi_qup_qcom.h> void bootblock_mainboard_init(void) { setup_chromeos_gpios(); + qup_spi_init(QUPV3_0_SE0, 1010 * KHz); /* H1 SPI */ + qup_spi_init(QUPV3_1_SE4, 1010 * KHz); /* EC SPI */ } diff --git a/src/soc/qualcomm/sc7180/Makefile.inc b/src/soc/qualcomm/sc7180/Makefile.inc index 18f8ada..66cb35c 100644 --- a/src/soc/qualcomm/sc7180/Makefile.inc +++ b/src/soc/qualcomm/sc7180/Makefile.inc @@ -6,6 +6,7 @@ bootblock-y += mmu.c bootblock-y += timer.c bootblock-y += spi.c +bootblock-y += spi_qup.c bootblock-y += gpio.c bootblock-$(CONFIG_DRIVERS_UART) += uart_bitbang.c bootblock-y += clock.c @@ -17,6 +18,7 @@ ################################################################################ verstage-y += timer.c verstage-y += spi.c +verstage-y += spi_qup.c verstage-y += gpio.c verstage-y += clock.c verstage-y += qcom_qup_se.c @@ -32,6 +34,7 @@ romstage-y += mmu.c romstage-y += usb.c romstage-y += spi.c +romstage-y += spi_qup.c romstage-y += gpio.c romstage-y += clock.c romstage-y += qcom_qup_se.c @@ -43,6 +46,7 @@ ramstage-y += cbmem.c ramstage-y += timer.c ramstage-y += spi.c +ramstage-y += spi_qup.c ramstage-y += gpio.c ramstage-y += clock.c ramstage-y += qupv3_fw_config.c diff --git a/src/soc/qualcomm/sc7180/include/soc/spi_qup_qcom.h b/src/soc/qualcomm/sc7180/include/soc/spi_qup_qcom.h new file mode 100644 index 0000000..4999422 --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/spi_qup_qcom.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2018-2019 Qualcomm Technologies + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SPI_QUP_QCOM_HEADER___ +#define __SPI_QUP_QCOM_HEADER___ + +#include <spi-generic.h> + +int qup_spi_claim_bus(const struct spi_slave *slave); +int qup_spi_xfer(const struct spi_slave *slave, const void *dout, + size_t bytes_out, void *din, size_t bytes_in); +void qup_spi_release_bus(const struct spi_slave *slave); +void qup_spi_init(unsigned int bus, unsigned int speed_hz); + +#endif /*__SPI_QUP_QCOM_HEADER___*/ diff --git a/src/soc/qualcomm/sc7180/qcom_qup_se.c b/src/soc/qualcomm/sc7180/qcom_qup_se.c index 1774a2c..d14a852 100644 --- a/src/soc/qualcomm/sc7180/qcom_qup_se.c +++ b/src/soc/qualcomm/sc7180/qcom_qup_se.c @@ -92,7 +92,6 @@ if (m_irq) break; } - write32(&regs->geni_m_irq_clear, m_irq); return m_irq; } @@ -147,17 +146,38 @@ void qup_handle_error(unsigned int bus) { struct qup_regs *regs = qup[bus].regs; + struct stopwatch sw; + unsigned int m_irq; write32(&regs->geni_tx_watermark_reg, 0); write32(&regs->geni_m_cmd_ctrl_reg, M_GENI_CMD_CANCEL); - if (!wait_us(100, qup_wait_for_irq(bus) & M_CMD_CANCEL_EN)) { + stopwatch_init_msecs_expire(&sw, 100); + do { + m_irq = qup_wait_for_irq(bus); + if (m_irq & M_CMD_CANCEL_EN) { + write32(&regs->geni_m_irq_clear, m_irq); + break; + } + write32(&regs->geni_m_irq_clear, m_irq); + } while (!stopwatch_expired(&sw)); + + if (!(m_irq & M_CMD_CANCEL_EN)) { printk(BIOS_INFO, "%s:Cancel failed" ",Abort the operation\n", __func__); - write32(&regs->geni_m_cmd_ctrl_reg, - M_GENI_CMD_ABORT); - if (!wait_us(100, qup_wait_for_irq(bus) & M_CMD_ABORT_EN)) + write32(&regs->geni_m_cmd_ctrl_reg, M_GENI_CMD_ABORT); + stopwatch_init_msecs_expire(&sw, 100); + do { + m_irq = qup_wait_for_irq(bus); + if (m_irq & M_CMD_ABORT_EN) { + write32(&regs->geni_m_irq_clear, m_irq); + break; + } + write32(&regs->geni_m_irq_clear, m_irq); + } while (!stopwatch_expired(&sw)); + + if (!(m_irq & M_CMD_ABORT_EN)) printk(BIOS_INFO, "%s:Abort failed\n", __func__); } } @@ -168,6 +188,7 @@ struct stopwatch sw; unsigned int rx_rem_bytes = din ? size : 0; unsigned int tx_rem_bytes = dout ? size : 0; + struct qup_regs *regs = qup[bus].regs; stopwatch_init_msecs_expire(&sw, 1000); do { @@ -179,8 +200,11 @@ if (m_irq & M_TX_FIFO_WATERMARK_EN) tx_rem_bytes -= handle_tx(bus, dout + size - tx_rem_bytes, tx_rem_bytes); - if (m_irq & M_CMD_DONE_EN) + if (m_irq & M_CMD_DONE_EN) { + write32(&regs->geni_m_irq_clear, m_irq); break; + } + write32(&regs->geni_m_irq_clear, m_irq); } while (!stopwatch_expired(&sw)); if (!(m_irq & M_CMD_DONE_EN) || tx_rem_bytes || rx_rem_bytes) { diff --git a/src/soc/qualcomm/sc7180/spi.c b/src/soc/qualcomm/sc7180/spi.c index c6d4cb1..4146032 100644 --- a/src/soc/qualcomm/sc7180/spi.c +++ b/src/soc/qualcomm/sc7180/spi.c @@ -16,6 +16,7 @@ #include <spi-generic.h> #include <spi_flash.h> #include <soc/qspi.h> +#include <soc/spi_qup_qcom.h> static const struct spi_ctrlr qspi_ctrlr = { .claim_bus = sc7180_claim_bus, @@ -25,12 +26,24 @@ .max_xfer_size = QSPI_MAX_PACKET_COUNT, }; +const struct spi_ctrlr spi_qup_ctrlr = { + .claim_bus = qup_spi_claim_bus, + .release_bus = qup_spi_release_bus, + .xfer = qup_spi_xfer, + .max_xfer_size = 65535, +}; + const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { { .ctrlr = &qspi_ctrlr, .bus_start = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, .bus_end = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, }, + { + .ctrlr = &spi_qup_ctrlr, + .bus_start = 0, + .bus_end = 11, + }, }; const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); diff --git a/src/soc/qualcomm/sc7180/spi_qup.c b/src/soc/qualcomm/sc7180/spi_qup.c new file mode 100644 index 0000000..6953c6a --- /dev/null +++ b/src/soc/qualcomm/sc7180/spi_qup.c @@ -0,0 +1,232 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <assert.h> +#include <delay.h> +#include <lib.h> +#include <soc/clock.h> +#include <soc/gpio.h> +#include <soc/qcom_qup_se.h> +#include <soc/spi_qup_qcom.h> + +/* SE_SPI_LOOPBACK register fields */ +#define LOOPBACK_ENABLE 0x1 + +/* SE_SPI_WORD_LEN register fields */ +#define WORD_LEN_MSK GENMASK(9, 0) +#define MIN_WORD_LEN 4 + +/* SPI_TX/SPI_RX_TRANS_LEN fields */ +#define TRANS_LEN_MSK GENMASK(23, 0) + +/* M_CMD OP codes for SPI */ +#define SPI_TX_ONLY 1 +#define SPI_RX_ONLY 2 +#define SPI_FULL_DUPLEX 3 +#define SPI_TX_RX 7 +#define SPI_CS_ASSERT 8 +#define SPI_CS_DEASSERT 9 +#define SPI_SCK_ONLY 10 + +/* M_CMD params for SPI */ +/* If fragmentation bit is set then CS will not toggle after each transfer */ +#define M_CMD_FRAGMENTATION BIT(2) + +#define BITS_PER_BYTE 8 +#define BITS_PER_WORD 8 +#define TX_WATERMARK 1 + +#define IRQ_TRIGGER (M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN | \ + M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN | \ + M_CMD_CANCEL_EN | M_CMD_ABORT_EN) + +static void setup_fifo_params(const struct spi_slave *slave) +{ + unsigned int se_bus = slave->bus; + struct qup_regs *regs = qup[se_bus].regs; + u32 word_len = 0; + + /* Disable loopback mode */ + write32(&regs->proto_loopback_cfg, 0); + + write32(&regs->spi_demux_sel, slave->cs); + word_len = ((BITS_PER_WORD - MIN_WORD_LEN) & WORD_LEN_MSK); + write32(&regs->word_len.spi_word_len, word_len); + + /* FIFO PACKING CONFIGURATION */ + write32(&regs->geni_tx_packing_cfg0, PACK_VECTOR0 + | (PACK_VECTOR1 << 10)); + write32(&regs->geni_tx_packing_cfg1, PACK_VECTOR2 + | (PACK_VECTOR3 << 10)); + write32(&regs->geni_rx_packing_cfg0, PACK_VECTOR0 + | (PACK_VECTOR1 << 10)); + write32(&regs->geni_rx_packing_cfg1, PACK_VECTOR2 + | (PACK_VECTOR3 << 10)); + write32(&regs->geni_byte_granularity, (log2(BITS_PER_WORD) - 3)); +} + +static void qup_setup_m_cmd(unsigned int se_bus, u32 cmd, u32 params) +{ + struct qup_regs *regs = qup[se_bus].regs; + u32 m_cmd = (cmd << M_OPCODE_SHFT); + + m_cmd |= (params & M_PARAMS_MSK); + write32(&regs->geni_m_cmd0, m_cmd); +} + +int qup_spi_xfer(const struct spi_slave *slave, const void *dout, + size_t bytes_out, void *din, size_t bytes_in) +{ + u32 m_cmd = 0; + u32 m_param = M_CMD_FRAGMENTATION; + int size; + unsigned int se_bus = slave->bus; + struct qup_regs *regs = qup[se_bus].regs; + + if ((bytes_in == 0) && (bytes_out == 0)) + return 0; + + setup_fifo_params(slave); + + if (!bytes_out) { + size = bytes_in; + m_cmd = SPI_RX_ONLY; + dout = NULL; + } else if (!bytes_in) { + size = bytes_out; + m_cmd = SPI_TX_ONLY; + din = NULL; + } else { + size = MIN(bytes_in, bytes_out); + m_cmd = SPI_FULL_DUPLEX; + } + + /* Check for maximum permissible transfer length */ + assert(!(size & ~TRANS_LEN_MSK)); + + if (bytes_out) { + write32(&regs->tx_trans_len.spi_tx_trans_len, size); + write32(&regs->geni_tx_watermark_reg, TX_WATERMARK); + } + if (bytes_in) + write32(&regs->rx_trans_len.spi_rx_trans_len, size); + + qup_setup_m_cmd(se_bus, m_cmd, m_param); + + if (qup_handle_transfer(se_bus, dout, din, size)) + return -1; + + qup_spi_xfer(slave, dout + size, MAX((int)bytes_out - size, 0), + din + size, MAX((int)bytes_in - size, 0)); + + return 0; +} + +static int spi_qup_set_cs(const struct spi_slave *slave, bool enable) +{ + u32 m_cmd = 0; + u32 m_irq = 0; + unsigned int se_bus = slave->bus; + struct stopwatch sw; + + m_cmd = (enable) ? SPI_CS_ASSERT : SPI_CS_DEASSERT; + qup_setup_m_cmd(se_bus, m_cmd, 0); + + stopwatch_init_usecs_expire(&sw, 100); + do { + m_irq = qup_wait_for_irq(se_bus); + if (m_irq & M_CMD_DONE_EN) { + write32(&qup[se_bus].regs->geni_m_irq_clear, m_irq); + break; + } + write32(&qup[se_bus].regs->geni_m_irq_clear, m_irq); + } while (!stopwatch_expired(&sw)); + + if (!(m_irq & M_CMD_DONE_EN)) { + printk(BIOS_INFO, "%s:Failed to %s chip\n", __func__, + (enable) ? "Assert" : "Deassert"); + qup_handle_error(se_bus); + return -1; + } + return 0; +} + +void qup_spi_init(unsigned int bus, unsigned int speed_hz) +{ + u32 m_clk_cfg = 0, div = DEFAULT_SE_CLK / speed_hz; + struct qup_regs *regs = qup[bus].regs; + + /* Make sure div can hit target frequency within +/- 1KHz range */ + assert(((DEFAULT_SE_CLK - speed_hz * div) <= div * KHz) && (div > 0)); + clock_enable_qup(bus); + m_clk_cfg |= ((div << CLK_DIV_SHFT) | SER_CLK_EN); + write32(&regs->geni_ser_m_clk_cfg, m_clk_cfg); + /* Mode:0, cpha=0, cpol=0 */ + write32(&regs->spi_cpha, 0); + write32(&regs->spi_cpol, 0); + /* Disable DFS */ + clrbits_le32(&regs->geni_dfs_if_cfg, + GENI_DFS_IF_CFG_DFS_IF_EN_BMSK); + + /* Serial engine IO initialization */ + write32(&regs->geni_cgc_ctrl, DEFAULT_CGC_EN); + write32(&regs->dma_general_cfg, + (AHB_SEC_SLV_CLK_CGC_ON | DMA_AHB_SLV_CFG_ON + | DMA_TX_CLK_CGC_ON | DMA_RX_CLK_CGC_ON)); + write32(&regs->geni_output_ctrl, + DEFAULT_IO_OUTPUT_CTRL_MSK); + write32(&regs->geni_force_default_reg, FORCE_DEFAULT); + + /* Serial engine IO set mode */ + write32(&regs->se_irq_en, (GENI_M_IRQ_EN | + GENI_S_IRQ_EN | DMA_TX_IRQ_EN | DMA_RX_IRQ_EN)); + write32(&regs->se_gsi_event_en, 0); + + /* Set RX and RFR watermark */ + write32(&regs->geni_rx_watermark_reg, 0); + write32(&regs->geni_rx_rfr_watermark_reg, FIFO_DEPTH - 2); + + /* GPIO Configuration */ + gpio_configure(qup[bus].pin[0], qup[bus].func[0], GPIO_NO_PULL, + GPIO_6MA, GPIO_INPUT); /* MISO */ + gpio_configure(qup[bus].pin[1], qup[bus].func[1], GPIO_NO_PULL, + GPIO_6MA, GPIO_OUTPUT); /* MOSI */ + gpio_configure(qup[bus].pin[2], qup[bus].func[2], GPIO_NO_PULL, + GPIO_6MA, GPIO_OUTPUT); /* CLK */ + gpio_configure(qup[bus].pin[3], qup[bus].func[3], GPIO_NO_PULL, + GPIO_6MA, GPIO_OUTPUT); /* CS */ + + /* Select and setup FIFO mode */ + write32(&regs->geni_m_irq_clear, 0xFFFFFFFF); + write32(&regs->geni_s_irq_clear, 0xFFFFFFFF); + write32(&regs->dma_tx_irq_clr, 0xFFFFFFFF); + write32(&regs->dma_rx_irq_clr, 0xFFFFFFFF); + write32(&regs->geni_m_irq_enable, (M_COMMON_GENI_M_IRQ_EN | + M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN | + M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN)); + write32(&regs->geni_s_irq_enable, (S_COMMON_GENI_S_IRQ_EN + | S_CMD_DONE_EN)); + clrbits_le32(&regs->geni_dma_mode_en, GENI_DMA_MODE_EN); +} + +int qup_spi_claim_bus(const struct spi_slave *slave) +{ + return spi_qup_set_cs(slave, 1); +} + +void qup_spi_release_bus(const struct spi_slave *slave) +{ + spi_qup_set_cs(slave, 0); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/36517 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86f4fcff6f9537373f70a43711130d7f28bd5e09 Gerrit-Change-Number: 36517 Gerrit-PatchSet: 1 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newchange

3 hours, 39 minutes

3
12
0 0

Change in coreboot[master]: security/vboot: Decouple measured boot from verified boot

by Bill XIE (Code Review)

Bill XIE has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35077 ) Change subject: security/vboot: Decouple measured boot from verified boot ...................................................................... security/vboot: Decouple measured boot from verified boot As said in CB:34977, currently TPM and CRTM are initialized just before romstage loads a file within CBFS, or initialized in vboot_logic() if CONFIG_VBOOT is set. Change-Id: I1fb376b4a8b98baffaee4d574937797bba1f8aee Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org> --- M src/lib/cbfs.c M src/security/tpm/Makefile.inc M src/security/tpm/tspi/tspi.c M src/security/vboot/Kconfig M src/security/vboot/Makefile.inc M src/security/vboot/misc.h M src/security/vboot/vboot_crtm.c M src/security/vboot/vboot_crtm.h 8 files changed, 136 insertions(+), 68 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/35077/1 diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 91368fb..246e741 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -327,6 +327,9 @@ * devices. */ const struct cbfs_locator __weak cbfs_master_header_locator = { .name = "Master Header Locator", +#if !CONFIG(VBOOT) && CONFIG(VBOOT_MEASURED_BOOT) + .prepare = measured_boot_init_crtm, +#endif .locate = cbfs_master_header_props, }; diff --git a/src/security/tpm/Makefile.inc b/src/security/tpm/Makefile.inc index a2d32cf..cb936cf 100644 --- a/src/security/tpm/Makefile.inc +++ b/src/security/tpm/Makefile.inc @@ -8,7 +8,10 @@ romstage-y += tss/tcg-1.2/tss.c verstage-$(CONFIG_VBOOT) += tss/tcg-1.2/tss.c -postcar-$(CONFIG_VBOOT) += tss/tcg-1.2/tss.c + +ifneq ($(CONFIG_VBOOT_MEASURED_BOOT)$(CONFIG_VBOOT),) +postcar-y += tss/tcg-1.2/tss.c +endif ## TSPI @@ -16,7 +19,10 @@ romstage-y += tspi/tspi.c verstage-$(CONFIG_VBOOT) += tspi/tspi.c -postcar-$(CONFIG_VBOOT) += tspi/tspi.c + +ifneq ($(CONFIG_VBOOT_MEASURED_BOOT)$(CONFIG_VBOOT),) +postcar-y += tspi/tspi.c +endif ramstage-$(CONFIG_VBOOT_MEASURED_BOOT) += tspi/log.c romstage-$(CONFIG_VBOOT_MEASURED_BOOT) += tspi/log.c @@ -45,7 +51,10 @@ romstage-y += tspi/tspi.c verstage-$(CONFIG_VBOOT) += tspi/tspi.c -postcar-$(CONFIG_VBOOT) += tspi/tspi.c + +ifneq ($(CONFIG_VBOOT_MEASURED_BOOT)$(CONFIG_VBOOT),) +postcar-y += tspi/tspi.c +endif ramstage-$(CONFIG_VBOOT_MEASURED_BOOT) += tspi/log.c romstage-$(CONFIG_VBOOT_MEASURED_BOOT) += tspi/log.c diff --git a/src/security/tpm/tspi/tspi.c b/src/security/tpm/tspi/tspi.c index 4698a4d..36dd3dd 100644 --- a/src/security/tpm/tspi/tspi.c +++ b/src/security/tpm/tspi/tspi.c @@ -20,7 +20,7 @@ #include <security/tpm/tspi.h> #include <security/tpm/tss.h> #include <stdlib.h> -#if CONFIG(VBOOT) +#if CONFIG(VBOOT) || CONFIG(VBOOT_MEASURED_BOOT) #include <vb2_api.h> #include <vb2_sha.h> #include <assert.h> @@ -220,7 +220,7 @@ return TPM_SUCCESS; } -#if CONFIG(VBOOT) +#if CONFIG(VBOOT) || CONFIG(VBOOT_MEASURED_BOOT) uint32_t tpm_measure_region(const struct region_device *rdev, uint8_t pcr, const char *rname) { @@ -279,4 +279,4 @@ printk(BIOS_DEBUG, "TPM: Measured %s into PCR %d\n", rname, pcr); return TPM_SUCCESS; } -#endif /* VBOOT */ +#endif /* VBOOT || VBOOT_MEASURED_BOOT */ diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index c5146c6..955e8a6 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -13,7 +13,7 @@ ## GNU General Public License for more details. ## -menu "Verified Boot (vboot)" +menu "vboot functionalities" config VBOOT bool "Verify firmware with vboot." @@ -21,21 +21,17 @@ select VBOOT_MOCK_SECDATA if !TPM1 && !TPM2 depends on !MISSING_BOARD_RESET help - Enabling VBOOT will use vboot to verify the components of the firmware + Enabling verified voot will use vboot to verify the components of the firmware (stages, payload, etc). -if VBOOT - -comment "Anti-Rollback Protection disabled because mocking secdata is enabled." - depends on VBOOT_MOCK_SECDATA - config VBOOT_MEASURED_BOOT - bool "Enable Measured Boot" + bool "Measure firmware components with vboot." default n depends on TPM1 || TPM2 depends on !VBOOT_RETURN_FROM_VERSTAGE help - Enables measured boot mode in vboot (experimental) + Enables measured boot will use vboot to measure the components of the firmware + (stages, payload, etc) to PCRs within TPM. (experimental) config VBOOT_MEASURED_BOOT_RUNTIME_DATA string "Runtime data whitelist" @@ -45,6 +41,13 @@ Runtime data whitelist of cbfs filenames. Needs to be a comma separated list +if VBOOT + +comment "Anti-Rollback Protection disabled because mocking secdata is enabled." + depends on VBOOT_MOCK_SECDATA + +comment "A non-trivial fmd file with sections required by vboot is needed." + config VBOOT_SLOTS_RW_A bool "Firmware RO + RW_A" help diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc index d554f10..0729d9f 100644 --- a/src/security/vboot/Makefile.inc +++ b/src/security/vboot/Makefile.inc @@ -14,6 +14,58 @@ ## GNU General Public License for more details. ## +ifneq ($(CONFIG_VBOOT_MEASURED_BOOT)$(CONFIG_VBOOT),) + +ifneq ($(CONFIG_TPM1)$(CONFIG_TPM2),) +verstage-y += tpm_common.c +endif + + +vboot-fixup-includes = $(patsubst -I%,-I$(top)/%,\ + $(patsubst $(src)/%.h,$(top)/$(src)/%.h,\ + $(filter-out -I$(obj),$(1)))) + +# call with $1 = stage name to create rules for building the library +# for the stage and adding it to the stage's set of object files. +define vboot-for-stage +VB2_LIB_$(1) = $(obj)/external/vboot_reference-$(1)/vboot_fw20.a +VBOOT_CFLAGS_$(1) += $$(call vboot-fixup-includes,$$(CPPFLAGS_$(1))) +VBOOT_CFLAGS_$(1) += $$(CFLAGS_$(1)) +VBOOT_CFLAGS_$(1) += $$(call vboot-fixup-includes,$$($(1)-c-ccopts)) +VBOOT_CFLAGS_$(1) += -I$(abspath $(obj)) -Wno-missing-prototypes +VBOOT_CFLAGS_$(1) += -DVBOOT_DEBUG + +$$(VB2_LIB_$(1)): $(obj)/config.h + printf " MAKE $(subst $(obj)/,,$(@))\n" + +FIRMWARE_ARCH=$$(ARCHDIR-$$(ARCH-$(1)-y)) \ + CC="$$(CC_$(1))" \ + CFLAGS="$$(VBOOT_CFLAGS_$(1))" VBOOT2="y" \ + $(MAKE) -C $(VBOOT_SOURCE) \ + BUILD=$$(abspath $$(dir $$(VB2_LIB_$(1)))) \ + V=$(V) \ + fwlib20 + +$(1)-srcs += $$(VB2_LIB_$(1)) + +endef # vboot-for-stage + +CFLAGS_common += -I3rdparty/vboot/firmware/2lib/include + +$(eval $(call vboot-for-stage,bootblock)) +$(eval $(call vboot-for-stage,romstage)) +$(eval $(call vboot-for-stage,ramstage)) +$(eval $(call vboot-for-stage,postcar)) + +endif # CONFIG_VBOOT_MEASURED_BOOT || CONFIG_VBOOT + +ifeq ($(CONFIG_VBOOT_MEASURED_BOOT),y) +bootblock-y += vboot_crtm.c +verstage-y += vboot_crtm.c +romstage-y += vboot_crtm.c +ramstage-y += vboot_crtm.c +postcar-y += vboot_crtm.c +endif # CONFIG_VBOOT_MEASURED_BOOT + ifeq ($(CONFIG_VBOOT),y) bootblock-y += bootmode.c @@ -22,6 +74,12 @@ verstage-y += bootmode.c postcar-y += bootmode.c +bootblock-y += vboot_common.c +verstage-y += vboot_common.c +romstage-y += vboot_common.c +ramstage-y += vboot_common.c +postcar-y += vboot_common.c + # When VBOOT_STARTS_IN_ROMSTAGE is selected, DRAM is already up by # the time verstage runs. ifneq ($(CONFIG_VBOOT_STARTS_IN_ROMSTAGE),y) @@ -63,19 +121,7 @@ verstage-y += vboot_loader.c postcar-y += vboot_loader.c -bootblock-y += vboot_common.c -verstage-y += vboot_common.c -romstage-y += vboot_common.c -ramstage-y += vboot_common.c -postcar-y += vboot_common.c -ifeq ($(CONFIG_VBOOT_MEASURED_BOOT),y) -bootblock-y += vboot_crtm.c -verstage-y += vboot_crtm.c -romstage-y += vboot_crtm.c -ramstage-y += vboot_crtm.c -postcar-y += vboot_crtm.c -endif bootblock-y += common.c verstage-y += vboot_logic.c @@ -89,10 +135,6 @@ romstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += secdata_tpm.c endif -ifneq ($(CONFIG_TPM1)$(CONFIG_TPM2),) -verstage-y += tpm_common.c -endif - romstage-y += vboot_logic.c romstage-y += common.c @@ -101,41 +143,6 @@ romstage-$(CONFIG_FSP2_0_USES_TPM_MRC_HASH) += mrc_cache_hash_tpm.c -vboot-fixup-includes = $(patsubst -I%,-I$(top)/%,\ - $(patsubst $(src)/%.h,$(top)/$(src)/%.h,\ - $(filter-out -I$(obj),$(1)))) - -# call with $1 = stage name to create rules for building the library -# for the stage and adding it to the stage's set of object files. -define vboot-for-stage -VB2_LIB_$(1) = $(obj)/external/vboot_reference-$(1)/vboot_fw20.a -VBOOT_CFLAGS_$(1) += $$(call vboot-fixup-includes,$$(CPPFLAGS_$(1))) -VBOOT_CFLAGS_$(1) += $$(CFLAGS_$(1)) -VBOOT_CFLAGS_$(1) += $$(call vboot-fixup-includes,$$($(1)-c-ccopts)) -VBOOT_CFLAGS_$(1) += -I$(abspath $(obj)) -Wno-missing-prototypes -VBOOT_CFLAGS_$(1) += -DVBOOT_DEBUG - -$$(VB2_LIB_$(1)): $(obj)/config.h - printf " MAKE $(subst $(obj)/,,$(@))\n" - +FIRMWARE_ARCH=$$(ARCHDIR-$$(ARCH-$(1)-y)) \ - CC="$$(CC_$(1))" \ - CFLAGS="$$(VBOOT_CFLAGS_$(1))" VBOOT2="y" \ - $(MAKE) -C $(VBOOT_SOURCE) \ - BUILD=$$(abspath $$(dir $$(VB2_LIB_$(1)))) \ - V=$(V) \ - fwlib20 - -$(1)-srcs += $$(VB2_LIB_$(1)) - -endef # vboot-for-stage - -CFLAGS_common += -I3rdparty/vboot/firmware/2lib/include - -$(eval $(call vboot-for-stage,bootblock)) -$(eval $(call vboot-for-stage,romstage)) -$(eval $(call vboot-for-stage,ramstage)) -$(eval $(call vboot-for-stage,postcar)) - ifeq ($(CONFIG_VBOOT_SEPARATE_VERSTAGE),y) $(eval $(call vboot-for-stage,verstage)) diff --git a/src/security/vboot/misc.h b/src/security/vboot/misc.h index 725f5fd..8761b84 100644 --- a/src/security/vboot/misc.h +++ b/src/security/vboot/misc.h @@ -127,5 +127,21 @@ } } +static inline int vboot_crtm_is_set(void) +{ + extern int crtm_is_set; + if (CONFIG(VBOOT)) { + return vboot_logic_executed(); + } else if(ENV_ROMSTAGE) { + return car_get_var(crtm_is_set); + } else { +#ifdef __PRE_RAM__ + return 0; +#else + return 1; +#endif + } +} + #endif /* __VBOOT_MISC_H__ */ diff --git a/src/security/vboot/vboot_crtm.c b/src/security/vboot/vboot_crtm.c index e4266b2..92f05e5 100644 --- a/src/security/vboot/vboot_crtm.c +++ b/src/security/vboot/vboot_crtm.c @@ -19,11 +19,13 @@ #include <security/vboot/vboot_crtm.h> #include <security/vboot/misc.h> #include <string.h> +#include <timestamp.h> /* * This functions sets the TCPA log namespace * for the cbfs file (region) lookup. */ + static int create_tcpa_metadata(const struct region_device *rdev, const char *cbfs_name, char log_string[TCPA_PCR_HASH_NAME]) { @@ -90,7 +92,8 @@ } } - if (CONFIG(VBOOT_STARTS_IN_ROMSTAGE)) { + if (CONFIG(VBOOT_STARTS_IN_ROMSTAGE) || + CONFIG(VBOOT_MEASURED_BOOT)) { struct cbfsf romstage_data; /* measure romstage from RO */ if (cbfs_boot_locate(&romstage_data, @@ -164,7 +167,7 @@ struct region_device rdev; char tcpa_metadata[TCPA_PCR_HASH_NAME]; - if (!vboot_logic_executed()) + if (!vboot_crtm_is_set()) return 0; cbfsf_file_type(fh, &cbfs_type); @@ -193,3 +196,26 @@ return tpm_measure_region(&rdev, pcr_index, tcpa_metadata); } + +int crtm_is_set CAR_GLOBAL; + +void measured_boot_init_crtm(void) +{ + if (ENV_ROMSTAGE) { + timestamp_add_now(TS_START_TPMINIT); + int result = tpm_setup(vboot_platform_is_resuming()); + timestamp_add_now(TS_END_TPMINIT); + + if (result == TPM_SUCCESS) { + result = vboot_init_crtm(); + if(result != VB2_SUCCESS) { + printk(BIOS_INFO, + "Initializing CRTM failed!"); + } else { + car_set_var(crtm_is_set, 1); + } + } else { + printk(BIOS_INFO, "TPM setup failed!"); + } + } +} diff --git a/src/security/vboot/vboot_crtm.h b/src/security/vboot/vboot_crtm.h index 64cb4f2..87bfa2d 100644 --- a/src/security/vboot/vboot_crtm.h +++ b/src/security/vboot/vboot_crtm.h @@ -53,6 +53,10 @@ * return 0 if successful, else an error */ uint32_t vboot_measure_cbfs_hook(struct cbfsf *fh, const char *name); +/* + * Initialize crtm without running vboot_logic() + */ +void measured_boot_init_crtm(void); #else #define vboot_measure_cbfs_hook(fh, name) 0 -- To view, visit https://review.coreboot.org/c/coreboot/+/35077 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fb376b4a8b98baffaee4d574937797bba1f8aee Gerrit-Change-Number: 35077 Gerrit-PatchSet: 1 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-MessageType: newchange

4 hours, 28 minutes

6
63
0 0

Change in ...coreboot[master]: security/intel/stm STM support

by Name of user not set (Code Review)

Name of user not set #1002358 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33234 Change subject: security/intel/stm STM support ...................................................................... security/intel/stm STM support Initial commit for Coreboot STM supporX Change-Id: If4adcd92c341162630ce1ec357ffcf8a135785ec --- M src/security/Kconfig M src/security/Makefile.inc A src/security/intel/stm/Kconfig A src/security/intel/stm/Makefile.inc A src/security/intel/stm/SmmStm.c A src/security/intel/stm/SmmStm.h A src/security/intel/stm/StmApi.h A src/security/intel/stm/StmPlatformResource.c A src/security/intel/stm/StmPlatformResource.h A src/security/intel/stm/StmPlatformSmm.c 10 files changed, 2,235 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/33234/1 diff --git a/src/security/Kconfig b/src/security/Kconfig index 6a334ac..e9b5225 100644 --- a/src/security/Kconfig +++ b/src/security/Kconfig @@ -14,3 +14,4 @@ source "src/security/vboot/Kconfig" source "src/security/tpm/Kconfig" +source "src/security/intel/stm/Kconfig" diff --git a/src/security/Makefile.inc b/src/security/Makefile.inc index a940b82..e49c172 100644 --- a/src/security/Makefile.inc +++ b/src/security/Makefile.inc @@ -1,2 +1,4 @@ subdirs-y += vboot subdirs-y += tpm +subdirs-y += intel/stm + diff --git a/src/security/intel/stm/Kconfig b/src/security/intel/stm/Kconfig new file mode 100644 index 0000000..e8eea02 --- /dev/null +++ b/src/security/intel/stm/Kconfig @@ -0,0 +1,17 @@ + +menu "SMI Transfer Monitor (STM)" + +config STM + bool "Enable STM" + default y + depends on (PLATFORM_USES_FSP2_0||PLATFORM_USES_FSP1_1||PLATFORM_USES_FSP1_0) + +if STM + +config MSEG_SIZE + hex "mseg size" + default 0x400000 + +endif #STM + +endmenu diff --git a/src/security/intel/stm/Makefile.inc b/src/security/intel/stm/Makefile.inc new file mode 100644 index 0000000..24d7bac --- /dev/null +++ b/src/security/intel/stm/Makefile.inc @@ -0,0 +1,16 @@ + +# put the stm where is can be found + +cbfs-files-y += stm.bin +stm.bin-file = stm.bin +stm.bin-type = raw + +ramstage-y += SmmStm.c +ramstage-y += StmPlatformSmm.c +ramstage-y += StmPlatformResource.c + +smm-y += StmPlatformResource.c +smm-y += SmmStm.c +smm-y += StmPlatformSmm.c + + diff --git a/src/security/intel/stm/SmmStm.c b/src/security/intel/stm/SmmStm.c new file mode 100644 index 0000000..677d514 --- /dev/null +++ b/src/security/intel/stm/SmmStm.c @@ -0,0 +1,894 @@ +/** @file + + SMM STM support + + Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved. + + This program and the accompanying materials are licensed and made available + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <security/intel/stm/SmmStm.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/cr.h> +#include <string.h> +#include <cpu/x86/mp.h> +#include <console/console.h> + +#define TXT_EVTYPE_BASE 0x400 +#define TXT_EVTYPE_STM_HASH (TXT_EVTYPE_BASE + 14) + +#define RDWR_ACCS 3 +#define FULL_ACCS 7 + +#define SIZE_4KB 0x00001000 +#define SIZE_4MB 0x00400000 + +#define IA32_PG_P (1<<0) +#define IA32_PG_RW (1<<1) +#define IA32_PG_PS (1<<7) + +#define STM_PAGE_SHIFT 12 +#define STM_PAGE_MASK 0xFFF +#define STM_SIZE_TO_PAGES(a) (((a) >> STM_PAGE_SHIFT) + (((a) & STM_PAGE_MASK) ? 1 : 0)) +#define STM_PAGES_TO_SIZE(a) ((a) << STM_PAGE_SHIFT) + +#define STM_ACCESS_DENIED 15 +#define STM_UNSUPPORTED 3 + +#define STM_BUFFER_TOO_SMALL 1 + +#define STM_SM_MONITOR_STATE_ENABLED 1 + +#define RESOURCEHEAPSIZE 4096 + +uint32_t GetVmcsSize(void); +void StmGen4GPageTableIa32(uint32_t PageTableBase); +void StmGen4GPageTableX64(uint32_t PageTableBase); +bool StmCheckStmImage(void * StmImage, uint32_t StmImageSize); +void StmLoadStmImage(void * StmImage, UINTN StmImageSize); + +bool HandleSingleResource(STM_RSC *Resource, STM_RSC *Record); +void AddSingleResource(STM_RSC *Resource); +void AddResource(STM_RSC *ResourceList, uint32_t NumEntries); +bool ValidateResource(STM_RSC *ResourceList, uint32_t NumEntries); +UINTN GetResourceSize(STM_RSC *ResourceList, uint32_t NumEntries); + +typedef struct { + + uint64_t VmcsRevisionID:31; + uint64_t AlwaysZero:1; + uint64_t VmcsSize:13; + uint64_t Reserved1:3; + uint64_t VmxonAddWidth:1; + uint64_t StmSupported:1; + uint64_t VmcsMemoryType:4; + uint64_t InOutReporting:1; + uint64_t MayClearDefaults:1; + uint64_t Reserved2:8; +} VMX_BASIC_MSR_BITS; + +typedef union { + VMX_BASIC_MSR_BITS bits; + uint64_t uint64; + msr_t msr; +} VMX_BASIC_MSR; + +typedef struct { + uint64_t valid:1; + uint64_t reserved1:1; + uint64_t VmxOffBlockSmi:1; + uint64_t reserved2:9; + uint64_t MsegAddress:20; + uint64_t reserved3:32; +} SMM_MONITOR_CTL_MSR_BITS; + +extern struct mp_state { + struct mp_ops ops; + int cpu_count; + uintptr_t perm_smbase; + size_t perm_smsize; + size_t smm_save_state_size; + int do_smm; +} mp_state; + +typedef union { + SMM_MONITOR_CTL_MSR_BITS bits; + uint64_t uint64; + msr_t msr; +} SMM_MONITOR_CTL_MSR; + +// +// Template of STM_RSC_END structure for copying. +// + +STM_RSC_END mRscEndNode = { + {END_OF_RESOURCES, sizeof(STM_RSC_END)}, +}; + +uint8_t *mStmResourcesPtr = NULL; +UINTN mStmResourceTotalSize = 0x0; +UINTN mStmResourceSizeUsed = 0x0; +UINTN mStmResourceSizeAvailable = 0x0; + +uint8_t StmResourceHeap[RESOURCEHEAPSIZE]; + +uint32_t mStmState = 0; + +/** + + Handle single Resource to see if it can be merged into Record. + + @param Resource A pointer to resource node to be added + @param Record A pointer to record node to be merged + + @retval true resource handled + @retval false resource is not handled + +**/ + +bool +HandleSingleResource( + STM_RSC *Resource, + STM_RSC *Record + ) +{ + uint64_t ResourceLo; + uint64_t ResourceHi; + uint64_t RecordLo; + uint64_t RecordHi; + + ResourceLo = 0; + ResourceHi = 0; + RecordLo = 0; + RecordHi = 0; + + // + // Calling code is responsible for making sure that + // Resource->Header.RscType == (*Record)->Header.RscType + // thus we use just one of them as switch variable. + // + + switch (Resource->Header.RscType) { + case MEM_RANGE: + case MMIO_RANGE: + ResourceLo = Resource->Mem.Base; + ResourceHi = Resource->Mem.Base + Resource->Mem.Length; + RecordLo = Record->Mem.Base; + RecordHi = Record->Mem.Base + Record->Mem.Length; + if (Resource->Mem.RWXAttributes != Record->Mem.RWXAttributes) { + if ((ResourceLo == RecordLo) && (ResourceHi == RecordHi)) { + Record->Mem.RWXAttributes = Resource->Mem.RWXAttributes | Record->Mem.RWXAttributes; + return true; + } else { + return false; + } + } + break; + case IO_RANGE: + case TRAPPED_IO_RANGE: + ResourceLo = (uint64_t) Resource->Io.Base; + ResourceHi = (uint64_t) Resource->Io.Base + (uint64_t) Resource->Io.Length; + RecordLo = (uint64_t) Record->Io.Base; + RecordHi = (uint64_t) Record->Io.Base + (uint64_t) Record->Io.Length; + break; + case PCI_CFG_RANGE: + if ((Resource->PciCfg.OriginatingBusNumber != Record->PciCfg.OriginatingBusNumber) || + (Resource->PciCfg.LastNodeIndex != Record->PciCfg.LastNodeIndex)) { + return false; + } + if (memcmp (Resource->PciCfg.PciDevicePath, Record->PciCfg.PciDevicePath, sizeof(STM_PCI_DEVICE_PATH_NODE) * (Resource->PciCfg.LastNodeIndex + 1)) != 0) { + return false; + } + ResourceLo = (uint64_t) Resource->PciCfg.Base; + ResourceHi = (uint64_t) Resource->PciCfg.Base + (uint64_t) Resource->PciCfg.Length; + RecordLo = (uint64_t) Record->PciCfg.Base; + RecordHi = (uint64_t) Record->PciCfg.Base + (uint64_t) Record->PciCfg.Length; + if (Resource->PciCfg.RWAttributes != Record->PciCfg.RWAttributes) { + if ((ResourceLo == RecordLo) && (ResourceHi == RecordHi)) { + Record->PciCfg.RWAttributes = Resource->PciCfg.RWAttributes | Record->PciCfg.RWAttributes; + return true; + } else { + return false; + } + } + break; + case MACHINE_SPECIFIC_REG: + // + // Special case - merge MSR masks in place. + // + if (Resource->Msr.MsrIndex != Record->Msr.MsrIndex) { + return false; + } + Record->Msr.ReadMask |= Resource->Msr.ReadMask; + Record->Msr.WriteMask |= Resource->Msr.WriteMask; + return true; + default: + return false; + } + // + // If resources are disjoint + // + if ((ResourceHi < RecordLo) || (ResourceLo > RecordHi)) { + return false; + } + + // + // If resource is consumed by record. + // + if ((ResourceLo >= RecordLo) && (ResourceHi <= RecordHi)) { + return true; + } + // + // Resources are overlapping. + // Resource and record are merged. + // + ResourceLo = (ResourceLo < RecordLo) ? ResourceLo : RecordLo; + ResourceHi = (ResourceHi > RecordHi) ? ResourceHi : RecordHi; + + switch (Resource->Header.RscType) { + case MEM_RANGE: + case MMIO_RANGE: + Record->Mem.Base = ResourceLo; + Record->Mem.Length = ResourceHi - ResourceLo; + break; + case IO_RANGE: + case TRAPPED_IO_RANGE: + Record->Io.Base = (uint64_t) ResourceLo; + Record->Io.Length = (uint64_t) (ResourceHi - ResourceLo); + break; + case PCI_CFG_RANGE: + Record->PciCfg.Base = (uint64_t) ResourceLo; + Record->PciCfg.Length = (uint64_t) (ResourceHi - ResourceLo); + break; + default: + return false; + } + + return true; +} + +/** + + Add resource node. + + @param Resource A pointer to resource node to be added + +**/ +void AddSingleResource(STM_RSC *Resource) +{ + STM_RSC *Record; + + Record = (STM_RSC *)mStmResourcesPtr; + + while (true) { + if (Record->Header.RscType == END_OF_RESOURCES) { + break; + } + // + // Go to next record if resource and record types don't match. + // + if (Resource->Header.RscType != Record->Header.RscType) { + Record = (STM_RSC *)((void *)Record + Record->Header.Length); + continue; + } + // + // Record is handled inside of procedure - don't adjust. + // + if (HandleSingleResource (Resource, Record)) { + return ; + } + Record = (STM_RSC *)((void *)Record + Record->Header.Length); + } + + // + // Add resource to the end of area. + // + memcpy ( + mStmResourcesPtr + mStmResourceSizeUsed - sizeof(mRscEndNode), + Resource, + Resource->Header.Length + ); + memcpy ( + mStmResourcesPtr + mStmResourceSizeUsed - sizeof(mRscEndNode) + Resource->Header.Length, + &mRscEndNode, + sizeof(mRscEndNode) + ); + mStmResourceSizeUsed += Resource->Header.Length; + mStmResourceSizeAvailable = mStmResourceTotalSize - mStmResourceSizeUsed; + + return ; +} + +/** + + Add resource list. + + @param ResourceList A pointer to resource list to be added + @param NumEntries Optional number of entries. + If 0, list must be terminated by END_OF_RESOURCES. + +**/ +void AddResource(STM_RSC *ResourceList, uint32_t NumEntries) +{ + uint32_t Count; + UINTN Index; + STM_RSC *Resource; + + if (NumEntries == 0) { + Count = 0xFFFFFFFF; + } else { + Count = NumEntries; + } + + Resource = ResourceList; + + for (Index = 0; Index < Count; Index++) { + if (Resource->Header.RscType == END_OF_RESOURCES) { + return ; + } + AddSingleResource (Resource); + Resource = (STM_RSC *)((void *)Resource + Resource->Header.Length); + } + return ; +} + +/** + + Validate resource list. + + @param ResourceList A pointer to resource list to be added + @param NumEntries Optional number of entries. + If 0, list must be terminated by END_OF_RESOURCES. + + @retval true resource valid + @retval false resource invalid + +**/ +bool +ValidateResource ( + STM_RSC *ResourceList, + uint32_t NumEntries + ) +{ + uint32_t Count; + UINTN Index; + STM_RSC *Resource; + UINTN SubIndex; + + // + // If NumEntries == 0 make it very big. Scan will be terminated by + // END_OF_RESOURCES. + // + if (NumEntries == 0) { + Count = 0xFFFFFFFF; + } else { + Count = NumEntries; + } + + // + // Start from beginning of resource list. + // + Resource = ResourceList; + + for (Index = 0; Index < Count; Index++) { + printk(BIOS_DEBUG, "ValidateResource (%llu) - RscType(%x)\n", Index, Resource->Header.RscType); + // + // Validate resource. + // + switch (Resource->Header.RscType) { + case END_OF_RESOURCES: + if (Resource->Header.Length != sizeof (STM_RSC_END)) { + return false; + } + // + // If we are passed actual number of resources to add, + // END_OF_RESOURCES structure between them is considered an + // error. If NumEntries == 0 END_OF_RESOURCES is a termination. + // + if (NumEntries != 0) { + return false; + } else { + // + // If NumEntries == 0 and list reached end - return success. + // + return true; + } + break; + + case MEM_RANGE: + case MMIO_RANGE: + if (Resource->Header.Length != sizeof (STM_RSC_MEM_DESC)) { + return false; + } + + if (Resource->Mem.RWXAttributes > FULL_ACCS) { + return false; + } + break; + + case IO_RANGE: + case TRAPPED_IO_RANGE: + if (Resource->Header.Length != sizeof (STM_RSC_IO_DESC)) { + return false; + } + + if ((Resource->Io.Base + Resource->Io.Length) > 0xFFFF) { + return false; + } + break; + + case PCI_CFG_RANGE: + printk(BIOS_DEBUG, "ValidateResource - PCI (0x%02x, 0x%08x, 0x%02x, 0x%02x)\n", Resource->PciCfg.OriginatingBusNumber, Resource->PciCfg.LastNodeIndex, Resource->PciCfg.PciDevicePath[0].PciDevice, Resource->PciCfg.PciDevicePath[0].PciFunction); + if (Resource->Header.Length != sizeof (STM_RSC_PCI_CFG_DESC) + (sizeof(STM_PCI_DEVICE_PATH_NODE) * Resource->PciCfg.LastNodeIndex)) { + return false; + } + for (SubIndex = 0; SubIndex <= Resource->PciCfg.LastNodeIndex; SubIndex++) { + if ((Resource->PciCfg.PciDevicePath[SubIndex].PciDevice > 0x1F) || (Resource->PciCfg.PciDevicePath[SubIndex].PciFunction > 7)) { + return false; + } + } + if ((Resource->PciCfg.Base + Resource->PciCfg.Length) > 0x1000) { + return false; + } + break; + + case MACHINE_SPECIFIC_REG: + if (Resource->Header.Length != sizeof (STM_RSC_MSR_DESC)) { + return false; + } + break; + + default : + printk(BIOS_DEBUG, "ValidateResource - Unknown RscType(%x)\n", Resource->Header.RscType); + return false; + } + Resource = (STM_RSC *)((void *)Resource + Resource->Header.Length); + } + return true; +} + +/** + + Get resource list. + EndResource is excluded. + + @param ResourceList A pointer to resource list to be added + @param NumEntries Optional number of entries. + If 0, list must be terminated by END_OF_RESOURCES. + + @retval true resource valid + @retval false resource invalid + +**/ +UINTN +GetResourceSize ( + STM_RSC *ResourceList, + uint32_t NumEntries + ) +{ + uint32_t Count; + UINTN Index; + STM_RSC *Resource; + + Resource = ResourceList; + + // + // If NumEntries == 0 make it very big. Scan will be terminated by + // END_OF_RESOURCES. + // + if (NumEntries == 0) { + Count = 0xFFFFFFFF; + } else { + Count = NumEntries; + } + + // + // Start from beginning of resource list. + // + Resource = ResourceList; + + for (Index = 0; Index < Count; Index++) { + if (Resource->Header.RscType == END_OF_RESOURCES) { + break; + } + Resource = (STM_RSC *)((void *)Resource + Resource->Header.Length); + } + return (UINTN)((uint32_t)Resource - (uint32_t) ResourceList); +} + +/** + + Add resources in list to database. Allocate new memory areas as needed. + + @param ResourceList A pointer to resource list to be added + @param NumEntries Optional number of entries. + If 0, list must be terminated by END_OF_RESOURCES. + + @retval EFI_SUCCESS If resources are added + @retval EFI_INVALID_PARAMETER If nested procedure detected resource failer + @retval EFI_OUT_OF_RESOURCES If nested procedure returned it and we cannot allocate more areas. + +**/ +int +AddPiResource ( + STM_RSC *ResourceList, + uint32_t NumEntries + ) +{ + //int Status; + UINTN ResourceSize; + //void * NewResource; + //UINTN NewResourceSize; + + printk (BIOS_DEBUG, "AddPiResource - Enter\n"); + + if (!ValidateResource (ResourceList, NumEntries)) { + return -1; //EFI_INVALID_PARAMETER; + } + + ResourceSize = GetResourceSize (ResourceList, NumEntries); + printk (BIOS_DEBUG, "ResourceSize - 0x%08llx\n", ResourceSize); + if (ResourceSize == 0) { + return -1;//EFI_INVALID_PARAMETER; + } + + if (mStmResourcesPtr == NULL) { + // + // Copy EndResource for intialization + // + //mStmResourcesPtr = (uint8_t *)(UINTN)NewResource; + //mStmResourceTotalSize = NewResourceSize; + + mStmResourcesPtr = StmResourceHeap; + mStmResourceTotalSize = RESOURCEHEAPSIZE; + memset(mStmResourcesPtr, 0, RESOURCEHEAPSIZE); + + memcpy (mStmResourcesPtr, &mRscEndNode, sizeof(mRscEndNode)); + mStmResourceSizeUsed = sizeof(mRscEndNode); + mStmResourceSizeAvailable = mStmResourceTotalSize - sizeof(mRscEndNode); + + // + // Let SmmCore change resource ptr + // + //NotifyStmResourceChange (mStmResourcesPtr); + } else if (mStmResourceSizeAvailable < ResourceSize) { + // + // Need enlarge + // + printk(BIOS_DEBUG, "ERROR - not enough soace for SMM resource list\n"); + return -1; + } + + // + // Check duplication + // + AddResource (ResourceList, NumEntries); + + return 0;//EFI_SUCCESS; +} + +/** + + Delete resources in list to database. + + @param ResourceList A pointer to resource list to be deleted + NULL means delete all resources. + @param NumEntries Optional number of entries. + If 0, list must be terminated by END_OF_RESOURCES. + + @retval EFI_SUCCESS If resources are deleted + @retval EFI_INVALID_PARAMETER If nested procedure detected resource failer + +**/ +int32_t +DeletePiResource ( + STM_RSC *ResourceList, + uint32_t NumEntries + ) +{ + if (ResourceList != NULL) { + // TBD + //ASSERT (false); + return -1;//EFI_UNSUPPORTED; + } + // + // Delete all + // + memcpy (mStmResourcesPtr, &mRscEndNode, sizeof(mRscEndNode)); + mStmResourceSizeUsed = sizeof(mRscEndNode); + mStmResourceSizeAvailable = mStmResourceTotalSize - sizeof(mRscEndNode); + return 0;//EFI_SUCCESS; +} + +/** + + Get BIOS resources. + + @param ResourceList A pointer to resource list to be filled + @param ResourceSize On input it means size of resource list input. + On output it means size of resource list filled, + or the size of resource list to be filled if size of too small. + + @retval EFI_SUCCESS If resources are returned. + @retval EFI_BUFFER_TOO_SMALL If resource list buffer is too small to hold the whole resources. + +**/ +int32_t +GetPiResource ( + STM_RSC *ResourceList, + uint32_t *ResourceSize + ) +{ + if (*ResourceSize < mStmResourceSizeUsed) { + *ResourceSize = (uint32_t)mStmResourceSizeUsed; + return -1;//EFI_BUFFER_TOO_SMALL; + } + + memcpy (ResourceList, mStmResourcesPtr, mStmResourceSizeUsed); + *ResourceSize = (uint32_t)mStmResourceSizeUsed; + return 0;//EFI_SUCCESS; +} + +/** + Get 4K page aligned VMCS size. + @return 4K page aligned VMCS size + +**/ +uint32_t +GetVmcsSize ( + void + ) +{ + uint32_t ThisVmcsSize; + VMX_BASIC_MSR MsrData64; + int StmSupport; + + MsrData64.msr = rdmsr (IA32_VMX_BASIC_MSR_INDEX); + + ThisVmcsSize = MsrData64.bits.VmcsSize; + StmSupport = MsrData64.bits.StmSupported; + printk(BIOS_DEBUG, "GetVmcsSize: Size %d StmSupport %d\n", ThisVmcsSize, StmSupport); + + // + // VMCS require 0x1000 alignment + // + ThisVmcsSize = STM_PAGES_TO_SIZE (STM_SIZE_TO_PAGES (ThisVmcsSize)); + + return ThisVmcsSize; +} + +/** + + Create 4G page table for STM. + 4M Non-PAE page table in IA32 version. + + @param PageTableBase The page table base in MSEG + +**/ +void +StmGen4GPageTableIa32 ( + uint32_t PageTableBase + ) +{ + UINTN Index; + uint32_t *Pte; + uint32_t Address; + + Pte = (uint32_t*)(uint32_t)PageTableBase; + + Address = 0; + for (Index = 0; Index < SIZE_4KB / sizeof (*Pte); Index++) { + *Pte = Address | IA32_PG_PS | IA32_PG_RW | IA32_PG_P; + Pte++; + Address += SIZE_4MB; + } + + return ; +} + +/** + + Create 4G page table for STM. + 2M PAE page table in X64 version. + + @param PageTableBase The page table base in MSEG + +**/ +void +StmGen4GPageTableX64 ( + uint32_t PageTableBase + ) +{ + UINTN Index; + UINTN SubIndex; + uint64_t *Pde; + uint64_t *Pte; + uint64_t *Pml4; + + Pml4 = (uint64_t*)(uint32_t) PageTableBase; + PageTableBase += SIZE_4KB; + *Pml4 = PageTableBase | IA32_PG_RW | IA32_PG_P; + + Pde = (uint64_t*)(uint32_t)PageTableBase; + PageTableBase += SIZE_4KB; + Pte = (uint64_t *)(uint32_t)PageTableBase; + + for (Index = 0; Index < 4; Index++) { + *Pde = PageTableBase | IA32_PG_RW | IA32_PG_P; + Pde++; + PageTableBase += SIZE_4KB; + + for (SubIndex = 0; SubIndex < SIZE_4KB / sizeof (*Pte); SubIndex++) { + *Pte = (((Index << 9) + SubIndex) << 21) | IA32_PG_PS | IA32_PG_RW | IA32_PG_P; + Pte++; + } + } + + return ; +} + +/** + + Check STM image size. + + @param StmImage STM image + @param StmImageSize STM image size + + @retval true check pass + @retval false check fail +**/ + +bool StmCheckStmImage ( + void * StmImage, + uint32_t StmImageSize + ) +{ + UINTN MinMsegSize; + STM_HEADER *StmHeader; + + StmHeader = (STM_HEADER *)StmImage; + + // + // Get Minimal required Mseg size + // + MinMsegSize = (STM_PAGES_TO_SIZE (STM_SIZE_TO_PAGES (StmHeader->SwStmHdr.StaticImageSize)) + + StmHeader->SwStmHdr.AdditionalDynamicMemorySize + + (StmHeader->SwStmHdr.PerProcDynamicMemorySize + GetVmcsSize () * 2) * mp_state.cpu_count); + if (MinMsegSize < StmImageSize) { + MinMsegSize = StmImageSize; + } + + if (StmHeader->HwStmHdr.Cr3Offset >= StmHeader->SwStmHdr.StaticImageSize) { + // + // We will create page table, just in case that SINIT does not create it. + // + if (MinMsegSize < StmHeader->HwStmHdr.Cr3Offset + STM_PAGES_TO_SIZE(6)) { + MinMsegSize = StmHeader->HwStmHdr.Cr3Offset + STM_PAGES_TO_SIZE(6); + } + } + + // + // Check if it exceeds MSEG size + // + if (MinMsegSize > CONFIG_MSEG_SIZE) { + return false; + } + + return true; + +} + + +/** + + Load STM image to MSEG. + + @param StmImage STM image + @param StmImageSize STM image size + +**/ +void +StmLoadStmImage ( + void * StmImage, + UINTN StmImageSize + ) +{ + uint32_t MsegBase; + STM_HEADER *StmHeader; + SMM_MONITOR_CTL_MSR SmmMonitorMsr; + + StmHeader = (STM_HEADER *)(uint32_t)StmImage; + SmmMonitorMsr.msr = rdmsr(IA32_SMM_MONITOR_CTL_MSR_INDEX); + MsegBase = SmmMonitorMsr.bits.MsegAddress << 12; + + //ZeroMem ((void *)(uint32_t)MsegBase, (uint32_t)PcdGet32 (PcdCpuMsegSize)); + + memset((void *) MsegBase, 0, CONFIG_MSEG_SIZE); + //memcpy ((void *)(uint32_t)MsegBase, (void *)(uint32_t)StmImage, StmImageSize); + memcpy((void *) MsegBase, (void *) StmImage, (size_t) StmImageSize); + + + if (sizeof(UINTN) == sizeof(uint64_t)) { + StmGen4GPageTableX64 ((UINTN)MsegBase + StmHeader->HwStmHdr.Cr3Offset); + } else { + StmGen4GPageTableIa32 ((UINTN)MsegBase + StmHeader->HwStmHdr.Cr3Offset); + } + + // BUGBUG: SNB can not write 0x9B twice +// WriteCpuMsegInfo (); +} + +/** + + Load STM image to MSEG. + + @param StmImage STM image + @param StmImageSize STM image size + + @retval EFI_SUCCESS Load STM to MSEG successfully + @retval EFI_ALREADY_STARTED STM image is already loaded to MSEG + @retval EFI_BUFFER_TOO_SMALL MSEG is smaller than minimal requirement of STM image + @retval EFI_UNSUPPORTED MSEG is not enabled + +**/ +int LoadMonitor ( + void * StmImage, + uint32_t StmImageSize + ) +{ + SMM_MONITOR_CTL_MSR SmmMonCtlMsr; + + SmmMonCtlMsr.msr = (msr_t) rdmsr(IA32_SMM_MONITOR_CTL_MSR_INDEX); + + if (SmmMonCtlMsr.bits.MsegAddress == 0) { + return STM_UNSUPPORTED; + } + if (SmmMonCtlMsr.bits.valid != 0) { + // BUGBUG: SNB can not write 0x9B twice +// return EFI_ALREADY_STARTED; + } + + if (!StmCheckStmImage (StmImage, StmImageSize)) { + return STM_BUFFER_TOO_SMALL; + } + +#ifdef TPMSUPPORT + // Record STM_HASH to PCR 0, just in case it is NOT TXT launch, we still need provide the evidence. + TpmMeasureAndLogData( + 0, // PcrIndex + TXT_EVTYPE_STM_HASH, // EventType + NULL, // EventLog + 0, // LogLen + (void *)StmImage, // HashData + StmImageSize // HashDataLen + ); +#endif + StmLoadStmImage (StmImage, StmImageSize); + + mStmState |= STM_SM_MONITOR_STATE_ENABLED; + + return STM_SUCCESS; +} + +/** + This function return BIOS STM resource. + Produced by SmmStm. + Comsumed by SmmMpService when Init. + + @return BIOS STM resource +**/ +void * +GetStmResource( + void + ) +{ + return mStmResourcesPtr; +} + diff --git a/src/security/intel/stm/SmmStm.h b/src/security/intel/stm/SmmStm.h new file mode 100644 index 0000000..4442a63 --- /dev/null +++ b/src/security/intel/stm/SmmStm.h @@ -0,0 +1,122 @@ +/** @file + SMM STM support + + Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved. + This program and the accompanying materials are licensed and made + available under the terms and conditions of the BSD License which + accompanies this distribution. The full text of the license may + be found at http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED + +**/ + +#ifndef _SMM_STM_H_ +#define _SMM_STM_H_ + +#include "StmApi.h" + +#define IA32_VMX_BASIC_MSR_INDEX 0x480 +#define IA32_VMX_MISC_MSR_INDEX 0x485 +#define IA32_SMM_MONITOR_CTL_MSR_INDEX 0x9B +#define IA32_SMM_MONITOR_VALID (1<<0) + +/** + + Load STM image to MSEG. + + @param StmImage STM image + @param StmImageSize STM image size + + @retval SUCCESS Load STM to MSEG successfully + @retval BUFFER_TOO_SMALL MSEG is smaller than minimal size of STM image + +**/ +int LoadMonitor( + void *StmImage, + uint32_t StmImageSize + ); + +/** + + Add resources in list to database. Allocate new memory areas as needed. + + @param ResourceList A pointer to resource list to be added + @param NumEntries Optional number of entries. + If 0, list must be terminated by END_OF_RESOURCES. + + @retval SUCCESS If resources are added + @retval INVALID_PARAMETER If nested procedure detected resource failer + @retval OUT_OF_RESOURCES If nested procedure returned it and we cannot allocate more areas. + +**/ +int AddPiResource( + STM_RSC *ResourceList, + uint32_t NumEntries + ); + +/** + + Delete resources in list to database. + + @param ResourceList A pointer to resource list to be deleted + NULL means delete all resources. + @param NumEntries Optional number of entries. + If 0, list must be terminated by END_OF_RESOURCES. + + @retval SUCCESS If resources are deleted + @retval NVALID_PARAMETER If nested procedure detected resource failer + +**/ +int DeletePiResource( + STM_RSC *ResourceList, + uint32_t NumEntries + ); + +/** + + Get BIOS resources. + + @param ResourceList A pointer to resource list to be filled + @param ResourceSize On input it means size of resource list input. + On output it means size of resource list filled, + or the size of resource list to be filled if + size of too small. + + @retval SUCCESS If resources are returned. + @retval BUFFER_TOO_SMALL If resource list buffer is too small to + hold the whole resources. + +**/ +int GetPiResource( + STM_RSC *ResourceList, + uint32_t *ResourceSize + ); + +/** + This function notify STM resource change. + + @param StmResource BIOS STM resource + +**/ +void +NotifyStmResourceChange( + void *StmResource + ); + +/** + This function return BIOS STM resource. + + @return BIOS STM resource + +**/ +void * +GetStmResource( + void + ); + +void SetupSmmDescriptor(void *smbase, int32_t state_size, int32_t apic_id, + int32_t entry32_off); + +#endif diff --git a/src/security/intel/stm/StmApi.h b/src/security/intel/stm/StmApi.h new file mode 100644 index 0000000..2328b32 --- /dev/null +++ b/src/security/intel/stm/StmApi.h @@ -0,0 +1,753 @@ +/** @file + STM API definition + + Copyright (c) 2015, Intel Corporation. All rights reserved. + This program and the accompanying materials are licensed and made available + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _STM_API_H_ +#define _STM_API_H_ + +#include <stdint.h> + +// definition in STM spec + +#define STM_SPEC_VERSION_MAJOR 1 +#define STM_SPEC_VERSION_MINOR 0 + +typedef uint64_t UINTN; + +#pragma pack (push, 1) + +#define STM_HARDWARE_FIELD_FILL_TO_2K (2048 - sizeof(uint32_t) * 8) +typedef struct { + uint32_t StmHeaderRevision; + uint32_t MonitorFeatures; + uint32_t GdtrLimit; + uint32_t GdtrBaseOffset; + uint32_t CsSelector; + uint32_t EipOffset; + uint32_t EspOffset; + uint32_t Cr3Offset; + uint8_t Reserved[STM_HARDWARE_FIELD_FILL_TO_2K]; +} HARDWARE_STM_HEADER; + +#define STM_FEATURES_IA32E 0x1 + +typedef struct { + uint32_t Intel64ModeSupported :1; // bitfield + uint32_t EptSupported :1; // bitfield + uint32_t Reserved :30; // must be 0 +} STM_FEAT; + +typedef struct { + uint8_t StmSpecVerMajor; + uint8_t StmSpecVerMinor; + uint16_t Reserved; // must be zero + uint32_t StaticImageSize; + uint32_t PerProcDynamicMemorySize; + uint32_t AdditionalDynamicMemorySize; + STM_FEAT StmFeatures; + uint32_t NumberOfRevIDs; + uint32_t StmSmmRevID[1]; + // + // The total STM_HEADER should be 4K. + // +} SOFTWARE_STM_HEADER; + +typedef struct { + HARDWARE_STM_HEADER HwStmHdr; + SOFTWARE_STM_HEADER SwStmHdr; +} STM_HEADER; + +#define SHA1 1 +#define SHA256 2 +typedef struct { + uint64_t BiosComponentBase; + uint32_t ImageSize; + uint32_t HashAlgorithm; // SHA1 or SHA256 + uint8_t Hash[32]; +} TXT_BIOS_COMPONENT_STATUS; + +#define PAGE_SIZE 4096 +typedef struct { + uint32_t ImageSize; + uint32_t Reserved; + uint64_t ImagePageBase[1]; //[NumberOfPages]; +} TXT_BIOS_COMPONENT_UPDATE; + +// If (ImageSizeInBytes % PAGE_SIZE == 0) { +// NumberOfPages = ImageSizeInBytes / PAGE_SIZE +// } else { +// NumberOfPages = ImageSizeInBytes / PAGE_SIZE + 1 +// } + + +typedef struct { + uint64_t SpeRip; + uint64_t SpeRsp; + uint16_t SpeSs; + uint16_t PageViolationException:1; + uint16_t MsrViolationException:1; + uint16_t RegisterViolationException:1; + uint16_t IoViolationException:1; + uint16_t PciViolationException:1; + uint16_t Reserved1:11; + uint32_t Reserved2; +} STM_PROTECTION_EXCEPTION_HANDLER; + +typedef struct { + uint8_t ExecutionDisableOutsideSmrr:1; + uint8_t Intel64Mode:1; + uint8_t Cr4Pae : 1; + uint8_t Cr4Pse : 1; + uint8_t Reserved1 : 4; +} STM_SMM_ENTRY_STATE; + +typedef struct { + uint8_t SmramToVmcsRestoreRequired : 1; // BIOS restore hint + uint8_t ReinitializeVmcsRequired : 1; // BIOS request + uint8_t Reserved2 : 6; +} STM_SMM_RESUME_STATE; + +typedef struct { + uint8_t DomainType : 4; // STM input to BIOS on each SM + uint8_t XStatePolicy : 2; // STM input to BIOS on each SMI + uint8_t EptEnabled : 1; + uint8_t Reserved3 : 1; +} STM_SMM_STATE; + +typedef struct { + uint64_t Signature; + uint16_t Size; + uint8_t SmmDescriptorVerMajor; + uint8_t SmmDescriptorVerMinor; + uint32_t LocalApicId; + STM_SMM_ENTRY_STATE SmmEntryState; + STM_SMM_RESUME_STATE SmmResumeState; + STM_SMM_STATE StmSmmState; + uint8_t Reserved4; + uint16_t SmmCs; + uint16_t SmmDs; + uint16_t SmmSs; + uint16_t SmmOtherSegment; + uint16_t SmmTr; + uint16_t Reserved5; + uint64_t SmmCr3; + uint64_t SmmStmSetupRip; + uint64_t SmmStmTeardownRip; + uint64_t SmmSmiHandlerRip; + uint64_t SmmSmiHandlerRsp; + uint64_t SmmGdtPtr; + uint32_t SmmGdtSize; + uint32_t RequiredStmSmmRevId; + STM_PROTECTION_EXCEPTION_HANDLER StmProtectionExceptionHandler; + uint64_t Reserved6; + uint64_t BiosHwResourceRequirementsPtr; + // extend area + uint64_t AcpiRsdp; + uint8_t PhysicalAddressBits; +} TXT_PROCESSOR_SMM_DESCRIPTOR; + +#define TXT_PROCESSOR_SMM_DESCRIPTOR_SIGNATURE "TXTPSSIG" +#define TXT_PROCESSOR_SMM_DESCRIPTOR_VERSION_MAJOR 1 +#define TXT_PROCESSOR_SMM_DESCRIPTOR_VERSION_MINOR 0 + +#define SMM_PSD_OFFSET 0xfb00 + +typedef enum { + TxtSmmPageViolation = 1, + TxtSmmMsrViolation, + TxtSmmRegisterViolation, + TxtSmmIoViolation, + TxtSmmPciViolation +} TXT_SMM_PROTECTION_EXCEPTION_TYPE; + +typedef struct { + uint32_t Rdi; + uint32_t Rsi; + uint32_t Rbp; + uint32_t Rdx; + uint32_t Rcx; + uint32_t Rbx; + uint32_t Rax; + uint32_t Cr3; + uint32_t Cr2; + uint32_t Cr0; + uint32_t VmcsExitInstructionInfo; + uint32_t VmcsExitInstructionLength; + uint64_t VmcsExitQualification; + uint32_t ErrorCode; // TXT_SMM_PROTECTION_EXCEPTION_TYPE + uint32_t Rip; + uint32_t Cs; + uint32_t Rflags; + uint32_t Rsp; + uint32_t Ss; +} STM_PROTECTION_EXCEPTION_STACK_FRAME_IA32; + +typedef struct { + uint64_t R15; + uint64_t R14; + uint64_t R13; + uint64_t R12; + uint64_t R11; + uint64_t R10; + uint64_t R9; + uint64_t R8; + uint64_t Rdi; + uint64_t Rsi; + uint64_t Rbp; + uint64_t Rdx; + uint64_t Rcx; + uint64_t Rbx; + uint64_t Rax; + uint64_t Cr8; + uint64_t Cr3; + uint64_t Cr2; + uint64_t Cr0; + uint64_t VmcsExitInstructionInfo; + uint64_t VmcsExitInstructionLength; + uint64_t VmcsExitQualification; + uint64_t ErrorCode; // TXT_SMM_PROTECTION_EXCEPTION_TYPE + uint64_t Rip; + uint64_t Cs; + uint64_t Rflags; + uint64_t Rsp; + uint64_t Ss; +} STM_PROTECTION_EXCEPTION_STACK_FRAME_X64; + +typedef union { + STM_PROTECTION_EXCEPTION_STACK_FRAME_IA32 *Ia32StackFrame; + STM_PROTECTION_EXCEPTION_STACK_FRAME_X64 *X64StackFrame; +} STM_PROTECTION_EXCEPTION_STACK_FRAME; + +#define STM_SMM_REV_ID 0x80010100 + +typedef struct _STM_SMM_CPU_STATE { + uint8_t Reserved1[0x1d0]; // fc00h + uint32_t GdtBaseHiDword; // fdd0h : NO + uint32_t LdtBaseHiDword; // fdd4h : NO + uint32_t IdtBaseHiDword; // fdd8h : NO + uint8_t Reserved2[0x4]; // fddch + uint64_t IoRdi; // fde0h : NO + // - restricted + uint64_t IoEip; // fde8h : YES + uint64_t IoRcx; // fdf0h : NO + // - restricted + uint64_t IoRsi; // fdf8h : NO + // - restricted + uint8_t Reserved3[0x40]; // fe00h + uint32_t Cr4; // fe40h : NO + uint8_t Reserved4[0x48]; // fe44h + uint32_t GdtBaseLoDword; // fe8ch : NO + uint32_t GdtLimit; // fe90h : NO + // - RESTRICTED + uint32_t IdtBaseLoDword; // fe94h : NO + uint32_t IdtLimit; // fe98h : NO + // - RESTRICTED + uint32_t LdtBaseLoDword; // fe9ch : NO + uint32_t LdtLimit; // fea0h : NO + // - RESTRICTED + uint32_t LdtInfo; // fea4h : NO + // - RESTRICTED + uint8_t Reserved5[0x30]; // fea8h + uint64_t Eptp; // fed8h : NO + uint32_t EnabledEPT; // fee0h : NO + uint8_t Reserved6[0x14]; // fee4h + uint32_t Smbase; // fef8h : YES + // - NO for STM + uint32_t SMMRevId; // fefch : NO + uint16_t IORestart; // ff00h : YES + uint16_t AutoHALTRestart; // ff02h : YES + uint8_t Reserved7[0x18]; // ff04h + uint64_t R15; // ff1ch : YES + uint64_t R14; // ff24h : YES + uint64_t R13; // ff2ch : YES + uint64_t R12; // ff34h : YES + uint64_t R11; // ff3ch : YES + uint64_t R10; // ff44h : YES + uint64_t R9; // ff4ch : YES + uint64_t R8; // ff54h : YES + uint64_t Rax; // ff5ch : YES + uint64_t Rcx; // ff64h : YES + uint64_t Rdx; // ff6ch : YES + uint64_t Rbx; // ff74h : YES + uint64_t Rsp; // ff7ch : YES + uint64_t Rbp; // ff84h : YES + uint64_t Rsi; // ff8ch : YES + uint64_t Rdi; // ff94h : YES + uint64_t IOMemAddr; // ff9ch : NO + uint32_t IOMisc; // ffa4h : NO + uint32_t Es; // ffa8h : NO + uint32_t Cs; // ffach : NO + uint32_t Ss; // ffb0h : NO + uint32_t Ds; // ffb4h : NO + uint32_t Fs; // ffb8h : NO + uint32_t Gs; // ffbch : NO + uint32_t Ldtr; // ffc0h : NO + uint32_t Tr; // ffc4h : NO + uint64_t Dr7; // ffc8h : NO + uint64_t Dr6; // ffd0h : NO + uint64_t Rip; // ffd8h : YES + uint64_t Ia32Efer; // ffe0h : YES + // - NO for STM + uint64_t Rflags; // ffe8h : YES + uint64_t Cr3; // fff0h : NO + uint64_t Cr0; // fff8h : NO +} STM_SMM_CPU_STATE; + +// +// STM Mapping +// + +typedef struct { + uint64_t PhysicalAddress; + uint64_t VirtualAddress; + uint32_t PageCount; + uint32_t PatCacheType; +} STM_MAP_ADDRESS_RANGE_DESCRIPTOR; +#define ST_UC 0x00 +#define WC 0x01 +#define WT 0x04 +#define WP 0x05 +#define WB 0x06 +#define UC 0x07 +#define FOLLOW_MTRR 0xFFFFFFFF + +typedef struct { + uint64_t VirtualAddress; + uint32_t Length; +} STM_UNMAP_ADDRESS_RANGE_DESCRIPTOR; + +typedef struct { + uint64_t InterruptedGuestVirtualAddress; + uint32_t Length; + uint64_t InterruptedCr3; + uint64_t InterruptedEptp; + uint32_t MapToSmmGuest:2; + uint32_t InterruptedCr4Pae:1; + uint32_t InterruptedCr4Pse:1; + uint32_t InterruptedIa32eMode:1; + uint32_t Reserved1:27; + uint32_t Reserved2; + uint64_t PhysicalAddress; + uint64_t SmmGuestVirtualAddress; +} STM_ADDRESS_LOOKUP_DESCRIPTOR; +#define DO_NOT_MAP 0 +#define ONE_TO_ONE 1 +#define VIRTUAL_ADDRESS_SPECIFIED 3 + +// +// STM_RESOURCE_LIST +// +#define END_OF_RESOURCES 0 +#define MEM_RANGE 1 +#define IO_RANGE 2 +#define MMIO_RANGE 3 +#define MACHINE_SPECIFIC_REG 4 +#define PCI_CFG_RANGE 5 +#define TRAPPED_IO_RANGE 6 +#define ALL_RESOURCES 7 +#define REGISTER_VIOLATION 8 +#define MAX_DESC_TYPE 8 + +typedef struct { + uint32_t RscType; + uint16_t Length; + uint16_t ReturnStatus:1; + uint16_t Reserved:14; + uint16_t IgnoreResource:1; +} STM_RSC_DESC_HEADER; + +typedef struct { + STM_RSC_DESC_HEADER Hdr; + uint64_t ResourceListContinuation; +} STM_RSC_END; + +// byte granular Memory range support +#define STM_RSC_BGM 0x4 + +typedef struct { + STM_RSC_DESC_HEADER Hdr; + uint64_t Base; + uint64_t Length; + uint32_t RWXAttributes:3; + uint32_t Reserved:29; + uint32_t Reserved_2; +} STM_RSC_MEM_DESC; +#define STM_RSC_MEM_R 0x1 +#define STM_RSC_MEM_W 0x2 +#define STM_RSC_MEM_X 0x4 + +typedef struct { + STM_RSC_DESC_HEADER Hdr; + uint16_t Base; + uint16_t Length; + uint32_t Reserved; +} STM_RSC_IO_DESC; + +// byte granular MMIO range support +#define STM_RSC_BGI 0x2 + +typedef struct { + STM_RSC_DESC_HEADER Hdr; + uint64_t Base; + uint64_t Length; + uint32_t RWXAttributes:3; + uint32_t Reserved:29; + uint32_t Reserved_2; +} STM_RSC_MMIO_DESC; +#define STM_RSC_MMIO_R 0x1 +#define STM_RSC_MMIO_W 0x2 +#define STM_RSC_MMIO_X 0x4 + +typedef struct { + STM_RSC_DESC_HEADER Hdr; + uint32_t MsrIndex; + uint32_t KernelModeProcessing:1; + uint32_t Reserved:31; + uint64_t ReadMask; + uint64_t WriteMask; +} STM_RSC_MSR_DESC; + +// bit granular MSR resource support +#define STM_RSC_MSR 0x8 + +typedef struct { + uint8_t Type; // must be 1, indicating Hardware Device Path + uint8_t Subtype; // must be 1, indicating PCI + uint16_t Length; // sizeof(STM_PCI_DEVICE_PATH_NODE) which is 6 + uint8_t PciFunction; + uint8_t PciDevice; +} STM_PCI_DEVICE_PATH_NODE; +typedef struct { + STM_RSC_DESC_HEADER Hdr; + uint16_t RWAttributes:2; + uint16_t Reserved:14; + uint16_t Base; + uint16_t Length; + uint8_t OriginatingBusNumber; + uint8_t LastNodeIndex; + STM_PCI_DEVICE_PATH_NODE PciDevicePath[1]; +//STM_PCI_DEVICE_PATH_NODE PciDevicePath[LastNodeIndex + 1]; +} STM_RSC_PCI_CFG_DESC; + +#define STM_RSC_PCI_CFG_R 0x1 +#define STM_RSC_PCI_CFG_W 0x2 + +typedef struct { + STM_RSC_DESC_HEADER Hdr; + uint16_t Base; + uint16_t Length; + uint16_t In:1; + uint16_t Out:1; + uint16_t Api:1; + uint16_t Reserved1:13; + uint16_t Reserved2; +} STM_RSC_TRAPPED_IO_DESC; + +typedef struct { + STM_RSC_DESC_HEADER Hdr; +} STM_RSC_ALL_RESOURCES_DESC; + +typedef struct { + STM_RSC_DESC_HEADER Hdr; + uint32_t RegisterType; + uint32_t Reserved; + uint64_t ReadMask; + uint64_t WriteMask; +} STM_REGISTER_VIOLATION_DESC; + +typedef enum { + StmRegisterCr0, + StmRegisterCr2, + StmRegisterCr3, + StmRegisterCr4, + StmRegisterCr8, + StmRegisterMax, +} STM_REGISTER_VIOLATION_TYPE; + +typedef union { + STM_RSC_DESC_HEADER Header; + STM_RSC_END End; + STM_RSC_MEM_DESC Mem; + STM_RSC_IO_DESC Io; + STM_RSC_MMIO_DESC Mmio; + STM_RSC_MSR_DESC Msr; + STM_RSC_PCI_CFG_DESC PciCfg; + STM_RSC_TRAPPED_IO_DESC TrappedIo; + STM_RSC_ALL_RESOURCES_DESC All; + STM_REGISTER_VIOLATION_DESC RegisterViolation; +} STM_RSC; + +// +// VMCS database +// +#define STM_VMCS_DATABASE_REQUEST_ADD 1 +#define STM_VMCS_DATABASE_REQUEST_REMOVE 0 + +// Values for DomainType +// Intepreter of DomainType +#define DOMAIN_DISALLOWED_IO_OUT (1u << 0) +#define DOMAIN_DISALLOWED_IO_IN (1u << 1) +#define DOMAIN_INTEGRITY (1u << 2) +#define DOMAIN_CONFIDENTIALITY (1u << 3) + +#define DOMAIN_UNPROTECTED 0x00 +#define DOMAIN_INTEGRITY_PROT_OUT_IN (DOMAIN_INTEGRITY) +//#define DOMAIN_INTEGRITY_PROT_OUT (DOMAIN_INTEGRITY | DOMAIN_DISALLOWED_IO_IN) +#define DOMAIN_FULLY_PROT_OUT_IN (DOMAIN_CONFIDENTIALITY | DOMAIN_INTEGRITY) +//#define DOMAIN_FULLY_PROT_IN (DOMAIN_CONFIDENTIALITY | DOMAIN_INTEGRITY | DOMAIN_DISALLOWED_IO_OUT) +//#define DOMAIN_FULLY_PROT_OUT (DOMAIN_CONFIDENTIALITY | DOMAIN_INTEGRITY | DOMAIN_DISALLOWED_IO_IN) +#define DOMAIN_FULLY_PROT (DOMAIN_CONFIDENTIALITY | DOMAIN_INTEGRITY | DOMAIN_DISALLOWED_IO_IN | DOMAIN_DISALLOWED_IO_OUT) + +// Values for XStatePolicy +#define XSTATE_READWRITE 0x00 +#define XSTATE_READONLY 0x01 +#define XSTATE_SCRUB 0x03 + +typedef struct { + uint64_t VmcsPhysPointer; // bits 11:0 are reserved and must be 0 + uint32_t DomainType :4; + uint32_t XStatePolicy :2; + uint32_t DegradationPolicy :4; + uint32_t Reserved1 :22; // Must be 0 + uint32_t AddOrRemove; +} STM_VMCS_DATABASE_REQUEST; + +// +// Event log +// +#define NEW_LOG 1 +#define CONFIGURE_LOG 2 +#define START_LOG 3 +#define STOP_LOG 4 +#define CLEAR_LOG 5 +#define DELETE_LOG 6 +typedef enum { + EvtLogStarted, + EvtLogStopped, + EvtLogInvalidParameterDetected, + EvtHandledProtectionException, + // unhandled protection exceptions result in reset & cannot be logged + EvtBiosAccessToUnclaimedResource, + EvtMleResourceProtectionGranted, + EvtMleResourceProtectionDenied, + EvtMleResourceUnprotect, + EvtMleResourceUnprotectError, + EvtMleDomainTypeDegraded, + // add more here + EvtMleMax, + // Not used + EvtInvalid = 0xFFFFFFFF, +} EVENT_TYPE; + +//#define STM_EVENT_LOG_PAGE_COUNT_MAX 62 + +typedef struct { + uint32_t PageCount; + uint64_t Pages[1]; // number of elements is PageCount +} STM_EVENT_LOG_MANAGEMENT_REQUEST_DATA_LOG_BUFFER; + +typedef union { + STM_EVENT_LOG_MANAGEMENT_REQUEST_DATA_LOG_BUFFER LogBuffer; + uint32_t EventEnableBitmap; // bitmap of EVENT_TYPE +} STM_EVENT_LOG_MANAGEMENT_REQUEST_DATA; + +typedef struct { + uint32_t SubFunctionIndex; + STM_EVENT_LOG_MANAGEMENT_REQUEST_DATA Data; +} STM_EVENT_LOG_MANAGEMENT_REQUEST; + +// +// VMCALL API Numbers +// + +// API number convention: BIOS facing VMCALL interfaces have bit 16 clear +#define STM_API_MAP_ADDRESS_RANGE 0x00000001 +#define STM_API_UNMAP_ADDRESS_RANGE 0x00000002 +#define STM_API_ADDRESS_LOOKUP 0x00000003 +#define STM_API_RETURN_FROM_PROTECTION_EXCEPTION 0x00000004 + +// API number convention: MLE facing VMCALL interfaces have bit 16 set +// +// The STM configuration lifecycle is as follows: +// 1. SENTER->SINIT->MLE: MLE begins execution with SMI disabled (masked). +// 2. MLE invokes InitializeProtectionVMCALL() to prepare STM for setup of +// initial protection profile. This is done on a single CPU and has global +// effect. +// 3. MLE invokes ProtectResourceVMCALL() to define the initial protection +// profile. The protection profile is global across all CPUs. +// 4. MLE invokes StartStmVMCALL() to enable the STM to begin receiving SMI +// events. This must be done on every logical CPU. +// 5. MLE may invoke ProtectResourceVMCALL() or UnProtectResourceVMCALL() +// during runtime as many times as necessary. +// 6. MLE invokes StopStmVMCALL() to disable the STM. SMI is again masked +// following StopStmVMCALL(). +// +#define STM_API_START 0x00010001 +#define STM_API_STOP 0x00010002 +#define STM_API_PROTECT_RESOURCE 0x00010003 +#define STM_API_UNPROTECT_RESOURCE 0x00010004 +#define STM_API_GET_BIOS_RESOURCES 0x00010005 +#define STM_API_MANAGE_VMCS_DATABASE 0x00010006 +#define STM_API_INITIALIZE_PROTECTION 0x00010007 +#define STM_API_MANAGE_EVENT_LOG 0x00010008 + +// +// Return codes +// +typedef uint32_t STM_STATUS; + +#define STM_SUCCESS 0x00000000 +#define SMM_SUCCESS 0x00000000 +// all error codes have bit 31 set +// STM errors have bit 16 set +#define ERROR_STM_SECURITY_VIOLATION 0x80010001 +#define ERROR_STM_CACHE_TYPE_NOT_SUPPORTED 0x80010002 +#define ERROR_STM_PAGE_NOT_FOUND 0x80010003 +#define ERROR_STM_BAD_CR3 0x80010004 +#define ERROR_STM_PHYSICAL_OVER_4G 0x80010005 +#define ERROR_STM_VIRTUAL_SPACE_TOO_SMALL 0x80010006 +#define ERROR_STM_UNPROTECTABLE_RESOURCE 0x80010007 +#define ERROR_STM_ALREADY_STARTED 0x80010008 +#define ERROR_STM_WITHOUT_SMX_UNSUPPORTED 0x80010009 +#define ERROR_STM_STOPPED 0x8001000A +#define ERROR_STM_BUFFER_TOO_SMALL 0x8001000B +#define ERROR_STM_INVALID_VMCS_DATABASE 0x8001000C +#define ERROR_STM_MALFORMED_RESOURCE_LIST 0x8001000D +#define ERROR_STM_INVALID_PAGECOUNT 0x8001000E +#define ERROR_STM_LOG_ALLOCATED 0x8001000F +#define ERROR_STM_LOG_NOT_ALLOCATED 0x80010010 +#define ERROR_STM_LOG_NOT_STOPPED 0x80010011 +#define ERROR_STM_LOG_NOT_STARTED 0x80010012 +#define ERROR_STM_RESERVED_BIT_SET 0x80010013 +#define ERROR_STM_NO_EVENTS_ENABLED 0x80010014 +#define ERROR_STM_OUT_OF_RESOURCES 0x80010015 +#define ERROR_STM_FUNCTION_NOT_SUPPORTED 0x80010016 +#define ERROR_STM_UNPROTECTABLE 0x80010017 +#define ERROR_STM_UNSUPPORTED_MSR_BIT 0x80010018 +#define ERROR_STM_UNSPECIFIED 0x8001FFFF + +// SMM errors have bit 17 set +#define ERROR_SMM_BAD_BUFFER 0x80020001 +#define ERROR_SMM_INVALID_RSC 0x80020004 +#define ERROR_SMM_INVALID_BUFFER_SIZE 0x80020005 +#define ERROR_SMM_BUFFER_TOO_SHORT 0x80020006 +#define ERROR_SMM_INVALID_LIST 0x80020007 +#define ERROR_SMM_OUT_OF_MEMORY 0x80020008 +#define ERROR_SMM_AFTER_INIT 0x80020009 +#define ERROR_SMM_UNSPECIFIED 0x8002FFFF + +// Errors that apply to both have bits 15, 16, and 17 set +#define ERROR_INVALID_API 0x80038001 +#define ERROR_INVALID_PARAMETER 0x80038002 + +// +// STM TXT.ERRORCODE codes +// +#define STM_CRASH_PROTECTION_EXCEPTION 0xC000F001 +#define STM_CRASH_PROTECTION_EXCEPTION_FAILURE 0xC000F002 +#define STM_CRASH_DOMAIN_DEGRADATION_FAILURE 0xC000F003 +#define STM_CRASH_BIOS_PANIC 0xC000E000 + +typedef struct { + uint32_t EventSerialNumber; + uint16_t Type; + uint16_t Lock :1; + uint16_t Valid :1; + uint16_t ReadByMle :1; + uint16_t Wrapped :1; + uint16_t Reserved :12; +} LOG_ENTRY_HEADER; + +typedef struct { + uint32_t Reserved; +} ENTRY_EVT_LOG_STARTED; + +typedef struct { + uint32_t Reserved; +} ENTRY_EVT_LOG_STOPPED; + +typedef struct { + uint32_t VmcallApiNumber; +} ENTRY_EVT_LOG_INVALID_PARAM; + +typedef struct { + STM_RSC Resource; +} ENTRY_EVT_LOG_HANDLED_PROTECTION_EXCEPTION; + +typedef struct { + STM_RSC Resource; +} ENTRY_EVT_BIOS_ACCESS_UNCLAIMED_RSC; + +typedef struct { + STM_RSC Resource; +} ENTRY_EVT_MLE_RSC_PROT_GRANTED; + +typedef struct { + STM_RSC Resource; +} ENTRY_EVT_MLE_RSC_PROT_DENIED; + +typedef struct { + STM_RSC Resource; +} ENTRY_EVT_MLE_RSC_UNPROT; + +typedef struct { + STM_RSC Resource; +} ENTRY_EVT_MLE_RSC_UNPROT_ERROR; + +typedef struct { + uint64_t VmcsPhysPointer; + uint8_t ExpectedDomainType; + uint8_t DegradedDomainType; +} ENTRY_EVT_MLE_DOMAIN_TYPE_DEGRADED; + +typedef union { + ENTRY_EVT_LOG_STARTED Started; + ENTRY_EVT_LOG_STOPPED Stopped; + ENTRY_EVT_LOG_INVALID_PARAM InvalidParam; + ENTRY_EVT_LOG_HANDLED_PROTECTION_EXCEPTION HandledProtectionException; + ENTRY_EVT_BIOS_ACCESS_UNCLAIMED_RSC BiosUnclaimedRsc; + ENTRY_EVT_MLE_RSC_PROT_GRANTED MleRscProtGranted; + ENTRY_EVT_MLE_RSC_PROT_DENIED MleRscProtDenied; + ENTRY_EVT_MLE_RSC_UNPROT MleRscUnprot; + ENTRY_EVT_MLE_RSC_UNPROT_ERROR MleRscUnprotError; + ENTRY_EVT_MLE_DOMAIN_TYPE_DEGRADED MleDomainTypeDegraded; +} LOG_ENTRY_DATA; + +typedef struct { + LOG_ENTRY_HEADER Hdr; + LOG_ENTRY_DATA Data; +} STM_LOG_ENTRY; + +#define STM_LOG_ENTRY_SIZE 256 + +// +// +// +#define STM_CONFIG_SMI_UNBLOCKING_BY_VMX_OFF 0x1 + +// +// TXT debug +// +#define SW_SMI_STM_ADD_RUNTIME_RESOURCES_SUB_FUNC 0 +#define SW_SMI_STM_READ_BIOS_RESOURCES_SUB_FUNC 1 +#define SW_SMI_STM_REPLACE_BIOS_RESOURCES_SUB_FUNC 2 + +typedef struct { + uint32_t BufferSize; + uint32_t Reserved; + //uint8_t Data[]; +} TXT_BIOS_DEBUG; + +#pragma pack (pop) + +#endif diff --git a/src/security/intel/stm/StmPlatformResource.c b/src/security/intel/stm/StmPlatformResource.c new file mode 100644 index 0000000..ad8a69b --- /dev/null +++ b/src/security/intel/stm/StmPlatformResource.c @@ -0,0 +1,259 @@ +/** @file + STM platform SMM resource + + Copyright (c) 2015, Intel Corporation. All rights reserved. + This program and the accompanying materials are licensed and made + available under the terms and conditions of the BSD License which + accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <stdint.h> +#include <security/intel/stm/StmApi.h> +#include <security/intel/stm/SmmStm.h> +#include <security/intel/stm/StmPlatformResource.h> + +#include <southbridge/intel/common/pmutil.h> +#include <cpu/x86/msr.h> + +#define RDWR_ACCS 3 +#define FULL_ACCS 7 + +uint32_t mMaxBus; +uint32_t mTsegBase; +uint32_t mTsegSize; +uint16_t mPmBase; + +typedef union { + uint64_t uint64; + msr_t msr; +} msr64_t; + +//uint64_t PciRead64 (UINTN Address); +void ResourceInit(void); +void FixupPciexResource(void); +void AddSimpleResources(void); +void AddMsrResources(void); + +// +// Fixed memory ranges +// + +// +// TSEG memory! +// +STM_RSC_MEM_DESC RscTsegMemory = { + {MEM_RANGE, sizeof (STM_RSC_MEM_DESC)}, + 0, + 0, + FULL_ACCS +}; +// +// Flash part +// +STM_RSC_MEM_DESC RscSpiMemory = { + {MEM_RANGE, sizeof (STM_RSC_MEM_DESC)}, + 0xFE000000, + 0x01000000, + FULL_ACCS +}; +// +// ACPI +// +STM_RSC_IO_DESC RscPmIo = { + {IO_RANGE, sizeof (STM_RSC_IO_DESC)}, + 0, + 128 +}; + +// +// PCIE MMIO +// +STM_RSC_MMIO_DESC RscPcieMmio = { + {MMIO_RANGE, sizeof (STM_RSC_MMIO_DESC)}, + 0, + 0, // Length + RDWR_ACCS +}; +// +// Local APIC +// +STM_RSC_MMIO_DESC RscApicMmio = { + {MMIO_RANGE, sizeof (STM_RSC_MMIO_DESC)}, + 0, + 0x400, + RDWR_ACCS +}; +// +// Software SMI +// +STM_RSC_TRAPPED_IO_DESC RscSwSmiTrapIo = { + {TRAPPED_IO_RANGE, sizeof (STM_RSC_TRAPPED_IO_DESC)}, + 0xB2, + 2 +}; +// +// End of list +// +STM_RSC_END RscListEnd = { + {END_OF_RESOURCES, sizeof (STM_RSC_END)}, + 0 +}; + +// +// Common PCI devices +// +// +// LPC bridge +// +STM_RSC_PCI_CFG_DESC RscLpcBridgePci = { + {PCI_CFG_RANGE, sizeof (STM_RSC_PCI_CFG_DESC)}, + RDWR_ACCS, 0, + 0, + 0x1000, + 0, + 0, + { + {1, 1, sizeof(STM_PCI_DEVICE_PATH_NODE), LPC_FUNCTION, LPC_DEVICE}, + }, +}; + +// +// Template for MSR resources. +// +STM_RSC_MSR_DESC RscMsrTpl = { + {MACHINE_SPECIFIC_REG, sizeof (STM_RSC_MSR_DESC)}, +}; + +// +// MSR indices to register +// +typedef struct { + uint32_t MsrIndex; + uint64_t ReadMask; + uint64_t WriteMask; +} MSR_TABLE_ENTRY; + +MSR_TABLE_ENTRY MsrTable[] = { + // Index Read Write // MASK64 means need access, MASK0 means no need access. + {SMRR_PHYSBASE_MSR, MASK64, MASK0}, + {SMRR_PHYSMASK_MSR, MASK64, MASK0}, +}; + +/** + + BIOS resources initialization. + +**/ +void ResourceInit(void) +{ + mMaxBus = 255; + + msr_t MsrRead; + + mPmBase = get_pmbase(); + + //mTsegBase = (uint32_t)rdmsr(SMRR_PHYSBASE_MSR) & 0xFFFFF000; + + MsrRead = rdmsr(SMRR_PHYSBASE_MSR); + mTsegBase = MsrRead.lo & 0xFFFFF000; + + //mTsegSize = (uint32_t)(~((uint32_t)rdmsr(SMRR_PHYSMASK_MSR) & 0xFFFFF000) + 1); + + MsrRead = rdmsr(SMRR_PHYSMASK_MSR); + mTsegSize = (~(MsrRead.lo & 0xFFFFF000) + 1); +} + +/** + + Fix up PCIE resource. + +**/ +void FixupPciexResource(void) +{ + // bug, bug, need to fix for coreboot + // + // Find max bus number and PCIEX length + // + //RscPcieMmio.Length = 0x10000000; // 256 MB + //RscPcieMmio.Base = PcdGet64 (PcdPciExpressBaseAddress); +} + +/** + + Add basic resources to BIOS resource database. + +**/ +void +AddSimpleResources(void) +{ + int Status; + msr64_t ReadMsr; + + // + // Fix-up values + // + RscTsegMemory.Base = mTsegBase; + RscTsegMemory.Length = mTsegSize; + + RscPmIo.Base = (uint16_t) mPmBase; + + // + // Local APIC. We assume that all thteads are programmed identically + // despite that it is possible to have individual APIC address for + // each of the threads. If this is the case this programming should + // be corrected. + // + //RscApicMmio.Base = AsmReadMsr64 (IA32_APIC_BASE_MSR_INDEX) & 0xFFFFFF000ull; + + ReadMsr.msr = rdmsr(IA32_APIC_BASE_MSR_INDEX); + RscApicMmio.Base = ReadMsr.uint64 & 0xFFFFFF000ull; + + // + // PCIEX BAR + // + FixupPciexResource (); + + Status = AddPiResource((void *) &RscTsegMemory, 0); + //ASSERT_EFI_ERROR (Status); + Status = AddPiResource((void *) &RscLpcBridgePci, 1); + //ASSERT_EFI_ERROR (Status); +} + +/** + + Add MSR resources to BIOS resource database. + +**/ +void AddMsrResources(void) +{ + uint32_t Status; + uint32_t Index; + + for (Index = 0; Index < sizeof(MsrTable)/sizeof(MsrTable[0]); Index ++) { + + RscMsrTpl.MsrIndex = (uint32_t) MsrTable[Index].MsrIndex; + RscMsrTpl.ReadMask = (uint64_t) MsrTable[Index].ReadMask; + RscMsrTpl.WriteMask = (uint64_t) MsrTable[Index].WriteMask; + + Status = AddPiResource ((void *) &RscMsrTpl, 1); + } +} + +/** + + Add resources to BIOS resource database. + +**/ +void AddResourcesCmd(void) +{ + ResourceInit(); + + AddSimpleResources(); + + AddMsrResources(); +} diff --git a/src/security/intel/stm/StmPlatformResource.h b/src/security/intel/stm/StmPlatformResource.h new file mode 100644 index 0000000..e31e74b --- /dev/null +++ b/src/security/intel/stm/StmPlatformResource.h @@ -0,0 +1,43 @@ +/** @file + STM platform SMM resource + + Copyright (c) 2015, Intel Corporation. All rights reserved. + This program and the accompanying materials are licensed and made available + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _STM_PLATFORM_RESOURCE_H_ +#define _STM_PLATFORM_RESOURCE_H_ + +#define MASK0 0 +#define MASK64 0xFFFFFFFFFFFFFFFFull + +// +// LPC +// +#define LPC_BUS 0 +#define LPC_DEVICE 31 +#define LPC_FUNCTION 0 +#define R_ACPI_PM_BASE 0x40 +#define ACPI_PM_BASE_MASK 0xFFF8 + +// +// MSRs +// +#define IA32_APIC_BASE_MSR_INDEX 0x1B +#define SMRR_PHYSBASE_MSR 0x1F2 +#define SMRR_PHYSMASK_MSR 0x1F3 + +/** + + Add resources to BIOS resource database. + +**/ +void AddResourcesCmd(void); +#endif diff --git a/src/security/intel/stm/StmPlatformSmm.c b/src/security/intel/stm/StmPlatformSmm.c new file mode 100644 index 0000000..bd9cea5 --- /dev/null +++ b/src/security/intel/stm/StmPlatformSmm.c @@ -0,0 +1,128 @@ +/** @file + STM platform SMM API + + Copyright (c) 2015, Intel Corporation. All rights reserved. + This program and the accompanying materials are licensed and made + available under the terms and conditions of the BSD License which + accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <security/intel/stm/StmApi.h> +#include <security/intel/stm/SmmStm.h> +#include <cpu/x86/smm.h> + +#include <stddef.h> +#include <cbfs.h> +#include <console/console.h> +#include <lib.h> +#include <stdint.h> + +int LoadStmImage(uint32_t mseg); + +extern bool StmCheckStmImage(void *StmImage, uint32_t StmImageSize); +extern void StmGen4GPageTableIa32(uint32_t PageTableBase); +extern void StmGen4GPageTableX64(uint32_t PageTableBase); + +/** + Load STM image. + + @retval EFI_SUCCESS STM is loaded to MSEG + @retval EFI_BUFFER_TOO_SMALL MSEG is too small + @retval EFI_UNSUPPORTED MSEG is not enabled +**/ +int LoadStmImage(uint32_t mseg) +{ + int Status; + void *MsegBase; + uint32_t StmBufferSize; + uint32_t StmImageSize; + bool StmStatus; + + STM_HEADER *StmHeader; + + // + // Extract STM image from FV + // + MsegBase = (void *) mseg; + StmBufferSize = CONFIG_MSEG_SIZE; + StmImageSize = 0; + + memset((void *) MsegBase, 0, CONFIG_MSEG_SIZE); // clear the mseg + + StmImageSize = cbfs_boot_load_file("stm.bin", MsegBase, StmBufferSize, CBFS_TYPE_RAW); + printk(BIOS_DEBUG, "STM loaded into mseg: 0x%08x size: %u \n", (uint32_t) MsegBase, StmImageSize); /* status is number of bytes loaded */ + + StmStatus = StmCheckStmImage(MsegBase, StmImageSize); + + StmHeader = MsegBase; + + StmGen4GPageTableX64 ((uint32_t)MsegBase + StmHeader->HwStmHdr.Cr3Offset); + + // Debug stuff + + printk(BIOS_DEBUG, "STM Header - Revision: 0x%08x Features: 0x%08x ... Cr3Offset: 0x%08x\n", + StmHeader->HwStmHdr.StmHeaderRevision, + StmHeader->HwStmHdr.MonitorFeatures, + StmHeader->HwStmHdr.Cr3Offset); + printk(BIOS_DEBUG, "STM Header - StaticImageSize: %d Cr3Location: 0x%08x \n", + StmHeader->SwStmHdr.StaticImageSize, + ((uint32_t) MsegBase + StmHeader->HwStmHdr.Cr3Offset)); + + Status = 0; // always return good for now + + return Status; +} + +struct descriptor +{ + uint16_t limit; + uintptr_t base; +} __attribute__((packed)); + + +void ReadGdtr( struct descriptor *gdtr); + +void ReadGdtr( struct descriptor *gdtr) +{ + __asm__ __volatile__ ( + "sgdt %0" + : "=m" (*gdtr) + ); +} + +void SetupSmmDescriptor(void *smbase, int32_t state_size, int32_t apic_id, int32_t entry32_off) +{ + struct descriptor Gdtr; + + TXT_PROCESSOR_SMM_DESCRIPTOR * Psd; + + Psd = smbase + SMM_PSD_OFFSET - (apic_id * state_size); + + printk(BIOS_DEBUG, "Setting up Smm Descriptor - Smbase: %p Psd: %p\n", smbase, Psd); + + memset(Psd, 0, sizeof(TXT_PROCESSOR_SMM_DESCRIPTOR)); + + memcpy(&Psd->Signature, TXT_PROCESSOR_SMM_DESCRIPTOR_SIGNATURE, 8); + Psd->SmmDescriptorVerMajor = TXT_PROCESSOR_SMM_DESCRIPTOR_VERSION_MAJOR; + Psd->SmmDescriptorVerMinor = TXT_PROCESSOR_SMM_DESCRIPTOR_VERSION_MINOR; + Psd->SmmSmiHandlerRip = (uint64_t)((uint32_t)smbase + SMM_ENTRY_OFFSET + entry32_off); + Psd->LocalApicId = apic_id; + Psd->Size = sizeof(TXT_PROCESSOR_SMM_DESCRIPTOR); + Psd->AcpiRsdp = 0; + Psd->BiosHwResourceRequirementsPtr = (uint64_t)((uint32_t)GetStmResource()); + Psd->SmmCs = 0x8; + Psd->SmmDs = 0x10; + Psd->SmmSs = 0x10; + Psd->SmmOtherSegment = 0x10; + Psd->SmmTr = 0x18; + + ReadGdtr(&Gdtr); + + Psd->SmmGdtPtr = Gdtr.base; + Psd->SmmGdtSize = Gdtr.limit + 1; // the stm will subtract, so need to compensate +} -- To view, visit https://review.coreboot.org/c/coreboot/+/33234 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4adcd92c341162630ce1ec357ffcf8a135785ec Gerrit-Change-Number: 33234 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1002358 Gerrit-MessageType: newchange

8 hours, 21 minutes

7
90
0 0

Change in coreboot[master]: 4.12 release notes: Add some explanation behind depreciations

by Arthur Heymans (Code Review)

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37064 ) Change subject: 4.12 release notes: Add some explanation behind depreciations ...................................................................... 4.12 release notes: Add some explanation behind depreciations Some features are made mandatory, meaning that some platforms have been dropped from master. This also explains that further development on these popular platforms can happen on the 4.11 branch. TODO is this really the right place or is it too technical for release notes? Change-Id: I95e01c301e7db6f81ef88a89d709ebab35c9ccfb Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M Documentation/releases/coreboot-4.12-relnotes.md 1 file changed, 61 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/37064/1 diff --git a/Documentation/releases/coreboot-4.12-relnotes.md b/Documentation/releases/coreboot-4.12-relnotes.md index f9c5f7e..67bef34 100644 --- a/Documentation/releases/coreboot-4.12-relnotes.md +++ b/Documentation/releases/coreboot-4.12-relnotes.md @@ -10,6 +10,67 @@ * The chip and board additions and removals will be updated right before the release, so those do not need to be added. +Deprecations +------------ + +For the 4.12 release a few features on x86 became mandatory. These are +relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK. + +### Relocatable ramstage + +Relocatable stages are a feature only implemented only on x86, where +stages can be relocated at runtime. This is used to place ramstage in +a better location that does not collide with memory the OS tends to +use. The rationale behind making this mandatory is that you always +want cbmem to be cached so it's a good location to run ramstage from. +It avoids using lower memory altogether so the OS can make use +of it and no backing up needs to happen on S3 resume. + +### Postcar stage + +With Postcar stage tearing down Cache-as-Ram is done in a separate +stage. This means that romstage has a clean program boundary and +that all variables in romstage can be accessed via their initial +reference at all times. There is no need to link global and static +variables via the CAR\_GLOBAL macro and no need to access them with +car\_set/get\_var/ptr functions. + +### C\_ENVIRONMENT\_BOOTBLOCK + +Historically the bootblock on x86 platforms has been compiled with +romcc. This means that the generated code only uses CPU registers +and therefore no stack. This 20K+ LOC compiler is limited and hard +to maintain. A different solution is to set up Cache-as-Ram in the +bootblock and run GCC compiled code in the bootblock. The advantages +are increased flexibility: e.g. printing to console is possible and +VBOOT can run before romstage, making romstage updatable via RW FMAP +regions. + +### Platforms dropped from master + +The following platforms did not implement those feature are dropped +from master to allow the master branch to move on: +- AMDFAM10 +- all FSP1.0 platforms: BROADWELL_DE, FSP_BAYTRAIL, RANGELEY +- VIA VX900 +- TODO (AMD?) + +In particular on FSP1.0 it is impossible to implement POSTCAR stage. +The reason is that FSP1.0 relocates the CAR region to the HOB before +returning to coreboot. This means that after FSP returns to coreboot +accessing variables via their original address is not possible. One +way of obtaining that behavior would be to set up Cache-as-Ram again +(but with open source code) and copy the relocated data from the HOB +there. This solution is deemed too hacky. Maybe a lesson can be +learned from this: blobs should not interfere with the execution +environment, as this makes proper integration much harder. + +### 4.11_branch + +Given that some platforms supported by FSP1.0 are being produced and +popular, the 4.11 release was made into a branch in which further +development can happen. + Significant changes ------------------- -- To view, visit https://review.coreboot.org/c/coreboot/+/37064 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I95e01c301e7db6f81ef88a89d709ebab35c9ccfb Gerrit-Change-Number: 37064 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

1 day, 3 hours

6
17
0 0

Change in ...coreboot[master]: Kconfig: Display a warning if the board is updated incorrectly

by Martin Roth (Code Review)

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33641 Change subject: Kconfig: Display a warning if the board is updated incorrectly ...................................................................... Kconfig: Display a warning if the board is updated incorrectly Even though we have a comment to run make distclean before switching mainboards, people still ignore this and end up with confusing results. To try to fix this, save the mainboard directory in a Kconfig symbol that will not get updated when the mainboard gets changed. This allows us to compare it to the actual mainboard directory which will be updated when the platform changes and put up an obnoxious warning in the mainboard directory. Add another warning in the main menu, because the initial warning is probably going to be ignored. The main menu points to some documentation on how to fix the problem. Note that this will only catch issues going forward, and won't catch any already saved config that has a problem. Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: I2a1ccb62c7678f264015c87b9004be6a106f804a --- A Documentation/getting_started/fix_dot_config.md M src/Kconfig M src/mainboard/Kconfig 3 files changed, 78 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/33641/1 diff --git a/Documentation/getting_started/fix_dot_config.md b/Documentation/getting_started/fix_dot_config.md new file mode 100644 index 0000000..17d89d0 --- /dev/null +++ b/Documentation/getting_started/fix_dot_config.md @@ -0,0 +1,50 @@ +# How to repair your .config file + +## Overview +Many people rely on a saved .config file for building their +platform. This is reasonable, but can create unanticipated +problems. + +## TLDR +* Backup your .config: "cp .config .config_bak" +* Create the defconfig file: "make savedefconfig" +* Edit defconfig & delete unknown config lines: "vi defconfig" +* To just get rid of the warning about a bad .config, remove +* the CONFIG_MAINBOARD_CHECK line. +* The SMBIOS lines are probably incorrect as well. The ROM size +* is very suspect. Check the correct default for your platform. +* Save the defconfig +* Generate a new full config: +* "make -B defconfig KBUILD_DEFCONFIG=defconfig" + +## defconfig or "Mini config" +Instead of saving a "full" config, people should use a defconfig. +This is just the changes from a default coreboot configuration +file. It's significantly smaller, and when a new configuration option +gets added, it just takes the default value for that option when +expanded into a full .config. + +### Generating the defconfig file +To create the defconfig file, run "make savedefconfig". By default +this will generate the file in the root coreboot directory and call +it "defconfig". If there was already a file named "defconfig", this +will overwrite that file. + +### Contents of the defconfig file +As the defconfig file contains just the differences between the +platform and the default choices for the platform. For the current +default platform, the defconfig can actually be an empty file. + +Typically the defconfig will contain at least 2 lines - a +CONFIG_VENDOR_ line and a CONFIG_BOARD_ line. Again though, if you +are building the default board for any particular vendor, that line +may not be present. + +All additional lines in a defconfig file are options that the user +has specifically chosen to update in their config. + +### Generating a .config from a defconfig +To expand the defconfig so that can be used, run: + DFILE=defconfig; make -B defconfig KBUILD_DEFCONFIG=$DFILE + +You can point DFILE to any saved defconfig. diff --git a/src/Kconfig b/src/Kconfig index 72d826f..8eae329 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -16,6 +16,15 @@ mainmenu "coreboot configuration" +if MAINBOARD_CHECK != MAINBOARD_DIR +comment "***********************************************************************" +comment "WARNING: Your config is using defaults from a different mainboard " +comment "than you currently have set. We'd recommend that you delete your " +comment ".config file and start over, but if you want to try to repair the " +comment "file, see Documentation/getting_started/fix_dot_config.md " +comment "***********************************************************************" +endif + menu "General setup" config COREBOOT_BUILD @@ -1062,6 +1071,14 @@ mainboard code supports this. On supported Intel platforms this works by changing the settings in the descriptor.bin file. +config MAINBOARD_CHECK + string "Mainboard dir - Do not change manually" + default MAINBOARD_DIR + help + Check the platform. If this symbol doesn't match the currently + selected mainboard directory, give the user warnings that they're + probably doing something wrong. + endmenu diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index c88d317..d9216a9 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -1,5 +1,16 @@ comment "Important: Run 'make distclean' before switching boards" +if MAINBOARD_CHECK != MAINBOARD_DIR +comment "***********************************************************************" +comment "WARNING: Your config is using defaults from a different mainboard " +comment "than you currently have set. We'd recommend that you delete your " +comment ".config file and start over. " +comment "* *" +comment "If you ignore this warning and build anyway, you will almost certainly " +comment "get a bad rom with undefined results. " +comment "***********************************************************************" +endif + choice prompt "Mainboard vendor" default VENDOR_EMULATION -- To view, visit https://review.coreboot.org/c/coreboot/+/33641 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a1ccb62c7678f264015c87b9004be6a106f804a Gerrit-Change-Number: 33641 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

1 day, 7 hours

4
7
0 0

Change in ...coreboot[master]: Console: Allow console UART to be enabled without serial console

by Martin Roth (Code Review)

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33380 Change subject: Console: Allow console UART to be enabled without serial console ...................................................................... Console: Allow console UART to be enabled without serial console Currently, when we disable serial console, the serial console uart remains uninitialized. This patch allows coreboot to still set up the UART, even if we're not sending the console to it. BUG=b:74392237 TEST=Verify UART still works, even with coreboot console disabled Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: Ic0942634ab8a9fcafdc1ea099721c127202e9f9a --- M src/console/Kconfig M src/drivers/uart/Kconfig M src/include/console/uart.h 3 files changed, 28 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/33380/1 diff --git a/src/console/Kconfig b/src/console/Kconfig index 61ba667..da769d3 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -33,6 +33,7 @@ bool "Serial port console output" default y depends on DRIVERS_UART + select ENABLE_UART help Send coreboot debug output to a serial port. @@ -47,7 +48,7 @@ specific UART has to be used (e.g. when the platform code performs dangerous configurations). -if CONSOLE_SERIAL +if ENABLE_UART comment "I/O mapped, 8250-compatible" depends on DRIVERS_UART_8250IO @@ -79,13 +80,13 @@ Map the COM port number to the respective I/O port. comment "Serial port base address = 0x3f8" -depends on UART_FOR_CONSOLE = 0 +depends on UART_FOR_CONSOLE = 0 && DRIVERS_UART_8250IO comment "Serial port base address = 0x2f8" -depends on UART_FOR_CONSOLE = 1 +depends on UART_FOR_CONSOLE = 1 && DRIVERS_UART_8250IO comment "Serial port base address = 0x3e8" -depends on UART_FOR_CONSOLE = 2 +depends on UART_FOR_CONSOLE = 2 && DRIVERS_UART_8250IO comment "Serial port base address = 0x2e8" -depends on UART_FOR_CONSOLE = 3 +depends on UART_FOR_CONSOLE = 3 && DRIVERS_UART_8250IO config UART_OVERRIDE_BAUDRATE boolean @@ -156,7 +157,7 @@ default 3 depends on DRIVERS_UART_8250IO || DRIVERS_UART_8250MEM -endif # CONSOLE_SERIAL +endif # ENABLE_UART config SPKMODEM bool "spkmodem (console on speaker) console output" diff --git a/src/drivers/uart/Kconfig b/src/drivers/uart/Kconfig index 1f23a19..9b242fd 100644 --- a/src/drivers/uart/Kconfig +++ b/src/drivers/uart/Kconfig @@ -1,6 +1,21 @@ config DRIVERS_UART bool +config ENABLE_UART + def_bool n + +config ENABLE_UART_WITHOUT_CONSOLE + bool "Always configure primary UART" + depends on DRIVERS_UART + select ENABLE_UART + help + The primary UART has previously only been set up when the serial console + is enabled. + Selecting this choice will configure the console UART even if the serial + console is disabled. + + Select the UART in the console menu + config DRIVERS_UART_8250IO # FIXME: Shouldn't have a prompt, should default to n, and # should be selected by boards that have it instead. diff --git a/src/include/console/uart.h b/src/include/console/uart.h index aed67c2..6bd88ae 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -67,11 +67,16 @@ (ENV_BOOTBLOCK || ENV_ROMSTAGE || ENV_RAMSTAGE || ENV_VERSTAGE || \ ENV_POSTCAR || (ENV_SMM && CONFIG(DEBUG_SMI)))) -#if __CONSOLE_SERIAL_ENABLE__ +#if CONFIG(ENABLE_UART) static inline void __uart_init(void) { uart_init(CONFIG_UART_FOR_CONSOLE); } +#else +static inline void __uart_init(void) {} +#endif + +#if __CONSOLE_SERIAL_ENABLE__ static inline void __uart_tx_byte(u8 data) { uart_tx_byte(CONFIG_UART_FOR_CONSOLE, data); @@ -81,7 +86,6 @@ uart_tx_flush(CONFIG_UART_FOR_CONSOLE); } #else -static inline void __uart_init(void) {} static inline void __uart_tx_byte(u8 data) {} static inline void __uart_tx_flush(void) {} #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/33380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0942634ab8a9fcafdc1ea099721c127202e9f9a Gerrit-Change-Number: 33380 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

1 day, 7 hours

4
14
0 0

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2019