Change in ...coreboot[master]: autoport: Add support for Haswell-LynxPoint platform
by Iru Cai (vimacs) (Code Review)
Hello Iru Cai,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/30890
to review the following change.
Change subject: autoport: Add support for Haswell-LynxPoint platform
......................................................................
autoport: Add support for Haswell-LynxPoint platform
It can now generate a buildable source for Clevo W650SZ.
TODO:
- Support Lynx Point LP (GPIO registers differ from non-LP)
- Use PCH HD-Audio in azilia instead of the CPU/Northbridge HD-Audio
Change-Id: I4f6e8c97b5122101de2f36bba8ba9f8ddd5b813a
Signed-off-by: Iru Cai <mytbk920423(a)gmail.com>
---
M util/autoport/azalia.go
A util/autoport/haswell.go
A util/autoport/lynxpoint.go
M util/autoport/main.go
4 files changed, 625 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/30890/1
diff --git a/util/autoport/azalia.go b/util/autoport/azalia.go
index c525189..3090dd0 100644
--- a/util/autoport/azalia.go
+++ b/util/autoport/azalia.go
@@ -62,4 +62,9 @@
RegisterPCI(0x8086, 0x1c20, azalia{})
/* C216/ivybridge */
RegisterPCI(0x8086, 0x1e20, azalia{})
+ /* Haswell */
+ RegisterPCI(0x8086, 0x0c0c, azalia{})
+ /* Lynx Point */
+ RegisterPCI(0x8086, 0x8c20, azalia{})
+ RegisterPCI(0x8086, 0x9c20, azalia{})
}
diff --git a/util/autoport/haswell.go b/util/autoport/haswell.go
new file mode 100644
index 0000000..d3c9d9f
--- /dev/null
+++ b/util/autoport/haswell.go
@@ -0,0 +1,119 @@
+package main
+
+type haswellmc struct {
+ variant string
+}
+
+func (i haswellmc) Scan(ctx Context, addr PCIDevData) {
+ inteltool := ctx.InfoSource.GetInteltool()
+
+ /* FIXME:XX Move this somewhere else. */
+ MainboardIncludes = append(MainboardIncludes, "drivers/intel/gma/int15.h")
+ MainboardEnable += (` /* FIXME: fix those values*/
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+`)
+
+ DevTree = DevTreeNode{
+ Chip: "northbridge/intel/haswell",
+ MissingParent: "northbridge",
+ Comment: "FIXME: check gfx.ndid and gfx.did",
+ Registers: map[string]string{
+ "gpu_dp_b_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 2) & 7),
+ "gpu_dp_c_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 10) & 7),
+ "gpu_dp_d_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 18) & 7),
+ "gpu_panel_port_select": FormatInt32((inteltool.IGD[0xc7208] >> 30) & 3),
+ "gpu_panel_power_up_delay": FormatInt32((inteltool.IGD[0xc7208] >> 16) & 0x1fff),
+ "gpu_panel_power_backlight_on_delay": FormatInt32(inteltool.IGD[0xc7208] & 0x1fff),
+ "gpu_panel_power_down_delay": FormatInt32((inteltool.IGD[0xc720c] >> 16) & 0x1fff),
+ "gpu_panel_power_backlight_off_delay": FormatInt32(inteltool.IGD[0xc720c] & 0x1fff),
+ "gpu_panel_power_cycle_delay": FormatInt32(inteltool.IGD[0xc7210] & 0xff),
+ "gpu_cpu_backlight": FormatHex32(inteltool.IGD[0x48254]),
+ "gpu_pch_backlight": FormatHex32((inteltool.IGD[0xc8254] >> 16) * 0x10001),
+ "gpu_ddi_e_connected": FormatBool(((inteltool.IGD[0x64000] >> 4) & 1) == 0),
+ /* FIXME:XX hardcoded. */
+ "gfx.ndid": "3",
+ "gfx.did": "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }",
+ },
+ Children: []DevTreeNode{
+ {
+ Chip: "cpu_cluster",
+ Dev: 0,
+ Children: []DevTreeNode{
+ {
+ Chip: "cpu/intel/haswell",
+ Children: []DevTreeNode{
+ {
+ Chip: "lapic",
+ Dev: 0,
+ },
+ {
+ Chip: "lapic",
+ Dev: 0xacac,
+ Disabled: true,
+ },
+ },
+ Registers: map[string]string{
+ /* FIXME:XX hardcoded. */
+ "c1_acpower": "1",
+ "c2_acpower": "3",
+ "c3_acpower": "5",
+ "c1_battery": "1",
+ "c2_battery": "3",
+ "c3_battery": "5",
+ },
+ },
+ },
+ },
+
+ {
+ Chip: "domain",
+ Dev: 0,
+ PCIController: true,
+ ChildPCIBus: 0,
+ PCISlots: []PCISlot{
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x0, Func: 0}, writeEmpty: true, additionalComment: "Host bridge"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1, Func: 0}, writeEmpty: true, additionalComment: "PCIe Bridge for discrete graphics"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x2, Func: 0}, writeEmpty: true, additionalComment: "Internal graphics"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x3, Func: 0}, writeEmpty: true, additionalComment: "Mini-HD audio"},
+ },
+ },
+ },
+ }
+
+ PutPCIDev(addr, "Host bridge")
+
+ /* FIXME:XX some configs are unsupported. */
+
+ KconfigBool["CPU_INTEL_HASWELL"] = true
+ KconfigBool["NORTHBRIDGE_INTEL_HASWELL"] = true
+ KconfigBool["INTEL_INT15"] = true
+ KconfigBool["HAVE_ACPI_TABLES"] = true
+ KconfigBool["HAVE_ACPI_RESUME"] = true
+
+ KconfigInt["MAX_CPUS"] = 8
+
+ DSDTIncludes = append(DSDTIncludes, DSDTInclude{
+ File: "cpu/intel/common/acpi/cpu.asl",
+ })
+
+ DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{
+ File: "northbridge/intel/haswell/acpi/haswell.asl",
+ }, DSDTInclude{
+ File: "drivers/intel/gma/acpi/default_brightness_levels.asl",
+ })
+}
+
+func init() {
+ RegisterPCI(0x8086, 0x0c00, haswellmc{variant: "Desktop"})
+ RegisterPCI(0x8086, 0x0c04, haswellmc{variant: "Mobile"})
+ RegisterPCI(0x8086, 0x0a04, haswellmc{variant: "ULT"})
+ RegisterPCI(0x8086, 0x0c08, haswellmc{variant: "Server"})
+ for _, id := range []uint16{
+ 0x0402, 0x0412, 0x0422,
+ 0x0406, 0x0416, 0x0426,
+ 0x0d16, 0x0d26, 0x0d36,
+ 0x0a06, 0x0a16, 0x0a26,
+ } {
+ RegisterPCI(0x8086, id, GenericVGA{GenericPCI{Comment: "VGA controller"}})
+ }
+}
diff --git a/util/autoport/lynxpoint.go b/util/autoport/lynxpoint.go
new file mode 100644
index 0000000..df20c3f
--- /dev/null
+++ b/util/autoport/lynxpoint.go
@@ -0,0 +1,495 @@
+package main
+
+import (
+ "fmt"
+ "os"
+)
+
+type lynxpoint struct {
+ variant string
+ node *DevTreeNode
+}
+
+func (b lynxpoint) writeGPIOSet(ctx Context, sb *os.File,
+ val uint32, set uint, partno int, constraint uint32) {
+
+ max := uint(32)
+ if set == 3 {
+ max = 12
+ }
+
+ bits := [6][2]string{
+ {"GPIO_MODE_NATIVE", "GPIO_MODE_GPIO"},
+ {"GPIO_DIR_OUTPUT", "GPIO_DIR_INPUT"},
+ {"GPIO_LEVEL_LOW", "GPIO_LEVEL_HIGH"},
+ {"GPIO_RESET_PWROK", "GPIO_RESET_RSMRST"},
+ {"GPIO_NO_INVERT", "GPIO_INVERT"},
+ {"GPIO_NO_BLINK", "GPIO_BLINK"},
+ }
+
+ for i := uint(0); i < max; i++ {
+ if ((constraint>>i)&1 == 1) {
+ fmt.Fprintf(sb, " .gpio%d = %s,\n",
+ (set-1)*32+i,
+ bits[partno][(val>>i)&1])
+ }
+ }
+}
+
+func (b lynxpoint) GPIO(ctx Context, inteltool InteltoolData) {
+ var constraint uint32
+ gpio := Create(ctx, "gpio.c")
+ defer gpio.Close()
+
+ AddROMStageFile("gpio.c", "")
+
+ Add_gpl(gpio)
+ gpio.WriteString("#include <southbridge/intel/common/gpio.h>\n\n")
+
+ /* TODO: different in LP PCH */
+ addresses := [3][6]int{
+ {0x00, 0x04, 0x0c, 0x60, 0x2c, 0x18},
+ {0x30, 0x34, 0x38, 0x64, -1, -1},
+ {0x40, 0x44, 0x48, 0x68, -1, -1},
+ }
+
+ for set := 1; set <= 3; set++ {
+ for partno, part := range []string{"mode", "direction", "level", "reset", "invert", "blink"} {
+ addr := addresses[set-1][partno]
+ if addr < 0 {
+ continue
+ }
+ fmt.Fprintf(gpio, "static const struct pch_gpio_set%d pch_gpio_set%d_%s = {\n",
+ set, set, part)
+
+ constraint = 0xffffffff
+ switch part {
+ case "direction":
+ /* Ignored on native mode */
+ constraint = inteltool.GPIO[uint16(addresses[set-1][0])]
+ case "level":
+ /* Level doesn't matter for input */
+ constraint = inteltool.GPIO[uint16(addresses[set-1][0])]
+ constraint &^= inteltool.GPIO[uint16(addresses[set-1][1])]
+ case "reset":
+ /* Only show reset */
+ constraint = inteltool.GPIO[uint16(addresses[set-1][3])]
+ case "invert":
+ /* Only on input and only show inverted GPIO */
+ constraint = inteltool.GPIO[uint16(addresses[set-1][0])]
+ constraint &= inteltool.GPIO[uint16(addresses[set-1][1])]
+ constraint &= inteltool.GPIO[uint16(addresses[set-1][4])]
+ case "blink":
+ /* Only on output and only show blinking GPIO */
+ constraint = inteltool.GPIO[uint16(addresses[set-1][0])]
+ constraint &^= inteltool.GPIO[uint16(addresses[set-1][1])]
+ constraint &= inteltool.GPIO[uint16(addresses[set-1][5])]
+ }
+ b.writeGPIOSet(ctx, gpio, inteltool.GPIO[uint16(addr)], uint(set), partno, constraint)
+ gpio.WriteString("};\n\n")
+ }
+ }
+
+ gpio.WriteString(`const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
+`)
+}
+
+func (b lynxpoint) IsPCIeHotplug(ctx Context, port int) bool {
+ portDev, ok := PCIMap[PCIAddr{Bus: 0, Dev: 0x1c, Func: port}]
+ if !ok {
+ return false
+ }
+ return (portDev.ConfigDump[0xdb] & (1 << 6)) != 0
+}
+
+func (b lynxpoint) GetGPIOHeader() string {
+ return "southbridge/intel/lynxpoint/pch.h"
+}
+
+func (b lynxpoint) EnableGPE(in int) {
+ b.node.Registers[fmt.Sprintf("gpi%d_routing", in)] = "2"
+}
+
+func (b lynxpoint) EncodeGPE(in int) int {
+ return in + 0x10
+}
+
+func (b lynxpoint) DecodeGPE(in int) int {
+ return in - 0x10
+}
+
+func (b lynxpoint) NeedRouteGPIOManually() {
+ b.node.Comment += ", FIXME: set gpiX_routing for EC support"
+}
+
+func (b lynxpoint) Scan(ctx Context, addr PCIDevData) {
+
+ SouthBridge = &b
+
+ inteltool := ctx.InfoSource.GetInteltool()
+ b.GPIO(ctx, inteltool)
+
+ KconfigBool["SOUTHBRIDGE_INTEL_LYNXPOINT"] = true
+ if b.variant == "Lynx Point LP" {
+ KconfigBool["INTEL_LYNXPOINT_LP"] = true
+ }
+ KconfigBool["SERIRQ_CONTINUOUS_MODE"] = true
+ KconfigInt["USBDEBUG_HCD_INDEX"] = 2
+ KconfigComment["USBDEBUG_HCD_INDEX"] = "FIXME: check this"
+ dmi := ctx.InfoSource.GetDMI()
+ if dmi.Vendor == "LENOVO" {
+ KconfigInt["DRAM_RESET_GATE_GPIO"] = 10
+ } else {
+ KconfigInt["DRAM_RESET_GATE_GPIO"] = 60
+ }
+ KconfigComment["DRAM_RESET_GATE_GPIO"] = "FIXME: check this"
+
+ /* Not strictly speaking correct. These subsys/subvendor referer to PCI devices.
+ But most systems don't have any of those. But the config needs to be set
+ nevertheless. So set it to southbridge subsys/subvendor. */
+ KconfigHex["MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID"] = uint32(GetLE16(addr.ConfigDump[0x2c:0x2e]))
+ KconfigHex["MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID"] = uint32(GetLE16(addr.ConfigDump[0x2e:0x30]))
+
+ ich9GetFlashSize(ctx)
+
+ DSDTDefines = append(DSDTDefines,
+ DSDTDefine{
+ Key: "BRIGHTNESS_UP",
+ Value: "\\_SB.PCI0.GFX0.INCB",
+ },
+ DSDTDefine{
+ Key: "BRIGHTNESS_DOWN",
+ Value: "\\_SB.PCI0.GFX0.DECB",
+ },
+ DSDTDefine{
+ Key: "ACPI_VIDEO_DEVICE",
+ Value: "\\_SB.PCI0.GFX0",
+ })
+
+ /* SPI init */
+ MainboardIncludes = append(MainboardIncludes, "southbridge/intel/lynxpoint/pch.h")
+
+ cur := DevTreeNode{
+ Chip: "southbridge/intel/lynxpoint",
+ Comment: "Intel Series 8 Lynx Point PCH",
+
+ Registers: map[string]string{
+ "pirqa_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x60]),
+ "pirqb_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x61]),
+ "pirqc_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x62]),
+ "pirqd_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x63]),
+ "pirqe_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x68]),
+ "pirqf_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x69]),
+ "pirqg_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x6a]),
+ "pirqh_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x6b]),
+ "sata_ahci": "1",
+ "gen1_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x84:0x88]),
+ "gen2_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x88:0x8c]),
+ "gen3_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x8c:0x90]),
+ "gen4_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x90:0x94]),
+ "sata_port_map": fmt.Sprintf("0x%x", PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 2}].ConfigDump[0x92]&0x3f),
+ },
+ PCISlots: []PCISlot{
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x14, Func: 0}, writeEmpty: false, additionalComment: "USB 3.0 Controller"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 0}, writeEmpty: true, additionalComment: "Management Engine Interface 1"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 1}, writeEmpty: true, additionalComment: "Management Engine Interface 2"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 2}, writeEmpty: true, additionalComment: "Management Engine IDE-R"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 3}, writeEmpty: true, additionalComment: "Management Engine KT"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x19, Func: 0}, writeEmpty: true, additionalComment: "Intel Gigabit Ethernet"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1a, Func: 0}, writeEmpty: true, additionalComment: "USB2 EHCI #2"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1b, Func: 0}, writeEmpty: true, additionalComment: "High Definition Audio"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 0}, writeEmpty: true, additionalComment: "PCIe Port #1"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 1}, writeEmpty: true, additionalComment: "PCIe Port #2"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 2}, writeEmpty: true, additionalComment: "PCIe Port #3"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 3}, writeEmpty: true, additionalComment: "PCIe Port #4"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 4}, writeEmpty: true, additionalComment: "PCIe Port #5"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 5}, writeEmpty: true, additionalComment: "PCIe Port #6"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 6}, writeEmpty: true, additionalComment: "PCIe Port #7"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 7}, writeEmpty: true, additionalComment: "PCIe Port #8"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1d, Func: 0}, writeEmpty: true, additionalComment: "USB2 EHCI #1"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1e, Func: 0}, writeEmpty: true, additionalComment: "PCI bridge"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 0}, writeEmpty: true, additionalComment: "LPC bridge"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 2}, writeEmpty: true, additionalComment: "SATA Controller 1"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 3}, writeEmpty: true, additionalComment: "SMBus"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 5}, writeEmpty: true, additionalComment: "SATA Controller 2"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 6}, writeEmpty: true, additionalComment: "Thermal"},
+ },
+ }
+
+ b.node = &cur
+
+ PutPCIChip(addr, cur)
+ PutPCIDevParent(addr, "PCI-LPC bridge", "lpc")
+
+ DSDTIncludes = append(DSDTIncludes, DSDTInclude{
+ File: "southbridge/intel/lynxpoint/acpi/platform.asl",
+ })
+ DSDTIncludes = append(DSDTIncludes, DSDTInclude{
+ File: "southbridge/intel/lynxpoint/acpi/globalnvs.asl",
+ Comment: "global NVS and variables",
+ })
+ DSDTIncludes = append(DSDTIncludes, DSDTInclude{
+ File: "southbridge/intel/lynxpoint/acpi/sleepstates.asl",
+ })
+ DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{
+ File: "southbridge/intel/lynxpoint/acpi/pch.asl",
+ })
+
+ sb := Create(ctx, "romstage.c")
+ defer sb.Close()
+ Add_gpl(sb)
+ sb.WriteString(`#include <stdint.h>
+#include <cpu/intel/romstage.h>
+#include <cpu/intel/haswell/haswell.h>
+#include <northbridge/intel/haswell/haswell.h>
+#include <northbridge/intel/haswell/pei_data.h>
+#include <southbridge/intel/common/gpio.h>
+#include <southbridge/intel/lynxpoint/pch.h>
+
+static const struct rcba_config_instruction rcba_config[] = {
+`)
+ RestoreDIRRoute(sb, "D31IR", uint16(inteltool.RCBA[0x3140]))
+ RestoreDIRRoute(sb, "D29IR", uint16(inteltool.RCBA[0x3144]))
+ RestoreDIRRoute(sb, "D28IR", uint16(inteltool.RCBA[0x3146]))
+ RestoreDIRRoute(sb, "D27IR", uint16(inteltool.RCBA[0x3148]))
+ RestoreDIRRoute(sb, "D26IR", uint16(inteltool.RCBA[0x314c]))
+ RestoreDIRRoute(sb, "D25IR", uint16(inteltool.RCBA[0x3150]))
+ RestoreDIRRoute(sb, "D22IR", uint16(inteltool.RCBA[0x315c]))
+ RestoreDIRRoute(sb, "D20IR", uint16(inteltool.RCBA[0x3160]))
+
+ sb.WriteString(`
+ RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS),
+
+ RCBA_END_CONFIG,
+};`)
+
+ sb.WriteString(`
+
+void mainboard_config_superio(void)
+{
+}
+
+void mainboard_romstage_entry(unsigned long bist)
+{
+ struct pei_data pei_data = {
+ .pei_version = PEI_VERSION,
+ .mchbar = (uintptr_t)DEFAULT_MCHBAR,
+ .dmibar = (uintptr_t)DEFAULT_DMIBAR,
+ .epbar = DEFAULT_EPBAR,
+ .pciexbar = DEFAULT_PCIEXBAR,
+ .smbusbar = SMBUS_IO_BASE,
+ .wdbbar = 0x4000000,
+ .wdbsize = 0x1000,
+ .hpet_address = HPET_ADDR,
+ .rcba = (uintptr_t)DEFAULT_RCBA,
+ .pmbase = DEFAULT_PMBASE,
+ .gpiobase = DEFAULT_GPIOBASE,
+ .temp_mmio_base = 0xfed08000,
+ .system_type = 1, /* desktop/server, FIXME: check this */
+ .tseg_size = CONFIG_SMM_TSEG_SIZE,
+ .spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 }, /* FIXME: check this */
+ .ec_present = 0,
+ .dimm_channel0_disabled = 0, /* FIXME: leave channel 0 enabled */
+ .dimm_channel1_disabled = 0, /* FIXME: leave channel 1 enabled */
+ .max_ddr3_freq = 1600,
+ .usb2_ports = {
+ /* Length, Enable, OCn#, Location */
+`)
+
+ pdo1 := PCIMap[PCIAddr{Bus: 0, Dev: 0x1d, Func: 0}].ConfigDump[0x64]
+ ocmap1 := PCIMap[PCIAddr{Bus: 0, Dev: 0x1d, Func: 0}].ConfigDump[0x74:0x78]
+ pdo2 := PCIMap[PCIAddr{Bus: 0, Dev: 0x1a, Func: 0}].ConfigDump[0x64]
+ ocmap2 := PCIMap[PCIAddr{Bus: 0, Dev: 0x1a, Func: 0}].ConfigDump[0x74:0x78]
+
+ for port := uint(0); port < 14; port++ {
+ var port_oc int = -1
+ var port_pos string
+ var port_disable uint8
+
+ if port < 8 {
+ port_disable = (pdo1 >> port) & 1
+ for oc := 0; oc < 4; oc++ {
+ if ((ocmap1[oc] & (1 << port)) != 0) {
+ port_oc = oc
+ break
+ }
+ }
+ } else {
+ port_disable = (pdo2 >> (port - 8)) & 1
+ for oc := 0; oc < 4; oc++ {
+ if ((ocmap2[oc] & (1 << (port - 8))) != 0) {
+ port_oc = oc + 4
+ break
+ }
+ }
+ }
+ if port_disable == 1 {
+ port_pos = "USB_PORT_SKIP"
+ } else {
+ port_pos = "USB_PORT_BACK_PANEL"
+ }
+ if port_oc == -1 {
+ fmt.Fprintf(sb, " { 0x0040, %d, USB_OC_PIN_SKIP, %s },\n",
+ (port_disable ^ 1), port_pos)
+ } else {
+ fmt.Fprintf(sb, " { 0x0040, %d, %d, %s },\n",
+ (port_disable ^ 1), port_oc, port_pos)
+ }
+ }
+
+ sb.WriteString(` },
+ .usb3_ports = {
+`)
+
+ xpdo := PCIMap[PCIAddr{Bus: 0, Dev: 0x14, Func: 0}].ConfigDump[0xe8]
+ u3ocm := PCIMap[PCIAddr{Bus: 0, Dev: 0x14, Func: 0}].ConfigDump[0xc8:0xd0]
+
+ for port := uint(0); port < 6; port++ {
+ var port_oc int = -1
+ port_disable := (xpdo >> port) & 1
+ for oc := 0; oc < 8; oc++ {
+ if (u3ocm[oc] & (1 << port)) != 0 {
+ port_oc = oc
+ break
+ }
+ }
+ if port_oc == -1 {
+ fmt.Fprintf(sb, " { %d, USB_OC_PIN_SKIP },\n",
+ (port_disable ^ 1))
+ } else {
+ fmt.Fprintf(sb, " { %d, %d },\n",
+ (port_disable ^ 1), port_oc)
+ }
+ }
+
+ sb.WriteString(` },
+ };
+
+ struct romstage_params romstage_params = {
+ .pei_data = &pei_data,
+ .gpio_map = &mainboard_gpio_map,
+ .rcba_config = &rcba_config[0],
+ .bist = bist,
+ };
+
+ romstage_common(&romstage_params);
+}`)
+
+ gnvs := Create(ctx, "acpi_tables.c")
+ defer gnvs.Close()
+
+ Add_gpl(gnvs)
+ gnvs.WriteString(`#include <southbridge/intel/lynxpoint/nvs.h>
+
+/* FIXME: check this function. */
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+ /* Disable USB ports in S3 by default */
+ gnvs->s3u0 = 0;
+ gnvs->s3u1 = 0;
+
+ /* Disable USB ports in S5 by default */
+ gnvs->s5u0 = 0;
+ gnvs->s5u1 = 0;
+
+ // the lid is open by default.
+ gnvs->lids = 1;
+
+ gnvs->tcrt = 100;
+ gnvs->tpsv = 90;
+}
+`)
+
+}
+
+func init() {
+ for _, id := range []uint16 {
+ 0x8c41, 0x8c49, 0x8c4b, 0x8c4f,
+ } {
+ RegisterPCI(0x8086, uint16(id), lynxpoint{variant: "Lynx Point Mobile"})
+ }
+
+ for _, id := range []uint16 {
+ 0x8c42, 0x8c44, 0x8c46, 0x8c4a,
+ 0x8c4c, 0x8c4e, 0x8c50, 0x8c5c,
+ } {
+ RegisterPCI(0x8086, uint16(id), lynxpoint{variant: "Lynx Point Desktop"})
+ }
+
+ for _, id := range []uint16 {
+ 0x8c52, 0x8c54, 0x8c56,
+ } {
+ RegisterPCI(0x8086, uint16(id), lynxpoint{variant: "Lynx Point Server"})
+ }
+
+ for _, id := range []uint16 {
+ 0x9c41, 0x9c43, 0x9c45,
+ } {
+ RegisterPCI(0x8086, uint16(id), lynxpoint{variant: "Lynx Point LP"})
+ }
+
+ /* PCIe bridge */
+ for _, id := range []uint16{
+ 0x8c10, 0x8c12, 0x8c14, 0x8c16, 0x8c18, 0x8c1a, 0x8c1c, 0x8c1e,
+ 0x9c10, 0x9c12, 0x9c14, 0x9c16, 0x9c18, 0x9c1a,
+ } {
+ RegisterPCI(0x8086, id, GenericPCI{})
+ }
+
+ /* SMBus controller */
+ RegisterPCI(0x8086, 0x1c22, GenericPCI{MissingParent: "smbus"})
+ RegisterPCI(0x8086, 0x1e22, GenericPCI{MissingParent: "smbus"})
+ RegisterPCI(0x8086, 0x8c22, GenericPCI{MissingParent: "smbus"})
+ RegisterPCI(0x8086, 0x9c22, GenericPCI{MissingParent: "smbus"})
+
+ /* SATA */
+ for _, id := range []uint16{
+ 0x8c00, 0x8c02, 0x8c04, 0x8c06, 0x8c08, 0x8c0e,
+ 0x8c01, 0x8c03, 0x8c05, 0x8c07, 0x8c09, 0x8c0f,
+ 0x9c03, 0x9c05, 0x9c07, 0x9c0f,
+ } {
+ RegisterPCI(0x8086, id, GenericPCI{})
+ }
+
+ /* EHCI */
+ for _, id := range []uint16{
+ 0x9c26, 0x8c26, 0x8c2d,
+ } {
+ RegisterPCI(0x8086, id, GenericPCI{})
+ }
+
+ /* XHCI */
+ RegisterPCI(0x8086, 0x8c31, GenericPCI{})
+ RegisterPCI(0x8086, 0x9c31, GenericPCI{})
+
+ /* ME and children */
+ for _, id := range []uint16{
+ 0x8c3a, 0x8c3b,
+ } {
+ RegisterPCI(0x8086, id, GenericPCI{})
+ }
+
+ /* Ethernet */
+ RegisterPCI(0x8086, 0x8c33, GenericPCI{})
+}
diff --git a/util/autoport/main.go b/util/autoport/main.go
index 05a829b..c1920a7 100644
--- a/util/autoport/main.go
+++ b/util/autoport/main.go
@@ -236,6 +236,12 @@
pcidev.ConfigDump[addr])
}
+func RestoreDIRRoute(f *os.File, regname string, val uint16) {
+ fmt.Fprintf(f, " RCBA_SET_REG_16(%s, DIR_ROUTE(PIRQ%c, PIRQ%c, PIRQ%c, PIRQ%c)),\n",
+ regname, 'A' + (val & 7), 'A' + ((val >> 4) & 7),
+ 'A' + ((val >> 8) & 7), 'A' + ((val >> 12) & 7))
+}
+
func RestorePCI32Simple(f *os.File, pcidev PCIDevData, addr uint16) {
fmt.Fprintf(f, " pci_write_config32(PCI_DEV(%d, 0x%02x, %d), 0x%02x, 0x%02x%02x%02x%02x);\n",
pcidev.Bus, pcidev.Dev, pcidev.Func, addr,
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I4f6e8c97b5122101de2f36bba8ba9f8ddd5b813a
Gerrit-Change-Number: 30890
Gerrit-PatchSet: 1
Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com>
Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com>
Gerrit-MessageType: newchange
1 hour, 53 minutes
- 6
- 36
Change in coreboot[master]: cpu/qemu-x86/car: Move long mode entry right before c entry
by Patrick Rudolph (Code Review)
Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37370 )
Change subject: cpu/qemu-x86/car: Move long mode entry right before c entry
......................................................................
cpu/qemu-x86/car: Move long mode entry right before c entry
Change-Id: I45e56ed8db9a44c00cd61e962bb82f27926eb23f
Signed-off-by: Patrick Rudolph <siro(a)das-labor.org>
---
M src/arch/x86/bootblock_crt0.S
M src/cpu/qemu-x86/cache_as_ram_bootblock.S
2 files changed, 3 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/37370/1
diff --git a/src/arch/x86/bootblock_crt0.S b/src/arch/x86/bootblock_crt0.S
index 3256731..e167a12 100644
--- a/src/arch/x86/bootblock_crt0.S
+++ b/src/arch/x86/bootblock_crt0.S
@@ -30,12 +30,6 @@
#include <cpu/x86/16bit/reset16.inc>
#include <cpu/x86/32bit/entry32.inc>
- /* BIST result in eax */
- mov %eax, %ebx
- /* entry64.inc preserves ebx. */
-#include <cpu/x86/64bit/entry64.inc>
- mov %ebx, %eax
-
#if CONFIG(BOOTBLOCK_DEBUG_SPINLOOP)
/* Wait for a JTAG debugger to break in and set EBX non-zero */
diff --git a/src/cpu/qemu-x86/cache_as_ram_bootblock.S b/src/cpu/qemu-x86/cache_as_ram_bootblock.S
index 1fa0018..f7280bf 100644
--- a/src/cpu/qemu-x86/cache_as_ram_bootblock.S
+++ b/src/cpu/qemu-x86/cache_as_ram_bootblock.S
@@ -39,6 +39,9 @@
/* Align the stack and keep aligned for call to bootblock_c_entry() */
and $0xfffffff0, %esp
+ /* entry64.inc preserves ebx. */
+#include <cpu/x86/64bit/entry64.inc>
+
/* Restore the BIST result and timestamps. */
#if defined(__x86_64__)
movd %mm1, %rdi
--
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Gerrit-Branch: master
Gerrit-Change-Id: I45e56ed8db9a44c00cd61e962bb82f27926eb23f
Gerrit-Change-Number: 37370
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-MessageType: newchange
13 hours, 3 minutes
- 3
- 8
Change in coreboot[master]: [WIP]nehalem: Add x86_64 support
by Patrick Rudolph (Code Review)
Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37371 )
Change subject: [WIP]nehalem: Add x86_64 support
......................................................................
[WIP]nehalem: Add x86_64 support
Use correct datasize to compile on x86_64.
Change-Id: I213b2b1c5de174b5c14b67d1b437d19c656d13fd
Signed-off-by: Patrick Rudolph <siro(a)das-labor.org>
---
M src/arch/x86/Makefile.inc
M src/arch/x86/include/arch/cbfs.h
M src/cpu/intel/car/non-evict/cache_as_ram.S
M src/cpu/intel/microcode/microcode_asm.S
M src/cpu/intel/model_2065x/Kconfig
M src/cpu/x86/early_reset.S
M src/drivers/pc80/tpm/tis.c
M src/northbridge/intel/nehalem/raminit.c
M src/southbridge/intel/bd82x6x/me_8.x.c
M src/southbridge/intel/ibexpeak/azalia.c
M src/southbridge/intel/ibexpeak/lpc.c
M src/southbridge/intel/ibexpeak/me.c
M src/southbridge/intel/ibexpeak/sata.c
M src/southbridge/intel/ibexpeak/smihandler.c
14 files changed, 39 insertions(+), 16 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/37371/1
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 45db303..a25d91a 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -126,7 +126,7 @@
$(eval $(call early_x86_stage,bootblock,elf64-x86-64))
endif
-bootblock-$(CONFIG_ARCH_BOOTBLOCK_X86_32) += walkcbfs.S
+bootblock-y += walkcbfs.S
else # ROMCC_BOOTBLOCK
diff --git a/src/arch/x86/include/arch/cbfs.h b/src/arch/x86/include/arch/cbfs.h
index ec367ed..78bf2ed 100644
--- a/src/arch/x86/include/arch/cbfs.h
+++ b/src/arch/x86/include/arch/cbfs.h
@@ -33,7 +33,7 @@
static void *walkcbfs(char *target)
{
struct cbfs_file *head = walkcbfs_head(target);
- if ((u32)head != 0)
+ if ((uintptr_t)head != 0)
return CBFS_SUBHEADER(head);
/* We should never reach this if 'target' exists */
@@ -51,7 +51,7 @@
static inline unsigned long findstage(char *target)
{
struct cbfs_stage_restricted *stage = walkcbfs(target);
- if ((u32)stage != 0)
+ if ((uintptr_t)stage != 0)
return stage->entry;
/* We should never reach this if 'target' exists */
diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S
index 5a668c4..e458302 100644
--- a/src/cpu/intel/car/non-evict/cache_as_ram.S
+++ b/src/cpu/intel/car/non-evict/cache_as_ram.S
@@ -220,8 +220,20 @@
/* Need to align stack to 16 bytes at call instruction. Account for
the pushes below. */
andl $0xfffffff0, %esp
- subl $4, %esp
+ /* entry64.inc preserves ebx. */
+#include <cpu/x86/64bit/entry64.inc>
+
+#ifdef __x86_64__
+
+ movd %mm2, %rdi
+ shld %rdi, 32
+ movd %mm1, %rsi
+ or %rsi, %rdi /* tsc */
+
+ movd %mm0, %rsi /* BIST */
+#else
+ subl $4, %esp
/* push TSC and BIST to stack */
movd %mm0, %eax
pushl %eax /* BIST */
@@ -229,6 +241,7 @@
pushl %eax /* tsc[63:32] */
movd %mm1, %eax
pushl %eax /* tsc[31:0] */
+#endif
before_c_entry:
post_code(0x29)
diff --git a/src/cpu/intel/microcode/microcode_asm.S b/src/cpu/intel/microcode/microcode_asm.S
index 647f67c..b9c43cc 100644
--- a/src/cpu/intel/microcode/microcode_asm.S
+++ b/src/cpu/intel/microcode/microcode_asm.S
@@ -56,6 +56,7 @@
.section .text
.global update_bsp_microcode
+.code32
update_bsp_microcode:
/* Keep return address */
diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig
index a76a95d..d816b4e 100644
--- a/src/cpu/intel/model_2065x/Kconfig
+++ b/src/cpu/intel/model_2065x/Kconfig
@@ -3,12 +3,20 @@
if CPU_INTEL_MODEL_2065X
+config ARCH_EXP_X86_64
+ bool "Experimental 64bit support"
+ default n
+
config CPU_SPECIFIC_OPTIONS
def_bool y
- select ARCH_BOOTBLOCK_X86_32
- select ARCH_VERSTAGE_X86_32
- select ARCH_ROMSTAGE_X86_32
- select ARCH_RAMSTAGE_X86_32
+ select ARCH_BOOTBLOCK_X86_32 if !ARCH_EXP_X86_64
+ select ARCH_VERSTAGE_X86_32 if !ARCH_EXP_X86_64
+ select ARCH_ROMSTAGE_X86_32 if !ARCH_EXP_X86_64
+ select ARCH_RAMSTAGE_X86_32 if !ARCH_EXP_X86_64
+ select ARCH_BOOTBLOCK_X86_64 if ARCH_EXP_X86_64
+ select ARCH_VERSTAGE_X86_64 if ARCH_EXP_X86_64
+ select ARCH_ROMSTAGE_X86_64 if ARCH_EXP_X86_64
+ select ARCH_RAMSTAGE_X86_64 if ARCH_EXP_X86_64
select SMP
select SSE2
select UDELAY_TSC
diff --git a/src/cpu/x86/early_reset.S b/src/cpu/x86/early_reset.S
index ec015abe..998ebda 100644
--- a/src/cpu/x86/early_reset.S
+++ b/src/cpu/x86/early_reset.S
@@ -21,6 +21,7 @@
.section .text
.global check_mtrr
+.code32
check_mtrr:
/* Use the MTRR default type MSR as a proxy for detecting INIT#.
diff --git a/src/drivers/pc80/tpm/tis.c b/src/drivers/pc80/tpm/tis.c
index 39fa70d..27e11bd 100644
--- a/src/drivers/pc80/tpm/tis.c
+++ b/src/drivers/pc80/tpm/tis.c
@@ -55,7 +55,7 @@
/* the macro accepts the locality value, but only locality 0 is operational */
#define TIS_REG(LOCALITY, REG) \
- (void *)(CONFIG_TPM_TIS_BASE_ADDRESS + (LOCALITY << 12) + REG)
+ (void *)((uintptr_t)CONFIG_TPM_TIS_BASE_ADDRESS + (LOCALITY << 12) + REG)
/* hardware registers' offsets */
#define TIS_REG_ACCESS 0x0
diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c
index a393cb7..673cb5a 100644
--- a/src/northbridge/intel/nehalem/raminit.c
+++ b/src/northbridge/intel/nehalem/raminit.c
@@ -1999,7 +1999,7 @@
u32 offset;
u8 *base;
- base = (u8 *)(totalrank << 28);
+ base = (u8 *)(uintptr_t)(totalrank << 28);
for (offset = 0; offset < 9 * 480; offset += 2) {
write32(base + offset * 8, get_etalon2(flip, offset));
write32(base + offset * 8 + 4, get_etalon2(flip, offset));
diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c
index f13ced9..84960ea 100644
--- a/src/southbridge/intel/bd82x6x/me_8.x.c
+++ b/src/southbridge/intel/bd82x6x/me_8.x.c
@@ -482,7 +482,7 @@
struct me_hfs hfs;
u32 reg32;
- mei_base_address = (void *)
+ mei_base_address = (void *)(uintptr_t)
(pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf);
/* S3 path will have hidden this device already */
diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c
index 5b38ea7..c0d2494 100644
--- a/src/southbridge/intel/ibexpeak/azalia.c
+++ b/src/southbridge/intel/ibexpeak/azalia.c
@@ -238,7 +238,7 @@
// NOTE this will break as soon as the Azalia get's a bar above
// 4G. Is there anything we can do about it?
base = res2mmio(res, 0, 0);
- printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base);
+ printk(BIOS_DEBUG, "Azalia: base = %p\n", base);
if (RCBA32(0x2030) & (1 << 31)) {
reg32 = pci_read_config32(dev, 0x120);
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c
index 2b48eab..6771a7a 100644
--- a/src/southbridge/intel/ibexpeak/lpc.c
+++ b/src/southbridge/intel/ibexpeak/lpc.c
@@ -598,7 +598,7 @@
/* Add it to SSDT. */
acpigen_write_scope("\\");
- acpigen_write_name_dword("NVSA", (u32) gnvs);
+ acpigen_write_name_dword("NVSA", (uintptr_t) gnvs);
acpigen_pop_len();
}
}
diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c
index 63dff6a..62fd08a 100644
--- a/src/southbridge/intel/ibexpeak/me.c
+++ b/src/southbridge/intel/ibexpeak/me.c
@@ -372,7 +372,7 @@
struct me_hfs hfs;
u32 reg32;
- mei_base_address = (u32 *)
+ mei_base_address = (u32 *)(uintptr_t)
(pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf);
/* S3 path will have hidden this device already */
diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c
index 2d9412a..33e717a 100644
--- a/src/southbridge/intel/ibexpeak/sata.c
+++ b/src/southbridge/intel/ibexpeak/sata.c
@@ -104,7 +104,7 @@
pci_write_config32(dev, 0x98, 0x00590200);
/* Initialize AHCI memory-mapped space */
- abar = (u32 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5);
+ abar = (u32 *)(uintptr_t)pci_read_config32(dev, PCI_BASE_ADDRESS_5);
printk(BIOS_DEBUG, "ABAR: %p\n", abar);
/* CAP (HBA Capabilities) : enable power management */
reg32 = read32(abar + 0x00);
diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c
index 3668842..a68c89a 100644
--- a/src/southbridge/intel/ibexpeak/smihandler.c
+++ b/src/southbridge/intel/ibexpeak/smihandler.c
@@ -177,7 +177,7 @@
smi_apmc_find_state_save(apm_cnt);
if (state) {
/* EBX in the state save contains the GNVS pointer */
- gnvs = (global_nvs_t *)((u32)state->rbx);
+ gnvs = (global_nvs_t *)(uintptr_t)((u32)state->rbx);
*smm_done = 1;
printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I213b2b1c5de174b5c14b67d1b437d19c656d13fd
Gerrit-Change-Number: 37371
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-MessageType: newchange
2 days, 15 hours
- 2
- 8
Change in coreboot[master]: soc/intel/common/block: Update microcode for each core
by Patrick Rudolph (Code Review)
Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35739 )
Change subject: soc/intel/common/block: Update microcode for each core
......................................................................
soc/intel/common/block: Update microcode for each core
On Hyper-Threading enabled platform update the microcde only once
for each core, not for each thread.
Follow Intel Software Developer Guidelines as the added comment
also states.
Change-Id: I72804753e567a137a5648ca6950009fed332531b
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/soc/intel/common/block/cpu/mp_init.c
1 file changed, 20 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/35739/1
diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c
index 2c5061f..e7689cf 100644
--- a/src/soc/intel/common/block/cpu/mp_init.c
+++ b/src/soc/intel/common/block/cpu/mp_init.c
@@ -26,6 +26,7 @@
#include <intelblocks/fast_spi.h>
#include <intelblocks/mp_init.h>
#include <intelblocks/msr.h>
+#include <cpu/intel/common/common.h>
#include <soc/cpu.h>
static const void *microcode_patch;
@@ -44,7 +45,24 @@
static void init_one_cpu(struct device *dev)
{
soc_core_init(dev);
- intel_microcode_load_unlocked(microcode_patch);
+
+ /*
+ * Update just on the first CPU in the core. Other siblings
+ * get the update automatically according to Document: 253668-060US
+ * Intel SDM Chapter 9.11.6.3
+ * "Update in a System Supporting Intel Hyper-Threading Technology"
+ * Intel Hyper-Threading Technology has implications on the loading of the
+ * microcode update. The update must be loaded for each core in a physical
+ * processor. Thus, for a processor supporting Intel Hyper-Threading
+ * Technology, only one logical processor per core is required to load the
+ * microcode update. Each individual logical processor can independently
+ * load the update. However, MP initialization must provide some mechanism
+ * (e.g. a software semaphore) to force serialization of microcode update
+ * loads and to prevent simultaneous load attempts to the same core.
+ */
+ if (!intel_ht_sibling()) {
+ intel_microcode_load_unlocked(microcode_patch);
+ }
}
static struct device_operations cpu_dev_ops = {
@@ -141,6 +159,7 @@
if (CONFIG(USE_INTEL_FSP_MP_INIT))
return;
+ /* Update microcode on BSP */
microcode_patch = intel_microcode_find();
intel_microcode_load_unlocked(microcode_patch);
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I72804753e567a137a5648ca6950009fed332531b
Gerrit-Change-Number: 35739
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Gerrit-MessageType: newchange
5 days, 20 hours
- 7
- 31
Change in ...coreboot[master]: csb_patcher.sh: gets,checks,installs the coreboot and SeaBIOS patches
by Mike Banon (Code Review)
Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33509
Change subject: csb_patcher.sh: gets,checks,installs the coreboot and SeaBIOS patches
......................................................................
csb_patcher.sh: gets,checks,installs the coreboot and SeaBIOS patches
Conveniently and securely gets, checks SHA256 and installs some of my
patches from this page - https://review.coreboot.org/q/status:open+banon
- and also gets a collection of useful floppy-based operating systems.
Sometimes it takes quite a long time to get a patch merged, while the
people might need it today! - and this script could be really helpful.
It asks a [Y/N] question for every addition, and since there are some
"universal" patches as well as great floppies, you may still want to
run this script - even if your board is not Lenovo G505S or not AMD.
Please share your feedback/suggestions and tell about other useful patches,
preferably the "universal" ones - i.e. SeaBIOS. Currently included:
1) "board-specific": G505S dGPU support, G505S config and AtomBIOS ROMs
2) "universal": SeaBIOS patches: advanced_bootmenu, multiple_floppies,
writeprotected_usb ; tint build system ; and also a floppies collection :
KolibriOS, FreeDOS, MichalOS, Snowdrop, Fiwix, Memtest, Tatos, Plop, FloppyBird.
Run ./csb_patcher.sh help or ./csb_patcher.sh usage for more information.
Signed-off-by: Mike Banon <mikebdp2(a)gmail.com>
Change-Id: I66f4f2865ac63ce0f2615669c7a3abd70a397e49
---
A csb_patcher.sh
1 file changed, 876 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/33509/1
diff --git a/csb_patcher.sh b/csb_patcher.sh
new file mode 100755
index 0000000..b325f71
--- /dev/null
+++ b/csb_patcher.sh
@@ -0,0 +1,876 @@
+#!/bin/sh
+#
+# csb_patcher.sh: coreboot and SeaBIOS patcher script.
+#
+# Conveniently and securely gets, checks SHA256 and installs some of my
+# patches from this page - https://review.coreboot.org/q/status:open+banon
+# and also gets a collection of useful floppy-based operating systems.
+# Please send your feedback to Mike Banon <mikebdp2(a)gmail.com>
+#
+
+# Keys
+enter=$( printf '\015' )
+ctrl_c=$( printf '\003' )
+ctrl_x=$( printf '\030' )
+ctrl_z=$( printf '\032' )
+
+# Formatting
+bold="\e[1m"
+bred="\e[1;31m"
+bgreen="\e[1;32m"
+byellow="\e[1;33m"
+bend="\e[0m"
+
+# Asks a question '$1' and waits for Y/N user input, printing a decision - with '$2' message if Y.
+yesno () {
+ printf "$1 [Y/N] "
+ yesno_old_stty_cfg=$( stty -g )
+ stty raw -echo
+ while true ; do
+ yesno_answer=$( head -c 1 )
+ case "$yesno_answer" in
+ *"$ctrl_c"*|"$ctrl_x"*|"$ctrl_z"*)
+ stty "$yesno_old_stty_cfg"
+ printf "${bred}TERMINATED${bend}\n"
+ exit 1
+ ;;
+ *"y"*|"Y"*)
+ stty "$yesno_old_stty_cfg"
+ printf "${bgreen}YES${bend}$2\n"
+ return 0
+ ;;
+ *"n"*|"N"*)
+ stty "$yesno_old_stty_cfg"
+ printf "${byellow}NO${bend}\n"
+ return 1
+ ;;
+ esac
+ done
+}
+
+# Waits until a user presses Enter.
+encontinue () {
+ printf "\npress [ENTER] to continue... "
+ encontinue_old_stty_cfg=$( stty -g )
+ stty raw -echo
+ while true ; do
+ encontinue_answer=$( head -c 1 )
+ case "$encontinue_answer" in
+ *"$ctrl_c"*|"$ctrl_x"*|"$ctrl_z"*)
+ stty "$encontinue_old_stty_cfg"
+ printf "${bred}TERMINATED${bend}\n"
+ exit 1
+ ;;
+ *"$enter"*)
+ stty "$encontinue_old_stty_cfg"
+ printf "\n"
+ return 0
+ ;;
+ esac
+ done
+}
+
+# Checks if a command '$1' exists.
+command_exists() {
+ if [ ! -x "$( command -v $1 )" ] ; then
+ printf "\n${bred}ERROR${bend}: command ${bold}$1${bend} is not found !\n"
+ encontinue
+ return 1
+ else
+ return 0
+ fi
+}
+
+# Checks if a file '$1' exists.
+file_exists () {
+ if [ ! -f "$1" ] ; then
+ printf "\n${byellow}WARNING${bend}: file ${bold}$1${bend} is not found !\n"
+ encontinue
+ return 1
+ else
+ return 0
+ fi
+}
+
+# Force removes a file '$2' and then copies a file '$1' to '$2'.
+copier () {
+ if file_exists "$1" ; then
+ rm -f "$2"
+ cp "$1" "$2"
+ return 0
+ else
+ return 1
+ fi
+}
+
+# Force removes a file '$2' and then moves a file '$1' to '$2'.
+mover () {
+ if file_exists "$1" ; then
+ rm -f "$2"
+ mv "$1" "$2"
+ return 0
+ else
+ return 1
+ fi
+}
+
+# Checks if line '$1' contains the text '$2'.
+checker () {
+ case "$1" in
+ *"$2"*)
+ return 0
+ ;;
+ *)
+ return 1
+ ;;
+ esac
+}
+
+# Prints the lines of a file '$2' which contain the text '$1'.
+grepper () {
+ if file_exists "$2" ; then
+ while IFS= read -r grepper_line
+ do
+ case "$grepper_line" in
+ *"$1"*)
+ printf '%s\n' "$grepper_line"
+ ;;
+ esac
+ done < "$2"
+ return 0
+ else
+ return 1
+ fi
+}
+
+# Checks if a file '$2' contains the text '$1'.
+grepcheck () {
+ if file_exists "$2" ; then
+ while IFS= read -r grepcheck_line
+ do
+ case "$grepcheck_line" in
+ *"$1"*)
+ return 0
+ ;;
+ esac
+ done < "$2"
+ return 1
+ else
+ return 1
+ fi
+}
+
+# Replaces the lines containing the text '$2' of a file '$1' with a line '$3'.
+sedder () {
+ if file_exists "$1" ; then
+ csb_sedder_tmp="./.csb_sedder"
+ rm -f "$csb_sedder_tmp"
+ while IFS= read -r sedder_line
+ do
+ case "$sedder_line" in
+ *"$2"*)
+ if [ ! -z "$3" ] ; then
+ printf '%s\n' "$3" >> "$csb_sedder_tmp"
+ fi
+ ;;
+ *)
+ printf '%s\n' "$sedder_line" >> "$csb_sedder_tmp"
+ ;;
+ esac
+ done < "$1"
+ mover "$csb_sedder_tmp" "$1"
+ return 0
+ else
+ return 1
+ fi
+}
+
+# Downloads a file '$1' from a link '$2' using the options '$3' and checks if this was successful.
+wgetter () {
+ rm -f "$1"
+ if [ -z "$3" ] ; then
+ wget "$2"
+ else
+ wget "$3" "$2"
+ fi
+ if [ -f "$1" ] ; then
+ wgetter_file_size=$(($( wc -c < "$1" )))
+ if [ "$wgetter_file_size" -eq "0" ] ; then
+ rm -f "$1"
+ fi
+ fi
+ if [ ! -f "$1" ] ; then
+ printf "\n${byellow}WARNING${bend}: can't download a ${bold}$1${bend} file !"
+ printf "\n Please check your Internet connection and try again.\n"
+ encontinue
+ return 1
+ else
+ return 0
+ fi
+}
+
+# Unzips the archive '$1', optional '$2' for -j path inside the archive, and then force removes it.
+unzipper () {
+ if file_exists "$1" ; then
+ if [ -z "$2" ] ; then
+ unzip "$1"
+ else
+ unzip -j "$1" "$2"
+ fi
+ rm -f "$1"
+ return 0
+ else
+ return 1
+ fi
+}
+
+# Expands a file '$1' with zeroes using a dd to '$2' size - e.g. to a standard floppy size 1474560.
+expander () {
+ if file_exists "$1" && [ ! -z "$2" ] ; then
+ expander_file_size=$(($( wc -c < "$1" )))
+ if [ "$expander_file_size" -lt "$2" ] ; then
+ dd if=/dev/zero of=$1 bs=1 count=1 seek="$(( $2 - 1 ))" conv=notrunc iflag=nocache
+ fi
+ return 0
+ else
+ return 1
+ fi
+}
+
+# Compares sha256sum of '$1.img' floppy image with '$2' and creates a hidden '.$1' file if matches.
+floppy_verifier () {
+ rm -f "./.$1"
+ cd ".."
+ if [ ! -z "$2" ] ; then
+ if file_exists "./floppies/$1.img" ; then
+ floppy_verifier_sha256sum_correct="$2 ./floppies/$1.img"
+ floppy_verifier_sha256sum_my=$( sha256sum "./floppies/$1.img" )
+ printf "\n=== sha256sum should be:\n${bold}$floppy_verifier_sha256sum_correct${bend}\n"
+ if [ "$floppy_verifier_sha256sum_my" = "$floppy_verifier_sha256sum_correct" ] ; then
+ printf "^^^ this is correct, ./floppies/${bold}$1.img${bend} is verified and could be added.\n\n"
+ cd "./floppies/"
+ touch "./.$1"
+ return 0
+ else
+ printf "${bold}^^^ ! MISMATCH for ./floppies/$1.img ! Check sha256sum manually: sha256sum ./floppies/$1.img${bend}\n"
+ encontinue
+ cd "./floppies/"
+ return 1
+ fi
+ else
+ printf "\n${byellow}WARNING${bend}: cannot find ./floppies/${bold}$1.img${bend} !\n"
+ printf "\n Please re-download a set of floppies.\n"
+ encontinue
+ return 1
+ fi
+ else
+ printf "\n${byellow}WARNING${bend}: ./floppies/${bold}$1.img${bend} - is a rolling release, its' SHA256 checksum"
+ printf "\n is changing constantly and not provided by $1 project, so not checked.\n"
+ encontinue
+ cd "./floppies/"
+ touch "./.$1"
+ return 0
+ fi
+}
+
+# Downloads a collection of floppies, for the purpose of adding them later to a coreboot ROM image.
+floppy_mass_downloader () {
+ printf "\n"
+ if [ ! -d "./floppies/" ]; then
+ mkdir "./floppies/"
+ fi
+ cd "./floppies/"
+ # KOLIBRI
+ if command_exists "7za" ; then
+ if wgetter "./latest-img.7z" "https://builds.kolibrios.org/eng/latest-img.7z" ; then
+ rm -f "./kolibri.img"
+ 7za x "./latest-img.7z"
+ rm -f "./latest-img.7z"
+ floppy_verifier "kolibri" "" # IS A ROLLING RELEASE, NO SHA256 VERIFICATION
+ fi
+ else
+ printf "\n${byellow}WARNING${bend}: cannot get ./floppies/${bold}kolibri.img${bend} without ${bold}7za${bend}\n"
+ encontinue
+ fi
+ # FREEDOS
+ if wgetter "./FD12FLOPPY.zip" "https://www.freedos.org/download/download/FD12FLOPPY.zip" ; then
+ unzipper "./FD12FLOPPY.zip" "FLOPPY.img"
+ mover "./FLOPPY.img" "./freedos.img"
+ floppy_verifier "freedos" "de2fb84dc2f132324549e89d58c6383497ec1af538c5b0ecde389fb748b9d537"
+ fi
+ # MICHALOS
+ printf "\n${byellow}WARNING${bend}: getting ./floppies/${bold}michalos.img${bend} could take a couple of minutes...\n\n"
+ if wgetter "./MichalOS 2.0 Source.zip" "https://sourceforge.net/p/michalos/tickets/_discuss/thread/69ab1508c3/39cd/…" "--content-disposition" ; then
+ unzipper "./MichalOS 2.0 Source.zip" "disk_images/michalos.img"
+ floppy_verifier "michalos" "139e9d08881f646156971a0a061972ddca77057b8acf4164e36366271ab3658c"
+ fi
+ # SNOWDROP
+ if wgetter "./snowdrop.img" "http://sebastianmihai.com/downloads/snowdrop/snowdrop.img" ; then
+ floppy_verifier "snowdrop" "" # IS A ROLLING RELEASE, NO SHA256 VERIFICATION
+ fi
+ # FIWIX
+ if wgetter "./fiwix.img" "https://www.fiwix.org/fiwix-1.0.1-i386-initrd.img" "--output-document=fiwix.img" ; then
+ floppy_verifier "fiwix" "dbec2994ec619c9954327ab0b983ab24cd362406a2e515c35c79c79bd6417cfd"
+ fi
+ # MEMTEST
+ if wgetter "./memtest86+-5.01.floppy.zip" "https://www.memtest.org/download/5.01/memtest86+-5.01.floppy.zip" ; then
+ unzipper "./memtest86+-5.01.floppy.zip" "floppy/memtestp.bin"
+ expander "./memtestp.bin" "1474560"
+ mover "./memtestp.bin" "./memtest.img"
+ floppy_verifier "memtest" "364535abd0d105da9396df6015e480c4d4c52b07dcc4e1d4756bde8ef87a30f1"
+ fi
+ # TATOS
+ if wgetter "./tatos.img" "https://github.com/tatimmer/tatOS/raw/master/tatOS.img" "--output-document=tatos.img" ; then
+ expander "./tatos.img" "1474560"
+ floppy_verifier "tatos" "2c66f884498a4fe7b469bc213aebfccd84a09fd7ace1b3b4b3e747e2392c35d1"
+ fi
+ # PLOP
+ if wgetter "./plpbt-5.0.15.zip" "https://download.plop.at/files/bootmngr/plpbt-5.0.15.zip" ; then
+ unzipper "./plpbt-5.0.15.zip" "plpbt-5.0.15/plpbt.img"
+ mover "./plpbt.img" "./plop.img"
+ floppy_verifier "plop" "f170759966ec4efe60c8531158344a234d7543c8de81e54c8c1bb9d2d69eaf27"
+ fi
+ # FLOPPYBIRD
+ if wgetter "./floppybird.img" "https://github.com/mikebdp2/floparchive/raw/master/floppies_extra/floppybir…" ; then
+ floppy_verifier "floppybird" "5db1b469e25e9eda7b8c0f666d6b655bab083c85618a9453ee72f1201cca840f"
+ fi
+ # Some floppies have the weird permissions after their extraction
+ floppy_mass_downloader_floppies=$( find . -name "*.img" )
+ if [ ! -z "$floppy_mass_downloader_floppies" ] ; then
+ chmod 755 "./"*".img"
+ fi
+ # Return back to ./coreboot/
+ cd ".."
+ return 0
+}
+
+# Adds a './pci1002,$1.rom' to coreboot '$3' ROM using '$2' cbfstool, printing '$4'/'$5'/'$6' info.
+atombios_adder () {
+ if file_exists "$2" && file_exists "$3" ; then
+ if [ -f "./pci1002,$1.rom" ] ; then
+ atombios_adder_cbfs=$( "$2" "$3" print )
+ if checker "$atombios_adder_cbfs" "pci1002,$1.rom" ; then
+ printf "\n${bgreen}NOTE${bend}: ./${bold}pci1002,$1.rom${bend} for ${bold}$5 : $6${bend} is already at your $3.\n"
+ else
+ if yesno "\nAdd a ./${bold}pci1002,$1.rom${bend} for ${bold}$5 : $6${bend} to your $3 now? ${bold}~$4${bend}" ", adding..." ; then
+ "$2" "$3" add -f "./pci1002,$1.rom" -n "pci1002,$1.rom" -t optionrom
+ else
+ printf "\n${bold}You can add it later by running:${bend}"
+ printf "\n${bold} $2 $3 add -f ./pci1002,$1.rom -n pci1002,$1.rom -t optionrom${bend}\n\n"
+ fi
+ fi
+ return 0
+ else
+ printf "\n${byellow}WARNING${bend}: cannot find ./${bold}pci1002,$1.rom${bend} ,"
+ printf "\n please re-apply ${bold}AMD atombios${bend} patch.\n"
+ encontinue
+ return 1
+ fi
+ else
+ return 1
+ fi
+}
+
+# Adds a '$1.img' floppy image to coreboot '$3' ROM using '$2' cbfstool, printing '$4' size info.
+floppy_adder () {
+ if file_exists "$2" && file_exists "$3" ; then
+ if [ -f "./floppies/$1.img" ] ; then
+ if [ -f "./floppies/.$1" ] ; then
+ floppy_adder_cbfs=$( "$2" "$3" print )
+ if checker "$floppy_adder_cbfs" "floppyimg/$1.lzma" ; then
+ printf "\n${bgreen}NOTE${bend}: ./floppies/${bold}$1.img${bend} is already at your $3.\n"
+ else
+ if checker "$1" "plop" ; then
+ printf "\n${byellow}WARNING${bend}: ./floppies/${bold}$1.img${bend} - is proprietary: all its' source code is closed !"
+ printf "\n Add it only if you really need it and trust the author of $1 project.\n"
+ encontinue
+ fi
+ if yesno "\nAdd a ./floppies/${bold}$1.img${bend} to your $3 now? ${bold}~$4${bend}" ", adding..." ; then
+ "$2" "$3" add -f "./floppies/$1.img" -n "floppyimg/$1.lzma" -t raw -c lzma
+ else
+ printf "\n${bold}You can add it later by running:${bend}"
+ printf "\n${bold} $2 $3 add -f ./floppies/$1.img -n floppyimg/$1.lzma -t raw -c lzma${bend}\n\n"
+ fi
+ fi
+ return 0
+ else
+ printf "\n${byellow}WARNING${bend}: there was a SHA256 mismatch for ./floppies/${bold}$1.img${bend} -"
+ printf "\n check sha256sum manually: sha256sum ./floppies/${bold}$1.img${bend}\n"
+ encontinue
+ return 1
+ fi
+ else
+ printf "\n${byellow}WARNING${bend}: cannot find ./floppies/${bold}$1.img${bend} !\n"
+ printf "\n Please re-download a set of floppies.\n"
+ encontinue
+ return 1
+ fi
+ else
+ return 1
+ fi
+}
+
+# Adds a set of AtomBIOS/floppies ('$1') to coreboot '$3' ROM copied to '$4', using '$2' cbfstool.
+cbfs_mass_adder () {
+ if ! grepcheck "how to submit coreboot changes" ./MAINTAINERS ; then
+ printf "\n${byellow}WARNING${bend}: not sure if I am inside the coreboot directory,"
+ printf "\n trying to add a ${bold}$1${bend} set from here - could fail.\n\n"
+ fi
+ if file_exists "$2" && file_exists "$3" ; then
+ if checker "$1" "atom" || checker "$1" "flop" ; then
+ copier "$3" "$4"
+ printf "\n${bold}=== $4 - initial memory map${bend}\n\n"
+ "$2" "$4" print
+ printf "\n"
+ if checker "$1" "atom" ; then
+###
+### https://review.coreboot.org/c/coreboot/+/31944
+### G505S AtomBIOS ROMs: known good binaries with a script to check their SHA256
+###
+ csb_patcher "atombios" "31944" "6" "78a8454" "9a8efff284bbdb81d5b912ccc8279162553e04673bde53e5288ba4bed0e4bc3d" "$1" "AMD "
+ atombios_adder "990b" "$2" "$4" "62K" "Lenovo G505S with A10-5750M" "iGPU HD-8650G"
+ atombios_adder "6663" "$2" "$4" "33K" "Lenovo G505S with A10-5750M" "dGPU HD-8570M"
+ atombios_adder "6665" "$2" "$4" "32K" "Lenovo G505S with A10-5750M" "dGPU R5-M230"
+ atombios_adder "9830" "$2" "$4" "59K" "ASUS AM1I-A with Athlon-5370" "iGPU HD-8400 / R3-Series"
+ atombios_adder "990c" "$2" "$4" "62K" "ASUS A88XM-E with A10-6700" "iGPU HD-8670D"
+ fi
+ if checker "$1" "flop" ; then
+ if [ ! -d "./floppies/" ] ; then
+ printf "\n"
+ floppy_mass_downloader
+ fi
+ # Default boot order: the last floppy added - is the first floppy to boot!
+ floppy_adder "floppybird" "$2" "$4" "2K"
+ floppy_adder "plop" "$2" "$4" "74K"
+ floppy_adder "tatos" "$2" "$4" "60K"
+ floppy_adder "memtest" "$2" "$4" "44K"
+ floppy_adder "fiwix" "$2" "$4" "458K"
+ floppy_adder "snowdrop" "$2" "$4" "126K"
+ floppy_adder "michalos" "$2" "$4" "256K"
+ floppy_adder "freedos" "$2" "$4" "698K"
+ floppy_adder "kolibri" "$2" "$4" "1264K"
+ fi
+ printf "\n${bold}=== $4 - final memory map${bend}\n\n"
+ "$2" "$4" print
+ printf "\nYou can use ./build/${bold}coreflop.rom${bend} now !\n\n"
+ return 0
+ else
+ return 1
+ fi
+ else
+ return 1
+ fi
+}
+
+# Finds the files of '$1' extension, saves the result to '$2' log and prints a message with '$3'.
+csb_finder () {
+ csb_finder_files=$( find . -name "*.$1" )
+ if [ ! -z "$csb_finder_files" ] ; then
+ printf "%25s\n" "*.$1 - YES" >> "$2"
+ printf "\n${byellow}WARNING${bend}: found ${bold}*.$1${bend} files at these locations :\n"
+ printf "$csb_finder_files"
+ printf "\n That means - Some patches $3\n"
+ encontinue
+ return 0
+ else
+ printf "%24s\n" "*.$1 - NO" >> "$2"
+ return 1
+ fi
+}
+
+# Prints a csb_patcher_log '$1' with a custom highlighting.
+csb_printer () {
+ if ! file_exists "$1" ; then
+ return 1
+ fi
+ while IFS= read -r csb_printer_line
+ do
+ case "$csb_printer_line" in
+ *"orig - YES"*)
+ printf "${csb_printer_line%???}${byellow}YES" # YELLOW
+ ;;
+ *"rej - YES"*)
+ printf "${csb_printer_line%???}${bred}YES" # RED
+ ;;
+ *"YES"*)
+ printf "${csb_printer_line%???}${bgreen}YES" # GREEN
+ ;;
+ *"orig - NO"*|*"rej - NO"*)
+ printf "${csb_printer_line%??}${bgreen}NO" # GREEN
+ ;;
+ *"NO"*)
+ printf "${csb_printer_line%??}${byellow}NO" # YELLOW
+ ;;
+ *"FAILURE_1"*)
+ printf "${csb_printer_line%?????????}${bred}FAILURE_1" # RED
+ ;;
+ *"FAILURE_2"*)
+ printf "${csb_printer_line%?????????}${bred}FAILURE_2" # RED
+ ;;
+ *"FAILURE_3"*)
+ printf "${csb_printer_line%?????????}${bred}FAILURE_3" # RED
+ ;;
+ *"\\\\"*)
+ printf "${bold}${csb_printer_line%?????}\\\\\!//" # ALIEN HAIR
+ ;;
+ *)
+ printf "${bold}$csb_printer_line"
+ ;;
+ esac
+ printf "${bend}\n"
+ done < "$1"
+ return 0
+}
+
+# Configure some popular options of a config file '$1'.
+csb_configurer () {
+ if file_exists "$1" ; then
+ csb_configurer_tmp="./.csb_configurer"
+ rm -f "$csb_configurer_tmp"
+ grepper "CONFIG_BOARD_" "$1" > "$csb_configurer_tmp"
+ if grepcheck "_LENOVO_G505S=y" "$csb_configurer_tmp" ; then
+ printf "\n\n${bgreen}[CONFIG]${bend} Questions about your Lenovo G505S\n\n"
+ sedder "$1" "### CSB_CONFIGURER OPTIONS" ""
+ printf "### CSB_CONFIGURER OPTIONS\n" >> "$1"
+ sedder "$1" "# CONFIG_DRIVERS_INTEL_WIFI is not set" ""
+ if ! yesno "Do you have an Intel WiFi adapter?" "" ; then
+ printf "# CONFIG_DRIVERS_INTEL_WIFI is not set\n" >> "$1"
+ fi
+ sedder "$1" "CONFIG_MULTIPLE_VGA_ADAPTERS=y" ""
+ sedder "$1" "CONFIG_VGA_BIOS_DGPU=y" ""
+ sedder "$1" "CONFIG_VGA_BIOS_DGPU_FILE=\"pci1002,6663.rom\"" ""
+ sedder "$1" "CONFIG_VGA_BIOS_DGPU_ID=\"1002,6663\"" ""
+ sedder "$1" "CONFIG_VGA_BIOS_DGPU_FILE=\"pci1002,6665.rom\"" ""
+ sedder "$1" "CONFIG_VGA_BIOS_DGPU_ID=\"1002,6665\"" ""
+ if yesno "Do you have a Discrete GPU?" "" ; then
+ printf "CONFIG_MULTIPLE_VGA_ADAPTERS=y\n" >> "$1"
+ printf "CONFIG_VGA_BIOS_DGPU=y\n" >> "$1"
+ if yesno "No for HD-8570M, Yes for R5-M230" "" ; then
+ printf "CONFIG_VGA_BIOS_DGPU_FILE=\"pci1002,6665.rom\"\n" >> "$1"
+ printf "CONFIG_VGA_BIOS_DGPU_ID=\"1002,6665\"\n" >> "$1"
+ else
+ printf "CONFIG_VGA_BIOS_DGPU_FILE=\"pci1002,6663.rom\"\n" >> "$1"
+ printf "CONFIG_VGA_BIOS_DGPU_ID=\"1002,6663\"\n" >> "$1"
+ fi
+ fi
+
+ sedder "$1" "# NATIVE" ""
+ sedder "$1" "CONFIG_HUDSON_SATA_MODE=0" ""
+
+ sedder "$1" "# RAID" ""
+ sedder "$1" "CONFIG_HUDSON_SATA_MODE=1" ""
+ sedder "$1" "CONFIG_RAID_ROM_ID=\"1022,7802\"" ""
+ sedder "$1" "CONFIG_RAID_ROM_FILE=\"src/southbridge/amd/agesa/hudson/raid.bin\"" ""
+ sedder "$1" "CONFIG_RAID_MISC_ROM_FILE=\"src/southbridge/amd/agesa/hudson/misc.bin\"" ""
+ sedder "$1" "CONFIG_RAID_MISC_ROM_POSITION=0xFFF00000" ""
+
+ sedder "$1" "# AHCI" ""
+ sedder "$1" "CONFIG_HUDSON_SATA_MODE=2" ""
+ sedder "$1" "CONFIG_AHCI_ROM_ID=\"1022,7801\"" ""
+ sedder "$1" "# CONFIG_HUDSON_AHCI_ROM is not set" ""
+
+ sedder "$1" "# LEGACY IDE" ""
+ sedder "$1" "CONFIG_HUDSON_SATA_MODE=3" ""
+
+ sedder "$1" "# IDE to AHCI" ""
+ sedder "$1" "CONFIG_HUDSON_SATA_MODE=4" ""
+
+ sedder "$1" "# AHCI7804" ""
+ sedder "$1" "CONFIG_HUDSON_SATA_MODE=5" ""
+ sedder "$1" "CONFIG_AHCI_ROM_ID=\"1022,7804\"" ""
+
+ sedder "$1" "# IDE to AHCI7804" ""
+ sedder "$1" "CONFIG_HUDSON_SATA_MODE=6" ""
+ sedder "$1" "# CONFIG_HUDSON_AHCI_ROM is not set" ""
+
+ if yesno "Do you have a SSD? (enable AHCI if Y)" "" ; then
+ printf "# AHCI\n" >> "$1"
+ printf "CONFIG_HUDSON_SATA_MODE=2\n" >> "$1"
+ printf "CONFIG_AHCI_ROM_ID=\"1022,7801\"\n" >> "$1"
+ printf "# CONFIG_HUDSON_AHCI_ROM is not set\n" >> "$1"
+ else
+ printf "# NATIVE\n" >> "$1"
+ printf "CONFIG_HUDSON_SATA_MODE=0\n" >> "$1"
+ fi
+ rm -f "$csb_configurer_tmp"
+ return 0
+ else
+ printf "\n\n${byellow}WARNING${bend}: sorry, I don't know how to configure a board of ${bold}$1${bend}\n"
+ encontinue
+ return 1
+ fi
+ else
+ return 1
+ fi
+}
+
+#
+# Conveniently and securely gets, checks SHA256 and installs a patch.
+# Arguments are the patch properties:
+# $1 - new diff name, could be also a part of extracted scripts' filename
+# $2 - change ID number, part of download link to review.coreboot.org
+# $3 - change revision number, part of download link to review.coreboot.org
+# $4 - diff filename inside the downloaded archive, will be renamed to $1
+# $5 - diff known good SHA256 checksum, will be used for SHA256 verification
+# $6 - filepath where to save a csb_patcher_log which will be printed later
+# $7 - info about the target of a patch, if not specified ("") it is common
+#
+csb_patcher () {
+ if ! wgetter "./patch?zip" "https://review.coreboot.org/changes/$2/revisions/$3/patch?zip" ; then
+ printf "${bold}^^^ ! Can't download a $7$1 patch ! Check your Internet.${bend}\n"
+ printf "%31s\n" "$7$1 - FAILURE_1" >> "$6"
+ csb_printer "$6"
+ exit 1
+ fi
+ unzipper "./patch?zip"
+ mover "./$4.diff" "./$1.diff"
+ csb_patcher_sha256sum_correct="$5 ./$1.diff"
+ csb_patcher_sha256sum_my=$( sha256sum "./$1.diff" )
+ printf "\n=== sha256sum should be:\n${bold}$csb_patcher_sha256sum_correct${bend}\n"
+ if [ "$csb_patcher_sha256sum_my" = "$csb_patcher_sha256sum_correct" ] ; then
+ printf "^^^ this is correct, "
+ csb_patcher_patch_title=$( grepper "Subject" "./$1.diff" )
+ csb_patcher_patch_title=${csb_patcher_patch_title#?????????????????}
+ if [ "$1" = "dgpu" ] ; then
+ printf "will extract a ${bold}$7$1${bend} patch now...\n"
+ rm -f "./sha256sums_$1_correct.txt"
+ rm -f "./"*"_$1_patches.sh"
+ patch -p1 < "./$1.diff"
+ chmod +x "./"*"_$1_patches.sh"
+ "./get_$1_patches.sh"
+ if ! "./check_$1_patches.sh" ; then
+ printf "%31s\n" "$7$1 - FAILURE_3" >> "$6"
+ csb_printer "$6"
+ exit 1
+ fi
+ else
+ printf "${bold}$7$1${bend} patch could be applied now...\n"
+ fi
+ if [ "$1" = "dgpu" ] || [ "$1" = "atombios" ] || \
+ [ "$1" = "tint" ] || [ "$1" = "seabios" ] ; then
+ printf "\n\n${bgreen}[PATCH]${bend} $csb_patcher_patch_title\n\n"
+ if ! grepcheck "how to submit coreboot changes" ./MAINTAINERS ; then
+ printf "\n${byellow}WARNING${bend}: not sure if I am inside the coreboot directory,"
+ printf "\n trying to add a ${bold}$1${bend} set from here - could fail.\n\n"
+ fi
+ if [ -f "./.$1" ] ; then
+ printf "\n${byellow}WARNING${bend}: found a '.$1' hidden file at the current directory,"
+ printf "\n maybe you have applied this patch already.\n\n"
+ fi
+ if yesno "Apply a ${bold}$7$1${bend} patch now?" "" ; then
+ if [ "$1" = "dgpu" ] ; then
+ "./apply_$1_patches.sh"
+ else
+ if [ "$1" = "atombios" ] ; then
+ rm -f "./sha256sums_$1_correct.txt"
+ rm -f "./"*"_$1_roms.sh"
+ rm -f "./pci1002\,"*".rom"
+ rm -f "./pci1002\,"*".rom.txt"
+ fi
+ if [ "$1" = "tint" ] ; then
+ rm -f "./payloads/external/tint/tint.sh"
+ rm -f "./payloads/external/tint/"*"_core.sh"
+ rm -f "./payloads/external/tint/tint-0.04-nmu1_libpayload.patch"
+ fi
+ if [ "$1" = "seabios" ] ; then
+ rm -f "./payloads/external/SeaBIOS/"*".patch"
+ fi
+ patch -p1 < "./$1.diff"
+ if [ "$1" = "atombios" ] ; then
+ chmod +x "./"*"_$1_roms.sh"
+ "./extract_$1_roms.sh"
+ printf "\n"
+ if ! "./check_$1_roms.sh" ; then
+ printf "%31s\n" "$7$1 - FAILURE_3" >> "$6"
+ csb_printer "$6"
+ exit 1
+ fi
+ fi
+ if [ "$1" = "tint" ] ; then
+ chmod +x "./payloads/external/tint/"*"_core.sh"
+ fi
+ fi
+ touch ".$1"
+ printf "%25s\n" "$7$1 - YES" >> "$6"
+ if [ "$1" = "atombios" ] ; then
+ encontinue
+ fi
+ else
+ printf "%24s\n" "$7$1 - NO" >> "$6"
+ printf "\n${bold}You can apply it later by running:${bend}"
+ if [ "$1" = "dgpu" ] ; then
+ printf "\n${bold} ./apply_$1_patches.sh${bend}\n"
+ else
+ printf "\n${bold} patch -p1 < ./$1.diff${bend}\n"
+ fi
+ encontinue
+ fi
+ fi
+ if checker "$1" "config" ; then
+ rm -f "./configs/$1_"*
+ patch -p1 < "./$1.diff"
+ printf "\n\n${bgreen}[PATCH]${bend} $csb_patcher_patch_title\n\n"
+ ls "./configs" > "./.csb_configs"
+ csb_patcher_config_name=$( grepper "$1" "./.csb_configs" )
+ rm -f "./.csb_configs"
+ printf "\n${bold}$csb_patcher_config_name could now be found at ./configs/${bend}"
+ printf "\n${bold}To use it, it should be copied to '.config' of your ./coreboot directory.${bend}\n\n"
+ if [ -f "./.config" ] ; then
+ printf "\n${byellow}WARNING${bend}: copying it to ./.config will overwrite your current '.config'\n\n"
+ fi
+ if yesno "Copy it to ./.config now?" "" ; then
+ copier "./configs/$csb_patcher_config_name" "./.config"
+ printf "\n"
+ printf "%25s\n" "$7$1 - YES" >> "$6"
+ if yesno "Configure this ./.config now?" "" ; then
+ csb_configurer "./.config"
+ else
+ printf "\n${bold}You can configure it later by running:${bend}"
+ printf "\n${bold} ./csb_patcher.sh config${bend}\n\n"
+ fi
+ else
+ printf "%24s\n" "$7$1 - NO" >> "$6"
+ printf "\n${bold}You can copy it later by running:${bend}"
+ printf "\n${bold} cp ./configs/$csb_patcher_config_name ./.config${bend}\n"
+ fi
+ printf "\n${byellow}WARNING${bend}: important README at the beginning of ./$1.diff\n"
+ encontinue
+ fi
+ printf "\n\n"
+ return 0
+ else
+ printf "${bold}^^^ ! MISMATCH for a $7$1 patch ! Check sha256sum manually: sha256sum ./$1.diff${bend}\n"
+ printf "%31s\n" "$7$1 - FAILURE_2" >> "$6"
+ csb_printer "$6"
+ exit 1
+ fi
+}
+
+#
+# Conveniently and securely gets, checks SHA256 and applies my collection of unofficial patches.
+# $1 - filepath where to save a csb_patcher_log which will be printed later
+#
+csb_mass_patcher () {
+###
+### https://review.coreboot.org/c/coreboot/+/31929
+### G505S dGPU support: scripts for applying the unofficial (not-merged-yet) patches
+###
+ csb_patcher "dgpu" "31929" "13" "ed0c44f" "eb461931a1f34a8263405138eb1bf8d32a1f460026449c9ec1a9b9e7d8383f1c" "$1" "G505S "
+###
+### https://review.coreboot.org/c/coreboot/+/31944
+### G505S AtomBIOS ROMs: known good binaries with a script to check their SHA256
+###
+ csb_patcher "atombios" "31944" "6" "78a8454" "9a8efff284bbdb81d5b912ccc8279162553e04673bde53e5288ba4bed0e4bc3d" "$1" "AMD "
+###
+### https://review.coreboot.org/c/coreboot/+/23856
+### tint: introduce the new tint build system with checksum verification
+###
+ csb_patcher "tint" "23856" "15" "14630b6" "7b9719f675d83750c7d4fb21b3abcbf1758ac6d1db20a9e8ef0db22f15761317" "$1" ""
+###
+### https://review.coreboot.org/c/coreboot/+/32351
+### SeaBIOS patches: advanced_bootmenu, multiple_floppies, writeprotected_usb
+###
+ csb_patcher "seabios" "32351" "5" "4a9c3cd" "58348b0514446856d07078af443ac8a24cd3be8178290e7361a48a86d213a43b" "$1" ""
+###
+### https://review.coreboot.org/c/coreboot/+/32352
+### configs: add Lenovo G505S sample configuration (use with dGPU patches)
+###
+csb_patcher "config.lenovo_g505s" "32352" "12" "348d8ce" "5b3b663b3afe3fe5729be2632201f3665e75ed3848996901322d3528ed6dd897" "$1" ""
+
+ return 0
+}
+
+# Prints a usage info for this ./csb_patcher.sh script.
+csb_usage () {
+ printf "${bold}===============${bend} ${bgreen}USAGE${bend} ${bold}================${bend}\n\n"
+ printf "${bold}./csb_patcher.sh${bend}\n"
+ printf " patch your coreboot source code\n\n"
+ printf "${bold}./csb_patcher.sh${bend} ${byellow}help${bend} ${bold}|${bend} ${byellow}usage${bend}\n"
+ printf " print this usage info\n\n"
+ printf "${bold}==================== Before building :${bend}\n\n"
+ printf "${bold}./csb_patcher.sh ${byellow}config${bend}\n"
+ printf " configure some popular options\n\n"
+ printf "${bold}==================== After building :${bend}\n\n"
+ printf "${bold}./csb_patcher.sh ${byellow}atom${bend}\n"
+ printf " add the AtomBIOS to coreboot.rom\n\n"
+ printf "${bold}./csb_patcher.sh ${byellow}flop${bend}\n"
+ printf " add the floppies to coreboot.rom\n\n"
+ printf "${bold}./csb_patcher.sh ${byellow}atomflop${bend}\n"
+ printf " both AtomBIOS VGA ROMs and floppies\n\n"
+ printf "${bold}./csb_patcher.sh${bend} ${byellow}print${bend}\n"
+ printf " print a ./.csb_patcher log\n\n"
+ return 0
+}
+
+#
+# MAIN PART OF A CSB_PATCHER SCRIPT
+#
+
+if [ -z "$1" ] ; then
+ csb_patcher_log="./.csb_patcher"
+ rm -f "$csb_patcher_log"
+ if ! command_exists "wget" || \
+ ! command_exists "unzip" || \
+ ! command_exists "sha256sum" || \
+ ! command_exists "patch" ; then
+ exit 1
+ fi
+ printf '\n\n' >> "$csb_patcher_log"
+ printf ' \\\\!//\n' >> "$csb_patcher_log"
+ printf ' (o o)\n' >> "$csb_patcher_log"
+ printf ' oOOo-(_)-oOOo\n' >> "$csb_patcher_log"
+ printf 'Hi! I am coreboot and SeaBIOS patcher\n' >> "$csb_patcher_log"
+ printf 'Please send your feedback to\n' >> "$csb_patcher_log"
+ printf ' Mike Banon <mikebdp2(a)gmail.com>\n' >> "$csb_patcher_log"
+ csb_printer "$csb_patcher_log"
+ encontinue
+ printf '\n=== CSB_PATCHER LOG. Patches applied?\n' >> "$csb_patcher_log"
+
+ csb_mass_patcher "$csb_patcher_log"
+
+ if yesno "Download a ${bold}floppies${bend} collection?" "" ; then
+ floppy_mass_downloader
+ printf "%25s\n" "floppies - YES" >> "$csb_patcher_log"
+ else
+ printf "\n"
+ printf "%24s\n" "floppies - NO" >> "$csb_patcher_log"
+ fi
+
+ printf '==================== Bad files found?\n' >> "$csb_patcher_log"
+ csb_finder "orig" "$csb_patcher_log" "applied correctly although at slightly different lines, can ignore it."
+ csb_finder "rej" "$csb_patcher_log" "perhaps failed to apply, could result in a broken build! ${bred}Please report${bend}"
+
+ printf '\n' >> "$csb_patcher_log"
+ csb_printer "$csb_patcher_log"
+ csb_usage
+else
+ case "$1" in
+ *"print"*)
+ csb_patcher_log="./.csb_patcher"
+ csb_printer "$csb_patcher_log"
+ ;;
+ *"config"*)
+ csb_configurer "./.config"
+ ;;
+ *"atom"*|*"flop"*)
+ if ! command_exists "wget" || \
+ ! command_exists "unzip" || \
+ ! command_exists "sha256sum" ; then
+ exit 1
+ fi
+ cbfs_mass_adder "$1" "./build/cbfstool" "./build/coreboot.rom" "./build/coreflop.rom"
+ ;;
+ *"help"*|*"usage"*)
+ printf "\n"
+ csb_usage
+ ;;
+ *)
+ printf "\n${bred}ERROR${bend}: unknown argument ${bold}$1${bend} !\n\n"
+ csb_usage
+ exit 1
+ ;;
+ esac
+fi
+
+exit 0
+
--
To view, visit https://review.coreboot.org/c/coreboot/+/33509
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I66f4f2865ac63ce0f2615669c7a3abd70a397e49
Gerrit-Change-Number: 33509
Gerrit-PatchSet: 1
Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com>
Gerrit-MessageType: newchange
1 week, 4 days
- 3
- 67
Change in ...coreboot[master]: configs: add ASUS AM1I-A sample configuration
by Mike Banon (Code Review)
Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33800
Change subject: configs: add ASUS AM1I-A sample configuration
......................................................................
configs: add ASUS AM1I-A sample configuration
You can use this .config as the base configuration for your AM1I-A by saving it
to ./coreboot/.config - however, you may want to change some of its' configs!
If you are using a SSD - you may want to change the "CONFIG_HUDSON_SATA_MODE"
from "0: NATIVE" to "2: AHCI". In addition, I have disabled Intel WiFi adapter
at my .config to save some space ( CONFIG_DRIVERS_INTEL_WIFI is not set ).
If you have any questions/suggestions regarding this .config, please contact me.
Signed-off-by: Mike Banon <mikebdp2(a)gmail.com>
Change-Id: Ide7529762813944b4f91b2ee8b3ef327b5daffc4
---
A configs/config.asus_am1i-a
1 file changed, 789 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/33800/1
diff --git a/configs/config.asus_am1i-a b/configs/config.asus_am1i-a
new file mode 100644
index 0000000..0660c44
--- /dev/null
+++ b/configs/config.asus_am1i-a
@@ -0,0 +1,789 @@
+#########
+###
+### ./coreboot/.config for ASUS AM1I-A - 26 Jun 2019
+###
+#########
+#
+# Automatically generated file; DO NOT EDIT.
+# coreboot configuration
+#
+
+#
+# General setup
+#
+CONFIG_COREBOOT_BUILD=y
+CONFIG_LOCALVERSION=""
+CONFIG_CBFS_PREFIX="fallback"
+CONFIG_COMPILER_GCC=y
+# CONFIG_COMPILER_LLVM_CLANG is not set
+# CONFIG_ANY_TOOLCHAIN is not set
+# CONFIG_CCACHE is not set
+# CONFIG_FMD_GENPARSER is not set
+# CONFIG_UTIL_GENPARSER is not set
+CONFIG_USE_OPTION_TABLE=y
+# CONFIG_STATIC_OPTION_TABLE is not set
+CONFIG_COMPRESS_RAMSTAGE=y
+CONFIG_INCLUDE_CONFIG_FILE=y
+CONFIG_COLLECT_TIMESTAMPS=y
+# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
+# CONFIG_USE_BLOBS is not set
+# CONFIG_COVERAGE is not set
+# CONFIG_UBSAN is not set
+# CONFIG_NO_RELOCATABLE_RAMSTAGE is not set
+CONFIG_RELOCATABLE_RAMSTAGE=y
+# CONFIG_UPDATE_IMAGE is not set
+# CONFIG_BOOTSPLASH_IMAGE is not set
+
+#
+# Mainboard
+#
+
+#
+# Important: Run 'make distclean' before switching boards
+#
+# CONFIG_VENDOR_ADI is not set
+# CONFIG_VENDOR_ADLINK is not set
+# CONFIG_VENDOR_ADVANSUS is not set
+# CONFIG_VENDOR_AMD is not set
+# CONFIG_VENDOR_AOPEN is not set
+# CONFIG_VENDOR_APPLE is not set
+# CONFIG_VENDOR_ASROCK is not set
+CONFIG_VENDOR_ASUS=y
+# CONFIG_VENDOR_AVALUE is not set
+# CONFIG_VENDOR_BAP is not set
+# CONFIG_VENDOR_BIOSTAR is not set
+# CONFIG_VENDOR_CAVIUM is not set
+# CONFIG_VENDOR_COMPULAB is not set
+# CONFIG_VENDOR_CUBIETECH is not set
+# CONFIG_VENDOR_ELMEX is not set
+# CONFIG_VENDOR_EMULATION is not set
+# CONFIG_VENDOR_ESD is not set
+# CONFIG_VENDOR_FACEBOOK is not set
+# CONFIG_VENDOR_FOXCONN is not set
+# CONFIG_VENDOR_GETAC is not set
+# CONFIG_VENDOR_GIGABYTE is not set
+# CONFIG_VENDOR_GIZMOSPHERE is not set
+# CONFIG_VENDOR_GOOGLE is not set
+# CONFIG_VENDOR_HP is not set
+# CONFIG_VENDOR_IBASE is not set
+# CONFIG_VENDOR_IEI is not set
+# CONFIG_VENDOR_INTEL is not set
+# CONFIG_VENDOR_JETWAY is not set
+# CONFIG_VENDOR_KONTRON is not set
+# CONFIG_VENDOR_LENOVO is not set
+# CONFIG_VENDOR_LIPPERT is not set
+# CONFIG_VENDOR_MSI is not set
+# CONFIG_VENDOR_OCP is not set
+# CONFIG_VENDOR_OPENCELLULAR is not set
+# CONFIG_VENDOR_PACKARDBELL is not set
+# CONFIG_VENDOR_PCENGINES is not set
+# CONFIG_VENDOR_PURISM is not set
+# CONFIG_VENDOR_RODA is not set
+# CONFIG_VENDOR_SAMSUNG is not set
+# CONFIG_VENDOR_SAPPHIRE is not set
+# CONFIG_VENDOR_SCALEWAY is not set
+# CONFIG_VENDOR_SIEMENS is not set
+# CONFIG_VENDOR_SIFIVE is not set
+# CONFIG_VENDOR_SUPERMICRO is not set
+# CONFIG_VENDOR_TI is not set
+# CONFIG_VENDOR_TYAN is not set
+# CONFIG_VENDOR_UP is not set
+# CONFIG_VENDOR_VIA is not set
+CONFIG_BOARD_SPECIFIC_OPTIONS=y
+CONFIG_MAINBOARD_DIR="asus/am1i-a"
+CONFIG_MAINBOARD_PART_NUMBER="AM1I-A"
+CONFIG_MAX_CPUS=4
+CONFIG_CBFS_SIZE=0x800000
+CONFIG_UART_FOR_CONSOLE=0
+CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/config_seabios"
+CONFIG_MAINBOARD_VENDOR="ASUS"
+CONFIG_HW_MEM_HOLE_SIZEK=0x200000
+CONFIG_IRQ_SLOT_COUNT=9
+CONFIG_VGA_BIOS_ID="1002,9830"
+CONFIG_ONBOARD_VGA_IS_PRIMARY=y
+# CONFIG_HUDSON_LEGACY_FREE is not set
+CONFIG_DIMM_SPD_SIZE=256
+CONFIG_VGA_BIOS=y
+CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
+CONFIG_AZ_PIN=0xaa
+CONFIG_VGA_BIOS_FILE="pci1002,9830.rom"
+CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000
+CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="ASUS"
+CONFIG_DEVICETREE="devicetree.cb"
+CONFIG_BOARD_ASUS_AM1I_A=y
+# CONFIG_BOARD_ASUS_F2A85_M is not set
+# CONFIG_BOARD_ASUS_F2A85_M_PRO is not set
+# CONFIG_BOARD_ASUS_F2A85_M_LE is not set
+# CONFIG_BOARD_ASUS_H61M_CS is not set
+# CONFIG_BOARD_ASUS_KCMA_D8 is not set
+# CONFIG_BOARD_ASUS_KFSN4_DRE is not set
+# CONFIG_BOARD_ASUS_KGPE_D16 is not set
+# CONFIG_BOARD_ASUS_M4A78_EM is not set
+# CONFIG_BOARD_ASUS_M4A785M is not set
+# CONFIG_BOARD_ASUS_M4A785TM is not set
+# CONFIG_BOARD_ASUS_M5A88_V is not set
+# CONFIG_BOARD_ASUS_MAXIMUS_IV_GENE_Z is not set
+# CONFIG_BOARD_ASUS_P2B_D is not set
+# CONFIG_BOARD_ASUS_P2B_DS is not set
+# CONFIG_BOARD_ASUS_P2B_F is not set
+# CONFIG_BOARD_ASUS_P2B_LS is not set
+# CONFIG_BOARD_ASUS_P2B is not set
+# CONFIG_BOARD_ASUS_P3B_F is not set
+# CONFIG_BOARD_ASUS_P5GC_MX is not set
+# CONFIG_BOARD_ASUS_P5QC is not set
+# CONFIG_BOARD_ASUS_P5Q_PRO is not set
+# CONFIG_BOARD_ASUS_P5QL_PRO is not set
+# CONFIG_BOARD_ASUS_P5QPL_AM is not set
+# CONFIG_BOARD_ASUS_P5G41T_M_LX is not set
+# CONFIG_BOARD_ASUS_P8H61_M_LX is not set
+# CONFIG_BOARD_ASUS_P8H61_M_PRO is not set
+# CONFIG_HUDSON_IMC_FWM is not set
+# CONFIG_HUDSON_XHCI_FWM is not set
+CONFIG_DCACHE_RAM_BASE=0x30000
+CONFIG_DCACHE_RAM_SIZE=0x10000
+CONFIG_MAX_REBOOT_CNT=3
+CONFIG_OVERRIDE_DEVICETREE=""
+CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
+CONFIG_FMDFILE=""
+CONFIG_MMCONF_BASE_ADDRESS=0xF8000000
+CONFIG_DRIVERS_UART_8250IO=y
+# CONFIG_VBOOT is not set
+CONFIG_DIMM_MAX=4
+CONFIG_TPM_PIRQ=0x0
+CONFIG_TTYS0_LCS=3
+CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="AM1I-A"
+CONFIG_CPU_ADDR_BITS=40
+# CONFIG_USBDEBUG is not set
+CONFIG_MAINBOARD_VERSION="1.0"
+# CONFIG_DRIVERS_PS2_KEYBOARD is not set
+CONFIG_PCIEXP_L1_SUB_STATE=y
+CONFIG_SMBIOS_ENCLOSURE_TYPE=0x03
+CONFIG_HEAP_SIZE=0xc0000
+CONFIG_BOARD_ROMSIZE_KB_8192=y
+# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
+CONFIG_COREBOOT_ROMSIZE_KB_8192=y
+# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
+CONFIG_COREBOOT_ROMSIZE_KB=8192
+CONFIG_ROM_SIZE=0x800000
+# CONFIG_SYSTEM_TYPE_LAPTOP is not set
+# CONFIG_SYSTEM_TYPE_TABLET is not set
+# CONFIG_SYSTEM_TYPE_DETACHABLE is not set
+# CONFIG_SYSTEM_TYPE_CONVERTIBLE is not set
+# CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set
+
+#
+# Chipset
+#
+
+#
+# SoC
+#
+CONFIG_UDELAY_LAPIC_FIXED_FSB=200
+CONFIG_MMCONF_BUS_NUMBER=64
+CONFIG_S3_VGA_ROM_RUN=y
+CONFIG_EHCI_BAR=0xfef00000
+CONFIG_ACPI_CPU_STRING="\\_PR.CP%02d"
+# CONFIG_SOC_CAVIUM_CN81XX is not set
+CONFIG_ARCH_ARMV8_EXTENSION=0
+CONFIG_STACK_SIZE=0x1000
+# CONFIG_SOC_CAVIUM_COMMON is not set
+# CONFIG_SOC_INTEL_GLK is not set
+CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
+CONFIG_ROMSTAGE_ADDR=0x2000000
+CONFIG_VERSTAGE_ADDR=0x2000000
+CONFIG_PCIEXP_ASPM=y
+CONFIG_PCIEXP_COMMON_CLOCK=y
+CONFIG_PCIEXP_CLK_PM=y
+CONFIG_TTYS0_BASE=0x3f8
+# CONFIG_SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS is not set
+# CONFIG_SOC_INTEL_COFFEELAKE is not set
+# CONFIG_SOC_INTEL_WHISKEYLAKE is not set
+# CONFIG_SOC_INTEL_COMETLAKE is not set
+# CONFIG_SOC_INTEL_CANNONLAKE_PCH_H is not set
+CONFIG_UART_PCI_ADDR=0x0
+# CONFIG_SOC_MEDIATEK_MT8173 is not set
+# CONFIG_SOC_MEDIATEK_MT8183 is not set
+# CONFIG_SOC_NVIDIA_TEGRA124 is not set
+# CONFIG_SOC_NVIDIA_TEGRA210 is not set
+# CONFIG_SOC_QUALCOMM_COMMON is not set
+# CONFIG_SOC_QC_IPQ40XX is not set
+# CONFIG_SOC_QC_IPQ806X is not set
+# CONFIG_SOC_QUALCOMM_QCS405 is not set
+# CONFIG_SOC_QUALCOMM_SDM845 is not set
+# CONFIG_SOC_ROCKCHIP_RK3288 is not set
+# CONFIG_SOC_ROCKCHIP_RK3399 is not set
+# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set
+# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set
+# CONFIG_SOC_UCB_RISCV is not set
+
+#
+# CPU
+#
+# CONFIG_CPU_ALLWINNER_A10 is not set
+CONFIG_XIP_ROM_SIZE=0x100000
+CONFIG_NUM_IPI_STARTS=2
+CONFIG_CPU_AMD_AGESA=y
+# CONFIG_ENABLE_MRC_CACHE is not set
+CONFIG_S3_DATA_POS=0xFFFF0000
+CONFIG_S3_DATA_SIZE=32768
+CONFIG_CPU_AMD_AGESA_FAMILY16_KB=y
+CONFIG_FORCE_AM1_SOCKET_SUPPORT=y
+# CONFIG_CPU_AMD_PI is not set
+# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set
+# CONFIG_SSE2 is not set
+# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set
+# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set
+# CONFIG_CPU_TI_AM335X is not set
+# CONFIG_PARALLEL_CPU_INIT is not set
+# CONFIG_PARALLEL_MP is not set
+# CONFIG_UDELAY_IO is not set
+CONFIG_UDELAY_LAPIC=y
+CONFIG_LAPIC_MONOTONIC_TIMER=y
+# CONFIG_UDELAY_TSC is not set
+# CONFIG_UDELAY_TIMER2 is not set
+CONFIG_TSC_SYNC_LFENCE=y
+# CONFIG_TSC_SYNC_MFENCE is not set
+# CONFIG_NO_FIXED_XIP_ROM_SIZE is not set
+CONFIG_LOGICAL_CPUS=y
+# CONFIG_SMM_TSEG is not set
+# CONFIG_SMM_LAPIC_REMAP_MITIGATION is not set
+# CONFIG_SERIALIZED_SMM_INITIALIZATION is not set
+CONFIG_X86_AMD_FIXED_MTRRS=y
+# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set
+# CONFIG_SOC_SETS_MSRS is not set
+CONFIG_CACHE_AS_RAM=y
+CONFIG_NO_CAR_GLOBAL_MIGRATION=y
+CONFIG_SMP=y
+# CONFIG_SUPPORT_CPU_UCODE_IN_CBFS is not set
+# CONFIG_USES_MICROCODE_HEADER_FILES is not set
+
+#
+# Northbridge
+#
+CONFIG_NORTHBRIDGE_AMD_AGESA=y
+# CONFIG_CONSOLE_VGA_MULTI is not set
+CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY16_KB=y
+# CONFIG_NORTHBRIDGE_AMD_PI is not set
+CONFIG_MAX_PIRQ_LINKS=4
+
+#
+# Southbridge
+#
+CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE=y
+CONFIG_SOUTHBRIDGE_SPECIFIC_OPTIONS=y
+CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/amd/agesa/hudson/bootblock.c"
+# CONFIG_HUDSON_XHCI_ENABLE is not set
+# CONFIG_HUDSON_IMC_ENABLE is not set
+# CONFIG_HUDSON_GEC_FWM is not set
+CONFIG_HUDSON_SATA_MODE=0
+
+#
+# NATIVE
+#
+CONFIG_ACPI_ENABLE_THERMAL_ZONE=y
+# CONFIG_AMD_SB_CIMX is not set
+# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set
+# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set
+# CONFIG_SOUTHBRIDGE_INTEL_COMMON is not set
+# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set
+# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS is not set
+# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI is not set
+# CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN is not set
+# CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ is not set
+# CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN is not set
+# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM is not set
+# CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE is not set
+
+#
+# Super I/O
+#
+# CONFIG_SUPERIO_ASPEED_AST2400 is not set
+# CONFIG_SUPERIO_ASPEED_COMMON_PRE_RAM is not set
+CONFIG_SUPERIO_ITE_COMMON_PRE_RAM=y
+CONFIG_SUPERIO_ITE_ENV_CTRL=y
+CONFIG_SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG=y
+CONFIG_SUPERIO_ITE_ENV_CTRL_8BIT_PWM=y
+CONFIG_SUPERIO_ITE_ENV_CTRL_PWM_FREQ2=y
+CONFIG_SUPERIO_ITE_IT8623E=y
+
+#
+# Embedded Controllers
+#
+# CONFIG_EC_GOOGLE_WILCO is not set
+CONFIG_EC_BASE_ACPI_DATA=0x930
+CONFIG_EC_BASE_ACPI_COMMAND=0x934
+CONFIG_EC_BASE_HOST_DATA=0x940
+CONFIG_EC_BASE_HOST_COMMAND=0x944
+CONFIG_EC_BASE_PACKET=0x950
+CONFIG_SEABIOS_PS2_TIMEOUT=0
+
+#
+# AMD Platform Initialization
+#
+# CONFIG_CPU_AMD_AGESA_BINARY_PI is not set
+CONFIG_CPU_AMD_AGESA_OPENSOURCE=y
+CONFIG_AGESA_EXTRA_TIMESTAMPS=y
+# CONFIG_CAVIUM_BDK is not set
+# CONFIG_MAINBOARD_HAS_CHROMEOS is not set
+# CONFIG_GOOGLE_SMBIOS_MAINBOARD_VERSION is not set
+# CONFIG_UEFI_2_4_BINDING is not set
+# CONFIG_UDK_2015_BINDING is not set
+# CONFIG_UDK_2017_BINDING is not set
+CONFIG_UDK_2013_VERSION=2013
+CONFIG_UDK_2015_VERSION=2015
+CONFIG_UDK_2017_VERSION=2017
+CONFIG_UDK_VERSION=2013
+# CONFIG_USE_SIEMENS_HWILIB is not set
+# CONFIG_ARCH_ARM is not set
+# CONFIG_ARCH_BOOTBLOCK_ARM is not set
+# CONFIG_ARCH_VERSTAGE_ARM is not set
+# CONFIG_ARCH_ROMSTAGE_ARM is not set
+# CONFIG_ARCH_RAMSTAGE_ARM is not set
+# CONFIG_ARCH_BOOTBLOCK_ARMV4 is not set
+# CONFIG_ARCH_VERSTAGE_ARMV4 is not set
+# CONFIG_ARCH_ROMSTAGE_ARMV4 is not set
+# CONFIG_ARCH_RAMSTAGE_ARMV4 is not set
+# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set
+# CONFIG_ARCH_VERSTAGE_ARMV7 is not set
+# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set
+# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set
+# CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set
+# CONFIG_ARCH_VERSTAGE_ARMV7_M is not set
+# CONFIG_ARCH_BOOTBLOCK_ARMV7_R is not set
+# CONFIG_ARCH_VERSTAGE_ARMV7_R is not set
+# CONFIG_ARCH_ROMSTAGE_ARMV7_R is not set
+# CONFIG_ARCH_RAMSTAGE_ARMV7_R is not set
+# CONFIG_ARM_LPAE is not set
+# CONFIG_ARCH_ARM64 is not set
+# CONFIG_ARCH_BOOTBLOCK_ARM64 is not set
+# CONFIG_ARCH_VERSTAGE_ARM64 is not set
+# CONFIG_ARCH_ROMSTAGE_ARM64 is not set
+# CONFIG_ARCH_RAMSTAGE_ARM64 is not set
+# CONFIG_ARCH_BOOTBLOCK_ARMV8_64 is not set
+# CONFIG_ARCH_VERSTAGE_ARMV8_64 is not set
+# CONFIG_ARCH_ROMSTAGE_ARMV8_64 is not set
+# CONFIG_ARCH_RAMSTAGE_ARMV8_64 is not set
+# CONFIG_ARM64_USE_ARCH_TIMER is not set
+# CONFIG_ARM64_A53_ERRATUM_843419 is not set
+# CONFIG_ARCH_MIPS is not set
+# CONFIG_ARCH_BOOTBLOCK_MIPS is not set
+# CONFIG_ARCH_VERSTAGE_MIPS is not set
+# CONFIG_ARCH_ROMSTAGE_MIPS is not set
+# CONFIG_ARCH_RAMSTAGE_MIPS is not set
+# CONFIG_ARCH_PPC64 is not set
+# CONFIG_ARCH_BOOTBLOCK_PPC64 is not set
+# CONFIG_ARCH_VERSTAGE_PPC64 is not set
+# CONFIG_ARCH_ROMSTAGE_PPC64 is not set
+# CONFIG_ARCH_RAMSTAGE_PPC64 is not set
+# CONFIG_ARCH_RISCV is not set
+# CONFIG_ARCH_RISCV_M is not set
+# CONFIG_ARCH_RISCV_S is not set
+# CONFIG_ARCH_RISCV_U is not set
+# CONFIG_ARCH_RISCV_RV64 is not set
+# CONFIG_ARCH_RISCV_RV32 is not set
+# CONFIG_ARCH_RISCV_PMP is not set
+# CONFIG_ARCH_BOOTBLOCK_RISCV is not set
+# CONFIG_ARCH_VERSTAGE_RISCV is not set
+# CONFIG_ARCH_ROMSTAGE_RISCV is not set
+# CONFIG_ARCH_RAMSTAGE_RISCV is not set
+# CONFIG_RISCV_USE_ARCH_TIMER is not set
+CONFIG_ARCH_X86=y
+CONFIG_ARCH_BOOTBLOCK_X86_32=y
+CONFIG_ARCH_VERSTAGE_X86_32=y
+CONFIG_ARCH_ROMSTAGE_X86_32=y
+CONFIG_ARCH_POSTCAR_X86_32=y
+CONFIG_ARCH_RAMSTAGE_X86_32=y
+# CONFIG_ARCH_BOOTBLOCK_X86_64 is not set
+# CONFIG_ARCH_VERSTAGE_X86_64 is not set
+# CONFIG_ARCH_ROMSTAGE_X86_64 is not set
+# CONFIG_ARCH_POSTCAR_X86_64 is not set
+# CONFIG_ARCH_RAMSTAGE_X86_64 is not set
+# CONFIG_USE_MARCH_586 is not set
+# CONFIG_AP_IN_SIPI_WAIT is not set
+# CONFIG_SIPI_VECTOR_IN_ROM is not set
+CONFIG_RAMBASE=0xe00000
+CONFIG_RAMTOP=0x1000000
+CONFIG_CBMEM_TOP_BACKUP=y
+# CONFIG_EARLY_EBDA_INIT is not set
+CONFIG_PC80_SYSTEM=y
+# CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set
+# CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set
+CONFIG_HAVE_CMOS_DEFAULT=y
+CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
+CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y
+# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set
+# CONFIG_HPET_ADDRESS_OVERRIDE is not set
+CONFIG_HPET_ADDRESS=0xfed00000
+CONFIG_ID_SECTION_OFFSET=0x80
+CONFIG_POSTCAR_STAGE=y
+# CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set
+# CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set
+CONFIG_BOOTBLOCK_SIMPLE=y
+# CONFIG_BOOTBLOCK_NORMAL is not set
+CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c"
+CONFIG_ACPI_HAVE_PCAT_8259=y
+# CONFIG_COLLECT_TIMESTAMPS_NO_TSC is not set
+CONFIG_COLLECT_TIMESTAMPS_TSC=y
+# CONFIG_PAGING_IN_CACHE_AS_RAM is not set
+# CONFIG_IDT_IN_EVERY_STAGE is not set
+CONFIG_HAVE_CF9_RESET=y
+CONFIG_HAVE_CF9_RESET_PREPARE=y
+
+#
+# Devices
+#
+CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
+CONFIG_HAVE_VBE_LINEAR_FRAMEBUFFER=y
+# CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT is not set
+# CONFIG_MAINBOARD_HAS_LIBGFXINIT is not set
+CONFIG_VGA_ROM_RUN=y
+# CONFIG_NO_GFX_INIT is not set
+# CONFIG_ALWAYS_LOAD_OPROM is not set
+CONFIG_ON_DEVICE_ROM_LOAD=y
+# CONFIG_PCI_OPTION_ROM_RUN_REALMODE is not set
+CONFIG_PCI_OPTION_ROM_RUN_YABEL=y
+CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES=y
+# CONFIG_YABEL_PCI_FAKE_WRITING_OTHER_DEVICES_CONFIG is not set
+CONFIG_YABEL_VIRTMEM_LOCATION=0x1000000
+CONFIG_YABEL_DIRECTHW=y
+
+#
+# Display
+#
+CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
+# CONFIG_FRAMEBUFFER_VESA_MODE_100 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_101 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_102 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_103 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_104 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_105 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_106 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_107 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_108 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_109 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_10A is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_10B is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_10C is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_10D is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_10E is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_10F is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_110 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_111 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_112 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_113 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_114 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_115 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_116 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_117 is not set
+CONFIG_FRAMEBUFFER_VESA_MODE_118=y
+# CONFIG_FRAMEBUFFER_VESA_MODE_119 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_11A is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_11B is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_USER is not set
+CONFIG_FRAMEBUFFER_VESA_MODE=0x118
+CONFIG_BOOTSPLASH=y
+# CONFIG_VGA_TEXT_FRAMEBUFFER is not set
+CONFIG_VBE_LINEAR_FRAMEBUFFER=y
+CONFIG_LINEAR_FRAMEBUFFER=y
+# CONFIG_SMBUS_HAS_AUX_CHANNELS is not set
+CONFIG_PCI=y
+# CONFIG_NO_MMCONF_SUPPORT is not set
+CONFIG_MMCONF_SUPPORT=y
+# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set
+CONFIG_PCIX_PLUGIN_SUPPORT=y
+CONFIG_CARDBUS_PLUGIN_SUPPORT=y
+# CONFIG_AZALIA_PLUGIN_SUPPORT is not set
+CONFIG_PCIEXP_PLUGIN_SUPPORT=y
+# CONFIG_EARLY_PCI_BRIDGE is not set
+CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
+CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
+# CONFIG_VGA_BIOS_DGPU is not set
+# CONFIG_SOFTWARE_I2C is not set
+
+#
+# Generic Drivers
+#
+# CONFIG_DRIVERS_AS3722_RTC is not set
+# CONFIG_GIC is not set
+# CONFIG_IPMI_KCS is not set
+# CONFIG_DRIVERS_LENOVO_WACOM is not set
+# CONFIG_RT8168_GET_MAC_FROM_VPD is not set
+# CONFIG_RT8168_SET_LED_MODE is not set
+# CONFIG_SMMSTORE_IN_CBFS is not set
+CONFIG_SPI_FLASH=y
+CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
+# CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY is not set
+# CONFIG_SPI_FLASH_NO_FAST_READ is not set
+CONFIG_SPI_FLASH_ADESTO=y
+CONFIG_SPI_FLASH_AMIC=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
+# CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B is not set
+# CONFIG_SPI_FLASH_HAS_VOLATILE_GROUP is not set
+# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set
+CONFIG_DRIVERS_UART=y
+# CONFIG_DRIVERS_UART_8250IO_SKIP_INIT is not set
+# CONFIG_NO_UART_ON_SUPERIO is not set
+# CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set
+# CONFIG_UART_OVERRIDE_REFCLK is not set
+# CONFIG_DRIVERS_UART_8250MEM is not set
+# CONFIG_DRIVERS_UART_8250MEM_32 is not set
+# CONFIG_HAVE_UART_SPECIAL is not set
+# CONFIG_DRIVERS_UART_OXPCIE is not set
+# CONFIG_DRIVERS_UART_PL011 is not set
+# CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set
+CONFIG_HAVE_USBDEBUG=y
+CONFIG_HAVE_USBDEBUG_OPTIONS=y
+# CONFIG_VPD is not set
+CONFIG_DRIVERS_AMD_PI=y
+# CONFIG_SMBIOS_PROVIDED_BY_MOBO is not set
+# CONFIG_DRIVERS_I2C_MAX98373 is not set
+# CONFIG_DRIVERS_I2C_MAX98927 is not set
+# CONFIG_DRIVERS_I2C_PCA9538 is not set
+# CONFIG_DRIVERS_I2C_PCF8523 is not set
+# CONFIG_DRIVERS_I2C_RT5663 is not set
+# CONFIG_DRIVERS_I2C_RTD2132 is not set
+# CONFIG_DRIVERS_I2C_RX6110SA is not set
+# CONFIG_DRIVERS_I2C_SX9310 is not set
+# CONFIG_MAINBOARD_HAS_I2C_TPM_ATMEL is not set
+# CONFIG_MAINBOARD_HAS_I2C_TPM_CR50 is not set
+# CONFIG_MAINBOARD_HAS_I2C_TPM_GENERIC is not set
+# CONFIG_PLATFORM_USES_FSP1_0 is not set
+# CONFIG_PLATFORM_USES_FSP2_0 is not set
+# CONFIG_PLATFORM_USES_FSP2_1 is not set
+# CONFIG_INTEL_DDI is not set
+# CONFIG_INTEL_EDID is not set
+# CONFIG_INTEL_INT15 is not set
+# CONFIG_INTEL_GMA_ACPI is not set
+# CONFIG_INTEL_GMA_SSC_ALTERNATE_REF is not set
+# CONFIG_INTEL_GMA_SWSMISCI is not set
+# CONFIG_DRIVER_INTEL_I210 is not set
+# CONFIG_DRIVERS_INTEL_MIPI_CAMERA is not set
+# CONFIG_DRIVERS_INTEL_WIFI is not set
+# CONFIG_USE_SAR is not set
+# CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS is not set
+# CONFIG_DRIVER_MAXIM_MAX77686 is not set
+# CONFIG_DRIVER_PARADE_PS8625 is not set
+# CONFIG_DRIVER_PARADE_PS8640 is not set
+CONFIG_DRIVERS_MC146818=y
+CONFIG_LPC_TPM=y
+CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000
+CONFIG_MAINBOARD_HAS_LPC_TPM=y
+# CONFIG_DRIVERS_RICOH_RCE822 is not set
+# CONFIG_DRIVER_SIEMENS_NC_FPGA is not set
+# CONFIG_NC_FPGA_NOTIFY_CB_READY is not set
+# CONFIG_DRIVERS_SIL_3114 is not set
+# CONFIG_MAINBOARD_HAS_SPI_TPM_CR50 is not set
+# CONFIG_DRIVER_TI_TPS65090 is not set
+# CONFIG_DRIVERS_TI_TPS65913 is not set
+# CONFIG_DRIVERS_TI_TPS65913_RTC is not set
+# CONFIG_DRIVERS_USB_ACPI is not set
+# CONFIG_DRIVER_XPOWERS_AXP209 is not set
+# CONFIG_COMMONLIB_STORAGE is not set
+
+#
+# Security
+#
+
+#
+# Verified Boot (vboot)
+#
+
+#
+# Trusted Platform Module
+#
+CONFIG_USER_NO_TPM=y
+# CONFIG_USER_TPM1 is not set
+# CONFIG_USER_TPM2 is not set
+# CONFIG_TPM_RDRESP_NEED_DELAY is not set
+# CONFIG_ACPI_SATA_GENERATOR is not set
+# CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES is not set
+# CONFIG_ACPI_AMD_HARDWARE_SLEEP_VALUES is not set
+# CONFIG_BOOT_DEVICE_NOT_SPI_FLASH is not set
+CONFIG_BOOT_DEVICE_SPI_FLASH=y
+CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
+# CONFIG_BOOT_DEVICE_SUPPORTS_WRITES is not set
+# CONFIG_RTC is not set
+
+#
+# Console
+#
+# CONFIG_POSTCAR_CONSOLE is not set
+CONFIG_SQUELCH_EARLY_SMP=y
+CONFIG_CONSOLE_SERIAL=y
+CONFIG_CONSOLE_CBMEM=y
+CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
+
+#
+# I/O mapped, 8250-compatible
+#
+
+#
+# Serial port base address = 0x3f8
+#
+# CONFIG_CONSOLE_SERIAL_921600 is not set
+# CONFIG_CONSOLE_SERIAL_460800 is not set
+# CONFIG_CONSOLE_SERIAL_230400 is not set
+CONFIG_CONSOLE_SERIAL_115200=y
+# CONFIG_CONSOLE_SERIAL_57600 is not set
+# CONFIG_CONSOLE_SERIAL_38400 is not set
+# CONFIG_CONSOLE_SERIAL_19200 is not set
+# CONFIG_CONSOLE_SERIAL_9600 is not set
+CONFIG_TTYS0_BAUD=115200
+# CONFIG_SPKMODEM is not set
+# CONFIG_CONSOLE_NE2K is not set
+CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
+# CONFIG_CONSOLE_SPI_FLASH is not set
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
+# CONFIG_NO_POST is not set
+# CONFIG_CMOS_POST is not set
+# CONFIG_CONSOLE_POST is not set
+CONFIG_POST_DEVICE=y
+CONFIG_POST_DEVICE_NONE=y
+# CONFIG_POST_DEVICE_LPC is not set
+# CONFIG_POST_DEVICE_PCI_PCIE is not set
+CONFIG_POST_IO=y
+CONFIG_POST_IO_PORT=0x80
+# CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set
+CONFIG_HWBASE_DEBUG_CB=y
+CONFIG_HAVE_ACPI_RESUME=y
+# CONFIG_ACPI_HUGE_LOWMEM_BACKUP is not set
+CONFIG_RESUME_PATH_SAME_AS_BOOT=y
+# CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set
+# CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set
+# CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set
+CONFIG_HAVE_MONOTONIC_TIMER=y
+# CONFIG_GENERIC_UDELAY is not set
+# CONFIG_TIMER_QUEUE is not set
+CONFIG_HAVE_OPTION_TABLE=y
+# CONFIG_PIRQ_ROUTE is not set
+# CONFIG_HAVE_SMI_HANDLER is not set
+# CONFIG_PCI_IO_CFG_EXT is not set
+CONFIG_IOAPIC=y
+# CONFIG_USE_WATCHDOG_ON_BOOT is not set
+CONFIG_GFXUMA=y
+CONFIG_HAVE_ACPI_TABLES=y
+CONFIG_HAVE_MP_TABLE=y
+CONFIG_HAVE_PIRQ_TABLE=y
+# CONFIG_COMMON_FADT is not set
+# CONFIG_ACPI_NHLT is not set
+
+#
+# System tables
+#
+CONFIG_GENERATE_MP_TABLE=y
+CONFIG_GENERATE_PIRQ_TABLE=y
+CONFIG_GENERATE_SMBIOS_TABLES=y
+
+#
+# Payload
+#
+# CONFIG_PAYLOAD_NONE is not set
+# CONFIG_PAYLOAD_ELF is not set
+# CONFIG_PAYLOAD_BAYOU is not set
+# CONFIG_PAYLOAD_FILO is not set
+# CONFIG_PAYLOAD_GRUB2 is not set
+# CONFIG_PAYLOAD_LINUXBOOT is not set
+CONFIG_PAYLOAD_SEABIOS=y
+# CONFIG_PAYLOAD_UBOOT is not set
+# CONFIG_PAYLOAD_YABITS is not set
+# CONFIG_PAYLOAD_LINUX is not set
+# CONFIG_PAYLOAD_TIANOCORE is not set
+CONFIG_PAYLOAD_FILE="payloads/external/SeaBIOS/seabios/out/bios.bin.elf"
+# CONFIG_SEABIOS_STABLE is not set
+CONFIG_SEABIOS_MASTER=y
+# CONFIG_SEABIOS_REVISION is not set
+# CONFIG_SEABIOS_THREAD_OPTIONROMS is not set
+CONFIG_SEABIOS_BOOTORDER_FILE=""
+# CONFIG_SEABIOS_ADD_SERCON_PORT_FILE is not set
+CONFIG_SEABIOS_DEBUG_LEVEL=-1
+
+#
+# Using default SeaBIOS log level
+#
+CONFIG_PAYLOAD_OPTIONS=""
+# CONFIG_PXE is not set
+CONFIG_COMPRESSED_PAYLOAD_LZMA=y
+# CONFIG_COMPRESSED_PAYLOAD_LZ4 is not set
+# CONFIG_PAYLOAD_IS_FLAT_BINARY is not set
+CONFIG_COMPRESS_SECONDARY_PAYLOAD=y
+
+#
+# Secondary Payloads
+#
+CONFIG_COREINFO_SECONDARY_PAYLOAD=y
+# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set
+# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set
+CONFIG_TINT_SECONDARY_PAYLOAD=y
+
+#
+# Debugging
+#
+
+#
+# CPU Debug Settings
+#
+
+#
+# General Debug Settings
+#
+# CONFIG_GDB_STUB is not set
+# CONFIG_FATAL_ASSERTS is not set
+# CONFIG_DEBUG_CBFS is not set
+# CONFIG_HAVE_DEBUG_RAM_SETUP is not set
+# CONFIG_DEBUG_PIRQ is not set
+# CONFIG_HAVE_DEBUG_SMBUS is not set
+# CONFIG_DEBUG_MALLOC is not set
+# CONFIG_DEBUG_ACPI is not set
+# CONFIG_DEBUG_CONSOLE_INIT is not set
+# CONFIG_X86EMU_DEBUG is not set
+# CONFIG_DEBUG_SPI_FLASH is not set
+# CONFIG_TRACE is not set
+# CONFIG_DEBUG_BOOT_STATE is not set
+# CONFIG_DEBUG_ADA_CODE is not set
+# CONFIG_HAVE_EM100_SUPPORT is not set
+CONFIG_NO_EDID_FILL_FB=y
+# CONFIG_ENABLE_APIC_EXT_ID is not set
+CONFIG_WARNINGS_ARE_ERRORS=y
+# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set
+# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set
+# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set
+# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set
+# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set
+# CONFIG_REG_SCRIPT is not set
+# CONFIG_NO_XIP_EARLY_STAGES is not set
+# CONFIG_EARLY_CBMEM_LIST is not set
+CONFIG_RELOCATABLE_MODULES=y
+CONFIG_BOOTBLOCK_CUSTOM=y
+CONFIG_HAVE_BOOTBLOCK=y
+CONFIG_HAVE_ROMSTAGE=y
+CONFIG_HAVE_POSTCAR=y
+CONFIG_HAVE_RAMSTAGE=y
+
--
To view, visit https://review.coreboot.org/c/coreboot/+/33800
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ide7529762813944b4f91b2ee8b3ef327b5daffc4
Gerrit-Change-Number: 33800
Gerrit-PatchSet: 1
Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com>
Gerrit-MessageType: newchange
1 week, 4 days
- 5
- 24
Change in ...coreboot[master]: configs: add Lenovo G505S sample configuration (use with dGPU patches)
by mikeb mikeb (Code Review)
Hello Mike Banon,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/32352
to review the following change.
Change subject: configs: add Lenovo G505S sample configuration (use with dGPU patches)
......................................................................
configs: add Lenovo G505S sample configuration (use with dGPU patches)
This sample .config could not be merged before the dGPU patches at CB:31929
(see https://review.coreboot.org/c/coreboot/+/31929 for more information).
I'm sharing it with you here partially for the archival purposes.
After you have installed the dGPU patches above, you can use this .config
as the base configuration for your G505S by saving it to ./coreboot/.config -
however, you may want to change some of its' configs! For example: it specifies
CONFIG_VGA_BIOS_DGPU_FILE="pci1002,6665.rom"
CONFIG_VGA_BIOS_DGPU_ID="1002,6665"
which is compatible with R5-M230 discrete GPU, but if your G505S has HD-8570M
discrete GPU instead - you will need to change these configs to ",6663" etc.
Or, if your G505S does not have a discrete GPU at all, please disable
CONFIG_MULTIPLE_VGA_ADAPTERS=y
and those DGPU configs will be disabled. Also, if you are using a SSD - you
may want to change the "CONFIG_HUDSON_SATA_MODE" from "0: NATIVE" to "2: AHCI".
In addition, I've disabled this WiFi adapter at my .config to save some space:
If you have any questions/suggestions regarding this .config, please contact me.
Signed-off-by: Mike Banon <mikebdp2(a)gmail.com>
Change-Id: I85f17395afca52ef690f24fcef746d74bb72aab7
---
A configs/config.lenovo_g505s_use_with_dgpu_patches
1 file changed, 746 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/32352/1
diff --git a/configs/config.lenovo_g505s_use_with_dgpu_patches b/configs/config.lenovo_g505s_use_with_dgpu_patches
new file mode 100644
index 0000000..5ff218f
--- /dev/null
+++ b/configs/config.lenovo_g505s_use_with_dgpu_patches
@@ -0,0 +1,746 @@
+#
+# ./coreboot/.config for Lenovo G505S - 17 April 2019
+#
+###
+#
+# Automatically generated file; DO NOT EDIT.
+# coreboot configuration
+#
+
+#
+# General setup
+#
+CONFIG_COREBOOT_BUILD=y
+CONFIG_LOCALVERSION=""
+CONFIG_CBFS_PREFIX="fallback"
+CONFIG_COMPILER_GCC=y
+# CONFIG_COMPILER_LLVM_CLANG is not set
+# CONFIG_ANY_TOOLCHAIN is not set
+# CONFIG_CCACHE is not set
+# CONFIG_FMD_GENPARSER is not set
+# CONFIG_UTIL_GENPARSER is not set
+# CONFIG_USE_OPTION_TABLE is not set
+CONFIG_COMPRESS_RAMSTAGE=y
+CONFIG_INCLUDE_CONFIG_FILE=y
+CONFIG_COLLECT_TIMESTAMPS=y
+# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
+# CONFIG_USE_BLOBS is not set
+# CONFIG_COVERAGE is not set
+# CONFIG_UBSAN is not set
+# CONFIG_NO_RELOCATABLE_RAMSTAGE is not set
+CONFIG_RELOCATABLE_RAMSTAGE=y
+# CONFIG_UPDATE_IMAGE is not set
+# CONFIG_BOOTSPLASH_IMAGE is not set
+
+#
+# Mainboard
+#
+
+#
+# Important: Run 'make distclean' before switching boards
+#
+# CONFIG_VENDOR_ADI is not set
+# CONFIG_VENDOR_ADLINK is not set
+# CONFIG_VENDOR_ADVANSUS is not set
+# CONFIG_VENDOR_AMD is not set
+# CONFIG_VENDOR_AOPEN is not set
+# CONFIG_VENDOR_APPLE is not set
+# CONFIG_VENDOR_ASROCK is not set
+# CONFIG_VENDOR_ASUS is not set
+# CONFIG_VENDOR_AVALUE is not set
+# CONFIG_VENDOR_BAP is not set
+# CONFIG_VENDOR_BIOSTAR is not set
+# CONFIG_VENDOR_CAVIUM is not set
+# CONFIG_VENDOR_COMPULAB is not set
+# CONFIG_VENDOR_CUBIETECH is not set
+# CONFIG_VENDOR_ELMEX is not set
+# CONFIG_VENDOR_EMULATION is not set
+# CONFIG_VENDOR_ESD is not set
+# CONFIG_VENDOR_FACEBOOK is not set
+# CONFIG_VENDOR_FOXCONN is not set
+# CONFIG_VENDOR_GETAC is not set
+# CONFIG_VENDOR_GIGABYTE is not set
+# CONFIG_VENDOR_GIZMOSPHERE is not set
+# CONFIG_VENDOR_GOOGLE is not set
+# CONFIG_VENDOR_HP is not set
+# CONFIG_VENDOR_IBASE is not set
+# CONFIG_VENDOR_IEI is not set
+# CONFIG_VENDOR_INTEL is not set
+# CONFIG_VENDOR_JETWAY is not set
+# CONFIG_VENDOR_KONTRON is not set
+CONFIG_VENDOR_LENOVO=y
+# CONFIG_VENDOR_LIPPERT is not set
+# CONFIG_VENDOR_MSI is not set
+# CONFIG_VENDOR_OCP is not set
+# CONFIG_VENDOR_OPENCELLULAR is not set
+# CONFIG_VENDOR_PACKARDBELL is not set
+# CONFIG_VENDOR_PCENGINES is not set
+# CONFIG_VENDOR_PURISM is not set
+# CONFIG_VENDOR_RODA is not set
+# CONFIG_VENDOR_SAMSUNG is not set
+# CONFIG_VENDOR_SAPPHIRE is not set
+# CONFIG_VENDOR_SCALEWAY is not set
+# CONFIG_VENDOR_SIEMENS is not set
+# CONFIG_VENDOR_SIFIVE is not set
+# CONFIG_VENDOR_SUPERMICRO is not set
+# CONFIG_VENDOR_TI is not set
+# CONFIG_VENDOR_TYAN is not set
+# CONFIG_VENDOR_VIA is not set
+CONFIG_BOARD_SPECIFIC_OPTIONS=y
+CONFIG_MAINBOARD_DIR="lenovo/g505s"
+CONFIG_MAINBOARD_PART_NUMBER="LENOVO G505S"
+CONFIG_MAX_CPUS=4
+CONFIG_CBFS_SIZE=0x400000
+CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/config_seabios"
+CONFIG_MAINBOARD_VENDOR="LENOVO"
+CONFIG_HW_MEM_HOLE_SIZEK=0x200000
+CONFIG_VGA_BIOS_ID="1002,990b"
+CONFIG_ONBOARD_VGA_IS_PRIMARY=y
+# CONFIG_HUDSON_LEGACY_FREE is not set
+CONFIG_DIMM_SPD_SIZE=256
+CONFIG_VGA_BIOS=y
+CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
+CONFIG_VGA_BIOS_FILE="pci1002,990b.rom"
+CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000
+CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="LENOVO"
+CONFIG_DEVICETREE="devicetree.cb"
+CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
+# CONFIG_HUDSON_XHCI_FWM is not set
+CONFIG_POST_IO=y
+CONFIG_DCACHE_RAM_BASE=0x30000
+CONFIG_DCACHE_RAM_SIZE=0x10000
+CONFIG_MAX_REBOOT_CNT=3
+CONFIG_OVERRIDE_DEVICETREE=""
+CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
+CONFIG_FMDFILE=""
+CONFIG_MMCONF_BASE_ADDRESS=0xF8000000
+CONFIG_POST_DEVICE=y
+# CONFIG_DRIVERS_UART_8250IO is not set
+# CONFIG_VBOOT is not set
+CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="LENOVO G505S"
+CONFIG_BOARD_LENOVO_G505S=y
+# CONFIG_BOARD_LENOVO_L520 is not set
+# CONFIG_BOARD_LENOVO_S230U is not set
+# CONFIG_BOARD_LENOVO_T400 is not set
+# CONFIG_BOARD_LENOVO_T500 is not set
+# CONFIG_BOARD_LENOVO_R400 is not set
+# CONFIG_BOARD_LENOVO_W500 is not set
+# CONFIG_BOARD_LENOVO_T420 is not set
+# CONFIG_BOARD_LENOVO_T420S is not set
+# CONFIG_BOARD_LENOVO_THINKPAD_T430 is not set
+# CONFIG_BOARD_LENOVO_T430S is not set
+# CONFIG_BOARD_LENOVO_T431S is not set
+# CONFIG_BOARD_LENOVO_T520 is not set
+# CONFIG_BOARD_LENOVO_W520 is not set
+# CONFIG_BOARD_LENOVO_T530 is not set
+# CONFIG_BOARD_LENOVO_W530 is not set
+# CONFIG_BOARD_LENOVO_T60 is not set
+# CONFIG_BOARD_LENOVO_THINKCENTRE_A58 is not set
+# CONFIG_BOARD_LENOVO_X131E is not set
+# CONFIG_BOARD_LENOVO_X1_CARBON_GEN1 is not set
+# CONFIG_BOARD_LENOVO_X200 is not set
+# CONFIG_BOARD_LENOVO_X201 is not set
+# CONFIG_BOARD_LENOVO_X220 is not set
+# CONFIG_BOARD_LENOVO_X220I is not set
+# CONFIG_BOARD_LENOVO_X1 is not set
+# CONFIG_BOARD_LENOVO_X230 is not set
+# CONFIG_BOARD_LENOVO_X60 is not set
+# CONFIG_BOARD_LENOVO_Z61T is not set
+# CONFIG_BOARD_LENOVO_BASEBOARD_T520 is not set
+# CONFIG_BOARD_LENOVO_BASEBOARD_T530 is not set
+CONFIG_CPU_ADDR_BITS=48
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
+# CONFIG_USBDEBUG is not set
+CONFIG_MAINBOARD_VERSION="1.0"
+# CONFIG_DRIVERS_PS2_KEYBOARD is not set
+CONFIG_PCIEXP_L1_SUB_STATE=y
+CONFIG_SMBIOS_ENCLOSURE_TYPE=0x09
+CONFIG_HEAP_SIZE=0xc0000
+CONFIG_BOARD_ROMSIZE_KB_4096=y
+# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
+CONFIG_COREBOOT_ROMSIZE_KB_4096=y
+# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
+CONFIG_COREBOOT_ROMSIZE_KB=4096
+CONFIG_ROM_SIZE=0x400000
+CONFIG_SYSTEM_TYPE_LAPTOP=y
+# CONFIG_SYSTEM_TYPE_TABLET is not set
+# CONFIG_SYSTEM_TYPE_DETACHABLE is not set
+# CONFIG_SYSTEM_TYPE_CONVERTIBLE is not set
+# CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set
+
+#
+# Chipset
+#
+
+#
+# SoC
+#
+CONFIG_UDELAY_LAPIC_FIXED_FSB=200
+CONFIG_MMCONF_BUS_NUMBER=64
+CONFIG_S3_VGA_ROM_RUN=y
+CONFIG_EHCI_BAR=0xfef00000
+CONFIG_ACPI_CPU_STRING="\\_PR.CP%02d"
+# CONFIG_SOC_CAVIUM_CN81XX is not set
+CONFIG_ARCH_ARMV8_EXTENSION=0
+CONFIG_STACK_SIZE=0x1000
+# CONFIG_SOC_CAVIUM_COMMON is not set
+# CONFIG_SOC_INTEL_GLK is not set
+CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
+CONFIG_ROMSTAGE_ADDR=0x2000000
+CONFIG_VERSTAGE_ADDR=0x2000000
+CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
+CONFIG_PCIEXP_ASPM=y
+CONFIG_PCIEXP_COMMON_CLOCK=y
+CONFIG_PCIEXP_CLK_PM=y
+CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/amd/agesa/hudson/bootblock.c"
+# CONFIG_SOC_INTEL_COMMON_CANNONLAKE_BASE is not set
+# CONFIG_SOC_INTEL_COFFEELAKE is not set
+# CONFIG_SOC_INTEL_WHISKEYLAKE is not set
+# CONFIG_SOC_INTEL_COMETLAKE is not set
+# CONFIG_SOC_INTEL_CANNONLAKE_PCH_H is not set
+CONFIG_CONSOLE_CBMEM=y
+CONFIG_UART_PCI_ADDR=0x0
+# CONFIG_SOC_INTEL_KABYLAKE is not set
+# CONFIG_SOC_MEDIATEK_MT8173 is not set
+# CONFIG_SOC_MEDIATEK_MT8183 is not set
+# CONFIG_SOC_NVIDIA_TEGRA124 is not set
+# CONFIG_SOC_NVIDIA_TEGRA210 is not set
+# CONFIG_SOC_QC_IPQ40XX is not set
+# CONFIG_SOC_QC_IPQ806X is not set
+# CONFIG_SOC_QUALCOMM_QCS405 is not set
+# CONFIG_SOC_QUALCOMM_SDM845 is not set
+# CONFIG_SOC_ROCKCHIP_RK3288 is not set
+# CONFIG_SOC_ROCKCHIP_RK3399 is not set
+# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set
+# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set
+# CONFIG_SOC_UCB_RISCV is not set
+
+#
+# CPU
+#
+# CONFIG_CPU_ALLWINNER_A10 is not set
+CONFIG_XIP_ROM_SIZE=0x100000
+CONFIG_NUM_IPI_STARTS=2
+CONFIG_CPU_AMD_AGESA=y
+# CONFIG_ENABLE_MRC_CACHE is not set
+CONFIG_S3_DATA_POS=0xFFFF0000
+CONFIG_S3_DATA_SIZE=32768
+CONFIG_CPU_AMD_AGESA_FAMILY15_TN=y
+# CONFIG_CPU_AMD_PI is not set
+# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set
+# CONFIG_SSE2 is not set
+# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set
+# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set
+# CONFIG_CPU_TI_AM335X is not set
+# CONFIG_PARALLEL_CPU_INIT is not set
+# CONFIG_PARALLEL_MP is not set
+# CONFIG_UDELAY_IO is not set
+CONFIG_UDELAY_LAPIC=y
+CONFIG_LAPIC_MONOTONIC_TIMER=y
+# CONFIG_UDELAY_TSC is not set
+# CONFIG_UDELAY_TIMER2 is not set
+CONFIG_TSC_SYNC_LFENCE=y
+# CONFIG_TSC_SYNC_MFENCE is not set
+# CONFIG_NO_FIXED_XIP_ROM_SIZE is not set
+CONFIG_LOGICAL_CPUS=y
+# CONFIG_SMM_TSEG is not set
+# CONFIG_SMM_LAPIC_REMAP_MITIGATION is not set
+# CONFIG_SERIALIZED_SMM_INITIALIZATION is not set
+CONFIG_X86_AMD_FIXED_MTRRS=y
+# CONFIG_PLATFORM_USES_FSP1_0 is not set
+# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set
+# CONFIG_SOC_SETS_MSRS is not set
+CONFIG_CACHE_AS_RAM=y
+CONFIG_NO_CAR_GLOBAL_MIGRATION=y
+CONFIG_SMP=y
+# CONFIG_SUPPORT_CPU_UCODE_IN_CBFS is not set
+# CONFIG_USES_MICROCODE_HEADER_FILES is not set
+
+#
+# Northbridge
+#
+CONFIG_NORTHBRIDGE_AMD_AGESA=y
+# CONFIG_CONSOLE_VGA_MULTI is not set
+CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN=y
+# CONFIG_NORTHBRIDGE_AMD_PI is not set
+CONFIG_MAX_PIRQ_LINKS=4
+
+#
+# Southbridge
+#
+CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON=y
+CONFIG_SOUTHBRIDGE_SPECIFIC_OPTIONS=y
+# CONFIG_HUDSON_XHCI_ENABLE is not set
+# CONFIG_HUDSON_IMC_ENABLE is not set
+# CONFIG_HUDSON_GEC_FWM is not set
+CONFIG_HUDSON_SATA_MODE=0
+
+#
+# NATIVE
+#
+CONFIG_ACPI_ENABLE_THERMAL_ZONE=y
+# CONFIG_AMD_SB_CIMX is not set
+# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set
+# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set
+# CONFIG_SOUTHBRIDGE_INTEL_COMMON is not set
+# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set
+# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS is not set
+# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI is not set
+# CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN is not set
+# CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ is not set
+# CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN is not set
+# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM is not set
+# CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE is not set
+
+#
+# Super I/O
+#
+# CONFIG_SUPERIO_NUVOTON_NCT6776_COM_A is not set
+
+#
+# Embedded Controllers
+#
+CONFIG_EC_COMPAL_ENE932=y
+# CONFIG_EC_GOOGLE_WILCO is not set
+CONFIG_EC_BASE_ACPI_DATA=0x930
+CONFIG_EC_BASE_ACPI_COMMAND=0x934
+CONFIG_EC_BASE_HOST_DATA=0x940
+CONFIG_EC_BASE_HOST_COMMAND=0x944
+CONFIG_EC_BASE_PACKET=0x950
+CONFIG_SEABIOS_PS2_TIMEOUT=0
+
+#
+# AMD Platform Initialization
+#
+# CONFIG_CPU_AMD_AGESA_BINARY_PI is not set
+CONFIG_CPU_AMD_AGESA_OPENSOURCE=y
+# CONFIG_CAVIUM_BDK is not set
+# CONFIG_MAINBOARD_HAS_CHROMEOS is not set
+# CONFIG_GOOGLE_SMBIOS_MAINBOARD_VERSION is not set
+# CONFIG_UEFI_2_4_BINDING is not set
+# CONFIG_UDK_2015_BINDING is not set
+# CONFIG_UDK_2017_BINDING is not set
+CONFIG_UDK_2013_VERSION=2013
+CONFIG_UDK_2015_VERSION=2015
+CONFIG_UDK_2017_VERSION=2017
+CONFIG_UDK_VERSION=2013
+# CONFIG_USE_SIEMENS_HWILIB is not set
+# CONFIG_ARCH_ARM is not set
+# CONFIG_ARCH_BOOTBLOCK_ARM is not set
+# CONFIG_ARCH_VERSTAGE_ARM is not set
+# CONFIG_ARCH_ROMSTAGE_ARM is not set
+# CONFIG_ARCH_RAMSTAGE_ARM is not set
+# CONFIG_ARCH_BOOTBLOCK_ARMV4 is not set
+# CONFIG_ARCH_VERSTAGE_ARMV4 is not set
+# CONFIG_ARCH_ROMSTAGE_ARMV4 is not set
+# CONFIG_ARCH_RAMSTAGE_ARMV4 is not set
+# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set
+# CONFIG_ARCH_VERSTAGE_ARMV7 is not set
+# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set
+# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set
+# CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set
+# CONFIG_ARCH_VERSTAGE_ARMV7_M is not set
+# CONFIG_ARCH_BOOTBLOCK_ARMV7_R is not set
+# CONFIG_ARCH_VERSTAGE_ARMV7_R is not set
+# CONFIG_ARCH_ROMSTAGE_ARMV7_R is not set
+# CONFIG_ARCH_RAMSTAGE_ARMV7_R is not set
+# CONFIG_ARM_LPAE is not set
+# CONFIG_ARCH_ARM64 is not set
+# CONFIG_ARCH_BOOTBLOCK_ARM64 is not set
+# CONFIG_ARCH_VERSTAGE_ARM64 is not set
+# CONFIG_ARCH_ROMSTAGE_ARM64 is not set
+# CONFIG_ARCH_RAMSTAGE_ARM64 is not set
+# CONFIG_ARCH_BOOTBLOCK_ARMV8_64 is not set
+# CONFIG_ARCH_VERSTAGE_ARMV8_64 is not set
+# CONFIG_ARCH_ROMSTAGE_ARMV8_64 is not set
+# CONFIG_ARCH_RAMSTAGE_ARMV8_64 is not set
+# CONFIG_ARM64_USE_ARCH_TIMER is not set
+# CONFIG_ARM64_A53_ERRATUM_843419 is not set
+# CONFIG_ARCH_MIPS is not set
+# CONFIG_ARCH_BOOTBLOCK_MIPS is not set
+# CONFIG_ARCH_VERSTAGE_MIPS is not set
+# CONFIG_ARCH_ROMSTAGE_MIPS is not set
+# CONFIG_ARCH_RAMSTAGE_MIPS is not set
+# CONFIG_ARCH_PPC64 is not set
+# CONFIG_ARCH_BOOTBLOCK_PPC64 is not set
+# CONFIG_ARCH_VERSTAGE_PPC64 is not set
+# CONFIG_ARCH_ROMSTAGE_PPC64 is not set
+# CONFIG_ARCH_RAMSTAGE_PPC64 is not set
+# CONFIG_ARCH_RISCV is not set
+CONFIG_ARCH_RISCV_M=y
+# CONFIG_ARCH_RISCV_S is not set
+# CONFIG_ARCH_RISCV_U is not set
+# CONFIG_ARCH_RISCV_RV64 is not set
+# CONFIG_ARCH_RISCV_RV32 is not set
+# CONFIG_ARCH_RISCV_PMP is not set
+# CONFIG_ARCH_BOOTBLOCK_RISCV is not set
+# CONFIG_ARCH_VERSTAGE_RISCV is not set
+# CONFIG_ARCH_ROMSTAGE_RISCV is not set
+# CONFIG_ARCH_RAMSTAGE_RISCV is not set
+# CONFIG_RISCV_USE_ARCH_TIMER is not set
+CONFIG_ARCH_X86=y
+CONFIG_ARCH_BOOTBLOCK_X86_32=y
+CONFIG_ARCH_VERSTAGE_X86_32=y
+CONFIG_ARCH_ROMSTAGE_X86_32=y
+CONFIG_ARCH_POSTCAR_X86_32=y
+CONFIG_ARCH_RAMSTAGE_X86_32=y
+# CONFIG_ARCH_BOOTBLOCK_X86_64 is not set
+# CONFIG_ARCH_VERSTAGE_X86_64 is not set
+# CONFIG_ARCH_ROMSTAGE_X86_64 is not set
+# CONFIG_ARCH_POSTCAR_X86_64 is not set
+# CONFIG_ARCH_RAMSTAGE_X86_64 is not set
+# CONFIG_USE_MARCH_586 is not set
+# CONFIG_AP_IN_SIPI_WAIT is not set
+# CONFIG_SIPI_VECTOR_IN_ROM is not set
+CONFIG_RAMBASE=0xe00000
+CONFIG_RAMTOP=0x1000000
+CONFIG_CBMEM_TOP_BACKUP=y
+# CONFIG_EARLY_EBDA_INIT is not set
+CONFIG_PC80_SYSTEM=y
+# CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set
+# CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set
+# CONFIG_HAVE_CMOS_DEFAULT is not set
+CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y
+# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set
+# CONFIG_HPET_ADDRESS_OVERRIDE is not set
+CONFIG_HPET_ADDRESS=0xfed00000
+CONFIG_ID_SECTION_OFFSET=0x80
+CONFIG_POSTCAR_STAGE=y
+# CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set
+# CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set
+CONFIG_BOOTBLOCK_SIMPLE=y
+# CONFIG_BOOTBLOCK_NORMAL is not set
+CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c"
+# CONFIG_COLLECT_TIMESTAMPS_NO_TSC is not set
+CONFIG_COLLECT_TIMESTAMPS_TSC=y
+# CONFIG_PAGING_IN_CACHE_AS_RAM is not set
+# CONFIG_IDT_IN_EVERY_STAGE is not set
+CONFIG_HAVE_CF9_RESET=y
+CONFIG_HAVE_CF9_RESET_PREPARE=y
+
+#
+# Devices
+#
+CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
+CONFIG_HAVE_VBE_LINEAR_FRAMEBUFFER=y
+# CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT is not set
+# CONFIG_MAINBOARD_HAS_LIBGFXINIT is not set
+CONFIG_MAINBOARD_HAS_MULTIPLE_VGA_ADAPTERS=y
+CONFIG_VGA_ROM_RUN=y
+# CONFIG_NO_GFX_INIT is not set
+# CONFIG_ALWAYS_LOAD_OPROM is not set
+CONFIG_ON_DEVICE_ROM_LOAD=y
+# CONFIG_PCI_OPTION_ROM_RUN_REALMODE is not set
+CONFIG_PCI_OPTION_ROM_RUN_YABEL=y
+CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES=y
+# CONFIG_YABEL_PCI_FAKE_WRITING_OTHER_DEVICES_CONFIG is not set
+CONFIG_YABEL_VIRTMEM_LOCATION=0x1000000
+CONFIG_YABEL_DIRECTHW=y
+CONFIG_MULTIPLE_VGA_ADAPTERS=y
+
+#
+# Display
+#
+CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
+# CONFIG_FRAMEBUFFER_VESA_MODE_100 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_101 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_102 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_103 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_104 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_105 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_106 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_107 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_108 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_109 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_10A is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_10B is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_10C is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_10D is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_10E is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_10F is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_110 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_111 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_112 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_113 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_114 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_115 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_116 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_117 is not set
+CONFIG_FRAMEBUFFER_VESA_MODE_118=y
+# CONFIG_FRAMEBUFFER_VESA_MODE_119 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_11A is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_11B is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_USER is not set
+CONFIG_FRAMEBUFFER_VESA_MODE=0x118
+CONFIG_BOOTSPLASH=y
+# CONFIG_VGA_TEXT_FRAMEBUFFER is not set
+CONFIG_VBE_LINEAR_FRAMEBUFFER=y
+CONFIG_LINEAR_FRAMEBUFFER=y
+# CONFIG_SMBUS_HAS_AUX_CHANNELS is not set
+CONFIG_PCI=y
+# CONFIG_NO_MMCONF_SUPPORT is not set
+CONFIG_MMCONF_SUPPORT=y
+# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set
+CONFIG_PCIX_PLUGIN_SUPPORT=y
+CONFIG_CARDBUS_PLUGIN_SUPPORT=y
+# CONFIG_AZALIA_PLUGIN_SUPPORT is not set
+CONFIG_PCIEXP_PLUGIN_SUPPORT=y
+# CONFIG_EARLY_PCI_BRIDGE is not set
+CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
+CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
+CONFIG_VGA_BIOS_DGPU=y
+CONFIG_VGA_BIOS_DGPU_FILE="pci1002,6665.rom"
+CONFIG_VGA_BIOS_DGPU_ID="1002,6665"
+# CONFIG_SOFTWARE_I2C is not set
+
+#
+# Generic Drivers
+#
+# CONFIG_DRIVERS_AS3722_RTC is not set
+# CONFIG_GIC is not set
+# CONFIG_IPMI_KCS is not set
+# CONFIG_DRIVERS_LENOVO_WACOM is not set
+# CONFIG_RT8168_GET_MAC_FROM_VPD is not set
+# CONFIG_RT8168_SET_LED_MODE is not set
+# CONFIG_SMMSTORE_IN_CBFS is not set
+CONFIG_SPI_FLASH=y
+CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
+# CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY is not set
+# CONFIG_SPI_FLASH_NO_FAST_READ is not set
+CONFIG_SPI_FLASH_ADESTO=y
+CONFIG_SPI_FLASH_AMIC=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B is not set
+# CONFIG_SPI_FLASH_HAS_VOLATILE_GROUP is not set
+# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set
+CONFIG_NO_UART_ON_SUPERIO=y
+# CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set
+# CONFIG_UART_OVERRIDE_REFCLK is not set
+# CONFIG_DRIVERS_UART_8250MEM is not set
+# CONFIG_DRIVERS_UART_8250MEM_32 is not set
+# CONFIG_HAVE_UART_SPECIAL is not set
+# CONFIG_DRIVERS_UART_OXPCIE is not set
+# CONFIG_DRIVERS_UART_PL011 is not set
+# CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set
+CONFIG_HAVE_USBDEBUG=y
+CONFIG_HAVE_USBDEBUG_OPTIONS=y
+# CONFIG_VPD is not set
+CONFIG_DRIVERS_AMD_PI=y
+CONFIG_SMBIOS_PROVIDED_BY_MOBO=y
+# CONFIG_DRIVERS_I2C_MAX98373 is not set
+# CONFIG_DRIVERS_I2C_MAX98927 is not set
+# CONFIG_DRIVERS_I2C_PCA9538 is not set
+# CONFIG_DRIVERS_I2C_PCF8523 is not set
+# CONFIG_DRIVERS_I2C_RT5663 is not set
+# CONFIG_DRIVERS_I2C_RTD2132 is not set
+# CONFIG_DRIVERS_I2C_RX6110SA is not set
+# CONFIG_DRIVERS_I2C_SX9310 is not set
+# CONFIG_MAINBOARD_HAS_I2C_TPM_ATMEL is not set
+# CONFIG_MAINBOARD_HAS_I2C_TPM_CR50 is not set
+# CONFIG_MAINBOARD_HAS_I2C_TPM_GENERIC is not set
+# CONFIG_PLATFORM_USES_FSP2_0 is not set
+# CONFIG_PLATFORM_USES_FSP2_1 is not set
+# CONFIG_INTEL_DDI is not set
+# CONFIG_INTEL_EDID is not set
+# CONFIG_INTEL_INT15 is not set
+# CONFIG_INTEL_GMA_ACPI is not set
+# CONFIG_INTEL_GMA_SSC_ALTERNATE_REF is not set
+# CONFIG_INTEL_GMA_SWSMISCI is not set
+# CONFIG_DRIVER_INTEL_I210 is not set
+# CONFIG_DRIVERS_INTEL_MIPI_CAMERA is not set
+# CONFIG_DRIVERS_INTEL_WIFI is not set
+# CONFIG_USE_SAR is not set
+# CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS is not set
+# CONFIG_DRIVER_MAXIM_MAX77686 is not set
+# CONFIG_DRIVER_PARADE_PS8625 is not set
+# CONFIG_DRIVER_PARADE_PS8640 is not set
+CONFIG_DRIVERS_MC146818=y
+# CONFIG_LPC_TPM is not set
+# CONFIG_MAINBOARD_HAS_LPC_TPM is not set
+# CONFIG_DRIVERS_RICOH_RCE822 is not set
+# CONFIG_DRIVER_SIEMENS_NC_FPGA is not set
+# CONFIG_NC_FPGA_NOTIFY_CB_READY is not set
+# CONFIG_DRIVERS_SIL_3114 is not set
+# CONFIG_MAINBOARD_HAS_SPI_TPM_CR50 is not set
+# CONFIG_DRIVER_TI_TPS65090 is not set
+# CONFIG_DRIVERS_TI_TPS65913 is not set
+# CONFIG_DRIVERS_TI_TPS65913_RTC is not set
+# CONFIG_DRIVERS_USB_ACPI is not set
+# CONFIG_DRIVER_XPOWERS_AXP209 is not set
+# CONFIG_COMMONLIB_STORAGE is not set
+
+#
+# Security
+#
+
+#
+# Verified Boot (vboot)
+#
+
+#
+# Trusted Platform Module
+#
+CONFIG_USER_NO_TPM=y
+# CONFIG_ACPI_SATA_GENERATOR is not set
+# CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES is not set
+# CONFIG_ACPI_AMD_HARDWARE_SLEEP_VALUES is not set
+# CONFIG_BOOT_DEVICE_NOT_SPI_FLASH is not set
+CONFIG_BOOT_DEVICE_SPI_FLASH=y
+CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
+# CONFIG_BOOT_DEVICE_SUPPORTS_WRITES is not set
+# CONFIG_RTC is not set
+
+#
+# Console
+#
+# CONFIG_POSTCAR_CONSOLE is not set
+CONFIG_SQUELCH_EARLY_SMP=y
+# CONFIG_SPKMODEM is not set
+# CONFIG_CONSOLE_NE2K is not set
+CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
+# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
+# CONFIG_CONSOLE_SPI_FLASH is not set
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
+# CONFIG_NO_POST is not set
+# CONFIG_CMOS_POST is not set
+# CONFIG_CONSOLE_POST is not set
+CONFIG_POST_DEVICE_NONE=y
+# CONFIG_POST_DEVICE_LPC is not set
+# CONFIG_POST_DEVICE_PCI_PCIE is not set
+CONFIG_POST_IO_PORT=0x80
+# CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set
+CONFIG_HWBASE_DEBUG_CB=y
+CONFIG_HAVE_ACPI_RESUME=y
+# CONFIG_ACPI_HUGE_LOWMEM_BACKUP is not set
+CONFIG_RESUME_PATH_SAME_AS_BOOT=y
+# CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set
+# CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set
+# CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set
+CONFIG_HAVE_MONOTONIC_TIMER=y
+# CONFIG_GENERIC_UDELAY is not set
+# CONFIG_TIMER_QUEUE is not set
+CONFIG_HAVE_OPTION_TABLE=y
+# CONFIG_PIRQ_ROUTE is not set
+CONFIG_HAVE_SMI_HANDLER=y
+# CONFIG_PCI_IO_CFG_EXT is not set
+CONFIG_IOAPIC=y
+# CONFIG_USE_WATCHDOG_ON_BOOT is not set
+CONFIG_GFXUMA=y
+CONFIG_HAVE_ACPI_TABLES=y
+CONFIG_HAVE_MP_TABLE=y
+# CONFIG_COMMON_FADT is not set
+# CONFIG_ACPI_NHLT is not set
+
+#
+# System tables
+#
+CONFIG_GENERATE_MP_TABLE=y
+# CONFIG_GENERATE_PIRQ_TABLE is not set
+CONFIG_GENERATE_SMBIOS_TABLES=y
+
+#
+# Payload
+#
+# CONFIG_PAYLOAD_NONE is not set
+# CONFIG_PAYLOAD_ELF is not set
+# CONFIG_PAYLOAD_BAYOU is not set
+# CONFIG_PAYLOAD_FILO is not set
+# CONFIG_PAYLOAD_GRUB2 is not set
+# CONFIG_PAYLOAD_LINUXBOOT is not set
+CONFIG_PAYLOAD_SEABIOS=y
+# CONFIG_PAYLOAD_UBOOT is not set
+# CONFIG_PAYLOAD_YABITS is not set
+# CONFIG_PAYLOAD_LINUX is not set
+# CONFIG_PAYLOAD_TIANOCORE is not set
+CONFIG_PAYLOAD_FILE="payloads/external/SeaBIOS/seabios/out/bios.bin.elf"
+# CONFIG_SEABIOS_STABLE is not set
+CONFIG_SEABIOS_MASTER=y
+# CONFIG_SEABIOS_REVISION is not set
+# CONFIG_SEABIOS_THREAD_OPTIONROMS is not set
+CONFIG_SEABIOS_BOOTORDER_FILE=""
+# CONFIG_SEABIOS_ADD_SERCON_PORT_FILE is not set
+CONFIG_SEABIOS_DEBUG_LEVEL=-1
+
+#
+# Using default SeaBIOS log level
+#
+CONFIG_PAYLOAD_OPTIONS=""
+# CONFIG_PXE is not set
+CONFIG_COMPRESSED_PAYLOAD_LZMA=y
+# CONFIG_COMPRESSED_PAYLOAD_LZ4 is not set
+# CONFIG_PAYLOAD_IS_FLAT_BINARY is not set
+CONFIG_COMPRESS_SECONDARY_PAYLOAD=y
+
+#
+# Secondary Payloads
+#
+CONFIG_COREINFO_SECONDARY_PAYLOAD=y
+# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set
+# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set
+CONFIG_TINT_SECONDARY_PAYLOAD=y
+
+#
+# Debugging
+#
+
+#
+# CPU Debug Settings
+#
+# CONFIG_DEBUG_SMM_RELOCATION is not set
+
+#
+# General Debug Settings
+#
+# CONFIG_FATAL_ASSERTS is not set
+# CONFIG_DEBUG_CBFS is not set
+# CONFIG_HAVE_DEBUG_RAM_SETUP is not set
+# CONFIG_HAVE_DEBUG_SMBUS is not set
+# CONFIG_DEBUG_SMI is not set
+# CONFIG_DEBUG_MALLOC is not set
+# CONFIG_DEBUG_ACPI is not set
+# CONFIG_DEBUG_CONSOLE_INIT is not set
+# CONFIG_X86EMU_DEBUG is not set
+# CONFIG_DEBUG_SPI_FLASH is not set
+# CONFIG_TRACE is not set
+# CONFIG_DEBUG_BOOT_STATE is not set
+# CONFIG_DEBUG_ADA_CODE is not set
+# CONFIG_HAVE_EM100_SUPPORT is not set
+CONFIG_NO_EDID_FILL_FB=y
+# CONFIG_ENABLE_APIC_EXT_ID is not set
+CONFIG_WARNINGS_ARE_ERRORS=y
+# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set
+# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set
+# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set
+# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set
+# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set
+# CONFIG_REG_SCRIPT is not set
+# CONFIG_NO_XIP_EARLY_STAGES is not set
+# CONFIG_EARLY_CBMEM_LIST is not set
+CONFIG_RELOCATABLE_MODULES=y
+CONFIG_BOOTBLOCK_CUSTOM=y
+
--
To view, visit https://review.coreboot.org/c/coreboot/+/32352
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I85f17395afca52ef690f24fcef746d74bb72aab7
Gerrit-Change-Number: 32352
Gerrit-PatchSet: 1
Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com>
Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com>
Gerrit-MessageType: newchange
1 week, 4 days
- 4
- 37
Change in coreboot[master]: [WIP]arch/arm: Implement FIT support
by Arthur Heymans (Code Review)
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35410 )
Change subject: [WIP]arch/arm: Implement FIT support
......................................................................
[WIP]arch/arm: Implement FIT support
Untested
Change-Id: Ifae3cbae85bcd1c35f31278f76f4d97700979da3
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M payloads/Kconfig
M src/arch/arm/Makefile.inc
A src/arch/arm/fit_payload.c
3 files changed, 152 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/35410/1
diff --git a/payloads/Kconfig b/payloads/Kconfig
index 46cfaf5..04566cc 100644
--- a/payloads/Kconfig
+++ b/payloads/Kconfig
@@ -30,7 +30,7 @@
config PAYLOAD_FIT
bool "A FIT payload"
- depends on ARCH_ARM64 || ARCH_RISCV
+ depends on ARCH_ARM || ARCH_ARM64 || ARCH_RISCV
select PAYLOAD_FIT_SUPPORT
help
Select this option if you have a payload image (a FIT file) which
@@ -100,7 +100,7 @@
bool "FIT support"
default n
default y if PAYLOAD_LINUX && (ARCH_ARM || ARCH_ARM64 || ARCH_RISCV)
- depends on ARCH_ARM64 || ARCH_RISCV
+ depends on ARCH_ARM || ARCH_ARM64 || ARCH_RISCV
select FLATTENED_DEVICE_TREE
help
Select this option if your payload is of type FIT.
diff --git a/src/arch/arm/Makefile.inc b/src/arch/arm/Makefile.inc
index 508b0a8..83c698a 100644
--- a/src/arch/arm/Makefile.inc
+++ b/src/arch/arm/Makefile.inc
@@ -131,6 +131,7 @@
ramstage-y += memcpy.S
ramstage-y += memmove.S
ramstage-y += clock.c
+ramstage-$(CONFIG_PAYLOAD_FIT_SUPPORT) += fit_payload.c
rmodules_arm-y += memset.S
rmodules_arm-y += memcpy.S
diff --git a/src/arch/arm/fit_payload.c b/src/arch/arm/fit_payload.c
new file mode 100644
index 0000000..5792dfb
--- /dev/null
+++ b/src/arch/arm/fit_payload.c
@@ -0,0 +1,149 @@
+/*
+ * Copyright 2013 Google Inc.
+ * Copyright 2018 Facebook, Inc.
+ * Copyright 2019 9elements Agency GmbH <patrick.rudolph(a)9elements.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <bootmem.h>
+#include <stdlib.h>
+#include <program_loading.h>
+#include <string.h>
+#include <commonlib/compression.h>
+#include <commonlib/cbfs_serialized.h>
+#include <lib.h>
+#include <fit.h>
+#include <endian.h>
+
+#define MAX_KERNEL_SIZE (64*MiB)
+#define SECTION_ALIGN 64
+
+static size_t get_kernel_size(const struct fit_image_node *node)
+{
+ /*
+ * Since we don't have a way to determine the uncompressed size of the
+ * kernel, we have to keep as much memory as possible free for use by
+ * the kernel immediately after the end of the kernel image. The amount
+ * of space required will vary depending on selected features, and is
+ * effectively unbound.
+ */
+
+ printk(BIOS_INFO,
+ "FIT: Leaving additional %u MiB of free space after kernel.\n",
+ MAX_KERNEL_SIZE >> 20);
+
+ return node->size + MAX_KERNEL_SIZE;
+}
+
+/**
+ * Place the region in free memory range.
+ *
+ * The caller has to set region->offset to the minimum allowed address.
+ */
+static bool fit_place_mem(const struct range_entry *r, void *arg)
+{
+ struct region *region = arg;
+ resource_t start;
+
+ if (range_entry_tag(r) != BM_MEM_RAM)
+ return true;
+
+ /* Section must be aligned at page boundary */
+ start = ALIGN_UP(MAX(region->offset, range_entry_base(r)), SECTION_ALIGN);
+
+ if (start + region->size < range_entry_end(r)) {
+ region->offset = (size_t)start;
+ return false;
+ }
+
+ return true;
+}
+
+static uint32_t arm_kernel_args[3];
+
+bool fit_payload_arch(struct prog *payload, struct fit_config_node *config,
+ struct region *kernel,
+ struct region *fdt,
+ struct region *initrd)
+{
+ size_t lower_mem;
+
+ if (!config->fdt || !fdt) {
+ printk(BIOS_CRIT, "CRIT: Providing a valid FDT is mandatory to "
+ "boot a RISC-V kernel!\n");
+ return false;
+ /* TODO: Fall back to the ROM FDT? */
+ }
+
+ /* Update kernel size from image header, if possible */
+ kernel->size = get_kernel_size(config->kernel);
+ printk(BIOS_DEBUG, "FIT: Using kernel size of 0x%zx bytes\n",
+ kernel->size);
+
+ /*
+ * The code assumes that bootmem_walk provides a sorted list of memory
+ * regions, starting from the lowest address.
+ * The order of the calls here doesn't matter, as the placement is
+ * enforced in the called functions.
+ * For details check code on top.
+ */
+ kernel->offset = 0;
+ if (!bootmem_walk(fit_place_mem, kernel))
+ return false;
+
+ /*
+ * The kernel documentation recommends place the image 32M above to avoid
+ * the need to relocate prior to compression.
+ */
+ lower_mem = kernel->offset;
+ kernel->offset += 32 * MiB;
+
+ /* Mark as reserved for future allocations. */
+ bootmem_add_range(kernel->offset, kernel->size, BM_MEM_PAYLOAD);
+
+ /* Place FDT and INITRD after kernel. */
+
+ /* Place INITRD and FDT:
+ * The Kernel documentation recommends the safe location of 128M above
+ * the start of ram to avoid being overwritten by the kernel
+ * decompressor.
+ */
+ if (config->ramdisk) {
+ initrd->offset = lower_mem + 128 * MiB;
+
+ if (!bootmem_walk(fit_place_mem, initrd))
+ return false;
+ /* Mark as reserved for future allocations. */
+ bootmem_add_range(initrd->offset, initrd->size, BM_MEM_PAYLOAD);
+ }
+
+ /* Place FDT */
+ fdt->offset = lower_mem + 128 * MiB;
+
+ if (!bootmem_walk(fit_place_mem, fdt))
+ return false;
+ /* Mark as reserved for future allocations. */
+ bootmem_add_range(fdt->offset, fdt->size, BM_MEM_PAYLOAD);
+
+ /* Kernel expects FDT as argument */
+ arm_kernel_args[0] = 0;
+ /* All ones for FDT */
+ arm_kernel_args[1] = ~0;
+ arm_kernel_args[2] = fdt->offset;
+
+ prog_set_entry(payload, (void *)kernel->offset, (void *)arm_kernel_args);
+
+ bootmem_dump_ranges();
+
+ return true;
+}
--
To view, visit https://review.coreboot.org/c/coreboot/+/35410
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ifae3cbae85bcd1c35f31278f76f4d97700979da3
Gerrit-Change-Number: 35410
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-MessageType: newchange
2 weeks
- 7
- 16
Change in coreboot[master]: [WIP]arch/arm: Allow program loading of Linux kernels
by Arthur Heymans (Code Review)
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35409 )
Change subject: [WIP]arch/arm: Allow program loading of Linux kernels
......................................................................
[WIP]arch/arm: Allow program loading of Linux kernels
On ARM the linux kernel takes 3 arguments:
r0 = 0
r1 = machine_type (0xffffffff if using FDT)
r2 = &fdt
To allow this, a function with a different signature needs to be used
when using a FIT payload.
Change-Id: Ie0dcc26d647941de71669345911ba288341b834b
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/arch/arm/boot.c
1 file changed, 16 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/35409/1
diff --git a/src/arch/arm/boot.c b/src/arch/arm/boot.c
index 9d1e4cd..fd7ba68 100644
--- a/src/arch/arm/boot.c
+++ b/src/arch/arm/boot.c
@@ -11,15 +11,29 @@
* GNU General Public License for more details.
*/
+#include <cbfs.h>
#include <arch/cache.h>
#include <program_loading.h>
void arch_prog_run(struct prog *prog)
{
void (*doit)(void *);
+ void (*doit_3)(void *, void *, void *);
+ char *program_arg = prog_entry_arg(prog);
cache_sync_instructions();
- doit = prog_entry(prog);
- doit(prog_entry_arg(prog));
+ /* The Linux kernel takes 3 dword's as argument */
+ switch (prog_cbfs_type(prog)) {
+ case CBFS_TYPE_FIT: /* Flattened image tree */
+ if (CONFIG(PAYLOAD_FIT_SUPPORT)) {
+ doit_3 = prog_entry(prog);
+ doit_3((void *)program_arg, (void *)(program_arg + sizeof(void *)),
+ (void *)(program_arg + 2 * sizeof(void *)));
+ break;
+ } /* else fall-through */
+ default:
+ doit = prog_entry(prog);
+ doit((void *)program_arg);
+ }
}
--
To view, visit https://review.coreboot.org/c/coreboot/+/35409
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ie0dcc26d647941de71669345911ba288341b834b
Gerrit-Change-Number: 35409
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-MessageType: newchange
2 weeks
- 7
- 22
Change in coreboot[master]: [RFC] sconfig: Allow to give static device nodes a name
by Nico Huber (Code Review)
Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35456 )
Change subject: [RFC] sconfig: Allow to give static device nodes a name
......................................................................
[RFC] sconfig: Allow to give static device nodes a name
The idea is to give device nodes in the `devicetree.cb` a name that can
later be used in C code to identify the device (without having to look
it up by fragile means). For this, we add an optional `as <identifier>`
to the device declaration, for instance:
device i2c 0x50 as serial_eeprom on end
This leads to a `struct device __static_serial_eeprom;` that can then
be used throughout coreboot.
Change-Id: I058a319f9b968924fbef9485a96c9e3f900a3ee8
Signed-off-by: Nico Huber <nico.huber(a)secunet.com>
---
M Makefile.inc
M util/sconfig/lex.yy.c_shipped
M util/sconfig/main.c
M util/sconfig/sconfig.h
M util/sconfig/sconfig.l
M util/sconfig/sconfig.tab.c_shipped
M util/sconfig/sconfig.tab.h_shipped
M util/sconfig/sconfig.y
8 files changed, 589 insertions(+), 505 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/35456/1
diff --git a/Makefile.inc b/Makefile.inc
index 3c3088d..ed4874a 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -386,7 +386,7 @@
COREBOOT_EXPORTS += COREBOOT_EXTRA_VERSION
endif
-CPPFLAGS_common := -Isrc -Isrc/include -Isrc/commonlib/include -I$(obj)
+CPPFLAGS_common := -Isrc -Isrc/include -Isrc/commonlib/include -I$(obj) -I$(obj)/mainboard/$(MAINBOARDDIR)
VBOOT_SOURCE ?= 3rdparty/vboot
CPPFLAGS_common += -I$(VBOOT_SOURCE)/firmware/include
CPPFLAGS_common += -include $(src)/include/kconfig.h
diff --git a/util/sconfig/lex.yy.c_shipped b/util/sconfig/lex.yy.c_shipped
index 14ffeff..c8202a1 100644
--- a/util/sconfig/lex.yy.c_shipped
+++ b/util/sconfig/lex.yy.c_shipped
@@ -6,7 +6,7 @@
#define FLEX_SCANNER
#define YY_FLEX_MAJOR_VERSION 2
#define YY_FLEX_MINOR_VERSION 6
-#define YY_FLEX_SUBMINOR_VERSION 1
+#define YY_FLEX_SUBMINOR_VERSION 4
#if YY_FLEX_SUBMINOR_VERSION > 0
#define FLEX_BETA
#endif
@@ -81,10 +81,16 @@
#define UINT32_MAX (4294967295U)
#endif
+#ifndef SIZE_MAX
+#define SIZE_MAX (~(size_t)0)
+#endif
+
#endif /* ! C99 */
#endif /* ! FLEXINT_H */
+/* begin standard C++ headers. */
+
/* TODO: this is always defined, so inline it */
#define yyconst const
@@ -97,32 +103,26 @@
/* Returned upon end-of-file. */
#define YY_NULL 0
-/* Promotes a possibly negative, possibly signed char to an unsigned
- * integer for use as an array index. If the signed char is negative,
- * we want to instead treat it as an 8-bit unsigned char, hence the
- * double cast.
+/* Promotes a possibly negative, possibly signed char to an
+ * integer in range [0..255] for use as an array index.
*/
-#define YY_SC_TO_UI(c) ((unsigned int) (unsigned char) c)
+#define YY_SC_TO_UI(c) ((YY_CHAR) (c))
/* Enter a start condition. This macro really ought to take a parameter,
* but we do it the disgusting crufty way forced on us by the ()-less
* definition of BEGIN.
*/
#define BEGIN (yy_start) = 1 + 2 *
-
/* Translate the current start state into a value that can be later handed
* to BEGIN to return to the state. The YYSTATE alias is for lex
* compatibility.
*/
#define YY_START (((yy_start) - 1) / 2)
#define YYSTATE YY_START
-
/* Action number for EOF rule of a given start state. */
#define YY_STATE_EOF(state) (YY_END_OF_BUFFER + state + 1)
-
/* Special action meaning "start processing a new file". */
-#define YY_NEW_FILE yyrestart(yyin )
-
+#define YY_NEW_FILE yyrestart( yyin )
#define YY_END_OF_BUFFER_CHAR 0
/* Size of default input buffer. */
@@ -159,7 +159,7 @@
#define EOB_ACT_CONTINUE_SCAN 0
#define EOB_ACT_END_OF_FILE 1
#define EOB_ACT_LAST_MATCH 2
-
+
#define YY_LESS_LINENO(n)
#define YY_LINENO_REWIND_TO(ptr)
@@ -168,7 +168,7 @@
do \
{ \
/* Undo effects of setting up yytext. */ \
- yy_size_t yyless_macro_arg = (n); \
+ int yyless_macro_arg = (n); \
YY_LESS_LINENO(yyless_macro_arg);\
*yy_cp = (yy_hold_char); \
YY_RESTORE_YY_MORE_OFFSET \
@@ -176,7 +176,6 @@
YY_DO_BEFORE_ACTION; /* set up yytext again */ \
} \
while ( 0 )
-
#define unput(c) yyunput( c, (yytext_ptr) )
#ifndef YY_STRUCT_YY_BUFFER_STATE
@@ -258,7 +257,6 @@
#define YY_CURRENT_BUFFER ( (yy_buffer_stack) \
? (yy_buffer_stack)[(yy_buffer_stack_top)] \
: NULL)
-
/* Same as previous macro, but useful when we know that the buffer stack is not
* NULL or when we need an lvalue. For internal use only.
*/
@@ -279,62 +277,56 @@
*/
static int yy_did_buffer_switch_on_eof;
-void yyrestart (FILE *input_file );
-void yy_switch_to_buffer (YY_BUFFER_STATE new_buffer );
-YY_BUFFER_STATE yy_create_buffer (FILE *file,int size );
-void yy_delete_buffer (YY_BUFFER_STATE b );
-void yy_flush_buffer (YY_BUFFER_STATE b );
-void yypush_buffer_state (YY_BUFFER_STATE new_buffer );
-void yypop_buffer_state (void );
+void yyrestart ( FILE *input_file );
+void yy_switch_to_buffer ( YY_BUFFER_STATE new_buffer );
+YY_BUFFER_STATE yy_create_buffer ( FILE *file, int size );
+void yy_delete_buffer ( YY_BUFFER_STATE b );
+void yy_flush_buffer ( YY_BUFFER_STATE b );
+void yypush_buffer_state ( YY_BUFFER_STATE new_buffer );
+void yypop_buffer_state ( void );
-static void yyensure_buffer_stack (void );
-static void yy_load_buffer_state (void );
-static void yy_init_buffer (YY_BUFFER_STATE b,FILE *file );
+static void yyensure_buffer_stack ( void );
+static void yy_load_buffer_state ( void );
+static void yy_init_buffer ( YY_BUFFER_STATE b, FILE *file );
+#define YY_FLUSH_BUFFER yy_flush_buffer( YY_CURRENT_BUFFER )
-#define YY_FLUSH_BUFFER yy_flush_buffer(YY_CURRENT_BUFFER )
+YY_BUFFER_STATE yy_scan_buffer ( char *base, yy_size_t size );
+YY_BUFFER_STATE yy_scan_string ( const char *yy_str );
+YY_BUFFER_STATE yy_scan_bytes ( const char *bytes, int len );
-YY_BUFFER_STATE yy_scan_buffer (char *base,yy_size_t size );
-YY_BUFFER_STATE yy_scan_string (yyconst char *yy_str );
-YY_BUFFER_STATE yy_scan_bytes (yyconst char *bytes,int len );
-
-void *yyalloc (yy_size_t );
-void *yyrealloc (void *,yy_size_t );
-void yyfree (void * );
+void *yyalloc ( yy_size_t );
+void *yyrealloc ( void *, yy_size_t );
+void yyfree ( void * );
#define yy_new_buffer yy_create_buffer
-
#define yy_set_interactive(is_interactive) \
{ \
if ( ! YY_CURRENT_BUFFER ){ \
yyensure_buffer_stack (); \
YY_CURRENT_BUFFER_LVALUE = \
- yy_create_buffer(yyin,YY_BUF_SIZE ); \
+ yy_create_buffer( yyin, YY_BUF_SIZE ); \
} \
YY_CURRENT_BUFFER_LVALUE->yy_is_interactive = is_interactive; \
}
-
#define yy_set_bol(at_bol) \
{ \
if ( ! YY_CURRENT_BUFFER ){\
yyensure_buffer_stack (); \
YY_CURRENT_BUFFER_LVALUE = \
- yy_create_buffer(yyin,YY_BUF_SIZE ); \
+ yy_create_buffer( yyin, YY_BUF_SIZE ); \
} \
YY_CURRENT_BUFFER_LVALUE->yy_at_bol = at_bol; \
}
-
#define YY_AT_BOL() (YY_CURRENT_BUFFER_LVALUE->yy_at_bol)
/* Begin user sect3 */
-
-typedef unsigned char YY_CHAR;
+typedef flex_uint8_t YY_CHAR;
FILE *yyin = NULL, *yyout = NULL;
typedef int yy_state_type;
extern int yylineno;
-
int yylineno = 1;
extern char *yytext;
@@ -343,10 +335,10 @@
#endif
#define yytext_ptr yytext
-static yy_state_type yy_get_previous_state (void );
-static yy_state_type yy_try_NUL_trans (yy_state_type current_state );
-static int yy_get_next_buffer (void );
-static void yynoreturn yy_fatal_error (yyconst char* msg );
+static yy_state_type yy_get_previous_state ( void );
+static yy_state_type yy_try_NUL_trans ( yy_state_type current_state );
+static int yy_get_next_buffer ( void );
+static void yynoreturn yy_fatal_error ( const char* msg );
/* Done after the current pattern has been matched and before the
* corresponding action - sets up yytext.
@@ -357,9 +349,8 @@
(yy_hold_char) = *yy_cp; \
*yy_cp = '\0'; \
(yy_c_buf_p) = yy_cp;
-
-#define YY_NUM_RULES 38
-#define YY_END_OF_BUFFER 39
+#define YY_NUM_RULES 39
+#define YY_END_OF_BUFFER 40
/* This struct is not used in this scanner,
but its presence is necessary. */
struct yy_trans_info
@@ -367,28 +358,29 @@
flex_int32_t yy_verify;
flex_int32_t yy_nxt;
};
-static yyconst flex_int16_t yy_accept[160] =
+static const flex_int16_t yy_accept[162] =
{ 0,
- 0, 0, 39, 37, 1, 3, 37, 37, 37, 32,
- 32, 30, 33, 37, 33, 33, 33, 37, 37, 37,
- 37, 37, 37, 37, 37, 37, 37, 37, 1, 3,
- 37, 0, 37, 37, 0, 2, 32, 33, 37, 37,
- 37, 37, 33, 37, 37, 37, 37, 37, 37, 37,
- 24, 37, 37, 37, 37, 7, 37, 37, 37, 37,
- 37, 37, 37, 36, 36, 37, 0, 31, 37, 37,
- 16, 37, 37, 23, 28, 37, 37, 13, 37, 37,
- 22, 37, 37, 8, 10, 12, 37, 37, 20, 37,
- 21, 37, 0, 34, 4, 37, 37, 37, 37, 37,
+ 0, 0, 40, 38, 1, 3, 38, 38, 38, 33,
+ 33, 31, 34, 38, 34, 34, 34, 34, 38, 38,
+ 38, 38, 38, 38, 38, 38, 38, 38, 38, 1,
+ 3, 38, 0, 38, 38, 0, 2, 33, 34, 38,
+ 38, 7, 38, 38, 34, 38, 38, 38, 38, 38,
+ 38, 38, 25, 38, 38, 38, 38, 8, 38, 38,
+ 38, 38, 38, 38, 38, 37, 37, 38, 0, 32,
+ 38, 38, 17, 38, 38, 24, 29, 38, 38, 14,
+ 38, 38, 23, 38, 38, 9, 11, 13, 38, 38,
+ 21, 38, 22, 38, 0, 35, 4, 38, 38, 38,
- 37, 37, 37, 19, 37, 37, 37, 35, 35, 37,
- 37, 37, 37, 37, 37, 37, 14, 37, 37, 37,
- 37, 5, 17, 37, 9, 37, 11, 37, 37, 37,
- 37, 18, 26, 37, 37, 37, 37, 37, 37, 6,
- 37, 37, 37, 37, 37, 37, 37, 25, 37, 37,
- 15, 37, 27, 37, 37, 37, 37, 29, 0
+ 38, 38, 38, 38, 38, 20, 38, 38, 38, 36,
+ 36, 38, 38, 38, 38, 38, 38, 38, 15, 38,
+ 38, 38, 38, 5, 18, 38, 10, 38, 12, 38,
+ 38, 38, 38, 19, 27, 38, 38, 38, 38, 38,
+ 38, 6, 38, 38, 38, 38, 38, 38, 38, 26,
+ 38, 38, 16, 38, 28, 38, 38, 38, 38, 30,
+ 0
} ;
-static yyconst YY_CHAR yy_ec[256] =
+static const YY_CHAR yy_ec[256] =
{ 0,
1, 1, 1, 1, 1, 1, 1, 1, 2, 3,
1, 1, 4, 1, 1, 1, 1, 1, 1, 1,
@@ -420,7 +412,7 @@
1, 1, 1, 1, 1
} ;
-static yyconst YY_CHAR yy_meta[39] =
+static const YY_CHAR yy_meta[39] =
{ 0,
1, 2, 2, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
@@ -428,114 +420,114 @@
1, 1, 1, 1, 1, 1, 1, 1
} ;
-static yyconst flex_uint16_t yy_base[167] =
+static const flex_int16_t yy_base[169] =
{ 0,
- 0, 0, 227, 0, 224, 228, 222, 37, 41, 38,
- 187, 0, 44, 209, 54, 78, 60, 201, 196, 45,
- 203, 192, 42, 47, 197, 62, 184, 0, 214, 228,
- 77, 210, 88, 69, 211, 228, 0, 87, 104, 198,
- 187, 176, 93, 183, 178, 188, 179, 186, 186, 180,
- 186, 171, 171, 175, 177, 0, 173, 167, 173, 177,
- 169, 175, 174, 0, 228, 101, 186, 0, 179, 159,
- 172, 162, 169, 0, 0, 164, 164, 0, 162, 152,
- 0, 156, 151, 0, 0, 0, 154, 153, 0, 144,
- 0, 171, 170, 0, 0, 155, 154, 147, 139, 149,
+ 0, 0, 231, 0, 228, 232, 226, 37, 41, 38,
+ 191, 0, 44, 213, 54, 58, 82, 64, 205, 200,
+ 65, 207, 196, 26, 49, 201, 48, 188, 0, 218,
+ 232, 93, 214, 97, 67, 215, 232, 0, 72, 108,
+ 202, 0, 191, 180, 77, 187, 182, 192, 183, 190,
+ 190, 184, 190, 175, 175, 179, 181, 0, 177, 171,
+ 177, 181, 173, 179, 178, 0, 232, 102, 190, 0,
+ 183, 163, 176, 166, 173, 0, 0, 168, 168, 0,
+ 166, 156, 0, 160, 155, 0, 0, 0, 158, 157,
+ 0, 148, 0, 175, 174, 0, 0, 159, 158, 151,
- 137, 143, 148, 0, 133, 136, 126, 0, 228, 137,
- 141, 133, 135, 131, 133, 138, 0, 122, 122, 121,
- 118, 0, 0, 133, 0, 117, 134, 128, 132, 113,
- 113, 0, 0, 120, 112, 110, 121, 94, 95, 0,
- 94, 92, 97, 86, 85, 84, 76, 0, 71, 78,
- 0, 67, 0, 61, 55, 32, 29, 0, 228, 40,
- 129, 131, 133, 135, 137, 139
+ 143, 153, 141, 147, 152, 0, 137, 140, 130, 0,
+ 232, 141, 145, 137, 139, 135, 137, 142, 0, 126,
+ 126, 125, 122, 0, 0, 137, 0, 121, 138, 132,
+ 136, 117, 117, 0, 0, 124, 116, 114, 125, 111,
+ 112, 0, 117, 97, 102, 91, 92, 93, 80, 0,
+ 76, 89, 0, 92, 0, 86, 80, 43, 45, 0,
+ 232, 40, 130, 132, 134, 136, 138, 140
} ;
-static yyconst flex_int16_t yy_def[167] =
+static const flex_int16_t yy_def[169] =
{ 0,
- 159, 1, 159, 160, 159, 159, 160, 161, 162, 160,
- 10, 160, 10, 160, 10, 10, 10, 160, 160, 160,
- 160, 160, 160, 160, 160, 160, 160, 160, 159, 159,
- 161, 163, 164, 162, 165, 159, 10, 10, 10, 160,
- 160, 160, 10, 160, 160, 160, 160, 160, 160, 160,
- 160, 160, 160, 160, 160, 160, 160, 160, 160, 160,
- 160, 160, 160, 160, 159, 164, 166, 39, 160, 160,
- 160, 160, 160, 160, 160, 160, 160, 160, 160, 160,
- 160, 160, 160, 160, 160, 160, 160, 160, 160, 160,
- 160, 160, 159, 160, 160, 160, 160, 160, 160, 160,
+ 161, 1, 161, 162, 161, 161, 162, 163, 164, 162,
+ 10, 162, 10, 162, 10, 10, 10, 10, 162, 162,
+ 162, 162, 162, 162, 162, 162, 162, 162, 162, 161,
+ 161, 163, 165, 166, 164, 167, 161, 10, 10, 10,
+ 162, 162, 162, 162, 10, 162, 162, 162, 162, 162,
+ 162, 162, 162, 162, 162, 162, 162, 162, 162, 162,
+ 162, 162, 162, 162, 162, 162, 161, 166, 168, 40,
+ 162, 162, 162, 162, 162, 162, 162, 162, 162, 162,
+ 162, 162, 162, 162, 162, 162, 162, 162, 162, 162,
+ 162, 162, 162, 162, 161, 162, 162, 162, 162, 162,
- 160, 160, 160, 160, 160, 160, 160, 160, 159, 160,
- 160, 160, 160, 160, 160, 160, 160, 160, 160, 160,
- 160, 160, 160, 160, 160, 160, 160, 160, 160, 160,
- 160, 160, 160, 160, 160, 160, 160, 160, 160, 160,
- 160, 160, 160, 160, 160, 160, 160, 160, 160, 160,
- 160, 160, 160, 160, 160, 160, 160, 160, 0, 159,
- 159, 159, 159, 159, 159, 159
+ 162, 162, 162, 162, 162, 162, 162, 162, 162, 162,
+ 161, 162, 162, 162, 162, 162, 162, 162, 162, 162,
+ 162, 162, 162, 162, 162, 162, 162, 162, 162, 162,
+ 162, 162, 162, 162, 162, 162, 162, 162, 162, 162,
+ 162, 162, 162, 162, 162, 162, 162, 162, 162, 162,
+ 162, 162, 162, 162, 162, 162, 162, 162, 162, 162,
+ 0, 161, 161, 161, 161, 161, 161, 161
} ;
-static yyconst flex_uint16_t yy_nxt[267] =
+static const flex_int16_t yy_nxt[271] =
{ 0,
4, 5, 6, 7, 8, 9, 10, 11, 10, 12,
- 13, 13, 14, 4, 4, 4, 13, 13, 15, 16,
- 17, 13, 18, 19, 20, 21, 22, 4, 23, 24,
- 4, 25, 26, 4, 27, 4, 4, 4, 32, 32,
- 28, 33, 35, 36, 37, 37, 37, 158, 38, 38,
- 38, 38, 38, 49, 38, 38, 38, 38, 38, 38,
- 38, 38, 38, 55, 157, 57, 38, 38, 38, 56,
- 35, 36, 50, 51, 58, 156, 52, 41, 32, 32,
- 155, 64, 154, 42, 38, 38, 38, 46, 60, 67,
- 67, 61, 28, 38, 38, 38, 62, 153, 43, 38,
+ 13, 13, 14, 4, 4, 4, 15, 13, 16, 17,
+ 18, 13, 19, 20, 21, 22, 23, 4, 24, 25,
+ 4, 26, 27, 4, 28, 4, 4, 4, 33, 33,
+ 29, 34, 36, 37, 38, 38, 38, 57, 39, 39,
+ 39, 39, 39, 58, 39, 39, 39, 39, 39, 39,
+ 39, 39, 39, 160, 39, 39, 39, 59, 36, 37,
+ 39, 39, 39, 51, 62, 159, 60, 63, 39, 39,
+ 39, 43, 64, 39, 39, 39, 42, 44, 39, 39,
+ 39, 48, 52, 53, 33, 33, 54, 66, 69, 69,
- 38, 38, 67, 67, 152, 92, 44, 151, 150, 45,
- 68, 68, 68, 149, 68, 68, 148, 147, 146, 145,
- 68, 68, 68, 68, 68, 68, 144, 143, 72, 31,
- 31, 34, 34, 32, 32, 66, 66, 35, 35, 67,
- 67, 142, 141, 140, 139, 138, 137, 136, 135, 134,
- 133, 132, 131, 130, 129, 128, 127, 126, 125, 124,
- 123, 122, 121, 120, 119, 118, 117, 116, 115, 114,
- 113, 112, 111, 110, 109, 108, 107, 106, 105, 104,
- 103, 102, 101, 100, 99, 98, 97, 96, 95, 94,
- 93, 91, 90, 89, 88, 87, 86, 85, 84, 83,
+ 158, 29, 45, 69, 69, 157, 94, 156, 155, 154,
+ 46, 153, 74, 47, 70, 70, 70, 152, 70, 70,
+ 151, 150, 149, 148, 70, 70, 70, 70, 70, 70,
+ 32, 32, 35, 35, 33, 33, 68, 68, 36, 36,
+ 69, 69, 147, 146, 145, 144, 143, 142, 141, 140,
+ 139, 138, 137, 136, 135, 134, 133, 132, 131, 130,
+ 129, 128, 127, 126, 125, 124, 123, 122, 121, 120,
+ 119, 118, 117, 116, 115, 114, 113, 112, 111, 110,
+ 109, 108, 107, 106, 105, 104, 103, 102, 101, 100,
+ 99, 98, 97, 96, 95, 93, 92, 91, 90, 89,
- 82, 81, 80, 79, 78, 77, 76, 75, 74, 73,
- 71, 70, 69, 36, 65, 29, 63, 59, 54, 53,
- 48, 47, 40, 39, 30, 29, 159, 3, 159, 159,
- 159, 159, 159, 159, 159, 159, 159, 159, 159, 159,
- 159, 159, 159, 159, 159, 159, 159, 159, 159, 159,
- 159, 159, 159, 159, 159, 159, 159, 159, 159, 159,
- 159, 159, 159, 159, 159, 159
+ 88, 87, 86, 85, 84, 83, 82, 81, 80, 79,
+ 78, 77, 76, 75, 73, 72, 71, 37, 67, 30,
+ 65, 61, 56, 55, 50, 49, 41, 40, 31, 30,
+ 161, 3, 161, 161, 161, 161, 161, 161, 161, 161,
+ 161, 161, 161, 161, 161, 161, 161, 161, 161, 161,
+ 161, 161, 161, 161, 161, 161, 161, 161, 161, 161,
+ 161, 161, 161, 161, 161, 161, 161, 161, 161, 161
} ;
-static yyconst flex_int16_t yy_chk[267] =
+static const flex_int16_t yy_chk[271] =
{ 0,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 8, 8,
- 160, 8, 9, 9, 10, 10, 10, 157, 10, 10,
- 13, 13, 13, 20, 10, 10, 10, 10, 10, 10,
- 15, 15, 15, 23, 156, 24, 17, 17, 17, 23,
- 34, 34, 20, 20, 24, 155, 20, 15, 31, 31,
- 154, 31, 152, 15, 16, 16, 16, 17, 26, 33,
- 33, 26, 33, 38, 38, 38, 26, 150, 16, 43,
+ 162, 8, 9, 9, 10, 10, 10, 24, 10, 10,
+ 13, 13, 13, 24, 10, 10, 10, 10, 10, 10,
+ 15, 15, 15, 159, 16, 16, 16, 25, 35, 35,
+ 18, 18, 18, 21, 27, 158, 25, 27, 39, 39,
+ 39, 16, 27, 45, 45, 45, 15, 16, 17, 17,
+ 17, 18, 21, 21, 32, 32, 21, 32, 34, 34,
- 43, 43, 66, 66, 149, 66, 16, 147, 146, 16,
- 39, 39, 39, 145, 39, 39, 144, 143, 142, 141,
- 39, 39, 39, 39, 39, 39, 139, 138, 43, 161,
- 161, 162, 162, 163, 163, 164, 164, 165, 165, 166,
- 166, 137, 136, 135, 134, 131, 130, 129, 128, 127,
- 126, 124, 121, 120, 119, 118, 116, 115, 114, 113,
- 112, 111, 110, 107, 106, 105, 103, 102, 101, 100,
- 99, 98, 97, 96, 93, 92, 90, 88, 87, 83,
- 82, 80, 79, 77, 76, 73, 72, 71, 70, 69,
- 67, 63, 62, 61, 60, 59, 58, 57, 55, 54,
+ 157, 34, 17, 68, 68, 156, 68, 154, 152, 151,
+ 17, 149, 45, 17, 40, 40, 40, 148, 40, 40,
+ 147, 146, 145, 144, 40, 40, 40, 40, 40, 40,
+ 163, 163, 164, 164, 165, 165, 166, 166, 167, 167,
+ 168, 168, 143, 141, 140, 139, 138, 137, 136, 133,
+ 132, 131, 130, 129, 128, 126, 123, 122, 121, 120,
+ 118, 117, 116, 115, 114, 113, 112, 109, 108, 107,
+ 105, 104, 103, 102, 101, 100, 99, 98, 95, 94,
+ 92, 90, 89, 85, 84, 82, 81, 79, 78, 75,
+ 74, 73, 72, 71, 69, 65, 64, 63, 62, 61,
- 53, 52, 51, 50, 49, 48, 47, 46, 45, 44,
- 42, 41, 40, 35, 32, 29, 27, 25, 22, 21,
- 19, 18, 14, 11, 7, 5, 3, 159, 159, 159,
- 159, 159, 159, 159, 159, 159, 159, 159, 159, 159,
- 159, 159, 159, 159, 159, 159, 159, 159, 159, 159,
- 159, 159, 159, 159, 159, 159, 159, 159, 159, 159,
- 159, 159, 159, 159, 159, 159
+ 60, 59, 57, 56, 55, 54, 53, 52, 51, 50,
+ 49, 48, 47, 46, 44, 43, 41, 36, 33, 30,
+ 28, 26, 23, 22, 20, 19, 14, 11, 7, 5,
+ 3, 161, 161, 161, 161, 161, 161, 161, 161, 161,
+ 161, 161, 161, 161, 161, 161, 161, 161, 161, 161,
+ 161, 161, 161, 161, 161, 161, 161, 161, 161, 161,
+ 161, 161, 161, 161, 161, 161, 161, 161, 161, 161
} ;
static yy_state_type yy_last_accepting_state;
@@ -586,36 +578,36 @@
#define YY_EXTRA_TYPE void *
#endif
-static int yy_init_globals (void );
+static int yy_init_globals ( void );
/* Accessor methods to globals.
These are made visible to non-reentrant scanners for convenience. */
-int yylex_destroy (void );
+int yylex_destroy ( void );
-int yyget_debug (void );
+int yyget_debug ( void );
-void yyset_debug (int debug_flag );
+void yyset_debug ( int debug_flag );
-YY_EXTRA_TYPE yyget_extra (void );
+YY_EXTRA_TYPE yyget_extra ( void );
-void yyset_extra (YY_EXTRA_TYPE user_defined );
+void yyset_extra ( YY_EXTRA_TYPE user_defined );
-FILE *yyget_in (void );
+FILE *yyget_in ( void );
-void yyset_in (FILE * _in_str );
+void yyset_in ( FILE * _in_str );
-FILE *yyget_out (void );
+FILE *yyget_out ( void );
-void yyset_out (FILE * _out_str );
+void yyset_out ( FILE * _out_str );
- int yyget_leng (void );
+ int yyget_leng ( void );
-char *yyget_text (void );
+char *yyget_text ( void );
-int yyget_lineno (void );
+int yyget_lineno ( void );
-void yyset_lineno (int _line_number );
+void yyset_lineno ( int _line_number );
/* Macros after this point can all be overridden by user definitions in
* section 1.
@@ -623,32 +615,31 @@
#ifndef YY_SKIP_YYWRAP
#ifdef __cplusplus
-extern "C" int yywrap (void );
+extern "C" int yywrap ( void );
#else
-extern int yywrap (void );
+extern int yywrap ( void );
#endif
#endif
#ifndef YY_NO_UNPUT
- static void yyunput (int c,char *buf_ptr );
+ static void yyunput ( int c, char *buf_ptr );
#endif
#ifndef yytext_ptr
-static void yy_flex_strncpy (char *,yyconst char *,int );
+static void yy_flex_strncpy ( char *, const char *, int );
#endif
#ifdef YY_NEED_STRLEN
-static int yy_flex_strlen (yyconst char * );
+static int yy_flex_strlen ( const char * );
#endif
#ifndef YY_NO_INPUT
-
#ifdef __cplusplus
-static int yyinput (void );
+static int yyinput ( void );
#else
-static int input (void );
+static int input ( void );
#endif
#endif
@@ -781,10 +772,10 @@
if ( ! YY_CURRENT_BUFFER ) {
yyensure_buffer_stack ();
YY_CURRENT_BUFFER_LVALUE =
- yy_create_buffer(yyin,YY_BUF_SIZE );
+ yy_create_buffer( yyin, YY_BUF_SIZE );
}
- yy_load_buffer_state( );
+ yy_load_buffer_state( );
}
{
@@ -814,13 +805,13 @@
while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state )
{
yy_current_state = (int) yy_def[yy_current_state];
- if ( yy_current_state >= 160 )
- yy_c = yy_meta[(unsigned int) yy_c];
+ if ( yy_current_state >= 162 )
+ yy_c = yy_meta[yy_c];
}
- yy_current_state = yy_nxt[yy_base[yy_current_state] + (flex_int16_t) yy_c];
+ yy_current_state = yy_nxt[yy_base[yy_current_state] + yy_c];
++yy_cp;
}
- while ( yy_base[yy_current_state] != 228 );
+ while ( yy_base[yy_current_state] != 232 );
yy_find_action:
yy_act = yy_accept[yy_current_state];
@@ -872,103 +863,103 @@
YY_BREAK
case 7:
YY_RULE_SETUP
-{yylval.number=1; return(BOOL);}
+{return(MNEMONIC);}
YY_BREAK
case 8:
YY_RULE_SETUP
-{yylval.number=0; return(BOOL);}
+{yylval.number=1; return(BOOL);}
YY_BREAK
case 9:
YY_RULE_SETUP
-{yylval.number=3; return(HIDDEN);}
+{yylval.number=0; return(BOOL);}
YY_BREAK
case 10:
YY_RULE_SETUP
-{yylval.number=PCI; return(BUS);}
+{yylval.number=3; return(HIDDEN);}
YY_BREAK
case 11:
YY_RULE_SETUP
-{yylval.number=IOAPIC; return(BUS);}
+{yylval.number=PCI; return(BUS);}
YY_BREAK
case 12:
YY_RULE_SETUP
-{yylval.number=PNP; return(BUS);}
+{yylval.number=IOAPIC; return(BUS);}
YY_BREAK
case 13:
YY_RULE_SETUP
-{yylval.number=I2C; return(BUS);}
+{yylval.number=PNP; return(BUS);}
YY_BREAK
case 14:
YY_RULE_SETUP
-{yylval.number=APIC; return(BUS);}
+{yylval.number=I2C; return(BUS);}
YY_BREAK
case 15:
YY_RULE_SETUP
-{yylval.number=CPU_CLUSTER; return(BUS);}
+{yylval.number=APIC; return(BUS);}
YY_BREAK
case 16:
YY_RULE_SETUP
-{yylval.number=CPU; return(BUS);}
+{yylval.number=CPU_CLUSTER; return(BUS);}
YY_BREAK
case 17:
YY_RULE_SETUP
-{yylval.number=DOMAIN; return(BUS);}
+{yylval.number=CPU; return(BUS);}
YY_BREAK
case 18:
YY_RULE_SETUP
-{yylval.number=GENERIC; return(BUS);}
+{yylval.number=DOMAIN; return(BUS);}
YY_BREAK
case 19:
YY_RULE_SETUP
-{yylval.number=MMIO; return(BUS);}
+{yylval.number=GENERIC; return(BUS);}
YY_BREAK
case 20:
YY_RULE_SETUP
-{yylval.number=SPI; return(BUS);}
+{yylval.number=MMIO; return(BUS);}
YY_BREAK
case 21:
YY_RULE_SETUP
-{yylval.number=USB; return(BUS);}
+{yylval.number=SPI; return(BUS);}
YY_BREAK
case 22:
YY_RULE_SETUP
-{yylval.number=IRQ; return(RESOURCE);}
+{yylval.number=USB; return(BUS);}
YY_BREAK
case 23:
YY_RULE_SETUP
-{yylval.number=DRQ; return(RESOURCE);}
+{yylval.number=IRQ; return(RESOURCE);}
YY_BREAK
case 24:
YY_RULE_SETUP
-{yylval.number=IO; return(RESOURCE);}
+{yylval.number=DRQ; return(RESOURCE);}
YY_BREAK
case 25:
YY_RULE_SETUP
-{return(IOAPIC_IRQ);}
+{yylval.number=IO; return(RESOURCE);}
YY_BREAK
case 26:
YY_RULE_SETUP
-{return(INHERIT);}
+{return(IOAPIC_IRQ);}
YY_BREAK
case 27:
YY_RULE_SETUP
-{return(SUBSYSTEMID);}
+{return(INHERIT);}
YY_BREAK
case 28:
YY_RULE_SETUP
-{return(END);}
+{return(SUBSYSTEMID);}
YY_BREAK
case 29:
YY_RULE_SETUP
-{return(SLOT_DESC);}
+{return(END);}
YY_BREAK
case 30:
YY_RULE_SETUP
-{return(EQUALS);}
+{return(SLOT_DESC);}
YY_BREAK
case 31:
YY_RULE_SETUP
-{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);}
+{return(EQUALS);}
YY_BREAK
case 32:
YY_RULE_SETUP
@@ -980,12 +971,11 @@
YY_BREAK
case 34:
YY_RULE_SETUP
-{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(PCIINT);}
+{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);}
YY_BREAK
case 35:
-/* rule 35 can match eol */
YY_RULE_SETUP
-{yylval.string = malloc(yyleng-1); strncpy(yylval.string, yytext+1, yyleng-2); yylval.string[yyleng-2]='\0'; return(STRING);}
+{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(PCIINT);}
YY_BREAK
case 36:
/* rule 36 can match eol */
@@ -993,10 +983,15 @@
{yylval.string = malloc(yyleng-1); strncpy(yylval.string, yytext+1, yyleng-2); yylval.string[yyleng-2]='\0'; return(STRING);}
YY_BREAK
case 37:
+/* rule 37 can match eol */
+YY_RULE_SETUP
+{yylval.string = malloc(yyleng-1); strncpy(yylval.string, yytext+1, yyleng-2); yylval.string[yyleng-2]='\0'; return(STRING);}
+ YY_BREAK
+case 38:
YY_RULE_SETUP
{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(STRING);}
YY_BREAK
-case 38:
+case 39:
YY_RULE_SETUP
ECHO;
YY_BREAK
@@ -1077,7 +1072,7 @@
{
(yy_did_buffer_switch_on_eof) = 0;
- if ( yywrap( ) )
+ if ( yywrap( ) )
{
/* Note: because we've taken care in
* yy_get_next_buffer() to have set up
@@ -1144,7 +1139,7 @@
{
char *dest = YY_CURRENT_BUFFER_LVALUE->yy_ch_buf;
char *source = (yytext_ptr);
- yy_size_t number_to_move, i;
+ int number_to_move, i;
int ret_val;
if ( (yy_c_buf_p) > &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars) + 1] )
@@ -1173,7 +1168,7 @@
/* Try to read more data. */
/* First move last chars to start of buffer. */
- number_to_move = (yy_size_t) ((yy_c_buf_p) - (yytext_ptr)) - 1;
+ number_to_move = (int) ((yy_c_buf_p) - (yytext_ptr) - 1);
for ( i = 0; i < number_to_move; ++i )
*(dest++) = *(source++);
@@ -1209,7 +1204,8 @@
b->yy_ch_buf = (char *)
/* Include room in for 2 EOB chars. */
- yyrealloc((void *) b->yy_ch_buf,(yy_size_t) (b->yy_buf_size + 2) );
+ yyrealloc( (void *) b->yy_ch_buf,
+ (yy_size_t) (b->yy_buf_size + 2) );
}
else
/* Can't grow it, we don't own it. */
@@ -1241,7 +1237,7 @@
if ( number_to_move == YY_MORE_ADJ )
{
ret_val = EOB_ACT_END_OF_FILE;
- yyrestart(yyin );
+ yyrestart( yyin );
}
else
@@ -1255,12 +1251,15 @@
else
ret_val = EOB_ACT_CONTINUE_SCAN;
- if ((int) ((yy_n_chars) + number_to_move) > YY_CURRENT_BUFFER_LVALUE->yy_buf_size) {
+ if (((yy_n_chars) + number_to_move) > YY_CURRENT_BUFFER_LVALUE->yy_buf_size) {
/* Extend the array by 50%, plus the number we really need. */
int new_size = (yy_n_chars) + number_to_move + ((yy_n_chars) >> 1);
- YY_CURRENT_BUFFER_LVALUE->yy_ch_buf = (char *) yyrealloc((void *) YY_CURRENT_BUFFER_LVALUE->yy_ch_buf,(yy_size_t) new_size );
+ YY_CURRENT_BUFFER_LVALUE->yy_ch_buf = (char *) yyrealloc(
+ (void *) YY_CURRENT_BUFFER_LVALUE->yy_ch_buf, (yy_size_t) new_size );
if ( ! YY_CURRENT_BUFFER_LVALUE->yy_ch_buf )
YY_FATAL_ERROR( "out of dynamic memory in yy_get_next_buffer()" );
+ /* "- 2" to take care of EOB's */
+ YY_CURRENT_BUFFER_LVALUE->yy_buf_size = (int) (new_size - 2);
}
(yy_n_chars) += number_to_move;
@@ -1292,10 +1291,10 @@
while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state )
{
yy_current_state = (int) yy_def[yy_current_state];
- if ( yy_current_state >= 160 )
- yy_c = yy_meta[(unsigned int) yy_c];
+ if ( yy_current_state >= 162 )
+ yy_c = yy_meta[yy_c];
}
- yy_current_state = yy_nxt[yy_base[yy_current_state] + (flex_int16_t) yy_c];
+ yy_current_state = yy_nxt[yy_base[yy_current_state] + yy_c];
}
return yy_current_state;
@@ -1320,11 +1319,11 @@
while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state )
{
yy_current_state = (int) yy_def[yy_current_state];
- if ( yy_current_state >= 160 )
- yy_c = yy_meta[(unsigned int) yy_c];
+ if ( yy_current_state >= 162 )
+ yy_c = yy_meta[yy_c];
}
- yy_current_state = yy_nxt[yy_base[yy_current_state] + (flex_int16_t) yy_c];
- yy_is_jam = (yy_current_state == 159);
+ yy_current_state = yy_nxt[yy_base[yy_current_state] + yy_c];
+ yy_is_jam = (yy_current_state == 161);
return yy_is_jam ? 0 : yy_current_state;
}
@@ -1394,7 +1393,7 @@
else
{ /* need more input */
- int offset = (yy_c_buf_p) - (yytext_ptr);
+ int offset = (int) ((yy_c_buf_p) - (yytext_ptr));
++(yy_c_buf_p);
switch ( yy_get_next_buffer( ) )
@@ -1411,13 +1410,13 @@
*/
/* Reset buffer status. */
- yyrestart(yyin );
+ yyrestart( yyin );
/*FALLTHROUGH*/
case EOB_ACT_END_OF_FILE:
{
- if ( yywrap( ) )
+ if ( yywrap( ) )
return 0;
if ( ! (yy_did_buffer_switch_on_eof) )
@@ -1455,11 +1454,11 @@
if ( ! YY_CURRENT_BUFFER ){
yyensure_buffer_stack ();
YY_CURRENT_BUFFER_LVALUE =
- yy_create_buffer(yyin,YY_BUF_SIZE );
+ yy_create_buffer( yyin, YY_BUF_SIZE );
}
- yy_init_buffer(YY_CURRENT_BUFFER,input_file );
- yy_load_buffer_state( );
+ yy_init_buffer( YY_CURRENT_BUFFER, input_file );
+ yy_load_buffer_state( );
}
/** Switch to a different input buffer.
@@ -1487,7 +1486,7 @@
}
YY_CURRENT_BUFFER_LVALUE = new_buffer;
- yy_load_buffer_state( );
+ yy_load_buffer_state( );
/* We don't actually know whether we did this switch during
* EOF (yywrap()) processing, but the only time this flag
@@ -1515,7 +1514,7 @@
{
YY_BUFFER_STATE b;
- b = (YY_BUFFER_STATE) yyalloc(sizeof( struct yy_buffer_state ) );
+ b = (YY_BUFFER_STATE) yyalloc( sizeof( struct yy_buffer_state ) );
if ( ! b )
YY_FATAL_ERROR( "out of dynamic memory in yy_create_buffer()" );
@@ -1524,13 +1523,13 @@
/* yy_ch_buf has to be 2 characters longer than the size given because
* we need to put in 2 end-of-buffer characters.
*/
- b->yy_ch_buf = (char *) yyalloc((yy_size_t) (b->yy_buf_size + 2) );
+ b->yy_ch_buf = (char *) yyalloc( (yy_size_t) (b->yy_buf_size + 2) );
if ( ! b->yy_ch_buf )
YY_FATAL_ERROR( "out of dynamic memory in yy_create_buffer()" );
b->yy_is_our_buffer = 1;
- yy_init_buffer(b,file );
+ yy_init_buffer( b, file );
return b;
}
@@ -1549,9 +1548,9 @@
YY_CURRENT_BUFFER_LVALUE = (YY_BUFFER_STATE) 0;
if ( b->yy_is_our_buffer )
- yyfree((void *) b->yy_ch_buf );
+ yyfree( (void *) b->yy_ch_buf );
- yyfree((void *) b );
+ yyfree( (void *) b );
}
/* Initializes or reinitializes a buffer.
@@ -1563,7 +1562,7 @@
{
int oerrno = errno;
- yy_flush_buffer(b );
+ yy_flush_buffer( b );
b->yy_input_file = file;
b->yy_fill_buffer = 1;
@@ -1606,7 +1605,7 @@
b->yy_buffer_status = YY_BUFFER_NEW;
if ( b == YY_CURRENT_BUFFER )
- yy_load_buffer_state( );
+ yy_load_buffer_state( );
}
/** Pushes the new state onto the stack. The new state becomes
@@ -1637,7 +1636,7 @@
YY_CURRENT_BUFFER_LVALUE = new_buffer;
/* copied from yy_switch_to_buffer. */
- yy_load_buffer_state( );
+ yy_load_buffer_state( );
(yy_did_buffer_switch_on_eof) = 1;
}
@@ -1656,7 +1655,7 @@
--(yy_buffer_stack_top);
if (YY_CURRENT_BUFFER) {
- yy_load_buffer_state( );
+ yy_load_buffer_state( );
(yy_did_buffer_switch_on_eof) = 1;
}
}
@@ -1666,7 +1665,7 @@
*/
static void yyensure_buffer_stack (void)
{
- int num_to_alloc;
+ yy_size_t num_to_alloc;
if (!(yy_buffer_stack)) {
@@ -1723,7 +1722,7 @@
/* They forgot to leave room for the EOB's. */
return NULL;
- b = (YY_BUFFER_STATE) yyalloc(sizeof( struct yy_buffer_state ) );
+ b = (YY_BUFFER_STATE) yyalloc( sizeof( struct yy_buffer_state ) );
if ( ! b )
YY_FATAL_ERROR( "out of dynamic memory in yy_scan_buffer()" );
@@ -1737,7 +1736,7 @@
b->yy_fill_buffer = 0;
b->yy_buffer_status = YY_BUFFER_NEW;
- yy_switch_to_buffer(b );
+ yy_switch_to_buffer( b );
return b;
}
@@ -1750,10 +1749,10 @@
* @note If you want to scan bytes that may contain NUL values, then use
* yy_scan_bytes() instead.
*/
-YY_BUFFER_STATE yy_scan_string (yyconst char * yystr )
+YY_BUFFER_STATE yy_scan_string (const char * yystr )
{
- return yy_scan_bytes(yystr,(int) strlen(yystr) );
+ return yy_scan_bytes( yystr, (int) strlen(yystr) );
}
/** Setup the input buffer state to scan the given bytes. The next call to yylex() will
@@ -1763,7 +1762,7 @@
*
* @return the newly allocated buffer state object.
*/
-YY_BUFFER_STATE yy_scan_bytes (yyconst char * yybytes, int _yybytes_len )
+YY_BUFFER_STATE yy_scan_bytes (const char * yybytes, int _yybytes_len )
{
YY_BUFFER_STATE b;
char *buf;
@@ -1772,7 +1771,7 @@
/* Get memory for full buffer, including space for trailing EOB's. */
n = (yy_size_t) (_yybytes_len + 2);
- buf = (char *) yyalloc(n );
+ buf = (char *) yyalloc( n );
if ( ! buf )
YY_FATAL_ERROR( "out of dynamic memory in yy_scan_bytes()" );
@@ -1781,7 +1780,7 @@
buf[_yybytes_len] = buf[_yybytes_len+1] = YY_END_OF_BUFFER_CHAR;
- b = yy_scan_buffer(buf,n );
+ b = yy_scan_buffer( buf, n );
if ( ! b )
YY_FATAL_ERROR( "bad buffer in yy_scan_bytes()" );
@@ -1797,9 +1796,9 @@
#define YY_EXIT_FAILURE 2
#endif
-static void yynoreturn yy_fatal_error (yyconst char* msg )
+static void yynoreturn yy_fatal_error (const char* msg )
{
- (void) fprintf( stderr, "%s\n", msg );
+ fprintf( stderr, "%s\n", msg );
exit( YY_EXIT_FAILURE );
}
@@ -1810,7 +1809,7 @@
do \
{ \
/* Undo effects of setting up yytext. */ \
- yy_size_t yyless_macro_arg = (n); \
+ int yyless_macro_arg = (n); \
YY_LESS_LINENO(yyless_macro_arg);\
yytext[yyleng] = (yy_hold_char); \
(yy_c_buf_p) = yytext + yyless_macro_arg; \
@@ -1934,7 +1933,7 @@
/* Pop the buffer stack, destroying each element. */
while(YY_CURRENT_BUFFER){
- yy_delete_buffer(YY_CURRENT_BUFFER );
+ yy_delete_buffer( YY_CURRENT_BUFFER );
YY_CURRENT_BUFFER_LVALUE = NULL;
yypop_buffer_state();
}
@@ -1955,7 +1954,7 @@
*/
#ifndef yytext_ptr
-static void yy_flex_strncpy (char* s1, yyconst char * s2, int n )
+static void yy_flex_strncpy (char* s1, const char * s2, int n )
{
int i;
@@ -1965,7 +1964,7 @@
#endif
#ifdef YY_NEED_STRLEN
-static int yy_flex_strlen (yyconst char * s )
+static int yy_flex_strlen (const char * s )
{
int n;
for ( n = 0; s[n]; ++n )
diff --git a/util/sconfig/main.c b/util/sconfig/main.c
index 6b421ec..4d15c8f 100644
--- a/util/sconfig/main.c
+++ b/util/sconfig/main.c
@@ -483,9 +483,9 @@
struct device *new_device(struct bus *parent,
struct chip_instance *chip_instance,
const int bustype, const char *devnum,
- int status)
+ const char *const mnemonic, int status)
{
- char *tmp;
+ char *tmp, *name;
int path_a;
int path_b = 0;
struct device *new_d;
@@ -510,8 +510,14 @@
new_d->path_a = path_a;
new_d->path_b = path_b;
- char *name = S_ALLOC(10);
- sprintf(name, "_dev%d", new_d->id);
+ if (mnemonic) {
+ name = S_ALLOC(strlen("__static_") + strlen(mnemonic) + 1);
+ sprintf(name, "__static_%s", mnemonic);
+ new_d->has_mnemonic = 1;
+ } else {
+ name = S_ALLOC(10);
+ sprintf(name, "_dev%d", new_d->id);
+ }
new_d->name = name;
new_d->enabled = status & 0x01;
@@ -696,7 +702,7 @@
return 0;
}
-static void pass0(FILE *fil, struct device *ptr, struct device *next)
+static void pass0(FILE *fil, FILE *head, struct device *ptr, struct device *next)
{
if (ptr == &base_root_dev) {
fprintf(fil, "STORAGE struct bus %s_links[];\n",
@@ -704,7 +710,8 @@
return;
}
- fprintf(fil, "STORAGE struct device %s;\n", ptr->name);
+ if (!ptr->has_mnemonic)
+ fprintf(fil, "STORAGE struct device %s;\n", ptr->name);
if (ptr->res)
fprintf(fil, "STORAGE struct resource %s_res[];\n",
ptr->name);
@@ -781,13 +788,13 @@
fprintf(fil, "\t};\n");
}
-static void pass1(FILE *fil, struct device *ptr, struct device *next)
+static void pass1(FILE *fil, FILE *head, struct device *ptr, struct device *next)
{
int pin;
struct chip_instance *chip_ins = ptr->chip_instance;
int has_children = dev_has_children(ptr);
- if (ptr == &base_root_dev)
+ if (ptr == &base_root_dev || ptr->has_mnemonic)
fprintf(fil, "DEVTREE_CONST struct device %s = {\n", ptr->name);
else
fprintf(fil, "STORAGE struct device %s = {\n", ptr->name);
@@ -883,16 +890,25 @@
emit_dev_links(fil, ptr);
}
-static void expose_device_names(FILE *fil, struct device *ptr, struct device *next)
+static void expose_device_names(FILE *fil, FILE *head, struct device *ptr, struct device *next)
{
/* Only devices on root bus here. */
- if (ptr->bustype == PCI && ptr->parent->dev->bustype == DOMAIN)
+ if (ptr->bustype == PCI && ptr->parent->dev->bustype == DOMAIN) {
+ fprintf(head, "extern DEVTREE_CONST struct device *DEVTREE_CONST __pci_0_%02x_%d;\n",
+ ptr->path_a, ptr->path_b);
fprintf(fil, "DEVTREE_CONST struct device *DEVTREE_CONST __pci_0_%02x_%d = &%s;\n",
ptr->path_a, ptr->path_b, ptr->name);
+ }
- if (ptr->bustype == PNP)
+ if (ptr->bustype == PNP) {
+ fprintf(head, "extern DEVTREE_CONST struct device *DEVTREE_CONST __pnp_%04x_%02x;\n",
+ ptr->path_a, ptr->path_b);
fprintf(fil, "DEVTREE_CONST struct device *DEVTREE_CONST __pnp_%04x_%02x = &%s;\n",
ptr->path_a, ptr->path_b, ptr->name);
+ }
+
+ if (ptr->has_mnemonic)
+ fprintf(head, "extern DEVTREE_CONST struct device %s;\n", ptr->name);
}
static void add_siblings_to_queue(struct queue_entry **bfs_q_head,
@@ -916,8 +932,8 @@
}
}
-static void walk_device_tree(FILE *fil, struct device *ptr,
- void (*func)(FILE *, struct device *,
+static void walk_device_tree(FILE *fil, FILE *head, struct device *ptr,
+ void (*func)(FILE *, FILE *, struct device *,
struct device *))
{
struct queue_entry *bfs_q_head = NULL;
@@ -926,7 +942,7 @@
while ((ptr = dequeue_head(&bfs_q_head))) {
add_children_to_queue(&bfs_q_head, ptr);
- func(fil, ptr, peek_queue_head(bfs_q_head));
+ func(fil, head, ptr, peek_queue_head(bfs_q_head));
}
}
@@ -995,7 +1011,7 @@
}
}
-static void inherit_subsystem_ids(FILE *file, struct device *dev,
+static void inherit_subsystem_ids(FILE *file, FILE *head, struct device *dev,
struct device *next)
{
struct device *p;
@@ -1360,11 +1376,13 @@
int main(int argc, char **argv)
{
+ unsigned int i;
+
if ((argc < MANDATORY_ARG_COUNT) || (argc > TOTAL_ARG_COUNT))
usage();
const char *base_devtree = argv[DEVICEFILE_ARG];
- const char *outputc = argv[OUTPUTFILE_ARG];
+ char *outputf = argv[OUTPUTFILE_ARG];
const char *override_devtree;
parse_devicetree(base_devtree, &base_root_bus);
@@ -1381,26 +1399,49 @@
override_devicetree(&base_root_bus, &override_root_bus);
}
- FILE *autogen = fopen(outputc, "w");
+ FILE *autogen = fopen(outputf, "w");
if (!autogen) {
fprintf(stderr, "Could not open file '%s' for writing: ",
- outputc);
+ outputf);
perror(NULL);
exit(1);
}
+ outputf[strlen(outputf) - 1] = 'h';
+ FILE *autohead = fopen(outputf, "w");
+ if (!autohead) {
+ fprintf(stderr, "Could not open file '%s' for writing: ", outputf);
+ perror(NULL);
+ fclose(autogen);
+ exit(1);
+ }
+ fprintf(autohead, "#ifndef __STATIC_DEVICE_TREE_H\n");
+ fprintf(autohead, "#define __STATIC_DEVICE_TREE_H\n\n");
+ fprintf(autohead, "#include <device/device.h>\n\n");
+
+ char *header_name = outputf;
+ for (i = strlen(outputf) - 1; i > 0; --i) {
+ if (outputf[i] == '/') {
+ header_name = outputf + i + 1;
+ break;
+ }
+ }
+ fprintf(autogen, "#include \"%s\"\n", header_name);
+
emit_chips(autogen);
- walk_device_tree(autogen, &base_root_dev, inherit_subsystem_ids);
+ walk_device_tree(autogen, autohead, &base_root_dev, inherit_subsystem_ids);
fprintf(autogen, "\n/* pass 0 */\n");
- walk_device_tree(autogen, &base_root_dev, pass0);
+ walk_device_tree(autogen, autohead, &base_root_dev, pass0);
fprintf(autogen, "\n/* pass 1 */\n");
- walk_device_tree(autogen, &base_root_dev, pass1);
+ walk_device_tree(autogen, autohead, &base_root_dev, pass1);
/* Expose static devicenames to global namespace. */
fprintf(autogen, "\n/* expose_device_names */\n");
- walk_device_tree(autogen, &base_root_dev, expose_device_names);
+ walk_device_tree(autogen, autohead, &base_root_dev, expose_device_names);
+ fprintf(autohead, "\n#endif /* __STATIC_DEVICE_TREE_H */\n");
+ fclose(autohead);
fclose(autogen);
return 0;
diff --git a/util/sconfig/sconfig.h b/util/sconfig/sconfig.h
index eea2a14..ca834e8 100644
--- a/util/sconfig/sconfig.h
+++ b/util/sconfig/sconfig.h
@@ -112,6 +112,7 @@
/* Name of this device. */
char *name;
+ int has_mnemonic;
/* Path of this device. */
char *path;
@@ -159,7 +160,7 @@
struct device *new_device(struct bus *parent,
struct chip_instance *chip_instance,
const int bustype, const char *devnum,
- int status);
+ const char *mnemonic, int status);
void add_resource(struct bus *bus, int type, int index, int base);
diff --git a/util/sconfig/sconfig.l b/util/sconfig/sconfig.l
index 87de6e2..4752cca 100755
--- a/util/sconfig/sconfig.l
+++ b/util/sconfig/sconfig.l
@@ -27,6 +27,7 @@
chip {return(CHIP);}
device {return(DEVICE);}
register {return(REGISTER);}
+as {return(MNEMONIC);}
on {yylval.number=1; return(BOOL);}
off {yylval.number=0; return(BOOL);}
hidden {yylval.number=3; return(HIDDEN);}
diff --git a/util/sconfig/sconfig.tab.c_shipped b/util/sconfig/sconfig.tab.c_shipped
index 8e1e57d..9fd57e0 100644
--- a/util/sconfig/sconfig.tab.c_shipped
+++ b/util/sconfig/sconfig.tab.c_shipped
@@ -1,8 +1,9 @@
-/* A Bison parser, made by GNU Bison 3.0.5. */
+/* A Bison parser, made by GNU Bison 3.3.2. */
/* Bison implementation for Yacc-like parsers in C
- Copyright (C) 1984, 1989-1990, 2000-2015, 2018 Free Software Foundation, Inc.
+ Copyright (C) 1984, 1989-1990, 2000-2015, 2018-2019 Free Software Foundation,
+ Inc.
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
@@ -40,11 +41,14 @@
define necessary library symbols; they are noted "INFRINGES ON
USER NAME SPACE" below. */
+/* Undocumented macros, especially those whose name start with YY_,
+ are private implementation details. Do not rely on them. */
+
/* Identify Bison output. */
#define YYBISON 1
/* Bison version. */
-#define YYBISON_VERSION "3.0.5"
+#define YYBISON_VERSION "3.3.2"
/* Skeleton name. */
#define YYSKELETON_NAME "yacc.c"
@@ -61,7 +65,7 @@
-/* Copy the first part of user declarations. */
+/* First part of user prologue. */
/*
@@ -90,12 +94,15 @@
-
# ifndef YY_NULLPTR
-# if defined __cplusplus && 201103L <= __cplusplus
-# define YY_NULLPTR nullptr
+# if defined __cplusplus
+# if 201103L <= __cplusplus
+# define YY_NULLPTR nullptr
+# else
+# define YY_NULLPTR 0
+# endif
# else
-# define YY_NULLPTR 0
+# define YY_NULLPTR ((void*)0)
# endif
# endif
@@ -109,8 +116,8 @@
/* In a future release of Bison, this section will be replaced
by #include "sconfig.tab.h_shipped". */
-#ifndef YY_YY_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED
-# define YY_YY_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED
+#ifndef YY_YY_HOME_ICON_COREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED
+# define YY_YY_HOME_ICON_COREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED
/* Debug traces. */
#ifndef YYDEBUG
# define YYDEBUG 0
@@ -127,35 +134,36 @@
CHIP = 258,
DEVICE = 259,
REGISTER = 260,
- BOOL = 261,
- HIDDEN = 262,
- BUS = 263,
- RESOURCE = 264,
- END = 265,
- EQUALS = 266,
- HEX = 267,
- STRING = 268,
- PCI = 269,
- PNP = 270,
- I2C = 271,
- APIC = 272,
- CPU_CLUSTER = 273,
- CPU = 274,
- DOMAIN = 275,
- IRQ = 276,
- DRQ = 277,
- SLOT_DESC = 278,
- IO = 279,
- NUMBER = 280,
- SUBSYSTEMID = 281,
- INHERIT = 282,
- IOAPIC_IRQ = 283,
- IOAPIC = 284,
- PCIINT = 285,
- GENERIC = 286,
- SPI = 287,
- USB = 288,
- MMIO = 289
+ MNEMONIC = 261,
+ BOOL = 262,
+ HIDDEN = 263,
+ BUS = 264,
+ RESOURCE = 265,
+ END = 266,
+ EQUALS = 267,
+ HEX = 268,
+ STRING = 269,
+ PCI = 270,
+ PNP = 271,
+ I2C = 272,
+ APIC = 273,
+ CPU_CLUSTER = 274,
+ CPU = 275,
+ DOMAIN = 276,
+ IRQ = 277,
+ DRQ = 278,
+ SLOT_DESC = 279,
+ IO = 280,
+ NUMBER = 281,
+ SUBSYSTEMID = 282,
+ INHERIT = 283,
+ IOAPIC_IRQ = 284,
+ IOAPIC = 285,
+ PCIINT = 286,
+ GENERIC = 287,
+ SPI = 288,
+ USB = 289,
+ MMIO = 290
};
#endif
@@ -184,9 +192,7 @@
int yyparse (void);
-#endif /* !YY_YY_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED */
-
-/* Copy the second part of user declarations. */
+#endif /* !YY_YY_HOME_ICON_COREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED */
@@ -209,13 +215,13 @@
#ifdef YYTYPE_UINT16
typedef YYTYPE_UINT16 yytype_uint16;
#else
-typedef unsigned short int yytype_uint16;
+typedef unsigned short yytype_uint16;
#endif
#ifdef YYTYPE_INT16
typedef YYTYPE_INT16 yytype_int16;
#else
-typedef short int yytype_int16;
+typedef short yytype_int16;
#endif
#ifndef YYSIZE_T
@@ -227,7 +233,7 @@
# include <stddef.h> /* INFRINGES ON USER NAME SPACE */
# define YYSIZE_T size_t
# else
-# define YYSIZE_T unsigned int
+# define YYSIZE_T unsigned
# endif
#endif
@@ -263,15 +269,6 @@
# define YY_ATTRIBUTE_UNUSED YY_ATTRIBUTE ((__unused__))
#endif
-#if !defined _Noreturn \
- && (!defined __STDC_VERSION__ || __STDC_VERSION__ < 201112)
-# if defined _MSC_VER && 1200 <= _MSC_VER
-# define _Noreturn __declspec (noreturn)
-# else
-# define _Noreturn YY_ATTRIBUTE ((__noreturn__))
-# endif
-#endif
-
/* Suppress unused-variable warnings by "using" E. */
#if ! defined lint || defined __GNUC__
# define YYUSE(E) ((void) (E))
@@ -279,7 +276,7 @@
# define YYUSE(E) /* empty */
#endif
-#if defined __GNUC__ && 407 <= __GNUC__ * 100 + __GNUC_MINOR__
+#if defined __GNUC__ && ! defined __ICC && 407 <= __GNUC__ * 100 + __GNUC_MINOR__
/* Suppress an incorrect diagnostic about yylval being uninitialized. */
# define YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN \
_Pragma ("GCC diagnostic push") \
@@ -430,27 +427,27 @@
/* YYFINAL -- State number of the termination state. */
#define YYFINAL 3
/* YYLAST -- Last index in YYTABLE. */
-#define YYLAST 43
+#define YYLAST 47
/* YYNTOKENS -- Number of terminals. */
-#define YYNTOKENS 35
+#define YYNTOKENS 36
/* YYNNTS -- Number of nonterminals. */
-#define YYNNTS 15
+#define YYNNTS 16
/* YYNRULES -- Number of rules. */
-#define YYNRULES 28
+#define YYNRULES 30
/* YYNSTATES -- Number of states. */
-#define YYNSTATES 49
+#define YYNSTATES 52
-/* YYTRANSLATE[YYX] -- Symbol number corresponding to YYX as returned
- by yylex, with out-of-bounds checking. */
#define YYUNDEFTOK 2
-#define YYMAXUTOK 289
+#define YYMAXUTOK 290
+/* YYTRANSLATE(TOKEN-NUM) -- Symbol number corresponding to TOKEN-NUM
+ as returned by yylex, with out-of-bounds checking. */
#define YYTRANSLATE(YYX) \
- ((unsigned int) (YYX) <= YYMAXUTOK ? yytranslate[YYX] : YYUNDEFTOK)
+ ((unsigned) (YYX) <= YYMAXUTOK ? yytranslate[YYX] : YYUNDEFTOK)
/* YYTRANSLATE[TOKEN-NUM] -- Symbol number corresponding to TOKEN-NUM
- as returned by yylex, without out-of-bounds checking. */
+ as returned by yylex. */
static const yytype_uint8 yytranslate[] =
{
0, 2, 2, 2, 2, 2, 2, 2, 2, 2,
@@ -481,7 +478,8 @@
2, 2, 2, 2, 2, 2, 1, 2, 3, 4,
5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
- 25, 26, 27, 28, 29, 30, 31, 32, 33, 34
+ 25, 26, 27, 28, 29, 30, 31, 32, 33, 34,
+ 35
};
#if YYDEBUG
@@ -490,7 +488,8 @@
{
0, 36, 36, 36, 38, 38, 38, 38, 40, 40,
40, 40, 40, 40, 40, 42, 42, 51, 51, 59,
- 59, 61, 64, 67, 70, 73, 76, 79, 82
+ 61, 65, 65, 67, 70, 73, 76, 79, 82, 85,
+ 88
};
#endif
@@ -499,14 +498,14 @@
First, the terminals, then, starting at YYNTOKENS, nonterminals. */
static const char *const yytname[] =
{
- "$end", "error", "$undefined", "CHIP", "DEVICE", "REGISTER", "BOOL",
- "HIDDEN", "BUS", "RESOURCE", "END", "EQUALS", "HEX", "STRING", "PCI",
- "PNP", "I2C", "APIC", "CPU_CLUSTER", "CPU", "DOMAIN", "IRQ", "DRQ",
- "SLOT_DESC", "IO", "NUMBER", "SUBSYSTEMID", "INHERIT", "IOAPIC_IRQ",
- "IOAPIC", "PCIINT", "GENERIC", "SPI", "USB", "MMIO", "$accept",
- "devtree", "$@1", "chipchildren", "devicechildren", "chip", "@2",
- "device", "@3", "status", "resource", "registers", "subsystemid",
- "ioapic_irq", "smbios_slot_desc", YY_NULLPTR
+ "$end", "error", "$undefined", "CHIP", "DEVICE", "REGISTER", "MNEMONIC",
+ "BOOL", "HIDDEN", "BUS", "RESOURCE", "END", "EQUALS", "HEX", "STRING",
+ "PCI", "PNP", "I2C", "APIC", "CPU_CLUSTER", "CPU", "DOMAIN", "IRQ",
+ "DRQ", "SLOT_DESC", "IO", "NUMBER", "SUBSYSTEMID", "INHERIT",
+ "IOAPIC_IRQ", "IOAPIC", "PCIINT", "GENERIC", "SPI", "USB", "MMIO",
+ "$accept", "devtree", "$@1", "chipchildren", "devicechildren", "chip",
+ "@2", "device", "@3", "mnemonic", "status", "resource", "registers",
+ "subsystemid", "ioapic_irq", "smbios_slot_desc", YY_NULLPTR
};
#endif
@@ -518,7 +517,7 @@
0, 256, 257, 258, 259, 260, 261, 262, 263, 264,
265, 266, 267, 268, 269, 270, 271, 272, 273, 274,
275, 276, 277, 278, 279, 280, 281, 282, 283, 284,
- 285, 286, 287, 288, 289
+ 285, 286, 287, 288, 289, 290
};
# endif
@@ -536,11 +535,12 @@
STATE-NUM. */
static const yytype_int8 yypact[] =
{
- -12, 11, 9, -12, 1, -12, -12, -12, 0, 5,
- 3, -12, -12, -12, -12, -10, 6, 2, 8, -12,
- -12, -12, -12, -12, -3, -1, -12, 13, 4, 7,
- -12, -12, -12, -12, -12, -12, 16, 15, 10, -11,
- 12, 17, -5, 14, -12, 18, -12, -12, -12
+ -12, 11, -1, -12, 0, -12, -12, -12, 1, 4,
+ 3, -12, -12, -12, -12, -11, 6, 10, 5, 9,
+ 2, -12, -12, -12, -12, -12, -12, -3, -6, -12,
+ 13, 7, 8, -12, -12, -12, -12, -12, -12, 16,
+ 15, 12, 14, 17, 18, 19, 20, -12, 21, -12,
+ -12, -12
};
/* YYDEFACT[STATE-NUM] -- Default reduction number in state STATE-NUM.
@@ -549,24 +549,25 @@
static const yytype_uint8 yydefact[] =
{
2, 0, 0, 1, 0, 3, 15, 7, 0, 0,
- 0, 16, 5, 4, 6, 0, 0, 0, 0, 19,
- 20, 17, 22, 14, 0, 0, 18, 0, 0, 0,
- 9, 8, 10, 11, 12, 13, 0, 0, 0, 0,
- 0, 28, 23, 0, 21, 27, 24, 25, 26
+ 0, 16, 5, 4, 6, 0, 0, 19, 0, 0,
+ 0, 24, 20, 21, 22, 17, 14, 0, 0, 18,
+ 0, 0, 0, 9, 8, 10, 11, 12, 13, 0,
+ 0, 0, 0, 0, 30, 25, 0, 23, 29, 26,
+ 27, 28
};
/* YYPGOTO[NTERM-NUM]. */
static const yytype_int8 yypgoto[] =
{
- -12, -12, -12, -12, -12, -6, -12, 19, -12, -12,
- -12, -12, -12, -12, -12
+ -12, -12, -12, -12, -12, -5, -12, -2, -12, -12,
+ -12, -12, -12, -12, -12, -12
};
/* YYDEFGOTO[NTERM-NUM]. */
static const yytype_int8 yydefgoto[] =
{
- -1, 1, 2, 8, 24, 5, 7, 13, 23, 21,
- 32, 14, 33, 34, 35
+ -1, 1, 2, 8, 27, 5, 7, 13, 26, 20,
+ 25, 35, 14, 36, 37, 38
};
/* YYTABLE[YYPACT[STATE-NUM]] -- What to do in state STATE-NUM. If
@@ -574,47 +575,50 @@
number is the opposite. If YYTABLE_NINF, syntax error. */
static const yytype_uint8 yytable[] =
{
- 4, 9, 12, 4, 9, 10, 25, 26, 19, 20,
- 11, 3, 4, 15, 6, 17, 16, 18, 30, 43,
- 27, 22, 46, 28, 36, 29, 37, 40, 41, 38,
- 45, 48, 39, 0, 0, 42, 0, 44, 0, 47,
- 0, 0, 0, 31
+ 4, 9, 4, 12, 4, 9, 10, 28, 29, 23,
+ 24, 3, 11, 15, 6, 17, 19, 16, 18, 21,
+ 39, 30, 33, 22, 31, 34, 32, 40, 43, 44,
+ 0, 0, 48, 41, 42, 51, 0, 0, 45, 0,
+ 0, 0, 0, 47, 0, 46, 50, 49
};
static const yytype_int8 yycheck[] =
{
- 3, 4, 8, 3, 4, 5, 9, 10, 6, 7,
- 10, 0, 3, 8, 13, 25, 13, 11, 24, 30,
- 23, 13, 27, 26, 25, 28, 13, 11, 13, 25,
- 13, 13, 25, -1, -1, 25, -1, 25, -1, 25,
- -1, -1, -1, 24
+ 3, 4, 3, 8, 3, 4, 5, 10, 11, 7,
+ 8, 0, 11, 9, 14, 26, 6, 14, 12, 14,
+ 26, 24, 27, 14, 27, 27, 29, 14, 12, 14,
+ -1, -1, 14, 26, 26, 14, -1, -1, 26, -1,
+ -1, -1, -1, 26, -1, 31, 26, 28
};
/* YYSTOS[STATE-NUM] -- The (internal number of the) accessing
symbol of state STATE-NUM. */
static const yytype_uint8 yystos[] =
{
- 0, 36, 37, 0, 3, 40, 13, 41, 38, 4,
- 5, 10, 40, 42, 46, 8, 13, 25, 11, 6,
- 7, 44, 13, 43, 39, 9, 10, 23, 26, 28,
- 40, 42, 45, 47, 48, 49, 25, 13, 25, 25,
- 11, 13, 25, 30, 25, 13, 27, 25, 13
+ 0, 37, 38, 0, 3, 41, 14, 42, 39, 4,
+ 5, 11, 41, 43, 48, 9, 14, 26, 12, 6,
+ 45, 14, 14, 7, 8, 46, 44, 40, 10, 11,
+ 24, 27, 29, 41, 43, 47, 49, 50, 51, 26,
+ 14, 26, 26, 12, 14, 26, 31, 26, 14, 28,
+ 26, 14
};
/* YYR1[YYN] -- Symbol number of symbol that rule YYN derives. */
static const yytype_uint8 yyr1[] =
{
- 0, 35, 37, 36, 38, 38, 38, 38, 39, 39,
- 39, 39, 39, 39, 39, 41, 40, 43, 42, 44,
- 44, 45, 46, 47, 47, 48, 49, 49, 49
+ 0, 36, 38, 37, 39, 39, 39, 39, 40, 40,
+ 40, 40, 40, 40, 40, 42, 41, 44, 43, 45,
+ 45, 46, 46, 47, 48, 49, 49, 50, 51, 51,
+ 51
};
/* YYR2[YYN] -- Number of symbols on the right hand side of rule YYN. */
static const yytype_uint8 yyr2[] =
{
0, 2, 0, 2, 2, 2, 2, 0, 2, 2,
- 2, 2, 2, 2, 0, 0, 5, 0, 7, 1,
- 1, 4, 4, 3, 4, 4, 5, 4, 3
+ 2, 2, 2, 2, 0, 0, 5, 0, 8, 0,
+ 2, 1, 1, 4, 4, 3, 4, 4, 5, 4,
+ 3
};
@@ -630,22 +634,22 @@
#define YYRECOVERING() (!!yyerrstatus)
-#define YYBACKUP(Token, Value) \
-do \
- if (yychar == YYEMPTY) \
- { \
- yychar = (Token); \
- yylval = (Value); \
- YYPOPSTACK (yylen); \
- yystate = *yyssp; \
- goto yybackup; \
- } \
- else \
- { \
- yyerror (YY_("syntax error: cannot back up")); \
- YYERROR; \
- } \
-while (0)
+#define YYBACKUP(Token, Value) \
+ do \
+ if (yychar == YYEMPTY) \
+ { \
+ yychar = (Token); \
+ yylval = (Value); \
+ YYPOPSTACK (yylen); \
+ yystate = *yyssp; \
+ goto yybackup; \
+ } \
+ else \
+ { \
+ yyerror (YY_("syntax error: cannot back up")); \
+ YYERROR; \
+ } \
+ while (0)
/* Error token number */
#define YYTERROR 1
@@ -685,37 +689,37 @@
} while (0)
-/*----------------------------------------.
-| Print this symbol's value on YYOUTPUT. |
-`----------------------------------------*/
+/*-----------------------------------.
+| Print this symbol's value on YYO. |
+`-----------------------------------*/
static void
-yy_symbol_value_print (FILE *yyoutput, int yytype, YYSTYPE const * const yyvaluep)
+yy_symbol_value_print (FILE *yyo, int yytype, YYSTYPE const * const yyvaluep)
{
- FILE *yyo = yyoutput;
- YYUSE (yyo);
+ FILE *yyoutput = yyo;
+ YYUSE (yyoutput);
if (!yyvaluep)
return;
# ifdef YYPRINT
if (yytype < YYNTOKENS)
- YYPRINT (yyoutput, yytoknum[yytype], *yyvaluep);
+ YYPRINT (yyo, yytoknum[yytype], *yyvaluep);
# endif
YYUSE (yytype);
}
-/*--------------------------------.
-| Print this symbol on YYOUTPUT. |
-`--------------------------------*/
+/*---------------------------.
+| Print this symbol on YYO. |
+`---------------------------*/
static void
-yy_symbol_print (FILE *yyoutput, int yytype, YYSTYPE const * const yyvaluep)
+yy_symbol_print (FILE *yyo, int yytype, YYSTYPE const * const yyvaluep)
{
- YYFPRINTF (yyoutput, "%s %s (",
+ YYFPRINTF (yyo, "%s %s (",
yytype < YYNTOKENS ? "token" : "nterm", yytname[yytype]);
- yy_symbol_value_print (yyoutput, yytype, yyvaluep);
- YYFPRINTF (yyoutput, ")");
+ yy_symbol_value_print (yyo, yytype, yyvaluep);
+ YYFPRINTF (yyo, ")");
}
/*------------------------------------------------------------------.
@@ -749,7 +753,7 @@
static void
yy_reduce_print (yytype_int16 *yyssp, YYSTYPE *yyvsp, int yyrule)
{
- unsigned long int yylno = yyrline[yyrule];
+ unsigned long yylno = yyrline[yyrule];
int yynrhs = yyr2[yyrule];
int yyi;
YYFPRINTF (stderr, "Reducing stack by rule %d (line %lu):\n",
@@ -760,7 +764,7 @@
YYFPRINTF (stderr, " $%d = ", yyi + 1);
yy_symbol_print (stderr,
yystos[yyssp[yyi + 1 - yynrhs]],
- &(yyvsp[(yyi + 1) - (yynrhs)])
+ &yyvsp[(yyi + 1) - (yynrhs)]
);
YYFPRINTF (stderr, "\n");
}
@@ -864,7 +868,10 @@
case '\\':
if (*++yyp != '\\')
goto do_not_strip_quotes;
- /* Fall through. */
+ else
+ goto append;
+
+ append:
default:
if (yyres)
yyres[yyn] = *yyp;
@@ -882,7 +889,7 @@
if (! yyres)
return yystrlen (yystr);
- return yystpcpy (yyres, yystr) - yyres;
+ return (YYSIZE_T) (yystpcpy (yyres, yystr) - yyres);
}
# endif
@@ -960,10 +967,10 @@
yyarg[yycount++] = yytname[yyx];
{
YYSIZE_T yysize1 = yysize + yytnamerr (YY_NULLPTR, yytname[yyx]);
- if (! (yysize <= yysize1
- && yysize1 <= YYSTACK_ALLOC_MAXIMUM))
+ if (yysize <= yysize1 && yysize1 <= YYSTACK_ALLOC_MAXIMUM)
+ yysize = yysize1;
+ else
return 2;
- yysize = yysize1;
}
}
}
@@ -987,9 +994,10 @@
{
YYSIZE_T yysize1 = yysize + yystrlen (yyformat);
- if (! (yysize <= yysize1 && yysize1 <= YYSTACK_ALLOC_MAXIMUM))
+ if (yysize <= yysize1 && yysize1 <= YYSTACK_ALLOC_MAXIMUM)
+ yysize = yysize1;
+ else
return 2;
- yysize = yysize1;
}
if (*yymsg_alloc < yysize)
@@ -1115,23 +1123,31 @@
yychar = YYEMPTY; /* Cause a token to be read. */
goto yysetstate;
+
/*------------------------------------------------------------.
-| yynewstate -- Push a new state, which is found in yystate. |
+| yynewstate -- push a new state, which is found in yystate. |
`------------------------------------------------------------*/
- yynewstate:
+yynewstate:
/* In all cases, when you get here, the value and location stacks
have just been pushed. So pushing a state here evens the stacks. */
yyssp++;
- yysetstate:
- *yyssp = yystate;
+
+/*--------------------------------------------------------------------.
+| yynewstate -- set current state (the top of the stack) to yystate. |
+`--------------------------------------------------------------------*/
+yysetstate:
+ *yyssp = (yytype_int16) yystate;
if (yyss + yystacksize - 1 <= yyssp)
+#if !defined yyoverflow && !defined YYSTACK_RELOCATE
+ goto yyexhaustedlab;
+#else
{
/* Get the current used size of the three stacks, in elements. */
- YYSIZE_T yysize = yyssp - yyss + 1;
+ YYSIZE_T yysize = (YYSIZE_T) (yyssp - yyss + 1);
-#ifdef yyoverflow
+# if defined yyoverflow
{
/* Give user a chance to reallocate the stack. Use copies of
these so that the &'s don't force the real ones into
@@ -1147,14 +1163,10 @@
&yyss1, yysize * sizeof (*yyssp),
&yyvs1, yysize * sizeof (*yyvsp),
&yystacksize);
-
yyss = yyss1;
yyvs = yyvs1;
}
-#else /* no yyoverflow */
-# ifndef YYSTACK_RELOCATE
- goto yyexhaustedlab;
-# else
+# else /* defined YYSTACK_RELOCATE */
/* Extend the stack our own way. */
if (YYMAXDEPTH <= yystacksize)
goto yyexhaustedlab;
@@ -1170,22 +1182,22 @@
goto yyexhaustedlab;
YYSTACK_RELOCATE (yyss_alloc, yyss);
YYSTACK_RELOCATE (yyvs_alloc, yyvs);
-# undef YYSTACK_RELOCATE
+# undef YYSTACK_RELOCATE
if (yyss1 != yyssa)
YYSTACK_FREE (yyss1);
}
# endif
-#endif /* no yyoverflow */
yyssp = yyss + yysize - 1;
yyvsp = yyvs + yysize - 1;
YYDPRINTF ((stderr, "Stack size increased to %lu\n",
- (unsigned long int) yystacksize));
+ (unsigned long) yystacksize));
if (yyss + yystacksize - 1 <= yyssp)
YYABORT;
}
+#endif /* !defined yyoverflow && !defined YYSTACK_RELOCATE */
YYDPRINTF ((stderr, "Entering state %d\n", yystate));
@@ -1194,11 +1206,11 @@
goto yybackup;
+
/*-----------.
| yybackup. |
`-----------*/
yybackup:
-
/* Do appropriate processing given the current state. Read a
lookahead token if we need one and don't already have one. */
@@ -1271,7 +1283,7 @@
/*-----------------------------.
-| yyreduce -- Do a reduction. |
+| yyreduce -- do a reduction. |
`-----------------------------*/
yyreduce:
/* yyn is the number of a rule to reduce with. */
@@ -1318,7 +1330,7 @@
case 17:
{
- (yyval.dev) = new_device(cur_parent, cur_chip_instance, (yyvsp[-2].number), (yyvsp[-1].string), (yyvsp[0].number));
+ (yyval.dev) = new_device(cur_parent, cur_chip_instance, (yyvsp[-3].number), (yyvsp[-2].string), (yyvsp[-1].string), (yyvsp[0].number));
cur_parent = (yyval.dev)->last_bus;
}
@@ -1332,50 +1344,66 @@
break;
- case 21:
+ case 19:
- { add_resource(cur_parent, (yyvsp[-3].number), strtol((yyvsp[-2].string), NULL, 0), strtol((yyvsp[0].string), NULL, 0)); }
+ {
+ (yyval.string) = NULL;
+}
break;
- case 22:
+ case 20:
- { add_register(cur_chip_instance, (yyvsp[-2].string), (yyvsp[0].string)); }
+ {
+ (yyval.string) = (yyvsp[0].string);
+}
break;
case 23:
- { add_pci_subsystem_ids(cur_parent, strtol((yyvsp[-1].string), NULL, 16), strtol((yyvsp[0].string), NULL, 16), 0); }
+ { add_resource(cur_parent, (yyvsp[-3].number), strtol((yyvsp[-2].string), NULL, 0), strtol((yyvsp[0].string), NULL, 0)); }
break;
case 24:
- { add_pci_subsystem_ids(cur_parent, strtol((yyvsp[-2].string), NULL, 16), strtol((yyvsp[-1].string), NULL, 16), 1); }
+ { add_register(cur_chip_instance, (yyvsp[-2].string), (yyvsp[0].string)); }
break;
case 25:
- { add_ioapic_info(cur_parent, strtol((yyvsp[-2].string), NULL, 16), (yyvsp[-1].string), strtol((yyvsp[0].string), NULL, 16)); }
+ { add_pci_subsystem_ids(cur_parent, strtol((yyvsp[-1].string), NULL, 16), strtol((yyvsp[0].string), NULL, 16), 0); }
break;
case 26:
- { add_slot_desc(cur_parent, (yyvsp[-3].string), (yyvsp[-2].string), (yyvsp[-1].string), (yyvsp[0].string)); }
+ { add_pci_subsystem_ids(cur_parent, strtol((yyvsp[-2].string), NULL, 16), strtol((yyvsp[-1].string), NULL, 16), 1); }
break;
case 27:
- { add_slot_desc(cur_parent, (yyvsp[-2].string), (yyvsp[-1].string), (yyvsp[0].string), NULL); }
+ { add_ioapic_info(cur_parent, strtol((yyvsp[-2].string), NULL, 16), (yyvsp[-1].string), strtol((yyvsp[0].string), NULL, 16)); }
break;
case 28:
+ { add_slot_desc(cur_parent, (yyvsp[-3].string), (yyvsp[-2].string), (yyvsp[-1].string), (yyvsp[0].string)); }
+
+ break;
+
+ case 29:
+
+ { add_slot_desc(cur_parent, (yyvsp[-2].string), (yyvsp[-1].string), (yyvsp[0].string), NULL); }
+
+ break;
+
+ case 30:
+
{ add_slot_desc(cur_parent, (yyvsp[-1].string), (yyvsp[0].string), NULL, NULL); }
break;
@@ -1406,14 +1434,13 @@
/* Now 'shift' the result of the reduction. Determine what state
that goes to, based on the state we popped back to and the rule
number reduced by. */
-
- yyn = yyr1[yyn];
-
- yystate = yypgoto[yyn - YYNTOKENS] + *yyssp;
- if (0 <= yystate && yystate <= YYLAST && yycheck[yystate] == *yyssp)
- yystate = yytable[yystate];
- else
- yystate = yydefgoto[yyn - YYNTOKENS];
+ {
+ const int yylhs = yyr1[yyn] - YYNTOKENS;
+ const int yyi = yypgoto[yylhs] + *yyssp;
+ yystate = (0 <= yyi && yyi <= YYLAST && yycheck[yyi] == *yyssp
+ ? yytable[yyi]
+ : yydefgoto[yylhs]);
+ }
goto yynewstate;
@@ -1496,12 +1523,10 @@
| yyerrorlab -- error raised explicitly by YYERROR. |
`---------------------------------------------------*/
yyerrorlab:
-
- /* Pacify compilers like GCC when the user code never invokes
- YYERROR and the label yyerrorlab therefore never appears in user
- code. */
- if (/*CONSTCOND*/ 0)
- goto yyerrorlab;
+ /* Pacify compilers when the user code never invokes YYERROR and the
+ label yyerrorlab therefore never appears in user code. */
+ if (0)
+ YYERROR;
/* Do not reclaim the symbols of the rule whose action triggered
this YYERROR. */
@@ -1563,6 +1588,7 @@
yyresult = 0;
goto yyreturn;
+
/*-----------------------------------.
| yyabortlab -- YYABORT comes here. |
`-----------------------------------*/
@@ -1570,6 +1596,7 @@
yyresult = 1;
goto yyreturn;
+
#if !defined yyoverflow || YYERROR_VERBOSE
/*-------------------------------------------------.
| yyexhaustedlab -- memory exhaustion comes here. |
@@ -1580,6 +1607,10 @@
/* Fall through. */
#endif
+
+/*-----------------------------------------------------.
+| yyreturn -- parsing is finished, return the result. |
+`-----------------------------------------------------*/
yyreturn:
if (yychar != YYEMPTY)
{
diff --git a/util/sconfig/sconfig.tab.h_shipped b/util/sconfig/sconfig.tab.h_shipped
index bcbd644..8af828e 100644
--- a/util/sconfig/sconfig.tab.h_shipped
+++ b/util/sconfig/sconfig.tab.h_shipped
@@ -1,8 +1,9 @@
-/* A Bison parser, made by GNU Bison 3.0.5. */
+/* A Bison parser, made by GNU Bison 3.3.2. */
/* Bison interface for Yacc-like parsers in C
- Copyright (C) 1984, 1989-1990, 2000-2015, 2018 Free Software Foundation, Inc.
+ Copyright (C) 1984, 1989-1990, 2000-2015, 2018-2019 Free Software Foundation,
+ Inc.
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
@@ -30,8 +31,11 @@
This special exception was added by the Free Software Foundation in
version 2.2 of Bison. */
-#ifndef YY_YY_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED
-# define YY_YY_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED
+/* Undocumented macros, especially those whose name start with YY_,
+ are private implementation details. Do not rely on them. */
+
+#ifndef YY_YY_HOME_ICON_COREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED
+# define YY_YY_HOME_ICON_COREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED
/* Debug traces. */
#ifndef YYDEBUG
# define YYDEBUG 0
@@ -48,35 +52,36 @@
CHIP = 258,
DEVICE = 259,
REGISTER = 260,
- BOOL = 261,
- HIDDEN = 262,
- BUS = 263,
- RESOURCE = 264,
- END = 265,
- EQUALS = 266,
- HEX = 267,
- STRING = 268,
- PCI = 269,
- PNP = 270,
- I2C = 271,
- APIC = 272,
- CPU_CLUSTER = 273,
- CPU = 274,
- DOMAIN = 275,
- IRQ = 276,
- DRQ = 277,
- SLOT_DESC = 278,
- IO = 279,
- NUMBER = 280,
- SUBSYSTEMID = 281,
- INHERIT = 282,
- IOAPIC_IRQ = 283,
- IOAPIC = 284,
- PCIINT = 285,
- GENERIC = 286,
- SPI = 287,
- USB = 288,
- MMIO = 289
+ MNEMONIC = 261,
+ BOOL = 262,
+ HIDDEN = 263,
+ BUS = 264,
+ RESOURCE = 265,
+ END = 266,
+ EQUALS = 267,
+ HEX = 268,
+ STRING = 269,
+ PCI = 270,
+ PNP = 271,
+ I2C = 272,
+ APIC = 273,
+ CPU_CLUSTER = 274,
+ CPU = 275,
+ DOMAIN = 276,
+ IRQ = 277,
+ DRQ = 278,
+ SLOT_DESC = 279,
+ IO = 280,
+ NUMBER = 281,
+ SUBSYSTEMID = 282,
+ INHERIT = 283,
+ IOAPIC_IRQ = 284,
+ IOAPIC = 285,
+ PCIINT = 286,
+ GENERIC = 287,
+ SPI = 288,
+ USB = 289,
+ MMIO = 290
};
#endif
@@ -105,4 +110,4 @@
int yyparse (void);
-#endif /* !YY_YY_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED */
+#endif /* !YY_YY_HOME_ICON_COREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED */
diff --git a/util/sconfig/sconfig.y b/util/sconfig/sconfig.y
index 0d894a9..1f225c1 100755
--- a/util/sconfig/sconfig.y
+++ b/util/sconfig/sconfig.y
@@ -31,7 +31,7 @@
int number;
}
-%token CHIP DEVICE REGISTER BOOL HIDDEN BUS RESOURCE END EQUALS HEX STRING PCI PNP I2C APIC CPU_CLUSTER CPU DOMAIN IRQ DRQ SLOT_DESC IO NUMBER SUBSYSTEMID INHERIT IOAPIC_IRQ IOAPIC PCIINT GENERIC SPI USB MMIO
+%token CHIP DEVICE REGISTER MNEMONIC BOOL HIDDEN BUS RESOURCE END EQUALS HEX STRING PCI PNP I2C APIC CPU_CLUSTER CPU DOMAIN IRQ DRQ SLOT_DESC IO NUMBER SUBSYSTEMID INHERIT IOAPIC_IRQ IOAPIC PCIINT GENERIC SPI USB MMIO
%%
devtree: { cur_parent = root_parent; } chip;
@@ -48,12 +48,18 @@
cur_chip_instance = chip_dequeue_tail();
};
-device: DEVICE BUS NUMBER /* == devnum */ status {
- $<dev>$ = new_device(cur_parent, cur_chip_instance, $<number>2, $<string>3, $<number>4);
+device: DEVICE BUS NUMBER /* == devnum */ mnemonic status {
+ $<dev>$ = new_device(cur_parent, cur_chip_instance, $<number>2, $<string>3, $<string>4, $<number>5);
cur_parent = $<dev>$->last_bus;
}
devicechildren END {
- cur_parent = $<dev>5->parent;
+ cur_parent = $<dev>6->parent;
+};
+
+mnemonic: /* empty */ {
+ $<string>$ = NULL;
+} | MNEMONIC STRING {
+ $<string>$ = $<string>2;
};
status: BOOL | HIDDEN;
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I058a319f9b968924fbef9485a96c9e3f900a3ee8
Gerrit-Change-Number: 35456
Gerrit-PatchSet: 1
Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>
Gerrit-MessageType: newchange
2 weeks, 3 days
- 10
- 37