coreboot-gerrit November 2019

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: coreinfo/coreinfo.c: Provide information of time format
by Name of user not set (Code Review) 07 Aug '23

07 Aug '23

Name of user not set #1002476 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35847 ) Change subject: coreinfo/coreinfo.c: Provide information of time format ...................................................................... coreinfo/coreinfo.c: Provide information of time format Specify Coordinated Universal Time (UTC) time format while print date and time in the coreinfo payload. Change-Id: I359cef7697daf5d92d2c9fb58bf75c5b1345e982 Signed-off-by: Sourabh Kashyap <sourabhka(a)hcl.com> --- M payloads/coreinfo/coreinfo.c 1 file changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/35847/1 diff --git a/payloads/coreinfo/coreinfo.c b/payloads/coreinfo/coreinfo.c index 53985b2..ea4d424 100644 --- a/payloads/coreinfo/coreinfo.c +++ b/payloads/coreinfo/coreinfo.c @@ -124,8 +124,10 @@ rtc_read_clock(&tm); - mvwprintw(menuwin, 1, 57, "%02d/%02d/%04d - %02d:%02d:%02d", - tm.tm_mon + 1, tm.tm_mday, 1900 + tm.tm_year, tm.tm_hour, + mvwprintw(menuwin, 1, 53, "%02d/%02d/%04d", tm.tm_mon + 1, + tm.tm_mday, 1900 + tm.tm_year); + mvwprintw(menuwin, 1, 63, " - UTC "); + mvwprintw(menuwin, 1, 70, "%02d:%02d:%02d", tm.tm_hour, tm.tm_min, tm.tm_sec); } #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/35847 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I359cef7697daf5d92d2c9fb58bf75c5b1345e982 Gerrit-Change-Number: 35847 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1002476 Gerrit-MessageType: newchange

4 10

Change in coreboot[master]: soc/intel/(fsp_)baytrail: Initialize SPI before console init
by Arthur Heymans (Code Review) 07 Aug '23

07 Aug '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36407 ) Change subject: soc/intel/(fsp_)baytrail: Initialize SPI before console init ...................................................................... soc/intel/(fsp_)baytrail: Initialize SPI before console init This makes the spi flash console function during romstage. It was tested with the FSP baytrail codepath but it's a safe assumption that the same fix also applies for the google mrc.bin codepath. Tested on Intel Minnowboard Turbot. Change-Id: If6ef0eeea902ab76d398d0218ee943e482f69b43 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/baytrail/romstage/romstage.c M src/soc/intel/fsp_baytrail/romstage/romstage.c 2 files changed, 5 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/36407/1 diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 7c129e2..e06c39e 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -165,10 +165,10 @@ if (CONFIG(ENABLE_BUILTIN_COM1)) byt_config_com1_and_enable(); - console_init(); - spi_init(); + console_init(); + set_max_freq(); punit_init(); diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c index f347591..78aa9fc 100644 --- a/src/soc/intel/fsp_baytrail/romstage/romstage.c +++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c @@ -171,9 +171,11 @@ byt_config_com1_and_enable(); post_code(0x43); - console_init(); spi_init(); + + console_init(); + baytrail_rtc_init(); /* Call into mainboard. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/36407 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6ef0eeea902ab76d398d0218ee943e482f69b43 Gerrit-Change-Number: 36407 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: arch/acpi.h: Avoid explicitly assign values to enum names
by Name of user not set (Code Review) 07 Aug '23

07 Aug '23

Name of user not set #1002476 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36430 ) Change subject: arch/acpi.h: Avoid explicitly assign values to enum names ...................................................................... arch/acpi.h: Avoid explicitly assign values to enum names Compiler by default assign values starting from the initial integral constant. Change-Id: I1a5aa9762051780b67013f67f101112fc7a0bf6e Signed-off-by: Himanshu Sahdev <himanshusah(a)hcl.com> --- M src/arch/x86/include/arch/acpi.h 1 file changed, 19 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/36430/1 diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 479067f..a9bd9f6 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -302,10 +302,10 @@ enum dev_scope_type { SCOPE_PCI_ENDPOINT = 1, - SCOPE_PCI_SUB = 2, - SCOPE_IOAPIC = 3, - SCOPE_MSI_HPET = 4, - SCOPE_ACPI_NAMESPACE_DEVICE = 5 + SCOPE_PCI_SUB, + SCOPE_IOAPIC, + SCOPE_MSI_HPET, + SCOPE_ACPI_NAMESPACE_DEVICE }; typedef struct dev_scope { @@ -321,11 +321,11 @@ } __packed dev_scope_t; enum dmar_type { - DMAR_DRHD = 0, - DMAR_RMRR = 1, - DMAR_ATSR = 2, - DMAR_RHSA = 3, - DMAR_ANDD = 4 + DMAR_DRHD, + DMAR_RMRR, + DMAR_ATSR, + DMAR_RHSA, + DMAR_ANDD }; enum { @@ -599,15 +599,15 @@ /* FADT Preferred Power Management Profile */ enum acpi_preferred_pm_profiles { - PM_UNSPECIFIED = 0, - PM_DESKTOP = 1, - PM_MOBILE = 2, - PM_WORKSTATION = 3, - PM_ENTERPRISE_SERVER = 4, - PM_SOHO_SERVER = 5, - PM_APPLIANCE_PC = 6, - PM_PERFORMANCE_SERVER = 7, - PM_TABLET = 8, /* ACPI 5.0 & greater */ + PM_UNSPECIFIED, + PM_DESKTOP, + PM_MOBILE, + PM_WORKSTATION3, + PM_ENTERPRISE_SERVER4, + PM_SOHO_SERVER, + PM_APPLIANCE_PC, + PM_PERFORMANCE_SERVER, + PM_TABLET, /* ACPI 5.0 & greater */ }; /* FACS (Firmware ACPI Control Structure) */ @@ -780,7 +780,7 @@ }; enum acpi_ipmi_interface_type { - IPMI_INTERFACE_RESERVED = 0, + IPMI_INTERFACE_RESERVED, IPMI_INTERFACE_KCS, IPMI_INTERFACE_SMIC, IPMI_INTERFACE_BT, -- To view, visit https://review.coreboot.org/c/coreboot/+/36430 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1a5aa9762051780b67013f67f101112fc7a0bf6e Gerrit-Change-Number: 36430 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1002476 Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: arch/riscv: Fix cpu capabilities detection function
by Xiang Wang (Code Review) 07 Aug '23

07 Aug '23

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36944 ) Change subject: arch/riscv: Fix cpu capabilities detection function ...................................................................... arch/riscv: Fix cpu capabilities detection function On some platforms, misa may not be implemented. On such a platform, reading misa will get zero. At this time, soc is required to implement a non-standard method to detect the soc function. This modification add interfaces for non-standard function. The MXL field of misa is always at the highest two bits, whether it is a 32-bit 64-bit or a 128-bit machine. Therefore, this modification fixes the use of a fixed offset to detect the machine length. Change-Id: Id24f77bf21ef0c7c300faa477d67294d093eeecc Signed-off-by: Xiang Wang <merle(a)hardenedlinux.org> --- M src/arch/riscv/Makefile.inc A src/arch/riscv/cpu.c M src/arch/riscv/include/arch/cpu.h 3 files changed, 87 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/36944/1 diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index 0038523..0679be73 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -60,6 +60,7 @@ bootblock-y += trap_util.S bootblock-y += trap_handler.c bootblock-y += fp_asm.S +bootblock-y += cpu.c bootblock-y += misaligned.c bootblock-y += sbi.c bootblock-y += mcall.c @@ -100,6 +101,7 @@ romstage-y += boot.c romstage-y += romstage.c romstage-y += misc.c +romstage-y += cpu.c romstage-$(ARCH_RISCV_PMP) += pmp.c romstage-y += smp.c romstage-y += \ @@ -137,6 +139,7 @@ ramstage-y += trap_util.S ramstage-y += trap_handler.c ramstage-y += fp_asm.S +ramstage-y += cpu.c ramstage-y += misaligned.c ramstage-y += sbi.c ramstage-y += virtual_memory.c diff --git a/src/arch/riscv/cpu.c b/src/arch/riscv/cpu.c new file mode 100644 index 0000000..69556f3 --- /dev/null +++ b/src/arch/riscv/cpu.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/cpu.h> + + +__weak int soc_supports_extension(char ext) +{ + return 0; +} + +__weak int soc_machine_xlen(void) +{ + return -1; +} diff --git a/src/arch/riscv/include/arch/cpu.h b/src/arch/riscv/include/arch/cpu.h index c62199e..72a8a69 100644 --- a/src/arch/riscv/include/arch/cpu.h +++ b/src/arch/riscv/include/arch/cpu.h @@ -18,6 +18,7 @@ #include <arch/encoding.h> #include <device/device.h> +#include <commonlib/compiler.h> #define asmlinkage @@ -42,15 +43,68 @@ uint8_t riscv_model; }; +/* If the SOC does not implement misa, the read misa will be zero. + * Such SOC requires a non-standard mechanism to detect ISA extensions. + * If the soc does not implement misa, implement this function. + * */ +int soc_supports_extension(char ext); + static inline int supports_extension(char ext) { - return read_csr(misa) & (1 << (ext - 'A')); + uintptr_t isa = read_csr(misa); + if (isa) + return isa & (1 << (ext - 'A')); + else + return soc_supports_extension(ext); } +/* If the SOC does not implement misa, the read misa will be zero. + * Such SOC requires a non-standard mechanism to detect machine XLEN. + * If the soc does not implement misa, implement this function. + * */ +int soc_machine_xlen(void); + static inline int machine_xlen(void) { - int mxl = (read_csr(misa) >> (__riscv_xlen - 2)) & 3; - return (1 << mxl) * 16; + int r; + asm ( + "csrr t0, misa\n\t" + "bnez t0, 1f\n\t" + "call soc_machine_xlen\n\t" + "j 2f\n" + "1:\n\t" + "srli t1, t0, 30\n\t" + "srli t1, t1, 32\n\t" + "srli t1, t1, 32\n\t" + "srli t1, t1, 32\n\t" + "andi t1, t1, 3\n\t" + "li t2, 3\n\t" + "bne t1, t2, 1f\n\t" + "li %0, 128\n\t" + "j 2f\n" + "1:\n\t" + "srli t1, t0, 30\n\t" + "srli t1, t1, 32\n\t" + "andi t1, t1, 3\n\t" + "li t2, 2\n\t" + "bne t1, t2, 1f\n\t" + "li %0, 64\n\t" + "j 2f\n" + "1:\n\t" + "srli t1, t0, 30\n\t" + "andi t1, t1, 3\n\t" + "li t2, 1\n\t" + "bne t1, t2, 1f\n\t" + "li %0, 32\n\t" + "j 2f\n" + "1:\n\t" + "li %0, -1\n" + "2:" + : "=r"(r) + : + : "t0", "t1", "t2", "ra" + ); + return r; } struct cpu_info *cpu_info(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/36944 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id24f77bf21ef0c7c300faa477d67294d093eeecc Gerrit-Change-Number: 36944 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <merle(a)hardenedlinux.org> Gerrit-MessageType: newchange

2 11

Change in ...coreboot[master]: security/vboot: Add fmap measurements
by Philipp Deppenwiese (Code Review) 07 Aug '23

07 Aug '23

Philipp Deppenwiese has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31597 Change subject: security/vboot: Add fmap measurements ...................................................................... security/vboot: Add fmap measurements * Hook into fmap location * Add static measurements for IFD to the CRTM Change-Id: If7e4972805fbc8d19ab55d1f5e506836791c7bf0 Signed-off-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- M src/lib/fmap.c M src/security/vboot/vboot_crtm.c M src/security/vboot/vboot_crtm.h 3 files changed, 76 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/31597/1 diff --git a/src/lib/fmap.c b/src/lib/fmap.c index 9602134..ae0aaf8 100644 --- a/src/lib/fmap.c +++ b/src/lib/fmap.c @@ -20,6 +20,7 @@ #include <commonlib/fmap_serialized.h> #include <stddef.h> #include <string.h> +#include <security/vboot/vboot_crtm.h> #include "fmap_config.h" @@ -77,7 +78,12 @@ if (fmap_locate_area(name, &ar)) return -1; - return boot_device_ro_subregion(&ar, area); + int ret = boot_device_ro_subregion(&ar, area); + if (!ret) + if (vboot_measure_fmap_hook(area, name)) + return -1; + + return ret; } int fmap_locate_area_as_rdev_rw(const char *name, struct region_device *area) @@ -87,7 +93,12 @@ if (fmap_locate_area(name, &ar)) return -1; - return boot_device_rw_subregion(&ar, area); + int ret = boot_device_rw_subregion(&ar, area); + if (!ret) + if (vboot_measure_fmap_hook(area, name)) + return -1; + + return ret; } int fmap_locate_area(const char *name, struct region *ar) diff --git a/src/security/vboot/vboot_crtm.c b/src/security/vboot/vboot_crtm.c index 1914f20..a474fd0 100644 --- a/src/security/vboot/vboot_crtm.c +++ b/src/security/vboot/vboot_crtm.c @@ -18,6 +18,16 @@ #include <security/vboot/vboot_crtm.h> #include <security/vboot/misc.h> +const static char *fmap_runtime_data[] = { + "UNIFIED_MRC_CACHE", + "RW_MRC_CACHE", + "RW_ELOG", + "RW_VPD", + "RW_NVRAM", + "RECOVERY_MRC_CACHE", + "RW_VAR_MRC_CACHE", + "SMMSTORE"}; + uint32_t vboot_init_crtm(void) { struct prog bootblock = PROG_INIT(PROG_BOOTBLOCK, "bootblock"); @@ -88,6 +98,36 @@ } } + /* IFD measurements */ + struct region_device fmap; + if (fmap_locate_area_as_rdev("RO_VPD", &fmap) == 0) + if (tpm_measure_region(&fmap, TPM_CRTM_PCR, "Read-only VPD") != TPM_SUCCESS) + return VB2_ERROR_UNKNOWN; + + if (fmap_locate_area_as_rdev("GBB", &fmap) == 0) + if (tpm_measure_region(&fmap, TPM_CRTM_PCR, "Google Binary Blob") != TPM_SUCCESS) + return VB2_ERROR_UNKNOWN; + + if (fmap_locate_area_as_rdev("SI_DESC", &fmap) == 0) + if (tpm_measure_region(&fmap, TPM_CRTM_PCR, "Intel Flash Descriptor") != TPM_SUCCESS) + return VB2_ERROR_UNKNOWN; + + if (fmap_locate_area_as_rdev("SI_ME", &fmap) == 0) + if (tpm_measure_region(&fmap, TPM_RUNTIME_DATA_PCR, "Intel ME") != TPM_SUCCESS) + return VB2_ERROR_UNKNOWN; + + if (fmap_locate_area_as_rdev("SI_EC", &fmap) == 0) + if (tpm_measure_region(&fmap, TPM_RUNTIME_DATA_PCR, "EC firmware") != TPM_SUCCESS) + return VB2_ERROR_UNKNOWN; + + if (fmap_locate_area_as_rdev("SI_GBE", &fmap) == 0) + if (tpm_measure_region(&fmap, TPM_CRTM_PCR, "Intel GbE") != TPM_SUCCESS) + return VB2_ERROR_UNKNOWN; + + if (fmap_locate_area_as_rdev("SI_PDR", &fmap) == 0) + if (tpm_measure_region(&fmap, TPM_RUNTIME_DATA_PCR, "Platform Data") != TPM_SUCCESS) + return VB2_ERROR_UNKNOWN; + return VB2_SUCCESS; } @@ -142,3 +182,18 @@ return tpm_measure_region(&rdev, pcr_index, name); } + +uint32_t vboot_measure_fmap_hook(struct region_device *rdev, const char *name) +{ + int i; + + if (!vb2_logic_executed()) + return 0; + + for (i = 0; i < sizeof(fmap_runtime_data) / sizeof(fmap_runtime_data[0]); i++) { + if (!strncmp(fmap_runtime_data[i], name, sizeof(fmap_runtime_data[i]))) + return tpm_measure_region(rdev, TPM_RUNTIME_DATA_PCR, name); + } + + return 0; +} diff --git a/src/security/vboot/vboot_crtm.h b/src/security/vboot/vboot_crtm.h index d28e96e..259e486 100644 --- a/src/security/vboot/vboot_crtm.h +++ b/src/security/vboot/vboot_crtm.h @@ -54,8 +54,16 @@ */ uint32_t vboot_measure_cbfs_hook(struct cbfsf *fh, const char *name); +/* + * Measures fmap data via hook (fmap) + * rdev is the region device handle to measure + * return 0 if successful, else an error + */ +uint32_t vboot_measure_fmap_hook(struct region_device *rdev, const char *name); + #else #define vboot_measure_cbfs_hook(fh, name) 0 +#define vboot_measure_fmap_hook(rdev, name) 0 #endif #endif /* __VBOOT_VBOOT_CRTM_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31597 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7e4972805fbc8d19ab55d1f5e506836791c7bf0 Gerrit-Change-Number: 31597 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [TESTME]soc/intel/braswell: Attempt to skip FSP-T
by Arthur Heymans (Code Review) 07 Aug '23

07 Aug '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36263 ) Change subject: [TESTME]soc/intel/braswell: Attempt to skip FSP-T ...................................................................... [TESTME]soc/intel/braswell: Attempt to skip FSP-T Use native Cache as ram and make FSP-M not complain by faking FSP-T has ran. Change-Id: I15edf479b09bf9a87afb9ab27e09d4360d21b9ff Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/braswell/Kconfig M src/soc/intel/braswell/Makefile.inc M src/soc/intel/braswell/bootblock/bootblock.c 3 files changed, 91 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/36263/1 diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 5d6438f..7750534 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -39,7 +39,9 @@ select TSC_MONOTONIC_TIMER select TSC_SYNC_MFENCE select UDELAY_TSC - select USE_GENERIC_FSP_CAR_INC +# select USE_GENERIC_FSP_CAR_INC + select CPU_HAS_L2_ENABLE_MSR + select SKIP_FSP_CAR select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SPI_CONSOLE_SUPPORT select HAVE_FSP_GOP diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc index cc111da..b50dcb8 100644 --- a/src/soc/intel/braswell/Makefile.inc +++ b/src/soc/intel/braswell/Makefile.inc @@ -14,6 +14,8 @@ bootblock-y += lpc_init.c bootblock-y += pmutil.c bootblock-y += tsc_freq.c +bootblock-y += ../../../cpu/intel/car/non-evict/cache_as_ram.S +bootblock-y += ../../../cpu/x86/early_reset.S romstage-y += gpio_support.c romstage-y += iosf.c @@ -27,6 +29,7 @@ postcar-y += iosf.c postcar-y += spi.c postcar-y += tsc_freq.c +postcar-y += ../../../cpu/intel/car/non-evict/exit_car.S ramstage-y += acpi.c ramstage-y += chip.c diff --git a/src/soc/intel/braswell/bootblock/bootblock.c b/src/soc/intel/braswell/bootblock/bootblock.c index d8d953c..eb3712e 100644 --- a/src/soc/intel/braswell/bootblock/bootblock.c +++ b/src/soc/intel/braswell/bootblock/bootblock.c @@ -27,9 +27,14 @@ #include <soc/lpc.h> #include <soc/pm.h> #include <soc/spi.h> +#include <fsp/util.h> +#include <cpu/x86/tsc.h> -asmlinkage void bootblock_c_entry(uint64_t base_timestamp) +static uint64_t car_timestamp; + +asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist) { + car_timestamp = base_timestamp; /* Call lib/bootblock.c main */ bootblock_main_with_basetime(base_timestamp); } @@ -134,6 +139,83 @@ program_base_addresses(); tco_disable(); } + +const struct microcode { + u32 hdrver; /* Header Version */ + u32 rev; /* Update Revision */ + u32 date; /* Date */ + u32 sig; /* Processor Signature */ + + u32 cksum; /* Checksum */ + u32 ldrver; /* Loader Revision */ + u32 pf; /* Processor Flags */ + + u32 data_size; /* Data Size */ + u32 total_size; /* Total Size */ + + u32 reserved[3]; + u8 data[10]; /* Our fake microcode */ +} fake_microcode = { + .hdrver = 1, /* Header Version */ + .rev = 1, /* Update Revision */ + .date = 0x10232019, /* Date: Time of writing 23-10-2019 */ + .sig = 0x00010ff0, /* Sig: (non existing) Family: 0xf, Model: 0x1f, stepping: 0 */ + + .cksum = 0, /* Checksum: not checked by FSP, so won't care */ + .ldrver = 1, /* Loader Revision */ + .pf = 1, /* Processor Flags */ + + .data_size = 0x10, /* Data Size */ + .total_size = 0x40, /* Total Size */ + + .reserved = {}, + .data = {}, +}; + + + + +const FSP_TEMP_RAM_INIT_PARAMS CAR_init_params = { + .MicrocodeRegionBase = (uint32_t)&fake_microcode, + .MicrocodeRegionLength = sizeof(fake_microcode), + .CodeRegionBase = MAX_UINT32 - CONFIG_ROM_SIZE + 1, + .CodeRegionLength = CONFIG_ROM_SIZE, +}; + +struct fsp_t_handoff { + uint32_t bottom_number; + tsc_t final_timestamp; + tsc_t initial_timestamp; + char per0[4]; + uint32_t middle_number; + FSP_TEMP_RAM_INIT_PARAMS fsp_t_params; + char mcud[4]; + uint32_t top_number; +}; + +/* FSP-M expects FSP-T to have run, but we didn't do that. + Fake that we ran FSP by placing the handoff structure FSP-T + normally creates at the top of the CAR region */ +static void install_fsp_t_handoff(void) +{ + struct fsp_t_handoff handoff = { + .bottom_number = 0, + .per0 = "PER0", + .mcud = "MCUD", + .middle_number = 0x18, + .top_number = 0x18, + }; + handoff.initial_timestamp.lo = car_timestamp & UINT32_MAX; + handoff.initial_timestamp.hi = (car_timestamp >> 32) & UINT32_MAX; + handoff.final_timestamp = rdtsc(); + handoff.fsp_t_params = (FSP_TEMP_RAM_INIT_PARAMS)CAR_init_params; + + memcpy((void *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_BASE + + CONFIG_DCACHE_RAM_MRC_VAR_SIZE + - sizeof(struct fsp_t_handoff)), + &handoff, sizeof(handoff)); +} + void bootblock_soc_init(void) { /* Continue chipset initialization */ @@ -142,4 +224,6 @@ spi_init(); lpc_init(); + + install_fsp_t_handoff(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/36263 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15edf479b09bf9a87afb9ab27e09d4360d21b9ff Gerrit-Change-Number: 36263 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

5 5

Change in coreboot[master]: soc/intel/common: Make use of clflush in common platform_segment_loaded
by Subrata Banik (Code Review) 07 Aug '23

07 Aug '23

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34992 ) Change subject: soc/intel/common: Make use of clflush in common platform_segment_loaded ...................................................................... soc/intel/common: Make use of clflush in common platform_segment_loaded This patch clear cache lines based on platform_segment_loaded() supplied start and size values before loading the targeted stage. This changes is required to fix hang issues appeared due to marking DRAM ranges as WB (CONFIG_MARK_DRAM_CACHE_WB) to speed up next stage loading/ decompression/execution time. Idea is to run clflush on those ranges just before tearing down the CAR (running invd instruction) and after that postcar frame will set up new MTRR ranges. Change-Id: I591f21cb4199477af271f0dd6c073e1c11831bfd Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/common/block/cpu/Kconfig M src/soc/intel/common/block/cpu/Makefile.inc A src/soc/intel/common/block/cpu/car/car.c 3 files changed, 71 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/34992/1 diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig index 8cc572d..0d1506b 100644 --- a/src/soc/intel/common/block/cpu/Kconfig +++ b/src/soc/intel/common/block/cpu/Kconfig @@ -66,3 +66,15 @@ help This option allows FSP to make use of MP services PPI published by coreboot to perform multiprocessor initialization. + +config MARK_DRAM_CACHE_WB + bool + default n + help + This option allows you to select how DRAM intermediate cache is set up. + Till discovering DRAM ranges, system will make use of CAR and CAR tear + down will handle by postcar/ramstage, that means entire postcar/ramstage + stage will execute from UC range. Intention here is to optimize the boot + flow hence enabling the caching for applicable DRAM ranges before CAR + tear down and setting up new DRAM based MTRR range. MTRR type WB + provides best optimization. diff --git a/src/soc/intel/common/block/cpu/Makefile.inc b/src/soc/intel/common/block/cpu/Makefile.inc index a6c4f37..63a2ac9 100644 --- a/src/soc/intel/common/block/cpu/Makefile.inc +++ b/src/soc/intel/common/block/cpu/Makefile.inc @@ -5,6 +5,7 @@ romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CAR) += car/exit_car.S romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c +romstage-$(CONFIG_MARK_DRAM_CACHE_WB) += car.c postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CAR) += car/exit_car.S postcar-$(CONFIG_FSP_CAR) += car/exit_car_fsp.S diff --git a/src/soc/intel/common/block/cpu/car/car.c b/src/soc/intel/common/block/cpu/car/car.c new file mode 100644 index 0000000..82d8e9a --- /dev/null +++ b/src/soc/intel/common/block/cpu/car/car.c @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <assert.h> +#include <cbmem.h> +#include <cpu/x86/cache.h> +#include <program_loading.h> + +static inline int is_usable_dram_addr(uintptr_t addr) +{ + return (addr < (uintptr_t) cbmem_top()); +} + +/* + * CLFLUSH the impacted WB'ed cache lines before loading postcar/ramstage + * in order to avoid getting stuck while tearing down (invd) the CAR. + */ +static void flush_cache(uintptr_t start, size_t size) +{ + uintptr_t end; + uintptr_t addr; + + end = start + (ALIGN_DOWN(size + 4096, 4096)); + for (addr = start; addr < end; addr += 64) + clflush((void *)addr); +} + +void platform_segment_loaded(uintptr_t start, size_t size, int flags) +{ + /* Bail out if this is not the final segment. */ + if (!(flags & SEG_FINAL)) + return; + + char start_dram_check = is_usable_dram_addr(start); + char end_dram_check = is_usable_dram_addr(start + size - 1); + + /* + * Bail out if loaded program segment does not lie in + * usable DRAM region. + */ + if (!start_dram_check && !end_dram_check) + return; + + flush_cache(start, size); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/34992 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I591f21cb4199477af271f0dd6c073e1c11831bfd Gerrit-Change-Number: 34992 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: mb/lenovo/{t410,x201}: Make X201 a variant board of T410
by Maccraft123 (Code Review) 07 Aug '23

07 Aug '23

Maccraft123 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36871 ) Change subject: mb/lenovo/{t410,x201}: Make X201 a variant board of T410 ...................................................................... mb/lenovo/{t410,x201}: Make X201 a variant board of T410 T410 and X201 boards are similar enough to be variants in the same mainboard tree. So I did it. Change-Id: Icfa1818812347ceb4e2de5cc4a3130537a4e13e7 Signed-off-by: Maciej Matuszczyj <maccraft123mc(a)gmail.com> --- A .tmpconfig.lintiC3nbS M src/mainboard/lenovo/t410/Kconfig M src/mainboard/lenovo/t410/Kconfig.name M src/mainboard/lenovo/t410/Makefile.inc M src/mainboard/lenovo/t410/dock.c M src/mainboard/lenovo/t410/hda_verb.c M src/mainboard/lenovo/t410/mainboard.c M src/mainboard/lenovo/t410/romstage.c C src/mainboard/lenovo/t410/variants/t410/board_info.txt R src/mainboard/lenovo/t410/variants/t410/data.vbt R src/mainboard/lenovo/t410/variants/t410/devicetree.cb R src/mainboard/lenovo/t410/variants/t410/gpio.c R src/mainboard/lenovo/t410/variants/x201/board_info.txt R src/mainboard/lenovo/t410/variants/x201/data.vbt R src/mainboard/lenovo/t410/variants/x201/devicetree.cb R src/mainboard/lenovo/t410/variants/x201/gpio.c D src/mainboard/lenovo/x201/Kconfig D src/mainboard/lenovo/x201/Kconfig.name D src/mainboard/lenovo/x201/Makefile.inc D src/mainboard/lenovo/x201/acpi/dock.asl D src/mainboard/lenovo/x201/acpi/ec.asl D src/mainboard/lenovo/x201/acpi/gpe.asl D src/mainboard/lenovo/x201/acpi/platform.asl D src/mainboard/lenovo/x201/acpi/superio.asl D src/mainboard/lenovo/x201/acpi_tables.c D src/mainboard/lenovo/x201/cmos.default D src/mainboard/lenovo/x201/cmos.layout D src/mainboard/lenovo/x201/dock.c D src/mainboard/lenovo/x201/dock.h D src/mainboard/lenovo/x201/dsdt.asl D src/mainboard/lenovo/x201/early_init.c D src/mainboard/lenovo/x201/gma-mainboard.ads D src/mainboard/lenovo/x201/hda_verb.c D src/mainboard/lenovo/x201/mainboard.c D src/mainboard/lenovo/x201/romstage.c D src/mainboard/lenovo/x201/smihandler.c D src/mainboard/lenovo/x201/thermal.h D src/mainboard/lenovo/x201/vboot-rwa.fmd 38 files changed, 106 insertions(+), 1,132 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/36871/1 diff --git a/.tmpconfig.lintiC3nbS b/.tmpconfig.lintiC3nbS new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/.tmpconfig.lintiC3nbS diff --git a/src/mainboard/lenovo/t410/Kconfig b/src/mainboard/lenovo/t410/Kconfig index 329d08d..3b21f1b 100644 --- a/src/mainboard/lenovo/t410/Kconfig +++ b/src/mainboard/lenovo/t410/Kconfig @@ -1,4 +1,4 @@ -if BOARD_LENOVO_T410 +if BOARD_LENOVO_T410 || BOARD_LENOVO_X201 config BOARD_SPECIFIC_OPTIONS def_bool y @@ -14,6 +14,7 @@ select HAVE_ACPI_TABLES select INTEL_INT15 select HAVE_ACPI_RESUME + select SUPERIO_NSC_PC87382 if BOARD_LENOVO_X201 select DRIVERS_LENOVO_WACOM select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 @@ -38,6 +39,10 @@ hex default 0x2a +config DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + config FMDFILE string default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT @@ -48,7 +53,8 @@ config MAINBOARD_PART_NUMBER string - default "ThinkPad T410" + default "ThinkPad T410" if BOARD_LENOVO_T410 + default "ThinkPad X201" if BOARD_LENOVO_X201 config USBDEBUG_HCD_INDEX int @@ -66,4 +72,10 @@ int default 10 +# Without the Intel ME's EFFS partition some PCIe devices (like the USB and SATA +# controllers) don't work as expected +config ME_CLEANER_ARGS + string + default "-S -w EFFS" + endif diff --git a/src/mainboard/lenovo/t410/Kconfig.name b/src/mainboard/lenovo/t410/Kconfig.name index d79cf39..531f21f 100644 --- a/src/mainboard/lenovo/t410/Kconfig.name +++ b/src/mainboard/lenovo/t410/Kconfig.name @@ -1,2 +1,5 @@ config BOARD_LENOVO_T410 bool "ThinkPad T410" + +config BOARD_LENOVO_X201 + bool "ThinkPad X201" diff --git a/src/mainboard/lenovo/t410/Makefile.inc b/src/mainboard/lenovo/t410/Makefile.inc index 518d91a..9ff4abe 100644 --- a/src/mainboard/lenovo/t410/Makefile.inc +++ b/src/mainboard/lenovo/t410/Makefile.inc @@ -21,4 +21,5 @@ romstage-y += dock.c ramstage-y += dock.c -romstage-y += gpio.c +romstage-$(CONFIG_MAINBOARD_LENOVO_X201) += variants/x201/gpio.c +romstage-$(CONFIG_MAINBOARD_LENOVO_T410) += variants/t410/gpio.c diff --git a/src/mainboard/lenovo/t410/dock.c b/src/mainboard/lenovo/t410/dock.c index 1575aa1..5c5f731 100644 --- a/src/mainboard/lenovo/t410/dock.c +++ b/src/mainboard/lenovo/t410/dock.c @@ -3,6 +3,7 @@ * * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> * Copyright (C) 2013 Vladimir Serbinenko <phcoder(a)gmail.com> + * Copyright (C) 2019 Maciej Matuszczyk * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -37,6 +38,9 @@ ec_set_bit(0x02, 0); ec_set_bit(0x1a, 0); ec_set_bit(0xfe, 4); + #if CONFIG(BOARD_LENOVO_X201) + set_gpio(28, GPIO_LEVEL_HICH); // Might also work ok t410, + #endif } void dock_disconnect(void) @@ -45,6 +49,9 @@ ec_clr_bit(0x02, 0); ec_clr_bit(0x1a, 0); ec_clr_bit(0xfe, 4); + #if CONFIG(BOARD_LENOVO_X201) + set_gpio(28, GPIO_LEVEL_LOW); + #endif } int dock_present(void) diff --git a/src/mainboard/lenovo/t410/hda_verb.c b/src/mainboard/lenovo/t410/hda_verb.c index 752e5da..c12e8b4 100644 --- a/src/mainboard/lenovo/t410/hda_verb.c +++ b/src/mainboard/lenovo/t410/hda_verb.c @@ -19,15 +19,27 @@ const u32 cim_verb_data[] = { /* coreboot specific header */ 0x14F15069, /* Codec Vendor / Device ID: Conexant CX20585 */ + #if CONFIG(BOARD_LENOVO_T410) 0x17AA214C, /* Subsystem ID */ + #elif CONFIG(BOARD_LENOVO_X201) + 0x17AA2155, /* Subsystem ID */ + #endif 0x0000000B, /* Number of 4 dword sets */ + #if CONFIG(BOARD_LENOVO_T410) AZALIA_SUBVENDOR(0x0, 0x17AA214C), + #elif CONFIG(BOARD_LENOVO_X201) + AZALIA_SUBVENDOR(0x0, 0x17AA2155), + #endif AZALIA_PIN_CFG(0x0, 0x19, 0x042110F0), AZALIA_PIN_CFG(0x0, 0x1A, 0x61A190F0), AZALIA_PIN_CFG(0x0, 0x1B, 0x04A110F0), AZALIA_PIN_CFG(0x0, 0x1C, 0x612140F0), + #if CONFIG(BOARD_LENOVO_T410) AZALIA_PIN_CFG(0x0, 0x1D, 0x40F001F0), + #elif CONFIG(BOARD_LENOVO_X201) + AZALIA_PIN_CFG(0x0, 0x1D, 0x601700F0), + #endif AZALIA_PIN_CFG(0x0, 0x1E, 0x40F001F0), AZALIA_PIN_CFG(0x0, 0x1F, 0x901701F0), AZALIA_PIN_CFG(0x0, 0x20, 0x40F001F0), @@ -35,7 +47,11 @@ AZALIA_PIN_CFG(0x0, 0x23, 0x90A601F0), 0x80862804, /* Codec Vendor / Device ID: Intel Ibexpeak HDMI. */ + #if CONFIG(BOARD_LENOVO_T410) 0x17AA21B5, /* Subsystem ID */ + #elif CONFIG(BOARD_LENOVO_X201) + 0x17aa21b5, /* Subsystem ID */ + #endif 0x00000004, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0x3, 0x17AA21B5), diff --git a/src/mainboard/lenovo/t410/mainboard.c b/src/mainboard/lenovo/t410/mainboard.c index 8b6a737..d961db1 100644 --- a/src/mainboard/lenovo/t410/mainboard.c +++ b/src/mainboard/lenovo/t410/mainboard.c @@ -4,6 +4,7 @@ * Copyright (C) 2007-2009 coresystems GmbH * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> * Copyright (C) 2013 Vladimir Serbinenko <phcoder(a)gmail.com> + * Copyright (C) 2019 Maciej Matuszczyk * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -17,12 +18,28 @@ */ #include <device/device.h> -#include <arch/acpi.h> -#include <drivers/intel/gma/int15.h> +#include <device/pci_ops.h> +#include <ec/acpi/ec.h> +#include <northbridge/intel/nehalem/nehalem.h> +#include <southbridge/intel/bd82x6x/pch.h> #include "dock.h" +#include <drivers/intel/gma/int15.h> +#include <cpu/x86/lapic.h> +#include <drivers/lenovo/lenovo.h> + +static void fill_ssdt(struct device *device) +{ + drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 0); +} static void mainboard_enable(struct device *dev) { + dev->ops->acpi_fill_ssdt_generator = fill_ssdt; + + /* If we're resuming from suspend, blink suspend LED */ + if (acpi_is_wakeup_s3()) + ec_write(0x0c, 0xc7); + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_LFP, 2); diff --git a/src/mainboard/lenovo/t410/romstage.c b/src/mainboard/lenovo/t410/romstage.c index 7c796de..df4228b 100644 --- a/src/mainboard/lenovo/t410/romstage.c +++ b/src/mainboard/lenovo/t410/romstage.c @@ -19,11 +19,11 @@ #include <stdint.h> #include <device/pci_ops.h> #include <southbridge/intel/ibexpeak/pch.h> -#include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h> #include <northbridge/intel/nehalem/nehalem.h> const struct southbridge_usb_port mainboard_usb_ports[] = { /* Enabled, Current table lookup index, OC map */ + #if CONFIG(BOARD_LENOVO_T410) { 1, IF1_557, 0 }, { 1, IF1_55F, 1 }, { 1, IF1_74B, 3 }, @@ -38,8 +38,26 @@ { 1, IF1_74B, 7 }, { 1, IF1_557, 7 }, { 1, IF1_55F, 7 }, + #elif CONFIG(BOARD_LENOVO_X201) + { 1, IF1_557, 0 }, + { 1, IF1_55F, 1 }, + { 1, IF1_74B, 3 }, + { 1, IF1_74B, 3 }, + { 1, IF1_557, 3 }, + { 1, IF1_14B, 3 }, + { 1, IF1_74B, 3 }, + { 1, IF1_74B, 3 }, + { 1, IF1_74B, 4 }, + { 1, IF1_74B, 5 }, + { 1, IF1_55F, 7 }, + { 1, IF1_55F, 7 }, + { 1, IF1_557, 7 }, + { 1, IF1_55F, 7 }, + #endif }; +#if CONFIG(BOARD_LENOVO_T410) +#include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h> static void hybrid_graphics_init(void) { bool peg, igd; @@ -62,14 +80,38 @@ pci_write_config32(PCI_DEV(0, 0, 0), D0F0_DEVEN, reg32); } +#endif + +static void set_fsb_frequency(void) +{ + u8 block[5]; + u16 fsbfreq = 62879; + smbus_block_read(0x69, 0, 5, block); + block[0] = fsbfreq; + block[1] = fsbfreq >> 8; + + smbus_block_write(0x69, 0, 5, block); +} void mainboard_pre_raminit(void) { + #if CONFIG(BOARD_LENOVO_T410) hybrid_graphics_init(); + #elif CONFIG(BOARD_LENOVO_X201) + outb((inb(DEFAULT_GPIOBASE | 0x3a) & ~0x2) | 0x20, + DEFAULT_GPIOBASE | 0x3a); + outb(0x50, 0x15ec); + outb(inb(0x15ee) & 0x70, 0x15ee); + + set_fsb_frequency(); } void mainboard_get_spd_map(u8 *spd_addrmap) { spd_addrmap[0] = 0x50; + #if CONFIG(BOARD_LENOVO_T410) spd_addrmap[2] = 0x52; + #elif CONFIG(BOARD_LENOVO_X201) + spd_addrmap[2] = 0x51; + #endif } diff --git a/src/mainboard/lenovo/x201/board_info.txt b/src/mainboard/lenovo/t410/variants/t410/board_info.txt similarity index 75% copy from src/mainboard/lenovo/x201/board_info.txt copy to src/mainboard/lenovo/t410/variants/t410/board_info.txt index b33cbaf..f27808b 100644 --- a/src/mainboard/lenovo/x201/board_info.txt +++ b/src/mainboard/lenovo/t410/variants/t410/board_info.txt @@ -1,5 +1,5 @@ Category: laptop -ROM package: SOIC-8 +ROM package: SOIC-8 / WSON-8 ROM protocol: SPI ROM socketed: n Flashrom support: n diff --git a/src/mainboard/lenovo/t410/data.vbt b/src/mainboard/lenovo/t410/variants/t410/data.vbt similarity index 100% rename from src/mainboard/lenovo/t410/data.vbt rename to src/mainboard/lenovo/t410/variants/t410/data.vbt Binary files differ diff --git a/src/mainboard/lenovo/t410/devicetree.cb b/src/mainboard/lenovo/t410/variants/t410/devicetree.cb similarity index 100% rename from src/mainboard/lenovo/t410/devicetree.cb rename to src/mainboard/lenovo/t410/variants/t410/devicetree.cb diff --git a/src/mainboard/lenovo/t410/gpio.c b/src/mainboard/lenovo/t410/variants/t410/gpio.c similarity index 100% rename from src/mainboard/lenovo/t410/gpio.c rename to src/mainboard/lenovo/t410/variants/t410/gpio.c diff --git a/src/mainboard/lenovo/x201/board_info.txt b/src/mainboard/lenovo/t410/variants/x201/board_info.txt similarity index 81% rename from src/mainboard/lenovo/x201/board_info.txt rename to src/mainboard/lenovo/t410/variants/x201/board_info.txt index b33cbaf..7eb5a66 100644 --- a/src/mainboard/lenovo/x201/board_info.txt +++ b/src/mainboard/lenovo/t410/variants/x201/board_info.txt @@ -2,5 +2,5 @@ ROM package: SOIC-8 ROM protocol: SPI ROM socketed: n -Flashrom support: n +Flashrom support: y Release year: 2010 diff --git a/src/mainboard/lenovo/x201/data.vbt b/src/mainboard/lenovo/t410/variants/x201/data.vbt similarity index 100% rename from src/mainboard/lenovo/x201/data.vbt rename to src/mainboard/lenovo/t410/variants/x201/data.vbt Binary files differ diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/t410/variants/x201/devicetree.cb similarity index 100% rename from src/mainboard/lenovo/x201/devicetree.cb rename to src/mainboard/lenovo/t410/variants/x201/devicetree.cb diff --git a/src/mainboard/lenovo/x201/gpio.c b/src/mainboard/lenovo/t410/variants/x201/gpio.c similarity index 100% rename from src/mainboard/lenovo/x201/gpio.c rename to src/mainboard/lenovo/t410/variants/x201/gpio.c diff --git a/src/mainboard/lenovo/x201/Kconfig b/src/mainboard/lenovo/x201/Kconfig deleted file mode 100644 index e40c0d3..0000000 --- a/src/mainboard/lenovo/x201/Kconfig +++ /dev/null @@ -1,71 +0,0 @@ -if BOARD_LENOVO_X201 - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select SYSTEM_TYPE_LAPTOP - select NORTHBRIDGE_INTEL_NEHALEM - select SOUTHBRIDGE_INTEL_IBEXPEAK - select EC_LENOVO_PMH7 - select EC_LENOVO_H8 - select NO_UART_ON_SUPERIO - select HAVE_OPTION_TABLE - select HAVE_CMOS_DEFAULT - select BOARD_ROMSIZE_KB_8192 - select HAVE_ACPI_TABLES - select INTEL_INT15 - select HAVE_ACPI_RESUME - select MAINBOARD_HAS_LIBGFXINIT - select SUPERIO_NSC_PC87382 - select DRIVERS_LENOVO_WACOM - select MAINBOARD_HAS_LPC_TPM - select MAINBOARD_HAS_TPM1 - select INTEL_GMA_HAVE_VBT - select MAINBOARD_USES_IFD_GBE_REGION - select H8_HAS_BAT_TRESHOLDS_IMPL - -config VBOOT - select VBOOT_VBNV_CMOS - select GBB_FLAG_DISABLE_LID_SHUTDOWN - select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC - select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC - select GBB_FLAG_DISABLE_FWMP - select HAS_RECOVERY_MRC_CACHE - -config VBOOT_SLOTS_RW_A - default y - -config VBOOT_VBNV_OFFSET - hex - default 0x2a - -config FMDFILE - string - default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT - -config MAINBOARD_DIR - string - default lenovo/x201 - -config MAINBOARD_PART_NUMBER - string - default "ThinkPad X201" - -config USBDEBUG_HCD_INDEX - int - default 2 - -config DRAM_RESET_GATE_GPIO - int - default 10 - -config MAX_CPUS - int - default 4 - -# Without the Intel ME's EFFS partition some PCIe devices (like the USB and SATA -# controllers) don't work as expected -config ME_CLEANER_ARGS - string - default "-S -w EFFS" - -endif diff --git a/src/mainboard/lenovo/x201/Kconfig.name b/src/mainboard/lenovo/x201/Kconfig.name deleted file mode 100644 index a73d224..0000000 --- a/src/mainboard/lenovo/x201/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_LENOVO_X201 - bool "ThinkPad X201 / X201i / X201s / X201t" diff --git a/src/mainboard/lenovo/x201/Makefile.inc b/src/mainboard/lenovo/x201/Makefile.inc deleted file mode 100644 index 548beff..0000000 --- a/src/mainboard/lenovo/x201/Makefile.inc +++ /dev/null @@ -1,24 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2008 coresystems GmbH -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -bootblock-y += early_init.c - -smm-y += dock.c -smm-y += smihandler.c -romstage-y += dock.c -ramstage-y += dock.c -romstage-y += gpio.c - -ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/lenovo/x201/acpi/dock.asl b/src/mainboard/lenovo/x201/acpi/dock.asl deleted file mode 100644 index 2bba821..0000000 --- a/src/mainboard/lenovo/x201/acpi/dock.asl +++ /dev/null @@ -1,72 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Scope (\_SB) -{ - Device(DOCK) - { - Name(_HID, "ACPI0003") - Name(_UID, 0x00) - Name(_PCL, Package() { \_SB } ) - - Method(_DCK, 1, NotSerialized) - { - if (Arg0) { - /* connect dock */ - Store (1, \GP28) - Store (1, \_SB.PCI0.LPCB.EC.DKR1) - Store (1, \_SB.PCI0.LPCB.EC.DKR2) - Store (1, \_SB.PCI0.LPCB.EC.DKR3) - } else { - /* disconnect dock */ - Store (0, \GP28) - Store (0, \_SB.PCI0.LPCB.EC.DKR1) - Store (0, \_SB.PCI0.LPCB.EC.DKR2) - Store (0, \_SB.PCI0.LPCB.EC.DKR3) - } - Xor(Arg0, \_SB.PCI0.LPCB.EC.DKR1, Local0) - Return (Local0) - } - - Method(_STA, 0, NotSerialized) - { - Return (\_SB.PCI0.LPCB.EC.DKR1) - } - } -} - -Scope(\_SB.PCI0.LPCB.EC) -{ - Method(_Q18, 0, NotSerialized) - { - Notify(\_SB.DOCK, 3) - } - - Method(_Q45, 0, NotSerialized) - { - Notify(\_SB.DOCK, 3) - } - - Method(_Q58, 0, NotSerialized) - { - Notify(\_SB.DOCK, 0) - } - - Method(_Q37, 0, NotSerialized) - { - Notify(\_SB.DOCK, 0) - } -} diff --git a/src/mainboard/lenovo/x201/acpi/ec.asl b/src/mainboard/lenovo/x201/acpi/ec.asl deleted file mode 100644 index 411a0ec..0000000 --- a/src/mainboard/lenovo/x201/acpi/ec.asl +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <ec/lenovo/h8/acpi/ec.asl> - -Scope(\_SB.PCI0.LPCB.EC) -{ -} - -#define H8_BAT_THRESHOLDS_BIT7 -#include <ec/lenovo/h8/acpi/thinkpad_bat_thresholds_24.asl> diff --git a/src/mainboard/lenovo/x201/acpi/gpe.asl b/src/mainboard/lenovo/x201/acpi/gpe.asl deleted file mode 100644 index 5c900ca..0000000 --- a/src/mainboard/lenovo/x201/acpi/gpe.asl +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Scope (\_GPE) -{ - Method(_L18, 0, NotSerialized) - { - /* Read EC register to clear wake status */ - Store(\_SB.PCI0.LPCB.EC.WAKE, Local0) - /* So that we don't get a warning that Local0 is unused. */ - Increment (Local0) - } -} diff --git a/src/mainboard/lenovo/x201/acpi/platform.asl b/src/mainboard/lenovo/x201/acpi/platform.asl deleted file mode 100644 index bcd6de6..0000000 --- a/src/mainboard/lenovo/x201/acpi/platform.asl +++ /dev/null @@ -1,132 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* The _PTS method (Prepare To Sleep) is called before the OS is - * entering a sleep state. The sleep state number is passed in Arg0 - */ - -Method(_PTS,1) -{ - \_SB.PCI0.LPCB.EC.MUTE(1) - \_SB.PCI0.LPCB.EC.USBP(0) - \_SB.PCI0.LPCB.EC.RADI(0) -} - -/* The _WAK method is called on system wakeup */ - -Method(_WAK,1) -{ - /* ME may not be up yet. */ - Store (0, \_TZ.MEB1) - Store (0, \_TZ.MEB2) - - /* Wake the HKEY to init BT/WWAN */ - \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) - - /* Not implemented. */ - Return(Package(){0,0}) -} - -Method(UCMS, 1, Serialized) -{ - Switch(ToInteger(Arg0)) - { - Case (0x0c) /* Turn on ThinkLight */ - { - \_SB.PCI0.LPCB.EC.LGHT(1) - } - Case (0x0d) /* Turn off ThinkLight */ - { - \_SB.PCI0.LPCB.EC.LGHT(0) - } - } -} - -/* System Bus */ - -Scope(\_SB) -{ - /* This method is placed on the top level, so we can make sure it's the - * first executed _INI method. - */ - Method(_INI, 0) - { - /* The DTS data in NVS is probably not up to date. - * Update temperature values and make sure AP thermal - * interrupts can happen - */ - - /* TRAP(71) */ /* TODO */ - - /* Determine the Operating System and save the value in OSYS. - * We have to do this in order to be able to work around - * certain windows bugs. - * - * OSYS value | Operating System - * -----------+------------------ - * 2000 | Windows 2000 - * 2001 | Windows XP(+SP1) - * 2002 | Windows XP SP2 - * 2006 | Windows Vista - * ???? | Windows 7 - */ - - /* Let's assume we're running at least Windows 2000 */ - Store (2000, OSYS) - - If (CondRefOf(_OSI)) { - If (_OSI("Windows 2001")) { - Store (2001, OSYS) - } - - If (_OSI("Windows 2001 SP1")) { - Store (2001, OSYS) - } - - If (_OSI("Windows 2001 SP2")) { - Store (2002, OSYS) - } - - If (_OSI("Windows 2001.1")) { - Store (2001, OSYS) - } - - If (_OSI("Windows 2001.1 SP1")) { - Store (2001, OSYS) - } - - If (_OSI("Windows 2006")) { - Store (2006, OSYS) - } - - If (_OSI("Windows 2006.1")) { - Store (2006, OSYS) - } - - If (_OSI("Windows 2006 SP1")) { - Store (2006, OSYS) - } - - If (_OSI("Windows 2009")) { - Store (2009, OSYS) - } - - If (_OSI("Windows 2012")) { - Store (2012, OSYS) - } - } - } -} diff --git a/src/mainboard/lenovo/x201/acpi/superio.asl b/src/mainboard/lenovo/x201/acpi/superio.asl deleted file mode 100644 index f2b35ba..0000000 --- a/src/mainboard/lenovo/x201/acpi/superio.asl +++ /dev/null @@ -1 +0,0 @@ -#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/lenovo/x201/acpi_tables.c b/src/mainboard/lenovo/x201/acpi_tables.c deleted file mode 100644 index 6fd47d7..0000000 --- a/src/mainboard/lenovo/x201/acpi_tables.c +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2013 Vladimir Serbinenko <phcoder(a)gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <southbridge/intel/ibexpeak/nvs.h> -#include "thermal.h" - -static void acpi_update_thermal_table(global_nvs_t *gnvs) -{ - gnvs->tcrt = CRITICAL_TEMPERATURE; - gnvs->tpsv = PASSIVE_TEMPERATURE; -} - -void acpi_create_gnvs(global_nvs_t * gnvs) -{ - acpi_update_thermal_table(gnvs); -} diff --git a/src/mainboard/lenovo/x201/cmos.default b/src/mainboard/lenovo/x201/cmos.default deleted file mode 100644 index 2cf484f..0000000 --- a/src/mainboard/lenovo/x201/cmos.default +++ /dev/null @@ -1,17 +0,0 @@ -boot_option=Fallback -debug_level=Debug -power_on_after_fail=Disable -nmi=Enable -volume=0x3 -first_battery=Primary -bluetooth=Enable -wwan=Enable -wlan=Enable -touchpad=Enable -trackpoint=Enable -fn_ctrl_swap=Disable -sticky_fn=Disable -power_management_beeps=Enable -low_battery_beep=Enable -sata_mode=AHCI -usb_always_on=Disable diff --git a/src/mainboard/lenovo/x201/cmos.layout b/src/mainboard/lenovo/x201/cmos.layout deleted file mode 100644 index 990db6d..0000000 --- a/src/mainboard/lenovo/x201/cmos.layout +++ /dev/null @@ -1,128 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2008 coresystems GmbH -## Copyright (C) 2013 Vladimir Serbinenko -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -# ----------------------------------------------------------------- -entries - -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused - -# ----------------------------------------------------------------- -# RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? - -# ----------------------------------------------------------------- -# coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused - -#400 8 r 0 reserved for century byte - -# coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail - -# coreboot config options: EC -411 1 e 8 first_battery -412 1 e 1 bluetooth -413 1 e 1 wwan -414 1 e 1 touchpad -415 1 e 1 wlan -416 1 e 1 trackpoint -417 1 e 1 fn_ctrl_swap -418 1 e 1 sticky_fn -419 1 e 1 power_management_beeps -420 1 e 1 low_battery_beep -421 1 e 9 sata_mode -422 2 e 11 usb_always_on -#423 1 r 1 unused - -# coreboot config options: northbridge -424 3 e 10 gfx_uma_size -#427 5 r 0 unused -432 8 h 0 volume - -# VBOOT -448 128 r 0 vbnv - -# coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved - -# ----------------------------------------------------------------- - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 Secondary -8 1 Primary -9 0 AHCI -9 1 Compatible -10 0 32M -10 1 48M -10 2 64M -10 3 128M -10 5 96M -10 6 160M -11 0 Disable -11 1 AC and battery -11 2 AC only - -# ----------------------------------------------------------------- -checksums - -checksum 392 415 984 diff --git a/src/mainboard/lenovo/x201/dock.c b/src/mainboard/lenovo/x201/dock.c deleted file mode 100644 index 58510ce..0000000 --- a/src/mainboard/lenovo/x201/dock.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> - * Copyright (C) 2013 Vladimir Serbinenko <phcoder(a)gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/device.h> -#include "dock.h" -#include <southbridge/intel/common/gpio.h> -#include <ec/lenovo/h8/h8.h> -#include <ec/acpi/ec.h> - -void init_dock(void) -{ - if (dock_present()) { - printk(BIOS_DEBUG, "dock is connected\n"); - dock_connect(); - } else - printk(BIOS_DEBUG, "dock is not connected\n"); -} - -void dock_connect(void) -{ - ec_set_bit(0x02, 0); - ec_set_bit(0x1a, 0); - ec_set_bit(0xfe, 4); - - set_gpio(28, GPIO_LEVEL_HIGH); -} - -void dock_disconnect(void) -{ - ec_clr_bit(0x02, 0); - ec_clr_bit(0x1a, 0); - ec_clr_bit(0xfe, 4); - - set_gpio(28, GPIO_LEVEL_LOW); -} - -int dock_present(void) -{ - const int dock_id_gpio[] = { 3, 4, 5, -1}; - - return get_gpios(dock_id_gpio) != 7; -} diff --git a/src/mainboard/lenovo/x201/dock.h b/src/mainboard/lenovo/x201/dock.h deleted file mode 100644 index 6a08d81..0000000 --- a/src/mainboard/lenovo/x201/dock.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef THINKPAD_X201_DOCK_H -#define THINKPAD_X201_DOCK_H -void init_dock(void); -void dock_connect(void); -void dock_disconnect(void); -int dock_present(void); -#endif diff --git a/src/mainboard/lenovo/x201/dsdt.asl b/src/mainboard/lenovo/x201/dsdt.asl deleted file mode 100644 index 9d0204e..0000000 --- a/src/mainboard/lenovo/x201/dsdt.asl +++ /dev/null @@ -1,94 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define THINKPAD_EC_GPE 17 -#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB -#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 -#define EC_LENOVO_H8_ME_WORKAROUND 1 - -#include <arch/acpi.h> -DefinitionBlock( - "dsdt.aml", - "DSDT", - 0x02, /* DSDT revision: ACPI v2.0 and up */ - OEM_ID, - ACPI_TABLE_CREATOR, - 0x20130325 /* OEM revision */ -) -{ - #include <southbridge/intel/common/acpi/platform.asl> - - /* Some generic macros */ - #include "acpi/platform.asl" - - /* global NVS and variables */ - #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> - - /* General Purpose Events */ - #include "acpi/gpe.asl" - - #include <cpu/intel/common/acpi/cpu.asl> - - Scope (\_SB) { - Device (PCI0) - { - #include <northbridge/intel/nehalem/acpi/nehalem.asl> - #include <southbridge/intel/bd82x6x/acpi/pch.asl> - - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> - } - Device (UNCR) - { - Name (_BBN, 0xFF) - Name (RID, 0x00) - Name (_HID, EisaId ("PNP0A03")) - Name (_CRS, ResourceTemplate () - { - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, /* Granularity */ - 0x00FF, /* Range Minimum */ - 0x00FF, /* Range Maximum */ - 0x0000, /* Translation Offset */ - 0x0001, /* Length */ - ,, ) - }) - Device (SAD) - { - Name (_ADR, 0x01) - Name (RID, 0x00) - OperationRegion (SADC, PCI_Config, 0x00, 0x0100) - Field (SADC, DWordAcc, NoLock, Preserve) - { - Offset (0x40), - PAM0, 8, - PAM1, 8, - PAM2, 8, - PAM3, 8, - PAM4, 8, - PAM5, 8, - PAM6, 8 - } - } - } - } - - /* Chipset specific sleep states */ - #include <southbridge/intel/common/acpi/sleepstates.asl> - - /* Dock support code */ - #include "acpi/dock.asl" -} diff --git a/src/mainboard/lenovo/x201/early_init.c b/src/mainboard/lenovo/x201/early_init.c deleted file mode 100644 index 7383381..0000000 --- a/src/mainboard/lenovo/x201/early_init.c +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> - * Copyright (C) 2013 Vladimir Serbinenko <phcoder(a)gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <bootblock_common.h> -#include <ec/acpi/ec.h> - -void bootblock_mainboard_early_init(void) -{ - /* Enable USB Power. We need to do it early for usbdebug to work. */ - ec_set_bit(0x3b, 4); -} diff --git a/src/mainboard/lenovo/x201/gma-mainboard.ads b/src/mainboard/lenovo/x201/gma-mainboard.ads deleted file mode 100644 index 9c2a3cb..0000000 --- a/src/mainboard/lenovo/x201/gma-mainboard.ads +++ /dev/null @@ -1,30 +0,0 @@ --- --- This file is part of the coreboot project. --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- - -with HW.GFX.GMA; -with HW.GFX.GMA.Display_Probing; - -use HW.GFX.GMA; -use HW.GFX.GMA.Display_Probing; - -private package GMA.Mainboard is - - ports : constant Port_List := - (DP2, -- DP++ connector on the dock - HDMI2, - Analog, - Internal, - others => Disabled); - -end GMA.Mainboard; diff --git a/src/mainboard/lenovo/x201/hda_verb.c b/src/mainboard/lenovo/x201/hda_verb.c deleted file mode 100644 index 820e2c5..0000000 --- a/src/mainboard/lenovo/x201/hda_verb.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Vladimir Serbinenko. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License, - * or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/azalia_device.h> - -const u32 cim_verb_data[] = { - /* coreboot specific header */ - 0x14F15069, /* Codec Vendor / Device ID: Conexant CX20585 */ - 0x17AA2155, /* Subsystem ID */ - 0x0000000B, /* Number of 4 dword sets */ - - /* NID 0x01: Subsystem ID. */ - AZALIA_SUBVENDOR(0x0, 0x17AA2155), - - /* NID 0x19: Headphone jack. */ - AZALIA_PIN_CFG(0x0, 0x19, 0x042140F0), - - /* NID 0x1A: Dock mic jack. */ - AZALIA_PIN_CFG(0x0, 0x1A, 0x61A190F0), - - /* NID 0x1B: Mic jack. */ - AZALIA_PIN_CFG(0x0, 0x1B, 0x04A190F0), - - /* NID 0x1C: Dock headphone jack. */ - AZALIA_PIN_CFG(0x0, 0x1C, 0x612140F0), - - /* NID 0x1D: EAPD detect. */ - AZALIA_PIN_CFG(0x0, 0x1D, 0x601700F0), - - /* NID 0x1E */ - AZALIA_PIN_CFG(0x0, 0x1E, 0x40F001F0), - - /* NID 0x1F */ - AZALIA_PIN_CFG(0x0, 0x1F, 0x901701F0), - - /* NID 0x20 */ - AZALIA_PIN_CFG(0x0, 0x20, 0x40F001F0), - - /* NID 0x22 */ - AZALIA_PIN_CFG(0x0, 0x22, 0x40F001F0), - - /* NID 0x23: Internal mic boost volume. */ - AZALIA_PIN_CFG(0x0, 0x23, 0x90A601F0), - - 0x80862804, /* Codec Vendor / Device ID: Intel Ibexpeak HDMI. */ - 0x17aa21b5, /* Subsystem ID */ - 0x00000004, /* Number of 4 dword sets */ - - /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x17aa21b5 */ - AZALIA_SUBVENDOR(0x3, 0x17AA21B5), - - /* NID 0x04. */ - AZALIA_PIN_CFG(0x3, 0x04, 0x58560010), - - /* NID 0x05. */ - AZALIA_PIN_CFG(0x3, 0x05, 0x18560020), - - /* NID 0x06. */ - AZALIA_PIN_CFG(0x3, 0x06, 0x58560030), -}; - -const u32 pc_beep_verbs[0] = {}; - -AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c deleted file mode 100644 index a403237..0000000 --- a/src/mainboard/lenovo/x201/mainboard.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> - * Copyright (C) 2013 Vladimir Serbinenko <phcoder(a)gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/device.h> -#include <device/pci_ops.h> -#include <ec/acpi/ec.h> -#include <northbridge/intel/nehalem/nehalem.h> -#include <southbridge/intel/bd82x6x/pch.h> -#include "dock.h" -#include <drivers/intel/gma/int15.h> -#include <cpu/x86/lapic.h> -#include <drivers/lenovo/lenovo.h> - -static void fill_ssdt(struct device *device) -{ - drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 0); -} - -static void mainboard_enable(struct device *dev) -{ - dev->ops->acpi_fill_ssdt_generator = fill_ssdt; - - /* If we're resuming from suspend, blink suspend LED */ - if (acpi_is_wakeup_s3()) - ec_write(0x0c, 0xc7); - - install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, - GMA_INT15_PANEL_FIT_DEFAULT, - GMA_INT15_BOOT_DISPLAY_LFP, 2); - - init_dock(); -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c deleted file mode 100644 index 99875ed..0000000 --- a/src/mainboard/lenovo/x201/romstage.c +++ /dev/null @@ -1,70 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> - * Copyright (C) 2013 Vladimir Serbinenko <phcoder(a)gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <arch/io.h> -#include <device/pci_ops.h> -#include <ec/acpi/ec.h> - -#include <southbridge/intel/ibexpeak/pch.h> -#include <northbridge/intel/nehalem/nehalem.h> - -const struct southbridge_usb_port mainboard_usb_ports[] = { - /* Enabled, Current table lookup index, OC map */ - { 1, IF1_557, 0 }, - { 1, IF1_55F, 1 }, - { 1, IF1_74B, 3 }, - { 1, IF1_74B, 3 }, - { 1, IF1_557, 3 }, - { 1, IF1_14B, 3 }, - { 1, IF1_74B, 3 }, - { 1, IF1_74B, 3 }, - { 1, IF1_74B, 4 }, - { 1, IF1_74B, 5 }, - { 1, IF1_55F, 7 }, - { 1, IF1_55F, 7 }, - { 1, IF1_557, 7 }, - { 1, IF1_55F, 7 }, -}; - -static void set_fsb_frequency(void) -{ - u8 block[5]; - u16 fsbfreq = 62879; - smbus_block_read(0x69, 0, 5, block); - block[0] = fsbfreq; - block[1] = fsbfreq >> 8; - - smbus_block_write(0x69, 0, 5, block); -} - -void mainboard_pre_raminit(void) -{ - outb((inb(DEFAULT_GPIOBASE | 0x3a) & ~0x2) | 0x20, - DEFAULT_GPIOBASE | 0x3a); - outb(0x50, 0x15ec); - outb(inb(0x15ee) & 0x70, 0x15ee); - - set_fsb_frequency(); -} - -void mainboard_get_spd_map(u8 *spd_addrmap) -{ - spd_addrmap[0] = 0x50; - spd_addrmap[2] = 0x51; -} diff --git a/src/mainboard/lenovo/x201/smihandler.c b/src/mainboard/lenovo/x201/smihandler.c deleted file mode 100644 index 4ba10b4..0000000 --- a/src/mainboard/lenovo/x201/smihandler.c +++ /dev/null @@ -1,110 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <console/console.h> -#include <cpu/x86/smm.h> -#include <southbridge/intel/ibexpeak/nvs.h> -#include <southbridge/intel/common/pmutil.h> -#include <northbridge/intel/nehalem/nehalem.h> -#include <ec/acpi/ec.h> -#include <ec/lenovo/h8/h8.h> -#include <delay.h> -#include "dock.h" - -#define GPE_EC_SCI 1 -#define GPE_EC_WAKE 13 - -static void mainboard_smi_handle_ec_sci(void) -{ - u8 status = inb(EC_SC); - u8 event; - - if (!(status & EC_SCI_EVT)) - return; - - event = ec_query(); - printk(BIOS_DEBUG, "EC event %02x\n", event); - - switch (event) { - case 0x18: - /* Fn-F9 key */ - case 0x27: - /* Power loss */ - case 0x50: - /* Undock Key */ - ec_clr_bit(0x03, 2); - dock_disconnect(); - break; - case 0x37: - case 0x58: - /* Dock Event */ - ec_clr_bit(0x03, 2); - udelay(250000); - dock_connect(); - ec_set_bit(0x03, 2); - /* set dock LED to indicate status */ - ec_write(0x0c, 0x09); - ec_write(0x0c, 0x88); - break; - default: - break; - } -} - -void mainboard_smi_gpi(u32 gpi_sts) -{ - if (gpi_sts & (1 << GPE_EC_SCI)) - mainboard_smi_handle_ec_sci(); -} - -int mainboard_smi_apmc(u8 data) -{ - switch (data) { - case APM_CNT_ACPI_ENABLE: - /* use 0x1600/0x1604 to prevent races with userspace */ - ec_set_ports(0x1604, 0x1600); - /* route H8SCI to SCI */ - gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI); - /* discard all events, and enable attention */ - ec_write(0x80, 0x01); - break; - case APM_CNT_ACPI_DISABLE: - /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't - provide a EC query function */ - ec_set_ports(0x66, 0x62); - /* route H8SCI# to SMI */ - gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI); - /* discard all events, and enable attention */ - ec_write(0x80, 0x01); - break; - default: - break; - } - return 0; -} - -void mainboard_smi_sleep(u8 slp_typ) -{ - if (slp_typ == 3) { - u8 ec_wake = ec_read(0x32); - /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ - if (ec_wake & 0x14) { - /* Redirect EC WAKE GPE to SCI. */ - gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI); - } - } -} diff --git a/src/mainboard/lenovo/x201/thermal.h b/src/mainboard/lenovo/x201/thermal.h deleted file mode 100644 index 72953fd..0000000 --- a/src/mainboard/lenovo/x201/thermal.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> - * Copyright (C) 2017 James Ye <jye836(a)gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_THERMAL_H -#define MAINBOARD_THERMAL_H - -/* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 100 - -/* Temperature which OS will throttle CPU */ -#define PASSIVE_TEMPERATURE 90 - -#endif /* MAINBOARD_THERMAL_H */ diff --git a/src/mainboard/lenovo/x201/vboot-rwa.fmd b/src/mainboard/lenovo/x201/vboot-rwa.fmd deleted file mode 100644 index 0d1aa5d..0000000 --- a/src/mainboard/lenovo/x201/vboot-rwa.fmd +++ /dev/null @@ -1,30 +0,0 @@ -FLASH@0xff800000 0x800000 { - SI_ALL@0x0 0x500000 { - SI_DESC@0x0 0x1000 - SI_GBE@0x1000 0x2000 - SI_ME@0x3000 0x4ed000 - } - SI_BIOS@0x500000 0x300000 { - RW_SECTION_A 0x180000 { - VBLOCK_A 0x10000 - FW_MAIN_A(CBFS) - RW_FWID_A 0x40 - } - UNIFIED_MRC_CACHE 0x20000 { - RECOVERY_MRC_CACHE 0x10000 - RW_MRC_CACHE 0x10000 - } - RW_VPD(PRESERVE) 0x1000 - SMMSTORE(PRESERVE) 0x40000 - WP_RO { - RO_VPD(PRESERVE) 0x1000 - RO_SECTION { - FMAP 0x800 - RO_FRID 0x40 - RO_PADDING 0x7c0 - GBB 0x1e000 - COREBOOT(CBFS) - } - } - } -} -- To view, visit https://review.coreboot.org/c/coreboot/+/36871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icfa1818812347ceb4e2de5cc4a3130537a4e13e7 Gerrit-Change-Number: 36871 Gerrit-PatchSet: 1 Gerrit-Owner: Maccraft123 <maccraft123mc(a)gmail.com> Gerrit-MessageType: newchange

5 36

Change in coreboot[master]: [NOTFORMERGE]mb/*/*: Drop BINARYPI_LEGACY_WRAPPER boards
by Arthur Heymans (Code Review) 07 Aug '23

07 Aug '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37076 ) Change subject: [NOTFORMERGE]mb/*/*: Drop BINARYPI_LEGACY_WRAPPER boards ...................................................................... [NOTFORMERGE]mb/*/*: Drop BINARYPI_LEGACY_WRAPPER boards Change-Id: Ia3ffc6ef36bc42f58515dfb2674633c167c732fd Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- D src/mainboard/amd/bettong/BiosCallOuts.c D src/mainboard/amd/bettong/BiosCallOuts.h D src/mainboard/amd/bettong/Kconfig D src/mainboard/amd/bettong/Kconfig.name D src/mainboard/amd/bettong/Makefile.inc D src/mainboard/amd/bettong/OemCustomize.c D src/mainboard/amd/bettong/README D src/mainboard/amd/bettong/acpi/carrizo_fch.asl D src/mainboard/amd/bettong/acpi/gpe.asl D src/mainboard/amd/bettong/acpi/mainboard.asl D src/mainboard/amd/bettong/acpi/routing.asl D src/mainboard/amd/bettong/acpi/sleep.asl D src/mainboard/amd/bettong/acpi/usb_oc.asl D src/mainboard/amd/bettong/acpi_tables.c D src/mainboard/amd/bettong/board_info.txt D src/mainboard/amd/bettong/boardid.c D src/mainboard/amd/bettong/cmos.layout D src/mainboard/amd/bettong/devicetree.cb D src/mainboard/amd/bettong/dsdt.asl D src/mainboard/amd/bettong/fchec.c D src/mainboard/amd/bettong/irq_tables.c D src/mainboard/amd/bettong/mainboard.c D src/mainboard/amd/bettong/mptable.c D src/mainboard/amd/bettong/romstage.c D src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c D src/mainboard/amd/db-ft3b-lc/Kconfig D src/mainboard/amd/db-ft3b-lc/Kconfig.name D src/mainboard/amd/db-ft3b-lc/Makefile.inc D src/mainboard/amd/db-ft3b-lc/Memphis_MEM4G16D3EABG.spd.hex D src/mainboard/amd/db-ft3b-lc/OemCustomize.c D src/mainboard/amd/db-ft3b-lc/acpi/gpe.asl D src/mainboard/amd/db-ft3b-lc/acpi/ide.asl D src/mainboard/amd/db-ft3b-lc/acpi/mainboard.asl D src/mainboard/amd/db-ft3b-lc/acpi/routing.asl D src/mainboard/amd/db-ft3b-lc/acpi/si.asl D src/mainboard/amd/db-ft3b-lc/acpi/sleep.asl D src/mainboard/amd/db-ft3b-lc/acpi/thermal.asl D src/mainboard/amd/db-ft3b-lc/acpi/usb_oc.asl D src/mainboard/amd/db-ft3b-lc/acpi_tables.c D src/mainboard/amd/db-ft3b-lc/board_info.txt D src/mainboard/amd/db-ft3b-lc/cmos.layout D src/mainboard/amd/db-ft3b-lc/devicetree.cb D src/mainboard/amd/db-ft3b-lc/dsdt.asl D src/mainboard/amd/db-ft3b-lc/irq_tables.c D src/mainboard/amd/db-ft3b-lc/mainboard.c D src/mainboard/amd/db-ft3b-lc/mptable.c D src/mainboard/amd/db-ft3b-lc/romstage.c D src/mainboard/amd/lamar/BiosCallOuts.c D src/mainboard/amd/lamar/Kconfig D src/mainboard/amd/lamar/Kconfig.name D src/mainboard/amd/lamar/Makefile.inc D src/mainboard/amd/lamar/OemCustomize.c D src/mainboard/amd/lamar/acpi/gpe.asl D src/mainboard/amd/lamar/acpi/mainboard.asl D src/mainboard/amd/lamar/acpi/routing.asl D src/mainboard/amd/lamar/acpi/si.asl D src/mainboard/amd/lamar/acpi/sleep.asl D src/mainboard/amd/lamar/acpi/thermal.asl D src/mainboard/amd/lamar/acpi/usb_oc.asl D src/mainboard/amd/lamar/acpi_tables.c D src/mainboard/amd/lamar/board_info.txt D src/mainboard/amd/lamar/cmos.layout D src/mainboard/amd/lamar/devicetree.cb D src/mainboard/amd/lamar/dsdt.asl D src/mainboard/amd/lamar/irq_tables.c D src/mainboard/amd/lamar/mainboard.c D src/mainboard/amd/lamar/mptable.c D src/mainboard/amd/lamar/romstage.c D src/mainboard/amd/olivehillplus/BiosCallOuts.c D src/mainboard/amd/olivehillplus/Kconfig D src/mainboard/amd/olivehillplus/Kconfig.name D src/mainboard/amd/olivehillplus/Makefile.inc D src/mainboard/amd/olivehillplus/OemCustomize.c D src/mainboard/amd/olivehillplus/acpi/gpe.asl D src/mainboard/amd/olivehillplus/acpi/ide.asl D src/mainboard/amd/olivehillplus/acpi/mainboard.asl D src/mainboard/amd/olivehillplus/acpi/routing.asl D src/mainboard/amd/olivehillplus/acpi/si.asl D src/mainboard/amd/olivehillplus/acpi/sleep.asl D src/mainboard/amd/olivehillplus/acpi/thermal.asl D src/mainboard/amd/olivehillplus/acpi/usb_oc.asl D src/mainboard/amd/olivehillplus/acpi_tables.c D src/mainboard/amd/olivehillplus/board_info.txt D src/mainboard/amd/olivehillplus/cmos.layout D src/mainboard/amd/olivehillplus/devicetree.cb D src/mainboard/amd/olivehillplus/dsdt.asl D src/mainboard/amd/olivehillplus/irq_tables.c D src/mainboard/amd/olivehillplus/mainboard.c D src/mainboard/amd/olivehillplus/mptable.c D src/mainboard/amd/olivehillplus/romstage.c D src/mainboard/bap/ode_e21XX/BAP_Q7_1066.spd.hex D src/mainboard/bap/ode_e21XX/BAP_Q7_1333.spd.hex D src/mainboard/bap/ode_e21XX/BAP_Q7_800.spd.hex D src/mainboard/bap/ode_e21XX/BiosCallOuts.c D src/mainboard/bap/ode_e21XX/Kconfig D src/mainboard/bap/ode_e21XX/Kconfig.name D src/mainboard/bap/ode_e21XX/Makefile.inc D src/mainboard/bap/ode_e21XX/OemCustomize.c D src/mainboard/bap/ode_e21XX/acpi/gpe.asl D src/mainboard/bap/ode_e21XX/acpi/ide.asl D src/mainboard/bap/ode_e21XX/acpi/mainboard.asl D src/mainboard/bap/ode_e21XX/acpi/routing.asl D src/mainboard/bap/ode_e21XX/acpi/si.asl D src/mainboard/bap/ode_e21XX/acpi/sleep.asl D src/mainboard/bap/ode_e21XX/acpi/superio.asl D src/mainboard/bap/ode_e21XX/acpi/thermal.asl D src/mainboard/bap/ode_e21XX/acpi/usb_oc.asl D src/mainboard/bap/ode_e21XX/acpi_tables.c D src/mainboard/bap/ode_e21XX/board_info.txt D src/mainboard/bap/ode_e21XX/cmos.layout D src/mainboard/bap/ode_e21XX/devicetree.cb D src/mainboard/bap/ode_e21XX/dsdt.asl D src/mainboard/bap/ode_e21XX/irq_tables.c D src/mainboard/bap/ode_e21XX/mainboard.c D src/mainboard/bap/ode_e21XX/mptable.c D src/mainboard/bap/ode_e21XX/romstage.c D src/mainboard/pcengines/apu2/BiosCallOuts.c D src/mainboard/pcengines/apu2/Kconfig D src/mainboard/pcengines/apu2/Kconfig.name D src/mainboard/pcengines/apu2/Makefile.inc D src/mainboard/pcengines/apu2/OemCustomize.c D src/mainboard/pcengines/apu2/acpi/gpe.asl D src/mainboard/pcengines/apu2/acpi/mainboard.asl D src/mainboard/pcengines/apu2/acpi/routing.asl D src/mainboard/pcengines/apu2/acpi/si.asl D src/mainboard/pcengines/apu2/acpi/sleep.asl D src/mainboard/pcengines/apu2/acpi/usb_oc.asl D src/mainboard/pcengines/apu2/acpi_tables.c D src/mainboard/pcengines/apu2/board_info.txt D src/mainboard/pcengines/apu2/cmos.layout D src/mainboard/pcengines/apu2/dsdt.asl D src/mainboard/pcengines/apu2/gpio_ftns.c D src/mainboard/pcengines/apu2/gpio_ftns.h D src/mainboard/pcengines/apu2/irq_tables.c D src/mainboard/pcengines/apu2/mainboard.c D src/mainboard/pcengines/apu2/mptable.c D src/mainboard/pcengines/apu2/romstage.c D src/mainboard/pcengines/apu2/spd/HYNIX-2G-1333.spd.hex D src/mainboard/pcengines/apu2/spd/HYNIX-4G-1333-ECC.spd.hex D src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb D src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb D src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb D src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb 143 files changed, 0 insertions(+), 12,816 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/37076/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/37076 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia3ffc6ef36bc42f58515dfb2674633c167c732fd Gerrit-Change-Number: 37076 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-MessageType: newchange

2 1

Change in coreboot[master]: mb/google/octopus: test
by Regan Chang (Code Review) 07 Aug '23

07 Aug '23

Regan Chang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37268 ) Change subject: mb/google/octopus: test ...................................................................... mb/google/octopus: test Create new variant for Lick . Nothing is changed in the variant files. Signed-off-by: Regan Chang <regan.chang(a)lcfc.corp-partner.google.com> Change-Id: I6b1a79b022a0c698174dd08f3c11769a4fd6833c --- A compile.status M src/mainboard/google/octopus/Kconfig M src/mainboard/google/octopus/Kconfig.name A src/mainboard/google/octopus/variants/lick/Makefile.inc A src/mainboard/google/octopus/variants/lick/gpio.c A src/mainboard/google/octopus/variants/lick/include/variant/acpi/dptf.asl A src/mainboard/google/octopus/variants/lick/include/variant/ec.h A src/mainboard/google/octopus/variants/lick/include/variant/gpio.h A src/mainboard/google/octopus/variants/lick/mainboard.c A src/mainboard/google/octopus/variants/lick/overridetree.cb A src/mainboard/google/octopus/variants/lick/variant.c 11 files changed, 408 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/37268/1 diff --git a/compile.status b/compile.status new file mode 100644 index 0000000..74bb638 --- /dev/null +++ b/compile.status @@ -0,0 +1 @@ +failed diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig index 65a641b..f97b66d 100644 --- a/src/mainboard/google/octopus/Kconfig +++ b/src/mainboard/google/octopus/Kconfig @@ -63,6 +63,7 @@ default "octopus" if BOARD_GOOGLE_OCTOPUS default "garg" if BOARD_GOOGLE_GARG default "dood" if BOARD_GOOGLE_DOOD + default "lick" if BOARD_GOOGLE_LICK config DEVICETREE string @@ -85,6 +86,7 @@ default "Octopus" if BOARD_GOOGLE_OCTOPUS default "Garg" if BOARD_GOOGLE_GARG default "Dood" if BOARD_GOOGLE_DOOD + default "Lick" if BOARD_GOOGLE_LICK config MAINBOARD_FAMILY string @@ -119,6 +121,7 @@ default y if BOARD_GOOGLE_OCTOPUS default y if BOARD_GOOGLE_PHASER default y if BOARD_GOOGLE_YORP + default y if BOARD_GOOGLE_LICK config DRAM_PART_IN_CBI_BOARD_ID_MIN int @@ -129,5 +132,6 @@ default 3 if BOARD_GOOGLE_BOBBA default 1 if BOARD_GOOGLE_MEEP default 255 if BOARD_GOOGLE_OCTOPUS + default 2 if BOARD_GOOGLE_LICK endif # BOARD_GOOGLE_OCTOPUS diff --git a/src/mainboard/google/octopus/Kconfig.name b/src/mainboard/google/octopus/Kconfig.name index 8a8d339..b1f589d 100644 --- a/src/mainboard/google/octopus/Kconfig.name +++ b/src/mainboard/google/octopus/Kconfig.name @@ -64,3 +64,9 @@ select BASEBOARD_OCTOPUS_LAPTOP select BOARD_GOOGLE_BASEBOARD_OCTOPUS select NHLT_DA7219 if INCLUDE_NHLT_BLOBS + +config BOARD_GOOGLE_LICK + bool "-> Lick" + select BASEBOARD_OCTOPUS_LAPTOP + select BOARD_GOOGLE_BASEBOARD_OCTOPUS + select NHLT_DA7219 if INCLUDE_NHLT_BLOBS diff --git a/src/mainboard/google/octopus/variants/lick/Makefile.inc b/src/mainboard/google/octopus/variants/lick/Makefile.inc new file mode 100644 index 0000000..37270eb --- /dev/null +++ b/src/mainboard/google/octopus/variants/lick/Makefile.inc @@ -0,0 +1,5 @@ +bootblock-y += gpio.c + +ramstage-y += variant.c +ramstage-y += gpio.c +ramstage-y += mainboard.c diff --git a/src/mainboard/google/octopus/variants/lick/gpio.c b/src/mainboard/google/octopus/variants/lick/gpio.c new file mode 100644 index 0000000..281bde0 --- /dev/null +++ b/src/mainboard/google/octopus/variants/lick/gpio.c @@ -0,0 +1,90 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <boardid.h> +#include <gpio.h> +#include <soc/gpio.h> +#include <ec/google/chromeec/ec.h> + +#define SKU_UNKNOWN 0xFFFFFFFF + +static const struct pad_config default_override_table[] = { + PAD_NC(GPIO_52, UP_20K), + PAD_NC(GPIO_53, UP_20K), + PAD_NC(GPIO_67, UP_20K), + PAD_NC(GPIO_117, UP_20K), + PAD_NC(GPIO_143, UP_20K), + + /* EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0, + DISPUPD), + + PAD_NC(GPIO_161, DN_20K), + + PAD_NC(GPIO_213, DN_20K), + PAD_NC(GPIO_214, DN_20K), +}; + +static const struct pad_config sku1_default_override_table[] = { + /* disable I2C7 SCL and SDA */ + PAD_NC(GPIO_114, UP_20K), /* LPSS_I2C7_SDA */ + PAD_NC(GPIO_115, UP_20K), /* LPSS_I2C7_SCL */ + + PAD_NC(GPIO_52, UP_20K), + PAD_NC(GPIO_53, UP_20K), + PAD_NC(GPIO_67, UP_20K), + PAD_NC(GPIO_117, UP_20K), + PAD_NC(GPIO_143, UP_20K), + + /* EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0, + DISPUPD), + + PAD_NC(GPIO_161, DN_20K), + + /* EN_PP3300_WLAN_L */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_178, 0, DEEP, NONE, Tx0RxDCRx0, + DISPUPD), + + PAD_NC(GPIO_213, DN_20K), + PAD_NC(GPIO_214, DN_20K), +}; + +bool no_touchscreen_sku(uint32_t sku_id) +{ + if ((sku_id == 1) || (sku_id == 6)) + return true; + else + return false; +} + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + const struct pad_config *c; + uint32_t sku_id = SKU_UNKNOWN; + + google_chromeec_cbi_get_sku_id(&sku_id); + if (no_touchscreen_sku(sku_id)) { + c = sku1_default_override_table; + *num = ARRAY_SIZE(sku1_default_override_table); + } else { + c = default_override_table; + *num = ARRAY_SIZE(default_override_table); + } + + return c; +} diff --git a/src/mainboard/google/octopus/variants/lick/include/variant/acpi/dptf.asl b/src/mainboard/google/octopus/variants/lick/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..cc17d56 --- /dev/null +++ b/src/mainboard/google/octopus/variants/lick/include/variant/acpi/dptf.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/acpi/dptf.asl> diff --git a/src/mainboard/google/octopus/variants/lick/include/variant/ec.h b/src/mainboard/google/octopus/variants/lick/include/variant/ec.h new file mode 100644 index 0000000..16f931b --- /dev/null +++ b/src/mainboard/google/octopus/variants/lick/include/variant/ec.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/octopus/variants/lick/include/variant/gpio.h b/src/mainboard/google/octopus/variants/lick/include/variant/gpio.h new file mode 100644 index 0000000..1fd1e11 --- /dev/null +++ b/src/mainboard/google/octopus/variants/lick/include/variant/gpio.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <baseboard/gpio.h> + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/octopus/variants/lick/mainboard.c b/src/mainboard/google/octopus/variants/lick/mainboard.c new file mode 100644 index 0000000..2d44830 --- /dev/null +++ b/src/mainboard/google/octopus/variants/lick/mainboard.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boardid.h> +#include <ec/google/chromeec/ec.h> +#include <sar.h> + +const char *get_wifi_sar_cbfs_filename(void) +{ + const char *filename = NULL; + uint32_t sku_id; + + if (google_chromeec_cbi_get_sku_id(&sku_id)) + return NULL; + + if (sku_id == 5) + filename = "wifi_sar-laser.hex"; + + return filename; +} diff --git a/src/mainboard/google/octopus/variants/lick/overridetree.cb b/src/mainboard/google/octopus/variants/lick/overridetree.cb new file mode 100644 index 0000000..625c2a6 --- /dev/null +++ b/src/mainboard/google/octopus/variants/lick/overridetree.cb @@ -0,0 +1,176 @@ +chip soc/intel/apollolake + + # EMMC Tx CMD Delay + # Refer to EDS-Vol2-16.32. + # [14:8] steps of delay for DDR mode, each 125ps. + # [6:0] steps of delay for SDR mode, each 125ps. + register "emmc_tx_cmd_cntl" = "0x505" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-16.33. + # [14:8] steps of delay for HS400, each 125ps. + # [6:0] steps of delay for SDR104/HS200, each 125ps. + register "emmc_tx_data_cntl1" = "0x0b0c" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-16.34. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_tx_data_cntl2" = "0x1c282929" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-16.35. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_rx_cmd_data_cntl1" = "0x00181b1b" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-16.37. + # [17:16] stands for Rx Clock before Output Buffer + # [14:8] steps of delay for Auto Tuning Mode, each 125ps. + # [6:0] steps of delay for HS200, each 125ps. + register "emmc_rx_cmd_data_cntl2" = "0x10028" + + # EMMC Rx Strobe Delay + # Refer to EDS-Vol2-16.36. + # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps. + # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps. + register "emmc_rx_strobe_cntl" = "0x0b0b" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | Digitizer | + #| I2C5 | Audio | + #| I2C6 | Trackpad | + #| I2C7 | Touchscreen | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 66, + .fall_time_ns = 90, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 104, + .fall_time_ns = 52, + }, + .i2c[6] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 66, + .fall_time_ns = 90, + .data_hold_time_ns = 350, + }, + .i2c[7] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 76, + .fall_time_ns = 164, + }, + }" + + device domain 0 on + device pci 16.0 on + chip drivers/i2c/hid + register "generic.hid" = ""WCOM50C1"" + register "generic.desc" = ""WCOM Digitizer"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_139_IRQ)" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" + register "generic.reset_delay_ms" = "20" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x1" + device i2c 0x9 on end + end + end # - I2C 0 + device pci 17.1 on + chip drivers/i2c/da7219 + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_137_IRQ)" + register "btn_cfg" = "50" + register "mic_det_thr" = "500" + register "jack_ins_deb" = "20" + register "jack_det_rate" = ""32ms_64ms"" + register "jack_rem_deb" = "1" + register "a_d_btn_thr" = "0xa" + register "d_b_btn_thr" = "0x16" + register "b_c_btn_thr" = "0x21" + register "c_mic_btn_thr" = "0x3e" + register "btn_avg" = "4" + register "adc_1bit_rpt" = "1" + register "micbias_lvl" = "2600" + register "mic_amp_in_sel" = ""diff"" + device i2c 1a on end + end + end # - I2C 5 + device pci 17.2 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPIO_135_IRQ)" + register "wake" = "GPE0_DW3_27" + register "probed" = "1" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPIO_135_IRQ)" + register "generic.wake" = "GPE0_DW3_27" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 0x2c on end + end + end # - I2C 6 + device pci 17.3 on + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" + register "reset_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" + register "enable_delay_ms" = "1" + register "has_power_resource" = "1" + device i2c 10 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""SYTS7817"" + register "generic.desc" = ""Synaptics Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" + register "generic.reset_delay_ms" = "45" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 20 on end + end + chip drivers/i2c/generic + register "hid" = ""RAYD0001"" + register "desc" = ""Raydium Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" + register "reset_delay_ms" = "1" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" + register "enable_delay_ms" = "50" + register "has_power_resource" = "1" + device i2c 39 on end + end + end # - I2C 7 + end +end diff --git a/src/mainboard/google/octopus/variants/lick/variant.c b/src/mainboard/google/octopus/variants/lick/variant.c new file mode 100644 index 0000000..aeefda5 --- /dev/null +++ b/src/mainboard/google/octopus/variants/lick/variant.c @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/variants.h> +#include <soc/pci_devs.h> +#include <ec/google/chromeec/ec.h> + +#define SKU_UNKNOWN 0xFFFFFFFF + +void variant_update_devtree(struct device *dev) +{ + uint32_t sku_id = SKU_UNKNOWN; + struct device *touchscreen_i2c_host; + + touchscreen_i2c_host = pcidev_path_on_root(PCH_DEVFN_I2C7); + + if (touchscreen_i2c_host == NULL) + return; + + /* SKU ID 1, 6 does not have a touchscreen device, hence disable it. */ + google_chromeec_cbi_get_sku_id(&sku_id); + if (no_touchscreen_sku(sku_id)) + touchscreen_i2c_host->enabled = 0; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/37268 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b1a79b022a0c698174dd08f3c11769a4fd6833c Gerrit-Change-Number: 37268 Gerrit-PatchSet: 1 Gerrit-Owner: Regan Chang <regan.chang(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newchange

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coreboot-gerrit November 2019