Change in ...coreboot[master]: mb/*/romstage: Drop defines already set by raminit code
by Patrick Rudolph (Code Review)
Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32070
Change subject: mb/*/romstage: Drop defines already set by raminit code
......................................................................
mb/*/romstage: Drop defines already set by raminit code
Drop defines that are set by raminit code.
Change-Id: Ica844a70b50486b4db3744cb123b3e4b8d5bedb0
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/mainboard/asrock/h81m-hds/romstage.c
M src/mainboard/google/beltino/romstage.c
M src/mainboard/google/butterfly/romstage.c
M src/mainboard/google/link/romstage.c
M src/mainboard/google/parrot/romstage.c
M src/mainboard/google/slippy/variants/falco/romstage.c
M src/mainboard/google/slippy/variants/leon/romstage.c
M src/mainboard/google/slippy/variants/peppy/romstage.c
M src/mainboard/google/slippy/variants/wolf/romstage.c
M src/mainboard/google/stout/romstage.c
M src/mainboard/intel/dcp847ske/romstage.c
M src/mainboard/intel/emeraldlake2/romstage.c
M src/mainboard/kontron/ktqm77/romstage.c
M src/mainboard/lenovo/x220/romstage.c
M src/mainboard/roda/rv11/variants/rv11/romstage.c
M src/mainboard/roda/rv11/variants/rw11/romstage.c
M src/mainboard/samsung/lumpy/romstage.c
M src/mainboard/samsung/stumpy/romstage.c
M src/mainboard/supermicro/x10slm-f/romstage.c
19 files changed, 0 insertions(+), 265 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/32070/1
diff --git a/src/mainboard/asrock/h81m-hds/romstage.c b/src/mainboard/asrock/h81m-hds/romstage.c
index a917722..68ed658 100644
--- a/src/mainboard/asrock/h81m-hds/romstage.c
+++ b/src/mainboard/asrock/h81m-hds/romstage.c
@@ -74,20 +74,6 @@
{
struct pei_data pei_data = {
.pei_version = PEI_VERSION,
- .mchbar = (uintptr_t)DEFAULT_MCHBAR,
- .dmibar = (uintptr_t)DEFAULT_DMIBAR,
- .epbar = DEFAULT_EPBAR,
- .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
- .wdbbar = 0x4000000,
- .wdbsize = 0x1000,
- .hpet_address = HPET_ADDR,
- .rcba = (uintptr_t)DEFAULT_RCBA,
- .pmbase = DEFAULT_PMBASE,
- .gpiobase = DEFAULT_GPIOBASE,
- .temp_mmio_base = 0xfed08000,
- .system_type = 1, /* desktop/server */
- .tseg_size = CONFIG_SMM_TSEG_SIZE,
.spd_addresses = { 0xa0, 0x00, 0xa4, 0x00 },
.ec_present = 0,
.dimm_channel0_disabled = 2, /* Disable DIMM 1 on channel 0. */
diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c
index 70a8c19..6417f0d 100644
--- a/src/mainboard/google/beltino/romstage.c
+++ b/src/mainboard/google/beltino/romstage.c
@@ -71,20 +71,6 @@
{
struct pei_data pei_data = {
.pei_version = PEI_VERSION,
- .mchbar = (uintptr_t)DEFAULT_MCHBAR,
- .dmibar = (uintptr_t)DEFAULT_DMIBAR,
- .epbar = DEFAULT_EPBAR,
- .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
- .wdbbar = 0x4000000,
- .wdbsize = 0x1000,
- .hpet_address = HPET_ADDR,
- .rcba = (uintptr_t)DEFAULT_RCBA,
- .pmbase = DEFAULT_PMBASE,
- .gpiobase = DEFAULT_GPIOBASE,
- .temp_mmio_base = 0xfed08000,
- .system_type = 5, /* ULT */
- .tseg_size = CONFIG_SMM_TSEG_SIZE,
.spd_addresses = { 0xa0, 0x00, 0xa4, 0x00 },
.ec_present = 0,
// 0 = leave channel enabled
diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c
index d34b1e4..cbd9f3d 100644
--- a/src/mainboard/google/butterfly/romstage.c
+++ b/src/mainboard/google/butterfly/romstage.c
@@ -132,20 +132,6 @@
{
struct pei_data pei_data_template = {
.pei_version = PEI_VERSION,
- .mchbar = (uintptr_t)DEFAULT_MCHBAR,
- .dmibar = (uintptr_t)DEFAULT_DMIBAR,
- .epbar = DEFAULT_EPBAR,
- .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
- .wdbbar = 0x4000000,
- .wdbsize = 0x1000,
- .hpet_address = CONFIG_HPET_ADDRESS,
- .rcba = (uintptr_t)DEFAULT_RCBABASE,
- .pmbase = DEFAULT_PMBASE,
- .gpiobase = DEFAULT_GPIOBASE,
- .thermalbase = 0xfed08000,
- .system_type = 0, // 0 Mobile, 1 Desktop/Server
- .tseg_size = CONFIG_SMM_TSEG_SIZE,
.spd_addresses = { 0xA0, 0x00,0xA4,0x00 },
.ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
.ec_present = 1,
diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c
index 66a503d0..6617dc4 100644
--- a/src/mainboard/google/link/romstage.c
+++ b/src/mainboard/google/link/romstage.c
@@ -127,20 +127,6 @@
{
struct pei_data pei_data_template = {
.pei_version = PEI_VERSION,
- .mchbar = (uintptr_t)DEFAULT_MCHBAR,
- .dmibar = (uintptr_t)DEFAULT_DMIBAR,
- .epbar = DEFAULT_EPBAR,
- .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
- .wdbbar = 0x4000000,
- .wdbsize = 0x1000,
- .hpet_address = CONFIG_HPET_ADDRESS,
- .rcba = (uintptr_t)DEFAULT_RCBABASE,
- .pmbase = DEFAULT_PMBASE,
- .gpiobase = DEFAULT_GPIOBASE,
- .thermalbase = 0xfed08000,
- .system_type = 0, // 0 Mobile, 1 Desktop/Server
- .tseg_size = CONFIG_SMM_TSEG_SIZE,
.ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
.ec_present = 1,
.ddr3lv_support = 1,
diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c
index 76a4b4b..d76d814 100644
--- a/src/mainboard/google/parrot/romstage.c
+++ b/src/mainboard/google/parrot/romstage.c
@@ -101,20 +101,6 @@
{
struct pei_data pei_data_template = {
.pei_version = PEI_VERSION,
- .mchbar = (uintptr_t)DEFAULT_MCHBAR,
- .dmibar = (uintptr_t)DEFAULT_DMIBAR,
- .epbar = DEFAULT_EPBAR,
- .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
- .wdbbar = 0x4000000,
- .wdbsize = 0x1000,
- .hpet_address = CONFIG_HPET_ADDRESS,
- .rcba = (uintptr_t)DEFAULT_RCBABASE,
- .pmbase = DEFAULT_PMBASE,
- .gpiobase = DEFAULT_GPIOBASE,
- .thermalbase = 0xfed08000,
- .system_type = 0, // 0 Mobile, 1 Desktop/Server
- .tseg_size = CONFIG_SMM_TSEG_SIZE,
.spd_addresses = { 0xA0, 0x00,0xA4,0x00 },
.ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
.ec_present = 1,
diff --git a/src/mainboard/google/slippy/variants/falco/romstage.c b/src/mainboard/google/slippy/variants/falco/romstage.c
index 25f8d27..2244119 100644
--- a/src/mainboard/google/slippy/variants/falco/romstage.c
+++ b/src/mainboard/google/slippy/variants/falco/romstage.c
@@ -109,20 +109,6 @@
{
struct pei_data pei_data = {
.pei_version = PEI_VERSION,
- .mchbar = (uintptr_t)DEFAULT_MCHBAR,
- .dmibar = (uintptr_t)DEFAULT_DMIBAR,
- .epbar = DEFAULT_EPBAR,
- .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
- .wdbbar = 0x4000000,
- .wdbsize = 0x1000,
- .hpet_address = HPET_ADDR,
- .rcba = (uintptr_t)DEFAULT_RCBA,
- .pmbase = DEFAULT_PMBASE,
- .gpiobase = DEFAULT_GPIOBASE,
- .temp_mmio_base = 0xfed08000,
- .system_type = 5, /* ULT */
- .tseg_size = CONFIG_SMM_TSEG_SIZE,
.spd_addresses = { 0xff, 0x00, 0xff, 0x00 },
.ec_present = 1,
// 0 = leave channel enabled
diff --git a/src/mainboard/google/slippy/variants/leon/romstage.c b/src/mainboard/google/slippy/variants/leon/romstage.c
index b95c6e1..35345d0 100644
--- a/src/mainboard/google/slippy/variants/leon/romstage.c
+++ b/src/mainboard/google/slippy/variants/leon/romstage.c
@@ -106,20 +106,6 @@
{
struct pei_data pei_data = {
.pei_version = PEI_VERSION,
- .mchbar = (uintptr_t)DEFAULT_MCHBAR,
- .dmibar = (uintptr_t)DEFAULT_DMIBAR,
- .epbar = DEFAULT_EPBAR,
- .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
- .wdbbar = 0x4000000,
- .wdbsize = 0x1000,
- .hpet_address = HPET_ADDR,
- .rcba = (uintptr_t)DEFAULT_RCBA,
- .pmbase = DEFAULT_PMBASE,
- .gpiobase = DEFAULT_GPIOBASE,
- .temp_mmio_base = 0xfed08000,
- .system_type = 5, /* ULT */
- .tseg_size = CONFIG_SMM_TSEG_SIZE,
.spd_addresses = { 0xff, 0x00, 0xff, 0x00 },
.ec_present = 1,
// 0 = leave channel enabled
diff --git a/src/mainboard/google/slippy/variants/peppy/romstage.c b/src/mainboard/google/slippy/variants/peppy/romstage.c
index e47edc7..a5de6c0 100644
--- a/src/mainboard/google/slippy/variants/peppy/romstage.c
+++ b/src/mainboard/google/slippy/variants/peppy/romstage.c
@@ -124,20 +124,6 @@
{
struct pei_data pei_data = {
.pei_version = PEI_VERSION,
- .mchbar = (uintptr_t)DEFAULT_MCHBAR,
- .dmibar = (uintptr_t)DEFAULT_DMIBAR,
- .epbar = DEFAULT_EPBAR,
- .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
- .wdbbar = 0x4000000,
- .wdbsize = 0x1000,
- .hpet_address = HPET_ADDR,
- .rcba = (uintptr_t)DEFAULT_RCBA,
- .pmbase = DEFAULT_PMBASE,
- .gpiobase = DEFAULT_GPIOBASE,
- .temp_mmio_base = 0xfed08000,
- .system_type = 5, /* ULT */
- .tseg_size = CONFIG_SMM_TSEG_SIZE,
.spd_addresses = { 0xff, 0x00, 0xff, 0x00 },
.ec_present = 1,
// 0 = leave channel enabled
diff --git a/src/mainboard/google/slippy/variants/wolf/romstage.c b/src/mainboard/google/slippy/variants/wolf/romstage.c
index 3125efe..5a8c972 100644
--- a/src/mainboard/google/slippy/variants/wolf/romstage.c
+++ b/src/mainboard/google/slippy/variants/wolf/romstage.c
@@ -111,20 +111,7 @@
{
struct pei_data pei_data = {
.pei_version = PEI_VERSION,
- .mchbar = (uintptr_t)DEFAULT_MCHBAR,
- .dmibar = (uintptr_t)DEFAULT_DMIBAR,
- .epbar = DEFAULT_EPBAR,
- .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
- .wdbbar = 0x4000000,
- .wdbsize = 0x1000,
- .hpet_address = HPET_ADDR,
- .rcba = (uintptr_t)DEFAULT_RCBA,
- .pmbase = DEFAULT_PMBASE,
- .gpiobase = DEFAULT_GPIOBASE,
- .temp_mmio_base = 0xfed08000,
.system_type = 5, /* ULT */
- .tseg_size = CONFIG_SMM_TSEG_SIZE,
.spd_addresses = { 0xff, 0x00, 0xff, 0x00 },
.ec_present = 1,
// 0 = leave channel enabled
diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c
index 7539dd7..6e32145 100644
--- a/src/mainboard/google/stout/romstage.c
+++ b/src/mainboard/google/stout/romstage.c
@@ -137,20 +137,6 @@
{
struct pei_data pei_data_template = {
.pei_version = PEI_VERSION,
- .mchbar = (uintptr_t)DEFAULT_MCHBAR,
- .dmibar = (uintptr_t)DEFAULT_DMIBAR,
- .epbar = DEFAULT_EPBAR,
- .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
- .wdbbar = 0x4000000,
- .wdbsize = 0x1000,
- .hpet_address = CONFIG_HPET_ADDRESS,
- .rcba = (uintptr_t)DEFAULT_RCBABASE,
- .pmbase = DEFAULT_PMBASE,
- .gpiobase = DEFAULT_GPIOBASE,
- .thermalbase = 0xfed08000,
- .system_type = 0, // 0 Mobile, 1 Desktop/Server
- .tseg_size = CONFIG_SMM_TSEG_SIZE,
.spd_addresses = { 0xA0, 0x00,0xA4,0x00 },
.ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
.ec_present = 1,
diff --git a/src/mainboard/intel/dcp847ske/romstage.c b/src/mainboard/intel/dcp847ske/romstage.c
index 24ec912..2043cf6 100644
--- a/src/mainboard/intel/dcp847ske/romstage.c
+++ b/src/mainboard/intel/dcp847ske/romstage.c
@@ -29,20 +29,6 @@
{
struct pei_data pei_data_template = {
.pei_version = PEI_VERSION,
- .mchbar = (uintptr_t)DEFAULT_MCHBAR,
- .dmibar = (uintptr_t)DEFAULT_DMIBAR,
- .epbar = DEFAULT_EPBAR,
- .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
- .wdbbar = 0x4000000,
- .wdbsize = 0x1000,
- .hpet_address = CONFIG_HPET_ADDRESS,
- .rcba = (uintptr_t)DEFAULT_RCBABASE,
- .pmbase = DEFAULT_PMBASE,
- .gpiobase = DEFAULT_GPIOBASE,
- .thermalbase = 0xfed08000,
- .system_type = 0, // 0 Mobile, 1 Desktop/Server
- .tseg_size = CONFIG_SMM_TSEG_SIZE,
.spd_addresses = { 0xa0, 0x00, 0xa2, 0x00 },
.ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
.ec_present = 0,
diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c
index 9a9fc24..8cd7ec2 100644
--- a/src/mainboard/intel/emeraldlake2/romstage.c
+++ b/src/mainboard/intel/emeraldlake2/romstage.c
@@ -94,20 +94,6 @@
{
struct pei_data pei_data_template = {
.pei_version = PEI_VERSION,
- .mchbar = (uintptr_t)DEFAULT_MCHBAR,
- .dmibar = (uintptr_t)DEFAULT_DMIBAR,
- .epbar = DEFAULT_EPBAR,
- .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
- .wdbbar = 0x4000000,
- .wdbsize = 0x1000,
- .hpet_address = CONFIG_HPET_ADDRESS,
- .rcba = (uintptr_t)DEFAULT_RCBABASE,
- .pmbase = DEFAULT_PMBASE,
- .gpiobase = DEFAULT_GPIOBASE,
- .thermalbase = 0xfed08000,
- .system_type = 0, // 0 Mobile, 1 Desktop/Server
- .tseg_size = CONFIG_SMM_TSEG_SIZE,
.spd_addresses = { 0xa0, 0x00, 0xa4, 0x00 },
.ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
.ec_present = 0,
diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c
index f778f96..e0f8954 100644
--- a/src/mainboard/kontron/ktqm77/romstage.c
+++ b/src/mainboard/kontron/ktqm77/romstage.c
@@ -80,20 +80,6 @@
{
struct pei_data pei_data_template = {
.pei_version = PEI_VERSION,
- .mchbar = (uintptr_t)DEFAULT_MCHBAR,
- .dmibar = (uintptr_t)DEFAULT_DMIBAR,
- .epbar = DEFAULT_EPBAR,
- .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
- .wdbbar = 0x4000000,
- .wdbsize = 0x1000,
- .hpet_address = CONFIG_HPET_ADDRESS,
- .rcba = (uintptr_t)DEFAULT_RCBABASE,
- .pmbase = DEFAULT_PMBASE,
- .gpiobase = DEFAULT_GPIOBASE,
- .thermalbase = 0xfed08000,
- .system_type = 0, /* 0 Mobile, 1 Desktop/Server */
- .tseg_size = CONFIG_SMM_TSEG_SIZE,
.spd_addresses = { 0xA0, 0x00,0xA4,0x00 },
.ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
.ec_present = 1,
diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c
index a5b0c81..d398d81 100644
--- a/src/mainboard/lenovo/x220/romstage.c
+++ b/src/mainboard/lenovo/x220/romstage.c
@@ -50,20 +50,6 @@
{
struct pei_data pei_data_template = {
.pei_version = PEI_VERSION,
- .mchbar = (uintptr_t)DEFAULT_MCHBAR,
- .dmibar = (uintptr_t)DEFAULT_DMIBAR,
- .epbar = DEFAULT_EPBAR,
- .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
- .wdbbar = 0x4000000,
- .wdbsize = 0x1000,
- .hpet_address = CONFIG_HPET_ADDRESS,
- .rcba = (uintptr_t)DEFAULT_RCBABASE,
- .pmbase = DEFAULT_PMBASE,
- .gpiobase = DEFAULT_GPIOBASE,
- .thermalbase = 0xfed08000,
- .system_type = 0, // 0 Mobile, 1 Desktop/Server
- .tseg_size = CONFIG_SMM_TSEG_SIZE,
.spd_addresses = { 0xa0, 0x00,0xa2,0x00 },
.ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
.ec_present = 1,
diff --git a/src/mainboard/roda/rv11/variants/rv11/romstage.c b/src/mainboard/roda/rv11/variants/rv11/romstage.c
index 685e942..df679f1 100644
--- a/src/mainboard/roda/rv11/variants/rv11/romstage.c
+++ b/src/mainboard/roda/rv11/variants/rv11/romstage.c
@@ -37,20 +37,6 @@
{
const struct pei_data pei_data_template = {
.pei_version = PEI_VERSION,
- .mchbar = (uintptr_t)DEFAULT_MCHBAR,
- .dmibar = (uintptr_t)DEFAULT_DMIBAR,
- .epbar = DEFAULT_EPBAR,
- .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
- .wdbbar = 0x4000000,
- .wdbsize = 0x1000,
- .hpet_address = CONFIG_HPET_ADDRESS,
- .rcba = (uintptr_t)DEFAULT_RCBABASE,
- .pmbase = DEFAULT_PMBASE,
- .gpiobase = DEFAULT_GPIOBASE,
- .thermalbase = 0xfed08000,
- .system_type = 0, // 0 Mobile, 1 Desktop/Server
- .tseg_size = CONFIG_SMM_TSEG_SIZE,
.spd_addresses = { 0xA0, 0x00, 0xA4, 0x00 },
.ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
.ec_present = 1,
diff --git a/src/mainboard/roda/rv11/variants/rw11/romstage.c b/src/mainboard/roda/rv11/variants/rw11/romstage.c
index 97d9d2b..56ac32c 100644
--- a/src/mainboard/roda/rv11/variants/rw11/romstage.c
+++ b/src/mainboard/roda/rv11/variants/rw11/romstage.c
@@ -66,20 +66,6 @@
{
const struct pei_data pei_data_template = {
.pei_version = PEI_VERSION,
- .mchbar = (uintptr_t)DEFAULT_MCHBAR,
- .dmibar = (uintptr_t)DEFAULT_DMIBAR,
- .epbar = DEFAULT_EPBAR,
- .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
- .wdbbar = 0x4000000,
- .wdbsize = 0x1000,
- .hpet_address = CONFIG_HPET_ADDRESS,
- .rcba = (uintptr_t)DEFAULT_RCBABASE,
- .pmbase = DEFAULT_PMBASE,
- .gpiobase = DEFAULT_GPIOBASE,
- .thermalbase = 0xfed08000,
- .system_type = 0, // 0 Mobile, 1 Desktop/Server
- .tseg_size = CONFIG_SMM_TSEG_SIZE,
.spd_addresses = { 0xA0, 0xA2, 0xA4, 0xA6 },
.ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
.ec_present = 1,
diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c
index 1080689..29fe08b 100644
--- a/src/mainboard/samsung/lumpy/romstage.c
+++ b/src/mainboard/samsung/lumpy/romstage.c
@@ -156,20 +156,6 @@
{
struct pei_data pei_data_template = {
.pei_version = PEI_VERSION,
- .mchbar = (uintptr_t)DEFAULT_MCHBAR,
- .dmibar = (uintptr_t)DEFAULT_DMIBAR,
- .epbar = DEFAULT_EPBAR,
- .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
- .wdbbar = 0x4000000,
- .wdbsize = 0x1000,
- .hpet_address = CONFIG_HPET_ADDRESS,
- .rcba = (uintptr_t)DEFAULT_RCBABASE,
- .pmbase = DEFAULT_PMBASE,
- .gpiobase = DEFAULT_GPIOBASE,
- .thermalbase = 0xfed08000,
- .system_type = 0, // 0 Mobile, 1 Desktop/Server
- .tseg_size = CONFIG_SMM_TSEG_SIZE,
.spd_addresses = { 0xa0, 0x00,0x00,0x00 },
.ts_addresses = { 0x30, 0x00, 0x00, 0x00 },
.ec_present = 1,
diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c
index a8e28d6..510efbe 100644
--- a/src/mainboard/samsung/stumpy/romstage.c
+++ b/src/mainboard/samsung/stumpy/romstage.c
@@ -144,20 +144,6 @@
{
struct pei_data pei_data_template = {
.pei_version = PEI_VERSION,
- .mchbar = (uintptr_t)DEFAULT_MCHBAR,
- .dmibar = (uintptr_t)DEFAULT_DMIBAR,
- .epbar = DEFAULT_EPBAR,
- .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
- .wdbbar = 0x4000000,
- .wdbsize = 0x1000,
- .hpet_address = CONFIG_HPET_ADDRESS,
- .rcba = (uintptr_t)DEFAULT_RCBABASE,
- .pmbase = DEFAULT_PMBASE,
- .gpiobase = DEFAULT_GPIOBASE,
- .thermalbase = 0xfed08000,
- .system_type = 0, // 0 Mobile, 1 Desktop/Server
- .tseg_size = CONFIG_SMM_TSEG_SIZE,
.spd_addresses = { 0xa0, 0x00,0xa4,0x00 },
.ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
.ec_present = 0,
diff --git a/src/mainboard/supermicro/x10slm-f/romstage.c b/src/mainboard/supermicro/x10slm-f/romstage.c
index 84ad047..702e8bb 100644
--- a/src/mainboard/supermicro/x10slm-f/romstage.c
+++ b/src/mainboard/supermicro/x10slm-f/romstage.c
@@ -66,20 +66,6 @@
{
struct pei_data pei_data = {
.pei_version = PEI_VERSION,
- .mchbar = (uintptr_t)DEFAULT_MCHBAR,
- .dmibar = (uintptr_t)DEFAULT_DMIBAR,
- .epbar = DEFAULT_EPBAR,
- .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
- .wdbbar = 0x4000000,
- .wdbsize = 0x1000,
- .hpet_address = HPET_ADDR,
- .rcba = (uintptr_t)DEFAULT_RCBA,
- .pmbase = DEFAULT_PMBASE,
- .gpiobase = DEFAULT_GPIOBASE,
- .temp_mmio_base = 0xfed08000,
- .system_type = 1, /* desktop/server */
- .tseg_size = CONFIG_SMM_TSEG_SIZE,
.spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 },
.ec_present = 0,
.ddr_refresh_2x = 1,
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ica844a70b50486b4db3744cb123b3e4b8d5bedb0
Gerrit-Change-Number: 32070
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Gerrit-MessageType: newchange
1 day, 3 hours
- 3
- 12
Change in coreboot[master]: [TEST] mb/supermicro/x11-lga1151-series: rewrite gpio.h using intelp2m
by Maxim Polyakov (Code Review)
Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35679 )
Change subject: [TEST] mb/supermicro/x11-lga1151-series: rewrite gpio.h using intelp2m
......................................................................
[TEST] mb/supermicro/x11-lga1151-series: rewrite gpio.h using intelp2m
gpio.h was generated using the Intel Pad 2 Macro utility (intelp2m) [1]
Please review and test coreboot image with this patch
[1] https://review.coreboot.org/c/coreboot/+/35643
These changes are not tested on real hardware.
Change-Id: Idad7536854d4b1ae7dcf7934e81de438478fe059
Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com>
---
M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h
1 file changed, 213 insertions(+), 213 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/35679/1
diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h
index a5eed6b..5320298 100644
--- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h
+++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h
@@ -21,210 +21,210 @@
#ifndef __ACPI__
static const struct pad_config gpio_table[] = {
-/* RCIN# */ _PAD_CFG_STRUCT(GPP_A0, 0x44000702, 0x00000000),
-/* LAD0 */ _PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x00000000),
-/* LAD1 */ _PAD_CFG_STRUCT(GPP_A2, 0x44000700, 0x00000000),
-/* LAD2 */ _PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x00000000),
-/* LAD3 */ _PAD_CFG_STRUCT(GPP_A4, 0x44000700, 0x00000000),
-/* LFRAME# */ _PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x00000000),
-/* SERIRQ */ _PAD_CFG_STRUCT(GPP_A6, 0x44000700, 0x00000000),
-/* PIRQA# */ _PAD_CFG_STRUCT(GPP_A7, 0x44000702, 0x00000000),
-/* CLKRUN# */ _PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x00000000),
-/* CLKOUT_LPC0 */ _PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x00000000),
-/* CLKOUT_LPC1 */ _PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x00000000),
-/* PME# */ _PAD_CFG_STRUCT(GPP_A11, 0x44000702, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_A12, 0x80080201, 0x00000000),
-/* SUSWARN# */ _PAD_CFG_STRUCT(GPP_A13, 0x44000700, 0x00000000),
-/* SUS_STAT# */ _PAD_CFG_STRUCT(GPP_A14, 0x44000700, 0x00000000),
-/* SUS_ACK# */ _PAD_CFG_STRUCT(GPP_A15, 0x44000702, 0x00000000),
-/* CLKOUT_48 */ _PAD_CFG_STRUCT(GPP_A16, 0x44000700, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_A17, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_A18, 0x84000100, 0x00000000),
-/* RESERVED */ //_PAD_CFG_STRUCT(GPP_A19, 0xffffffff, 0xffffff00),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_A20, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_A21, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_A22, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_A23, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_B0, 0x44000201, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_B1, 0x44000201, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_B2, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_B3, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_B4, 0x44000301, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_B5, 0x44000301, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_B6, 0x84000301, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_B7, 0x44000301, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_B8, 0x44000301, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_B9, 0x44000301, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_B10, 0x44000301, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_B11, 0x44000200, 0x00000000),
-/* SLP_S0# */ _PAD_CFG_STRUCT(GPP_B12, 0x44000700, 0x00000000),
-/* PLTRST# */ _PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x00000000),
-/* SPKR */ _PAD_CFG_STRUCT(GPP_B14, 0x84000700, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_B15, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_B16, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_B17, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_B18, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_B19, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_B20, 0x84000201, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_B21, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_B22, 0x44000300, 0x00000000),
-/* PCHHOT# */ _PAD_CFG_STRUCT(GPP_B23, 0x40000b00, 0x00000000),
-/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C0, 0xffffffff, 0xffffff00),
-/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C1, 0xffffffff, 0xffffff00),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_C2, 0x44000300, 0x00000000),
-/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C3, 0xffffffff, 0xffffff00),
-/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C4, 0xffffffff, 0xffffff00),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_C5, 0x44000201, 0x00000000),
-/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C6, 0xffffffff, 0xffffff00),
-/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C7, 0xffffffff, 0xffffff00),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_C8, 0x84000102, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_C9, 0x84000100, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_C10, 0x84000102, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_C11, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_C12, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_C13, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_C14, 0x84000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_C15, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_C16, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_C17, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_C18, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_C19, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_C20, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_C21, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_C22, 0x42040102, 0x00003000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_C23, 0x84000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D0, 0x84000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D1, 0x44000201, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D2, 0x42020102, 0x00003000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D3, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D4, 0x84000200, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D5, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D6, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D7, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D8, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D9, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D10, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D11, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D12, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D13, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D14, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D15, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D16, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D17, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D18, 0x84000201, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D19, 0x84000201, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D20, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D21, 0x44000200, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D22, 0x04000102, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_D23, 0x44000300, 0x00000000),
-/* SATAXPCIE0 */ _PAD_CFG_STRUCT(GPP_E0, 0x44000502, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_E1, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_E2, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_E3, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_E4, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_E5, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_E6, 0x82020102, 0x00003000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_E7, 0x44000300, 0x00000000),
-/* SATA_LED# */ _PAD_CFG_STRUCT(GPP_E8, 0x44000700, 0x00000000),
-/* USB_OC0# */ _PAD_CFG_STRUCT(GPP_E9, 0x44000702, 0x00000000),
-/* USB_OC1# */ _PAD_CFG_STRUCT(GPP_E10, 0x44000702, 0x00000000),
-/* USB_OC2# */ _PAD_CFG_STRUCT(GPP_E11, 0x44000702, 0x00000000),
-/* USB_OC3# */ _PAD_CFG_STRUCT(GPP_E12, 0x44000702, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_F0, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_F1, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_F2, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_F3, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_F4, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_F5, 0x80100102, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_F6, 0x84000201, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_F7, 0x84000201, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_F8, 0x84000201, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_F9, 0x84000102, 0x00000000),
-/* SATA_SCLOCK */ _PAD_CFG_STRUCT(GPP_F10, 0x44000700, 0x00000000),
-/* SATA_SLOAD */ _PAD_CFG_STRUCT(GPP_F11, 0x44000700, 0x00000000),
-/* SATA_SDATAOUT1 */ _PAD_CFG_STRUCT(GPP_F12, 0x44000700, 0x00000000),
-/* SATA_SDATAOUT2 */ _PAD_CFG_STRUCT(GPP_F13, 0x44000700, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_F14, 0x44000300, 0x00000000),
-/* USB_OC4# */ _PAD_CFG_STRUCT(GPP_F15, 0x44000702, 0x00000000),
-/* USB_OC5# */ _PAD_CFG_STRUCT(GPP_F16, 0x44000702, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_F17, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_F18, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_F19, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_F20, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_F21, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_F22, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_F23, 0x04000200, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_G0, 0x44000100, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_G1, 0x44000100, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_G2, 0x44000102, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_G3, 0x44000102, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_G4, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_G5, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_G6, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_G7, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_G8, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_G9, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_G10, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_G11, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_G12, 0x84000100, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_G13, 0x84000100, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_G14, 0x84000102, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_G15, 0x84000100, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_G16, 0x84000100, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_G17, 0x44000300, 0x00000000),
-/* NMI# */ _PAD_CFG_STRUCT(GPP_G18, 0x44000700, 0x00000000),
-/* SMI# */ _PAD_CFG_STRUCT(GPP_G19, 0x44000700, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_G20, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_G21, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_G22, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_G23, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_H0, 0x44000201, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_H1, 0x84000103, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_H2, 0x44000201, 0x00000000),
-/* SRCCLKREQ9# */ _PAD_CFG_STRUCT(GPP_H3, 0x44000602, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_H4, 0x84000103, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_H5, 0x84000201, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_H6, 0x84000201, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_H7, 0x84000201, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_H8, 0x84000201, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_H9, 0x84000201, 0x00000000),
-/* SML2CLK */ _PAD_CFG_STRUCT(GPP_H10, 0x44000702, 0x00000000),
-/* SML2DATA */ _PAD_CFG_STRUCT(GPP_H11, 0x44000702, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_H12, 0x44000300, 0x00000000),
-/* SML3CLK */ _PAD_CFG_STRUCT(GPP_H13, 0x44000702, 0x00000000),
-/* SML3DATA */ _PAD_CFG_STRUCT(GPP_H14, 0x44000702, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_H15, 0x44000300, 0x00000000),
-/* SML4CLK */ _PAD_CFG_STRUCT(GPP_H16, 0x44000702, 0x00000000),
-/* SML4DATA */ _PAD_CFG_STRUCT(GPP_H17, 0x44000702, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_H18, 0x44000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_H19, 0x84000201, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_H20, 0x84000201, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_H21, 0x84000201, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_H22, 0x84000201, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_H23, 0x84000201, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPD0, 0x04000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPD1, 0x04000300, 0x00000000),
-/* LAN_WAKE# */ _PAD_CFG_STRUCT(GPD2, 0x04000702, 0x00000000),
-/* PWRBTN# */ _PAD_CFG_STRUCT(GPD3, 0x04000702, 0x00000000),
-/* SLP_S3# */ _PAD_CFG_STRUCT(GPD4, 0x04000700, 0x00000000),
-/* SLP_S4# */ _PAD_CFG_STRUCT(GPD5, 0x04000700, 0x00000000),
-/* SLP_A# */ _PAD_CFG_STRUCT(GPD6, 0x04000700, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPD7, 0x04000301, 0x00000000),
-/* SUSCLK */ _PAD_CFG_STRUCT(GPD8, 0x04000700, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPD9, 0x04000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPD10, 0x04000300, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPD11, 0x04000300, 0x00000000),
-/* DDPB_HPD0 */ _PAD_CFG_STRUCT(GPP_I0, 0x44000700, 0x00000000),
-/* DDPC_HPD1 */ _PAD_CFG_STRUCT(GPP_I1, 0x44000700, 0x00000000),
-/* DDPD_HPD2 */ _PAD_CFG_STRUCT(GPP_I2, 0x44000700, 0x00000000),
-/* DDPE_HPD3 */ _PAD_CFG_STRUCT(GPP_I3, 0x84000700, 0x00000000),
-/* GPIO */ _PAD_CFG_STRUCT(GPP_I4, 0x44000300, 0x00000000),
-/* DDPB_CTRLCLK */ _PAD_CFG_STRUCT(GPP_I5, 0x44000700, 0x00000000),
-/* DDPB_CTRLDATA */ _PAD_CFG_STRUCT(GPP_I6, 0x44000700, 0x00000000),
-/* DDPC_CTRLCLK */ _PAD_CFG_STRUCT(GPP_I7, 0x44000700, 0x00000000),
-/* DDPC_CTRLDATA */ _PAD_CFG_STRUCT(GPP_I8, 0x44000700, 0x00000000),
-/* DDPD_CTRLCLK */ _PAD_CFG_STRUCT(GPP_I9, 0x44000700, 0x00000000),
-/* DDPD_CTRLDATA */ _PAD_CFG_STRUCT(GPP_I10, 0x44000700, 0x00000000),
+ PAD_CFG_NF_BUF_TRIG(GPP_A0, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* RCIN# */
+ PAD_CFG_NF_BUF_TRIG(GPP_A1, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* LAD0 */
+ PAD_CFG_NF_BUF_TRIG(GPP_A2, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* LAD1 */
+ PAD_CFG_NF_BUF_TRIG(GPP_A3, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* LAD2 */
+ PAD_CFG_NF_BUF_TRIG(GPP_A4, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* LAD3 */
+ PAD_CFG_NF_BUF_TRIG(GPP_A5, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* LFRAME# */
+ PAD_CFG_NF_BUF_TRIG(GPP_A6, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* SERIRQ */
+ PAD_CFG_NF_BUF_TRIG(GPP_A7, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* PIRQA# */
+ PAD_CFG_NF_BUF_TRIG(GPP_A8, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* CLKRUN# */
+ PAD_CFG_NF_BUF_TRIG(GPP_A9, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* CLKOUT_LPC0 */
+ PAD_CFG_NF_BUF_TRIG(GPP_A10, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* CLKOUT_LPC1 */
+ PAD_CFG_NF_BUF_TRIG(GPP_A11, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* PME# */
+ PAD_CFG_GPO(GPP_A12, 1, PLTRST), /* GPIO */
+ PAD_CFG_NF_BUF_TRIG(GPP_A13, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* SUSWARN# */
+ PAD_CFG_NF_BUF_TRIG(GPP_A14, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* SUS_STAT# */
+ PAD_CFG_NF_BUF_TRIG(GPP_A15, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* SUS_ACK# */
+ PAD_CFG_NF_BUF_TRIG(GPP_A16, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* CLKOUT_48 */
+ PAD_NC(GPP_A17, NONE), /* GPIO */
+ PAD_CFG_GPI_INT(GPP_A18, NONE, PLTRST, OFF), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_A19, 0xffffffff, 0xffffff00) /* RESERVED */
+ PAD_NC(GPP_A20, NONE), /* GPIO */
+ PAD_NC(GPP_A21, NONE), /* GPIO */
+ PAD_NC(GPP_A22, NONE), /* GPIO */
+ PAD_NC(GPP_A23, NONE), /* GPIO */
+ PAD_CFG_GPO(GPP_B0, 1, DEEP), /* GPIO */
+ PAD_CFG_GPO(GPP_B1, 1, DEEP), /* GPIO */
+ PAD_NC(GPP_B2, NONE), /* GPIO */
+ PAD_NC(GPP_B3, NONE), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_B4, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(NONE)), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_B5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(NONE)), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_B6, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(NONE)), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_B7, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(NONE)), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_B8, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(NONE)), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_B9, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(NONE)), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_B10, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(NONE)), /* GPIO */
+ PAD_CFG_GPO(GPP_B11, 0, DEEP), /* GPIO */
+ PAD_CFG_NF_BUF_TRIG(GPP_B12, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* SLP_S0# */
+ PAD_CFG_NF_BUF_TRIG(GPP_B13, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* PLTRST# */
+ PAD_CFG_NF_BUF_TRIG(GPP_B14, NONE, PLTRST, NF1, TX_RX_DISABLE, OFF), /* SPKR */
+ PAD_NC(GPP_B15, NONE), /* GPIO */
+ PAD_NC(GPP_B16, NONE), /* GPIO */
+ PAD_NC(GPP_B17, NONE), /* GPIO */
+ PAD_NC(GPP_B18, NONE), /* GPIO */
+ PAD_NC(GPP_B19, NONE), /* GPIO */
+ PAD_CFG_GPO(GPP_B20, 1, PLTRST), /* GPIO */
+ PAD_NC(GPP_B21, NONE), /* GPIO */
+ PAD_NC(GPP_B22, NONE), /* GPIO */
+ PAD_CFG_NF_BUF_TRIG(GPP_B23, NONE, DEEP, NF2, TX_RX_DISABLE, LEVEL), /* PCHHOT# */
+ _PAD_CFG_STRUCT(GPP_C0, 0xffffffff, 0xffffff00) /* RESERVED */
+ _PAD_CFG_STRUCT(GPP_C1, 0xffffffff, 0xffffff00) /* RESERVED */
+ PAD_NC(GPP_C2, NONE), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_C3, 0xffffffff, 0xffffff00) /* RESERVED */
+ _PAD_CFG_STRUCT(GPP_C4, 0xffffffff, 0xffffff00) /* RESERVED */
+ PAD_CFG_GPO(GPP_C5, 1, DEEP), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_C6, 0xffffffff, 0xffffff00) /* RESERVED */
+ _PAD_CFG_STRUCT(GPP_C7, 0xffffffff, 0xffffff00) /* RESERVED */
+ PAD_CFG_GPI_INT(GPP_C8, NONE, PLTRST, OFF), /* GPIO */
+ PAD_CFG_GPI_INT(GPP_C9, NONE, PLTRST, OFF), /* GPIO */
+ PAD_CFG_GPI_INT(GPP_C10, NONE, PLTRST, OFF), /* GPIO */
+ PAD_NC(GPP_C11, NONE), /* GPIO */
+ PAD_NC(GPP_C12, NONE), /* GPIO */
+ PAD_NC(GPP_C13, NONE), /* GPIO */
+ PAD_NC(GPP_C14, NONE), /* GPIO */
+ PAD_NC(GPP_C15, NONE), /* GPIO */
+ PAD_NC(GPP_C16, NONE), /* GPIO */
+ PAD_NC(GPP_C17, NONE), /* GPIO */
+ PAD_NC(GPP_C18, NONE), /* GPIO */
+ PAD_NC(GPP_C19, NONE), /* GPIO */
+ PAD_NC(GPP_C20, NONE), /* GPIO */
+ PAD_NC(GPP_C21, NONE), /* GPIO */
+ PAD_CFG_GPI_ACPI_SMI(GPP_C22, 20K_PU, DEEP, NONE), /* GPIO */
+ PAD_NC(GPP_C23, NONE), /* GPIO */
+ PAD_NC(GPP_D0, NONE), /* GPIO */
+ PAD_CFG_GPO(GPP_D1, 1, DEEP), /* GPIO */
+ PAD_CFG_GPI_NMI(GPP_D2, 20K_PU, DEEP, EDGE_SINGLE, NONE), /* GPIO */
+ PAD_NC(GPP_D3, NONE), /* GPIO */
+ PAD_CFG_GPO(GPP_D4, 0, PLTRST), /* GPIO */
+ PAD_NC(GPP_D5, NONE), /* GPIO */
+ PAD_NC(GPP_D6, NONE), /* GPIO */
+ PAD_NC(GPP_D7, NONE), /* GPIO */
+ PAD_NC(GPP_D8, NONE), /* GPIO */
+ PAD_NC(GPP_D9, NONE), /* GPIO */
+ PAD_NC(GPP_D10, NONE), /* GPIO */
+ PAD_NC(GPP_D11, NONE), /* GPIO */
+ PAD_NC(GPP_D12, NONE), /* GPIO */
+ PAD_NC(GPP_D13, NONE), /* GPIO */
+ PAD_NC(GPP_D14, NONE), /* GPIO */
+ PAD_NC(GPP_D15, NONE), /* GPIO */
+ PAD_NC(GPP_D16, NONE), /* GPIO */
+ PAD_NC(GPP_D17, NONE), /* GPIO */
+ PAD_CFG_GPO(GPP_D18, 1, PLTRST), /* GPIO */
+ PAD_CFG_GPO(GPP_D19, 1, PLTRST), /* GPIO */
+ PAD_NC(GPP_D20, NONE), /* GPIO */
+ PAD_CFG_GPO(GPP_D21, 0, DEEP), /* GPIO */
+ PAD_CFG_GPI_INT(GPP_D22, NONE, PWROK, OFF), /* GPIO */
+ PAD_NC(GPP_D23, NONE), /* GPIO */
+ PAD_CFG_NF_BUF_TRIG(GPP_E0, NONE, DEEP, NF1, TX_DISABLE, OFF), /* SATAXPCIE0 */
+ PAD_NC(GPP_E1, NONE), /* GPIO */
+ PAD_NC(GPP_E2, NONE), /* GPIO */
+ PAD_NC(GPP_E3, NONE), /* GPIO */
+ PAD_NC(GPP_E4, NONE), /* GPIO */
+ PAD_NC(GPP_E5, NONE), /* GPIO */
+ PAD_CFG_GPI_NMI(GPP_E6, 20K_PU, PLTRST, EDGE_SINGLE, NONE), /* GPIO */
+ PAD_NC(GPP_E7, NONE), /* GPIO */
+ PAD_CFG_NF_BUF_TRIG(GPP_E8, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* SATA_LED# */
+ PAD_CFG_NF_BUF_TRIG(GPP_E9, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* USB_OC0# */
+ PAD_CFG_NF_BUF_TRIG(GPP_E10, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* USB_OC1# */
+ PAD_CFG_NF_BUF_TRIG(GPP_E11, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* USB_OC2# */
+ PAD_CFG_NF_BUF_TRIG(GPP_E12, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* USB_OC3# */
+ PAD_NC(GPP_F0, NONE), /* GPIO */
+ PAD_NC(GPP_F1, NONE), /* GPIO */
+ PAD_NC(GPP_F2, NONE), /* GPIO */
+ PAD_NC(GPP_F3, NONE), /* GPIO */
+ PAD_NC(GPP_F4, NONE), /* GPIO */
+ PAD_CFG_GPI_APIC(GPP_F5, NONE, PLTRST), /* GPIO */
+ PAD_CFG_GPO(GPP_F6, 1, PLTRST), /* GPIO */
+ PAD_CFG_GPO(GPP_F7, 1, PLTRST), /* GPIO */
+ PAD_CFG_GPO(GPP_F8, 1, PLTRST), /* GPIO */
+ PAD_CFG_GPI_INT(GPP_F9, NONE, PLTRST, OFF), /* GPIO */
+ PAD_CFG_NF_BUF_TRIG(GPP_F10, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* SATA_SCLOCK */
+ PAD_CFG_NF_BUF_TRIG(GPP_F11, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* SATA_SLOAD */
+ PAD_CFG_NF_BUF_TRIG(GPP_F12, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* SATA_SDATAOUT1 */
+ PAD_CFG_NF_BUF_TRIG(GPP_F13, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* SATA_SDATAOUT2 */
+ PAD_NC(GPP_F14, NONE), /* GPIO */
+ PAD_CFG_NF_BUF_TRIG(GPP_F15, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* USB_OC4# */
+ PAD_CFG_NF_BUF_TRIG(GPP_F16, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* USB_OC5# */
+ PAD_NC(GPP_F17, NONE), /* GPIO */
+ PAD_NC(GPP_F18, NONE), /* GPIO */
+ PAD_NC(GPP_F19, NONE), /* GPIO */
+ PAD_NC(GPP_F20, NONE), /* GPIO */
+ PAD_NC(GPP_F21, NONE), /* GPIO */
+ PAD_NC(GPP_F22, NONE), /* GPIO */
+ PAD_CFG_GPO(GPP_F23, 0, PWROK), /* GPIO */
+ PAD_CFG_GPI_INT(GPP_G0, NONE, DEEP, OFF), /* GPIO */
+ PAD_CFG_GPI_INT(GPP_G1, NONE, DEEP, OFF), /* GPIO */
+ PAD_CFG_GPI_INT(GPP_G2, NONE, DEEP, OFF), /* GPIO */
+ PAD_CFG_GPI_INT(GPP_G3, NONE, DEEP, OFF), /* GPIO */
+ PAD_NC(GPP_G4, NONE), /* GPIO */
+ PAD_NC(GPP_G5, NONE), /* GPIO */
+ PAD_NC(GPP_G6, NONE), /* GPIO */
+ PAD_NC(GPP_G7, NONE), /* GPIO */
+ PAD_NC(GPP_G8, NONE), /* GPIO */
+ PAD_NC(GPP_G9, NONE), /* GPIO */
+ PAD_NC(GPP_G10, NONE), /* GPIO */
+ PAD_NC(GPP_G11, NONE), /* GPIO */
+ PAD_CFG_GPI_INT(GPP_G12, NONE, PLTRST, OFF), /* GPIO */
+ PAD_CFG_GPI_INT(GPP_G13, NONE, PLTRST, OFF), /* GPIO */
+ PAD_CFG_GPI_INT(GPP_G14, NONE, PLTRST, OFF), /* GPIO */
+ PAD_CFG_GPI_INT(GPP_G15, NONE, PLTRST, OFF), /* GPIO */
+ PAD_CFG_GPI_INT(GPP_G16, NONE, PLTRST, OFF), /* GPIO */
+ PAD_NC(GPP_G17, NONE), /* GPIO */
+ PAD_CFG_NF_BUF_TRIG(GPP_G18, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* NMI# */
+ PAD_CFG_NF_BUF_TRIG(GPP_G19, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* SMI# */
+ PAD_NC(GPP_G20, NONE), /* GPIO */
+ PAD_NC(GPP_G21, NONE), /* GPIO */
+ PAD_NC(GPP_G22, NONE), /* GPIO */
+ PAD_NC(GPP_G23, NONE), /* GPIO */
+ PAD_CFG_GPO(GPP_H0, 1, DEEP), /* GPIO */
+ _PAD_CFG_STRUCT(GPP_H1, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_PULL(NONE)), /* GPIO */
+ PAD_CFG_GPO(GPP_H2, 1, DEEP), /* GPIO */
+ PAD_CFG_NF_BUF_TRIG(GPP_H3, NONE, DEEP, NF1, RX_DISABLE, OFF), /* SRCCLKREQ9# */
+ _PAD_CFG_STRUCT(GPP_H4, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_PULL(NONE)), /* GPIO */
+ PAD_CFG_GPO(GPP_H5, 1, PLTRST), /* GPIO */
+ PAD_CFG_GPO(GPP_H6, 1, PLTRST), /* GPIO */
+ PAD_CFG_GPO(GPP_H7, 1, PLTRST), /* GPIO */
+ PAD_CFG_GPO(GPP_H8, 1, PLTRST), /* GPIO */
+ PAD_CFG_GPO(GPP_H9, 1, PLTRST), /* GPIO */
+ PAD_CFG_NF_BUF_TRIG(GPP_H10, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* SML2CLK */
+ PAD_CFG_NF_BUF_TRIG(GPP_H11, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* SML2DATA */
+ PAD_NC(GPP_H12, NONE), /* GPIO */
+ PAD_CFG_NF_BUF_TRIG(GPP_H13, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* SML3CLK */
+ PAD_CFG_NF_BUF_TRIG(GPP_H14, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* SML3DATA */
+ PAD_NC(GPP_H15, NONE), /* GPIO */
+ PAD_CFG_NF_BUF_TRIG(GPP_H16, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* SML4CLK */
+ PAD_CFG_NF_BUF_TRIG(GPP_H17, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* SML4DATA */
+ PAD_NC(GPP_H18, NONE), /* GPIO */
+ PAD_CFG_GPO(GPP_H19, 1, PLTRST), /* GPIO */
+ PAD_CFG_GPO(GPP_H20, 1, PLTRST), /* GPIO */
+ PAD_CFG_GPO(GPP_H21, 1, PLTRST), /* GPIO */
+ PAD_CFG_GPO(GPP_H22, 1, PLTRST), /* GPIO */
+ PAD_CFG_GPO(GPP_H23, 1, PLTRST), /* GPIO */
+ PAD_NC(GPD0, NONE), /* GPIO */
+ PAD_NC(GPD1, NONE), /* GPIO */
+ PAD_CFG_NF_BUF_TRIG(GPD2, NONE, PWROK, NF1, TX_RX_DISABLE, OFF), /* LAN_WAKE# */
+ PAD_CFG_NF_BUF_TRIG(GPD3, NONE, PWROK, NF1, TX_RX_DISABLE, OFF), /* PWRBTN# */
+ PAD_CFG_NF_BUF_TRIG(GPD4, NONE, PWROK, NF1, TX_RX_DISABLE, OFF), /* SLP_S3# */
+ PAD_CFG_NF_BUF_TRIG(GPD5, NONE, PWROK, NF1, TX_RX_DISABLE, OFF), /* SLP_S4# */
+ PAD_CFG_NF_BUF_TRIG(GPD6, NONE, PWROK, NF1, TX_RX_DISABLE, OFF), /* SLP_A# */
+ _PAD_CFG_STRUCT(GPD7, PAD_FUNC(GPIO) | PAD_RESET(PWROK) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(NONE)), /* GPIO */
+ PAD_CFG_NF_BUF_TRIG(GPD8, NONE, PWROK, NF1, TX_RX_DISABLE, OFF), /* SUSCLK */
+ PAD_NC(GPD9, NONE), /* GPIO */
+ PAD_NC(GPD10, NONE), /* GPIO */
+ PAD_NC(GPD11, NONE), /* GPIO */
+ PAD_CFG_NF_BUF_TRIG(GPP_I0, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* DDPB_HPD0 */
+ PAD_CFG_NF_BUF_TRIG(GPP_I1, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* DDPC_HPD1 */
+ PAD_CFG_NF_BUF_TRIG(GPP_I2, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* DDPD_HPD2 */
+ PAD_CFG_NF_BUF_TRIG(GPP_I3, NONE, PLTRST, NF1, TX_RX_DISABLE, OFF), /* DDPE_HPD3 */
+ PAD_NC(GPP_I4, NONE), /* GPIO */
+ PAD_CFG_NF_BUF_TRIG(GPP_I5, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* DDPB_CTRLCLK */
+ PAD_CFG_NF_BUF_TRIG(GPP_I6, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* DDPB_CTRLDATA */
+ PAD_CFG_NF_BUF_TRIG(GPP_I7, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* DDPC_CTRLCLK */
+ PAD_CFG_NF_BUF_TRIG(GPP_I8, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* DDPC_CTRLDATA */
+ PAD_CFG_NF_BUF_TRIG(GPP_I9, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* DDPD_CTRLCLK */
+ PAD_CFG_NF_BUF_TRIG(GPP_I10, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* DDPD_CTRLDATA */
};
@@ -233,15 +233,15 @@
static const struct pad_config early_gpio_table[] = {
/* LPC */
-/* LAD0 */ _PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x00000000),
-/* LAD1 */ _PAD_CFG_STRUCT(GPP_A2, 0x44000700, 0x00000000),
-/* LAD2 */ _PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x00000000),
-/* LAD3 */ _PAD_CFG_STRUCT(GPP_A4, 0x44000700, 0x00000000),
-/* LFRAME# */ _PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x00000000),
-/* SERIRQ */ _PAD_CFG_STRUCT(GPP_A6, 0x44000700, 0x00000000),
-/* CLKRUN# */ _PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x00000000),
-/* CLKOUT_LPC0 */ _PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x00000000),
-/* CLKOUT_LPC1 */ _PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x00000000),
+ PAD_CFG_NF_BUF_TRIG(GPP_A1, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* LAD0 */
+ PAD_CFG_NF_BUF_TRIG(GPP_A2, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* LAD1 */
+ PAD_CFG_NF_BUF_TRIG(GPP_A3, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* LAD2 */
+ PAD_CFG_NF_BUF_TRIG(GPP_A4, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* LAD3 */
+ PAD_CFG_NF_BUF_TRIG(GPP_A5, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* LFRAME# */
+ PAD_CFG_NF_BUF_TRIG(GPP_A6, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* SERIRQ */
+ PAD_CFG_NF_BUF_TRIG(GPP_A8, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* CLKRUN# */
+ PAD_CFG_NF_BUF_TRIG(GPP_A9, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* CLKOUT_LPC0 */
+ PAD_CFG_NF_BUF_TRIG(GPP_A10, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* CLKOUT_LPC1 */
};
#endif /* __ACPI__ */
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Idad7536854d4b1ae7dcf7934e81de438478fe059
Gerrit-Change-Number: 35679
Gerrit-PatchSet: 1
Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com>
Gerrit-MessageType: newchange
1 day, 5 hours
- 3
- 19
Change in coreboot[master]: util/intelp2m: initial commit
by Maxim Polyakov (Code Review)
Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35643 )
Change subject: util/intelp2m: initial commit
......................................................................
util/intelp2m: initial commit
intelp2m - Intel Pad to Macro
A small utility for converting a pad configuration from an inteltool
dump to a PAD_CFG_ * macro coreboot.
Tested on Asroch-H110M-DVS motherboard [2]
[1] https://github.com/maxpoliak/pch-pads-parser
[2] https://review.coreboot.org/c/coreboot/+/33565
Change-Id: If3e3b523c4f63dc2f91e9ccd16934e3a1b6e21fa
Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com>
---
A util/intelp2m/main.go
A util/intelp2m/parser/parser.go
A util/intelp2m/sunrise/dw.go
A util/intelp2m/sunrise/macro.go
4 files changed, 871 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/35643/1
diff --git a/util/intelp2m/main.go b/util/intelp2m/main.go
new file mode 100644
index 0000000..0881e10
--- /dev/null
+++ b/util/intelp2m/main.go
@@ -0,0 +1,129 @@
+package main
+
+import (
+ "flag"
+ "fmt"
+ "os"
+)
+
+import "./parser"
+
+// HdrInfoAdd - adds license header to file f
+func HdrInfoAdd(f *os.File) {
+ f.WriteString(`/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+`)
+}
+
+// CreateHdrFile - generates include file
+func CreateHdrFile() (err error) {
+ hrdFile, err := os.Create("generate/gpio.h")
+ if err != nil {
+ fmt.Printf("Error!\n")
+ return err
+ }
+ defer hrdFile.Close()
+
+ HdrInfoAdd(hrdFile)
+ hrdFile.WriteString(`#ifndef PCH_GPIO_H
+#define PCH_GPIO_H
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+const struct pad_config *get_gpio_table(size_t *num);
+const struct pad_config *get_early_gpio_table(size_t *num);
+
+#endif /* PCH_GPIO_H */
+`)
+ return nil
+}
+
+// CreateGpioFile - generates gpio_raw.c file
+// parser : parser data structure
+// showRawDataFlag : raw data flag
+// in the case when this flag is false, pad information will
+// be create as macro
+func CreateGpioFile(parser *parser.ParserData, showRawDataFlag bool) (err error) {
+ var name = "generate/gpio"
+ if showRawDataFlag {
+ name += "_raw"
+ }
+ name += ".c"
+ gpio, err := os.Create(name)
+ if err != nil {
+ fmt.Printf("Error!\n")
+ return err
+ }
+ defer gpio.Close()
+
+ HdrInfoAdd(gpio)
+ gpio.WriteString(`
+#include <commonlib/helpers.h>
+#include "include/gpio.h"
+`)
+ // Add the pads map to gpio.h file
+ parser.PadMapFprint(gpio, showRawDataFlag)
+ return nil
+}
+
+// main
+func main() {
+ // Command line arguments
+ wordPtr := flag.String("file",
+ "inteltool.log",
+ "the path to the inteltool log file")
+ dbgPtr := flag.Bool("dbg", false, "debug flag")
+ flag.Parse()
+
+ fmt.Println("dbg:", *dbgPtr)
+ fmt.Println("file:", *wordPtr)
+
+ var parser parser.ParserData
+ parser.DbgFlag = *dbgPtr
+ err := parser.Parse(*wordPtr)
+ if err != nil {
+ fmt.Printf("Parser: Error!\n")
+ os.Exit(1)
+ }
+
+ // create dir for output files
+ err = os.MkdirAll("generate", os.ModePerm)
+ if err != nil {
+ fmt.Printf("Create a directory of generated files: Error!\n")
+ os.Exit(1)
+ }
+
+ // gpio.h
+ err = CreateHdrFile()
+ if err != nil {
+ fmt.Printf("Create pch_gpio.h: Error!\n")
+ os.Exit(1)
+ }
+
+ // gpio_raw.c
+ err = CreateGpioFile(&parser, true)
+ if err != nil {
+ fmt.Printf("Create gpio_raw.c: Error!\n")
+ os.Exit(1)
+ }
+
+ // gpio.c with macros
+ err = CreateGpioFile(&parser, false)
+ if err != nil {
+ fmt.Printf("Create gpio.c: Error!\n")
+ os.Exit(1)
+ }
+}
diff --git a/util/intelp2m/parser/parser.go b/util/intelp2m/parser/parser.go
new file mode 100644
index 0000000..b684653
--- /dev/null
+++ b/util/intelp2m/parser/parser.go
@@ -0,0 +1,189 @@
+package parser
+
+import (
+ "bufio"
+ "fmt"
+ "os"
+ "strings"
+)
+
+import "../sunrise"
+
+// padInfo - information about pad
+// id : pad id string
+// offset : the offset of the register address relative to the base
+// function : the string that means the pad function
+// dw0 : DW0 register value
+// dw1 : DW1 register value
+type padInfo struct {
+ id string
+ offset uint16
+ function string
+ community uint8
+ dw0 uint32
+ dw1 uint32
+}
+
+// add - add information about pad to data structure
+// line : string from inteltool log file
+func (info *padInfo) add(line string) {
+ var val uint64
+ if strings.HasPrefix(line, "----") {
+ // ------- GPIO Group GPP_A -------
+ // ------- GPIO Community 0 -------
+ // Add header to define GPIO group or community
+ info.function = line
+ return
+ }
+ // 0x0520: 0x0000003c44000600 GPP_B12 SLP_S0#
+ // 0x0438: 0xffffffffffffffff GPP_C7 RESERVED
+ fmt.Sscanf(line,
+ "0x%x: 0x%x %s %s",
+ &info.offset,
+ &val,
+ &info.id,
+ &info.function)
+ info.dw0 = uint32(val & 0xffffffff)
+ info.dw1 = uint32(val >> 32)
+}
+
+// titleFprint - print GPIO group title to file
+// gpio : gpio.c file descriptor
+func (info *padInfo) titleFprint(gpio *os.File) {
+ fmt.Fprintf(gpio, "\n\t/* %s */\n", info.function)
+}
+
+// reservedFprint - print reserved GPIO to file as comment
+// gpio : gpio.c file descriptor
+func (info *padInfo) reservedFprint(gpio *os.File) {
+ // small comment about reserved port
+ fmt.Fprintf(gpio, "\t/* %s - %s */\n", info.id, info.function)
+}
+
+// padInfoRawFprint - print information about current pad to file using
+// raw format:
+// _PAD_CFG_STRUCT(GPP_F1, 0x84000502, 0x00003026), /* SATAXPCIE4 */
+// gpio : gpio.c file descriptor
+func (info *padInfo) padInfoRawFprint(gpio *os.File) {
+ fmt.Fprintf(gpio,
+ "\t_PAD_CFG_STRUCT(%s, 0x%0.8x, 0x%0.8x), /* %s */\n",
+ info.id,
+ info.dw0,
+ (info.dw1 & 0xffffff00), // Interrupt Select - RO
+ info.function)
+}
+
+// padInfoMacroFprint - print information about current pad to file using
+// special macros:
+// PAD_CFG_NF(GPP_F1, 20K_PU, PLTRST, NF1), /* SATAXPCIE4 */
+// gpio : gpio.c file descriptor
+func (info *padInfo) padInfoMacroFprint(gpio *os.File) {
+ fmt.Fprintf(gpio, "\t/* %s - %s */\n\t%s\n",
+ info.id,
+ info.function,
+ sunrise.GetMacro(info.id, info.dw0, info.dw1))
+}
+
+// ParserData - global data
+// padmap : pad info map
+// dbgFlag : gebug flag, currently not used
+type ParserData struct {
+ padmap []padInfo
+ DbgFlag bool
+}
+
+// padInfoAdd - adds a new entry to pad info map
+// line : string/line from the inteltool log file
+// community : pads community number
+func (parser *ParserData) padInfoAdd(line string, community uint8) {
+ pad := padInfo{community : community}
+ pad.add(line)
+ parser.padmap = append(parser.padmap, pad)
+}
+
+// getCommunity - scans the string and returns the pads community number
+// line : string from inteltool log file
+// return
+// community number
+func (parser *ParserData) getCommunity(line string) uint8 {
+ var comm uint8
+ fmt.Sscanf(line, "------- GPIO Community %d -------", &comm)
+ return comm
+}
+
+// PadMapFprint - print pad info map to file
+// gpio : gpio.c descriptor file
+// raw : in the case when this flag is false, pad information will be print
+// as macro
+func (parser *ParserData) PadMapFprint(gpio *os.File, raw bool) {
+ gpio.WriteString("\n/* Pad configuration in ramstage */\n")
+ gpio.WriteString("static const struct pad_config gpio_table[] = {\n")
+ for _, pad := range parser.padmap {
+ switch pad.dw0 {
+ case 0:
+ pad.titleFprint(gpio)
+ case 0xffffffff:
+ pad.reservedFprint(gpio)
+ default:
+ if raw {
+ pad.padInfoRawFprint(gpio)
+ } else {
+ pad.padInfoMacroFprint(gpio)
+ }
+ }
+ }
+ gpio.WriteString("};\n")
+
+ // FIXME: need to add early configuration
+ gpio.WriteString(`/* Early pad configuration in romstage. */
+static const struct pad_config early_gpio_table[] = {
+ /* TODO: Add early pad configuration */
+};
+
+const struct pad_config *get_gpio_table(size_t *num)
+{
+ *num = ARRAY_SIZE(gpio_table);
+ return gpio_table;
+}
+
+const struct pad_config *get_early_gpio_table(size_t *num)
+{
+ *num = ARRAY_SIZE(early_gpio_table);
+ return early_gpio_table;
+}
+
+`)
+}
+
+// Parse pads groupe information in the inteltool log file
+// logFile : name of inteltool log file
+// return
+// err : error
+func (parser *ParserData) Parse(logFile string) (err error) {
+ file, err := os.Open(logFile)
+ if err != nil {
+ return err
+ }
+ defer file.Close()
+
+ // Read all lines from inteltool log file
+ fmt.Println("Parse IntelTool Log File...")
+ scanner := bufio.NewScanner(file)
+ var line string
+ var community uint8 = 0
+ for scanner.Scan() {
+ line = scanner.Text()
+ // Use only the string that contains the GPP information
+ if !strings.Contains(line, "GPP_") && !strings.Contains(line, "GPD") {
+ // ------- GPIO Community 0 -------
+ if strings.Contains(line, "Community") {
+ community = parser.getCommunity(line)
+ } else {
+ continue
+ }
+ }
+ parser.padInfoAdd(line, community)
+ }
+ fmt.Println("...done!")
+ return nil
+}
\ No newline at end of file
diff --git a/util/intelp2m/sunrise/dw.go b/util/intelp2m/sunrise/dw.go
new file mode 100644
index 0000000..f3623b0
--- /dev/null
+++ b/util/intelp2m/sunrise/dw.go
@@ -0,0 +1,198 @@
+package sunrise
+
+// Bit field constants for DW0 register
+const (
+ padRstCfgShift uint8 = 30
+ padRstCfgMask uint32 = 0x3 << padRstCfgShift
+
+ rxPadStateSelectShift uint8 = 29
+ rxPadStateSelectMask uint32 = 0x1 << rxPadStateSelectShift
+
+ rxRawOverrideTo1Shift uint8 = 28
+ rxRawOverrideTo1Mask uint32 = 0x1 << rxRawOverrideTo1Shift
+
+ rxLevelEdgeConfigurationShift uint8 = 25
+ rxLevelEdgeConfigurationMask uint32 = 0x3 << rxLevelEdgeConfigurationShift
+
+ rxInvertShift uint8 = 23
+ rxInvertMask uint32 = 0x1 << rxInvertShift
+
+ gpioInputRouteIOxApicShift uint8 = 20
+ gpioInputRouteIOxApicMask uint32 = 0x1 << gpioInputRouteIOxApicShift
+
+ gpioInputRouteSCIShift uint8 = 19
+ gpioInputRouteSCIMask uint32 = 0x1 << gpioInputRouteSCIShift
+
+ gpioInputRouteSMIShift uint8 = 18
+ gpioInputRouteSMIMask uint32 = 0x1 << gpioInputRouteSMIShift
+
+ gpioInputRouteNMIShift uint8 = 17
+ gpioInputRouteNMIMask uint32 = 0x1 << gpioInputRouteNMIShift
+
+ padModeShift uint8 = 10
+ padModeMask uint32 = 0x7 << padModeShift
+
+ gpioRxTxDisableShift uint8 = 8
+ gpioRxTxDisableMask uint32 = 0x3 << gpioRxTxDisableShift
+
+ gpioRxStateShift uint8 = 1
+ gpioRxStateMask uint32 = 0x1 << gpioRxStateShift
+
+ gpioTxStateMask uint32 = 0x1
+)
+
+// Bit field constants for DW1 register
+const (
+ termShift uint8 = 10
+ termMask uint32 = 0xF << termShift
+ interruptSelectShift uint32 = 0xFF
+)
+
+// Maximum numbers of the config DW register for Sunrise chipset
+const (
+ MaxDWNum = 2
+)
+
+// dwcfg - configuration data structure based on DW0/1 reg value
+// reg : register value
+// mask : bit fileds mask
+type dwcfg struct {
+ reg [MaxDWNum]uint32
+ mask [MaxDWNum]uint32
+}
+
+// getResetConfig - get Reset Configuration from PADRSTCFG field in PAD_CFG_DW0_GPx register
+func (dw *dwcfg) getFieldVal(regNum uint8, mask uint32, shift uint8) uint8 {
+ if regNum < MaxDWNum {
+ dw.mask[regNum] |= mask
+ return uint8((dw.reg[regNum] & mask) >> shift)
+ }
+ return 0
+}
+
+// Check the mask of the new macro
+// regNum : DW register number
+// Returns true if the macro is generated correctly
+func (dw *dwcfg) maskCheck(regNum uint8) bool {
+ if regNum >= MaxDWNum {
+ return false
+ }
+
+ // Take into account the bits that are read-only
+ readonly := [MaxDWNum]uint32{
+ (0x1 << 27) | (0x1 << 24) | (0x3 << 21) | (0xf << 16) | 0xfe,
+ 0xfffffc3f,
+ }
+ mask := ^(dw.mask[regNum] | readonly[regNum])
+ return dw.reg[regNum]&mask == 0
+}
+
+// Fix Pad Reset Config field in mask for DW0 register
+// Returns *dwcfg
+func (dw *dwcfg) maskResetFix() *dwcfg {
+ dw.mask[0] |= padRstCfgMask
+ return dw
+}
+
+// Fix RX Level/Edge Configuration field in mask for DW0 register
+// Returns *dwcfg
+func (dw *dwcfg) maskTrigFix() *dwcfg {
+ dw.mask[0] |= rxLevelEdgeConfigurationMask
+ return dw
+}
+
+// getResetConfig - returns type reset source for corresponding pad
+// PADRSTCFG field in PAD_CFG_DW0 register
+// 00 = RSMRST#, 01 = DEEP#, 10 = PLTRST#, 11 = RSMRST# for GPDx pads
+// and Reserved for others
+func (dw *dwcfg) getResetConfig() uint8 {
+ return dw.getFieldVal(0, padRstCfgMask, padRstCfgShift)
+}
+
+// getRXPadStateSelect - returns RX Pad State (RXINV)
+// 0 = Raw RX pad state directly from RX buffer
+// 1 = Internal RX pad state
+func (dw *dwcfg) getRXPadStateSelect() uint8 {
+ return dw.getFieldVal(0, rxPadStateSelectMask, rxPadStateSelectShift)
+}
+
+// getRXRawOverrideStatus - returns 1 if the selected pad state is being
+// overridden to '1' (RXRAW1 field)
+func (dw *dwcfg) getRXRawOverrideStatus() uint8 {
+ return dw.getFieldVal(0, rxRawOverrideTo1Mask, rxRawOverrideTo1Shift)
+}
+
+// getRXLevelEdgeConfiguration - returns RX Level/Edge Configuration (RXEVCFG)
+// 0h = Level, 1h = Edge, 2h = Drive '0', 3h = Reserved (implement as setting 0h)
+func (dw *dwcfg) getRXLevelEdgeConfiguration() uint8 {
+ return dw.getFieldVal(0, rxLevelEdgeConfigurationMask, rxLevelEdgeConfigurationShift)
+}
+
+// getRXLevelConfiguration - returns RX Invert state (RXINV)
+// 1 - Inversion, 0 - No inversion
+func (dw *dwcfg) getRXLevelConfiguration() bool {
+ return dw.getFieldVal(0, rxInvertMask, rxInvertShift) != 0
+}
+
+// getGPIOInputRouteIOxAPIC - returns 1 if the pad can be routed to cause
+// peripheral IRQ when configured in GPIO input mode.
+func (dw *dwcfg) getGPIOInputRouteIOxAPIC() bool {
+ return dw.getFieldVal(0, gpioInputRouteIOxApicMask, gpioInputRouteIOxApicShift) != 0
+}
+
+// getGPIOInputRouteSCI - returns 1 if the pad can be routed to cause SCI when
+// configured in GPIO input mode.
+func (dw *dwcfg) getGPIOInputRouteSCI() bool {
+ return dw.getFieldVal(0, gpioInputRouteSCIMask, gpioInputRouteSCIShift) != 0
+}
+
+// getGPIOInputRouteSMI - returns 1 if the pad can be routed to cause SMI when
+// configured in GPIO input mode
+func (dw *dwcfg) getGPIOInputRouteSMI() bool {
+ return dw.getFieldVal(0, gpioInputRouteSMIMask, gpioInputRouteSMIShift) != 0
+}
+
+// getGPIOInputRouteNMI - returns 1 if the pad can be routed to cause NMI when
+// configured in GPIO input mode
+func (dw *dwcfg) getGPIOInputRouteNMI() bool {
+ return dw.getFieldVal(0, gpioInputRouteNMIMask, gpioInputRouteNMIShift) != 0
+}
+
+// getPadMode - reutrns pad mode or one of the native functions
+// 0h = GPIO control the Pad.
+// 1h = native function 1, if applicable, controls the Pad
+// 2h = native function 2, if applicable, controls the Pad
+// 3h = native function 3, if applicable, controls the Pad
+// 4h = enable GPIO blink/PWM capability if applicable
+func (dw *dwcfg) getPadMode() uint8 {
+ return dw.getFieldVal(0, padModeMask, padModeShift)
+}
+
+// getGPIORxTxDisableStatus - returns GPIO RX/TX buffer state (GPIORXDIS | GPIOTXDIS)
+// 0 - both are enabled, 1 - TX Disable, 2 - RX Disable, 3 - both are disabled
+func (dw *dwcfg) getGPIORxTxDisableStatus() uint8 {
+ return dw.getFieldVal(0, gpioRxTxDisableMask, gpioRxTxDisableShift)
+}
+
+// getGPIORXState - returns GPIO RX State (GPIORXSTATE)
+func (dw *dwcfg) getGPIORXState() uint8 {
+ return dw.getFieldVal(0, gpioRxStateMask, gpioRxStateShift)
+}
+
+// getGPIOTXState - returns GPIO TX State (GPIOTXSTATE)
+func (dw *dwcfg) getGPIOTXState() int {
+ return int(dw.getFieldVal(0, gpioTxStateMask, 0))
+}
+
+// getTermination - returns the pad termination state defines the different weak
+// pull-up and pull-down settings that are supported by the buffer
+// 0000 = none; 0010 = 5k PD; 0100 = 20k PD; 1010 = 5k PU; 1100 = 20k PU;
+// 1111 = Native controller selected
+func (dw *dwcfg) getTermination() uint8 {
+ return dw.getFieldVal(1, termMask, termShift)
+}
+
+// getInterruptSelect - returns Interrupt Line number from the GPIO controller
+func (dw *dwcfg) getInterruptSelect() uint8 {
+ return dw.getFieldVal(1, interruptSelectShift, 0)
+}
diff --git a/util/intelp2m/sunrise/macro.go b/util/intelp2m/sunrise/macro.go
new file mode 100644
index 0000000..7489709
--- /dev/null
+++ b/util/intelp2m/sunrise/macro.go
@@ -0,0 +1,355 @@
+package sunrise
+
+import (
+ "fmt"
+ "strconv"
+ "strings"
+)
+
+// macro - contains macro information and methods
+// padID : pad ID string
+// str : macro string entirely
+// dwcfg : configuration data structure
+type macro struct {
+ padID string
+ str string
+ dwcfg
+}
+
+// dw - returns dwcfg data configuration structure with PAD_CFG_DW0/1 register
+// values
+func (macro *macro) dw() *dwcfg {
+ return ¯o.dwcfg
+}
+
+// add a string to macro
+func (macro *macro) add(str string) *macro {
+ macro.str += str
+ return macro
+}
+
+// set a string in a macro instead of its previous contents
+func (macro *macro) set(str string) *macro {
+ macro.str = str
+ return macro
+}
+
+// get macro string
+func (macro *macro) get() string {
+ return macro.str
+}
+
+// Adds PAD Id to the macro as a new argument
+// return: macro
+func (macro *macro) id() *macro {
+ return macro.add(macro.padID)
+}
+
+// Add separator to macro if needed
+func (macro *macro) separator() *macro {
+ str := macro.get()
+ c := str[len(str)-1]
+ if c != '(' && c != '_' {
+ macro.add(", ")
+ }
+ return macro
+}
+
+// Adds the PADRSTCFG parameter from DW0 to the macro as a new argument
+// return: macro
+func (macro *macro) rstsrc() *macro {
+ var resetSrc = map[uint8]string{
+ 0x0: "PWROK",
+ 0x1: "DEEP",
+ 0x2: "PLTRST",
+ }
+ str, valid := resetSrc[macro.dw().getResetConfig()]
+ if !valid {
+ // Pad Reset Config field in DW0 register should implements 3h value
+ // as RSMRST for GPD pads group, but this value is reserved for other
+ // groups
+ if strings.Contains(macro.padID, "GPD") {
+ str = "RSMRST"
+ } else {
+ str = resetSrc[0]
+ fmt.Println("Warning:", macro.padID, "PADRSTCFG = 3h Reserved")
+ fmt.Println("It is implemented as setting 0h (PWROK) for Sunrise PCH")
+ }
+ }
+ return macro.separator().add(str)
+}
+
+// Adds The Pad Termination (TERM) parameter from DW1 to the macro as a new argument
+// return: macro
+func (macro *macro) pull() *macro {
+ var pull = map[uint8]string{
+ 0x0: "NONE",
+ 0x2: "5K_PD",
+ 0x4: "20K_PD",
+ 0x9: "1K_PU",
+ 0xa: "5K_PU",
+ 0xb: "2K_PU",
+ 0xc: "20K_PU",
+ 0xd: "667_PU",
+ 0xf: "NATIVE",
+ }
+ str, valid := pull[macro.dw().getTermination()]
+ if !valid {
+ str = "INVALID"
+ fmt.Println("Error",
+ macro.padID,
+ " invalid TERM value = ",
+ int(macro.dw().getTermination()))
+ }
+ return macro.separator().add(str)
+}
+
+// Adds Pad GPO value to macro string as a new argument
+// return: macro
+func (macro *macro) val() *macro {
+ return macro.separator().add(strconv.Itoa(macro.dw().getGPIOTXState()))
+}
+
+// Adds Pad GPO value to macro string as a new argument
+// return: macro
+func (macro *macro) trig() *macro {
+ var dw = macro.dw()
+ var trig = map[uint8]string{
+ 0x0: "LEVEL",
+ 0x1: "EDGE_SINGLE",
+ 0x2: "OFF",
+ 0x3: "EDGE_BOTH",
+ }
+ return macro.separator().add(trig[dw.getRXLevelEdgeConfiguration()])
+}
+
+// Adds Pad Polarity Inversion Stage (RXINV) to macro string as a new argument
+// return: macro
+func (macro *macro) invert() *macro {
+ macro.separator()
+ if macro.dw().getRXLevelConfiguration() {
+ return macro.add("YES")
+ }
+ return macro.add("NONE")
+}
+
+// Adds input/output buffer state
+// return: macro
+func (macro *macro) bufdis() *macro {
+ var buffDisStat = map[uint8]string{
+ 0x0: "NO_DISABLE", // both buffers are enabled
+ 0x1: "TX_DISABLE", // output buffer is disabled
+ 0x2: "RX_DISABLE", // input buffer is disabled
+ 0x3: "TX_RX_DISABLE", // both buffers are disabled
+ }
+ state := macro.dw().getGPIORxTxDisableStatus()
+ return macro.separator().add(buffDisStat[state])
+}
+
+//Adds pad native function (PMODE) as a new argument
+//return: macro
+func (macro *macro) padfn() *macro {
+ nfnum := int(macro.dw().getPadMode())
+ if nfnum != 0 {
+ return macro.separator().add("NF" + strconv.Itoa(nfnum))
+ }
+ // GPIO used only for PAD_FUNC(x) macro
+ return macro.add("GPIO")
+}
+
+// Adds suffix to GPI macro with arguments
+func (macro *macro) addSuffixInput() {
+ dw := macro.dw()
+ isEdge := dw.getRXLevelEdgeConfiguration()
+ macro.add("_GPI")
+ switch {
+ case dw.getGPIOInputRouteNMI():
+ // e.g. PAD_CFG_GPI_NMI(GPIO_24, UP_20K, DEEP, LEVEL, INVERT),
+ macro.add("_NMI").add("(").id().pull().rstsrc().trig().invert()
+
+ case dw.getGPIOInputRouteIOxAPIC():
+ // e.g. PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST)
+ macro.add("_APIC")
+ if isEdge == 0 {
+ if dw.getRXLevelConfiguration() {
+ // e.g. PAD_CFG_GPI_APIC_INVERT(GPP_C5, DN_20K, DEEP),
+ macro.add("_INVERT")
+ }
+ macro.add("(").id().pull().rstsrc()
+ } else {
+ // PAD_CFG_GPI_APIC_IOS(GPP_C20, NONE, DEEP, LEVEL, INVERT,
+ // TxDRxE, DISPUPD) macro isn't used for this chipset. But, in
+ // the case when SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS is
+ // defined in the config, this macro allows you to set trig and
+ // invert parameters.
+ macro.add("_IOS").add("(").id().pull().rstsrc().trig().invert()
+ // IOStandby Config will be ignored for the Sunrise PCH, so use
+ // any values
+ macro.add(", TxDRxE, DISPUPD")
+ }
+
+ case dw.getGPIOInputRouteSCI():
+
+ // e.g. PAD_CFG_GPI_SCI(GPP_B18, UP_20K, PLTRST, LEVEL, INVERT),
+ if (isEdge & 0x1) != 0 {
+ // e.g. PAD_CFG_GPI_ACPI_SCI(GPP_G2, NONE, DEEP, YES),
+ macro.add("_ACPI")
+ }
+ macro.add("_SCI").add("(").id().pull().rstsrc()
+ if (isEdge & 0x1) == 0 {
+ macro.trig()
+ }
+ macro.invert()
+
+ case dw.getGPIOInputRouteSMI():
+ if (isEdge & 0x1) != 0 {
+ // e.g. PAD_CFG_GPI_ACPI_SMI(GPP_I3, NONE, DEEP, YES),
+ macro.add("_ACPI")
+ }
+ macro.add("_SMI").add("(").id().pull().rstsrc().invert()
+
+ case isEdge != 0:
+ // e.g. ISH_SPI_CS#
+ // PAD_CFG_GPI_INT(GPP_D9, NONE, PLTRST, EDGE),
+ macro.add("_INT").add("(").id().pull().rstsrc().trig()
+
+ default:
+ // e.g. PAD_CFG_GPI(GPP_A7, NONE, DEEP),
+ macro.add("(").id().pull().rstsrc()
+ }
+}
+
+// Adds suffix to GPO macro with arguments
+func (macro *macro) addSuffixOutput() {
+ term := macro.dw().getTermination()
+ // FIXME: don`t understand how to get PAD_CFG_GPI_GPIO_DRIVER(..)
+ if term != 0 {
+ // e.g. PAD_CFG_TERM_GPO(GPP_B23, 1, DN_20K, DEEP),
+ macro.add("_TERM")
+ }
+ macro.add("_GPO").add("(").id().val()
+ if term != 0 {
+ macro.pull()
+ }
+ macro.rstsrc()
+
+ // Fix mask for RX Level/Edge Configuration (RXEVCFG)
+ // See https://github.com/coreboot/coreboot/commit/3820e3c
+ macro.dw().maskTrigFix()
+}
+
+const (
+ rxDisable uint8 = 0x2
+ txDisable uint8 = 0x1
+)
+
+// Set common macros macros if the standard ones can't define the values from
+// the DW0/1 register
+func (macro *macro) common() *macro {
+ macro.set("_PAD_CFG_STRUCT(").id().
+ add(",\n\t\tPAD_FUNC(").padfn().
+ add(") | PAD_RESET(").rstsrc().add(") |\n\t\t")
+
+ var str string
+ var argument = true
+ switch dw := macro.dw(); {
+ case dw.getGPIOInputRouteIOxAPIC():
+ str = "IOAPIC"
+ case dw.getGPIOInputRouteSCI():
+ str = "SCI"
+ case dw.getGPIOInputRouteSMI():
+ str = "SMI"
+ case dw.getGPIOInputRouteNMI():
+ str = "NMI"
+ default:
+ argument = false
+ }
+
+ if argument {
+ macro.add("PAD_IRQ_CFG(").add(str).trig().invert().add(")")
+ } else {
+ macro.add("PAD_CFG0_TRIG_").trig().add(" | PAD_CFG0_RX_POL_").invert()
+ }
+
+ macro.add(" |\n\t\t").add("PAD_BUF(").bufdis().add(")")
+ if macro.dw().getGPIOTXState() != 0 {
+ macro.add(" | 1")
+ }
+ return macro.add(",\n\t\tPAD_PULL(").pull().add(")),")
+}
+
+// Check created macro
+func (macro *macro) check() {
+ if !macro.dw().maskCheck(0) {
+ macro.common()
+ // Debug message about this
+ fmt.Printf(
+ "\nCoreboot macros can't define the configuration for pad: %s\n",
+ macro.padID)
+ fmt.Printf("Use %s\n", macro.get())
+ }
+}
+
+// Gets base string of current macro
+// return: string of macro
+// error
+func (macro *macro) generate(id string, dw0 uint32, dw1 uint32) string {
+ macro.dwcfg.reg[0] = dw0
+ macro.dwcfg.reg[1] = dw1
+ dw := ¯o.dwcfg
+
+ macro.set("PAD_CFG")
+ if dw.getPadMode() == 0 {
+ // GPIO
+ switch dw.getGPIORxTxDisableStatus() {
+ case rxDisable:
+ // GPI
+ macro.addSuffixInput()
+
+ case txDisable:
+ // GPO
+ macro.addSuffixOutput()
+
+ case rxDisable | txDisable:
+ // NC
+ macro.set("PAD_NC").add("(").id().pull()
+ // Fix mask for RX Level/Edge Configuration (RXEVCFG)
+ // and Pad Reset Config (PADRSTCFG)
+ // There is no need to check these fields if the pad
+ // is in the NC state
+ macro.dw().maskResetFix().maskTrigFix()
+
+ default:
+ // In case the rule isn't found, a common macro is used
+ // to create the pad configuration
+ return macro.common().get()
+ }
+ } else {
+ isEdge := dw.getRXLevelEdgeConfiguration() != 0
+ isTxRxBufDis := dw.getGPIORxTxDisableStatus() != 0
+ // e.g. PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1)
+ macro.add("_NF")
+ if isEdge || isTxRxBufDis {
+ // e.g. PCHHOT#
+ // PAD_CFG_NF_BUF_TRIG(GPP_B23, 20K_PD, PLTRST, NF2, RX_DIS, OFF),
+ macro.add("_BUF_TRIG")
+ }
+ macro.add("(").id().pull().rstsrc().padfn()
+ if isEdge || isTxRxBufDis {
+ macro.bufdis().trig()
+ }
+ }
+ macro.add("),")
+ macro.check()
+ return macro.get()
+}
+
+// GetMacro - get pad macro
+// dw0 : DW0 config register value
+// dw1 : DW1 config register value
+// return: string of macro
+// error
+func GetMacro(id string, dw0 uint32, dw1 uint32) string {
+ macro := macro{padID : id}
+ return macro.generate(id, dw0, dw1)
+}
--
To view, visit https://review.coreboot.org/c/coreboot/+/35643
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: If3e3b523c4f63dc2f91e9ccd16934e3a1b6e21fa
Gerrit-Change-Number: 35643
Gerrit-PatchSet: 1
Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com>
Gerrit-MessageType: newchange
1 day, 18 hours
- 9
- 44
Change in coreboot[master]: cpu/x86/smm: Add support for long mode
by Patrick Rudolph (Code Review)
Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35681 )
Change subject: cpu/x86/smm: Add support for long mode
......................................................................
cpu/x86/smm: Add support for long mode
Enable long mode in SMM handler.
x86_32 isn't affected from this change.
As the rsm instruction used to leave SMM doesn't restore MSR registers,
drop back to protected mode after running the smi_handler and restore
IA32_EFER MSR to previous value.
Tested on Qemu Q35.
Needs tests on real hardware.
Change-Id: I8bba4af4688c723fc079ae905dac95f57ea956f8
Signed-off-by: Patrick Rudolph <siro(a)das-labor.org>
---
M Documentation/arch/x86/index.md
M src/cpu/x86/smm/smmhandler.S
2 files changed, 95 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/35681/1
diff --git a/Documentation/arch/x86/index.md b/Documentation/arch/x86/index.md
index 462e7e6..b02b879 100644
--- a/Documentation/arch/x86/index.md
+++ b/Documentation/arch/x86/index.md
@@ -45,6 +45,7 @@
* Add x86_64 exception handlers - *TODO*
* Setup page tables for long mode - *DONE*
* Add assembly code for long mode - *DONE*
+* Add assembly code for SMM - *DONE*
* Add assembly code for postcar stage - *TODO*
* Add assembly code to return to protected mode - *TODO*
* Implement reference code for mainboard `emulation/qemu-q35` - *TODO*
diff --git a/src/cpu/x86/smm/smmhandler.S b/src/cpu/x86/smm/smmhandler.S
index a2be7f2..fd8af79 100644
--- a/src/cpu/x86/smm/smmhandler.S
+++ b/src/cpu/x86/smm/smmhandler.S
@@ -20,6 +20,7 @@
*/
#include <cpu/x86/lapic_def.h>
+#include <cpu/x86/msr.h>
/*
* +--------------------------------+ 0xaffff
@@ -171,15 +172,104 @@
/* Get SMM revision */
movl $0xa8000 + 0x7efc, %ebx /* core 0 address */
subl %ebp, %ebx /* subtract core X offset */
+
+#if defined(__x86_64__)
+ /* Backup IA32_EFER. Preserves ebx. */
+ movl $(IA32_EFER), %ecx
+ rdmsr
+ movl %eax, ia32efer_backup
+
+ /* Enable long mode if required. Preserves ebx. */
+#include <cpu/x86/64bit/entry64.inc>
+
+ mov (%ebx), %rdi
+
+#else
movl (%ebx), %eax
pushl %eax
+#endif
- /* Call 32bit C handler */
+ /* Call C handler */
call smi_handler
+#if defined(__x86_64__)
+ /*
+ * The only reason to go back to protected mode is that rsm doesn't restore
+ * MSR registers and IA32_EFER was modified.
+ * To restore IA32_EFER go back to protected mode.
+ */
+
+ /* Ensure cache is clean. */
+ invd
+
+ /* Set 32-bit code segment and ss */
+ mov $0x08, %rcx
+ call SetCodeSelector32
+
+.code32
+ /* Running in 32-bit compatibility mode */
+
+ /* Use flat data segment */
+ movl $0x10, %eax
+ movl %eax, %ds
+ movl %eax, %es
+ movl %eax, %ss
+ movl %eax, %fs
+ movl %eax, %gs
+
+ /* Disable paging */
+ movl %cr0, %eax
+ andl $0x7FFFFFFF, %eax
+ movl %eax, %cr0
+
+ /* Disable long mode */
+ movl $(IA32_EFER), %ecx
+ rdmsr
+ andl $(~EFER_LME), %eax
+ wrmsr
+
+ /* Disable PAE */
+ movl %cr4, %eax
+ andl $(~0x20), %eax
+ movl %eax, %cr4
+
+ /* Restore IA32_EFER */
+ movl $(IA32_EFER), %ecx
+ rdmsr
+ movl ia32efer_backup, %eax
+ wrmsr
+#endif
+
/* To return, just do rsm. It will "clean up" protected mode */
rsm
+#if defined(__x86_64__)
+ia32efer_backup:
+.long
+
+.align 8
+.code64
+SetCodeSelector32:
+ # pop the return address from stack
+ pop %rbx
+
+ # save rsp because we need to push it after ss
+ mov %rsp, %rdx
+
+ # use iret to jump to a 32-bit offset in a new code segment
+ # iret will pop cs:rip, flags, then ss:rsp
+ mov %ss, %ax # need to push ss..
+ push %rax # push ss instuction not valid in x64 mode,
+ # so use ax
+ push %rdx # the rsp to load
+ pushfq # push rflags
+ push %rcx # cx is code segment selector from caller
+ push %rbx # push the IP for the next instruction
+
+ # the iretq will behave like ret, with the new cs/ss value loaded
+ iretq
+#endif
+
.code16
.align 4, 0xff
@@ -202,6 +292,9 @@
.word 0xffff, 0x0000
.byte 0x00, 0x93, 0xcf, 0x00
+ /* gdt selector 0x18, flat code segment (64-bit) */
+ .word 0xffff, 0x0000
+ .byte 0x00, 0x9b, 0xaf, 0x00
smm_gdt_end:
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I8bba4af4688c723fc079ae905dac95f57ea956f8
Gerrit-Change-Number: 35681
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-MessageType: newchange
5 days, 6 hours
- 6
- 31
Change in coreboot[master]: mb/lenovo/t60: Switch to override tree
by Peter Lemenkov (Code Review)
Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34779 )
Change subject: mb/lenovo/t60: Switch to override tree
......................................................................
mb/lenovo/t60: Switch to override tree
Change-Id: I13c0134b22e2203e6cee6ecafda0dae89e086aff
Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com>
---
M src/mainboard/lenovo/t60/Kconfig
R src/mainboard/lenovo/t60/devicetree.cb
A src/mainboard/lenovo/t60/variants/t60/overridetree.cb
D src/mainboard/lenovo/t60/variants/z61t/devicetree.cb
A src/mainboard/lenovo/t60/variants/z61t/overridetree.cb
5 files changed, 135 insertions(+), 257 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/34779/1
diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig
index 725528d..ad74f63 100644
--- a/src/mainboard/lenovo/t60/Kconfig
+++ b/src/mainboard/lenovo/t60/Kconfig
@@ -33,9 +33,9 @@
default "t60" if BOARD_LENOVO_T60
default "z61t" if BOARD_LENOVO_Z61T
-config DEVICETREE
+config OVERRIDE_DEVICETREE
string
- default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"
+ default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
config MAINBOARD_PART_NUMBER
string
diff --git a/src/mainboard/lenovo/t60/variants/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb
similarity index 93%
rename from src/mainboard/lenovo/t60/variants/t60/devicetree.cb
rename to src/mainboard/lenovo/t60/devicetree.cb
index 9279dcb..70900ea 100644
--- a/src/mainboard/lenovo/t60/variants/t60/devicetree.cb
+++ b/src/mainboard/lenovo/t60/devicetree.cb
@@ -116,7 +116,6 @@
end
register "scr" = "0x0844d070"
register "mrr" = "0x01d01002"
-
end
end
device pci 1e.2 off end # AC'97 Audio
@@ -159,10 +158,6 @@
register "eventb_enable" = "0xff"
register "eventc_enable" = "0x3c"
register "eventd_enable" = "0xff"
-
- register "has_bdc_detection" = "1"
- register "bdc_gpio_num" = "7"
- register "bdc_gpio_lvl" = "0"
end
chip superio/nsc/pc87382
device pnp 164e.2 on # IR
@@ -209,21 +204,12 @@
end
end
end
- device pci 1f.1 on # IDE
- subsystemid 0x17aa 0x200c
- end
device pci 1f.2 on # SATA
subsystemid 0x17aa 0x200d
end
device pci 1f.3 on # SMBUS
subsystemid 0x17aa 0x200f
chip drivers/i2c/ck505
- register "mask" = "{ 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff }"
- register "regs" = "{ 0x2e, 0xf7, 0x3c,
- 0x20, 0x01, 0x00, 0x1b, 0x01,
- 0x54, 0xff, 0xff, 0x07 }"
device i2c 69 on end
end
# eeprom, 8 virtual devices, same chip
diff --git a/src/mainboard/lenovo/t60/variants/t60/overridetree.cb b/src/mainboard/lenovo/t60/variants/t60/overridetree.cb
new file mode 100644
index 0000000..eee3a4d
--- /dev/null
+++ b/src/mainboard/lenovo/t60/variants/t60/overridetree.cb
@@ -0,0 +1,69 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2009 coresystems GmbH
+## Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org>
+##
+## This program is free software; you can redistribute it and/or
+## modify it under the terms of the GNU General Public License as
+## published by the Free Software Foundation; version 2 of
+## the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+chip northbridge/intel/i945
+ device domain 0 on
+ device pci 00.0 on # Host bridge
+ subsystemid 0x17aa 0x2015
+ end
+ device pci 01.0 on # PCI-e
+ device pci 00.0 on # VGA
+ subsystemid 0x17aa 0x20a4
+ end
+ end
+ chip southbridge/intel/i82801gx
+ device pci 1c.0 on # Ethernet
+ subsystemid 0x17aa 0x2001
+ end
+ device pci 1c.1 on end # WLAN
+ device pci 1c.2 on end # PCIe port 3
+ device pci 1c.3 on end # PCIe port 4
+ device pci 1e.0 on # PCI Bridge
+ chip southbridge/ti/pci1x2x
+ device pci 00.0 on
+ subsystemid 0x17aa 0x2012
+ end
+ end
+ end
+ device pci 1f.0 on # PCI-LPC bridge
+ chip ec/lenovo/h8
+ register "has_bdc_detection" = "1"
+ register "bdc_gpio_num" = "7"
+ register "bdc_gpio_lvl" = "0"
+ end
+ chip superio/nsc/pc87384
+ device pnp 2e.2 off # Serial Port / IR
+ irq 0x70 = 4
+ end
+ end
+ end
+ device pci 1f.1 on # IDE
+ subsystemid 0x17aa 0x200c
+ end
+ device pci 1f.3 on # SMBUS
+ chip drivers/i2c/ck505
+ register "mask" = "{ 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff }"
+ register "regs" = "{ 0x2e, 0xf7, 0x3c,
+ 0x20, 0x01, 0x00, 0x1b, 0x01,
+ 0x54, 0xff, 0xff, 0x07 }"
+ end
+ end
+ end
+ end
+end
diff --git a/src/mainboard/lenovo/t60/variants/z61t/devicetree.cb b/src/mainboard/lenovo/t60/variants/z61t/devicetree.cb
deleted file mode 100644
index d35c62b..0000000
--- a/src/mainboard/lenovo/t60/variants/z61t/devicetree.cb
+++ /dev/null
@@ -1,241 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007-2009 coresystems GmbH
-## Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org>
-##
-## This program is free software; you can redistribute it and/or
-## modify it under the terms of the GNU General Public License as
-## published by the Free Software Foundation; version 2 of
-## the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-chip northbridge/intel/i945
- # IGD Displays
- register "gfx.ndid" = "3"
- register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
-
- register "gpu_hotplug" = "0x00000220"
- register "gpu_lvds_use_spread_spectrum_clock" = "1"
- register "pwm_freq" = "275"
- register "gpu_panel_power_up_delay" = "250"
- register "gpu_panel_power_backlight_on_delay" = "2380"
- register "gpu_panel_power_down_delay" = "250"
- register "gpu_panel_power_backlight_off_delay" = "2380"
- register "gpu_panel_power_cycle_delay" = "2"
-
- device cpu_cluster 0 on
- chip cpu/intel/socket_m
- device lapic 0 on end
- end
- end
-
- register "pci_mmio_size" = "768"
-
- device domain 0 on
- device pci 00.0 on # Host bridge
- subsystemid 0x17aa 0x2017
- end
-
- device pci 01.0 on # PEG
- device pci 00.0 on end # VGA
- end
-
- device pci 02.0 on # GMA Graphics controller
- subsystemid 0x17aa 0x201a
- end
- device pci 02.1 on # display controller
- subsystemid 0x17aa 0x201a
- end
-
- chip southbridge/intel/i82801gx
- register "pirqa_routing" = "0x0b"
- register "pirqb_routing" = "0x0b"
- register "pirqc_routing" = "0x0b"
- register "pirqd_routing" = "0x0b"
- register "pirqe_routing" = "0x0b"
- register "pirqf_routing" = "0x0b"
- register "pirqg_routing" = "0x0b"
- register "pirqh_routing" = "0x0b"
-
- # GPI routing
- # 0 No effect (default)
- # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
- # 2 SCI (if corresponding GPIO_EN bit is also set)
- register "gpi13_routing" = "2"
- register "gpi12_routing" = "2"
- register "gpi8_routing" = "2"
-
- register "sata_ports_implemented" = "0x01"
-
- register "gpe0_en" = "0x11000006"
- register "alt_gp_smi_en" = "0x1000"
-
- register "c4onc3_enable" = "1"
- register "c3_latency" = "0x23"
- register "docking_supported" = "1"
- register "p_cnt_throttling_supported" = "1"
-
- device pci 1b.0 on # Audio Controller
- subsystemid 0x17aa 0x2010
- end
- device pci 1c.0 on # PCI Express Port 1
- subsystemid 0x17aa 0x2011
- end
- device pci 1c.1 on # PCI Express Port 2
- subsystemid 0x17aa 0x2011
- end
- device pci 1c.2 on # PCI Express Port 3
- subsystemid 0x17aa 0x2011
- end
- device pci 1c.3 on # PCI Express Port 4
- subsystemid 0x17aa 0x2011
- end
- device pci 1c.4 off end # PCIe port 5
- device pci 1c.5 off end # PCIe port 6
-
- device pci 1d.0 on # USB UHCI
- subsystemid 0x17aa 0x200a
- end
- device pci 1d.1 on # USB UHCI
- subsystemid 0x17aa 0x200a
- end
- device pci 1d.2 on # USB UHCI
- subsystemid 0x17aa 0x200a
- end
- device pci 1d.3 on # USB UHCI
- subsystemid 0x17aa 0x200a
- end
- device pci 1d.7 on # USB2 EHCI
- subsystemid 0x17aa 0x200b
- end
- device pci 1e.0 on # PCI Bridge
- chip southbridge/ti/pci1x2x
- device pci 00.0 on
- subsystemid 0x17aa 0x2013
- end
- register "scr" = "0x0844d070"
- register "mrr" = "0x01d01002"
-
- end
- end
- device pci 1e.2 off end # AC'97 Audio
- device pci 1e.3 off end # AC'97 Modem
- device pci 1f.0 on # PCI-LPC bridge
- subsystemid 0x17aa 0x2009
- chip ec/lenovo/pmh7
- device pnp ff.1 on # dummy
- end
-
- register "backlight_enable" = "0x01"
- register "dock_event_enable" = "0x01"
- end
- chip ec/lenovo/h8
- device pnp ff.2 on # dummy
- io 0x60 = 0x62
- io 0x62 = 0x66
- io 0x64 = 0x1600
- io 0x66 = 0x1604
- end
-
- register "config0" = "0xa6"
- register "config1" = "0x05"
- register "config2" = "0xa0"
- register "config3" = "0x01"
-
- register "beepmask0" = "0xfe"
- register "beepmask1" = "0x96"
- register "has_power_management_beeps" = "1"
-
- register "event2_enable" = "0xff"
- register "event3_enable" = "0xff"
- register "event4_enable" = "0xf4"
- register "event5_enable" = "0x3f"
- register "event6_enable" = "0x80"
- register "event7_enable" = "0x01"
- register "event8_enable" = "0x01"
- register "event9_enable" = "0xff"
- register "eventa_enable" = "0xff"
- register "eventb_enable" = "0xff"
- register "eventc_enable" = "0x3c"
- register "eventd_enable" = "0xff"
-
- end
- chip superio/nsc/pc87382
- device pnp 164e.2 on # IR
- io 0x60 = 0x2f8
- end
-
- device pnp 164e.3 off # Serial Port
- io 0x60 = 0x3f8
- end
-
- device pnp 164e.7 on # GPIO
- io 0x60 = 0x1680
- end
-
- device pnp 164e.19 on # DLPC
- io 0x60 = 0x164c
- end
- end
-
- chip superio/nsc/pc87384
- device pnp 2e.0 off #FDC
- end
-
- device pnp 2e.1 on # Parallel Port
- io 0x60 = 0x3bc
- irq 0x70 = 7
- end
-
- device pnp 2e.2 off # Serial Port / IR
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
-
- device pnp 2e.3 on # Serial Port
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
-
- device pnp 2e.7 on # GPIO
- io 0x60 = 0x1620
- end
-
- device pnp 2e.a off # WDT
- end
- end
- end
- device pci 1f.2 on # SATA
- subsystemid 0x17aa 0x200d
- end
- device pci 1f.3 on # SMBUS
- subsystemid 0x17aa 0x200f
- chip drivers/i2c/ck505
- register "mask" = "{ 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff }"
- # vendor clockgen setup
- register "regs" = "{ 0x6d, 0xff, 0xff,
- 0x20, 0x41, 0x7f, 0x18, 0x00 }"
- device i2c 69 on end
- end
- # eeprom, 8 virtual devices, same chip
- chip drivers/i2c/at24rf08c
- device i2c 54 on end
- device i2c 55 on end
- device i2c 56 on end
- device i2c 57 on end
- device i2c 5c on end
- device i2c 5d on end
- device i2c 5e on end
- device i2c 5f on end
- end
- end
- end
- end
-end
diff --git a/src/mainboard/lenovo/t60/variants/z61t/overridetree.cb b/src/mainboard/lenovo/t60/variants/z61t/overridetree.cb
new file mode 100644
index 0000000..d29df3b
--- /dev/null
+++ b/src/mainboard/lenovo/t60/variants/z61t/overridetree.cb
@@ -0,0 +1,64 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2009 coresystems GmbH
+## Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org>
+##
+## This program is free software; you can redistribute it and/or
+## modify it under the terms of the GNU General Public License as
+## published by the Free Software Foundation; version 2 of
+## the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+chip northbridge/intel/i945
+ device domain 0 on
+ device pci 00.0 on # Host bridge
+ subsystemid 0x17aa 0x2017
+ end
+ device pci 01.0 on # PEG
+ device pci 00.0 on end # VGA
+ end
+ chip southbridge/intel/i82801gx
+ device pci 1c.0 on # PCI Express Port 1
+ subsystemid 0x17aa 0x2011
+ end
+ device pci 1c.1 on # PCI Express Port 2
+ subsystemid 0x17aa 0x2011
+ end
+ device pci 1c.2 on # PCI Express Port 3
+ subsystemid 0x17aa 0x2011
+ end
+ device pci 1c.3 on # PCI Express Port 4
+ subsystemid 0x17aa 0x2011
+ end
+ device pci 1e.0 on # PCI Bridge
+ chip southbridge/ti/pci1x2x
+ device pci 00.0 on
+ subsystemid 0x17aa 0x2013
+ end
+ end
+ end
+ device pci 1f.0 on # PCI-LPC bridge
+ chip superio/nsc/pc87384
+ device pnp 2e.2 off # Serial Port / IR
+ irq 0x70 = 3
+ end
+ end
+ end
+ device pci 1f.3 on # SMBUS
+ chip drivers/i2c/ck505
+ register "mask" = "{ 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff }"
+ # vendor clockgen setup
+ register "regs" = "{ 0x6d, 0xff, 0xff,
+ 0x20, 0x41, 0x7f, 0x18, 0x00 }"
+ end
+ end
+ end
+ end
+end
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I13c0134b22e2203e6cee6ecafda0dae89e086aff
Gerrit-Change-Number: 34779
Gerrit-PatchSet: 1
Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com>
Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Peter Lemenkov <lemenkov(a)gmail.com>
Gerrit-MessageType: newchange
6 days, 16 hours
- 5
- 5
Change in ...coreboot[master]: configs: Build test experimental x86_64 code
by Patrick Rudolph (Code Review)
Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31472
Change subject: configs: Build test experimental x86_64 code
......................................................................
configs: Build test experimental x86_64 code
Add additional build config to test qemu-i440fx x86_64 code.
Change-Id: I63f7a6e1602728e4d5ff67f9bd702efebe315c16
Signed-off-by: Patrick Rudolph <siro(a)das-labor.org>
---
A configs/config.emulation_qemu_x86_i440fx_x86_64
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/31472/1
diff --git a/configs/config.emulation_qemu_x86_i440fx_x86_64 b/configs/config.emulation_qemu_x86_i440fx_x86_64
new file mode 100644
index 0000000..0ddb3f1
--- /dev/null
+++ b/configs/config.emulation_qemu_x86_i440fx_x86_64
@@ -0,0 +1 @@
+CONFIG_CPU_QEMU_X86_64=y
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I63f7a6e1602728e4d5ff67f9bd702efebe315c16
Gerrit-Change-Number: 31472
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-MessageType: newchange
6 days, 17 hours
- 3
- 5
Change in coreboot[master]: [TESTONLY] devicetree: Remove weak declarations for ops
by Kyösti Mälkki (Code Review)
Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35086 )
Change subject: [TESTONLY] devicetree: Remove weak declarations for ops
......................................................................
[TESTONLY] devicetree: Remove weak declarations for ops
Change-Id: Ifb783e2f733d5c65c615e5c1879e3e4c7a83e049
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M util/sconfig/main.c
1 file changed, 8 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/35086/1
diff --git a/util/sconfig/main.c b/util/sconfig/main.c
index 5e3a1d4..586de06 100644
--- a/util/sconfig/main.c
+++ b/util/sconfig/main.c
@@ -936,9 +936,14 @@
chip = tmp;
while (chip) {
- fprintf(fil,
- "__attribute__((weak)) struct chip_operations %s_ops = {};\n",
- chip->name_underscore);
+ if (strstr(chip->name_underscore, "cpu_") == chip->name_underscore) {
+ fprintf(fil,
+ "__attribute__((weak)) struct chip_operations %s_ops = {};\n",
+ chip->name_underscore);
+ } else {
+ fprintf(fil, "extern struct chip_operations %s_ops;\n",
+ chip->name_underscore);
+ }
chip = chip->next;
}
fprintf(fil, "#endif\n");
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ifb783e2f733d5c65c615e5c1879e3e4c7a83e049
Gerrit-Change-Number: 35086
Gerrit-PatchSet: 1
Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Gerrit-MessageType: newchange
6 days, 21 hours
- 9
- 25
Change in ...coreboot[master]: util/inteltool: Refactoring #2
by Felix Singer (Code Review)
Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31634
Change subject: util/inteltool: Refactoring #2
......................................................................
util/inteltool: Refactoring #2
Change-Id: Ie92a5af141a907251fc847d53c767984949d9312
Signed-off-by: Felix Singer <migy(a)darmstadt.ccc.de>
---
M util/inteltool/Makefile
M util/inteltool/gpio.h
A util/inteltool/gpio_test.c
A util/inteltool/gpio_test.h
4 files changed, 447 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/31634/1
diff --git a/util/inteltool/Makefile b/util/inteltool/Makefile
index d88063b..0097831 100644
--- a/util/inteltool/Makefile
+++ b/util/inteltool/Makefile
@@ -28,7 +28,7 @@
CPPFLAGS += -I$(top)/src/commonlib/include
OBJS = inteltool.o pcr.o cpu.o gpio.o gpio_groups.o rootcmplx.o powermgt.o \
- memory.o pcie.o amb.o ivy_memory.o spi.o gfx.o ahci.o \
+ memory.o pcie.o amb.o ivy_memory.o spi.o gfx.o ahci.o gpio_test.o \
OS_ARCH = $(shell uname)
ifeq ($(OS_ARCH), Darwin)
diff --git a/util/inteltool/gpio.h b/util/inteltool/gpio.h
index c89f393..161e9bb 100644
--- a/util/inteltool/gpio.h
+++ b/util/inteltool/gpio.h
@@ -17,6 +17,36 @@
#ifndef GPIO_H
#define GPIO_H
+
+// Describes a native function
+struct native_mode {
+ uint8_t mode;
+ char *name;
+};
+
+/*
+ * Describes a GPIO pad, which optionally can
+ * have one or more native functions and a default
+ * mode. If no default mode is set,
+ * default_mode to -1, else set it to the
+ * function number.
+ */
+struct gpio_pad {
+ const char *name;
+ uint8_t default_mode;
+ const struct native_mode *modes;
+ uint64_t default_config;
+ uint64_t config;
+};
+
+/*
+struct gpio_pad {
+ const char *name;
+ size_t defaultMode;
+ const char **functions;
+};
+*/
+
struct gpio_group {
const char *display;
size_t pad_count;
diff --git a/util/inteltool/gpio_test.c b/util/inteltool/gpio_test.c
new file mode 100644
index 0000000..9052623
--- /dev/null
+++ b/util/inteltool/gpio_test.c
@@ -0,0 +1,66 @@
+/*
+ * inteltool - dump all registers on an Intel CPU + chipset based system.
+ *
+ * Copyright (C) 2017 secunet Security Networks AG
+ * Copyright (C) 2019 Felix Singer <migy(a)darmstadt.ccc.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <stddef.h>
+#include <stdint.h>
+#include <assert.h>
+#include <inttypes.h>
+#include "inteltool.h"
+#include "pcr.h"
+#include "gpio.h"
+#include "gpio_test.h"
+
+#define SBBAR_SIZE (16 * MiB)
+#define PCR_PORT_SIZE (64 * KiB)
+
+void select_gpio_community(struct pci_dev *const sb)
+{
+ size_t community_count;
+ const struct gpio_community *const *communities;
+
+ switch (sb->device_id) {
+ case PCI_DEVICE_ID_INTEL_B150:
+ case PCI_DEVICE_ID_INTEL_CM236:
+// community_count = ARRAY_SIZE(sunrise_communities);
+// communities = sunrise_communities;
+// pcr_init(sb);
+ break;
+ case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE:
+ case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM:
+ case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM:
+ case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE:
+ case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM:
+ case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM:
+// community_count = ARRAY_SIZE(sunrise_lp_communities);
+// communities = sunrise_lp_communities;
+// pcr_init(sb);
+ break;
+ case PCI_DEVICE_ID_INTEL_DNV_LPC:
+// community_count = ARRAY_SIZE(denverton_communities);
+// communities = denverton_communities;
+// pcr_init(sb);
+ break;
+ default:
+ return;
+ }
+
+ printf("\n============= GPIOS =============\n\n");
+
+// for (; community_count; --community_count)
+// print_gpio_community(*communities++);
+}
diff --git a/util/inteltool/gpio_test.h b/util/inteltool/gpio_test.h
new file mode 100644
index 0000000..9edc4fe
--- /dev/null
+++ b/util/inteltool/gpio_test.h
@@ -0,0 +1,350 @@
+/*
+ * inteltool - dump all registers on an Intel CPU + chipset based system.
+ *
+ * Copyright (C) 2017 secunet Security Networks AG
+ * Copyright (C) 2019 Felix Singer <migy(a)darmstadt.ccc.de>
+ * Copyright (C) 2019 by 9elements Agency GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "gpio.h"
+
+#ifndef GPIO_TEST_H
+#define GPIO_TEST_H
+
+/*
+const struct gpio_pad test[] = {
+ { "gpio1", 2, (const char *[]) { "function1", "function2", NULL, } },
+};
+*/
+
+const struct gpio_pad test[] = {
+ { "GPP_A0", -1, (const struct native_mode[]) { {1, "RCIN#" }, }, },
+ { "GPP_A1", -1, (const struct native_mode[]) { {1, "LAD0" }, {3, "ESPI_IO0" }, }, },
+ { "GPP_A2", -1, (const struct native_mode[]) { {1, "LAD1" }, {3, "ESPI_IO1" }, }, },
+ { "GPP_A3", -1, (const struct native_mode[]) { {1, "LAD2" }, {3, "ESPI_IO2" }, }, },
+ { "GPP_A4", -1, (const struct native_mode[]) { {1, "LAD3" }, {3, "ESPI_IO3" }, }, },
+ { "GPP_A5", -1, (const struct native_mode[]) { {1, "LFRAME#" }, {3, "ESPI_CS#" }, }, },
+ { "GPP_A6", -1, (const struct native_mode[]) { {1, "SERIRQ#" }, }, },
+ { "GPP_A7", -1, (const struct native_mode[]) { {1, "PIRQA#" }, }, },
+ { "GPP_A8", -1, (const struct native_mode[]) { {1, "CLKRUN#" }, }, },
+ { "GPP_A9", -1, (const struct native_mode[]) { {1, "CLKOUT_LPC0" }, {3, "ESPI_CLK" }, }, },
+ { "GPP_A10", -1, (const struct native_mode[]) { {1, "CLKOUT_LPC1" }, }, },
+ { "GPP_A11", -1, (const struct native_mode[]) { {1, "PME#" }, }, },
+ { "GPP_A12", -1, (const struct native_mode[]) { {1, "BM_BUSY#" }, {2, "ISH_GP6" }, {3, "SX_EXIT_HOLDOFF#" }, }, },
+ { "GPP_A13", -1, (const struct native_mode[]) { {1, "SUSWARN#/SUSPWRDNACK" }, }, },
+ { "GPP_A14", -1, (const struct native_mode[]) { {1, "SUS_STAT#" }, {3, "ESPI_RESET#" }, }, },
+ { "GPP_A15", -1, (const struct native_mode[]) { {1, "SUS_ACK#" }, }, },
+ { "GPP_A16", -1, (const struct native_mode[]) { {1, "SD_1P8_SEL" }, }, },
+ { "GPP_A17", -1, (const struct native_mode[]) { {1, "SD_PWR_EN#" }, {2, "ISH_GP7" }, }, },
+ { "GPP_A18", -1, (const struct native_mode[]) { {1, "ISH_GP0" }, }, },
+ { "GPP_A19", -1, (const struct native_mode[]) { {1, "ISH_GP1" }, }, },
+ { "GPP_A20", -1, (const struct native_mode[]) { {1, "ISH_GP2" }, }, },
+ { "GPP_A21", -1, (const struct native_mode[]) { {1, "ISH_GP3" }, }, },
+ { "GPP_A22", -1, (const struct native_mode[]) { {1, "ISH_GP4" }, }, },
+ { "GPP_A23", -1, (const struct native_mode[]) { {1, "ISH_GP5" }, }, },
+};
+
+/*
+const char *const sunrise_lp_group_a_names[] = {
+ "GPP_A0", "RCIN#", "n/a", "n/a",
+ "GPP_A1", "LAD0", "n/a", "ESPI_IO0",
+ "GPP_A2", "LAD1", "n/a", "ESPI_IO1",
+ "GPP_A3", "LAD2", "n/a", "ESPI_IO2",
+ "GPP_A4", "LAD3", "n/a", "ESPI_IO3",
+ "GPP_A5", "LFRAME#", "n/a", "ESPI_CS#",
+ "GPP_A6", "SERIRQ", "n/a", "n/a",
+ "GPP_A7", "PIRQA#", "n/a", "n/a",
+ "GPP_A8", "CLKRUN#", "n/a", "n/a",
+ "GPP_A9", "CLKOUT_LPC0", "n/a", "ESPI_CLK",
+ "GPP_A10", "CLKOUT_LPC1", "n/a", "n/a",
+ "GPP_A11", "PME#", "n/a", "n/a",
+ "GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#",
+ "GPP_A13", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a",
+ "GPP_A14", "SUS_STAT#", "n/a", "ESPI_RESET#",
+ "GPP_A15", "SUS_ACK#", "n/a", "n/a",
+ "GPP_A16", "SD_1P8_SEL", "n/a", "n/a",
+ "GPP_A17", "SD_PWR_EN#", "ISH_GP7", "n/a",
+ "GPP_A18", "ISH_GP0", "n/a", "n/a",
+ "GPP_A19", "ISH_GP1", "n/a", "n/a",
+ "GPP_A20", "ISH_GP2", "n/a", "n/a",
+ "GPP_A21", "ISH_GP3", "n/a", "n/a",
+ "GPP_A22", "ISH_GP4", "n/a", "n/a",
+ "GPP_A23", "ISH_GP5", "n/a", "n/a",
+};
+
+const struct gpio_group sunrise_lp_group_a = {
+ .display = "------- GPIO group GPP_A -------",
+ .pad_count = ARRAY_SIZE(sunrise_lp_group_a_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_lp_group_a_names,
+};
+
+const char *const sunrise_lp_group_b_names[] = {
+ "GPP_B0", "CORE_VID0", "n/a", "n/a",
+ "GPP_B1", "CORE_VID1", "n/a", "n/a",
+ "GPP_B2", "VRALERT#", "n/a", "n/a",
+ "GPP_B3", "CPU_GP2", "n/a", "n/a",
+ "GPP_B4", "CPU_GP3", "n/a", "n/a",
+ "GPP_B5", "SRCCLKREQ0#", "n/a", "n/a",
+ "GPP_B6", "SRCCLKREQ1#", "n/a", "n/a",
+ "GPP_B7", "SRCCLKREQ2#", "n/a", "n/a",
+ "GPP_B8", "SRCCLKREQ3#", "n/a", "n/a",
+ "GPP_B9", "SRCCLKREQ4#", "n/a", "n/a",
+ "GPP_B10", "SRCCLKREQ5#", "n/a", "n/a",
+ "GPP_B11", "EXT_PWR_GATE#", "n/a", "n/a",
+ "GPP_B12", "SLP_S0#", "n/a", "n/a",
+ "GPP_B13", "PLTRST#", "n/a", "n/a",
+ "GPP_B14", "SPKR", "n/a", "n/a",
+ "GPP_B15", "GSPI0_CS#", "n/a", "n/a",
+ "GPP_B16", "GSPI0_CLK", "n/a", "n/a",
+ "GPP_B17", "GSPI0_MISO", "n/a", "n/a",
+ "GPP_B18", "GSPI0_MOSI", "n/a", "n/a",
+ "GPP_B19", "GSPI1_CS#", "n/a", "n/a",
+ "GPP_B20", "GSPI1_CLK", "n/a", "n/a",
+ "GPP_B21", "GSPI1_MISO", "n/a", "n/a",
+ "GPP_B22", "GSPI1_MOSI", "n/a", "n/a",
+ "GPP_B23", "SML1ALERT#", "PCHHOT#", "n/a",
+};
+
+const struct gpio_group sunrise_lp_group_b = {
+ .display = "------- GPIO Group GPP_B -------",
+ .pad_count = ARRAY_SIZE(sunrise_lp_group_b_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_lp_group_b_names,
+};
+
+const struct gpio_group *const sunrise_lp_community_ab_groups[] = {
+ &sunrise_lp_group_a, &sunrise_lp_group_b,
+};
+
+const struct gpio_community sunrise_lp_community_ab = {
+ .name = "------- GPIO Community 0 -------",
+ .pcr_port_id = 0xaf,
+ .group_count = ARRAY_SIZE(sunrise_lp_community_ab_groups),
+ .groups = sunrise_lp_community_ab_groups,
+};
+
+const char *const sunrise_group_c_names[] = {
+ "GPP_C0", "SMBCLK", "n/a", "n/a",
+ "GPP_C1", "SMBDATA", "n/a", "n/a",
+ "GPP_C2", "SMBALERT#", "n/a", "n/a",
+ "GPP_C3", "SML0CLK", "n/a", "n/a",
+ "GPP_C4", "SML0DATA", "n/a", "n/a",
+ "GPP_C5", "SML0ALERT#", "n/a", "n/a",
+ "GPP_C6", "SML1CLK", "n/a", "n/a",
+ "GPP_C7", "SML1DATA", "n/a", "n/a",
+ "GPP_C8", "UART0_RXD", "n/a", "n/a",
+ "GPP_C9", "UART0_TXD", "n/a", "n/a",
+ "GPP_C10", "UART0_RTS#", "n/a", "n/a",
+ "GPP_C11", "UART0_CTS#", "n/a", "n/a",
+ "GPP_C12", "UART1_RXD", "ISH_UART1_RXD", "n/a",
+ "GPP_C13", "UART1_TXD", "ISH_UART1_TXD", "n/a",
+ "GPP_C14", "UART1_RTS#", "ISH_UART1_RTS#", "n/a",
+ "GPP_C15", "UART1_CTS#", "ISH_UART1_CTS#", "n/a",
+ "GPP_C16", "I2C0_SDA", "n/a", "n/a",
+ "GPP_C17", "I2C0_SCL", "n/a", "n/a",
+ "GPP_C18", "I2C1_SDA", "n/a", "n/a",
+ "GPP_C19", "I2C1_SCL", "n/a", "n/a",
+ "GPP_C20", "UART2_RXD", "n/a", "n/a",
+ "GPP_C21", "UART2_TXD", "n/a", "n/a",
+ "GPP_C22", "UART2_RTS#", "n/a", "n/a",
+ "GPP_C23", "UART2_CTS#", "n/a", "n/a",
+};
+
+const struct gpio_group sunrise_group_c = {
+ .display = "------- GPIO Group GPP_C -------",
+ .pad_count = ARRAY_SIZE(sunrise_group_c_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_group_c_names,
+};
+
+const char *const sunrise_lp_group_d_names[] = {
+ "GPP_D0", "SPI1_CS#", "n/a", "n/a",
+ "GPP_D1", "SPI1_CLK", "n/a", "n/a",
+ "GPP_D2", "SPI1_MISO", "n/a", "n/a",
+ "GPP_D3", "SPI1_MOSI", "n/a", "n/a",
+ "GPP_D4", "FLASHTRIG", "n/a", "n/a",
+ "GPP_D5", "ISH_I2C0_SDA", "n/a", "n/a",
+ "GPP_D6", "ISH_I2C0_SCL", "n/a", "n/a",
+ "GPP_D7", "ISH_I2C1_SDA", "n/a", "n/a",
+ "GPP_D8", "ISH_I2C1_SCL", "n/a", "n/a",
+ "GPP_D9", "n/a", "n/a", "n/a",
+ "GPP_D10", "n/a", "n/a", "n/a",
+ "GPP_D11", "n/a", "n/a", "n/a",
+ "GPP_D12", "n/a", "n/a", "n/a",
+ "GPP_D13", "ISH_UART0_RXD", "n/a", "n/a",
+ "GPP_D14", "ISH_UART0_TXD", "n/a", "n/a",
+ "GPP_D15", "ISH_UART0_RTS#", "n/a", "n/a",
+ "GPP_D16", "ISH_UART0_CTS#", "n/a", "n/a",
+ "GPP_D17", "DMIC_CLK1", "n/a", "n/a",
+ "GPP_D18", "DMIC_DATA1", "n/a", "n/a",
+ "GPP_D19", "DMIC_CLK0", "n/a", "n/a",
+ "GPP_D20", "DMIC_DATA0", "n/a", "n/a",
+ "GPP_D21", "SPI1_IO2", "n/a", "n/a",
+ "GPP_D22", "SPI1_IO3", "n/a", "n/a",
+ "GPP_D23", "I2S_MCLK", "n/a", "n/a",
+};
+
+const struct gpio_group sunrise_lp_group_d = {
+ .display = "------- GPIO Group GPP_D -------",
+ .pad_count = ARRAY_SIZE(sunrise_lp_group_d_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_lp_group_d_names,
+};
+
+const char *const sunrise_lp_group_e_names[] = {
+ "GPP_E0", "SATAXPCIE0", "SATAGP0", "n/a",
+ "GPP_E1", "SATAXPCIE1", "SATAGP1", "n/a",
+ "GPP_E2", "SATAXPCIE2", "SATAGP2", "n/a",
+ "GPP_E3", "CPU_GP0", "n/a", "n/a",
+ "GPP_E4", "SATA_DEVSLP0", "n/a", "n/a",
+ "GPP_E5", "SATA_DEVSLP1", "n/a", "n/a",
+ "GPP_E6", "SATA_DEVSLP2", "n/a", "n/a",
+ "GPP_E7", "CPU_GP1", "n/a", "n/a",
+ "GPP_E8", "SATALED#", "n/a", "n/a",
+ "GPP_E9", "USB2_OC0#", "n/a", "n/a",
+ "GPP_E10", "USB2_OC1#", "n/a", "n/a",
+ "GPP_E11", "USB2_OC2#", "n/a", "n/a",
+ "GPP_E12", "USB2_OC3#", "n/a", "n/a",
+ "GPP_E13", "DDPB_HPD0", "n/a", "n/a",
+ "GPP_E14", "DDPC_HPD1", "n/a", "n/a",
+ "GPP_E15", "DDPD_HPD2", "n/a", "n/a",
+ "GPP_E16", "DDPE_HPD3", "n/a", "n/a",
+ "GPP_E17", "EDP_HPD", "n/a", "n/a",
+ "GPP_E18", "DDPB_CTRLCLK", "n/a", "n/a",
+ "GPP_E19", "DDPB_CTRLDATA", "n/a", "n/a",
+ "GPP_E20", "DDPC_CTRLCLK", "n/a", "n/a",
+ "GPP_E21", "DDPC_CTRLDATA", "n/a", "n/a",
+ "GPP_E22", "n/a", "n/a", "n/a",
+ "GPP_E23", "n/a", "n/a", "n/a",
+};
+
+const struct gpio_group sunrise_lp_group_e = {
+ .display = "------- GPIO Group GPP_E -------",
+ .pad_count = ARRAY_SIZE(sunrise_lp_group_e_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_lp_group_e_names,
+};
+
+const char *const sunrise_lp_group_f_names[] = {
+ "GPP_F0", "I2S2_SCLK", "n/a", "n/a",
+ "GPP_F1", "I2S2_SFRM", "n/a", "n/a",
+ "GPP_F2", "I2S2_TXD", "n/a", "n/a",
+ "GPP_F3", "I2S2_RXD", "n/a", "n/a",
+ "GPP_F4", "I2C2_SDA", "n/a", "n/a",
+ "GPP_F5", "I2C2_SCL", "n/a", "n/a",
+ "GPP_F6", "I2C3_SDA", "n/a", "n/a",
+ "GPP_F7", "I2C3_SCL", "n/a", "n/a",
+ "GPP_F8", "I2C4_SDA", "n/a", "n/a",
+ "GPP_F9", "I2C4_SCL", "n/a", "n/a",
+ "GPP_F10", "I2C5_SDA", "ISH_I2C2_SDA", "n/a",
+ "GPP_F11", "I2C5_SCL", "ISH_I2C2_SCL", "n/a",
+ "GPP_F12", "EMMC_CMD", "n/a", "n/a",
+ "GPP_F13", "EMMC_DATA0", "n/a", "n/a",
+ "GPP_F14", "EMMC_DATA1", "n/a", "n/a",
+ "GPP_F15", "EMMC_DATA2", "n/a", "n/a",
+ "GPP_F16", "EMMC_DATA3", "n/a", "n/a",
+ "GPP_F17", "EMMC_DATA4", "n/a", "n/a",
+ "GPP_F18", "EMMC_DATA5", "n/a", "n/a",
+ "GPP_F19", "EMMC_DATA6", "n/a", "n/a",
+ "GPP_F20", "EMMC_DATA7", "n/a", "n/a",
+ "GPP_F21", "EMMC_RCLK", "n/a", "n/a",
+ "GPP_F22", "EMMC_CLK", "n/a", "n/a",
+ "GPP_F23", "n/a", "n/a", "n/a",
+};
+
+const struct gpio_group sunrise_lp_group_f = {
+ .display = "------- GPIO Group GPP_F -------",
+ .pad_count = ARRAY_SIZE(sunrise_lp_group_f_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_lp_group_f_names,
+};
+
+const char *const sunrise_lp_group_g_names[] = {
+ "GPP_G0", "SD_CMD", "n/a", "n/a",
+ "GPP_G1", "SD_DATA0", "n/a", "n/a",
+ "GPP_G2", "SD_DATA1", "n/a", "n/a",
+ "GPP_G3", "SD_DATA2", "n/a", "n/a",
+ "GPP_G4", "SD_DATA3", "n/a", "n/a",
+ "GPP_G5", "SD_CD#", "n/a", "n/a",
+ "GPP_G6", "SD_CLK", "n/a", "n/a",
+ "GPP_G7", "SD_WP", "n/a", "n/a",
+};
+
+const struct gpio_group sunrise_lp_group_g = {
+ .display = "------- GPIO Group GPP_G -------",
+ .pad_count = ARRAY_SIZE(sunrise_lp_group_g_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_lp_group_g_names,
+};
+
+const struct gpio_group *const sunrise_lp_community_cde_groups[] = {
+ &sunrise_group_c, &sunrise_lp_group_d, &sunrise_lp_group_e,
+};
+
+const struct gpio_community sunrise_lp_community_cde = {
+ .name = "------- GPIO Community 1 -------",
+ .pcr_port_id = 0xae,
+ .group_count = ARRAY_SIZE(sunrise_lp_community_cde_groups),
+ .groups = sunrise_lp_community_cde_groups,
+};
+
+const char *const sunrise_group_gpd_names[] = {
+ "GPD0", "BATLOW#", "n/a", "n/a",
+ "GPD1", "ACPRESENT", "n/a", "n/a",
+ "GPD2", "LAN_WAKE#", "n/a", "n/a",
+ "GPD3", "PWRBTN#", "n/a", "n/a",
+ "GPD4", "SLP_S3#", "n/a", "n/a",
+ "GPD5", "SLP_S4#", "n/a", "n/a",
+ "GPD6", "SLP_A#", "n/a", "n/a",
+ "GPD7", "RESERVED", "n/a", "n/a",
+ "GPD8", "SUSCLK", "n/a", "n/a",
+ "GPD9", "SLP_WLAN#", "n/a", "n/a",
+ "GPD10", "SLP_S5#", "n/a", "n/a",
+ "GPD11", "LANPHYPC", "n/a", "n/a",
+};
+
+const struct gpio_group sunrise_group_gpd = {
+ .display = "-------- GPIO Group GPD --------",
+ .pad_count = ARRAY_SIZE(sunrise_group_gpd_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_group_gpd_names,
+};
+
+const struct gpio_group *const sunrise_community_gpd_groups[] = {
+ &sunrise_group_gpd,
+};
+
+const struct gpio_community sunrise_community_gpd = {
+ .name = "------- GPIO Community 2 -------",
+ .pcr_port_id = 0xad,
+ .group_count = ARRAY_SIZE(sunrise_community_gpd_groups),
+ .groups = sunrise_community_gpd_groups,
+};
+
+const struct gpio_group *const sunrise_lp_community_fg_groups[] = {
+ &sunrise_lp_group_f, &sunrise_lp_group_g,
+};
+
+const struct gpio_community sunrise_lp_community_fg = {
+ .name = "------- GPIO Community 3 -------",
+ .pcr_port_id = 0xac,
+ .group_count = ARRAY_SIZE(sunrise_lp_community_fg_groups),
+ .groups = sunrise_lp_community_fg_groups,
+};
+
+const struct gpio_community *const sunrise_lp_communities[] = {
+ &sunrise_lp_community_ab, &sunrise_lp_community_cde,
+ &sunrise_community_gpd, &sunrise_lp_community_fg,
+};
+*/
+#endif
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ie92a5af141a907251fc847d53c767984949d9312
Gerrit-Change-Number: 31634
Gerrit-PatchSet: 1
Gerrit-Owner: Felix Singer <migy(a)darmstadt.ccc.de>
Gerrit-MessageType: newchange
1 week, 1 day
- 3
- 10
Change in ...coreboot[master]: util/inteltool: Refactor code of GPIO groups
by Felix Singer (Code Review)
Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31504
Change subject: util/inteltool: Refactor code of GPIO groups
......................................................................
util/inteltool: Refactor code of GPIO groups
Change-Id: Ic61871f5cf95ac3da93892fa2f7721e682176c8d
Signed-off-by: Felix Singer <migy(a)darmstadt.ccc.de>
---
A util/inteltool/gpio.h
A util/inteltool/gpio_denverton.h
M util/inteltool/gpio_groups.c
A util/inteltool/gpio_sunrise.h
4 files changed, 865 insertions(+), 816 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/31504/1
diff --git a/util/inteltool/gpio.h b/util/inteltool/gpio.h
new file mode 100644
index 0000000..64f62f8
--- /dev/null
+++ b/util/inteltool/gpio.h
@@ -0,0 +1,29 @@
+/*
+ * inteltool - dump all registers on an Intel CPU + chipset based system.
+ *
+ * Copyright (C) 2017 secunet Security Networks AG
+ * Copyright (C) 2019 Felix Singer <migy(a)darmstadt.ccc.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+struct gpio_group {
+ const char *display;
+ size_t pad_count;
+ size_t func_count;
+ const char *const *pad_names; /* indexed by 'pad * func_count + func' */
+};
+
+struct gpio_community {
+ const char *name;
+ uint8_t pcr_port_id;
+ size_t group_count;
+ const struct gpio_group *const *groups;
+};
diff --git a/util/inteltool/gpio_denverton.h b/util/inteltool/gpio_denverton.h
new file mode 100644
index 0000000..e745b44
--- /dev/null
+++ b/util/inteltool/gpio_denverton.h
@@ -0,0 +1,237 @@
+/*
+ * inteltool - dump all registers on an Intel CPU + chipset based system.
+ *
+ * Copyright (C) 2017 secunet Security Networks AG
+ * Copyright (C) 2019 Felix Singer <migy(a)darmstadt.ccc.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+static const char *const denverton_group_north_all_names[] = {
+ "NORTH_ALL_GBE0_SDP0",
+ "NORTH_ALL_GBE1_SDP0",
+ "NORTH_ALL_GBE0_SDP1",
+ "NORTH_ALL_GBE1_SDP1",
+ "NORTH_ALL_GBE0_SDP2",
+ "NORTH_ALL_GBE1_SDP2",
+ "NORTH_ALL_GBE0_SDP3",
+ "NORTH_ALL_GBE1_SDP3",
+ "NORTH_ALL_GBE2_LED0",
+ "NORTH_ALL_GBE2_LED1",
+ "NORTH_ALL_GBE0_I2C_CLK",
+ "NORTH_ALL_GBE0_I2C_DATA",
+ "NORTH_ALL_GBE1_I2C_CLK",
+ "NORTH_ALL_GBE1_I2C_DATA",
+ "NORTH_ALL_NCSI_RXD0",
+ "NORTH_ALL_NCSI_CLK_IN",
+ "NORTH_ALL_NCSI_RXD1",
+ "NORTH_ALL_NCSI_CRS_DV",
+ "NORTH_ALL_NCSI_ARB_IN",
+ "NORTH_ALL_NCSI_TX_EN",
+ "NORTH_ALL_NCSI_TXD0",
+ "NORTH_ALL_NCSI_TXD1",
+ "NORTH_ALL_NCSI_ARB_OUT",
+ "NORTH_ALL_GBE0_LED0",
+ "NORTH_ALL_GBE0_LED1",
+ "NORTH_ALL_GBE1_LED0",
+ "NORTH_ALL_GBE1_LED1",
+ "NORTH_ALL_GPIO_0",
+ "NORTH_ALL_PCIE_CLKREQ0_N",
+ "NORTH_ALL_PCIE_CLKREQ1_N",
+ "NORTH_ALL_PCIE_CLKREQ2_N",
+ "NORTH_ALL_PCIE_CLKREQ3_N",
+ "NORTH_ALL_PCIE_CLKREQ4_N",
+ "NORTH_ALL_GPIO_1",
+ "NORTH_ALL_GPIO_2",
+ "NORTH_ALL_SVID_ALERT_N",
+ "NORTH_ALL_SVID_DATA",
+ "NORTH_ALL_SVID_CLK",
+ "NORTH_ALL_THERMTRIP_N",
+ "NORTH_ALL_PROCHOT_N",
+ "NORTH_ALL_MEMHOT_N",
+};
+
+static const struct gpio_group denverton_group_north_all = {
+ .display = "------- GPIO Group North All -------",
+ .pad_count = ARRAY_SIZE(denverton_group_north_all_names) / 1,
+ .func_count = 1,
+ .pad_names = denverton_group_north_all_names,
+};
+
+static const struct gpio_group *const denverton_community_north_groups[] = {
+ &denverton_group_north_all,
+};
+
+static const struct gpio_community denverton_community_north = {
+ .name = "------- GPIO Community 0 -------",
+ .pcr_port_id = 0xc2,
+ .group_count = ARRAY_SIZE(denverton_community_north_groups),
+ .groups = denverton_community_north_groups,
+};
+
+static const char *const denverton_group_south_dfx_names[] = {
+ "SOUTH_DFX_DFX_PORT_CLK0",
+ "SOUTH_DFX_DFX_PORT_CLK1",
+ "SOUTH_DFX_DFX_PORT0",
+ "SOUTH_DFX_DFX_PORT1",
+ "SOUTH_DFX_DFX_PORT2",
+ "SOUTH_DFX_DFX_PORT3",
+ "SOUTH_DFX_DFX_PORT4",
+ "SOUTH_DFX_DFX_PORT5",
+ "SOUTH_DFX_DFX_PORT6",
+ "SOUTH_DFX_DFX_PORT7",
+ "SOUTH_DFX_DFX_PORT8",
+ "SOUTH_DFX_DFX_PORT9",
+ "SOUTH_DFX_DFX_PORT10",
+ "SOUTH_DFX_DFX_PORT11",
+ "SOUTH_DFX_DFX_PORT12",
+ "SOUTH_DFX_DFX_PORT13",
+ "SOUTH_DFX_DFX_PORT14",
+ "SOUTH_DFX_DFX_PORT15",
+};
+
+static const struct gpio_group denverton_group_south_dfx = {
+ .display = "------- GPIO Group South DFX -------",
+ .pad_count = ARRAY_SIZE(denverton_group_south_dfx_names) / 1,
+ .func_count = 1,
+ .pad_names = denverton_group_south_dfx_names,
+};
+
+static const char *const denverton_group_south_group0_names[] = {
+ "SOUTH_GROUP0_GPIO_12",
+ "SOUTH_GROUP0_SMB5_GBE_ALRT_N",
+ "SOUTH_GROUP0_PCIE_CLKREQ5_N",
+ "SOUTH_GROUP0_PCIE_CLKREQ6_N",
+ "SOUTH_GROUP0_PCIE_CLKREQ7_N",
+ "SOUTH_GROUP0_UART0_RXD",
+ "SOUTH_GROUP0_UART0_TXD",
+ "SOUTH_GROUP0_SMB5_GBE_CLK",
+ "SOUTH_GROUP0_SMB5_GBE_DATA",
+ "SOUTH_GROUP0_ERROR2_N",
+ "SOUTH_GROUP0_ERROR1_N",
+ "SOUTH_GROUP0_ERROR0_N",
+ "SOUTH_GROUP0_IERR_N",
+ "SOUTH_GROUP0_MCERR_N",
+ "SOUTH_GROUP0_SMB0_LEG_CLK",
+ "SOUTH_GROUP0_SMB0_LEG_DATA",
+ "SOUTH_GROUP0_SMB0_LEG_ALRT_N",
+ "SOUTH_GROUP0_SMB1_HOST_DATA",
+ "SOUTH_GROUP0_SMB1_HOST_CLK",
+ "SOUTH_GROUP0_SMB2_PECI_DATA",
+ "SOUTH_GROUP0_SMB2_PECI_CLK",
+ "SOUTH_GROUP0_SMB4_CSME0_DATA",
+ "SOUTH_GROUP0_SMB4_CSME0_CLK",
+ "SOUTH_GROUP0_SMB4_CSME0_ALRT_N",
+ "SOUTH_GROUP0_USB_OC0_N",
+ "SOUTH_GROUP0_FLEX_CLK_SE0",
+ "SOUTH_GROUP0_FLEX_CLK_SE1",
+ "SOUTH_GROUP0_GPIO_4",
+ "SOUTH_GROUP0_GPIO_5",
+ "SOUTH_GROUP0_GPIO_6",
+ "SOUTH_GROUP0_GPIO_7",
+ "SOUTH_GROUP0_SATA0_LED_N",
+ "SOUTH_GROUP0_SATA1_LED_N",
+ "SOUTH_GROUP0_SATA_PDETECT0",
+ "SOUTH_GROUP0_SATA_PDETECT1",
+ "SOUTH_GROUP0_SATA0_SDOUT",
+ "SOUTH_GROUP0_SATA1_SDOUT",
+ "SOUTH_GROUP0_UART1_RXD",
+ "SOUTH_GROUP0_UART1_TXD",
+ "SOUTH_GROUP0_GPIO_8",
+ "SOUTH_GROUP0_GPIO_9",
+ "SOUTH_GROUP0_TCK",
+ "SOUTH_GROUP0_TRST_N",
+ "SOUTH_GROUP0_TMS",
+ "SOUTH_GROUP0_TDI",
+ "SOUTH_GROUP0_TDO",
+ "SOUTH_GROUP0_CX_PRDY_N",
+ "SOUTH_GROUP0_CX_PREQ_N",
+ "SOUTH_GROUP0_CTBTRIGINOUT",
+ "SOUTH_GROUP0_CTBTRIGOUT",
+ "SOUTH_GROUP0_DFX_SPARE2",
+ "SOUTH_GROUP0_DFX_SPARE3",
+ "SOUTH_GROUP0_DFX_SPARE4",
+};
+
+static const struct gpio_group denverton_group_south_group0 = {
+ .display = "------- GPIO Group South Group0 -------",
+ .pad_count = ARRAY_SIZE(denverton_group_south_group0_names) / 1,
+ .func_count = 1,
+ .pad_names = denverton_group_south_group0_names,
+};
+
+static const char *const denverton_group_south_group1_names[] = {
+ "SOUTH_GROUP1_SUSPWRDNACK",
+ "SOUTH_GROUP1_PMU_SUSCLK",
+ "SOUTH_GROUP1_ADR_TRIGGER",
+ "SOUTH_GROUP1_PMU_SLP_S45_N",
+ "SOUTH_GROUP1_PMU_SLP_S3_N",
+ "SOUTH_GROUP1_PMU_WAKE_N",
+ "SOUTH_GROUP1_PMU_PWRBTN_N",
+ "SOUTH_GROUP1_PMU_RESETBUTTON_N",
+ "SOUTH_GROUP1_PMU_PLTRST_N",
+ "SOUTH_GROUP1_SUS_STAT_N",
+ "SOUTH_GROUP1_SLP_S0IX_N",
+ "SOUTH_GROUP1_SPI_CS0_N",
+ "SOUTH_GROUP1_SPI_CS1_N",
+ "SOUTH_GROUP1_SPI_MOSI_IO0",
+ "SOUTH_GROUP1_SPI_MISO_IO1",
+ "SOUTH_GROUP1_SPI_IO2",
+ "SOUTH_GROUP1_SPI_IO3",
+ "SOUTH_GROUP1_SPI_CLK",
+ "SOUTH_GROUP1_SPI_CLK_LOOPBK",
+ "SOUTH_GROUP1_ESPI_IO0",
+ "SOUTH_GROUP1_ESPI_IO1",
+ "SOUTH_GROUP1_ESPI_IO2",
+ "SOUTH_GROUP1_ESPI_IO3",
+ "SOUTH_GROUP1_ESPI_CS0_N",
+ "SOUTH_GROUP1_ESPI_CLK",
+ "SOUTH_GROUP1_ESPI_RST_N",
+ "SOUTH_GROUP1_ESPI_ALRT0_N",
+ "SOUTH_GROUP1_GPIO_10",
+ "SOUTH_GROUP1_GPIO_11",
+ "SOUTH_GROUP1_ESPI_CLK_LOOPBK",
+ "SOUTH_GROUP1_EMMC_CMD",
+ "SOUTH_GROUP1_EMMC_STROBE",
+ "SOUTH_GROUP1_EMMC_CLK",
+ "SOUTH_GROUP1_EMMC_D0",
+ "SOUTH_GROUP1_EMMC_D1",
+ "SOUTH_GROUP1_EMMC_D2",
+ "SOUTH_GROUP1_EMMC_D3",
+ "SOUTH_GROUP1_EMMC_D4",
+ "SOUTH_GROUP1_EMMC_D5",
+ "SOUTH_GROUP1_EMMC_D6",
+ "SOUTH_GROUP1_EMMC_D7",
+ "SOUTH_GROUP1_GPIO_3",
+};
+
+static const struct gpio_group denverton_group_south_group1 = {
+ .display = "------- GPIO Group South Group1 -------",
+ .pad_count = ARRAY_SIZE(denverton_group_south_group1_names) / 1,
+ .func_count = 1,
+ .pad_names = denverton_group_south_group1_names,
+};
+
+static const struct gpio_group *const denverton_community_south_groups[] = {
+ &denverton_group_south_dfx,
+ &denverton_group_south_group0,
+ &denverton_group_south_group1,
+};
+
+static const struct gpio_community denverton_community_south = {
+ .name = "------- GPIO Community 1 -------",
+ .pcr_port_id = 0xc5,
+ .group_count = ARRAY_SIZE(denverton_community_south_groups),
+ .groups = denverton_community_south_groups,
+};
+
+static const struct gpio_community *const denverton_communities[] = {
+ &denverton_community_north, &denverton_community_south,
+};
diff --git a/util/inteltool/gpio_groups.c b/util/inteltool/gpio_groups.c
index 53a8eb9..c7ab186 100644
--- a/util/inteltool/gpio_groups.c
+++ b/util/inteltool/gpio_groups.c
@@ -2,6 +2,7 @@
* inteltool - dump all registers on an Intel CPU + chipset based system.
*
* Copyright (C) 2017 secunet Security Networks AG
+ * Copyright (C) 2019 Felix Singer <migy(a)darmstadt.ccc.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -21,826 +22,13 @@
#include <inttypes.h>
#include "inteltool.h"
#include "pcr.h"
+#include "gpio.h"
+#include "gpio_denverton.h"
+#include "gpio_sunrise.h"
#define SBBAR_SIZE (16 * MiB)
#define PCR_PORT_SIZE (64 * KiB)
-struct gpio_group {
- const char *display;
- size_t pad_count;
- size_t func_count;
- const char *const *pad_names; /* indexed by 'pad * func_count + func' */
-};
-
-struct gpio_community {
- const char *name;
- uint8_t pcr_port_id;
- size_t group_count;
- const struct gpio_group *const *groups;
-};
-
-static const char *const sunrise_group_a_names[] = {
- "GPP_A0", "RCIN#", "n/a", "ESPI_ALERT1#",
- "GPP_A1", "LAD0", "n/a", "ESPI_IO0",
- "GPP_A2", "LAD1", "n/a", "ESPI_IO1",
- "GPP_A3", "LAD2", "n/a", "ESPI_IO2",
- "GPP_A4", "LAD3", "n/a", "ESPI_IO3",
- "GPP_A5", "LFRAME#", "n/a", "ESPI_CS#",
- "GPP_A6", "SERIRQ", "n/a", "ESPI_CS1#",
- "GPP_A7", "PIRQA#", "n/a", "ESPI_ALERT0#",
- "GPP_A8", "CLKRUN#", "n/a", "n/a",
- "GPP_A9", "CLKOUT_LPC0", "n/a", "ESPI_CLK",
- "GPP_A10", "CLKOUT_LPC1", "n/a", "n/a",
- "GPP_A11", "PME#", "n/a", "n/a",
- "GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#",
- "GPP_A13", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a",
- "GPP_A14", "SUS_STAT#", "n/a", "ESPI_RESET#",
- "GPP_A15", "SUS_ACK#", "n/a", "n/a",
- "GPP_A16", "CLKOUT_48", "n/a", "n/a",
- "GPP_A17", "ISH_GP7", "n/a", "n/a",
- "GPP_A18", "ISH_GP0", "n/a", "n/a",
- "GPP_A19", "ISH_GP1", "n/a", "n/a",
- "GPP_A20", "ISH_GP2", "n/a", "n/a",
- "GPP_A21", "ISH_GP3", "n/a", "n/a",
- "GPP_A22", "ISH_GP4", "n/a", "n/a",
- "GPP_A23", "ISH_GP5", "n/a", "n/a",
-};
-
-static const struct gpio_group sunrise_group_a = {
- .display = "------- GPIO Group GPP_A -------",
- .pad_count = ARRAY_SIZE(sunrise_group_a_names) / 4,
- .func_count = 4,
- .pad_names = sunrise_group_a_names,
-};
-
-static const char *const sunrise_lp_group_a_names[] = {
- "GPP_A0", "RCIN#", "n/a", "n/a",
- "GPP_A1", "LAD0", "n/a", "ESPI_IO0",
- "GPP_A2", "LAD1", "n/a", "ESPI_IO1",
- "GPP_A3", "LAD2", "n/a", "ESPI_IO2",
- "GPP_A4", "LAD3", "n/a", "ESPI_IO3",
- "GPP_A5", "LFRAME#", "n/a", "ESPI_CS#",
- "GPP_A6", "SERIRQ", "n/a", "n/a",
- "GPP_A7", "PIRQA#", "n/a", "n/a",
- "GPP_A8", "CLKRUN#", "n/a", "n/a",
- "GPP_A9", "CLKOUT_LPC0", "n/a", "ESPI_CLK",
- "GPP_A10", "CLKOUT_LPC1", "n/a", "n/a",
- "GPP_A11", "PME#", "n/a", "n/a",
- "GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#",
- "GPP_A13", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a",
- "GPP_A14", "SUS_STAT#", "n/a", "ESPI_RESET#",
- "GPP_A15", "SUS_ACK#", "n/a", "n/a",
- "GPP_A16", "SD_1P8_SEL", "n/a", "n/a",
- "GPP_A17", "SD_PWR_EN#", "ISH_GP7", "n/a",
- "GPP_A18", "ISH_GP0", "n/a", "n/a",
- "GPP_A19", "ISH_GP1", "n/a", "n/a",
- "GPP_A20", "ISH_GP2", "n/a", "n/a",
- "GPP_A21", "ISH_GP3", "n/a", "n/a",
- "GPP_A22", "ISH_GP4", "n/a", "n/a",
- "GPP_A23", "ISH_GP5", "n/a", "n/a",
-};
-
-static const struct gpio_group sunrise_lp_group_a = {
- .display = "------- GPIO group GPP_A -------",
- .pad_count = ARRAY_SIZE(sunrise_lp_group_a_names) / 4,
- .func_count = 4,
- .pad_names = sunrise_lp_group_a_names,
-};
-
-static const char *const sunrise_group_b_names[] = {
- "GPP_B0", "n/a", "n/a", "n/a",
- "GPP_B1", "n/a", "n/a", "n/a",
- "GPP_B2", "VRALERT#", "n/a", "n/a",
- "GPP_B3", "CPU_GP2", "n/a", "n/a",
- "GPP_B4", "CPU_GP3", "n/a", "n/a",
- "GPP_B5", "SRCCLKREQ0#", "n/a", "n/a",
- "GPP_B6", "SRCCLKREQ1#", "n/a", "n/a",
- "GPP_B7", "SRCCLKREQ2#", "n/a", "n/a",
- "GPP_B8", "SRCCLKREQ3#", "n/a", "n/a",
- "GPP_B9", "SRCCLKREQ4#", "n/a", "n/a",
- "GPP_B10", "SRCCLKREQ5#", "n/a", "n/a",
- "GPP_B11", "n/a", "n/a", "n/a",
- "GPP_B12", "SLP_S0#", "n/a", "n/a",
- "GPP_B13", "PLTRST#", "n/a", "n/a",
- "GPP_B14", "SPKR", "n/a", "n/a",
- "GPP_B15", "GSPIO_CS#", "n/a", "n/a",
- "GPP_B16", "GSPIO_CLK", "n/a", "n/a",
- "GPP_B17", "GSPIO_MISO", "n/a", "n/a",
- "GPP_B18", "GSPIO_MOSI", "n/a", "n/a",
- "GPP_B19", "GSPI1_CS#", "n/a", "n/a",
- "GPP_B20", "GSPI1_CLK", "n/a", "n/a",
- "GPP_B21", "GSPI1_MISO", "n/a", "n/a",
- "GPP_B22", "GSPI1_MOSI", "n/a", "n/a",
- "GPP_B23", "SML1ALERT#", "PCHHOT#", "n/a",
-};
-
-static const struct gpio_group sunrise_group_b = {
- .display = "------- GPIO Group GPP_B -------",
- .pad_count = ARRAY_SIZE(sunrise_group_b_names) / 4,
- .func_count = 4,
- .pad_names = sunrise_group_b_names,
-};
-
-static const char *const sunrise_lp_group_b_names[] = {
- "GPP_B0", "CORE_VID0", "n/a", "n/a",
- "GPP_B1", "CORE_VID1", "n/a", "n/a",
- "GPP_B2", "VRALERT#", "n/a", "n/a",
- "GPP_B3", "CPU_GP2", "n/a", "n/a",
- "GPP_B4", "CPU_GP3", "n/a", "n/a",
- "GPP_B5", "SRCCLKREQ0#", "n/a", "n/a",
- "GPP_B6", "SRCCLKREQ1#", "n/a", "n/a",
- "GPP_B7", "SRCCLKREQ2#", "n/a", "n/a",
- "GPP_B8", "SRCCLKREQ3#", "n/a", "n/a",
- "GPP_B9", "SRCCLKREQ4#", "n/a", "n/a",
- "GPP_B10", "SRCCLKREQ5#", "n/a", "n/a",
- "GPP_B11", "EXT_PWR_GATE#", "n/a", "n/a",
- "GPP_B12", "SLP_S0#", "n/a", "n/a",
- "GPP_B13", "PLTRST#", "n/a", "n/a",
- "GPP_B14", "SPKR", "n/a", "n/a",
- "GPP_B15", "GSPI0_CS#", "n/a", "n/a",
- "GPP_B16", "GSPI0_CLK", "n/a", "n/a",
- "GPP_B17", "GSPI0_MISO", "n/a", "n/a",
- "GPP_B18", "GSPI0_MOSI", "n/a", "n/a",
- "GPP_B19", "GSPI1_CS#", "n/a", "n/a",
- "GPP_B20", "GSPI1_CLK", "n/a", "n/a",
- "GPP_B21", "GSPI1_MISO", "n/a", "n/a",
- "GPP_B22", "GSPI1_MOSI", "n/a", "n/a",
- "GPP_B23", "SML1ALERT#", "PCHHOT#", "n/a",
-};
-
-static const struct gpio_group sunrise_lp_group_b = {
- .display = "------- GPIO Group GPP_B -------",
- .pad_count = ARRAY_SIZE(sunrise_lp_group_b_names) / 4,
- .func_count = 4,
- .pad_names = sunrise_lp_group_b_names,
-};
-
-static const struct gpio_group *const sunrise_community_ab_groups[] = {
- &sunrise_group_a, &sunrise_group_b,
-};
-
-static const struct gpio_group *const sunrise_lp_community_ab_groups[] = {
- &sunrise_lp_group_a, &sunrise_lp_group_b,
-};
-
-static const struct gpio_community sunrise_community_ab = {
- .name = "------- GPIO Community 0 -------",
- .pcr_port_id = 0xaf,
- .group_count = ARRAY_SIZE(sunrise_community_ab_groups),
- .groups = sunrise_community_ab_groups,
-};
-
-static const struct gpio_community sunrise_lp_community_ab = {
- .name = "------- GPIO Community 0 -------",
- .pcr_port_id = 0xaf,
- .group_count = ARRAY_SIZE(sunrise_lp_community_ab_groups),
- .groups = sunrise_lp_community_ab_groups,
-};
-
-static const char *const sunrise_group_c_names[] = {
- "GPP_C0", "SMBCLK", "n/a", "n/a",
- "GPP_C1", "SMBDATA", "n/a", "n/a",
- "GPP_C2", "SMBALERT#", "n/a", "n/a",
- "GPP_C3", "SML0CLK", "n/a", "n/a",
- "GPP_C4", "SML0DATA", "n/a", "n/a",
- "GPP_C5", "SML0ALERT#", "n/a", "n/a",
- "GPP_C6", "SML1CLK", "n/a", "n/a",
- "GPP_C7", "SML1DATA", "n/a", "n/a",
- "GPP_C8", "UART0_RXD", "n/a", "n/a",
- "GPP_C9", "UART0_TXD", "n/a", "n/a",
- "GPP_C10", "UART0_RTS#", "n/a", "n/a",
- "GPP_C11", "UART0_CTS#", "n/a", "n/a",
- "GPP_C12", "UART1_RXD", "ISH_UART1_RXD", "n/a",
- "GPP_C13", "UART1_TXD", "ISH_UART1_TXD", "n/a",
- "GPP_C14", "UART1_RTS#", "ISH_UART1_RTS#", "n/a",
- "GPP_C15", "UART1_CTS#", "ISH_UART1_CTS#", "n/a",
- "GPP_C16", "I2C0_SDA", "n/a", "n/a",
- "GPP_C17", "I2C0_SCL", "n/a", "n/a",
- "GPP_C18", "I2C1_SDA", "n/a", "n/a",
- "GPP_C19", "I2C1_SCL", "n/a", "n/a",
- "GPP_C20", "UART2_RXD", "n/a", "n/a",
- "GPP_C21", "UART2_TXD", "n/a", "n/a",
- "GPP_C22", "UART2_RTS#", "n/a", "n/a",
- "GPP_C23", "UART2_CTS#", "n/a", "n/a",
-};
-
-static const struct gpio_group sunrise_group_c = {
- .display = "------- GPIO Group GPP_C -------",
- .pad_count = ARRAY_SIZE(sunrise_group_c_names) / 4,
- .func_count = 4,
- .pad_names = sunrise_group_c_names,
-};
-
-static const char *const sunrise_group_d_names[] = {
- "GPP_D0", "n/a", "n/a", "n/a",
- "GPP_D1", "n/a", "n/a", "n/a",
- "GPP_D2", "n/a", "n/a", "n/a",
- "GPP_D3", "n/a", "n/a", "n/a",
- "GPP_D4", "ISH_I2C2_SDA", "I2C3_SDA", "n/a",
- "GPP_D5", "I2S_SFRM", "n/a", "n/a",
- "GPP_D6", "I2S_TXD", "n/a", "n/a",
- "GPP_D7", "I2S_RXD", "n/a", "n/a",
- "GPP_D8", "I2S_SCLK", "n/a", "n/a",
- "GPP_D9", "n/a", "n/a", "n/a",
- "GPP_D10", "n/a", "n/a", "n/a",
- "GPP_D11", "n/a", "n/a", "n/a",
- "GPP_D12", "n/a", "n/a", "n/a",
- "GPP_D13", "ISH_UART0_RXD", "n/a", "I2C2_SDA",
- "GPP_D14", "ISH_UART0_TXD", "n/a", "I2C2_SCL",
- "GPP_D15", "ISH_UART0_RTS#", "n/a", "n/a",
- "GPP_D16", "ISH_UART0_CTS#", "n/a", "n/a",
- "GPP_D17", "DMIC_CLK1", "n/a", "n/a",
- "GPP_D18", "DMIC_DATA1", "n/a", "n/a",
- "GPP_D19", "DMIC_CLK0", "n/a", "n/a",
- "GPP_D20", "DMIC_DATA0", "n/a", "n/a",
- "GPP_D21", "n/a", "n/a", "n/a",
- "GPP_D22", "n/a", "n/a", "n/a",
- "GPP_D23", "ISH_I2C2_SCL", "I2C3_SCL", "n/a",
-};
-
-static const struct gpio_group sunrise_group_d = {
- .display = "------- GPIO Group GPP_D -------",
- .pad_count = ARRAY_SIZE(sunrise_group_d_names) / 4,
- .func_count = 4,
- .pad_names = sunrise_group_d_names,
-};
-
-static const char *const sunrise_lp_group_d_names[] = {
- "GPP_D0", "SPI1_CS#", "n/a", "n/a",
- "GPP_D1", "SPI1_CLK", "n/a", "n/a",
- "GPP_D2", "SPI1_MISO", "n/a", "n/a",
- "GPP_D3", "SPI1_MOSI", "n/a", "n/a",
- "GPP_D4", "FLASHTRIG", "n/a", "n/a",
- "GPP_D5", "ISH_I2C0_SDA", "n/a", "n/a",
- "GPP_D6", "ISH_I2C0_SCL", "n/a", "n/a",
- "GPP_D7", "ISH_I2C1_SDA", "n/a", "n/a",
- "GPP_D8", "ISH_I2C1_SCL", "n/a", "n/a",
- "GPP_D9", "n/a", "n/a", "n/a",
- "GPP_D10", "n/a", "n/a", "n/a",
- "GPP_D11", "n/a", "n/a", "n/a",
- "GPP_D12", "n/a", "n/a", "n/a",
- "GPP_D13", "ISH_UART0_RXD", "n/a", "n/a",
- "GPP_D14", "ISH_UART0_TXD", "n/a", "n/a",
- "GPP_D15", "ISH_UART0_RTS#", "n/a", "n/a",
- "GPP_D16", "ISH_UART0_CTS#", "n/a", "n/a",
- "GPP_D17", "DMIC_CLK1", "n/a", "n/a",
- "GPP_D18", "DMIC_DATA1", "n/a", "n/a",
- "GPP_D19", "DMIC_CLK0", "n/a", "n/a",
- "GPP_D20", "DMIC_DATA0", "n/a", "n/a",
- "GPP_D21", "SPI1_IO2", "n/a", "n/a",
- "GPP_D22", "SPI1_IO3", "n/a", "n/a",
- "GPP_D23", "I2S_MCLK", "n/a", "n/a",
-};
-
-static const struct gpio_group sunrise_lp_group_d = {
- .display = "------- GPIO Group GPP_D -------",
- .pad_count = ARRAY_SIZE(sunrise_lp_group_d_names) / 4,
- .func_count = 4,
- .pad_names = sunrise_lp_group_d_names,
-};
-
-static const char *const sunrise_group_e_names[] = {
- "GPP_E0", "SATAXPCIE0", "SATAGP0", "n/a",
- "GPP_E1", "SATAXPCIE1", "SATAGP1", "n/a",
- "GPP_E2", "SATAXPCIE2", "SATAGP2", "n/a",
- "GPP_E3", "CPU_GP0", "n/a", "n/a",
- "GPP_E4", "SATA_DEVSLP0", "n/a", "n/a",
- "GPP_E5", "SATA_DEVSLP1", "n/a", "n/a",
- "GPP_E6", "SATA_DEVSLP2", "n/a", "n/a",
- "GPP_E7", "CPU_GP1", "n/a", "n/a",
- "GPP_E8", "SATA_LED#", "n/a", "n/a",
- "GPP_E9", "USB_OC0#", "n/a", "n/a",
- "GPP_E10", "USB_OC1#", "n/a", "n/a",
- "GPP_E11", "USB_OC2#", "n/a", "n/a",
- "GPP_E12", "USB_OC3#", "n/a", "n/a",
-};
-
-static const struct gpio_group sunrise_group_e = {
- .display = "------- GPIO Group GPP_E -------",
- .pad_count = ARRAY_SIZE(sunrise_group_e_names) / 4,
- .func_count = 4,
- .pad_names = sunrise_group_e_names,
-};
-
-static const char *const sunrise_lp_group_e_names[] = {
- "GPP_E0", "SATAXPCIE0", "SATAGP0", "n/a",
- "GPP_E1", "SATAXPCIE1", "SATAGP1", "n/a",
- "GPP_E2", "SATAXPCIE2", "SATAGP2", "n/a",
- "GPP_E3", "CPU_GP0", "n/a", "n/a",
- "GPP_E4", "SATA_DEVSLP0", "n/a", "n/a",
- "GPP_E5", "SATA_DEVSLP1", "n/a", "n/a",
- "GPP_E6", "SATA_DEVSLP2", "n/a", "n/a",
- "GPP_E7", "CPU_GP1", "n/a", "n/a",
- "GPP_E8", "SATALED#", "n/a", "n/a",
- "GPP_E9", "USB2_OC0#", "n/a", "n/a",
- "GPP_E10", "USB2_OC1#", "n/a", "n/a",
- "GPP_E11", "USB2_OC2#", "n/a", "n/a",
- "GPP_E12", "USB2_OC3#", "n/a", "n/a",
- "GPP_E13", "DDPB_HPD0", "n/a", "n/a",
- "GPP_E14", "DDPC_HPD1", "n/a", "n/a",
- "GPP_E15", "DDPD_HPD2", "n/a", "n/a",
- "GPP_E16", "DDPE_HPD3", "n/a", "n/a",
- "GPP_E17", "EDP_HPD", "n/a", "n/a",
- "GPP_E18", "DDPB_CTRLCLK", "n/a", "n/a",
- "GPP_E19", "DDPB_CTRLDATA", "n/a", "n/a",
- "GPP_E20", "DDPC_CTRLCLK", "n/a", "n/a",
- "GPP_E21", "DDPC_CTRLDATA", "n/a", "n/a",
- "GPP_E22", "n/a", "n/a", "n/a",
- "GPP_E23", "n/a", "n/a", "n/a",
-};
-
-static const struct gpio_group sunrise_lp_group_e = {
- .display = "------- GPIO Group GPP_E -------",
- .pad_count = ARRAY_SIZE(sunrise_lp_group_e_names) / 4,
- .func_count = 4,
- .pad_names = sunrise_lp_group_e_names,
-};
-
-static const char *const sunrise_group_f_names[] = {
- "GPP_F0", "SATAXPCIE3", "SATAGP3", "n/a",
- "GPP_F1", "SATAXPCIE4", "SATAGP4", "n/a",
- "GPP_F2", "SATAXPCIE5", "SATAGP5", "n/a",
- "GPP_F3", "SATAXPCIE6", "SATAGP6", "n/a",
- "GPP_F4", "SATAXPCIE7", "SATAGP7", "n/a",
- "GPP_F5", "SATA_DEVSLP3", "n/a", "n/a",
- "GPP_F6", "SATA_DEVSLP4", "n/a", "n/a",
- "GPP_F7", "SATA_DEVSLP5", "n/a", "n/a",
- "GPP_F8", "SATA_DEVSLP6", "n/a", "n/a",
- "GPP_F9", "SATA_DEVSLP7", "n/a", "n/a",
- "GPP_F10", "SATA_SCLOCK", "n/a", "n/a",
- "GPP_F11", "SATA_SLOAD", "n/a", "n/a",
- "GPP_F12", "SATA_SDATAOUT1", "n/a", "n/a",
- "GPP_F13", "SATA_SDATAOUT2", "n/a", "n/a",
- "GPP_F14", "n/a", "n/a", "n/a",
- "GPP_F15", "USB_OC4#", "n/a", "n/a",
- "GPP_F16", "USB_OC5#", "n/a", "n/a",
- "GPP_F17", "USB_OC6#", "n/a", "n/a",
- "GPP_F18", "USB_OC7#", "n/a", "n/a",
- "GPP_F19", "eDP_VDDEN", "n/a", "n/a",
- "GPP_F20", "eDP_BKLTEN", "n/a", "n/a",
- "GPP_F21", "eDP_BKLTCTL", "n/a", "n/a",
- "GPP_F22", "n/a", "n/a", "n/a",
- "GPP_F23", "n/a", "n/a", "n/a",
-};
-
-static const struct gpio_group sunrise_group_f = {
- .display = "------- GPIO Group GPP_F -------",
- .pad_count = ARRAY_SIZE(sunrise_group_f_names) / 4,
- .func_count = 4,
- .pad_names = sunrise_group_f_names,
-};
-
-static const char *const sunrise_lp_group_f_names[] = {
- "GPP_F0", "I2S2_SCLK", "n/a", "n/a",
- "GPP_F1", "I2S2_SFRM", "n/a", "n/a",
- "GPP_F2", "I2S2_TXD", "n/a", "n/a",
- "GPP_F3", "I2S2_RXD", "n/a", "n/a",
- "GPP_F4", "I2C2_SDA", "n/a", "n/a",
- "GPP_F5", "I2C2_SCL", "n/a", "n/a",
- "GPP_F6", "I2C3_SDA", "n/a", "n/a",
- "GPP_F7", "I2C3_SCL", "n/a", "n/a",
- "GPP_F8", "I2C4_SDA", "n/a", "n/a",
- "GPP_F9", "I2C4_SCL", "n/a", "n/a",
- "GPP_F10", "I2C5_SDA", "ISH_I2C2_SDA", "n/a",
- "GPP_F11", "I2C5_SCL", "ISH_I2C2_SCL", "n/a",
- "GPP_F12", "EMMC_CMD", "n/a", "n/a",
- "GPP_F13", "EMMC_DATA0", "n/a", "n/a",
- "GPP_F14", "EMMC_DATA1", "n/a", "n/a",
- "GPP_F15", "EMMC_DATA2", "n/a", "n/a",
- "GPP_F16", "EMMC_DATA3", "n/a", "n/a",
- "GPP_F17", "EMMC_DATA4", "n/a", "n/a",
- "GPP_F18", "EMMC_DATA5", "n/a", "n/a",
- "GPP_F19", "EMMC_DATA6", "n/a", "n/a",
- "GPP_F20", "EMMC_DATA7", "n/a", "n/a",
- "GPP_F21", "EMMC_RCLK", "n/a", "n/a",
- "GPP_F22", "EMMC_CLK", "n/a", "n/a",
- "GPP_F23", "n/a", "n/a", "n/a",
-};
-
-static const struct gpio_group sunrise_lp_group_f = {
- .display = "------- GPIO Group GPP_F -------",
- .pad_count = ARRAY_SIZE(sunrise_lp_group_f_names) / 4,
- .func_count = 4,
- .pad_names = sunrise_lp_group_f_names,
-};
-
-static const char *const sunrise_group_g_names[] = {
- "GPP_G0", "FAN_TACH_0", "n/a", "n/a",
- "GPP_G1", "FAN_TACH_1", "n/a", "n/a",
- "GPP_G2", "FAN_TACH_2", "n/a", "n/a",
- "GPP_G3", "FAN_TACH_3", "n/a", "n/a",
- "GPP_G4", "FAN_TACH_4", "n/a", "n/a",
- "GPP_G5", "FAN_TACH_5", "n/a", "n/a",
- "GPP_G6", "FAN_TACH_6", "n/a", "n/a",
- "GPP_G7", "FAN_TACH_7", "n/a", "n/a",
- "GPP_G8", "FAN_PWM_0", "n/a", "n/a",
- "GPP_G9", "FAN_PWM_1", "n/a", "n/a",
- "GPP_G10", "FAN_PWM_2", "n/a", "n/a",
- "GPP_G11", "FAN_PWM_3", "n/a", "n/a",
- "GPP_G12", "GSXDOUT", "n/a", "n/a",
- "GPP_G13", "GSXSLOAD", "n/a", "n/a",
- "GPP_G14", "GSXDIN", "n/a", "n/a",
- "GPP_G15", "GSXRESET#", "n/a", "n/a",
- "GPP_G16", "GSXCLK", "n/a", "n/a",
- "GPP_G17", "ADR_COMPLETE", "n/a", "n/a",
- "GPP_G18", "NMI#", "n/a", "n/a",
- "GPP_G19", "SMI#", "n/a", "n/a",
- "GPP_G20", "n/a", "n/a", "n/a",
- "GPP_G21", "n/a", "n/a", "n/a",
- "GPP_G22", "n/a", "n/a", "n/a",
- "GPP_G23", "n/a", "n/a", "n/a",
-};
-
-static const struct gpio_group sunrise_group_g = {
- .display = "------- GPIO Group GPP_G -------",
- .pad_count = ARRAY_SIZE(sunrise_group_g_names) / 4,
- .func_count = 4,
- .pad_names = sunrise_group_g_names,
-};
-
-static const char *const sunrise_lp_group_g_names[] = {
- "GPP_G0", "SD_CMD", "n/a", "n/a",
- "GPP_G1", "SD_DATA0", "n/a", "n/a",
- "GPP_G2", "SD_DATA1", "n/a", "n/a",
- "GPP_G3", "SD_DATA2", "n/a", "n/a",
- "GPP_G4", "SD_DATA3", "n/a", "n/a",
- "GPP_G5", "SD_CD#", "n/a", "n/a",
- "GPP_G6", "SD_CLK", "n/a", "n/a",
- "GPP_G7", "SD_WP", "n/a", "n/a",
-};
-
-static const struct gpio_group sunrise_lp_group_g = {
- .display = "------- GPIO Group GPP_G -------",
- .pad_count = ARRAY_SIZE(sunrise_lp_group_g_names) / 4,
- .func_count = 4,
- .pad_names = sunrise_lp_group_g_names,
-};
-
-static const char *const sunrise_group_h_names[] = {
- "GPP_H0", "SRCCLKREQ6#", "n/a", "n/a",
- "GPP_H1", "SRCCLKREQ7#", "n/a", "n/a",
- "GPP_H2", "SRCCLKREQ8#", "n/a", "n/a",
- "GPP_H3", "SRCCLKREQ9#", "n/a", "n/a",
- "GPP_H4", "SRCCLKREQ10#", "n/a", "n/a",
- "GPP_H5", "SRCCLKREQ11#", "n/a", "n/a",
- "GPP_H6", "SRCCLKREQ12#", "n/a", "n/a",
- "GPP_H7", "SRCCLKREQ13#", "n/a", "n/a",
- "GPP_H8", "SRCCLKREQ14#", "n/a", "n/a",
- "GPP_H9", "SRCCLKREQ15#", "n/a", "n/a",
- "GPP_H10", "SML2CLK", "n/a", "n/a",
- "GPP_H11", "SML2DATA", "n/a", "n/a",
- "GPP_H12", "SML2ALERT#", "n/a", "n/a",
- "GPP_H13", "SML3CLK", "n/a", "n/a",
- "GPP_H14", "SML3DATA", "n/a", "n/a",
- "GPP_H15", "SML3ALERT#", "n/a", "n/a",
- "GPP_H16", "SML4CLK", "n/a", "n/a",
- "GPP_H17", "SML4DATA", "n/a", "n/a",
- "GPP_H18", "SML4ALERT#", "n/a", "n/a",
- "GPP_H19", "ISH_I2C0_SDA", "n/a", "n/a",
- "GPP_H20", "ISH_I2C0_SCL", "n/a", "n/a",
- "GPP_H21", "ISH_I2C1_SDA", "n/a", "n/a",
- "GPP_H22", "ISH_I2C1_SCL", "n/a", "n/a",
- "GPP_H23", "n/a", "n/a", "n/a",
-};
-
-static const struct gpio_group sunrise_group_h = {
- .display = "------- GPIO Group GPP_H -------",
- .pad_count = ARRAY_SIZE(sunrise_group_h_names) / 4,
- .func_count = 4,
- .pad_names = sunrise_group_h_names,
-};
-
-static const struct gpio_group *const sunrise_community_cdefgh_groups[] = {
- &sunrise_group_c, &sunrise_group_d, &sunrise_group_e,
- &sunrise_group_f, &sunrise_group_g, &sunrise_group_h,
-};
-
-static const struct gpio_group *const sunrise_lp_community_cde_groups[] = {
- &sunrise_group_c, &sunrise_lp_group_d, &sunrise_lp_group_e,
-};
-
-static const struct gpio_community sunrise_community_cdefgh = {
- .name = "------- GPIO Community 1 -------",
- .pcr_port_id = 0xae,
- .group_count = ARRAY_SIZE(sunrise_community_cdefgh_groups),
- .groups = sunrise_community_cdefgh_groups,
-};
-
-static const struct gpio_community sunrise_lp_community_cde = {
- .name = "------- GPIO Community 1 -------",
- .pcr_port_id = 0xae,
- .group_count = ARRAY_SIZE(sunrise_lp_community_cde_groups),
- .groups = sunrise_lp_community_cde_groups,
-};
-
-static const char *const sunrise_group_gpd_names[] = {
- "GPD0", "BATLOW#", "n/a", "n/a",
- "GPD1", "ACPRESENT", "n/a", "n/a",
- "GPD2", "LAN_WAKE#", "n/a", "n/a",
- "GPD3", "PWRBTN#", "n/a", "n/a",
- "GPD4", "SLP_S3#", "n/a", "n/a",
- "GPD5", "SLP_S4#", "n/a", "n/a",
- "GPD6", "SLP_A#", "n/a", "n/a",
- "GPD7", "RESERVED", "n/a", "n/a",
- "GPD8", "SUSCLK", "n/a", "n/a",
- "GPD9", "SLP_WLAN#", "n/a", "n/a",
- "GPD10", "SLP_S5#", "n/a", "n/a",
- "GPD11", "LANPHYPC", "n/a", "n/a",
-};
-
-static const struct gpio_group sunrise_group_gpd = {
- .display = "-------- GPIO Group GPD --------",
- .pad_count = ARRAY_SIZE(sunrise_group_gpd_names) / 4,
- .func_count = 4,
- .pad_names = sunrise_group_gpd_names,
-};
-
-static const struct gpio_group *const sunrise_community_gpd_groups[] = {
- &sunrise_group_gpd,
-};
-
-static const struct gpio_community sunrise_community_gpd = {
- .name = "------- GPIO Community 2 -------",
- .pcr_port_id = 0xad,
- .group_count = ARRAY_SIZE(sunrise_community_gpd_groups),
- .groups = sunrise_community_gpd_groups,
-};
-
-static const char *const sunrise_group_i_names[] = {
- "GPP_I0", "DDPB_HPD0", "n/a", "n/a",
- "GPP_I1", "DDPC_HPD1", "n/a", "n/a",
- "GPP_I2", "DDPD_HPD2", "n/a", "n/a",
- "GPP_I3", "DDPE_HPD3", "n/a", "n/a",
- "GPP_I4", "EDP_HPD", "n/a", "n/a",
- "GPP_I5", "DDPB_CTRLCLK", "n/a", "n/a",
- "GPP_I6", "DDPB_CTRLDATA", "n/a", "n/a",
- "GPP_I7", "DDPC_CTRLCLK", "n/a", "n/a",
- "GPP_I8", "DDPC_CTRLDATA", "n/a", "n/a",
- "GPP_I9", "DDPD_CTRLCLK", "n/a", "n/a",
- "GPP_I10", "DDPD_CTRLDATA", "n/a", "n/a",
-};
-
-static const struct gpio_group sunrise_group_i = {
- .display = "------- GPIO Group GPP_I -------",
- .pad_count = ARRAY_SIZE(sunrise_group_i_names) / 4,
- .func_count = 4,
- .pad_names = sunrise_group_i_names,
-};
-
-static const struct gpio_group *const sunrise_community_i_groups[] = {
- &sunrise_group_i,
-};
-
-static const struct gpio_group *const sunrise_lp_community_fg_groups[] = {
- &sunrise_lp_group_f, &sunrise_lp_group_g,
-};
-
-static const struct gpio_community sunrise_community_i = {
- .name = "------- GPIO Community 3 -------",
- .pcr_port_id = 0xac,
- .group_count = ARRAY_SIZE(sunrise_community_i_groups),
- .groups = sunrise_community_i_groups,
-};
-
-static const struct gpio_community sunrise_lp_community_fg = {
- .name = "------- GPIO Community 3 -------",
- .pcr_port_id = 0xac,
- .group_count = ARRAY_SIZE(sunrise_lp_community_fg_groups),
- .groups = sunrise_lp_community_fg_groups,
-};
-
-static const struct gpio_community *const sunrise_communities[] = {
- &sunrise_community_ab, &sunrise_community_cdefgh,
- &sunrise_community_gpd, &sunrise_community_i,
-};
-
-static const struct gpio_community *const sunrise_lp_communities[] = {
- &sunrise_lp_community_ab, &sunrise_lp_community_cde,
- &sunrise_community_gpd, &sunrise_lp_community_fg,
-};
-
-static const char *const denverton_group_north_all_names[] = {
- "NORTH_ALL_GBE0_SDP0",
- "NORTH_ALL_GBE1_SDP0",
- "NORTH_ALL_GBE0_SDP1",
- "NORTH_ALL_GBE1_SDP1",
- "NORTH_ALL_GBE0_SDP2",
- "NORTH_ALL_GBE1_SDP2",
- "NORTH_ALL_GBE0_SDP3",
- "NORTH_ALL_GBE1_SDP3",
- "NORTH_ALL_GBE2_LED0",
- "NORTH_ALL_GBE2_LED1",
- "NORTH_ALL_GBE0_I2C_CLK",
- "NORTH_ALL_GBE0_I2C_DATA",
- "NORTH_ALL_GBE1_I2C_CLK",
- "NORTH_ALL_GBE1_I2C_DATA",
- "NORTH_ALL_NCSI_RXD0",
- "NORTH_ALL_NCSI_CLK_IN",
- "NORTH_ALL_NCSI_RXD1",
- "NORTH_ALL_NCSI_CRS_DV",
- "NORTH_ALL_NCSI_ARB_IN",
- "NORTH_ALL_NCSI_TX_EN",
- "NORTH_ALL_NCSI_TXD0",
- "NORTH_ALL_NCSI_TXD1",
- "NORTH_ALL_NCSI_ARB_OUT",
- "NORTH_ALL_GBE0_LED0",
- "NORTH_ALL_GBE0_LED1",
- "NORTH_ALL_GBE1_LED0",
- "NORTH_ALL_GBE1_LED1",
- "NORTH_ALL_GPIO_0",
- "NORTH_ALL_PCIE_CLKREQ0_N",
- "NORTH_ALL_PCIE_CLKREQ1_N",
- "NORTH_ALL_PCIE_CLKREQ2_N",
- "NORTH_ALL_PCIE_CLKREQ3_N",
- "NORTH_ALL_PCIE_CLKREQ4_N",
- "NORTH_ALL_GPIO_1",
- "NORTH_ALL_GPIO_2",
- "NORTH_ALL_SVID_ALERT_N",
- "NORTH_ALL_SVID_DATA",
- "NORTH_ALL_SVID_CLK",
- "NORTH_ALL_THERMTRIP_N",
- "NORTH_ALL_PROCHOT_N",
- "NORTH_ALL_MEMHOT_N",
-};
-
-static const struct gpio_group denverton_group_north_all = {
- .display = "------- GPIO Group North All -------",
- .pad_count = ARRAY_SIZE(denverton_group_north_all_names) / 1,
- .func_count = 1,
- .pad_names = denverton_group_north_all_names,
-};
-
-static const struct gpio_group *const denverton_community_north_groups[] = {
- &denverton_group_north_all,
-};
-
-static const struct gpio_community denverton_community_north = {
- .name = "------- GPIO Community 0 -------",
- .pcr_port_id = 0xc2,
- .group_count = ARRAY_SIZE(denverton_community_north_groups),
- .groups = denverton_community_north_groups,
-};
-
-static const char *const denverton_group_south_dfx_names[] = {
- "SOUTH_DFX_DFX_PORT_CLK0",
- "SOUTH_DFX_DFX_PORT_CLK1",
- "SOUTH_DFX_DFX_PORT0",
- "SOUTH_DFX_DFX_PORT1",
- "SOUTH_DFX_DFX_PORT2",
- "SOUTH_DFX_DFX_PORT3",
- "SOUTH_DFX_DFX_PORT4",
- "SOUTH_DFX_DFX_PORT5",
- "SOUTH_DFX_DFX_PORT6",
- "SOUTH_DFX_DFX_PORT7",
- "SOUTH_DFX_DFX_PORT8",
- "SOUTH_DFX_DFX_PORT9",
- "SOUTH_DFX_DFX_PORT10",
- "SOUTH_DFX_DFX_PORT11",
- "SOUTH_DFX_DFX_PORT12",
- "SOUTH_DFX_DFX_PORT13",
- "SOUTH_DFX_DFX_PORT14",
- "SOUTH_DFX_DFX_PORT15",
-};
-
-static const struct gpio_group denverton_group_south_dfx = {
- .display = "------- GPIO Group South DFX -------",
- .pad_count = ARRAY_SIZE(denverton_group_south_dfx_names) / 1,
- .func_count = 1,
- .pad_names = denverton_group_south_dfx_names,
-};
-
-static const char *const denverton_group_south_group0_names[] = {
- "SOUTH_GROUP0_GPIO_12",
- "SOUTH_GROUP0_SMB5_GBE_ALRT_N",
- "SOUTH_GROUP0_PCIE_CLKREQ5_N",
- "SOUTH_GROUP0_PCIE_CLKREQ6_N",
- "SOUTH_GROUP0_PCIE_CLKREQ7_N",
- "SOUTH_GROUP0_UART0_RXD",
- "SOUTH_GROUP0_UART0_TXD",
- "SOUTH_GROUP0_SMB5_GBE_CLK",
- "SOUTH_GROUP0_SMB5_GBE_DATA",
- "SOUTH_GROUP0_ERROR2_N",
- "SOUTH_GROUP0_ERROR1_N",
- "SOUTH_GROUP0_ERROR0_N",
- "SOUTH_GROUP0_IERR_N",
- "SOUTH_GROUP0_MCERR_N",
- "SOUTH_GROUP0_SMB0_LEG_CLK",
- "SOUTH_GROUP0_SMB0_LEG_DATA",
- "SOUTH_GROUP0_SMB0_LEG_ALRT_N",
- "SOUTH_GROUP0_SMB1_HOST_DATA",
- "SOUTH_GROUP0_SMB1_HOST_CLK",
- "SOUTH_GROUP0_SMB2_PECI_DATA",
- "SOUTH_GROUP0_SMB2_PECI_CLK",
- "SOUTH_GROUP0_SMB4_CSME0_DATA",
- "SOUTH_GROUP0_SMB4_CSME0_CLK",
- "SOUTH_GROUP0_SMB4_CSME0_ALRT_N",
- "SOUTH_GROUP0_USB_OC0_N",
- "SOUTH_GROUP0_FLEX_CLK_SE0",
- "SOUTH_GROUP0_FLEX_CLK_SE1",
- "SOUTH_GROUP0_GPIO_4",
- "SOUTH_GROUP0_GPIO_5",
- "SOUTH_GROUP0_GPIO_6",
- "SOUTH_GROUP0_GPIO_7",
- "SOUTH_GROUP0_SATA0_LED_N",
- "SOUTH_GROUP0_SATA1_LED_N",
- "SOUTH_GROUP0_SATA_PDETECT0",
- "SOUTH_GROUP0_SATA_PDETECT1",
- "SOUTH_GROUP0_SATA0_SDOUT",
- "SOUTH_GROUP0_SATA1_SDOUT",
- "SOUTH_GROUP0_UART1_RXD",
- "SOUTH_GROUP0_UART1_TXD",
- "SOUTH_GROUP0_GPIO_8",
- "SOUTH_GROUP0_GPIO_9",
- "SOUTH_GROUP0_TCK",
- "SOUTH_GROUP0_TRST_N",
- "SOUTH_GROUP0_TMS",
- "SOUTH_GROUP0_TDI",
- "SOUTH_GROUP0_TDO",
- "SOUTH_GROUP0_CX_PRDY_N",
- "SOUTH_GROUP0_CX_PREQ_N",
- "SOUTH_GROUP0_CTBTRIGINOUT",
- "SOUTH_GROUP0_CTBTRIGOUT",
- "SOUTH_GROUP0_DFX_SPARE2",
- "SOUTH_GROUP0_DFX_SPARE3",
- "SOUTH_GROUP0_DFX_SPARE4",
-};
-
-static const struct gpio_group denverton_group_south_group0 = {
- .display = "------- GPIO Group South Group0 -------",
- .pad_count = ARRAY_SIZE(denverton_group_south_group0_names) / 1,
- .func_count = 1,
- .pad_names = denverton_group_south_group0_names,
-};
-
-static const char *const denverton_group_south_group1_names[] = {
- "SOUTH_GROUP1_SUSPWRDNACK",
- "SOUTH_GROUP1_PMU_SUSCLK",
- "SOUTH_GROUP1_ADR_TRIGGER",
- "SOUTH_GROUP1_PMU_SLP_S45_N",
- "SOUTH_GROUP1_PMU_SLP_S3_N",
- "SOUTH_GROUP1_PMU_WAKE_N",
- "SOUTH_GROUP1_PMU_PWRBTN_N",
- "SOUTH_GROUP1_PMU_RESETBUTTON_N",
- "SOUTH_GROUP1_PMU_PLTRST_N",
- "SOUTH_GROUP1_SUS_STAT_N",
- "SOUTH_GROUP1_SLP_S0IX_N",
- "SOUTH_GROUP1_SPI_CS0_N",
- "SOUTH_GROUP1_SPI_CS1_N",
- "SOUTH_GROUP1_SPI_MOSI_IO0",
- "SOUTH_GROUP1_SPI_MISO_IO1",
- "SOUTH_GROUP1_SPI_IO2",
- "SOUTH_GROUP1_SPI_IO3",
- "SOUTH_GROUP1_SPI_CLK",
- "SOUTH_GROUP1_SPI_CLK_LOOPBK",
- "SOUTH_GROUP1_ESPI_IO0",
- "SOUTH_GROUP1_ESPI_IO1",
- "SOUTH_GROUP1_ESPI_IO2",
- "SOUTH_GROUP1_ESPI_IO3",
- "SOUTH_GROUP1_ESPI_CS0_N",
- "SOUTH_GROUP1_ESPI_CLK",
- "SOUTH_GROUP1_ESPI_RST_N",
- "SOUTH_GROUP1_ESPI_ALRT0_N",
- "SOUTH_GROUP1_GPIO_10",
- "SOUTH_GROUP1_GPIO_11",
- "SOUTH_GROUP1_ESPI_CLK_LOOPBK",
- "SOUTH_GROUP1_EMMC_CMD",
- "SOUTH_GROUP1_EMMC_STROBE",
- "SOUTH_GROUP1_EMMC_CLK",
- "SOUTH_GROUP1_EMMC_D0",
- "SOUTH_GROUP1_EMMC_D1",
- "SOUTH_GROUP1_EMMC_D2",
- "SOUTH_GROUP1_EMMC_D3",
- "SOUTH_GROUP1_EMMC_D4",
- "SOUTH_GROUP1_EMMC_D5",
- "SOUTH_GROUP1_EMMC_D6",
- "SOUTH_GROUP1_EMMC_D7",
- "SOUTH_GROUP1_GPIO_3",
-};
-
-static const struct gpio_group denverton_group_south_group1 = {
- .display = "------- GPIO Group South Group1 -------",
- .pad_count = ARRAY_SIZE(denverton_group_south_group1_names) / 1,
- .func_count = 1,
- .pad_names = denverton_group_south_group1_names,
-};
-
-static const struct gpio_group *const denverton_community_south_groups[] = {
- &denverton_group_south_dfx,
- &denverton_group_south_group0,
- &denverton_group_south_group1,
-};
-
-static const struct gpio_community denverton_community_south = {
- .name = "------- GPIO Community 1 -------",
- .pcr_port_id = 0xc5,
- .group_count = ARRAY_SIZE(denverton_community_south_groups),
- .groups = denverton_community_south_groups,
-};
-
-static const struct gpio_community *const denverton_communities[] = {
- &denverton_community_north, &denverton_community_south,
-};
-
static const char *decode_pad_mode(const struct gpio_group *const group,
const size_t pad, const uint32_t dw0)
{
diff --git a/util/inteltool/gpio_sunrise.h b/util/inteltool/gpio_sunrise.h
new file mode 100644
index 0000000..5553b7d
--- /dev/null
+++ b/util/inteltool/gpio_sunrise.h
@@ -0,0 +1,595 @@
+/*
+ * inteltool - dump all registers on an Intel CPU + chipset based system.
+ *
+ * Copyright (C) 2017 secunet Security Networks AG
+ * Copyright (C) 2019 Felix Singer <migy(a)darmstadt.ccc.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+static const char *const sunrise_group_a_names[] = {
+ "GPP_A0", "RCIN#", "n/a", "ESPI_ALERT1#",
+ "GPP_A1", "LAD0", "n/a", "ESPI_IO0",
+ "GPP_A2", "LAD1", "n/a", "ESPI_IO1",
+ "GPP_A3", "LAD2", "n/a", "ESPI_IO2",
+ "GPP_A4", "LAD3", "n/a", "ESPI_IO3",
+ "GPP_A5", "LFRAME#", "n/a", "ESPI_CS#",
+ "GPP_A6", "SERIRQ", "n/a", "ESPI_CS1#",
+ "GPP_A7", "PIRQA#", "n/a", "ESPI_ALERT0#",
+ "GPP_A8", "CLKRUN#", "n/a", "n/a",
+ "GPP_A9", "CLKOUT_LPC0", "n/a", "ESPI_CLK",
+ "GPP_A10", "CLKOUT_LPC1", "n/a", "n/a",
+ "GPP_A11", "PME#", "n/a", "n/a",
+ "GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#",
+ "GPP_A13", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a",
+ "GPP_A14", "SUS_STAT#", "n/a", "ESPI_RESET#",
+ "GPP_A15", "SUS_ACK#", "n/a", "n/a",
+ "GPP_A16", "CLKOUT_48", "n/a", "n/a",
+ "GPP_A17", "ISH_GP7", "n/a", "n/a",
+ "GPP_A18", "ISH_GP0", "n/a", "n/a",
+ "GPP_A19", "ISH_GP1", "n/a", "n/a",
+ "GPP_A20", "ISH_GP2", "n/a", "n/a",
+ "GPP_A21", "ISH_GP3", "n/a", "n/a",
+ "GPP_A22", "ISH_GP4", "n/a", "n/a",
+ "GPP_A23", "ISH_GP5", "n/a", "n/a",
+};
+
+static const struct gpio_group sunrise_group_a = {
+ .display = "------- GPIO Group GPP_A -------",
+ .pad_count = ARRAY_SIZE(sunrise_group_a_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_group_a_names,
+};
+
+static const char *const sunrise_lp_group_a_names[] = {
+ "GPP_A0", "RCIN#", "n/a", "n/a",
+ "GPP_A1", "LAD0", "n/a", "ESPI_IO0",
+ "GPP_A2", "LAD1", "n/a", "ESPI_IO1",
+ "GPP_A3", "LAD2", "n/a", "ESPI_IO2",
+ "GPP_A4", "LAD3", "n/a", "ESPI_IO3",
+ "GPP_A5", "LFRAME#", "n/a", "ESPI_CS#",
+ "GPP_A6", "SERIRQ", "n/a", "n/a",
+ "GPP_A7", "PIRQA#", "n/a", "n/a",
+ "GPP_A8", "CLKRUN#", "n/a", "n/a",
+ "GPP_A9", "CLKOUT_LPC0", "n/a", "ESPI_CLK",
+ "GPP_A10", "CLKOUT_LPC1", "n/a", "n/a",
+ "GPP_A11", "PME#", "n/a", "n/a",
+ "GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#",
+ "GPP_A13", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a",
+ "GPP_A14", "SUS_STAT#", "n/a", "ESPI_RESET#",
+ "GPP_A15", "SUS_ACK#", "n/a", "n/a",
+ "GPP_A16", "SD_1P8_SEL", "n/a", "n/a",
+ "GPP_A17", "SD_PWR_EN#", "ISH_GP7", "n/a",
+ "GPP_A18", "ISH_GP0", "n/a", "n/a",
+ "GPP_A19", "ISH_GP1", "n/a", "n/a",
+ "GPP_A20", "ISH_GP2", "n/a", "n/a",
+ "GPP_A21", "ISH_GP3", "n/a", "n/a",
+ "GPP_A22", "ISH_GP4", "n/a", "n/a",
+ "GPP_A23", "ISH_GP5", "n/a", "n/a",
+};
+
+static const struct gpio_group sunrise_lp_group_a = {
+ .display = "------- GPIO group GPP_A -------",
+ .pad_count = ARRAY_SIZE(sunrise_lp_group_a_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_lp_group_a_names,
+};
+
+static const char *const sunrise_group_b_names[] = {
+ "GPP_B0", "n/a", "n/a", "n/a",
+ "GPP_B1", "n/a", "n/a", "n/a",
+ "GPP_B2", "VRALERT#", "n/a", "n/a",
+ "GPP_B3", "CPU_GP2", "n/a", "n/a",
+ "GPP_B4", "CPU_GP3", "n/a", "n/a",
+ "GPP_B5", "SRCCLKREQ0#", "n/a", "n/a",
+ "GPP_B6", "SRCCLKREQ1#", "n/a", "n/a",
+ "GPP_B7", "SRCCLKREQ2#", "n/a", "n/a",
+ "GPP_B8", "SRCCLKREQ3#", "n/a", "n/a",
+ "GPP_B9", "SRCCLKREQ4#", "n/a", "n/a",
+ "GPP_B10", "SRCCLKREQ5#", "n/a", "n/a",
+ "GPP_B11", "n/a", "n/a", "n/a",
+ "GPP_B12", "SLP_S0#", "n/a", "n/a",
+ "GPP_B13", "PLTRST#", "n/a", "n/a",
+ "GPP_B14", "SPKR", "n/a", "n/a",
+ "GPP_B15", "GSPIO_CS#", "n/a", "n/a",
+ "GPP_B16", "GSPIO_CLK", "n/a", "n/a",
+ "GPP_B17", "GSPIO_MISO", "n/a", "n/a",
+ "GPP_B18", "GSPIO_MOSI", "n/a", "n/a",
+ "GPP_B19", "GSPI1_CS#", "n/a", "n/a",
+ "GPP_B20", "GSPI1_CLK", "n/a", "n/a",
+ "GPP_B21", "GSPI1_MISO", "n/a", "n/a",
+ "GPP_B22", "GSPI1_MOSI", "n/a", "n/a",
+ "GPP_B23", "SML1ALERT#", "PCHHOT#", "n/a",
+};
+
+static const struct gpio_group sunrise_group_b = {
+ .display = "------- GPIO Group GPP_B -------",
+ .pad_count = ARRAY_SIZE(sunrise_group_b_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_group_b_names,
+};
+
+static const char *const sunrise_lp_group_b_names[] = {
+ "GPP_B0", "CORE_VID0", "n/a", "n/a",
+ "GPP_B1", "CORE_VID1", "n/a", "n/a",
+ "GPP_B2", "VRALERT#", "n/a", "n/a",
+ "GPP_B3", "CPU_GP2", "n/a", "n/a",
+ "GPP_B4", "CPU_GP3", "n/a", "n/a",
+ "GPP_B5", "SRCCLKREQ0#", "n/a", "n/a",
+ "GPP_B6", "SRCCLKREQ1#", "n/a", "n/a",
+ "GPP_B7", "SRCCLKREQ2#", "n/a", "n/a",
+ "GPP_B8", "SRCCLKREQ3#", "n/a", "n/a",
+ "GPP_B9", "SRCCLKREQ4#", "n/a", "n/a",
+ "GPP_B10", "SRCCLKREQ5#", "n/a", "n/a",
+ "GPP_B11", "EXT_PWR_GATE#", "n/a", "n/a",
+ "GPP_B12", "SLP_S0#", "n/a", "n/a",
+ "GPP_B13", "PLTRST#", "n/a", "n/a",
+ "GPP_B14", "SPKR", "n/a", "n/a",
+ "GPP_B15", "GSPI0_CS#", "n/a", "n/a",
+ "GPP_B16", "GSPI0_CLK", "n/a", "n/a",
+ "GPP_B17", "GSPI0_MISO", "n/a", "n/a",
+ "GPP_B18", "GSPI0_MOSI", "n/a", "n/a",
+ "GPP_B19", "GSPI1_CS#", "n/a", "n/a",
+ "GPP_B20", "GSPI1_CLK", "n/a", "n/a",
+ "GPP_B21", "GSPI1_MISO", "n/a", "n/a",
+ "GPP_B22", "GSPI1_MOSI", "n/a", "n/a",
+ "GPP_B23", "SML1ALERT#", "PCHHOT#", "n/a",
+};
+
+static const struct gpio_group sunrise_lp_group_b = {
+ .display = "------- GPIO Group GPP_B -------",
+ .pad_count = ARRAY_SIZE(sunrise_lp_group_b_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_lp_group_b_names,
+};
+
+static const struct gpio_group *const sunrise_community_ab_groups[] = {
+ &sunrise_group_a, &sunrise_group_b,
+};
+
+static const struct gpio_group *const sunrise_lp_community_ab_groups[] = {
+ &sunrise_lp_group_a, &sunrise_lp_group_b,
+};
+
+static const struct gpio_community sunrise_community_ab = {
+ .name = "------- GPIO Community 0 -------",
+ .pcr_port_id = 0xaf,
+ .group_count = ARRAY_SIZE(sunrise_community_ab_groups),
+ .groups = sunrise_community_ab_groups,
+};
+
+static const struct gpio_community sunrise_lp_community_ab = {
+ .name = "------- GPIO Community 0 -------",
+ .pcr_port_id = 0xaf,
+ .group_count = ARRAY_SIZE(sunrise_lp_community_ab_groups),
+ .groups = sunrise_lp_community_ab_groups,
+};
+
+static const char *const sunrise_group_c_names[] = {
+ "GPP_C0", "SMBCLK", "n/a", "n/a",
+ "GPP_C1", "SMBDATA", "n/a", "n/a",
+ "GPP_C2", "SMBALERT#", "n/a", "n/a",
+ "GPP_C3", "SML0CLK", "n/a", "n/a",
+ "GPP_C4", "SML0DATA", "n/a", "n/a",
+ "GPP_C5", "SML0ALERT#", "n/a", "n/a",
+ "GPP_C6", "SML1CLK", "n/a", "n/a",
+ "GPP_C7", "SML1DATA", "n/a", "n/a",
+ "GPP_C8", "UART0_RXD", "n/a", "n/a",
+ "GPP_C9", "UART0_TXD", "n/a", "n/a",
+ "GPP_C10", "UART0_RTS#", "n/a", "n/a",
+ "GPP_C11", "UART0_CTS#", "n/a", "n/a",
+ "GPP_C12", "UART1_RXD", "ISH_UART1_RXD", "n/a",
+ "GPP_C13", "UART1_TXD", "ISH_UART1_TXD", "n/a",
+ "GPP_C14", "UART1_RTS#", "ISH_UART1_RTS#", "n/a",
+ "GPP_C15", "UART1_CTS#", "ISH_UART1_CTS#", "n/a",
+ "GPP_C16", "I2C0_SDA", "n/a", "n/a",
+ "GPP_C17", "I2C0_SCL", "n/a", "n/a",
+ "GPP_C18", "I2C1_SDA", "n/a", "n/a",
+ "GPP_C19", "I2C1_SCL", "n/a", "n/a",
+ "GPP_C20", "UART2_RXD", "n/a", "n/a",
+ "GPP_C21", "UART2_TXD", "n/a", "n/a",
+ "GPP_C22", "UART2_RTS#", "n/a", "n/a",
+ "GPP_C23", "UART2_CTS#", "n/a", "n/a",
+};
+
+static const struct gpio_group sunrise_group_c = {
+ .display = "------- GPIO Group GPP_C -------",
+ .pad_count = ARRAY_SIZE(sunrise_group_c_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_group_c_names,
+};
+
+static const char *const sunrise_group_d_names[] = {
+ "GPP_D0", "n/a", "n/a", "n/a",
+ "GPP_D1", "n/a", "n/a", "n/a",
+ "GPP_D2", "n/a", "n/a", "n/a",
+ "GPP_D3", "n/a", "n/a", "n/a",
+ "GPP_D4", "ISH_I2C2_SDA", "I2C3_SDA", "n/a",
+ "GPP_D5", "I2S_SFRM", "n/a", "n/a",
+ "GPP_D6", "I2S_TXD", "n/a", "n/a",
+ "GPP_D7", "I2S_RXD", "n/a", "n/a",
+ "GPP_D8", "I2S_SCLK", "n/a", "n/a",
+ "GPP_D9", "n/a", "n/a", "n/a",
+ "GPP_D10", "n/a", "n/a", "n/a",
+ "GPP_D11", "n/a", "n/a", "n/a",
+ "GPP_D12", "n/a", "n/a", "n/a",
+ "GPP_D13", "ISH_UART0_RXD", "n/a", "I2C2_SDA",
+ "GPP_D14", "ISH_UART0_TXD", "n/a", "I2C2_SCL",
+ "GPP_D15", "ISH_UART0_RTS#", "n/a", "n/a",
+ "GPP_D16", "ISH_UART0_CTS#", "n/a", "n/a",
+ "GPP_D17", "DMIC_CLK1", "n/a", "n/a",
+ "GPP_D18", "DMIC_DATA1", "n/a", "n/a",
+ "GPP_D19", "DMIC_CLK0", "n/a", "n/a",
+ "GPP_D20", "DMIC_DATA0", "n/a", "n/a",
+ "GPP_D21", "n/a", "n/a", "n/a",
+ "GPP_D22", "n/a", "n/a", "n/a",
+ "GPP_D23", "ISH_I2C2_SCL", "I2C3_SCL", "n/a",
+};
+
+static const struct gpio_group sunrise_group_d = {
+ .display = "------- GPIO Group GPP_D -------",
+ .pad_count = ARRAY_SIZE(sunrise_group_d_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_group_d_names,
+};
+
+static const char *const sunrise_lp_group_d_names[] = {
+ "GPP_D0", "SPI1_CS#", "n/a", "n/a",
+ "GPP_D1", "SPI1_CLK", "n/a", "n/a",
+ "GPP_D2", "SPI1_MISO", "n/a", "n/a",
+ "GPP_D3", "SPI1_MOSI", "n/a", "n/a",
+ "GPP_D4", "FLASHTRIG", "n/a", "n/a",
+ "GPP_D5", "ISH_I2C0_SDA", "n/a", "n/a",
+ "GPP_D6", "ISH_I2C0_SCL", "n/a", "n/a",
+ "GPP_D7", "ISH_I2C1_SDA", "n/a", "n/a",
+ "GPP_D8", "ISH_I2C1_SCL", "n/a", "n/a",
+ "GPP_D9", "n/a", "n/a", "n/a",
+ "GPP_D10", "n/a", "n/a", "n/a",
+ "GPP_D11", "n/a", "n/a", "n/a",
+ "GPP_D12", "n/a", "n/a", "n/a",
+ "GPP_D13", "ISH_UART0_RXD", "n/a", "n/a",
+ "GPP_D14", "ISH_UART0_TXD", "n/a", "n/a",
+ "GPP_D15", "ISH_UART0_RTS#", "n/a", "n/a",
+ "GPP_D16", "ISH_UART0_CTS#", "n/a", "n/a",
+ "GPP_D17", "DMIC_CLK1", "n/a", "n/a",
+ "GPP_D18", "DMIC_DATA1", "n/a", "n/a",
+ "GPP_D19", "DMIC_CLK0", "n/a", "n/a",
+ "GPP_D20", "DMIC_DATA0", "n/a", "n/a",
+ "GPP_D21", "SPI1_IO2", "n/a", "n/a",
+ "GPP_D22", "SPI1_IO3", "n/a", "n/a",
+ "GPP_D23", "I2S_MCLK", "n/a", "n/a",
+};
+
+static const struct gpio_group sunrise_lp_group_d = {
+ .display = "------- GPIO Group GPP_D -------",
+ .pad_count = ARRAY_SIZE(sunrise_lp_group_d_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_lp_group_d_names,
+};
+
+static const char *const sunrise_group_e_names[] = {
+ "GPP_E0", "SATAXPCIE0", "SATAGP0", "n/a",
+ "GPP_E1", "SATAXPCIE1", "SATAGP1", "n/a",
+ "GPP_E2", "SATAXPCIE2", "SATAGP2", "n/a",
+ "GPP_E3", "CPU_GP0", "n/a", "n/a",
+ "GPP_E4", "SATA_DEVSLP0", "n/a", "n/a",
+ "GPP_E5", "SATA_DEVSLP1", "n/a", "n/a",
+ "GPP_E6", "SATA_DEVSLP2", "n/a", "n/a",
+ "GPP_E7", "CPU_GP1", "n/a", "n/a",
+ "GPP_E8", "SATA_LED#", "n/a", "n/a",
+ "GPP_E9", "USB_OC0#", "n/a", "n/a",
+ "GPP_E10", "USB_OC1#", "n/a", "n/a",
+ "GPP_E11", "USB_OC2#", "n/a", "n/a",
+ "GPP_E12", "USB_OC3#", "n/a", "n/a",
+};
+
+static const struct gpio_group sunrise_group_e = {
+ .display = "------- GPIO Group GPP_E -------",
+ .pad_count = ARRAY_SIZE(sunrise_group_e_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_group_e_names,
+};
+
+static const char *const sunrise_lp_group_e_names[] = {
+ "GPP_E0", "SATAXPCIE0", "SATAGP0", "n/a",
+ "GPP_E1", "SATAXPCIE1", "SATAGP1", "n/a",
+ "GPP_E2", "SATAXPCIE2", "SATAGP2", "n/a",
+ "GPP_E3", "CPU_GP0", "n/a", "n/a",
+ "GPP_E4", "SATA_DEVSLP0", "n/a", "n/a",
+ "GPP_E5", "SATA_DEVSLP1", "n/a", "n/a",
+ "GPP_E6", "SATA_DEVSLP2", "n/a", "n/a",
+ "GPP_E7", "CPU_GP1", "n/a", "n/a",
+ "GPP_E8", "SATALED#", "n/a", "n/a",
+ "GPP_E9", "USB2_OC0#", "n/a", "n/a",
+ "GPP_E10", "USB2_OC1#", "n/a", "n/a",
+ "GPP_E11", "USB2_OC2#", "n/a", "n/a",
+ "GPP_E12", "USB2_OC3#", "n/a", "n/a",
+ "GPP_E13", "DDPB_HPD0", "n/a", "n/a",
+ "GPP_E14", "DDPC_HPD1", "n/a", "n/a",
+ "GPP_E15", "DDPD_HPD2", "n/a", "n/a",
+ "GPP_E16", "DDPE_HPD3", "n/a", "n/a",
+ "GPP_E17", "EDP_HPD", "n/a", "n/a",
+ "GPP_E18", "DDPB_CTRLCLK", "n/a", "n/a",
+ "GPP_E19", "DDPB_CTRLDATA", "n/a", "n/a",
+ "GPP_E20", "DDPC_CTRLCLK", "n/a", "n/a",
+ "GPP_E21", "DDPC_CTRLDATA", "n/a", "n/a",
+ "GPP_E22", "n/a", "n/a", "n/a",
+ "GPP_E23", "n/a", "n/a", "n/a",
+};
+
+static const struct gpio_group sunrise_lp_group_e = {
+ .display = "------- GPIO Group GPP_E -------",
+ .pad_count = ARRAY_SIZE(sunrise_lp_group_e_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_lp_group_e_names,
+};
+
+static const char *const sunrise_group_f_names[] = {
+ "GPP_F0", "SATAXPCIE3", "SATAGP3", "n/a",
+ "GPP_F1", "SATAXPCIE4", "SATAGP4", "n/a",
+ "GPP_F2", "SATAXPCIE5", "SATAGP5", "n/a",
+ "GPP_F3", "SATAXPCIE6", "SATAGP6", "n/a",
+ "GPP_F4", "SATAXPCIE7", "SATAGP7", "n/a",
+ "GPP_F5", "SATA_DEVSLP3", "n/a", "n/a",
+ "GPP_F6", "SATA_DEVSLP4", "n/a", "n/a",
+ "GPP_F7", "SATA_DEVSLP5", "n/a", "n/a",
+ "GPP_F8", "SATA_DEVSLP6", "n/a", "n/a",
+ "GPP_F9", "SATA_DEVSLP7", "n/a", "n/a",
+ "GPP_F10", "SATA_SCLOCK", "n/a", "n/a",
+ "GPP_F11", "SATA_SLOAD", "n/a", "n/a",
+ "GPP_F12", "SATA_SDATAOUT1", "n/a", "n/a",
+ "GPP_F13", "SATA_SDATAOUT2", "n/a", "n/a",
+ "GPP_F14", "n/a", "n/a", "n/a",
+ "GPP_F15", "USB_OC4#", "n/a", "n/a",
+ "GPP_F16", "USB_OC5#", "n/a", "n/a",
+ "GPP_F17", "USB_OC6#", "n/a", "n/a",
+ "GPP_F18", "USB_OC7#", "n/a", "n/a",
+ "GPP_F19", "eDP_VDDEN", "n/a", "n/a",
+ "GPP_F20", "eDP_BKLTEN", "n/a", "n/a",
+ "GPP_F21", "eDP_BKLTCTL", "n/a", "n/a",
+ "GPP_F22", "n/a", "n/a", "n/a",
+ "GPP_F23", "n/a", "n/a", "n/a",
+};
+
+static const struct gpio_group sunrise_group_f = {
+ .display = "------- GPIO Group GPP_F -------",
+ .pad_count = ARRAY_SIZE(sunrise_group_f_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_group_f_names,
+};
+
+static const char *const sunrise_lp_group_f_names[] = {
+ "GPP_F0", "I2S2_SCLK", "n/a", "n/a",
+ "GPP_F1", "I2S2_SFRM", "n/a", "n/a",
+ "GPP_F2", "I2S2_TXD", "n/a", "n/a",
+ "GPP_F3", "I2S2_RXD", "n/a", "n/a",
+ "GPP_F4", "I2C2_SDA", "n/a", "n/a",
+ "GPP_F5", "I2C2_SCL", "n/a", "n/a",
+ "GPP_F6", "I2C3_SDA", "n/a", "n/a",
+ "GPP_F7", "I2C3_SCL", "n/a", "n/a",
+ "GPP_F8", "I2C4_SDA", "n/a", "n/a",
+ "GPP_F9", "I2C4_SCL", "n/a", "n/a",
+ "GPP_F10", "I2C5_SDA", "ISH_I2C2_SDA", "n/a",
+ "GPP_F11", "I2C5_SCL", "ISH_I2C2_SCL", "n/a",
+ "GPP_F12", "EMMC_CMD", "n/a", "n/a",
+ "GPP_F13", "EMMC_DATA0", "n/a", "n/a",
+ "GPP_F14", "EMMC_DATA1", "n/a", "n/a",
+ "GPP_F15", "EMMC_DATA2", "n/a", "n/a",
+ "GPP_F16", "EMMC_DATA3", "n/a", "n/a",
+ "GPP_F17", "EMMC_DATA4", "n/a", "n/a",
+ "GPP_F18", "EMMC_DATA5", "n/a", "n/a",
+ "GPP_F19", "EMMC_DATA6", "n/a", "n/a",
+ "GPP_F20", "EMMC_DATA7", "n/a", "n/a",
+ "GPP_F21", "EMMC_RCLK", "n/a", "n/a",
+ "GPP_F22", "EMMC_CLK", "n/a", "n/a",
+ "GPP_F23", "n/a", "n/a", "n/a",
+};
+
+static const struct gpio_group sunrise_lp_group_f = {
+ .display = "------- GPIO Group GPP_F -------",
+ .pad_count = ARRAY_SIZE(sunrise_lp_group_f_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_lp_group_f_names,
+};
+
+static const char *const sunrise_group_g_names[] = {
+ "GPP_G0", "FAN_TACH_0", "n/a", "n/a",
+ "GPP_G1", "FAN_TACH_1", "n/a", "n/a",
+ "GPP_G2", "FAN_TACH_2", "n/a", "n/a",
+ "GPP_G3", "FAN_TACH_3", "n/a", "n/a",
+ "GPP_G4", "FAN_TACH_4", "n/a", "n/a",
+ "GPP_G5", "FAN_TACH_5", "n/a", "n/a",
+ "GPP_G6", "FAN_TACH_6", "n/a", "n/a",
+ "GPP_G7", "FAN_TACH_7", "n/a", "n/a",
+ "GPP_G8", "FAN_PWM_0", "n/a", "n/a",
+ "GPP_G9", "FAN_PWM_1", "n/a", "n/a",
+ "GPP_G10", "FAN_PWM_2", "n/a", "n/a",
+ "GPP_G11", "FAN_PWM_3", "n/a", "n/a",
+ "GPP_G12", "GSXDOUT", "n/a", "n/a",
+ "GPP_G13", "GSXSLOAD", "n/a", "n/a",
+ "GPP_G14", "GSXDIN", "n/a", "n/a",
+ "GPP_G15", "GSXRESET#", "n/a", "n/a",
+ "GPP_G16", "GSXCLK", "n/a", "n/a",
+ "GPP_G17", "ADR_COMPLETE", "n/a", "n/a",
+ "GPP_G18", "NMI#", "n/a", "n/a",
+ "GPP_G19", "SMI#", "n/a", "n/a",
+ "GPP_G20", "n/a", "n/a", "n/a",
+ "GPP_G21", "n/a", "n/a", "n/a",
+ "GPP_G22", "n/a", "n/a", "n/a",
+ "GPP_G23", "n/a", "n/a", "n/a",
+};
+
+static const struct gpio_group sunrise_group_g = {
+ .display = "------- GPIO Group GPP_G -------",
+ .pad_count = ARRAY_SIZE(sunrise_group_g_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_group_g_names,
+};
+
+static const char *const sunrise_lp_group_g_names[] = {
+ "GPP_G0", "SD_CMD", "n/a", "n/a",
+ "GPP_G1", "SD_DATA0", "n/a", "n/a",
+ "GPP_G2", "SD_DATA1", "n/a", "n/a",
+ "GPP_G3", "SD_DATA2", "n/a", "n/a",
+ "GPP_G4", "SD_DATA3", "n/a", "n/a",
+ "GPP_G5", "SD_CD#", "n/a", "n/a",
+ "GPP_G6", "SD_CLK", "n/a", "n/a",
+ "GPP_G7", "SD_WP", "n/a", "n/a",
+};
+
+static const struct gpio_group sunrise_lp_group_g = {
+ .display = "------- GPIO Group GPP_G -------",
+ .pad_count = ARRAY_SIZE(sunrise_lp_group_g_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_lp_group_g_names,
+};
+
+static const char *const sunrise_group_h_names[] = {
+ "GPP_H0", "SRCCLKREQ6#", "n/a", "n/a",
+ "GPP_H1", "SRCCLKREQ7#", "n/a", "n/a",
+ "GPP_H2", "SRCCLKREQ8#", "n/a", "n/a",
+ "GPP_H3", "SRCCLKREQ9#", "n/a", "n/a",
+ "GPP_H4", "SRCCLKREQ10#", "n/a", "n/a",
+ "GPP_H5", "SRCCLKREQ11#", "n/a", "n/a",
+ "GPP_H6", "SRCCLKREQ12#", "n/a", "n/a",
+ "GPP_H7", "SRCCLKREQ13#", "n/a", "n/a",
+ "GPP_H8", "SRCCLKREQ14#", "n/a", "n/a",
+ "GPP_H9", "SRCCLKREQ15#", "n/a", "n/a",
+ "GPP_H10", "SML2CLK", "n/a", "n/a",
+ "GPP_H11", "SML2DATA", "n/a", "n/a",
+ "GPP_H12", "SML2ALERT#", "n/a", "n/a",
+ "GPP_H13", "SML3CLK", "n/a", "n/a",
+ "GPP_H14", "SML3DATA", "n/a", "n/a",
+ "GPP_H15", "SML3ALERT#", "n/a", "n/a",
+ "GPP_H16", "SML4CLK", "n/a", "n/a",
+ "GPP_H17", "SML4DATA", "n/a", "n/a",
+ "GPP_H18", "SML4ALERT#", "n/a", "n/a",
+ "GPP_H19", "ISH_I2C0_SDA", "n/a", "n/a",
+ "GPP_H20", "ISH_I2C0_SCL", "n/a", "n/a",
+ "GPP_H21", "ISH_I2C1_SDA", "n/a", "n/a",
+ "GPP_H22", "ISH_I2C1_SCL", "n/a", "n/a",
+ "GPP_H23", "n/a", "n/a", "n/a",
+};
+
+static const struct gpio_group sunrise_group_h = {
+ .display = "------- GPIO Group GPP_H -------",
+ .pad_count = ARRAY_SIZE(sunrise_group_h_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_group_h_names,
+};
+
+static const struct gpio_group *const sunrise_community_cdefgh_groups[] = {
+ &sunrise_group_c, &sunrise_group_d, &sunrise_group_e,
+ &sunrise_group_f, &sunrise_group_g, &sunrise_group_h,
+};
+
+static const struct gpio_group *const sunrise_lp_community_cde_groups[] = {
+ &sunrise_group_c, &sunrise_lp_group_d, &sunrise_lp_group_e,
+};
+
+static const struct gpio_community sunrise_community_cdefgh = {
+ .name = "------- GPIO Community 1 -------",
+ .pcr_port_id = 0xae,
+ .group_count = ARRAY_SIZE(sunrise_community_cdefgh_groups),
+ .groups = sunrise_community_cdefgh_groups,
+};
+
+static const struct gpio_community sunrise_lp_community_cde = {
+ .name = "------- GPIO Community 1 -------",
+ .pcr_port_id = 0xae,
+ .group_count = ARRAY_SIZE(sunrise_lp_community_cde_groups),
+ .groups = sunrise_lp_community_cde_groups,
+};
+
+static const char *const sunrise_group_gpd_names[] = {
+ "GPD0", "BATLOW#", "n/a", "n/a",
+ "GPD1", "ACPRESENT", "n/a", "n/a",
+ "GPD2", "LAN_WAKE#", "n/a", "n/a",
+ "GPD3", "PWRBTN#", "n/a", "n/a",
+ "GPD4", "SLP_S3#", "n/a", "n/a",
+ "GPD5", "SLP_S4#", "n/a", "n/a",
+ "GPD6", "SLP_A#", "n/a", "n/a",
+ "GPD7", "RESERVED", "n/a", "n/a",
+ "GPD8", "SUSCLK", "n/a", "n/a",
+ "GPD9", "SLP_WLAN#", "n/a", "n/a",
+ "GPD10", "SLP_S5#", "n/a", "n/a",
+ "GPD11", "LANPHYPC", "n/a", "n/a",
+};
+
+static const struct gpio_group sunrise_group_gpd = {
+ .display = "-------- GPIO Group GPD --------",
+ .pad_count = ARRAY_SIZE(sunrise_group_gpd_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_group_gpd_names,
+};
+
+static const struct gpio_group *const sunrise_community_gpd_groups[] = {
+ &sunrise_group_gpd,
+};
+
+static const struct gpio_community sunrise_community_gpd = {
+ .name = "------- GPIO Community 2 -------",
+ .pcr_port_id = 0xad,
+ .group_count = ARRAY_SIZE(sunrise_community_gpd_groups),
+ .groups = sunrise_community_gpd_groups,
+};
+
+static const char *const sunrise_group_i_names[] = {
+ "GPP_I0", "DDPB_HPD0", "n/a", "n/a",
+ "GPP_I1", "DDPC_HPD1", "n/a", "n/a",
+ "GPP_I2", "DDPD_HPD2", "n/a", "n/a",
+ "GPP_I3", "DDPE_HPD3", "n/a", "n/a",
+ "GPP_I4", "EDP_HPD", "n/a", "n/a",
+ "GPP_I5", "DDPB_CTRLCLK", "n/a", "n/a",
+ "GPP_I6", "DDPB_CTRLDATA", "n/a", "n/a",
+ "GPP_I7", "DDPC_CTRLCLK", "n/a", "n/a",
+ "GPP_I8", "DDPC_CTRLDATA", "n/a", "n/a",
+ "GPP_I9", "DDPD_CTRLCLK", "n/a", "n/a",
+ "GPP_I10", "DDPD_CTRLDATA", "n/a", "n/a",
+};
+
+static const struct gpio_group sunrise_group_i = {
+ .display = "------- GPIO Group GPP_I -------",
+ .pad_count = ARRAY_SIZE(sunrise_group_i_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_group_i_names,
+};
+
+static const struct gpio_group *const sunrise_community_i_groups[] = {
+ &sunrise_group_i,
+};
+
+static const struct gpio_group *const sunrise_lp_community_fg_groups[] = {
+ &sunrise_lp_group_f, &sunrise_lp_group_g,
+};
+
+static const struct gpio_community sunrise_community_i = {
+ .name = "------- GPIO Community 3 -------",
+ .pcr_port_id = 0xac,
+ .group_count = ARRAY_SIZE(sunrise_community_i_groups),
+ .groups = sunrise_community_i_groups,
+};
+
+static const struct gpio_community sunrise_lp_community_fg = {
+ .name = "------- GPIO Community 3 -------",
+ .pcr_port_id = 0xac,
+ .group_count = ARRAY_SIZE(sunrise_lp_community_fg_groups),
+ .groups = sunrise_lp_community_fg_groups,
+};
+
+static const struct gpio_community *const sunrise_communities[] = {
+ &sunrise_community_ab, &sunrise_community_cdefgh,
+ &sunrise_community_gpd, &sunrise_community_i,
+};
+
+static const struct gpio_community *const sunrise_lp_communities[] = {
+ &sunrise_lp_community_ab, &sunrise_lp_community_cde,
+ &sunrise_community_gpd, &sunrise_lp_community_fg,
+};
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ic61871f5cf95ac3da93892fa2f7721e682176c8d
Gerrit-Change-Number: 31504
Gerrit-PatchSet: 1
Gerrit-Owner: Felix Singer <migy(a)darmstadt.ccc.de>
Gerrit-MessageType: newchange
1 week, 1 day
- 7
- 34
Change in coreboot[master]: sb/nvidia/{ck804,mcp55}: Use new device references for MAC EEPROM
by Nico Huber (Code Review)
Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35489 )
Change subject: sb/nvidia/{ck804,mcp55}: Use new device references for MAC EEPROM
......................................................................
sb/nvidia/{ck804,mcp55}: Use new device references for MAC EEPROM
Instead of using fragile dev_find_slot_on_smbus(), link the devices
in the devicetree directly.
msi/ms9652 referenced a non-existing device (commented), so remove
the reference entirely.
Change-Id: I050e681142c5b19f97fec865e887eda157ee830b
Signed-off-by: Nico Huber <nico.huber(a)secunet.com>
---
M src/mainboard/msi/ms9652_fam10/devicetree.cb
M src/mainboard/supermicro/h8dmr_fam10/devicetree.cb
M src/mainboard/supermicro/h8qme_fam10/devicetree.cb
M src/mainboard/tyan/s2912_fam10/devicetree.cb
M src/southbridge/nvidia/ck804/chip.h
M src/southbridge/nvidia/ck804/nic.c
M src/southbridge/nvidia/mcp55/chip.h
M src/southbridge/nvidia/mcp55/nic.c
8 files changed, 56 insertions(+), 77 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/35489/1
diff --git a/src/mainboard/msi/ms9652_fam10/devicetree.cb b/src/mainboard/msi/ms9652_fam10/devicetree.cb
index c6dae6d..1815870 100644
--- a/src/mainboard/msi/ms9652_fam10/devicetree.cb
+++ b/src/mainboard/msi/ms9652_fam10/devicetree.cb
@@ -149,9 +149,6 @@
register "ide0_enable" = "1"
register "sata0_enable" = "1"
register "sata1_enable" = "1"
- # 1: SMBus under 2e.8, 2: SM0 3: SM1
- register "mac_eeprom_smbus" = "3"
- register "mac_eeprom_addr" = "0x51"
end
end
device pci 18.0 on end # HT 1.0
diff --git a/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb b/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb
index ee88c31..89c579e 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb
+++ b/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb
@@ -103,7 +103,7 @@
# device i2c 55 on end
# end
chip drivers/generic/generic # MAC EEPROM
- device i2c 51 on end
+ device i2c 51 alias mac on end
end
end
device pci 2.0 on end # USB 1.1
@@ -133,9 +133,7 @@
register "ide0_enable" = "1"
register "sata0_enable" = "1"
register "sata1_enable" = "1"
- # 1: SMBus under 2e.8, 2: SM0 3: SM1
- register "mac_eeprom_smbus" = "3"
- register "mac_eeprom_addr" = "0x51"
+ use mac as mac_eeprom
end
end
device pci 18.1 on end
diff --git a/src/mainboard/supermicro/h8qme_fam10/devicetree.cb b/src/mainboard/supermicro/h8qme_fam10/devicetree.cb
index 317d643..de78ce2 100644
--- a/src/mainboard/supermicro/h8qme_fam10/devicetree.cb
+++ b/src/mainboard/supermicro/h8qme_fam10/devicetree.cb
@@ -56,11 +56,8 @@
end
device pci 1.1 on end
device pci 1.1 on # SM 1
- # PCI device SMBus address will
- # depend on addon PCI device, do
- # we need to scan_smbus_bus?
chip drivers/generic/generic # MAC EEPROM
- device i2c 51 on end
+ device i2c 51 alias mac on end
end
end
device pci 2.0 on end # USB 1.1
@@ -84,9 +81,7 @@
register "ide0_enable" = "1"
register "sata0_enable" = "1"
register "sata1_enable" = "1"
- # 1: SMBus under 2e.8, 2: SM0 3: SM1
- register "mac_eeprom_smbus" = "3"
- register "mac_eeprom_addr" = "0x51"
+ use mac as mac_eeprom
end
end
device pci 18.1 on end
diff --git a/src/mainboard/tyan/s2912_fam10/devicetree.cb b/src/mainboard/tyan/s2912_fam10/devicetree.cb
index e49e16b..4a4118e 100644
--- a/src/mainboard/tyan/s2912_fam10/devicetree.cb
+++ b/src/mainboard/tyan/s2912_fam10/devicetree.cb
@@ -103,7 +103,7 @@
# device i2c 55 on end
# end
chip drivers/generic/generic # MAC EEPROM
- device i2c 51 on end
+ device i2c 51 alias mac on end
end
end
device pci 2.0 on end # USB 1.1
@@ -127,9 +127,7 @@
register "ide0_enable" = "1"
register "sata0_enable" = "1"
register "sata1_enable" = "1"
- # 1: SMBus under 2e.8, 2: SM0 3: SM1
- register "mac_eeprom_smbus" = "3"
- register "mac_eeprom_addr" = "0x51"
+ use mac as mac_eeprom
end
end
device pci 18.1 on end
diff --git a/src/southbridge/nvidia/ck804/chip.h b/src/southbridge/nvidia/ck804/chip.h
index b1676ce..16fdbde 100644
--- a/src/southbridge/nvidia/ck804/chip.h
+++ b/src/southbridge/nvidia/ck804/chip.h
@@ -17,14 +17,15 @@
#ifndef SOUTHBRIDGE_NVIDIA_CK804_CHIP_H
#define SOUTHBRIDGE_NVIDIA_CK804_CHIP_H
+#include <device/device.h>
+
struct southbridge_nvidia_ck804_config {
unsigned int usb1_hc_reset : 1;
unsigned int ide0_enable : 1;
unsigned int ide1_enable : 1;
unsigned int sata0_enable : 1;
unsigned int sata1_enable : 1;
- unsigned int mac_eeprom_smbus;
- unsigned int mac_eeprom_addr;
+ DEVTREE_CONST struct device *mac_eeprom;
};
extern struct pci_operations ck804_pci_ops;
diff --git a/src/southbridge/nvidia/ck804/nic.c b/src/southbridge/nvidia/ck804/nic.c
index 5dbb6b4..188dc23 100644
--- a/src/southbridge/nvidia/ck804/nic.c
+++ b/src/southbridge/nvidia/ck804/nic.c
@@ -47,37 +47,31 @@
conf = dev->chip_info;
- if (conf->mac_eeprom_smbus != 0) {
+ if (conf->mac_eeprom) {
/* Read MAC address from EEPROM at first. */
- struct device *dev_eeprom;
- dev_eeprom = dev_find_slot_on_smbus(conf->mac_eeprom_smbus,
- conf->mac_eeprom_addr);
-
- if (dev_eeprom) {
- /* If that is valid we will use that. */
- unsigned char dat[6];
- int i, status;
- for (i = 0; i < 6; i++) {
- status = smbus_read_byte(dev_eeprom, i);
- if (status < 0)
- break;
- dat[i] = status & 0xff;
+ /* If that is valid we will use that. */
+ unsigned char dat[6];
+ int i, status;
+ for (i = 0; i < 6; i++) {
+ status = smbus_read_byte(conf->mac_eeprom, i);
+ if (status < 0)
+ break;
+ dat[i] = status & 0xff;
+ }
+ if (status >= 0) {
+ mac_l = 0;
+ for (i = 3; i >= 0; i--) {
+ mac_l <<= 8;
+ mac_l += dat[i];
}
- if (status >= 0) {
- mac_l = 0;
- for (i = 3; i >= 0; i--) {
- mac_l <<= 8;
- mac_l += dat[i];
+ if (mac_l != 0xffffffff) {
+ mac_l += nic_index;
+ mac_h = 0;
+ for (i = 5; i >= 4; i--) {
+ mac_h <<= 8;
+ mac_h += dat[i];
}
- if (mac_l != 0xffffffff) {
- mac_l += nic_index;
- mac_h = 0;
- for (i = 5; i >= 4; i--) {
- mac_h <<= 8;
- mac_h += dat[i];
- }
- eeprom_valid = 1;
- }
+ eeprom_valid = 1;
}
}
}
diff --git a/src/southbridge/nvidia/mcp55/chip.h b/src/southbridge/nvidia/mcp55/chip.h
index 4bc8428..36eea22 100644
--- a/src/southbridge/nvidia/mcp55/chip.h
+++ b/src/southbridge/nvidia/mcp55/chip.h
@@ -18,14 +18,15 @@
#ifndef SOUTHBRIDGE_NVIDIA_MCP55_CHIP_H
#define SOUTHBRIDGE_NVIDIA_MCP55_CHIP_H
+#include <device/device.h>
+
struct southbridge_nvidia_mcp55_config
{
unsigned int ide0_enable : 1;
unsigned int ide1_enable : 1;
unsigned int sata0_enable : 1;
unsigned int sata1_enable : 1;
- unsigned int mac_eeprom_smbus;
- unsigned int mac_eeprom_addr;
+ DEVTREE_CONST struct device *mac_eeprom;
};
#endif
diff --git a/src/southbridge/nvidia/mcp55/nic.c b/src/southbridge/nvidia/mcp55/nic.c
index af4df44..b562503 100644
--- a/src/southbridge/nvidia/mcp55/nic.c
+++ b/src/southbridge/nvidia/mcp55/nic.c
@@ -124,36 +124,31 @@
conf = dev->chip_info;
- if (conf->mac_eeprom_smbus != 0) {
+ if (conf->mac_eeprom) {
// read MAC address from EEPROM at first
- struct device *dev_eeprom;
- dev_eeprom = dev_find_slot_on_smbus(conf->mac_eeprom_smbus, conf->mac_eeprom_addr);
-
- if (dev_eeprom) {
- // if that is valid we will use that
- unsigned char dat[6];
- int status;
- int i;
- for (i=0;i<6;i++) {
- status = smbus_read_byte(dev_eeprom, i);
- if (status < 0) break;
- dat[i] = status & 0xff;
+ // if that is valid we will use that
+ unsigned char dat[6];
+ int status;
+ int i;
+ for (i=0;i<6;i++) {
+ status = smbus_read_byte(conf->mac_eeprom, i);
+ if (status < 0) break;
+ dat[i] = status & 0xff;
+ }
+ if (status >= 0) {
+ mac_l = 0;
+ for (i=3;i>=0;i--) {
+ mac_l <<= 8;
+ mac_l += dat[i];
}
- if (status >= 0) {
- mac_l = 0;
- for (i=3;i>=0;i--) {
- mac_l <<= 8;
- mac_l += dat[i];
+ if (mac_l != 0xffffffff) {
+ mac_l += nic_index;
+ mac_h = 0;
+ for (i=5;i>=4;i--) {
+ mac_h <<= 8;
+ mac_h += dat[i];
}
- if (mac_l != 0xffffffff) {
- mac_l += nic_index;
- mac_h = 0;
- for (i=5;i>=4;i--) {
- mac_h <<= 8;
- mac_h += dat[i];
- }
- eeprom_valid = 1;
- }
+ eeprom_valid = 1;
}
}
}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I050e681142c5b19f97fec865e887eda157ee830b
Gerrit-Change-Number: 35489
Gerrit-PatchSet: 1
Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>
Gerrit-MessageType: newchange
1 week, 3 days
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