Change in coreboot[master]: mb/acer/aspire_vn7_572g: Adds support for an Acer laptop Adds initial...
by Benjamin Doron (Code Review)
Benjamin Doron has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35523 )
Change subject: mb/acer/aspire_vn7_572g: Adds support for an Acer laptop Adds initial, rudimentary support for Acer Aspire VN7-572G. May not boot correctly or at all. For testing purposes only.
......................................................................
mb/acer/aspire_vn7_572g: Adds support for an Acer laptop
Adds initial, rudimentary support for Acer Aspire VN7-572G. May not boot correctly or at all. For testing purposes only.
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6
Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com>
---
A src/mainboard/acer/Kconfig
A src/mainboard/acer/Kconfig.name
A src/mainboard/acer/aspire_vn7_572g/Kconfig
A src/mainboard/acer/aspire_vn7_572g/Kconfig.name
A src/mainboard/acer/aspire_vn7_572g/Makefile.inc
A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl
A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl
A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl
A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl
A src/mainboard/acer/aspire_vn7_572g/acpi_tables.c
A src/mainboard/acer/aspire_vn7_572g/board_info.txt
A src/mainboard/acer/aspire_vn7_572g/devicetree.cb
A src/mainboard/acer/aspire_vn7_572g/dsdt.asl
A src/mainboard/acer/aspire_vn7_572g/gpio.h
A src/mainboard/acer/aspire_vn7_572g/hda_verb.c
A src/mainboard/acer/aspire_vn7_572g/mainboard.c
A src/mainboard/acer/aspire_vn7_572g/ramstage.c
A src/mainboard/acer/aspire_vn7_572g/romstage.c
18 files changed, 1,282 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/1
diff --git a/src/mainboard/acer/Kconfig b/src/mainboard/acer/Kconfig
new file mode 100644
index 0000000..f56a2a2
--- /dev/null
+++ b/src/mainboard/acer/Kconfig
@@ -0,0 +1,16 @@
+if VENDOR_ACER
+
+choice
+ prompt "Mainboard model"
+
+source "src/mainboard/acer/*/Kconfig.name"
+
+endchoice
+
+source "src/mainboard/acer/*/Kconfig"
+
+config MAINBOARD_VENDOR
+ string "Mainboard Vendor"
+ default "Acer"
+
+endif # VENDOR_ACER
diff --git a/src/mainboard/acer/Kconfig.name b/src/mainboard/acer/Kconfig.name
new file mode 100644
index 0000000..bb177f9
--- /dev/null
+++ b/src/mainboard/acer/Kconfig.name
@@ -0,0 +1,2 @@
+config VENDOR_ACER
+ bool "Acer"
diff --git a/src/mainboard/acer/aspire_vn7_572g/Kconfig b/src/mainboard/acer/aspire_vn7_572g/Kconfig
new file mode 100644
index 0000000..4b3c127
--- /dev/null
+++ b/src/mainboard/acer/aspire_vn7_572g/Kconfig
@@ -0,0 +1,68 @@
+if BOARD_ACER_VN7_572G
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select SYSTEM_TYPE_LAPTOP
+ select BOARD_ROMSIZE_KB_8192
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+ select SOC_INTEL_SKYLAKE
+ select MAINBOARD_USES_FSP2_0
+ select SPD_READ_BY_WORD
+ select MAINBOARD_HAS_LPC_TPM
+ select NO_POST # This platform has no way to see POST codes so disable them by default.
+
+config IRQ_SLOT_COUNT
+ int
+ default 18
+
+config MAINBOARD_VENDOR
+ string
+ default "Acer"
+
+config MAINBOARD_FAMILY
+ string
+ default "Aspire V Nitro"
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "Aspire VN7-572G"
+
+config MAINBOARD_DIR
+ string
+ default "acer/aspire_vn7_572g"
+
+config DEVICETREE
+ string
+ default "devicetree.cb"
+
+config MAX_CPUS
+ int
+ default 4
+
+config VGA_BIOS_ID
+ string
+ default "8086,1916"
+
+config DIMM_MAX
+ int
+ default 2
+
+config DIMM_SPD_SIZE
+ int
+ default 512
+
+config CPU_MICROCODE_CBFS_LEN
+ hex
+ default 0x18000
+
+config CPU_MICROCODE_CBFS_LOC
+ hex
+ default 0xFFE115A0
+
+config CBFS_SIZE
+ hex
+ default 0x5c0000
+
+endif
diff --git a/src/mainboard/acer/aspire_vn7_572g/Kconfig.name b/src/mainboard/acer/aspire_vn7_572g/Kconfig.name
new file mode 100644
index 0000000..b881680
--- /dev/null
+++ b/src/mainboard/acer/aspire_vn7_572g/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_ACER_VN7_572G
+ bool "Aspire VN7-572G"
diff --git a/src/mainboard/acer/aspire_vn7_572g/Makefile.inc b/src/mainboard/acer/aspire_vn7_572g/Makefile.inc
new file mode 100644
index 0000000..35f0f6c
--- /dev/null
+++ b/src/mainboard/acer/aspire_vn7_572g/Makefile.inc
@@ -0,0 +1,17 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2015 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+ramstage-y += ramstage.c
+ramstage-y += hda_verb.c
diff --git a/src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl b/src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl
new file mode 100644
index 0000000..2eed489
--- /dev/null
+++ b/src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl
@@ -0,0 +1,328 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Name (EMBA, 0xFE800000)
+
+Device (EC0)
+{
+ Name (_HID, EisaId ("PNP0C09")) /* Embedded Controller Device */ // _HID: Hardware ID
+
+ Name (_GPE, 0x50) // _GPE: General Purpose Events
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (0x0F)
+ }
+
+ Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
+ IO (Decode16, 0x62, 0x62, 0, 1) // Range Minimum, Range Maximum, Alignment, Length
+ IO (Decode16, 0x66, 0x66, 0, 1) // Range Minimum, Range Maximum, Alignment, Length
+ })
+ OperationRegion (ECO1, SystemIO, 0x62, One)
+ Field (ECO1, ByteAcc, Lock, Preserve)
+ {
+ PX62, 8
+ }
+
+ OperationRegion (ECO2, SystemIO, 0x66, One)
+ Field (ECO2, ByteAcc, Lock, Preserve)
+ {
+ PX66, 8
+ }
+
+ OperationRegion (ECMB, SystemMemory, EMBA, 0x0200)
+ OperationRegion (RAM, EmbeddedControl, Zero, 0xFF)
+ Field (RAM, ByteAcc, Lock, Preserve)
+ {
+ CMDB, 8,
+ Offset (0x06),
+ CMD2, 8,
+ CMD1, 8,
+ CMD0, 8,
+ Offset (0x0A),
+ , 1, /* Reserved */
+ , 1, /* Reserved */
+ Offset (0x10),
+ EQEN, 1,
+ , 1, /* Reserved */
+ Offset (0x4E),
+ ISEN, 1, /* Sense? (0=Not Exist, 1=Exist) */
+ Offset (0x51),
+ , 3, /* Reserved */
+ TPEN, 1,
+ Offset (0x52),
+ WLEX, 1, /* Wireless LAN (0=Not Exist, 1=Exist) */
+ BTEX, 1, /* Bluetooth? (0=Not Exist, 1=Exist) */
+ EX3G, 1, /* 3G (0=Not Exist, 1=Exist) */
+ , 3, /* Reserved */
+ RFEX, 1,
+ Offset (0x57),
+ , 7, /* Reserved */
+ AHKB, 1,
+ AHKE, 8,
+ Offset (0x5C),
+ Offset (0x5D),
+ Offset (0x70),
+ , 1, /* Reserved */
+ KLID, 1, /* LID? */
+ , 3, /* Reserved */
+ KACS, 1, /* AC power? */
+ Offset (0x71),
+ WLEN, 1, /* Wireless LAN (0=Not Enabled, 1=Enabled) */
+ BTEN, 1, /* Bluetooth (0=Not Enabled, 1=Enabled) */
+ , 3, /* Reserved */
+ ISS3, 1,
+ ISS4, 1,
+ ISS5, 1,
+ Offset (0x74),
+ , 2, /* Reserved */
+ , 1, /* Reserved */
+ TPEX, 1,
+ Offset (0x75),
+ BLST, 1,
+ LMIB, 1,
+ Offset (0x76),
+ ECSS, 4,
+ EOSS, 4
+ }
+
+ Method (_REG, 2, NotSerialized) // _REG: Region Availability
+ {
+ /* Initialize AC power state */
+ Store (KACS, \PWRS)
+
+ /* Initialize LID switch state */
+ Store (KLID, \LIDS)
+ }
+
+ /* KEY_BRIGHTNESSUP */
+ Method (_Q1C, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ Notify (^^^GFX0.DD1F, 0x86) // Device-Specific
+ }
+
+ /* KEY_BRIGHTNESSDOWN */
+ Method (_Q1D, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ Notify (^^^GFX0.DD1F, 0x87) // Device-Specific
+ }
+
+ /* Battery Information Event */
+ Method (_Q40, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ Notify (BAT0, 0x81) // Information Change
+ }
+
+ /* AC event */
+ Method (_Q50, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ Notify (ADP1, 0x80) // Status Change
+ }
+
+ /* Lid event */
+ Method (_Q52, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ Notify (LID0, 0x80) // Status Change
+ }
+
+ /* Battery Information Event */
+ Method (_Q41, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ Notify (BAT0, 0x81) // Information Change
+ }
+
+ /* Battery Status Event */
+ Method (_Q48, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ Notify (BAT0, 0x80) // Status Change
+ }
+
+ Method (ECWK, 1, NotSerialized)
+ {
+ EQEN = One
+ Notify (BAT0, 0x81) // Information Change
+ If (((Arg0 == 0x03) || (Arg0 == 0x04)))
+ {
+ Notify (SLPB, 0x02) // Device Wake
+ }
+ }
+
+ Name (B0ST, Zero)
+ Field (ECMB, ByteAcc, Lock, Preserve)
+ {
+ Offset (0x08),
+ MB0S, 8
+ }
+
+ OperationRegion (MBB0, SystemMemory, (EMBA + 0x80), 0xFF)
+ Field (MBB0, ByteAcc, Lock, Preserve)
+ {
+ MBRC, 16,
+ MBFC, 16,
+ MBPE, 16,
+ MBAC, 16,
+ MBVO, 16,
+ , 15,
+ MBCM, 1,
+ MBCU, 16,
+ MBTV, 16
+ }
+
+ Method (GBIF, 3, NotSerialized)
+ {
+ If (Arg2)
+ {
+ Arg1 [One] = 0xFFFFFFFF
+ Arg1 [0x02] = 0xFFFFFFFF
+ Arg1 [0x04] = 0xFFFFFFFF
+ Arg1 [0x05] = Zero
+ Arg1 [0x06] = Zero
+ }
+
+ Return (Arg1)
+ }
+
+ Method (GBST, 4, NotSerialized)
+ {
+ Local0 = Zero
+
+ If ((Arg1 & One))
+ {
+ Local1 = MBAC /* \_SB_.PCI0.LPCB.EC0_.MBAC */
+ Local2 = MBRC /* \_SB_.PCI0.LPCB.EC0_.MBRC */
+ If (ACST)
+ {
+ If ((Arg1 & 0x20))
+ {
+ Local2 = MBFC /* \_SB_.PCI0.LPCB.EC0_.MBFC */
+ }
+ }
+
+ Local3 = MBVO /* \_SB_.PCI0.LPCB.EC0_.MBVO */
+ If ((Local1 >= 0x8000))
+ {
+ If ((Local0 & One))
+ {
+ Local1 = (0x00010000 - Local1)
+ }
+ Else
+ {
+ Local1 = Zero
+ }
+ }
+
+ If (Arg2)
+ {
+ Local1 *= Local3
+ Divide (Local1, 0x03E8, Local1)
+ }
+ }
+ Else
+ {
+ Local0 = Zero
+ Local1 = 0xFFFFFFFF
+ Local2 = 0xFFFFFFFF
+ Local3 = 0xFFFFFFFF
+ }
+
+ Arg3 [Zero] = Local0
+ Arg3 [One] = Local1
+ Arg3 [0x02] = Local2
+ Arg3 [0x03] = Local3
+ Return (Arg3)
+ }
+
+ Name (ACST, One)
+ Device (ADP1)
+ {
+ Name (_HID, "ACPI0003") /* Power Source Device */ // _HID: Hardware ID
+ Name (_PCL, Package () { \_SB }) // _PCL: Power Consumer List
+ Method (_PSR) // _PSR: Power Source
+ {
+ Return (\PWRS)
+ }
+ Method (_STA) // _STA: Status
+ {
+ Return (0x0F)
+ }
+ }
+
+ Device (BAT0)
+ {
+ Name (_HID, EisaId ("PNP0C0A")) /* Control Method Battery */ // _HID: Hardware ID
+ Name (_UID, Zero) // _UID: Unique ID
+ Method (_PCL, 0, NotSerialized) // _PCL: Power Consumer List
+ {
+ Return (_SB) /* \_SB_ */
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ If (B0ST)
+ {
+ Return (0x1F)
+ }
+ Else
+ {
+ Return (0x0F)
+ }
+ }
+
+ Name (B0IP, Package (0x0D)
+ {
+ 0x00000001, /* 0x00: Power Unit: mAH */
+ 0xFFFFFFFF, /* 0x01: Design Capacity */
+ 0xFFFFFFFF, /* 0x02: Last Full Charge Capacity */
+ 0x00000001, /* 0x03: Battery Technology: Rechargeable */
+ 0xFFFFFFFF, /* 0x04: Design Voltage */
+ 0x00000000, /* 0x05: Design Capacity of Warning */
+ 0x00000000, /* 0x06: Design Capacity of Low */
+ 0x00000001, /* 0x07: Capacity Granularity 1 */
+ 0x00000001, /* 0x08: Capacity Granularity 2 */
+ "", /* 0x09: Model Number */
+ "100", /* 0x0a: Serial Number */
+ "Lion", /* 0x0b: Battery Type */
+ 0x00000000 /* 0x0c: OEM Information */
+ })
+
+ Method (_BIF, 0, NotSerialized) // _BIF: Battery Information
+ {
+ Local6 = B0ST /* \_SB_.PCI0.LPCB.EC0_.B0ST */
+ While ((Local6))
+ {
+ Local1 = MB0S /* \_SB_.PCI0.LPCB.EC0_.MB0S */
+ If ((Local1 & 0x08))
+ {
+ Local6 = Zero
+ }
+ }
+
+ Return (GBIF (Zero, B0IP, Local6))
+ }
+
+ Name (B0SP, Package (0x04)
+ {
+ 0x00000000, /* 0x00: Battery State */
+ 0xFFFFFFFF, /* 0x01: Battery Present Rate */
+ 0xFFFFFFFF, /* 0x02: Battery Remaining Capacity */
+ 0xFFFFFFFF /* 0x03: Battery Present Voltage */
+ })
+
+ Method (_BST, 0, NotSerialized) // _BST: Battery Status
+ {
+ Local0 = (DerefOf (B0IP [Zero]) ^ One)
+ Return (GBST (Zero, MB0S, Local0, B0SP))
+ }
+ }
+}
diff --git a/src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl b/src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl
new file mode 100644
index 0000000..e145a2b
--- /dev/null
+++ b/src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl
@@ -0,0 +1,68 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+OperationRegion (SANV, SystemMemory, 0x7CE5FD98, Zero)
+Field (SANV, AnyAcc, Lock, Preserve)
+{
+ BRTL, 8
+}
+
+Scope (\_SB.PCI0)
+{
+ Device (GFX0)
+ {
+ Name (_ADR, 0x00020000) // _ADR: Address
+
+ Device (DD1F)
+ {
+ Method (_ADR, 0, Serialized) // _ADR: Address
+ {
+ Return (0x1F)
+ }
+
+ Method (_BCL, 0, NotSerialized) // _BCL: Brightness Control Levels
+ {
+ Return (Package (0x0C)
+ {
+ 0x50,
+ 0x32,
+ 0x0A,
+ 0x14,
+ 0x1E,
+ 0x28,
+ 0x32,
+ 0x3C,
+ 0x46,
+ 0x50,
+ 0x5A,
+ 0x64
+ })
+ }
+
+ Method (_BCM, 1, NotSerialized) // _BCM: Brightness Control Method
+ {
+ If (((Arg0 >= Zero) && (Arg0 <= 0x64)))
+ {
+ BRTL = Arg0
+ }
+ }
+
+ Method (_BQC, 0, NotSerialized) // _BQC: Brightness Query Current
+ {
+ Return (BRTL) /* \BRTL */
+ }
+ }
+ }
+}
diff --git a/src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl b/src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl
new file mode 100644
index 0000000..90e75f2
--- /dev/null
+++ b/src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl
@@ -0,0 +1,54 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Scope (\_SB)
+{
+ Device (LID0) /* Lid Device */
+ {
+ Name (_HID, EisaId ("PNP0C0D"))
+
+ Method (_STA) // _STA: Status
+ {
+ Return (0xF)
+ }
+
+ Method (_LID) // _LID: Lid Status
+ {
+ Return (\LIDS)
+ }
+ }
+
+ Device (PWRB)
+ {
+ Name (_HID, EisaId ("PNP0C0C"))
+
+ Method (_STA)
+ {
+ Return (0xF)
+ }
+
+ Name (_PRW, Package () { 27, 4 })
+ }
+
+ Device (SLPB) /* Sleep Button Device */ // _HID: Hardware ID
+ {
+ Name (_HID, EisaId ("PNP0C0E"))
+
+ Method (_STA) // _STA: Status
+ {
+ Return (0xF)
+ }
+ }
+}
diff --git a/src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl b/src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl
new file mode 100644
index 0000000..92c272e
--- /dev/null
+++ b/src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl
@@ -0,0 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <drivers/pc80/pc/ps2_controller.asl>
diff --git a/src/mainboard/acer/aspire_vn7_572g/acpi_tables.c b/src/mainboard/acer/aspire_vn7_572g/acpi_tables.c
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/acer/aspire_vn7_572g/acpi_tables.c
diff --git a/src/mainboard/acer/aspire_vn7_572g/board_info.txt b/src/mainboard/acer/aspire_vn7_572g/board_info.txt
new file mode 100644
index 0000000..f16707e
--- /dev/null
+++ b/src/mainboard/acer/aspire_vn7_572g/board_info.txt
@@ -0,0 +1,8 @@
+Vendor name: Acer
+Board name: Aspire VN7-572G
+Category: laptop
+ROM package: SOIC8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
+Release year: 2015
diff --git a/src/mainboard/acer/aspire_vn7_572g/devicetree.cb b/src/mainboard/acer/aspire_vn7_572g/devicetree.cb
new file mode 100644
index 0000000..f38b0b8
--- /dev/null
+++ b/src/mainboard/acer/aspire_vn7_572g/devicetree.cb
@@ -0,0 +1,218 @@
+chip soc/intel/skylake
+
+ # Disable deep Sx states
+ register "deep_s3_enable_ac" = "0"
+ register "deep_s3_enable_dc" = "0"
+ register "deep_s5_enable_ac" = "0"
+ register "deep_s5_enable_dc" = "0"
+ register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
+
+ register "eist_enable" = "1"
+
+ # Set the Thermal Control Circuit (TCC) activaction value to 95C
+ # even though FSP integration guide says to set it to 100C for SKL-U
+ # (offset at 0), because when the TCC activates at 100C, the CPU
+ # will have already shut itself down from overheating protection.
+ register "tcc_offset" = "5" # TCC of 95C
+
+ # GPE configuration
+ # Note that GPE events called out in ASL code rely on this
+ # route. i.e. If this route changes then the affected GPE
+ # offset bits also need to be changed.
+ register "gpe0_dw0" = "GPP_C"
+ register "gpe0_dw1" = "GPP_D"
+ register "gpe0_dw2" = "GPP_E"
+
+ # EC host command ranges are in 0x60-0x66
+ register "gen1_dec" = "0x00000061"
+
+ # Enable "Intel Speed Shift Technology"
+ register "speed_shift_enable" = "1"
+
+ # Disable DPTF
+ register "dptf_enable" = "0"
+
+ # FSP Configuration
+ register "ProbelessTrace" = "0"
+ register "EnableLan" = "0"
+ register "EnableSata" = "1"
+ register "SataSalpSupport" = "1"
+ register "SataMode" = "0"
+ register "SataPortsEnable[0]" = "1"
+ register "SataPortsEnable[1]" = "1"
+ register "SataPortsEnable[2]" = "1"
+ register "SataPortsDevSlp[0]" = "0"
+ register "SataPortsDevSlp[1]" = "0"
+ register "SataPortsDevSlp[2]" = "0"
+ register "EnableAzalia" = "1"
+ register "DspEnable" = "1"
+ register "IoBufferOwnership" = "0"
+ register "EnableTraceHub" = "0"
+ register "SsicPortEnable" = "0"
+ register "SmbusEnable" = "1"
+ register "Cio2Enable" = "0"
+ register "ScsEmmcEnabled" = "0"
+ register "ScsEmmcHs400Enabled" = "0"
+ register "ScsSdCardEnabled" = "0"
+ register "PttSwitch" = "0"
+ register "SkipExtGfxScan" = "0"
+ register "Device4Enable" = "0"
+ register "HeciEnabled" = "1"
+ register "SaGv" = "0"
+ register "PmConfigSlpS3MinAssert" = "2" # 50ms
+ register "PmConfigSlpS4MinAssert" = "1" # 1s
+ register "PmConfigSlpSusMinAssert" = "3" # 500ms
+ register "PmConfigSlpAMinAssert" = "3" # 2s
+ register "PmTimerDisabled" = "0"
+
+ # EC/KBC requires continuous mode
+ register "serirq_mode" = "SERIRQ_CONTINUOUS"
+
+ register "pirqa_routing" = "PCH_IRQ11"
+ register "pirqb_routing" = "PCH_IRQ10"
+ register "pirqc_routing" = "PCH_IRQ11"
+ register "pirqd_routing" = "PCH_IRQ11"
+ register "pirqe_routing" = "PCH_IRQ11"
+ register "pirqf_routing" = "PCH_IRQ11"
+ register "pirqg_routing" = "PCH_IRQ11"
+ register "pirqh_routing" = "PCH_IRQ11"
+
+ # VR Settings Configuration for 4 Domains
+ #+----------------+-----------+-----------+-------------+----------+
+ #| Domain/Setting | SA | IA | GT Unsliced | GT |
+ #+----------------+-----------+-----------+-------------+----------+
+ #| Psi1Threshold | 20A | 20A | 20A | 20A |
+ #| Psi2Threshold | 4A | 5A | 5A | 5A |
+ #| Psi3Threshold | 1A | 1A | 1A | 1A |
+ #| Psi3Enable | 1 | 1 | 1 | 1 |
+ #| Psi4Enable | 1 | 1 | 1 | 1 |
+ #| ImonSlope | 0 | 0 | 0 | 0 |
+ #| ImonOffset | 0 | 0 | 0 | 0 |
+ #| IccMax | 7A | 34A | 35A | 35A |
+ #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
+ #+----------------+-----------+-----------+-------------+----------+
+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(4),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(7),
+ .voltage_limit = 1520,
+ }"
+
+ register "domain_vr_config[VR_IA_CORE]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(34),
+ .voltage_limit = 1520,
+ }"
+
+ register "domain_vr_config[VR_GT_UNSLICED]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(35),
+ .voltage_limit = 1520,
+ }"
+
+ register "domain_vr_config[VR_GT_SLICED]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(35),
+ .voltage_limit = 1520,
+ }"
+
+ # Enable Root Ports 1, 9 and 10
+ register "PcieRpEnable[2]" = "1"
+ register "PcieRpLtrEnable[2]" = "1"
+ register "PcieRpEnable[8]" = "1"
+ register "PcieRpLtrEnable[8]" = "1"
+ register "PcieRpEnable[9]" = "1"
+ register "PcieRpLtrEnable[9]" = "1"
+
+# register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port
+ register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-A Port (right)
+ register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-A Port (right)
+ register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" # Type-A Port (left)
+ register "usb2_ports[4]" = "USB2_PORT_FLEX(OC2)" # Bluetooth
+ register "usb2_ports[6]" = "USB2_PORT_FLEX(OC2)" # Webcam
+ register "usb2_ports[7]" = "USB2_PORT_FLEX(OC2)" # SD
+
+ # OC0 should be for Type-C but it seems to not have been wired, according to
+ # the available schematics, even though it is labeled as USB_OC_TYPEC.
+# register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (right)
+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (right)
+
+ # PL2 override 25W
+ register "tdp_pl2_override" = "25"
+
+ # Send an extra VR mailbox command for the PS4 exit issue
+ register "SendVrMbxCmd" = "2"
+
+ # Lock Down
+ register "common_soc_config" = "{
+ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+ }"
+
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+ device domain 0 on
+ device pci 00.0 on end # Host Bridge
+ device pci 02.0 on end # Integrated Graphics Device
+ device pci 14.0 on end # USB xHCI
+ device pci 14.1 on end # USB xDCI (OTG)
+ device pci 14.2 on end # Thermal Subsystem
+ device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT Redirection
+ device pci 16.4 off end # Management Engine Interface 3
+ device pci 17.0 on end # SATA
+ device pci 1c.0 on end # PCI Express Port 1
+ device pci 1c.1 off end # PCI Express Port 2
+ device pci 1c.2 off end # PCI Express Port 3
+ device pci 1c.3 off end # PCI Express Port 4
+ device pci 1c.4 off end # PCI Express Port 5
+ device pci 1c.5 off end # PCI Express Port 6
+ device pci 1c.6 off end # PCI Express Port 7
+ device pci 1c.7 off end # PCI Express Port 8
+ device pci 1d.0 on end # PCI Express Port 9
+ device pci 1d.1 on end # PCI Express Port 10
+ device pci 1d.2 off end # PCI Express Port 11
+ device pci 1d.3 off end # PCI Express Port 12
+ device pci 1f.0 on
+ chip drivers/pc80/tpm
+ device pnp 0c31.0 on end
+ end
+ end # LPC Interface
+ device pci 1f.1 off end # P2SB
+ device pci 1f.2 on end # Power Management Controller
+ device pci 1f.3 on end # Intel HDA
+ device pci 1f.4 on end # SMBus
+ device pci 1f.5 on end # PCH SPI
+ device pci 1f.6 off end # GbE
+ end
+end
diff --git a/src/mainboard/acer/aspire_vn7_572g/dsdt.asl b/src/mainboard/acer/aspire_vn7_572g/dsdt.asl
new file mode 100644
index 0000000..c9bcb7d
--- /dev/null
+++ b/src/mainboard/acer/aspire_vn7_572g/dsdt.asl
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2016 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, // DSDT revision: ACPI v2.0 and up
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20141018 // OEM revision
+)
+{
+ // Some generic macros
+ #include <soc/intel/skylake/acpi/platform.asl>
+
+ // global NVS and variables
+ #include <soc/intel/skylake/acpi/globalnvs.asl>
+
+ // CPU
+ #include <cpu/intel/common/acpi/cpu.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <soc/intel/skylake/acpi/systemagent.asl>
+ #include <soc/intel/skylake/acpi/pch.asl>
+ }
+ }
+
+ // Chipset specific sleep states
+ #include <soc/intel/skylake/acpi/sleepstates.asl>
+
+ // Mainboard specific
+ #include "acpi/mainboard.asl"
+
+ // Graphics display
+ #include "acpi/graphics.asl"
+}
diff --git a/src/mainboard/acer/aspire_vn7_572g/gpio.h b/src/mainboard/acer/aspire_vn7_572g/gpio.h
new file mode 100644
index 0000000..4d98da1
--- /dev/null
+++ b/src/mainboard/acer/aspire_vn7_572g/gpio.h
@@ -0,0 +1,201 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+#ifndef __ACPI__
+
+/* Pad configuration in ramstage. */
+static const struct pad_config gpio_table[] = {
+_PAD_CFG_STRUCT(GPP_A0, 0x44000703, 0x0), /* RCIN# */
+_PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x3c00), /* LAD0 */
+_PAD_CFG_STRUCT(GPP_A2, 0x44000702, 0x3c00), /* LAD1 */
+_PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x3c00), /* LAD2 */
+_PAD_CFG_STRUCT(GPP_A4, 0x44000702, 0x3c00), /* LAD3 */
+_PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x0), /* LFRAME# */
+_PAD_CFG_STRUCT(GPP_A6, 0x44000702, 0x0), /* SERIRQ */
+_PAD_CFG_STRUCT(GPP_A7, 0x44000702, 0x0), /* PIRQA# */
+_PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x0), /* CLKRUN# */
+_PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x1000), /* CLKOUT_LPC0 */
+_PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x1000), /* CLKOUT_LPC1 */
+_PAD_CFG_STRUCT(GPP_A11, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_A12, 0x44000100, 0x0), /* GPIO */
+_PAD_CFG_STRUCT(GPP_A13, 0x44000700, 0x0), /* SUSWARN#/SUSPWRDNACK */
+_PAD_CFG_STRUCT(GPP_A14, 0x44000700, 0x0), /* SUS_STAT# */
+_PAD_CFG_STRUCT(GPP_A15, 0x44000700, 0x1000), /* SUS_ACK# */
+_PAD_CFG_STRUCT(GPP_A16, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_A17, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_A18, 0x44000102, 0x0), /* GPIO */
+_PAD_CFG_STRUCT(GPP_A19, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_A20, 0x44000100, 0x0), /* GPIO */
+_PAD_CFG_STRUCT(GPP_A21, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_A22, 0x44000201, 0x0), /* GPIO */
+_PAD_CFG_STRUCT(GPP_A23, 0x44000201, 0x1000), /* GPIO */
+
+_PAD_CFG_STRUCT(GPP_B0, 0x44000700, 0x0), /* CORE_VID0 */
+_PAD_CFG_STRUCT(GPP_B1, 0x44000700, 0x0), /* CORE_VID1 */
+_PAD_CFG_STRUCT(GPP_B2, 0x44000100, 0x0), /* GPIO */
+_PAD_CFG_STRUCT(GPP_B3, 0x80100102, 0x0), /* GPIO */
+_PAD_CFG_STRUCT(GPP_B4, 0x44000200, 0x0), /* GPIO */
+_PAD_CFG_STRUCT(GPP_B5, 0x44000702, 0x0), /* SRCCLKREQ0# */
+_PAD_CFG_STRUCT(GPP_B6, 0x44000702, 0x0), /* SRCCLKREQ1# */
+_PAD_CFG_STRUCT(GPP_B7, 0x44000700, 0x0), /* SRCCLKREQ2# */
+_PAD_CFG_STRUCT(GPP_B8, 0x44000702, 0x0), /* SRCCLKREQ3# */
+_PAD_CFG_STRUCT(GPP_B9, 0x44000702, 0x0), /* SRCCLKREQ4# */
+_PAD_CFG_STRUCT(GPP_B10, 0x44000702, 0x0), /* SRCCLKREQ5# */
+_PAD_CFG_STRUCT(GPP_B11, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_B12, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x0), /* PLTRST# */
+_PAD_CFG_STRUCT(GPP_B14, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_B15, 0x44000200, 0x0), /* GPIO */
+_PAD_CFG_STRUCT(GPP_B16, 0x44000200, 0x0), /* GPIO */
+_PAD_CFG_STRUCT(GPP_B17, 0x42880100, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_B18, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_B19, 0x44000100, 0x0), /* GPIO */
+_PAD_CFG_STRUCT(GPP_B20, 0x44000102, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_B21, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_B22, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_B23, 0x44000201, 0x1000), /* GPIO */
+
+_PAD_CFG_STRUCT(GPP_C0, 0x44000702, 0x0), /* SMBCLK */
+_PAD_CFG_STRUCT(GPP_C1, 0x44000702, 0x1000), /* SMBDATA */
+_PAD_CFG_STRUCT(GPP_C2, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_C3, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_C4, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_C5, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_C6, 0x44000702, 0x0), /* SML1CLK */
+_PAD_CFG_STRUCT(GPP_C7, 0x44000702, 0x1000), /* SML1DATA */
+_PAD_CFG_STRUCT(GPP_C8, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_C9, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_C10, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_C11, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_C12, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_C13, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_C14, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_C15, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_C16, 0x44000702, 0x0), /* I2C0_SDA */
+_PAD_CFG_STRUCT(GPP_C17, 0x44000702, 0x0), /* I2C0_SCL */
+_PAD_CFG_STRUCT(GPP_C18, 0x44000702, 0x0), /* I2C1_SDA */
+_PAD_CFG_STRUCT(GPP_C19, 0x44000702, 0x0), /* I2C1_SCL */
+_PAD_CFG_STRUCT(GPP_C20, 0x44000702, 0x0), /* UART2_RXD */
+_PAD_CFG_STRUCT(GPP_C21, 0x44000700, 0x0), /* UART2_TXD */
+_PAD_CFG_STRUCT(GPP_C22, 0x44000700, 0x0), /* UART2_RTS# */
+_PAD_CFG_STRUCT(GPP_C23, 0x44000702, 0x0), /* UART2_CTS# */
+
+_PAD_CFG_STRUCT(GPP_D0, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_D1, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_D2, 0x44000700, 0x0), /* SPI1_MISO */
+_PAD_CFG_STRUCT(GPP_D3, 0x44000700, 0x0), /* SPI1_MOSI */
+_PAD_CFG_STRUCT(GPP_D4, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_D5, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_D6, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_D7, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_D8, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_D9, 0x40000102, 0x0), /* GPIO */
+_PAD_CFG_STRUCT(GPP_D10, 0x40000102, 0x0), /* GPIO */
+_PAD_CFG_STRUCT(GPP_D11, 0x40000102, 0x0), /* GPIO */
+_PAD_CFG_STRUCT(GPP_D12, 0x40000102, 0x0), /* GPIO */
+_PAD_CFG_STRUCT(GPP_D13, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_D14, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_D15, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_D16, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_D17, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_D18, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_D19, 0x44000700, 0x0), /* DMIC_CLK0 */
+_PAD_CFG_STRUCT(GPP_D20, 0x44000700, 0x0), /* DMIC_DATA0 */
+_PAD_CFG_STRUCT(GPP_D21, 0x44000700, 0x0), /* SPI1_IO2 */
+_PAD_CFG_STRUCT(GPP_D22, 0x44000700, 0x0), /* SPI1_IO3 */
+_PAD_CFG_STRUCT(GPP_D23, 0x44000201, 0x1000), /* GPIO */
+
+_PAD_CFG_STRUCT(GPP_E0, 0x44000700, 0x0), /* SATAXPCIE0 */
+_PAD_CFG_STRUCT(GPP_E1, 0x44000700, 0x0), /* SATAXPCIE1 */
+_PAD_CFG_STRUCT(GPP_E2, 0x44000702, 0x0), /* SATAXPCIE2 */
+_PAD_CFG_STRUCT(GPP_E3, 0x44000201, 0x0), /* GPIO */
+_PAD_CFG_STRUCT(GPP_E4, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_E5, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_E6, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_E7, 0x40900100, 0x0), /* GPIO */
+_PAD_CFG_STRUCT(GPP_E8, 0xffffffff, 0xffffff00),/* RESERVED */
+_PAD_CFG_STRUCT(GPP_E9, 0x44000702, 0x0), /* USB2_OC0# */
+_PAD_CFG_STRUCT(GPP_E10, 0x44000702, 0x0), /* USB2_OC1# */
+_PAD_CFG_STRUCT(GPP_E11, 0x44000702, 0x0), /* USB2_OC2# */
+_PAD_CFG_STRUCT(GPP_E12, 0x44000702, 0x0), /* USB2_OC3# */
+_PAD_CFG_STRUCT(GPP_E13, 0x44000700, 0x0), /* DDPB_HPD0 */
+_PAD_CFG_STRUCT(GPP_E14, 0x44000700, 0x0), /* DDPC_HPD1 */
+_PAD_CFG_STRUCT(GPP_E15, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_E16, 0x80880102, 0x0), /* GPIO */
+_PAD_CFG_STRUCT(GPP_E17, 0x44000702, 0x0), /* EDP_HPD */
+_PAD_CFG_STRUCT(GPP_E18, 0x44000702, 0x0), /* DDPB_CTRLCLK */
+_PAD_CFG_STRUCT(GPP_E19, 0x44000702, 0x1000), /* DDPB_CTRLDATA */
+_PAD_CFG_STRUCT(GPP_E20, 0x44000700, 0x0), /* DDPC_CTRLCLK */
+_PAD_CFG_STRUCT(GPP_E21, 0x44000702, 0x1000), /* DDPC_CTRLDATA */
+_PAD_CFG_STRUCT(GPP_E22, 0x40100000, 0x0), /* GPIO */
+_PAD_CFG_STRUCT(GPP_E23, 0x44000201, 0x1000), /* GPIO */
+
+_PAD_CFG_STRUCT(GPD0, 0x4000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPD1, 0x4000702, 0x0), /* ACPRESENT */
+_PAD_CFG_STRUCT(GPD2, 0x4000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPD3, 0x4000702, 0x3000), /* PWRBTN# */
+_PAD_CFG_STRUCT(GPD4, 0x4000700, 0x0), /* SLP_S3# */
+_PAD_CFG_STRUCT(GPD5, 0x4000700, 0x0), /* SLP_S4# */
+_PAD_CFG_STRUCT(GPD6, 0x4000601, 0x1000), /* SLP_A# */
+_PAD_CFG_STRUCT(GPD7, 0x4000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPD8, 0x4000700, 0x0), /* SUSCLK */
+_PAD_CFG_STRUCT(GPD9, 0x4000601, 0x1000), /* SLP_WLAN# */
+_PAD_CFG_STRUCT(GPD10, 0x4000601, 0x1000), /* SLP_S5# */
+_PAD_CFG_STRUCT(GPD11, 0x4000201, 0x1000), /* GPIO */
+
+_PAD_CFG_STRUCT(GPP_F0, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F1, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F2, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F3, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F4, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F5, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F6, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F7, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F8, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F9, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F10, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F11, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F12, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F13, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F14, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F15, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F16, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F17, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F18, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F19, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F20, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F21, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F22, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F23, 0x40100100, 0x0), /* GPIO */
+
+_PAD_CFG_STRUCT(GPP_G0, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_G1, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_G2, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_G3, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_G4, 0x44000200, 0x0), /* GPIO */
+_PAD_CFG_STRUCT(GPP_G5, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_G6, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_G7, 0x44000201, 0x1000), /* GPIO */
+};
+
+#endif
+
+#endif
diff --git a/src/mainboard/acer/aspire_vn7_572g/hda_verb.c b/src/mainboard/acer/aspire_vn7_572g/hda_verb.c
new file mode 100644
index 0000000..8cd5f97
--- /dev/null
+++ b/src/mainboard/acer/aspire_vn7_572g/hda_verb.c
@@ -0,0 +1,72 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Purism SPC.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ /* coreboot specific header */
+ 0x10ec0255, /* Codec Vendor / Device ID: Realtek ALC255 */
+ 0x10251037, /* Subsystem ID */
+ 0x0000000c, /* Number of jacks (NID entries) */
+
+ 0x0017ff00, /* Function Reset */
+ 0x0017ff00, /* Double Function Reset */
+ 0x0017ff00,
+ 0x0017ff00,
+
+ /* Bits 31:28 - Codec Address */
+ /* Bits 27:20 - NID */
+ /* Bits 19:8 - Verb ID */
+ /* Bits 7:0 - Payload */
+
+ /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x10251037 */
+ AZALIA_SUBVENDOR(0x0, 0x10251037),
+
+ /* Pin Widget Verb Table */
+
+ /* Pin Complex (NID 0x12) */
+ AZALIA_PIN_CFG(0x0, 0x12, 0x411111c0),
+
+ /* Pin Complex (NID 0x14) */
+ AZALIA_PIN_CFG(0x0, 0x14, 0x90172120),
+
+ /* Pin Complex (NID 0x17) */
+ AZALIA_PIN_CFG(0x0, 0x17, 0x40000000),
+
+ /* Pin Complex (NID 0x18) */
+ AZALIA_PIN_CFG(0x0, 0x18, 0x411111f0),
+
+ /* Pin Complex (NID 0x19) */
+ AZALIA_PIN_CFG(0x0, 0x19, 0x411111f0),
+
+ /* Pin Complex (NID 0x1A) */
+ AZALIA_PIN_CFG(0x0, 0x1A, 0x411111f0),
+
+ /* Pin Complex (NID 0x1B) */
+ AZALIA_PIN_CFG(0x0, 0x1B, 0x411111f0),
+
+ /* Pin Complex (NID 0x1D) */
+ AZALIA_PIN_CFG(0x0, 0x1D, 0x40700001),
+
+ /* Pin Complex (NID 0x1E) */
+ AZALIA_PIN_CFG(0x0, 0x1E, 0x411111f0),
+
+ /* Pin Complex (NID 0x21) */
+ AZALIA_PIN_CFG(0x0, 0x21, 0x02211030),
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/acer/aspire_vn7_572g/mainboard.c b/src/mainboard/acer/aspire_vn7_572g/mainboard.c
new file mode 100644
index 0000000..462b995
--- /dev/null
+++ b/src/mainboard/acer/aspire_vn7_572g/mainboard.c
@@ -0,0 +1,50 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Purism SPC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <smbios.h>
+#include <string.h>
+#include <cbfs.h>
+
+#define MAX_SERIAL_LENGTH 0x100
+
+const char *smbios_mainboard_serial_number(void)
+{
+ static char serial_number[MAX_SERIAL_LENGTH + 1] = {0};
+ struct cbfsf file;
+
+ if (serial_number[0] != 0)
+ return serial_number;
+
+ if (cbfs_boot_locate(&file, "serial_number", NULL) == 0) {
+ struct region_device cbfs_region;
+ size_t serial_len;
+
+ cbfs_file_data(&cbfs_region, &file);
+
+ serial_len = region_device_sz(&cbfs_region);
+ if (serial_len <= MAX_SERIAL_LENGTH) {
+ if (rdev_readat(&cbfs_region, serial_number, 0,
+ serial_len) == serial_len) {
+ serial_number[serial_len] = 0;
+ return serial_number;
+ }
+ }
+ }
+
+ strncpy(serial_number, CONFIG_MAINBOARD_SERIAL_NUMBER,
+ MAX_SERIAL_LENGTH);
+
+ return serial_number;
+}
diff --git a/src/mainboard/acer/aspire_vn7_572g/ramstage.c b/src/mainboard/acer/aspire_vn7_572g/ramstage.c
new file mode 100644
index 0000000..94f8071
--- /dev/null
+++ b/src/mainboard/acer/aspire_vn7_572g/ramstage.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corporation
+ * Copyright (C) 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/ramstage.h>
+#include "gpio.h"
+
+void mainboard_silicon_init_params(FSP_SIL_UPD *params)
+{
+ /* Configure pads prior to SiliconInit() in case there's any
+ * dependencies during hardware initialization. */
+ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
diff --git a/src/mainboard/acer/aspire_vn7_572g/romstage.c b/src/mainboard/acer/aspire_vn7_572g/romstage.c
new file mode 100644
index 0000000..86ef5af
--- /dev/null
+++ b/src/mainboard/acer/aspire_vn7_572g/romstage.c
@@ -0,0 +1,84 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2015 Intel Corporation
+ * Copyright (C) 2017 Purism SPC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <assert.h>
+#include <soc/romstage.h>
+#include <spd_bin.h>
+#include <string.h>
+
+static void mainboard_fill_dq_map_data(void *dq_map_ch0, void *dq_map_ch1)
+{
+ /* DQ byte map */
+ const u8 dq_map[2][12] = {
+ { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,
+ 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 },
+ { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC,
+ 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } };
+ memcpy(dq_map_ch0, dq_map[0], sizeof(dq_map[0]));
+ memcpy(dq_map_ch1, dq_map[1], sizeof(dq_map[1]));
+}
+
+static void mainboard_fill_dqs_map_data(void *dqs_map_ch0, void *dqs_map_ch1)
+{
+ /* DQS CPU<>DRAM map */
+ const u8 dqs_map[2][8] = {
+ { 0, 1, 3, 2, 4, 5, 6, 7 },
+ { 1, 0, 4, 5, 2, 3, 6, 7 } };
+ memcpy(dqs_map_ch0, dqs_map[0], sizeof(dqs_map[0]));
+ memcpy(dqs_map_ch1, dqs_map[1], sizeof(dqs_map[1]));
+}
+
+static void mainboard_fill_rcomp_res_data(void *rcomp_ptr)
+{
+ /* Rcomp resistor */
+ const u16 RcompResistor[3] = { 121, 81, 100 };
+ memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor));
+}
+
+static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr)
+{
+ /* Rcomp target */
+ const u16 RcompTarget[5] = { 100, 40, 20, 20, 26 };
+ memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget));
+}
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+ FSP_M_CONFIG *mem_cfg;
+ struct spd_block blk = {
+ .addr_map = { 0x50, 0x52 },
+ };
+
+ mem_cfg = &mupd->FspmConfig;
+
+ get_spd_smbus(&blk);
+ dump_spd_info(&blk);
+ assert(blk.spd_array[0][0] != 0);
+
+ mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0,
+ &mem_cfg->DqByteMapCh1);
+ mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0,
+ &mem_cfg->DqsMapCpu2DramCh1);
+ mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor);
+ mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);
+
+ mem_cfg->DqPinsInterleaved = TRUE;
+ mem_cfg->MemorySpdDataLen = blk.len;
+ mem_cfg->MemorySpdPtr00 = (uintptr_t) blk.spd_array[0];
+ mem_cfg->MemorySpdPtr10 = (uintptr_t) blk.spd_array[1];
+}
--
To view, visit https://review.coreboot.org/c/coreboot/+/35523
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6
Gerrit-Change-Number: 35523
Gerrit-PatchSet: 1
Gerrit-Owner: Benjamin Doron
Gerrit-MessageType: newchange
4 days, 3 hours
- 8
- 291
Change in ...coreboot[master]: soc/intel/denverton_ns: Rewrite pmutil using pmclib
by Patrick Georgi (Code Review)
Hello Julien Viard de Galbert,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/31072
to review the following change.
Change subject: soc/intel/denverton_ns: Rewrite pmutil using pmclib
......................................................................
soc/intel/denverton_ns: Rewrite pmutil using pmclib
Change-Id: I13ab94e7440886f77e3091b16e50e48b17151751
Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net>
---
M src/soc/intel/denverton_ns/include/soc/pm.h
M src/soc/intel/denverton_ns/pmutil.c
M src/soc/intel/denverton_ns/smihandler.c
M src/soc/intel/denverton_ns/smm.c
4 files changed, 33 insertions(+), 184 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/31072/1
diff --git a/src/soc/intel/denverton_ns/include/soc/pm.h b/src/soc/intel/denverton_ns/include/soc/pm.h
index 09ce158..0aab0e2 100644
--- a/src/soc/intel/denverton_ns/include/soc/pm.h
+++ b/src/soc/intel/denverton_ns/include/soc/pm.h
@@ -47,18 +47,6 @@
struct chipset_power_state *fill_power_state(void);
/* Power Management Utility Functions. */
-uint32_t clear_smi_status(void);
-uint16_t clear_pm1_status(void);
-uint32_t clear_tco_status(void);
-uint32_t clear_gpe_status(void);
void clear_pmc_status(void);
-void enable_smi(uint32_t mask);
-void disable_smi(uint32_t mask);
-void enable_pm1(uint16_t events);
-void enable_pm1_control(uint32_t mask);
-void disable_pm1_control(uint32_t mask);
-void enable_gpe(uint32_t mask);
-void disable_gpe(uint32_t mask);
-void disable_all_gpe(void);
#endif /* _DENVERTON_NS_PM_H_ */
diff --git a/src/soc/intel/denverton_ns/pmutil.c b/src/soc/intel/denverton_ns/pmutil.c
index ccf0d95..344f8b9 100644
--- a/src/soc/intel/denverton_ns/pmutil.c
+++ b/src/soc/intel/denverton_ns/pmutil.c
@@ -19,29 +19,12 @@
#include <arch/io.h>
#include <console/console.h>
+#include <intelblocks/pmclib.h>
#include <soc/iomap.h>
#include <soc/soc_util.h>
#include <soc/pm.h>
-static void print_num_status_bits(int num_bits, uint32_t status,
- const char *const bit_names[])
-{
- int i;
-
- if (!status)
- return;
-
- for (i = num_bits - 1; i >= 0; i--) {
- if (status & (1 << i)) {
- if (bit_names[i])
- printk(BIOS_DEBUG, "%s ", bit_names[i]);
- else
- printk(BIOS_DEBUG, "BIT%d ", i);
- }
- }
-}
-
-static uint32_t print_smi_status(uint32_t smi_sts)
+const char *const *soc_smi_sts_array(size_t *a)
{
static const char *const smi_sts_bits[] = {
[2] = "BIOS",
@@ -67,93 +50,11 @@
[31] = "LEGACY_USB3",
};
- if (!smi_sts)
- return 0;
-
- printk(BIOS_DEBUG, "SMI_STS: ");
- print_num_status_bits(ARRAY_SIZE(smi_sts_bits), smi_sts, smi_sts_bits);
- printk(BIOS_DEBUG, "\n");
-
- return smi_sts;
+ *a = ARRAY_SIZE(smi_sts_bits);
+ return smi_sts_bits;
}
-static uint32_t reset_smi_status(void)
-{
- uint16_t pmbase = get_pmbase();
- uint32_t smi_sts = inl((uint16_t)(pmbase + SMI_STS));
- outl(smi_sts, (uint16_t)(pmbase + SMI_STS));
- return smi_sts;
-}
-
-uint32_t clear_smi_status(void) { return print_smi_status(reset_smi_status()); }
-
-void enable_smi(uint32_t mask)
-{
- uint16_t pmbase = get_pmbase();
- uint32_t smi_en = inl((uint16_t)(pmbase + SMI_EN));
- smi_en |= mask;
- outl(smi_en, (uint16_t)(pmbase + SMI_EN));
-}
-
-void disable_smi(uint32_t mask)
-{
- uint16_t pmbase = get_pmbase();
- uint32_t smi_en = inl((uint16_t)(pmbase + SMI_EN));
- smi_en &= ~mask;
- outl(smi_en, (uint16_t)(pmbase + SMI_EN));
-}
-
-void enable_pm1_control(uint32_t mask)
-{
- uint16_t pmbase = get_pmbase();
- uint32_t pm1_cnt = inl((uint16_t)(pmbase + PM1_CNT));
- pm1_cnt |= mask;
- outl(pm1_cnt, (uint16_t)(pmbase + PM1_CNT));
-}
-
-void disable_pm1_control(uint32_t mask)
-{
- uint16_t pmbase = get_pmbase();
- uint32_t pm1_cnt = inl((uint16_t)(pmbase + PM1_CNT));
- pm1_cnt &= ~mask;
- outl(pm1_cnt, (uint16_t)(pmbase + PM1_CNT));
-}
-
-static uint16_t reset_pm1_status(void)
-{
- uint16_t pmbase = get_pmbase();
- uint16_t pm1_sts = inw((uint16_t)(pmbase + PM1_STS));
- outw(pm1_sts, (uint16_t)(pmbase + PM1_STS));
- return pm1_sts;
-}
-
-static uint16_t print_pm1_status(uint16_t pm1_sts)
-{
- static const char *const pm1_sts_bits[] = {
- [0] = "TMROF", [4] = "BM", [5] = "GBL",
- [8] = "PWRBTN", [10] = "RTC", [11] = "PRBTNOR",
- [15] = "WAK",
- };
-
- if (!pm1_sts)
- return 0;
-
- printk(BIOS_SPEW, "PM1_STS: ");
- print_num_status_bits(ARRAY_SIZE(pm1_sts_bits), pm1_sts, pm1_sts_bits);
- printk(BIOS_SPEW, "\n");
-
- return pm1_sts;
-}
-
-uint16_t clear_pm1_status(void) { return print_pm1_status(reset_pm1_status()); }
-
-void enable_pm1(uint16_t events)
-{
- uint16_t pmbase = get_pmbase();
- outw(events, (uint16_t)(pmbase + PM1_EN));
-}
-
-static uint32_t print_tco_status(uint32_t tco_sts)
+const char *const *soc_tco_sts_array(size_t *a)
{
static const char *const tco_sts_bits[] = {
[0] = "NMI2SMI", [1] = "OS_TCO_SMI",
@@ -164,17 +65,11 @@
[17] = "SECOND_TO", [20] = "SMLINK_SLV_SMI",
};
- if (!tco_sts)
- return 0;
-
- printk(BIOS_DEBUG, "TCO_STS: ");
- print_num_status_bits(ARRAY_SIZE(tco_sts_bits), tco_sts, tco_sts_bits);
- printk(BIOS_DEBUG, "\n");
-
- return tco_sts;
+ *a = ARRAY_SIZE(tco_sts_bits);
+ return tco_sts_bits;
}
-static uint32_t reset_tco_status(void)
+uint32_t soc_reset_tco_status(void)
{
uint16_t tcobase = get_tcobase();
uint32_t tco_sts = inl((uint16_t)(tcobase + TCO1_STS));
@@ -184,35 +79,7 @@
return tco_sts & tco_en;
}
-uint32_t clear_tco_status(void) { return print_tco_status(reset_tco_status()); }
-
-void enable_gpe(uint32_t mask)
-{
- uint16_t pmbase = get_pmbase();
- uint32_t gpe0_en = inl((uint16_t)(pmbase + GPE0_EN(GPE_STD)));
- gpe0_en |= mask;
- outl(gpe0_en, (uint16_t)(pmbase + GPE0_EN(GPE_STD)));
-}
-
-void disable_gpe(uint32_t mask)
-{
- uint16_t pmbase = get_pmbase();
- uint32_t gpe0_en = inl((uint16_t)(pmbase + GPE0_EN(GPE_STD)));
- gpe0_en &= ~mask;
- outl(gpe0_en, (uint16_t)(pmbase + GPE0_EN(GPE_STD)));
-}
-
-void disable_all_gpe(void) { disable_gpe(~0); }
-
-static uint32_t reset_gpe_status(void)
-{
- uint16_t pmbase = get_pmbase();
- uint32_t gpe_sts = inl((uint16_t)(pmbase + GPE0_STS(GPE_STD)));
- outl(gpe_sts, (uint16_t)(pmbase + GPE0_STS(GPE_STD)));
- return gpe_sts;
-}
-
-static uint32_t print_gpe_sts(uint32_t gpe_sts)
+const char *const *soc_std_gpe_sts_array(size_t *a)
{
static const char *const gpe_sts_bits[] = {
[0] = "GPIO_0", [1] = "GPIO_1",
@@ -233,16 +100,8 @@
[30] = "GPIO_30", [31] = "GPIO_31",
};
- if (!gpe_sts)
- return gpe_sts;
-
- printk(BIOS_DEBUG, "GPE0a_STS: ");
- print_num_status_bits(ARRAY_SIZE(gpe_sts_bits), gpe_sts, gpe_sts_bits);
- printk(BIOS_DEBUG, "\n");
-
- return gpe_sts;
+ *a = ARRAY_SIZE(gpe_sts_bits);
+ return gpe_sts_bits;
}
-uint32_t clear_gpe_status(void) { return print_gpe_sts(reset_gpe_status()); }
-
void clear_pmc_status(void) { /* TODO */ }
diff --git a/src/soc/intel/denverton_ns/smihandler.c b/src/soc/intel/denverton_ns/smihandler.c
index 85f99d7..e1e7bc4 100644
--- a/src/soc/intel/denverton_ns/smihandler.c
+++ b/src/soc/intel/denverton_ns/smihandler.c
@@ -25,6 +25,7 @@
#include <device/pci_def.h>
#include <elog.h>
#include <intelblocks/fast_spi.h>
+#include <intelblocks/pmclib.h>
#include <spi-generic.h>
#include <soc/iomap.h>
#include <soc/soc_util.h>
@@ -52,7 +53,7 @@
return 0;
}
-void southbridge_smi_set_eos(void) { enable_smi(EOS); }
+void southbridge_smi_set_eos(void) { pmc_enable_smi(EOS); }
global_nvs_t *smm_get_gnvs(void) { return gnvs; }
@@ -98,7 +99,7 @@
uint16_t pmbase = get_pmbase();
/* First, disable further SMIs */
- disable_smi(SLP_SMI_EN);
+ pmc_disable_smi(SLP_SMI_EN);
/* Figure out SLP_TYP */
reg32 = inl((uint16_t)(pmbase + PM1_CNT));
@@ -131,7 +132,7 @@
printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n");
/* Disable all GPE */
- disable_all_gpe();
+ pmc_disable_all_gpe();
/* also iterates over all bridges on bus 0 */
busmaster_disable_on_bus(0);
@@ -145,7 +146,7 @@
* event again. We need to set BIT13 (SLP_EN) though to make the
* sleep happen.
*/
- enable_pm1_control(SLP_EN);
+ pmc_enable_pm1_control(SLP_EN);
/* Make sure to stop executing code here for S3/S4/S5 */
if (slp_typ > 1)
@@ -158,7 +159,7 @@
reg32 = inl((uint16_t)(pmbase + PM1_CNT));
if (reg32 & SCI_EN) {
/* The OS is not an ACPI OS, so we set the state to S0 */
- disable_pm1_control(SLP_EN | SLP_TYP);
+ pmc_disable_pm1_control(SLP_EN | SLP_TYP);
}
}
@@ -237,11 +238,11 @@
printk(BIOS_DEBUG, "P-state control\n");
break;
case APM_CNT_ACPI_DISABLE:
- disable_pm1_control(SCI_EN);
+ pmc_disable_pm1_control(SCI_EN);
printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n");
break;
case APM_CNT_ACPI_ENABLE:
- enable_pm1_control(SCI_EN);
+ pmc_enable_pm1_control(SCI_EN);
printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n");
break;
case APM_CNT_FINALIZE:
@@ -268,23 +269,23 @@
static void southbridge_smi_pm1(void)
{
- uint16_t pm1_sts = clear_pm1_status();
+ uint16_t pm1_sts = pmc_clear_pm1_status();
/* While OSPM is not active, poweroff immediately
* on a power button event.
*/
if (pm1_sts & PWRBTN_STS) {
// power button pressed
- disable_pm1_control(-1UL);
- enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT));
+ pmc_disable_pm1_control(-1UL);
+ pmc_enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT));
}
}
-static void southbridge_smi_gpe0(void) { clear_gpe_status(); }
+static void southbridge_smi_gpe0(void) { pmc_clear_all_gpe_status(); }
static void southbridge_smi_tco(void)
{
- uint32_t tco_sts = clear_tco_status();
+ uint32_t tco_sts = pmc_clear_tco_status();
/* Any TCO event? */
if (!tco_sts)
@@ -354,7 +355,7 @@
/* We need to clear the SMI status registers, or we won't see what's
* happening in the following calls.
*/
- smi_sts = clear_smi_status();
+ smi_sts = pmc_clear_smi_status();
/* Call SMI sub handler for each of the status bits */
for (i = 0; i < ARRAY_SIZE(southbridge_smi); i++) {
diff --git a/src/soc/intel/denverton_ns/smm.c b/src/soc/intel/denverton_ns/smm.c
index 9d3fa75..65d2499 100644
--- a/src/soc/intel/denverton_ns/smm.c
+++ b/src/soc/intel/denverton_ns/smm.c
@@ -23,6 +23,7 @@
#include <cpu/x86/smm.h>
#include <string.h>
+#include <intelblocks/pmclib.h>
#include <soc/iomap.h>
#include <soc/soc_util.h>
#include <soc/pm.h>
@@ -48,10 +49,10 @@
}
/* Dump and clear status registers */
- clear_smi_status();
- clear_pm1_status();
- clear_tco_status();
- clear_gpe_status();
+ pmc_clear_smi_status();
+ pmc_clear_pm1_status();
+ pmc_clear_tco_status();
+ pmc_clear_all_gpe_status();
clear_pmc_status();
}
@@ -60,8 +61,8 @@
printk(BIOS_DEBUG, "Enabling SMIs.\n");
/* Configure events Disable pcie wake. */
- enable_pm1(PWRBTN_EN | GBL_EN | PCIEXPWAK_DIS);
- disable_gpe(PME_B0_EN);
+ pmc_enable_pm1(PWRBTN_EN | GBL_EN | PCIEXPWAK_DIS);
+ pmc_disable_std_gpe(PME_B0_EN);
/* Enable SMI generation:
* - on APMC writes (io 0xb2)
@@ -71,7 +72,7 @@
* - on TCO events
* - on microcontroller writes (io 0x62/0x66)
*/
- enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS);
+ pmc_enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS);
}
void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
--
To view, visit https://review.coreboot.org/c/coreboot/+/31072
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I13ab94e7440886f77e3091b16e50e48b17151751
Gerrit-Change-Number: 31072
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name>
Gerrit-MessageType: newchange
4 days, 19 hours
- 4
- 6
Change in coreboot[master]: device/pci: Ensure full 16-bit VGA port i/o decoding
by Nico Huber (Code Review)
Hello Kyösti Mälkki, Patrick Rudolph, Michael Niewöhner,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/35516
to review the following change.
Change subject: device/pci: Ensure full 16-bit VGA port i/o decoding
......................................................................
device/pci: Ensure full 16-bit VGA port i/o decoding
So, the PCI to PCI bridge specification had a pitfall for us:
Originally, when decoding i/o ports for legacy VGA cycles, bridges
should only consider the 10 least significant bits of the port address.
This means all VGA registers were aliased every 1024 ports!
e.g. 0x3b0 was also decoded as 0x7b0, 0xbb0 etc.
However, it seems, we never reserved the aliased ports, resulting in
random conflicts. We neither use much external VGA nor many i/o ports
these days, so nobody noticed.
To avoid this mess, a bridge control bit (VGA16) was introduced in
2003 to enable decoding of 16-bit port addresses. As we don't want
to clutter our i/o port space, we'll now simply fail for VGA behind
bridges that don't support it. Famous last words: I assume there
can't be many bridges left that don't support this bit ;)
Change-Id: Id7a07f069dd54331df79f605c6bcda37882a602d
Signed-off-by: Nico Huber <nico.h(a)gmx.de>
---
M src/device/device.c
M src/device/pci_device.c
M src/include/device/device.h
M src/include/device/pci_def.h
4 files changed, 48 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/35516/1
diff --git a/src/device/device.c b/src/device/device.c
index 44d1f95..523bd1c 100644
--- a/src/device/device.c
+++ b/src/device/device.c
@@ -757,6 +757,12 @@
while ((dev = dev_find_class(PCI_CLASS_DISPLAY_VGA << 8, dev))) {
if (!dev->enabled)
continue;
+ if (dev->bus->no_vga) {
+ printk(BIOS_WARNING, "Ignoring VGA at %s"
+ ", a bridge on the path isn't supported",
+ dev_path(dev));
+ continue;
+ }
printk(BIOS_DEBUG, "found VGA at %s\n", dev_path(dev));
@@ -797,7 +803,7 @@
while (bus) {
printk(BIOS_DEBUG, "Setting PCI_BRIDGE_CTL_VGA for bridge %s\n",
dev_path(bus->dev));
- bus->bridge_ctrl |= PCI_BRIDGE_CTL_VGA;
+ bus->bridge_ctrl |= PCI_BRIDGE_CTL_VGA | PCI_BRIDGE_CTL_VGA16;
bus = (bus == bus->dev->bus) ? 0 : bus->dev->bus;
}
}
diff --git a/src/device/pci_device.c b/src/device/pci_device.c
index 7ecb652..2fadb55 100644
--- a/src/device/pci_device.c
+++ b/src/device/pci_device.c
@@ -788,6 +788,43 @@
};
/**
+ * Check for compatibility to route legacy VGA cycles through a bridge.
+ *
+ * Originally, when decoding i/o ports for legacy VGA cycles, bridges
+ * should only consider the 10 least significant bits of the port address.
+ * This means all VGA registers were aliased every 1024 ports!
+ * e.g. 0x3b0 was also decoded as 0x7b0, 0xbb0 etc.
+ *
+ * To avoid this mess, a bridge control bit (VGA16) was introduced in
+ * 2003 to enable decoding of 16-bit port addresses. As we don't want
+ * to clutter our i/o port space, we simply fail for VGA behind bridges
+ * that don't support it (set .no_vga = 1).
+ */
+static void pci_bridge_vga_compat(struct bus *const bus)
+{
+ uint16_t bridge_ctrl;
+
+ bridge_ctrl = pci_read_config16(bus->dev, PCI_BRIDGE_CONTROL);
+
+ /* Ensure VGA decoding is disabled during probing (it should
+ be by default, but we run blobs nowadays) */
+ bridge_ctrl &= ~PCI_BRIDGE_CTL_VGA;
+ pci_write_config16(bus->dev, PCI_BRIDGE_CONTROL, bridge_ctrl);
+
+ /* If the upstream bridge doesn't support VGA, we don't have to check */
+ bus->no_vga |= bus->dev->bus->no_vga;
+ if (bus->no_vga)
+ return;
+
+ /* Test if we can enable 16-bit decoding */
+ bridge_ctrl |= PCI_BRIDGE_CTL_VGA16;
+ pci_write_config16(bus->dev, PCI_BRIDGE_CONTROL, bridge_ctrl);
+ bridge_ctrl = pci_read_config16(bus->dev, PCI_BRIDGE_CONTROL);
+
+ bus->no_vga = !(bridge_ctrl & PCI_BRIDGE_CTL_VGA16);
+}
+
+/**
* Detect the type of downstream bridge.
*
* This function is a heuristic to detect which type of bus is downstream
@@ -1288,6 +1325,8 @@
bus = dev->link_list;
+ pci_bridge_vga_compat(bus);
+
pci_bridge_route(bus, PCI_ROUTE_SCAN);
do_scan_bus(bus, 0x00, 0xff);
diff --git a/src/include/device/device.h b/src/include/device/device.h
index b2221cc..78e234e 100644
--- a/src/include/device/device.h
+++ b/src/include/device/device.h
@@ -94,6 +94,7 @@
unsigned int reset_needed : 1;
unsigned int disable_relaxed_ordering : 1;
unsigned int ht_link_up : 1;
+ unsigned int no_vga : 1; /* We can't support VGA behind this bridge */
};
/*
diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h
index bc5bc79..c8b86d5 100644
--- a/src/include/device/pci_def.h
+++ b/src/include/device/pci_def.h
@@ -138,6 +138,7 @@
#define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
#define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */
#define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
+#define PCI_BRIDGE_CTL_VGA16 0x10 /* Enable 16-bit i/o port decoding */
#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
#define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
/* Fast Back2Back enabled on secondary interface */
--
To view, visit https://review.coreboot.org/c/coreboot/+/35516
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Id7a07f069dd54331df79f605c6bcda37882a602d
Gerrit-Change-Number: 35516
Gerrit-PatchSet: 1
Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Gerrit-Reviewer: Michael Niewöhner
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-MessageType: newchange
1 week
- 4
- 26
Change in ...coreboot[master]: csb_patcher.sh: gets,checks,installs the coreboot and SeaBIOS patches
by Mike Banon (Code Review)
Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33509
Change subject: csb_patcher.sh: gets,checks,installs the coreboot and SeaBIOS patches
......................................................................
csb_patcher.sh: gets,checks,installs the coreboot and SeaBIOS patches
Conveniently and securely gets, checks SHA256 and installs some of my
patches from this page - https://review.coreboot.org/q/status:open+banon
- and also gets a collection of useful floppy-based operating systems.
Sometimes it takes quite a long time to get a patch merged, while the
people might need it today! - and this script could be really helpful.
It asks a [Y/N] question for every addition, and since there are some
"universal" patches as well as great floppies, you may still want to
run this script - even if your board is not Lenovo G505S or not AMD.
Please share your feedback/suggestions and tell about other useful patches,
preferably the "universal" ones - i.e. SeaBIOS. Currently included:
1) "board-specific": G505S dGPU support, G505S config and AtomBIOS ROMs
2) "universal": SeaBIOS patches: advanced_bootmenu, multiple_floppies,
writeprotected_usb ; tint build system ; and also a floppies collection :
KolibriOS, FreeDOS, MichalOS, Snowdrop, Fiwix, Memtest, Tatos, Plop, FloppyBird.
Run ./csb_patcher.sh help or ./csb_patcher.sh usage for more information.
Signed-off-by: Mike Banon <mikebdp2(a)gmail.com>
Change-Id: I66f4f2865ac63ce0f2615669c7a3abd70a397e49
---
A csb_patcher.sh
1 file changed, 876 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/33509/1
diff --git a/csb_patcher.sh b/csb_patcher.sh
new file mode 100755
index 0000000..b325f71
--- /dev/null
+++ b/csb_patcher.sh
@@ -0,0 +1,876 @@
+#!/bin/sh
+#
+# csb_patcher.sh: coreboot and SeaBIOS patcher script.
+#
+# Conveniently and securely gets, checks SHA256 and installs some of my
+# patches from this page - https://review.coreboot.org/q/status:open+banon
+# and also gets a collection of useful floppy-based operating systems.
+# Please send your feedback to Mike Banon <mikebdp2(a)gmail.com>
+#
+
+# Keys
+enter=$( printf '\015' )
+ctrl_c=$( printf '\003' )
+ctrl_x=$( printf '\030' )
+ctrl_z=$( printf '\032' )
+
+# Formatting
+bold="\e[1m"
+bred="\e[1;31m"
+bgreen="\e[1;32m"
+byellow="\e[1;33m"
+bend="\e[0m"
+
+# Asks a question '$1' and waits for Y/N user input, printing a decision - with '$2' message if Y.
+yesno () {
+ printf "$1 [Y/N] "
+ yesno_old_stty_cfg=$( stty -g )
+ stty raw -echo
+ while true ; do
+ yesno_answer=$( head -c 1 )
+ case "$yesno_answer" in
+ *"$ctrl_c"*|"$ctrl_x"*|"$ctrl_z"*)
+ stty "$yesno_old_stty_cfg"
+ printf "${bred}TERMINATED${bend}\n"
+ exit 1
+ ;;
+ *"y"*|"Y"*)
+ stty "$yesno_old_stty_cfg"
+ printf "${bgreen}YES${bend}$2\n"
+ return 0
+ ;;
+ *"n"*|"N"*)
+ stty "$yesno_old_stty_cfg"
+ printf "${byellow}NO${bend}\n"
+ return 1
+ ;;
+ esac
+ done
+}
+
+# Waits until a user presses Enter.
+encontinue () {
+ printf "\npress [ENTER] to continue... "
+ encontinue_old_stty_cfg=$( stty -g )
+ stty raw -echo
+ while true ; do
+ encontinue_answer=$( head -c 1 )
+ case "$encontinue_answer" in
+ *"$ctrl_c"*|"$ctrl_x"*|"$ctrl_z"*)
+ stty "$encontinue_old_stty_cfg"
+ printf "${bred}TERMINATED${bend}\n"
+ exit 1
+ ;;
+ *"$enter"*)
+ stty "$encontinue_old_stty_cfg"
+ printf "\n"
+ return 0
+ ;;
+ esac
+ done
+}
+
+# Checks if a command '$1' exists.
+command_exists() {
+ if [ ! -x "$( command -v $1 )" ] ; then
+ printf "\n${bred}ERROR${bend}: command ${bold}$1${bend} is not found !\n"
+ encontinue
+ return 1
+ else
+ return 0
+ fi
+}
+
+# Checks if a file '$1' exists.
+file_exists () {
+ if [ ! -f "$1" ] ; then
+ printf "\n${byellow}WARNING${bend}: file ${bold}$1${bend} is not found !\n"
+ encontinue
+ return 1
+ else
+ return 0
+ fi
+}
+
+# Force removes a file '$2' and then copies a file '$1' to '$2'.
+copier () {
+ if file_exists "$1" ; then
+ rm -f "$2"
+ cp "$1" "$2"
+ return 0
+ else
+ return 1
+ fi
+}
+
+# Force removes a file '$2' and then moves a file '$1' to '$2'.
+mover () {
+ if file_exists "$1" ; then
+ rm -f "$2"
+ mv "$1" "$2"
+ return 0
+ else
+ return 1
+ fi
+}
+
+# Checks if line '$1' contains the text '$2'.
+checker () {
+ case "$1" in
+ *"$2"*)
+ return 0
+ ;;
+ *)
+ return 1
+ ;;
+ esac
+}
+
+# Prints the lines of a file '$2' which contain the text '$1'.
+grepper () {
+ if file_exists "$2" ; then
+ while IFS= read -r grepper_line
+ do
+ case "$grepper_line" in
+ *"$1"*)
+ printf '%s\n' "$grepper_line"
+ ;;
+ esac
+ done < "$2"
+ return 0
+ else
+ return 1
+ fi
+}
+
+# Checks if a file '$2' contains the text '$1'.
+grepcheck () {
+ if file_exists "$2" ; then
+ while IFS= read -r grepcheck_line
+ do
+ case "$grepcheck_line" in
+ *"$1"*)
+ return 0
+ ;;
+ esac
+ done < "$2"
+ return 1
+ else
+ return 1
+ fi
+}
+
+# Replaces the lines containing the text '$2' of a file '$1' with a line '$3'.
+sedder () {
+ if file_exists "$1" ; then
+ csb_sedder_tmp="./.csb_sedder"
+ rm -f "$csb_sedder_tmp"
+ while IFS= read -r sedder_line
+ do
+ case "$sedder_line" in
+ *"$2"*)
+ if [ ! -z "$3" ] ; then
+ printf '%s\n' "$3" >> "$csb_sedder_tmp"
+ fi
+ ;;
+ *)
+ printf '%s\n' "$sedder_line" >> "$csb_sedder_tmp"
+ ;;
+ esac
+ done < "$1"
+ mover "$csb_sedder_tmp" "$1"
+ return 0
+ else
+ return 1
+ fi
+}
+
+# Downloads a file '$1' from a link '$2' using the options '$3' and checks if this was successful.
+wgetter () {
+ rm -f "$1"
+ if [ -z "$3" ] ; then
+ wget "$2"
+ else
+ wget "$3" "$2"
+ fi
+ if [ -f "$1" ] ; then
+ wgetter_file_size=$(($( wc -c < "$1" )))
+ if [ "$wgetter_file_size" -eq "0" ] ; then
+ rm -f "$1"
+ fi
+ fi
+ if [ ! -f "$1" ] ; then
+ printf "\n${byellow}WARNING${bend}: can't download a ${bold}$1${bend} file !"
+ printf "\n Please check your Internet connection and try again.\n"
+ encontinue
+ return 1
+ else
+ return 0
+ fi
+}
+
+# Unzips the archive '$1', optional '$2' for -j path inside the archive, and then force removes it.
+unzipper () {
+ if file_exists "$1" ; then
+ if [ -z "$2" ] ; then
+ unzip "$1"
+ else
+ unzip -j "$1" "$2"
+ fi
+ rm -f "$1"
+ return 0
+ else
+ return 1
+ fi
+}
+
+# Expands a file '$1' with zeroes using a dd to '$2' size - e.g. to a standard floppy size 1474560.
+expander () {
+ if file_exists "$1" && [ ! -z "$2" ] ; then
+ expander_file_size=$(($( wc -c < "$1" )))
+ if [ "$expander_file_size" -lt "$2" ] ; then
+ dd if=/dev/zero of=$1 bs=1 count=1 seek="$(( $2 - 1 ))" conv=notrunc iflag=nocache
+ fi
+ return 0
+ else
+ return 1
+ fi
+}
+
+# Compares sha256sum of '$1.img' floppy image with '$2' and creates a hidden '.$1' file if matches.
+floppy_verifier () {
+ rm -f "./.$1"
+ cd ".."
+ if [ ! -z "$2" ] ; then
+ if file_exists "./floppies/$1.img" ; then
+ floppy_verifier_sha256sum_correct="$2 ./floppies/$1.img"
+ floppy_verifier_sha256sum_my=$( sha256sum "./floppies/$1.img" )
+ printf "\n=== sha256sum should be:\n${bold}$floppy_verifier_sha256sum_correct${bend}\n"
+ if [ "$floppy_verifier_sha256sum_my" = "$floppy_verifier_sha256sum_correct" ] ; then
+ printf "^^^ this is correct, ./floppies/${bold}$1.img${bend} is verified and could be added.\n\n"
+ cd "./floppies/"
+ touch "./.$1"
+ return 0
+ else
+ printf "${bold}^^^ ! MISMATCH for ./floppies/$1.img ! Check sha256sum manually: sha256sum ./floppies/$1.img${bend}\n"
+ encontinue
+ cd "./floppies/"
+ return 1
+ fi
+ else
+ printf "\n${byellow}WARNING${bend}: cannot find ./floppies/${bold}$1.img${bend} !\n"
+ printf "\n Please re-download a set of floppies.\n"
+ encontinue
+ return 1
+ fi
+ else
+ printf "\n${byellow}WARNING${bend}: ./floppies/${bold}$1.img${bend} - is a rolling release, its' SHA256 checksum"
+ printf "\n is changing constantly and not provided by $1 project, so not checked.\n"
+ encontinue
+ cd "./floppies/"
+ touch "./.$1"
+ return 0
+ fi
+}
+
+# Downloads a collection of floppies, for the purpose of adding them later to a coreboot ROM image.
+floppy_mass_downloader () {
+ printf "\n"
+ if [ ! -d "./floppies/" ]; then
+ mkdir "./floppies/"
+ fi
+ cd "./floppies/"
+ # KOLIBRI
+ if command_exists "7za" ; then
+ if wgetter "./latest-img.7z" "https://builds.kolibrios.org/eng/latest-img.7z" ; then
+ rm -f "./kolibri.img"
+ 7za x "./latest-img.7z"
+ rm -f "./latest-img.7z"
+ floppy_verifier "kolibri" "" # IS A ROLLING RELEASE, NO SHA256 VERIFICATION
+ fi
+ else
+ printf "\n${byellow}WARNING${bend}: cannot get ./floppies/${bold}kolibri.img${bend} without ${bold}7za${bend}\n"
+ encontinue
+ fi
+ # FREEDOS
+ if wgetter "./FD12FLOPPY.zip" "https://www.freedos.org/download/download/FD12FLOPPY.zip" ; then
+ unzipper "./FD12FLOPPY.zip" "FLOPPY.img"
+ mover "./FLOPPY.img" "./freedos.img"
+ floppy_verifier "freedos" "de2fb84dc2f132324549e89d58c6383497ec1af538c5b0ecde389fb748b9d537"
+ fi
+ # MICHALOS
+ printf "\n${byellow}WARNING${bend}: getting ./floppies/${bold}michalos.img${bend} could take a couple of minutes...\n\n"
+ if wgetter "./MichalOS 2.0 Source.zip" "https://sourceforge.net/p/michalos/tickets/_discuss/thread/69ab1508c3/39cd/…" "--content-disposition" ; then
+ unzipper "./MichalOS 2.0 Source.zip" "disk_images/michalos.img"
+ floppy_verifier "michalos" "139e9d08881f646156971a0a061972ddca77057b8acf4164e36366271ab3658c"
+ fi
+ # SNOWDROP
+ if wgetter "./snowdrop.img" "http://sebastianmihai.com/downloads/snowdrop/snowdrop.img" ; then
+ floppy_verifier "snowdrop" "" # IS A ROLLING RELEASE, NO SHA256 VERIFICATION
+ fi
+ # FIWIX
+ if wgetter "./fiwix.img" "https://www.fiwix.org/fiwix-1.0.1-i386-initrd.img" "--output-document=fiwix.img" ; then
+ floppy_verifier "fiwix" "dbec2994ec619c9954327ab0b983ab24cd362406a2e515c35c79c79bd6417cfd"
+ fi
+ # MEMTEST
+ if wgetter "./memtest86+-5.01.floppy.zip" "https://www.memtest.org/download/5.01/memtest86+-5.01.floppy.zip" ; then
+ unzipper "./memtest86+-5.01.floppy.zip" "floppy/memtestp.bin"
+ expander "./memtestp.bin" "1474560"
+ mover "./memtestp.bin" "./memtest.img"
+ floppy_verifier "memtest" "364535abd0d105da9396df6015e480c4d4c52b07dcc4e1d4756bde8ef87a30f1"
+ fi
+ # TATOS
+ if wgetter "./tatos.img" "https://github.com/tatimmer/tatOS/raw/master/tatOS.img" "--output-document=tatos.img" ; then
+ expander "./tatos.img" "1474560"
+ floppy_verifier "tatos" "2c66f884498a4fe7b469bc213aebfccd84a09fd7ace1b3b4b3e747e2392c35d1"
+ fi
+ # PLOP
+ if wgetter "./plpbt-5.0.15.zip" "https://download.plop.at/files/bootmngr/plpbt-5.0.15.zip" ; then
+ unzipper "./plpbt-5.0.15.zip" "plpbt-5.0.15/plpbt.img"
+ mover "./plpbt.img" "./plop.img"
+ floppy_verifier "plop" "f170759966ec4efe60c8531158344a234d7543c8de81e54c8c1bb9d2d69eaf27"
+ fi
+ # FLOPPYBIRD
+ if wgetter "./floppybird.img" "https://github.com/mikebdp2/floparchive/raw/master/floppies_extra/floppybir…" ; then
+ floppy_verifier "floppybird" "5db1b469e25e9eda7b8c0f666d6b655bab083c85618a9453ee72f1201cca840f"
+ fi
+ # Some floppies have the weird permissions after their extraction
+ floppy_mass_downloader_floppies=$( find . -name "*.img" )
+ if [ ! -z "$floppy_mass_downloader_floppies" ] ; then
+ chmod 755 "./"*".img"
+ fi
+ # Return back to ./coreboot/
+ cd ".."
+ return 0
+}
+
+# Adds a './pci1002,$1.rom' to coreboot '$3' ROM using '$2' cbfstool, printing '$4'/'$5'/'$6' info.
+atombios_adder () {
+ if file_exists "$2" && file_exists "$3" ; then
+ if [ -f "./pci1002,$1.rom" ] ; then
+ atombios_adder_cbfs=$( "$2" "$3" print )
+ if checker "$atombios_adder_cbfs" "pci1002,$1.rom" ; then
+ printf "\n${bgreen}NOTE${bend}: ./${bold}pci1002,$1.rom${bend} for ${bold}$5 : $6${bend} is already at your $3.\n"
+ else
+ if yesno "\nAdd a ./${bold}pci1002,$1.rom${bend} for ${bold}$5 : $6${bend} to your $3 now? ${bold}~$4${bend}" ", adding..." ; then
+ "$2" "$3" add -f "./pci1002,$1.rom" -n "pci1002,$1.rom" -t optionrom
+ else
+ printf "\n${bold}You can add it later by running:${bend}"
+ printf "\n${bold} $2 $3 add -f ./pci1002,$1.rom -n pci1002,$1.rom -t optionrom${bend}\n\n"
+ fi
+ fi
+ return 0
+ else
+ printf "\n${byellow}WARNING${bend}: cannot find ./${bold}pci1002,$1.rom${bend} ,"
+ printf "\n please re-apply ${bold}AMD atombios${bend} patch.\n"
+ encontinue
+ return 1
+ fi
+ else
+ return 1
+ fi
+}
+
+# Adds a '$1.img' floppy image to coreboot '$3' ROM using '$2' cbfstool, printing '$4' size info.
+floppy_adder () {
+ if file_exists "$2" && file_exists "$3" ; then
+ if [ -f "./floppies/$1.img" ] ; then
+ if [ -f "./floppies/.$1" ] ; then
+ floppy_adder_cbfs=$( "$2" "$3" print )
+ if checker "$floppy_adder_cbfs" "floppyimg/$1.lzma" ; then
+ printf "\n${bgreen}NOTE${bend}: ./floppies/${bold}$1.img${bend} is already at your $3.\n"
+ else
+ if checker "$1" "plop" ; then
+ printf "\n${byellow}WARNING${bend}: ./floppies/${bold}$1.img${bend} - is proprietary: all its' source code is closed !"
+ printf "\n Add it only if you really need it and trust the author of $1 project.\n"
+ encontinue
+ fi
+ if yesno "\nAdd a ./floppies/${bold}$1.img${bend} to your $3 now? ${bold}~$4${bend}" ", adding..." ; then
+ "$2" "$3" add -f "./floppies/$1.img" -n "floppyimg/$1.lzma" -t raw -c lzma
+ else
+ printf "\n${bold}You can add it later by running:${bend}"
+ printf "\n${bold} $2 $3 add -f ./floppies/$1.img -n floppyimg/$1.lzma -t raw -c lzma${bend}\n\n"
+ fi
+ fi
+ return 0
+ else
+ printf "\n${byellow}WARNING${bend}: there was a SHA256 mismatch for ./floppies/${bold}$1.img${bend} -"
+ printf "\n check sha256sum manually: sha256sum ./floppies/${bold}$1.img${bend}\n"
+ encontinue
+ return 1
+ fi
+ else
+ printf "\n${byellow}WARNING${bend}: cannot find ./floppies/${bold}$1.img${bend} !\n"
+ printf "\n Please re-download a set of floppies.\n"
+ encontinue
+ return 1
+ fi
+ else
+ return 1
+ fi
+}
+
+# Adds a set of AtomBIOS/floppies ('$1') to coreboot '$3' ROM copied to '$4', using '$2' cbfstool.
+cbfs_mass_adder () {
+ if ! grepcheck "how to submit coreboot changes" ./MAINTAINERS ; then
+ printf "\n${byellow}WARNING${bend}: not sure if I am inside the coreboot directory,"
+ printf "\n trying to add a ${bold}$1${bend} set from here - could fail.\n\n"
+ fi
+ if file_exists "$2" && file_exists "$3" ; then
+ if checker "$1" "atom" || checker "$1" "flop" ; then
+ copier "$3" "$4"
+ printf "\n${bold}=== $4 - initial memory map${bend}\n\n"
+ "$2" "$4" print
+ printf "\n"
+ if checker "$1" "atom" ; then
+###
+### https://review.coreboot.org/c/coreboot/+/31944
+### G505S AtomBIOS ROMs: known good binaries with a script to check their SHA256
+###
+ csb_patcher "atombios" "31944" "6" "78a8454" "9a8efff284bbdb81d5b912ccc8279162553e04673bde53e5288ba4bed0e4bc3d" "$1" "AMD "
+ atombios_adder "990b" "$2" "$4" "62K" "Lenovo G505S with A10-5750M" "iGPU HD-8650G"
+ atombios_adder "6663" "$2" "$4" "33K" "Lenovo G505S with A10-5750M" "dGPU HD-8570M"
+ atombios_adder "6665" "$2" "$4" "32K" "Lenovo G505S with A10-5750M" "dGPU R5-M230"
+ atombios_adder "9830" "$2" "$4" "59K" "ASUS AM1I-A with Athlon-5370" "iGPU HD-8400 / R3-Series"
+ atombios_adder "990c" "$2" "$4" "62K" "ASUS A88XM-E with A10-6700" "iGPU HD-8670D"
+ fi
+ if checker "$1" "flop" ; then
+ if [ ! -d "./floppies/" ] ; then
+ printf "\n"
+ floppy_mass_downloader
+ fi
+ # Default boot order: the last floppy added - is the first floppy to boot!
+ floppy_adder "floppybird" "$2" "$4" "2K"
+ floppy_adder "plop" "$2" "$4" "74K"
+ floppy_adder "tatos" "$2" "$4" "60K"
+ floppy_adder "memtest" "$2" "$4" "44K"
+ floppy_adder "fiwix" "$2" "$4" "458K"
+ floppy_adder "snowdrop" "$2" "$4" "126K"
+ floppy_adder "michalos" "$2" "$4" "256K"
+ floppy_adder "freedos" "$2" "$4" "698K"
+ floppy_adder "kolibri" "$2" "$4" "1264K"
+ fi
+ printf "\n${bold}=== $4 - final memory map${bend}\n\n"
+ "$2" "$4" print
+ printf "\nYou can use ./build/${bold}coreflop.rom${bend} now !\n\n"
+ return 0
+ else
+ return 1
+ fi
+ else
+ return 1
+ fi
+}
+
+# Finds the files of '$1' extension, saves the result to '$2' log and prints a message with '$3'.
+csb_finder () {
+ csb_finder_files=$( find . -name "*.$1" )
+ if [ ! -z "$csb_finder_files" ] ; then
+ printf "%25s\n" "*.$1 - YES" >> "$2"
+ printf "\n${byellow}WARNING${bend}: found ${bold}*.$1${bend} files at these locations :\n"
+ printf "$csb_finder_files"
+ printf "\n That means - Some patches $3\n"
+ encontinue
+ return 0
+ else
+ printf "%24s\n" "*.$1 - NO" >> "$2"
+ return 1
+ fi
+}
+
+# Prints a csb_patcher_log '$1' with a custom highlighting.
+csb_printer () {
+ if ! file_exists "$1" ; then
+ return 1
+ fi
+ while IFS= read -r csb_printer_line
+ do
+ case "$csb_printer_line" in
+ *"orig - YES"*)
+ printf "${csb_printer_line%???}${byellow}YES" # YELLOW
+ ;;
+ *"rej - YES"*)
+ printf "${csb_printer_line%???}${bred}YES" # RED
+ ;;
+ *"YES"*)
+ printf "${csb_printer_line%???}${bgreen}YES" # GREEN
+ ;;
+ *"orig - NO"*|*"rej - NO"*)
+ printf "${csb_printer_line%??}${bgreen}NO" # GREEN
+ ;;
+ *"NO"*)
+ printf "${csb_printer_line%??}${byellow}NO" # YELLOW
+ ;;
+ *"FAILURE_1"*)
+ printf "${csb_printer_line%?????????}${bred}FAILURE_1" # RED
+ ;;
+ *"FAILURE_2"*)
+ printf "${csb_printer_line%?????????}${bred}FAILURE_2" # RED
+ ;;
+ *"FAILURE_3"*)
+ printf "${csb_printer_line%?????????}${bred}FAILURE_3" # RED
+ ;;
+ *"\\\\"*)
+ printf "${bold}${csb_printer_line%?????}\\\\\!//" # ALIEN HAIR
+ ;;
+ *)
+ printf "${bold}$csb_printer_line"
+ ;;
+ esac
+ printf "${bend}\n"
+ done < "$1"
+ return 0
+}
+
+# Configure some popular options of a config file '$1'.
+csb_configurer () {
+ if file_exists "$1" ; then
+ csb_configurer_tmp="./.csb_configurer"
+ rm -f "$csb_configurer_tmp"
+ grepper "CONFIG_BOARD_" "$1" > "$csb_configurer_tmp"
+ if grepcheck "_LENOVO_G505S=y" "$csb_configurer_tmp" ; then
+ printf "\n\n${bgreen}[CONFIG]${bend} Questions about your Lenovo G505S\n\n"
+ sedder "$1" "### CSB_CONFIGURER OPTIONS" ""
+ printf "### CSB_CONFIGURER OPTIONS\n" >> "$1"
+ sedder "$1" "# CONFIG_DRIVERS_INTEL_WIFI is not set" ""
+ if ! yesno "Do you have an Intel WiFi adapter?" "" ; then
+ printf "# CONFIG_DRIVERS_INTEL_WIFI is not set\n" >> "$1"
+ fi
+ sedder "$1" "CONFIG_MULTIPLE_VGA_ADAPTERS=y" ""
+ sedder "$1" "CONFIG_VGA_BIOS_DGPU=y" ""
+ sedder "$1" "CONFIG_VGA_BIOS_DGPU_FILE=\"pci1002,6663.rom\"" ""
+ sedder "$1" "CONFIG_VGA_BIOS_DGPU_ID=\"1002,6663\"" ""
+ sedder "$1" "CONFIG_VGA_BIOS_DGPU_FILE=\"pci1002,6665.rom\"" ""
+ sedder "$1" "CONFIG_VGA_BIOS_DGPU_ID=\"1002,6665\"" ""
+ if yesno "Do you have a Discrete GPU?" "" ; then
+ printf "CONFIG_MULTIPLE_VGA_ADAPTERS=y\n" >> "$1"
+ printf "CONFIG_VGA_BIOS_DGPU=y\n" >> "$1"
+ if yesno "No for HD-8570M, Yes for R5-M230" "" ; then
+ printf "CONFIG_VGA_BIOS_DGPU_FILE=\"pci1002,6665.rom\"\n" >> "$1"
+ printf "CONFIG_VGA_BIOS_DGPU_ID=\"1002,6665\"\n" >> "$1"
+ else
+ printf "CONFIG_VGA_BIOS_DGPU_FILE=\"pci1002,6663.rom\"\n" >> "$1"
+ printf "CONFIG_VGA_BIOS_DGPU_ID=\"1002,6663\"\n" >> "$1"
+ fi
+ fi
+
+ sedder "$1" "# NATIVE" ""
+ sedder "$1" "CONFIG_HUDSON_SATA_MODE=0" ""
+
+ sedder "$1" "# RAID" ""
+ sedder "$1" "CONFIG_HUDSON_SATA_MODE=1" ""
+ sedder "$1" "CONFIG_RAID_ROM_ID=\"1022,7802\"" ""
+ sedder "$1" "CONFIG_RAID_ROM_FILE=\"src/southbridge/amd/agesa/hudson/raid.bin\"" ""
+ sedder "$1" "CONFIG_RAID_MISC_ROM_FILE=\"src/southbridge/amd/agesa/hudson/misc.bin\"" ""
+ sedder "$1" "CONFIG_RAID_MISC_ROM_POSITION=0xFFF00000" ""
+
+ sedder "$1" "# AHCI" ""
+ sedder "$1" "CONFIG_HUDSON_SATA_MODE=2" ""
+ sedder "$1" "CONFIG_AHCI_ROM_ID=\"1022,7801\"" ""
+ sedder "$1" "# CONFIG_HUDSON_AHCI_ROM is not set" ""
+
+ sedder "$1" "# LEGACY IDE" ""
+ sedder "$1" "CONFIG_HUDSON_SATA_MODE=3" ""
+
+ sedder "$1" "# IDE to AHCI" ""
+ sedder "$1" "CONFIG_HUDSON_SATA_MODE=4" ""
+
+ sedder "$1" "# AHCI7804" ""
+ sedder "$1" "CONFIG_HUDSON_SATA_MODE=5" ""
+ sedder "$1" "CONFIG_AHCI_ROM_ID=\"1022,7804\"" ""
+
+ sedder "$1" "# IDE to AHCI7804" ""
+ sedder "$1" "CONFIG_HUDSON_SATA_MODE=6" ""
+ sedder "$1" "# CONFIG_HUDSON_AHCI_ROM is not set" ""
+
+ if yesno "Do you have a SSD? (enable AHCI if Y)" "" ; then
+ printf "# AHCI\n" >> "$1"
+ printf "CONFIG_HUDSON_SATA_MODE=2\n" >> "$1"
+ printf "CONFIG_AHCI_ROM_ID=\"1022,7801\"\n" >> "$1"
+ printf "# CONFIG_HUDSON_AHCI_ROM is not set\n" >> "$1"
+ else
+ printf "# NATIVE\n" >> "$1"
+ printf "CONFIG_HUDSON_SATA_MODE=0\n" >> "$1"
+ fi
+ rm -f "$csb_configurer_tmp"
+ return 0
+ else
+ printf "\n\n${byellow}WARNING${bend}: sorry, I don't know how to configure a board of ${bold}$1${bend}\n"
+ encontinue
+ return 1
+ fi
+ else
+ return 1
+ fi
+}
+
+#
+# Conveniently and securely gets, checks SHA256 and installs a patch.
+# Arguments are the patch properties:
+# $1 - new diff name, could be also a part of extracted scripts' filename
+# $2 - change ID number, part of download link to review.coreboot.org
+# $3 - change revision number, part of download link to review.coreboot.org
+# $4 - diff filename inside the downloaded archive, will be renamed to $1
+# $5 - diff known good SHA256 checksum, will be used for SHA256 verification
+# $6 - filepath where to save a csb_patcher_log which will be printed later
+# $7 - info about the target of a patch, if not specified ("") it is common
+#
+csb_patcher () {
+ if ! wgetter "./patch?zip" "https://review.coreboot.org/changes/$2/revisions/$3/patch?zip" ; then
+ printf "${bold}^^^ ! Can't download a $7$1 patch ! Check your Internet.${bend}\n"
+ printf "%31s\n" "$7$1 - FAILURE_1" >> "$6"
+ csb_printer "$6"
+ exit 1
+ fi
+ unzipper "./patch?zip"
+ mover "./$4.diff" "./$1.diff"
+ csb_patcher_sha256sum_correct="$5 ./$1.diff"
+ csb_patcher_sha256sum_my=$( sha256sum "./$1.diff" )
+ printf "\n=== sha256sum should be:\n${bold}$csb_patcher_sha256sum_correct${bend}\n"
+ if [ "$csb_patcher_sha256sum_my" = "$csb_patcher_sha256sum_correct" ] ; then
+ printf "^^^ this is correct, "
+ csb_patcher_patch_title=$( grepper "Subject" "./$1.diff" )
+ csb_patcher_patch_title=${csb_patcher_patch_title#?????????????????}
+ if [ "$1" = "dgpu" ] ; then
+ printf "will extract a ${bold}$7$1${bend} patch now...\n"
+ rm -f "./sha256sums_$1_correct.txt"
+ rm -f "./"*"_$1_patches.sh"
+ patch -p1 < "./$1.diff"
+ chmod +x "./"*"_$1_patches.sh"
+ "./get_$1_patches.sh"
+ if ! "./check_$1_patches.sh" ; then
+ printf "%31s\n" "$7$1 - FAILURE_3" >> "$6"
+ csb_printer "$6"
+ exit 1
+ fi
+ else
+ printf "${bold}$7$1${bend} patch could be applied now...\n"
+ fi
+ if [ "$1" = "dgpu" ] || [ "$1" = "atombios" ] || \
+ [ "$1" = "tint" ] || [ "$1" = "seabios" ] ; then
+ printf "\n\n${bgreen}[PATCH]${bend} $csb_patcher_patch_title\n\n"
+ if ! grepcheck "how to submit coreboot changes" ./MAINTAINERS ; then
+ printf "\n${byellow}WARNING${bend}: not sure if I am inside the coreboot directory,"
+ printf "\n trying to add a ${bold}$1${bend} set from here - could fail.\n\n"
+ fi
+ if [ -f "./.$1" ] ; then
+ printf "\n${byellow}WARNING${bend}: found a '.$1' hidden file at the current directory,"
+ printf "\n maybe you have applied this patch already.\n\n"
+ fi
+ if yesno "Apply a ${bold}$7$1${bend} patch now?" "" ; then
+ if [ "$1" = "dgpu" ] ; then
+ "./apply_$1_patches.sh"
+ else
+ if [ "$1" = "atombios" ] ; then
+ rm -f "./sha256sums_$1_correct.txt"
+ rm -f "./"*"_$1_roms.sh"
+ rm -f "./pci1002\,"*".rom"
+ rm -f "./pci1002\,"*".rom.txt"
+ fi
+ if [ "$1" = "tint" ] ; then
+ rm -f "./payloads/external/tint/tint.sh"
+ rm -f "./payloads/external/tint/"*"_core.sh"
+ rm -f "./payloads/external/tint/tint-0.04-nmu1_libpayload.patch"
+ fi
+ if [ "$1" = "seabios" ] ; then
+ rm -f "./payloads/external/SeaBIOS/"*".patch"
+ fi
+ patch -p1 < "./$1.diff"
+ if [ "$1" = "atombios" ] ; then
+ chmod +x "./"*"_$1_roms.sh"
+ "./extract_$1_roms.sh"
+ printf "\n"
+ if ! "./check_$1_roms.sh" ; then
+ printf "%31s\n" "$7$1 - FAILURE_3" >> "$6"
+ csb_printer "$6"
+ exit 1
+ fi
+ fi
+ if [ "$1" = "tint" ] ; then
+ chmod +x "./payloads/external/tint/"*"_core.sh"
+ fi
+ fi
+ touch ".$1"
+ printf "%25s\n" "$7$1 - YES" >> "$6"
+ if [ "$1" = "atombios" ] ; then
+ encontinue
+ fi
+ else
+ printf "%24s\n" "$7$1 - NO" >> "$6"
+ printf "\n${bold}You can apply it later by running:${bend}"
+ if [ "$1" = "dgpu" ] ; then
+ printf "\n${bold} ./apply_$1_patches.sh${bend}\n"
+ else
+ printf "\n${bold} patch -p1 < ./$1.diff${bend}\n"
+ fi
+ encontinue
+ fi
+ fi
+ if checker "$1" "config" ; then
+ rm -f "./configs/$1_"*
+ patch -p1 < "./$1.diff"
+ printf "\n\n${bgreen}[PATCH]${bend} $csb_patcher_patch_title\n\n"
+ ls "./configs" > "./.csb_configs"
+ csb_patcher_config_name=$( grepper "$1" "./.csb_configs" )
+ rm -f "./.csb_configs"
+ printf "\n${bold}$csb_patcher_config_name could now be found at ./configs/${bend}"
+ printf "\n${bold}To use it, it should be copied to '.config' of your ./coreboot directory.${bend}\n\n"
+ if [ -f "./.config" ] ; then
+ printf "\n${byellow}WARNING${bend}: copying it to ./.config will overwrite your current '.config'\n\n"
+ fi
+ if yesno "Copy it to ./.config now?" "" ; then
+ copier "./configs/$csb_patcher_config_name" "./.config"
+ printf "\n"
+ printf "%25s\n" "$7$1 - YES" >> "$6"
+ if yesno "Configure this ./.config now?" "" ; then
+ csb_configurer "./.config"
+ else
+ printf "\n${bold}You can configure it later by running:${bend}"
+ printf "\n${bold} ./csb_patcher.sh config${bend}\n\n"
+ fi
+ else
+ printf "%24s\n" "$7$1 - NO" >> "$6"
+ printf "\n${bold}You can copy it later by running:${bend}"
+ printf "\n${bold} cp ./configs/$csb_patcher_config_name ./.config${bend}\n"
+ fi
+ printf "\n${byellow}WARNING${bend}: important README at the beginning of ./$1.diff\n"
+ encontinue
+ fi
+ printf "\n\n"
+ return 0
+ else
+ printf "${bold}^^^ ! MISMATCH for a $7$1 patch ! Check sha256sum manually: sha256sum ./$1.diff${bend}\n"
+ printf "%31s\n" "$7$1 - FAILURE_2" >> "$6"
+ csb_printer "$6"
+ exit 1
+ fi
+}
+
+#
+# Conveniently and securely gets, checks SHA256 and applies my collection of unofficial patches.
+# $1 - filepath where to save a csb_patcher_log which will be printed later
+#
+csb_mass_patcher () {
+###
+### https://review.coreboot.org/c/coreboot/+/31929
+### G505S dGPU support: scripts for applying the unofficial (not-merged-yet) patches
+###
+ csb_patcher "dgpu" "31929" "13" "ed0c44f" "eb461931a1f34a8263405138eb1bf8d32a1f460026449c9ec1a9b9e7d8383f1c" "$1" "G505S "
+###
+### https://review.coreboot.org/c/coreboot/+/31944
+### G505S AtomBIOS ROMs: known good binaries with a script to check their SHA256
+###
+ csb_patcher "atombios" "31944" "6" "78a8454" "9a8efff284bbdb81d5b912ccc8279162553e04673bde53e5288ba4bed0e4bc3d" "$1" "AMD "
+###
+### https://review.coreboot.org/c/coreboot/+/23856
+### tint: introduce the new tint build system with checksum verification
+###
+ csb_patcher "tint" "23856" "15" "14630b6" "7b9719f675d83750c7d4fb21b3abcbf1758ac6d1db20a9e8ef0db22f15761317" "$1" ""
+###
+### https://review.coreboot.org/c/coreboot/+/32351
+### SeaBIOS patches: advanced_bootmenu, multiple_floppies, writeprotected_usb
+###
+ csb_patcher "seabios" "32351" "5" "4a9c3cd" "58348b0514446856d07078af443ac8a24cd3be8178290e7361a48a86d213a43b" "$1" ""
+###
+### https://review.coreboot.org/c/coreboot/+/32352
+### configs: add Lenovo G505S sample configuration (use with dGPU patches)
+###
+csb_patcher "config.lenovo_g505s" "32352" "12" "348d8ce" "5b3b663b3afe3fe5729be2632201f3665e75ed3848996901322d3528ed6dd897" "$1" ""
+
+ return 0
+}
+
+# Prints a usage info for this ./csb_patcher.sh script.
+csb_usage () {
+ printf "${bold}===============${bend} ${bgreen}USAGE${bend} ${bold}================${bend}\n\n"
+ printf "${bold}./csb_patcher.sh${bend}\n"
+ printf " patch your coreboot source code\n\n"
+ printf "${bold}./csb_patcher.sh${bend} ${byellow}help${bend} ${bold}|${bend} ${byellow}usage${bend}\n"
+ printf " print this usage info\n\n"
+ printf "${bold}==================== Before building :${bend}\n\n"
+ printf "${bold}./csb_patcher.sh ${byellow}config${bend}\n"
+ printf " configure some popular options\n\n"
+ printf "${bold}==================== After building :${bend}\n\n"
+ printf "${bold}./csb_patcher.sh ${byellow}atom${bend}\n"
+ printf " add the AtomBIOS to coreboot.rom\n\n"
+ printf "${bold}./csb_patcher.sh ${byellow}flop${bend}\n"
+ printf " add the floppies to coreboot.rom\n\n"
+ printf "${bold}./csb_patcher.sh ${byellow}atomflop${bend}\n"
+ printf " both AtomBIOS VGA ROMs and floppies\n\n"
+ printf "${bold}./csb_patcher.sh${bend} ${byellow}print${bend}\n"
+ printf " print a ./.csb_patcher log\n\n"
+ return 0
+}
+
+#
+# MAIN PART OF A CSB_PATCHER SCRIPT
+#
+
+if [ -z "$1" ] ; then
+ csb_patcher_log="./.csb_patcher"
+ rm -f "$csb_patcher_log"
+ if ! command_exists "wget" || \
+ ! command_exists "unzip" || \
+ ! command_exists "sha256sum" || \
+ ! command_exists "patch" ; then
+ exit 1
+ fi
+ printf '\n\n' >> "$csb_patcher_log"
+ printf ' \\\\!//\n' >> "$csb_patcher_log"
+ printf ' (o o)\n' >> "$csb_patcher_log"
+ printf ' oOOo-(_)-oOOo\n' >> "$csb_patcher_log"
+ printf 'Hi! I am coreboot and SeaBIOS patcher\n' >> "$csb_patcher_log"
+ printf 'Please send your feedback to\n' >> "$csb_patcher_log"
+ printf ' Mike Banon <mikebdp2(a)gmail.com>\n' >> "$csb_patcher_log"
+ csb_printer "$csb_patcher_log"
+ encontinue
+ printf '\n=== CSB_PATCHER LOG. Patches applied?\n' >> "$csb_patcher_log"
+
+ csb_mass_patcher "$csb_patcher_log"
+
+ if yesno "Download a ${bold}floppies${bend} collection?" "" ; then
+ floppy_mass_downloader
+ printf "%25s\n" "floppies - YES" >> "$csb_patcher_log"
+ else
+ printf "\n"
+ printf "%24s\n" "floppies - NO" >> "$csb_patcher_log"
+ fi
+
+ printf '==================== Bad files found?\n' >> "$csb_patcher_log"
+ csb_finder "orig" "$csb_patcher_log" "applied correctly although at slightly different lines, can ignore it."
+ csb_finder "rej" "$csb_patcher_log" "perhaps failed to apply, could result in a broken build! ${bred}Please report${bend}"
+
+ printf '\n' >> "$csb_patcher_log"
+ csb_printer "$csb_patcher_log"
+ csb_usage
+else
+ case "$1" in
+ *"print"*)
+ csb_patcher_log="./.csb_patcher"
+ csb_printer "$csb_patcher_log"
+ ;;
+ *"config"*)
+ csb_configurer "./.config"
+ ;;
+ *"atom"*|*"flop"*)
+ if ! command_exists "wget" || \
+ ! command_exists "unzip" || \
+ ! command_exists "sha256sum" ; then
+ exit 1
+ fi
+ cbfs_mass_adder "$1" "./build/cbfstool" "./build/coreboot.rom" "./build/coreflop.rom"
+ ;;
+ *"help"*|*"usage"*)
+ printf "\n"
+ csb_usage
+ ;;
+ *)
+ printf "\n${bred}ERROR${bend}: unknown argument ${bold}$1${bend} !\n\n"
+ csb_usage
+ exit 1
+ ;;
+ esac
+fi
+
+exit 0
+
--
To view, visit https://review.coreboot.org/c/coreboot/+/33509
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I66f4f2865ac63ce0f2615669c7a3abd70a397e49
Gerrit-Change-Number: 33509
Gerrit-PatchSet: 1
Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com>
Gerrit-MessageType: newchange
1 week, 1 day
- 4
- 85
Change in ...coreboot[master]: libpayload: nvme driver
by Thomas Heijligen (Code Review)
Thomas Heijligen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33582
Change subject: libpayload: nvme driver
......................................................................
libpayload: nvme driver
Change-Id: Ie75b1dc743dac3426c230c57ee23b771ba3a6e0c
Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.com>
---
M payloads/libpayload/drivers/Makefile.inc
M payloads/libpayload/drivers/storage/Kconfig
A payloads/libpayload/drivers/storage/nvme.c
M payloads/libpayload/drivers/storage/storage.c
A payloads/libpayload/include/storage/nvme.h
M payloads/libpayload/include/storage/storage.h
M payloads/libpayload/include/x86/arch/io.h
A payloads/libpayload/sample/nvme_test.c
8 files changed, 429 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/33582/1
diff --git a/payloads/libpayload/drivers/Makefile.inc b/payloads/libpayload/drivers/Makefile.inc
index 40e587c..676dbd3 100644
--- a/payloads/libpayload/drivers/Makefile.inc
+++ b/payloads/libpayload/drivers/Makefile.inc
@@ -77,6 +77,7 @@
libc-$(CONFIG_LP_STORAGE) += storage/storage.c
libc-$(CONFIG_LP_STORAGE_AHCI) += storage/ahci.c
libc-$(CONFIG_LP_STORAGE_AHCI) += storage/ahci_common.c
+libc-$(CONFIG_LP_STORAGE_NVME) += storage/nvme.c
ifeq ($(CONFIG_LP_STORAGE_ATA),y)
libc-$(CONFIG_LP_STORAGE_ATA) += storage/ata.c
libc-$(CONFIG_LP_STORAGE_ATA) += storage/ahci_ata.c
diff --git a/payloads/libpayload/drivers/storage/Kconfig b/payloads/libpayload/drivers/storage/Kconfig
index 04e9a29..3eabf6a 100644
--- a/payloads/libpayload/drivers/storage/Kconfig
+++ b/payloads/libpayload/drivers/storage/Kconfig
@@ -57,3 +57,10 @@
help
If this option is selected only AHCI controllers which are known
to work will be used.
+
+config STORAGE_NVME
+ bool "Support for NVMe devices"
+ depends on STORAGE && PCI
+ default y
+ help
+ Select this option if you want support for NVMe devices
diff --git a/payloads/libpayload/drivers/storage/nvme.c b/payloads/libpayload/drivers/storage/nvme.c
new file mode 100644
index 0000000..871759d
--- /dev/null
+++ b/payloads/libpayload/drivers/storage/nvme.c
@@ -0,0 +1,331 @@
+#include <libpayload.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <pci.h>
+#include <pci/pci.h>
+#include <storage/nvme.h>
+#include <storage/storage.h>
+
+#define PCI_CLASS_CODE_NVME 0x0108
+
+// NVME Controller Configuration
+#define NVME_CC_EN (1 << 0)
+#define NVME_CC_CSS (0 << 4)
+#define NVME_CC_MPS (0 << 7)
+#define NVME_CC_AMS (0 << 11)
+#define NVME_CC_SHN (0 << 14)
+#define NVME_CC_IOSQES (6 << 16)
+#define NVME_CC_IOCQES (4 << 20)
+
+#define NVME_QUEUE_SIZE 2
+#define NVME_SQ_ENTRY_SIZE 64
+#define NVME_CQ_ENTRY_SIZE 16
+
+struct nvme_s_queue_entry {
+ uint32_t dw[16];
+};
+
+struct nvme_c_queue_entry {
+ uint32_t dw[4];
+};
+
+enum nvme_queue {
+ NVME_ADMIN_QUEUE = 0,
+ NVME_IO_QUEUE = 2,
+ ads = 0,
+ adc = 1,
+ ios = 2,
+ ioc = 3,
+};
+
+static storage_poll_t nvme_poll(struct storage_dev *dev);
+static void nvme_detach_device(struct storage_dev *dev);
+static ssize_t nvme_read_blocks512(struct storage_dev *dev, lba_t start, size_t count, unsigned char *buf);
+
+static int create_admin_queues(struct nvme_dev *nvme);
+static int create_io_submission_queue(struct nvme_dev *nvme);
+static int create_io_completion_queue(struct nvme_dev *nvme);
+static void delete_admin_queues(struct nvme_dev *nvme);
+static void delete_io_submission_queue(struct nvme_dev *nvme);
+static void delete_io_completion_queue(struct nvme_dev *nvme);
+static int nvme_cmd(struct nvme_dev *nvme, enum nvme_queue q, const struct nvme_s_queue_entry *cmd);
+static int read(struct nvme_dev *nvme, void *buffer, uint64_t base, uint16_t count);
+
+
+static storage_poll_t nvme_poll(struct storage_dev *dev)
+{
+ return POLL_MEDIUM_PRESENT;
+}
+
+static void nvme_detach_device(struct storage_dev *dev)
+{
+ //nvme_free(dev->driver_struct);
+ // FIXME remove from list
+}
+
+static ssize_t nvme_read_blocks512(struct storage_dev *dev, lba_t start, size_t count, unsigned char *buf)
+{
+ void *buffer = memalign(0x1000, count * 512);
+ if (!buffer)
+ return 0;
+
+ for (int i = 0; i < count; i++) {
+ if (read((struct nvme_dev*)dev, buffer+(i*512), start + i, 1)) {
+ free(buffer);
+ return 0;
+ }
+ }
+
+ memcpy(buf, buffer, count * 512);
+ free(buffer);
+ return count;
+}
+
+static int read(struct nvme_dev *nvme, void *buffer, uint64_t base, uint16_t count)
+{
+ if (count == 0)
+ return -1;
+
+ struct nvme_s_queue_entry e = {
+ .dw[0] = 0x02,
+ .dw[1] = 0x1,
+ .dw[6] = virt_to_phys(buffer),
+ .dw[10] = base,
+ .dw[11] = base >> 32,
+ .dw[12] = count - 1,
+ };
+ return nvme_cmd(nvme, ios, &e);
+}
+
+static void delete_io_submission_queue(struct nvme_dev *nvme)
+{
+ // TODO
+}
+
+static int create_io_submission_queue(struct nvme_dev *nvme)
+{
+ void *sq_buffer = memalign(0x1000, NVME_SQ_ENTRY_SIZE * NVME_QUEUE_SIZE);
+ if (!sq_buffer) {
+ printf("NVMe ERROR: Faild to allocate memory for io submission queue.\n");
+ return -1;
+ }
+ memset(sq_buffer, 0, NVME_SQ_ENTRY_SIZE * NVME_QUEUE_SIZE);
+
+ struct nvme_s_queue_entry e = {
+ .dw[0] = 0x01,
+ .dw[6] = virt_to_phys(sq_buffer),
+ .dw[10] = (NVME_QUEUE_SIZE << 16) | ios >> 1,
+ .dw[11] = (1 << 16) | 1,
+ };
+
+ int res = nvme_cmd(nvme, NVME_ADMIN_QUEUE, &e);
+ if (res) {
+ printf("NVMe ERROR: nvme_cmd returned with %i.\n", res);
+ free(sq_buffer);
+ return res;
+ }
+
+ uint8_t cap_dstrd = (read64(nvme->config) >> 32) & 0xf;
+ nvme->queue[ios].base = sq_buffer;
+ nvme->queue[ios].bell = nvme->config + 0x1000 + (ios * (4 << cap_dstrd));
+ nvme->queue[ios].idx = 0;
+ return 0;
+}
+
+static void delete_io_completion_queue(struct nvme_dev *nvme)
+{
+ // TODO
+}
+
+static int create_io_completion_queue(struct nvme_dev *nvme)
+{
+ void *const cq_buffer = memalign(0x1000, NVME_CQ_ENTRY_SIZE * NVME_QUEUE_SIZE);
+ if (!cq_buffer) {
+ printf("NVMe ERROR: Faild to allocate memory for io competion queue.\n");
+ return -1;
+ }
+ memset(cq_buffer, 0, NVME_CQ_ENTRY_SIZE * NVME_QUEUE_SIZE);
+
+ const struct nvme_s_queue_entry e = {
+ .dw[0] = 0x05,
+ .dw[6] = virt_to_phys(cq_buffer),
+ .dw[10] = (NVME_QUEUE_SIZE << 16) | ioc >> 1,
+ .dw[11] = 1,
+ };
+
+ int res = nvme_cmd(nvme, NVME_ADMIN_QUEUE, &e);
+ if (res) {
+ printf("NVMe ERROR: nvme_cmd returned with %i.\n", res);
+ free(cq_buffer);
+ return res;
+ }
+
+ uint8_t cap_dstrd = (read64(nvme->config) >> 32) & 0xf;
+ nvme->queue[ioc].base = cq_buffer;
+ nvme->queue[ioc].bell = nvme->config + 0x1000 + (ioc * (4 << cap_dstrd));
+ nvme->queue[ioc].idx = 0;
+ nvme->queue[ioc].round = 0;
+
+ return 0;
+}
+
+static int nvme_cmd(struct nvme_dev *nvme, enum nvme_queue q, const struct nvme_s_queue_entry *cmd)
+{
+ int sq = q, cq = q+1;
+
+ void *s_entry = nvme->queue[sq].base + (nvme->queue[sq].idx * NVME_SQ_ENTRY_SIZE);
+ memcpy(s_entry, cmd, NVME_SQ_ENTRY_SIZE);
+ write32(nvme->queue[sq].bell, nvme->queue[sq].idx + 1);
+ nvme->queue[sq].idx = (nvme->queue[sq].idx + 1) & 1;
+
+ struct nvme_c_queue_entry *c_entry = nvme->queue[cq].base + (nvme->queue[cq].idx * NVME_CQ_ENTRY_SIZE);
+ while (((c_entry->dw[3] >> 16 ) & 0x1) == nvme->queue[cq].round)
+ ; // FIXME timeout
+ write32(nvme->queue[cq].bell, nvme->queue[cq].idx + 1);
+ nvme->queue[cq].idx = (nvme->queue[cq].idx + 1) & 1;
+ if (nvme->queue[cq].idx == 0)
+ nvme->queue[cq].round = (nvme->queue[cq].round + 1) & 1;
+ return c_entry->dw[3] >> 17;
+}
+
+static void delete_admin_queues(struct nvme_dev *nvme)
+{
+ free(nvme->queue[ads].base);
+ free(nvme->queue[adc].base);
+ // TODO clean nvme admin queue struct ???
+}
+
+static int create_admin_queues(struct nvme_dev *nvme)
+{
+ uint8_t cap_dstrd = (read64(nvme->config) >> 32) & 0xf;
+ write32(nvme->config + 0x24, NVME_QUEUE_SIZE << 16 | NVME_QUEUE_SIZE);
+
+ void *sq_buffer = memalign(0x1000, NVME_SQ_ENTRY_SIZE * NVME_QUEUE_SIZE);
+ if (!sq_buffer) {
+ printf("NVMe ERROR: faild to allocated memory for admin submission queue\n");
+ return -1;
+ }
+ memset(sq_buffer, 0, NVME_SQ_ENTRY_SIZE * NVME_QUEUE_SIZE);
+ write64(nvme->config + 0x28, virt_to_phys(sq_buffer));
+
+ nvme->queue[ads].base = sq_buffer;
+ nvme->queue[ads].bell = nvme->config + 0x1000 + (ads * (4 << cap_dstrd));
+ nvme->queue[ads].idx = 0;
+
+ void *cq_buffer = memalign(0x1000, NVME_CQ_ENTRY_SIZE * NVME_QUEUE_SIZE);
+ if (!cq_buffer) {
+ printf("NVMe ERROR: Faild to allocate memory for admin completion queue\n");
+ free(cq_buffer);
+ return -1;
+ }
+ memset(cq_buffer, 0, NVME_CQ_ENTRY_SIZE * NVME_QUEUE_SIZE);
+ write64(nvme->config + 0x30, virt_to_phys(cq_buffer));
+
+ nvme->queue[adc].base = cq_buffer;
+ nvme->queue[adc].bell = nvme->config + 0x1000 + (adc * (4 << cap_dstrd));
+ nvme->queue[adc].idx = 0;
+ nvme->queue[adc].round = 0;
+
+ return 0;
+}
+
+static void nvme_init(pcidev_t dev)
+{
+ printf("NVMe init (Device %02x:%02x.%02x)\n", PCI_BUS(dev), PCI_SLOT(dev), PCI_FUNC(dev));
+
+ void *pci_bar0 = phys_to_virt(pci_read_config32(dev, 0x10) & ~0x3ff);
+
+ if ( !(((read64(pci_bar0) >> 37 ) & 0xff) == 0x01)) {
+ printf("NVMe ERROR: PCIe device does not support the NVMe command set\n");
+ return;
+ }
+
+ struct nvme_dev *nvme = malloc(sizeof(*nvme));
+ if (!nvme) {
+ printf("NVMe ERROR: Faild to allocate buffer for nvme driver struct\n");
+ return;
+ }
+ nvme->storage_dev.port_type = PORT_TYPE_NVME;
+ nvme->storage_dev.poll = nvme_poll;
+ nvme->storage_dev.read_blocks512 = nvme_read_blocks512;
+ nvme->storage_dev.write_blocks512 = NULL; // not implemented
+ nvme->storage_dev.detach_device = nvme_detach_device;
+ nvme->config = pci_bar0;
+
+ uint32_t cc = 0;
+ write32(nvme->config + 0x1c, 0);
+
+ int status, timeout = (read64(nvme->config) >> 24 & 0xff) * 500;
+ do {
+ status = read32(nvme->config + 0x1c) & 0x3;
+ if (status == 0x2) {
+ printf("NVMe ERROR: Faild to disable controller. FATAL ERROR\n");
+ goto abort;
+ }
+ if (timeout < 0) {
+ printf("NVMe ERROR: Faild to disable controller. Timeout.\n");
+ goto abort;
+ }
+ timeout -= 10;
+ mdelay(10);
+ } while (status != 0x0);
+
+ if (create_admin_queues(nvme))
+ goto abort;
+
+ cc = NVME_CC_EN | NVME_CC_CSS | NVME_CC_MPS | NVME_CC_AMS |NVME_CC_SHN
+ | NVME_CC_IOSQES | NVME_CC_IOCQES;
+ write32(nvme->config + 0x14, cc);
+
+ timeout = (read64(nvme->config) >> 24 & 0xff) * 500;
+ do {
+ status = read32(nvme->config + 0x1c) & 0x3;
+ if (status == 0x2) {
+ printf("NVMe ERROR: Faild to disable controller. FATAL ERROR\n");
+ goto abort;
+ }
+ if (timeout < 0) {
+ printf("NVMe ERROR: Faild to disable controller. Timeout.\n");
+ goto abort;
+ }
+ timeout -= 10;
+ mdelay(10);
+ } while (status != 0x1);
+
+ uint16_t command = pci_read_config16(dev, PCI_COMMAND);
+ pci_write_config16(dev, PCI_COMMAND, command | PCI_COMMAND_MASTER);
+
+ if (create_io_completion_queue(nvme))
+ goto abort;
+ if (create_io_submission_queue(nvme))
+ goto abort;
+
+ storage_attach_device((storage_dev_t*)nvme);
+ printf("NVMe init done.\n");
+ return;
+
+abort:
+ delete_io_submission_queue(nvme);
+ delete_io_completion_queue(nvme);
+ delete_admin_queues(nvme);
+ free(nvme);
+ printf("failed\n");
+ return;
+}
+
+void nvme_initialize(void)
+{
+ int bus, dev, func;
+ uint16_t class;
+
+ for (bus = 0; bus < 256; ++bus) {
+ for (dev = 0; dev < 32; ++dev) {
+ for (func = 0; func < 8; ++func) {
+ class = pci_read_config16(PCI_DEV(bus, dev, func), 0xa);
+ if (class == PCI_CLASS_CODE_NVME)
+ nvme_init(PCI_DEV(bus, dev, func));
+ }
+ }
+ }
+}
diff --git a/payloads/libpayload/drivers/storage/storage.c b/payloads/libpayload/drivers/storage/storage.c
index a7141ee..55cb60d 100644
--- a/payloads/libpayload/drivers/storage/storage.c
+++ b/payloads/libpayload/drivers/storage/storage.c
@@ -31,6 +31,9 @@
#if CONFIG(LP_STORAGE_AHCI)
# include <storage/ahci.h>
#endif
+#if CONFIG(LP_STORAGE_NVME)
+#include <storage/nvme.h>
+#endif
#include <storage/storage.h>
@@ -113,4 +116,7 @@
#if CONFIG(LP_STORAGE_AHCI)
ahci_initialize();
#endif
+#if CONFIG(LP_STORAGE_NVME)
+ nvme_initialize();
+#endif
}
diff --git a/payloads/libpayload/include/storage/nvme.h b/payloads/libpayload/include/storage/nvme.h
new file mode 100644
index 0000000..090c6d0
--- /dev/null
+++ b/payloads/libpayload/include/storage/nvme.h
@@ -0,0 +1,22 @@
+#ifndef _STORAGE_NVME_H
+#define _STORAGE_NVME_H
+
+#include <stdint.h>
+#include "storage.h"
+
+struct nvme_dev {
+ storage_dev_t storage_dev;
+
+ void *config;
+ void *admin_s_queue;
+ struct {
+ void *base;
+ uint32_t *bell;
+ uint16_t idx; // bool pos 0 or 1
+ uint16_t round; // bool round 0 or 1+0xd
+ } queue[4];
+};
+
+void nvme_initialize(void);
+
+#endif /* _STORAGE_NVME_H */
diff --git a/payloads/libpayload/include/storage/storage.h b/payloads/libpayload/include/storage/storage.h
index 2dc70b0..d1f998e 100644
--- a/payloads/libpayload/include/storage/storage.h
+++ b/payloads/libpayload/include/storage/storage.h
@@ -45,6 +45,7 @@
PORT_TYPE_IDE = (1 << 0),
PORT_TYPE_SATA = (1 << 1),
PORT_TYPE_USB = (1 << 2),
+ PORT_TYPE_NVME = (1 << 3),
} storage_port_t;
typedef enum {
diff --git a/payloads/libpayload/include/x86/arch/io.h b/payloads/libpayload/include/x86/arch/io.h
index c417ce0..46836d9 100644
--- a/payloads/libpayload/include/x86/arch/io.h
+++ b/payloads/libpayload/include/x86/arch/io.h
@@ -64,6 +64,11 @@
return *((volatile uint32_t *)(addr));
}
+static inline __attribute__((always_inline)) uint64_t read64(const volatile void *addr)
+{
+ return *((volatile uint64_t *)(addr));
+}
+
static inline __attribute__((always_inline)) void write8(volatile void *addr, uint8_t value)
{
*((volatile uint8_t *)(addr)) = value;
@@ -79,6 +84,11 @@
*((volatile uint32_t *)(addr)) = value;
}
+static inline __attribute__((always_inline)) void write64(volatile void *addr, uint64_t value)
+{
+ *((volatile uint64_t *)(addr)) = value;
+}
+
static inline unsigned int inl(int port)
{
unsigned long val;
diff --git a/payloads/libpayload/sample/nvme_test.c b/payloads/libpayload/sample/nvme_test.c
new file mode 100644
index 0000000..d2bdf10
--- /dev/null
+++ b/payloads/libpayload/sample/nvme_test.c
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the libpayload project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/* Example file for libpayload. */
+
+#include <libpayload-config.h>
+#include <libpayload.h>
+#include <storage/storage.h>
+
+#define STORAGE_ID 0
+
+int main(void)
+{
+ printf("---------- TEST PROGRAM BEGIN ----------\n");
+ storage_initialize();
+
+ void *buffer = memalign(0x1000, 0x2000);
+ storage_read_blocks512(STORAGE_ID, 0, 15, buffer);
+ printf("\nbuffer content:\n");
+ //hexdump(buffer,0x2000);
+
+ printf("----------- TEST PROGRAM END -----------\n");
+ halt();
+ return 0;
+}
--
To view, visit https://review.coreboot.org/c/coreboot/+/33582
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ie75b1dc743dac3426c230c57ee23b771ba3a6e0c
Gerrit-Change-Number: 33582
Gerrit-PatchSet: 1
Gerrit-Owner: Thomas Heijligen <src(a)posteo.de>
Gerrit-MessageType: newchange
1 week, 4 days
- 7
- 25
Change in ...coreboot[master]: Documentation: Convert cbfs.txt to markdown
by Patrick Rudolph (Code Review)
Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33663
Change subject: Documentation: Convert cbfs.txt to markdown
......................................................................
Documentation: Convert cbfs.txt to markdown
Convert the document to markdown.
Needs to be fixed in a separate commit as it doesn't reflect coreboot v4.
Change-Id: I0fb2713a9cda08e528902ec641dd4a4e0dc148fe
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
A Documentation/lib/cbfs.md
M Documentation/lib/index.md
2 files changed, 372 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/33663/1
diff --git a/Documentation/lib/cbfs.md b/Documentation/lib/cbfs.md
new file mode 100644
index 0000000..83d8b44
--- /dev/null
+++ b/Documentation/lib/cbfs.md
@@ -0,0 +1,371 @@
+# coreboot CBFS Specification
+by Jordan Crouse <jordan(a)cosmicpenguin.net>
+
+**WARNING: This documentation is written against coreboot v1.**
+
+**TODO: Update this document ASAP**
+
+## Introduction
+
+This document describes the coreboot CBFS specification (from here
+referred to as CBFS). CBFS is a scheme for managing independent chunks
+of data in a system ROM. Though not a true filesystem, the style and
+concepts are similar.
+
+
+## Architecture
+
+The CBFS architecture looks like the following:
+
+```
+/---------------\ <-- Start of ROM
+| /-----------\ | --|
+| | Header | | |
+| |-----------| | |
+| | Name | | |-- Component
+| |-----------| | |
+| |Data | | |
+| |.. | | |
+| \-----------/ | --|
+| |
+| /-----------\ |
+| | Header | |
+| |-----------| |
+| | Name | |
+| |-----------| |
+| |Data | |
+| |.. | |
+| \-----------/ |
+| |
+| ... |
+| /-----------\ |
+| | | |
+| | Bootblock | |
+| | --------- | |
+| | Reset | | <- 0xFFFFFFF0
+| \-----------/ |
+\---------------/
+```
+
+The CBFS architecture consists of a binary associated with a physical
+ROM disk referred hereafter as the ROM. A number of independent of
+components, each with a header prepended on to data are located within
+the ROM. The components are nominally arranged sequentially, though they
+are aligned along a pre-defined boundary.
+
+The bootblock occupies the last 20k of the ROM. Within
+the bootblock is a master header containing information about the ROM
+including the size, alignment of the components, and the offset of the
+start of the first CBFS component within the ROM.
+
+## Master Header
+
+The master header contains essential information about the ROM that is
+used by both the CBFS implementation within coreboot at runtime as well
+as host based utilities to create and manage the ROM. The master header
+will be located somewhere within the bootblock (last 20k of the ROM). A
+pointer to the location of the header will be located at offset
+-4 from the end of the ROM. This translates to address 0xFFFFFFFC on a
+normal x86 system. The pointer will be to physical memory somewhere
+between - 0xFFFFB000 and 0xFFFFFFF0. This makes it easier for coreboot
+to locate the header at run time. Build time utilities will
+need to read the pointer and do the appropriate math to locate the header.
+
+The following is the structure of the master header:
+
+```c
+struct cbfs_header {
+ u32 magic;
+ u32 version;
+ u32 romsize;
+ u32 bootblocksize;
+ u32 align;
+ u32 offset;
+ u32 architecture;
+ u32 pad[1];
+} __packed;
+```
+
+The meaning of each member is as follows:
+
+`magic` is a 32 bit number that identifies the ROM as a CBFS type. The
+magic
+number is 0x4F524243, which is 'ORBC' in ASCII.
+
+`version` is a version number for CBFS header. cbfs_header structure may be
+different if version is not matched.
+
+`romsize` is the size of the ROM in bytes. coreboot will subtract 'size' from
+0xFFFFFFFF to locate the beginning of the ROM in memory.
+
+`bootblocksize` is the size of bootblock reserved in firmware image.
+
+`align` is the number of bytes that each component is aligned to within the
+ROM. This is used to make sure that each component is aligned correctly
+with
+regards to the erase block sizes on the ROM - allowing one to replace a
+component at runtime without disturbing the others.
+
+`offset` is the offset of the first CBFS component (from the start of
+the ROM). This is to allow for arbitrary space to be left at the beginning
+of the ROM for things like embedded controller firmware.
+
+`architecture` describes which architecture (x86, arm, ...) this CBFS is created
+for.
+
+## Bootblock
+The bootblock is a mandatory component in the ROM. It is located in the
+last 20k of the ROM space, and contains, among other things, the location of the
+master header and the entry point for the loader firmware. The bootblock
+does not have a component header attached to it.
+
+## Components
+
+CBFS components are placed in the ROM starting at 'offset' specified in
+the master header and ending at the bootblock. Thus the total size
+available for components in the ROM is (ROM size - 20k - 'offset').
+Each CBFS component is to be aligned according to the 'align' value in the
+header.
+Thus, if a component of size 1052 is located at offset 0 with an 'align'
+value of 1024, the next component will be located at offset 2048.
+
+Each CBFS component will be indexed with a unique ASCII string name of
+unlimited size.
+
+Each CBFS component starts with a header:
+
+```c
+struct cbfs_file {
+ char magic[8];
+ unsigned int len;
+ unsigned int type;
+ unsigned int checksum;
+ unsigned int offset;
+};
+```
+
+`magic` is a magic value used to identify the header. During runtime,
+coreboot will scan the ROM looking for this value. The default magic is
+the string 'LARCHIVE'.
+
+`len` is the length of the data, not including the size of the header and
+the size of the name.
+
+`type` is a 32 bit number indicating the type of data that is attached.
+The data type is used in a number of ways, as detailed in the section
+below.
+
+`checksum` is a 32bit checksum of the entire component, including the
+header and name.
+
+`offset` is the start of the component data, based off the start of the
+header.
+The difference between the size of the header and offset is the size of the
+component name.
+
+Immediately following the header will be the name of the component,
+which will null terminated and 16 byte aligned. The following picture shows the
+structure of the header:
+
+```
+/--------\ <- start
+| Header |
+|--------| <- sizeof(struct cbfs_file)
+| Name |
+|--------| <- 'offset'
+| Data |
+| ... |
+\--------/ <- start + 'offset' + 'len'
+```
+
+### Searching Algorithm
+
+To locate a specific component in the ROM, one starts at the 'offset'
+specified in the CBFS master header. For this example, the offset will
+be 0.
+
+From that offset, the code should search for the magic string on the
+component, jumping 'align' bytes each time. So, assuming that 'align' is
+16, the code will search for the string 'LARCHIVE' at offset 0, 16, 32, etc.
+If the offset ever exceeds the allowable range for CBFS components, then no
+component was found.
+
+Upon recognizing a component, the software then has to search for the
+specific name of the component. This is accomplished by comparing the
+desired name with the string on the component located at
+`offset + sizeof(struct cbfs_file)`. If the string matches, then the
+component has been located, otherwise the software should add
+`'offset' + 'len'` to the offset and resume the search for the magic value.
+
+### Data Types
+
+The 'type' member of struct cbfs_file is used to identify the content
+of the component data, and is used by coreboot and other
+run-time entities to make decisions about how to handle the data.
+
+There are three component types that are essential to coreboot, and so
+are defined here.
+
+#### Stages
+
+Stages are code loaded by coreboot during the boot process. They are
+essential to a successful boot. Stages are comprised of a single blob
+of binary data that is to be loaded into a particular location in memory
+and executed. The uncompressed header contains information about how
+large the data is, and where it should be placed, and what additional memory
+needs to be cleared.
+
+Stages are assigned a component value of 0x10. When coreboot sees this
+component type, it knows that it should pass the data to a sub-function
+that will process the stage.
+
+The following is the format of a stage component:
+
+```
+/--------\
+| Header |
+|--------|
+| Binary |
+| .. |
+\--------/
+```
+
+The header is defined as:
+
+```c
+struct cbfs_stage {
+ unsigned int compression;
+ unsigned long long entry;
+ unsigned long long load;
+ unsigned int len;
+ unsigned int memlen;
+};
+```
+
+`compression` is an integer defining how the data is compressed. There
+are three compression types defined by this version of the standard:
+none (0x0), lzma (0x1), and nrv2b (0x02, deprecated), though additional
+types may be added assuming that coreboot understands how to handle the scheme.
+
+`entry` is a 64 bit value indicating the location where the program
+counter should jump following the loading of the stage. This should be
+an absolute physical memory address.
+
+`load` is a 64 bit value indicating where the subsequent data should be
+loaded. This should be an absolute physical memory address.
+
+`len` is the length of the compressed data in the component.
+
+`memlen` is the amount of memory that will be used by the component when
+it is loaded.
+
+The component data will start immediately following the header.
+
+When coreboot loads a stage, it will first zero the memory from 'load' to
+'memlen'. It will then decompress the component data according to the
+specified scheme and place it in memory starting at 'load'. Following that,
+it will jump execution to the address specified by 'entry'.
+Some components are designed to execute directly from the ROM - coreboot
+knows which components must do that and will act accordingly.
+
+#### Payloads
+
+Payloads are loaded by coreboot following the boot process.
+
+Stages are assigned a component value of 0x20. When coreboot sees this
+component type, it knows that it should pass the data to a sub-function
+that will process the payload. Furthermore, other run time applications such
+as 'bayou' may easily index all available payloads
+on the system by searching for the payload type.
+
+
+The following is the format of a stage component:
+
+```
+/-----------\
+| Header |
+| Segment 1 |
+| Segment 2 |
+| ... |
+|-----------|
+| Binary |
+| .. |
+\-----------/
+```
+
+The header is as follows:
+
+```c
+struct cbfs_payload {
+ struct cbfs_payload_segment segments;
+}
+```
+
+The header contains a number of segments corresponding to the segments
+that need to be loaded for the payload.
+
+The following is the structure of each segment header:
+
+```c
+struct cbfs_payload_segment {
+ unsigned int type;
+ unsigned int compression;
+ unsigned int offset;
+ unsigned long long load_addr;
+ unsigned int len;
+ unsigned int mem_len;
+};
+```
+
+`type` is the type of segment, one of the following:
+
+```eval_rst
++----------------------+-------------+---------------------------------------+
+|PAYLOAD_SEGMENT_CODE | 0x45444F43 | The segment contains executable code |
++----------------------+-------------+---------------------------------------+
+|PAYLOAD_SEGMENT_DATA | 0x41544144 | The segment contains data |
++----------------------+-------------+---------------------------------------+
+|PAYLOAD_SEGMENT_BSS | 0x20535342 | The memory specified by the segment |
+| | | should be zeroed |
++----------------------+-------------+---------------------------------------+
+|PAYLOAD_SEGMENT_PARAMS| 0x41524150 | The segment contains information for |
+| | | the payload |
++----------------------+-------------+---------------------------------------+
+|PAYLOAD_SEGMENT_ENTRY | 0x52544E45 | The segment contains the entry point |
+| | | for the payload |
++----------------------+-------------+---------------------------------------+
+```
+
+`compression` is the compression scheme for the segment. Each segment can
+be independently compressed. There are three compression types defined by
+this version of the standard: none (0x0), lzma (0x1), and nrv2b
+(0x02, deprecated), though additional types may be added assuming that
+coreboot understands how to handle the scheme.
+
+`offset` is the address of the data within the component, starting from
+the component header.
+
+`load_addr` is a 64 bit value indicating where the segment should be placed
+in memory.
+
+`len` is a 32 bit value indicating the size of the segment within the
+component.
+
+`mem_len` is the size of the data when it is placed into memory.
+
+The data will located immediately following the last segment.
+
+#### Option ROMS
+
+The third specified component type will be Option ROMs. Option ROMS will
+have component type '0x30'. They will have no additional header, the
+uncompressed binary data will be located in the data portion of the
+component.
+
+#### NULL
+
+There is a 4th component type ,defined as NULL (0xFFFFFFFF). This is
+the "don't care" component type. This can be used when the component
+type is not necessary (such as when the name of the component is unique.
+i.e. option_table). It is recommended that all components be assigned a
+unique type, but NULL can be used when the type does not matter.
diff --git a/Documentation/lib/index.md b/Documentation/lib/index.md
index 99b8061..808bac8 100644
--- a/Documentation/lib/index.md
+++ b/Documentation/lib/index.md
@@ -6,4 +6,5 @@
## Structure and layout
- [Flashmap and Flashmap Descriptor](flashmap.md)
- [ABI data consumption](abi-data-consumption.md)
+- [CBFS](cbfs.md)
- [Timestamps](timestamp.md)
--
To view, visit https://review.coreboot.org/c/coreboot/+/33663
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I0fb2713a9cda08e528902ec641dd4a4e0dc148fe
Gerrit-Change-Number: 33663
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Gerrit-MessageType: newchange
1 week, 5 days
- 4
- 3
Change in ...coreboot[master]: mb/apple: Add MacBook Pro 10,1 (A1398) support
by Evgeny Zinoviev (Code Review)
Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32673
Change subject: mb/apple: Add MacBook Pro 10,1 (A1398) support
......................................................................
mb/apple: Add MacBook Pro 10,1 (A1398) support
MacBook Pro Retina 15 (Mid 2012) with Ivy Bridge CPU.
This is WIP. Not for merging.
Change-Id: Ica03aba442493c0d369a3d360ad569ddc16954df
Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io>
---
M 3rdparty/vboot
A src/mainboard/apple/macbookpro10_1/Kconfig
A src/mainboard/apple/macbookpro10_1/Kconfig.name
A src/mainboard/apple/macbookpro10_1/Makefile.inc
A src/mainboard/apple/macbookpro10_1/acpi/ec.asl
A src/mainboard/apple/macbookpro10_1/acpi/platform.asl
A src/mainboard/apple/macbookpro10_1/acpi/superio.asl
A src/mainboard/apple/macbookpro10_1/acpi_tables.c
A src/mainboard/apple/macbookpro10_1/board_info.txt
A src/mainboard/apple/macbookpro10_1/devicetree.cb
A src/mainboard/apple/macbookpro10_1/dsdt.asl
A src/mainboard/apple/macbookpro10_1/gma-mainboard.ads
A src/mainboard/apple/macbookpro10_1/gpio.c
A src/mainboard/apple/macbookpro10_1/hda_verb.c
A src/mainboard/apple/macbookpro10_1/mainboard.c
A src/mainboard/apple/macbookpro10_1/romstage.c
16 files changed, 758 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/32673/1
diff --git a/3rdparty/vboot b/3rdparty/vboot
index e7edff6..304aa42 160000
--- a/3rdparty/vboot
+++ b/3rdparty/vboot
@@ -1 +1 @@
-Subproject commit e7edff6653e16ed915c3ad12234d133d1ef4dcc9
+Subproject commit 304aa429c1a04cda3ab2ce37b9e31af84405bfca
diff --git a/src/mainboard/apple/macbookpro10_1/Kconfig b/src/mainboard/apple/macbookpro10_1/Kconfig
new file mode 100644
index 0000000..603f3ee
--- /dev/null
+++ b/src/mainboard/apple/macbookpro10_1/Kconfig
@@ -0,0 +1,46 @@
+if BOARD_APPLE_MACBOOKPRO10_1
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select BOARD_ROMSIZE_KB_8192
+ select EC_ACPI
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select INTEL_INT15
+ select NORTHBRIDGE_INTEL_IVYBRIDGE
+ select SERIRQ_CONTINUOUS_MODE
+ select SOUTHBRIDGE_INTEL_C216
+ select SYSTEM_TYPE_LAPTOP
+ select USE_NATIVE_RAMINIT
+ select MAINBOARD_HAS_LIBGFXINIT
+ select GFX_GMA_INTERNAL_IS_EDP
+ select SERIRQ_CONTINUOUS_MODE
+
+config MAINBOARD_DIR
+ string
+ default apple/macbookpro10_1
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "MacBookPro10,1"
+
+config VGA_BIOS_FILE
+ string
+ default "pci8086,0166.rom"
+
+config VGA_BIOS_ID
+ string
+ default "8086,0166"
+
+config DRAM_RESET_GATE_GPIO
+ int
+ default 28
+
+config MAX_CPUS
+ int
+ default 8
+
+config USBDEBUG_HCD_INDEX # FIXME: check this
+ int
+ default 2
+endif
diff --git a/src/mainboard/apple/macbookpro10_1/Kconfig.name b/src/mainboard/apple/macbookpro10_1/Kconfig.name
new file mode 100644
index 0000000..c257f7a
--- /dev/null
+++ b/src/mainboard/apple/macbookpro10_1/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_APPLE_MACBOOKPRO10_1
+ bool "MacBookPro10,1"
diff --git a/src/mainboard/apple/macbookpro10_1/Makefile.inc b/src/mainboard/apple/macbookpro10_1/Makefile.inc
new file mode 100644
index 0000000..fd60338
--- /dev/null
+++ b/src/mainboard/apple/macbookpro10_1/Makefile.inc
@@ -0,0 +1,7 @@
+romstage-y += gpio.c
+
+cbfs-files-y += spd.bin
+spd.bin-file := spd.bin
+spd.bin-type := spd
+
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/apple/macbookpro10_1/acpi/ec.asl b/src/mainboard/apple/macbookpro10_1/acpi/ec.asl
new file mode 100644
index 0000000..f70cb3d
--- /dev/null
+++ b/src/mainboard/apple/macbookpro10_1/acpi/ec.asl
@@ -0,0 +1,20 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Device(EC)
+{
+ Name (_HID, EISAID("PNP0C09"))
+ Name (_UID, 0)
+ Name (_GPE, 23)
+/* FIXME: EC support */
+}
diff --git a/src/mainboard/apple/macbookpro10_1/acpi/platform.asl b/src/mainboard/apple/macbookpro10_1/acpi/platform.asl
new file mode 100644
index 0000000..a17c6ea
--- /dev/null
+++ b/src/mainboard/apple/macbookpro10_1/acpi/platform.asl
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Method(_WAK,1)
+{
+ /* FIXME: EC support */
+ Return(Package(){0,0})
+}
+
+Method(_PTS,1)
+{
+ /* FIXME: EC support */
+}
diff --git a/src/mainboard/apple/macbookpro10_1/acpi/superio.asl b/src/mainboard/apple/macbookpro10_1/acpi/superio.asl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/apple/macbookpro10_1/acpi/superio.asl
diff --git a/src/mainboard/apple/macbookpro10_1/acpi_tables.c b/src/mainboard/apple/macbookpro10_1/acpi_tables.c
new file mode 100644
index 0000000..c48f0bd
--- /dev/null
+++ b/src/mainboard/apple/macbookpro10_1/acpi_tables.c
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/bd82x6x/nvs.h>
+
+/* FIXME: check this function. */
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+ /* Disable USB ports in S3 by default */
+ gnvs->s3u0 = 0;
+ gnvs->s3u1 = 0;
+
+ /* Disable USB ports in S5 by default */
+ gnvs->s5u0 = 0;
+ gnvs->s5u1 = 0;
+
+ // the lid is open by default.
+ gnvs->lids = 1;
+
+ gnvs->tcrt = 100;
+ gnvs->tpsv = 90;
+}
diff --git a/src/mainboard/apple/macbookpro10_1/board_info.txt b/src/mainboard/apple/macbookpro10_1/board_info.txt
new file mode 100644
index 0000000..81a5134
--- /dev/null
+++ b/src/mainboard/apple/macbookpro10_1/board_info.txt
@@ -0,0 +1,6 @@
+Category: laptop
+ROM protocol: SPI
+Flashrom support: n
+ROM package: SOIC-8
+ROM socketed: n
+Release year: 2012
diff --git a/src/mainboard/apple/macbookpro10_1/devicetree.cb b/src/mainboard/apple/macbookpro10_1/devicetree.cb
new file mode 100644
index 0000000..f9e7eb4
--- /dev/null
+++ b/src/mainboard/apple/macbookpro10_1/devicetree.cb
@@ -0,0 +1,124 @@
+chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did
+ #register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }"
+ register "gfx.did" = "{ 0x80000410, 0x80000320, 0x80000410, 0x80000410, 0x00000005 }"
+ register "gfx.link_frequency_270_mhz" = "0"
+ register "gfx.ndid" = "3"
+ register "gfx.use_spread_spectrum_clock" = "1"
+ register "gpu_cpu_backlight" = "0xffffffff"
+ register "gpu_dp_b_hotplug" = "7"
+ register "gpu_dp_c_hotplug" = "7"
+ register "gpu_dp_d_hotplug" = "7"
+ register "gpu_panel_port_select" = "3"
+ register "gpu_panel_power_backlight_off_delay" = "8191"
+ register "gpu_panel_power_backlight_on_delay" = "8191"
+ register "gpu_panel_power_cycle_delay" = "255"
+ register "gpu_panel_power_down_delay" = "8191"
+ register "gpu_panel_power_up_delay" = "8191"
+ register "gpu_pch_backlight" = "0xffffffff"
+ device cpu_cluster 0x0 on
+ chip cpu/intel/model_206ax # FIXME: check all registers
+ register "c1_acpower" = "1"
+ register "c1_battery" = "1"
+ register "c2_acpower" = "3"
+ register "c2_battery" = "3"
+ register "c3_acpower" = "5"
+ register "c3_battery" = "5"
+ device lapic 0x0 on
+ end
+ device lapic 0xacac off
+ end
+ end
+ end
+ device domain 0x0 on
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+ register "c2_latency" = "0x0065"
+ register "docking_supported" = "0"
+ register "gen1_dec" = "0x000c0681"
+ register "gen2_dec" = "0x000c1641"
+ register "gen3_dec" = "0x001c0301"
+ register "gen4_dec" = "0x00fc0701"
+ register "gpi7_routing" = "2"
+ register "p_cnt_throttling_supported" = "1"
+ register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
+ register "pcie_port_coalesce" = "1"
+ register "sata_interface_speed_support" = "0x3"
+ register "sata_port_map" = "0x1"
+ register "spi_lvscc" = "0x0"
+ register "spi_uvscc" = "0x2005"
+ register "superspeed_capable_ports" = "0x0000000f"
+ register "xhci_overcurrent_mapping" = "0x08040201"
+ register "xhci_switchable_ports" = "0x0000000f"
+ device pci 14.0 on # USB 3.0 Controller
+ subsystemid 0x8086 0x7270
+ end
+ device pci 16.0 on # Management Engine Interface 1
+ subsystemid 0x8086 0x7270
+ end
+ device pci 16.1 off # Management Engine Interface 2
+ end
+ device pci 16.2 off # Management Engine IDE-R
+ end
+ device pci 16.3 off # Management Engine KT
+ end
+ device pci 19.0 off # Intel Gigabit Ethernet
+ end
+ device pci 1a.0 on # USB2 EHCI #2
+ subsystemid 0x8086 0x7270
+ end
+ device pci 1b.0 on # High Definition Audio Audio controller
+ subsystemid 0x8086 0x7270
+ end
+ device pci 1c.0 on # PCIe Port #1
+ subsystemid 0x8086 0x7270
+ end
+ device pci 1c.1 on # PCIe Port #2
+ subsystemid 0x8086 0x7270
+ end
+ device pci 1c.2 off # PCIe Port #3
+ end
+ device pci 1c.3 off # PCIe Port #4
+ end
+ device pci 1c.4 off # PCIe Port #5
+ end
+ device pci 1c.5 off # PCIe Port #6
+ end
+ device pci 1c.6 off # PCIe Port #7
+ end
+ device pci 1c.7 off # PCIe Port #8
+ end
+ device pci 1d.0 on # USB2 EHCI #1
+ subsystemid 0x8086 0x7270
+ end
+ device pci 1e.0 off # PCI bridge
+ end
+ device pci 1f.0 on # LPC bridge PCI-LPC bridge
+ subsystemid 0x8086 0x7270
+ end
+ device pci 1f.2 on # SATA Controller 1
+ subsystemid 0x8086 0x7270
+ end
+ device pci 1f.3 on # SMBus
+ subsystemid 0x8086 0x7270
+ end
+ device pci 1f.5 off # SATA Controller 2
+ end
+ device pci 1f.6 off # Thermal
+ end
+ end
+ device pci 00.0 on # Host bridge Host bridge
+ subsystemid 0x106b 0x00f7
+ end
+ device pci 01.0 on # PCIe Bridge for discrete graphics
+ subsystemid 0x106b 0x00f7
+ end
+ device pci 02.0 on # Internal graphics VGA controller
+ subsystemid 0x106b 0x00f7
+ end
+ device pci 01.2 on
+ subsystemid 0x106b 0x00f7
+ end
+ device pci 01.1 on
+ subsystemid 0x106b 0x00f7
+ end
+ end
+end
diff --git a/src/mainboard/apple/macbookpro10_1/dsdt.asl b/src/mainboard/apple/macbookpro10_1/dsdt.asl
new file mode 100644
index 0000000..455ac17
--- /dev/null
+++ b/src/mainboard/apple/macbookpro10_1/dsdt.asl
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
+#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
+
+#include <arch/acpi.h>
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, // DSDT revision: ACPI 2.0 and up
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20141018 // OEM revision
+)
+{
+ /* Some generic macros */
+ #include "acpi/platform.asl"
+ #include <cpu/intel/common/acpi/cpu.asl>
+ #include <southbridge/intel/bd82x6x/acpi/platform.asl>
+ /* global NVS and variables. */
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+ #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
+
+ Device (\_SB.PCI0)
+ {
+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
+ }
+}
diff --git a/src/mainboard/apple/macbookpro10_1/gma-mainboard.ads b/src/mainboard/apple/macbookpro10_1/gma-mainboard.ads
new file mode 100644
index 0000000..d4a5d7d
--- /dev/null
+++ b/src/mainboard/apple/macbookpro10_1/gma-mainboard.ads
@@ -0,0 +1,34 @@
+--
+-- This file is part of the coreboot project.
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ ports : constant Port_List :=
+ (DP1,
+ DP2,
+ DP3,
+ HDMI1,
+ HDMI2,
+ HDMI3,
+ Analog,
+ Internal,
+ others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/apple/macbookpro10_1/gpio.c b/src/mainboard/apple/macbookpro10_1/gpio.c
new file mode 100644
index 0000000..a445687
--- /dev/null
+++ b/src/mainboard/apple/macbookpro10_1/gpio.c
@@ -0,0 +1,243 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio1 = GPIO_MODE_GPIO,
+ .gpio2 = GPIO_MODE_GPIO,
+ .gpio3 = GPIO_MODE_GPIO,
+ .gpio4 = GPIO_MODE_GPIO,
+ .gpio5 = GPIO_MODE_GPIO,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_NATIVE,
+ .gpio10 = GPIO_MODE_GPIO,
+ .gpio11 = GPIO_MODE_GPIO,
+ .gpio12 = GPIO_MODE_GPIO,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_GPIO,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio16 = GPIO_MODE_GPIO,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_NATIVE,
+ .gpio19 = GPIO_MODE_GPIO,
+ .gpio20 = GPIO_MODE_NATIVE,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio23 = GPIO_MODE_GPIO,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_NATIVE,
+ .gpio26 = GPIO_MODE_GPIO,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_GPIO,
+ .gpio30 = GPIO_MODE_NATIVE,
+ .gpio31 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT,
+ .gpio1 = GPIO_DIR_INPUT,
+ .gpio2 = GPIO_DIR_INPUT,
+ .gpio3 = GPIO_DIR_INPUT,
+ .gpio4 = GPIO_DIR_INPUT,
+ .gpio5 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_OUTPUT,
+ .gpio10 = GPIO_DIR_INPUT,
+ .gpio11 = GPIO_DIR_INPUT,
+ .gpio12 = GPIO_DIR_OUTPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio14 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_OUTPUT,
+ .gpio16 = GPIO_DIR_OUTPUT,
+ .gpio17 = GPIO_DIR_INPUT,
+ .gpio19 = GPIO_DIR_OUTPUT,
+ .gpio21 = GPIO_DIR_OUTPUT,
+ .gpio22 = GPIO_DIR_OUTPUT,
+ .gpio23 = GPIO_DIR_OUTPUT,
+ .gpio24 = GPIO_DIR_OUTPUT,
+ .gpio26 = GPIO_DIR_INPUT,
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_OUTPUT,
+ .gpio29 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio8 = GPIO_LEVEL_HIGH,
+ .gpio12 = GPIO_LEVEL_LOW,
+ .gpio15 = GPIO_LEVEL_HIGH,
+ .gpio16 = GPIO_LEVEL_LOW,
+ .gpio19 = GPIO_LEVEL_HIGH,
+ .gpio21 = GPIO_LEVEL_LOW,
+ .gpio22 = GPIO_LEVEL_LOW,
+ .gpio23 = GPIO_LEVEL_HIGH,
+ .gpio24 = GPIO_LEVEL_LOW,
+ .gpio28 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+ .gpio11 = GPIO_RESET_RSMRST,
+ .gpio15 = GPIO_RESET_RSMRST,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio1 = GPIO_INVERT,
+ .gpio2 = GPIO_INVERT,
+ .gpio4 = GPIO_INVERT,
+ .gpio5 = GPIO_INVERT,
+ .gpio7 = GPIO_INVERT,
+ .gpio14 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_NATIVE,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_GPIO,
+ .gpio36 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio40 = GPIO_MODE_NATIVE,
+ .gpio41 = GPIO_MODE_NATIVE,
+ .gpio42 = GPIO_MODE_NATIVE,
+ .gpio43 = GPIO_MODE_NATIVE,
+ .gpio44 = GPIO_MODE_NATIVE,
+ .gpio45 = GPIO_MODE_NATIVE,
+ .gpio46 = GPIO_MODE_NATIVE,
+ .gpio47 = GPIO_MODE_GPIO,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio50 = GPIO_MODE_GPIO,
+ .gpio51 = GPIO_MODE_GPIO,
+ .gpio52 = GPIO_MODE_GPIO,
+ .gpio53 = GPIO_MODE_GPIO,
+ .gpio54 = GPIO_MODE_GPIO,
+ .gpio55 = GPIO_MODE_GPIO,
+ .gpio56 = GPIO_MODE_GPIO,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_NATIVE,
+ .gpio60 = GPIO_MODE_GPIO,
+ .gpio61 = GPIO_MODE_NATIVE,
+ .gpio62 = GPIO_MODE_NATIVE,
+ .gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio33 = GPIO_DIR_INPUT,
+ .gpio34 = GPIO_DIR_OUTPUT,
+ .gpio35 = GPIO_DIR_OUTPUT,
+ .gpio36 = GPIO_DIR_OUTPUT,
+ .gpio37 = GPIO_DIR_INPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio47 = GPIO_DIR_INPUT,
+ .gpio48 = GPIO_DIR_OUTPUT,
+ .gpio49 = GPIO_DIR_OUTPUT,
+ .gpio50 = GPIO_DIR_INPUT,
+ .gpio51 = GPIO_DIR_OUTPUT,
+ .gpio52 = GPIO_DIR_OUTPUT,
+ .gpio53 = GPIO_DIR_OUTPUT,
+ .gpio54 = GPIO_DIR_OUTPUT,
+ .gpio55 = GPIO_DIR_OUTPUT,
+ .gpio56 = GPIO_DIR_INPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+ .gpio60 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio34 = GPIO_LEVEL_HIGH,
+ .gpio35 = GPIO_LEVEL_LOW,
+ .gpio36 = GPIO_LEVEL_LOW,
+ .gpio48 = GPIO_LEVEL_HIGH,
+ .gpio49 = GPIO_LEVEL_HIGH,
+ .gpio51 = GPIO_LEVEL_HIGH,
+ .gpio52 = GPIO_LEVEL_LOW,
+ .gpio53 = GPIO_LEVEL_HIGH,
+ .gpio54 = GPIO_LEVEL_LOW,
+ .gpio55 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_GPIO,
+ .gpio65 = GPIO_MODE_GPIO,
+ .gpio66 = GPIO_MODE_GPIO,
+ .gpio67 = GPIO_MODE_GPIO,
+ .gpio68 = GPIO_MODE_GPIO,
+ .gpio69 = GPIO_MODE_GPIO,
+ .gpio70 = GPIO_MODE_GPIO,
+ .gpio71 = GPIO_MODE_GPIO,
+ .gpio72 = GPIO_MODE_NATIVE,
+ .gpio73 = GPIO_MODE_GPIO,
+ .gpio74 = GPIO_MODE_GPIO,
+ .gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio64 = GPIO_DIR_OUTPUT,
+ .gpio65 = GPIO_DIR_OUTPUT,
+ .gpio66 = GPIO_DIR_OUTPUT,
+ .gpio67 = GPIO_DIR_OUTPUT,
+ .gpio68 = GPIO_DIR_INPUT,
+ .gpio69 = GPIO_DIR_INPUT,
+ .gpio70 = GPIO_DIR_INPUT,
+ .gpio71 = GPIO_DIR_INPUT,
+ .gpio73 = GPIO_DIR_INPUT,
+ .gpio74 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+ .gpio64 = GPIO_LEVEL_LOW,
+ .gpio65 = GPIO_LEVEL_LOW,
+ .gpio66 = GPIO_LEVEL_LOW,
+ .gpio67 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/apple/macbookpro10_1/hda_verb.c b/src/mainboard/apple/macbookpro10_1/hda_verb.c
new file mode 100644
index 0000000..b8e4855
--- /dev/null
+++ b/src/mainboard/apple/macbookpro10_1/hda_verb.c
@@ -0,0 +1,58 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x10134206, /* Codec Vendor / Device ID: Cirrus */
+ 0x106b2800, /* Subsystem ID */
+
+ 0x0000000b, /* Number of 4 dword sets */
+ /* NID 0x01: Subsystem ID. */
+ AZALIA_SUBVENDOR(0x0, 0x106b2800),
+
+ /* NID 0x09. */
+ AZALIA_PIN_CFG(0x0, 0x09, 0x002b4020),
+
+ /* NID 0x0a. */
+ AZALIA_PIN_CFG(0x0, 0x0a, 0x90100112),
+
+ /* NID 0x0b. */
+ AZALIA_PIN_CFG(0x0, 0x0b, 0x90100110),
+
+ /* NID 0x0c. */
+ AZALIA_PIN_CFG(0x0, 0x0c, 0x400000f0),
+
+ /* NID 0x0d. */
+ AZALIA_PIN_CFG(0x0, 0x0d, 0x400000f0),
+
+ /* NID 0x0e. */
+ AZALIA_PIN_CFG(0x0, 0x0e, 0x90a60100),
+
+ /* NID 0x0f. */
+ AZALIA_PIN_CFG(0x0, 0x0f, 0x400000f0),
+
+ /* NID 0x10. */
+ AZALIA_PIN_CFG(0x0, 0x10, 0x004be030),
+
+ /* NID 0x12. */
+ AZALIA_PIN_CFG(0x0, 0x12, 0x400000f0),
+
+ /* NID 0x15. */
+ AZALIA_PIN_CFG(0x0, 0x15, 0x400000f0),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/apple/macbookpro10_1/mainboard.c b/src/mainboard/apple/macbookpro10_1/mainboard.c
new file mode 100644
index 0000000..3910541
--- /dev/null
+++ b/src/mainboard/apple/macbookpro10_1/mainboard.c
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/device.h>
+#include <drivers/intel/gma/int15.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <ec/acpi/ec.h>
+#include <console/console.h>
+
+static void mainboard_init(struct device *dev)
+{
+
+}
+
+static void mainboard_enable(struct device *dev)
+{
+ dev->ops->init = mainboard_init;
+
+ /* FIXME: fix those values*/
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
+ GMA_INT15_PANEL_FIT_DEFAULT,
+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/apple/macbookpro10_1/romstage.c b/src/mainboard/apple/macbookpro10_1/romstage.c
new file mode 100644
index 0000000..c35604b
--- /dev/null
+++ b/src/mainboard/apple/macbookpro10_1/romstage.c
@@ -0,0 +1,82 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* FIXME: Check if all includes are needed. */
+
+#include <stdint.h>
+#include <string.h>
+#include <timestamp.h>
+#include <arch/byteorder.h>
+#include <arch/io.h>
+#include <device/mmio.h>
+#include <device/pci_ops.h>
+#include <device/pnp_ops.h>
+#include <console/console.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/gpio.h>
+#include <cbfs.h>
+
+void pch_enable_lpc(void)
+{
+ pci_write_config16(PCH_LPC_DEV, 0x82, 0x3f0f);
+ pci_write_config32(PCH_LPC_DEV, 0x84, 0x000c0681);
+ pci_write_config32(PCH_LPC_DEV, 0x88, 0x000c1641);
+ pci_write_config32(PCH_LPC_DEV, 0x8c, 0x001c0301);
+ pci_write_config32(PCH_LPC_DEV, 0x90, 0x00fc0701);
+ pci_write_config16(PCH_LPC_DEV, 0x80, 0x0070);
+}
+
+void mainboard_rcba_config(void)
+{
+}
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+ { 1, 0, 0 },
+ { 1, 0, 1 },
+ { 1, 0, 2 },
+ { 1, 0, 3 },
+ { 1, 0, -1 },
+ { 1, 0, -1 },
+ { 1, 0, -1 },
+ { 1, 0, -1 },
+ { 1, 0, -1 },
+ { 1, 0, -1 },
+ { 1, 0, -1 },
+ { 1, 0, -1 },
+ { 1, 0, -1 },
+ { 1, 0, -1 },
+};
+
+void mainboard_early_init(int s3resume)
+{
+}
+
+void mainboard_config_superio(void)
+{
+}
+
+// FIXME
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+{
+ void *spd_file;
+ size_t spd_file_len = 0;
+ spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,
+ &spd_file_len);
+ if (spd_file && spd_file_len >= 128) {
+ memcpy(&spd[0], spd_file, 128);
+ memcpy(&spd[2], spd_file, 128);
+ }
+}
--
To view, visit https://review.coreboot.org/c/coreboot/+/32673
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ica03aba442493c0d369a3d360ad569ddc16954df
Gerrit-Change-Number: 32673
Gerrit-PatchSet: 1
Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.com>
Gerrit-MessageType: newchange
2 weeks, 1 day
- 5
- 35
Change in ...coreboot[master]: mb/apple: Add MacBook Air 5,2 (A1466)
by Evgeny Zinoviev (Code Review)
Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32604
Change subject: mb/apple: Add MacBook Air 5,2 (A1466)
......................................................................
mb/apple: Add MacBook Air 5,2 (A1466)
This is WIP.
Change-Id: I1ebe6f87a8254871698be74f913b9d969d722447
Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io>
---
A src/mainboard/apple/macbookair5_2/Kconfig
A src/mainboard/apple/macbookair5_2/Kconfig.name
A src/mainboard/apple/macbookair5_2/Makefile.inc
A src/mainboard/apple/macbookair5_2/acpi/ec.asl
A src/mainboard/apple/macbookair5_2/acpi/platform.asl
A src/mainboard/apple/macbookair5_2/acpi/superio.asl
A src/mainboard/apple/macbookair5_2/acpi_tables.c
A src/mainboard/apple/macbookair5_2/board_info.txt
A src/mainboard/apple/macbookair5_2/devicetree.cb
A src/mainboard/apple/macbookair5_2/dsdt.asl
A src/mainboard/apple/macbookair5_2/gma-mainboard.ads
A src/mainboard/apple/macbookair5_2/gnvs.c
A src/mainboard/apple/macbookair5_2/gpio.c
A src/mainboard/apple/macbookair5_2/hda_verb.c
A src/mainboard/apple/macbookair5_2/mainboard.c
A src/mainboard/apple/macbookair5_2/romstage.c
A src/mainboard/apple/macbookair5_2/spd.bin
17 files changed, 843 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/32604/1
diff --git a/src/mainboard/apple/macbookair5_2/Kconfig b/src/mainboard/apple/macbookair5_2/Kconfig
new file mode 100644
index 0000000..853021f
--- /dev/null
+++ b/src/mainboard/apple/macbookair5_2/Kconfig
@@ -0,0 +1,55 @@
+if BOARD_APPLE_MACBOOKAIR5_2
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select BOARD_ROMSIZE_KB_8192
+ select EC_ACPI
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select INTEL_INT15
+ select NORTHBRIDGE_INTEL_IVYBRIDGE
+ select SERIRQ_CONTINUOUS_MODE
+ select SOUTHBRIDGE_INTEL_C216
+ select SYSTEM_TYPE_LAPTOP
+ select USE_NATIVE_RAMINIT
+ select MAINBOARD_HAS_LIBGFXINIT
+ select GFX_GMA_INTERNAL_IS_LVDS
+ select SERIRQ_CONTINUOUS_MODE
+
+config MAINBOARD_DIR
+ string
+ default apple/macbookair5_2
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "MacBookAir5,2"
+
+config VGA_BIOS_FILE
+ string
+ default "pci8086,0166.rom"
+
+config VGA_BIOS_ID
+ string
+ default "8086,0166"
+
+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+ hex
+ default 0x7270
+
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+ hex
+ default 0x8086
+
+config DRAM_RESET_GATE_GPIO # FIXME: check this
+ int
+ default 60
+
+config MAX_CPUS
+ int
+ default 8
+
+config MAINBOARD_SMBIOS_MANUFACTURER
+ string
+ default "Apple Inc."
+
+endif
diff --git a/src/mainboard/apple/macbookair5_2/Kconfig.name b/src/mainboard/apple/macbookair5_2/Kconfig.name
new file mode 100644
index 0000000..d8a1fbf
--- /dev/null
+++ b/src/mainboard/apple/macbookair5_2/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_APPLE_MACBOOKAIR5_2
+ bool "MacBookAir5,2"
diff --git a/src/mainboard/apple/macbookair5_2/Makefile.inc b/src/mainboard/apple/macbookair5_2/Makefile.inc
new file mode 100644
index 0000000..fd60338
--- /dev/null
+++ b/src/mainboard/apple/macbookair5_2/Makefile.inc
@@ -0,0 +1,7 @@
+romstage-y += gpio.c
+
+cbfs-files-y += spd.bin
+spd.bin-file := spd.bin
+spd.bin-type := spd
+
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/apple/macbookair5_2/acpi/ec.asl b/src/mainboard/apple/macbookair5_2/acpi/ec.asl
new file mode 100644
index 0000000..f70cb3d
--- /dev/null
+++ b/src/mainboard/apple/macbookair5_2/acpi/ec.asl
@@ -0,0 +1,20 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Device(EC)
+{
+ Name (_HID, EISAID("PNP0C09"))
+ Name (_UID, 0)
+ Name (_GPE, 23)
+/* FIXME: EC support */
+}
diff --git a/src/mainboard/apple/macbookair5_2/acpi/platform.asl b/src/mainboard/apple/macbookair5_2/acpi/platform.asl
new file mode 100644
index 0000000..a17c6ea
--- /dev/null
+++ b/src/mainboard/apple/macbookair5_2/acpi/platform.asl
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Method(_WAK,1)
+{
+ /* FIXME: EC support */
+ Return(Package(){0,0})
+}
+
+Method(_PTS,1)
+{
+ /* FIXME: EC support */
+}
diff --git a/src/mainboard/apple/macbookair5_2/acpi/superio.asl b/src/mainboard/apple/macbookair5_2/acpi/superio.asl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/apple/macbookair5_2/acpi/superio.asl
diff --git a/src/mainboard/apple/macbookair5_2/acpi_tables.c b/src/mainboard/apple/macbookair5_2/acpi_tables.c
new file mode 100644
index 0000000..c48f0bd
--- /dev/null
+++ b/src/mainboard/apple/macbookair5_2/acpi_tables.c
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/bd82x6x/nvs.h>
+
+/* FIXME: check this function. */
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+ /* Disable USB ports in S3 by default */
+ gnvs->s3u0 = 0;
+ gnvs->s3u1 = 0;
+
+ /* Disable USB ports in S5 by default */
+ gnvs->s5u0 = 0;
+ gnvs->s5u1 = 0;
+
+ // the lid is open by default.
+ gnvs->lids = 1;
+
+ gnvs->tcrt = 100;
+ gnvs->tpsv = 90;
+}
diff --git a/src/mainboard/apple/macbookair5_2/board_info.txt b/src/mainboard/apple/macbookair5_2/board_info.txt
new file mode 100644
index 0000000..cbd72ee
--- /dev/null
+++ b/src/mainboard/apple/macbookair5_2/board_info.txt
@@ -0,0 +1,6 @@
+Category: laptop
+ROM protocol: SPI
+Flashrom support: n
+ROM package: WSON-8
+ROM socketed: n
+Release year: 2012
diff --git a/src/mainboard/apple/macbookair5_2/devicetree.cb b/src/mainboard/apple/macbookair5_2/devicetree.cb
new file mode 100644
index 0000000..efc5ddb
--- /dev/null
+++ b/src/mainboard/apple/macbookair5_2/devicetree.cb
@@ -0,0 +1,119 @@
+chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did
+ register "gfx.did" = "{ 0x80000410, 0x80000320, 0x80000410, 0x80000410, 0x00000005 }"
+ #register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }"
+ register "gfx.link_frequency_270_mhz" = "0"
+ register "gfx.ndid" = "2"
+ register "gfx.use_spread_spectrum_clock" = "1"
+ register "gpu_cpu_backlight" = "0x00000710"
+ register "gpu_dp_b_hotplug" = "4"
+ register "gpu_dp_c_hotplug" = "4"
+ register "gpu_dp_d_hotplug" = "4"
+ register "gpu_panel_port_select" = "1"
+ register "gpu_panel_power_backlight_off_delay" = "2000"
+ register "gpu_panel_power_backlight_on_delay" = "10"
+ register "gpu_panel_power_cycle_delay" = "6"
+ register "gpu_panel_power_down_delay" = "740"
+ register "gpu_panel_power_up_delay" = "2000"
+ register "gpu_pch_backlight" = "0x07100710"
+ device cpu_cluster 0x0 on
+ chip cpu/intel/model_206ax # FIXME: check all registers
+ register "c1_acpower" = "1"
+ register "c1_battery" = "1"
+ register "c2_acpower" = "3"
+ register "c2_battery" = "3"
+ register "c3_acpower" = "5"
+ register "c3_battery" = "5"
+ device lapic 0x0 on end
+ device lapic 0xacac off end
+ end
+ end
+
+ register "pci_mmio_size" = "2048"
+
+ device domain 0x0 on
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+ register "c2_latency" = "0x0065"
+ register "docking_supported" = "0"
+ register "gen1_dec" = "0x000c0681"
+ register "gen2_dec" = "0x000c1641"
+ register "gen3_dec" = "0x001c0301"
+ register "gen4_dec" = "0x00fc0701"
+ register "gpi7_routing" = "2"
+ register "p_cnt_throttling_supported" = "1"
+ register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
+ register "pcie_port_coalesce" = "1"
+ register "sata_interface_speed_support" = "0x3"
+ register "sata_port_map" = "0x1"
+ register "spi_lvscc" = "0x0"
+ register "spi_uvscc" = "0x2005"
+ register "superspeed_capable_ports" = "0x0000000f"
+ register "xhci_overcurrent_mapping" = "0x08040201"
+ register "xhci_switchable_ports" = "0x0000000f"
+ device pci 14.0 on # USB 3.0 Controller
+ subsystemid 0x8086 0x7270
+ end
+ device pci 16.0 on # Management Engine Interface 1
+ subsystemid 0x8086 0x7270
+ end
+ device pci 16.1 off # Management Engine Interface 2
+ end
+ device pci 16.2 off # Management Engine IDE-R
+ end
+ device pci 16.3 off # Management Engine KT
+ end
+ device pci 19.0 off # Intel Gigabit Ethernet
+ end
+ device pci 1a.0 on # USB2 EHCI #2
+ subsystemid 0x8086 0x7270
+ end
+ device pci 1b.0 on # High Definition Audio Audio controller
+ subsystemid 0x8086 0x7270
+ end
+ device pci 1c.0 on # PCIe Port #1
+ subsystemid 0x8086 0x7270
+ end
+ device pci 1c.1 on # PCIe Port #2
+ subsystemid 0x8086 0x7270
+ end
+ device pci 1c.2 off # PCIe Port #3
+ end
+ device pci 1c.3 off # PCIe Port #4
+ end
+ device pci 1c.4 on # PCIe Port #5
+ subsystemid 0x8086 0x7270
+ end
+ device pci 1c.5 off # PCIe Port #6
+ end
+ device pci 1c.6 off # PCIe Port #7
+ end
+ device pci 1c.7 off # PCIe Port #8
+ end
+ device pci 1d.0 on # USB2 EHCI #1
+ subsystemid 0x8086 0x7270
+ end
+ device pci 1e.0 off # PCI bridge
+ end
+ device pci 1f.0 on # LPC bridge PCI-LPC bridge
+ subsystemid 0x8086 0x7270
+ end
+ device pci 1f.2 on # SATA Controller 1
+ subsystemid 0x8086 0x7270
+ end
+ device pci 1f.3 on # SMBus
+ subsystemid 0x8086 0x7270
+ end
+ device pci 1f.5 off # SATA Controller 2
+ end
+ device pci 1f.6 off # Thermal
+ end
+ end
+ device pci 00.0 on # Host bridge Host bridge
+ subsystemid 0x106b 0x00fe
+ end
+ device pci 01.0 off # PCIe Bridge for discrete graphics
+ end
+ device pci 02.0 on # Internal graphics VGA controller
+ subsystemid 0x106b 0x00fe
+ end
+ end
+end
diff --git a/src/mainboard/apple/macbookair5_2/dsdt.asl b/src/mainboard/apple/macbookair5_2/dsdt.asl
new file mode 100644
index 0000000..455ac17
--- /dev/null
+++ b/src/mainboard/apple/macbookair5_2/dsdt.asl
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
+#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
+
+#include <arch/acpi.h>
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, // DSDT revision: ACPI 2.0 and up
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20141018 // OEM revision
+)
+{
+ /* Some generic macros */
+ #include "acpi/platform.asl"
+ #include <cpu/intel/common/acpi/cpu.asl>
+ #include <southbridge/intel/bd82x6x/acpi/platform.asl>
+ /* global NVS and variables. */
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+ #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
+
+ Device (\_SB.PCI0)
+ {
+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
+ }
+}
diff --git a/src/mainboard/apple/macbookair5_2/gma-mainboard.ads b/src/mainboard/apple/macbookair5_2/gma-mainboard.ads
new file mode 100644
index 0000000..d4a5d7d
--- /dev/null
+++ b/src/mainboard/apple/macbookair5_2/gma-mainboard.ads
@@ -0,0 +1,34 @@
+--
+-- This file is part of the coreboot project.
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ ports : constant Port_List :=
+ (DP1,
+ DP2,
+ DP3,
+ HDMI1,
+ HDMI2,
+ HDMI3,
+ Analog,
+ Internal,
+ others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/apple/macbookair5_2/gnvs.c b/src/mainboard/apple/macbookair5_2/gnvs.c
new file mode 100644
index 0000000..def9e5f
--- /dev/null
+++ b/src/mainboard/apple/macbookair5_2/gnvs.c
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/bd82x6x/nvs.h>
+
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+ /* Disable USB ports in S3 by default */
+ gnvs->s3u0 = 0;
+ gnvs->s3u1 = 0;
+
+ /* Disable USB ports in S5 by default */
+ gnvs->s5u0 = 0;
+ gnvs->s5u1 = 0;
+
+ /* the lid is open by default. */
+ gnvs->lids = 1;
+
+ gnvs->tcrt = 100;
+ gnvs->tpsv = 90;
+}
diff --git a/src/mainboard/apple/macbookair5_2/gpio.c b/src/mainboard/apple/macbookair5_2/gpio.c
new file mode 100644
index 0000000..9f2cd14
--- /dev/null
+++ b/src/mainboard/apple/macbookair5_2/gpio.c
@@ -0,0 +1,242 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio1 = GPIO_MODE_GPIO,
+ .gpio2 = GPIO_MODE_GPIO,
+ .gpio3 = GPIO_MODE_GPIO,
+ .gpio4 = GPIO_MODE_GPIO,
+ .gpio5 = GPIO_MODE_GPIO,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_NATIVE,
+ .gpio10 = GPIO_MODE_GPIO,
+ .gpio11 = GPIO_MODE_GPIO,
+ .gpio12 = GPIO_MODE_GPIO,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_GPIO,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio16 = GPIO_MODE_GPIO,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_NATIVE,
+ .gpio19 = GPIO_MODE_GPIO,
+ .gpio20 = GPIO_MODE_NATIVE,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio23 = GPIO_MODE_GPIO,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_NATIVE,
+ .gpio26 = GPIO_MODE_GPIO,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_GPIO,
+ .gpio30 = GPIO_MODE_NATIVE,
+ .gpio31 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT,
+ .gpio1 = GPIO_DIR_INPUT,
+ .gpio2 = GPIO_DIR_INPUT,
+ .gpio3 = GPIO_DIR_INPUT,
+ .gpio4 = GPIO_DIR_INPUT,
+ .gpio5 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_OUTPUT,
+ .gpio10 = GPIO_DIR_INPUT,
+ .gpio11 = GPIO_DIR_INPUT,
+ .gpio12 = GPIO_DIR_OUTPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio14 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_OUTPUT,
+ .gpio16 = GPIO_DIR_OUTPUT,
+ .gpio17 = GPIO_DIR_INPUT,
+ .gpio19 = GPIO_DIR_OUTPUT,
+ .gpio21 = GPIO_DIR_OUTPUT,
+ .gpio22 = GPIO_DIR_OUTPUT,
+ .gpio23 = GPIO_DIR_OUTPUT,
+ .gpio24 = GPIO_DIR_OUTPUT,
+ .gpio26 = GPIO_DIR_INPUT,
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_OUTPUT,
+ .gpio29 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio8 = GPIO_LEVEL_HIGH,
+ .gpio12 = GPIO_LEVEL_LOW,
+ .gpio15 = GPIO_LEVEL_HIGH,
+ .gpio16 = GPIO_LEVEL_LOW,
+ .gpio19 = GPIO_LEVEL_HIGH,
+ .gpio21 = GPIO_LEVEL_LOW,
+ .gpio22 = GPIO_LEVEL_LOW,
+ .gpio23 = GPIO_LEVEL_HIGH,
+ .gpio24 = GPIO_LEVEL_LOW,
+ .gpio28 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+ .gpio11 = GPIO_RESET_RSMRST,
+ .gpio15 = GPIO_RESET_RSMRST,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio1 = GPIO_INVERT,
+ .gpio2 = GPIO_INVERT,
+ .gpio4 = GPIO_INVERT,
+ .gpio5 = GPIO_INVERT,
+ .gpio7 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_NATIVE,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_GPIO,
+ .gpio36 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio40 = GPIO_MODE_NATIVE,
+ .gpio41 = GPIO_MODE_NATIVE,
+ .gpio42 = GPIO_MODE_NATIVE,
+ .gpio43 = GPIO_MODE_NATIVE,
+ .gpio44 = GPIO_MODE_NATIVE,
+ .gpio45 = GPIO_MODE_NATIVE,
+ .gpio46 = GPIO_MODE_NATIVE,
+ .gpio47 = GPIO_MODE_GPIO,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio50 = GPIO_MODE_GPIO,
+ .gpio51 = GPIO_MODE_GPIO,
+ .gpio52 = GPIO_MODE_GPIO,
+ .gpio53 = GPIO_MODE_GPIO,
+ .gpio54 = GPIO_MODE_GPIO,
+ .gpio55 = GPIO_MODE_GPIO,
+ .gpio56 = GPIO_MODE_GPIO,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_NATIVE,
+ .gpio60 = GPIO_MODE_GPIO,
+ .gpio61 = GPIO_MODE_NATIVE,
+ .gpio62 = GPIO_MODE_NATIVE,
+ .gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio33 = GPIO_DIR_INPUT,
+ .gpio34 = GPIO_DIR_OUTPUT,
+ .gpio35 = GPIO_DIR_OUTPUT,
+ .gpio36 = GPIO_DIR_OUTPUT,
+ .gpio37 = GPIO_DIR_INPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio47 = GPIO_DIR_INPUT,
+ .gpio48 = GPIO_DIR_OUTPUT,
+ .gpio49 = GPIO_DIR_OUTPUT,
+ .gpio50 = GPIO_DIR_INPUT,
+ .gpio51 = GPIO_DIR_OUTPUT,
+ .gpio52 = GPIO_DIR_OUTPUT,
+ .gpio53 = GPIO_DIR_OUTPUT,
+ .gpio54 = GPIO_DIR_OUTPUT,
+ .gpio55 = GPIO_DIR_OUTPUT,
+ .gpio56 = GPIO_DIR_INPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+ .gpio60 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio34 = GPIO_LEVEL_HIGH,
+ .gpio35 = GPIO_LEVEL_LOW,
+ .gpio36 = GPIO_LEVEL_LOW,
+ .gpio48 = GPIO_LEVEL_HIGH,
+ .gpio49 = GPIO_LEVEL_LOW,
+ .gpio51 = GPIO_LEVEL_HIGH,
+ .gpio52 = GPIO_LEVEL_LOW,
+ .gpio53 = GPIO_LEVEL_HIGH,
+ .gpio54 = GPIO_LEVEL_LOW,
+ .gpio55 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_GPIO,
+ .gpio65 = GPIO_MODE_GPIO,
+ .gpio66 = GPIO_MODE_GPIO,
+ .gpio67 = GPIO_MODE_GPIO,
+ .gpio68 = GPIO_MODE_GPIO,
+ .gpio69 = GPIO_MODE_GPIO,
+ .gpio70 = GPIO_MODE_GPIO,
+ .gpio71 = GPIO_MODE_GPIO,
+ .gpio72 = GPIO_MODE_NATIVE,
+ .gpio73 = GPIO_MODE_NATIVE,
+ .gpio74 = GPIO_MODE_GPIO,
+ .gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio64 = GPIO_DIR_OUTPUT,
+ .gpio65 = GPIO_DIR_OUTPUT,
+ .gpio66 = GPIO_DIR_OUTPUT,
+ .gpio67 = GPIO_DIR_OUTPUT,
+ .gpio68 = GPIO_DIR_INPUT,
+ .gpio69 = GPIO_DIR_INPUT,
+ .gpio70 = GPIO_DIR_INPUT,
+ .gpio71 = GPIO_DIR_INPUT,
+ .gpio74 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+ .gpio64 = GPIO_LEVEL_LOW,
+ .gpio65 = GPIO_LEVEL_LOW,
+ .gpio66 = GPIO_LEVEL_LOW,
+ .gpio67 = GPIO_LEVEL_LOW,
+ .gpio74 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/apple/macbookair5_2/hda_verb.c b/src/mainboard/apple/macbookair5_2/hda_verb.c
new file mode 100644
index 0000000..6c8e555
--- /dev/null
+++ b/src/mainboard/apple/macbookair5_2/hda_verb.c
@@ -0,0 +1,76 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x10134206, /* Codec Vendor / Device ID: Cirrus */
+ 0x106b5600, /* Subsystem ID */
+
+ 0x0000000b, /* Number of 4 dword sets */
+ /* NID 0x01: Subsystem ID. */
+ AZALIA_SUBVENDOR(0x0, 0x106b5600),
+
+ /* NID 0x09. */
+ AZALIA_PIN_CFG(0x0, 0x09, 0x0e2b4030),
+
+ /* NID 0x0a. */
+ AZALIA_PIN_CFG(0x0, 0x0a, 0x400000f0),
+
+ /* NID 0x0b. */
+ AZALIA_PIN_CFG(0x0, 0x0b, 0x90100120),
+
+ /* NID 0x0c. */
+ AZALIA_PIN_CFG(0x0, 0x0c, 0x400000f0),
+
+ /* NID 0x0d. */
+ AZALIA_PIN_CFG(0x0, 0x0d, 0x90a00110),
+
+ /* NID 0x0e. */
+ AZALIA_PIN_CFG(0x0, 0x0e, 0x400000f0),
+
+ /* NID 0x0f. */
+ AZALIA_PIN_CFG(0x0, 0x0f, 0x400000f0),
+
+ /* NID 0x10. */
+ AZALIA_PIN_CFG(0x0, 0x10, 0x400000f0),
+
+ /* NID 0x12. */
+ AZALIA_PIN_CFG(0x0, 0x12, 0x400000f0),
+
+ /* NID 0x15. */
+ AZALIA_PIN_CFG(0x0, 0x15, 0x400000f0),
+ 0x80862806, /* Codec Vendor / Device ID: Intel */
+ 0x80860101, /* Subsystem ID */
+
+ 0x00000004, /* Number of 4 dword sets */
+ /* NID 0x01: Subsystem ID. */
+ AZALIA_SUBVENDOR(0x3, 0x80860101),
+
+ /* NID 0x05. */
+ AZALIA_PIN_CFG(0x3, 0x05, 0x18560010),
+
+ /* NID 0x06. */
+ AZALIA_PIN_CFG(0x3, 0x06, 0x18560010),
+
+ /* NID 0x07. */
+ AZALIA_PIN_CFG(0x3, 0x07, 0x18560010),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/apple/macbookair5_2/mainboard.c b/src/mainboard/apple/macbookair5_2/mainboard.c
new file mode 100644
index 0000000..d497c51
--- /dev/null
+++ b/src/mainboard/apple/macbookair5_2/mainboard.c
@@ -0,0 +1,67 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/device.h>
+#include <drivers/intel/gma/int15.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <ec/acpi/ec.h>
+#include <console/console.h>
+
+static void mainboard_init(struct device *dev)
+{
+ /* FIXME: trim this down or remove if necessary */
+// {
+// int i;
+// const u8 dmp[256] = {
+// /* 00 */ 0x40, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+// /* 10 */ 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+// /* 20 */ 0x00, 0x80, 0x16, 0x16, 0xe0, 0x40, 0x4f, 0x4e, 0x7a, 0x34, 0x35, 0x31, 0x38, 0x31, 0x32, 0x44,
+// /* 30 */ 0x4b, 0x52, 0x4e, 0x41, 0x38, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x41, 0x42,
+// /* 40 */ 0x43, 0x44, 0x45, 0x00, 0x02, 0x14, 0x11, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+// /* 50 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+// /* 60 */ 0x03, 0x00, 0x00, 0x00, 0x0f, 0x3d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+// /* 70 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+// /* 80 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+// /* 90 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+// /* a0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+// /* b0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+// /* c0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+// /* d0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+// /* e0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+// /* f0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+// };
+//
+// printk(BIOS_DEBUG, "Replaying EC dump ...");
+// for (i = 0; i < 256; i++)
+// ec_write (i, dmp[i]);
+// printk(BIOS_DEBUG, "done\n");
+// }
+
+ RCBA32(0x38c8) = 0x00002005;
+ RCBA32(0x38c4) = 0x00800000;
+}
+
+static void mainboard_enable(struct device *dev)
+{
+ dev->ops->init = mainboard_init;
+
+// /* FIXME: fix those values*/
+// install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
+// GMA_INT15_PANEL_FIT_DEFAULT,
+// GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/apple/macbookair5_2/romstage.c b/src/mainboard/apple/macbookair5_2/romstage.c
new file mode 100644
index 0000000..6594b15
--- /dev/null
+++ b/src/mainboard/apple/macbookair5_2/romstage.c
@@ -0,0 +1,86 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* FIXME: Check if all includes are needed. */
+
+#include <stdint.h>
+#include <string.h>
+#include <timestamp.h>
+#include <arch/byteorder.h>
+#include <arch/io.h>
+#include <device/mmio.h>
+#include <device/pci_ops.h>
+#include <device/pnp_ops.h>
+#include <console/console.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/gpio.h>
+#include <cbfs.h>
+
+void pch_enable_lpc(void)
+{
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x40, 0x00000401);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0070);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x000c0681);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c1641);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x001c0301);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00fc0701);
+}
+
+void mainboard_rcba_config(void)
+{
+ RCBA32(0x3414) = 0x00000020;
+}
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+ { 1, 0, 0 },
+ { 1, 0, 1 },
+ { 1, 0, 2 },
+ { 1, 0, 3 },
+ { 1, 0, -1 },
+ { 1, 0, -1 },
+ { 1, 0, -1 },
+ { 1, 0, -1 },
+ { 1, 0, -1 },
+ { 1, 0, -1 },
+ { 1, 0, -1 },
+ { 1, 0, -1 },
+ { 1, 0, -1 },
+ { 1, 0, -1 },
+};
+
+void mainboard_early_init(int s3resume)
+{
+}
+
+void mainboard_config_superio(void)
+{
+}
+
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+{
+ void *spd_file;
+ size_t spd_file_len = 0;
+ spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,
+ &spd_file_len);
+ if (spd_file && spd_file_len >= 512) {
+ memcpy(&spd[0], spd_file, 128);
+ memcpy(&spd[2], spd_file + 256, 128);
+ }
+}
diff --git a/src/mainboard/apple/macbookair5_2/spd.bin b/src/mainboard/apple/macbookair5_2/spd.bin
new file mode 100644
index 0000000..2e2a6b4
--- /dev/null
+++ b/src/mainboard/apple/macbookair5_2/spd.bin
Binary files differ
--
To view, visit https://review.coreboot.org/c/coreboot/+/32604
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I1ebe6f87a8254871698be74f913b9d969d722447
Gerrit-Change-Number: 32604
Gerrit-PatchSet: 1
Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.com>
Gerrit-MessageType: newchange
2 weeks, 5 days
- 6
- 41
Change in ...coreboot[master]: mb/apple/macbook21: Use common ACPI code
by Evgeny Zinoviev (Code Review)
Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33104
Change subject: mb/apple/macbook21: Use common ACPI code
......................................................................
mb/apple/macbook21: Use common ACPI code
Use common ACPI code from ec/apple to avoid duplication between boards.
Change-Id: I790d1353adea432e9697c5edf0dbb7841d308728
Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io>
---
M src/mainboard/apple/macbook21/acpi/ec.asl
1 file changed, 5 insertions(+), 232 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/33104/1
diff --git a/src/mainboard/apple/macbook21/acpi/ec.asl b/src/mainboard/apple/macbook21/acpi/ec.asl
index 0a8ebca..bd56af5 100644
--- a/src/mainboard/apple/macbook21/acpi/ec.asl
+++ b/src/mainboard/apple/macbook21/acpi/ec.asl
@@ -1,6 +1,8 @@
/*
* This file is part of the coreboot project.
*
+ * Copyright (c) 2019 Evgeny Zinoviev <me(a)ch1p.io>
+ *
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
@@ -11,235 +13,6 @@
* GNU General Public License for more details.
*/
-Device(EC)
-{
- Name(_HID, EISAID("PNP0C09"))
- Name(_UID, 0)
-
- Name(_GPE, 0x17)
- Mutex(ECLK, 0)
-
- OperationRegion(ERAM, EmbeddedControl, 0x00, 0x100)
- Field(ERAM, ByteAcc, NoLock, Preserve)
- {
- Offset(0x01),
- LIDS, 1, /* Lid status */
- HPAC, 1,
- Offset(0x02),
- WKLD, 1, /* Lid wake */
-
- Offset(0x20),
- SPTR, 8,
- SSTS, 8,
- SADR, 8,
- SCMD, 8,
- SBFR, 256,
- }
- Field(ERAM, ByteAcc, Lock, Preserve)
- {
- Offset(0x24),
- SBDW, 16,
- }
-
- Method(SBPC, 0, NotSerialized)
- {
- Store(1000, Local0)
- While(Local0)
- {
- If(LEqual(SPTR, 0x00))
- {
- Return()
- }
-
- Sleep(1)
- Decrement(Local0)
- }
- }
-
- Method(SBRW, 2, NotSerialized)
- {
- Acquire(ECLK, 0xFFFF)
- Store(ShiftLeft(Arg0, 0x01), SADR)
- Store(Arg1, SCMD)
- Store(0x09, SPTR)
- SBPC()
- Store(SBDW, Local0)
- Release(ECLK)
- Return(Local0)
- }
-
- Method(SBRB, 2, NotSerialized)
- {
- Acquire(ECLK, 0xFFFF)
- Store(ShiftLeft(Arg0, 0x01), SADR)
- Store(Arg1, SCMD)
- Store(0x0B, SPTR)
- SBPC()
- Store(SBFR, Local0)
- Release(ECLK)
- Return(Local0)
- }
-
- /* LID status change. */
- Method(_Q20, 0, NotSerialized)
- {
- Notify(LID, 0x80)
- }
-
- /* AC status change. */
- Method(_Q21, 0, NotSerialized)
- {
- Notify(AC, 0x80)
- }
-
- Method(_CRS, 0)
- {
- Name(ECMD, ResourceTemplate()
- {
- IO(Decode16, 0x62, 0x62, 1, 1)
- IO(Decode16, 0x66, 0x66, 1, 1)
- })
- Return(ECMD)
- }
-
- Method(_INI, 0, NotSerialized)
- {
- }
-
- Device(LID)
- {
- Name(_HID, "PNP0C0D")
-
- Method(_LID, 0, NotSerialized)
- {
- return(LIDS)
- }
-
- Method(_PRW, 0, NotSerialized)
- {
- Return (Package() { 0x1d, 0x03 })
- }
-
- Method(_PSW, 1, NotSerialized)
- {
- if (Arg0) {
- Store(1, WKLD)
- } else {
- Store(0, WKLD)
- }
- }
- }
-
- Device(AC)
- {
- Name(_HID, "ACPI0003")
- Name(_UID, 0x00)
- Name(_PCL, Package() { \_SB } )
-
- Method(_PSR, 0, NotSerialized)
- {
- return(HPAC)
- }
-
- Method(_STA, 0, NotSerialized)
- {
- Return(0x0f)
- }
- }
-
- Device(BAT0)
- {
- Name(_HID, EisaId("PNP0C0A"))
- Name(_UID, 0x00)
- Name(_PCL, Package() { \_SB })
-
- Name(BATS, Package()
- {
- 0x00, // 0: PowerUnit: Report in mWh
- 0xFFFFFFFF, // 1: Design cap
- 0xFFFFFFFF, // 2: Last full charge cap
- 0x01, // 3: Battery Technology
- 10800, // 4: Design Voltage(mV)
- 0x00, // 5: Warning design capacity
- 200, // 6: Low design capacity
- 10, // 7: granularity1
- 10, // 8: granularity2
- "", // 9: Model number
- "", // A: Serial number
- "", // B: Battery Type
- "" // C: OEM information
- })
-
- Name(BATI, Package()
- {
- 0, // Battery State
- // Bit 0 - discharge
- // Bit 1 - charge
- // Bit 2 - critical state
- 0, // Battery present Rate
- 0, // Battery remaining capacity
- 0 // Battery present voltage
- })
-
- Method(_BIF, 0, NotSerialized)
- {
- Multiply(^^SBRW(0x0B, 0x18), 10, Index(BATS, 0x01))
- Multiply(^^SBRW(0x0B, 0x10), 10, Index(BATS, 0x02))
- Store(^^SBRW(0x0B, 0x19), Index(BATS, 0x04))
- Store(^^SBRB(0x0B, 0x21), Index(BATS, 0x09))
- Store(^^SBRB(0x0B, 0x22), Index(BATS, 0x0B))
- Store(^^SBRB(0x0B, 0x20), Index(BATS, 0x0C))
-
- Return(BATS)
- }
-
- Method(_STA, 0, NotSerialized)
- {
- If(And(^^SBRW(0x0A, 0x01), 0x01)) {
- Return(0x1f)
- } else {
- Return(0x0f)
- }
- }
-
- Method(_BST, 0, NotSerialized)
- {
- /* Check for battery presence. */
- If(LNot(And(^^SBRW(0x0A, 0x01), 0x01))) {
- Return(Package(4) {
- 0,
- 0xFFFFFFFF,
- 0xFFFFFFFF,
- 0xFFFFFFFF
- })
- }
- Store(^^SBRW(0x0B, 0x09), Local1)
- Store(Local1, Index(BATI, 0x03))
- Store(^^SBRW(0x0B, 0x0A), Local0)
- /* Sign-extend Local0. */
- If(And(Local0, 0x8000))
- {
- Not(Local0, Local0)
- And(Increment(Local0), 0xFFFF, Local0)
- }
-
- Multiply(Local0, Local1, Local0)
- Divide(Local0, 1000, , Index(BATI, 1))
- Multiply(^^SBRW(0x0B, 0x0F), 10, Index(BATI, 2))
- If(HPAC)
- {
- If(LNot(And(^^SBRW(0x0B, 0x16), 0x40))) {
- Store(2, Index(BATI, 0))
- } Else {
- Store(0, Index(BATI, 0))
- }
- }
- Else
- {
- Store(0x01, Index(BATI, 0))
- }
-
- Return(BATI)
- }
- }
-}
+#include <ec/apple/acpi/ec.asl>
+#include <ec/apple/acpi/ac_01.asl>
+#include <ec/apple/acpi/lid_01.asl>
--
To view, visit https://review.coreboot.org/c/coreboot/+/33104
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I790d1353adea432e9697c5edf0dbb7841d308728
Gerrit-Change-Number: 33104
Gerrit-PatchSet: 1
Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.com>
Gerrit-MessageType: newchange
3 weeks
- 4
- 8
Change in ...coreboot[master]: configs: add ASUS AM1I-A sample configuration
by Mike Banon (Code Review)
Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33800
Change subject: configs: add ASUS AM1I-A sample configuration
......................................................................
configs: add ASUS AM1I-A sample configuration
You can use this .config as the base configuration for your AM1I-A by saving it
to ./coreboot/.config - however, you may want to change some of its' configs!
If you are using a SSD - you may want to change the "CONFIG_HUDSON_SATA_MODE"
from "0: NATIVE" to "2: AHCI". In addition, I have disabled Intel WiFi adapter
at my .config to save some space ( CONFIG_DRIVERS_INTEL_WIFI is not set ).
If you have any questions/suggestions regarding this .config, please contact me.
Signed-off-by: Mike Banon <mikebdp2(a)gmail.com>
Change-Id: Ide7529762813944b4f91b2ee8b3ef327b5daffc4
---
A configs/config.asus_am1i-a
1 file changed, 789 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/33800/1
diff --git a/configs/config.asus_am1i-a b/configs/config.asus_am1i-a
new file mode 100644
index 0000000..0660c44
--- /dev/null
+++ b/configs/config.asus_am1i-a
@@ -0,0 +1,789 @@
+#########
+###
+### ./coreboot/.config for ASUS AM1I-A - 26 Jun 2019
+###
+#########
+#
+# Automatically generated file; DO NOT EDIT.
+# coreboot configuration
+#
+
+#
+# General setup
+#
+CONFIG_COREBOOT_BUILD=y
+CONFIG_LOCALVERSION=""
+CONFIG_CBFS_PREFIX="fallback"
+CONFIG_COMPILER_GCC=y
+# CONFIG_COMPILER_LLVM_CLANG is not set
+# CONFIG_ANY_TOOLCHAIN is not set
+# CONFIG_CCACHE is not set
+# CONFIG_FMD_GENPARSER is not set
+# CONFIG_UTIL_GENPARSER is not set
+CONFIG_USE_OPTION_TABLE=y
+# CONFIG_STATIC_OPTION_TABLE is not set
+CONFIG_COMPRESS_RAMSTAGE=y
+CONFIG_INCLUDE_CONFIG_FILE=y
+CONFIG_COLLECT_TIMESTAMPS=y
+# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
+# CONFIG_USE_BLOBS is not set
+# CONFIG_COVERAGE is not set
+# CONFIG_UBSAN is not set
+# CONFIG_NO_RELOCATABLE_RAMSTAGE is not set
+CONFIG_RELOCATABLE_RAMSTAGE=y
+# CONFIG_UPDATE_IMAGE is not set
+# CONFIG_BOOTSPLASH_IMAGE is not set
+
+#
+# Mainboard
+#
+
+#
+# Important: Run 'make distclean' before switching boards
+#
+# CONFIG_VENDOR_ADI is not set
+# CONFIG_VENDOR_ADLINK is not set
+# CONFIG_VENDOR_ADVANSUS is not set
+# CONFIG_VENDOR_AMD is not set
+# CONFIG_VENDOR_AOPEN is not set
+# CONFIG_VENDOR_APPLE is not set
+# CONFIG_VENDOR_ASROCK is not set
+CONFIG_VENDOR_ASUS=y
+# CONFIG_VENDOR_AVALUE is not set
+# CONFIG_VENDOR_BAP is not set
+# CONFIG_VENDOR_BIOSTAR is not set
+# CONFIG_VENDOR_CAVIUM is not set
+# CONFIG_VENDOR_COMPULAB is not set
+# CONFIG_VENDOR_CUBIETECH is not set
+# CONFIG_VENDOR_ELMEX is not set
+# CONFIG_VENDOR_EMULATION is not set
+# CONFIG_VENDOR_ESD is not set
+# CONFIG_VENDOR_FACEBOOK is not set
+# CONFIG_VENDOR_FOXCONN is not set
+# CONFIG_VENDOR_GETAC is not set
+# CONFIG_VENDOR_GIGABYTE is not set
+# CONFIG_VENDOR_GIZMOSPHERE is not set
+# CONFIG_VENDOR_GOOGLE is not set
+# CONFIG_VENDOR_HP is not set
+# CONFIG_VENDOR_IBASE is not set
+# CONFIG_VENDOR_IEI is not set
+# CONFIG_VENDOR_INTEL is not set
+# CONFIG_VENDOR_JETWAY is not set
+# CONFIG_VENDOR_KONTRON is not set
+# CONFIG_VENDOR_LENOVO is not set
+# CONFIG_VENDOR_LIPPERT is not set
+# CONFIG_VENDOR_MSI is not set
+# CONFIG_VENDOR_OCP is not set
+# CONFIG_VENDOR_OPENCELLULAR is not set
+# CONFIG_VENDOR_PACKARDBELL is not set
+# CONFIG_VENDOR_PCENGINES is not set
+# CONFIG_VENDOR_PURISM is not set
+# CONFIG_VENDOR_RODA is not set
+# CONFIG_VENDOR_SAMSUNG is not set
+# CONFIG_VENDOR_SAPPHIRE is not set
+# CONFIG_VENDOR_SCALEWAY is not set
+# CONFIG_VENDOR_SIEMENS is not set
+# CONFIG_VENDOR_SIFIVE is not set
+# CONFIG_VENDOR_SUPERMICRO is not set
+# CONFIG_VENDOR_TI is not set
+# CONFIG_VENDOR_TYAN is not set
+# CONFIG_VENDOR_UP is not set
+# CONFIG_VENDOR_VIA is not set
+CONFIG_BOARD_SPECIFIC_OPTIONS=y
+CONFIG_MAINBOARD_DIR="asus/am1i-a"
+CONFIG_MAINBOARD_PART_NUMBER="AM1I-A"
+CONFIG_MAX_CPUS=4
+CONFIG_CBFS_SIZE=0x800000
+CONFIG_UART_FOR_CONSOLE=0
+CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/config_seabios"
+CONFIG_MAINBOARD_VENDOR="ASUS"
+CONFIG_HW_MEM_HOLE_SIZEK=0x200000
+CONFIG_IRQ_SLOT_COUNT=9
+CONFIG_VGA_BIOS_ID="1002,9830"
+CONFIG_ONBOARD_VGA_IS_PRIMARY=y
+# CONFIG_HUDSON_LEGACY_FREE is not set
+CONFIG_DIMM_SPD_SIZE=256
+CONFIG_VGA_BIOS=y
+CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
+CONFIG_AZ_PIN=0xaa
+CONFIG_VGA_BIOS_FILE="pci1002,9830.rom"
+CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000
+CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="ASUS"
+CONFIG_DEVICETREE="devicetree.cb"
+CONFIG_BOARD_ASUS_AM1I_A=y
+# CONFIG_BOARD_ASUS_F2A85_M is not set
+# CONFIG_BOARD_ASUS_F2A85_M_PRO is not set
+# CONFIG_BOARD_ASUS_F2A85_M_LE is not set
+# CONFIG_BOARD_ASUS_H61M_CS is not set
+# CONFIG_BOARD_ASUS_KCMA_D8 is not set
+# CONFIG_BOARD_ASUS_KFSN4_DRE is not set
+# CONFIG_BOARD_ASUS_KGPE_D16 is not set
+# CONFIG_BOARD_ASUS_M4A78_EM is not set
+# CONFIG_BOARD_ASUS_M4A785M is not set
+# CONFIG_BOARD_ASUS_M4A785TM is not set
+# CONFIG_BOARD_ASUS_M5A88_V is not set
+# CONFIG_BOARD_ASUS_MAXIMUS_IV_GENE_Z is not set
+# CONFIG_BOARD_ASUS_P2B_D is not set
+# CONFIG_BOARD_ASUS_P2B_DS is not set
+# CONFIG_BOARD_ASUS_P2B_F is not set
+# CONFIG_BOARD_ASUS_P2B_LS is not set
+# CONFIG_BOARD_ASUS_P2B is not set
+# CONFIG_BOARD_ASUS_P3B_F is not set
+# CONFIG_BOARD_ASUS_P5GC_MX is not set
+# CONFIG_BOARD_ASUS_P5QC is not set
+# CONFIG_BOARD_ASUS_P5Q_PRO is not set
+# CONFIG_BOARD_ASUS_P5QL_PRO is not set
+# CONFIG_BOARD_ASUS_P5QPL_AM is not set
+# CONFIG_BOARD_ASUS_P5G41T_M_LX is not set
+# CONFIG_BOARD_ASUS_P8H61_M_LX is not set
+# CONFIG_BOARD_ASUS_P8H61_M_PRO is not set
+# CONFIG_HUDSON_IMC_FWM is not set
+# CONFIG_HUDSON_XHCI_FWM is not set
+CONFIG_DCACHE_RAM_BASE=0x30000
+CONFIG_DCACHE_RAM_SIZE=0x10000
+CONFIG_MAX_REBOOT_CNT=3
+CONFIG_OVERRIDE_DEVICETREE=""
+CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
+CONFIG_FMDFILE=""
+CONFIG_MMCONF_BASE_ADDRESS=0xF8000000
+CONFIG_DRIVERS_UART_8250IO=y
+# CONFIG_VBOOT is not set
+CONFIG_DIMM_MAX=4
+CONFIG_TPM_PIRQ=0x0
+CONFIG_TTYS0_LCS=3
+CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="AM1I-A"
+CONFIG_CPU_ADDR_BITS=40
+# CONFIG_USBDEBUG is not set
+CONFIG_MAINBOARD_VERSION="1.0"
+# CONFIG_DRIVERS_PS2_KEYBOARD is not set
+CONFIG_PCIEXP_L1_SUB_STATE=y
+CONFIG_SMBIOS_ENCLOSURE_TYPE=0x03
+CONFIG_HEAP_SIZE=0xc0000
+CONFIG_BOARD_ROMSIZE_KB_8192=y
+# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
+CONFIG_COREBOOT_ROMSIZE_KB_8192=y
+# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
+CONFIG_COREBOOT_ROMSIZE_KB=8192
+CONFIG_ROM_SIZE=0x800000
+# CONFIG_SYSTEM_TYPE_LAPTOP is not set
+# CONFIG_SYSTEM_TYPE_TABLET is not set
+# CONFIG_SYSTEM_TYPE_DETACHABLE is not set
+# CONFIG_SYSTEM_TYPE_CONVERTIBLE is not set
+# CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set
+
+#
+# Chipset
+#
+
+#
+# SoC
+#
+CONFIG_UDELAY_LAPIC_FIXED_FSB=200
+CONFIG_MMCONF_BUS_NUMBER=64
+CONFIG_S3_VGA_ROM_RUN=y
+CONFIG_EHCI_BAR=0xfef00000
+CONFIG_ACPI_CPU_STRING="\\_PR.CP%02d"
+# CONFIG_SOC_CAVIUM_CN81XX is not set
+CONFIG_ARCH_ARMV8_EXTENSION=0
+CONFIG_STACK_SIZE=0x1000
+# CONFIG_SOC_CAVIUM_COMMON is not set
+# CONFIG_SOC_INTEL_GLK is not set
+CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
+CONFIG_ROMSTAGE_ADDR=0x2000000
+CONFIG_VERSTAGE_ADDR=0x2000000
+CONFIG_PCIEXP_ASPM=y
+CONFIG_PCIEXP_COMMON_CLOCK=y
+CONFIG_PCIEXP_CLK_PM=y
+CONFIG_TTYS0_BASE=0x3f8
+# CONFIG_SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS is not set
+# CONFIG_SOC_INTEL_COFFEELAKE is not set
+# CONFIG_SOC_INTEL_WHISKEYLAKE is not set
+# CONFIG_SOC_INTEL_COMETLAKE is not set
+# CONFIG_SOC_INTEL_CANNONLAKE_PCH_H is not set
+CONFIG_UART_PCI_ADDR=0x0
+# CONFIG_SOC_MEDIATEK_MT8173 is not set
+# CONFIG_SOC_MEDIATEK_MT8183 is not set
+# CONFIG_SOC_NVIDIA_TEGRA124 is not set
+# CONFIG_SOC_NVIDIA_TEGRA210 is not set
+# CONFIG_SOC_QUALCOMM_COMMON is not set
+# CONFIG_SOC_QC_IPQ40XX is not set
+# CONFIG_SOC_QC_IPQ806X is not set
+# CONFIG_SOC_QUALCOMM_QCS405 is not set
+# CONFIG_SOC_QUALCOMM_SDM845 is not set
+# CONFIG_SOC_ROCKCHIP_RK3288 is not set
+# CONFIG_SOC_ROCKCHIP_RK3399 is not set
+# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set
+# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set
+# CONFIG_SOC_UCB_RISCV is not set
+
+#
+# CPU
+#
+# CONFIG_CPU_ALLWINNER_A10 is not set
+CONFIG_XIP_ROM_SIZE=0x100000
+CONFIG_NUM_IPI_STARTS=2
+CONFIG_CPU_AMD_AGESA=y
+# CONFIG_ENABLE_MRC_CACHE is not set
+CONFIG_S3_DATA_POS=0xFFFF0000
+CONFIG_S3_DATA_SIZE=32768
+CONFIG_CPU_AMD_AGESA_FAMILY16_KB=y
+CONFIG_FORCE_AM1_SOCKET_SUPPORT=y
+# CONFIG_CPU_AMD_PI is not set
+# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set
+# CONFIG_SSE2 is not set
+# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set
+# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set
+# CONFIG_CPU_TI_AM335X is not set
+# CONFIG_PARALLEL_CPU_INIT is not set
+# CONFIG_PARALLEL_MP is not set
+# CONFIG_UDELAY_IO is not set
+CONFIG_UDELAY_LAPIC=y
+CONFIG_LAPIC_MONOTONIC_TIMER=y
+# CONFIG_UDELAY_TSC is not set
+# CONFIG_UDELAY_TIMER2 is not set
+CONFIG_TSC_SYNC_LFENCE=y
+# CONFIG_TSC_SYNC_MFENCE is not set
+# CONFIG_NO_FIXED_XIP_ROM_SIZE is not set
+CONFIG_LOGICAL_CPUS=y
+# CONFIG_SMM_TSEG is not set
+# CONFIG_SMM_LAPIC_REMAP_MITIGATION is not set
+# CONFIG_SERIALIZED_SMM_INITIALIZATION is not set
+CONFIG_X86_AMD_FIXED_MTRRS=y
+# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set
+# CONFIG_SOC_SETS_MSRS is not set
+CONFIG_CACHE_AS_RAM=y
+CONFIG_NO_CAR_GLOBAL_MIGRATION=y
+CONFIG_SMP=y
+# CONFIG_SUPPORT_CPU_UCODE_IN_CBFS is not set
+# CONFIG_USES_MICROCODE_HEADER_FILES is not set
+
+#
+# Northbridge
+#
+CONFIG_NORTHBRIDGE_AMD_AGESA=y
+# CONFIG_CONSOLE_VGA_MULTI is not set
+CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY16_KB=y
+# CONFIG_NORTHBRIDGE_AMD_PI is not set
+CONFIG_MAX_PIRQ_LINKS=4
+
+#
+# Southbridge
+#
+CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE=y
+CONFIG_SOUTHBRIDGE_SPECIFIC_OPTIONS=y
+CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/amd/agesa/hudson/bootblock.c"
+# CONFIG_HUDSON_XHCI_ENABLE is not set
+# CONFIG_HUDSON_IMC_ENABLE is not set
+# CONFIG_HUDSON_GEC_FWM is not set
+CONFIG_HUDSON_SATA_MODE=0
+
+#
+# NATIVE
+#
+CONFIG_ACPI_ENABLE_THERMAL_ZONE=y
+# CONFIG_AMD_SB_CIMX is not set
+# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set
+# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set
+# CONFIG_SOUTHBRIDGE_INTEL_COMMON is not set
+# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set
+# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS is not set
+# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI is not set
+# CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN is not set
+# CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ is not set
+# CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN is not set
+# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM is not set
+# CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE is not set
+
+#
+# Super I/O
+#
+# CONFIG_SUPERIO_ASPEED_AST2400 is not set
+# CONFIG_SUPERIO_ASPEED_COMMON_PRE_RAM is not set
+CONFIG_SUPERIO_ITE_COMMON_PRE_RAM=y
+CONFIG_SUPERIO_ITE_ENV_CTRL=y
+CONFIG_SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG=y
+CONFIG_SUPERIO_ITE_ENV_CTRL_8BIT_PWM=y
+CONFIG_SUPERIO_ITE_ENV_CTRL_PWM_FREQ2=y
+CONFIG_SUPERIO_ITE_IT8623E=y
+
+#
+# Embedded Controllers
+#
+# CONFIG_EC_GOOGLE_WILCO is not set
+CONFIG_EC_BASE_ACPI_DATA=0x930
+CONFIG_EC_BASE_ACPI_COMMAND=0x934
+CONFIG_EC_BASE_HOST_DATA=0x940
+CONFIG_EC_BASE_HOST_COMMAND=0x944
+CONFIG_EC_BASE_PACKET=0x950
+CONFIG_SEABIOS_PS2_TIMEOUT=0
+
+#
+# AMD Platform Initialization
+#
+# CONFIG_CPU_AMD_AGESA_BINARY_PI is not set
+CONFIG_CPU_AMD_AGESA_OPENSOURCE=y
+CONFIG_AGESA_EXTRA_TIMESTAMPS=y
+# CONFIG_CAVIUM_BDK is not set
+# CONFIG_MAINBOARD_HAS_CHROMEOS is not set
+# CONFIG_GOOGLE_SMBIOS_MAINBOARD_VERSION is not set
+# CONFIG_UEFI_2_4_BINDING is not set
+# CONFIG_UDK_2015_BINDING is not set
+# CONFIG_UDK_2017_BINDING is not set
+CONFIG_UDK_2013_VERSION=2013
+CONFIG_UDK_2015_VERSION=2015
+CONFIG_UDK_2017_VERSION=2017
+CONFIG_UDK_VERSION=2013
+# CONFIG_USE_SIEMENS_HWILIB is not set
+# CONFIG_ARCH_ARM is not set
+# CONFIG_ARCH_BOOTBLOCK_ARM is not set
+# CONFIG_ARCH_VERSTAGE_ARM is not set
+# CONFIG_ARCH_ROMSTAGE_ARM is not set
+# CONFIG_ARCH_RAMSTAGE_ARM is not set
+# CONFIG_ARCH_BOOTBLOCK_ARMV4 is not set
+# CONFIG_ARCH_VERSTAGE_ARMV4 is not set
+# CONFIG_ARCH_ROMSTAGE_ARMV4 is not set
+# CONFIG_ARCH_RAMSTAGE_ARMV4 is not set
+# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set
+# CONFIG_ARCH_VERSTAGE_ARMV7 is not set
+# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set
+# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set
+# CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set
+# CONFIG_ARCH_VERSTAGE_ARMV7_M is not set
+# CONFIG_ARCH_BOOTBLOCK_ARMV7_R is not set
+# CONFIG_ARCH_VERSTAGE_ARMV7_R is not set
+# CONFIG_ARCH_ROMSTAGE_ARMV7_R is not set
+# CONFIG_ARCH_RAMSTAGE_ARMV7_R is not set
+# CONFIG_ARM_LPAE is not set
+# CONFIG_ARCH_ARM64 is not set
+# CONFIG_ARCH_BOOTBLOCK_ARM64 is not set
+# CONFIG_ARCH_VERSTAGE_ARM64 is not set
+# CONFIG_ARCH_ROMSTAGE_ARM64 is not set
+# CONFIG_ARCH_RAMSTAGE_ARM64 is not set
+# CONFIG_ARCH_BOOTBLOCK_ARMV8_64 is not set
+# CONFIG_ARCH_VERSTAGE_ARMV8_64 is not set
+# CONFIG_ARCH_ROMSTAGE_ARMV8_64 is not set
+# CONFIG_ARCH_RAMSTAGE_ARMV8_64 is not set
+# CONFIG_ARM64_USE_ARCH_TIMER is not set
+# CONFIG_ARM64_A53_ERRATUM_843419 is not set
+# CONFIG_ARCH_MIPS is not set
+# CONFIG_ARCH_BOOTBLOCK_MIPS is not set
+# CONFIG_ARCH_VERSTAGE_MIPS is not set
+# CONFIG_ARCH_ROMSTAGE_MIPS is not set
+# CONFIG_ARCH_RAMSTAGE_MIPS is not set
+# CONFIG_ARCH_PPC64 is not set
+# CONFIG_ARCH_BOOTBLOCK_PPC64 is not set
+# CONFIG_ARCH_VERSTAGE_PPC64 is not set
+# CONFIG_ARCH_ROMSTAGE_PPC64 is not set
+# CONFIG_ARCH_RAMSTAGE_PPC64 is not set
+# CONFIG_ARCH_RISCV is not set
+# CONFIG_ARCH_RISCV_M is not set
+# CONFIG_ARCH_RISCV_S is not set
+# CONFIG_ARCH_RISCV_U is not set
+# CONFIG_ARCH_RISCV_RV64 is not set
+# CONFIG_ARCH_RISCV_RV32 is not set
+# CONFIG_ARCH_RISCV_PMP is not set
+# CONFIG_ARCH_BOOTBLOCK_RISCV is not set
+# CONFIG_ARCH_VERSTAGE_RISCV is not set
+# CONFIG_ARCH_ROMSTAGE_RISCV is not set
+# CONFIG_ARCH_RAMSTAGE_RISCV is not set
+# CONFIG_RISCV_USE_ARCH_TIMER is not set
+CONFIG_ARCH_X86=y
+CONFIG_ARCH_BOOTBLOCK_X86_32=y
+CONFIG_ARCH_VERSTAGE_X86_32=y
+CONFIG_ARCH_ROMSTAGE_X86_32=y
+CONFIG_ARCH_POSTCAR_X86_32=y
+CONFIG_ARCH_RAMSTAGE_X86_32=y
+# CONFIG_ARCH_BOOTBLOCK_X86_64 is not set
+# CONFIG_ARCH_VERSTAGE_X86_64 is not set
+# CONFIG_ARCH_ROMSTAGE_X86_64 is not set
+# CONFIG_ARCH_POSTCAR_X86_64 is not set
+# CONFIG_ARCH_RAMSTAGE_X86_64 is not set
+# CONFIG_USE_MARCH_586 is not set
+# CONFIG_AP_IN_SIPI_WAIT is not set
+# CONFIG_SIPI_VECTOR_IN_ROM is not set
+CONFIG_RAMBASE=0xe00000
+CONFIG_RAMTOP=0x1000000
+CONFIG_CBMEM_TOP_BACKUP=y
+# CONFIG_EARLY_EBDA_INIT is not set
+CONFIG_PC80_SYSTEM=y
+# CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set
+# CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set
+CONFIG_HAVE_CMOS_DEFAULT=y
+CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
+CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y
+# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set
+# CONFIG_HPET_ADDRESS_OVERRIDE is not set
+CONFIG_HPET_ADDRESS=0xfed00000
+CONFIG_ID_SECTION_OFFSET=0x80
+CONFIG_POSTCAR_STAGE=y
+# CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set
+# CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set
+CONFIG_BOOTBLOCK_SIMPLE=y
+# CONFIG_BOOTBLOCK_NORMAL is not set
+CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c"
+CONFIG_ACPI_HAVE_PCAT_8259=y
+# CONFIG_COLLECT_TIMESTAMPS_NO_TSC is not set
+CONFIG_COLLECT_TIMESTAMPS_TSC=y
+# CONFIG_PAGING_IN_CACHE_AS_RAM is not set
+# CONFIG_IDT_IN_EVERY_STAGE is not set
+CONFIG_HAVE_CF9_RESET=y
+CONFIG_HAVE_CF9_RESET_PREPARE=y
+
+#
+# Devices
+#
+CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
+CONFIG_HAVE_VBE_LINEAR_FRAMEBUFFER=y
+# CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT is not set
+# CONFIG_MAINBOARD_HAS_LIBGFXINIT is not set
+CONFIG_VGA_ROM_RUN=y
+# CONFIG_NO_GFX_INIT is not set
+# CONFIG_ALWAYS_LOAD_OPROM is not set
+CONFIG_ON_DEVICE_ROM_LOAD=y
+# CONFIG_PCI_OPTION_ROM_RUN_REALMODE is not set
+CONFIG_PCI_OPTION_ROM_RUN_YABEL=y
+CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES=y
+# CONFIG_YABEL_PCI_FAKE_WRITING_OTHER_DEVICES_CONFIG is not set
+CONFIG_YABEL_VIRTMEM_LOCATION=0x1000000
+CONFIG_YABEL_DIRECTHW=y
+
+#
+# Display
+#
+CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
+# CONFIG_FRAMEBUFFER_VESA_MODE_100 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_101 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_102 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_103 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_104 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_105 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_106 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_107 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_108 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_109 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_10A is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_10B is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_10C is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_10D is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_10E is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_10F is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_110 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_111 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_112 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_113 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_114 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_115 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_116 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_117 is not set
+CONFIG_FRAMEBUFFER_VESA_MODE_118=y
+# CONFIG_FRAMEBUFFER_VESA_MODE_119 is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_11A is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_11B is not set
+# CONFIG_FRAMEBUFFER_VESA_MODE_USER is not set
+CONFIG_FRAMEBUFFER_VESA_MODE=0x118
+CONFIG_BOOTSPLASH=y
+# CONFIG_VGA_TEXT_FRAMEBUFFER is not set
+CONFIG_VBE_LINEAR_FRAMEBUFFER=y
+CONFIG_LINEAR_FRAMEBUFFER=y
+# CONFIG_SMBUS_HAS_AUX_CHANNELS is not set
+CONFIG_PCI=y
+# CONFIG_NO_MMCONF_SUPPORT is not set
+CONFIG_MMCONF_SUPPORT=y
+# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set
+CONFIG_PCIX_PLUGIN_SUPPORT=y
+CONFIG_CARDBUS_PLUGIN_SUPPORT=y
+# CONFIG_AZALIA_PLUGIN_SUPPORT is not set
+CONFIG_PCIEXP_PLUGIN_SUPPORT=y
+# CONFIG_EARLY_PCI_BRIDGE is not set
+CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
+CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
+# CONFIG_VGA_BIOS_DGPU is not set
+# CONFIG_SOFTWARE_I2C is not set
+
+#
+# Generic Drivers
+#
+# CONFIG_DRIVERS_AS3722_RTC is not set
+# CONFIG_GIC is not set
+# CONFIG_IPMI_KCS is not set
+# CONFIG_DRIVERS_LENOVO_WACOM is not set
+# CONFIG_RT8168_GET_MAC_FROM_VPD is not set
+# CONFIG_RT8168_SET_LED_MODE is not set
+# CONFIG_SMMSTORE_IN_CBFS is not set
+CONFIG_SPI_FLASH=y
+CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
+# CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY is not set
+# CONFIG_SPI_FLASH_NO_FAST_READ is not set
+CONFIG_SPI_FLASH_ADESTO=y
+CONFIG_SPI_FLASH_AMIC=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
+# CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B is not set
+# CONFIG_SPI_FLASH_HAS_VOLATILE_GROUP is not set
+# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set
+CONFIG_DRIVERS_UART=y
+# CONFIG_DRIVERS_UART_8250IO_SKIP_INIT is not set
+# CONFIG_NO_UART_ON_SUPERIO is not set
+# CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set
+# CONFIG_UART_OVERRIDE_REFCLK is not set
+# CONFIG_DRIVERS_UART_8250MEM is not set
+# CONFIG_DRIVERS_UART_8250MEM_32 is not set
+# CONFIG_HAVE_UART_SPECIAL is not set
+# CONFIG_DRIVERS_UART_OXPCIE is not set
+# CONFIG_DRIVERS_UART_PL011 is not set
+# CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set
+CONFIG_HAVE_USBDEBUG=y
+CONFIG_HAVE_USBDEBUG_OPTIONS=y
+# CONFIG_VPD is not set
+CONFIG_DRIVERS_AMD_PI=y
+# CONFIG_SMBIOS_PROVIDED_BY_MOBO is not set
+# CONFIG_DRIVERS_I2C_MAX98373 is not set
+# CONFIG_DRIVERS_I2C_MAX98927 is not set
+# CONFIG_DRIVERS_I2C_PCA9538 is not set
+# CONFIG_DRIVERS_I2C_PCF8523 is not set
+# CONFIG_DRIVERS_I2C_RT5663 is not set
+# CONFIG_DRIVERS_I2C_RTD2132 is not set
+# CONFIG_DRIVERS_I2C_RX6110SA is not set
+# CONFIG_DRIVERS_I2C_SX9310 is not set
+# CONFIG_MAINBOARD_HAS_I2C_TPM_ATMEL is not set
+# CONFIG_MAINBOARD_HAS_I2C_TPM_CR50 is not set
+# CONFIG_MAINBOARD_HAS_I2C_TPM_GENERIC is not set
+# CONFIG_PLATFORM_USES_FSP1_0 is not set
+# CONFIG_PLATFORM_USES_FSP2_0 is not set
+# CONFIG_PLATFORM_USES_FSP2_1 is not set
+# CONFIG_INTEL_DDI is not set
+# CONFIG_INTEL_EDID is not set
+# CONFIG_INTEL_INT15 is not set
+# CONFIG_INTEL_GMA_ACPI is not set
+# CONFIG_INTEL_GMA_SSC_ALTERNATE_REF is not set
+# CONFIG_INTEL_GMA_SWSMISCI is not set
+# CONFIG_DRIVER_INTEL_I210 is not set
+# CONFIG_DRIVERS_INTEL_MIPI_CAMERA is not set
+# CONFIG_DRIVERS_INTEL_WIFI is not set
+# CONFIG_USE_SAR is not set
+# CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS is not set
+# CONFIG_DRIVER_MAXIM_MAX77686 is not set
+# CONFIG_DRIVER_PARADE_PS8625 is not set
+# CONFIG_DRIVER_PARADE_PS8640 is not set
+CONFIG_DRIVERS_MC146818=y
+CONFIG_LPC_TPM=y
+CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000
+CONFIG_MAINBOARD_HAS_LPC_TPM=y
+# CONFIG_DRIVERS_RICOH_RCE822 is not set
+# CONFIG_DRIVER_SIEMENS_NC_FPGA is not set
+# CONFIG_NC_FPGA_NOTIFY_CB_READY is not set
+# CONFIG_DRIVERS_SIL_3114 is not set
+# CONFIG_MAINBOARD_HAS_SPI_TPM_CR50 is not set
+# CONFIG_DRIVER_TI_TPS65090 is not set
+# CONFIG_DRIVERS_TI_TPS65913 is not set
+# CONFIG_DRIVERS_TI_TPS65913_RTC is not set
+# CONFIG_DRIVERS_USB_ACPI is not set
+# CONFIG_DRIVER_XPOWERS_AXP209 is not set
+# CONFIG_COMMONLIB_STORAGE is not set
+
+#
+# Security
+#
+
+#
+# Verified Boot (vboot)
+#
+
+#
+# Trusted Platform Module
+#
+CONFIG_USER_NO_TPM=y
+# CONFIG_USER_TPM1 is not set
+# CONFIG_USER_TPM2 is not set
+# CONFIG_TPM_RDRESP_NEED_DELAY is not set
+# CONFIG_ACPI_SATA_GENERATOR is not set
+# CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES is not set
+# CONFIG_ACPI_AMD_HARDWARE_SLEEP_VALUES is not set
+# CONFIG_BOOT_DEVICE_NOT_SPI_FLASH is not set
+CONFIG_BOOT_DEVICE_SPI_FLASH=y
+CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
+# CONFIG_BOOT_DEVICE_SUPPORTS_WRITES is not set
+# CONFIG_RTC is not set
+
+#
+# Console
+#
+# CONFIG_POSTCAR_CONSOLE is not set
+CONFIG_SQUELCH_EARLY_SMP=y
+CONFIG_CONSOLE_SERIAL=y
+CONFIG_CONSOLE_CBMEM=y
+CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
+
+#
+# I/O mapped, 8250-compatible
+#
+
+#
+# Serial port base address = 0x3f8
+#
+# CONFIG_CONSOLE_SERIAL_921600 is not set
+# CONFIG_CONSOLE_SERIAL_460800 is not set
+# CONFIG_CONSOLE_SERIAL_230400 is not set
+CONFIG_CONSOLE_SERIAL_115200=y
+# CONFIG_CONSOLE_SERIAL_57600 is not set
+# CONFIG_CONSOLE_SERIAL_38400 is not set
+# CONFIG_CONSOLE_SERIAL_19200 is not set
+# CONFIG_CONSOLE_SERIAL_9600 is not set
+CONFIG_TTYS0_BAUD=115200
+# CONFIG_SPKMODEM is not set
+# CONFIG_CONSOLE_NE2K is not set
+CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
+# CONFIG_CONSOLE_SPI_FLASH is not set
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
+# CONFIG_NO_POST is not set
+# CONFIG_CMOS_POST is not set
+# CONFIG_CONSOLE_POST is not set
+CONFIG_POST_DEVICE=y
+CONFIG_POST_DEVICE_NONE=y
+# CONFIG_POST_DEVICE_LPC is not set
+# CONFIG_POST_DEVICE_PCI_PCIE is not set
+CONFIG_POST_IO=y
+CONFIG_POST_IO_PORT=0x80
+# CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set
+CONFIG_HWBASE_DEBUG_CB=y
+CONFIG_HAVE_ACPI_RESUME=y
+# CONFIG_ACPI_HUGE_LOWMEM_BACKUP is not set
+CONFIG_RESUME_PATH_SAME_AS_BOOT=y
+# CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set
+# CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set
+# CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set
+CONFIG_HAVE_MONOTONIC_TIMER=y
+# CONFIG_GENERIC_UDELAY is not set
+# CONFIG_TIMER_QUEUE is not set
+CONFIG_HAVE_OPTION_TABLE=y
+# CONFIG_PIRQ_ROUTE is not set
+# CONFIG_HAVE_SMI_HANDLER is not set
+# CONFIG_PCI_IO_CFG_EXT is not set
+CONFIG_IOAPIC=y
+# CONFIG_USE_WATCHDOG_ON_BOOT is not set
+CONFIG_GFXUMA=y
+CONFIG_HAVE_ACPI_TABLES=y
+CONFIG_HAVE_MP_TABLE=y
+CONFIG_HAVE_PIRQ_TABLE=y
+# CONFIG_COMMON_FADT is not set
+# CONFIG_ACPI_NHLT is not set
+
+#
+# System tables
+#
+CONFIG_GENERATE_MP_TABLE=y
+CONFIG_GENERATE_PIRQ_TABLE=y
+CONFIG_GENERATE_SMBIOS_TABLES=y
+
+#
+# Payload
+#
+# CONFIG_PAYLOAD_NONE is not set
+# CONFIG_PAYLOAD_ELF is not set
+# CONFIG_PAYLOAD_BAYOU is not set
+# CONFIG_PAYLOAD_FILO is not set
+# CONFIG_PAYLOAD_GRUB2 is not set
+# CONFIG_PAYLOAD_LINUXBOOT is not set
+CONFIG_PAYLOAD_SEABIOS=y
+# CONFIG_PAYLOAD_UBOOT is not set
+# CONFIG_PAYLOAD_YABITS is not set
+# CONFIG_PAYLOAD_LINUX is not set
+# CONFIG_PAYLOAD_TIANOCORE is not set
+CONFIG_PAYLOAD_FILE="payloads/external/SeaBIOS/seabios/out/bios.bin.elf"
+# CONFIG_SEABIOS_STABLE is not set
+CONFIG_SEABIOS_MASTER=y
+# CONFIG_SEABIOS_REVISION is not set
+# CONFIG_SEABIOS_THREAD_OPTIONROMS is not set
+CONFIG_SEABIOS_BOOTORDER_FILE=""
+# CONFIG_SEABIOS_ADD_SERCON_PORT_FILE is not set
+CONFIG_SEABIOS_DEBUG_LEVEL=-1
+
+#
+# Using default SeaBIOS log level
+#
+CONFIG_PAYLOAD_OPTIONS=""
+# CONFIG_PXE is not set
+CONFIG_COMPRESSED_PAYLOAD_LZMA=y
+# CONFIG_COMPRESSED_PAYLOAD_LZ4 is not set
+# CONFIG_PAYLOAD_IS_FLAT_BINARY is not set
+CONFIG_COMPRESS_SECONDARY_PAYLOAD=y
+
+#
+# Secondary Payloads
+#
+CONFIG_COREINFO_SECONDARY_PAYLOAD=y
+# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set
+# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set
+CONFIG_TINT_SECONDARY_PAYLOAD=y
+
+#
+# Debugging
+#
+
+#
+# CPU Debug Settings
+#
+
+#
+# General Debug Settings
+#
+# CONFIG_GDB_STUB is not set
+# CONFIG_FATAL_ASSERTS is not set
+# CONFIG_DEBUG_CBFS is not set
+# CONFIG_HAVE_DEBUG_RAM_SETUP is not set
+# CONFIG_DEBUG_PIRQ is not set
+# CONFIG_HAVE_DEBUG_SMBUS is not set
+# CONFIG_DEBUG_MALLOC is not set
+# CONFIG_DEBUG_ACPI is not set
+# CONFIG_DEBUG_CONSOLE_INIT is not set
+# CONFIG_X86EMU_DEBUG is not set
+# CONFIG_DEBUG_SPI_FLASH is not set
+# CONFIG_TRACE is not set
+# CONFIG_DEBUG_BOOT_STATE is not set
+# CONFIG_DEBUG_ADA_CODE is not set
+# CONFIG_HAVE_EM100_SUPPORT is not set
+CONFIG_NO_EDID_FILL_FB=y
+# CONFIG_ENABLE_APIC_EXT_ID is not set
+CONFIG_WARNINGS_ARE_ERRORS=y
+# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set
+# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set
+# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set
+# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set
+# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set
+# CONFIG_REG_SCRIPT is not set
+# CONFIG_NO_XIP_EARLY_STAGES is not set
+# CONFIG_EARLY_CBMEM_LIST is not set
+CONFIG_RELOCATABLE_MODULES=y
+CONFIG_BOOTBLOCK_CUSTOM=y
+CONFIG_HAVE_BOOTBLOCK=y
+CONFIG_HAVE_ROMSTAGE=y
+CONFIG_HAVE_POSTCAR=y
+CONFIG_HAVE_RAMSTAGE=y
+
--
To view, visit https://review.coreboot.org/c/coreboot/+/33800
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ide7529762813944b4f91b2ee8b3ef327b5daffc4
Gerrit-Change-Number: 33800
Gerrit-PatchSet: 1
Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com>
Gerrit-MessageType: newchange
3 weeks, 2 days
- 5
- 33