by Benjamin Doron (Code Review)
Benjamin Doron has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35523 )
Change subject: mb/acer/aspire_vn7_572g: Adds support for an Acer laptop Adds initial, rudimentary support for Acer Aspire VN7-572G. May not boot correctly or at all. For testing purposes only.
......................................................................
mb/acer/aspire_vn7_572g: Adds support for an Acer laptop
Adds initial, rudimentary support for Acer Aspire VN7-572G. May not boot correctly or at all. For testing purposes only.
Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6
Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com>
---
A src/mainboard/acer/Kconfig
A src/mainboard/acer/Kconfig.name
A src/mainboard/acer/aspire_vn7_572g/Kconfig
A src/mainboard/acer/aspire_vn7_572g/Kconfig.name
A src/mainboard/acer/aspire_vn7_572g/Makefile.inc
A src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl
A src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl
A src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl
A src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl
A src/mainboard/acer/aspire_vn7_572g/acpi_tables.c
A src/mainboard/acer/aspire_vn7_572g/board_info.txt
A src/mainboard/acer/aspire_vn7_572g/devicetree.cb
A src/mainboard/acer/aspire_vn7_572g/dsdt.asl
A src/mainboard/acer/aspire_vn7_572g/gpio.h
A src/mainboard/acer/aspire_vn7_572g/hda_verb.c
A src/mainboard/acer/aspire_vn7_572g/mainboard.c
A src/mainboard/acer/aspire_vn7_572g/ramstage.c
A src/mainboard/acer/aspire_vn7_572g/romstage.c
18 files changed, 1,282 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35523/1
diff --git a/src/mainboard/acer/Kconfig b/src/mainboard/acer/Kconfig
new file mode 100644
index 0000000..f56a2a2
--- /dev/null
+++ b/src/mainboard/acer/Kconfig
@@ -0,0 +1,16 @@
+if VENDOR_ACER
+
+choice
+ prompt "Mainboard model"
+
+source "src/mainboard/acer/*/Kconfig.name"
+
+endchoice
+
+source "src/mainboard/acer/*/Kconfig"
+
+config MAINBOARD_VENDOR
+ string "Mainboard Vendor"
+ default "Acer"
+
+endif # VENDOR_ACER
diff --git a/src/mainboard/acer/Kconfig.name b/src/mainboard/acer/Kconfig.name
new file mode 100644
index 0000000..bb177f9
--- /dev/null
+++ b/src/mainboard/acer/Kconfig.name
@@ -0,0 +1,2 @@
+config VENDOR_ACER
+ bool "Acer"
diff --git a/src/mainboard/acer/aspire_vn7_572g/Kconfig b/src/mainboard/acer/aspire_vn7_572g/Kconfig
new file mode 100644
index 0000000..4b3c127
--- /dev/null
+++ b/src/mainboard/acer/aspire_vn7_572g/Kconfig
@@ -0,0 +1,68 @@
+if BOARD_ACER_VN7_572G
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select SYSTEM_TYPE_LAPTOP
+ select BOARD_ROMSIZE_KB_8192
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+ select SOC_INTEL_SKYLAKE
+ select MAINBOARD_USES_FSP2_0
+ select SPD_READ_BY_WORD
+ select MAINBOARD_HAS_LPC_TPM
+ select NO_POST # This platform has no way to see POST codes so disable them by default.
+
+config IRQ_SLOT_COUNT
+ int
+ default 18
+
+config MAINBOARD_VENDOR
+ string
+ default "Acer"
+
+config MAINBOARD_FAMILY
+ string
+ default "Aspire V Nitro"
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "Aspire VN7-572G"
+
+config MAINBOARD_DIR
+ string
+ default "acer/aspire_vn7_572g"
+
+config DEVICETREE
+ string
+ default "devicetree.cb"
+
+config MAX_CPUS
+ int
+ default 4
+
+config VGA_BIOS_ID
+ string
+ default "8086,1916"
+
+config DIMM_MAX
+ int
+ default 2
+
+config DIMM_SPD_SIZE
+ int
+ default 512
+
+config CPU_MICROCODE_CBFS_LEN
+ hex
+ default 0x18000
+
+config CPU_MICROCODE_CBFS_LOC
+ hex
+ default 0xFFE115A0
+
+config CBFS_SIZE
+ hex
+ default 0x5c0000
+
+endif
diff --git a/src/mainboard/acer/aspire_vn7_572g/Kconfig.name b/src/mainboard/acer/aspire_vn7_572g/Kconfig.name
new file mode 100644
index 0000000..b881680
--- /dev/null
+++ b/src/mainboard/acer/aspire_vn7_572g/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_ACER_VN7_572G
+ bool "Aspire VN7-572G"
diff --git a/src/mainboard/acer/aspire_vn7_572g/Makefile.inc b/src/mainboard/acer/aspire_vn7_572g/Makefile.inc
new file mode 100644
index 0000000..35f0f6c
--- /dev/null
+++ b/src/mainboard/acer/aspire_vn7_572g/Makefile.inc
@@ -0,0 +1,17 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2015 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+ramstage-y += ramstage.c
+ramstage-y += hda_verb.c
diff --git a/src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl b/src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl
new file mode 100644
index 0000000..2eed489
--- /dev/null
+++ b/src/mainboard/acer/aspire_vn7_572g/acpi/ec.asl
@@ -0,0 +1,328 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Name (EMBA, 0xFE800000)
+
+Device (EC0)
+{
+ Name (_HID, EisaId ("PNP0C09")) /* Embedded Controller Device */ // _HID: Hardware ID
+
+ Name (_GPE, 0x50) // _GPE: General Purpose Events
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (0x0F)
+ }
+
+ Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
+ IO (Decode16, 0x62, 0x62, 0, 1) // Range Minimum, Range Maximum, Alignment, Length
+ IO (Decode16, 0x66, 0x66, 0, 1) // Range Minimum, Range Maximum, Alignment, Length
+ })
+ OperationRegion (ECO1, SystemIO, 0x62, One)
+ Field (ECO1, ByteAcc, Lock, Preserve)
+ {
+ PX62, 8
+ }
+
+ OperationRegion (ECO2, SystemIO, 0x66, One)
+ Field (ECO2, ByteAcc, Lock, Preserve)
+ {
+ PX66, 8
+ }
+
+ OperationRegion (ECMB, SystemMemory, EMBA, 0x0200)
+ OperationRegion (RAM, EmbeddedControl, Zero, 0xFF)
+ Field (RAM, ByteAcc, Lock, Preserve)
+ {
+ CMDB, 8,
+ Offset (0x06),
+ CMD2, 8,
+ CMD1, 8,
+ CMD0, 8,
+ Offset (0x0A),
+ , 1, /* Reserved */
+ , 1, /* Reserved */
+ Offset (0x10),
+ EQEN, 1,
+ , 1, /* Reserved */
+ Offset (0x4E),
+ ISEN, 1, /* Sense? (0=Not Exist, 1=Exist) */
+ Offset (0x51),
+ , 3, /* Reserved */
+ TPEN, 1,
+ Offset (0x52),
+ WLEX, 1, /* Wireless LAN (0=Not Exist, 1=Exist) */
+ BTEX, 1, /* Bluetooth? (0=Not Exist, 1=Exist) */
+ EX3G, 1, /* 3G (0=Not Exist, 1=Exist) */
+ , 3, /* Reserved */
+ RFEX, 1,
+ Offset (0x57),
+ , 7, /* Reserved */
+ AHKB, 1,
+ AHKE, 8,
+ Offset (0x5C),
+ Offset (0x5D),
+ Offset (0x70),
+ , 1, /* Reserved */
+ KLID, 1, /* LID? */
+ , 3, /* Reserved */
+ KACS, 1, /* AC power? */
+ Offset (0x71),
+ WLEN, 1, /* Wireless LAN (0=Not Enabled, 1=Enabled) */
+ BTEN, 1, /* Bluetooth (0=Not Enabled, 1=Enabled) */
+ , 3, /* Reserved */
+ ISS3, 1,
+ ISS4, 1,
+ ISS5, 1,
+ Offset (0x74),
+ , 2, /* Reserved */
+ , 1, /* Reserved */
+ TPEX, 1,
+ Offset (0x75),
+ BLST, 1,
+ LMIB, 1,
+ Offset (0x76),
+ ECSS, 4,
+ EOSS, 4
+ }
+
+ Method (_REG, 2, NotSerialized) // _REG: Region Availability
+ {
+ /* Initialize AC power state */
+ Store (KACS, \PWRS)
+
+ /* Initialize LID switch state */
+ Store (KLID, \LIDS)
+ }
+
+ /* KEY_BRIGHTNESSUP */
+ Method (_Q1C, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ Notify (^^^GFX0.DD1F, 0x86) // Device-Specific
+ }
+
+ /* KEY_BRIGHTNESSDOWN */
+ Method (_Q1D, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ Notify (^^^GFX0.DD1F, 0x87) // Device-Specific
+ }
+
+ /* Battery Information Event */
+ Method (_Q40, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ Notify (BAT0, 0x81) // Information Change
+ }
+
+ /* AC event */
+ Method (_Q50, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ Notify (ADP1, 0x80) // Status Change
+ }
+
+ /* Lid event */
+ Method (_Q52, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ Notify (LID0, 0x80) // Status Change
+ }
+
+ /* Battery Information Event */
+ Method (_Q41, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ Notify (BAT0, 0x81) // Information Change
+ }
+
+ /* Battery Status Event */
+ Method (_Q48, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF
+ {
+ Notify (BAT0, 0x80) // Status Change
+ }
+
+ Method (ECWK, 1, NotSerialized)
+ {
+ EQEN = One
+ Notify (BAT0, 0x81) // Information Change
+ If (((Arg0 == 0x03) || (Arg0 == 0x04)))
+ {
+ Notify (SLPB, 0x02) // Device Wake
+ }
+ }
+
+ Name (B0ST, Zero)
+ Field (ECMB, ByteAcc, Lock, Preserve)
+ {
+ Offset (0x08),
+ MB0S, 8
+ }
+
+ OperationRegion (MBB0, SystemMemory, (EMBA + 0x80), 0xFF)
+ Field (MBB0, ByteAcc, Lock, Preserve)
+ {
+ MBRC, 16,
+ MBFC, 16,
+ MBPE, 16,
+ MBAC, 16,
+ MBVO, 16,
+ , 15,
+ MBCM, 1,
+ MBCU, 16,
+ MBTV, 16
+ }
+
+ Method (GBIF, 3, NotSerialized)
+ {
+ If (Arg2)
+ {
+ Arg1 [One] = 0xFFFFFFFF
+ Arg1 [0x02] = 0xFFFFFFFF
+ Arg1 [0x04] = 0xFFFFFFFF
+ Arg1 [0x05] = Zero
+ Arg1 [0x06] = Zero
+ }
+
+ Return (Arg1)
+ }
+
+ Method (GBST, 4, NotSerialized)
+ {
+ Local0 = Zero
+
+ If ((Arg1 & One))
+ {
+ Local1 = MBAC /* \_SB_.PCI0.LPCB.EC0_.MBAC */
+ Local2 = MBRC /* \_SB_.PCI0.LPCB.EC0_.MBRC */
+ If (ACST)
+ {
+ If ((Arg1 & 0x20))
+ {
+ Local2 = MBFC /* \_SB_.PCI0.LPCB.EC0_.MBFC */
+ }
+ }
+
+ Local3 = MBVO /* \_SB_.PCI0.LPCB.EC0_.MBVO */
+ If ((Local1 >= 0x8000))
+ {
+ If ((Local0 & One))
+ {
+ Local1 = (0x00010000 - Local1)
+ }
+ Else
+ {
+ Local1 = Zero
+ }
+ }
+
+ If (Arg2)
+ {
+ Local1 *= Local3
+ Divide (Local1, 0x03E8, Local1)
+ }
+ }
+ Else
+ {
+ Local0 = Zero
+ Local1 = 0xFFFFFFFF
+ Local2 = 0xFFFFFFFF
+ Local3 = 0xFFFFFFFF
+ }
+
+ Arg3 [Zero] = Local0
+ Arg3 [One] = Local1
+ Arg3 [0x02] = Local2
+ Arg3 [0x03] = Local3
+ Return (Arg3)
+ }
+
+ Name (ACST, One)
+ Device (ADP1)
+ {
+ Name (_HID, "ACPI0003") /* Power Source Device */ // _HID: Hardware ID
+ Name (_PCL, Package () { \_SB }) // _PCL: Power Consumer List
+ Method (_PSR) // _PSR: Power Source
+ {
+ Return (\PWRS)
+ }
+ Method (_STA) // _STA: Status
+ {
+ Return (0x0F)
+ }
+ }
+
+ Device (BAT0)
+ {
+ Name (_HID, EisaId ("PNP0C0A")) /* Control Method Battery */ // _HID: Hardware ID
+ Name (_UID, Zero) // _UID: Unique ID
+ Method (_PCL, 0, NotSerialized) // _PCL: Power Consumer List
+ {
+ Return (_SB) /* \_SB_ */
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ If (B0ST)
+ {
+ Return (0x1F)
+ }
+ Else
+ {
+ Return (0x0F)
+ }
+ }
+
+ Name (B0IP, Package (0x0D)
+ {
+ 0x00000001, /* 0x00: Power Unit: mAH */
+ 0xFFFFFFFF, /* 0x01: Design Capacity */
+ 0xFFFFFFFF, /* 0x02: Last Full Charge Capacity */
+ 0x00000001, /* 0x03: Battery Technology: Rechargeable */
+ 0xFFFFFFFF, /* 0x04: Design Voltage */
+ 0x00000000, /* 0x05: Design Capacity of Warning */
+ 0x00000000, /* 0x06: Design Capacity of Low */
+ 0x00000001, /* 0x07: Capacity Granularity 1 */
+ 0x00000001, /* 0x08: Capacity Granularity 2 */
+ "", /* 0x09: Model Number */
+ "100", /* 0x0a: Serial Number */
+ "Lion", /* 0x0b: Battery Type */
+ 0x00000000 /* 0x0c: OEM Information */
+ })
+
+ Method (_BIF, 0, NotSerialized) // _BIF: Battery Information
+ {
+ Local6 = B0ST /* \_SB_.PCI0.LPCB.EC0_.B0ST */
+ While ((Local6))
+ {
+ Local1 = MB0S /* \_SB_.PCI0.LPCB.EC0_.MB0S */
+ If ((Local1 & 0x08))
+ {
+ Local6 = Zero
+ }
+ }
+
+ Return (GBIF (Zero, B0IP, Local6))
+ }
+
+ Name (B0SP, Package (0x04)
+ {
+ 0x00000000, /* 0x00: Battery State */
+ 0xFFFFFFFF, /* 0x01: Battery Present Rate */
+ 0xFFFFFFFF, /* 0x02: Battery Remaining Capacity */
+ 0xFFFFFFFF /* 0x03: Battery Present Voltage */
+ })
+
+ Method (_BST, 0, NotSerialized) // _BST: Battery Status
+ {
+ Local0 = (DerefOf (B0IP [Zero]) ^ One)
+ Return (GBST (Zero, MB0S, Local0, B0SP))
+ }
+ }
+}
diff --git a/src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl b/src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl
new file mode 100644
index 0000000..e145a2b
--- /dev/null
+++ b/src/mainboard/acer/aspire_vn7_572g/acpi/graphics.asl
@@ -0,0 +1,68 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+OperationRegion (SANV, SystemMemory, 0x7CE5FD98, Zero)
+Field (SANV, AnyAcc, Lock, Preserve)
+{
+ BRTL, 8
+}
+
+Scope (\_SB.PCI0)
+{
+ Device (GFX0)
+ {
+ Name (_ADR, 0x00020000) // _ADR: Address
+
+ Device (DD1F)
+ {
+ Method (_ADR, 0, Serialized) // _ADR: Address
+ {
+ Return (0x1F)
+ }
+
+ Method (_BCL, 0, NotSerialized) // _BCL: Brightness Control Levels
+ {
+ Return (Package (0x0C)
+ {
+ 0x50,
+ 0x32,
+ 0x0A,
+ 0x14,
+ 0x1E,
+ 0x28,
+ 0x32,
+ 0x3C,
+ 0x46,
+ 0x50,
+ 0x5A,
+ 0x64
+ })
+ }
+
+ Method (_BCM, 1, NotSerialized) // _BCM: Brightness Control Method
+ {
+ If (((Arg0 >= Zero) && (Arg0 <= 0x64)))
+ {
+ BRTL = Arg0
+ }
+ }
+
+ Method (_BQC, 0, NotSerialized) // _BQC: Brightness Query Current
+ {
+ Return (BRTL) /* \BRTL */
+ }
+ }
+ }
+}
diff --git a/src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl b/src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl
new file mode 100644
index 0000000..90e75f2
--- /dev/null
+++ b/src/mainboard/acer/aspire_vn7_572g/acpi/mainboard.asl
@@ -0,0 +1,54 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Scope (\_SB)
+{
+ Device (LID0) /* Lid Device */
+ {
+ Name (_HID, EisaId ("PNP0C0D"))
+
+ Method (_STA) // _STA: Status
+ {
+ Return (0xF)
+ }
+
+ Method (_LID) // _LID: Lid Status
+ {
+ Return (\LIDS)
+ }
+ }
+
+ Device (PWRB)
+ {
+ Name (_HID, EisaId ("PNP0C0C"))
+
+ Method (_STA)
+ {
+ Return (0xF)
+ }
+
+ Name (_PRW, Package () { 27, 4 })
+ }
+
+ Device (SLPB) /* Sleep Button Device */ // _HID: Hardware ID
+ {
+ Name (_HID, EisaId ("PNP0C0E"))
+
+ Method (_STA) // _STA: Status
+ {
+ Return (0xF)
+ }
+ }
+}
diff --git a/src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl b/src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl
new file mode 100644
index 0000000..92c272e
--- /dev/null
+++ b/src/mainboard/acer/aspire_vn7_572g/acpi/superio.asl
@@ -0,0 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <drivers/pc80/pc/ps2_controller.asl>
diff --git a/src/mainboard/acer/aspire_vn7_572g/acpi_tables.c b/src/mainboard/acer/aspire_vn7_572g/acpi_tables.c
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/acer/aspire_vn7_572g/acpi_tables.c
diff --git a/src/mainboard/acer/aspire_vn7_572g/board_info.txt b/src/mainboard/acer/aspire_vn7_572g/board_info.txt
new file mode 100644
index 0000000..f16707e
--- /dev/null
+++ b/src/mainboard/acer/aspire_vn7_572g/board_info.txt
@@ -0,0 +1,8 @@
+Vendor name: Acer
+Board name: Aspire VN7-572G
+Category: laptop
+ROM package: SOIC8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
+Release year: 2015
diff --git a/src/mainboard/acer/aspire_vn7_572g/devicetree.cb b/src/mainboard/acer/aspire_vn7_572g/devicetree.cb
new file mode 100644
index 0000000..f38b0b8
--- /dev/null
+++ b/src/mainboard/acer/aspire_vn7_572g/devicetree.cb
@@ -0,0 +1,218 @@
+chip soc/intel/skylake
+
+ # Disable deep Sx states
+ register "deep_s3_enable_ac" = "0"
+ register "deep_s3_enable_dc" = "0"
+ register "deep_s5_enable_ac" = "0"
+ register "deep_s5_enable_dc" = "0"
+ register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
+
+ register "eist_enable" = "1"
+
+ # Set the Thermal Control Circuit (TCC) activaction value to 95C
+ # even though FSP integration guide says to set it to 100C for SKL-U
+ # (offset at 0), because when the TCC activates at 100C, the CPU
+ # will have already shut itself down from overheating protection.
+ register "tcc_offset" = "5" # TCC of 95C
+
+ # GPE configuration
+ # Note that GPE events called out in ASL code rely on this
+ # route. i.e. If this route changes then the affected GPE
+ # offset bits also need to be changed.
+ register "gpe0_dw0" = "GPP_C"
+ register "gpe0_dw1" = "GPP_D"
+ register "gpe0_dw2" = "GPP_E"
+
+ # EC host command ranges are in 0x60-0x66
+ register "gen1_dec" = "0x00000061"
+
+ # Enable "Intel Speed Shift Technology"
+ register "speed_shift_enable" = "1"
+
+ # Disable DPTF
+ register "dptf_enable" = "0"
+
+ # FSP Configuration
+ register "ProbelessTrace" = "0"
+ register "EnableLan" = "0"
+ register "EnableSata" = "1"
+ register "SataSalpSupport" = "1"
+ register "SataMode" = "0"
+ register "SataPortsEnable[0]" = "1"
+ register "SataPortsEnable[1]" = "1"
+ register "SataPortsEnable[2]" = "1"
+ register "SataPortsDevSlp[0]" = "0"
+ register "SataPortsDevSlp[1]" = "0"
+ register "SataPortsDevSlp[2]" = "0"
+ register "EnableAzalia" = "1"
+ register "DspEnable" = "1"
+ register "IoBufferOwnership" = "0"
+ register "EnableTraceHub" = "0"
+ register "SsicPortEnable" = "0"
+ register "SmbusEnable" = "1"
+ register "Cio2Enable" = "0"
+ register "ScsEmmcEnabled" = "0"
+ register "ScsEmmcHs400Enabled" = "0"
+ register "ScsSdCardEnabled" = "0"
+ register "PttSwitch" = "0"
+ register "SkipExtGfxScan" = "0"
+ register "Device4Enable" = "0"
+ register "HeciEnabled" = "1"
+ register "SaGv" = "0"
+ register "PmConfigSlpS3MinAssert" = "2" # 50ms
+ register "PmConfigSlpS4MinAssert" = "1" # 1s
+ register "PmConfigSlpSusMinAssert" = "3" # 500ms
+ register "PmConfigSlpAMinAssert" = "3" # 2s
+ register "PmTimerDisabled" = "0"
+
+ # EC/KBC requires continuous mode
+ register "serirq_mode" = "SERIRQ_CONTINUOUS"
+
+ register "pirqa_routing" = "PCH_IRQ11"
+ register "pirqb_routing" = "PCH_IRQ10"
+ register "pirqc_routing" = "PCH_IRQ11"
+ register "pirqd_routing" = "PCH_IRQ11"
+ register "pirqe_routing" = "PCH_IRQ11"
+ register "pirqf_routing" = "PCH_IRQ11"
+ register "pirqg_routing" = "PCH_IRQ11"
+ register "pirqh_routing" = "PCH_IRQ11"
+
+ # VR Settings Configuration for 4 Domains
+ #+----------------+-----------+-----------+-------------+----------+
+ #| Domain/Setting | SA | IA | GT Unsliced | GT |
+ #+----------------+-----------+-----------+-------------+----------+
+ #| Psi1Threshold | 20A | 20A | 20A | 20A |
+ #| Psi2Threshold | 4A | 5A | 5A | 5A |
+ #| Psi3Threshold | 1A | 1A | 1A | 1A |
+ #| Psi3Enable | 1 | 1 | 1 | 1 |
+ #| Psi4Enable | 1 | 1 | 1 | 1 |
+ #| ImonSlope | 0 | 0 | 0 | 0 |
+ #| ImonOffset | 0 | 0 | 0 | 0 |
+ #| IccMax | 7A | 34A | 35A | 35A |
+ #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
+ #+----------------+-----------+-----------+-------------+----------+
+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(4),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(7),
+ .voltage_limit = 1520,
+ }"
+
+ register "domain_vr_config[VR_IA_CORE]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(34),
+ .voltage_limit = 1520,
+ }"
+
+ register "domain_vr_config[VR_GT_UNSLICED]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(35),
+ .voltage_limit = 1520,
+ }"
+
+ register "domain_vr_config[VR_GT_SLICED]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(35),
+ .voltage_limit = 1520,
+ }"
+
+ # Enable Root Ports 1, 9 and 10
+ register "PcieRpEnable[2]" = "1"
+ register "PcieRpLtrEnable[2]" = "1"
+ register "PcieRpEnable[8]" = "1"
+ register "PcieRpLtrEnable[8]" = "1"
+ register "PcieRpEnable[9]" = "1"
+ register "PcieRpLtrEnable[9]" = "1"
+
+# register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port
+ register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-A Port (right)
+ register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-A Port (right)
+ register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" # Type-A Port (left)
+ register "usb2_ports[4]" = "USB2_PORT_FLEX(OC2)" # Bluetooth
+ register "usb2_ports[6]" = "USB2_PORT_FLEX(OC2)" # Webcam
+ register "usb2_ports[7]" = "USB2_PORT_FLEX(OC2)" # SD
+
+ # OC0 should be for Type-C but it seems to not have been wired, according to
+ # the available schematics, even though it is labeled as USB_OC_TYPEC.
+# register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (right)
+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (right)
+
+ # PL2 override 25W
+ register "tdp_pl2_override" = "25"
+
+ # Send an extra VR mailbox command for the PS4 exit issue
+ register "SendVrMbxCmd" = "2"
+
+ # Lock Down
+ register "common_soc_config" = "{
+ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+ }"
+
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+ device domain 0 on
+ device pci 00.0 on end # Host Bridge
+ device pci 02.0 on end # Integrated Graphics Device
+ device pci 14.0 on end # USB xHCI
+ device pci 14.1 on end # USB xDCI (OTG)
+ device pci 14.2 on end # Thermal Subsystem
+ device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT Redirection
+ device pci 16.4 off end # Management Engine Interface 3
+ device pci 17.0 on end # SATA
+ device pci 1c.0 on end # PCI Express Port 1
+ device pci 1c.1 off end # PCI Express Port 2
+ device pci 1c.2 off end # PCI Express Port 3
+ device pci 1c.3 off end # PCI Express Port 4
+ device pci 1c.4 off end # PCI Express Port 5
+ device pci 1c.5 off end # PCI Express Port 6
+ device pci 1c.6 off end # PCI Express Port 7
+ device pci 1c.7 off end # PCI Express Port 8
+ device pci 1d.0 on end # PCI Express Port 9
+ device pci 1d.1 on end # PCI Express Port 10
+ device pci 1d.2 off end # PCI Express Port 11
+ device pci 1d.3 off end # PCI Express Port 12
+ device pci 1f.0 on
+ chip drivers/pc80/tpm
+ device pnp 0c31.0 on end
+ end
+ end # LPC Interface
+ device pci 1f.1 off end # P2SB
+ device pci 1f.2 on end # Power Management Controller
+ device pci 1f.3 on end # Intel HDA
+ device pci 1f.4 on end # SMBus
+ device pci 1f.5 on end # PCH SPI
+ device pci 1f.6 off end # GbE
+ end
+end
diff --git a/src/mainboard/acer/aspire_vn7_572g/dsdt.asl b/src/mainboard/acer/aspire_vn7_572g/dsdt.asl
new file mode 100644
index 0000000..c9bcb7d
--- /dev/null
+++ b/src/mainboard/acer/aspire_vn7_572g/dsdt.asl
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2016 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, // DSDT revision: ACPI v2.0 and up
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20141018 // OEM revision
+)
+{
+ // Some generic macros
+ #include <soc/intel/skylake/acpi/platform.asl>
+
+ // global NVS and variables
+ #include <soc/intel/skylake/acpi/globalnvs.asl>
+
+ // CPU
+ #include <cpu/intel/common/acpi/cpu.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <soc/intel/skylake/acpi/systemagent.asl>
+ #include <soc/intel/skylake/acpi/pch.asl>
+ }
+ }
+
+ // Chipset specific sleep states
+ #include <soc/intel/skylake/acpi/sleepstates.asl>
+
+ // Mainboard specific
+ #include "acpi/mainboard.asl"
+
+ // Graphics display
+ #include "acpi/graphics.asl"
+}
diff --git a/src/mainboard/acer/aspire_vn7_572g/gpio.h b/src/mainboard/acer/aspire_vn7_572g/gpio.h
new file mode 100644
index 0000000..4d98da1
--- /dev/null
+++ b/src/mainboard/acer/aspire_vn7_572g/gpio.h
@@ -0,0 +1,201 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+#ifndef __ACPI__
+
+/* Pad configuration in ramstage. */
+static const struct pad_config gpio_table[] = {
+_PAD_CFG_STRUCT(GPP_A0, 0x44000703, 0x0), /* RCIN# */
+_PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x3c00), /* LAD0 */
+_PAD_CFG_STRUCT(GPP_A2, 0x44000702, 0x3c00), /* LAD1 */
+_PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x3c00), /* LAD2 */
+_PAD_CFG_STRUCT(GPP_A4, 0x44000702, 0x3c00), /* LAD3 */
+_PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x0), /* LFRAME# */
+_PAD_CFG_STRUCT(GPP_A6, 0x44000702, 0x0), /* SERIRQ */
+_PAD_CFG_STRUCT(GPP_A7, 0x44000702, 0x0), /* PIRQA# */
+_PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x0), /* CLKRUN# */
+_PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x1000), /* CLKOUT_LPC0 */
+_PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x1000), /* CLKOUT_LPC1 */
+_PAD_CFG_STRUCT(GPP_A11, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_A12, 0x44000100, 0x0), /* GPIO */
+_PAD_CFG_STRUCT(GPP_A13, 0x44000700, 0x0), /* SUSWARN#/SUSPWRDNACK */
+_PAD_CFG_STRUCT(GPP_A14, 0x44000700, 0x0), /* SUS_STAT# */
+_PAD_CFG_STRUCT(GPP_A15, 0x44000700, 0x1000), /* SUS_ACK# */
+_PAD_CFG_STRUCT(GPP_A16, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_A17, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_A18, 0x44000102, 0x0), /* GPIO */
+_PAD_CFG_STRUCT(GPP_A19, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_A20, 0x44000100, 0x0), /* GPIO */
+_PAD_CFG_STRUCT(GPP_A21, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_A22, 0x44000201, 0x0), /* GPIO */
+_PAD_CFG_STRUCT(GPP_A23, 0x44000201, 0x1000), /* GPIO */
+
+_PAD_CFG_STRUCT(GPP_B0, 0x44000700, 0x0), /* CORE_VID0 */
+_PAD_CFG_STRUCT(GPP_B1, 0x44000700, 0x0), /* CORE_VID1 */
+_PAD_CFG_STRUCT(GPP_B2, 0x44000100, 0x0), /* GPIO */
+_PAD_CFG_STRUCT(GPP_B3, 0x80100102, 0x0), /* GPIO */
+_PAD_CFG_STRUCT(GPP_B4, 0x44000200, 0x0), /* GPIO */
+_PAD_CFG_STRUCT(GPP_B5, 0x44000702, 0x0), /* SRCCLKREQ0# */
+_PAD_CFG_STRUCT(GPP_B6, 0x44000702, 0x0), /* SRCCLKREQ1# */
+_PAD_CFG_STRUCT(GPP_B7, 0x44000700, 0x0), /* SRCCLKREQ2# */
+_PAD_CFG_STRUCT(GPP_B8, 0x44000702, 0x0), /* SRCCLKREQ3# */
+_PAD_CFG_STRUCT(GPP_B9, 0x44000702, 0x0), /* SRCCLKREQ4# */
+_PAD_CFG_STRUCT(GPP_B10, 0x44000702, 0x0), /* SRCCLKREQ5# */
+_PAD_CFG_STRUCT(GPP_B11, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_B12, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x0), /* PLTRST# */
+_PAD_CFG_STRUCT(GPP_B14, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_B15, 0x44000200, 0x0), /* GPIO */
+_PAD_CFG_STRUCT(GPP_B16, 0x44000200, 0x0), /* GPIO */
+_PAD_CFG_STRUCT(GPP_B17, 0x42880100, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_B18, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_B19, 0x44000100, 0x0), /* GPIO */
+_PAD_CFG_STRUCT(GPP_B20, 0x44000102, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_B21, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_B22, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_B23, 0x44000201, 0x1000), /* GPIO */
+
+_PAD_CFG_STRUCT(GPP_C0, 0x44000702, 0x0), /* SMBCLK */
+_PAD_CFG_STRUCT(GPP_C1, 0x44000702, 0x1000), /* SMBDATA */
+_PAD_CFG_STRUCT(GPP_C2, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_C3, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_C4, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_C5, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_C6, 0x44000702, 0x0), /* SML1CLK */
+_PAD_CFG_STRUCT(GPP_C7, 0x44000702, 0x1000), /* SML1DATA */
+_PAD_CFG_STRUCT(GPP_C8, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_C9, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_C10, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_C11, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_C12, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_C13, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_C14, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_C15, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_C16, 0x44000702, 0x0), /* I2C0_SDA */
+_PAD_CFG_STRUCT(GPP_C17, 0x44000702, 0x0), /* I2C0_SCL */
+_PAD_CFG_STRUCT(GPP_C18, 0x44000702, 0x0), /* I2C1_SDA */
+_PAD_CFG_STRUCT(GPP_C19, 0x44000702, 0x0), /* I2C1_SCL */
+_PAD_CFG_STRUCT(GPP_C20, 0x44000702, 0x0), /* UART2_RXD */
+_PAD_CFG_STRUCT(GPP_C21, 0x44000700, 0x0), /* UART2_TXD */
+_PAD_CFG_STRUCT(GPP_C22, 0x44000700, 0x0), /* UART2_RTS# */
+_PAD_CFG_STRUCT(GPP_C23, 0x44000702, 0x0), /* UART2_CTS# */
+
+_PAD_CFG_STRUCT(GPP_D0, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_D1, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_D2, 0x44000700, 0x0), /* SPI1_MISO */
+_PAD_CFG_STRUCT(GPP_D3, 0x44000700, 0x0), /* SPI1_MOSI */
+_PAD_CFG_STRUCT(GPP_D4, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_D5, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_D6, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_D7, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_D8, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_D9, 0x40000102, 0x0), /* GPIO */
+_PAD_CFG_STRUCT(GPP_D10, 0x40000102, 0x0), /* GPIO */
+_PAD_CFG_STRUCT(GPP_D11, 0x40000102, 0x0), /* GPIO */
+_PAD_CFG_STRUCT(GPP_D12, 0x40000102, 0x0), /* GPIO */
+_PAD_CFG_STRUCT(GPP_D13, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_D14, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_D15, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_D16, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_D17, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_D18, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_D19, 0x44000700, 0x0), /* DMIC_CLK0 */
+_PAD_CFG_STRUCT(GPP_D20, 0x44000700, 0x0), /* DMIC_DATA0 */
+_PAD_CFG_STRUCT(GPP_D21, 0x44000700, 0x0), /* SPI1_IO2 */
+_PAD_CFG_STRUCT(GPP_D22, 0x44000700, 0x0), /* SPI1_IO3 */
+_PAD_CFG_STRUCT(GPP_D23, 0x44000201, 0x1000), /* GPIO */
+
+_PAD_CFG_STRUCT(GPP_E0, 0x44000700, 0x0), /* SATAXPCIE0 */
+_PAD_CFG_STRUCT(GPP_E1, 0x44000700, 0x0), /* SATAXPCIE1 */
+_PAD_CFG_STRUCT(GPP_E2, 0x44000702, 0x0), /* SATAXPCIE2 */
+_PAD_CFG_STRUCT(GPP_E3, 0x44000201, 0x0), /* GPIO */
+_PAD_CFG_STRUCT(GPP_E4, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_E5, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_E6, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_E7, 0x40900100, 0x0), /* GPIO */
+_PAD_CFG_STRUCT(GPP_E8, 0xffffffff, 0xffffff00),/* RESERVED */
+_PAD_CFG_STRUCT(GPP_E9, 0x44000702, 0x0), /* USB2_OC0# */
+_PAD_CFG_STRUCT(GPP_E10, 0x44000702, 0x0), /* USB2_OC1# */
+_PAD_CFG_STRUCT(GPP_E11, 0x44000702, 0x0), /* USB2_OC2# */
+_PAD_CFG_STRUCT(GPP_E12, 0x44000702, 0x0), /* USB2_OC3# */
+_PAD_CFG_STRUCT(GPP_E13, 0x44000700, 0x0), /* DDPB_HPD0 */
+_PAD_CFG_STRUCT(GPP_E14, 0x44000700, 0x0), /* DDPC_HPD1 */
+_PAD_CFG_STRUCT(GPP_E15, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_E16, 0x80880102, 0x0), /* GPIO */
+_PAD_CFG_STRUCT(GPP_E17, 0x44000702, 0x0), /* EDP_HPD */
+_PAD_CFG_STRUCT(GPP_E18, 0x44000702, 0x0), /* DDPB_CTRLCLK */
+_PAD_CFG_STRUCT(GPP_E19, 0x44000702, 0x1000), /* DDPB_CTRLDATA */
+_PAD_CFG_STRUCT(GPP_E20, 0x44000700, 0x0), /* DDPC_CTRLCLK */
+_PAD_CFG_STRUCT(GPP_E21, 0x44000702, 0x1000), /* DDPC_CTRLDATA */
+_PAD_CFG_STRUCT(GPP_E22, 0x40100000, 0x0), /* GPIO */
+_PAD_CFG_STRUCT(GPP_E23, 0x44000201, 0x1000), /* GPIO */
+
+_PAD_CFG_STRUCT(GPD0, 0x4000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPD1, 0x4000702, 0x0), /* ACPRESENT */
+_PAD_CFG_STRUCT(GPD2, 0x4000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPD3, 0x4000702, 0x3000), /* PWRBTN# */
+_PAD_CFG_STRUCT(GPD4, 0x4000700, 0x0), /* SLP_S3# */
+_PAD_CFG_STRUCT(GPD5, 0x4000700, 0x0), /* SLP_S4# */
+_PAD_CFG_STRUCT(GPD6, 0x4000601, 0x1000), /* SLP_A# */
+_PAD_CFG_STRUCT(GPD7, 0x4000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPD8, 0x4000700, 0x0), /* SUSCLK */
+_PAD_CFG_STRUCT(GPD9, 0x4000601, 0x1000), /* SLP_WLAN# */
+_PAD_CFG_STRUCT(GPD10, 0x4000601, 0x1000), /* SLP_S5# */
+_PAD_CFG_STRUCT(GPD11, 0x4000201, 0x1000), /* GPIO */
+
+_PAD_CFG_STRUCT(GPP_F0, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F1, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F2, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F3, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F4, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F5, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F6, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F7, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F8, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F9, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F10, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F11, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F12, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F13, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F14, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F15, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F16, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F17, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F18, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F19, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F20, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F21, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F22, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_F23, 0x40100100, 0x0), /* GPIO */
+
+_PAD_CFG_STRUCT(GPP_G0, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_G1, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_G2, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_G3, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_G4, 0x44000200, 0x0), /* GPIO */
+_PAD_CFG_STRUCT(GPP_G5, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_G6, 0x44000201, 0x1000), /* GPIO */
+_PAD_CFG_STRUCT(GPP_G7, 0x44000201, 0x1000), /* GPIO */
+};
+
+#endif
+
+#endif
diff --git a/src/mainboard/acer/aspire_vn7_572g/hda_verb.c b/src/mainboard/acer/aspire_vn7_572g/hda_verb.c
new file mode 100644
index 0000000..8cd5f97
--- /dev/null
+++ b/src/mainboard/acer/aspire_vn7_572g/hda_verb.c
@@ -0,0 +1,72 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Purism SPC.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ /* coreboot specific header */
+ 0x10ec0255, /* Codec Vendor / Device ID: Realtek ALC255 */
+ 0x10251037, /* Subsystem ID */
+ 0x0000000c, /* Number of jacks (NID entries) */
+
+ 0x0017ff00, /* Function Reset */
+ 0x0017ff00, /* Double Function Reset */
+ 0x0017ff00,
+ 0x0017ff00,
+
+ /* Bits 31:28 - Codec Address */
+ /* Bits 27:20 - NID */
+ /* Bits 19:8 - Verb ID */
+ /* Bits 7:0 - Payload */
+
+ /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x10251037 */
+ AZALIA_SUBVENDOR(0x0, 0x10251037),
+
+ /* Pin Widget Verb Table */
+
+ /* Pin Complex (NID 0x12) */
+ AZALIA_PIN_CFG(0x0, 0x12, 0x411111c0),
+
+ /* Pin Complex (NID 0x14) */
+ AZALIA_PIN_CFG(0x0, 0x14, 0x90172120),
+
+ /* Pin Complex (NID 0x17) */
+ AZALIA_PIN_CFG(0x0, 0x17, 0x40000000),
+
+ /* Pin Complex (NID 0x18) */
+ AZALIA_PIN_CFG(0x0, 0x18, 0x411111f0),
+
+ /* Pin Complex (NID 0x19) */
+ AZALIA_PIN_CFG(0x0, 0x19, 0x411111f0),
+
+ /* Pin Complex (NID 0x1A) */
+ AZALIA_PIN_CFG(0x0, 0x1A, 0x411111f0),
+
+ /* Pin Complex (NID 0x1B) */
+ AZALIA_PIN_CFG(0x0, 0x1B, 0x411111f0),
+
+ /* Pin Complex (NID 0x1D) */
+ AZALIA_PIN_CFG(0x0, 0x1D, 0x40700001),
+
+ /* Pin Complex (NID 0x1E) */
+ AZALIA_PIN_CFG(0x0, 0x1E, 0x411111f0),
+
+ /* Pin Complex (NID 0x21) */
+ AZALIA_PIN_CFG(0x0, 0x21, 0x02211030),
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/acer/aspire_vn7_572g/mainboard.c b/src/mainboard/acer/aspire_vn7_572g/mainboard.c
new file mode 100644
index 0000000..462b995
--- /dev/null
+++ b/src/mainboard/acer/aspire_vn7_572g/mainboard.c
@@ -0,0 +1,50 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Purism SPC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <smbios.h>
+#include <string.h>
+#include <cbfs.h>
+
+#define MAX_SERIAL_LENGTH 0x100
+
+const char *smbios_mainboard_serial_number(void)
+{
+ static char serial_number[MAX_SERIAL_LENGTH + 1] = {0};
+ struct cbfsf file;
+
+ if (serial_number[0] != 0)
+ return serial_number;
+
+ if (cbfs_boot_locate(&file, "serial_number", NULL) == 0) {
+ struct region_device cbfs_region;
+ size_t serial_len;
+
+ cbfs_file_data(&cbfs_region, &file);
+
+ serial_len = region_device_sz(&cbfs_region);
+ if (serial_len <= MAX_SERIAL_LENGTH) {
+ if (rdev_readat(&cbfs_region, serial_number, 0,
+ serial_len) == serial_len) {
+ serial_number[serial_len] = 0;
+ return serial_number;
+ }
+ }
+ }
+
+ strncpy(serial_number, CONFIG_MAINBOARD_SERIAL_NUMBER,
+ MAX_SERIAL_LENGTH);
+
+ return serial_number;
+}
diff --git a/src/mainboard/acer/aspire_vn7_572g/ramstage.c b/src/mainboard/acer/aspire_vn7_572g/ramstage.c
new file mode 100644
index 0000000..94f8071
--- /dev/null
+++ b/src/mainboard/acer/aspire_vn7_572g/ramstage.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corporation
+ * Copyright (C) 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/ramstage.h>
+#include "gpio.h"
+
+void mainboard_silicon_init_params(FSP_SIL_UPD *params)
+{
+ /* Configure pads prior to SiliconInit() in case there's any
+ * dependencies during hardware initialization. */
+ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
diff --git a/src/mainboard/acer/aspire_vn7_572g/romstage.c b/src/mainboard/acer/aspire_vn7_572g/romstage.c
new file mode 100644
index 0000000..86ef5af
--- /dev/null
+++ b/src/mainboard/acer/aspire_vn7_572g/romstage.c
@@ -0,0 +1,84 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2015 Intel Corporation
+ * Copyright (C) 2017 Purism SPC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <assert.h>
+#include <soc/romstage.h>
+#include <spd_bin.h>
+#include <string.h>
+
+static void mainboard_fill_dq_map_data(void *dq_map_ch0, void *dq_map_ch1)
+{
+ /* DQ byte map */
+ const u8 dq_map[2][12] = {
+ { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,
+ 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 },
+ { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC,
+ 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } };
+ memcpy(dq_map_ch0, dq_map[0], sizeof(dq_map[0]));
+ memcpy(dq_map_ch1, dq_map[1], sizeof(dq_map[1]));
+}
+
+static void mainboard_fill_dqs_map_data(void *dqs_map_ch0, void *dqs_map_ch1)
+{
+ /* DQS CPU<>DRAM map */
+ const u8 dqs_map[2][8] = {
+ { 0, 1, 3, 2, 4, 5, 6, 7 },
+ { 1, 0, 4, 5, 2, 3, 6, 7 } };
+ memcpy(dqs_map_ch0, dqs_map[0], sizeof(dqs_map[0]));
+ memcpy(dqs_map_ch1, dqs_map[1], sizeof(dqs_map[1]));
+}
+
+static void mainboard_fill_rcomp_res_data(void *rcomp_ptr)
+{
+ /* Rcomp resistor */
+ const u16 RcompResistor[3] = { 121, 81, 100 };
+ memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor));
+}
+
+static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr)
+{
+ /* Rcomp target */
+ const u16 RcompTarget[5] = { 100, 40, 20, 20, 26 };
+ memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget));
+}
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+ FSP_M_CONFIG *mem_cfg;
+ struct spd_block blk = {
+ .addr_map = { 0x50, 0x52 },
+ };
+
+ mem_cfg = &mupd->FspmConfig;
+
+ get_spd_smbus(&blk);
+ dump_spd_info(&blk);
+ assert(blk.spd_array[0][0] != 0);
+
+ mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0,
+ &mem_cfg->DqByteMapCh1);
+ mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0,
+ &mem_cfg->DqsMapCpu2DramCh1);
+ mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor);
+ mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);
+
+ mem_cfg->DqPinsInterleaved = TRUE;
+ mem_cfg->MemorySpdDataLen = blk.len;
+ mem_cfg->MemorySpdPtr00 = (uintptr_t) blk.spd_array[0];
+ mem_cfg->MemorySpdPtr10 = (uintptr_t) blk.spd_array[1];
+}
--
To view, visit https://review.coreboot.org/c/coreboot/+/35523
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6
Gerrit-Change-Number: 35523
Gerrit-PatchSet: 1
Gerrit-Owner: Benjamin Doron
Gerrit-MessageType: newchange
by Mike Banon (Code Review)
Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33920
Change subject: src/mainboard/asus/am1i-a/buildOpts.c: improve the RAM frequency related defines
......................................................................
src/mainboard/asus/am1i-a/buildOpts.c: improve the RAM frequency related defines
This improvement is likely required for forcing a pair of 1866MHz CL9 RAM sticks
to work faster than a mediocre 1333MHz CL9, but sadly alone it's not enough...
Still it doesn't bring any downsides to a system operation, just no upsides yet.
Signed-off-by: Mike Banon <mikebdp2(a)gmail.com>
Change-Id: Ib2bc605b98ad99066549017697bb483ad3be3910
---
M src/mainboard/asus/am1i-a/buildOpts.c
1 file changed, 5 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/33920/1
diff --git a/src/mainboard/asus/am1i-a/buildOpts.c b/src/mainboard/asus/am1i-a/buildOpts.c
index 98bc620..48c5c56 100644
--- a/src/mainboard/asus/am1i-a/buildOpts.c
+++ b/src/mainboard/asus/am1i-a/buildOpts.c
@@ -117,22 +117,22 @@
#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_DESKTOP
-#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1600_FREQUENCY
+#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY
#define BLDCFG_MEMORY_MODE_UNGANGED TRUE
#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE
#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
#define BLDCFG_MEMORY_RDIMM_CAPABLE TRUE
#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE
#define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE
-#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING FALSE
-#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE
-#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE
+#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE
+#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING TRUE
+#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE
#define BLDCFG_MEMORY_POWER_DOWN TRUE
#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT
#define BLDCFG_ONLINE_SPARE FALSE
#define BLDCFG_BANK_SWIZZLE TRUE
#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
-#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY
+#define BLDCFG_MEMORY_CLOCK_SELECT DDR1866_FREQUENCY
#define BLDCFG_DQS_TRAINING_CONTROL TRUE
#define BLDCFG_IGNORE_SPD_CHECKSUM TRUE
#define BLDCFG_USE_BURST_MODE FALSE
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ib2bc605b98ad99066549017697bb483ad3be3910
Gerrit-Change-Number: 33920
Gerrit-PatchSet: 1
Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com>
Gerrit-MessageType: newchange
by Mike Banon (Code Review)
Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33919
Change subject: src/mainboard/asus/am1i-a/buildOpts.c: set a board type to AMD_PLATFORM_DESKTOP
......................................................................
src/mainboard/asus/am1i-a/buildOpts.c: set a board type to AMD_PLATFORM_DESKTOP
Original AMD_PLATFORM_MOBILE is incorrect because this board is a desktop one.
Signed-off-by: Mike Banon <mikebdp2(a)gmail.com>
Change-Id: I02adedffe8624c38e7b93fadd0449ddf094388fd
---
M src/mainboard/asus/am1i-a/buildOpts.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/33919/1
diff --git a/src/mainboard/asus/am1i-a/buildOpts.c b/src/mainboard/asus/am1i-a/buildOpts.c
index cba0894..98bc620 100644
--- a/src/mainboard/asus/am1i-a/buildOpts.c
+++ b/src/mainboard/asus/am1i-a/buildOpts.c
@@ -115,7 +115,7 @@
#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
#define BLDCFG_MEM_INIT_PSTATE 0
-#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
+#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_DESKTOP
#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1600_FREQUENCY
#define BLDCFG_MEMORY_MODE_UNGANGED TRUE
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I02adedffe8624c38e7b93fadd0449ddf094388fd
Gerrit-Change-Number: 33919
Gerrit-PatchSet: 1
Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com>
Gerrit-MessageType: newchange
by Mike Banon (Code Review)
Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33918
Change subject: src/mainboard/asus/am1i-a/buildOpts.c: uncomment the RAM speed-related defines
......................................................................
src/mainboard/asus/am1i-a/buildOpts.c: uncomment the RAM speed-related defines
Not sure why they have been commented out. Bringing them back does not affect a
system operation, and they may be useful later while fixing the low RAM speeds.
Signed-off-by: Mike Banon <mikebdp2(a)gmail.com>
Change-Id: Ic0468d329c6efa9abffc8859a542aae0cf702863
---
M src/mainboard/asus/am1i-a/buildOpts.c
1 file changed, 25 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/33918/1
diff --git a/src/mainboard/asus/am1i-a/buildOpts.c b/src/mainboard/asus/am1i-a/buildOpts.c
index 643b306..cba0894 100644
--- a/src/mainboard/asus/am1i-a/buildOpts.c
+++ b/src/mainboard/asus/am1i-a/buildOpts.c
@@ -265,31 +265,31 @@
#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '}
/* MEMORY_BUS_SPEED */
-//#define DDR400_FREQUENCY 200 ///< DDR 400
-//#define DDR533_FREQUENCY 266 ///< DDR 533
-//#define DDR667_FREQUENCY 333 ///< DDR 667
-//#define DDR800_FREQUENCY 400 ///< DDR 800
-//#define DDR1066_FREQUENCY 533 ///< DDR 1066
-//#define DDR1333_FREQUENCY 667 ///< DDR 1333
-//#define DDR1600_FREQUENCY 800 ///< DDR 1600
-//#define DDR1866_FREQUENCY 933 ///< DDR 1866
-//#define DDR2100_FREQUENCY 1050 ///< DDR 2100
-//#define DDR2133_FREQUENCY 1066 ///< DDR 2133
-//#define DDR2400_FREQUENCY 1200 ///< DDR 2400
-//#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency
-//
-///* QUANDRANK_TYPE*/
-//#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
-//#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
-//
-///* USER_MEMORY_TIMING_MODE */
-//#define TIMING_MODE_AUTO 0 ///< Use best rate possible
-//#define TIMING_MODE_LIMITED 1 ///< Set user top limit
-//#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
-//
-///* POWER_DOWN_MODE */
-//#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
-//#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
+#define DDR400_FREQUENCY 200 ///< DDR 400
+#define DDR533_FREQUENCY 266 ///< DDR 533
+#define DDR667_FREQUENCY 333 ///< DDR 667
+#define DDR800_FREQUENCY 400 ///< DDR 800
+#define DDR1066_FREQUENCY 533 ///< DDR 1066
+#define DDR1333_FREQUENCY 667 ///< DDR 1333
+#define DDR1600_FREQUENCY 800 ///< DDR 1600
+#define DDR1866_FREQUENCY 933 ///< DDR 1866
+#define DDR2100_FREQUENCY 1050 ///< DDR 2100
+#define DDR2133_FREQUENCY 1066 ///< DDR 2133
+#define DDR2400_FREQUENCY 1200 ///< DDR 2400
+#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency
+
+/* QUANDRANK_TYPE*/
+#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
+#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
+
+/* USER_MEMORY_TIMING_MODE */
+#define TIMING_MODE_AUTO 0 ///< Use best rate possible
+#define TIMING_MODE_LIMITED 1 ///< Set user top limit
+#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
+
+/* POWER_DOWN_MODE */
+#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
+#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
/*
* Agesa optional capabilities selection.
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ic0468d329c6efa9abffc8859a542aae0cf702863
Gerrit-Change-Number: 33918
Gerrit-PatchSet: 1
Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com>
Gerrit-MessageType: newchange
by Mike Banon (Code Review)
Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33917
Change subject: src/mainboard/asus/am1i-a/buildOpts.c: add includes for adjusting RAM timings
......................................................................
src/mainboard/asus/am1i-a/buildOpts.c: add includes for adjusting RAM timings
These tables may be used to adjust memory timing settings.
Signed-off-by: Mike Banon <mikebdp2(a)gmail.com>
Change-Id: I782f76119c5ce9a3cc4bc07596d27dd42b615b6d
---
M src/mainboard/asus/am1i-a/buildOpts.c
1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/33917/1
diff --git a/src/mainboard/asus/am1i-a/buildOpts.c b/src/mainboard/asus/am1i-a/buildOpts.c
index dfd27cd..643b306 100644
--- a/src/mainboard/asus/am1i-a/buildOpts.c
+++ b/src/mainboard/asus/am1i-a/buildOpts.c
@@ -42,6 +42,9 @@
#include <vendorcode/amd/agesa/f16kb/Proc/Common/CreateStruct.h>
#include <vendorcode/amd/agesa/f16kb/Proc/CPU/cpuEarlyInit.h>
#include <vendorcode/amd/agesa/f16kb/Proc/CPU/cpuLateInit.h>
+/* These tables are optional and may be used to adjust memory timing settings */
+#include <vendorcode/amd/agesa/f16kb/Proc/Mem/mm.h>
+#include <vendorcode/amd/agesa/f16kb/Proc/Mem/mn.h>
/* Select the CPU family. */
#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I782f76119c5ce9a3cc4bc07596d27dd42b615b6d
Gerrit-Change-Number: 33917
Gerrit-PatchSet: 1
Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com>
Gerrit-MessageType: newchange
by Mike Banon (Code Review)
Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33916
Change subject: src/mainboard/asus/am1i-a/buildOpts.c: guard UMA-related options by CONFIG_GFXUMA
......................................................................
src/mainboard/asus/am1i-a/buildOpts.c: guard UMA-related options by CONFIG_GFXUMA
Seems this guard has been accidentally removed during the creation of this file.
Signed-off-by: Mike Banon <mikebdp2(a)gmail.com>
Change-Id: Ie73c4d6cb557820ae7427fef15ca8110722c5b68
---
M src/mainboard/asus/am1i-a/buildOpts.c
1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/33916/1
diff --git a/src/mainboard/asus/am1i-a/buildOpts.c b/src/mainboard/asus/am1i-a/buildOpts.c
index 2a1f13d..dfd27cd 100644
--- a/src/mainboard/asus/am1i-a/buildOpts.c
+++ b/src/mainboard/asus/am1i-a/buildOpts.c
@@ -176,9 +176,11 @@
#define BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT 17000
#define BLDCFG_VRM_NB_SVI_OCP_LEVEL BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT
+#if CONFIG(GFXUMA)
#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED
#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO
#define OPTION_GFX_INIT_SVIEW FALSE
+#endif
#define BLDCFG_PCIE_TRAINING_ALGORITHM PcieTrainingDistributed
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ie73c4d6cb557820ae7427fef15ca8110722c5b68
Gerrit-Change-Number: 33916
Gerrit-PatchSet: 1
Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com>
Gerrit-MessageType: newchange
by Mike Banon (Code Review)
Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33915
Change subject: src/mainboard/asus/am1i-a/buildOpts.c: return the removed comments
......................................................................
src/mainboard/asus/am1i-a/buildOpts.c: return the removed comments
These comments exist in some other buildOpts.c files, but not in this one.
Signed-off-by: Mike Banon <mikebdp2(a)gmail.com>
Change-Id: Ic0aab06f1956bc0bf9f96d6176643c113a1e4cc5
---
M src/mainboard/asus/am1i-a/buildOpts.c
1 file changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/33915/1
diff --git a/src/mainboard/asus/am1i-a/buildOpts.c b/src/mainboard/asus/am1i-a/buildOpts.c
index 8ba5975..2a1f13d 100644
--- a/src/mainboard/asus/am1i-a/buildOpts.c
+++ b/src/mainboard/asus/am1i-a/buildOpts.c
@@ -43,8 +43,10 @@
#include <vendorcode/amd/agesa/f16kb/Proc/CPU/cpuEarlyInit.h>
#include <vendorcode/amd/agesa/f16kb/Proc/CPU/cpuLateInit.h>
+/* Select the CPU family. */
#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE
+/* Select the CPU socket type. */
#define INSTALL_G34_SOCKET_SUPPORT FALSE
#define INSTALL_C32_SOCKET_SUPPORT FALSE
#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
@@ -165,6 +167,8 @@
#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770
+// Specify the default values for the VRM controlling the VDDNB plane.
+// If not specified, the values used for the core VRM will be applied
#define BLDCFG_VRM_NB_CURRENT_LIMIT 13000
#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 0
#define BLDCFG_VRM_SLEW_RATE 10000
@@ -344,4 +348,5 @@
#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
#define DFLT_VRM_SLEW_RATE (5000)
+/* AGESA nonsense: this header depends on the definitions above */
#include <PlatformInstall.h>
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ic0aab06f1956bc0bf9f96d6176643c113a1e4cc5
Gerrit-Change-Number: 33915
Gerrit-PatchSet: 1
Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com>
Gerrit-MessageType: newchange
by Mike Banon (Code Review)
Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33913
Change subject: src/mainboard/asus/am1i-a/buildOpts.c: reorder lines for comparison convenience
......................................................................
src/mainboard/asus/am1i-a/buildOpts.c: reorder lines for comparison convenience
Reorder lines to make it more similar to i.e. buildOpts.c of Lenovo G505S.
This is needed to improve the convenience of comparison during the debugging.
Signed-off-by: Mike Banon <mikebdp2(a)gmail.com>
Change-Id: I1674252fab2fc6fbf9be2b37e97a6f5ff97a04b3
---
M src/mainboard/asus/am1i-a/buildOpts.c
1 file changed, 39 insertions(+), 35 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/33913/1
diff --git a/src/mainboard/asus/am1i-a/buildOpts.c b/src/mainboard/asus/am1i-a/buildOpts.c
index 30c0699..93d7738 100644
--- a/src/mainboard/asus/am1i-a/buildOpts.c
+++ b/src/mainboard/asus/am1i-a/buildOpts.c
@@ -28,7 +28,6 @@
#include <stdlib.h>
#include <AGESA.h>
-#define INSTALL_FT3_SOCKET_SUPPORT TRUE
#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE
#define INSTALL_G34_SOCKET_SUPPORT FALSE
@@ -43,6 +42,7 @@
#define INSTALL_AM3_SOCKET_SUPPORT FALSE
#define INSTALL_FM2_SOCKET_SUPPORT FALSE
+#define INSTALL_FT3_SOCKET_SUPPORT TRUE
#ifdef BLDOPT_REMOVE_FT3_SOCKET_SUPPORT
#if BLDOPT_REMOVE_FT3_SOCKET_SUPPORT == TRUE
@@ -66,7 +66,7 @@
#define BLDOPT_REMOVE_SRAT FALSE //TRUE
#define BLDOPT_REMOVE_SLIT FALSE //TRUE
#define BLDOPT_REMOVE_WHEA FALSE //TRUE
-#define BLDOPT_REMOVE_CRAT TRUE
+#define BLDOPT_REMOVE_CRAT TRUE
#define BLDOPT_REMOVE_CDIT TRUE
#define BLDOPT_REMOVE_DMI TRUE
//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE
@@ -86,28 +86,14 @@
#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER
/* Build configuration values here.
*/
-#define BLDCFG_VRM_CURRENT_LIMIT 15000
-#define BLDCFG_VRM_NB_CURRENT_LIMIT 13000
-#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 21000
-#define BLDCFG_VRM_SVI_OCP_LEVEL BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT
-#define BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT 17000
-#define BLDCFG_VRM_NB_SVI_OCP_LEVEL BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT
-#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0
-#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 0
-#define BLDCFG_VRM_SLEW_RATE 10000
-#define BLDCFG_VRM_NB_SLEW_RATE BLDCFG_VRM_SLEW_RATE
-#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE
-
+#define BLDCFG_VRM_CURRENT_LIMIT 15000
+#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0
+#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 21000
+#define BLDCFG_VRM_SVI_OCP_LEVEL BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT
#define BLDCFG_PLAT_NUM_IO_APICS 3
-#define BLDCFG_GNB_IOAPIC_ADDRESS 0xFEC20000
+#define BLDCFG_GNB_IOAPIC_ADDRESS 0xFEC20000
#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
#define BLDCFG_MEM_INIT_PSTATE 0
-#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 // Specifies the IO addresses trapped by the
- // core for C-state entry requests. A value
- // of 0 in this field specifies that the core
- // does not trap any IO addresses for C-state entry.
- // Values greater than 0xFFF8 results in undefined behavior.
-#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770
#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
@@ -138,34 +124,52 @@
#define BLDCFG_SCRUB_L3_RATE 0
#define BLDCFG_SCRUB_IC_RATE 0
#define BLDCFG_SCRUB_DC_RATE 0
-#define BLDCFG_ECC_SYNC_FLOOD FALSE
#define BLDCFG_ECC_SYMBOL_SIZE 4
-#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000ul
+#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000
+#define BLDCFG_ECC_SYNC_FLOOD FALSE
+#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE
#define BLDCFG_1GB_ALIGN FALSE
-#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED
-#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO
-#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeDisabled
-#define BLDCFG_IOMMU_SUPPORT FALSE
-#define OPTION_GFX_INIT_SVIEW FALSE
//#define BLDCFG_PLATFORM_POWER_POLICY_MODE BatteryLife
+#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 // Specifies the IO addresses trapped by the
+ // core for C-state entry requests. A value
+ // of 0 in this field specifies that the core
+ // does not trap any IO addresses for C-state entry.
+ // Values greater than 0xFFF8 results in undefined behavior.
+
+#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P'
+#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0'
+#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeDisabled
//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL OEM_LCD_BACK_LIGHT_CONTROL
#define BLDCFG_CFG_ABM_SUPPORT TRUE
-#define BLDCFG_CFG_GNB_HD_AUDIO TRUE
-//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID
-//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID
-//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID
-
#ifdef PCIEX_BASE_ADDRESS
#define BLDCFG_PCI_MMIO_BASE PCIEX_BASE_ADDRESS
#define BLDCFG_PCI_MMIO_SIZE (PCIEX_LENGTH >> 20)
#endif
-#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P'
-#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0'
+#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770
+
+#define BLDCFG_VRM_NB_CURRENT_LIMIT 13000
+#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 0
+#define BLDCFG_VRM_SLEW_RATE 10000
+#define BLDCFG_VRM_NB_SLEW_RATE BLDCFG_VRM_SLEW_RATE
+#define BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT 17000
+#define BLDCFG_VRM_NB_SVI_OCP_LEVEL BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT
+
+#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED
+#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO
+#define OPTION_GFX_INIT_SVIEW FALSE
+
#define BLDCFG_PCIE_TRAINING_ALGORITHM PcieTrainingDistributed
+#define BLDCFG_IOMMU_SUPPORT FALSE
+
+#define BLDCFG_CFG_GNB_HD_AUDIO TRUE
+//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID
+//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID
+//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID
+
/* Process the options...
* This file include MUST occur AFTER the user option selection settings
*/
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I1674252fab2fc6fbf9be2b37e97a6f5ff97a04b3
Gerrit-Change-Number: 33913
Gerrit-PatchSet: 1
Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com>
Gerrit-MessageType: newchange
by Mike Banon (Code Review)
Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33914
Change subject: src/mainboard/asus/am1i-a/buildOpts.c: detailed paths to the include files
......................................................................
src/mainboard/asus/am1i-a/buildOpts.c: detailed paths to the include files
Make it clear which include files are being used, by using the detailed paths.
Signed-off-by: Mike Banon <mikebdp2(a)gmail.com>
Change-Id: Ic096848f23910e2ad9183e44d882450ab8d4fdf1
---
M src/mainboard/asus/am1i-a/buildOpts.c
1 file changed, 15 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/33914/1
diff --git a/src/mainboard/asus/am1i-a/buildOpts.c b/src/mainboard/asus/am1i-a/buildOpts.c
index 93d7738..b5b06d3 100644
--- a/src/mainboard/asus/am1i-a/buildOpts.c
+++ b/src/mainboard/asus/am1i-a/buildOpts.c
@@ -26,7 +26,21 @@
*/
#include <stdlib.h>
-#include <AGESA.h>
+#include <vendorcode/amd/agesa/f16kb/AGESA.h>
+
+/* Include the files that instantiate the configuration definitions. */
+#include <vendorcode/amd/agesa/f16kb/Include/AdvancedApi.h>
+#include <vendorcode/amd/agesa/f16kb/Include/GnbInterface.h>
+#include <vendorcode/amd/agesa/f16kb/Proc/CPU/cpuFamilyTranslation.h>
+#include <vendorcode/amd/agesa/f16kb/Proc/CPU/cpuRegisters.h>
+#include <vendorcode/amd/agesa/f16kb/Proc/CPU/Family/cpuFamRegisters.h>
+#include <vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuFeatures.h>
+#include <vendorcode/amd/agesa/f16kb/Proc/CPU/Table.h>
+#include <vendorcode/amd/agesa/f16kb/Proc/CPU/heapManager.h>
+/* AGESA nonesense: the next three headers depend on heapManager.h */
+#include <vendorcode/amd/agesa/f16kb/Proc/Common/CreateStruct.h>
+#include <vendorcode/amd/agesa/f16kb/Proc/CPU/cpuEarlyInit.h>
+#include <vendorcode/amd/agesa/f16kb/Proc/CPU/cpuLateInit.h>
#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE
@@ -232,20 +246,6 @@
#define BLDCFG_AP_MTRR_SETTINGS_LIST &KabiniApMtrrSettingsList
-
-/* Include the files that instantiate the configuration definitions. */
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "AdvancedApi.h"
-#include "heapManager.h"
-#include "CreateStruct.h"
-#include "cpuFeatures.h"
-#include "Table.h"
-#include "cpuEarlyInit.h"
-#include "cpuLateInit.h"
-#include "GnbInterface.h"
-
// This is the delivery package title, "BrazosPI"
// This string MUST be exactly 8 characters long
#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'}
--
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Gerrit-Change-Id: Ic096848f23910e2ad9183e44d882450ab8d4fdf1
Gerrit-Change-Number: 33914
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Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com>
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by Kyösti Mälkki (Code Review)
Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35035 )
Change subject: [WIP] arch/x86: Add linker script for early DRAM
......................................................................
[WIP] arch/x86: Add linker script for early DRAM
Change-Id: I9c084ff6fdcf7e9154436f038705e8679daea780
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
A src/arch/x86/early_dram.ld
1 file changed, 50 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/35035/1
diff --git a/src/arch/x86/early_dram.ld b/src/arch/x86/early_dram.ld
new file mode 100644
index 0000000..24b9551
--- /dev/null
+++ b/src/arch/x86/early_dram.ld
@@ -0,0 +1,50 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2006 Advanced Micro Devices, Inc.
+ * Copyright (C) 2008-2010 coresystems GmbH
+ * Copyright 2015 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* This file is included inside a SECTIONS block */
+. = CONFIG_DCACHE_RAM_BASE;
+.car.data . (NOLOAD) : {
+ _car_region_start = . ;
+
+ /* Stack for CAR stages. Since it persists across all stages that
+ * use CAR it can be reused. The chipset/SoC is expected to provide
+ * the stack size. */
+#if CONFIG(C_ENVIRONMENT_BOOTBLOCK)
+ _car_stack_start = .;
+ . += CONFIG_DCACHE_BSP_STACK_SIZE;
+ _car_stack_end = .;
+#endif
+ /* The pre-ram cbmem console as well as the timestamp region are fixed
+ * in size. Therefore place them above the car global section so that
+ * multiple stages (romstage and verstage) have a consistent
+ * link address of these shared objects. */
+ PRERAM_CBMEM_CONSOLE(., CONFIG_PRERAM_CBMEM_CONSOLE_SIZE)
+
+ TIMESTAMP(., 0x200)
+
+ _car_ehci_dbg_info_start = .;
+ /* Reserve sizeof(struct ehci_dbg_info). */
+ . += 80;
+ _car_ehci_dbg_info_end = .;
+
+ _car_region_end = . + CONFIG_DCACHE_RAM_SIZE - (. - _car_region_start);
+}
+
+_bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full");
+#if !CONFIG(CAR_GLOBAL_MIGRATION)
+_bogus3 = ASSERT(CONFIG_DCACHE_BSP_STACK_SIZE > 0x0, "BSP stack size not configured");
+#endif
--
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Gerrit-Change-Number: 35035
Gerrit-PatchSet: 1
Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org>
Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Gerrit-MessageType: newchange
