by mturney mturney (Code Review)
mturney mturney has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35506 )
Change subject: trogdor: support mbn_version 6 with python build scripts
......................................................................
trogdor: support mbn_version 6 with python build scripts
Developer/Reviewer, be aware of this patch from Mistral:
https://review.coreboot.org/c/coreboot/+/33425/18
Change-Id: I020d1e4d4f5c948948e1b39dd18af1d0e860c279
Signed-off-by: T Michael Turney <mturney(a)codeaurora.org>
---
M util/qualcomm/createxbl.py
M util/qualcomm/mbn_tools.py
2 files changed, 90 insertions(+), 36 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/35506/1
diff --git a/util/qualcomm/createxbl.py b/util/qualcomm/createxbl.py
index 4a21854..769e9f1e 100755
--- a/util/qualcomm/createxbl.py
+++ b/util/qualcomm/createxbl.py
@@ -44,6 +44,7 @@
#
# when who what, where, why
# -------- --- ------------------------------------------------------
+# 05/21/19 rissha Added --mbn_version to add MBN header accordingly
# 03/26/18 tv Added -e to enable extended MBNV5 support
# 09/04/15 et Added -x and -d to embed xbl_sec ELF
# 02/11/15 ck Fixed missing elf type check in ZI OOB feature
@@ -119,6 +120,10 @@
help="Removes ZI segments that have addresses greater" + \
" than 32 bits when converting from a 64 to 32 bit ELF")
+ parser.add_option("--mbn_version",
+ action="store", type="int", dest="mbn_version",
+ help="Add mbn header in elf image. '3', '5' or '6'")
+
(options, args) = parser.parse_args()
if not options.elf_inp_file1:
@@ -206,11 +211,16 @@
else:
zi_oob_enabled = True
+ header_version = 3
+
if options.elf_inp_xbl_sec:
is_ext_mbn_v5 = True
+ header_version = 5
else:
is_ext_mbn_v5 = False
+ if options.mbn_version:
+ header_version = options.mbn_version
mbn_type = 'elf'
header_format = 'reg'
@@ -259,7 +269,7 @@
source_elf,
target_hash,
elf_out_file_name = target_phdr_elf,
- secure_type = image_header_secflag)
+ secure_type = image_header_secflag, header_version = header_version )
if rv:
raise RuntimeError, "Failed to run pboot_gen_elf"
@@ -270,7 +280,8 @@
target_hash_hd,
image_header_secflag,
is_ext_mbn_v5,
- elf_file_name = source_elf)
+ elf_file_name = source_elf,
+ header_version = header_version)
if rv:
raise RuntimeError, "Failed to create image header for hash segment"
diff --git a/util/qualcomm/mbn_tools.py b/util/qualcomm/mbn_tools.py
index 12dc210..079e02e 100755
--- a/util/qualcomm/mbn_tools.py
+++ b/util/qualcomm/mbn_tools.py
@@ -41,6 +41,7 @@
#
# when who what, where, why
# -------- --- ---------------------------------------------------------
+# 05/21/18 rissha Added support for extended MBNV6 and Add support for hashing elf segments with SHA384
# 03/22/18 thiru Added support for extended MBNV5.
# 06/06/13 yliong CR 497042: Signed and encrypted image is corrupted. MRC features.
# 03/18/13 dhaval Add support for hashing elf segments with SHA256 and
@@ -64,23 +65,24 @@
#----------------------------------------------------------------------------
# GLOBAL VARIABLES BEGIN
#----------------------------------------------------------------------------
-PAD_BYTE_1 = 255 # Padding byte 1s
-PAD_BYTE_0 = 0 # Padding byte 0s
-SHA256_SIGNATURE_SIZE = 256 # Support SHA256
-MAX_NUM_ROOT_CERTS = 4 # Maximum number of OEM root certificates
-MI_BOOT_IMG_HDR_SIZE = 40 # sizeof(mi_boot_image_header_type)
-MI_BOOT_SBL_HDR_SIZE = 80 # sizeof(sbl_header)
-BOOT_HEADER_LENGTH = 20 # Boot Header Number of Elements
-SBL_HEADER_LENGTH = 20 # SBL Header Number of Elements
-FLASH_PARTI_VERSION = 3 # Flash Partition Version Number
-MAX_PHDR_COUNT = 100 # Maximum allowable program headers
-CERT_CHAIN_ONEROOT_MAXSIZE = 6*1024 # Default Cert Chain Max Size for one root
-VIRTUAL_BLOCK_SIZE = 131072 # Virtual block size for MCs insertion in SBL1 if ENABLE_VIRTUAL_BLK ON
-MAGIC_COOKIE_LENGTH = 12 # Length of magic Cookie inserted per VIRTUAL_BLOCK_SIZE
-MIN_IMAGE_SIZE_WITH_PAD = 256*1024 # Minimum image size for sbl1 Nand based OTA feature
+PAD_BYTE_1 = 255 # Padding byte 1s
+PAD_BYTE_0 = 0 # Padding byte 0s
+SHA256_SIGNATURE_SIZE = 256 # Support SHA256
+MAX_NUM_ROOT_CERTS = 4 # Maximum number of OEM root certificates
+MBN_HEADER_VERSION_3 = 3 # Mbn header_version 3
+MBN_HEADER_VERSION_5 = 5 # Mbn header_version 5
+MBN_HEADER_VERSION_6 = 6 # Mbn header_version 6
+MI_BOOT_SBL_HDR_SIZE = 80 # sizeof(sbl_header)
+BOOT_HEADER_LENGTH = 20 # Boot Header Number of Elements
+SBL_HEADER_LENGTH = 20 # SBL Header Number of Elements
+MAX_PHDR_COUNT = 100 # Maximum allowable program headers
+CERT_CHAIN_ONEROOT_MAXSIZE = 6*1024 # Default Cert Chain Max Size for one root
+VIRTUAL_BLOCK_SIZE = 131072 # Virtual block size for MCs insertion in SBL1 if ENABLE_VIRTUAL_BLK ON
+MAGIC_COOKIE_LENGTH = 12 # Length of magic Cookie inserted per VIRTUAL_BLOCK_SIZE
+MIN_IMAGE_SIZE_WITH_PAD = 256*1024 # Minimum image size for sbl1 Nand based OTA feature
-SBL_AARCH64 = 0xF # Indicate that SBL is a Aarch64 image
-SBL_AARCH32 = 0x0 # Indicate that SBL is a Aarch32 image
+SBL_AARCH64 = 0xF # Indicate that SBL is a Aarch64 image
+SBL_AARCH32 = 0x0 # Indicate that SBL is a Aarch32 image
# Magic numbers filled in for boot headers
FLASH_CODE_WORD = 0x844BDCD1
@@ -528,7 +530,7 @@
class Boot_Hdr:
def __init__(self, init_val):
self.image_id = ImageType.NONE_IMG
- self.flash_parti_ver = FLASH_PARTI_VERSION
+ self.flash_parti_ver = MBN_HEADER_VERSION_3
self.image_src = init_val
self.image_dest_ptr = init_val
self.image_size = init_val
@@ -573,6 +575,10 @@
self.reserved_2,
self.reserved_3 ]
+ if self.flash_parti_ver == MBN_HEADER_VERSION_6:
+ values.insert(10, self.metadata_size_qti)
+ values.insert(11, self.metadata_size)
+
if self.image_dest_ptr >= 0x100000000:
values[3] = 0xFFFFFFFF
@@ -584,8 +590,12 @@
# Write 10 entries(40B) or 20 entries(80B) of boot header
if write_full_hdr is False:
- s = struct.Struct('I'* 10)
- values = values[:10]
+ if self.flash_parti_ver == MBN_HEADER_VERSION_6:
+ s = struct.Struct('I'* 12)
+ values = values[:12]
+ else:
+ s = struct.Struct('I'* 10)
+ values = values[:10]
else:
s = struct.Struct('I' * self.getLength())
@@ -912,7 +922,8 @@
write_full_hdr = False,
in_code_size = None,
cert_chain_size_in = CERT_CHAIN_ONEROOT_MAXSIZE,
- num_of_pages = None):
+ num_of_pages = None,
+ header_version = None):
# Preliminary checks
if (requires_preamble is True) and (preamble_file_name is None):
@@ -945,9 +956,12 @@
cert_chain_size = 0
image_size = code_size
+ if header_version:
+ assert header_version in [MBN_HEADER_VERSION_3, MBN_HEADER_VERSION_5, MBN_HEADER_VERSION_6], 'Not a valid MBN header version'
+
# For ELF or hashed images, image destination will be determined from an ELF input file
if gen_dict['IMAGE_KEY_MBN_TYPE'] == 'elf':
- image_dest = get_hash_address(elf_file_name) + MI_BOOT_IMG_HDR_SIZE
+ image_dest = get_hash_address(elf_file_name) + (header_size(header_version))
elif gen_dict['IMAGE_KEY_MBN_TYPE'] == 'bin':
image_dest = gen_dict['IMAGE_KEY_IMAGE_DEST']
image_source = gen_dict['IMAGE_KEY_IMAGE_SOURCE']
@@ -993,10 +1007,17 @@
boot_header.cert_chain_size = cert_chain_size
if is_ext_mbn_v5 == True:
- # If platform image integrity check is enabled
- boot_header.flash_parti_ver = 5 # version
- boot_header.image_src = 0 # sig_size_qc
- boot_header.image_dest_ptr = 0 # cert_chain_size_qc
+ # If platform image integrity check is enabled
+ boot_header.flash_parti_ver = MBN_HEADER_VERSION_5 # version
+ boot_header.image_src = 0 # sig_size_qc
+ boot_header.image_dest_ptr = 0 # cert_chain_size_qc
+
+ if header_version == MBN_HEADER_VERSION_6:
+ boot_header.flash_parti_ver = MBN_HEADER_VERSION_6 # version
+ boot_header.image_src = 0 # sig_size_qc
+ boot_header.image_dest_ptr = 0 # cert_chain_size_qc
+ boot_header.metadata_size_qti = 0 # qti_metadata size
+ boot_header.metadata_size = 0 # oem_metadata size
# If preamble is required, output the preamble file and update the boot_header
if requires_preamble is True:
@@ -1021,9 +1042,20 @@
last_phys_addr = None,
append_xml_hdr = False,
is_sha256_algo = True,
- cert_chain_size_in = CERT_CHAIN_ONEROOT_MAXSIZE):
+ cert_chain_size_in = CERT_CHAIN_ONEROOT_MAXSIZE,
+ header_version = None):
+ sha_algo = 'SHA1'
+ if is_sha256_algo:
+ sha_algo = 'SHA256'
+
+ if header_version == MBN_HEADER_VERSION_6:
+ sha_algo = 'SHA384'
global MI_PROG_BOOT_DIGEST_SIZE
- if (is_sha256_algo is True):
+ image_header_size = header_size(header_version)
+
+ if (sha_algo == 'SHA384'):
+ MI_PROG_BOOT_DIGEST_SIZE = 48
+ elif sha_algo == 'SHA256':
MI_PROG_BOOT_DIGEST_SIZE = 32
else:
MI_PROG_BOOT_DIGEST_SIZE = 20
@@ -1110,7 +1142,7 @@
fbuf = elf_in_fp.read(hash_size)
if MI_PBT_CHECK_FLAG_TYPE(curr_phdr.p_flags) is True:
- hash = generate_hash(fbuf, is_sha256_algo)
+ hash = generate_hash(fbuf, sha_algo)
else:
hash = '\0' * MI_PROG_BOOT_DIGEST_SIZE
@@ -1129,7 +1161,7 @@
file_buff = elf_in_fp.read(data_len)
if (MI_PBT_CHECK_FLAG_TYPE(curr_phdr.p_flags) is True) and (data_len > 0):
- hash = generate_hash(file_buff, is_sha256_algo)
+ hash = generate_hash(file_buff, sha_algo)
else:
hash = '\0' * MI_PROG_BOOT_DIGEST_SIZE
@@ -1151,7 +1183,7 @@
# Initialize the hash table program header
[hash_Phdr, pad_hash_segment, hash_tbl_end_addr, hash_tbl_offset] = \
- initialize_hash_phdr(elf_in_file_name, hashtable_size, MI_BOOT_IMG_HDR_SIZE, ELF_BLOCK_ALIGN, is_elf64)
+ initialize_hash_phdr(elf_in_file_name, hashtable_size, image_header_size, ELF_BLOCK_ALIGN, is_elf64)
# Check if hash segment max size parameter was passed
if (hash_seg_max_size is not None):
@@ -1252,7 +1284,7 @@
# Read the program header and compute hash
proghdr_buff = elf_out_fp.read(elf_header.e_phnum * phdr_size)
- hash = generate_hash(elfhdr_buff + proghdr_buff, is_sha256_algo)
+ hash = generate_hash(elfhdr_buff + proghdr_buff, sha_algo)
# Write hash to file as first hash table entry
hash_out_fp.seek(0)
@@ -1592,7 +1624,7 @@
page = page + elf_in_fp.read(bytes_in_page - len(page))
if (len(page) < DP_PAGE_SIZE):
page = page + (struct.pack('b', 0) * (DP_PAGE_SIZE - len(page)))
- hashes = hashes + [generate_hash(page, True)]
+ hashes = hashes + [generate_hash(page, 'SHA256')]
bytes_left -= bytes_in_page
# And write them to the hash segment
@@ -2101,9 +2133,20 @@
#----------------------------------------------------------------------------
# sha1/sha256 hash routine wrapper
#----------------------------------------------------------------------------
-def generate_hash(in_buf, is_sha256_algo):
+def header_size(header_version):
+ if header_version == MBN_HEADER_VERSION_6:
+ return 48
+ else:
+ return 40
+
+#----------------------------------------------------------------------------
+# sha1/sha256 hash routine wrapper
+#----------------------------------------------------------------------------
+def generate_hash(in_buf, sha_algo):
# Initialize a SHA1 object from the Python hash library
- if (is_sha256_algo is True):
+ if sha_algo == 'SHA384':
+ m = hashlib.sha384()
+ elif sha_algo == 'SHA256':
m = hashlib.sha256()
else:
m = hashlib.sha1()
--
To view, visit https://review.coreboot.org/c/coreboot/+/35506
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I020d1e4d4f5c948948e1b39dd18af1d0e860c279
Gerrit-Change-Number: 35506
Gerrit-PatchSet: 1
Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org>
Gerrit-MessageType: newchange
by Kyösti Mälkki (Code Review)
Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34840 )
Change subject: intel/smm: Provide common smm_relocation_params
......................................................................
intel/smm: Provide common smm_relocation_params
Pull in all copies of smm_relocation_params structs defined
for intel platforms.
Pull in all the inlined MSR accessors to the header file.
Change-Id: I39c6cffee95433aea1a3c783b869eedfff094413
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/cpu/intel/haswell/smmrelocate.c
M src/cpu/intel/smm/gen1/smmrelocate.c
A src/include/cpu/intel/smm_reloc.h
M src/soc/intel/apollolake/cpu.c
M src/soc/intel/baytrail/cpu.c
M src/soc/intel/broadwell/include/soc/smm.h
M src/soc/intel/broadwell/smmrelocate.c
M src/soc/intel/cannonlake/include/soc/smm.h
M src/soc/intel/cannonlake/smmrelocate.c
M src/soc/intel/common/Makefile.inc
M src/soc/intel/fsp_broadwell_de/include/soc/smm.h
M src/soc/intel/fsp_broadwell_de/smmrelocate.c
M src/soc/intel/icelake/include/soc/smm.h
M src/soc/intel/icelake/smmrelocate.c
M src/soc/intel/skylake/include/soc/smm.h
M src/soc/intel/skylake/smmrelocate.c
16 files changed, 91 insertions(+), 185 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/34840/1
diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c
index 5cda618..5a26aff 100644
--- a/src/cpu/intel/haswell/smmrelocate.c
+++ b/src/cpu/intel/haswell/smmrelocate.c
@@ -25,6 +25,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/smm.h>
#include <cpu/intel/em64t101_save_state.h>
+#include <cpu/intel/smm_reloc.h>
#include <console/console.h>
#include <northbridge/intel/haswell/haswell.h>
#include <southbridge/intel/lynxpoint/pch.h>
@@ -46,49 +47,10 @@
#define SMRR_SUPPORTED (1 << 11)
#define PRMRR_SUPPORTED (1 << 12)
-struct smm_relocation_params {
- uintptr_t ied_base;
- size_t ied_size;
- msr_t smrr_base;
- msr_t smrr_mask;
- msr_t prmrr_base;
- msr_t prmrr_mask;
- msr_t uncore_prmrr_base;
- msr_t uncore_prmrr_mask;
- /* The smm_save_state_in_msrs field indicates if SMM save state
- * locations live in MSRs. This indicates to the CPUs how to adjust
- * the SMMBASE and IEDBASE */
- int smm_save_state_in_msrs;
-};
/* This gets filled in and used during relocation. */
-static struct smm_relocation_params smm_reloc_params;
+struct smm_relocation_params smm_reloc_params;
-static inline void write_smrr(struct smm_relocation_params *relo_params)
-{
- printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
- relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
- wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base);
- wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask);
-}
-
-static inline void write_prmrr(struct smm_relocation_params *relo_params)
-{
- printk(BIOS_DEBUG, "Writing PRMRR. base = 0x%08x, mask=0x%08x\n",
- relo_params->prmrr_base.lo, relo_params->prmrr_mask.lo);
- wrmsr(MSR_PRMRR_PHYS_BASE, relo_params->prmrr_base);
- wrmsr(MSR_PRMRR_PHYS_MASK, relo_params->prmrr_mask);
-}
-
-static inline void write_uncore_prmrr(struct smm_relocation_params *relo_params)
-{
- printk(BIOS_DEBUG,
- "Writing UNCORE_PRMRR. base = 0x%08x, mask=0x%08x\n",
- relo_params->uncore_prmrr_base.lo,
- relo_params->uncore_prmrr_mask.lo);
- wrmsr(MSR_UNCORE_PRMRR_PHYS_BASE, relo_params->uncore_prmrr_base);
- wrmsr(MSR_UNCORE_PRMRR_PHYS_MASK, relo_params->uncore_prmrr_mask);
-}
static void update_save_state(int cpu, uintptr_t curr_smbase,
uintptr_t staggered_smbase,
diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c
index d200805..bb19c8c 100644
--- a/src/cpu/intel/smm/gen1/smmrelocate.c
+++ b/src/cpu/intel/smm/gen1/smmrelocate.c
@@ -28,6 +28,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/smm.h>
#include <cpu/intel/em64t101_save_state.h>
+#include <cpu/intel/smm_reloc.h>
#include <console/console.h>
#include <smp/node.h>
#include "smi.h"
@@ -47,15 +48,9 @@
} __packed;
-struct smm_relocation_params {
- uintptr_t ied_base;
- size_t ied_size;
- msr_t smrr_base;
- msr_t smrr_mask;
-};
/* This gets filled in and used during relocation. */
-static struct smm_relocation_params smm_reloc_params;
+struct smm_relocation_params smm_reloc_params;
/* On model_6fx, model_1067x and model_106cx SMRR functions slightly
differently. The MSR are at different location from the rest
@@ -95,15 +90,6 @@
wrmsr(MSR_SMRR_PHYS_MASK, relo_params->smrr_mask);
}
-static void write_smrr(struct smm_relocation_params *relo_params)
-{
- printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
- relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
-
- wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base);
- wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask);
-}
-
static void fill_in_relocation_params(struct smm_relocation_params *params)
{
uintptr_t tseg_base;
diff --git a/src/include/cpu/intel/smm_reloc.h b/src/include/cpu/intel/smm_reloc.h
new file mode 100644
index 0000000..cbcdb56
--- /dev/null
+++ b/src/include/cpu/intel/smm_reloc.h
@@ -0,0 +1,73 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __INTEL_SMM_RELOC_H__
+#define __INTEL_SMM_RELOC_H__
+
+#include <console/console.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/mtrr.h>
+
+struct smm_relocation_params {
+ uintptr_t ied_base;
+ size_t ied_size;
+ msr_t smrr_base;
+ msr_t smrr_mask;
+ msr_t prmrr_base;
+ msr_t prmrr_mask;
+ msr_t uncore_prmrr_base;
+ msr_t uncore_prmrr_mask;
+ /*
+ * The smm_save_state_in_msrs field indicates if SMM save state
+ * locations live in MSRs. This indicates to the CPUs how to adjust
+ * the SMMBASE and IEDBASE
+ */
+ int smm_save_state_in_msrs;
+};
+
+extern struct smm_relocation_params smm_reloc_params;
+
+void fill_in_smrr(struct smm_relocation_params *params);
+
+#define MSR_PRMRR_PHYS_BASE 0x1f4
+#define MSR_PRMRR_PHYS_MASK 0x1f5
+#define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4
+#define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5
+
+static inline void write_smrr(struct smm_relocation_params *relo_params)
+{
+ printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
+ relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
+ wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base);
+ wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask);
+}
+
+static inline void write_prmrr(struct smm_relocation_params *relo_params)
+{
+ printk(BIOS_DEBUG, "Writing PRMRR. base = 0x%08x, mask=0x%08x\n",
+ relo_params->prmrr_base.lo, relo_params->prmrr_mask.lo);
+ wrmsr(MSR_PRMRR_PHYS_BASE, relo_params->prmrr_base);
+ wrmsr(MSR_PRMRR_PHYS_MASK, relo_params->prmrr_mask);
+}
+
+static inline void write_uncore_prmrr(struct smm_relocation_params *relo_params)
+{
+ printk(BIOS_DEBUG,
+ "Writing UNCORE_PRMRR. base = 0x%08x, mask=0x%08x\n",
+ relo_params->uncore_prmrr_base.lo,
+ relo_params->uncore_prmrr_mask.lo);
+ wrmsr(MSR_UNCORE_PRMRR_PHYS_BASE, relo_params->uncore_prmrr_base);
+ wrmsr(MSR_UNCORE_PRMRR_PHYS_MASK, relo_params->uncore_prmrr_mask);
+}
+
+#endif
diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c
index 9fbcc07..e834142 100644
--- a/src/soc/intel/apollolake/cpu.c
+++ b/src/soc/intel/apollolake/cpu.c
@@ -31,6 +31,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/smm.h>
#include <cpu/intel/em64t100_save_state.h>
+#include <cpu/intel/smm_reloc.h>
#include <device/device.h>
#include <device/pci.h>
#include <fsp/api.h>
diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c
index d25a740..05d7a82 100644
--- a/src/soc/intel/baytrail/cpu.c
+++ b/src/soc/intel/baytrail/cpu.c
@@ -26,6 +26,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/smm.h>
#include <cpu/intel/em64t100_save_state.h>
+#include <cpu/intel/smm_reloc.h>
#include <reg_script.h>
#include <soc/iosf.h>
diff --git a/src/soc/intel/broadwell/include/soc/smm.h b/src/soc/intel/broadwell/include/soc/smm.h
index 9ad3128..08c1ad8 100644
--- a/src/soc/intel/broadwell/include/soc/smm.h
+++ b/src/soc/intel/broadwell/include/soc/smm.h
@@ -25,20 +25,6 @@
u8 reserved[34];
} __packed;
-struct smm_relocation_params {
- uintptr_t ied_base;
- size_t ied_size;
- msr_t smrr_base;
- msr_t smrr_mask;
- msr_t prmrr_base;
- msr_t prmrr_mask;
- msr_t uncore_prmrr_base;
- msr_t uncore_prmrr_mask;
- /* The smm_save_state_in_msrs field indicates if SMM save state
- * locations live in MSRs. This indicates to the CPUs how to adjust
- * the SMMBASE and IEDBASE */
- int smm_save_state_in_msrs;
-};
void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
uintptr_t staggered_smbase);
diff --git a/src/soc/intel/broadwell/smmrelocate.c b/src/soc/intel/broadwell/smmrelocate.c
index 2cf97e3..5cac560 100644
--- a/src/soc/intel/broadwell/smmrelocate.c
+++ b/src/soc/intel/broadwell/smmrelocate.c
@@ -25,6 +25,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/smm.h>
#include <cpu/intel/em64t101_save_state.h>
+#include <cpu/intel/smm_reloc.h>
#include <console/console.h>
#include <soc/cpu.h>
#include <soc/msr.h>
@@ -33,33 +34,8 @@
#include <soc/systemagent.h>
/* This gets filled in and used during relocation. */
-static struct smm_relocation_params smm_reloc_params;
+struct smm_relocation_params smm_reloc_params;
-static inline void write_smrr(struct smm_relocation_params *relo_params)
-{
- printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
- relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
- wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base);
- wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask);
-}
-
-static inline void write_prmrr(struct smm_relocation_params *relo_params)
-{
- printk(BIOS_DEBUG, "Writing PRMRR. base = 0x%08x, mask=0x%08x\n",
- relo_params->prmrr_base.lo, relo_params->prmrr_mask.lo);
- wrmsr(MSR_PRMRR_PHYS_BASE, relo_params->prmrr_base);
- wrmsr(MSR_PRMRR_PHYS_MASK, relo_params->prmrr_mask);
-}
-
-static inline void write_uncore_prmrr(struct smm_relocation_params *relo_params)
-{
- printk(BIOS_DEBUG,
- "Writing UNCORE_PRMRR. base = 0x%08x, mask=0x%08x\n",
- relo_params->uncore_prmrr_base.lo,
- relo_params->uncore_prmrr_mask.lo);
- wrmsr(MSR_UNCORE_PRMRR_PHYS_BASE, relo_params->uncore_prmrr_base);
- wrmsr(MSR_UNCORE_PRMRR_PHYS_MASK, relo_params->uncore_prmrr_mask);
-}
static void update_save_state(int cpu, uintptr_t curr_smbase,
uintptr_t staggered_smbase,
diff --git a/src/soc/intel/cannonlake/include/soc/smm.h b/src/soc/intel/cannonlake/include/soc/smm.h
index ed8cbef..3c1f35c 100644
--- a/src/soc/intel/cannonlake/include/soc/smm.h
+++ b/src/soc/intel/cannonlake/include/soc/smm.h
@@ -28,19 +28,6 @@
u8 reserved[34];
} __packed;
-struct smm_relocation_params {
- uintptr_t ied_base;
- size_t ied_size;
- msr_t smrr_base;
- msr_t smrr_mask;
- /*
- * The smm_save_state_in_msrs field indicates if SMM save state
- * locations live in MSRs. This indicates to the CPUs how to adjust
- * the SMMBASE and IEDBASE
- */
- int smm_save_state_in_msrs;
-};
-
/* Mainboard handler for eSPI SMIs */
void mainboard_smi_espi_handler(void);
diff --git a/src/soc/intel/cannonlake/smmrelocate.c b/src/soc/intel/cannonlake/smmrelocate.c
index 3da1a56..a552b58 100644
--- a/src/soc/intel/cannonlake/smmrelocate.c
+++ b/src/soc/intel/cannonlake/smmrelocate.c
@@ -27,6 +27,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/smm.h>
#include <cpu/intel/em64t101_save_state.h>
+#include <cpu/intel/smm_reloc.h>
#include <console/console.h>
#include <intelblocks/smm.h>
#include <soc/cpu.h>
@@ -37,15 +38,8 @@
#include "chip.h"
/* This gets filled in and used during relocation. */
-static struct smm_relocation_params smm_reloc_params;
+struct smm_relocation_params smm_reloc_params;
-static inline void write_smrr(struct smm_relocation_params *relo_params)
-{
- printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
- relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
- wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base);
- wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask);
-}
static void update_save_state(int cpu, uintptr_t curr_smbase,
uintptr_t staggered_smbase,
diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc
index 22d350c..b5d45bb 100644
--- a/src/soc/intel/common/Makefile.inc
+++ b/src/soc/intel/common/Makefile.inc
@@ -4,6 +4,8 @@
subdirs-y += block/
subdirs-y += pch/
+subdirs-y += ../../../cpu/intel/smm
+
verstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c
bootblock-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c
diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/smm.h b/src/soc/intel/fsp_broadwell_de/include/soc/smm.h
index 3307cb0..3040688 100644
--- a/src/soc/intel/fsp_broadwell_de/include/soc/smm.h
+++ b/src/soc/intel/fsp_broadwell_de/include/soc/smm.h
@@ -26,18 +26,6 @@
u8 reserved[34];
} __packed;
-struct smm_relocation_params {
- uintptr_t ied_base;
- size_t ied_size;
- msr_t smrr_base;
- msr_t smrr_mask;
- msr_t prmrr_base;
- msr_t prmrr_mask;
- /* The smm_save_state_in_msrs field indicates if SMM save state
- locations live in MSRs. This indicates to the CPUs how to adjust
- the SMMBASE and IEDBASE. */
- int smm_save_state_in_msrs;
-};
void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
uintptr_t staggered_smbase);
diff --git a/src/soc/intel/fsp_broadwell_de/smmrelocate.c b/src/soc/intel/fsp_broadwell_de/smmrelocate.c
index 283f5c1..d797438 100644
--- a/src/soc/intel/fsp_broadwell_de/smmrelocate.c
+++ b/src/soc/intel/fsp_broadwell_de/smmrelocate.c
@@ -24,6 +24,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/smm.h>
#include <cpu/intel/em64t101_save_state.h>
+#include <cpu/intel/smm_reloc.h>
#include <console/console.h>
#include <device/pci_ops.h>
#include <soc/lpc.h>
@@ -33,23 +34,8 @@
#include <soc/broadwell_de.h>
/* This gets filled in and used during relocation. */
-static struct smm_relocation_params smm_reloc_params;
+struct smm_relocation_params smm_reloc_params;
-static inline void write_smrr(struct smm_relocation_params *relo_params)
-{
- printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
- relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
- wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base);
- wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask);
-}
-
-static inline void write_prmrr(struct smm_relocation_params *relo_params)
-{
- printk(BIOS_DEBUG, "Writing PRMRR. base = 0x%08x, mask=0x%08x\n",
- relo_params->prmrr_base.lo, relo_params->prmrr_mask.lo);
- wrmsr(MSR_PRMRR_PHYS_BASE, relo_params->prmrr_base);
- wrmsr(MSR_PRMRR_PHYS_MASK, relo_params->prmrr_mask);
-}
static void update_save_state(int cpu, uintptr_t curr_smbase,
uintptr_t staggered_smbase,
diff --git a/src/soc/intel/icelake/include/soc/smm.h b/src/soc/intel/icelake/include/soc/smm.h
index 5d64d3b..b427085 100644
--- a/src/soc/intel/icelake/include/soc/smm.h
+++ b/src/soc/intel/icelake/include/soc/smm.h
@@ -27,18 +27,6 @@
u8 reserved[34];
} __packed;
-struct smm_relocation_params {
- uintptr_t ied_base;
- size_t ied_size;
- msr_t smrr_base;
- msr_t smrr_mask;
- /*
- * The smm_save_state_in_msrs field indicates if SMM save state
- * locations live in MSRs. This indicates to the CPUs how to adjust
- * the SMMBASE and IEDBASE
- */
- int smm_save_state_in_msrs;
-};
/* Mainboard handler for eSPI SMIs */
void mainboard_smi_espi_handler(void);
diff --git a/src/soc/intel/icelake/smmrelocate.c b/src/soc/intel/icelake/smmrelocate.c
index 3e949b2..21b9a13 100644
--- a/src/soc/intel/icelake/smmrelocate.c
+++ b/src/soc/intel/icelake/smmrelocate.c
@@ -26,6 +26,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/smm.h>
#include <cpu/intel/em64t101_save_state.h>
+#include <cpu/intel/smm_reloc.h>
#include <console/console.h>
#include <intelblocks/smm.h>
#include <soc/cpu.h>
@@ -36,15 +37,8 @@
#include <soc/systemagent.h>
/* This gets filled in and used during relocation. */
-static struct smm_relocation_params smm_reloc_params;
+struct smm_relocation_params smm_reloc_params;
-static inline void write_smrr(struct smm_relocation_params *relo_params)
-{
- printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
- relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
- wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base);
- wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask);
-}
static void update_save_state(int cpu, uintptr_t curr_smbase,
uintptr_t staggered_smbase,
diff --git a/src/soc/intel/skylake/include/soc/smm.h b/src/soc/intel/skylake/include/soc/smm.h
index 6eb6b1e..8fa415c 100644
--- a/src/soc/intel/skylake/include/soc/smm.h
+++ b/src/soc/intel/skylake/include/soc/smm.h
@@ -29,18 +29,6 @@
u8 reserved[34];
} __packed;
-struct smm_relocation_params {
- uintptr_t ied_base;
- size_t ied_size;
- msr_t smrr_base;
- msr_t smrr_mask;
- /*
- * The smm_save_state_in_msrs field indicates if SMM save state
- * locations live in MSRs. This indicates to the CPUs how to adjust
- * the SMMBASE and IEDBASE
- */
- int smm_save_state_in_msrs;
-};
void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
uintptr_t staggered_smbase);
diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c
index ebb853a..b80aa14 100644
--- a/src/soc/intel/skylake/smmrelocate.c
+++ b/src/soc/intel/skylake/smmrelocate.c
@@ -26,6 +26,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/smm.h>
#include <cpu/intel/em64t101_save_state.h>
+#include <cpu/intel/smm_reloc.h>
#include <console/console.h>
#include <intelblocks/smm.h>
#include <soc/cpu.h>
@@ -36,15 +37,8 @@
#include "chip.h"
/* This gets filled in and used during relocation. */
-static struct smm_relocation_params smm_reloc_params;
+struct smm_relocation_params smm_reloc_params;
-static inline void write_smrr(struct smm_relocation_params *relo_params)
-{
- printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
- relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
- wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base);
- wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask);
-}
static void update_save_state(int cpu, uintptr_t curr_smbase,
uintptr_t staggered_smbase,
--
To view, visit https://review.coreboot.org/c/coreboot/+/34840
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I39c6cffee95433aea1a3c783b869eedfff094413
Gerrit-Change-Number: 34840
Gerrit-PatchSet: 1
Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Gerrit-MessageType: newchange
by Julius Werner (Code Review)
Hello Aaron Durbin, Frans Hendriks, Philipp Deppenwiese,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/32716
to review the following change.
Change subject: vboot: Turn vboot_logic_executed() into a static inline
......................................................................
vboot: Turn vboot_logic_executed() into a static inline
This patch moves vboot_logic_executed() (and its dependencies) into a
header and turns it into a static inline function. The function is used
to guard larger amounts of code in several places, so this should allow
us to safe some more space through compile-time elimination (and also
makes it easier to avoid undefined reference issues in some cases).
Change-Id: I193f608882cbfe07dc91ee90d02fafbd67a3c324
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
---
M src/security/vboot/misc.h
M src/security/vboot/vboot_loader.c
2 files changed, 58 insertions(+), 54 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/32716/1
diff --git a/src/security/vboot/misc.h b/src/security/vboot/misc.h
index b4fae19..2a0523d 100644
--- a/src/security/vboot/misc.h
+++ b/src/security/vboot/misc.h
@@ -16,6 +16,8 @@
#ifndef __VBOOT_MISC_H__
#define __VBOOT_MISC_H__
+#include <assert.h>
+#include <arch/early_variables.h>
#include <security/vboot/vboot_common.h>
struct vb2_context;
@@ -66,13 +68,63 @@
void vboot_fill_handoff(void);
/*
- * Source: security/vboot/vboot_loader.c
- */
-int vboot_logic_executed(void);
-
-/*
* Source: security/vboot/bootmode.c
*/
void vboot_save_recovery_reason_vbnv(void);
+/*
+ * The stage loading code is compiled and entered from multiple stages. The
+ * helper functions below attempt to provide more clarity on when certain
+ * code should be called. They are implemented inline for better compile-time
+ * code elimination.
+ */
+
+static inline int verification_should_run(void)
+{
+ if (CONFIG(VBOOT_SEPARATE_VERSTAGE))
+ return ENV_VERSTAGE;
+ else if (CONFIG(VBOOT_STARTS_IN_ROMSTAGE))
+ return ENV_ROMSTAGE;
+ else if (CONFIG(VBOOT_STARTS_IN_BOOTBLOCK))
+ return ENV_BOOTBLOCK;
+ else
+ dead_code();
+}
+
+static inline int verstage_should_load(void)
+{
+ if (CONFIG(VBOOT_SEPARATE_VERSTAGE))
+ return ENV_BOOTBLOCK;
+ else
+ return 0;
+}
+
+/* Only for use by functions in this header, do not access directly! */
+extern int vboot_executed;
+
+static inline int vboot_logic_executed(void)
+{
+ /* If we are in the stage that runs verification, or in the stage that
+ both loads the verstage and is returned to from it afterwards, we
+ need to check a global to see if verfication has run. */
+ if (verification_should_run() ||
+ (verstage_should_load() && CONFIG(VBOOT_RETURN_FROM_VERSTAGE)))
+ return car_get_var(vboot_executed);
+
+ if (CONFIG(VBOOT_STARTS_IN_BOOTBLOCK)) {
+ /* All other stages are "after the bootblock" */
+ return !ENV_BOOTBLOCK;
+ } else if (CONFIG(VBOOT_STARTS_IN_ROMSTAGE)) {
+ /* Post-RAM stages are "after the romstage" */
+#ifdef __PRE_RAM__
+ return 0;
+#else
+ return 1;
+#endif
+ } else {
+ dead_code();
+ }
+}
+
+
#endif /* __VBOOT_MISC_H__ */
diff --git a/src/security/vboot/vboot_loader.c b/src/security/vboot/vboot_loader.c
index 3bbb3da..1350307 100644
--- a/src/security/vboot/vboot_loader.c
+++ b/src/security/vboot/vboot_loader.c
@@ -36,55 +36,7 @@
CONFIG(VBOOT_SEPARATE_VERSTAGE),
"return from verstage only makes sense for separate verstages");
-/* The stage loading code is compiled and entered from multiple stages. The
- * helper functions below attempt to provide more clarity on when certain
- * code should be called. */
-
-static int verification_should_run(void)
-{
- if (CONFIG(VBOOT_SEPARATE_VERSTAGE))
- return ENV_VERSTAGE;
- else if (CONFIG(VBOOT_STARTS_IN_ROMSTAGE))
- return ENV_ROMSTAGE;
- else if (CONFIG(VBOOT_STARTS_IN_BOOTBLOCK))
- return ENV_BOOTBLOCK;
- else
- die("impossible!");
-}
-
-static int verstage_should_load(void)
-{
- if (CONFIG(VBOOT_SEPARATE_VERSTAGE))
- return ENV_BOOTBLOCK;
- else
- return 0;
-}
-
-static int vboot_executed CAR_GLOBAL;
-
-int vboot_logic_executed(void)
-{
- /* If we are in the stage that runs verification, or in the stage that
- both loads the verstage and is returned to from it afterwards, we
- need to check a global to see if verfication has run. */
- if (verification_should_run() ||
- (verstage_should_load() && CONFIG(VBOOT_RETURN_FROM_VERSTAGE)))
- return car_get_var(vboot_executed);
-
- if (CONFIG(VBOOT_STARTS_IN_BOOTBLOCK)) {
- /* All other stages are "after the bootblock" */
- return !ENV_BOOTBLOCK;
- } else if (CONFIG(VBOOT_STARTS_IN_ROMSTAGE)) {
- /* Post-RAM stages are "after the romstage" */
-#ifdef __PRE_RAM__
- return 0;
-#else
- return 1;
-#endif
- } else {
- die("impossible!");
- }
-}
+int vboot_executed CAR_GLOBAL;
static void vboot_prepare(void)
{
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I193f608882cbfe07dc91ee90d02fafbd67a3c324
Gerrit-Change-Number: 32716
Gerrit-PatchSet: 1
Gerrit-Owner: Julius Werner <jwerner(a)chromium.org>
Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org>
Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com>
Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org>
Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>
Gerrit-MessageType: newchange
by Patrick Rudolph (Code Review)
Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32705
Change subject: security/lockdown: Write-protect WP_RO
......................................................................
security/lockdown: Write-protect WP_RO
Add another choice to boot media protection and write-protect WP_RO
in case VBOOT is enabled.
Tested on Lenovo T520:
The WP_RO region is write-protected.
Change-Id: I72c3e1a0720514b9b85b0433944ab5fb7109b2a2
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/security/lockdown/Kconfig
M src/security/lockdown/bootmedia.c
2 files changed, 29 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/32705/1
diff --git a/src/security/lockdown/Kconfig b/src/security/lockdown/Kconfig
index bb4d072..1e982d8 100644
--- a/src/security/lockdown/Kconfig
+++ b/src/security/lockdown/Kconfig
@@ -15,6 +15,18 @@
config BOOTMEDIA_LOCK_NONE
bool "Don't lock boot media sections"
+config BOOTMEDIA_LOCK_VBOOT_RO
+ bool "Write-protect WP_RO region in boot media"
+ depends on VBOOT
+ help
+ Select this if you want to write-protect the WP_RO region as specified
+ in the VBOOT FMAP. You will only be able to write the regions
+ FW_MAIN_A/FW_MAIN_B, which are not write-protected using the internal
+ programmer.
+ The locking will take place during the chipset lockdown, which
+ is either triggered by coreboot (when INTEL_CHIPSET_LOCKDOWN is set)
+ or has to be triggered later (e.g. by the payload or the OS).
+
config BOOTMEDIA_LOCK_RO
bool "Write-protect the whole boot media"
help
diff --git a/src/security/lockdown/bootmedia.c b/src/security/lockdown/bootmedia.c
index 8fb4ae9..6fa2de2 100644
--- a/src/security/lockdown/bootmedia.c
+++ b/src/security/lockdown/bootmedia.c
@@ -17,6 +17,7 @@
#include <commonlib/region.h>
#include <console/console.h>
#include <bootstate.h>
+#include <fmap.h>
/*
* Enable write protection on the WP_RO region of the bootmedia.
@@ -47,8 +48,23 @@
"of whole bootmedia\n");
locked = true;
}
- }
+ } else if (CONFIG(BOOTMEDIA_LOCK_VBOOT_RO)) {
+ struct region_device dev;
+ if (fmap_locate_area_as_rdev("WP_RO", &dev) < 0) {
+ printk(BIOS_ERR, "BM-LOCKDOWN: Could not find region 'WP_RO'\n");
+ } else {
+ for (size_t i = 0; i < ARRAY_SIZE(wp_prot); i++) {
+ printk(BIOS_DEBUG, "BM-LOCKDOWN: Trying write-protection"
+ "#%zu ...\n", i);
+ if (boot_device_wp_region(&dev, wp_prot[i]) < 0)
+ continue;
+ printk(BIOS_INFO, "BM-LOCKDOWN: Enabled write-protection of"
+ "WP_RO region\n");
+ locked = true;
+ }
+ }
+ }
if (!locked)
printk(BIOS_INFO, "BM-LOCKDOWN: Didn't enable bootmedia protection\n");
}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I72c3e1a0720514b9b85b0433944ab5fb7109b2a2
Gerrit-Change-Number: 32705
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Gerrit-MessageType: newchange
by Frans Hendriks (Code Review)
Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34448 )
Change subject: mainboard/facebook/fbg1701: Add IFD and ME binary
......................................................................
mainboard/facebook/fbg1701: Add IFD and ME binary
Use IFD and ME binary to generate complete SPI image
BUG=N/A
TEST=Boot Embedded Linux 4.20 on Facebook FBG-1701
Change-Id: I9370bf9f2bba8887988bc6484524f6cf53bed8db
Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com>
---
M src/mainboard/facebook/fbg1701/Kconfig
1 file changed, 10 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/34448/1
diff --git a/src/mainboard/facebook/fbg1701/Kconfig b/src/mainboard/facebook/fbg1701/Kconfig
index 95d8f6c..dce315e 100644
--- a/src/mainboard/facebook/fbg1701/Kconfig
+++ b/src/mainboard/facebook/fbg1701/Kconfig
@@ -19,6 +19,8 @@
def_bool y
select BOARD_ROMSIZE_KB_8192
select HAVE_ACPI_TABLES
+ select HAVE_IFD_BIN
+ select HAVE_ME_BIN
select HAVE_OPTION_TABLE
select MAINBOARD_HAS_LPC_TPM
select MAINBOARD_HAS_TPM2
@@ -94,4 +96,12 @@
hex "C Bootblock Size"
default 0x4000
+config IFD_BIN_PATH
+ string
+ default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin"
+
+config ME_BIN_PATH
+ string
+ default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin"
+
endif # BOARD_FACEBOOK_FBG1701
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I9370bf9f2bba8887988bc6484524f6cf53bed8db
Gerrit-Change-Number: 34448
Gerrit-PatchSet: 1
Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com>
Gerrit-MessageType: newchange
by Frans Hendriks (Code Review)
Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34442 )
Change subject: 3rdparty/blobs: Add Facebook FBG1701 descriptor and Intel ME
......................................................................
3rdparty/blobs: Add Facebook FBG1701 descriptor and Intel ME
Upgrade to blobs version with descriptor and Intel ME binary
BUG=N/A
TEST=booting Facebook FBG1701
Change-Id: I2143b94a81eebfb22d99833aaf1f3743983dd80c
Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com>
---
M 3rdparty/blobs
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/34442/1
diff --git a/3rdparty/blobs b/3rdparty/blobs
index d7600dd..c7dc4f2 160000
--- a/3rdparty/blobs
+++ b/3rdparty/blobs
@@ -1 +1 @@
-Subproject commit d7600dd8718a076f0f9a89e53968b484254624dc
+Subproject commit c7dc4f25229fd3c022afdb410264b02f292ddca6
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I2143b94a81eebfb22d99833aaf1f3743983dd80c
Gerrit-Change-Number: 34442
Gerrit-PatchSet: 1
Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com>
Gerrit-MessageType: newchange
by Kyösti Mälkki (Code Review)
Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31489
Change subject: [WIP] soc/amd/common: Use static allocation for params
......................................................................
[WIP] soc/amd/common: Use static allocation for params
Lifetime of the structure is the duration of call to
AGESA. There is no need to allocate and release these
from AGESA's internal heap for every single call.
Change-Id: Ibef6ca8481f926d4e18e1aef5136e69f5834feb1
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/soc/amd/common/block/pi/agesawrapper.c
1 file changed, 22 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/31489/1
diff --git a/src/soc/amd/common/block/pi/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c
index 821535d..e769a45 100644
--- a/src/soc/amd/common/block/pi/agesawrapper.c
+++ b/src/soc/amd/common/block/pi/agesawrapper.c
@@ -410,6 +410,26 @@
}
+union AMD_MAX_ALLOC_PARAMS {
+ AMD_INTERFACE_PARAMS p1;
+ AMD_RESET_PARAMS p2;
+ AMD_EARLY_PARAMS p3;
+ AMD_POST_PARAMS p4;
+ AMD_RESUME_PARAMS p5;
+ AMD_ENV_PARAMS p6;
+ AMD_MID_PARAMS p7;
+ AMD_LATE_PARAMS p8;
+#if 1
+ AMD_RTB_PARAMS p9;
+#else
+ AMD_S3SAVE_PARAMS p10;
+#endif
+ AMD_S3LATE_PARAMS p11;
+ AMD_S3FINAL_PARAMS p12;
+};
+
+static union AMD_MAX_ALLOC_PARAMS sp;
+
AGESA_STATUS agesa_execute_state(AGESA_STRUCT_NAME func)
{
AGESA_STATUS status = AGESA_UNSUPPORTED;
@@ -417,19 +437,9 @@
AMD_CONFIG_PARAMS *StdHeader = &template;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_INTERFACE_PARAMS *aip = &AmdParamStruct;
- union {
- AMD_RESET_PARAMS ResetParams;
- AMD_S3LATE_PARAMS S3LateParams;
- AMD_S3FINAL_PARAMS S3FinalParams;
- } sp;
- if ((func == AMD_INIT_RESET) || (func == AMD_S3LATE_RESTORE) ||
- (func == AMD_S3FINAL_RESTORE)) {
- memset(&sp, 0, sizeof(sp));
- amd_create_struct(aip, func, &sp, sizeof(sp));
- } else {
- amd_create_struct(aip, func, NULL, 0);
- }
+ memset(&sp, 0, sizeof(sp));
+ amd_create_struct(aip, func, &sp, sizeof(sp));
StdHeader = aip->NewStructPtr;
StdHeader->Func = func;
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ibef6ca8481f926d4e18e1aef5136e69f5834feb1
Gerrit-Change-Number: 31489
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Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Gerrit-MessageType: newchange
by Kyösti Mälkki (Code Review)
Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34883 )
Change subject: [WIP] amd/stoneyridge: Fix CAR stack location
......................................................................
[WIP] amd/stoneyridge: Fix CAR stack location
As far as I can see, for BSP, gcccar.inc exits with
%esp at _car_region_end, not _car_stack_end.
On exit from ENABLE_AMD_STACK, %esp will have value
of DCACHE_RAM_BASE + DCACHE_RAM_SIZE. This was correct
for the stack placement with C_ENVIRONMENT_BOOTBLOCK=n.
It would be nice if AMD code had guards so we knew how
much stack it needs. Setting of DCACHE_BSP_STACK_SIZE
works with inverse logic now, the higher you set it,
the less space is where the stack is located. This
raises the question how its size was determined.
00030000 B _car_region_start
00030000 B _car_stack_start
00034000 B _car_stack_end
00034000 B _preram_cbmem_console
00035600 B _car_relocatable_data_start
00035850 B _car_global_start
00035860 B _car_global_end
00035860 B _car_relocatable_data_end
00040000 B _car_region_end
Use the symbol _car_stack_end to have early stage use
the location assigned by the linker script car.ld.
Change-Id: Id91393f1e7faf86b01fdc113e7940893673a27a7
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/drivers/amd/agesa/cache_as_ram.S
M src/soc/amd/common/block/cpu/car/cache_as_ram.S
2 files changed, 12 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/34883/1
diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S
index 4f0bb3f..c23939c 100644
--- a/src/drivers/amd/agesa/cache_as_ram.S
+++ b/src/drivers/amd/agesa/cache_as_ram.S
@@ -31,6 +31,8 @@
.globl _cache_as_ram_setup, _cache_as_ram_setup_end
.globl chipset_teardown_car
+#if ENV_ROMSTAGE
+
_cache_as_ram_setup:
/* Preserve BIST. */
@@ -49,6 +51,10 @@
AMD_ENABLE_STACK
+ /* Let arch/x86/car.ld determine our stack location.
+ * FIXME: Only do this for BSP. !! */
+ movl $_car_stack_end, %esp
+
/* Align the stack. */
and $0xFFFFFFF0, %esp
@@ -107,6 +113,8 @@
pushl %eax
call romstage_main
+#endif /* ENV_ROMSTAGE */
+
#if CONFIG(POSTCAR_STAGE)
/* We do not return. Execution continues with run_postcar_phase()
diff --git a/src/soc/amd/common/block/cpu/car/cache_as_ram.S b/src/soc/amd/common/block/cpu/car/cache_as_ram.S
index 402da3a..ad0ea53 100644
--- a/src/soc/amd/common/block/cpu/car/cache_as_ram.S
+++ b/src/soc/amd/common/block/cpu/car/cache_as_ram.S
@@ -38,6 +38,10 @@
AMD_ENABLE_STACK
+ /* Let arch/x86/car.ld determine our stack location.
+ * FIXME: Only do this for BSP. !! */
+ movl $_car_stack_end, %esp
+
/* Align the stack and keep aligned for call to bootblock_c_entry() */
and $0xfffffff0, %esp
sub $8, %esp
--
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Gerrit-Change-Id: Id91393f1e7faf86b01fdc113e7940893673a27a7
Gerrit-Change-Number: 34883
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Gerrit-MessageType: newchange
by Kyösti Mälkki (Code Review)
Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34152 )
Change subject: cpu/x86: Move some PARALLEL_MP prototypes
......................................................................
cpu/x86: Move some PARALLEL_MP prototypes
The implementations live inside platform directories,
but the function signatures must match those defined
by PARALLEL_MP implementation.
Change-Id: If05ee2e44504e5511f3a7a2c5dc6e48fc16a07b2
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/cpu/intel/haswell/haswell.h
M src/cpu/intel/smm/gen1/smi.h
M src/include/cpu/x86/mp.h
M src/soc/intel/broadwell/include/soc/smm.h
M src/soc/intel/cannonlake/include/soc/smm.h
M src/soc/intel/fsp_broadwell_de/include/soc/smm.h
M src/soc/intel/icelake/include/soc/smm.h
M src/soc/intel/skylake/include/soc/smm.h
8 files changed, 7 insertions(+), 49 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/34152/1
diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h
index cd8d5cb..2c52caf 100644
--- a/src/cpu/intel/haswell/haswell.h
+++ b/src/cpu/intel/haswell/haswell.h
@@ -160,13 +160,6 @@
/* Configure power limits for turbo mode */
void set_power_limits(u8 power_limit_1_time);
int cpu_config_tdp_levels(void);
-void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
- uintptr_t staggered_smbase);
-void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
- size_t *smm_save_state_size);
-void smm_initialize(void);
-void smm_relocate(void);
-void smm_lock(void);
struct bus;
void bsp_init_and_start_aps(struct bus *cpu_bus);
/* Determine if HyperThreading is disabled. The variable is not valid until
diff --git a/src/cpu/intel/smm/gen1/smi.h b/src/cpu/intel/smm/gen1/smi.h
index 3d5149a..4c80230 100644
--- a/src/cpu/intel/smm/gen1/smi.h
+++ b/src/cpu/intel/smm/gen1/smi.h
@@ -24,11 +24,4 @@
bool cpu_has_alternative_smrr(void);
/* parallel MP helper functions */
-void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
- size_t *smm_save_state_size);
-void smm_initialize(void);
void southbridge_smm_clear_state(void);
-void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
- uintptr_t staggered_smbase);
-void smm_relocate(void);
-void smm_lock(void);
diff --git a/src/include/cpu/x86/mp.h b/src/include/cpu/x86/mp.h
index c04252e..05f2471 100644
--- a/src/include/cpu/x86/mp.h
+++ b/src/include/cpu/x86/mp.h
@@ -154,4 +154,11 @@
/* Send SMI to self with single execution. */
void smm_initiate_relocation(void);
+/* Parallel MP helper functions. */
+void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size);
+void smm_initialize(void);
+void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase);
+void smm_relocate(void);
+void smm_lock(void);
+
#endif /* _X86_MP_H_ */
diff --git a/src/soc/intel/broadwell/include/soc/smm.h b/src/soc/intel/broadwell/include/soc/smm.h
index d3e1cdd..fe38dc9 100644
--- a/src/soc/intel/broadwell/include/soc/smm.h
+++ b/src/soc/intel/broadwell/include/soc/smm.h
@@ -53,13 +53,6 @@
return CONFIG_SMM_TSEG_SIZE;
}
-void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
- uintptr_t staggered_smbase);
-void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
- size_t *smm_save_state_size);
-void smm_initialize(void);
-void smm_relocate(void);
-void smm_lock(void);
/* These helpers are for performing SMM relocation. */
void southbridge_trigger_smi(void);
diff --git a/src/soc/intel/cannonlake/include/soc/smm.h b/src/soc/intel/cannonlake/include/soc/smm.h
index c0ab82f..5cf7407 100644
--- a/src/soc/intel/cannonlake/include/soc/smm.h
+++ b/src/soc/intel/cannonlake/include/soc/smm.h
@@ -50,12 +50,5 @@
/* Mainboard handler for eSPI SMIs */
void mainboard_smi_espi_handler(void);
-void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
- uintptr_t staggered_smbase);
-void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
- size_t *smm_save_state_size);
-void smm_initialize(void);
-void smm_relocate(void);
-void smm_lock(void);
#endif
diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/smm.h b/src/soc/intel/fsp_broadwell_de/include/soc/smm.h
index 72aa7fa..a3400ff 100644
--- a/src/soc/intel/fsp_broadwell_de/include/soc/smm.h
+++ b/src/soc/intel/fsp_broadwell_de/include/soc/smm.h
@@ -54,13 +54,6 @@
return CONFIG_SMM_TSEG_SIZE;
}
-void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
- uintptr_t staggered_smbase);
-void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
- size_t *smm_save_state_size);
-void smm_initialize(void);
-void smm_relocate(void);
-void smm_lock(void);
/* These helpers are for performing SMM relocation. */
void southbridge_trigger_smi(void);
diff --git a/src/soc/intel/icelake/include/soc/smm.h b/src/soc/intel/icelake/include/soc/smm.h
index 991c593..9777599 100644
--- a/src/soc/intel/icelake/include/soc/smm.h
+++ b/src/soc/intel/icelake/include/soc/smm.h
@@ -49,12 +49,5 @@
/* Mainboard handler for eSPI SMIs */
void mainboard_smi_espi_handler(void);
-void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
- uintptr_t staggered_smbase);
-void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
- size_t *smm_save_state_size);
-void smm_initialize(void);
-void smm_relocate(void);
-void smm_lock(void);
#endif
diff --git a/src/soc/intel/skylake/include/soc/smm.h b/src/soc/intel/skylake/include/soc/smm.h
index 0c5e976..4dfa627 100644
--- a/src/soc/intel/skylake/include/soc/smm.h
+++ b/src/soc/intel/skylake/include/soc/smm.h
@@ -48,12 +48,5 @@
int smm_save_state_in_msrs;
};
-void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
- uintptr_t staggered_smbase);
-void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
- size_t *smm_save_state_size);
-void smm_initialize(void);
-void smm_relocate(void);
-void smm_lock(void);
#endif
--
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Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
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by Kyösti Mälkki (Code Review)
Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30704
Change subject: device/hypertransport: Drop dev_find_slot() debugging
......................................................................
device/hypertransport: Drop dev_find_slot() debugging
Change-Id: I810ca9cfc72de9ea532d53cabdaf8845be837432
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/device/device.c
M src/device/device_const.c
M src/include/device/device.h
3 files changed, 5 insertions(+), 32 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/30704/1
diff --git a/src/device/device.c b/src/device/device.c
index 20a4077..7836af1 100644
--- a/src/device/device.c
+++ b/src/device/device.c
@@ -1253,7 +1253,4 @@
final_link(link);
printk(BIOS_INFO, "Devices finalized\n");
-
- if (IS_ENABLED(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT))
- ht_report_devtree_sanity();
}
diff --git a/src/device/device_const.c b/src/device/device_const.c
index 480ac76..cdae33d 100644
--- a/src/device/device_const.c
+++ b/src/device/device_const.c
@@ -177,15 +177,6 @@
* Work around the devicetree topology being manipulated on-the-fly
* on systems with HyperTransport Support.
*/
-
-static int ht_tree_needs_fixing, ht_tree_fixup_failed;
-
-void ht_report_devtree_sanity(void)
-{
- printk(BIOS_INFO, "HT fixup counters %d / %d (rqrd/failed)\n",
- ht_tree_needs_fixing, ht_tree_fixup_failed);
-}
-
static const struct bus *ht_bus_reloc(const struct bus *parent,
pci_devfn_t devfn)
{
@@ -222,34 +213,20 @@
DEVTREE_CONST struct device *pcidev_path_on_root(pci_devfn_t devfn)
{
- DEVTREE_CONST struct device *dev;
DEVTREE_CONST struct device *pci_domain;
+ const struct bus *root;
pci_domain = dev_find_path(NULL, DEVICE_PATH_DOMAIN);
if (!pci_domain)
return NULL;
- dev = pcidev_path_behind(pci_domain->link_list, devfn);
+ root = pci_domain->link_list;
/* Static devicetree with HyperTransport has whacky topology. */
- if (!IS_ENABLED(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT))
- return dev;
+ if (IS_ENABLED(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT))
+ root = ht_bus_reloc(root, devfn);
- DEVTREE_CONST struct device *dev_fixup, *dev_old_method;
-
- const struct bus *root = ht_bus_reloc(pci_domain->link_list, devfn);
- dev_fixup = pcidev_path_behind(root, devfn);
- dev_old_method = dev_find_slot(0, devfn);
-
- if (ENV_RAMSTAGE) {
- if (dev != dev_old_method)
- ht_tree_needs_fixing++;
-
- if (dev_fixup != dev_old_method)
- ht_tree_fixup_failed++;
- }
-
- return dev_old_method;
+ return pcidev_path_behind(root, devfn);
}
DEVTREE_CONST struct device *pcidev_on_root(uint8_t dev, uint8_t fn)
diff --git a/src/include/device/device.h b/src/include/device/device.h
index 40a0f58..540b7e3 100644
--- a/src/include/device/device.h
+++ b/src/include/device/device.h
@@ -227,7 +227,6 @@
void show_one_resource(int debug_level, struct device *dev,
struct resource *resource, const char *comment);
void show_all_devs_resources(int debug_level, const char *msg);
-void ht_report_devtree_sanity(void);
/* Rounding for boundaries.
* Due to some chip bugs, go ahead and round IO to 16
--
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