coreboot-gerrit June 2022

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Change in coreboot[master]: AMD good IRQs: scripts for applying the unofficial (not-merged-yet) p...
by Mike Banon (Code Review) 29 Nov '22

29 Nov '22

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48427 ) Change subject: AMD good IRQs: scripts for applying the unofficial (not-merged-yet) patches ...................................................................... AMD good IRQs: scripts for applying the unofficial (not-merged-yet) patches These scripts will help you to securely and conveniently apply seven changes for improving the IRQ routing on these AMD boards: 1) CB:48161, CB:48162, CB:48163, CB:48179 - for AMD Lenovo G505S; 2) CB:48424, CB:48425, CB:48426 - for ASUS A88XM-E; 3) Not ready yet - for ASUS AM1I-A. Save to ./coreboot/ then run ./get_irq_patches.sh , ./check... and ./apply... Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I04869ae24185eef5399c3fd9b8d4965ec4e33a19 --- A apply_irq_patches.sh A check_irq_patches.sh A get_irq_patches.sh A sha256sums_irq_correct.txt 4 files changed, 113 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/48427/1 diff --git a/apply_irq_patches.sh b/apply_irq_patches.sh new file mode 100755 index 0000000..8fc5318 --- /dev/null +++ b/apply_irq_patches.sh @@ -0,0 +1,37 @@ +#!/bin/sh +### +### https://review.coreboot.org/c/coreboot/+/48161 +### lenovo/g505s: properly program the IRQ tables +### +patch -p1 < "./cd096f9.diff" +### +### https://review.coreboot.org/c/coreboot/+/48162 +### lenovo/g505s: update the ACPI routing to match the new IRQ routing +### +patch -p1 < "./42aeed4.diff" +### +### https://review.coreboot.org/c/coreboot/+/48163 +### lenovo/g505s: add the PIRQ routing table +### +patch -p1 < "./c6ab05e.diff" +### +### https://review.coreboot.org/c/coreboot/+/48179 +### lenovo/g505s: enable the webcam [WIP] +### +patch -p1 < "./8517e5a.diff" +### +### https://review.coreboot.org/c/coreboot/+/48424 +### asus/a88xm-e: properly program the IRQ tables +### +patch -p1 < "./cfc8288.diff" +### +### https://review.coreboot.org/c/coreboot/+/48425 +### asus/a88xm-e: update the ACPI routing to match the new IRQ routing +### +patch -p1 < "./489e510.diff" +### +### https://review.coreboot.org/c/coreboot/+/48426 +### asus/a88xm-e: add the PIRQ routing table +### +patch -p1 < "./08638df.diff" +### diff --git a/check_irq_patches.sh b/check_irq_patches.sh new file mode 100755 index 0000000..3a2bb16 --- /dev/null +++ b/check_irq_patches.sh @@ -0,0 +1,18 @@ +#!/bin/sh +rm -f "./sha256sums_irq_my.txt" +sha256sum "./cd096f9.diff" > "./sha256sums_irq_my.txt" +sha256sum "./42aeed4.diff" >> "./sha256sums_irq_my.txt" +sha256sum "./c6ab05e.diff" >> "./sha256sums_irq_my.txt" +sha256sum "./8517e5a.diff" >> "./sha256sums_irq_my.txt" +sha256sum "./cfc8288.diff" >> "./sha256sums_irq_my.txt" +sha256sum "./489e510.diff" >> "./sha256sums_irq_my.txt" +sha256sum "./08638df.diff" >> "./sha256sums_irq_my.txt" +if cmp -s "./sha256sums_irq_my.txt" "./sha256sums_irq_correct.txt" +then + echo "SHA256 checksums are correct, please run ./apply_irq_patches.sh" + exit 0 +else + echo "! MISMATCH ! See ./sha256sums_irq_my.txt and ./sha256sums_irq_correct.txt" + exit 1 +fi +# diff --git a/get_irq_patches.sh b/get_irq_patches.sh new file mode 100755 index 0000000..97da6b5 --- /dev/null +++ b/get_irq_patches.sh @@ -0,0 +1,51 @@ +#!/bin/sh +### +### https://review.coreboot.org/c/coreboot/+/48161 +### lenovo/g505s: properly program the IRQ tables +### +rm -f "./cd096f9.diff" +wget "https://review.coreboot.org/changes/48161/revisions/1/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./cd096f9.diff" +### +### https://review.coreboot.org/c/coreboot/+/48162 +### lenovo/g505s: update the ACPI routing to match the new IRQ routing +### +rm -f "./42aeed4.diff" +wget "https://review.coreboot.org/changes/48162/revisions/1/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./42aeed4.diff" +### +### https://review.coreboot.org/c/coreboot/+/48163 +### lenovo/g505s: add the PIRQ routing table +### +rm -f "./c6ab05e.diff" +wget "https://review.coreboot.org/changes/48163/revisions/3/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./c6ab05e.diff" +### +### https://review.coreboot.org/c/coreboot/+/48179 +### lenovo/g505s: enable the webcam [WIP] +### +rm -f "./8517e5a.diff" +wget "https://review.coreboot.org/changes/48179/revisions/1/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./8517e5a.diff" +### +### https://review.coreboot.org/c/coreboot/+/48424 +### asus/a88xm-e: properly program the IRQ tables +### +rm -f "./cfc8288.diff" +wget "https://review.coreboot.org/changes/48424/revisions/1/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./cfc8288.diff" +### +### https://review.coreboot.org/c/coreboot/+/48425 +### asus/a88xm-e: update the ACPI routing to match the new IRQ routing +### +rm -f "./489e510.diff" +wget "https://review.coreboot.org/changes/48425/revisions/1/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./489e510.diff" +### +### https://review.coreboot.org/c/coreboot/+/48426 +### asus/a88xm-e: add the PIRQ routing table +### +rm -f "./08638df.diff" +wget "https://review.coreboot.org/changes/48426/revisions/1/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./08638df.diff" +### diff --git a/sha256sums_irq_correct.txt b/sha256sums_irq_correct.txt new file mode 100755 index 0000000..a06b640 --- /dev/null +++ b/sha256sums_irq_correct.txt @@ -0,0 +1,7 @@ +9fd4cca063bb6e6c9063f00f4c972c019d616560883b9bda76177a462817ae8e ./cd096f9.diff +357a1e1e9f250149127fa8f7aac089e481a39f96b313ae1a0310c7e5d22faa72 ./42aeed4.diff +e350591056f1a10b5922cc7180a07e1142f14fe8af41f6c545317a37c12880ed ./c6ab05e.diff +ab0b347af164e5c50c580f036e7ed55757e90158ad3cb04fc2f8154b5392f804 ./8517e5a.diff +358c3a5fcce7085ca49154370c21cd95396fa8fa9d0b30e1de8625fe1db0f36d ./cfc8288.diff +669bd10d74229f3e2200a9e206fad49326928348a6ad3f261f14ebe920b63c56 ./489e510.diff +fab791e93eb63b880d2692eff527979051dadcf504018f58346c6f0c4c6173b6 ./08638df.diff -- To view, visit https://review.coreboot.org/c/coreboot/+/48427 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I04869ae24185eef5399c3fd9b8d4965ec4e33a19 Gerrit-Change-Number: 48427 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

3 13

Change in coreboot[master]: Disable SeaBIOS options unsupported by hardware: scripts to apply the...
by Mike Banon (Code Review) 29 Nov '22

29 Nov '22

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44638 ) Change subject: Disable SeaBIOS options unsupported by hardware: scripts to apply the patches ...................................................................... Disable SeaBIOS options unsupported by hardware: scripts to apply the patches These scripts will help you to securely and conveniently apply CB:44636 and CB:44637 to disable SeaBIOS options unsupported by ASUS AM1I-A and ASUS A88XM-E. Save to ./coreboot/ then run ./get_cfgsb_patches.sh , ./check... and ./apply... https://review.coreboot.org/c/coreboot/+/44636 mb/asus/am1i-a: Disable SeaBIOS options unsupported by hardware https://review.coreboot.org/c/coreboot/+/44637 mb/asus/a88xm-e: Disable SeaBIOS options unsupported by hardware Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I8baaca0d58b863a7084b8672fb9574ebb5e72591 --- A apply_cfgsb_patches.sh A check_cfgsb_patches.sh A get_cfgsb_patches.sh A sha256sums_cfgsb_correct.txt 4 files changed, 43 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/44638/1 diff --git a/apply_cfgsb_patches.sh b/apply_cfgsb_patches.sh new file mode 100755 index 0000000..657211e --- /dev/null +++ b/apply_cfgsb_patches.sh @@ -0,0 +1,12 @@ +#!/bin/sh +### +### https://review.coreboot.org/c/coreboot/+/44636 +### mb/asus/am1i-a: Disable SeaBIOS options unsupported by hardware +### +patch -p1 < "./f4b8121.diff" +### +### https://review.coreboot.org/c/coreboot/+/44637 +### mb/asus/a88xm-e: Disable SeaBIOS options unsupported by hardware +### +patch -p1 < "./4f95dab.diff" +### diff --git a/check_cfgsb_patches.sh b/check_cfgsb_patches.sh new file mode 100755 index 0000000..87f2bac --- /dev/null +++ b/check_cfgsb_patches.sh @@ -0,0 +1,13 @@ +#!/bin/sh +rm -f "./sha256sums_cfgsb_my.txt" +sha256sum "./f4b8121.diff" > "./sha256sums_cfgsb_my.txt" +sha256sum "./4f95dab.diff" >> "./sha256sums_cfgsb_my.txt" +if cmp -s "./sha256sums_cfgsb_my.txt" "./sha256sums_cfgsb_correct.txt" +then + echo "SHA256 checksums are correct, please run ./apply_cfgsb_patches.sh" + exit 0 +else + echo "! MISMATCH ! See ./sha256sums_cfgsb_my.txt and ./sha256sums_cfgsb_correct.txt" + exit 1 +fi +# diff --git a/get_cfgsb_patches.sh b/get_cfgsb_patches.sh new file mode 100755 index 0000000..8070382 --- /dev/null +++ b/get_cfgsb_patches.sh @@ -0,0 +1,16 @@ +#!/bin/sh +### +### https://review.coreboot.org/c/coreboot/+/44636 +### mb/asus/am1i-a: Disable SeaBIOS options unsupported by hardware +### +rm -f "./f4b8121.diff" +wget "https://review.coreboot.org/changes/44636/revisions/1/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./f4b8121.diff" +### +### https://review.coreboot.org/c/coreboot/+/44637 +### mb/asus/a88xm-e: Disable SeaBIOS options unsupported by hardware +### +rm -f "./4f95dab.diff" +wget "https://review.coreboot.org/changes/44637/revisions/1/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./4f95dab.diff" +### diff --git a/sha256sums_cfgsb_correct.txt b/sha256sums_cfgsb_correct.txt new file mode 100644 index 0000000..afe90bc --- /dev/null +++ b/sha256sums_cfgsb_correct.txt @@ -0,0 +1,2 @@ +1a3aced0e9d3cce8aaeeebf94c035ed028dc4b262d06cce0addc97df85905dc3 ./f4b8121.diff +270e30aa319e0fa9b661b2f7f0aaa6e04e6c6f2fea0fc354160867c4e92bb7a3 ./4f95dab.diff -- To view, visit https://review.coreboot.org/c/coreboot/+/44638 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8baaca0d58b863a7084b8672fb9574ebb5e72591 Gerrit-Change-Number: 44638 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

2 3

Change in ...coreboot[master]: SeaBIOS - unofficial patches: advanced_bootmenu and multiple_floppies
by mikeb mikeb (Code Review) 29 Nov '22

29 Nov '22

Hello Mike Banon, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/32351 to review the following change. Change subject: SeaBIOS - unofficial patches: advanced_bootmenu and multiple_floppies ...................................................................... SeaBIOS - unofficial patches: advanced_bootmenu and multiple_floppies If you'd like to add the useful floppies to your coreboot (read about them at http://dangerousprototypes.com/docs/Lenovo_G505S_hacking#Useful_floppies ), or to use your USB numpad for choosing a SeaBIOS boot entry, then this change is for you! It contains two valuable patches together with a Makefile mod needed to automatically apply these patches to a cloned SeaBIOS before its' compilation. advanced_bootmenu: up to 35 entries (2 pages if >18), numpad support (console) https://mail.coreboot.org/hyperkitty/list/seabios@seabios.org/thread/CKWLNT… [PATCH v2] ramdisk: search for all available floppy images instead of one https://mail.coreboot.org/pipermail/seabios/2018-December/012670.html Patch descriptions are available at these links, and just in case here's a copy: advanced_bootmenu: up to 35 entries (2 pages if >18), numpad support (console) Add support for up to 35 boot menu entries (2 pages if >18). To solve the ">10" problem currently experienced by SeaBIOS users (there are no 11, 12, etc. keys on a keyboard - so impossible to choose the last menu entries if you got >10 entries because of multiple hard drives / secondary payloads / floppies) - the boot menu has been extended to the letter keys. NOTE: TPM menu has been moved from T to M letter: it is at the end of keyboard's 3rd row of letters and "Trusted" is adjective while "Module" is a noun; alternatively could press '-'. Also, add support for a numpad. Small USB numpad could be really convenient for choosing the boot entries at coreboot boards used as (maybe headless) servers. '/' char on numpad could be used to open the boot menu or to exit it. If there are >10 boot menu entries - the numpad console interface will be enabled: press one or two digit keys and then ENTER to confirm your choice, or remove a digit by pressing the '.Del' key. Also you could call TPM with '-' key at any moment, or boot with a single key press of your fullsize keyboard. [PATCH v2] ramdisk: search for all available floppy images instead of one All the floppy images available at CBFS will be found and listed in a boot menu, instead of the first found. Could be highly valuable if you are participating in a hobby OS development - would like to test multiple versions of your floppy at the same coreboot image, to reduce the amount of re-flashes and accelerate the development at bare metal - or simply you would like to access multiple floppies as a coreboot user. For example: KolibriOS (nice assembly OS with GUI and apps), FreeDOS, MichalOS, Snowdrop and memtest (coreboot's memtest version is buggy, e.g. external USB keyboard isn't working at some laptops; floppy is much better) Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: Idf4efba31091a8678b51c2f6541d440c5cc6d37d --- M payloads/external/SeaBIOS/Makefile A payloads/external/SeaBIOS/advanced_bootmenu.patch A payloads/external/SeaBIOS/multiple_floppies.patch 3 files changed, 551 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/32351/1 diff --git a/payloads/external/SeaBIOS/Makefile b/payloads/external/SeaBIOS/Makefile index e505c8c..ae58c8c 100644 --- a/payloads/external/SeaBIOS/Makefile +++ b/payloads/external/SeaBIOS/Makefile @@ -76,7 +76,18 @@ # echo "# CONFIG_SMBIOS is not set" >> seabios/.config $(MAKE) -C seabios olddefconfig OUT=out/ -build: config +patch: + if [ -d seabios ]; then \ + cd seabios; \ + if [ ! -f .patched ]; then \ + echo " PATCH SeaBIOS $(TAG-y)"; \ + patch -p1 < ./../advanced_bootmenu.patch; \ + patch -p1 < ./../multiple_floppies.patch; \ + touch .patched; \ + fi; \ + fi + +build: config patch echo " MAKE SeaBIOS $(TAG-y)" $(MAKE) -C seabios OUT=out/ diff --git a/payloads/external/SeaBIOS/advanced_bootmenu.patch b/payloads/external/SeaBIOS/advanced_bootmenu.patch new file mode 100644 index 0000000..c914588 --- /dev/null +++ b/payloads/external/SeaBIOS/advanced_bootmenu.patch @@ -0,0 +1,332 @@ +diff --git a/src/boot.c b/src/boot.c +index 9f82f3c..f94dd27 100644 +--- a/src/boot.c ++++ b/src/boot.c +@@ -463,6 +463,7 @@ get_keystroke(int msec) + * Boot menu and BCV execution + ****************************************************************/ + ++#define BOOTMENU_PAGE_SIZE 18 + #define DEFAULT_BOOTMENU_WAIT 2500 + + // Show IPL option menu. +@@ -478,59 +479,282 @@ interactive_bootmenu(void) + ; + + char *bootmsg = romfile_loadfile("etc/boot-menu-message", NULL); +- int menukey = romfile_loadint("etc/boot-menu-key", 1); +- printf("%s", bootmsg ?: "\nPress ESC for boot menu.\n\n"); ++ int menukey = romfile_loadint("etc/boot-menu-key", 1); // custom menukey ++ printf("%s", bootmsg ?: "\nPress ESC or \\ / slash for boot menu.\n\n"); + free(bootmsg); + + u32 menutime = romfile_loadint("etc/boot-menu-wait", DEFAULT_BOOTMENU_WAIT); + enable_bootsplash(); + int scan_code = get_keystroke(menutime); + disable_bootsplash(); +- if (scan_code != menukey) ++ if (scan_code != menukey && // custom menukey ++ scan_code != 1 && // ESC ++ scan_code != 43 && // '\' char on keyboard ++ scan_code != 53 && // '/' char on keyboard ++ scan_code != 98) { // '/' char on numpad ++ if (scan_code == -1) ++ printf("No key pressed.\n"); ++ else ++ printf("Not a menukey pressed.\n"); + return; ++ } + + while (get_keystroke(0) >= 0) + ; + +- printf("Select boot device:\n\n"); + wait_threads(); + +- // Show menu items ++ char keyboard_keys[35] = {'1','2','3','4','5','6','7','8','9','0', ++ 'q','w','e','r','t','y','u','i','o','p', ++ 'a','s','d','f','g','h','j','k','l', ++ 'z','x','c','v','b','n'}; /* m = TPM */ ++ int numpad_scancodes[10] = { 82, 79, 80, 81, 75, 76, 77, 71, 72, 73 }; ++ int numpi = 0; // Key index: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9. ++ int digits = 0; // Numerical length of a current choice number. ++ int decode = 0; // Decode the current choice number into a letter? ++ int entry_id = 0; ++ char desc[77]; ++ ++ printf("Select boot device"); ++ ++ // Show menu items after counting them and determining a number of pages. ++ // Only 35 boot menu items (36 if to count a TPM) are supported currently. ++ + int maxmenu = 0; + struct bootentry_s *pos; +- hlist_for_each_entry(pos, &BootList, node) { +- char desc[77]; ++ hlist_for_each_entry(pos, &BootList, node) + maxmenu++; +- printf("%d. %s\n", maxmenu ++ ++ if (maxmenu > 10) { ++ if (maxmenu > 35) ++ maxmenu = 35; ++ if (maxmenu > BOOTMENU_PAGE_SIZE) ++ printf(" - page 1 :"); ++ else ++ printf(": "); ++ printf(" // press ENTER after your numpad input"); ++ if (maxmenu > BOOTMENU_PAGE_SIZE) ++ printf(" - if any -\n " ++ " // - or to switch between the pages...\n"); ++ else ++ printf(" (if any)\n\n"); ++ } else { ++ printf(":\n\n"); ++ } ++ ++ hlist_for_each_entry(pos, &BootList, node) { ++ if (entry_id == BOOTMENU_PAGE_SIZE) // Show only the first page. ++ break; ++ printf("%c. %s\n", keyboard_keys[entry_id] + , strtcpy(desc, pos->description, ARRAY_SIZE(desc))); ++ entry_id++; + } ++ int tpm_cshm = 0; + if (tpm_can_show_menu()) { +- printf("\nt. TPM Configuration\n"); ++ tpm_cshm = 1; ++ printf("\nm-. TPM Configuration"); + } +- +- // Get key press. If the menu key is ESC, do not restart boot unless +- // 1.5 seconds have passed. Otherwise users (trained by years of +- // repeatedly hitting keys to enter the BIOS) will end up hitting ESC +- // multiple times and immediately booting the primary boot device. +- int esc_accepted_time = irqtimer_calc(menukey == 1 ? 1500 : 0); ++ printf("\n> "); ++ ++ // Do not restart boot on menukey press, unless DEFAULT_BOOTMENU_WAIT msecs ++ // have passed. Otherwise users (trained by years of repeatedly hitting keys ++ // to enter the BIOS) will end up hitting menukey multiple times and ++ // immediately booting the primary boot device. ++ int esc_accepted_time = irqtimer_calc(DEFAULT_BOOTMENU_WAIT); ++ int choice = 0, kb_choice = 0; ++ int page_num = 1; ++ int enter = 0; ++ int backspace = 0; ++ int tpm_show_menu = 0; + for (;;) { + scan_code = get_keystroke(1000); +- if (scan_code == 1 && !irqtimer_check(esc_accepted_time)) +- continue; +- if (tpm_can_show_menu() && scan_code == 20 /* t */) { ++ if (scan_code == menukey || // custom menukey ++ scan_code == 1 || // ESC ++ scan_code == 43 || // '\' char on keyboard ++ scan_code == 53 || // '/' char on keyboard ++ scan_code == 98) { // '/' char on numpad ++ if (!irqtimer_check(esc_accepted_time)) ++ continue; ++ if (digits == 2) // Remove the decoded "(*)" ++ printf(" \b\b\b"); ++ /* Remove the existing input before printing a message. */ ++ for (; digits > 0; digits--) ++ printf("\b \b"); ++ printf("Menukey pressed.\n"); ++ return; ++ } ++ kb_choice = 0; ++ /* 4 rows of keyboard_keys: 1 row with numbers, 3 rows with letters. ++ Use any of them to select a boot device (except the TPM 'm-' keys) */ ++ // 1st range: 1-9 and 0 (10) keys <==> 2-11 scan codes <==> 1-10 choice ++ if (scan_code >= 2 && scan_code <= 11) kb_choice = scan_code - 1; ++ // 2nd range: Q-P row of letters <==> 16-25 scan codes <==> 11-20 choice ++ if (scan_code >= 16 && scan_code <= 25) kb_choice = scan_code - 5; ++ // 3rd range: A-L row of letters <==> 30-38 scan codes <==> 21-29 choice ++ if (scan_code >= 30 && scan_code <= 38) kb_choice = scan_code - 9; ++ // 4th range: Z-N row of letters <==> 44-49 scan codes <==> 30-35 choice ++ if (scan_code >= 44 && scan_code <= 49) kb_choice = scan_code - 14; ++ // ENTER: (28) on keyboard, (96) on numpad. ++ if (scan_code == 28 || scan_code == 96) ++ enter = 1; ++ // BCKSPC: '<-'(14) and 'Delete'(111) on keyboard, '.Del'(83) on numpad. ++ if (scan_code == 14 || scan_code == 111 || scan_code == 83) ++ backspace = 1; ++ // TPM keys: 'm'(50) and '-'(12) chars on keyboard, '-'(74) on numpad. ++ if ((scan_code == 50 || scan_code == 12 || scan_code == 74) && tpm_cshm) ++ tpm_show_menu = 1; ++ ++ if (kb_choice != 0 || tpm_show_menu) { ++ if (kb_choice > maxmenu) { ++ if (!tpm_show_menu) ++ continue; ++ } else { ++ choice = kb_choice; ++ } ++ if (digits == 2) // Remove the decoded "(*)" ++ printf(" \b\b\b"); ++ /* Remove the existing input before printing a choice. */ ++ for (; digits > 0; digits--) ++ printf("\b \b"); ++ if (!tpm_show_menu) { ++ // Choice is any of the detected boot devices ==> lets boot! ++ break; ++ } ++ } else { ++ // Internal/USB Numpad console interface. ++ if (digits < 9) { ++ for (numpi = 0; numpi < 10; numpi++) { ++ if (scan_code == numpad_scancodes[numpi]) { ++ if (maxmenu <= 10) { // Console interface is not needed. ++ if ((numpi != 0 && numpi <= maxmenu) || ++ (numpi == 0 && 10 <= maxmenu)) { // 10(0) ++ choice = numpi; ++ enter = 1; // Fake ENTER to boot this entry now. ++ } else { // If no such an entry, don't try to boot. ++ break; ++ } ++ } else { ++ if (digits == 2) { ++ printf(" \b\b\b"); // Remove the decoded "(*)" ++ if (choice == 0) { ++ printf("\b\b \b\b"); // Remove "10". ++ digits = 0; ++ } ++ } ++ choice = 10 * choice + numpi; ++ } ++ if (choice > 0) { ++ printf("%d", numpi); // Print the entered digit. ++ digits++; ++ } else { ++ if (10 <= maxmenu) ++ printf("10(0)\b\b\b"); ++ else ++ printf("10(?)\b\b\b"); ++ digits = 2; ++ } ++ if (choice > 9 && digits == 2) // Decode into a letter. ++ decode = 1; ++ break; ++ } ++ } ++ } ++ if (backspace && digits > 0) { ++ backspace = 0; ++ choice = choice / 10; ++ if (digits == 2) { ++ printf(" \b\b\b"); // Remove the decoded "(*)" ++ // 0 turned into 10: one more Backspace is needed to remove. ++ if (choice == 0) { ++ printf("\b \b"); ++ digits--; ++ } ++ } ++ printf("\b \b"); // Remove the last entered digit. ++ digits--; ++ if (choice > 9 && digits == 2) // Decode into a letter. ++ decode = 1; ++ } ++ if (decode) { // Decode the current choice number into a letter. ++ decode = 0; ++ if (choice <= maxmenu) { ++ printf("(%c)", keyboard_keys[choice-1]); ++ } else { ++ if (tpm_cshm && choice == 36) ++ printf("(m)"); // For TPM. ++ else ++ printf("(?)"); // No matching letter found. ++ } ++ printf("\b\b\b"); // Move a cursor before the "(*)" ++ } ++ } ++ ++ if (enter) { ++ enter = 0; ++ if (choice == 0) { ++ if (digits == 2) { // for 0 that turned into 10 ++ if (10 <= maxmenu) ++ break; ++ else ++ continue; ++ } ++ // If there are two pages - switch between them. ++ if (maxmenu > BOOTMENU_PAGE_SIZE) { ++ entry_id = 0; ++ page_num = 3 - page_num; // 3 - 1 = 2; 3 - 2 = 1. ++ printf("\n\nSelect boot device - page %d :" ++ " // press ENTER after your numpad input" ++ " - if any -\n " ++ " // - or to switch between the pages...\n", ++ page_num); ++ hlist_for_each_entry(pos, &BootList, node) { ++ if ((page_num == 1 && entry_id == BOOTMENU_PAGE_SIZE) || ++ (page_num == 2 && entry_id == 35)) ++ break; ++ if (page_num == 1 || entry_id >= BOOTMENU_PAGE_SIZE) ++ printf("%c. %s\n", keyboard_keys[entry_id], ++ strtcpy(desc, pos->description, ARRAY_SIZE(desc))); ++ entry_id++; ++ } ++ if (tpm_cshm) ++ printf("\nm-. TPM Configuration"); ++ printf("\n> "); ++ } ++ } else { ++ if (choice > maxmenu) { ++ if (tpm_cshm && choice == 36) ++ tpm_show_menu = 1; ++ } else { ++ // Choice is any of the detected boot devices ==> lets boot! ++ break; ++ } ++ } ++ } ++ ++ if (tpm_show_menu) { ++ tpm_show_menu = 0; ++ choice = 0; ++ if (digits == 0) ++ printf("TPM key pressed."); ++ else ++ digits = 0; + printf("\n"); + tpm_menu(); ++ printf("> "); + } +- if (scan_code >= 1 && scan_code <= maxmenu+1) +- break; ++ } ++ ++ if (choice == 0) // 10(0) ++ choice = 10; ++ ++ if (digits == 0 && choice < 36) { ++ printf("%c", keyboard_keys[choice-1]); ++ if (choice > 9) // Decode into a number. ++ printf("(%d)", choice); + } + printf("\n"); +- if (scan_code == 0x01) +- // ESC +- return; + + // Find entry and make top priority. +- int choice = scan_code - 1; + hlist_for_each_entry(pos, &BootList, node) { + if (! --choice) + break; +diff --git a/src/config.h b/src/config.h +index 93c8dbc..f85cc14 100644 +--- a/src/config.h ++++ b/src/config.h +@@ -19,7 +19,7 @@ + // Space to reserve in high-memory for tables + #define BUILD_MAX_HIGHTABLE (256*1024) + // Largest supported externaly facing drive id +-#define BUILD_MAX_EXTDRIVE 16 ++#define BUILD_MAX_EXTDRIVE 36 + // Number of bytes the smbios may be and still live in the f-segment + #define BUILD_MAX_SMBIOS_FSEG 600 + // Maximum number of bytes the mptable may be and still be copied to f-segment diff --git a/payloads/external/SeaBIOS/multiple_floppies.patch b/payloads/external/SeaBIOS/multiple_floppies.patch new file mode 100644 index 0000000..5249394 --- /dev/null +++ b/payloads/external/SeaBIOS/multiple_floppies.patch @@ -0,0 +1,207 @@ +diff --git a/src/block.h b/src/block.h +index f64e880..aaa236f 100644 +--- a/src/block.h ++++ b/src/block.h +@@ -2,7 +2,7 @@ + #define __BLOCK_H + + #include "types.h" // u32 +- ++#include "romfile.h" // struct romfile_s + + /**************************************************************** + * Disk command request +@@ -48,6 +48,7 @@ struct drive_s { + struct drive_s { + u8 type; // Driver type (DTYPE_*) + u8 floppy_type; // Type of floppy (only for floppy drives). ++ struct romfile_s *floppy_file; // Floppy file (only for virtual floppies). + struct chs_s lchs; // Logical CHS + u64 sectors; // Total sectors count + u32 cntl_id; // Unique id for a given driver type. +diff --git a/src/boot.c b/src/boot.c +index 9f82f3c..79f1e7d 100644 +--- a/src/boot.c ++++ b/src/boot.c +@@ -584,7 +584,7 @@ bcv_prepboot(void) + break; + case IPL_TYPE_FLOPPY: + map_floppy_drive(pos->drive); +- add_bev(IPL_TYPE_FLOPPY, 0); ++ add_bev(IPL_TYPE_FLOPPY, (u32)pos->drive); + break; + case IPL_TYPE_HARDDISK: + map_hd_drive(pos->drive); +@@ -733,6 +733,12 @@ do_boot(int seq_nr) + static void + do_boot(int seq_nr) + { ++ ++ int ret; ++ void *pos; ++ struct romfile_s *file; ++ struct drive_s *drive; ++ + if (! CONFIG_BOOT) + panic("Boot support not compiled in.\n"); + +@@ -744,6 +750,16 @@ do_boot(int seq_nr) + switch (ie->type) { + case IPL_TYPE_FLOPPY: + printf("Booting from Floppy...\n"); ++ drive = (struct drive_s *)ie->vector; ++ file = drive->floppy_file; ++ // File is NULL if a floppy is physical. ++ if (file) { ++ // Copy virtual floppy image into ram. ++ pos = (void *)drive->cntl_id; ++ ret = file->copy(file, pos, file->size); ++ if (ret < 0) ++ break; ++ } + boot_disk(0x00, CheckFloppySig); + break; + case IPL_TYPE_HARDDISK: +diff --git a/src/hw/floppy.c b/src/hw/floppy.c +index 9e6647d..5b37c6c 100644 +--- a/src/hw/floppy.c ++++ b/src/hw/floppy.c +@@ -107,7 +107,7 @@ struct floppyinfo_s FloppyInfo[] VARFSEG = { + }; + + struct drive_s * +-init_floppy(int floppyid, int ftype) ++init_floppy(int floppyid, int ftype, struct romfile_s *ffile) + { + if (ftype <= 0 || ftype >= ARRAY_SIZE(FloppyInfo)) { + dprintf(1, "Bad floppy type %d\n", ftype); +@@ -124,6 +124,7 @@ init_floppy(int floppyid, int ftype) + drive->type = DTYPE_FLOPPY; + drive->blksize = DISK_SECTOR_SIZE; + drive->floppy_type = ftype; ++ drive->floppy_file = ffile; + drive->sectors = (u64)-1; + + memcpy(&drive->lchs, &FloppyInfo[ftype].chs +@@ -134,7 +135,7 @@ addFloppy(int floppyid, int ftype) + static void + addFloppy(int floppyid, int ftype) + { +- struct drive_s *drive = init_floppy(floppyid, ftype); ++ struct drive_s *drive = init_floppy(floppyid, ftype, 0); + if (!drive) + return; + char *desc = znprintf(MAXDESCSIZE, "Floppy [drive %c]", 'A' + floppyid); +diff --git a/src/hw/ramdisk.c b/src/hw/ramdisk.c +index b9e9baa..a679385 100644 +--- a/src/hw/ramdisk.c ++++ b/src/hw/ramdisk.c +@@ -23,40 +23,69 @@ ramdisk_setup(void) + if (!CONFIG_FLASH_FLOPPY) + return; + +- // Find image. +- struct romfile_s *file = romfile_findprefix("floppyimg/", NULL); +- if (!file) +- return; +- const char *filename = file->name; +- u32 size = file->size; +- dprintf(3, "Found floppy file %s of size %d\n", filename, size); +- int ftype = find_floppy_type(size); +- if (ftype < 0) { +- dprintf(3, "No floppy type found for ramdisk size\n"); ++ struct romfile_s *file = NULL; ++ char *filename, *desc; ++ u32 size, max_size = 0; ++ int ftype; ++ void *pos; ++ struct drive_s *drive; ++ ++ // Find the max floppy size ++ for (;;) { ++ // Find the next image. ++ file = romfile_findprefix("floppyimg/", file); ++ if (!file) ++ break; ++ filename = file->name; ++ size = file->size; ++ dprintf(3, "Found floppy file %s of size %d\n", filename, size); ++ // Check if this size is valid. ++ ftype = find_floppy_type(size); ++ if (ftype < 0) { ++ dprintf(3, "No floppy type found for ramdisk size\n"); ++ } else { ++ if (size > max_size) ++ max_size = size; ++ } ++ } ++ if (max_size == 0) { ++ dprintf(3, "No floppies found\n"); + return; + } + + // Allocate ram for image. +- void *pos = memalign_tmphigh(PAGE_SIZE, size); ++ pos = memalign_tmphigh(PAGE_SIZE, max_size); + if (!pos) { + warn_noalloc(); + return; + } +- e820_add((u32)pos, size, E820_RESERVED); ++ e820_add((u32)pos, max_size, E820_RESERVED); ++ dprintf(3, "Allocate %u bytes for a floppy\n", max_size); + +- // Copy image into ram. +- int ret = file->copy(file, pos, size); +- if (ret < 0) +- return; +- +- // Setup driver. +- struct drive_s *drive = init_floppy((u32)pos, ftype); +- if (!drive) +- return; +- drive->type = DTYPE_RAMDISK; +- dprintf(1, "Mapping floppy %s to addr %p\n", filename, pos); +- char *desc = znprintf(MAXDESCSIZE, "Ramdisk [%s]", &filename[10]); +- boot_add_floppy(drive, desc, bootprio_find_named_rom(filename, 0)); ++ // Setup the floppy drivers. ++ file = NULL; ++ for (;;) { ++ // Find the next image. ++ file = romfile_findprefix("floppyimg/", file); ++ if (!file) ++ return; ++ filename = file->name; ++ size = file->size; ++ dprintf(3, "Found floppy file %s of size %d\n", filename, size); ++ ftype = find_floppy_type(size); ++ if (ftype < 0) { ++ dprintf(3, "No floppy type found for ramdisk size\n"); ++ } else { ++ // Setup driver. ++ drive = init_floppy((u32)pos, ftype, file); ++ if (!drive) ++ return; ++ drive->type = DTYPE_RAMDISK; ++ dprintf(1, "Mapping floppy %s to addr %p\n", filename, pos); ++ desc = znprintf(MAXDESCSIZE, "Ramdisk [%s]", &filename[10]); ++ boot_add_floppy(drive, desc, bootprio_find_named_rom(filename, 0)); ++ } ++ } + } + + static int +diff --git a/src/util.h b/src/util.h +index 9c06850..ce3a26d 100644 +--- a/src/util.h ++++ b/src/util.h +@@ -147,7 +147,8 @@ void dma_setup(void); + // hw/floppy.c + extern struct floppy_ext_dbt_s diskette_param_table2; + void floppy_setup(void); +-struct drive_s *init_floppy(int floppyid, int ftype); ++extern struct romfile_s *ffile; ++struct drive_s *init_floppy(int floppyid, int ftype, struct romfile_s *ffile); + int find_floppy_type(u32 size); + int floppy_process_op(struct disk_op_s *op); + void floppy_tick(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/32351 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf4efba31091a8678b51c2f6541d440c5cc6d37d Gerrit-Change-Number: 32351 Gerrit-PatchSet: 1 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

5 31

Change in coreboot[master]: mb/asus/a88xm-e: Disable SeaBIOS options unsupported by hardware
by Mike Banon (Code Review) 29 Nov '22

29 Nov '22

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44637 ) Change subject: mb/asus/a88xm-e: Disable SeaBIOS options unsupported by hardware ...................................................................... mb/asus/a88xm-e: Disable SeaBIOS options unsupported by hardware A88XM-E doesn't have any SAS or NVMe controllers and couldn't have a TPM so it makes sense to disable the related SeaBIOS options for this board. This reduces the size of compiled SeaBIOS by 129344-110048=19296 bytes. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: Ie9760449734499628637e015cacc0541ec0002a2 --- M src/mainboard/asus/a88xm-e/Kconfig A src/mainboard/asus/a88xm-e/config_seabios 2 files changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/44637/1 diff --git a/src/mainboard/asus/a88xm-e/Kconfig b/src/mainboard/asus/a88xm-e/Kconfig index 6874e9e..139f989 100644 --- a/src/mainboard/asus/a88xm-e/Kconfig +++ b/src/mainboard/asus/a88xm-e/Kconfig @@ -56,4 +56,8 @@ bool default n +config PAYLOAD_CONFIGFILE + string + default "$(top)/src/mainboard/$(MAINBOARDDIR)/config_seabios" if PAYLOAD_SEABIOS + endif # BOARD_ASUS_A88XM_E diff --git a/src/mainboard/asus/a88xm-e/config_seabios b/src/mainboard/asus/a88xm-e/config_seabios new file mode 100644 index 0000000..03bf0e8 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/config_seabios @@ -0,0 +1,7 @@ +### +### SeaBIOS custom configuration for ASUS A88XM-E +### +# CONFIG_MEGASAS is not set +# CONFIG_NVME is not set +# CONFIG_TCGBIOS is not set +# -- To view, visit https://review.coreboot.org/c/coreboot/+/44637 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9760449734499628637e015cacc0541ec0002a2 Gerrit-Change-Number: 44637 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: mb/asus/am1i-a: Disable SeaBIOS options unsupported by hardware
by Mike Banon (Code Review) 29 Nov '22

29 Nov '22

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44636 ) Change subject: mb/asus/am1i-a: Disable SeaBIOS options unsupported by hardware ...................................................................... mb/asus/am1i-a: Disable SeaBIOS options unsupported by hardware AM1I-A does not have any SAS or NVMe controllers, so it makes sense to disable the related SeaBIOS options for this board. This reduces the size of compiled SeaBIOS by 129344-124096 = 5248 bytes. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: Ideec5d8cf3cf4cc7fba0787e56ab38b5172a5314 --- M src/mainboard/asus/am1i-a/Kconfig A src/mainboard/asus/am1i-a/config_seabios 2 files changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/44636/1 diff --git a/src/mainboard/asus/am1i-a/Kconfig b/src/mainboard/asus/am1i-a/Kconfig index 172d808..ff12d74 100644 --- a/src/mainboard/asus/am1i-a/Kconfig +++ b/src/mainboard/asus/am1i-a/Kconfig @@ -51,4 +51,8 @@ bool default n +config PAYLOAD_CONFIGFILE + string + default "$(top)/src/mainboard/$(MAINBOARDDIR)/config_seabios" if PAYLOAD_SEABIOS + endif # BOARD_ASUS_AM1I_A diff --git a/src/mainboard/asus/am1i-a/config_seabios b/src/mainboard/asus/am1i-a/config_seabios new file mode 100644 index 0000000..0ee9cea --- /dev/null +++ b/src/mainboard/asus/am1i-a/config_seabios @@ -0,0 +1,6 @@ +### +### SeaBIOS custom configuration for ASUS AM1I-A +### +# CONFIG_MEGASAS is not set +# CONFIG_NVME is not set +# -- To view, visit https://review.coreboot.org/c/coreboot/+/44636 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ideec5d8cf3cf4cc7fba0787e56ab38b5172a5314 Gerrit-Change-Number: 44636 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

1 4

Change in coreboot[master]: asus/a88xm-e: add the PIRQ routing table
by Mike Banon (Code Review) 29 Nov '22

29 Nov '22

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48426 ) Change subject: asus/a88xm-e: add the PIRQ routing table ...................................................................... asus/a88xm-e: add the PIRQ routing table Add the PIRQ routing table for this board. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I8fe3fb03ca0e7a2fecb92efeaf621925b198a39f --- M src/mainboard/asus/a88xm-e/Kconfig M src/mainboard/asus/a88xm-e/irq_tables.c 2 files changed, 68 insertions(+), 77 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/48426/1 diff --git a/src/mainboard/asus/a88xm-e/Kconfig b/src/mainboard/asus/a88xm-e/Kconfig index 17fbe28..c889497 100644 --- a/src/mainboard/asus/a88xm-e/Kconfig +++ b/src/mainboard/asus/a88xm-e/Kconfig @@ -42,7 +42,7 @@ config IRQ_SLOT_COUNT int - default 11 + default 21 config VGA_BIOS_ID string diff --git a/src/mainboard/asus/a88xm-e/irq_tables.c b/src/mainboard/asus/a88xm-e/irq_tables.c index 7ca1c4b..47dbb11 100644 --- a/src/mainboard/asus/a88xm-e/irq_tables.c +++ b/src/mainboard/asus/a88xm-e/irq_tables.c @@ -1,84 +1,75 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/pirq_routing.h> -#include <console/console.h> -#include <device/pci_def.h> -#include <string.h> -static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, - u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, - u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, u8 slot, u8 rfu) -{ - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; -} +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */ + 0x00, /* Interrupt router bus */ + (0x14 << 3) | 0x3, /* Interrupt router dev */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x1022, /* Vendor */ + 0x780e, /* Device */ + 0, /* Miniport */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0x14, /* Checksum (has to be set to some value that + * would give 0 after the sum of all bytes + * for this structure (including checksum). + */ + { + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* IOMMU: 0:00.02 - IRQ 3 */ + {0x00, (0x00 << 3) | 0x2, {{0x01, 0xccf0}, {0x02, 0xccf0}, {0x03, 0xccf0}, {0x04, 0xccf0} }, 0x0, 0x0}, + /* APU Integrated Graphics: 0:01.00 - IRQ 3 */ + /* APU HDMI Audio Controller: 0:01.01 - IRQ 4 */ + {0x00, (0x01 << 3) | 0x0, {{0x01, 0xccf0}, {0x02, 0xccf0}, {0x00, 0x0000}, {0x00, 0x0000} }, 0x0, 0x0}, + /* PCIe GPP to dGPU 1:00.00: 0:02.00 - IRQ 3 */ + {0x00, (0x02 << 3) | 0x0, {{0x01, 0xccf0}, {0x02, 0xccf0}, {0x03, 0xccf0}, {0x04, 0xccf0} }, 0x0, 0x0}, + /* PCIe GPP to 2:00.00: 0:04.00 - IRQ 3 */ + {0x00, (0x04 << 3) | 0x0, {{0x01, 0xccf0}, {0x02, 0xccf0}, {0x03, 0xccf0}, {0x04, 0xccf0} }, 0x0, 0x0}, + /* PCIe GPP to 3:00.00: 0:05.00 - IRQ 3 */ + {0x00, (0x05 << 3) | 0x0, {{0x01, 0xccf0}, {0x02, 0xccf0}, {0x03, 0xccf0}, {0x04, 0xccf0} }, 0x0, 0x0}, + /* PCIe GPP to Eth 4:00.00: 0:06.00 - IRQ 4 */ + {0x00, (0x06 << 3) | 0x0, {{0x02, 0xccf0}, {0x03, 0xccf0}, {0x04, 0xccf0}, {0x01, 0xccf0} }, 0x0, 0x0}, + /* USB XHCI: 0:10.00 - IRQ 5 */ + {0x00, (0x10 << 3) | 0x0, {{0x03, 0xccf0}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000} }, 0x0, 0x0}, + /* SATA: 0:11.00 - IRQ 7 */ + {0x00, (0x11 << 3) | 0x0, {{0x04, 0xccf0}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000} }, 0x0, 0x0}, + /* USB OHCI1: 0:12.00 - IRQ 5 */ + /* USB EHCI1: 0:12.02 - IRQ 4 */ + {0x00, (0x12 << 3) | 0x0, {{0x03, 0xccf0}, {0x02, 0xccf0}, {0x00, 0x0000}, {0x00, 0x0000} }, 0x0, 0x0}, + /* USB OHCI2: 0:13.00 - IRQ 5 */ + /* USB EHCI2: 0:13.02 - IRQ 4 */ + {0x00, (0x16 << 3) | 0x0, {{0x03, 0xccf0}, {0x02, 0xccf0}, {0x00, 0x0000}, {0x00, 0x0000} }, 0x0, 0x0}, + /* USB OHCI3: 0:16.00 - IRQ 5 */ + /* USB EHCI3: 0:16.02 - IRQ 4 */ + {0x00, (0x13 << 3) | 0x0, {{0x03, 0xccf0}, {0x02, 0xccf0}, {0x00, 0x0000}, {0x00, 0x0000} }, 0x0, 0x0}, + /* Southbridge HD Audio: 0:14.02 - IRQ 3 */ + /* USB OHCI4: 0:14.05 - IRQ 5 */ + {0x00, (0x14 << 3) | 0x0, {{0x01, 0xccf0}, {0x02, 0xccf0}, {0x03, 0xccf0}, {0x04, 0xccf0} }, 0x0, 0x0}, + /* Southbridge PCI Port: 0:14.04 - IRQ 11 */ + {0x00, (0x14 << 3) | 0x4, {{0x05, 0xccf0}, {0x06, 0xccf0}, {0x00, 0x0000}, {0x00, 0x0000} }, 0x0, 0x0}, + /* Southbridge PCIe Port 1: 0:15.00 - IRQ 4 */ + {0x00, (0x15 << 3) | 0x0, {{0x02, 0xccf0}, {0x03, 0xccf0}, {0x04, 0xccf0}, {0x01, 0xccf0} }, 0x0, 0x0}, + /* Southbridge PCIe Port 2: 0:15.01 - IRQ 5 */ + {0x00, (0x15 << 3) | 0x1, {{0x03, 0xccf0}, {0x04, 0xccf0}, {0x01, 0xccf0}, {0x02, 0xccf0} }, 0x0, 0x0}, + /* Southbridge PCIe Port 3: 0:15.02 - IRQ 7 */ + {0x00, (0x15 << 3) | 0x2, {{0x04, 0xccf0}, {0x01, 0xccf0}, {0x02, 0xccf0}, {0x03, 0xccf0} }, 0x0, 0x0}, + /* Southbridge PCIe Port 4: 0:15.03 - IRQ 3 */ + {0x00, (0x15 << 3) | 0x3, {{0x01, 0xccf0}, {0x02, 0xccf0}, {0x03, 0xccf0}, {0x04, 0xccf0} }, 0x0, 0x0}, + /* Discrete Graphics (dGPU) 1:00.00 behind a 0:02.00 PCIe GPP - IRQ 3 */ + {0x01, (0x00 << 3) | 0x0, {{0x01, 0xccf0}, {0x02, 0xccf0}, {0x03, 0xccf0}, {0x04, 0xccf0} }, 0x1, 0x0}, + /* 2:00.00 behind a 0:04.00 PCIe GPP - IRQ 3 */ + {0x02, (0x00 << 3) | 0x0, {{0x01, 0xccf0}, {0x02, 0xccf0}, {0x03, 0xccf0}, {0x04, 0xccf0} }, 0x2, 0x0}, + /* 3:00.00 behind a 0:05.00 PCIe GPP - IRQ 4 */ + {0x03, (0x00 << 3) | 0x0, {{0x02, 0xccf0}, {0x03, 0xccf0}, {0x04, 0xccf0}, {0x01, 0xccf0} }, 0x3, 0x0}, + /* Onboard Ethernet (Eth) 4:00.00 behind a 0:06.00 PCIe GPP - IRQ 4 */ + {0x04, (0x00 << 3) | 0x0, {{0x02, 0xccf0}, {0x03, 0xccf0}, {0x04, 0xccf0}, {0x01, 0xccf0} }, 0x4, 0x0} + } +}; unsigned long write_pirq_routing_table(unsigned long addr) { - struct irq_routing_table *pirq; - struct irq_info *pirq_info; - u32 slot_num; - - u8 sum = 0; - int i; - - /* Align the table to be 16 byte aligned. */ - addr = ALIGN_UP(addr, 16); - - /* This table must be between 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); - - pirq = (void *)(addr); - - pirq->signature = PIRQ_SIGNATURE; - pirq->version = PIRQ_VERSION; - - pirq->rtr_bus = 0; - pirq->rtr_devfn = PCI_DEVFN(0x14, 4); - - pirq->exclusive_irqs = 0; - - pirq->rtr_vendor = 0x1002; - pirq->rtr_device = 0x4384; - - pirq->miniport_data = 0; - - memset(pirq->rfu, 0, sizeof(pirq->rfu)); - - pirq_info = (void *)(&pirq->slots); - slot_num = 0; - - /* pci bridge */ - write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), - 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); - pirq_info++; - - slot_num++; - - pirq->size = 32 + 16 * slot_num; - - { - const u8 *const v = (u8 *)(pirq); - for (i = 0; i < pirq->size; i++) - sum += v[i]; - } - - sum = pirq->checksum - sum; - - if (sum != pirq->checksum) - pirq->checksum = sum; - - printk(BIOS_INFO, "%s done.\n", __func__); - - return (unsigned long)pirq_info; + return copy_pirq_routing_table(addr, &intel_irq_routing_table); } -- To view, visit https://review.coreboot.org/c/coreboot/+/48426 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8fe3fb03ca0e7a2fecb92efeaf621925b198a39f Gerrit-Change-Number: 48426 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

2 10

Change in coreboot[master]: asus/a88xm-e: properly program the IRQ tables
by Mike Banon (Code Review) 29 Nov '22

29 Nov '22

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48424 ) Change subject: asus/a88xm-e: properly program the IRQ tables ...................................................................... asus/a88xm-e: properly program the IRQ tables IRQ programming should be outside the obsolete MP table generation, just like the proper way done for asus/am1i-a AMD fam16h - closest example for ASUS A88XM-E: all the fam15h boards have these "bad IRQs". OS like Linux still finds a way, but Kolibri can't see the IRQ table. With this change applied: * A88XM-E boots fine to Linux - no angry IRQ-related messages at dmesg; * KolibriOS sees 16 IRQs in a table and could successfully attach a driver to Realtek RTL8168 onboard Ethernet controller with an IRQ 7. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I9a6ab9e24a828ebaffe87205a2ce0ebd811a935d --- M src/mainboard/asus/a88xm-e/mainboard.c M src/mainboard/asus/a88xm-e/mptable.c 2 files changed, 207 insertions(+), 69 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/48424/1 diff --git a/src/mainboard/asus/a88xm-e/mainboard.c b/src/mainboard/asus/a88xm-e/mainboard.c index 2e08188..5caf224 100644 --- a/src/mainboard/asus/a88xm-e/mainboard.c +++ b/src/mainboard/asus/a88xm-e/mainboard.c @@ -6,26 +6,54 @@ #include <device/device.h> #include <southbridge/amd/common/amd_pci_util.h> -static const u8 mainboard_picr_data[] = { - 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x0A, 0xF1, 0x00, 0x00, 0x1F, 0x1F, - 0x1F, 0x1F, 0x09, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, -}; -static const u8 mainboard_intr_data[84] = { - 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, - 0x1F, 0x1F, 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x05, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x11, 0x12, 0x13, +#include <southbridge/amd/agesa/hudson/pci_devs.h> +#include <southbridge/amd/agesa/hudson/amd_pci_int_defs.h> +#include <northbridge/amd/agesa/family15tn/pci_devs.h> + +extern const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE]; +extern const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE]; + +/* + * This table defines the index into the picr/intr_data + * tables for each device. Any enabled device and slot + * that uses hardware interrupts should have an entry + * in this table to define its index into the FCH + * PCI_INTR register 0xC00/0xC01. This index will define + * the interrupt that it should use. Putting PIRQ_A into + * the PIN A index for a device will tell that device to + * use PIC IRQ picr_data[PIRQ_A] if it uses PIN A for its hardware INT. + */ +static const struct pirq_struct mainboard_pirq_data[] = { + /* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D} }, */ + {IOMMU_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, /* IOMMU: 0:00.02 - IRQ 3 */ + {GFX_DEVFN, {PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* APU Integrated Graphics: 0:01.00 - IRQ 3 */ + {ACTL_DEVFN, {PIRQ_NC, PIRQ_B, PIRQ_NC, PIRQ_NC} }, /* APU HDMI Audio Controller: 0:01.01 - IRQ 4 */ + {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, /* PCIe GPP to dGPU 1:00.00: 0:02.00 - IRQ 3 */ + {NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, /* PCIe GPP to 2:00.00: 0:04.00 - IRQ 3 */ + {NB_PCIE_PORT4_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A} }, /* PCIe GPP to 3:00.00: 0:05.00 - IRQ 4 */ + {NB_PCIE_PORT5_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A} }, /* PCIe GPP to Eth 4:00.00: 0:06.00 - IRQ 4 */ + {XHCI_DEVFN, {PIRQ_C, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* USB XHCI: 0:10.00 - IRQ 5 */ + {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* SATA: 0:11.00 - IRQ 7 */ + {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* USB OHCI1: 0:12.00 - IRQ 5 */ + {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC} }, /* USB EHCI1: 0:12.02 - IRQ 4 */ + {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* USB OHCI2: 0:13.00 - IRQ 5 */ + {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC} }, /* USB EHCI2: 0:13.02 - IRQ 4 */ + {OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* USB OHCI3: 0:16.00 - IRQ 5 */ + {EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC} }, /* USB EHCI3: 0:16.02 - IRQ 4 */ + {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* Southbridge HD Audio: 0:14.02 - IRQ 3 */ + {SB_PCI_PORT_DEVFN, {PIRQ_E, PIRQ_F, PIRQ_NC, PIRQ_NC} }, /* Southbridge PCI Port: 0:14.04 - IRQ 11 */ + {OHCI4_DEVFN, {PIRQ_NC, PIRQ_NC, PIRQ_OHCI4, PIRQ_NC} }, /* USB OHCI4: 0:14.05 - IRQ 5 */ + {SB_PCIE_PORT1_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A} }, /* Southbridge PCIe Port 1: 0:15.00 - IRQ 4 */ + {SB_PCIE_PORT2_DEVFN, {PIRQ_C, PIRQ_D, PIRQ_A, PIRQ_B} }, /* Southbridge PCIe Port 2: 0:15.01 - IRQ 5 */ + {SB_PCIE_PORT3_DEVFN, {PIRQ_D, PIRQ_A, PIRQ_B, PIRQ_C} }, /* Southbridge PCIe Port 3: 0:15.02 - IRQ 7 */ + {SB_PCIE_PORT4_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} } /* Southbridge PCIe Port 4: 0:15.03 - IRQ 3 */ }; /* PIRQ Setup */ static void pirq_setup(void) { + pirq_data_ptr = mainboard_pirq_data; + pirq_data_size = ARRAY_SIZE(mainboard_pirq_data); intr_data_ptr = mainboard_intr_data; picr_data_ptr = mainboard_picr_data; } @@ -36,6 +64,7 @@ msr_t msr; printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + /* Initialize the PIRQ data structures for consumption */ pirq_setup(); msr = rdmsr(LS_CFG_MSR); diff --git a/src/mainboard/asus/a88xm-e/mptable.c b/src/mainboard/asus/a88xm-e/mptable.c index b9e743c..5d9731f 100644 --- a/src/mainboard/asus/a88xm-e/mptable.c +++ b/src/mainboard/asus/a88xm-e/mptable.c @@ -1,10 +1,61 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <arch/io.h> #include <arch/ioapic.h> #include <arch/smp/mpspec.h> +#include <stdint.h> #include <string.h> #include <southbridge/amd/common/amd_pci_util.h> #include <southbridge/amd/agesa/hudson/hudson.h> +#include <drivers/generic/ioapic/chip.h> + +/* + * Based on 51205_Bolton_FCH_BIOS_Dev_Guide.pdf. Acronyms: + * + * SCI - System Controller Interrupt, + * SMBUS - System Management Bus, + * ASF - Advanced Synchronization Facility, + * HDA - HD Audio, + * SD - SD Flash Controller, + * GEC - Gigabit Ethernet Controller, + * PerMon - Performance Monitor, + * IMC - Integrated Memory Controller, + * GPP - PCIe General Purpose Ports. + */ + +const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = { + /* INTA# - INTH# */ + [0x00] = 0x03, 0x04, 0x05, 0x07, 0x0B, 0x0A, 0x1F, 0x1F, + /* Misc-nil,0,1,2, INTA-INTD from Serial irq */ + [0x08] = 0xAA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, + /* SCI, SMBUS0, ASF, HDA, SD, GEC, PerMon */ + [0x10] = 0x09, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, + /* IMC INT0-INT5 */ + [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + /* USB Devs: 18 INTA#,B#; 19 INTA#,B#; 22 INTA#,B#; 20 INTC# */ + [0x30] = 0x05, 0x04, 0x05, 0x04, 0x05, 0x04, 0x05, + /* IDE, SATA */ + [0x40] = 0x1F, 0x07, + /* GPP Int0-Int3 */ + [0x50] = 0x1F, 0x1F, 0x1F, 0x1F +}; + +const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = { + /* INTA# - INTH# */ + [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x1F, 0x1F, + /* Misc-nil,0,1,2, INTA-INTD from Serial irq */ + [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, + /* SCI, SMBUS0, ASF, HDA, SD, GEC, PerMon */ + [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x1F, 0x1F, + /* IMC INT0-INT5 */ + [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + /* USB Devs: 18 INTA#,B#; 19 INTA#,B#; 22 INTA#,B#; 20 INTC# */ + [0x30] = 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, + /* IDE, SATA */ + [0x40] = 0x1F, 0x13, + /* GPP Int0-Int3 */ + [0x50] = 0x1F, 0x1F, 0x1F, 0x1F +}; static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) { @@ -37,92 +88,150 @@ u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); + /* Initialize the MP_Table */ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LOCAL_APIC_ADDR); memcpy(mc->mpc_oem, "AMD ", 8); + /* + * Type 0: Processor Entries: + * LAPIC ID, LAPIC Version, CPU Flags:EN/BP, + * CPU Signature (Stepping, Model, Family), + * Feature Flags + */ smp_write_processors(mc); - //mptable_write_buses(mc, NULL, &bus_isa); + /* + * Type 1: Bus Entries: + * Bus ID, Bus Type + */ + // mptable_write_buses(mc, NULL, &bus_isa); my_smp_write_bus(mc, 0, "PCI "); my_smp_write_bus(mc, 1, "PCI "); bus_isa = 0x02; my_smp_write_bus(mc, bus_isa, "ISA "); - /* I/O APICs: APIC ID Version State Address */ + /* + * Type 2: I/O APICs: + * APIC ID, Version, APIC Flags:EN, Address + */ smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,\ - bus_isa, (intr), (apicid), (pin)) + /* + * Type 3: I/O Interrupt Table Entries: + * Int Type, Int Polarity, Int Level, Source Bus ID, + * Source Bus IRQ, Dest APIC ID, Dest PIN# + */ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,\ - (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) +#define PCI_INT(bus, dev, fn, pin) \ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) - /* IOMMU */ - PCI_INT(0x0, 0x0, 0x0, 0x10); - PCI_INT(0x0, 0x0, 0x1, 0x11); - PCI_INT(0x0, 0x0, 0x2, 0x12); - PCI_INT(0x0, 0x0, 0x3, 0x13); + /* IOMMU: 0:00.02 - IRQ 3 */ + PCI_INT(0x0, 0x00, 0x0, intr_data_ptr[PIRQ_A]); + PCI_INT(0x0, 0x00, 0x1, intr_data_ptr[PIRQ_B]); + PCI_INT(0x0, 0x00, 0x2, intr_data_ptr[PIRQ_C]); + PCI_INT(0x0, 0x00, 0x3, intr_data_ptr[PIRQ_D]); - /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); + /* APU Integrated Graphics: 0:01.00 - IRQ 3 */ + PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_A]); + /* APU HDMI Audio Controller: 0:01.01 - IRQ 4 */ + PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_B]); - /* SMBUS */ - PCI_INT(0x0, 0x14, 0x0, 0x10); + /* PCIe GPP to dGPU 1:00.00: 0:02.00 - IRQ 3 */ + PCI_INT(0x0, 0x02, 0x0, intr_data_ptr[PIRQ_A]); + PCI_INT(0x0, 0x02, 0x1, intr_data_ptr[PIRQ_B]); + PCI_INT(0x0, 0x02, 0x2, intr_data_ptr[PIRQ_C]); + PCI_INT(0x0, 0x02, 0x3, intr_data_ptr[PIRQ_D]); + /* PCIe GPP to 2:00.00: 0:04.00 - IRQ 3 */ + PCI_INT(0x0, 0x04, 0x0, intr_data_ptr[PIRQ_A]); + PCI_INT(0x0, 0x04, 0x1, intr_data_ptr[PIRQ_B]); + PCI_INT(0x0, 0x04, 0x2, intr_data_ptr[PIRQ_C]); + PCI_INT(0x0, 0x04, 0x3, intr_data_ptr[PIRQ_D]); + /* PCIe GPP to 3:00.00: 0:05.00 - IRQ 4 */ + PCI_INT(0x0, 0x05, 0x0, intr_data_ptr[PIRQ_B]); + PCI_INT(0x0, 0x05, 0x1, intr_data_ptr[PIRQ_C]); + PCI_INT(0x0, 0x05, 0x2, intr_data_ptr[PIRQ_D]); + PCI_INT(0x0, 0x05, 0x3, intr_data_ptr[PIRQ_A]); + /* PCIe GPP to Eth 4:00.00: 0:06.00 - IRQ 4 */ + PCI_INT(0x0, 0x06, 0x0, intr_data_ptr[PIRQ_B]); + PCI_INT(0x0, 0x06, 0x1, intr_data_ptr[PIRQ_C]); + PCI_INT(0x0, 0x06, 0x2, intr_data_ptr[PIRQ_D]); + PCI_INT(0x0, 0x06, 0x3, intr_data_ptr[PIRQ_A]); - /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ + /* USB XHCI: 0:10.00 - IRQ 5 */ + PCI_INT(0x0, 0x10, 0x0, intr_data_ptr[PIRQ_C]); + /* SATA: 0:11.00 - IRQ 7 */ + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]); + /* USB OHCI1: 0:12.00 - IRQ 5 */ + PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]); + /* USB EHCI1: 0:12.02 - IRQ 4 */ + PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]); + /* USB OHCI2: 0:13.00 - IRQ 5 */ + PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]); + /* USB EHCI2: 0:13.02 - IRQ 4 */ + PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]); + /* USB OHCI3: 0:16.00 - IRQ 5 */ + PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]); + /* USB EHCI3: 0:16.02 - IRQ 4 */ + PCI_INT(0x0, 0x16, 0x2, intr_data_ptr[PIRQ_EHCI3]); + /* Southbridge HD Audio: 0:14.02 - IRQ 3 */ + PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]); + /* USB OHCI4: 0:14.05 - IRQ 5 */ + PCI_INT(0x0, 0x14, 0x5, intr_data_ptr[PIRQ_C]); /* PCI slots */ struct device *dev = pcidev_on_root(0x14, 4); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); + /* PCI slot 0 */ + PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); + PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); } - /* PCIe Lan */ - PCI_INT(0x0, 0x06, 0x0, 0x13); + /* Southbridge PCIe Port 1: 0:15.00 - IRQ 4 */ + PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_B]); + /* Southbridge PCIe Port 2: 0:15.01 - IRQ 5 */ + PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_C]); + /* Southbridge PCIe Port 3: 0:15.02 - IRQ 7 */ + PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_D]); + /* Southbridge PCIe Port 4: 0:15.03 - IRQ 3 */ + PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_A]); - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); + /* Discrete Graphics (dGPU) 1:00.00 behind a 0:02.00 PCIe GPP - IRQ 3 */ + PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_A]); + PCI_INT(0x1, 0x0, 0x1, intr_data_ptr[PIRQ_B]); + PCI_INT(0x1, 0x0, 0x2, intr_data_ptr[PIRQ_C]); + PCI_INT(0x1, 0x0, 0x3, intr_data_ptr[PIRQ_D]); - /* Local Ints: Type IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); + /* 2:00.00 behind a 0:04.00 PCIe GPP - IRQ 3 */ + PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_A]); + PCI_INT(0x2, 0x0, 0x1, intr_data_ptr[PIRQ_B]); + PCI_INT(0x2, 0x0, 0x2, intr_data_ptr[PIRQ_C]); + PCI_INT(0x2, 0x0, 0x3, intr_data_ptr[PIRQ_D]); + + /* 3:00.00 behind a 0:05.00 PCIe GPP - IRQ 4 */ + PCI_INT(0x3, 0x0, 0x0, intr_data_ptr[PIRQ_B]); + PCI_INT(0x3, 0x0, 0x1, intr_data_ptr[PIRQ_C]); + PCI_INT(0x3, 0x0, 0x2, intr_data_ptr[PIRQ_D]); + PCI_INT(0x3, 0x0, 0x3, intr_data_ptr[PIRQ_A]); + + /* Onboard Ethernet (Eth) 4:00.00 behind a 0:06.00 PCIe GPP - IRQ 4 */ + PCI_INT(0x4, 0x0, 0x0, intr_data_ptr[PIRQ_B]); + PCI_INT(0x4, 0x0, 0x1, intr_data_ptr[PIRQ_C]); + PCI_INT(0x4, 0x0, 0x2, intr_data_ptr[PIRQ_D]); + PCI_INT(0x4, 0x0, 0x3, intr_data_ptr[PIRQ_A]); + + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ +#define IO_LOCAL_INT(type, intr, apicid, pin) \ + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)) + + IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); + IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ -- To view, visit https://review.coreboot.org/c/coreboot/+/48424 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9a6ab9e24a828ebaffe87205a2ce0ebd811a935d Gerrit-Change-Number: 48424 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

3 13

Change in coreboot[master]: soc/intel/apl: Add ACPI for SBMBUS control
by Maxim Polyakov (Code Review) 16 Nov '22

16 Nov '22

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44507 ) Change subject: soc/intel/apl: Add ACPI for SBMBUS control ...................................................................... soc/intel/apl: Add ACPI for SBMBUS control Based on acpidump from AMI firmware on the Kontron mAL10 COMe module and SMBus Control Methods Interface Specification, Ver 1.0, 1999. Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> Change-Id: I3846266d3155bbe831123fef4751748ff0e00511 --- A src/soc/intel/apollolake/acpi/smbus.asl M src/soc/intel/apollolake/acpi/southbridge.asl 2 files changed, 795 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/44507/1 diff --git a/src/soc/intel/apollolake/acpi/smbus.asl b/src/soc/intel/apollolake/acpi/smbus.asl new file mode 100644 index 0000000..b41c0f2 --- /dev/null +++ b/src/soc/intel/apollolake/acpi/smbus.asl @@ -0,0 +1,792 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device (SBUS) +{ + /* Intel SMBus Controller 0:1f.1 */ + Name (_ADR, 0x001F0001) + + OperationRegion (SMBP, PCI_Config, 0x40, 0xC0) + Field (SMBP, DWordAcc, NoLock, Preserve) + { + , 2, + I2CE, 1 + } + + OperationRegion (SMPB, PCI_Config, 0x20, 0x04) + Field (SMPB, DWordAcc, NoLock, Preserve) + { + , 5, + SBAR, 11 + } + + OperationRegion (SMBI, SystemIO, (SBAR << 0x05), 0x10) + Field (SMBI, ByteAcc, NoLock, Preserve) + { + HSTS, 8, // Host Status + Offset (0x02), + HCON, 8, // Host Control + HCOM, 8, // Host Command + TXSA, 8, // Transmit Slave Address + DAT0, 8, // Host Data 0 + DAT1, 8, // Host Data 1 + HBDR, 8, // Host Block Data Byte + PECR, 8, // Packet Error Check + RXSA, 8, // Receive Slave Data + SDAT, 16 + } + + // SMBus Send Byte + // Arg0: Address + // Arg1: Data + // Return: 1 = Success, 0=Failure + Method (SSXB, 2, Serialized) + { + If (STRT ()) + { // Is the SMBus Controller Ready? + Return (Zero) + } + + // Send Byte + // SMBus Enable + I2CE = Zero + HSTS = 0xBF + TXSA = Arg0 // Write Address + HCOM = Arg1 // Write Data + HCON = 0x48 // Start + Byte Data Protocol + If (COMP ()) + { + HSTS |= 0xFF // Clean up + Return (One) // Success + } + + Return (Zero) + } + + // SMBus Receive Byte + // Arg0: Address + // Return: 0xffff = Failure, Data (8bit) = Success + Method (SRXB, 1, Serialized) + { + // Is the SMBus Controller Ready? + If (STRT ()) + { + Return (0xFFFF) + } + + // Receive Byte + I2CE = Zero // SMBus Enable + HSTS = 0xBF + TXSA = (Arg0 | One) // Write Address + HCON = 0x44 + If (COMP ()) + { + HSTS |= 0xFF // Clean up + Return (DAT0) // Success + } + + Return (0xFFFF) + } + + // SMBus Write Byte + // Arg0: Address + // Arg1: Command + // Arg2: Data + // Return: 1 = Success, 0=Failure + Method (SWRB, 3, Serialized) + { + If (STRT ()) + { // Is the SMBus Controller Ready? + Return (Zero) + } + + I2CE = Zero // SMBus Enable + HSTS = 0xBF + TXSA = Arg0 // Write Address + HCOM = Arg1 // Write Command + DAT0 = Arg2 // Write Data + HCON = 0x48 // Start + Byte Protocol + If (COMP ()) + { + HSTS |= 0xFF // Clean up + Return (One) // Success + } + + Return (Zero) + } + + // SMBus Read Byte + // Arg0: Address + // Arg1: Command + // Return: 0xffff = Failure, Data (8bit) = Success + Method (SRDB, 2, Serialized) + { + If (STRT ()) + { // Is the SMBus Controller Ready? + Return (0xFFFF) + } + + I2CE = Zero // SMBus Enable + HSTS = 0xBF + // Write Address + TXSA = (Arg0 | One) + HCOM = Arg1 // Command + HCON = 0x48 // Start + If (COMP ()) + { + HSTS |= 0xFF // Clean up + Return (DAT0) // Success + } + + Return (0xFFFF) + } + + // SWRW - write word + // Arg0: Address + // Arg1: Command + // Arg2: Data + // Return: 0 on failure, 1, on success + Method (SWRW, 3, Serialized) + { + If (STRT ()) + { + Return (Zero) + } + + I2CE = Zero + HSTS = 0xBF + TXSA = Arg0 + HCOM = Arg1 + DAT1 = (Arg2 & 0xFF) + DAT0 = ((Arg2 >> 0x08) & 0xFF) + HCON = 0x4C + If (COMP ()) + { + HSTS |= 0xFF + Return (One) + } + + Return (Zero) + } + + // SRDW - read word + // Arg0: Address + // Arg1: Command + // Return: 0xffffffff on failure, the read word otherwise + Method (SRDW, 2, Serialized) + { + If (STRT ()) + { + Return (0xFFFF) + } + + I2CE = Zero + HSTS = 0xBF + TXSA = (Arg0 | One) + HCOM = Arg1 + HCON = 0x4C + If (COMP ()) + { + HSTS |= 0xFF + Return (((DAT0 << 0x08) | DAT1)) + } + + Return (0xFFFFFFFF) + } + + // SBLW - write block data + // Arg0: Address + // Arg1: Command + // Arg2: Data - data[0] is the number of bytes that follow + // Return: 0 on failure, 1, on success + Method (SBLW, 4, Serialized) + { + If (STRT ()) + { + Return (Zero) + } + + I2CE = Arg3 + HSTS = 0xBF + TXSA = Arg0 + HCOM = Arg1 + DAT0 = SizeOf (Arg2) + Local1 = Zero + HBDR = DerefOf (Arg2 [Zero]) + HCON = 0x54 + While ((SizeOf (Arg2) > Local1)) + { + Local0 = 0x0FA0 + While ((!(HSTS & 0x80) && Local0)) + { + Local0-- + Stall (0x32) + } + + If (!Local0) + { + KILL () + Return (Zero) + } + + HSTS = 0x80 + Local1++ + If ((SizeOf (Arg2) > Local1)) + { + HBDR = DerefOf (Arg2 [Local1]) + } + } + + If (COMP ()) + { + HSTS |= 0xFF + Return (One) + } + + Return (Zero) + } + + // SBLR - read block data + // Arg0: Address + // Arg1: Command + // Return: 0 on failure, the read data otherwise + Method (SBLR, 3, Serialized) + { + Name (TBUF, Buffer (0x0100){}) + If (STRT ()) + { + Return (Zero) + } + + I2CE = Arg2 + HSTS = 0xBF + TXSA = (Arg0 | One) + HCOM = Arg1 + HCON = 0x54 + Local0 = 0x0FA0 + While ((!(HSTS & 0x80) && Local0)) + { + Local0-- + Stall (0x32) + } + + If (!Local0) + { + KILL () + Return (Zero) + } + + TBUF [Zero] = DAT0 /* \_SB_.PCI0.SBUS.DAT0 */ + HSTS = 0x80 + Local1 = One + While ((Local1 < DerefOf (TBUF [Zero]))) + { + Local0 = 0x0FA0 + While ((!(HSTS & 0x80) && Local0)) + { + Local0-- + Stall (0x32) + } + + If (!Local0) + { + KILL () + Return (Zero) + } + + TBUF [Local1] = HBDR /* \_SB_.PCI0.SBUS.HBDR */ + HSTS = 0x80 + Local1++ + } + + If (COMP ()) + { + HSTS |= 0xFF + Return (TBUF) /* \_SB_.PCI0.SBUS.SBLR.TBUF */ + } + + Return (Zero) + } + + // Wait for SMBus to become ready + Method (STRT, 0, Serialized) + { + // Timeout 200ms + Local0 = 0xC8 + + While (Local0) + { + If ((HSTS & 0x40)) + { // Is used? + // timeout-- + Local0-- + + // Wait 1ms + Sleep (One) + If ((Local0 == Zero)) + { + Return (One) + } + } + Else + { + // We're ready + Local0 = Zero + } + } + + // Timeout 200ms (50us * 4000) + Local0 = 0x0FA0 + While (Local0) + { + If ((HSTS & One)) + { // Is the host busy? + // timeout-- + Local0-- + + // Wait 50us + Stall (0x32) + + If ((Local0 == Zero)) + { + KILL () + } + } + Else + { // Success + Return (Zero) + } + } + // Failure + Return (One) + } + + // Check if last operation completed + // return Failure = 0, Success = 1 + Method (COMP, 0, Serialized) + { + Local0 = 0x0FA0 // Timeout 200ms in 50us steps + While (Local0) + { + If ((HSTS & 0x02)) + { // Completion Status? + // Operation Completed + Return (One) + } + Else + { + Local0-- + Stall (0x32) + If ((Local0 == Zero)) + { + KILL () + } + } + } + Return (Zero) // Failure + } + + // Kill all SMBus communication + Method (KILL, 0, Serialized) + { + HCON |= 0x02 // Send Kill + HSTS |= 0xFF // Clean Status + } + + // SMBus transactional synchronization + Mutex (SBX0, 0x00) + + OperationRegion (SBU0, SystemIO, (SBAR << 0x05), 0x10) + Field (SBU0, ByteAcc, NoLock, Preserve) + { + HSTA, 8, + Offset (0x02), + HCNT, 8, + HCMD, 8, + HADD, 8, + HDT0, 8, + HDT1, 8, + BLKD, 8, + Offset (0x0D), + AUCT, 8 + } + + // SWTC - Wait for Transaction Complete + // Wait until the previous SMBus transaction has completed + // Arg0 : Timeout Value + // return + // 0x00 : OK + // 0x07 : Unknown Failure + // 0x10 : Address Not Acknowledged + // 0x11 : Device Error + // 0x12 : Command Access Denied + // 0x13 : Unknown Error + // 0x17 : Device Access Denied + // 0x18 : Timeout + // 0x19 : Unsupported Protocol + // 0x1A : Bus Busy + // 0x1F : PEC (CRC-8) Error + Method (SWTC, 1, NotSerialized) + { + Local0 = Arg0 + Local2 = 0x07 + // The previous command has completed when the protocol + // register is equal to 0 (zero). Wait <timeout> ms + // for this to occur. + Local1 = One + While ((Local1 == One)) + { + Local3 = (HSTA & 0x1E) + If ((Local3 != Zero)) + { + If ((Local3 == 0x02)) + { + Local2 = Zero + } + Else + { + Local2 = 0x07 + } + + Local1 = Zero + } + // Transaction isn't complete. Check for timeout, and if not, + // sleep 10ms and loop again. + ElseIf ((Local0 < 0x0A)) + { + Local2 = 0x18 // ERROR: Timeout occurred. + Local1 = Zero // Terminate loop. + } + Else + { + Sleep (0x0A) + Local0 -= 0x0A + } + } + Return (Local2) + } + + // SBR - SMBus Read + // Arg0 : Protocol (Integer) + // Arg1 : Slave Address (Integer) + // Arg2 : Command (Integer) + // return + // (0) : Status (Integer) + // (1) : Data Length (Integer) + // (2) : Data (Integer | Buffer) + Method (SBR, 3, Serialized) + { + I2CE = Zero + Local0 = Package (0x12) + { + 0x07, + Zero, + Zero, + Zero, + Zero, + Zero, + Zero, + Zero, + Zero, + Zero, + Zero, + Zero, + Zero, + Zero, + Zero, + Zero, + Zero, + Zero + } + + // Make sure the protocol is valid, if not return the + // 'invalid protocol' status code. Note that this segment + // does not support packet error checking. + If ((Arg0 != 0x03)) + { // Read Quick + If ((Arg0 != 0x05)) + { // Receive Byte + If ((Arg0 != 0x07)) + { // Read Byte + If ((Arg0 != 0x09)) + { // Read Word + If ((Arg0 != 0x0B)) + { // Read Block + Local0 [Zero] = 0x19 + Return (Local0) + } + } + } + } + } + + // Acquire the SMBus mutex to ensure transactional synchronization. + If ((Acquire (SBX0, 0xFFFF) == Zero)) + { + // Initiate the transaction by writing the slave address, + // command, and protocol registers. Note that the command + // code and data length are always written, even if the + // protocol doesn't require it (it + // will be ignored). + HSTA = (HSTA | 0xFF) + HADD = (Arg1 | One) + HCMD = Arg2 + If ((Arg0 == 0x03)) + { // Read Quick + HCNT = ((HCNT & 0xA0) | 0x40) + } + + If ((Arg0 == 0x05)) + { // Receive Byte + HCNT = ((HCNT & 0xA0) | 0x44) + } + + If ((Arg0 == 0x07)) + { // Read Byte + HCNT = ((HCNT & 0xA0) | 0x48) + } + + If ((Arg0 == 0x09)) + { // Read Word + HCNT = ((HCNT & 0xA0) | 0x4C) + } + + If ((Arg0 == 0x0B)) + { // Read Block + AUCT &= 0xFD + HCNT = ((HCNT & 0xA0) | 0x54) + Local1 = Zero + } + Else + { + // Wait for completion + Local1 = SWTC (0x03E8) + } + + // Save the status code, data size, and data into the return + // package (if required by the protocol). + Local0 [Zero] = Local1 + If ((Local1 == Zero)) + { + If ((Arg0 == 0x05)) + { // Receive Byte + Local0 [One] = One + Local0 [0x02] = HDT0 + } + + If ((Arg0 == 0x07)) + { // Read Byte + Local0 [One] = One + Local0 [0x02] = HDT0 + } + + If ((Arg0 == 0x09)) + { // Read Word + Local0 [One] = 0x02 + Local2 = HDT1 + Local2 <<= 0x08 + Local2 += HDT0 + Local0 [0x02] = Local2 + } + + If ((Arg0 == 0x0B)) + { // Read Block + Local0 [Zero] = 0x07 + Local4 = 0x9C40 + While ((!(HSTA & 0x80) && Local4)) + { + Local4-- + Stall (0x32) + } + + If (!Local4) + { + HCNT |= 0x02 + HSTA |= 0xFF + Local0 [Zero] = 0x17 + Release (SBX0) + Return (Local0) + } + + Local0 [Zero] = Zero + Local2 = HDT0 + If ((Local2 > 0x10)) + { + Local2 = 0x10 + } + + Local0 [One] = Local2 + Local0 [0x02] = BLKD + Local3 = 0x03 + HSTA = 0x80 + While ((Local3 < (Local2 + 0x02))) + { + Local4 = 0x9C40 + While ((!(HSTA & 0x80) && Local4)) + { + Local4-- + Stall (0x32) + } + + If (!Local4) + { + HCNT |= 0x02 + HSTA |= 0xFF + Local0 [Zero] = 0x18 + Release (SBX0) + Return (Local0) + } + + Local0 [Local3] = BLKD + HSTA = 0x80 + Local3++ + } + } + } + + Release (SBX0) + } + + Return (Local0) + } + + // _SBW - SMBus Write + // + // Arg0 : Protocol Value (Integer) + // Arg1 : Slave Address (Integer) + // Arg2 : Command Code (Integer) + // Arg3 : Data Length (Integer) + // Arg4 : Data (Integer | Buffer) + // + // return Value (Package): + // (0) : Status (Integer) + Method (SBW, 5, Serialized) + { + I2CE = Zero + // Local0 is the return package. The status code is defaulted + // to 'unknown failure' (0x07). + Local0 = Package (0x01) + { + 0x07 + } + + // Make sure the protocol is valid, if not return the + // 'invalid protocol' status code. Note that this segment + // does not support packet error checking or the 'process call' + // protocol. + If ((Arg0 != 0x02)) + { // Write Quick + If ((Arg0 != 0x04)) + { // Send Byte + If ((Arg0 != 0x06)) + { // Write Byte + If ((Arg0 != 0x08)) + { // Write Word + If ((Arg0 != 0x0A)) + { // Write Block + Local0 [Zero] = 0x19 + Return (Local0) + } + } + } + } + } + + // Acquire the SMBus mutex to ensure transactional synchronization. + If ((Acquire (SBX0, 0xFFFF) == Zero)) + { + HSTA = (HSTA | 0xFF) + HADD = (Arg1 & 0xFE) + HCMD = Arg2 + If ((Arg0 == 0x02)) + { // Write Quick + HCNT = ((HCNT & 0xA0) | 0x40) + } + + If ((Arg0 == 0x04)) + { // Send Byte + HCNT = ((HCNT & 0xA0) | 0x44) + } + + If ((Arg0 == 0x06)) + { // Write Byte + HDT0 = Arg4 + HCNT = ((HCNT & 0xA0) | 0x48) + } + + If ((Arg0 == 0x08)) + { // Write Word + HDT0 = (Arg4 & 0xFF) + HDT1 = (Arg4 >> 0x08) + HCNT = ((HCNT & 0xA0) | 0x4C) + } + + If ((Arg0 == 0x0A)) + { // Write Block + If ((Arg3 > 0x10)) + { + Local0 [Zero] = 0x12 + Release (SBX0) + Return (Local0) + } + + If ((Arg3 == Zero)) + { + Local0 [Zero] = 0x12 + Release (SBX0) + Return (Local0) + } + + AUCT &= 0xFD + HDT0 = Arg3 + Local3 = One + BLKD = DerefOf (Arg4 [Zero]) + HCNT = ((HCNT & 0x80) | 0x54) + While ((Arg3 > Local3)) + { + Local4 = 0x9C40 + While ((!(HSTA & 0x80) && Local4)) + { + Local4-- + Stall (0x32) + } + + If (!Local4) + { + HCNT |= 0x02 + HSTA |= 0xFF + Local0 [Zero] = 0x18 + Release (SBX0) + Return (Local0) + } + + BLKD = DerefOf (Arg4 [Local3]) + Local3++ + HSTA = 0x80 + } + + Local4 = 0x9C40 + While ((!(HSTA & 0x80) && Local4)) + { + Local4-- + Stall (0x32) + } + + If (!Local4) + { + HCNT |= 0x02 + HSTA |= 0xFF + Local0 [Zero] = 0x18 + Release (SBX0) + Return (Local0) + } + + HSTA = 0x80 + } + + Local0 [Zero] = SWTC (0x03E8) + Release (SBX0) + } + + Return (Local0) + } +} diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl index f4d1497..9a5a5ec 100644 --- a/src/soc/intel/apollolake/acpi/southbridge.asl +++ b/src/soc/intel/apollolake/acpi/southbridge.asl @@ -20,6 +20,9 @@ /* LPC */ #include <soc/intel/common/block/acpi/acpi/lpc.asl> +/* SMBus 0:1f.1 */ +#include "smbus.asl" + /* eMMC */ #include "scs.asl" -- To view, visit https://review.coreboot.org/c/coreboot/+/44507 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3846266d3155bbe831123fef4751748ff0e00511 Gerrit-Change-Number: 44507 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

7 16

Change in ...coreboot[master]: soc/intel/common/block/pcr: Remove unneded 'esle'
by HAOUAS Elyes (Code Review) 14 Nov '22

14 Nov '22

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33336 Change subject: soc/intel/common/block/pcr: Remove unneded 'esle' ...................................................................... soc/intel/common/block/pcr: Remove unneded 'esle' 'else' is not needed after a 'break' or 'return'. Change-Id: Ib3371ef6edb85a47ed734dd2ff9ce94008aa4e65 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/common/block/pcr/pcr.c 1 file changed, 3 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/33336/1 diff --git a/src/soc/intel/common/block/pcr/pcr.c b/src/soc/intel/common/block/pcr/pcr.c index 4a35a03..f3971c2 100644 --- a/src/soc/intel/common/block/pcr/pcr.c +++ b/src/soc/intel/common/block/pcr/pcr.c @@ -394,10 +394,9 @@ break; } return 0; - } else { - printk(BIOS_ERR, "SBI Failure: Transaction Status = %x\n", - *response); - return -1; } + printk(BIOS_ERR, "SBI Failure: Transaction Status = %x\n", + *response); + return -1; } #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/33336 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib3371ef6edb85a47ed734dd2ff9ce94008aa4e65 Gerrit-Change-Number: 33336 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

5 6

Change in ...coreboot[master]: src/Kconfig: Move DRAM section to 'Devices' menu
by HAOUAS Elyes (Code Review) 14 Nov '22

14 Nov '22

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32882 Change subject: src/Kconfig: Move DRAM section to 'Devices' menu ...................................................................... src/Kconfig: Move DRAM section to 'Devices' menu This moves DRAM to 'Devices' menu and allow to change default DIMM_MAX value if needed. Change-Id: I7aa5436c6ff5fef53fde2081e902d793f3581c1e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/Kconfig M src/device/Kconfig 2 files changed, 24 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/32882/1 diff --git a/src/Kconfig b/src/Kconfig index 2c9dc4a..d30aa99 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1158,31 +1158,6 @@ implies configurability usually found on SoCs, particularly the ability to control internal pull resistors. -config GENERIC_SPD_BIN - bool - help - If enabled, add support for adding spd.hex files in cbfs as spd.bin - and locating it runtime to load SPD. Additionally provide provision to - fetch SPD over SMBus. - -config DIMM_MAX - int - default 4 - help - Total number of memory DIMM slots available on motherboard. - It is multiplication of number of channel to number of DIMMs per - channel - -config DIMM_SPD_SIZE - int - default 256 - help - Total SPD size that will be used for DIMM. - Ex: DDR3 256, DDR4 512. - -config SPD_READ_BY_WORD - bool - config BOOTBLOCK_CUSTOM # To be selected by arch, SoC or mainboard if it does not want use the normal # src/lib/bootblock.c#main() C entry point. diff --git a/src/device/Kconfig b/src/device/Kconfig index 0539062..d4cacec 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -681,5 +681,29 @@ be useful for debugging or on platforms where a driver for the real I2C controller is not (yet) available. The platform code needs to provide bindings to manually toggle I2C lines. +config GENERIC_SPD_BIN + bool + help + If enabled, add support for adding spd.hex files in cbfs as spd.bin + and locating it runtime to load SPD. Additionally provide provision to + fetch SPD over SMBus. + +config DIMM_MAX + int "Total number of memory DIMM slots" + default 4 + help + Total number of memory DIMM slots available on motherboard. + It is multiplication of number of channel to number of DIMMs per + channel + +config DIMM_SPD_SIZE + int + default 256 + help + Total SPD size that will be used for DIMM. + Ex: DDR3 256, DDR4 512. + +config SPD_READ_BY_WORD + bool endmenu -- To view, visit https://review.coreboot.org/c/coreboot/+/32882 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7aa5436c6ff5fef53fde2081e902d793f3581c1e Gerrit-Change-Number: 32882 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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