coreboot-gerrit April 2023

coreboot-gerrit@coreboot.org

1 participants
5752 discussions

Change in coreboot[master]: soc/intel/broadwell: Add ACPI CIDs for SerialIO devices
by Angel Pons (Code Review) 14 Apr '24

14 Apr '24

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46973 ) Change subject: soc/intel/broadwell: Add ACPI CIDs for SerialIO devices ...................................................................... soc/intel/broadwell: Add ACPI CIDs for SerialIO devices Lynxpoint has them, so add them on Broadwell as well. Change-Id: Iaa3e8044090262a64e58062ec4b116976978ce55 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/pch/acpi/serialio.asl 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/46973/1 diff --git a/src/soc/intel/broadwell/pch/acpi/serialio.asl b/src/soc/intel/broadwell/pch/acpi/serialio.asl index 2bacd2b..1e6dbac 100644 --- a/src/soc/intel/broadwell/pch/acpi/serialio.asl +++ b/src/soc/intel/broadwell/pch/acpi/serialio.asl @@ -166,6 +166,7 @@ // LynxPoint-LP Return ("INT33C2") } + Name (_CID, "INT33C2") Name (_UID, 1) Name (SSCN, Package () { 432, 507, 30 }) @@ -242,6 +243,7 @@ // LynxPoint-LP Return ("INT33C3") } + Name (_CID, "INT33C3") Name (_UID, 1) Name (SSCN, Package () { 432, 507, 30 }) @@ -318,6 +320,7 @@ // LynxPoint-LP Return ("INT33C0") } + Name (_CID, "INT33C0") Name (_UID, 1) // BAR0 is assigned during PCI enumeration and saved into NVS @@ -379,6 +382,7 @@ // LynxPoint-LP Return ("INT33C1") } + Name (_CID, "INT33C1") Name (_UID, 1) // BAR0 is assigned during PCI enumeration and saved into NVS @@ -452,6 +456,7 @@ // LynxPoint-LP Return ("INT33C4") } + Name (_CID, "INT33C4") Name (_UID, 1) // BAR0 is assigned during PCI enumeration and saved into NVS @@ -525,6 +530,7 @@ // LynxPoint-LP Return ("INT33C5") } + Name (_CID, "INT33C5") Name (_UID, 1) // BAR0 is assigned during PCI enumeration and saved into NVS -- To view, visit https://review.coreboot.org/c/coreboot/+/46973 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa3e8044090262a64e58062ec4b116976978ce55 Gerrit-Change-Number: 46973 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: soc/intel/broadwell/pch/sata.c: Add missing SATA init steps
by Angel Pons (Code Review) 13 Apr '24

13 Apr '24

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47029 ) Change subject: soc/intel/broadwell/pch/sata.c: Add missing SATA init steps ...................................................................... soc/intel/broadwell/pch/sata.c: Add missing SATA init steps WildcatPoint-LP BIOS spec lists them, and are the same for Lynxpoint. Keep the BWG comments for now, since both platforms will be merged soon. Change-Id: Iba28c1591affafeb37097084c2fa58128974bd00 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/pch/sata.c 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/47029/1 diff --git a/src/soc/intel/broadwell/pch/sata.c b/src/soc/intel/broadwell/pch/sata.c index 91c2ff5..e9d70f1 100644 --- a/src/soc/intel/broadwell/pch/sata.c +++ b/src/soc/intel/broadwell/pch/sata.c @@ -95,6 +95,15 @@ /* Setup register 98h */ reg32 = pci_read_config32(dev, 0x98); + reg32 |= 1 << 19; /* BWG step 6 */ + reg32 |= 1 << 22; /* BWG step 5 */ + reg32 &= ~(0x3f << 7); + reg32 |= 0x04 << 7; /* BWG step 7 */ + reg32 |= 1 << 20; /* BWG step 8 */ + reg32 &= ~(0x03 << 5); + reg32 |= 1 << 5; /* BWG step 9 */ + reg32 |= 1 << 18; /* BWG step 10 */ + reg32 |= 1 << 29; /* BWG step 11 */ reg32 &= ~((1 << 31) | (1 << 30)); reg32 |= 1 << 23; reg32 |= 1 << 24; /* Enable MPHY Dynamic Power Gating */ -- To view, visit https://review.coreboot.org/c/coreboot/+/47029 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iba28c1591affafeb37097084c2fa58128974bd00 Gerrit-Change-Number: 47029 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 14

Change in coreboot[master]: sb/intel/lynxpoint/lpc.c: Follow Broadwell's order
by Angel Pons (Code Review) 11 Apr '24

11 Apr '24

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47046 ) Change subject: sb/intel/lynxpoint/lpc.c: Follow Broadwell's order ...................................................................... sb/intel/lynxpoint/lpc.c: Follow Broadwell's order Change-Id: Ibddac69297fd7ae901cde92d66e6c0485b526da1 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/lpc.c 1 file changed, 35 insertions(+), 35 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/47046/1 diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 1845273..d1780fa 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -190,7 +190,6 @@ u16 reg16; u32 reg32; const char *state; - u16 pmbase = get_pmbase(); int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; int nmi_option; @@ -232,26 +231,6 @@ pci_write_config16(dev, GEN_PMCON_3, reg16); printk(BIOS_INFO, "Set power %s after power failure.\n", state); - /* Set up NMI on errors. */ - reg8 = inb(0x61); - reg8 &= 0x0f; /* Higher Nibble must be 0 */ - reg8 &= ~(1 << 3); /* IOCHK# NMI Enable */ - // reg8 &= ~(1 << 2); /* PCI SERR# Enable */ - reg8 |= (1 << 2); /* PCI SERR# Disable for now */ - outb(reg8, 0x61); - - reg8 = inb(0x70); - nmi_option = NMI_OFF; - get_option(&nmi_option, "nmi"); - if (nmi_option) { - printk(BIOS_INFO, "NMI sources enabled.\n"); - reg8 &= ~(1 << 7); /* Set NMI. */ - } else { - printk(BIOS_INFO, "NMI sources disabled.\n"); - reg8 |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */ - } - outb(reg8, 0x70); - /* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */ reg16 = pci_read_config16(dev, GEN_PMCON_1); reg16 &= ~(3 << 0); // SMI# rate 1 minute @@ -275,6 +254,11 @@ /* SMI setup based on device tree configuration */ enable_alt_smi(config->alt_gp_smi_en); } +} + +static void pch_misc_init(struct device *dev) +{ + u16 pmbase = get_pmbase(); /* Set up power management block and determine sleep mode */ reg32 = inl(pmbase + 0x04); // PM1_CNT @@ -282,12 +266,40 @@ reg32 |= (1 << 0); // SCI_EN outl(reg32, pmbase + 0x04); + /* Set up NMI on errors. */ + reg8 = inb(0x61); + reg8 &= 0x0f; /* Higher Nibble must be 0 */ + reg8 &= ~(1 << 3); /* IOCHK# NMI Enable */ + // reg8 &= ~(1 << 2); /* PCI SERR# Enable */ + reg8 |= (1 << 2); /* PCI SERR# Disable for now */ + outb(reg8, 0x61); + + reg8 = inb(0x70); + nmi_option = NMI_OFF; + get_option(&nmi_option, "nmi"); + if (nmi_option) { + printk(BIOS_INFO, "NMI sources enabled.\n"); + reg8 &= ~(1 << 7); /* Set NMI. */ + } else { + printk(BIOS_INFO, "NMI sources disabled.\n"); + reg8 |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */ + } + outb(reg8, 0x70); + + /* Indicate DRAM init done for MRC S3 to know it can resume */ + pci_or_config8(dev, GEN_PMCON_2, 1 << 7); + + /* Enable BIOS updates outside of SMM */ + pci_and_config8(dev, BIOS_CNTL, ~(1 << 5)); + /* Clear magic status bits to prevent unexpected wake */ RCBA32_OR(0x3310, (1 << 4) | (1 << 5) | (1 << 0)); reg16 = RCBA16(0x3f02); reg16 &= ~0xf; RCBA16(0x3f02) = reg16; + + pch_enable_serial_irqs(dev); } /* LynxPoint PCH Power Management init */ @@ -461,18 +473,8 @@ apm_control(APM_CNT_ACPI_DISABLE); } -static void pch_disable_smm_only_flashing(struct device *dev) -{ - printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... "); - - pci_and_config8(dev, BIOS_CNTL, ~(1 << 5)); -} - static void pch_fixups(struct device *dev) { - /* Indicate DRAM init done for MRC S3 to know it can resume */ - pci_or_config8(dev, GEN_PMCON_2, 1 << 7); - /* * Enable DMI ASPM in the PCH */ @@ -488,14 +490,14 @@ /* IO APIC initialization. */ pch_enable_ioapic(dev); - pch_enable_serial_irqs(dev); - /* Setup the PIRQ. */ pch_pirq_init(dev); /* Setup power options. */ pch_power_options(dev); + pch_misc_init(dev); + /* Initialize power management */ if (pch_is_lp()) { lpt_lp_pm_init(dev); @@ -519,8 +521,6 @@ /* Interrupt 9 should be level triggered (SCI) */ i8259_configure_irq_trigger(9, 1); - pch_disable_smm_only_flashing(dev); - pch_set_acpi_mode(); pch_fixups(dev); -- To view, visit https://review.coreboot.org/c/coreboot/+/47046 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibddac69297fd7ae901cde92d66e6c0485b526da1 Gerrit-Change-Number: 47046 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: [UNTESTED] sb/intel/bd82x6x: Replace `write_iobp`
by Angel Pons (Code Review) 11 Apr '24

11 Apr '24

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49177 ) Change subject: [UNTESTED] sb/intel/bd82x6x: Replace `write_iobp` ...................................................................... [UNTESTED] sb/intel/bd82x6x: Replace `write_iobp` Use the already-existing `pch_iobp_update` function instead. Only update individual fields, like reference code does. Several replay issues still remain, and have been marked with comments. Follow-ups will handle them. Change-Id: I5b95134a504d693f8e6f2df35784bf75037b7b16 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/early_pch.c 1 file changed, 71 insertions(+), 94 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/49177/1 diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index 903dc01..0b60d13 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -16,41 +16,6 @@ #include "pch.h" #include "chip.h" -static void wait_iobp(void) -{ - while (RCBA8(IOBPS) & 1) - ; // implement timeout? -} - -static u32 read_iobp(u32 address) -{ - u32 ret; - - RCBA32(IOBPIRI) = address; - RCBA16(IOBPS) = (RCBA16(IOBPS) & 0x1ff) | 0x600; - wait_iobp(); - ret = RCBA32(IOBPD); - wait_iobp(); - RCBA8(IOBPS); // call wait_iobp() instead here? - return ret; -} - -static void write_iobp(u32 address, u32 val) -{ - /* this function was probably pch_iobp_update with the andvalue - * being 0. So either the IOBP read can be removed or this function - * and the pch_iobp_update function in ramstage could be merged */ - read_iobp(address); - RCBA16(IOBPS) = (RCBA16(IOBPS) & 0x1ff) | 0x600; - wait_iobp(); - - RCBA32(IOBPD) = val; - wait_iobp(); - RCBA16(IOBPS) = (RCBA16(IOBPS) & 0x1ff) | 0x600; - - RCBA8(IOBPS); // call wait_iobp() instead here? -} - void early_pch_init_native_dmi_pre(void) { /* Link Capabilities Register */ @@ -184,67 +149,79 @@ pch_assign_pcie_lane_mapping(); - write_iobp(0xea007f62, 0x00590133); - write_iobp(0xec007f62, 0x00590133); - write_iobp(0xec007f64, 0x59555588); - write_iobp(0xea0040b9, 0x0001051c); - write_iobp(0xeb0040a1, 0x800084ff); - write_iobp(0xec0040a1, 0x800084ff); - write_iobp(0xea004001, 0x00008400); - write_iobp(0xeb004002, 0x40201758); - write_iobp(0xec004002, 0x40201758); - write_iobp(0xea004002, 0x00601758); - write_iobp(0xea0040a1, 0x810084ff); - write_iobp(0xeb0040b1, 0x0001c598); - write_iobp(0xec0040b1, 0x0001c598); - write_iobp(0xeb0040b6, 0x0001c598); - write_iobp(0xea0000a9, 0x80ff969f); - write_iobp(0xea0001a9, 0x80ff969f); - write_iobp(0xeb0040b2, 0x0001c396); - write_iobp(0xeb0040b3, 0x0001c396); - write_iobp(0xec0040b2, 0x0001c396); - write_iobp(0xea0001a9, 0x80ff94ff); - write_iobp(SATA_IOBP_SP0G3IR, 0x0088037f); - write_iobp(0xea0000a9, 0x80ff94ff); - write_iobp(SATA_IOBP_SP1G3IR, 0x0088037f); + pch_iobp_update(0xea007f62, ~(0xff << 16), 0x59 << 16); + pch_iobp_update(0xec007f62, ~(0xff << 16), 0x59 << 16); + pch_iobp_update(0xec007f64, ~(0xf << 24), 0x9 << 24); + pch_iobp_update(0xea0040b9, ~0xffff, 0x051c); + pch_iobp_update(0xeb0040a1, ~(0x3ff << 3), 0x9f << 3); + pch_iobp_update(0xec0040a1, ~(0x3ff << 3), 0x9f << 3); - write_iobp(0xea007f05, 0x00010642); - write_iobp(0xea0040b7, 0x0001c91c); - write_iobp(0xea0040b8, 0x0001c91c); - write_iobp(0xeb0040a1, 0x820084ff); - write_iobp(0xec0040a1, 0x820084ff); - write_iobp(0xea007f0a, 0xc2480000); + /* Some CPT-only writes go here */ - write_iobp(0xec00404d, 0x1ff177f); - write_iobp(0xec000084, 0x5a600000); - write_iobp(0xec000184, 0x5a600000); - write_iobp(0xec000284, 0x5a600000); - write_iobp(0xec000384, 0x5a600000); - write_iobp(0xec000094, 0x000f0501); - write_iobp(0xec000194, 0x000f0501); - write_iobp(0xec000294, 0x000f0501); - write_iobp(0xec000394, 0x000f0501); - write_iobp(0xec000096, 0x00000001); - write_iobp(0xec000196, 0x00000001); - write_iobp(0xec000296, 0x00000001); - write_iobp(0xec000396, 0x00000001); - write_iobp(0xec000001, 0x00008c08); - write_iobp(0xec000101, 0x00008c08); - write_iobp(0xec000201, 0x00008c08); - write_iobp(0xec000301, 0x00008c08); - write_iobp(0xec0040b5, 0x0001c518); - write_iobp(0xec000087, 0x06077597); - write_iobp(0xec000187, 0x06077597); - write_iobp(0xec000287, 0x06077597); - write_iobp(0xec000387, 0x06077597); - write_iobp(0xea000050, 0x00bb0157); - write_iobp(0xea000150, 0x00bb0157); - write_iobp(0xec007f60, 0x77777d77); - write_iobp(0xea00008d, 0x01320000); - write_iobp(0xea00018d, 0x01320000); - write_iobp(0xec0007b2, 0x04514b5e); - write_iobp(0xec00078c, 0x40000200); - write_iobp(0xec000780, 0x02000020); + pch_iobp_update(0xea004001, ~(3 << 10), 1 << 10); + pch_iobp_update(0xeb004002, ~0, 1 << 30 | 1 << 21); + pch_iobp_update(0xec004002, ~0, 1 << 30 | 1 << 21); + pch_iobp_update(0xea004002, ~0, 1 << 22 | 1 << 21); + pch_iobp_update(0xea0040a1, ~0, 1 << 24); + pch_iobp_update(0xeb0040b1, ~0xffff, 0xc598); + pch_iobp_update(0xec0040b1, ~0xffff, 0xc598); + pch_iobp_update(0xeb0040b6, ~0xffff, 0xc598); + pch_iobp_update(0xea0000a9, ~(3 << 14), 2 << 14); + pch_iobp_update(0xea0001a9, ~(3 << 14), 2 << 14); + pch_iobp_update(0xeb0040b2, ~0xffff, 0xc396); + pch_iobp_update(0xeb0040b3, ~0xffff, 0xc396); + pch_iobp_update(0xec0040b2, ~0xffff, 0xc396); + + /* Assumes SATA direct connect, trace length <= 3.5" */ + pch_iobp_update(0xea0001a9, ~(0x3ff << 3), 0x29f << 3); + pch_iobp_update(SATA_IOBP_SP0G3IR, ~(0xff << 16 | 0x3f << 8), 0x88 << 16 | 3 << 8); + pch_iobp_update(0xea0000a9, ~(0x3ff << 3), 0x29f << 3); + pch_iobp_update(SATA_IOBP_SP1G3IR, ~(0xff << 16 | 0x3f << 8), 0x88 << 16 | 3 << 8); + + /* TODO: Needs special handling */ + pch_iobp_update(0xea007f05, 0, 0x00010642); + + pch_iobp_update(0xea0040b7, ~0xffff, 0xc91c); + pch_iobp_update(0xea0040b8, ~0xffff, 0xc91c); + pch_iobp_update(0xeb0040a1, ~0, 1 << 25); + pch_iobp_update(0xec0040a1, ~0, 1 << 25); + pch_iobp_update(0xea007f0a, ~0, 3 << 30); + + /* PPT A0 resume-only xHCI workaround goes here */ + + /* TODO: This section is PPT-only */ + pch_iobp_update(0xec00404d, ~(0xff3f << 8), 0xff17 << 8); + pch_iobp_update(0xec000084, ~(1 << 31), 0); + pch_iobp_update(0xec000184, ~(1 << 31), 0); + pch_iobp_update(0xec000284, ~(1 << 31), 0); + pch_iobp_update(0xec000384, ~(1 << 31), 0); + pch_iobp_update(0xec000094, ~0, 0xf << 16); + pch_iobp_update(0xec000194, ~0, 0xf << 16); + pch_iobp_update(0xec000294, ~0, 0xf << 16); + pch_iobp_update(0xec000394, ~0, 0xf << 16); + pch_iobp_update(0xec000096, ~0x3ff, 1); + pch_iobp_update(0xec000196, ~0x3ff, 1); + pch_iobp_update(0xec000296, ~0x3ff, 1); + pch_iobp_update(0xec000396, ~0x3ff, 1); + pch_iobp_update(0xec000001, ~0, 3 << 10 | 1 << 3); + pch_iobp_update(0xec000101, ~0, 3 << 10 | 1 << 3); + pch_iobp_update(0xec000201, ~0, 3 << 10 | 1 << 3); + pch_iobp_update(0xec000301, ~0, 3 << 10 | 1 << 3); + pch_iobp_update(0xec0040b5, ~0xffff, 0xc518); + pch_iobp_update(0xec000087, ~(0xf << 8), 5 << 8); + pch_iobp_update(0xec000187, ~(0xf << 8), 5 << 8); + pch_iobp_update(0xec000287, ~(0xf << 8), 5 << 8); + pch_iobp_update(0xec000387, ~(0xf << 8), 5 << 8); + pch_iobp_update(0xea000050, ~(0xff << 16), 0xbb << 16); + pch_iobp_update(0xea000150, ~(0xff << 16), 0xbb << 16); + pch_iobp_update(0xec007f60, ~(0xf << 8), 0xd << 8); + pch_iobp_update(0xea00008d, ~0, 3 << 20); + pch_iobp_update(0xea00018d, ~0, 3 << 20); + + /* TODO: Figure out what these writes mean */ + pch_iobp_update(0xec0007b2, 0, 0x04514b5e); + pch_iobp_update(0xec00078c, 0, 0x40000200); + pch_iobp_update(0xec000780, 0, 0x02000020); } static void pch_enable_gbe(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/49177 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b95134a504d693f8e6f2df35784bf75037b7b16 Gerrit-Change-Number: 49177 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: nb/intel/sandybridge: Improve channel disable logic
by Angel Pons (Code Review) 11 Apr '24

11 Apr '24

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45500 ) Change subject: nb/intel/sandybridge: Improve channel disable logic ...................................................................... nb/intel/sandybridge: Improve channel disable logic Do not consider the failed channel's SPDs in emergency mode. Also, force a full training if not resuming from S3 and the saved data indicates a channel has failed. Special care needs to be taken as the selected memory frequency could be raised after a channel has been disabled. Tested on Asus P8Z77-V LX2, with a good DIMM on channel 0 and a bad DIMM on channel 1. The failing channel causes errors when discovering timB, and emergency mode raminit for the other channel is good enough to boot. With this commit: a. Regular boots always result in full training. b. The board still boots, as emergency raminit trained the good DIMM. c. S3 resume still works in all tested configurations. d. If pretending the bad DIMM is slower: 1. The MPLL gets locked at the slow frequency of the bad DIMM. 2. The first raminit attempt still fails miserably on the bad DIMM. 3. Emergency mode uses the frequency the MPLL is locked at. 4. The board boots with the good DIMM running at the slow frequency. With good DIMMs on both channels, everything works the same as before. Change-Id: I3d34594561680906cb0b15a9c6a5fa7a773c0496 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_common.h M src/northbridge/intel/sandybridge/raminit_native.c 3 files changed, 38 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/45500/1 diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 319fea3..51c57c6 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -43,15 +43,7 @@ /* Disable a channel in ramctr_timing */ static void disable_channel(ramctr_timing *ctrl, int channel) { - ctrl->rankmap[channel] = 0; - - memset(&ctrl->rank_mirror[channel][0], 0, sizeof(ctrl->rank_mirror[0])); - - ctrl->channel_size_mb[channel] = 0; - ctrl->cmd_stretch[channel] = 0; - ctrl->mad_dimm[channel] = 0; - memset(&ctrl->timings[channel][0], 0, sizeof(ctrl->timings[0])); - memset(&ctrl->info.dimm[channel][0], 0, sizeof(ctrl->info.dimm[0])); + ctrl->failed_channels |= BIT(channel); } static bool nb_supports_ecc(const uint32_t capid0_a) @@ -163,6 +155,10 @@ FOR_ALL_CHANNELS { ctrl->channel_size_mb[channel] = 0; + /* Skip decoding the SPDs of failed channels */ + if (ctrl->failed_channels & BIT(channel)) + continue; + ch_dimms = 0; /* Count dimms on channel */ for (slot = 0; slot < NUM_SLOTS; slot++) { @@ -345,8 +341,21 @@ system_reset(); } + /* + * Discard the saved data if it is from raminit emergency mode. + * Ideally, we would not advertise support for ACPI S3 in such + * cases, because there is evidence that the RAM has stability + * problems. Until then, skip this sanity check on S3 resumes. + */ + if (!s3resume && ctrl_cached && ctrl_cached->failed_channels) { + printk(BIOS_ERR, "Stored timings indicate channels have failed.\n"); + + ctrl_cached = NULL; + } + /* Verify MRC cache for fast boot */ if (!s3resume && ctrl_cached) { + /* Load SPD unique information data. */ memset(spds, 0, sizeof(spds)); mainboard_get_spd(spds, 1); @@ -391,6 +400,13 @@ } if (err) { + /* + * We can't reinitialize the DRAM MPLL at a different frequency. + * As we want to ignore the SPDs on the failed channel, we have + * to use the same tCK in emergency mode to avoid some troubles. + */ + const u32 old_tCK = ctrl.tCK; + /* Fallback: disable failing channel */ printk(BIOS_ERR, "RAM training failed, trying fallback.\n"); printram("Disable failing channel.\n"); @@ -398,12 +414,15 @@ /* Reset internal state */ reinit_ctrl(&ctrl, cpuid); - /* Reset DDR3 frequency */ - dram_find_spds_ddr3(spds, &ctrl); - /* Disable failing channel */ disable_channel(&ctrl, GET_ERR_CHANNEL(err)); + /* Restore tCK */ + ctrl.tCK = old_tCK; + + /* Recalculate DDR3 frequency */ + dram_find_spds_ddr3(spds, &ctrl); + err = try_init_dram_ddr3(&ctrl, fast_boot, s3resume, me_uma_size); } diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 32f2b44..cf3d6a9 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -105,7 +105,7 @@ /* * WARNING: Do not forget to increase MRC_CACHE_VERSION when the saved data is changed! */ -#define MRC_CACHE_VERSION 5 +#define MRC_CACHE_VERSION 6 typedef struct odtmap_st { u16 rttwr; @@ -185,6 +185,9 @@ /* Bits [0..11] of PM_DLL_CONFIG: Master DLL wakeup delay timer */ u16 mdll_wake_delay; + /* Bitmap of channels that have failed */ + u8 failed_channels; + u8 rankmap[NUM_CHANNELS]; int ref_card_offset[NUM_CHANNELS]; u32 mad_dimm[NUM_CHANNELS]; diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index c23a5ac..a469910 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -265,7 +265,9 @@ printk(BIOS_DEBUG, "PLL_REF100_CFG value: 0x%x\n", ref_100mhz_support); - ctrl->tCK = get_mem_min_tck(); + /* In emergency mode, use provided tCK if non-zero. Otherwise, calculate it. */ + if (!ctrl->failed_channels || !ctrl->tCK) + ctrl->tCK = get_mem_min_tck(); /* Find CAS latency */ while (1) { -- To view, visit https://review.coreboot.org/c/coreboot/+/45500 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d34594561680906cb0b15a9c6a5fa7a773c0496 Gerrit-Change-Number: 45500 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 8

Change in coreboot[master]: [UNTESTED] sb/intel/bd82x6x: Clean up `early_pch_init` function
by Angel Pons (Code Review) 11 Apr '24

11 Apr '24

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49169 ) Change subject: [UNTESTED] sb/intel/bd82x6x: Clean up `early_pch_init` function ...................................................................... [UNTESTED] sb/intel/bd82x6x: Clean up `early_pch_init` function It was being run twice, in both bootblock and romstage. Using Lynxpoint as a reference, reorder the code so that it is only run once. Change-Id: Ia77042c0640929cec05fdd9a9f8c7235fdfe8390 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/bootblock.c M src/southbridge/intel/bd82x6x/early_pch.c M src/southbridge/intel/bd82x6x/pch.h 3 files changed, 37 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/49169/1 diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c index a3228e7..f594a9f 100644 --- a/src/southbridge/intel/bd82x6x/bootblock.c +++ b/src/southbridge/intel/bd82x6x/bootblock.c @@ -3,8 +3,15 @@ #include <arch/bootblock.h> #include <device/pci_ops.h> #include <southbridge/intel/common/early_spi.h> +#include <types.h> + #include "pch.h" +static void map_rcba(void) +{ + pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1); +} + static void enable_port80_on_lpc(void) { /* Enable port 80 POST on LPC */ @@ -33,13 +40,14 @@ void bootblock_early_southbridge_init(void) { + map_rcba(); enable_spi_prefetching_and_caching(); - - early_pch_init(); - enable_port80_on_lpc(); set_spi_speed(); /* Enable upper 128bytes of CMOS */ RCBA32(RC) = (1 << 2); + + pch_enable_lpc_decode(); + mainboard_pch_lpc_setup(); } diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index 6daafe0..f684a96 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -216,26 +216,6 @@ write_iobp(0xec000780, 0x02000020); } -static void pch_enable_bars(void) -{ - pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1); - - pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1); - - pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, ACPI_EN); - - pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); - - /* Enable GPIO functionality. */ - pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); -} - -static void pch_generic_setup(void) -{ - RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ - write_pmbase16(TCO1_CNT, 1 << 11); /* halt timer */ -} - static void pch_enable_gbe(void) { uint8_t wanted_buc; @@ -260,7 +240,27 @@ } } -static void pch_enable_lpc_decode(void) +static void pch_enable_bars(void) +{ + pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1); + + pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1); + + pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, ACPI_EN); + + pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); + + /* Enable GPIO functionality. */ + pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); +} + +static void pch_generic_setup(void) +{ + RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ + write_pmbase16(TCO1_CNT, 1 << 11); /* halt timer */ +} + +void pch_enable_lpc_decode(void) { /* * Enable some common LPC IO ranges: @@ -298,18 +298,13 @@ void early_pch_init(void) { - pch_enable_lpc_decode(); - - mainboard_pch_lpc_setup(); + pch_enable_gbe(); pch_enable_bars(); - pch_generic_setup(); - - pch_enable_gbe(); - setup_pch_gpios(&mainboard_gpio_map); - if (ENV_ROMSTAGE) - enable_smbus(); + pch_generic_setup(); + + enable_smbus(); } diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index dcab839..3b91e31 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -56,6 +56,7 @@ /* Optional mainboard hook to do additional LPC configuration or to override what is set up by default. */ void mainboard_pch_lpc_setup(void); +void pch_enable_lpc_decode(void); void early_pch_init_native(void); void early_pch_init(void); void early_pch_init_native_dmi_pre(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/49169 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia77042c0640929cec05fdd9a9f8c7235fdfe8390 Gerrit-Change-Number: 49169 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: [UNTESTED] sb/intel/bd82x6x: Account for PCH type in IOBP magic
by Angel Pons (Code Review) 11 Apr '24

11 Apr '24

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49178 ) Change subject: [UNTESTED] sb/intel/bd82x6x: Account for PCH type in IOBP magic ...................................................................... [UNTESTED] sb/intel/bd82x6x: Account for PCH type in IOBP magic The initial steps came out of trace output from a Panther Point system. Add missing Cougar Point steps, and guard Panther Point specific steps. Change-Id: I2569f9c436f545a5e3ffda5a31ab27c27469f540 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/early_pch.c 1 file changed, 33 insertions(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/49178/1 diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index 0b60d13..e86297b 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -156,7 +156,10 @@ pch_iobp_update(0xeb0040a1, ~(0x3ff << 3), 0x9f << 3); pch_iobp_update(0xec0040a1, ~(0x3ff << 3), 0x9f << 3); - /* Some CPT-only writes go here */ + if (pch_silicon_type() == PCH_TYPE_CPT) { + pch_iobp_update(0xec004086, ~0, 1 << 30); + pch_iobp_update(0xec004086, ~0, 1 << 31); + } pch_iobp_update(0xea004001, ~(3 << 10), 1 << 10); pch_iobp_update(0xeb004002, ~0, 1 << 30 | 1 << 21); @@ -189,34 +192,35 @@ /* PPT A0 resume-only xHCI workaround goes here */ - /* TODO: This section is PPT-only */ - pch_iobp_update(0xec00404d, ~(0xff3f << 8), 0xff17 << 8); - pch_iobp_update(0xec000084, ~(1 << 31), 0); - pch_iobp_update(0xec000184, ~(1 << 31), 0); - pch_iobp_update(0xec000284, ~(1 << 31), 0); - pch_iobp_update(0xec000384, ~(1 << 31), 0); - pch_iobp_update(0xec000094, ~0, 0xf << 16); - pch_iobp_update(0xec000194, ~0, 0xf << 16); - pch_iobp_update(0xec000294, ~0, 0xf << 16); - pch_iobp_update(0xec000394, ~0, 0xf << 16); - pch_iobp_update(0xec000096, ~0x3ff, 1); - pch_iobp_update(0xec000196, ~0x3ff, 1); - pch_iobp_update(0xec000296, ~0x3ff, 1); - pch_iobp_update(0xec000396, ~0x3ff, 1); - pch_iobp_update(0xec000001, ~0, 3 << 10 | 1 << 3); - pch_iobp_update(0xec000101, ~0, 3 << 10 | 1 << 3); - pch_iobp_update(0xec000201, ~0, 3 << 10 | 1 << 3); - pch_iobp_update(0xec000301, ~0, 3 << 10 | 1 << 3); - pch_iobp_update(0xec0040b5, ~0xffff, 0xc518); - pch_iobp_update(0xec000087, ~(0xf << 8), 5 << 8); - pch_iobp_update(0xec000187, ~(0xf << 8), 5 << 8); - pch_iobp_update(0xec000287, ~(0xf << 8), 5 << 8); - pch_iobp_update(0xec000387, ~(0xf << 8), 5 << 8); - pch_iobp_update(0xea000050, ~(0xff << 16), 0xbb << 16); - pch_iobp_update(0xea000150, ~(0xff << 16), 0xbb << 16); - pch_iobp_update(0xec007f60, ~(0xf << 8), 0xd << 8); - pch_iobp_update(0xea00008d, ~0, 3 << 20); - pch_iobp_update(0xea00018d, ~0, 3 << 20); + if (pch_silicon_type() == PCH_TYPE_CPT) { + pch_iobp_update(0xec00404d, ~(0xff3f << 8), 0xff17 << 8); + pch_iobp_update(0xec000084, ~(1 << 31), 0); + pch_iobp_update(0xec000184, ~(1 << 31), 0); + pch_iobp_update(0xec000284, ~(1 << 31), 0); + pch_iobp_update(0xec000384, ~(1 << 31), 0); + pch_iobp_update(0xec000094, ~0, 0xf << 16); + pch_iobp_update(0xec000194, ~0, 0xf << 16); + pch_iobp_update(0xec000294, ~0, 0xf << 16); + pch_iobp_update(0xec000394, ~0, 0xf << 16); + pch_iobp_update(0xec000096, ~0x3ff, 1); + pch_iobp_update(0xec000196, ~0x3ff, 1); + pch_iobp_update(0xec000296, ~0x3ff, 1); + pch_iobp_update(0xec000396, ~0x3ff, 1); + pch_iobp_update(0xec000001, ~0, 3 << 10 | 1 << 3); + pch_iobp_update(0xec000101, ~0, 3 << 10 | 1 << 3); + pch_iobp_update(0xec000201, ~0, 3 << 10 | 1 << 3); + pch_iobp_update(0xec000301, ~0, 3 << 10 | 1 << 3); + pch_iobp_update(0xec0040b5, ~0xffff, 0xc518); + pch_iobp_update(0xec000087, ~(0xf << 8), 5 << 8); + pch_iobp_update(0xec000187, ~(0xf << 8), 5 << 8); + pch_iobp_update(0xec000287, ~(0xf << 8), 5 << 8); + pch_iobp_update(0xec000387, ~(0xf << 8), 5 << 8); + pch_iobp_update(0xea000050, ~(0xff << 16), 0xbb << 16); + pch_iobp_update(0xea000150, ~(0xff << 16), 0xbb << 16); + pch_iobp_update(0xec007f60, ~(0xf << 8), 0xd << 8); + pch_iobp_update(0xea00008d, ~0, 3 << 20); + pch_iobp_update(0xea00018d, ~0, 3 << 20); + } /* TODO: Figure out what these writes mean */ pch_iobp_update(0xec0007b2, 0, 0x04514b5e); -- To view, visit https://review.coreboot.org/c/coreboot/+/49178 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2569f9c436f545a5e3ffda5a31ab27c27469f540 Gerrit-Change-Number: 49178 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: [UNTESTED] sb/intel/bd82x6x: Get DMI TC/VC mapping from northbridge
by Angel Pons (Code Review) 11 Apr '24

11 Apr '24

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49181 ) Change subject: [UNTESTED] sb/intel/bd82x6x: Get DMI TC/VC mapping from northbridge ...................................................................... [UNTESTED] sb/intel/bd82x6x: Get DMI TC/VC mapping from northbridge Both ends of the DMI link must use the same TC/VC mapping. Since the register values are identical, pass the northbridge values as parameters and have the southbridge code use them. This prevents any inconsistency. Change-Id: I598cd5b6bd1af22ee2ae25a4f29cae381116bd5d Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/early_dmi.c M src/southbridge/intel/bd82x6x/early_pch.c M src/southbridge/intel/bd82x6x/pch.h 3 files changed, 27 insertions(+), 46 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/49181/1 diff --git a/src/northbridge/intel/sandybridge/early_dmi.c b/src/northbridge/intel/sandybridge/early_dmi.c index bcf3e4c..7d536b5 100644 --- a/src/northbridge/intel/sandybridge/early_dmi.c +++ b/src/northbridge/intel/sandybridge/early_dmi.c @@ -180,26 +180,33 @@ printk(BIOS_DEBUG, "DMI: Running at X%x @ %dMT/s\n", w, t); /* - * Virtual Channel resources must match settings in RCBA! - * * Channel Vp and Vm are documented in: * "Desktop 4th Generation Intel Core Processor Family, Desktop Intel Pentium * Processor Family, and Desktop Intel Celeron Processor Family Vol. 2" */ - /* Channel 0: Enable, Set ID to 0, map TC0 and TC3 and TC4 to VC0. */ - DMIBAR32(DMIVC0RCTL) = (1 << 31) | (0 << 24) | (0x0c << 1) | 1; - /* Channel 1: Enable, Set ID to 1, map TC1 and TC5 to VC1. */ - DMIBAR32(DMIVC1RCTL) = (1 << 31) | (1 << 24) | (0x11 << 1); - /* Channel p: Enable, Set ID to 2, map TC2 and TC6 to VCp */ - DMIBAR32(DMIVCPRCTL) = (1 << 31) | (2 << 24) | (0x22 << 1); + /* Channel 0: Enable, Set ID to 0, map TC0 and TC3 and TC4 to VC0 */ + const u32 vc0 = (1 << 31) | (0 << 24) | (0x0c << 1) | 1; + + /* Channel 1: Enable, Set ID to 1, map TC1 and TC5 to VC1 */ + const u32 vc1 = (1 << 31) | (1 << 24) | (0x11 << 1); + + /* Channel p: Enable, Set ID to 2, map TC2 and TC6 to VCp */ + const u32 vcp = (1 << 31) | (2 << 24) | (0x22 << 1); + /* Channel m: Enable, Set ID to 0, map TC7 to VCm */ - DMIBAR32(DMIVCMRCTL) = (1 << 31) | (7 << 24) | (0x40 << 1); + const u32 vcm = (1 << 31) | (7 << 24) | (0x40 << 1); + + DMIBAR32(DMIVC0RCTL) = vc0; + DMIBAR32(DMIVC1RCTL) = vc1; + DMIBAR32(DMIVCPRCTL) = vcp; + DMIBAR32(DMIVCMRCTL) = vcm; /* Set Extended VC Count (EVCC) to 1 as Channel 1 is active. */ DMIBAR8(DMIPVCCAP1) |= 1; - early_pch_init_native_dmi_post(); + /* Ensure the PCH side uses the same virtual channel settings */ + early_pch_init_native_dmi_post(vc0, vc1, vcp, vcm); /* * BIOS Requirement: Check if DMI VC Negotiation was successful. diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index 251ff86..eac8e1f 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -28,7 +28,7 @@ RCBA8(DLCTL2) = (RCBA8(DLCTL2) & ~0xf) | 2; } -void early_pch_init_native_dmi_post(void) +void early_pch_init_native_dmi_post(const u32 vc0, const u32 vc1, const u32 vcp, const u32 vcm) { u32 reg32; @@ -42,47 +42,21 @@ RCBA8(UPDCR) = RCBA8(UPDCR) | 1 << 2 | 1 << 0; - /* - * Virtual Channel resources must match settings in DMIBAR! - * - * Some of the following settings are taken from - * "Intel Core i5-600, i3-500 Desktop Processor Series and Intel - * Pentium Desktop Processor 6000 Series Vol. 2" datasheet and - * serialice traces. - */ + /* Virtual Channel 0 */ + RCBA32(V0CTL) = vc0; - /* Virtual Channel 0 Resource Control Register. - * Enable channel. - * Set Virtual Channel Identifier. - * Map TC0 and TC3 and TC4 to VC0. - */ - - RCBA32(V0CTL) = (1 << 31) | (0 << 24) | (0x0c << 1) | 1; - - /* Virtual Channel 1 Resource Control Register. - * Enable channel. - * Set Virtual Channel Identifier. - * Map TC1 and TC5 to VC1. - */ - RCBA32(V1CTL) = (1 << 31) | (1 << 24) | (0x11 << 1); + /* Virtual Channel 1 */ + RCBA32(V1CTL) = vc1; /* Read back register */ RCBA32(V1CTL); - /* Virtual Channel private Resource Control Register. - * Enable channel. - * Set Virtual Channel Identifier. - * Map TC2 and TC6 to VCp. - */ - RCBA32(CIR31) = (1 << 31) | (2 << 24) | (0x22 << 1); + /* Virtual Channel private */ + RCBA32(CIR31) = vcp; /* Read back register */ RCBA32(CIR31); - /* Virtual Channel ME Resource Control Register. - * Enable channel. - * Set Virtual Channel Identifier. - * Map TC7 to VCm. - */ - RCBA32(CIR32) = (1 << 31) | (7 << 24) | (0x40 << 1); + /* Virtual Channel ME */ + RCBA32(CIR32) = vcm; /* Lock Virtual Channel Resource control register. */ RCBA32(CIR0) |= TCLOCKDN; diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 42c56a2..5eaaf51 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -63,7 +63,7 @@ void early_pch_init_native(void); void early_pch_init(void); void early_pch_init_native_dmi_pre(void); -void early_pch_init_native_dmi_post(void); +void early_pch_init_native_dmi_post(const u32 vc0, const u32 vc1, const u32 vcp, const u32 vcm); struct southbridge_usb_port { -- To view, visit https://review.coreboot.org/c/coreboot/+/49181 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I598cd5b6bd1af22ee2ae25a4f29cae381116bd5d Gerrit-Change-Number: 49181 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: sb/intel/bd82x6x: Split `pch_iobp_update` function
by Angel Pons (Code Review) 11 Apr '24

11 Apr '24

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49179 ) Change subject: sb/intel/bd82x6x: Split `pch_iobp_update` function ...................................................................... sb/intel/bd82x6x: Split `pch_iobp_update` function A follow-up needs to use the value of an IOBP register in a condition, so split the read and write operations into independent functions. Change-Id: Ic8fe5be8f0cf8e4672d3e32db7746609ff5da841 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/common.c M src/southbridge/intel/bd82x6x/pch.h 2 files changed, 23 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/49179/1 diff --git a/src/southbridge/intel/bd82x6x/common.c b/src/southbridge/intel/bd82x6x/common.c index 3fad12e..bd1b4cd 100644 --- a/src/southbridge/intel/bd82x6x/common.c +++ b/src/southbridge/intel/bd82x6x/common.c @@ -73,7 +73,7 @@ return 0; } -void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) +u32 pch_iobp_read(u32 address) { u32 data; @@ -85,24 +85,26 @@ RCBA32(IOBPS) = IOBPS_RW_BX; else RCBA32(IOBPS) = IOBPS_READ_AX; + if (!iobp_poll()) - return; + return 0; /* Read IOBP data */ data = RCBA32(IOBPD); if (!iobp_poll()) - return; + return 0; /* Check for successful transaction */ if ((RCBA32(IOBPS) & 0x6) != 0) { printk(BIOS_ERR, "IOBP read 0x%08x failed\n", address); - return; + return 0; } - /* Update the data */ - data &= andvalue; - data |= orvalue; + return data; +} +void pch_iobp_write(u32 address, u32 data) +{ /* WRITE OPCODE */ if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0)) RCBA32(IOBPS) = IOBPS_RW_BX; @@ -116,3 +118,14 @@ if (!iobp_poll()) return; } + +void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) +{ + u32 data = pch_iobp_read(address); + + /* Update the data */ + data &= andvalue; + data |= orvalue; + + pch_iobp_write(address, data); +} diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 3b91e31..42c56a2 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -43,6 +43,9 @@ int pch_silicon_revision(void); int pch_silicon_type(void); int pch_silicon_supported(int type, int rev); + +u32 pch_iobp_read(u32 address); +void pch_iobp_write(u32 address, u32 data); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); void enable_usb_bar(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/49179 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8fe5be8f0cf8e4672d3e32db7746609ff5da841 Gerrit-Change-Number: 49179 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: [UNTESTED] sb/intel/bd82x6x: Correct conditional IOBP update
by Angel Pons (Code Review) 11 Apr '24

11 Apr '24

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49180 ) Change subject: [UNTESTED] sb/intel/bd82x6x: Correct conditional IOBP update ...................................................................... [UNTESTED] sb/intel/bd82x6x: Correct conditional IOBP update This one IOBP register only needs to be updated if its bit 20 is zero. Change-Id: I7c9e268f9fdf0ae57c6f453f8bce160b177889a4 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/early_pch.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/49180/1 diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index e86297b..251ff86 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -181,8 +181,8 @@ pch_iobp_update(0xea0000a9, ~(0x3ff << 3), 0x29f << 3); pch_iobp_update(SATA_IOBP_SP1G3IR, ~(0xff << 16 | 0x3f << 8), 0x88 << 16 | 3 << 8); - /* TODO: Needs special handling */ - pch_iobp_update(0xea007f05, 0, 0x00010642); + if ((pch_iobp_read(0xea007f05) & 1 << 20) == 0) + pch_iobp_update(0xea007f05, ~(7 << 8), 6 << 8); pch_iobp_update(0xea0040b7, ~0xffff, 0xc91c); pch_iobp_update(0xea0040b8, ~0xffff, 0xc91c); -- To view, visit https://review.coreboot.org/c/coreboot/+/49180 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c9e268f9fdf0ae57c6f453f8bce160b177889a4 Gerrit-Change-Number: 49180 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 3

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2023