coreboot-gerrit April 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: Add support for rust
by Felix Singer (Code Review) 01 Apr '23

01 Apr '23

Attention is currently required from: Martin L Roth, ron minnich, Elyes Haouas. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74124 ) Change subject: Add support for rust ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > I'll need to update the toolchain builder for this. the docker images don't build at the moment. Seems like Debian made some changes. I'm already on it. -- To view, visit https://review.coreboot.org/c/coreboot/+/74124 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibff3ca83b3dfebcc18006cddf0f649bcfb076500 Gerrit-Change-Number: 74124 Gerrit-PatchSet: 1 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sat, 01 Apr 2023 04:16:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: mb/intel: add Archer City CRB support
by Johnny Lin (Code Review) 01 Apr '23

01 Apr '23

Attention is currently required from: Patrick Rudolph, Simon Chou, Paul Menzel, Shuming Chu (Shuming), Arthur Heymans, Juan Sanchez. Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71968 ) Change subject: mb/intel: add Archer City CRB support ...................................................................... Patch Set 28: (9 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/71968/comment/a47b6341_f2c8a03a PS27, Line 11: > What hardware configuration and what payloads were tested? Done File src/mainboard/intel/archercity_crb/romstage.c: https://review.coreboot.org/c/coreboot/+/71968/comment/33c4fac9_b56c1a02 PS27, Line 76: /* Disable CXL header bypass */ > Redundant comment, as it does not add any more information. Done https://review.coreboot.org/c/coreboot/+/71968/comment/c29f550a_d7b8e6a5 PS27, Line 79: /* Set DFX CXL security level to fully trusted */ > Redundant comment, as it does not add any more information. Done https://review.coreboot.org/c/coreboot/+/71968/comment/94d39a69_3587723b PS27, Line 83: mupd->FspmConfig.DelayAfterPCIeLinkTraining = 2000; > Maybe just add a comment `/* ms */` at the end to document the unit? […] I think the above comment already has mentioned ms. https://review.coreboot.org/c/coreboot/+/71968/comment/f763f6b7_a55d4ed4 PS27, Line 96: "SerialIoUartDebugEnable to %d\n", FSP_LOG, FSP_LOG_DEFAULT); > Output strings should be on one line. Ack. Put into online would exceed 96 characters. https://review.coreboot.org/c/coreboot/+/71968/comment/580fed7a_f0e2bc70 PS27, Line 102: /* Enable - Portions of memory reference code will be skipped */ : /* when possible to increase boot speed on warm boots.*/ > Please use the comment styles from the coding style. Done https://review.coreboot.org/c/coreboot/+/71968/comment/a23649b8_543e0e06 PS27, Line 107: /* Set Attempt Fast Cold Boot to enable. */ > Redundant. Done https://review.coreboot.org/c/coreboot/+/71968/comment/c8258e33_52beff0a PS27, Line 108: /* Enable - Portions of memory reference code will be skipped */ : /* when possible to increase boot speed on cold boots. */ : /* Disable - Disables this feature. */ : /* Auto - Sets it to the MRC default setting. */ > Aren’t these comments in the header file? Done https://review.coreboot.org/c/coreboot/+/71968/comment/ed706695_3f5e0128 PS27, Line 126: /* Disable FSP memory train results*/ > 1. Missing space at the end. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/71968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic02634cd615e2245e394f10aad24b0430cf5cd17 Gerrit-Change-Number: 71968 Gerrit-PatchSet: 28 Gerrit-Owner: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-CC: Juan Sanchez Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-CC: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Juan Sanchez Gerrit-Comment-Date: Sat, 01 Apr 2023 03:51:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: mb/intel: add Archer City CRB support
by Johnny Lin (Code Review) 01 Apr '23

01 Apr '23

Attention is currently required from: Patrick Rudolph, Simon Chou, Johnny Lin, Shuming Chu (Shuming), Arthur Heymans, Juan Sanchez. Johnny Lin has uploaded a new patch set (#28) to the change originally created by Simon Chou. ( https://review.coreboot.org/c/coreboot/+/71968 ) Change subject: mb/intel: add Archer City CRB support ...................................................................... mb/intel: add Archer City CRB support Intel Archer City CRB is a dual socket CRB with Intel Sapphire Rapids Scalable Processor chipset. The chipset also includes Emmitsburg PCH. It was tested with LiuxBoot payload on both dual and single socket configurations. Change-Id: Ic02634cd615e2245e394f10aad24b0430cf5cd17 Signed-off-by: Jonathan Zhang <jonzhang(a)meta.com> Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- A src/mainboard/intel/archercity_crb/Kconfig A src/mainboard/intel/archercity_crb/Kconfig.name A src/mainboard/intel/archercity_crb/Makefile.inc A src/mainboard/intel/archercity_crb/acpi/platform.asl A src/mainboard/intel/archercity_crb/board.fmd A src/mainboard/intel/archercity_crb/board_info.txt A src/mainboard/intel/archercity_crb/bootblock.c A src/mainboard/intel/archercity_crb/devicetree.cb A src/mainboard/intel/archercity_crb/dsdt.asl A src/mainboard/intel/archercity_crb/include/mainboard_ras.h A src/mainboard/intel/archercity_crb/include/sprsp_ac_iio.h A src/mainboard/intel/archercity_crb/ramstage.c A src/mainboard/intel/archercity_crb/romstage.c 13 files changed, 488 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/71968/28 -- To view, visit https://review.coreboot.org/c/coreboot/+/71968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic02634cd615e2245e394f10aad24b0430cf5cd17 Gerrit-Change-Number: 71968 Gerrit-PatchSet: 28 Gerrit-Owner: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-CC: Juan Sanchez Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-CC: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Juan Sanchez Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: Makefile.inc: introduce all_x86 target
by Kyösti Mälkki (Code Review) 01 Apr '23

01 Apr '23

Attention is currently required from: Martin L Roth, Felix Held. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74150 ) Change subject: Makefile.inc: introduce all_x86 target ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: https://review.coreboot.org/c/coreboot/+/42062/9/src/cpu/x86/lapic/Makefile… I hope the syntax is expanded, some day, such that we have "all_x86-y += " for cases like these. Even better, if every "bootblock-y +=" under cpu/x86/ would be automatically treated as "bootblock_x86-y +=" since that is ultimately what we need here. -- To view, visit https://review.coreboot.org/c/coreboot/+/74150 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d0184182b931185990094d0874b49c0b5cb9f7e Gerrit-Change-Number: 74150 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 01 Apr 2023 00:46:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/meteorlake: Fix PortUsb30Enable configuration
by Ivy Jian (Code Review) 01 Apr '23

01 Apr '23

Attention is currently required from: Tarun Tuli, Eric Lai. Ivy Jian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74143 ) Change subject: soc/intel/meteorlake: Fix PortUsb30Enable configuration ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > > @subrata, We should check why this not working, and we should change the enable to is_dev_enable. […] UsbTcPortEn has been checked by is_dev_enabled in fill_fsps_tcss_paramsand. PortUsb30Enable is the configuration for xhci usb3. -- To view, visit https://review.coreboot.org/c/coreboot/+/74143 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic04b9eb236ed28a76ee516c52fc0c983cb8f2c0e Gerrit-Change-Number: 74143 Gerrit-PatchSet: 2 Gerrit-Owner: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Sat, 01 Apr 2023 00:14:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/common/block/cpu/tsc/Makefile: order targets by stage
by Felix Held (Code Review) 01 Apr '23

01 Apr '23

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74017 ) Change subject: soc/amd/common/block/cpu/tsc/Makefile: order targets by stage ...................................................................... Patch Set 6: (1 comment) File src/soc/amd/common/block/cpu/tsc/Makefile.inc: https://review.coreboot.org/c/coreboot/+/74017/comment/673e8225_daed5e51 PS4, Line 26: smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_TSC) += tsc_freq.c > ack CB:74150 introduces the all_x86 target which CB:74151 and following then use to finally replace this duplication. that ended up being much simpler than i expected -- To view, visit https://review.coreboot.org/c/coreboot/+/74017 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9e551b37707081eb2ea1d682013f57c7ca8aabd Gerrit-Change-Number: 74017 Gerrit-PatchSet: 6 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 01 Apr 2023 00:03:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: drivers/pc80/pc/Makefile: use all_x86 make target
by Felix Held (Code Review) 01 Apr '23

01 Apr '23

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74153 ) Change subject: drivers/pc80/pc/Makefile: use all_x86 make target ...................................................................... drivers/pc80/pc/Makefile: use all_x86 make target Use the newly introduced all_x86 make target to add the compilation unit to all stages that run on the x86 cores, but not to verstage on PSP. TEST=Timeless build for Mandolin results in identical image. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I23c6977ae8acebb8dcd546f86f7f7b677272a6cb --- M src/drivers/pc80/pc/Makefile.inc 1 file changed, 16 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/74153/1 diff --git a/src/drivers/pc80/pc/Makefile.inc b/src/drivers/pc80/pc/Makefile.inc index 63ed998..7cf2957 100644 --- a/src/drivers/pc80/pc/Makefile.inc +++ b/src/drivers/pc80/pc/Makefile.inc @@ -6,11 +6,7 @@ ramstage-$(CONFIG_SPKMODEM) += spkmodem.c romstage-$(CONFIG_SPKMODEM) += spkmodem.c -bootblock-y += i8254.c -verstage_x86-y += i8254.c -romstage-y += i8254.c -ramstage-y += i8254.c -postcar-y += i8254.c +all_x86-y += i8254.c smm-y += i8254.c endif -- To view, visit https://review.coreboot.org/c/coreboot/+/74153 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23c6977ae8acebb8dcd546f86f7f7b677272a6cb Gerrit-Change-Number: 74153 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: cpu/x86/lapic,pae,tsc/Makefile: use all_x86 target
by Felix Held (Code Review) 01 Apr '23

01 Apr '23

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74152 ) Change subject: cpu/x86/lapic,pae,tsc/Makefile: use all_x86 target ...................................................................... cpu/x86/lapic,pae,tsc/Makefile: use all_x86 target Use the newly introduced all_x86 make target to add the compilation unit to all stages that run on the x86 cores, but not to verstage on PSP. TEST=Timeless build for Mandolin results in identical image. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I181c3207bb1ebe9c5080ef3a3cdda8146ed05822 --- M src/cpu/x86/lapic/Makefile.inc M src/cpu/x86/pae/Makefile.inc M src/cpu/x86/tsc/Makefile.inc 3 files changed, 19 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/74152/1 diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc index 22bd987..308e9b2 100644 --- a/src/cpu/x86/lapic/Makefile.inc +++ b/src/cpu/x86/lapic/Makefile.inc @@ -4,14 +4,6 @@ romstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c ramstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c postcar-$(CONFIG_UDELAY_LAPIC) += apic_timer.c -bootblock-y += boot_cpu.c -verstage_x86-y += boot_cpu.c -romstage-y += boot_cpu.c -ramstage-y += boot_cpu.c -postcar-y += boot_cpu.c -bootblock-y += lapic.c -verstage_x86-y += lapic.c -romstage-y += lapic.c -ramstage-y += lapic.c -postcar-y += lapic.c +all_x86-y += boot_cpu.c +all_x86-y += lapic.c diff --git a/src/cpu/x86/pae/Makefile.inc b/src/cpu/x86/pae/Makefile.inc index 70e0b2f..331b5a8 100644 --- a/src/cpu/x86/pae/Makefile.inc +++ b/src/cpu/x86/pae/Makefile.inc @@ -1,6 +1,2 @@ -bootblock-y += pgtbl.c -verstage_x86-y += pgtbl.c -romstage-y += pgtbl.c -postcar-y += pgtbl.c -ramstage-y += pgtbl.c +all_x86-y += pgtbl.c smm-y += pgtbl.c diff --git a/src/cpu/x86/tsc/Makefile.inc b/src/cpu/x86/tsc/Makefile.inc index 978d7fa..18ce4db 100644 --- a/src/cpu/x86/tsc/Makefile.inc +++ b/src/cpu/x86/tsc/Makefile.inc @@ -1,6 +1,2 @@ -bootblock-y += delay_tsc.c -ramstage-y += delay_tsc.c -romstage-y += delay_tsc.c -verstage_x86-y += delay_tsc.c -postcar-y += delay_tsc.c +all_x86-y += delay_tsc.c smm-y += delay_tsc.c -- To view, visit https://review.coreboot.org/c/coreboot/+/74152 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I181c3207bb1ebe9c5080ef3a3cdda8146ed05822 Gerrit-Change-Number: 74152 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/amd/*/Makefile: use all_x86 target
by Felix Held (Code Review) 01 Apr '23

01 Apr '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74151 ) Change subject: soc/amd/*/Makefile: use all_x86 target ...................................................................... soc/amd/*/Makefile: use all_x86 target Use the newly introduced all_x86 make target to add the compilation unit to all stages that run on the x86 cores, but not to verstage on PSP. TEST=Timeless builds for Mandolin without verstage on PSP and Guybrush with verstage on PSP result in identical images with and without this patch applied. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I94de6de5a4c7723065a4eb1b7149f9933ef134a1 --- M src/soc/amd/cezanne/Makefile.inc M src/soc/amd/common/block/acpi/Makefile.inc M src/soc/amd/common/block/alink/Makefile.inc M src/soc/amd/common/block/cpu/tsc/Makefile.inc M src/soc/amd/common/block/lpc/Makefile.inc M src/soc/amd/common/block/pci/Makefile.inc M src/soc/amd/common/block/pm/Makefile.inc M src/soc/amd/common/block/uart/Makefile.inc M src/soc/amd/glinda/Makefile.inc M src/soc/amd/mendocino/Makefile.inc M src/soc/amd/phoenix/Makefile.inc M src/soc/amd/picasso/Makefile.inc 12 files changed, 49 insertions(+), 97 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/74151/1 diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index bf57698..062a19d 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -9,18 +9,15 @@ all-y += config.c all-y += i2c.c +# all_x86-y adds the compilation unit to all stages that run on the x86 cores +all_x86-y += gpio.c +all_x86-y += uart.c + bootblock-y += early_fch.c bootblock-y += espi_util.c -bootblock-y += gpio.c -bootblock-y += uart.c - -verstage_x86-y += gpio.c -verstage_x86-y += uart.c romstage-y += fsp_m_params.c -romstage-y += gpio.c romstage-y += romstage.c -romstage-y += uart.c ramstage-y += acpi.c ramstage-y += agesa_acpi.c @@ -28,11 +25,9 @@ ramstage-y += cpu.c ramstage-y += fch.c ramstage-y += fsp_s_params.c -ramstage-y += gpio.c ramstage-y += graphics.c ramstage-y += mca.c ramstage-y += root_complex.c -ramstage-y += uart.c ramstage-y += xhci.c smm-y += gpio.c diff --git a/src/soc/amd/common/block/acpi/Makefile.inc b/src/soc/amd/common/block/acpi/Makefile.inc index cf1e9c1..a0d9290 100644 --- a/src/soc/amd/common/block/acpi/Makefile.inc +++ b/src/soc/amd/common/block/acpi/Makefile.inc @@ -1,11 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-only ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI),y) -bootblock-y += acpi.c -verstage_x86-y += acpi.c -romstage-y += acpi.c -ramstage-y += acpi.c -postcar-y += acpi.c +all_x86-y += acpi.c smm-y += acpi.c ramstage-y += pm_state.c diff --git a/src/soc/amd/common/block/alink/Makefile.inc b/src/soc/amd/common/block/alink/Makefile.inc index fbb96ee..ef0728a 100644 --- a/src/soc/amd/common/block/alink/Makefile.inc +++ b/src/soc/amd/common/block/alink/Makefile.inc @@ -1,11 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-only ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_ALINK),y) -bootblock-y += alink.c -verstage_x86-y += alink.c -romstage-y += alink.c -postcar-y += alink.c -ramstage-y += alink.c +all_x86-y += alink.c smm-y += alink.c endif # CONFIG_SOC_AMD_COMMON_BLOCK_ALINK diff --git a/src/soc/amd/common/block/cpu/tsc/Makefile.inc b/src/soc/amd/common/block/cpu/tsc/Makefile.inc index 65e849a..4ec0e0f 100644 --- a/src/soc/amd/common/block/cpu/tsc/Makefile.inc +++ b/src/soc/amd/common/block/cpu/tsc/Makefile.inc @@ -1,24 +1,9 @@ ## SPDX-License-Identifier: GPL-2.0-only -bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM15H_16H) += cpufreq_15_16.c -bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H) += cpufreq_17_19.c -bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH) += cpufreq_1a.c -bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_TSC) += tsc_freq.c - -verstage_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM15H_16H) += cpufreq_15_16.c -verstage_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H) += cpufreq_17_19.c -verstage_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH) += cpufreq_1a.c -verstage_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_TSC) += tsc_freq.c - -romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM15H_16H) += cpufreq_15_16.c -romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H) += cpufreq_17_19.c -romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH) += cpufreq_1a.c -romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_TSC) += tsc_freq.c - -ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM15H_16H) += cpufreq_15_16.c -ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H) += cpufreq_17_19.c -ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH) += cpufreq_1a.c -ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_TSC) += tsc_freq.c +all_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM15H_16H) += cpufreq_15_16.c +all_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H) += cpufreq_17_19.c +all_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH) += cpufreq_1a.c +all_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_TSC) += tsc_freq.c smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM15H_16H) += cpufreq_15_16.c smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H) += cpufreq_17_19.c diff --git a/src/soc/amd/common/block/lpc/Makefile.inc b/src/soc/amd/common/block/lpc/Makefile.inc index 6bec843..11de514 100644 --- a/src/soc/amd/common/block/lpc/Makefile.inc +++ b/src/soc/amd/common/block/lpc/Makefile.inc @@ -3,20 +3,13 @@ ramstage-y += lpc.c -bootblock-y += lpc_util.c -verstage_x86-y += lpc_util.c -romstage-y += lpc_util.c -postcar-y += lpc_util.c -ramstage-y += lpc_util.c +all_x86-y += lpc_util.c smm-y += lpc_util.c endif # CONFIG_SOC_AMD_COMMON_BLOCK_LPC ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA),y) -bootblock-y += spi_dma.c -verstage_x86-y += spi_dma.c -romstage-y += spi_dma.c -ramstage-y += spi_dma.c +all_x86-y += spi_dma.c smm-y += spi_dma.c endif # CONFIG_SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA diff --git a/src/soc/amd/common/block/pci/Makefile.inc b/src/soc/amd/common/block/pci/Makefile.inc index b938c67..372c6ce 100644 --- a/src/soc/amd/common/block/pci/Makefile.inc +++ b/src/soc/amd/common/block/pci/Makefile.inc @@ -11,10 +11,6 @@ ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PCI_MMCONF),y) -bootblock-y += amd_pci_mmconf.c -verstage_x86-y += amd_pci_mmconf.c -romstage-y += amd_pci_mmconf.c -postcar-y += amd_pci_mmconf.c -ramstage-y += amd_pci_mmconf.c +all_x86-y += amd_pci_mmconf.c endif # CONFIG_SOC_AMD_COMMON_BLOCK_PCI_MMCONF diff --git a/src/soc/amd/common/block/pm/Makefile.inc b/src/soc/amd/common/block/pm/Makefile.inc index de1809a..cae4099 100644 --- a/src/soc/amd/common/block/pm/Makefile.inc +++ b/src/soc/amd/common/block/pm/Makefile.inc @@ -1,13 +1,9 @@ ## SPDX-License-Identifier: GPL-2.0-only -bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_PM) += pmlib.c -bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_RESET) += reset.c +all_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_RESET) += reset.c -verstage_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_RESET) += reset.c +bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_PM) += pmlib.c romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE) += chipset_state.c -romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_RESET) += reset.c - -ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_RESET) += reset.c smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE) += chipset_state.c diff --git a/src/soc/amd/common/block/uart/Makefile.inc b/src/soc/amd/common/block/uart/Makefile.inc index de7b68e..bd182d9 100644 --- a/src/soc/amd/common/block/uart/Makefile.inc +++ b/src/soc/amd/common/block/uart/Makefile.inc @@ -1,12 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-only ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_UART),y) -# all-y can't be used, since verstage on PSP has a different implementation -bootblock-y += uart.c -verstage_x86-y += uart.c -romstage-y += uart.c -postcar-y += uart.c -ramstage-y += uart.c +all_x86-y += uart.c smm-$(CONFIG_DEBUG_SMI) += uart.c all-$(CONFIG_AMD_SOC_CONSOLE_UART) += uart_console.c diff --git a/src/soc/amd/glinda/Makefile.inc b/src/soc/amd/glinda/Makefile.inc index 81033e9..47c121e 100644 --- a/src/soc/amd/glinda/Makefile.inc +++ b/src/soc/amd/glinda/Makefile.inc @@ -12,19 +12,17 @@ all-y += config.c all-y += i2c.c +# all_x86-y adds the compilation unit to all stages that run on the x86 cores +all_x86-y += gpio.c +all_x86-y += uart.c + bootblock-y += early_fch.c bootblock-y += espi_util.c -bootblock-y += gpio.c -bootblock-y += uart.c verstage-y += espi_util.c -verstage_x86-y += gpio.c -verstage_x86-y += uart.c romstage-y += fsp_m_params.c -romstage-y += gpio.c romstage-y += romstage.c -romstage-y += uart.c ramstage-y += acpi.c ramstage-y += agesa_acpi.c @@ -32,10 +30,8 @@ ramstage-y += cpu.c ramstage-y += fch.c ramstage-y += fsp_s_params.c -ramstage-y += gpio.c ramstage-y += mca.c ramstage-y += root_complex.c -ramstage-y += uart.c ramstage-y += xhci.c smm-y += gpio.c diff --git a/src/soc/amd/mendocino/Makefile.inc b/src/soc/amd/mendocino/Makefile.inc index 5ed8386..9d9adce 100644 --- a/src/soc/amd/mendocino/Makefile.inc +++ b/src/soc/amd/mendocino/Makefile.inc @@ -9,19 +9,17 @@ all-y += config.c all-y += i2c.c +# all_x86-y adds the compilation unit to all stages that run on the x86 cores +all_x86-y += gpio.c +all_x86-y += uart.c + bootblock-y += early_fch.c bootblock-y += espi_util.c -bootblock-y += gpio.c -bootblock-y += uart.c verstage-y += espi_util.c -verstage_x86-y += gpio.c -verstage_x86-y += uart.c romstage-y += fsp_m_params.c -romstage-y += gpio.c romstage-y += romstage.c -romstage-y += uart.c ramstage-y += acpi.c ramstage-y += agesa_acpi.c @@ -30,10 +28,8 @@ ramstage-y += fch.c ramstage-y += fsp_misc_data_hob.c ramstage-y += fsp_s_params.c -ramstage-y += gpio.c ramstage-y += mca.c ramstage-y += root_complex.c -ramstage-y += uart.c ramstage-y += xhci.c smm-y += gpio.c diff --git a/src/soc/amd/phoenix/Makefile.inc b/src/soc/amd/phoenix/Makefile.inc index 27e5abc..a40aa2c 100644 --- a/src/soc/amd/phoenix/Makefile.inc +++ b/src/soc/amd/phoenix/Makefile.inc @@ -12,20 +12,18 @@ all-y += config.c all-y += i2c.c +# all_x86-y adds the compilation unit to all stages that run on the x86 cores +all_x86-y += gpio.c +all_x86-y += uart.c + bootblock-y += early_fch.c bootblock-y += espi_util.c -bootblock-y += gpio.c -bootblock-y += uart.c verstage-y += espi_util.c -verstage_x86-y += gpio.c -verstage_x86-y += uart.c romstage-y += fsp_m_params.c -romstage-y += gpio.c romstage-y += romstage.c romstage-y += soc_util.c -romstage-y += uart.c ramstage-y += acpi.c ramstage-y += agesa_acpi.c @@ -33,12 +31,10 @@ ramstage-y += cpu.c ramstage-y += fch.c ramstage-y += fsp_s_params.c -ramstage-y += gpio.c ramstage-y += graphics.c ramstage-y += mca.c ramstage-y += root_complex.c ramstage-y += soc_util.c -ramstage-y += uart.c ramstage-y += xhci.c smm-y += gpio.c diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index b5957b9..cb42582 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -10,17 +10,14 @@ all-y += config.c all-y += i2c.c +# all_x86-y adds the compilation unit to all stages that run on the x86 cores +all_x86-y += gpio.c +all_x86-y += uart.c + bootblock-y += early_fch.c -bootblock-y += gpio.c -bootblock-y += uart.c romstage-y += fsp_m_params.c -romstage-y += gpio.c romstage-y += romstage.c -romstage-y += uart.c - -verstage_x86-y += gpio.c -verstage_x86-y += uart.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += agesa_acpi.c @@ -28,14 +25,12 @@ ramstage-y += cpu.c ramstage-y += fch.c ramstage-y += fsp_s_params.c -ramstage-y += gpio.c ramstage-y += graphics.c ramstage-y += mca.c ramstage-y += pcie_gpp.c ramstage-y += root_complex.c ramstage-y += sata.c ramstage-y += soc_util.c -ramstage-y += uart.c ramstage-y += xhci.c smm-y += smihandler.c -- To view, visit https://review.coreboot.org/c/coreboot/+/74151 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94de6de5a4c7723065a4eb1b7149f9933ef134a1 Gerrit-Change-Number: 74151 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: Makefile.inc: introduce all_x86 target
by Felix Held (Code Review) 01 Apr '23

01 Apr '23

Attention is currently required from: Martin L Roth. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74150 ) Change subject: Makefile.inc: introduce all_x86 target ...................................................................... Makefile.inc: introduce all_x86 target For compilation units that should be built for all stages that run on the x86 cores in a newer AMD SoC, but can't be built for verstage on PSP which is an ARM core, the all target can't be used, since that would result in the compilation unit also being added to the verstage target in the verstage on PSP case. In order to not need to add a compilation unit to bootblock, verstage_x8, romstage and ramstage in separate lines in the makefile, introduce the all_x86 target that adds a file to bootblock, verstage_x86, romstage, postcar, ramstage. The compilation units also need to be added to the postcar stage which is only present on the pre-Zen SoCs to be able to also use the all_x86 target in common AMD code that is also used in those per-Zen SoCs. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I9d0184182b931185990094d0874b49c0b5cb9f7e --- M Makefile.inc 1 file changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/74150/1 diff --git a/Makefile.inc b/Makefile.inc index d2d3f88..3b34a99 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -114,6 +114,9 @@ verstage_x86-handler = endif +$(call add-special-class,all_x86) +all_x86-handler = $(foreach class,bootblock verstage_x86 romstage postcar ramstage,$(eval $(class)-y += $(2))) + # Add dynamic classes for rmodules $(foreach supported_arch,$(ARCH_SUPPORTED), \ $(eval $(call define_class,rmodules_$(supported_arch),$(supported_arch)))) -- To view, visit https://review.coreboot.org/c/coreboot/+/74150 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d0184182b931185990094d0874b49c0b5cb9f7e Gerrit-Change-Number: 74150 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newchange

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