Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49168 )
Change subject: sb/intel/bd82x6x: Rework PCH ID cache
......................................................................
sb/intel/bd82x6x: Rework PCH ID cache
Work around a romstage restriction. Globals (or static variables) cannot
be initialized to a non-zero value because there's no data section. Note
that the revision ID for stepping A0 is zero, so `pch_silicon_revision`
will no longer use the cached value for this PCH stepping. Since it is a
pre-production stepping, it is most likely not used anywhere anymore.
Change-Id: I07663d151cbc2d2ed7e4813bf870de52848753fd
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M src/southbridge/intel/bd82x6x/common.c
1 file changed, 4 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/49168/1
diff --git a/src/southbridge/intel/bd82x6x/common.c b/src/southbridge/intel/bd82x6x/common.c
index 7480174..0094db6 100644
--- a/src/southbridge/intel/bd82x6x/common.c
+++ b/src/southbridge/intel/bd82x6x/common.c
@@ -13,9 +13,9 @@
int pch_silicon_revision(void)
{
- static int pch_revision_id = -1;
+ static int pch_revision_id = 0;
- if (pch_revision_id < 0)
+ if (!pch_revision_id)
pch_revision_id = pci_read_config8(PCH_LPC_DEV, PCI_REVISION_ID);
return pch_revision_id;
@@ -23,9 +23,9 @@
int pch_silicon_type(void)
{
- static int pch_type = -1;
+ static int pch_type = 0;
- if (pch_type < 0)
+ if (!pch_type)
pch_type = pci_read_config8(PCH_LPC_DEV, PCI_DEVICE_ID + 1);
return pch_type;
--
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Gerrit-Project: coreboot
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Gerrit-Change-Id: I07663d151cbc2d2ed7e4813bf870de52848753fd
Gerrit-Change-Number: 49168
Gerrit-PatchSet: 1
Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
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Attention is currently required from: Bora Guvendik, Cliff Huang, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Tarun.
Hello Bora Guvendik, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Li1 Feng, Subrata Banik, Tarun,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/78179?usp=email
to look at the new patch set (#4).
Change subject: mb/google/rex: Fix ISH I2C pad for suspend
......................................................................
mb/google/rex: Fix ISH I2C pad for suspend
During suspend, the ISH I2C transactions cannot go through
because the GPIO pads remain the pervious value.
The IO Standby State (IOSSTATE) needs to be changed to keep I2C bus
active and functional during suspend.
BUG=b:302612549
TEST=on Google/rex platform with ISH enabled, do suspend_stress_test
and check that no i2c failure.
Signed-off-by: Cliff Huang <cliff.huang(a)intel.com>
Change-Id: I9a2c902ed56461f3a535428db399c2050756f2da
---
M src/mainboard/google/rex/variants/rex0/fw_config.c
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/78179/4
--
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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78133?usp=email )
Change subject: cpu/intel/model_206ax: Print supported C-states
......................................................................
Patch Set 4:
(1 comment)
File src/arch/x86/cpu_common.c:
https://review.coreboot.org/c/coreboot/+/78133/comment/f9b6216f_ef663660 :
PS4, Line 198: cpuid_eax(0)
cpuid_get_max_func() can be used instead of cpuid_eax(0)
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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78192?usp=email )
Change subject: x86/include/arch/cpuid.h: Fix inline assembly
......................................................................
Patch Set 1: Code-Review+1
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Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78205?usp=email )
Change subject: mb/asus/p8z77-m: Fix ACPI S3 suspend
......................................................................
mb/asus/p8z77-m: Fix ACPI S3 suspend
Set a bit in super I/O configuration like other variants in the
family. Without it S3 suspend totally fails.
(It's safe to set it in devicetree; it needs not be done in early
board init.)
TEST=I have working S3 again.
Change-Id: Ia8059b2a263ab5c459e54685f046eeb913776473
Signed-off-by: Keith Hui <buurin(a)gmail.com>
---
M src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/78205/1
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb
index cad9c5c..476b305 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb
@@ -47,6 +47,7 @@
drq 0xe1 = 0x80 # GP07 high
end
device pnp 2e.a on # ACPI
+ drq 0xe4 = 0x10 # Enable 3VSBSW#, needed for S3 suspend
drq 0xe7 = 0x11 # HWM reset by LRESET#, 0.5s S3 delay for compatibility
drq 0xf2 = 0x5d # Enable RSTOUT[0-2]# and PME
end
--
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