coreboot-gerrit September 2023

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Change in coreboot[master]: sb/intel/bd82x6x/pch.c: Extract common functions
by Angel Pons (Code Review) 25 Nov '23

25 Nov '23

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49167 ) Change subject: sb/intel/bd82x6x/pch.c: Extract common functions ...................................................................... sb/intel/bd82x6x/pch.c: Extract common functions PCH identification functions and `pch_iobp_update` are used in multiple stages. Move them out of `pch.c` to drop some ugly preprocessor usage. Subsequent commits will use `pch_iobp_update` in romstage as well. Change-Id: I8d33338a4f74fd03c8f99f8fcece99b63c28adab Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/Makefile.inc A src/southbridge/intel/bd82x6x/common.c M src/southbridge/intel/bd82x6x/pch.c M src/southbridge/intel/bd82x6x/pch.h 4 files changed, 122 insertions(+), 119 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/49167/1 diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index 687fc97..469a50e 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -7,6 +7,7 @@ ramstage-y += pch.c ramstage-y += azalia.c +ramstage-y += common.c ramstage-y += fadt.c ramstage-y += lpc.c ramstage-y += pci.c @@ -26,8 +27,9 @@ ramstage-$(CONFIG_ELOG) += elog.c -smm-y += smihandler.c me.c me_8.x.c pch.c me_common.c +smm-y += common.c smihandler.c me.c me_8.x.c me_common.c +romstage-y += common.c romstage-y += me_status.c romstage-y += early_rcba.c romstage-y += early_pch.c diff --git a/src/southbridge/intel/bd82x6x/common.c b/src/southbridge/intel/bd82x6x/common.c new file mode 100644 index 0000000..7480174 --- /dev/null +++ b/src/southbridge/intel/bd82x6x/common.c @@ -0,0 +1,118 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define __SIMPLE_DEVICE__ + +#include <console/console.h> +#include <delay.h> +#include <device/pci.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <stdint.h> + +#include "pch.h" + +int pch_silicon_revision(void) +{ + static int pch_revision_id = -1; + + if (pch_revision_id < 0) + pch_revision_id = pci_read_config8(PCH_LPC_DEV, PCI_REVISION_ID); + + return pch_revision_id; +} + +int pch_silicon_type(void) +{ + static int pch_type = -1; + + if (pch_type < 0) + pch_type = pci_read_config8(PCH_LPC_DEV, PCI_DEVICE_ID + 1); + + return pch_type; +} + +int pch_silicon_supported(int type, int rev) +{ + int cur_type = pch_silicon_type(); + int cur_rev = pch_silicon_revision(); + + switch (type) { + case PCH_TYPE_CPT: + /* CougarPoint minimum revision */ + if (cur_type == PCH_TYPE_CPT && cur_rev >= rev) + return 1; + /* PantherPoint any revision */ + if (cur_type == PCH_TYPE_PPT) + return 1; + break; + + case PCH_TYPE_PPT: + /* PantherPoint minimum revision */ + if (cur_type == PCH_TYPE_PPT && cur_rev >= rev) + return 1; + break; + } + + return 0; +} + +#define IOBP_RETRY 1000 +static inline int iobp_poll(void) +{ + unsigned int try = IOBP_RETRY; + u32 data; + + while (try--) { + data = RCBA32(IOBPS); + if ((data & 1) == 0) + return 1; + udelay(10); + } + + printk(BIOS_ERR, "IOBP timeout\n"); + return 0; +} + +void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) +{ + u32 data; + + /* Set the address */ + RCBA32(IOBPIRI) = address; + + /* READ OPCODE */ + if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0)) + RCBA32(IOBPS) = IOBPS_RW_BX; + else + RCBA32(IOBPS) = IOBPS_READ_AX; + if (!iobp_poll()) + return; + + /* Read IOBP data */ + data = RCBA32(IOBPD); + if (!iobp_poll()) + return; + + /* Check for successful transaction */ + if ((RCBA32(IOBPS) & 0x6) != 0) { + printk(BIOS_ERR, "IOBP read 0x%08x failed\n", address); + return; + } + + /* Update the data */ + data &= andvalue; + data |= orvalue; + + /* WRITE OPCODE */ + if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0)) + RCBA32(IOBPS) = IOBPS_RW_BX; + else + RCBA32(IOBPS) = IOBPS_WRITE_AX; + if (!iobp_poll()) + return; + + /* Write IOBP data */ + RCBA32(IOBPD) = data; + if (!iobp_poll()) + return; +} diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index 82b95f6..1c8786d 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -11,123 +11,6 @@ #include "chip.h" #include "pch.h" -int pch_silicon_revision(void) -{ - static int pch_revision_id = -1; - -#ifdef __SIMPLE_DEVICE__ - pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); -#else - struct device *dev = pcidev_on_root(0x1f, 0); -#endif - - if (pch_revision_id < 0) - pch_revision_id = pci_read_config8(dev, PCI_REVISION_ID); - return pch_revision_id; -} - -int pch_silicon_type(void) -{ - static int pch_type = -1; - -#ifdef __SIMPLE_DEVICE__ - pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); -#else - struct device *dev = pcidev_on_root(0x1f, 0); -#endif - - if (pch_type < 0) - pch_type = pci_read_config8(dev, PCI_DEVICE_ID + 1); - return pch_type; -} - -static int pch_silicon_supported(int type, int rev) -{ - int cur_type = pch_silicon_type(); - int cur_rev = pch_silicon_revision(); - - switch (type) { - case PCH_TYPE_CPT: - /* CougarPoint minimum revision */ - if (cur_type == PCH_TYPE_CPT && cur_rev >= rev) - return 1; - /* PantherPoint any revision */ - if (cur_type == PCH_TYPE_PPT) - return 1; - break; - - case PCH_TYPE_PPT: - /* PantherPoint minimum revision */ - if (cur_type == PCH_TYPE_PPT && cur_rev >= rev) - return 1; - break; - } - - return 0; -} - -#define IOBP_RETRY 1000 -static inline int iobp_poll(void) -{ - unsigned int try = IOBP_RETRY; - u32 data; - - while (try--) { - data = RCBA32(IOBPS); - if ((data & 1) == 0) - return 1; - udelay(10); - } - - printk(BIOS_ERR, "IOBP timeout\n"); - return 0; -} - -void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) -{ - u32 data; - - /* Set the address */ - RCBA32(IOBPIRI) = address; - - /* READ OPCODE */ - if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0)) - RCBA32(IOBPS) = IOBPS_RW_BX; - else - RCBA32(IOBPS) = IOBPS_READ_AX; - if (!iobp_poll()) - return; - - /* Read IOBP data */ - data = RCBA32(IOBPD); - if (!iobp_poll()) - return; - - /* Check for successful transaction */ - if ((RCBA32(IOBPS) & 0x6) != 0) { - printk(BIOS_ERR, "IOBP read 0x%08x failed\n", address); - return; - } - - /* Update the data */ - data &= andvalue; - data |= orvalue; - - /* WRITE OPCODE */ - if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0)) - RCBA32(IOBPS) = IOBPS_RW_BX; - else - RCBA32(IOBPS) = IOBPS_WRITE_AX; - if (!iobp_poll()) - return; - - /* Write IOBP data */ - RCBA32(IOBPD) = data; - if (!iobp_poll()) - return; -} - -#ifndef __SIMPLE_DEVICE__ /* Set bit in function disable register to hide this device */ static void pch_hide_devfn(unsigned int devfn) { @@ -426,4 +309,3 @@ CHIP_NAME("Intel Series 6/7 (Cougar Point/Panther Point) Southbridge") .enable_dev = pch_enable, }; -#endif diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 1840a2b..dcab839 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -42,6 +42,7 @@ int pch_silicon_revision(void); int pch_silicon_type(void); +int pch_silicon_supported(int type, int rev); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); void enable_usb_bar(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/49167 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d33338a4f74fd03c8f99f8fcece99b63c28adab Gerrit-Change-Number: 49167 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: sb/intel/bd82x6x: Rework PCH ID cache
by Angel Pons (Code Review) 25 Nov '23

25 Nov '23

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49168 ) Change subject: sb/intel/bd82x6x: Rework PCH ID cache ...................................................................... sb/intel/bd82x6x: Rework PCH ID cache Work around a romstage restriction. Globals (or static variables) cannot be initialized to a non-zero value because there's no data section. Note that the revision ID for stepping A0 is zero, so `pch_silicon_revision` will no longer use the cached value for this PCH stepping. Since it is a pre-production stepping, it is most likely not used anywhere anymore. Change-Id: I07663d151cbc2d2ed7e4813bf870de52848753fd Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/common.c 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/49168/1 diff --git a/src/southbridge/intel/bd82x6x/common.c b/src/southbridge/intel/bd82x6x/common.c index 7480174..0094db6 100644 --- a/src/southbridge/intel/bd82x6x/common.c +++ b/src/southbridge/intel/bd82x6x/common.c @@ -13,9 +13,9 @@ int pch_silicon_revision(void) { - static int pch_revision_id = -1; + static int pch_revision_id = 0; - if (pch_revision_id < 0) + if (!pch_revision_id) pch_revision_id = pci_read_config8(PCH_LPC_DEV, PCI_REVISION_ID); return pch_revision_id; @@ -23,9 +23,9 @@ int pch_silicon_type(void) { - static int pch_type = -1; + static int pch_type = 0; - if (pch_type < 0) + if (!pch_type) pch_type = pci_read_config8(PCH_LPC_DEV, PCI_DEVICE_ID + 1); return pch_type; -- To view, visit https://review.coreboot.org/c/coreboot/+/49168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I07663d151cbc2d2ed7e4813bf870de52848753fd Gerrit-Change-Number: 49168 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: spi/winbond: Pull out winbond_region_to_bpbits function
by Daniel Gröber (dxld) (Code Review) 05 Oct '23

05 Oct '23

Hello Daniel Gröber, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/42115 to review the following change. Change subject: spi/winbond: Pull out winbond_region_to_bpbits function ...................................................................... spi/winbond: Pull out winbond_region_to_bpbits function Split region>bpbits conversion related logic out from winbond_set_write_protection into a new function: winbond_region_to_bpbits. Change-Id: I2c7b08cb56772aa620e690077bbbb1fde3d7aae7 Signed-off-by: Daniel Gröber <dxld(a)darkboxed.org> --- M src/drivers/spi/winbond.c 1 file changed, 94 insertions(+), 59 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/42115/1 diff --git a/src/drivers/spi/winbond.c b/src/drivers/spi/winbond.c index 77191e4..51d43a8 100644 --- a/src/drivers/spi/winbond.c +++ b/src/drivers/spi/winbond.c @@ -211,6 +211,13 @@ static int winbond_get_bpbits(const struct spi_flash *flash, struct spi_flash_bpbits *bpbits); +static int winbond_region_to_bpbits( + const struct spi_flash *flash, + const struct spi_flash_part_id *params, + const struct region *region, + const enum spi_flash_status_reg_lockdown mode, + struct spi_flash_bpbits *bits); + /* * Convert BPx, TB and CMP to a region. * SEC (if available) must be zero. @@ -449,19 +456,77 @@ { const struct spi_flash_part_id *params; struct status_regs mask, val; - struct region wp_region; - u8 cmp, bp, tb; + struct spi_flash_bpbits bpbits; int ret; - /* Need to touch TOP or BOTTOM */ - if (region_offset(region) != 0 && region_end(region) != flash->size) - return -1; - params = flash->part; if (!params) return -1; + ret = winbond_get_bpbits(flash, &bpbits); + if (!ret) + return ret; + + ret = winbond_region_to_bpbits(flash, params, region, mode, &bpbits); + if (!ret) + return ret; + + /* Write block protection bits */ + + if (params->bp_bits == 3) { + val.reg1 = (union status_reg1) { + .bp3 = { .bp = bpbits.bp, .tb = bpbits.tb, .sec = 0 } + }; + mask.reg1 = (union status_reg1) { + .bp3 = { .bp = ~0, .tb = 1, .sec = 1 } + }; + } else { + val.reg1 = (union status_reg1) { + .bp4 = { .bp = bpbits.bp, .tb = bpbits.tb } + }; + mask.reg1 = (union status_reg1) { + .bp4 = { .bp = ~0, .tb = 1 } + }; + } + + val.reg2 = (union status_reg2) { .cmp = bpbits.cmp }; + mask.reg2 = (union status_reg2) { .cmp = 1 }; + + if (params->bp_bits == 3) { + val.reg1.bp3.srp0 = bpbits.winbond.srp0; + mask.reg1.bp3.srp0 = 1; + } else { + val.reg1.bp4.srp0 = bpbits.winbond.srp0; + mask.reg1.bp4.srp0 = 1; + } + + val.reg2.srp1 = bpbits.winbond.srp1; + mask.reg2.srp1 = 1; + + ret = winbond_flash_cmd_status(flash, mask.u, val.u, true); + if (ret) + return ret; + + printk(BIOS_DEBUG, "WINBOND: write-protection set to range " + "0x%08zx-0x%08zx\n", region_offset(region), region_end(region)); + + return ret; +} + +static int winbond_region_to_bpbits( + const struct spi_flash *flash, + const struct spi_flash_part_id *params, + const struct region *region, + const enum spi_flash_status_reg_lockdown mode, + struct spi_flash_bpbits *bits) +{ + struct region wp_region; + + /* Need to touch TOP or BOTTOM */ + if (region_offset(region) != 0 && region_end(region) != flash->size) + return -1; + if (params->bp_bits != 3 && params->bp_bits != 4) { /* FIXME: not implemented */ return -1; @@ -470,91 +535,61 @@ wp_region = *region; if (region_offset(&wp_region) == 0) - tb = 1; + bits->tb = 1; else - tb = 0; + bits->tb = 0; if (region_sz(&wp_region) > flash->size / 2) { - cmp = 1; - wp_region.offset = tb ? 0 : region_sz(&wp_region); + bits->cmp = 1; + wp_region.offset = bits->tb ? 0 : region_sz(&wp_region); wp_region.size = flash->size - region_sz(&wp_region); - tb = !tb; + bits->tb = !bits->tb; } else { - cmp = 0; + bits->cmp = 0; } if (region_sz(&wp_region) == 0) { - bp = 0; + bits->bp = 0; } else if (IS_POWER_OF_2(region_sz(&wp_region)) && (region_sz(&wp_region) >= (1 << params->protection_granularity_shift))) { - bp = log2(region_sz(&wp_region)) - + bits->bp = log2(region_sz(&wp_region)) - params->protection_granularity_shift + 1; } else { printk(BIOS_ERR, "WINBOND: ERROR: unsupported region size\n"); return -1; } - /* Write block protection bits */ - - if (params->bp_bits == 3) { - val.reg1 = (union status_reg1) { - .bp3 = { .bp = bp, .tb = tb, .sec = 0 } - }; - mask.reg1 = (union status_reg1) { - .bp3 = { .bp = ~0, .tb = 1, .sec = 1 } - }; - } else { - val.reg1 = (union status_reg1) { - .bp4 = { .bp = bp, .tb = tb } - }; - mask.reg1 = (union status_reg1) { - .bp4 = { .bp = ~0, .tb = 1 } - }; - } - - val.reg2 = (union status_reg2) { .cmp = cmp }; - mask.reg2 = (union status_reg2) { .cmp = 1 }; - if (mode != SPI_WRITE_PROTECTION_PRESERVE) { - u8 srp; switch (mode) { case SPI_WRITE_PROTECTION_NONE: - srp = 0; + bits->winbond.srp1 = 0; + bits->winbond.srp0 = 0; break; case SPI_WRITE_PROTECTION_PIN: - srp = 1; + bits->winbond.srp1 = 0; + bits->winbond.srp0 = 1; break; case SPI_WRITE_PROTECTION_REBOOT: - srp = 2; + bits->winbond.srp1 = 1; + bits->winbond.srp0 = 0; break; case SPI_WRITE_PROTECTION_PERMANENT: - srp = 3; + if (params->bp_bits == 3) { + bits->winbond.srp1 = 1; + bits->winbond.srp0 = 1; + } else { + /* FIXME: special permanent protect write + * sequence not implemented. */ + return -1; + } break; default: return -1; } - - if (params->bp_bits == 3) { - val.reg1.bp3.srp0 = !!(srp & 1); - mask.reg1.bp3.srp0 = 1; - } else { - val.reg1.bp4.srp0 = !!(srp & 1); - mask.reg1.bp4.srp0 = 1; - } - - val.reg2.srp1 = !!(srp & 2); - mask.reg2.srp1 = 1; } - ret = winbond_flash_cmd_status(flash, mask.u, val.u, true); - if (ret) - return ret; - - printk(BIOS_DEBUG, "WINBOND: write-protection set to range " - "0x%08zx-0x%08zx\n", region_offset(region), region_end(region)); - - return ret; + return 0; } static const struct spi_flash_protection_ops spi_flash_protection_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/42115 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c7b08cb56772aa620e690077bbbb1fde3d7aae7 Gerrit-Change-Number: 42115 Gerrit-PatchSet: 1 Gerrit-Owner: Daniel Gröber (dxld) Gerrit-Reviewer: Daniel Gröber <dxld(a)darkboxed.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: spi/winbond: Use spi_flash_bpbits in winbond_bpbits_to_region
by Daniel Gröber (dxld) (Code Review) 05 Oct '23

05 Oct '23

Hello Daniel Gröber, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/42113 to review the following change. Change subject: spi/winbond: Use spi_flash_bpbits in winbond_bpbits_to_region ...................................................................... spi/winbond: Use spi_flash_bpbits in winbond_bpbits_to_region Change-Id: I2a1a77fb73047df733498c0fa8b8de1153c3b09e Signed-off-by: Daniel Gröber <dxld(a)darkboxed.org> --- M src/drivers/spi/winbond.c 1 file changed, 30 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/42113/1 diff --git a/src/drivers/spi/winbond.c b/src/drivers/spi/winbond.c index e4151de..ccc7ae9 100644 --- a/src/drivers/spi/winbond.c +++ b/src/drivers/spi/winbond.c @@ -213,16 +213,15 @@ * SEC (if available) must be zero. */ static void winbond_bpbits_to_region(const size_t granularity, - const u8 bp, - bool tb, - const bool cmp, + const struct spi_flash_bpbits *bits, const size_t flash_size, struct region *out) { size_t protected_size = - MIN(bp ? granularity << (bp - 1) : 0, flash_size); + MIN(bits->bp ? granularity << (bits->bp - 1) : 0, flash_size); - if (cmp) { + int tb = bits->tb; + if (bits->cmp) { protected_size = flash_size - protected_size; tb = !tb; } @@ -246,8 +245,7 @@ { const struct spi_flash_part_id *params; struct region wp_region; - union status_reg2 reg2; - u8 bp, tb; + struct spi_flash_bpbits bpbits; int ret; params = flash->part; @@ -258,34 +256,49 @@ const size_t granularity = (1 << params->protection_granularity_shift); union status_reg1 reg1 = { .u = 0 }; + union status_reg2 reg2 = { .u = 0 }; ret = spi_flash_cmd(&flash->spi, flash->status_cmd, &reg1.u, sizeof(reg1.u)); if (ret) return ret; + ret = spi_flash_cmd(&flash->spi, CMD_W25_RDSR2, &reg2.u, + sizeof(reg2.u)); + if (ret) + return ret; + if (params->bp_bits == 3) { if (reg1.bp3.sec) { // FIXME: not supported return -1; } - bp = reg1.bp3.bp; - tb = reg1.bp3.tb; + bpbits = (struct spi_flash_bpbits){ + .bp = reg1.bp3.bp, + .cmp = reg2.cmp, + .tb = reg1.bp3.tb, + .winbond = { + .srp0 = reg1.bp3.srp0, + .srp1 = reg2.srp1, + }, + }; } else if (params->bp_bits == 4) { - bp = reg1.bp4.bp; - tb = reg1.bp4.tb; + bpbits = (struct spi_flash_bpbits){ + .bp = reg1.bp4.bp, + .cmp = reg2.cmp, + .tb = reg1.bp4.tb, + .winbond = { + .srp = reg1.bp4.srp0, + .srl = reg2.srp1, + }, + }; } else { // FIXME: not supported return -1; } - ret = spi_flash_cmd(&flash->spi, CMD_W25_RDSR2, &reg2.u, - sizeof(reg2.u)); - if (ret) - return ret; - - winbond_bpbits_to_region(granularity, bp, tb, reg2.cmp, flash->size, + winbond_bpbits_to_region(granularity, &bpbits, flash->size, &wp_region); if (!region_sz(&wp_region)) { -- To view, visit https://review.coreboot.org/c/coreboot/+/42113 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a1a77fb73047df733498c0fa8b8de1153c3b09e Gerrit-Change-Number: 42113 Gerrit-PatchSet: 1 Gerrit-Owner: Daniel Gröber (dxld) Gerrit-Reviewer: Daniel Gröber <dxld(a)darkboxed.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: spi: Add struct spi_flash_bpbits, a common rep. for block protection
by Daniel Gröber (dxld) (Code Review) 05 Oct '23

05 Oct '23

Hello Daniel Gröber, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/42112 to review the following change. Change subject: spi: Add struct spi_flash_bpbits, a common rep. for block protection ...................................................................... spi: Add struct spi_flash_bpbits, a common rep. for block protection Change-Id: I02828b1f764aea29374e794001e74cdc86a94c92 Signed-off-by: Daniel Gröber <dxld(a)darkboxed.org> --- M src/include/spi_flash.h 1 file changed, 33 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/42112/1 diff --git a/src/include/spi_flash.h b/src/include/spi_flash.h index 35b02db..7dce216 100644 --- a/src/include/spi_flash.h +++ b/src/include/spi_flash.h @@ -49,6 +49,39 @@ int (*status)(const struct spi_flash *flash, u8 *reg); }; +struct spi_flash_bpbits { + unsigned int bp; /*< block protection select bits */ + bool cmp; /*< complement protect */ + bool tb; /*< top=0 / bottom=1 select */ + union { + struct { + union { bool srp1, srl; }; + union { bool srp0, srp; }; + /* + * For W25Q*{,F}* parts: + * srp1 srp0 + * 0 0 | writable if WEL==1 + * 0 1 | writable if WEL==1 && #WP==Vcc + * 1 0 | not writable until next power-down + * 1 1 | not writable, permanently + * + * checked datasheets: W25Q128FV, (W25Q80, W25Q16, + * W25Q32) + * + * For W25Q*{J,D}* parts: + * + * srl srp + * 0 0 | writable if WEL==1 + * 0 1 | writable if WEL==1 && #WP==Vcc + * 1 x | not writable until next power-down + * + * checked datasheets: W25Q132JW, W25Q128JW, W25Q256JV. + * W25Q16DW + */ + } winbond; + }; +}; + /* Current code assumes all callbacks are supplied in this object. */ struct spi_flash_protection_ops { /* -- To view, visit https://review.coreboot.org/c/coreboot/+/42112 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I02828b1f764aea29374e794001e74cdc86a94c92 Gerrit-Change-Number: 42112 Gerrit-PatchSet: 1 Gerrit-Owner: Daniel Gröber (dxld) Gerrit-Reviewer: Daniel Gröber <dxld(a)darkboxed.org> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: mb/google/rex: Fix ISH I2C pad for suspend
by Cliff Huang (Code Review) 30 Sep '23

30 Sep '23

Attention is currently required from: Bora Guvendik, Cliff Huang, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Tarun. Hello Bora Guvendik, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Li1 Feng, Subrata Banik, Tarun, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78179?usp=email to look at the new patch set (#4). Change subject: mb/google/rex: Fix ISH I2C pad for suspend ...................................................................... mb/google/rex: Fix ISH I2C pad for suspend During suspend, the ISH I2C transactions cannot go through because the GPIO pads remain the pervious value. The IO Standby State (IOSSTATE) needs to be changed to keep I2C bus active and functional during suspend. BUG=b:302612549 TEST=on Google/rex platform with ISH enabled, do suspend_stress_test and check that no i2c failure. Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: I9a2c902ed56461f3a535428db399c2050756f2da --- M src/mainboard/google/rex/variants/rex0/fw_config.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/78179/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/78179?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9a2c902ed56461f3a535428db399c2050756f2da Gerrit-Change-Number: 78179 Gerrit-PatchSet: 4 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Li1 Feng <li1.feng(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: cpu/intel/model_206ax: Print supported C-states
by Felix Held (Code Review) 30 Sep '23

30 Sep '23

Attention is currently required from: Patrick Rudolph. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78133?usp=email ) Change subject: cpu/intel/model_206ax: Print supported C-states ...................................................................... Patch Set 4: (1 comment) File src/arch/x86/cpu_common.c: https://review.coreboot.org/c/coreboot/+/78133/comment/f9b6216f_ef663660 : PS4, Line 198: cpuid_eax(0) cpuid_get_max_func() can be used instead of cpuid_eax(0) -- To view, visit https://review.coreboot.org/c/coreboot/+/78133?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I713712a1a104714cbf3091782e564e7e784cf21d Gerrit-Change-Number: 78133 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Sat, 30 Sep 2023 17:40:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: x86/include/arch/cpuid.h: Fix inline assembly
by Felix Held (Code Review) 30 Sep '23

30 Sep '23

Attention is currently required from: Patrick Rudolph. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78192?usp=email ) Change subject: x86/include/arch/cpuid.h: Fix inline assembly ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/78192?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5dc0bb620184a355716b9c8d4206d55554b41ab9 Gerrit-Change-Number: 78192 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Sat, 30 Sep 2023 17:37:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: configs: Fix FSP binaries for config.google.skyrim.with_binaries
by Matt DeVillier (Code Review) 30 Sep '23

30 Sep '23

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78195?usp=email ) Change subject: configs: Fix FSP binaries for config.google.skyrim.with_binaries ...................................................................... configs: Fix FSP binaries for config.google.skyrim.with_binaries CZN binaries were likely placeholders, correct to MDN. Change-Id: I6d355b838d30dca64a9e6206eb6000763cc105a1 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M configs/config.google_skyrim.with_binaries 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/78195/1 diff --git a/configs/config.google_skyrim.with_binaries b/configs/config.google_skyrim.with_binaries index 7c56ceb..a1ace44 100644 --- a/configs/config.google_skyrim.with_binaries +++ b/configs/config.google_skyrim.with_binaries @@ -8,8 +8,8 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_SPL_TABLE_FILE="3rdparty/amd_blobs/mendocino/PSP/TypeId0x55_SplTableBl_MDN.sbin" CONFIG_VGA_BIOS_FILE="3rdparty/amd_blobs/mendocino/MdnGenericVbios.bin" -CONFIG_FSP_M_FILE="3rdparty/amd_blobs/cezanne/CEZANNE_M.fd" -CONFIG_FSP_S_FILE="3rdparty/amd_blobs/cezanne/CEZANNE_S.fd" +CONFIG_FSP_M_FILE="3rdparty/amd_blobs/mendocino/MENDOCINO_M.fd" +CONFIG_FSP_S_FILE="3rdparty/amd_blobs/mendocino/MENDOCINO_S.fd" CONFIG_ASYNC_FILE_LOADING=y CONFIG_PSP_SOFTFUSE_BITS="34 28" CONFIG_UART_PCI_ADDR=0x0 -- To view, visit https://review.coreboot.org/c/coreboot/+/78195?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6d355b838d30dca64a9e6206eb6000763cc105a1 Gerrit-Change-Number: 78195 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: mb/asus/p8z77-m: Fix ACPI S3 suspend
by Keith Hui (Code Review) 30 Sep '23

30 Sep '23

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78205?usp=email ) Change subject: mb/asus/p8z77-m: Fix ACPI S3 suspend ...................................................................... mb/asus/p8z77-m: Fix ACPI S3 suspend Set a bit in super I/O configuration like other variants in the family. Without it S3 suspend totally fails. (It's safe to set it in devicetree; it needs not be done in early board init.) TEST=I have working S3 again. Change-Id: Ia8059b2a263ab5c459e54685f046eeb913776473 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/78205/1 diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb index cad9c5c..476b305 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb @@ -47,6 +47,7 @@ drq 0xe1 = 0x80 # GP07 high end device pnp 2e.a on # ACPI + drq 0xe4 = 0x10 # Enable 3VSBSW#, needed for S3 suspend drq 0xe7 = 0x11 # HWM reset by LRESET#, 0.5s S3 delay for compatibility drq 0xf2 = 0x5d # Enable RSTOUT[0-2]# and PME end -- To view, visit https://review.coreboot.org/c/coreboot/+/78205?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia8059b2a263ab5c459e54685f046eeb913776473 Gerrit-Change-Number: 78205 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-MessageType: newchange

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