coreboot-gerrit September 2023

coreboot-gerrit@coreboot.org

1 participants
3799 discussions

[XS] Change in coreboot[main]: configs: Fix FSP binaries for config.google.skyrim.with_binaries
by Matt DeVillier (Code Review) 30 Sep '23

30 Sep '23

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78195?usp=email ) Change subject: configs: Fix FSP binaries for config.google.skyrim.with_binaries ...................................................................... configs: Fix FSP binaries for config.google.skyrim.with_binaries CZN binaries were likely placeholders, correct to MDN. Change-Id: I6d355b838d30dca64a9e6206eb6000763cc105a1 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M configs/config.google_skyrim.with_binaries 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/78195/1 diff --git a/configs/config.google_skyrim.with_binaries b/configs/config.google_skyrim.with_binaries index 7c56ceb..a1ace44 100644 --- a/configs/config.google_skyrim.with_binaries +++ b/configs/config.google_skyrim.with_binaries @@ -8,8 +8,8 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_SPL_TABLE_FILE="3rdparty/amd_blobs/mendocino/PSP/TypeId0x55_SplTableBl_MDN.sbin" CONFIG_VGA_BIOS_FILE="3rdparty/amd_blobs/mendocino/MdnGenericVbios.bin" -CONFIG_FSP_M_FILE="3rdparty/amd_blobs/cezanne/CEZANNE_M.fd" -CONFIG_FSP_S_FILE="3rdparty/amd_blobs/cezanne/CEZANNE_S.fd" +CONFIG_FSP_M_FILE="3rdparty/amd_blobs/mendocino/MENDOCINO_M.fd" +CONFIG_FSP_S_FILE="3rdparty/amd_blobs/mendocino/MENDOCINO_S.fd" CONFIG_ASYNC_FILE_LOADING=y CONFIG_PSP_SOFTFUSE_BITS="34 28" CONFIG_UART_PCI_ADDR=0x0 -- To view, visit https://review.coreboot.org/c/coreboot/+/78195?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6d355b838d30dca64a9e6206eb6000763cc105a1 Gerrit-Change-Number: 78195 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

1 0

[XS] Change in coreboot[main]: mb/asus/p8z77-m: Fix ACPI S3 suspend
by Keith Hui (Code Review) 30 Sep '23

30 Sep '23

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78205?usp=email ) Change subject: mb/asus/p8z77-m: Fix ACPI S3 suspend ...................................................................... mb/asus/p8z77-m: Fix ACPI S3 suspend Set a bit in super I/O configuration like other variants in the family. Without it S3 suspend totally fails. (It's safe to set it in devicetree; it needs not be done in early board init.) TEST=I have working S3 again. Change-Id: Ia8059b2a263ab5c459e54685f046eeb913776473 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/78205/1 diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb index cad9c5c..476b305 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb @@ -47,6 +47,7 @@ drq 0xe1 = 0x80 # GP07 high end device pnp 2e.a on # ACPI + drq 0xe4 = 0x10 # Enable 3VSBSW#, needed for S3 suspend drq 0xe7 = 0x11 # HWM reset by LRESET#, 0.5s S3 delay for compatibility drq 0xf2 = 0x5d # Enable RSTOUT[0-2]# and PME end -- To view, visit https://review.coreboot.org/c/coreboot/+/78205?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia8059b2a263ab5c459e54685f046eeb913776473 Gerrit-Change-Number: 78205 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[main]: Documentation/mb/asus/p8z77-m: Latest test results
by Keith Hui (Code Review) 30 Sep '23

30 Sep '23

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78204?usp=email ) Change subject: Documentation/mb/asus/p8z77-m: Latest test results ...................................................................... Documentation/mb/asus/p8z77-m: Latest test results Documents latest results with this board. Mostly RAM related, but also success with edk2. Change-Id: I4f4c9268cd272caa83267be3f71d4a2022c26a1c Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M Documentation/mainboard/asus/p8z77-m.md 1 file changed, 17 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/78204/1 diff --git a/Documentation/mainboard/asus/p8z77-m.md b/Documentation/mainboard/asus/p8z77-m.md index a701169..428a0f5 100644 --- a/Documentation/mainboard/asus/p8z77-m.md +++ b/Documentation/mainboard/asus/p8z77-m.md @@ -58,6 +58,7 @@ - S3 suspend from Linux - 2-channel analog audio (WAV playback by mplayer via back panel line out port) - Windows 10 with libgfxinit high resolution framebuffer and VBT +- UEFI boot into Fedora 38 with edk2 payload ## Known issues @@ -86,16 +87,27 @@ - 4 and 6 channel analog audio out: Rear left and right audio is a muted copy of front left and right audio, and the other two channels are silent. -## Native (and MRC) raminit compatibility +## RAM compatibility + +### Native and MRC raminit: - OCZ OCZ3G1600LVAM 2x2GB kit works at DDR3-1066 instead of DDR3-1600. - -- GSkill F3-1600C9D-16GRSL 2x8GB SODIMM kit on adapter boots, but is highly unstable - with obvious pattern of bit errors during memtest86+ runs. - - Samsung PC3-10600U 2x2GB kit works at full rated speed. +### MRC raminit: + +- Corsair ValueSelect CMSO4GX3M1C1600C11 4GB SODIMM works at full rated speed + on an unbranded adapter. +- Samsung PC3-12800S 4GB SODIMM on adapter works at full rated speed. +- GSkill F3-1600C9D-16GRSL 2x8GB SODIMM kit on adapter works at full rated speed. + +### Native raminit: + +- It appears all memory modules rated for DDR3-1600 will fail to boot if + max_mem_clock_mhz is set to 800 in devicetree. - Kingston KTH9600B-4G 2x4GB kit works at full rated speed. +- Only one module is detected with Corsair ValueSelect and Samsung SODIMM above. +- GSkill SODIMM kit apparently works at full rated speed with reduced max_mem_clock_mhz. ## Extra onboard buttons -- To view, visit https://review.coreboot.org/c/coreboot/+/78204?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4f4c9268cd272caa83267be3f71d4a2022c26a1c Gerrit-Change-Number: 78204 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-MessageType: newchange

1 0

[XS] Change in coreboot[main]: soc/amd/common/noncar/cpu: simplify get_reserved_phys_addr_bits
by Matt DeVillier (Code Review) 30 Sep '23

30 Sep '23

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78176?usp=email ) Change subject: soc/amd/common/noncar/cpu: simplify get_reserved_phys_addr_bits ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78176?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7536b82d98e55c51105448090d1206e1ed7f62d8 Gerrit-Change-Number: 78176 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 30 Sep 2023 15:17:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: soc/amd/common: use common physical address bit reservation code
by Matt DeVillier (Code Review) 30 Sep '23

30 Sep '23

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Jérémy Compostella, Marshall Dawson. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78074?usp=email ) Change subject: soc/amd/common: use common physical address bit reservation code ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78074?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iad65144006f1116cd82efc3c94e1d6d1ccb31b6e Gerrit-Change-Number: 78074 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 30 Sep 2023 15:16:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[L] Change in coreboot[main]: security/tpm/: turn tis_{init,open} into tis_probe
by Sergii Dmytruk (Code Review) 30 Sep '23

30 Sep '23

Attention is currently required from: Arthur Heymans, Christian Walter, Felix Held, Krystian Hebel, Michał Żygowski, Sergii Dmytruk. Hello Arthur Heymans, Christian Walter, Felix Held, Julius Werner, Krystian Hebel, Michał Żygowski, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/76954?usp=email to look at the new patch set (#5). Change subject: security/tpm/: turn tis_{init,open} into tis_probe ...................................................................... security/tpm/: turn tis_{init,open} into tis_probe init() was always followed by open() and after successful initialization we only need send-receive function which is now returned by tis_probe() on success, thus further reducing number of functions to export from drivers. This also removes check for opening TIS twice that seems to have no value. Change-Id: I52ad8d69d50d449f031c36b15bf70ef07986946c Ticket: https://ticket.coreboot.org/issues/433 Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M src/drivers/crb/tis.c M src/drivers/i2c/tpm/cr50.c M src/drivers/i2c/tpm/tis.c M src/drivers/i2c/tpm/tis_atmel.c M src/drivers/i2c/tpm/tpm.c M src/drivers/i2c/tpm/tpm.h M src/drivers/pc80/tpm/tis.c M src/drivers/spi/tpm/tis.c M src/security/tpm/tis.h M src/security/tpm/tss/tcg-1.2/tss.c M src/security/tpm/tss/tcg-2.0/tss.c 11 files changed, 141 insertions(+), 179 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/76954/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/76954?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I52ad8d69d50d449f031c36b15bf70ef07986946c Gerrit-Change-Number: 76954 Gerrit-PatchSet: 5 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

1 0

[XS] Change in coreboot[main]: mb/asus/p8z77-m: Remove settings to replicate OEM
by Keith Hui (Code Review) 30 Sep '23

30 Sep '23

Attention is currently required from: Fabian Groffen, Keith Hui. Keith Hui has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75137?usp=email ) Change subject: mb/asus/p8z77-m: Remove settings to replicate OEM ...................................................................... Patch Set 4: (1 comment) File src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb: https://review.coreboot.org/c/coreboot/+/75137/comment/5633a2cf_5e3e8f89 : PS4, Line 30: drq 0x1a = 0x02 > Can you test with these two settings (0x1a,0x1b) retained if serial port still work? I did this test. Serial port still works both ways. These two lines should also stay. -- To view, visit https://review.coreboot.org/c/coreboot/+/75137?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iae526762e79e9e2d46d06e12c338f375e5555e8c Gerrit-Change-Number: 75137 Gerrit-PatchSet: 4 Gerrit-Owner: Fabian Groffen <grobian(a)gentoo.org> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Keith Hui <buurin(a)gmail.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Fabian Groffen <grobian(a)gentoo.org> Gerrit-Comment-Date: Sat, 30 Sep 2023 14:07:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Keith Hui <buurin(a)gmail.com> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: x86/include/arch/cpuid.h: Fix inline assembly
by Krystian Hebel (Code Review) 30 Sep '23

30 Sep '23

Attention is currently required from: Patrick Rudolph. Krystian Hebel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78192?usp=email ) Change subject: x86/include/arch/cpuid.h: Fix inline assembly ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78192?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5dc0bb620184a355716b9c8d4206d55554b41ab9 Gerrit-Change-Number: 78192 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Sat, 30 Sep 2023 13:19:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[M] Change in coreboot[main]: cpu/intel/model_206ax: Only use supported C-states
by Patrick Rudolph (Code Review) 30 Sep '23

30 Sep '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78194?usp=email ) Change subject: cpu/intel/model_206ax: Only use supported C-states ...................................................................... cpu/intel/model_206ax: Only use supported C-states Make sure that the C-state is supported by the CPU. Downgrade if it's not and make sure to not advertise duplicate states. Add debug prints for the finally selected mapping of ACPI C state vs Intel CPU C state. Change-Id: Iaaee050e0ce3c29c12e97f5819a29f485a7946c2 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/intel/model_206ax/acpi.c 1 file changed, 57 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/78194/1 diff --git a/src/cpu/intel/model_206ax/acpi.c b/src/cpu/intel/model_206ax/acpi.c index 785fcb9..0273c70 100644 --- a/src/cpu/intel/model_206ax/acpi.c +++ b/src/cpu/intel/model_206ax/acpi.c @@ -88,11 +88,36 @@ printk(BIOS_DEBUG, "Supported C-states: C0 %s\n", str); } +/* + * Returns the supported C-state or the next lower one that + * is supported. + */ +static int get_supported_cstate(int cstate) +{ + uint8_t h, l; + size_t i; + + assert(cstate < NUM_C_STATES); + + for (i = cstate; i > 0; i--) { + h = (cstate_map[i].resource.addrl >> 4) + 1; + l = cstate_map[i].resource.addrl & 0xf; + if (cpu_get_c_state_support(h) > l) + break; + } + + if (cstate != i) + printk(BIOS_DEBUG, "Requested C-state %s not supported, using %s instead\n", + c_state_names[cstate], c_state_names[i]); + + return i; +} + static void generate_C_state_entries(const struct device *dev) { struct cpu_intel_model_206ax_config *conf = dev->chip_info; - const int acpi_cstates[3] = { conf->acpi_c1, conf->acpi_c2, conf->acpi_c3 }; + int acpi_cstates[3] = { conf->acpi_c1, conf->acpi_c2, conf->acpi_c3 }; acpi_cstate_t acpi_cstate_map[ARRAY_SIZE(acpi_cstates)] = { 0 }; /* Count number of active C-states */ @@ -101,12 +126,39 @@ print_supported_cstates(); for (int i = 0; i < ARRAY_SIZE(acpi_cstates); i++) { - if (acpi_cstates[i] > 0 && acpi_cstates[i] < ARRAY_SIZE(cstate_map)) { - acpi_cstate_map[count] = cstate_map[acpi_cstates[i]]; - acpi_cstate_map[count].ctype = i + 1; - count++; + /* Remove invalid states */ + if (acpi_cstates[i] >= ARRAY_SIZE(cstate_map)) { + printk(BIOS_ERR, "Invalid C-state in devicetree: %d\n", + acpi_cstates[i]); + acpi_cstates[i] = 0; + continue; + } + /* Skip C0, it's always supported */ + if (acpi_cstates[i] == 0) + continue; + + /* Find supported state. Might downgrade a state. */ + acpi_cstates[i] = get_supported_cstate(acpi_cstates[i]); + + /* Remove duplicate states */ + for (int j = i - 1; j >= 0; j--) { + if (acpi_cstates[i] == acpi_cstates[j]) { + acpi_cstates[i] = 0; + break; + } } } + + /* Convert C-state to ACPI C-states */ + for (int i = 0; i < ARRAY_SIZE(acpi_cstates); i++) { + if (acpi_cstates[i] == 0) + continue; + acpi_cstate_map[count] = cstate_map[acpi_cstates[i]]; + count++; + printk(BIOS_DEBUG, "Advertising ACPI C State type C%d as CPU %s\n", + count, c_state_names[acpi_cstates[i]]); + } + acpigen_write_CST_package(acpi_cstate_map, count); } -- To view, visit https://review.coreboot.org/c/coreboot/+/78194?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaaee050e0ce3c29c12e97f5819a29f485a7946c2 Gerrit-Change-Number: 78194 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[main]: cpu/intel/model_206ax: Use haswell cstate_map
by Patrick Rudolph (Code Review) 30 Sep '23

30 Sep '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78193?usp=email ) Change subject: cpu/intel/model_206ax: Use haswell cstate_map ...................................................................... cpu/intel/model_206ax: Use haswell cstate_map Change-Id: Ie7076d11720d55a4ac11318cbbdab9f75d08e15e Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/intel/model_206ax/acpi.c M src/cpu/intel/model_206ax/model_206ax.h 2 files changed, 37 insertions(+), 50 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/78193/1 diff --git a/src/cpu/intel/model_206ax/acpi.c b/src/cpu/intel/model_206ax/acpi.c index d72e300..785fcb9 100644 --- a/src/cpu/intel/model_206ax/acpi.c +++ b/src/cpu/intel/model_206ax/acpi.c @@ -13,79 +13,52 @@ #include "model_206ax.h" #include "chip.h" +#define MWAIT_RES(state, sub_state) \ + { \ + .addrl = (((state) << 4) | (sub_state)), \ + .space_id = ACPI_ADDRESS_SPACE_FIXED, \ + .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \ + .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \ + .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \ + } + /* * List of supported C-states in this processor * * Latencies are typical worst-case package exit time in uS * taken from the SandyBridge BIOS specification. */ -static const acpi_cstate_t cstate_map[] = { - { /* 0: C0 */ - }, { /* 1: C1 */ +static acpi_cstate_t cstate_map[NUM_C_STATES] = { + [C_STATE_C0] = { }, + [C_STATE_C1] = { .latency = 1, .power = 1000, - .resource = { - .addrl = 0x00, /* MWAIT State 0 */ - .space_id = ACPI_ADDRESS_SPACE_FIXED, - .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, - .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, - .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, - } + .resource = MWAIT_RES(0, 0), }, - { /* 2: C1E */ + [C_STATE_C1E] = { .latency = 1, .power = 1000, - .resource = { - .addrl = 0x01, /* MWAIT State 0 Sub-state 1 */ - .space_id = ACPI_ADDRESS_SPACE_FIXED, - .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, - .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, - .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, - } + .resource = MWAIT_RES(0, 1), }, - { /* 3: C3 */ + [C_STATE_C3] = { .latency = 63, .power = 500, - .resource = { - .addrl = 0x10, /* MWAIT State 1 */ - .space_id = ACPI_ADDRESS_SPACE_FIXED, - .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, - .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, - .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, - } + .resource = MWAIT_RES(1, 0), }, - { /* 4: C6 */ + [C_STATE_C6] = { .latency = 87, .power = 350, - .resource = { - .addrl = 0x20, /* MWAIT State 2 */ - .space_id = ACPI_ADDRESS_SPACE_FIXED, - .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, - .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, - .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, - } + .resource = MWAIT_RES(2, 0), }, - { /* 5: C7 */ + [C_STATE_C7] = { .latency = 90, .power = 200, - .resource = { - .addrl = 0x30, /* MWAIT State 3 */ - .space_id = ACPI_ADDRESS_SPACE_FIXED, - .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, - .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, - .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, - } + .resource = MWAIT_RES(3, 0), }, - { /* 6: C7S */ + [C_STATE_C7S] = { .latency = 90, .power = 200, - .resource = { - .addrl = 0x31, /* MWAIT State 3 Sub-state 1 */ - .space_id = ACPI_ADDRESS_SPACE_FIXED, - .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, - .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, - .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, - } + .resource = MWAIT_RES(3, 1), }, }; diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h index b145523..ecbf323 100644 --- a/src/cpu/intel/model_206ax/model_206ax.h +++ b/src/cpu/intel/model_206ax/model_206ax.h @@ -109,6 +109,20 @@ # error "CONFIG_IED_REGION_SIZE is not a power of 2" #endif +/* + * List of supported C-states for Sandy Bridge/Ivy Bridge. + */ +enum { + C_STATE_C0 = 0, + C_STATE_C1 = 1, + C_STATE_C1E = 2, + C_STATE_C3 = 3, + C_STATE_C6 = 4, + C_STATE_C7 = 5, + C_STATE_C7S = 6, + NUM_C_STATES, +}; + /* Lock MSRs */ void intel_model_206ax_finalize_smm(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/78193?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie7076d11720d55a4ac11318cbbdab9f75d08e15e Gerrit-Change-Number: 78193 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

1 0

← Newer
1
2
3
4
5
6
7
...
380
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit September 2023