coreboot-gerrit September 2023

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[S] Change in coreboot[main]: soc/amd/common: use common physical address bit reservation code
by Matt DeVillier (Code Review) 30 Sep '23

30 Sep '23

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Jérémy Compostella, Marshall Dawson. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78074?usp=email ) Change subject: soc/amd/common: use common physical address bit reservation code ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78074?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iad65144006f1116cd82efc3c94e1d6d1ccb31b6e Gerrit-Change-Number: 78074 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 30 Sep 2023 15:16:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[main]: security/tpm/: turn tis_{init,open} into tis_probe
by Sergii Dmytruk (Code Review) 30 Sep '23

30 Sep '23

Attention is currently required from: Arthur Heymans, Christian Walter, Felix Held, Krystian Hebel, Michał Żygowski, Sergii Dmytruk. Hello Arthur Heymans, Christian Walter, Felix Held, Julius Werner, Krystian Hebel, Michał Żygowski, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/76954?usp=email to look at the new patch set (#5). Change subject: security/tpm/: turn tis_{init,open} into tis_probe ...................................................................... security/tpm/: turn tis_{init,open} into tis_probe init() was always followed by open() and after successful initialization we only need send-receive function which is now returned by tis_probe() on success, thus further reducing number of functions to export from drivers. This also removes check for opening TIS twice that seems to have no value. Change-Id: I52ad8d69d50d449f031c36b15bf70ef07986946c Ticket: https://ticket.coreboot.org/issues/433 Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M src/drivers/crb/tis.c M src/drivers/i2c/tpm/cr50.c M src/drivers/i2c/tpm/tis.c M src/drivers/i2c/tpm/tis_atmel.c M src/drivers/i2c/tpm/tpm.c M src/drivers/i2c/tpm/tpm.h M src/drivers/pc80/tpm/tis.c M src/drivers/spi/tpm/tis.c M src/security/tpm/tis.h M src/security/tpm/tss/tcg-1.2/tss.c M src/security/tpm/tss/tcg-2.0/tss.c 11 files changed, 141 insertions(+), 179 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/76954/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/76954?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I52ad8d69d50d449f031c36b15bf70ef07986946c Gerrit-Change-Number: 76954 Gerrit-PatchSet: 5 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: mb/asus/p8z77-m: Remove settings to replicate OEM
by Keith Hui (Code Review) 30 Sep '23

30 Sep '23

Attention is currently required from: Fabian Groffen, Keith Hui. Keith Hui has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75137?usp=email ) Change subject: mb/asus/p8z77-m: Remove settings to replicate OEM ...................................................................... Patch Set 4: (1 comment) File src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb: https://review.coreboot.org/c/coreboot/+/75137/comment/5633a2cf_5e3e8f89 : PS4, Line 30: drq 0x1a = 0x02 > Can you test with these two settings (0x1a,0x1b) retained if serial port still work? I did this test. Serial port still works both ways. These two lines should also stay. -- To view, visit https://review.coreboot.org/c/coreboot/+/75137?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iae526762e79e9e2d46d06e12c338f375e5555e8c Gerrit-Change-Number: 75137 Gerrit-PatchSet: 4 Gerrit-Owner: Fabian Groffen <grobian(a)gentoo.org> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Keith Hui <buurin(a)gmail.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Fabian Groffen <grobian(a)gentoo.org> Gerrit-Comment-Date: Sat, 30 Sep 2023 14:07:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Keith Hui <buurin(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: x86/include/arch/cpuid.h: Fix inline assembly
by Krystian Hebel (Code Review) 30 Sep '23

30 Sep '23

Attention is currently required from: Patrick Rudolph. Krystian Hebel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78192?usp=email ) Change subject: x86/include/arch/cpuid.h: Fix inline assembly ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78192?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5dc0bb620184a355716b9c8d4206d55554b41ab9 Gerrit-Change-Number: 78192 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Sat, 30 Sep 2023 13:19:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: cpu/intel/model_206ax: Only use supported C-states
by Patrick Rudolph (Code Review) 30 Sep '23

30 Sep '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78194?usp=email ) Change subject: cpu/intel/model_206ax: Only use supported C-states ...................................................................... cpu/intel/model_206ax: Only use supported C-states Make sure that the C-state is supported by the CPU. Downgrade if it's not and make sure to not advertise duplicate states. Add debug prints for the finally selected mapping of ACPI C state vs Intel CPU C state. Change-Id: Iaaee050e0ce3c29c12e97f5819a29f485a7946c2 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/intel/model_206ax/acpi.c 1 file changed, 57 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/78194/1 diff --git a/src/cpu/intel/model_206ax/acpi.c b/src/cpu/intel/model_206ax/acpi.c index 785fcb9..0273c70 100644 --- a/src/cpu/intel/model_206ax/acpi.c +++ b/src/cpu/intel/model_206ax/acpi.c @@ -88,11 +88,36 @@ printk(BIOS_DEBUG, "Supported C-states: C0 %s\n", str); } +/* + * Returns the supported C-state or the next lower one that + * is supported. + */ +static int get_supported_cstate(int cstate) +{ + uint8_t h, l; + size_t i; + + assert(cstate < NUM_C_STATES); + + for (i = cstate; i > 0; i--) { + h = (cstate_map[i].resource.addrl >> 4) + 1; + l = cstate_map[i].resource.addrl & 0xf; + if (cpu_get_c_state_support(h) > l) + break; + } + + if (cstate != i) + printk(BIOS_DEBUG, "Requested C-state %s not supported, using %s instead\n", + c_state_names[cstate], c_state_names[i]); + + return i; +} + static void generate_C_state_entries(const struct device *dev) { struct cpu_intel_model_206ax_config *conf = dev->chip_info; - const int acpi_cstates[3] = { conf->acpi_c1, conf->acpi_c2, conf->acpi_c3 }; + int acpi_cstates[3] = { conf->acpi_c1, conf->acpi_c2, conf->acpi_c3 }; acpi_cstate_t acpi_cstate_map[ARRAY_SIZE(acpi_cstates)] = { 0 }; /* Count number of active C-states */ @@ -101,12 +126,39 @@ print_supported_cstates(); for (int i = 0; i < ARRAY_SIZE(acpi_cstates); i++) { - if (acpi_cstates[i] > 0 && acpi_cstates[i] < ARRAY_SIZE(cstate_map)) { - acpi_cstate_map[count] = cstate_map[acpi_cstates[i]]; - acpi_cstate_map[count].ctype = i + 1; - count++; + /* Remove invalid states */ + if (acpi_cstates[i] >= ARRAY_SIZE(cstate_map)) { + printk(BIOS_ERR, "Invalid C-state in devicetree: %d\n", + acpi_cstates[i]); + acpi_cstates[i] = 0; + continue; + } + /* Skip C0, it's always supported */ + if (acpi_cstates[i] == 0) + continue; + + /* Find supported state. Might downgrade a state. */ + acpi_cstates[i] = get_supported_cstate(acpi_cstates[i]); + + /* Remove duplicate states */ + for (int j = i - 1; j >= 0; j--) { + if (acpi_cstates[i] == acpi_cstates[j]) { + acpi_cstates[i] = 0; + break; + } } } + + /* Convert C-state to ACPI C-states */ + for (int i = 0; i < ARRAY_SIZE(acpi_cstates); i++) { + if (acpi_cstates[i] == 0) + continue; + acpi_cstate_map[count] = cstate_map[acpi_cstates[i]]; + count++; + printk(BIOS_DEBUG, "Advertising ACPI C State type C%d as CPU %s\n", + count, c_state_names[acpi_cstates[i]]); + } + acpigen_write_CST_package(acpi_cstate_map, count); } -- To view, visit https://review.coreboot.org/c/coreboot/+/78194?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaaee050e0ce3c29c12e97f5819a29f485a7946c2 Gerrit-Change-Number: 78194 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: cpu/intel/model_206ax: Use haswell cstate_map
by Patrick Rudolph (Code Review) 30 Sep '23

30 Sep '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78193?usp=email ) Change subject: cpu/intel/model_206ax: Use haswell cstate_map ...................................................................... cpu/intel/model_206ax: Use haswell cstate_map Change-Id: Ie7076d11720d55a4ac11318cbbdab9f75d08e15e Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/intel/model_206ax/acpi.c M src/cpu/intel/model_206ax/model_206ax.h 2 files changed, 37 insertions(+), 50 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/78193/1 diff --git a/src/cpu/intel/model_206ax/acpi.c b/src/cpu/intel/model_206ax/acpi.c index d72e300..785fcb9 100644 --- a/src/cpu/intel/model_206ax/acpi.c +++ b/src/cpu/intel/model_206ax/acpi.c @@ -13,79 +13,52 @@ #include "model_206ax.h" #include "chip.h" +#define MWAIT_RES(state, sub_state) \ + { \ + .addrl = (((state) << 4) | (sub_state)), \ + .space_id = ACPI_ADDRESS_SPACE_FIXED, \ + .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \ + .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \ + .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \ + } + /* * List of supported C-states in this processor * * Latencies are typical worst-case package exit time in uS * taken from the SandyBridge BIOS specification. */ -static const acpi_cstate_t cstate_map[] = { - { /* 0: C0 */ - }, { /* 1: C1 */ +static acpi_cstate_t cstate_map[NUM_C_STATES] = { + [C_STATE_C0] = { }, + [C_STATE_C1] = { .latency = 1, .power = 1000, - .resource = { - .addrl = 0x00, /* MWAIT State 0 */ - .space_id = ACPI_ADDRESS_SPACE_FIXED, - .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, - .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, - .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, - } + .resource = MWAIT_RES(0, 0), }, - { /* 2: C1E */ + [C_STATE_C1E] = { .latency = 1, .power = 1000, - .resource = { - .addrl = 0x01, /* MWAIT State 0 Sub-state 1 */ - .space_id = ACPI_ADDRESS_SPACE_FIXED, - .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, - .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, - .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, - } + .resource = MWAIT_RES(0, 1), }, - { /* 3: C3 */ + [C_STATE_C3] = { .latency = 63, .power = 500, - .resource = { - .addrl = 0x10, /* MWAIT State 1 */ - .space_id = ACPI_ADDRESS_SPACE_FIXED, - .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, - .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, - .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, - } + .resource = MWAIT_RES(1, 0), }, - { /* 4: C6 */ + [C_STATE_C6] = { .latency = 87, .power = 350, - .resource = { - .addrl = 0x20, /* MWAIT State 2 */ - .space_id = ACPI_ADDRESS_SPACE_FIXED, - .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, - .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, - .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, - } + .resource = MWAIT_RES(2, 0), }, - { /* 5: C7 */ + [C_STATE_C7] = { .latency = 90, .power = 200, - .resource = { - .addrl = 0x30, /* MWAIT State 3 */ - .space_id = ACPI_ADDRESS_SPACE_FIXED, - .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, - .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, - .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, - } + .resource = MWAIT_RES(3, 0), }, - { /* 6: C7S */ + [C_STATE_C7S] = { .latency = 90, .power = 200, - .resource = { - .addrl = 0x31, /* MWAIT State 3 Sub-state 1 */ - .space_id = ACPI_ADDRESS_SPACE_FIXED, - .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, - .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, - .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, - } + .resource = MWAIT_RES(3, 1), }, }; diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h index b145523..ecbf323 100644 --- a/src/cpu/intel/model_206ax/model_206ax.h +++ b/src/cpu/intel/model_206ax/model_206ax.h @@ -109,6 +109,20 @@ # error "CONFIG_IED_REGION_SIZE is not a power of 2" #endif +/* + * List of supported C-states for Sandy Bridge/Ivy Bridge. + */ +enum { + C_STATE_C0 = 0, + C_STATE_C1 = 1, + C_STATE_C1E = 2, + C_STATE_C3 = 3, + C_STATE_C6 = 4, + C_STATE_C7 = 5, + C_STATE_C7S = 6, + NUM_C_STATES, +}; + /* Lock MSRs */ void intel_model_206ax_finalize_smm(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/78193?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie7076d11720d55a4ac11318cbbdab9f75d08e15e Gerrit-Change-Number: 78193 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: x86/include/arch/cpuid.h: Fix inline assembly
by Patrick Rudolph (Code Review) 30 Sep '23

30 Sep '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78192?usp=email ) Change subject: x86/include/arch/cpuid.h: Fix inline assembly ...................................................................... x86/include/arch/cpuid.h: Fix inline assembly In the cpuid helper function eax is always written to by cpuid, so add it to the output clobbered list. This prevent GCC from generating code with undefined behaviour when the function is inlined. Change-Id: I5dc0bb620184a355716b9c8d4206d55554b41ab9 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/arch/x86/include/arch/cpuid.h 1 file changed, 9 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/78192/1 diff --git a/src/arch/x86/include/arch/cpuid.h b/src/arch/x86/include/arch/cpuid.h index 70a5beb..b2780be 100644 --- a/src/arch/x86/include/arch/cpuid.h +++ b/src/arch/x86/include/arch/cpuid.h @@ -56,39 +56,36 @@ return eax; } -static inline uint32_t cpuid_ebx(const uint32_t eax) +static inline uint32_t cpuid_ebx(uint32_t eax) { uint32_t ebx; asm volatile( "cpuid;" - : "=b" (ebx) - : "a" (eax) - : "ecx", "edx"); + : "=b" (ebx), "+a" (eax) + :: "ecx", "edx"); return ebx; } -static inline uint32_t cpuid_ecx(const uint32_t eax) +static inline uint32_t cpuid_ecx(uint32_t eax) { uint32_t ecx; asm volatile( "cpuid;" - : "=c" (ecx) - : "a" (eax) - : "ebx", "edx"); + : "=c" (ecx), "+a" (eax) + :: "ebx", "edx"); return ecx; } -static inline uint32_t cpuid_edx(const uint32_t eax) +static inline uint32_t cpuid_edx(uint32_t eax) { uint32_t edx; asm volatile( "cpuid;" - : "=d" (edx) - : "a" (eax) - : "ebx", "ecx"); + : "=d" (edx), "+a" (eax) + :: "ebx", "ecx"); return edx; } -- To view, visit https://review.coreboot.org/c/coreboot/+/78192?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5dc0bb620184a355716b9c8d4206d55554b41ab9 Gerrit-Change-Number: 78192 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: cpu/intel/model_206ax: Print supported C-states
by Patrick Rudolph (Code Review) 30 Sep '23

30 Sep '23

Attention is currently required from: Patrick Rudolph. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78133?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: cpu/intel/model_206ax: Print supported C-states ...................................................................... cpu/intel/model_206ax: Print supported C-states According to the BWG C-states are processor specific. Print the supported C-states in model_206ax_report(). Test: Tested on i5-2540M. Change-Id: I713712a1a104714cbf3091782e564e7e784cf21d Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/arch/x86/cpu_common.c M src/arch/x86/include/arch/cpu.h M src/cpu/intel/model_206ax/acpi.c 3 files changed, 47 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/78133/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/78133?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I713712a1a104714cbf3091782e564e7e784cf21d Gerrit-Change-Number: 78133 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: security/tpm: support compiling in multiple TPM drivers
by Sergii Dmytruk (Code Review) 30 Sep '23

30 Sep '23

Attention is currently required from: Christian Walter, Felix Held, Fred Reitberger, Jason Glenesk, Julius Werner, Krystian Hebel, Matt DeVillier, Michał Żygowski, Raul Rangel, Sergii Dmytruk. Hello Christian Walter, Felix Held, Fred Reitberger, Jason Glenesk, Julius Werner, Krystian Hebel, Matt DeVillier, Michał Żygowski, Raul Rangel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69162?usp=email to look at the new patch set (#19). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: security/tpm: support compiling in multiple TPM drivers ...................................................................... security/tpm: support compiling in multiple TPM drivers Starting from here CONFIG_TPM1 and CONFIG_TPM2 are no longer mutually exclusive. Making probe functions static and always using them uncovered that bootblock stage included TPM driver which it didn't use. This is why Makefile.inc files were updated to replace `all-*` with romstage, ramstage and verstage. Change-Id: I44c5a1d825afe414c2f5c2c90f4cfe41ba9bef5f Ticket: https://ticket.coreboot.org/issues/433 Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M src/drivers/crb/Makefile.inc M src/drivers/crb/tis.c M src/drivers/i2c/tpm/Makefile.inc M src/drivers/i2c/tpm/tis.c M src/drivers/i2c/tpm/tis_atmel.c M src/drivers/pc80/tpm/Makefile.inc M src/drivers/pc80/tpm/tis.c M src/drivers/spi/tpm/Makefile.inc M src/drivers/spi/tpm/tis.c M src/lib/program.ld M src/security/tpm/Kconfig M src/security/tpm/tis.h M src/security/tpm/tss/tss.c M src/soc/amd/common/block/cpu/noncar/memlayout_psp_verstage.ld 14 files changed, 81 insertions(+), 34 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/69162/19 -- To view, visit https://review.coreboot.org/c/coreboot/+/69162?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I44c5a1d825afe414c2f5c2c90f4cfe41ba9bef5f Gerrit-Change-Number: 69162 Gerrit-PatchSet: 19 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: security/tpm: replace CONFIG(TPMx) checks with runtime check
by Sergii Dmytruk (Code Review) 30 Sep '23

30 Sep '23

Attention is currently required from: Christian Walter, Jan Samek, Julius Werner, Krystian Hebel, Lance Zhao, Martin L Roth, Michał Żygowski, Sergii Dmytruk, Tim Wawrzynczak. Hello Christian Walter, Julius Werner, Krystian Hebel, Lance Zhao, Michał Żygowski, Tim Wawrzynczak, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69161?usp=email to look at the new patch set (#18). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: security/tpm: replace CONFIG(TPMx) checks with runtime check ...................................................................... security/tpm: replace CONFIG(TPMx) checks with runtime check This prepares the code for enabling both CONFIG_TPM1 and CONFIG_TPM2 during compilation, in which case actual TPM family in use can be determined at runtime. In some places both compile time and runtime checks are necessary. Change-Id: Id9cc25aad8d1d7bfad12b7a92059b1b3641bbfa9 Ticket: https://ticket.coreboot.org/issues/433 Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M src/acpi/acpi.c M src/drivers/crb/tis.c M src/drivers/pc80/tpm/tis.c M src/drivers/tpm/ppi.c M src/security/tpm/tspi/crtm.h M src/security/tpm/tspi/tspi.c M src/security/tpm/tss.h M src/security/vboot/secdata_tpm.c M src/security/vboot/tpm_common.c M src/vendorcode/google/chromeos/cse_board_reset.c M src/vendorcode/google/chromeos/tpm2.c 11 files changed, 116 insertions(+), 63 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/69161/18 -- To view, visit https://review.coreboot.org/c/coreboot/+/69161?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id9cc25aad8d1d7bfad12b7a92059b1b3641bbfa9 Gerrit-Change-Number: 69161 Gerrit-PatchSet: 18 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jan Samek <jan.samek(a)siemens.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Jan Samek <jan.samek(a)siemens.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit September 2023