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Change subject: soc/intel/alderlake: Hook up FSP repo for RPL-P/S
......................................................................
soc/intel/alderlake: Hook up FSP repo for RPL-P/S
Now that Intel has publicly released FSP headers/binaries for
RaptorLake-P/S client platforms, set the defaults accordingly if
FSP_USE_REPO is not selected. This does not change any existing
defaults as the RaptorLake headers in vendorcode are only used when
FSP_USE_REPO is not set.
TEST=build/boot google/brya (osiris)
Change-Id: Ida92d269fcaf6f323599ec174f4dcedbbe65f03c
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
M src/soc/intel/alderlake/Kconfig
1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/78190/1
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index c96056d..038d57c 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -405,6 +405,8 @@
default "src/vendorcode/intel/fsp/fsp2_0/alderlake_n/" if SOC_INTEL_ALDERLAKE_PCH_N && !FSP_USE_REPO
default "src/vendorcode/intel/fsp/fsp2_0/raptorlake/4221.00_google/" if VENDOR_GOOGLE && SOC_INTEL_RAPTORLAKE && !FSP_USE_REPO
default "src/vendorcode/intel/fsp/fsp2_0/raptorlake/4301.01/" if SOC_INTEL_RAPTORLAKE && !FSP_USE_REPO
+ default "3rdparty/fsp/RaptorLakeFspBinPkg/Client/RaptorLakeP/Include/" if SOC_INTEL_ALDERLAKE_PCH_P && SOC_INTEL_RAPTORLAKE
+ default "3rdparty/fsp/RaptorLakeFspBinPkg/Client/RaptorLakeS/Include/" if SOC_INTEL_ALDERLAKE_PCH_S && SOC_INTEL_RAPTORLAKE
default "3rdparty/fsp/RaptorLakeFspBinPkg/IoT/RaptorLakeS/Include/" if SOC_INTEL_RAPTORLAKE_PCH_S && FSP_TYPE_IOT
default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeP/Include/" if SOC_INTEL_ALDERLAKE_PCH_P && FSP_TYPE_IOT
default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeS/Include/" if SOC_INTEL_ALDERLAKE_PCH_S && FSP_TYPE_IOT
@@ -417,6 +419,8 @@
string
depends on FSP_USE_REPO
default "3rdparty/fsp/RaptorLakeFspBinPkg/IoT/RaptorLakeS/FSP.fd" if SOC_INTEL_RAPTORLAKE_PCH_S && FSP_TYPE_IOT
+ default "3rdparty/fsp/RaptorLakeFspBinPkg/Client/RaptorLakeP/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_P && SOC_INTEL_RAPTORLAKE
+ default "3rdparty/fsp/RaptorLakeFspBinPkg/Client/RaptorLakeS/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_S && SOC_INTEL_RAPTORLAKE
default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeP/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_P && FSP_TYPE_IOT
default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeS/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_S && FSP_TYPE_IOT
default "3rdparty/fsp/AlderLakeFspBinPkg/Client/AlderLakeP/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_P
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Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78189?usp=email )
Change subject: Update fsp submodule to upstream master branch
......................................................................
Update fsp submodule to upstream master branch
Updating from commit id a72794810884 (2023-09-07):
IoT ADL-N MR1 (4172_00)
to commit id 481ea7cf0bae (2023-09-19):
Move to RaptorLakeFspBinPkg.dec
This brings in 9 new commits:
481ea7cf0b Move to RaptorLakeFspBinPkg.dec
55e25b819e Raptor Lake FSP C.1.BD.40
2b0aac4f64 Raptor Lake FSP C.0.BD.40
3fa75657aa Add Client Raptor Lake FSP
8d24189361 Add Alder Lake and Raptor Lake to README.md
98f4a1fe2f Rename to AlderlakeSiliconPkg
c78a6784cb Add FvLateSilicon for Alder Lake
849ce8261b Tiger Lake FSP A.0.7E.70
4b0b1eb4e3 Update SplitFspBin.py to latest from edk2
Change-Id: I8a724bf0a03cba5a9689894e1aec0a81a5bf2c94
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
M 3rdparty/fsp
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/78189/1
diff --git a/3rdparty/fsp b/3rdparty/fsp
index a727948..481ea7c 160000
--- a/3rdparty/fsp
+++ b/3rdparty/fsp
@@ -1 +1 @@
-Subproject commit a72794810884966001c927a5f202a46eb5161488
+Subproject commit 481ea7cf0bae0107c3e14aa746e52657647142f3
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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76508?usp=email )
Change subject: soc/amd/genoa: Enable eSPI early
......................................................................
Patch Set 4:
(1 comment)
File src/mainboard/amd/onyx/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/76508/comment/e9b07c7b_7f56135f :
PS4, Line 19: device cpu_cluster 0 on end
not needed, since we already have that in the chipset devicetree
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Change subject: soc/amd/genoa: Add aoac.c & enable AOAC devices early
......................................................................
Patch Set 8:
(1 comment)
File src/soc/amd/genoa/include/soc/aoac_defs.h:
https://review.coreboot.org/c/coreboot/+/76506/comment/886daef5_b09d3f3d :
PS7, Line 17: #define FCH_AOAC_DEV_UART3 26
: #define FCH_AOAC_DEV_UART4 20
does genoa have uart3 and 4? from the devicetree i'd assume that it has only uarts 0..2
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Change subject: soc/amd/genoa: Enable PM and cf9 IO early
......................................................................
Patch Set 7: Code-Review-1
(1 comment)
File src/soc/amd/genoa/early_fch.c:
https://review.coreboot.org/c/coreboot/+/76505/comment/4b7efc23_aba2183e :
PS2, Line 16: enable_acpimmio_decode_pm04();
> The Genoa PPR claims that PMIO can still be accessed through the CD6/CD7 mechanism, so I added the K […]
i read the ppr like that this won't work, so i wouldn't select SOC_AMD_COMMON_BLOCK_ACPIMMIO_PM_IO_ACCESS and remove the enable_acpimmio_decode_pm04 call. have a look at phoenix; the difference will be though that while on phoenix it's not available, on genoa it's just not functional
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Change subject: tests: Add static_testable macro
......................................................................
Patch Set 13:
(2 comments)
Patchset:
PS13:
> I think the comment is a bit misleading, as the original author was very responsive, and the reviewe […]
Daniel's last response on this patch was over 2 years ago. I wasn't making any judgement, just stating a fact. How is that misleading?
PS13:
Please feel free to restore this patch if desired.
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Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/77963?usp=email )
Change subject: mb/google/guybrush: Disable WLAN ASPM
......................................................................
mb/google/guybrush: Disable WLAN ASPM
ASPM on the WLAN PCIe bus introduces large latency spikes, which can be
measured with cyclictest:
$ cyclictest --policy=rr --priority=12 --interval=10000 --threads=1 --loops=6000
Disabling ASPM for WLAN reduces the latency spikes from 2,500-3,000 usec
down to 35-65 usec. These latency spikes can impact the user when
real-time processes like Audio (cras) are starved of CPU time, leading
to buffer underruns resulting in crackling/distorted audio.
ASPM is already disabled for Nipperkin devices (CB:63537), so this CL
disables it for both in the shared declaration of
guybrush_czn_dxio_descriptors.
Power impact for Dewatt:
* ASPM enabled
power_VideoCall.FDO_25min_webrtc
w_energy_rate 7.425043688811071
power_Idle.default20min
wh_energy_used 1.4164200000000022
* ASPM disabled
power_VideoCall.FDO_25min_webrtc
w_energy_rate 8.779998551703423
power_Idle.default20min
wh_energy_used 1.4860800000000012
When using Google Meet over WiFi, power increases by ~1.5W.
BUG=b:297970318
TEST=cyclictest --policy=rr --priority=12 --interval=10000 --threads=1 --loops=6000
Change-Id: I16940987d598943bd5d6ace8b4008eba4d4a177c
Signed-off-by: Tim Van Patten <timvp(a)google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77963
Reviewed-by: Martin L Roth <gaumless(a)gmail.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com>
---
M src/mainboard/google/guybrush/port_descriptors.c
M src/mainboard/google/guybrush/variants/nipperkin/variant.c
2 files changed, 2 insertions(+), 6 deletions(-)
Approvals:
Martin L Roth: Looks good to me, approved
Karthik Ramasubramanian: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/src/mainboard/google/guybrush/port_descriptors.c b/src/mainboard/google/guybrush/port_descriptors.c
index 49fe617..fc6ccb8 100644
--- a/src/mainboard/google/guybrush/port_descriptors.c
+++ b/src/mainboard/google/guybrush/port_descriptors.c
@@ -18,8 +18,8 @@
.device_number = PCI_SLOT(WLAN_DEVFN),
.function_number = PCI_FUNC(WLAN_DEVFN),
.link_aspm = ASPM_L1,
- .link_aspm_L1_1 = true,
- .link_aspm_L1_2 = true,
+ .link_aspm_L1_1 = false,
+ .link_aspm_L1_2 = false,
.turn_off_unused_lanes = true,
.clk_req = CLK_REQ0,
.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
diff --git a/src/mainboard/google/guybrush/variants/nipperkin/variant.c b/src/mainboard/google/guybrush/variants/nipperkin/variant.c
index 48e768d..bd6c48c 100644
--- a/src/mainboard/google/guybrush/variants/nipperkin/variant.c
+++ b/src/mainboard/google/guybrush/variants/nipperkin/variant.c
@@ -1,13 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <baseboard/variants.h>
-#include <string.h>
void variant_update_dxio_descriptors(fsp_dxio_descriptor *dxio_descriptors)
{
- dxio_descriptors[WLAN].link_aspm_L1_1 = false;
- dxio_descriptors[WLAN].link_aspm_L1_2 = false;
-
/* Fix link speed to GEN2 - b/228830362 */
dxio_descriptors[WLAN].link_speed_capability = GEN2;
dxio_descriptors[WLAN].port_params[0] = PP_PSPP_AC;
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Change subject: soc/intel/cse: Add function to get cse_bp_info early
......................................................................
Patch Set 6:
(1 comment)
Patchset:
PS5:
> please do rebase properly. […]
Done
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Change subject: soc/amd/genoa: Enable PM and cf9 IO early
......................................................................
Patch Set 7: Code-Review+2
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