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Change subject: soc/amd/genoa: Enable PM and cf9 IO early
......................................................................
Patch Set 7: Code-Review-1
(1 comment)
File src/soc/amd/genoa/early_fch.c:
https://review.coreboot.org/c/coreboot/+/76505/comment/4b7efc23_aba2183e :
PS2, Line 16: enable_acpimmio_decode_pm04();
> The Genoa PPR claims that PMIO can still be accessed through the CD6/CD7 mechanism, so I added the K […]
i read the ppr like that this won't work, so i wouldn't select SOC_AMD_COMMON_BLOCK_ACPIMMIO_PM_IO_ACCESS and remove the enable_acpimmio_decode_pm04 call. have a look at phoenix; the difference will be though that while on phoenix it's not available, on genoa it's just not functional
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Change subject: tests: Add static_testable macro
......................................................................
Patch Set 13:
(2 comments)
Patchset:
PS13:
> I think the comment is a bit misleading, as the original author was very responsive, and the reviewe […]
Daniel's last response on this patch was over 2 years ago. I wasn't making any judgement, just stating a fact. How is that misleading?
PS13:
Please feel free to restore this patch if desired.
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Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/77963?usp=email )
Change subject: mb/google/guybrush: Disable WLAN ASPM
......................................................................
mb/google/guybrush: Disable WLAN ASPM
ASPM on the WLAN PCIe bus introduces large latency spikes, which can be
measured with cyclictest:
$ cyclictest --policy=rr --priority=12 --interval=10000 --threads=1 --loops=6000
Disabling ASPM for WLAN reduces the latency spikes from 2,500-3,000 usec
down to 35-65 usec. These latency spikes can impact the user when
real-time processes like Audio (cras) are starved of CPU time, leading
to buffer underruns resulting in crackling/distorted audio.
ASPM is already disabled for Nipperkin devices (CB:63537), so this CL
disables it for both in the shared declaration of
guybrush_czn_dxio_descriptors.
Power impact for Dewatt:
* ASPM enabled
power_VideoCall.FDO_25min_webrtc
w_energy_rate 7.425043688811071
power_Idle.default20min
wh_energy_used 1.4164200000000022
* ASPM disabled
power_VideoCall.FDO_25min_webrtc
w_energy_rate 8.779998551703423
power_Idle.default20min
wh_energy_used 1.4860800000000012
When using Google Meet over WiFi, power increases by ~1.5W.
BUG=b:297970318
TEST=cyclictest --policy=rr --priority=12 --interval=10000 --threads=1 --loops=6000
Change-Id: I16940987d598943bd5d6ace8b4008eba4d4a177c
Signed-off-by: Tim Van Patten <timvp(a)google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77963
Reviewed-by: Martin L Roth <gaumless(a)gmail.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com>
---
M src/mainboard/google/guybrush/port_descriptors.c
M src/mainboard/google/guybrush/variants/nipperkin/variant.c
2 files changed, 2 insertions(+), 6 deletions(-)
Approvals:
Martin L Roth: Looks good to me, approved
Karthik Ramasubramanian: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/src/mainboard/google/guybrush/port_descriptors.c b/src/mainboard/google/guybrush/port_descriptors.c
index 49fe617..fc6ccb8 100644
--- a/src/mainboard/google/guybrush/port_descriptors.c
+++ b/src/mainboard/google/guybrush/port_descriptors.c
@@ -18,8 +18,8 @@
.device_number = PCI_SLOT(WLAN_DEVFN),
.function_number = PCI_FUNC(WLAN_DEVFN),
.link_aspm = ASPM_L1,
- .link_aspm_L1_1 = true,
- .link_aspm_L1_2 = true,
+ .link_aspm_L1_1 = false,
+ .link_aspm_L1_2 = false,
.turn_off_unused_lanes = true,
.clk_req = CLK_REQ0,
.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
diff --git a/src/mainboard/google/guybrush/variants/nipperkin/variant.c b/src/mainboard/google/guybrush/variants/nipperkin/variant.c
index 48e768d..bd6c48c 100644
--- a/src/mainboard/google/guybrush/variants/nipperkin/variant.c
+++ b/src/mainboard/google/guybrush/variants/nipperkin/variant.c
@@ -1,13 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <baseboard/variants.h>
-#include <string.h>
void variant_update_dxio_descriptors(fsp_dxio_descriptor *dxio_descriptors)
{
- dxio_descriptors[WLAN].link_aspm_L1_1 = false;
- dxio_descriptors[WLAN].link_aspm_L1_2 = false;
-
/* Fix link speed to GEN2 - b/228830362 */
dxio_descriptors[WLAN].link_speed_capability = GEN2;
dxio_descriptors[WLAN].port_params[0] = PP_PSPP_AC;
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Change subject: soc/intel/cse: Add function to get cse_bp_info early
......................................................................
Patch Set 6:
(1 comment)
Patchset:
PS5:
> please do rebase properly. […]
Done
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Change subject: soc/amd/genoa: Enable PM and cf9 IO early
......................................................................
Patch Set 7: Code-Review+2
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Martin L Roth has uploaded a new patch set (#8) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/76506?usp=email )
Change subject: soc/amd/genoa: Add aoac.c & enable AOAC devices early
......................................................................
soc/amd/genoa: Add aoac.c & enable AOAC devices early
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Signed-off-by: Martin Roth <gaumless(a)gmail.com>
Change-Id: Ic9553e6016c92c9b1678c395cd6a9e6860bf8a76
---
M src/soc/amd/genoa/Makefile.inc
A src/soc/amd/genoa/aoac.c
M src/soc/amd/genoa/early_fch.c
A src/soc/amd/genoa/include/soc/aoac_defs.h
4 files changed, 57 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/76506/8
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Change subject: vendorcode/amd: Add opensil code
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
I pushed the submodule, so I think this can be abandoned.
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Change subject: soc/amd/genoa: Enable PM and cf9 IO early
......................................................................
Patch Set 6:
(1 comment)
File src/soc/amd/genoa/early_fch.c:
https://review.coreboot.org/c/coreboot/+/76505/comment/ccf8c155_a93989ea :
PS2, Line 16: enable_acpimmio_decode_pm04();
> not 100% sure about this one; it should either be removed or an additional kconfig option needs to b […]
The Genoa PPR claims that PMIO can still be accessed through the CD6/CD7 mechanism, so I added the Kconfig option to allow for that. Of course, the public PPR doesn't even mention the FCH section. :-/
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Martin L Roth has uploaded a new patch set (#7) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/76505?usp=email )
Change subject: soc/amd/genoa: Enable PM and cf9 IO early
......................................................................
soc/amd/genoa: Enable PM and cf9 IO early
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Change-Id: I05990c2aca40d9cf47a9ebdfd269b80b8f60e300
---
M src/soc/amd/genoa/Kconfig
M src/soc/amd/genoa/early_fch.c
2 files changed, 6 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/76505/7
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