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Change in coreboot[master]: sb/intel/bd82x6x/pch.c: Extract common functions
by Angel Pons (Code Review) 25 Nov '23

25 Nov '23

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49167 ) Change subject: sb/intel/bd82x6x/pch.c: Extract common functions ...................................................................... sb/intel/bd82x6x/pch.c: Extract common functions PCH identification functions and `pch_iobp_update` are used in multiple stages. Move them out of `pch.c` to drop some ugly preprocessor usage. Subsequent commits will use `pch_iobp_update` in romstage as well. Change-Id: I8d33338a4f74fd03c8f99f8fcece99b63c28adab Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/Makefile.inc A src/southbridge/intel/bd82x6x/common.c M src/southbridge/intel/bd82x6x/pch.c M src/southbridge/intel/bd82x6x/pch.h 4 files changed, 122 insertions(+), 119 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/49167/1 diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index 687fc97..469a50e 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -7,6 +7,7 @@ ramstage-y += pch.c ramstage-y += azalia.c +ramstage-y += common.c ramstage-y += fadt.c ramstage-y += lpc.c ramstage-y += pci.c @@ -26,8 +27,9 @@ ramstage-$(CONFIG_ELOG) += elog.c -smm-y += smihandler.c me.c me_8.x.c pch.c me_common.c +smm-y += common.c smihandler.c me.c me_8.x.c me_common.c +romstage-y += common.c romstage-y += me_status.c romstage-y += early_rcba.c romstage-y += early_pch.c diff --git a/src/southbridge/intel/bd82x6x/common.c b/src/southbridge/intel/bd82x6x/common.c new file mode 100644 index 0000000..7480174 --- /dev/null +++ b/src/southbridge/intel/bd82x6x/common.c @@ -0,0 +1,118 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define __SIMPLE_DEVICE__ + +#include <console/console.h> +#include <delay.h> +#include <device/pci.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <stdint.h> + +#include "pch.h" + +int pch_silicon_revision(void) +{ + static int pch_revision_id = -1; + + if (pch_revision_id < 0) + pch_revision_id = pci_read_config8(PCH_LPC_DEV, PCI_REVISION_ID); + + return pch_revision_id; +} + +int pch_silicon_type(void) +{ + static int pch_type = -1; + + if (pch_type < 0) + pch_type = pci_read_config8(PCH_LPC_DEV, PCI_DEVICE_ID + 1); + + return pch_type; +} + +int pch_silicon_supported(int type, int rev) +{ + int cur_type = pch_silicon_type(); + int cur_rev = pch_silicon_revision(); + + switch (type) { + case PCH_TYPE_CPT: + /* CougarPoint minimum revision */ + if (cur_type == PCH_TYPE_CPT && cur_rev >= rev) + return 1; + /* PantherPoint any revision */ + if (cur_type == PCH_TYPE_PPT) + return 1; + break; + + case PCH_TYPE_PPT: + /* PantherPoint minimum revision */ + if (cur_type == PCH_TYPE_PPT && cur_rev >= rev) + return 1; + break; + } + + return 0; +} + +#define IOBP_RETRY 1000 +static inline int iobp_poll(void) +{ + unsigned int try = IOBP_RETRY; + u32 data; + + while (try--) { + data = RCBA32(IOBPS); + if ((data & 1) == 0) + return 1; + udelay(10); + } + + printk(BIOS_ERR, "IOBP timeout\n"); + return 0; +} + +void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) +{ + u32 data; + + /* Set the address */ + RCBA32(IOBPIRI) = address; + + /* READ OPCODE */ + if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0)) + RCBA32(IOBPS) = IOBPS_RW_BX; + else + RCBA32(IOBPS) = IOBPS_READ_AX; + if (!iobp_poll()) + return; + + /* Read IOBP data */ + data = RCBA32(IOBPD); + if (!iobp_poll()) + return; + + /* Check for successful transaction */ + if ((RCBA32(IOBPS) & 0x6) != 0) { + printk(BIOS_ERR, "IOBP read 0x%08x failed\n", address); + return; + } + + /* Update the data */ + data &= andvalue; + data |= orvalue; + + /* WRITE OPCODE */ + if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0)) + RCBA32(IOBPS) = IOBPS_RW_BX; + else + RCBA32(IOBPS) = IOBPS_WRITE_AX; + if (!iobp_poll()) + return; + + /* Write IOBP data */ + RCBA32(IOBPD) = data; + if (!iobp_poll()) + return; +} diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index 82b95f6..1c8786d 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -11,123 +11,6 @@ #include "chip.h" #include "pch.h" -int pch_silicon_revision(void) -{ - static int pch_revision_id = -1; - -#ifdef __SIMPLE_DEVICE__ - pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); -#else - struct device *dev = pcidev_on_root(0x1f, 0); -#endif - - if (pch_revision_id < 0) - pch_revision_id = pci_read_config8(dev, PCI_REVISION_ID); - return pch_revision_id; -} - -int pch_silicon_type(void) -{ - static int pch_type = -1; - -#ifdef __SIMPLE_DEVICE__ - pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); -#else - struct device *dev = pcidev_on_root(0x1f, 0); -#endif - - if (pch_type < 0) - pch_type = pci_read_config8(dev, PCI_DEVICE_ID + 1); - return pch_type; -} - -static int pch_silicon_supported(int type, int rev) -{ - int cur_type = pch_silicon_type(); - int cur_rev = pch_silicon_revision(); - - switch (type) { - case PCH_TYPE_CPT: - /* CougarPoint minimum revision */ - if (cur_type == PCH_TYPE_CPT && cur_rev >= rev) - return 1; - /* PantherPoint any revision */ - if (cur_type == PCH_TYPE_PPT) - return 1; - break; - - case PCH_TYPE_PPT: - /* PantherPoint minimum revision */ - if (cur_type == PCH_TYPE_PPT && cur_rev >= rev) - return 1; - break; - } - - return 0; -} - -#define IOBP_RETRY 1000 -static inline int iobp_poll(void) -{ - unsigned int try = IOBP_RETRY; - u32 data; - - while (try--) { - data = RCBA32(IOBPS); - if ((data & 1) == 0) - return 1; - udelay(10); - } - - printk(BIOS_ERR, "IOBP timeout\n"); - return 0; -} - -void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) -{ - u32 data; - - /* Set the address */ - RCBA32(IOBPIRI) = address; - - /* READ OPCODE */ - if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0)) - RCBA32(IOBPS) = IOBPS_RW_BX; - else - RCBA32(IOBPS) = IOBPS_READ_AX; - if (!iobp_poll()) - return; - - /* Read IOBP data */ - data = RCBA32(IOBPD); - if (!iobp_poll()) - return; - - /* Check for successful transaction */ - if ((RCBA32(IOBPS) & 0x6) != 0) { - printk(BIOS_ERR, "IOBP read 0x%08x failed\n", address); - return; - } - - /* Update the data */ - data &= andvalue; - data |= orvalue; - - /* WRITE OPCODE */ - if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0)) - RCBA32(IOBPS) = IOBPS_RW_BX; - else - RCBA32(IOBPS) = IOBPS_WRITE_AX; - if (!iobp_poll()) - return; - - /* Write IOBP data */ - RCBA32(IOBPD) = data; - if (!iobp_poll()) - return; -} - -#ifndef __SIMPLE_DEVICE__ /* Set bit in function disable register to hide this device */ static void pch_hide_devfn(unsigned int devfn) { @@ -426,4 +309,3 @@ CHIP_NAME("Intel Series 6/7 (Cougar Point/Panther Point) Southbridge") .enable_dev = pch_enable, }; -#endif diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 1840a2b..dcab839 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -42,6 +42,7 @@ int pch_silicon_revision(void); int pch_silicon_type(void); +int pch_silicon_supported(int type, int rev); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); void enable_usb_bar(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/49167 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d33338a4f74fd03c8f99f8fcece99b63c28adab Gerrit-Change-Number: 49167 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/bd82x6x: Rework PCH ID cache
by Angel Pons (Code Review) 25 Nov '23

25 Nov '23

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49168 ) Change subject: sb/intel/bd82x6x: Rework PCH ID cache ...................................................................... sb/intel/bd82x6x: Rework PCH ID cache Work around a romstage restriction. Globals (or static variables) cannot be initialized to a non-zero value because there's no data section. Note that the revision ID for stepping A0 is zero, so `pch_silicon_revision` will no longer use the cached value for this PCH stepping. Since it is a pre-production stepping, it is most likely not used anywhere anymore. Change-Id: I07663d151cbc2d2ed7e4813bf870de52848753fd Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/common.c 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/49168/1 diff --git a/src/southbridge/intel/bd82x6x/common.c b/src/southbridge/intel/bd82x6x/common.c index 7480174..0094db6 100644 --- a/src/southbridge/intel/bd82x6x/common.c +++ b/src/southbridge/intel/bd82x6x/common.c @@ -13,9 +13,9 @@ int pch_silicon_revision(void) { - static int pch_revision_id = -1; + static int pch_revision_id = 0; - if (pch_revision_id < 0) + if (!pch_revision_id) pch_revision_id = pci_read_config8(PCH_LPC_DEV, PCI_REVISION_ID); return pch_revision_id; @@ -23,9 +23,9 @@ int pch_silicon_type(void) { - static int pch_type = -1; + static int pch_type = 0; - if (pch_type < 0) + if (!pch_type) pch_type = pci_read_config8(PCH_LPC_DEV, PCI_DEVICE_ID + 1); return pch_type; -- To view, visit https://review.coreboot.org/c/coreboot/+/49168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I07663d151cbc2d2ed7e4813bf870de52848753fd Gerrit-Change-Number: 49168 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: Revert "Update vboot submodule to upstream main"
by Martin L Roth (Code Review) 01 Nov '23

01 Nov '23

Attention is currently required from: Eric Lai, Julius Werner, Martin L Roth, Yu-Ping Wu. Hello David Hendricks, Eric Lai, Felix Singer, Julius Werner, Matt DeVillier, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78844?usp=email to look at the new patch set (#2). Change subject: Revert "Update vboot submodule to upstream main" ...................................................................... Revert "Update vboot submodule to upstream main" This reverts commit 6e03007bfa948d679f5d4d6998c12c581b390d1a. Reason for revert: Build fails - Jenkins test escappe. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I726e2e1ce7dc3350a281dc30256b116580fd63c0 --- M 3rdparty/vboot 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/78844/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78844?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I726e2e1ce7dc3350a281dc30256b116580fd63c0 Gerrit-Change-Number: 78844 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: Revert "Update vboot submodule to upstream main"
by Matt DeVillier (Code Review) 01 Nov '23

01 Nov '23

Attention is currently required from: Eric Lai, Julius Werner, Martin L Roth, Yu-Ping Wu. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78844?usp=email ) Change subject: Revert "Update vboot submodule to upstream main" ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78844?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I726e2e1ce7dc3350a281dc30256b116580fd63c0 Gerrit-Change-Number: 78844 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 31 Oct 2023 23:56:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: Revert "Update vboot submodule to upstream main"
by Felix Singer (Code Review) 01 Nov '23

01 Nov '23

Attention is currently required from: Eric Lai, Julius Werner, Martin L Roth, Yu-Ping Wu. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78844?usp=email ) Change subject: Revert "Update vboot submodule to upstream main" ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78844?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I726e2e1ce7dc3350a281dc30256b116580fd63c0 Gerrit-Change-Number: 78844 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 31 Oct 2023 23:56:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: Revert "Update vboot submodule to upstream main"
by David Hendricks (Code Review) 01 Nov '23

01 Nov '23

Attention is currently required from: Eric Lai, Felix Singer, Julius Werner, Martin L Roth, Yu-Ping Wu. David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78844?usp=email ) Change subject: Revert "Update vboot submodule to upstream main" ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78844?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I726e2e1ce7dc3350a281dc30256b116580fd63c0 Gerrit-Change-Number: 78844 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 31 Oct 2023 23:55:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: drivers/intel/gma/opregion: Use CBFS cache to load VBT
by Nico Huber (Code Review) 01 Nov '23

01 Nov '23

Attention is currently required from: Arthur Heymans, Eran Mitrani, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Nick Vaccaro, Tarun. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77886?usp=email ) Change subject: drivers/intel/gma/opregion: Use CBFS cache to load VBT ...................................................................... Patch Set 33: (1 comment) File src/drivers/intel/gma/opregion.c: https://review.coreboot.org/c/coreboot/+/77886/comment/e661bfc8_a00f66ee : PS4, Line 27: cbfs_map > I find this quite confusing. The way you describe it, I see no difference to […] NB. Looking at the code below and the history of the static array, it looks like it was never necessary. We eventually copy the VBT to CBMEM anyway. So there shouldn't be a need to map twice. Probably just a shortcut that was taken when adding FSP/GOP support. -- To view, visit https://review.coreboot.org/c/coreboot/+/77886?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1e37e718a71bd85b0d7dee1efc4c0391798f16f7 Gerrit-Change-Number: 77886 Gerrit-PatchSet: 33 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Tue, 31 Oct 2023 23:53:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: Update vboot submodule to upstream main
by Martin L Roth (Code Review) 01 Nov '23

01 Nov '23

Martin L Roth has created a revert of this change. ( https://review.coreboot.org/c/coreboot/+/78820?usp=email ) Change subject: Update vboot submodule to upstream main ...................................................................... -- To view, visit https://review.coreboot.org/c/coreboot/+/78820?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic7ecd1755d26df349b8abf1c5a77c806facfe1d8 Gerrit-Change-Number: 78820 Gerrit-PatchSet: 2 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: revert

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[XS] Change in coreboot[main]: Revert "Update vboot submodule to upstream main"
by Martin L Roth (Code Review) 01 Nov '23

01 Nov '23

Attention is currently required from: Eric Lai, Felix Singer, Julius Werner, Yu-Ping Wu. Hello Felix Singer, Eric Lai, build bot (Jenkins), Julius Werner, Yu-Ping Wu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/78844?usp=email to review the following change. Change subject: Revert "Update vboot submodule to upstream main" ...................................................................... Revert "Update vboot submodule to upstream main" This reverts commit 6e03007bfa948d679f5d4d6998c12c581b390d1a. Reason for revert: Build fails - Jenkins test escappe. Change-Id: I726e2e1ce7dc3350a281dc30256b116580fd63c0 --- M 3rdparty/vboot 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/78844/1 diff --git a/3rdparty/vboot b/3rdparty/vboot index f2b01bf..24cb127 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit f2b01bf08a813fb3035102c7c948b78fa191e544 +Subproject commit 24cb127a5e83a713131ab75cc39b11336019443c -- To view, visit https://review.coreboot.org/c/coreboot/+/78844?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I726e2e1ce7dc3350a281dc30256b116580fd63c0 Gerrit-Change-Number: 78844 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: drivers/intel/gma/opregion: Use CBFS cache to load VBT
by Nico Huber (Code Review) 01 Nov '23

01 Nov '23

Attention is currently required from: Arthur Heymans, Eran Mitrani, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Nick Vaccaro, Tarun. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77886?usp=email ) Change subject: drivers/intel/gma/opregion: Use CBFS cache to load VBT ...................................................................... Patch Set 33: (1 comment) File src/drivers/intel/gma/opregion.c: https://review.coreboot.org/c/coreboot/+/77886/comment/7e0b7468_3019f356 : PS4, Line 27: cbfs_map > Yes, it's pretty common practice to leak when necessary (e.g. […] I find this quite confusing. The way you describe it, I see no difference to using malloc() and leaking. Only that we have to fear another heap that might be too small for some combinations of options. If it's like the generic heap, why have it separate? More on topic, was this tested sufficiently? that the cache is usually big enough? -- To view, visit https://review.coreboot.org/c/coreboot/+/77886?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1e37e718a71bd85b0d7dee1efc4c0391798f16f7 Gerrit-Change-Number: 77886 Gerrit-PatchSet: 33 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Tue, 31 Oct 2023 23:40:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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coreboot-gerrit October 2023