Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49168 )
Change subject: sb/intel/bd82x6x: Rework PCH ID cache
......................................................................
sb/intel/bd82x6x: Rework PCH ID cache
Work around a romstage restriction. Globals (or static variables) cannot
be initialized to a non-zero value because there's no data section. Note
that the revision ID for stepping A0 is zero, so `pch_silicon_revision`
will no longer use the cached value for this PCH stepping. Since it is a
pre-production stepping, it is most likely not used anywhere anymore.
Change-Id: I07663d151cbc2d2ed7e4813bf870de52848753fd
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M src/southbridge/intel/bd82x6x/common.c
1 file changed, 4 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/49168/1
diff --git a/src/southbridge/intel/bd82x6x/common.c b/src/southbridge/intel/bd82x6x/common.c
index 7480174..0094db6 100644
--- a/src/southbridge/intel/bd82x6x/common.c
+++ b/src/southbridge/intel/bd82x6x/common.c
@@ -13,9 +13,9 @@
int pch_silicon_revision(void)
{
- static int pch_revision_id = -1;
+ static int pch_revision_id = 0;
- if (pch_revision_id < 0)
+ if (!pch_revision_id)
pch_revision_id = pci_read_config8(PCH_LPC_DEV, PCI_REVISION_ID);
return pch_revision_id;
@@ -23,9 +23,9 @@
int pch_silicon_type(void)
{
- static int pch_type = -1;
+ static int pch_type = 0;
- if (pch_type < 0)
+ if (!pch_type)
pch_type = pci_read_config8(PCH_LPC_DEV, PCI_DEVICE_ID + 1);
return pch_type;
--
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Hello David Hendricks, Eric Lai, Felix Singer, Julius Werner, Matt DeVillier, Yu-Ping Wu, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: Revert "Update vboot submodule to upstream main"
......................................................................
Revert "Update vboot submodule to upstream main"
This reverts commit 6e03007bfa948d679f5d4d6998c12c581b390d1a.
Reason for revert: Build fails - Jenkins test escappe.
Signed-off-by: Martin Roth <gaumless(a)gmail.com>
Change-Id: I726e2e1ce7dc3350a281dc30256b116580fd63c0
---
M 3rdparty/vboot
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/78844/2
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Change subject: Revert "Update vboot submodule to upstream main"
......................................................................
Patch Set 1: Code-Review+2
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......................................................................
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Change subject: drivers/intel/gma/opregion: Use CBFS cache to load VBT
......................................................................
Patch Set 33:
(1 comment)
File src/drivers/intel/gma/opregion.c:
https://review.coreboot.org/c/coreboot/+/77886/comment/e661bfc8_a00f66ee :
PS4, Line 27: cbfs_map
> I find this quite confusing. The way you describe it, I see no difference to […]
NB. Looking at the code below and the history of the static array, it
looks like it was never necessary. We eventually copy the VBT to CBMEM
anyway. So there shouldn't be a need to map twice. Probably just a
shortcut that was taken when adding FSP/GOP support.
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Martin L Roth has created a revert of this change. ( https://review.coreboot.org/c/coreboot/+/78820?usp=email )
Change subject: Update vboot submodule to upstream main
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I'd like you to do a code review.
Please visit
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Change subject: Revert "Update vboot submodule to upstream main"
......................................................................
Revert "Update vboot submodule to upstream main"
This reverts commit 6e03007bfa948d679f5d4d6998c12c581b390d1a.
Reason for revert: Build fails - Jenkins test escappe.
Change-Id: I726e2e1ce7dc3350a281dc30256b116580fd63c0
---
M 3rdparty/vboot
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/78844/1
diff --git a/3rdparty/vboot b/3rdparty/vboot
index f2b01bf..24cb127 160000
--- a/3rdparty/vboot
+++ b/3rdparty/vboot
@@ -1 +1 @@
-Subproject commit f2b01bf08a813fb3035102c7c948b78fa191e544
+Subproject commit 24cb127a5e83a713131ab75cc39b11336019443c
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Change subject: drivers/intel/gma/opregion: Use CBFS cache to load VBT
......................................................................
Patch Set 33:
(1 comment)
File src/drivers/intel/gma/opregion.c:
https://review.coreboot.org/c/coreboot/+/77886/comment/7e0b7468_3019f356 :
PS4, Line 27: cbfs_map
> Yes, it's pretty common practice to leak when necessary (e.g. […]
I find this quite confusing. The way you describe it, I see no difference to
using malloc() and leaking. Only that we have to fear another heap that might
be too small for some combinations of options. If it's like the generic heap,
why have it separate?
More on topic, was this tested sufficiently? that the cache is usually big enough?
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