Change in ...coreboot[master]: security/intel/stm STM support
by Name of user not set (Code Review)
Name of user not set #1002358 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33234
Change subject: security/intel/stm STM support
......................................................................
security/intel/stm STM support
Initial commit for Coreboot STM supporX
Change-Id: If4adcd92c341162630ce1ec357ffcf8a135785ec
---
M src/security/Kconfig
M src/security/Makefile.inc
A src/security/intel/stm/Kconfig
A src/security/intel/stm/Makefile.inc
A src/security/intel/stm/SmmStm.c
A src/security/intel/stm/SmmStm.h
A src/security/intel/stm/StmApi.h
A src/security/intel/stm/StmPlatformResource.c
A src/security/intel/stm/StmPlatformResource.h
A src/security/intel/stm/StmPlatformSmm.c
10 files changed, 2,235 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/33234/1
diff --git a/src/security/Kconfig b/src/security/Kconfig
index 6a334ac..e9b5225 100644
--- a/src/security/Kconfig
+++ b/src/security/Kconfig
@@ -14,3 +14,4 @@
source "src/security/vboot/Kconfig"
source "src/security/tpm/Kconfig"
+source "src/security/intel/stm/Kconfig"
diff --git a/src/security/Makefile.inc b/src/security/Makefile.inc
index a940b82..e49c172 100644
--- a/src/security/Makefile.inc
+++ b/src/security/Makefile.inc
@@ -1,2 +1,4 @@
subdirs-y += vboot
subdirs-y += tpm
+subdirs-y += intel/stm
+
diff --git a/src/security/intel/stm/Kconfig b/src/security/intel/stm/Kconfig
new file mode 100644
index 0000000..e8eea02
--- /dev/null
+++ b/src/security/intel/stm/Kconfig
@@ -0,0 +1,17 @@
+
+menu "SMI Transfer Monitor (STM)"
+
+config STM
+ bool "Enable STM"
+ default y
+ depends on (PLATFORM_USES_FSP2_0||PLATFORM_USES_FSP1_1||PLATFORM_USES_FSP1_0)
+
+if STM
+
+config MSEG_SIZE
+ hex "mseg size"
+ default 0x400000
+
+endif #STM
+
+endmenu
diff --git a/src/security/intel/stm/Makefile.inc b/src/security/intel/stm/Makefile.inc
new file mode 100644
index 0000000..24d7bac
--- /dev/null
+++ b/src/security/intel/stm/Makefile.inc
@@ -0,0 +1,16 @@
+
+# put the stm where is can be found
+
+cbfs-files-y += stm.bin
+stm.bin-file = stm.bin
+stm.bin-type = raw
+
+ramstage-y += SmmStm.c
+ramstage-y += StmPlatformSmm.c
+ramstage-y += StmPlatformResource.c
+
+smm-y += StmPlatformResource.c
+smm-y += SmmStm.c
+smm-y += StmPlatformSmm.c
+
+
diff --git a/src/security/intel/stm/SmmStm.c b/src/security/intel/stm/SmmStm.c
new file mode 100644
index 0000000..677d514
--- /dev/null
+++ b/src/security/intel/stm/SmmStm.c
@@ -0,0 +1,894 @@
+/** @file
+
+ SMM STM support
+
+ Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
+
+ This program and the accompanying materials are licensed and made available
+ under the terms and conditions of the BSD License which accompanies this
+ distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <security/intel/stm/SmmStm.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/cr.h>
+#include <string.h>
+#include <cpu/x86/mp.h>
+#include <console/console.h>
+
+#define TXT_EVTYPE_BASE 0x400
+#define TXT_EVTYPE_STM_HASH (TXT_EVTYPE_BASE + 14)
+
+#define RDWR_ACCS 3
+#define FULL_ACCS 7
+
+#define SIZE_4KB 0x00001000
+#define SIZE_4MB 0x00400000
+
+#define IA32_PG_P (1<<0)
+#define IA32_PG_RW (1<<1)
+#define IA32_PG_PS (1<<7)
+
+#define STM_PAGE_SHIFT 12
+#define STM_PAGE_MASK 0xFFF
+#define STM_SIZE_TO_PAGES(a) (((a) >> STM_PAGE_SHIFT) + (((a) & STM_PAGE_MASK) ? 1 : 0))
+#define STM_PAGES_TO_SIZE(a) ((a) << STM_PAGE_SHIFT)
+
+#define STM_ACCESS_DENIED 15
+#define STM_UNSUPPORTED 3
+
+#define STM_BUFFER_TOO_SMALL 1
+
+#define STM_SM_MONITOR_STATE_ENABLED 1
+
+#define RESOURCEHEAPSIZE 4096
+
+uint32_t GetVmcsSize(void);
+void StmGen4GPageTableIa32(uint32_t PageTableBase);
+void StmGen4GPageTableX64(uint32_t PageTableBase);
+bool StmCheckStmImage(void * StmImage, uint32_t StmImageSize);
+void StmLoadStmImage(void * StmImage, UINTN StmImageSize);
+
+bool HandleSingleResource(STM_RSC *Resource, STM_RSC *Record);
+void AddSingleResource(STM_RSC *Resource);
+void AddResource(STM_RSC *ResourceList, uint32_t NumEntries);
+bool ValidateResource(STM_RSC *ResourceList, uint32_t NumEntries);
+UINTN GetResourceSize(STM_RSC *ResourceList, uint32_t NumEntries);
+
+typedef struct {
+
+ uint64_t VmcsRevisionID:31;
+ uint64_t AlwaysZero:1;
+ uint64_t VmcsSize:13;
+ uint64_t Reserved1:3;
+ uint64_t VmxonAddWidth:1;
+ uint64_t StmSupported:1;
+ uint64_t VmcsMemoryType:4;
+ uint64_t InOutReporting:1;
+ uint64_t MayClearDefaults:1;
+ uint64_t Reserved2:8;
+} VMX_BASIC_MSR_BITS;
+
+typedef union {
+ VMX_BASIC_MSR_BITS bits;
+ uint64_t uint64;
+ msr_t msr;
+} VMX_BASIC_MSR;
+
+typedef struct {
+ uint64_t valid:1;
+ uint64_t reserved1:1;
+ uint64_t VmxOffBlockSmi:1;
+ uint64_t reserved2:9;
+ uint64_t MsegAddress:20;
+ uint64_t reserved3:32;
+} SMM_MONITOR_CTL_MSR_BITS;
+
+extern struct mp_state {
+ struct mp_ops ops;
+ int cpu_count;
+ uintptr_t perm_smbase;
+ size_t perm_smsize;
+ size_t smm_save_state_size;
+ int do_smm;
+} mp_state;
+
+typedef union {
+ SMM_MONITOR_CTL_MSR_BITS bits;
+ uint64_t uint64;
+ msr_t msr;
+} SMM_MONITOR_CTL_MSR;
+
+//
+// Template of STM_RSC_END structure for copying.
+//
+
+STM_RSC_END mRscEndNode = {
+ {END_OF_RESOURCES, sizeof(STM_RSC_END)},
+};
+
+uint8_t *mStmResourcesPtr = NULL;
+UINTN mStmResourceTotalSize = 0x0;
+UINTN mStmResourceSizeUsed = 0x0;
+UINTN mStmResourceSizeAvailable = 0x0;
+
+uint8_t StmResourceHeap[RESOURCEHEAPSIZE];
+
+uint32_t mStmState = 0;
+
+/**
+
+ Handle single Resource to see if it can be merged into Record.
+
+ @param Resource A pointer to resource node to be added
+ @param Record A pointer to record node to be merged
+
+ @retval true resource handled
+ @retval false resource is not handled
+
+**/
+
+bool
+HandleSingleResource(
+ STM_RSC *Resource,
+ STM_RSC *Record
+ )
+{
+ uint64_t ResourceLo;
+ uint64_t ResourceHi;
+ uint64_t RecordLo;
+ uint64_t RecordHi;
+
+ ResourceLo = 0;
+ ResourceHi = 0;
+ RecordLo = 0;
+ RecordHi = 0;
+
+ //
+ // Calling code is responsible for making sure that
+ // Resource->Header.RscType == (*Record)->Header.RscType
+ // thus we use just one of them as switch variable.
+ //
+
+ switch (Resource->Header.RscType) {
+ case MEM_RANGE:
+ case MMIO_RANGE:
+ ResourceLo = Resource->Mem.Base;
+ ResourceHi = Resource->Mem.Base + Resource->Mem.Length;
+ RecordLo = Record->Mem.Base;
+ RecordHi = Record->Mem.Base + Record->Mem.Length;
+ if (Resource->Mem.RWXAttributes != Record->Mem.RWXAttributes) {
+ if ((ResourceLo == RecordLo) && (ResourceHi == RecordHi)) {
+ Record->Mem.RWXAttributes = Resource->Mem.RWXAttributes | Record->Mem.RWXAttributes;
+ return true;
+ } else {
+ return false;
+ }
+ }
+ break;
+ case IO_RANGE:
+ case TRAPPED_IO_RANGE:
+ ResourceLo = (uint64_t) Resource->Io.Base;
+ ResourceHi = (uint64_t) Resource->Io.Base + (uint64_t) Resource->Io.Length;
+ RecordLo = (uint64_t) Record->Io.Base;
+ RecordHi = (uint64_t) Record->Io.Base + (uint64_t) Record->Io.Length;
+ break;
+ case PCI_CFG_RANGE:
+ if ((Resource->PciCfg.OriginatingBusNumber != Record->PciCfg.OriginatingBusNumber) ||
+ (Resource->PciCfg.LastNodeIndex != Record->PciCfg.LastNodeIndex)) {
+ return false;
+ }
+ if (memcmp (Resource->PciCfg.PciDevicePath, Record->PciCfg.PciDevicePath, sizeof(STM_PCI_DEVICE_PATH_NODE) * (Resource->PciCfg.LastNodeIndex + 1)) != 0) {
+ return false;
+ }
+ ResourceLo = (uint64_t) Resource->PciCfg.Base;
+ ResourceHi = (uint64_t) Resource->PciCfg.Base + (uint64_t) Resource->PciCfg.Length;
+ RecordLo = (uint64_t) Record->PciCfg.Base;
+ RecordHi = (uint64_t) Record->PciCfg.Base + (uint64_t) Record->PciCfg.Length;
+ if (Resource->PciCfg.RWAttributes != Record->PciCfg.RWAttributes) {
+ if ((ResourceLo == RecordLo) && (ResourceHi == RecordHi)) {
+ Record->PciCfg.RWAttributes = Resource->PciCfg.RWAttributes | Record->PciCfg.RWAttributes;
+ return true;
+ } else {
+ return false;
+ }
+ }
+ break;
+ case MACHINE_SPECIFIC_REG:
+ //
+ // Special case - merge MSR masks in place.
+ //
+ if (Resource->Msr.MsrIndex != Record->Msr.MsrIndex) {
+ return false;
+ }
+ Record->Msr.ReadMask |= Resource->Msr.ReadMask;
+ Record->Msr.WriteMask |= Resource->Msr.WriteMask;
+ return true;
+ default:
+ return false;
+ }
+ //
+ // If resources are disjoint
+ //
+ if ((ResourceHi < RecordLo) || (ResourceLo > RecordHi)) {
+ return false;
+ }
+
+ //
+ // If resource is consumed by record.
+ //
+ if ((ResourceLo >= RecordLo) && (ResourceHi <= RecordHi)) {
+ return true;
+ }
+ //
+ // Resources are overlapping.
+ // Resource and record are merged.
+ //
+ ResourceLo = (ResourceLo < RecordLo) ? ResourceLo : RecordLo;
+ ResourceHi = (ResourceHi > RecordHi) ? ResourceHi : RecordHi;
+
+ switch (Resource->Header.RscType) {
+ case MEM_RANGE:
+ case MMIO_RANGE:
+ Record->Mem.Base = ResourceLo;
+ Record->Mem.Length = ResourceHi - ResourceLo;
+ break;
+ case IO_RANGE:
+ case TRAPPED_IO_RANGE:
+ Record->Io.Base = (uint64_t) ResourceLo;
+ Record->Io.Length = (uint64_t) (ResourceHi - ResourceLo);
+ break;
+ case PCI_CFG_RANGE:
+ Record->PciCfg.Base = (uint64_t) ResourceLo;
+ Record->PciCfg.Length = (uint64_t) (ResourceHi - ResourceLo);
+ break;
+ default:
+ return false;
+ }
+
+ return true;
+}
+
+/**
+
+ Add resource node.
+
+ @param Resource A pointer to resource node to be added
+
+**/
+void AddSingleResource(STM_RSC *Resource)
+{
+ STM_RSC *Record;
+
+ Record = (STM_RSC *)mStmResourcesPtr;
+
+ while (true) {
+ if (Record->Header.RscType == END_OF_RESOURCES) {
+ break;
+ }
+ //
+ // Go to next record if resource and record types don't match.
+ //
+ if (Resource->Header.RscType != Record->Header.RscType) {
+ Record = (STM_RSC *)((void *)Record + Record->Header.Length);
+ continue;
+ }
+ //
+ // Record is handled inside of procedure - don't adjust.
+ //
+ if (HandleSingleResource (Resource, Record)) {
+ return ;
+ }
+ Record = (STM_RSC *)((void *)Record + Record->Header.Length);
+ }
+
+ //
+ // Add resource to the end of area.
+ //
+ memcpy (
+ mStmResourcesPtr + mStmResourceSizeUsed - sizeof(mRscEndNode),
+ Resource,
+ Resource->Header.Length
+ );
+ memcpy (
+ mStmResourcesPtr + mStmResourceSizeUsed - sizeof(mRscEndNode) + Resource->Header.Length,
+ &mRscEndNode,
+ sizeof(mRscEndNode)
+ );
+ mStmResourceSizeUsed += Resource->Header.Length;
+ mStmResourceSizeAvailable = mStmResourceTotalSize - mStmResourceSizeUsed;
+
+ return ;
+}
+
+/**
+
+ Add resource list.
+
+ @param ResourceList A pointer to resource list to be added
+ @param NumEntries Optional number of entries.
+ If 0, list must be terminated by END_OF_RESOURCES.
+
+**/
+void AddResource(STM_RSC *ResourceList, uint32_t NumEntries)
+{
+ uint32_t Count;
+ UINTN Index;
+ STM_RSC *Resource;
+
+ if (NumEntries == 0) {
+ Count = 0xFFFFFFFF;
+ } else {
+ Count = NumEntries;
+ }
+
+ Resource = ResourceList;
+
+ for (Index = 0; Index < Count; Index++) {
+ if (Resource->Header.RscType == END_OF_RESOURCES) {
+ return ;
+ }
+ AddSingleResource (Resource);
+ Resource = (STM_RSC *)((void *)Resource + Resource->Header.Length);
+ }
+ return ;
+}
+
+/**
+
+ Validate resource list.
+
+ @param ResourceList A pointer to resource list to be added
+ @param NumEntries Optional number of entries.
+ If 0, list must be terminated by END_OF_RESOURCES.
+
+ @retval true resource valid
+ @retval false resource invalid
+
+**/
+bool
+ValidateResource (
+ STM_RSC *ResourceList,
+ uint32_t NumEntries
+ )
+{
+ uint32_t Count;
+ UINTN Index;
+ STM_RSC *Resource;
+ UINTN SubIndex;
+
+ //
+ // If NumEntries == 0 make it very big. Scan will be terminated by
+ // END_OF_RESOURCES.
+ //
+ if (NumEntries == 0) {
+ Count = 0xFFFFFFFF;
+ } else {
+ Count = NumEntries;
+ }
+
+ //
+ // Start from beginning of resource list.
+ //
+ Resource = ResourceList;
+
+ for (Index = 0; Index < Count; Index++) {
+ printk(BIOS_DEBUG, "ValidateResource (%llu) - RscType(%x)\n", Index, Resource->Header.RscType);
+ //
+ // Validate resource.
+ //
+ switch (Resource->Header.RscType) {
+ case END_OF_RESOURCES:
+ if (Resource->Header.Length != sizeof (STM_RSC_END)) {
+ return false;
+ }
+ //
+ // If we are passed actual number of resources to add,
+ // END_OF_RESOURCES structure between them is considered an
+ // error. If NumEntries == 0 END_OF_RESOURCES is a termination.
+ //
+ if (NumEntries != 0) {
+ return false;
+ } else {
+ //
+ // If NumEntries == 0 and list reached end - return success.
+ //
+ return true;
+ }
+ break;
+
+ case MEM_RANGE:
+ case MMIO_RANGE:
+ if (Resource->Header.Length != sizeof (STM_RSC_MEM_DESC)) {
+ return false;
+ }
+
+ if (Resource->Mem.RWXAttributes > FULL_ACCS) {
+ return false;
+ }
+ break;
+
+ case IO_RANGE:
+ case TRAPPED_IO_RANGE:
+ if (Resource->Header.Length != sizeof (STM_RSC_IO_DESC)) {
+ return false;
+ }
+
+ if ((Resource->Io.Base + Resource->Io.Length) > 0xFFFF) {
+ return false;
+ }
+ break;
+
+ case PCI_CFG_RANGE:
+ printk(BIOS_DEBUG, "ValidateResource - PCI (0x%02x, 0x%08x, 0x%02x, 0x%02x)\n", Resource->PciCfg.OriginatingBusNumber, Resource->PciCfg.LastNodeIndex, Resource->PciCfg.PciDevicePath[0].PciDevice, Resource->PciCfg.PciDevicePath[0].PciFunction);
+ if (Resource->Header.Length != sizeof (STM_RSC_PCI_CFG_DESC) + (sizeof(STM_PCI_DEVICE_PATH_NODE) * Resource->PciCfg.LastNodeIndex)) {
+ return false;
+ }
+ for (SubIndex = 0; SubIndex <= Resource->PciCfg.LastNodeIndex; SubIndex++) {
+ if ((Resource->PciCfg.PciDevicePath[SubIndex].PciDevice > 0x1F) || (Resource->PciCfg.PciDevicePath[SubIndex].PciFunction > 7)) {
+ return false;
+ }
+ }
+ if ((Resource->PciCfg.Base + Resource->PciCfg.Length) > 0x1000) {
+ return false;
+ }
+ break;
+
+ case MACHINE_SPECIFIC_REG:
+ if (Resource->Header.Length != sizeof (STM_RSC_MSR_DESC)) {
+ return false;
+ }
+ break;
+
+ default :
+ printk(BIOS_DEBUG, "ValidateResource - Unknown RscType(%x)\n", Resource->Header.RscType);
+ return false;
+ }
+ Resource = (STM_RSC *)((void *)Resource + Resource->Header.Length);
+ }
+ return true;
+}
+
+/**
+
+ Get resource list.
+ EndResource is excluded.
+
+ @param ResourceList A pointer to resource list to be added
+ @param NumEntries Optional number of entries.
+ If 0, list must be terminated by END_OF_RESOURCES.
+
+ @retval true resource valid
+ @retval false resource invalid
+
+**/
+UINTN
+GetResourceSize (
+ STM_RSC *ResourceList,
+ uint32_t NumEntries
+ )
+{
+ uint32_t Count;
+ UINTN Index;
+ STM_RSC *Resource;
+
+ Resource = ResourceList;
+
+ //
+ // If NumEntries == 0 make it very big. Scan will be terminated by
+ // END_OF_RESOURCES.
+ //
+ if (NumEntries == 0) {
+ Count = 0xFFFFFFFF;
+ } else {
+ Count = NumEntries;
+ }
+
+ //
+ // Start from beginning of resource list.
+ //
+ Resource = ResourceList;
+
+ for (Index = 0; Index < Count; Index++) {
+ if (Resource->Header.RscType == END_OF_RESOURCES) {
+ break;
+ }
+ Resource = (STM_RSC *)((void *)Resource + Resource->Header.Length);
+ }
+ return (UINTN)((uint32_t)Resource - (uint32_t) ResourceList);
+}
+
+/**
+
+ Add resources in list to database. Allocate new memory areas as needed.
+
+ @param ResourceList A pointer to resource list to be added
+ @param NumEntries Optional number of entries.
+ If 0, list must be terminated by END_OF_RESOURCES.
+
+ @retval EFI_SUCCESS If resources are added
+ @retval EFI_INVALID_PARAMETER If nested procedure detected resource failer
+ @retval EFI_OUT_OF_RESOURCES If nested procedure returned it and we cannot allocate more areas.
+
+**/
+int
+AddPiResource (
+ STM_RSC *ResourceList,
+ uint32_t NumEntries
+ )
+{
+ //int Status;
+ UINTN ResourceSize;
+ //void * NewResource;
+ //UINTN NewResourceSize;
+
+ printk (BIOS_DEBUG, "AddPiResource - Enter\n");
+
+ if (!ValidateResource (ResourceList, NumEntries)) {
+ return -1; //EFI_INVALID_PARAMETER;
+ }
+
+ ResourceSize = GetResourceSize (ResourceList, NumEntries);
+ printk (BIOS_DEBUG, "ResourceSize - 0x%08llx\n", ResourceSize);
+ if (ResourceSize == 0) {
+ return -1;//EFI_INVALID_PARAMETER;
+ }
+
+ if (mStmResourcesPtr == NULL) {
+ //
+ // Copy EndResource for intialization
+ //
+ //mStmResourcesPtr = (uint8_t *)(UINTN)NewResource;
+ //mStmResourceTotalSize = NewResourceSize;
+
+ mStmResourcesPtr = StmResourceHeap;
+ mStmResourceTotalSize = RESOURCEHEAPSIZE;
+ memset(mStmResourcesPtr, 0, RESOURCEHEAPSIZE);
+
+ memcpy (mStmResourcesPtr, &mRscEndNode, sizeof(mRscEndNode));
+ mStmResourceSizeUsed = sizeof(mRscEndNode);
+ mStmResourceSizeAvailable = mStmResourceTotalSize - sizeof(mRscEndNode);
+
+ //
+ // Let SmmCore change resource ptr
+ //
+ //NotifyStmResourceChange (mStmResourcesPtr);
+ } else if (mStmResourceSizeAvailable < ResourceSize) {
+ //
+ // Need enlarge
+ //
+ printk(BIOS_DEBUG, "ERROR - not enough soace for SMM resource list\n");
+ return -1;
+ }
+
+ //
+ // Check duplication
+ //
+ AddResource (ResourceList, NumEntries);
+
+ return 0;//EFI_SUCCESS;
+}
+
+/**
+
+ Delete resources in list to database.
+
+ @param ResourceList A pointer to resource list to be deleted
+ NULL means delete all resources.
+ @param NumEntries Optional number of entries.
+ If 0, list must be terminated by END_OF_RESOURCES.
+
+ @retval EFI_SUCCESS If resources are deleted
+ @retval EFI_INVALID_PARAMETER If nested procedure detected resource failer
+
+**/
+int32_t
+DeletePiResource (
+ STM_RSC *ResourceList,
+ uint32_t NumEntries
+ )
+{
+ if (ResourceList != NULL) {
+ // TBD
+ //ASSERT (false);
+ return -1;//EFI_UNSUPPORTED;
+ }
+ //
+ // Delete all
+ //
+ memcpy (mStmResourcesPtr, &mRscEndNode, sizeof(mRscEndNode));
+ mStmResourceSizeUsed = sizeof(mRscEndNode);
+ mStmResourceSizeAvailable = mStmResourceTotalSize - sizeof(mRscEndNode);
+ return 0;//EFI_SUCCESS;
+}
+
+/**
+
+ Get BIOS resources.
+
+ @param ResourceList A pointer to resource list to be filled
+ @param ResourceSize On input it means size of resource list input.
+ On output it means size of resource list filled,
+ or the size of resource list to be filled if size of too small.
+
+ @retval EFI_SUCCESS If resources are returned.
+ @retval EFI_BUFFER_TOO_SMALL If resource list buffer is too small to hold the whole resources.
+
+**/
+int32_t
+GetPiResource (
+ STM_RSC *ResourceList,
+ uint32_t *ResourceSize
+ )
+{
+ if (*ResourceSize < mStmResourceSizeUsed) {
+ *ResourceSize = (uint32_t)mStmResourceSizeUsed;
+ return -1;//EFI_BUFFER_TOO_SMALL;
+ }
+
+ memcpy (ResourceList, mStmResourcesPtr, mStmResourceSizeUsed);
+ *ResourceSize = (uint32_t)mStmResourceSizeUsed;
+ return 0;//EFI_SUCCESS;
+}
+
+/**
+ Get 4K page aligned VMCS size.
+ @return 4K page aligned VMCS size
+
+**/
+uint32_t
+GetVmcsSize (
+ void
+ )
+{
+ uint32_t ThisVmcsSize;
+ VMX_BASIC_MSR MsrData64;
+ int StmSupport;
+
+ MsrData64.msr = rdmsr (IA32_VMX_BASIC_MSR_INDEX);
+
+ ThisVmcsSize = MsrData64.bits.VmcsSize;
+ StmSupport = MsrData64.bits.StmSupported;
+ printk(BIOS_DEBUG, "GetVmcsSize: Size %d StmSupport %d\n", ThisVmcsSize, StmSupport);
+
+ //
+ // VMCS require 0x1000 alignment
+ //
+ ThisVmcsSize = STM_PAGES_TO_SIZE (STM_SIZE_TO_PAGES (ThisVmcsSize));
+
+ return ThisVmcsSize;
+}
+
+/**
+
+ Create 4G page table for STM.
+ 4M Non-PAE page table in IA32 version.
+
+ @param PageTableBase The page table base in MSEG
+
+**/
+void
+StmGen4GPageTableIa32 (
+ uint32_t PageTableBase
+ )
+{
+ UINTN Index;
+ uint32_t *Pte;
+ uint32_t Address;
+
+ Pte = (uint32_t*)(uint32_t)PageTableBase;
+
+ Address = 0;
+ for (Index = 0; Index < SIZE_4KB / sizeof (*Pte); Index++) {
+ *Pte = Address | IA32_PG_PS | IA32_PG_RW | IA32_PG_P;
+ Pte++;
+ Address += SIZE_4MB;
+ }
+
+ return ;
+}
+
+/**
+
+ Create 4G page table for STM.
+ 2M PAE page table in X64 version.
+
+ @param PageTableBase The page table base in MSEG
+
+**/
+void
+StmGen4GPageTableX64 (
+ uint32_t PageTableBase
+ )
+{
+ UINTN Index;
+ UINTN SubIndex;
+ uint64_t *Pde;
+ uint64_t *Pte;
+ uint64_t *Pml4;
+
+ Pml4 = (uint64_t*)(uint32_t) PageTableBase;
+ PageTableBase += SIZE_4KB;
+ *Pml4 = PageTableBase | IA32_PG_RW | IA32_PG_P;
+
+ Pde = (uint64_t*)(uint32_t)PageTableBase;
+ PageTableBase += SIZE_4KB;
+ Pte = (uint64_t *)(uint32_t)PageTableBase;
+
+ for (Index = 0; Index < 4; Index++) {
+ *Pde = PageTableBase | IA32_PG_RW | IA32_PG_P;
+ Pde++;
+ PageTableBase += SIZE_4KB;
+
+ for (SubIndex = 0; SubIndex < SIZE_4KB / sizeof (*Pte); SubIndex++) {
+ *Pte = (((Index << 9) + SubIndex) << 21) | IA32_PG_PS | IA32_PG_RW | IA32_PG_P;
+ Pte++;
+ }
+ }
+
+ return ;
+}
+
+/**
+
+ Check STM image size.
+
+ @param StmImage STM image
+ @param StmImageSize STM image size
+
+ @retval true check pass
+ @retval false check fail
+**/
+
+bool StmCheckStmImage (
+ void * StmImage,
+ uint32_t StmImageSize
+ )
+{
+ UINTN MinMsegSize;
+ STM_HEADER *StmHeader;
+
+ StmHeader = (STM_HEADER *)StmImage;
+
+ //
+ // Get Minimal required Mseg size
+ //
+ MinMsegSize = (STM_PAGES_TO_SIZE (STM_SIZE_TO_PAGES (StmHeader->SwStmHdr.StaticImageSize)) +
+ StmHeader->SwStmHdr.AdditionalDynamicMemorySize +
+ (StmHeader->SwStmHdr.PerProcDynamicMemorySize + GetVmcsSize () * 2) * mp_state.cpu_count);
+ if (MinMsegSize < StmImageSize) {
+ MinMsegSize = StmImageSize;
+ }
+
+ if (StmHeader->HwStmHdr.Cr3Offset >= StmHeader->SwStmHdr.StaticImageSize) {
+ //
+ // We will create page table, just in case that SINIT does not create it.
+ //
+ if (MinMsegSize < StmHeader->HwStmHdr.Cr3Offset + STM_PAGES_TO_SIZE(6)) {
+ MinMsegSize = StmHeader->HwStmHdr.Cr3Offset + STM_PAGES_TO_SIZE(6);
+ }
+ }
+
+ //
+ // Check if it exceeds MSEG size
+ //
+ if (MinMsegSize > CONFIG_MSEG_SIZE) {
+ return false;
+ }
+
+ return true;
+
+}
+
+
+/**
+
+ Load STM image to MSEG.
+
+ @param StmImage STM image
+ @param StmImageSize STM image size
+
+**/
+void
+StmLoadStmImage (
+ void * StmImage,
+ UINTN StmImageSize
+ )
+{
+ uint32_t MsegBase;
+ STM_HEADER *StmHeader;
+ SMM_MONITOR_CTL_MSR SmmMonitorMsr;
+
+ StmHeader = (STM_HEADER *)(uint32_t)StmImage;
+ SmmMonitorMsr.msr = rdmsr(IA32_SMM_MONITOR_CTL_MSR_INDEX);
+ MsegBase = SmmMonitorMsr.bits.MsegAddress << 12;
+
+ //ZeroMem ((void *)(uint32_t)MsegBase, (uint32_t)PcdGet32 (PcdCpuMsegSize));
+
+ memset((void *) MsegBase, 0, CONFIG_MSEG_SIZE);
+ //memcpy ((void *)(uint32_t)MsegBase, (void *)(uint32_t)StmImage, StmImageSize);
+ memcpy((void *) MsegBase, (void *) StmImage, (size_t) StmImageSize);
+
+
+ if (sizeof(UINTN) == sizeof(uint64_t)) {
+ StmGen4GPageTableX64 ((UINTN)MsegBase + StmHeader->HwStmHdr.Cr3Offset);
+ } else {
+ StmGen4GPageTableIa32 ((UINTN)MsegBase + StmHeader->HwStmHdr.Cr3Offset);
+ }
+
+ // BUGBUG: SNB can not write 0x9B twice
+// WriteCpuMsegInfo ();
+}
+
+/**
+
+ Load STM image to MSEG.
+
+ @param StmImage STM image
+ @param StmImageSize STM image size
+
+ @retval EFI_SUCCESS Load STM to MSEG successfully
+ @retval EFI_ALREADY_STARTED STM image is already loaded to MSEG
+ @retval EFI_BUFFER_TOO_SMALL MSEG is smaller than minimal requirement of STM image
+ @retval EFI_UNSUPPORTED MSEG is not enabled
+
+**/
+int LoadMonitor (
+ void * StmImage,
+ uint32_t StmImageSize
+ )
+{
+ SMM_MONITOR_CTL_MSR SmmMonCtlMsr;
+
+ SmmMonCtlMsr.msr = (msr_t) rdmsr(IA32_SMM_MONITOR_CTL_MSR_INDEX);
+
+ if (SmmMonCtlMsr.bits.MsegAddress == 0) {
+ return STM_UNSUPPORTED;
+ }
+ if (SmmMonCtlMsr.bits.valid != 0) {
+ // BUGBUG: SNB can not write 0x9B twice
+// return EFI_ALREADY_STARTED;
+ }
+
+ if (!StmCheckStmImage (StmImage, StmImageSize)) {
+ return STM_BUFFER_TOO_SMALL;
+ }
+
+#ifdef TPMSUPPORT
+ // Record STM_HASH to PCR 0, just in case it is NOT TXT launch, we still need provide the evidence.
+ TpmMeasureAndLogData(
+ 0, // PcrIndex
+ TXT_EVTYPE_STM_HASH, // EventType
+ NULL, // EventLog
+ 0, // LogLen
+ (void *)StmImage, // HashData
+ StmImageSize // HashDataLen
+ );
+#endif
+ StmLoadStmImage (StmImage, StmImageSize);
+
+ mStmState |= STM_SM_MONITOR_STATE_ENABLED;
+
+ return STM_SUCCESS;
+}
+
+/**
+ This function return BIOS STM resource.
+ Produced by SmmStm.
+ Comsumed by SmmMpService when Init.
+
+ @return BIOS STM resource
+**/
+void *
+GetStmResource(
+ void
+ )
+{
+ return mStmResourcesPtr;
+}
+
diff --git a/src/security/intel/stm/SmmStm.h b/src/security/intel/stm/SmmStm.h
new file mode 100644
index 0000000..4442a63
--- /dev/null
+++ b/src/security/intel/stm/SmmStm.h
@@ -0,0 +1,122 @@
+/** @file
+ SMM STM support
+
+ Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
+ This program and the accompanying materials are licensed and made
+ available under the terms and conditions of the BSD License which
+ accompanies this distribution. The full text of the license may
+ be found at http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED
+
+**/
+
+#ifndef _SMM_STM_H_
+#define _SMM_STM_H_
+
+#include "StmApi.h"
+
+#define IA32_VMX_BASIC_MSR_INDEX 0x480
+#define IA32_VMX_MISC_MSR_INDEX 0x485
+#define IA32_SMM_MONITOR_CTL_MSR_INDEX 0x9B
+#define IA32_SMM_MONITOR_VALID (1<<0)
+
+/**
+
+ Load STM image to MSEG.
+
+ @param StmImage STM image
+ @param StmImageSize STM image size
+
+ @retval SUCCESS Load STM to MSEG successfully
+ @retval BUFFER_TOO_SMALL MSEG is smaller than minimal size of STM image
+
+**/
+int LoadMonitor(
+ void *StmImage,
+ uint32_t StmImageSize
+ );
+
+/**
+
+ Add resources in list to database. Allocate new memory areas as needed.
+
+ @param ResourceList A pointer to resource list to be added
+ @param NumEntries Optional number of entries.
+ If 0, list must be terminated by END_OF_RESOURCES.
+
+ @retval SUCCESS If resources are added
+ @retval INVALID_PARAMETER If nested procedure detected resource failer
+ @retval OUT_OF_RESOURCES If nested procedure returned it and we cannot allocate more areas.
+
+**/
+int AddPiResource(
+ STM_RSC *ResourceList,
+ uint32_t NumEntries
+ );
+
+/**
+
+ Delete resources in list to database.
+
+ @param ResourceList A pointer to resource list to be deleted
+ NULL means delete all resources.
+ @param NumEntries Optional number of entries.
+ If 0, list must be terminated by END_OF_RESOURCES.
+
+ @retval SUCCESS If resources are deleted
+ @retval NVALID_PARAMETER If nested procedure detected resource failer
+
+**/
+int DeletePiResource(
+ STM_RSC *ResourceList,
+ uint32_t NumEntries
+ );
+
+/**
+
+ Get BIOS resources.
+
+ @param ResourceList A pointer to resource list to be filled
+ @param ResourceSize On input it means size of resource list input.
+ On output it means size of resource list filled,
+ or the size of resource list to be filled if
+ size of too small.
+
+ @retval SUCCESS If resources are returned.
+ @retval BUFFER_TOO_SMALL If resource list buffer is too small to
+ hold the whole resources.
+
+**/
+int GetPiResource(
+ STM_RSC *ResourceList,
+ uint32_t *ResourceSize
+ );
+
+/**
+ This function notify STM resource change.
+
+ @param StmResource BIOS STM resource
+
+**/
+void
+NotifyStmResourceChange(
+ void *StmResource
+ );
+
+/**
+ This function return BIOS STM resource.
+
+ @return BIOS STM resource
+
+**/
+void *
+GetStmResource(
+ void
+ );
+
+void SetupSmmDescriptor(void *smbase, int32_t state_size, int32_t apic_id,
+ int32_t entry32_off);
+
+#endif
diff --git a/src/security/intel/stm/StmApi.h b/src/security/intel/stm/StmApi.h
new file mode 100644
index 0000000..2328b32
--- /dev/null
+++ b/src/security/intel/stm/StmApi.h
@@ -0,0 +1,753 @@
+/** @file
+ STM API definition
+
+ Copyright (c) 2015, Intel Corporation. All rights reserved.
+ This program and the accompanying materials are licensed and made available
+ under the terms and conditions of the BSD License which accompanies this
+ distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _STM_API_H_
+#define _STM_API_H_
+
+#include <stdint.h>
+
+// definition in STM spec
+
+#define STM_SPEC_VERSION_MAJOR 1
+#define STM_SPEC_VERSION_MINOR 0
+
+typedef uint64_t UINTN;
+
+#pragma pack (push, 1)
+
+#define STM_HARDWARE_FIELD_FILL_TO_2K (2048 - sizeof(uint32_t) * 8)
+typedef struct {
+ uint32_t StmHeaderRevision;
+ uint32_t MonitorFeatures;
+ uint32_t GdtrLimit;
+ uint32_t GdtrBaseOffset;
+ uint32_t CsSelector;
+ uint32_t EipOffset;
+ uint32_t EspOffset;
+ uint32_t Cr3Offset;
+ uint8_t Reserved[STM_HARDWARE_FIELD_FILL_TO_2K];
+} HARDWARE_STM_HEADER;
+
+#define STM_FEATURES_IA32E 0x1
+
+typedef struct {
+ uint32_t Intel64ModeSupported :1; // bitfield
+ uint32_t EptSupported :1; // bitfield
+ uint32_t Reserved :30; // must be 0
+} STM_FEAT;
+
+typedef struct {
+ uint8_t StmSpecVerMajor;
+ uint8_t StmSpecVerMinor;
+ uint16_t Reserved; // must be zero
+ uint32_t StaticImageSize;
+ uint32_t PerProcDynamicMemorySize;
+ uint32_t AdditionalDynamicMemorySize;
+ STM_FEAT StmFeatures;
+ uint32_t NumberOfRevIDs;
+ uint32_t StmSmmRevID[1];
+ //
+ // The total STM_HEADER should be 4K.
+ //
+} SOFTWARE_STM_HEADER;
+
+typedef struct {
+ HARDWARE_STM_HEADER HwStmHdr;
+ SOFTWARE_STM_HEADER SwStmHdr;
+} STM_HEADER;
+
+#define SHA1 1
+#define SHA256 2
+typedef struct {
+ uint64_t BiosComponentBase;
+ uint32_t ImageSize;
+ uint32_t HashAlgorithm; // SHA1 or SHA256
+ uint8_t Hash[32];
+} TXT_BIOS_COMPONENT_STATUS;
+
+#define PAGE_SIZE 4096
+typedef struct {
+ uint32_t ImageSize;
+ uint32_t Reserved;
+ uint64_t ImagePageBase[1]; //[NumberOfPages];
+} TXT_BIOS_COMPONENT_UPDATE;
+
+// If (ImageSizeInBytes % PAGE_SIZE == 0) {
+// NumberOfPages = ImageSizeInBytes / PAGE_SIZE
+// } else {
+// NumberOfPages = ImageSizeInBytes / PAGE_SIZE + 1
+// }
+
+
+typedef struct {
+ uint64_t SpeRip;
+ uint64_t SpeRsp;
+ uint16_t SpeSs;
+ uint16_t PageViolationException:1;
+ uint16_t MsrViolationException:1;
+ uint16_t RegisterViolationException:1;
+ uint16_t IoViolationException:1;
+ uint16_t PciViolationException:1;
+ uint16_t Reserved1:11;
+ uint32_t Reserved2;
+} STM_PROTECTION_EXCEPTION_HANDLER;
+
+typedef struct {
+ uint8_t ExecutionDisableOutsideSmrr:1;
+ uint8_t Intel64Mode:1;
+ uint8_t Cr4Pae : 1;
+ uint8_t Cr4Pse : 1;
+ uint8_t Reserved1 : 4;
+} STM_SMM_ENTRY_STATE;
+
+typedef struct {
+ uint8_t SmramToVmcsRestoreRequired : 1; // BIOS restore hint
+ uint8_t ReinitializeVmcsRequired : 1; // BIOS request
+ uint8_t Reserved2 : 6;
+} STM_SMM_RESUME_STATE;
+
+typedef struct {
+ uint8_t DomainType : 4; // STM input to BIOS on each SM
+ uint8_t XStatePolicy : 2; // STM input to BIOS on each SMI
+ uint8_t EptEnabled : 1;
+ uint8_t Reserved3 : 1;
+} STM_SMM_STATE;
+
+typedef struct {
+ uint64_t Signature;
+ uint16_t Size;
+ uint8_t SmmDescriptorVerMajor;
+ uint8_t SmmDescriptorVerMinor;
+ uint32_t LocalApicId;
+ STM_SMM_ENTRY_STATE SmmEntryState;
+ STM_SMM_RESUME_STATE SmmResumeState;
+ STM_SMM_STATE StmSmmState;
+ uint8_t Reserved4;
+ uint16_t SmmCs;
+ uint16_t SmmDs;
+ uint16_t SmmSs;
+ uint16_t SmmOtherSegment;
+ uint16_t SmmTr;
+ uint16_t Reserved5;
+ uint64_t SmmCr3;
+ uint64_t SmmStmSetupRip;
+ uint64_t SmmStmTeardownRip;
+ uint64_t SmmSmiHandlerRip;
+ uint64_t SmmSmiHandlerRsp;
+ uint64_t SmmGdtPtr;
+ uint32_t SmmGdtSize;
+ uint32_t RequiredStmSmmRevId;
+ STM_PROTECTION_EXCEPTION_HANDLER StmProtectionExceptionHandler;
+ uint64_t Reserved6;
+ uint64_t BiosHwResourceRequirementsPtr;
+ // extend area
+ uint64_t AcpiRsdp;
+ uint8_t PhysicalAddressBits;
+} TXT_PROCESSOR_SMM_DESCRIPTOR;
+
+#define TXT_PROCESSOR_SMM_DESCRIPTOR_SIGNATURE "TXTPSSIG"
+#define TXT_PROCESSOR_SMM_DESCRIPTOR_VERSION_MAJOR 1
+#define TXT_PROCESSOR_SMM_DESCRIPTOR_VERSION_MINOR 0
+
+#define SMM_PSD_OFFSET 0xfb00
+
+typedef enum {
+ TxtSmmPageViolation = 1,
+ TxtSmmMsrViolation,
+ TxtSmmRegisterViolation,
+ TxtSmmIoViolation,
+ TxtSmmPciViolation
+} TXT_SMM_PROTECTION_EXCEPTION_TYPE;
+
+typedef struct {
+ uint32_t Rdi;
+ uint32_t Rsi;
+ uint32_t Rbp;
+ uint32_t Rdx;
+ uint32_t Rcx;
+ uint32_t Rbx;
+ uint32_t Rax;
+ uint32_t Cr3;
+ uint32_t Cr2;
+ uint32_t Cr0;
+ uint32_t VmcsExitInstructionInfo;
+ uint32_t VmcsExitInstructionLength;
+ uint64_t VmcsExitQualification;
+ uint32_t ErrorCode; // TXT_SMM_PROTECTION_EXCEPTION_TYPE
+ uint32_t Rip;
+ uint32_t Cs;
+ uint32_t Rflags;
+ uint32_t Rsp;
+ uint32_t Ss;
+} STM_PROTECTION_EXCEPTION_STACK_FRAME_IA32;
+
+typedef struct {
+ uint64_t R15;
+ uint64_t R14;
+ uint64_t R13;
+ uint64_t R12;
+ uint64_t R11;
+ uint64_t R10;
+ uint64_t R9;
+ uint64_t R8;
+ uint64_t Rdi;
+ uint64_t Rsi;
+ uint64_t Rbp;
+ uint64_t Rdx;
+ uint64_t Rcx;
+ uint64_t Rbx;
+ uint64_t Rax;
+ uint64_t Cr8;
+ uint64_t Cr3;
+ uint64_t Cr2;
+ uint64_t Cr0;
+ uint64_t VmcsExitInstructionInfo;
+ uint64_t VmcsExitInstructionLength;
+ uint64_t VmcsExitQualification;
+ uint64_t ErrorCode; // TXT_SMM_PROTECTION_EXCEPTION_TYPE
+ uint64_t Rip;
+ uint64_t Cs;
+ uint64_t Rflags;
+ uint64_t Rsp;
+ uint64_t Ss;
+} STM_PROTECTION_EXCEPTION_STACK_FRAME_X64;
+
+typedef union {
+ STM_PROTECTION_EXCEPTION_STACK_FRAME_IA32 *Ia32StackFrame;
+ STM_PROTECTION_EXCEPTION_STACK_FRAME_X64 *X64StackFrame;
+} STM_PROTECTION_EXCEPTION_STACK_FRAME;
+
+#define STM_SMM_REV_ID 0x80010100
+
+typedef struct _STM_SMM_CPU_STATE {
+ uint8_t Reserved1[0x1d0]; // fc00h
+ uint32_t GdtBaseHiDword; // fdd0h : NO
+ uint32_t LdtBaseHiDword; // fdd4h : NO
+ uint32_t IdtBaseHiDword; // fdd8h : NO
+ uint8_t Reserved2[0x4]; // fddch
+ uint64_t IoRdi; // fde0h : NO
+ // - restricted
+ uint64_t IoEip; // fde8h : YES
+ uint64_t IoRcx; // fdf0h : NO
+ // - restricted
+ uint64_t IoRsi; // fdf8h : NO
+ // - restricted
+ uint8_t Reserved3[0x40]; // fe00h
+ uint32_t Cr4; // fe40h : NO
+ uint8_t Reserved4[0x48]; // fe44h
+ uint32_t GdtBaseLoDword; // fe8ch : NO
+ uint32_t GdtLimit; // fe90h : NO
+ // - RESTRICTED
+ uint32_t IdtBaseLoDword; // fe94h : NO
+ uint32_t IdtLimit; // fe98h : NO
+ // - RESTRICTED
+ uint32_t LdtBaseLoDword; // fe9ch : NO
+ uint32_t LdtLimit; // fea0h : NO
+ // - RESTRICTED
+ uint32_t LdtInfo; // fea4h : NO
+ // - RESTRICTED
+ uint8_t Reserved5[0x30]; // fea8h
+ uint64_t Eptp; // fed8h : NO
+ uint32_t EnabledEPT; // fee0h : NO
+ uint8_t Reserved6[0x14]; // fee4h
+ uint32_t Smbase; // fef8h : YES
+ // - NO for STM
+ uint32_t SMMRevId; // fefch : NO
+ uint16_t IORestart; // ff00h : YES
+ uint16_t AutoHALTRestart; // ff02h : YES
+ uint8_t Reserved7[0x18]; // ff04h
+ uint64_t R15; // ff1ch : YES
+ uint64_t R14; // ff24h : YES
+ uint64_t R13; // ff2ch : YES
+ uint64_t R12; // ff34h : YES
+ uint64_t R11; // ff3ch : YES
+ uint64_t R10; // ff44h : YES
+ uint64_t R9; // ff4ch : YES
+ uint64_t R8; // ff54h : YES
+ uint64_t Rax; // ff5ch : YES
+ uint64_t Rcx; // ff64h : YES
+ uint64_t Rdx; // ff6ch : YES
+ uint64_t Rbx; // ff74h : YES
+ uint64_t Rsp; // ff7ch : YES
+ uint64_t Rbp; // ff84h : YES
+ uint64_t Rsi; // ff8ch : YES
+ uint64_t Rdi; // ff94h : YES
+ uint64_t IOMemAddr; // ff9ch : NO
+ uint32_t IOMisc; // ffa4h : NO
+ uint32_t Es; // ffa8h : NO
+ uint32_t Cs; // ffach : NO
+ uint32_t Ss; // ffb0h : NO
+ uint32_t Ds; // ffb4h : NO
+ uint32_t Fs; // ffb8h : NO
+ uint32_t Gs; // ffbch : NO
+ uint32_t Ldtr; // ffc0h : NO
+ uint32_t Tr; // ffc4h : NO
+ uint64_t Dr7; // ffc8h : NO
+ uint64_t Dr6; // ffd0h : NO
+ uint64_t Rip; // ffd8h : YES
+ uint64_t Ia32Efer; // ffe0h : YES
+ // - NO for STM
+ uint64_t Rflags; // ffe8h : YES
+ uint64_t Cr3; // fff0h : NO
+ uint64_t Cr0; // fff8h : NO
+} STM_SMM_CPU_STATE;
+
+//
+// STM Mapping
+//
+
+typedef struct {
+ uint64_t PhysicalAddress;
+ uint64_t VirtualAddress;
+ uint32_t PageCount;
+ uint32_t PatCacheType;
+} STM_MAP_ADDRESS_RANGE_DESCRIPTOR;
+#define ST_UC 0x00
+#define WC 0x01
+#define WT 0x04
+#define WP 0x05
+#define WB 0x06
+#define UC 0x07
+#define FOLLOW_MTRR 0xFFFFFFFF
+
+typedef struct {
+ uint64_t VirtualAddress;
+ uint32_t Length;
+} STM_UNMAP_ADDRESS_RANGE_DESCRIPTOR;
+
+typedef struct {
+ uint64_t InterruptedGuestVirtualAddress;
+ uint32_t Length;
+ uint64_t InterruptedCr3;
+ uint64_t InterruptedEptp;
+ uint32_t MapToSmmGuest:2;
+ uint32_t InterruptedCr4Pae:1;
+ uint32_t InterruptedCr4Pse:1;
+ uint32_t InterruptedIa32eMode:1;
+ uint32_t Reserved1:27;
+ uint32_t Reserved2;
+ uint64_t PhysicalAddress;
+ uint64_t SmmGuestVirtualAddress;
+} STM_ADDRESS_LOOKUP_DESCRIPTOR;
+#define DO_NOT_MAP 0
+#define ONE_TO_ONE 1
+#define VIRTUAL_ADDRESS_SPECIFIED 3
+
+//
+// STM_RESOURCE_LIST
+//
+#define END_OF_RESOURCES 0
+#define MEM_RANGE 1
+#define IO_RANGE 2
+#define MMIO_RANGE 3
+#define MACHINE_SPECIFIC_REG 4
+#define PCI_CFG_RANGE 5
+#define TRAPPED_IO_RANGE 6
+#define ALL_RESOURCES 7
+#define REGISTER_VIOLATION 8
+#define MAX_DESC_TYPE 8
+
+typedef struct {
+ uint32_t RscType;
+ uint16_t Length;
+ uint16_t ReturnStatus:1;
+ uint16_t Reserved:14;
+ uint16_t IgnoreResource:1;
+} STM_RSC_DESC_HEADER;
+
+typedef struct {
+ STM_RSC_DESC_HEADER Hdr;
+ uint64_t ResourceListContinuation;
+} STM_RSC_END;
+
+// byte granular Memory range support
+#define STM_RSC_BGM 0x4
+
+typedef struct {
+ STM_RSC_DESC_HEADER Hdr;
+ uint64_t Base;
+ uint64_t Length;
+ uint32_t RWXAttributes:3;
+ uint32_t Reserved:29;
+ uint32_t Reserved_2;
+} STM_RSC_MEM_DESC;
+#define STM_RSC_MEM_R 0x1
+#define STM_RSC_MEM_W 0x2
+#define STM_RSC_MEM_X 0x4
+
+typedef struct {
+ STM_RSC_DESC_HEADER Hdr;
+ uint16_t Base;
+ uint16_t Length;
+ uint32_t Reserved;
+} STM_RSC_IO_DESC;
+
+// byte granular MMIO range support
+#define STM_RSC_BGI 0x2
+
+typedef struct {
+ STM_RSC_DESC_HEADER Hdr;
+ uint64_t Base;
+ uint64_t Length;
+ uint32_t RWXAttributes:3;
+ uint32_t Reserved:29;
+ uint32_t Reserved_2;
+} STM_RSC_MMIO_DESC;
+#define STM_RSC_MMIO_R 0x1
+#define STM_RSC_MMIO_W 0x2
+#define STM_RSC_MMIO_X 0x4
+
+typedef struct {
+ STM_RSC_DESC_HEADER Hdr;
+ uint32_t MsrIndex;
+ uint32_t KernelModeProcessing:1;
+ uint32_t Reserved:31;
+ uint64_t ReadMask;
+ uint64_t WriteMask;
+} STM_RSC_MSR_DESC;
+
+// bit granular MSR resource support
+#define STM_RSC_MSR 0x8
+
+typedef struct {
+ uint8_t Type; // must be 1, indicating Hardware Device Path
+ uint8_t Subtype; // must be 1, indicating PCI
+ uint16_t Length; // sizeof(STM_PCI_DEVICE_PATH_NODE) which is 6
+ uint8_t PciFunction;
+ uint8_t PciDevice;
+} STM_PCI_DEVICE_PATH_NODE;
+typedef struct {
+ STM_RSC_DESC_HEADER Hdr;
+ uint16_t RWAttributes:2;
+ uint16_t Reserved:14;
+ uint16_t Base;
+ uint16_t Length;
+ uint8_t OriginatingBusNumber;
+ uint8_t LastNodeIndex;
+ STM_PCI_DEVICE_PATH_NODE PciDevicePath[1];
+//STM_PCI_DEVICE_PATH_NODE PciDevicePath[LastNodeIndex + 1];
+} STM_RSC_PCI_CFG_DESC;
+
+#define STM_RSC_PCI_CFG_R 0x1
+#define STM_RSC_PCI_CFG_W 0x2
+
+typedef struct {
+ STM_RSC_DESC_HEADER Hdr;
+ uint16_t Base;
+ uint16_t Length;
+ uint16_t In:1;
+ uint16_t Out:1;
+ uint16_t Api:1;
+ uint16_t Reserved1:13;
+ uint16_t Reserved2;
+} STM_RSC_TRAPPED_IO_DESC;
+
+typedef struct {
+ STM_RSC_DESC_HEADER Hdr;
+} STM_RSC_ALL_RESOURCES_DESC;
+
+typedef struct {
+ STM_RSC_DESC_HEADER Hdr;
+ uint32_t RegisterType;
+ uint32_t Reserved;
+ uint64_t ReadMask;
+ uint64_t WriteMask;
+} STM_REGISTER_VIOLATION_DESC;
+
+typedef enum {
+ StmRegisterCr0,
+ StmRegisterCr2,
+ StmRegisterCr3,
+ StmRegisterCr4,
+ StmRegisterCr8,
+ StmRegisterMax,
+} STM_REGISTER_VIOLATION_TYPE;
+
+typedef union {
+ STM_RSC_DESC_HEADER Header;
+ STM_RSC_END End;
+ STM_RSC_MEM_DESC Mem;
+ STM_RSC_IO_DESC Io;
+ STM_RSC_MMIO_DESC Mmio;
+ STM_RSC_MSR_DESC Msr;
+ STM_RSC_PCI_CFG_DESC PciCfg;
+ STM_RSC_TRAPPED_IO_DESC TrappedIo;
+ STM_RSC_ALL_RESOURCES_DESC All;
+ STM_REGISTER_VIOLATION_DESC RegisterViolation;
+} STM_RSC;
+
+//
+// VMCS database
+//
+#define STM_VMCS_DATABASE_REQUEST_ADD 1
+#define STM_VMCS_DATABASE_REQUEST_REMOVE 0
+
+// Values for DomainType
+// Intepreter of DomainType
+#define DOMAIN_DISALLOWED_IO_OUT (1u << 0)
+#define DOMAIN_DISALLOWED_IO_IN (1u << 1)
+#define DOMAIN_INTEGRITY (1u << 2)
+#define DOMAIN_CONFIDENTIALITY (1u << 3)
+
+#define DOMAIN_UNPROTECTED 0x00
+#define DOMAIN_INTEGRITY_PROT_OUT_IN (DOMAIN_INTEGRITY)
+//#define DOMAIN_INTEGRITY_PROT_OUT (DOMAIN_INTEGRITY | DOMAIN_DISALLOWED_IO_IN)
+#define DOMAIN_FULLY_PROT_OUT_IN (DOMAIN_CONFIDENTIALITY | DOMAIN_INTEGRITY)
+//#define DOMAIN_FULLY_PROT_IN (DOMAIN_CONFIDENTIALITY | DOMAIN_INTEGRITY | DOMAIN_DISALLOWED_IO_OUT)
+//#define DOMAIN_FULLY_PROT_OUT (DOMAIN_CONFIDENTIALITY | DOMAIN_INTEGRITY | DOMAIN_DISALLOWED_IO_IN)
+#define DOMAIN_FULLY_PROT (DOMAIN_CONFIDENTIALITY | DOMAIN_INTEGRITY | DOMAIN_DISALLOWED_IO_IN | DOMAIN_DISALLOWED_IO_OUT)
+
+// Values for XStatePolicy
+#define XSTATE_READWRITE 0x00
+#define XSTATE_READONLY 0x01
+#define XSTATE_SCRUB 0x03
+
+typedef struct {
+ uint64_t VmcsPhysPointer; // bits 11:0 are reserved and must be 0
+ uint32_t DomainType :4;
+ uint32_t XStatePolicy :2;
+ uint32_t DegradationPolicy :4;
+ uint32_t Reserved1 :22; // Must be 0
+ uint32_t AddOrRemove;
+} STM_VMCS_DATABASE_REQUEST;
+
+//
+// Event log
+//
+#define NEW_LOG 1
+#define CONFIGURE_LOG 2
+#define START_LOG 3
+#define STOP_LOG 4
+#define CLEAR_LOG 5
+#define DELETE_LOG 6
+typedef enum {
+ EvtLogStarted,
+ EvtLogStopped,
+ EvtLogInvalidParameterDetected,
+ EvtHandledProtectionException,
+ // unhandled protection exceptions result in reset & cannot be logged
+ EvtBiosAccessToUnclaimedResource,
+ EvtMleResourceProtectionGranted,
+ EvtMleResourceProtectionDenied,
+ EvtMleResourceUnprotect,
+ EvtMleResourceUnprotectError,
+ EvtMleDomainTypeDegraded,
+ // add more here
+ EvtMleMax,
+ // Not used
+ EvtInvalid = 0xFFFFFFFF,
+} EVENT_TYPE;
+
+//#define STM_EVENT_LOG_PAGE_COUNT_MAX 62
+
+typedef struct {
+ uint32_t PageCount;
+ uint64_t Pages[1]; // number of elements is PageCount
+} STM_EVENT_LOG_MANAGEMENT_REQUEST_DATA_LOG_BUFFER;
+
+typedef union {
+ STM_EVENT_LOG_MANAGEMENT_REQUEST_DATA_LOG_BUFFER LogBuffer;
+ uint32_t EventEnableBitmap; // bitmap of EVENT_TYPE
+} STM_EVENT_LOG_MANAGEMENT_REQUEST_DATA;
+
+typedef struct {
+ uint32_t SubFunctionIndex;
+ STM_EVENT_LOG_MANAGEMENT_REQUEST_DATA Data;
+} STM_EVENT_LOG_MANAGEMENT_REQUEST;
+
+//
+// VMCALL API Numbers
+//
+
+// API number convention: BIOS facing VMCALL interfaces have bit 16 clear
+#define STM_API_MAP_ADDRESS_RANGE 0x00000001
+#define STM_API_UNMAP_ADDRESS_RANGE 0x00000002
+#define STM_API_ADDRESS_LOOKUP 0x00000003
+#define STM_API_RETURN_FROM_PROTECTION_EXCEPTION 0x00000004
+
+// API number convention: MLE facing VMCALL interfaces have bit 16 set
+//
+// The STM configuration lifecycle is as follows:
+// 1. SENTER->SINIT->MLE: MLE begins execution with SMI disabled (masked).
+// 2. MLE invokes InitializeProtectionVMCALL() to prepare STM for setup of
+// initial protection profile. This is done on a single CPU and has global
+// effect.
+// 3. MLE invokes ProtectResourceVMCALL() to define the initial protection
+// profile. The protection profile is global across all CPUs.
+// 4. MLE invokes StartStmVMCALL() to enable the STM to begin receiving SMI
+// events. This must be done on every logical CPU.
+// 5. MLE may invoke ProtectResourceVMCALL() or UnProtectResourceVMCALL()
+// during runtime as many times as necessary.
+// 6. MLE invokes StopStmVMCALL() to disable the STM. SMI is again masked
+// following StopStmVMCALL().
+//
+#define STM_API_START 0x00010001
+#define STM_API_STOP 0x00010002
+#define STM_API_PROTECT_RESOURCE 0x00010003
+#define STM_API_UNPROTECT_RESOURCE 0x00010004
+#define STM_API_GET_BIOS_RESOURCES 0x00010005
+#define STM_API_MANAGE_VMCS_DATABASE 0x00010006
+#define STM_API_INITIALIZE_PROTECTION 0x00010007
+#define STM_API_MANAGE_EVENT_LOG 0x00010008
+
+//
+// Return codes
+//
+typedef uint32_t STM_STATUS;
+
+#define STM_SUCCESS 0x00000000
+#define SMM_SUCCESS 0x00000000
+// all error codes have bit 31 set
+// STM errors have bit 16 set
+#define ERROR_STM_SECURITY_VIOLATION 0x80010001
+#define ERROR_STM_CACHE_TYPE_NOT_SUPPORTED 0x80010002
+#define ERROR_STM_PAGE_NOT_FOUND 0x80010003
+#define ERROR_STM_BAD_CR3 0x80010004
+#define ERROR_STM_PHYSICAL_OVER_4G 0x80010005
+#define ERROR_STM_VIRTUAL_SPACE_TOO_SMALL 0x80010006
+#define ERROR_STM_UNPROTECTABLE_RESOURCE 0x80010007
+#define ERROR_STM_ALREADY_STARTED 0x80010008
+#define ERROR_STM_WITHOUT_SMX_UNSUPPORTED 0x80010009
+#define ERROR_STM_STOPPED 0x8001000A
+#define ERROR_STM_BUFFER_TOO_SMALL 0x8001000B
+#define ERROR_STM_INVALID_VMCS_DATABASE 0x8001000C
+#define ERROR_STM_MALFORMED_RESOURCE_LIST 0x8001000D
+#define ERROR_STM_INVALID_PAGECOUNT 0x8001000E
+#define ERROR_STM_LOG_ALLOCATED 0x8001000F
+#define ERROR_STM_LOG_NOT_ALLOCATED 0x80010010
+#define ERROR_STM_LOG_NOT_STOPPED 0x80010011
+#define ERROR_STM_LOG_NOT_STARTED 0x80010012
+#define ERROR_STM_RESERVED_BIT_SET 0x80010013
+#define ERROR_STM_NO_EVENTS_ENABLED 0x80010014
+#define ERROR_STM_OUT_OF_RESOURCES 0x80010015
+#define ERROR_STM_FUNCTION_NOT_SUPPORTED 0x80010016
+#define ERROR_STM_UNPROTECTABLE 0x80010017
+#define ERROR_STM_UNSUPPORTED_MSR_BIT 0x80010018
+#define ERROR_STM_UNSPECIFIED 0x8001FFFF
+
+// SMM errors have bit 17 set
+#define ERROR_SMM_BAD_BUFFER 0x80020001
+#define ERROR_SMM_INVALID_RSC 0x80020004
+#define ERROR_SMM_INVALID_BUFFER_SIZE 0x80020005
+#define ERROR_SMM_BUFFER_TOO_SHORT 0x80020006
+#define ERROR_SMM_INVALID_LIST 0x80020007
+#define ERROR_SMM_OUT_OF_MEMORY 0x80020008
+#define ERROR_SMM_AFTER_INIT 0x80020009
+#define ERROR_SMM_UNSPECIFIED 0x8002FFFF
+
+// Errors that apply to both have bits 15, 16, and 17 set
+#define ERROR_INVALID_API 0x80038001
+#define ERROR_INVALID_PARAMETER 0x80038002
+
+//
+// STM TXT.ERRORCODE codes
+//
+#define STM_CRASH_PROTECTION_EXCEPTION 0xC000F001
+#define STM_CRASH_PROTECTION_EXCEPTION_FAILURE 0xC000F002
+#define STM_CRASH_DOMAIN_DEGRADATION_FAILURE 0xC000F003
+#define STM_CRASH_BIOS_PANIC 0xC000E000
+
+typedef struct {
+ uint32_t EventSerialNumber;
+ uint16_t Type;
+ uint16_t Lock :1;
+ uint16_t Valid :1;
+ uint16_t ReadByMle :1;
+ uint16_t Wrapped :1;
+ uint16_t Reserved :12;
+} LOG_ENTRY_HEADER;
+
+typedef struct {
+ uint32_t Reserved;
+} ENTRY_EVT_LOG_STARTED;
+
+typedef struct {
+ uint32_t Reserved;
+} ENTRY_EVT_LOG_STOPPED;
+
+typedef struct {
+ uint32_t VmcallApiNumber;
+} ENTRY_EVT_LOG_INVALID_PARAM;
+
+typedef struct {
+ STM_RSC Resource;
+} ENTRY_EVT_LOG_HANDLED_PROTECTION_EXCEPTION;
+
+typedef struct {
+ STM_RSC Resource;
+} ENTRY_EVT_BIOS_ACCESS_UNCLAIMED_RSC;
+
+typedef struct {
+ STM_RSC Resource;
+} ENTRY_EVT_MLE_RSC_PROT_GRANTED;
+
+typedef struct {
+ STM_RSC Resource;
+} ENTRY_EVT_MLE_RSC_PROT_DENIED;
+
+typedef struct {
+ STM_RSC Resource;
+} ENTRY_EVT_MLE_RSC_UNPROT;
+
+typedef struct {
+ STM_RSC Resource;
+} ENTRY_EVT_MLE_RSC_UNPROT_ERROR;
+
+typedef struct {
+ uint64_t VmcsPhysPointer;
+ uint8_t ExpectedDomainType;
+ uint8_t DegradedDomainType;
+} ENTRY_EVT_MLE_DOMAIN_TYPE_DEGRADED;
+
+typedef union {
+ ENTRY_EVT_LOG_STARTED Started;
+ ENTRY_EVT_LOG_STOPPED Stopped;
+ ENTRY_EVT_LOG_INVALID_PARAM InvalidParam;
+ ENTRY_EVT_LOG_HANDLED_PROTECTION_EXCEPTION HandledProtectionException;
+ ENTRY_EVT_BIOS_ACCESS_UNCLAIMED_RSC BiosUnclaimedRsc;
+ ENTRY_EVT_MLE_RSC_PROT_GRANTED MleRscProtGranted;
+ ENTRY_EVT_MLE_RSC_PROT_DENIED MleRscProtDenied;
+ ENTRY_EVT_MLE_RSC_UNPROT MleRscUnprot;
+ ENTRY_EVT_MLE_RSC_UNPROT_ERROR MleRscUnprotError;
+ ENTRY_EVT_MLE_DOMAIN_TYPE_DEGRADED MleDomainTypeDegraded;
+} LOG_ENTRY_DATA;
+
+typedef struct {
+ LOG_ENTRY_HEADER Hdr;
+ LOG_ENTRY_DATA Data;
+} STM_LOG_ENTRY;
+
+#define STM_LOG_ENTRY_SIZE 256
+
+//
+//
+//
+#define STM_CONFIG_SMI_UNBLOCKING_BY_VMX_OFF 0x1
+
+//
+// TXT debug
+//
+#define SW_SMI_STM_ADD_RUNTIME_RESOURCES_SUB_FUNC 0
+#define SW_SMI_STM_READ_BIOS_RESOURCES_SUB_FUNC 1
+#define SW_SMI_STM_REPLACE_BIOS_RESOURCES_SUB_FUNC 2
+
+typedef struct {
+ uint32_t BufferSize;
+ uint32_t Reserved;
+ //uint8_t Data[];
+} TXT_BIOS_DEBUG;
+
+#pragma pack (pop)
+
+#endif
diff --git a/src/security/intel/stm/StmPlatformResource.c b/src/security/intel/stm/StmPlatformResource.c
new file mode 100644
index 0000000..ad8a69b
--- /dev/null
+++ b/src/security/intel/stm/StmPlatformResource.c
@@ -0,0 +1,259 @@
+/** @file
+ STM platform SMM resource
+
+ Copyright (c) 2015, Intel Corporation. All rights reserved.
+ This program and the accompanying materials are licensed and made
+ available under the terms and conditions of the BSD License which
+ accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <stdint.h>
+#include <security/intel/stm/StmApi.h>
+#include <security/intel/stm/SmmStm.h>
+#include <security/intel/stm/StmPlatformResource.h>
+
+#include <southbridge/intel/common/pmutil.h>
+#include <cpu/x86/msr.h>
+
+#define RDWR_ACCS 3
+#define FULL_ACCS 7
+
+uint32_t mMaxBus;
+uint32_t mTsegBase;
+uint32_t mTsegSize;
+uint16_t mPmBase;
+
+typedef union {
+ uint64_t uint64;
+ msr_t msr;
+} msr64_t;
+
+//uint64_t PciRead64 (UINTN Address);
+void ResourceInit(void);
+void FixupPciexResource(void);
+void AddSimpleResources(void);
+void AddMsrResources(void);
+
+//
+// Fixed memory ranges
+//
+
+//
+// TSEG memory!
+//
+STM_RSC_MEM_DESC RscTsegMemory = {
+ {MEM_RANGE, sizeof (STM_RSC_MEM_DESC)},
+ 0,
+ 0,
+ FULL_ACCS
+};
+//
+// Flash part
+//
+STM_RSC_MEM_DESC RscSpiMemory = {
+ {MEM_RANGE, sizeof (STM_RSC_MEM_DESC)},
+ 0xFE000000,
+ 0x01000000,
+ FULL_ACCS
+};
+//
+// ACPI
+//
+STM_RSC_IO_DESC RscPmIo = {
+ {IO_RANGE, sizeof (STM_RSC_IO_DESC)},
+ 0,
+ 128
+};
+
+//
+// PCIE MMIO
+//
+STM_RSC_MMIO_DESC RscPcieMmio = {
+ {MMIO_RANGE, sizeof (STM_RSC_MMIO_DESC)},
+ 0,
+ 0, // Length
+ RDWR_ACCS
+};
+//
+// Local APIC
+//
+STM_RSC_MMIO_DESC RscApicMmio = {
+ {MMIO_RANGE, sizeof (STM_RSC_MMIO_DESC)},
+ 0,
+ 0x400,
+ RDWR_ACCS
+};
+//
+// Software SMI
+//
+STM_RSC_TRAPPED_IO_DESC RscSwSmiTrapIo = {
+ {TRAPPED_IO_RANGE, sizeof (STM_RSC_TRAPPED_IO_DESC)},
+ 0xB2,
+ 2
+};
+//
+// End of list
+//
+STM_RSC_END RscListEnd = {
+ {END_OF_RESOURCES, sizeof (STM_RSC_END)},
+ 0
+};
+
+//
+// Common PCI devices
+//
+//
+// LPC bridge
+//
+STM_RSC_PCI_CFG_DESC RscLpcBridgePci = {
+ {PCI_CFG_RANGE, sizeof (STM_RSC_PCI_CFG_DESC)},
+ RDWR_ACCS, 0,
+ 0,
+ 0x1000,
+ 0,
+ 0,
+ {
+ {1, 1, sizeof(STM_PCI_DEVICE_PATH_NODE), LPC_FUNCTION, LPC_DEVICE},
+ },
+};
+
+//
+// Template for MSR resources.
+//
+STM_RSC_MSR_DESC RscMsrTpl = {
+ {MACHINE_SPECIFIC_REG, sizeof (STM_RSC_MSR_DESC)},
+};
+
+//
+// MSR indices to register
+//
+typedef struct {
+ uint32_t MsrIndex;
+ uint64_t ReadMask;
+ uint64_t WriteMask;
+} MSR_TABLE_ENTRY;
+
+MSR_TABLE_ENTRY MsrTable[] = {
+ // Index Read Write // MASK64 means need access, MASK0 means no need access.
+ {SMRR_PHYSBASE_MSR, MASK64, MASK0},
+ {SMRR_PHYSMASK_MSR, MASK64, MASK0},
+};
+
+/**
+
+ BIOS resources initialization.
+
+**/
+void ResourceInit(void)
+{
+ mMaxBus = 255;
+
+ msr_t MsrRead;
+
+ mPmBase = get_pmbase();
+
+ //mTsegBase = (uint32_t)rdmsr(SMRR_PHYSBASE_MSR) & 0xFFFFF000;
+
+ MsrRead = rdmsr(SMRR_PHYSBASE_MSR);
+ mTsegBase = MsrRead.lo & 0xFFFFF000;
+
+ //mTsegSize = (uint32_t)(~((uint32_t)rdmsr(SMRR_PHYSMASK_MSR) & 0xFFFFF000) + 1);
+
+ MsrRead = rdmsr(SMRR_PHYSMASK_MSR);
+ mTsegSize = (~(MsrRead.lo & 0xFFFFF000) + 1);
+}
+
+/**
+
+ Fix up PCIE resource.
+
+**/
+void FixupPciexResource(void)
+{
+ // bug, bug, need to fix for coreboot
+ //
+ // Find max bus number and PCIEX length
+ //
+ //RscPcieMmio.Length = 0x10000000; // 256 MB
+ //RscPcieMmio.Base = PcdGet64 (PcdPciExpressBaseAddress);
+}
+
+/**
+
+ Add basic resources to BIOS resource database.
+
+**/
+void
+AddSimpleResources(void)
+{
+ int Status;
+ msr64_t ReadMsr;
+
+ //
+ // Fix-up values
+ //
+ RscTsegMemory.Base = mTsegBase;
+ RscTsegMemory.Length = mTsegSize;
+
+ RscPmIo.Base = (uint16_t) mPmBase;
+
+ //
+ // Local APIC. We assume that all thteads are programmed identically
+ // despite that it is possible to have individual APIC address for
+ // each of the threads. If this is the case this programming should
+ // be corrected.
+ //
+ //RscApicMmio.Base = AsmReadMsr64 (IA32_APIC_BASE_MSR_INDEX) & 0xFFFFFF000ull;
+
+ ReadMsr.msr = rdmsr(IA32_APIC_BASE_MSR_INDEX);
+ RscApicMmio.Base = ReadMsr.uint64 & 0xFFFFFF000ull;
+
+ //
+ // PCIEX BAR
+ //
+ FixupPciexResource ();
+
+ Status = AddPiResource((void *) &RscTsegMemory, 0);
+ //ASSERT_EFI_ERROR (Status);
+ Status = AddPiResource((void *) &RscLpcBridgePci, 1);
+ //ASSERT_EFI_ERROR (Status);
+}
+
+/**
+
+ Add MSR resources to BIOS resource database.
+
+**/
+void AddMsrResources(void)
+{
+ uint32_t Status;
+ uint32_t Index;
+
+ for (Index = 0; Index < sizeof(MsrTable)/sizeof(MsrTable[0]); Index ++) {
+
+ RscMsrTpl.MsrIndex = (uint32_t) MsrTable[Index].MsrIndex;
+ RscMsrTpl.ReadMask = (uint64_t) MsrTable[Index].ReadMask;
+ RscMsrTpl.WriteMask = (uint64_t) MsrTable[Index].WriteMask;
+
+ Status = AddPiResource ((void *) &RscMsrTpl, 1);
+ }
+}
+
+/**
+
+ Add resources to BIOS resource database.
+
+**/
+void AddResourcesCmd(void)
+{
+ ResourceInit();
+
+ AddSimpleResources();
+
+ AddMsrResources();
+}
diff --git a/src/security/intel/stm/StmPlatformResource.h b/src/security/intel/stm/StmPlatformResource.h
new file mode 100644
index 0000000..e31e74b
--- /dev/null
+++ b/src/security/intel/stm/StmPlatformResource.h
@@ -0,0 +1,43 @@
+/** @file
+ STM platform SMM resource
+
+ Copyright (c) 2015, Intel Corporation. All rights reserved.
+ This program and the accompanying materials are licensed and made available
+ under the terms and conditions of the BSD License which accompanies this
+ distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _STM_PLATFORM_RESOURCE_H_
+#define _STM_PLATFORM_RESOURCE_H_
+
+#define MASK0 0
+#define MASK64 0xFFFFFFFFFFFFFFFFull
+
+//
+// LPC
+//
+#define LPC_BUS 0
+#define LPC_DEVICE 31
+#define LPC_FUNCTION 0
+#define R_ACPI_PM_BASE 0x40
+#define ACPI_PM_BASE_MASK 0xFFF8
+
+//
+// MSRs
+//
+#define IA32_APIC_BASE_MSR_INDEX 0x1B
+#define SMRR_PHYSBASE_MSR 0x1F2
+#define SMRR_PHYSMASK_MSR 0x1F3
+
+/**
+
+ Add resources to BIOS resource database.
+
+**/
+void AddResourcesCmd(void);
+#endif
diff --git a/src/security/intel/stm/StmPlatformSmm.c b/src/security/intel/stm/StmPlatformSmm.c
new file mode 100644
index 0000000..bd9cea5
--- /dev/null
+++ b/src/security/intel/stm/StmPlatformSmm.c
@@ -0,0 +1,128 @@
+/** @file
+ STM platform SMM API
+
+ Copyright (c) 2015, Intel Corporation. All rights reserved.
+ This program and the accompanying materials are licensed and made
+ available under the terms and conditions of the BSD License which
+ accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <security/intel/stm/StmApi.h>
+#include <security/intel/stm/SmmStm.h>
+#include <cpu/x86/smm.h>
+
+#include <stddef.h>
+#include <cbfs.h>
+#include <console/console.h>
+#include <lib.h>
+#include <stdint.h>
+
+int LoadStmImage(uint32_t mseg);
+
+extern bool StmCheckStmImage(void *StmImage, uint32_t StmImageSize);
+extern void StmGen4GPageTableIa32(uint32_t PageTableBase);
+extern void StmGen4GPageTableX64(uint32_t PageTableBase);
+
+/**
+ Load STM image.
+
+ @retval EFI_SUCCESS STM is loaded to MSEG
+ @retval EFI_BUFFER_TOO_SMALL MSEG is too small
+ @retval EFI_UNSUPPORTED MSEG is not enabled
+**/
+int LoadStmImage(uint32_t mseg)
+{
+ int Status;
+ void *MsegBase;
+ uint32_t StmBufferSize;
+ uint32_t StmImageSize;
+ bool StmStatus;
+
+ STM_HEADER *StmHeader;
+
+ //
+ // Extract STM image from FV
+ //
+ MsegBase = (void *) mseg;
+ StmBufferSize = CONFIG_MSEG_SIZE;
+ StmImageSize = 0;
+
+ memset((void *) MsegBase, 0, CONFIG_MSEG_SIZE); // clear the mseg
+
+ StmImageSize = cbfs_boot_load_file("stm.bin", MsegBase, StmBufferSize, CBFS_TYPE_RAW);
+ printk(BIOS_DEBUG, "STM loaded into mseg: 0x%08x size: %u \n", (uint32_t) MsegBase, StmImageSize); /* status is number of bytes loaded */
+
+ StmStatus = StmCheckStmImage(MsegBase, StmImageSize);
+
+ StmHeader = MsegBase;
+
+ StmGen4GPageTableX64 ((uint32_t)MsegBase + StmHeader->HwStmHdr.Cr3Offset);
+
+ // Debug stuff
+
+ printk(BIOS_DEBUG, "STM Header - Revision: 0x%08x Features: 0x%08x ... Cr3Offset: 0x%08x\n",
+ StmHeader->HwStmHdr.StmHeaderRevision,
+ StmHeader->HwStmHdr.MonitorFeatures,
+ StmHeader->HwStmHdr.Cr3Offset);
+ printk(BIOS_DEBUG, "STM Header - StaticImageSize: %d Cr3Location: 0x%08x \n",
+ StmHeader->SwStmHdr.StaticImageSize,
+ ((uint32_t) MsegBase + StmHeader->HwStmHdr.Cr3Offset));
+
+ Status = 0; // always return good for now
+
+ return Status;
+}
+
+struct descriptor
+{
+ uint16_t limit;
+ uintptr_t base;
+} __attribute__((packed));
+
+
+void ReadGdtr( struct descriptor *gdtr);
+
+void ReadGdtr( struct descriptor *gdtr)
+{
+ __asm__ __volatile__ (
+ "sgdt %0"
+ : "=m" (*gdtr)
+ );
+}
+
+void SetupSmmDescriptor(void *smbase, int32_t state_size, int32_t apic_id, int32_t entry32_off)
+{
+ struct descriptor Gdtr;
+
+ TXT_PROCESSOR_SMM_DESCRIPTOR * Psd;
+
+ Psd = smbase + SMM_PSD_OFFSET - (apic_id * state_size);
+
+ printk(BIOS_DEBUG, "Setting up Smm Descriptor - Smbase: %p Psd: %p\n", smbase, Psd);
+
+ memset(Psd, 0, sizeof(TXT_PROCESSOR_SMM_DESCRIPTOR));
+
+ memcpy(&Psd->Signature, TXT_PROCESSOR_SMM_DESCRIPTOR_SIGNATURE, 8);
+ Psd->SmmDescriptorVerMajor = TXT_PROCESSOR_SMM_DESCRIPTOR_VERSION_MAJOR;
+ Psd->SmmDescriptorVerMinor = TXT_PROCESSOR_SMM_DESCRIPTOR_VERSION_MINOR;
+ Psd->SmmSmiHandlerRip = (uint64_t)((uint32_t)smbase + SMM_ENTRY_OFFSET + entry32_off);
+ Psd->LocalApicId = apic_id;
+ Psd->Size = sizeof(TXT_PROCESSOR_SMM_DESCRIPTOR);
+ Psd->AcpiRsdp = 0;
+ Psd->BiosHwResourceRequirementsPtr = (uint64_t)((uint32_t)GetStmResource());
+ Psd->SmmCs = 0x8;
+ Psd->SmmDs = 0x10;
+ Psd->SmmSs = 0x10;
+ Psd->SmmOtherSegment = 0x10;
+ Psd->SmmTr = 0x18;
+
+ ReadGdtr(&Gdtr);
+
+ Psd->SmmGdtPtr = Gdtr.base;
+ Psd->SmmGdtSize = Gdtr.limit + 1; // the stm will subtract, so need to compensate
+}
--
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Gerrit-Branch: master
Gerrit-Change-Id: If4adcd92c341162630ce1ec357ffcf8a135785ec
Gerrit-Change-Number: 33234
Gerrit-PatchSet: 1
Gerrit-Owner: Name of user not set #1002358
Gerrit-MessageType: newchange
7 hours, 39 minutes
- 7
- 90
Change in ...coreboot[master]: Kconfig: Display a warning if the board is updated incorrectly
by Martin Roth (Code Review)
Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33641
Change subject: Kconfig: Display a warning if the board is updated incorrectly
......................................................................
Kconfig: Display a warning if the board is updated incorrectly
Even though we have a comment to run make distclean before switching
mainboards, people still ignore this and end up with confusing results.
To try to fix this, save the mainboard directory in a Kconfig symbol
that will not get updated when the mainboard gets changed. This allows
us to compare it to the actual mainboard directory which will be updated
when the platform changes and put up an obnoxious warning in the
mainboard directory. Add another warning in the main menu, because
the initial warning is probably going to be ignored. The main menu
points to some documentation on how to fix the problem.
Note that this will only catch issues going forward, and won't catch
any already saved config that has a problem.
Signed-off-by: Martin Roth <martinroth(a)chromium.org>
Change-Id: I2a1ccb62c7678f264015c87b9004be6a106f804a
---
A Documentation/getting_started/fix_dot_config.md
M src/Kconfig
M src/mainboard/Kconfig
3 files changed, 78 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/33641/1
diff --git a/Documentation/getting_started/fix_dot_config.md b/Documentation/getting_started/fix_dot_config.md
new file mode 100644
index 0000000..17d89d0
--- /dev/null
+++ b/Documentation/getting_started/fix_dot_config.md
@@ -0,0 +1,50 @@
+# How to repair your .config file
+
+## Overview
+Many people rely on a saved .config file for building their
+platform. This is reasonable, but can create unanticipated
+problems.
+
+## TLDR
+* Backup your .config: "cp .config .config_bak"
+* Create the defconfig file: "make savedefconfig"
+* Edit defconfig & delete unknown config lines: "vi defconfig"
+* To just get rid of the warning about a bad .config, remove
+* the CONFIG_MAINBOARD_CHECK line.
+* The SMBIOS lines are probably incorrect as well. The ROM size
+* is very suspect. Check the correct default for your platform.
+* Save the defconfig
+* Generate a new full config:
+* "make -B defconfig KBUILD_DEFCONFIG=defconfig"
+
+## defconfig or "Mini config"
+Instead of saving a "full" config, people should use a defconfig.
+This is just the changes from a default coreboot configuration
+file. It's significantly smaller, and when a new configuration option
+gets added, it just takes the default value for that option when
+expanded into a full .config.
+
+### Generating the defconfig file
+To create the defconfig file, run "make savedefconfig". By default
+this will generate the file in the root coreboot directory and call
+it "defconfig". If there was already a file named "defconfig", this
+will overwrite that file.
+
+### Contents of the defconfig file
+As the defconfig file contains just the differences between the
+platform and the default choices for the platform. For the current
+default platform, the defconfig can actually be an empty file.
+
+Typically the defconfig will contain at least 2 lines - a
+CONFIG_VENDOR_ line and a CONFIG_BOARD_ line. Again though, if you
+are building the default board for any particular vendor, that line
+may not be present.
+
+All additional lines in a defconfig file are options that the user
+has specifically chosen to update in their config.
+
+### Generating a .config from a defconfig
+To expand the defconfig so that can be used, run:
+ DFILE=defconfig; make -B defconfig KBUILD_DEFCONFIG=$DFILE
+
+You can point DFILE to any saved defconfig.
diff --git a/src/Kconfig b/src/Kconfig
index 72d826f..8eae329 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -16,6 +16,15 @@
mainmenu "coreboot configuration"
+if MAINBOARD_CHECK != MAINBOARD_DIR
+comment "***********************************************************************"
+comment "WARNING: Your config is using defaults from a different mainboard "
+comment "than you currently have set. We'd recommend that you delete your "
+comment ".config file and start over, but if you want to try to repair the "
+comment "file, see Documentation/getting_started/fix_dot_config.md "
+comment "***********************************************************************"
+endif
+
menu "General setup"
config COREBOOT_BUILD
@@ -1062,6 +1071,14 @@
mainboard code supports this. On supported Intel platforms this works
by changing the settings in the descriptor.bin file.
+config MAINBOARD_CHECK
+ string "Mainboard dir - Do not change manually"
+ default MAINBOARD_DIR
+ help
+ Check the platform. If this symbol doesn't match the currently
+ selected mainboard directory, give the user warnings that they're
+ probably doing something wrong.
+
endmenu
diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig
index c88d317..d9216a9 100644
--- a/src/mainboard/Kconfig
+++ b/src/mainboard/Kconfig
@@ -1,5 +1,16 @@
comment "Important: Run 'make distclean' before switching boards"
+if MAINBOARD_CHECK != MAINBOARD_DIR
+comment "***********************************************************************"
+comment "WARNING: Your config is using defaults from a different mainboard "
+comment "than you currently have set. We'd recommend that you delete your "
+comment ".config file and start over. "
+comment "* *"
+comment "If you ignore this warning and build anyway, you will almost certainly "
+comment "get a bad rom with undefined results. "
+comment "***********************************************************************"
+endif
+
choice
prompt "Mainboard vendor"
default VENDOR_EMULATION
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I2a1ccb62c7678f264015c87b9004be6a106f804a
Gerrit-Change-Number: 33641
Gerrit-PatchSet: 1
Gerrit-Owner: Martin Roth <martinroth(a)google.com>
Gerrit-MessageType: newchange
1 day, 7 hours
- 4
- 7
Change in ...coreboot[master]: Console: Allow console UART to be enabled without serial console
by Martin Roth (Code Review)
Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33380
Change subject: Console: Allow console UART to be enabled without serial console
......................................................................
Console: Allow console UART to be enabled without serial console
Currently, when we disable serial console, the serial console uart
remains uninitialized. This patch allows coreboot to still set up
the UART, even if we're not sending the console to it.
BUG=b:74392237
TEST=Verify UART still works, even with coreboot console disabled
Signed-off-by: Martin Roth <martinroth(a)chromium.org>
Change-Id: Ic0942634ab8a9fcafdc1ea099721c127202e9f9a
---
M src/console/Kconfig
M src/drivers/uart/Kconfig
M src/include/console/uart.h
3 files changed, 28 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/33380/1
diff --git a/src/console/Kconfig b/src/console/Kconfig
index 61ba667..da769d3 100644
--- a/src/console/Kconfig
+++ b/src/console/Kconfig
@@ -33,6 +33,7 @@
bool "Serial port console output"
default y
depends on DRIVERS_UART
+ select ENABLE_UART
help
Send coreboot debug output to a serial port.
@@ -47,7 +48,7 @@
specific UART has to be used (e.g. when the platform code
performs dangerous configurations).
-if CONSOLE_SERIAL
+if ENABLE_UART
comment "I/O mapped, 8250-compatible"
depends on DRIVERS_UART_8250IO
@@ -79,13 +80,13 @@
Map the COM port number to the respective I/O port.
comment "Serial port base address = 0x3f8"
-depends on UART_FOR_CONSOLE = 0
+depends on UART_FOR_CONSOLE = 0 && DRIVERS_UART_8250IO
comment "Serial port base address = 0x2f8"
-depends on UART_FOR_CONSOLE = 1
+depends on UART_FOR_CONSOLE = 1 && DRIVERS_UART_8250IO
comment "Serial port base address = 0x3e8"
-depends on UART_FOR_CONSOLE = 2
+depends on UART_FOR_CONSOLE = 2 && DRIVERS_UART_8250IO
comment "Serial port base address = 0x2e8"
-depends on UART_FOR_CONSOLE = 3
+depends on UART_FOR_CONSOLE = 3 && DRIVERS_UART_8250IO
config UART_OVERRIDE_BAUDRATE
boolean
@@ -156,7 +157,7 @@
default 3
depends on DRIVERS_UART_8250IO || DRIVERS_UART_8250MEM
-endif # CONSOLE_SERIAL
+endif # ENABLE_UART
config SPKMODEM
bool "spkmodem (console on speaker) console output"
diff --git a/src/drivers/uart/Kconfig b/src/drivers/uart/Kconfig
index 1f23a19..9b242fd 100644
--- a/src/drivers/uart/Kconfig
+++ b/src/drivers/uart/Kconfig
@@ -1,6 +1,21 @@
config DRIVERS_UART
bool
+config ENABLE_UART
+ def_bool n
+
+config ENABLE_UART_WITHOUT_CONSOLE
+ bool "Always configure primary UART"
+ depends on DRIVERS_UART
+ select ENABLE_UART
+ help
+ The primary UART has previously only been set up when the serial console
+ is enabled.
+ Selecting this choice will configure the console UART even if the serial
+ console is disabled.
+
+ Select the UART in the console menu
+
config DRIVERS_UART_8250IO
# FIXME: Shouldn't have a prompt, should default to n, and
# should be selected by boards that have it instead.
diff --git a/src/include/console/uart.h b/src/include/console/uart.h
index aed67c2..6bd88ae 100644
--- a/src/include/console/uart.h
+++ b/src/include/console/uart.h
@@ -67,11 +67,16 @@
(ENV_BOOTBLOCK || ENV_ROMSTAGE || ENV_RAMSTAGE || ENV_VERSTAGE || \
ENV_POSTCAR || (ENV_SMM && CONFIG(DEBUG_SMI))))
-#if __CONSOLE_SERIAL_ENABLE__
+#if CONFIG(ENABLE_UART)
static inline void __uart_init(void)
{
uart_init(CONFIG_UART_FOR_CONSOLE);
}
+#else
+static inline void __uart_init(void) {}
+#endif
+
+#if __CONSOLE_SERIAL_ENABLE__
static inline void __uart_tx_byte(u8 data)
{
uart_tx_byte(CONFIG_UART_FOR_CONSOLE, data);
@@ -81,7 +86,6 @@
uart_tx_flush(CONFIG_UART_FOR_CONSOLE);
}
#else
-static inline void __uart_init(void) {}
static inline void __uart_tx_byte(u8 data) {}
static inline void __uart_tx_flush(void) {}
#endif
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ic0942634ab8a9fcafdc1ea099721c127202e9f9a
Gerrit-Change-Number: 33380
Gerrit-PatchSet: 1
Gerrit-Owner: Martin Roth <martinroth(a)google.com>
Gerrit-MessageType: newchange
1 day, 7 hours
- 4
- 14
Change in ...coreboot[master]: Documentation: Update soc/intel/apollolake
by Patrick Rudolph (Code Review)
Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33740
Change subject: Documentation: Update soc/intel/apollolake
......................................................................
Documentation: Update soc/intel/apollolake
Explaing LBPs and how to disable dual partition mode.
Change-Id: I0b609f802d96aa90d0c1479ffeccf3aaaa70a85d
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M Documentation/soc/intel/apollolake/flash_layout.dia
M Documentation/soc/intel/apollolake/flash_layout.svg
A Documentation/soc/intel/apollolake/flash_layout2.dia
A Documentation/soc/intel/apollolake/flash_layout2.svg
M Documentation/soc/intel/apollolake/index.md
5 files changed, 272 insertions(+), 27 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/33740/1
diff --git a/Documentation/soc/intel/apollolake/flash_layout.dia b/Documentation/soc/intel/apollolake/flash_layout.dia
index 4ea5440..a329620 100644
--- a/Documentation/soc/intel/apollolake/flash_layout.dia
+++ b/Documentation/soc/intel/apollolake/flash_layout.dia
Binary files differ
diff --git a/Documentation/soc/intel/apollolake/flash_layout.svg b/Documentation/soc/intel/apollolake/flash_layout.svg
index 9322875..07b3a58 100644
--- a/Documentation/soc/intel/apollolake/flash_layout.svg
+++ b/Documentation/soc/intel/apollolake/flash_layout.svg
@@ -1,6 +1,6 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.0//EN" "http://www.w3.org/TR/2001/PR-SVG-20010719/DTD/svg10.dtd">
-<svg width="38cm" height="18cm" viewBox="118 98 744 344" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink">
+<svg width="38cm" height="19cm" viewBox="118 61 744 380" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink">
<g>
<rect style="fill: #ffffff" x="620" y="100" width="180" height="60"/>
<rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="620" y="100" width="180" height="60"/>
@@ -16,18 +16,18 @@
<tspan x="460" y="134.425">BIOS</tspan>
</text>
<g>
- <rect style="fill: #ffffff" x="240" y="100" width="60" height="60"/>
- <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="240" y="100" width="60" height="60"/>
+ <rect style="fill: #ffffff" x="227.633" y="99.4585" width="60" height="60"/>
+ <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="227.633" y="99.4585" width="60" height="60"/>
</g>
- <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="270" y="134.425">
- <tspan x="270" y="134.425">IFD</tspan>
+ <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="257.633" y="133.884">
+ <tspan x="257.633" y="133.884">IFD</tspan>
</text>
<g>
<rect style="fill: #ffffff" x="200" y="240" width="80" height="60"/>
<rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="200" y="240" width="80" height="60"/>
</g>
- <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="240" y="274.425">
- <tspan x="240" y="274.425">IFWI</tspan>
+ <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="240" y="274.238">
+ <tspan x="240" y="274.238">IFWI</tspan>
</text>
<g>
<path style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" d="M 200 240 C 200,160 460,220 460,169.736"/>
@@ -35,7 +35,7 @@
<polygon style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" points="460,162.236 465,172.236 460,169.736 455,172.236 "/>
</g>
<g>
- <path style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" d="M 700 240 C 700,160 460,220 460,169.736"/>
+ <path style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" d="M 700.289 239.999 C 700.289,159.999 460,220 460,169.736"/>
<polygon style="fill: #000000" points="460,162.236 465,172.236 460,169.736 455,172.236 "/>
<polygon style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" points="460,162.236 465,172.236 460,169.736 455,172.236 "/>
</g>
@@ -65,11 +65,11 @@
<tspan x="620" y="414.425">COREBOOT(CBFS)</tspan>
</text>
<g>
- <rect style="fill: #ffffff" x="700" y="380" width="140" height="60"/>
- <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="700" y="380" width="140" height="60"/>
+ <rect style="fill: #d8e5e5" x="495.265" y="102.433" width="122.658" height="54.6579"/>
+ <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="495.265" y="102.433" width="122.658" height="54.6579"/>
</g>
- <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="770" y="414.425">
- <tspan x="770" y="414.425">BIOS_UNUSABLE</tspan>
+ <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="556.594" y="134.187">
+ <tspan x="556.594" y="134.187">BIOS_UNUSABLE</tspan>
</text>
<g>
<rect style="fill: #ffffff" x="380" y="380" width="60" height="60"/>
@@ -79,21 +79,21 @@
<tspan x="410" y="414.425">MRC</tspan>
</text>
<g>
- <rect style="fill: #ffffff" x="280" y="240" width="420" height="60"/>
- <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="280" y="240" width="420" height="60"/>
+ <rect style="fill: #ffffff" x="280" y="240" width="420.151" height="60"/>
+ <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="280" y="240" width="420.151" height="60"/>
</g>
- <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="490" y="274.425">
- <tspan x="490" y="274.425">OBB</tspan>
+ <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="490.076" y="274.425">
+ <tspan x="490.076" y="274.425">OBB</tspan>
</text>
<g>
- <path style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" d="M 320 380 C 320,300 490,360 490,311"/>
- <polygon style="fill: #000000" points="495,311 490,301 485,311 "/>
- <polygon style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" points="495,311 490,301 485,311 "/>
+ <path style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" d="M 320 380 C 320,300 490.076,360 490.076,311"/>
+ <polygon style="fill: #000000" points="495.076,311 490.076,301 485.076,311 "/>
+ <polygon style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" points="495.076,311 490.076,301 485.076,311 "/>
</g>
<g>
- <path style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" d="M 840 380 C 840,300 490,360 490,311"/>
- <polygon style="fill: #000000" points="495,311 490,301 485,311 "/>
- <polygon style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" points="495,311 490,301 485,311 "/>
+ <path style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" d="M 728.771 380.768 C 728.771,300.768 490.076,360 490.076,311"/>
+ <polygon style="fill: #000000" points="495.076,311 490.076,301 485.076,311 "/>
+ <polygon style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" points="495.076,311 490.076,301 485.076,311 "/>
</g>
<g>
<rect style="fill: #ffffff" x="120" y="380" width="60" height="60"/>
@@ -119,4 +119,39 @@
<polygon style="fill: #000000" points="245,311 240,301 235,311 "/>
<polygon style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" points="245,311 240,301 235,311 "/>
</g>
+ <text font-size="12.7998" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="385.009" y="232.505">
+ <tspan x="385.009" y="232.505">Logical Boot Partition 1</tspan>
+ </text>
+ <text font-size="12.7998" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="644.3" y="90.55">
+ <tspan x="644.3" y="90.55">TXE private partition</tspan>
+ </text>
+ <text font-size="12.7998" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="768" y="77.25">
+ <tspan x="768" y="77.25"></tspan>
+ </text>
+ <text font-size="12.7998" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="739" y="77.25">
+ <tspan x="739" y="77.25"></tspan>
+ </text>
+ <text font-size="12.7998" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="389.3" y="90.55">
+ <tspan x="389.3" y="90.55">TXE / BIOS shared partition</tspan>
+ </text>
+ <g>
+ <rect style="fill: #ffffff" x="288.321" y="99.2493" width="11.6609" height="60"/>
+ <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="288.321" y="99.2493" width="11.6609" height="60"/>
+ </g>
+ <text font-size="12.7998" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="232.975" y="73.4916">
+ <tspan x="232.975" y="73.4916">ME region (unused)</tspan>
+ </text>
+ <g>
+ <line style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" x1="295.223" y1="77.2138" x2="295.229" y2="86.6145"/>
+ <polygon style="fill: #000000" points="295.234,94.1145 290.228,84.1176 295.229,86.6145 300.228,84.1113 "/>
+ <polygon style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" points="295.234,94.1145 290.228,84.1176 295.229,86.6145 300.228,84.1113 "/>
+ </g>
+ <g>
+ <rect style="fill: #d8e5e5" x="669.038" y="243.016" width="28.5491" height="54.6579"/>
+ <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="669.038" y="243.016" width="28.5491" height="54.6579"/>
+ </g>
+ <g>
+ <rect style="fill: #d8e5e5" x="700.222" y="380.768" width="28.5491" height="58.0215"/>
+ <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="700.222" y="380.768" width="28.5491" height="58.0215"/>
+ </g>
</svg>
diff --git a/Documentation/soc/intel/apollolake/flash_layout2.dia b/Documentation/soc/intel/apollolake/flash_layout2.dia
new file mode 100644
index 0000000..0bde2e5
--- /dev/null
+++ b/Documentation/soc/intel/apollolake/flash_layout2.dia
Binary files differ
diff --git a/Documentation/soc/intel/apollolake/flash_layout2.svg b/Documentation/soc/intel/apollolake/flash_layout2.svg
new file mode 100644
index 0000000..15c7a8d
--- /dev/null
+++ b/Documentation/soc/intel/apollolake/flash_layout2.svg
@@ -0,0 +1,171 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.0//EN" "http://www.w3.org/TR/2001/PR-SVG-20010719/DTD/svg10.dtd">
+<svg width="38cm" height="19cm" viewBox="118 61 744 380" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink">
+ <g>
+ <rect style="fill: #ffffff" x="620" y="100" width="180" height="60"/>
+ <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="620" y="100" width="180" height="60"/>
+ </g>
+ <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="710" y="134.425">
+ <tspan x="710" y="134.425">DEVICE_EXTENSION</tspan>
+ </text>
+ <g>
+ <rect style="fill: #ffffff" x="300" y="100" width="320" height="60"/>
+ <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="300" y="100" width="320" height="60"/>
+ </g>
+ <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="460" y="134.425">
+ <tspan x="460" y="134.425">BIOS</tspan>
+ </text>
+ <g>
+ <rect style="fill: #ffffff" x="227.632" y="99.4586" width="60" height="60"/>
+ <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="227.632" y="99.4586" width="60" height="60"/>
+ </g>
+ <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="257.632" y="133.884">
+ <tspan x="257.632" y="133.884">IFD</tspan>
+ </text>
+ <g>
+ <rect style="fill: #ffffff" x="200" y="240" width="80" height="60"/>
+ <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="200" y="240" width="80" height="60"/>
+ </g>
+ <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="240" y="274.425">
+ <tspan x="240" y="274.425">IFWI</tspan>
+ </text>
+ <g>
+ <path style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" d="M 200 240 C 200,160 460,220 460,169.736"/>
+ <polygon style="fill: #000000" points="460,162.236 465,172.236 460,169.736 455,172.236 "/>
+ <polygon style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" points="460,162.236 465,172.236 460,169.736 455,172.236 "/>
+ </g>
+ <g>
+ <path style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" d="M 700.288 240 C 700.288,159.999 460,220 460,169.736"/>
+ <polygon style="fill: #000000" points="460,162.236 465,172.236 460,169.736 455,172.236 "/>
+ <polygon style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" points="460,162.236 465,172.236 460,169.736 455,172.236 "/>
+ </g>
+ <g>
+ <rect style="fill: #ffffff" x="800" y="100" width="60" height="60"/>
+ <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="800" y="100" width="60" height="60"/>
+ </g>
+ <g>
+ <rect style="fill: #ffffff" x="320" y="380" width="60" height="60"/>
+ <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="320" y="380" width="60" height="60"/>
+ </g>
+ <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="350" y="414.425">
+ <tspan x="350" y="414.425">FMAP</tspan>
+ </text>
+ <g>
+ <rect style="fill: #ffffff" x="440" y="380" width="100" height="60"/>
+ <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="440" y="380" width="100" height="60"/>
+ </g>
+ <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="490" y="414.425">
+ <tspan x="490" y="414.425">CONSOLE</tspan>
+ </text>
+ <g>
+ <rect style="fill: #ffffff" x="540" y="380" width="160" height="60"/>
+ <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="540" y="380" width="160" height="60"/>
+ </g>
+ <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="620" y="414.425">
+ <tspan x="620" y="414.425">COREBOOT(CBFS)</tspan>
+ </text>
+ <g>
+ <rect style="fill: #d8e5e5" x="495.264" y="102.433" width="122.658" height="54.6579"/>
+ <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="495.264" y="102.433" width="122.658" height="54.6579"/>
+ </g>
+ <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="556.594" y="134.187">
+ <tspan x="556.594" y="134.187">BIOS_UNUSABLE</tspan>
+ </text>
+ <g>
+ <rect style="fill: #ffffff" x="380" y="380" width="60" height="60"/>
+ <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="380" y="380" width="60" height="60"/>
+ </g>
+ <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="410" y="414.425">
+ <tspan x="410" y="414.425">MRC</tspan>
+ </text>
+ <g>
+ <rect style="fill: #ffffff" x="280" y="240" width="161.104" height="60"/>
+ <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="280" y="240" width="161.104" height="60"/>
+ </g>
+ <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="360.552" y="274.425">
+ <tspan x="360.552" y="274.425">OBB</tspan>
+ </text>
+ <g>
+ <path style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" d="M 320 380 C 320,300 360.552,360 360.552,311"/>
+ <polygon style="fill: #000000" points="365.552,311 360.552,301 355.552,311 "/>
+ <polygon style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" points="365.552,311 360.552,301 355.552,311 "/>
+ </g>
+ <g>
+ <path style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" d="M 700 380 C 700,300 360.552,360 360.552,311"/>
+ <polygon style="fill: #000000" points="365.552,311 360.552,301 355.552,311 "/>
+ <polygon style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" points="365.552,311 360.552,301 355.552,311 "/>
+ </g>
+ <g>
+ <rect style="fill: #ffffff" x="120" y="380" width="60" height="60"/>
+ <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="120" y="380" width="60" height="60"/>
+ </g>
+ <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="150" y="414.425">
+ <tspan x="150" y="414.425">TXE</tspan>
+ </text>
+ <g>
+ <rect style="fill: #ffffff" x="180" y="380" width="120" height="60"/>
+ <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="180" y="380" width="120" height="60"/>
+ </g>
+ <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="240" y="414.425">
+ <tspan x="240" y="414.425">BOOTBLOCK</tspan>
+ </text>
+ <g>
+ <path style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" d="M 300 380 C 300,320 240,360 240,311"/>
+ <polygon style="fill: #000000" points="245,311 240,301 235,311 "/>
+ <polygon style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" points="245,311 240,301 235,311 "/>
+ </g>
+ <g>
+ <path style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" d="M 120 380 C 120,320 240,360 240,311"/>
+ <polygon style="fill: #000000" points="245,311 240,301 235,311 "/>
+ <polygon style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" points="245,311 240,301 235,311 "/>
+ </g>
+ <text font-size="12.8" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="247.944" y="231.664">
+ <tspan x="247.944" y="231.664">Logical Boot Partition 1</tspan>
+ </text>
+ <text font-size="12.8" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="644.3" y="90.55">
+ <tspan x="644.3" y="90.55">TXE private partition</tspan>
+ </text>
+ <text font-size="12.8" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="768" y="77.25">
+ <tspan x="768" y="77.25"></tspan>
+ </text>
+ <text font-size="12.8" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="739" y="77.25">
+ <tspan x="739" y="77.25"></tspan>
+ </text>
+ <text font-size="12.8" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="389.3" y="90.55">
+ <tspan x="389.3" y="90.55">TXE / BIOS shared partition</tspan>
+ </text>
+ <g>
+ <rect style="fill: #ffffff" x="288.32" y="99.2492" width="11.6609" height="60"/>
+ <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="288.32" y="99.2492" width="11.6609" height="60"/>
+ </g>
+ <text font-size="12.8" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="232.974" y="73.4916">
+ <tspan x="232.974" y="73.4916">ME region (unused)</tspan>
+ </text>
+ <g>
+ <line style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" x1="295.224" y1="77.2138" x2="295.23" y2="86.6145"/>
+ <polygon style="fill: #000000" points="295.235,94.1145 290.228,84.1177 295.23,86.6145 300.228,84.1114 "/>
+ <polygon style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" points="295.235,94.1145 290.228,84.1177 295.23,86.6145 300.228,84.1114 "/>
+ </g>
+ <g>
+ <rect style="fill: #ffffff" x="511.814" y="240" width="188.474" height="60"/>
+ <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="511.814" y="240" width="188.474" height="60"/>
+ </g>
+ <g>
+ <rect style="fill: #ffffff" x="440.696" y="240.49" width="71.1194" height="60"/>
+ <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="440.696" y="240.49" width="71.1194" height="60"/>
+ </g>
+ <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="606.052" y="274.425">
+ <tspan x="606.052" y="274.425">OBB</tspan>
+ </text>
+ <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="476.254" y="274.915">
+ <tspan x="476.254" y="274.915">IFWI</tspan>
+ </text>
+ <text font-size="12.8" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="493.642" y="231.092">
+ <tspan x="493.642" y="231.092">Logical Boot Partition 2</tspan>
+ </text>
+ <line style="fill: none; fill-opacity:0; stroke-width: 2; stroke-dasharray: 4; stroke: #000000" x1="439.69" y1="207.594" x2="440.696" y2="240.49"/>
+ <g>
+ <rect style="fill: #d8e5e5" x="668.7" y="241.9" width="28.5491" height="54.6579"/>
+ <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="668.7" y="241.9" width="28.5491" height="54.6579"/>
+ </g>
+</svg>
diff --git a/Documentation/soc/intel/apollolake/index.md b/Documentation/soc/intel/apollolake/index.md
index d4a5ee5..3ff0027 100644
--- a/Documentation/soc/intel/apollolake/index.md
+++ b/Documentation/soc/intel/apollolake/index.md
@@ -1,9 +1,7 @@
# Apollolake
-## SPI flash layout
-![][apl_flash_layout]
-
-With Apollolake Intel invented another flash layout for x86 firmware called IFWI (Intel FirmWare Image).
+With Apollolake Intel invented another flash layout for x86 firmware called
+IFWI (Intel FirmWare Image).
Usually on x86 platforms the bootblock is stored at the end of the bios region
and the Intel ME / TXE has its own IFD region. On Apollolake both have been
@@ -12,6 +10,47 @@
The IFWI region can be manipulated by `ifwitool`.
-[apl_flash_layout]: flash_layout.svg
+## SPI flash layout
+IFD regions:
+* The "ME" region isn't used on production boards
+* The "BIOS" region contains one or two logical boot partitions (LBP)
+ * The IFD controls if one or two LBP are active
+ * Each LBP has it's own IFWI and OBB
+ * The last 256 KiB of the "BIOS" region are BIOS_UNUSABLE
+* The "device extension" region is used by TXE as secure filesystem
+
+### SPI layout with single LBP
+
+When configured for single LBP mode, the LBP uses the whole "BIOS" region's
+flash size.
+
+![][apl_flash_layout]
+
+### SPI layout with dual LBP
+
+When configured for dual LBP mode, each LBP uses exactly half of the "BIOS"
+region's flash size.
+
+![][apl_flash_layout2]
+
+### IFWI
+
+The IFWI contains the bootblock, while the OBB contains the CBFS and other
+regions as specified in the FMAP.
+The OBB spans the whole size from IFWI till the end of the LBP.
+
+**Note:** ifwitool doesn't care about LBP2!
+
+### Logical boot partitions
+
+Each LBP has their own IFWI and OBB. It allows failsafe firmware updates.
+
+**Note:** If configured in dual partition mode, the TXE will enter recovery
+mode if LBP2 is missing.
+
+To disable dual partitioning mode, set bit3 in IFD at offset `0x1ff` to 1.
+
+[apl_flash_layout]: flash_layout.svg
+[apl_flash_layout2]: flash_layout2.svg
--
To view, visit https://review.coreboot.org/c/coreboot/+/33740
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I0b609f802d96aa90d0c1479ffeccf3aaaa70a85d
Gerrit-Change-Number: 33740
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Gerrit-MessageType: newchange
3 days, 14 hours
- 7
- 35
Change in ...coreboot[master]: superio/nsc: Use common defines for NSC PC8xxxx chips
by Peter Lemenkov (Code Review)
Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31427
Change subject: superio/nsc: Use common defines for NSC PC8xxxx chips
......................................................................
superio/nsc: Use common defines for NSC PC8xxxx chips
* Some common NSC defines moved to superio/nsc/common
* All NSC's pc8xxxx chips uses these common definitions
* Lenovo T60/X60/Z61t/T400 docking updated to use these common defines
* HP ProLiant DL165 G6 Fam10 updated to use this common code
Build tested - Lenovo T60/X60/Z61t/T400, HP ProLiant DL165 G6 Fam10
builds fine.
Change-Id: Iffdb4752f3075b1a1b391d4cf8d4416748bfe485
Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com>
---
M src/mainboard/hp/dl165_g6_fam10/romstage.c
M src/mainboard/lenovo/t400/dock.c
M src/mainboard/lenovo/t60/dock.c
M src/mainboard/lenovo/x60/dock.c
M src/mainboard/lenovo/z61t/dock.c
A src/superio/nsc/common/superio_defs.h
D src/superio/nsc/pc87309/pc87309.h
M src/superio/nsc/pc87309/superio.c
D src/superio/nsc/pc87360/pc87360.h
M src/superio/nsc/pc87360/superio.c
D src/superio/nsc/pc87366/pc87366.h
M src/superio/nsc/pc87366/superio.c
D src/superio/nsc/pc87382/pc87382.h
M src/superio/nsc/pc87382/superio.c
D src/superio/nsc/pc87384/pc87384.h
M src/superio/nsc/pc87384/superio.c
D src/superio/nsc/pc87392/pc87392.h
M src/superio/nsc/pc87392/superio.c
M src/superio/nsc/pc87417/pc87417.h
M src/superio/nsc/pc87417/superio.c
20 files changed, 219 insertions(+), 369 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/31427/1
diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c
index 6d2eed4..7f5411e 100644
--- a/src/mainboard/hp/dl165_g6_fam10/romstage.c
+++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c
@@ -34,6 +34,7 @@
#include <spd.h>
#include <delay.h>
#include <superio/serverengines/pilot/pilot.h>
+#include <superio/nsc/common/superio_defs.h>
#include <superio/nsc/pc87417/pc87417.h>
#include <cpu/x86/bist.h>
#include <cpu/amd/car.h>
@@ -50,7 +51,7 @@
#include "cpu/amd/quadcore/quadcore.c"
#define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1)
-#define RTC_DEV PNP_DEV(0x4e, PC87417_RTC)
+#define RTC_DEV PNP_DEV(0x4e, PC8XXXX_RTC)
void activate_spd_rom(const struct mem_controller *ctrl);
int spd_read_byte(unsigned int device, unsigned int address);
diff --git a/src/mainboard/lenovo/t400/dock.c b/src/mainboard/lenovo/t400/dock.c
index 6d1a80c..58788e7 100644
--- a/src/mainboard/lenovo/t400/dock.c
+++ b/src/mainboard/lenovo/t400/dock.c
@@ -23,7 +23,7 @@
#include <device/pnp.h>
#include <delay.h>
#include "dock.h"
-#include <superio/nsc/pc87382/pc87382.h>
+#include <superio/nsc/common/superio_defs.h>
#include <southbridge/intel/i82801ix/i82801ix.h>
#include <ec/lenovo/h8/h8.h>
@@ -64,8 +64,8 @@
return 0;
}
-static const pnp_devfn_t l_dlpc = PNP_DEV(0x164e, PC87382_DOCK);
-static const pnp_devfn_t l_gpio = PNP_DEV(0x164e, PC87382_GPIO);
+static const pnp_devfn_t l_dlpc = PNP_DEV(0x164e, PC8XXXX_DOCK);
+static const pnp_devfn_t l_gpio = PNP_DEV(0x164e, PC8XXXX_GPIO);
static int pc87382_init(pnp_devfn_t dlpc, u16 dlpc_base)
{
@@ -170,20 +170,18 @@
/* Docking station side. */
-#include <superio/nsc/pc87384/pc87384.h>
-
-static const pnp_devfn_t r_gpio = PNP_DEV(SUPERIO_DEV, PC87384_GPIO);
-static const pnp_devfn_t r_serial = PNP_DEV(SUPERIO_DEV, PC87384_SP1);
+static const pnp_devfn_t r_gpio = PNP_DEV(SUPERIO_DEV, PC8XXXX_GPIO);
+static const pnp_devfn_t r_serial = PNP_DEV(SUPERIO_DEV, PC8XXXX_SP1);
static const struct pin_config remote_gpio[] = {
- {0x00, PC87384_GPIO_PIN_DEBOUNCE | PC87384_GPIO_PIN_PULLUP},
- {0x01, PC87384_GPIO_PIN_TYPE_PUSH_PULL | PC87384_GPIO_PIN_OE},
- {0x02, PC87384_GPIO_PIN_TYPE_PUSH_PULL | PC87384_GPIO_PIN_OE},
- {0x03, PC87384_GPIO_PIN_DEBOUNCE | PC87384_GPIO_PIN_PULLUP},
- {0x04, PC87384_GPIO_PIN_DEBOUNCE | PC87384_GPIO_PIN_PULLUP},
- {0x05, PC87384_GPIO_PIN_DEBOUNCE | PC87384_GPIO_PIN_PULLUP},
- {0x06, PC87384_GPIO_PIN_DEBOUNCE | PC87384_GPIO_PIN_PULLUP},
- {0x07, PC87384_GPIO_PIN_DEBOUNCE | PC87384_GPIO_PIN_PULLUP},
+ {0x00, PC8XXXX_GPIO_PIN_DEBOUNCE | PC8XXXX_GPIO_PIN_PULLUP},
+ {0x01, PC8XXXX_GPIO_PIN_TYPE_PUSH_PULL | PC8XXXX_GPIO_PIN_OE},
+ {0x02, PC8XXXX_GPIO_PIN_TYPE_PUSH_PULL | PC8XXXX_GPIO_PIN_OE},
+ {0x03, PC8XXXX_GPIO_PIN_DEBOUNCE | PC8XXXX_GPIO_PIN_PULLUP},
+ {0x04, PC8XXXX_GPIO_PIN_DEBOUNCE | PC8XXXX_GPIO_PIN_PULLUP},
+ {0x05, PC8XXXX_GPIO_PIN_DEBOUNCE | PC8XXXX_GPIO_PIN_PULLUP},
+ {0x06, PC8XXXX_GPIO_PIN_DEBOUNCE | PC8XXXX_GPIO_PIN_PULLUP},
+ {0x07, PC8XXXX_GPIO_PIN_DEBOUNCE | PC8XXXX_GPIO_PIN_PULLUP},
};
static int pc87384_init(void)
diff --git a/src/mainboard/lenovo/t60/dock.c b/src/mainboard/lenovo/t60/dock.c
index 05dd65e..57a5a00 100644
--- a/src/mainboard/lenovo/t60/dock.c
+++ b/src/mainboard/lenovo/t60/dock.c
@@ -18,7 +18,7 @@
#include <arch/io.h>
#include <delay.h>
#include "dock.h"
-#include <superio/nsc/pc87384/pc87384.h>
+#include <superio/nsc/common/superio_defs.h>
#include "ec/acpi/ec.h"
#include "ec/lenovo/pmh7/pmh7.h"
#include <southbridge/intel/i82801gx/i82801gx.h>
@@ -128,38 +128,38 @@
dock_write_register(0x22, 0xa9);
/* enable serial port */
- dock_write_register(0x07, PC87384_SP1);
+ dock_write_register(0x07, PC8XXXX_SP1);
dock_write_register(0x30, 0x01);
- dock_write_register(0x07, PC87384_GPIO);
+ dock_write_register(0x07, PC8XXXX_GPIO);
dock_write_register(0x60, 0x16);
dock_write_register(0x61, 0x20);
/* enable GPIO */
dock_write_register(0x30, 0x01);
- dock_gpio_set_mode(0x00, PC87384_GPIO_PIN_DEBOUNCE |
- PC87384_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x00, PC8XXXX_GPIO_PIN_DEBOUNCE |
+ PC8XXXX_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x01, PC87384_GPIO_PIN_TYPE_PUSH_PULL |
- PC87384_GPIO_PIN_OE, 0x00);
+ dock_gpio_set_mode(0x01, PC8XXXX_GPIO_PIN_TYPE_PUSH_PULL |
+ PC8XXXX_GPIO_PIN_OE, 0x00);
- dock_gpio_set_mode(0x02, PC87384_GPIO_PIN_TYPE_PUSH_PULL |
- PC87384_GPIO_PIN_OE, 0x00);
+ dock_gpio_set_mode(0x02, PC8XXXX_GPIO_PIN_TYPE_PUSH_PULL |
+ PC8XXXX_GPIO_PIN_OE, 0x00);
- dock_gpio_set_mode(0x03, PC87384_GPIO_PIN_DEBOUNCE |
- PC87384_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x03, PC8XXXX_GPIO_PIN_DEBOUNCE |
+ PC8XXXX_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x04, PC87384_GPIO_PIN_DEBOUNCE |
- PC87384_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x04, PC8XXXX_GPIO_PIN_DEBOUNCE |
+ PC8XXXX_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x05, PC87384_GPIO_PIN_DEBOUNCE |
- PC87384_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x05, PC8XXXX_GPIO_PIN_DEBOUNCE |
+ PC8XXXX_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x06, PC87384_GPIO_PIN_DEBOUNCE |
- PC87384_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x06, PC8XXXX_GPIO_PIN_DEBOUNCE |
+ PC8XXXX_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x07, PC87384_GPIO_PIN_DEBOUNCE |
- PC87384_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x07, PC8XXXX_GPIO_PIN_DEBOUNCE |
+ PC8XXXX_GPIO_PIN_PULLUP, 0x00);
/* no GPIO events enabled for PORT0 */
diff --git a/src/mainboard/lenovo/x60/dock.c b/src/mainboard/lenovo/x60/dock.c
index b94d818..cf5e71d 100644
--- a/src/mainboard/lenovo/x60/dock.c
+++ b/src/mainboard/lenovo/x60/dock.c
@@ -20,7 +20,7 @@
#include <delay.h>
#include "dock.h"
#include <southbridge/intel/i82801gx/i82801gx.h>
-#include <superio/nsc/pc87392/pc87392.h>
+#include <superio/nsc/common/superio_defs.h>
static void dlpc_write_register(int reg, int value)
{
@@ -165,58 +165,58 @@
dock_write_register(0x61, 0x20);
/* init GPIO pins */
- dock_gpio_set_mode(0x00, PC87392_GPIO_PIN_DEBOUNCE |
- PC87392_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x00, PC8XXXX_GPIO_PIN_DEBOUNCE |
+ PC8XXXX_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x01, PC87392_GPIO_PIN_DEBOUNCE |
- PC87392_GPIO_PIN_PULLUP,
- PC87392_GPIO_PIN_TRIGGERS_SMI);
+ dock_gpio_set_mode(0x01, PC8XXXX_GPIO_PIN_DEBOUNCE |
+ PC8XXXX_GPIO_PIN_PULLUP,
+ PC8XXXX_GPIO_PIN_TRIGGERS_SMI);
- dock_gpio_set_mode(0x02, PC87392_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x03, PC87392_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x04, PC87392_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x05, PC87392_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x06, PC87392_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x07, PC87392_GPIO_PIN_PULLUP, 0x02);
+ dock_gpio_set_mode(0x02, PC8XXXX_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x03, PC8XXXX_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x04, PC8XXXX_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x05, PC8XXXX_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x06, PC8XXXX_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x07, PC8XXXX_GPIO_PIN_PULLUP, 0x02);
- dock_gpio_set_mode(0x10, PC87392_GPIO_PIN_DEBOUNCE |
- PC87392_GPIO_PIN_PULLUP,
- PC87392_GPIO_PIN_TRIGGERS_SMI);
+ dock_gpio_set_mode(0x10, PC8XXXX_GPIO_PIN_DEBOUNCE |
+ PC8XXXX_GPIO_PIN_PULLUP,
+ PC8XXXX_GPIO_PIN_TRIGGERS_SMI);
- dock_gpio_set_mode(0x11, PC87392_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x12, PC87392_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x13, PC87392_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x14, PC87392_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x15, PC87392_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x16, PC87392_GPIO_PIN_PULLUP |
- PC87392_GPIO_PIN_OE, 0x00);
+ dock_gpio_set_mode(0x11, PC8XXXX_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x12, PC8XXXX_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x13, PC8XXXX_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x14, PC8XXXX_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x15, PC8XXXX_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x16, PC8XXXX_GPIO_PIN_PULLUP |
+ PC8XXXX_GPIO_PIN_OE, 0x00);
- dock_gpio_set_mode(0x17, PC87392_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x17, PC8XXXX_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x20, PC87392_GPIO_PIN_TYPE_PUSH_PULL |
- PC87392_GPIO_PIN_OE, 0x00);
+ dock_gpio_set_mode(0x20, PC8XXXX_GPIO_PIN_TYPE_PUSH_PULL |
+ PC8XXXX_GPIO_PIN_OE, 0x00);
- dock_gpio_set_mode(0x21, PC87392_GPIO_PIN_TYPE_PUSH_PULL |
- PC87392_GPIO_PIN_OE, 0x00);
+ dock_gpio_set_mode(0x21, PC8XXXX_GPIO_PIN_TYPE_PUSH_PULL |
+ PC8XXXX_GPIO_PIN_OE, 0x00);
- dock_gpio_set_mode(0x22, PC87392_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x23, PC87392_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x24, PC87392_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x25, PC87392_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x26, PC87392_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x27, PC87392_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x22, PC8XXXX_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x23, PC8XXXX_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x24, PC8XXXX_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x25, PC8XXXX_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x26, PC8XXXX_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x27, PC8XXXX_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x30, PC87392_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x31, PC87392_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x32, PC87392_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x33, PC87392_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x34, PC87392_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x30, PC8XXXX_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x31, PC8XXXX_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x32, PC8XXXX_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x33, PC8XXXX_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x34, PC8XXXX_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x35, PC87392_GPIO_PIN_PULLUP |
- PC87392_GPIO_PIN_OE, 0x00);
+ dock_gpio_set_mode(0x35, PC8XXXX_GPIO_PIN_PULLUP |
+ PC8XXXX_GPIO_PIN_OE, 0x00);
- dock_gpio_set_mode(0x36, PC87392_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x37, PC87392_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x36, PC8XXXX_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x37, PC8XXXX_GPIO_PIN_PULLUP, 0x00);
/* enable GPIO */
dock_write_register(0x30, 0x01);
diff --git a/src/mainboard/lenovo/z61t/dock.c b/src/mainboard/lenovo/z61t/dock.c
index 05dd65e..57a5a00 100644
--- a/src/mainboard/lenovo/z61t/dock.c
+++ b/src/mainboard/lenovo/z61t/dock.c
@@ -18,7 +18,7 @@
#include <arch/io.h>
#include <delay.h>
#include "dock.h"
-#include <superio/nsc/pc87384/pc87384.h>
+#include <superio/nsc/common/superio_defs.h>
#include "ec/acpi/ec.h"
#include "ec/lenovo/pmh7/pmh7.h"
#include <southbridge/intel/i82801gx/i82801gx.h>
@@ -128,38 +128,38 @@
dock_write_register(0x22, 0xa9);
/* enable serial port */
- dock_write_register(0x07, PC87384_SP1);
+ dock_write_register(0x07, PC8XXXX_SP1);
dock_write_register(0x30, 0x01);
- dock_write_register(0x07, PC87384_GPIO);
+ dock_write_register(0x07, PC8XXXX_GPIO);
dock_write_register(0x60, 0x16);
dock_write_register(0x61, 0x20);
/* enable GPIO */
dock_write_register(0x30, 0x01);
- dock_gpio_set_mode(0x00, PC87384_GPIO_PIN_DEBOUNCE |
- PC87384_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x00, PC8XXXX_GPIO_PIN_DEBOUNCE |
+ PC8XXXX_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x01, PC87384_GPIO_PIN_TYPE_PUSH_PULL |
- PC87384_GPIO_PIN_OE, 0x00);
+ dock_gpio_set_mode(0x01, PC8XXXX_GPIO_PIN_TYPE_PUSH_PULL |
+ PC8XXXX_GPIO_PIN_OE, 0x00);
- dock_gpio_set_mode(0x02, PC87384_GPIO_PIN_TYPE_PUSH_PULL |
- PC87384_GPIO_PIN_OE, 0x00);
+ dock_gpio_set_mode(0x02, PC8XXXX_GPIO_PIN_TYPE_PUSH_PULL |
+ PC8XXXX_GPIO_PIN_OE, 0x00);
- dock_gpio_set_mode(0x03, PC87384_GPIO_PIN_DEBOUNCE |
- PC87384_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x03, PC8XXXX_GPIO_PIN_DEBOUNCE |
+ PC8XXXX_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x04, PC87384_GPIO_PIN_DEBOUNCE |
- PC87384_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x04, PC8XXXX_GPIO_PIN_DEBOUNCE |
+ PC8XXXX_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x05, PC87384_GPIO_PIN_DEBOUNCE |
- PC87384_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x05, PC8XXXX_GPIO_PIN_DEBOUNCE |
+ PC8XXXX_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x06, PC87384_GPIO_PIN_DEBOUNCE |
- PC87384_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x06, PC8XXXX_GPIO_PIN_DEBOUNCE |
+ PC8XXXX_GPIO_PIN_PULLUP, 0x00);
- dock_gpio_set_mode(0x07, PC87384_GPIO_PIN_DEBOUNCE |
- PC87384_GPIO_PIN_PULLUP, 0x00);
+ dock_gpio_set_mode(0x07, PC8XXXX_GPIO_PIN_DEBOUNCE |
+ PC8XXXX_GPIO_PIN_PULLUP, 0x00);
/* no GPIO events enabled for PORT0 */
diff --git a/src/superio/nsc/common/superio_defs.h b/src/superio/nsc/common/superio_defs.h
new file mode 100644
index 0000000..cc35508
--- /dev/null
+++ b/src/superio/nsc/common/superio_defs.h
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2000 AG Electronics Ltd.
+ * Copyright (C) 2003-2004 Linux Networx
+ * Copyright (C) 2004 Tyan
+ * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de>
+ * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SUPERIO_NSC_COMMON_SUPERIO_DEFS_H
+#define SUPERIO_NSC_COMMON_SUPERIO_DEFS_H
+
+#define PC8XXXX_FDC 0x00 /* Floppy */
+#define PC8XXXX_PP 0x01 /* Parallel port */
+#define PC8XXXX_SP2 0x02 /* COM 2 / IR */
+#define PC8XXXX_SP1 0x03 /* COM 1 */
+#define PC8XXXX_SWC 0x04 /* System wakeup control */
+//#define PC8XXXX_PM 0x04 /* Power management */
+#define PC8XXXX_KBCM 0x05 /* Mouse */
+#define PC8XXXX_KBCK 0x06 /* Keyboard */
+#define PC8XXXX_GPIO 0x07 /* General purpose IO */
+//#define PC8XXXX_HM 0x08
+#define PC8XXXX_FSD 0x08 /* Fan speed device */
+#define PC8XXXX_ACB 0x08
+#define PC8XXXX_FSCM 0x09
+#define PC8XXXX_FMC 0x09
+#define PC8XXXX_WDT 0x0A
+#define PC8XXXX_GMP 0x0B
+#define PC8XXXX_MIDI 0x0C
+#define PC8XXXX_VLM 0x0D
+#define PC8XXXX_TMS 0x0E
+#define PC8XXXX_XBUS 0x0F
+#define PC8XXXX_RTC 0x10
+#define PC8XXXX_MHC 0x14
+#define PC8XXXX_DOCK 0x19
+
+#define PC8XXXX_GPIO_PIN_OE 0x01
+#define PC8XXXX_GPIO_PIN_TYPE_PUSH_PULL 0x02
+#define PC8XXXX_GPIO_PIN_PULLUP 0x04
+#define PC8XXXX_GPIO_PIN_LOCK 0x08
+#define PC8XXXX_GPIO_PIN_TRIG_LEVEL 0x10
+#define PC8XXXX_GPIO_PIN_TRIG_LOW 0x20
+#define PC8XXXX_GPIO_PIN_DEBOUNCE 0x40
+
+#define PC8XXXX_GPIO_PIN_TRIGGERS_IRQ 0x01
+#define PC8XXXX_GPIO_PIN_TRIGGERS_SMI 0x02
+
+#endif /* SUPERIO_NSC_COMMON_SUPERIO_DEFS_H */
diff --git a/src/superio/nsc/pc87309/pc87309.h b/src/superio/nsc/pc87309/pc87309.h
deleted file mode 100644
index 3b912ea..0000000
--- a/src/superio/nsc/pc87309/pc87309.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef SUPERIO_NSC_PC87309_H
-#define SUPERIO_NSC_PC87309_H
-
-/* Datasheet: PC87309 SuperI/O Plug and Play Compatible Chip. */
-
-#define PC87309_FDC 0x00 /* Floppy */
-#define PC87309_PP 0x01 /* Parallel port */
-#define PC87309_SP2 0x02 /* Com2 / IR */
-#define PC87309_SP1 0x03 /* Com1 */
-#define PC87309_PM 0x04 /* Power management */
-#define PC87309_KBCM 0x05 /* Mouse */
-#define PC87309_KBCK 0x06 /* Keyboard */
-
-#endif /* SUPERIO_NSC_PC87309_H */
diff --git a/src/superio/nsc/pc87309/superio.c b/src/superio/nsc/pc87309/superio.c
index 458c501..f63bea9 100644
--- a/src/superio/nsc/pc87309/superio.c
+++ b/src/superio/nsc/pc87309/superio.c
@@ -19,7 +19,7 @@
#include <device/pnp.h>
#include <pc80/keyboard.h>
#include <stdlib.h>
-#include "pc87309.h"
+#include <superio/nsc/common/superio_defs.h>
static void init(struct device *dev)
{
@@ -28,7 +28,7 @@
return;
switch (dev->path.pnp.device) {
- case PC87309_KBCK:
+ case PC8XXXX_KBCK:
pc_keyboard_init(NO_AUX_DEVICE);
break;
}
@@ -43,14 +43,14 @@
};
static struct pnp_info pnp_dev_info[] = {
- { NULL, PC87309_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
- { NULL, PC87309_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
- { NULL, PC87309_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1,
+ { NULL, PC8XXXX_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
+ { NULL, PC8XXXX_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
+ { NULL, PC8XXXX_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1,
0x07f8, },
- { NULL, PC87309_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
+ { NULL, PC8XXXX_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
/* TODO: PM. */
- { NULL, PC87309_KBCM, PNP_IRQ0, },
- { NULL, PC87309_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x7f8, },
+ { NULL, PC8XXXX_KBCM, PNP_IRQ0, },
+ { NULL, PC8XXXX_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x7f8, },
};
static void enable_dev(struct device *dev)
diff --git a/src/superio/nsc/pc87360/pc87360.h b/src/superio/nsc/pc87360/pc87360.h
deleted file mode 100644
index c969746..0000000
--- a/src/superio/nsc/pc87360/pc87360.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000 AG Electronics Ltd.
- * Copyright (C) 2003-2004 Linux Networx
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef SUPERIO_NSC_PC87360_H
-#define SUPERIO_NSC_PC87360_H
-
-#define PC87360_FDC 0x00 /* Floppy */
-#define PC87360_PP 0x01 /* Parallel port */
-#define PC87360_SP2 0x02 /* Com2 */
-#define PC87360_SP1 0x03 /* Com1 */
-#define PC87360_SWC 0x04
-#define PC87360_KBCM 0x05 /* Mouse */
-#define PC87360_KBCK 0x06 /* Keyboard */
-#define PC87360_GPIO 0x07
-#define PC87360_ACB 0x08
-#define PC87360_FSCM 0x09
-#define PC87360_WDT 0x0A
-
-#endif /* SUPERIO_NSC_PC87360_H */
diff --git a/src/superio/nsc/pc87360/superio.c b/src/superio/nsc/pc87360/superio.c
index cf5c7ca..85f21a2 100644
--- a/src/superio/nsc/pc87360/superio.c
+++ b/src/superio/nsc/pc87360/superio.c
@@ -21,7 +21,7 @@
#include <string.h>
#include <pc80/keyboard.h>
#include <stdlib.h>
-#include "pc87360.h"
+#include <superio/nsc/common/superio_defs.h>
static void init(struct device *dev)
{
@@ -29,7 +29,7 @@
return;
switch (dev->path.pnp.device) {
- case PC87360_KBCK:
+ case PC8XXXX_KBCK:
pc_keyboard_init(NO_AUX_DEVICE);
break;
}
@@ -44,18 +44,18 @@
};
static struct pnp_info pnp_dev_info[] = {
- { NULL, PC87360_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
- { NULL, PC87360_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
- { NULL, PC87360_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1,
+ { NULL, PC8XXXX_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
+ { NULL, PC8XXXX_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
+ { NULL, PC8XXXX_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1,
0x07f8, },
- { NULL, PC87360_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
- { NULL, PC87360_SWC, PNP_IO0 | PNP_IRQ0, 0xfff0, },
- { NULL, PC87360_KBCM, PNP_IRQ0, },
- { NULL, PC87360_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, },
- { NULL, PC87360_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8, },
- { NULL, PC87360_ACB, PNP_IO0 | PNP_IRQ0, 0xfff8, },
- { NULL, PC87360_FSCM, PNP_IO0 | PNP_IRQ0, 0xfff8, },
- { NULL, PC87360_WDT, PNP_IO0 | PNP_IRQ0, 0xfffc, },
+ { NULL, PC8XXXX_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
+ { NULL, PC8XXXX_SWC, PNP_IO0 | PNP_IRQ0, 0xfff0, },
+ { NULL, PC8XXXX_KBCM, PNP_IRQ0, },
+ { NULL, PC8XXXX_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, },
+ { NULL, PC8XXXX_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8, },
+ { NULL, PC8XXXX_ACB, PNP_IO0 | PNP_IRQ0, 0xfff8, },
+ { NULL, PC8XXXX_FSCM, PNP_IO0 | PNP_IRQ0, 0xfff8, },
+ { NULL, PC8XXXX_WDT, PNP_IO0 | PNP_IRQ0, 0xfffc, },
};
static void enable_dev(struct device *dev)
diff --git a/src/superio/nsc/pc87366/pc87366.h b/src/superio/nsc/pc87366/pc87366.h
deleted file mode 100644
index b1df69f..0000000
--- a/src/superio/nsc/pc87366/pc87366.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000 AG Electronics Ltd.
- * Copyright (C) 2003-2004 Linux Networx
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef SUPERIO_NSC_PC87366_H
-#define SUPERIO_NSC_PC87366_H
-
-#define PC87366_FDC 0x00 /* Floppy */
-#define PC87366_PP 0x01 /* Parallel port */
-#define PC87366_SP2 0x02 /* Com2 */
-#define PC87366_SP1 0x03 /* Com1 */
-#define PC87366_SWC 0x04
-#define PC87366_KBCM 0x05 /* Mouse */
-#define PC87366_KBCK 0x06 /* Keyboard */
-#define PC87366_GPIO 0x07
-#define PC87366_ACB 0x08
-#define PC87366_FSCM 0x09
-#define PC87366_WDT 0x0A
-#define PC87366_GMP 0x0b
-#define PC87366_MIDI 0x0C
-#define PC87366_VLM 0x0D
-#define PC87366_TMS 0x0E
-
-#endif /* SUPERIO_NSC_PC87366_H */
diff --git a/src/superio/nsc/pc87366/superio.c b/src/superio/nsc/pc87366/superio.c
index e1cba17..60e5e23 100644
--- a/src/superio/nsc/pc87366/superio.c
+++ b/src/superio/nsc/pc87366/superio.c
@@ -21,7 +21,7 @@
#include <string.h>
#include <pc80/keyboard.h>
#include <stdlib.h>
-#include "pc87366.h"
+#include <superio/nsc/common/superio_defs.h>
static void init(struct device *dev)
{
@@ -29,7 +29,7 @@
return;
switch (dev->path.pnp.device) {
- case PC87366_KBCK:
+ case PC8XXXX_KBCK:
pc_keyboard_init(NO_AUX_DEVICE);
break;
}
@@ -44,18 +44,18 @@
};
static struct pnp_info pnp_dev_info[] = {
- { NULL, PC87366_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
- { NULL, PC87366_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
- { NULL, PC87366_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1,
+ { NULL, PC8XXXX_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
+ { NULL, PC8XXXX_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
+ { NULL, PC8XXXX_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1,
0x07f8, },
- { NULL, PC87366_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
- { NULL, PC87366_SWC, PNP_IO0 | PNP_IRQ0, 0xfff0, },
- { NULL, PC87366_KBCM, PNP_IRQ0, },
- { NULL, PC87366_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, },
- { NULL, PC87366_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8, },
- { NULL, PC87366_ACB, PNP_IO0 | PNP_IRQ0, 0xfff8, },
- { NULL, PC87366_FSCM, PNP_IO0 | PNP_IRQ0, 0xfff8, },
- { NULL, PC87366_WDT, PNP_IO0 | PNP_IRQ0, 0xfffc, },
+ { NULL, PC8XXXX_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
+ { NULL, PC8XXXX_SWC, PNP_IO0 | PNP_IRQ0, 0xfff0, },
+ { NULL, PC8XXXX_KBCM, PNP_IRQ0, },
+ { NULL, PC8XXXX_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, },
+ { NULL, PC8XXXX_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8, },
+ { NULL, PC8XXXX_ACB, PNP_IO0 | PNP_IRQ0, 0xfff8, },
+ { NULL, PC8XXXX_FSCM, PNP_IO0 | PNP_IRQ0, 0xfff8, },
+ { NULL, PC8XXXX_WDT, PNP_IO0 | PNP_IRQ0, 0xfffc, },
};
static void enable_dev(struct device *dev)
diff --git a/src/superio/nsc/pc87382/pc87382.h b/src/superio/nsc/pc87382/pc87382.h
deleted file mode 100644
index 6826f45..0000000
--- a/src/superio/nsc/pc87382/pc87382.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef SUPERIO_NSC_PC87382_H
-#define SUPERIO_NSC_PC87382_H
-
-#define PC87382_IR 0x02
-#define PC87382_SP1 0x03
-#define PC87382_GPIO 0x07
-#define PC87382_DOCK 0x19
-#endif
diff --git a/src/superio/nsc/pc87382/superio.c b/src/superio/nsc/pc87382/superio.c
index 688f08c..6a21f51 100644
--- a/src/superio/nsc/pc87382/superio.c
+++ b/src/superio/nsc/pc87382/superio.c
@@ -19,7 +19,7 @@
#include <device/pnp.h>
#include <string.h>
#include <stdlib.h>
-#include "pc87382.h"
+#include <superio/nsc/common/superio_defs.h>
static void init(struct device *dev)
{
@@ -27,10 +27,10 @@
return;
switch (dev->path.pnp.device) {
- case PC87382_DOCK:
+ case PC8XXXX_DOCK:
break;
- case PC87382_GPIO:
+ case PC8XXXX_GPIO:
break;
}
}
@@ -44,11 +44,11 @@
};
static struct pnp_info pnp_dev_info[] = {
- { NULL, PC87382_IR, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1,
+ { NULL, PC8XXXX_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1,
0x07f8 },
- { NULL, PC87382_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8 },
- { NULL, PC87382_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff0 },
- { NULL, PC87382_DOCK, PNP_IO0 | PNP_IRQ0, 0xfffe },
+ { NULL, PC8XXXX_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8 },
+ { NULL, PC8XXXX_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff0 },
+ { NULL, PC8XXXX_DOCK, PNP_IO0 | PNP_IRQ0, 0xfffe },
};
static void enable_dev(struct device *dev)
diff --git a/src/superio/nsc/pc87384/pc87384.h b/src/superio/nsc/pc87384/pc87384.h
deleted file mode 100644
index 2184584..0000000
--- a/src/superio/nsc/pc87384/pc87384.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef SUPERIO_NSC_PC87384_H
-#define SUPERIO_NSC_PC87384_H
-
-#define PC87384_PP 0x01
-#define PC87384_SP2 0x02
-#define PC87384_SP1 0x03
-#define PC87384_GPIO 0x07
-
-#define PC87384_GPIO_PIN_OE 0x01
-#define PC87384_GPIO_PIN_TYPE_PUSH_PULL 0x02
-#define PC87384_GPIO_PIN_PULLUP 0x04
-#define PC87384_GPIO_PIN_LOCK 0x08
-#define PC87384_GPIO_PIN_TRIG_LEVEL 0x10
-#define PC87384_GPIO_PIN_TRIG_LOW 0x20
-#define PC87384_GPIO_PIN_DEBOUNCE 0x40
-
-#define PC87384_GPIO_PIN_TRIGGERS_IRQ 0x01
-
-#endif
diff --git a/src/superio/nsc/pc87384/superio.c b/src/superio/nsc/pc87384/superio.c
index f34acd5..9548d2c 100644
--- a/src/superio/nsc/pc87384/superio.c
+++ b/src/superio/nsc/pc87384/superio.c
@@ -19,7 +19,7 @@
#include <device/pnp.h>
#include <string.h>
#include <stdlib.h>
-#include "pc87384.h"
+#include <superio/nsc/common/superio_defs.h>
static struct device_operations ops = {
.read_resources = pnp_read_resources,
@@ -29,10 +29,10 @@
};
static struct pnp_info pnp_dev_info[] = {
- { NULL, PC87384_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8 },
- { NULL, PC87384_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8 },
- { NULL, PC87384_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8 },
- { NULL, PC87384_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff0 },
+ { NULL, PC8XXXX_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8 },
+ { NULL, PC8XXXX_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8 },
+ { NULL, PC8XXXX_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8 },
+ { NULL, PC8XXXX_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff0 },
};
static void enable_dev(struct device *dev)
diff --git a/src/superio/nsc/pc87392/pc87392.h b/src/superio/nsc/pc87392/pc87392.h
deleted file mode 100644
index 5832435..0000000
--- a/src/superio/nsc/pc87392/pc87392.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef SUPERIO_NSC_PC87392_H
-#define SUPERIO_NSC_PC87392_H
-
-#define PC87392_FDC 0x00
-#define PC87392_PP 0x01
-#define PC87392_SP2 0x02
-#define PC87392_SP1 0x03
-#define PC87392_GPIO 0x07
-#define PC87392_WDT 0x0A
-
-#define PC87392_GPIO_PIN_OE 0x01
-#define PC87392_GPIO_PIN_TYPE_PUSH_PULL 0x02
-#define PC87392_GPIO_PIN_PULLUP 0x04
-#define PC87392_GPIO_PIN_LOCK 0x08
-#define PC87392_GPIO_PIN_TRIG_LEVEL 0x10
-#define PC87392_GPIO_PIN_TRIG_LOW 0x20
-#define PC87392_GPIO_PIN_DEBOUNCE 0x40
-
-#define PC87392_GPIO_PIN_TRIGGERS_IRQ 0x01
-#define PC87392_GPIO_PIN_TRIGGERS_SMI 0x02
-
-#endif
diff --git a/src/superio/nsc/pc87392/superio.c b/src/superio/nsc/pc87392/superio.c
index edd4619..9971b5c 100644
--- a/src/superio/nsc/pc87392/superio.c
+++ b/src/superio/nsc/pc87392/superio.c
@@ -19,7 +19,7 @@
#include <device/pnp.h>
#include <string.h>
#include <stdlib.h>
-#include "pc87392.h"
+#include <superio/nsc/common/superio_defs.h>
static void init(struct device *dev)
{
@@ -36,13 +36,13 @@
};
static struct pnp_info pnp_dev_info[] = {
- { NULL, PC87392_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8 },
- { NULL, PC87392_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8 },
- { NULL, PC87392_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1,
+ { NULL, PC8XXXX_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8 },
+ { NULL, PC8XXXX_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8 },
+ { NULL, PC8XXXX_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1,
0x07f8 },
- { NULL, PC87392_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8 },
- { NULL, PC87392_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8 },
- { NULL, PC87392_WDT, PNP_IO0 | PNP_IRQ0, 0xfffc },
+ { NULL, PC8XXXX_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8 },
+ { NULL, PC8XXXX_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8 },
+ { NULL, PC8XXXX_WDT, PNP_IO0 | PNP_IRQ0, 0xfffc },
};
static void enable_dev(struct device *dev)
diff --git a/src/superio/nsc/pc87417/pc87417.h b/src/superio/nsc/pc87417/pc87417.h
index b50a920..e6c7f79 100644
--- a/src/superio/nsc/pc87417/pc87417.h
+++ b/src/superio/nsc/pc87417/pc87417.h
@@ -19,17 +19,6 @@
#ifndef SUPERIO_NSC_PC87417_H
#define SUPERIO_NSC_PC87417_H
-#define PC87417_FDC 0x00 /* Floppy */
-#define PC87417_PP 0x01 /* Parallel Port */
-#define PC87417_SP2 0x02 /* Com2 */
-#define PC87417_SP1 0x03 /* Com1 */
-#define PC87417_SWC 0x04 /* System Wake-Up Controller (SWC) */
-#define PC87417_KBCM 0x05 /* Mouse */
-#define PC87417_KBCK 0x06 /* Keyboard */
-#define PC87417_GPIO 0x07
-#define PC87417_XBUS 0x0F
-#define PC87417_RTC 0x10
-
#define PC87417_GPIO_DEV PNP_DEV(0x2e, PC87417_GPIO)
/* This is to get around a romcc bug */
/* #define PC87417_XBUS_DEV PNP_DEV(0x2e, PC87417_XBUS) */
diff --git a/src/superio/nsc/pc87417/superio.c b/src/superio/nsc/pc87417/superio.c
index f0e0bb1..a4e8022 100644
--- a/src/superio/nsc/pc87417/superio.c
+++ b/src/superio/nsc/pc87417/superio.c
@@ -22,7 +22,7 @@
#include <string.h>
#include <pc80/keyboard.h>
#include <stdlib.h>
-#include "pc87417.h"
+#include <superio/nsc/common/superio_defs.h>
static void init(struct device *dev)
{
@@ -30,7 +30,7 @@
return;
switch (dev->path.pnp.device) {
- case PC87417_KBCK:
+ case PC8XXXX_KBCK:
pc_keyboard_init(NO_AUX_DEVICE);
break;
}
@@ -45,17 +45,17 @@
};
static struct pnp_info pnp_dev_info[] = {
- { NULL, PC87417_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
- { NULL, PC87417_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
- { NULL, PC87417_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1,
+ { NULL, PC8XXXX_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
+ { NULL, PC8XXXX_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
+ { NULL, PC8XXXX_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1,
0x07f8, },
- { NULL, PC87417_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
- { NULL, PC87417_SWC, PNP_IO0 | PNP_IRQ0, 0xfff0, },
- { NULL, PC87417_KBCM, PNP_IRQ0, },
- { NULL, PC87417_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, },
- { NULL, PC87417_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8, },
- { NULL, PC87417_XBUS, PNP_IO0 | PNP_IRQ0, 0xffe0, },
- { NULL, PC87417_RTC, PNP_IO0 | PNP_IO1, 0xfffe, 0xfffe, },
+ { NULL, PC8XXXX_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
+ { NULL, PC8XXXX_SWC, PNP_IO0 | PNP_IRQ0, 0xfff0, },
+ { NULL, PC8XXXX_KBCM, PNP_IRQ0, },
+ { NULL, PC8XXXX_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, },
+ { NULL, PC8XXXX_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8, },
+ { NULL, PC8XXXX_XBUS, PNP_IO0 | PNP_IRQ0, 0xffe0, },
+ { NULL, PC8XXXX_RTC, PNP_IO0 | PNP_IO1, 0xfffe, 0xfffe, },
};
static void enable_dev(struct device *dev)
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Iffdb4752f3075b1a1b391d4cf8d4416748bfe485
Gerrit-Change-Number: 31427
Gerrit-PatchSet: 1
Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com>
Gerrit-MessageType: newchange
3 days, 17 hours
- 2
- 2
Change in ...coreboot[master]: intel/skylake: nhlt: Add 24 bit blobs for Max98373
by Jenny Tc (Code Review)
Jenny Tc has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31635
Change subject: intel/skylake: nhlt: Add 24 bit blobs for Max98373
......................................................................
intel/skylake: nhlt: Add 24 bit blobs for Max98373
Enable 24 bit nhlt blobs and remove 16 bit blobs. 16 bit and 24 bit
blobs cannot be supported together since the OS NHLT parsing relies
on container bit format. The container bit format for 16 and 24 bit
capture are same (32) and putting both blobs in configs results in
selecting the first blob. To enable 24 and 16 bit blobs together, the
core nhlt parsing logic has to be changed which would impact SKL and
KBL platforms. In order to minimize the impact, the 16 bit blob is
removed considering that the machine driver for max98373 is expected to
support only format due to topology configuration for 16 and 24 bit.
BUG=b:110795132
BRANCH=none
TEST=Verify playback after flashing
CQ-DEPEND=*806750
Change-Id: I62cc109fb0aca9269736779a6ce80980b0571b78
Signed-off-by: Jenny TC <jenny.tc(a)intel.com>
---
M src/soc/intel/skylake/nhlt/Makefile.inc
M src/soc/intel/skylake/nhlt/max98373.c
2 files changed, 6 insertions(+), 16 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/31635/1
diff --git a/src/soc/intel/skylake/nhlt/Makefile.inc b/src/soc/intel/skylake/nhlt/Makefile.inc
index 5c8bd80..548747a 100644
--- a/src/soc/intel/skylake/nhlt/Makefile.inc
+++ b/src/soc/intel/skylake/nhlt/Makefile.inc
@@ -21,7 +21,6 @@
DMIC_4CH_48KHZ_32B = dmic-4ch-48khz-32b.bin
NAU88L25 = nau88l25-2ch-48khz-24b.bin
MAX98357_RENDER = max98357-render-2ch-48khz-24b.bin
-MAX98373_RENDER_16B = max98373-render-2ch-48khz-16b.bin
MAX98373_RENDER_24B = max98373-render-2ch-48khz-24b.bin
MAX98927_RENDER_24B = max98927-render-2ch-48khz-24b.bin
MAX98927_RENDER_16B = max98927-render-2ch-48khz-16b.bin
diff --git a/src/soc/intel/skylake/nhlt/max98373.c b/src/soc/intel/skylake/nhlt/max98373.c
index 0e3a413..a781943 100644
--- a/src/soc/intel/skylake/nhlt/max98373.c
+++ b/src/soc/intel/skylake/nhlt/max98373.c
@@ -25,35 +25,26 @@
.speaker_mask = SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT,
.settings_file = "max98373-render-2ch-48khz-24b.bin",
},
- /* 48 KHz 16-bits per sample. */
- {
- .num_channels = 2,
- .sample_freq_khz = 48,
- .container_bits_per_sample = 16,
- .valid_bits_per_sample = 16,
- .speaker_mask = SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT,
- .settings_file = "max98373-render-2ch-48khz-16b.bin",
- }
};
static const struct nhlt_format_config max98373_capture_formats[] = {
- /* 48 KHz 16-bits per sample - Quad Channel. */
+ /* 48 KHz 24-bits per sample - Quad Channel. */
{
.num_channels = 4,
.sample_freq_khz = 48,
.container_bits_per_sample = 32,
- .valid_bits_per_sample = 16,
+ .valid_bits_per_sample = 24,
.speaker_mask = SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT,
- .settings_file = "max98373-render-2ch-48khz-16b.bin",
+ .settings_file = "max98373-render-2ch-48khz-24b.bin",
},
- /* 48 KHz 16-bits per sample - Stereo Channel */
+ /* 48 KHz 24-bits per sample - Stereo Channel */
{
.num_channels = 2,
.sample_freq_khz = 48,
.container_bits_per_sample = 32,
- .valid_bits_per_sample = 16,
+ .valid_bits_per_sample = 24,
.speaker_mask = SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT,
- .settings_file = "max98373-render-2ch-48khz-16b.bin",
+ .settings_file = "max98373-render-2ch-48khz-24b.bin",
},
};
--
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Gerrit-Branch: master
Gerrit-Change-Id: I62cc109fb0aca9269736779a6ce80980b0571b78
Gerrit-Change-Number: 31635
Gerrit-PatchSet: 1
Gerrit-Owner: Jenny Tc <jenny.tc(a)intel.com>
Gerrit-MessageType: newchange
4 days
- 7
- 26
Change in ...coreboot[master]: arch/x86: Add option for running Romstage out of RAM
by Martin Roth (Code Review)
Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32414
Change subject: arch/x86: Add option for running Romstage out of RAM
......................................................................
arch/x86: Add option for running Romstage out of RAM
AMD's Picasso SOC brings up memory before releasing the X86 processor,
and jumps directly to Romstage. Add a global config option to handle
that.
TEST=None
BUG=b:130804851
Signed-off-by: Martin Roth <martinroth(a)chromium.org>
Change-Id: I678b1f74546ea30abcc655a0daed795d6cfa0034
---
M src/Kconfig
M src/arch/x86/assembly_entry.S
M src/arch/x86/memlayout.ld
3 files changed, 25 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/32414/1
diff --git a/src/Kconfig b/src/Kconfig
index 62b3818..bfa0b51 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -146,6 +146,16 @@
time spent decompressing. Doesn't work for XIP stages (assume all
ARCH_X86 for now) for obvious reasons.
+config ROMSTAGE_IN_RAM
+ bool
+ depends on ARCH_X86
+ help
+ Some newer x86 processors come alive with memory enabled, and the
+ reset vector's physical address falling within DRAM. Select this
+ item to build romstage to execute in DRAM instead of XIP. Because
+ this is not a standard, the soc/ or cpu/ code must handle the reset
+ natively before jumping into the standard romstage code.
+
config COMPRESS_BOOTBLOCK
bool
help
diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S
index 4ead9ea..01c0865 100644
--- a/src/arch/x86/assembly_entry.S
+++ b/src/arch/x86/assembly_entry.S
@@ -26,6 +26,16 @@
* variables that are stage specific.
*/
.section ".text._start", "ax", @progbits
+#if ENV_ROMSTAGE && IS_ENABLED(CONFIG_ROMSTAGE_IN_RAM)
+/*
+ * Systems that run romstage in DRAM, i.e. where romstage is the first
+ * executed code, are responsible for getting the processor into protected
+ * mode, setting the stack pointer, and jumping to this location.
+ */
+.global _romstage_in_ram_continue
+_romstage_in_ram_continue:
+
+#else
.global _start
_start:
@@ -34,6 +44,7 @@
/* reset stack pointer to CAR stack */
mov $_car_stack_end, %esp
+#endif
/* clear CAR_GLOBAL area as it is not shared */
cld
diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld
index cc72552..da63b05 100644
--- a/src/arch/x86/memlayout.ld
+++ b/src/arch/x86/memlayout.ld
@@ -57,6 +57,10 @@
#endif
}
+#if ENV_ROMSTAGE && CONFIG(ROMSTAGE_IN_RAM)
+#include <soc/romstage.ld>
+#endif
+
#if ENV_BOOTBLOCK
/* Bootblock specific scripts which provide more SECTION directives. */
#include <cpu/x86/16bit/entry16.ld>
--
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Gerrit-Branch: master
Gerrit-Change-Id: I678b1f74546ea30abcc655a0daed795d6cfa0034
Gerrit-Change-Number: 32414
Gerrit-PatchSet: 1
Gerrit-Owner: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-MessageType: newchange
4 days, 6 hours
- 8
- 40
Change in ...coreboot[master]: HACK PATCH: SDM845: Enable DFS mode for QUP
by mturney mturney (Code Review)
mturney mturney has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33813
Change subject: HACK PATCH: SDM845: Enable DFS mode for QUP
......................................................................
HACK PATCH: SDM845: Enable DFS mode for QUP
Enable DFS mode for QUP which are PORed with I2C & SPI use case in kernel.
Change-Id: Id36f20c562337c645db8fc127fe0370d4b0c10fa
Signed-off-by: Akash Asthana <akashast(a)codeaurora.org>
---
M src/mainboard/google/cheza/mainboard.c
1 file changed, 8 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/33813/1
diff --git a/src/mainboard/google/cheza/mainboard.c b/src/mainboard/google/cheza/mainboard.c
index 1a2e42a..a5d1bdb 100644
--- a/src/mainboard/google/cheza/mainboard.c
+++ b/src/mainboard/google/cheza/mainboard.c
@@ -82,6 +82,14 @@
qupv3_fw_init();
setup_usb();
i2c_init(QUPV3_1_SE4, I2C_SPEED_FAST); /* Speaker amp */
+ write32((void *)0x117048, 0x21);
+ write32((void *)0x1172a8, 0x21);
+ write32((void *)0x1173d8, 0x21);
+ write32((void *)0x117638, 0x21);
+ write32((void *)0x11828c, 0x21);
+ write32((void *)0x1183bc, 0x21);
+ write32((void *)0x1184ec, 0x21);
+ write32((void *)0x11874c, 0x21);
sdm845_sound_init();
}
--
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Gerrit-Change-Id: Id36f20c562337c645db8fc127fe0370d4b0c10fa
Gerrit-Change-Number: 33813
Gerrit-PatchSet: 1
Gerrit-Owner: mturney mturney <mturney(a)qualcomm.corp-partner.google.com>
Gerrit-MessageType: newchange
6 days, 11 hours
- 1
- 1
Change in ...coreboot[master]: HACK fix upstream bug in util/cbfstool/fit.c
by mturney mturney (Code Review)
mturney mturney has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33812
Change subject: HACK fix upstream bug in util/cbfstool/fit.c
......................................................................
HACK fix upstream bug in util/cbfstool/fit.c
Change-Id: Iac4df05477de0a7a26af46720c4a19156767463f
Signed-off-by: T Michael Turney <mturney(a)codeaurora.org>
---
M util/cbfstool/fit.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/33812/1
diff --git a/util/cbfstool/fit.c b/util/cbfstool/fit.c
index 4cd84f2..500e14f 100644
--- a/util/cbfstool/fit.c
+++ b/util/cbfstool/fit.c
@@ -601,7 +601,7 @@
name = "unknown";
}
- printf(" %6zd %-20s 0x%08"PRIx64" 0x%08zx\n", i, name,
+ printf(" %6zd %-20s 0x%08zx 0x%08zx\n", i, name,
fit->entries[i].address,
fit_entry_size_bytes(&fit->entries[i]));
}
--
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Gerrit-Change-Id: Iac4df05477de0a7a26af46720c4a19156767463f
Gerrit-Change-Number: 33812
Gerrit-PatchSet: 1
Gerrit-Owner: mturney mturney <mturney(a)qualcomm.corp-partner.google.com>
Gerrit-MessageType: newchange
6 days, 11 hours
- 1
- 1
Change in ...coreboot[master]: Adding Asus A88XM-E FM2+ motherboard with documentation
by Balázs Vinarz (Code Review)
Balázs Vinarz has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30987
Change subject: Adding Asus A88XM-E FM2+ motherboard with documentation
......................................................................
Adding Asus A88XM-E FM2+ motherboard with documentation
Signed-off-by: Balazs Vinarz <vinibali1(a)gmail.com>
Change-Id: I60fa0636ba41f5f1a6a3faa2764bf2f0a968cf90
---
A Documentation/mainboard/asus/a88xm-e.md
A src/mainboard/asus/a88xm-e/BiosCallOuts.c
A src/mainboard/asus/a88xm-e/Kconfig
A src/mainboard/asus/a88xm-e/Kconfig.name
A src/mainboard/asus/a88xm-e/Makefile.inc
A src/mainboard/asus/a88xm-e/OemCustomize.c
A src/mainboard/asus/a88xm-e/OptionsIds.h
A src/mainboard/asus/a88xm-e/acpi/cpstate.asl
A src/mainboard/asus/a88xm-e/acpi/gpe.asl
A src/mainboard/asus/a88xm-e/acpi/mainboard.asl
A src/mainboard/asus/a88xm-e/acpi/routing.asl
A src/mainboard/asus/a88xm-e/acpi/sata.asl
A src/mainboard/asus/a88xm-e/acpi/si.asl
A src/mainboard/asus/a88xm-e/acpi/sleep.asl
A src/mainboard/asus/a88xm-e/acpi/superio.asl
A src/mainboard/asus/a88xm-e/acpi/thermal.asl
A src/mainboard/asus/a88xm-e/acpi/usb_oc.asl
A src/mainboard/asus/a88xm-e/acpi_tables.c
A src/mainboard/asus/a88xm-e/board_info.txt
A src/mainboard/asus/a88xm-e/buildOpts.c
A src/mainboard/asus/a88xm-e/cmos.layout
A src/mainboard/asus/a88xm-e/devicetree_a88xm-e.cb
A src/mainboard/asus/a88xm-e/dsdt.asl
A src/mainboard/asus/a88xm-e/irq_tables.c
A src/mainboard/asus/a88xm-e/mainboard.c
A src/mainboard/asus/a88xm-e/mptable.c
A src/mainboard/asus/a88xm-e/romstage.c
27 files changed, 2,371 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/30987/1
diff --git a/Documentation/mainboard/asus/a88xm-e.md b/Documentation/mainboard/asus/a88xm-e.md
new file mode 100644
index 0000000..5f50c5a
--- /dev/null
+++ b/Documentation/mainboard/asus/a88xm-e.md
@@ -0,0 +1,131 @@
+# ASUS A88XM-E
+
+This page describes how to run coreboot on the [ASUS A88XM-E].
+
+## Technology
+
+Both "Trinity" and "Richland" FM2 desktop processing units are working,
+the CPU architecture in these CPUs/APUs are [Piledriver],
+and their GPU is [TeraScale 3] (VLIW4-based).
+
+Kaveri is non-working at the moment (FM2+),
+the CPU architecture in these CPUs/APUs are [Steamroller],
+and their GPU is [Sea Islands] (GCN2-based).
+
+```eval_rst
++------------------+--------------------------------------------------+
+| A88XM-E | |
++------------------+--------------------------------------------------+
+| DDR voltage IC | Nuvoton 3101S |
++------------------+--------------------------------------------------+
+| Network | Realtek RTL8111G - Not working |
++------------------+--------------------------------------------------+
+| Northbridge | Integrated into CPU with IMC and GPU (APUs only) |
++------------------+--------------------------------------------------+
+| Southbridge | Bolton-D4 |
++------------------+--------------------------------------------------+
+| Sound IC | Realtek ALC887 |
++------------------+--------------------------------------------------+
+| Super I/O | ITE 8603E |
++------------------+--------------------------------------------------+
+| VRM controller | DIGI VRM ASP1206 |
++------------------+--------------------------------------------------+
+```
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+------------+
+| Type | Value |
++=====================+============+
+| Socketed flash | yes |
++---------------------+------------+
+| Model | [GD25Q64] |
++---------------------+------------+
+| Size | 8 MiB |
++---------------------+------------+
+| Package | DIP-8 |
++---------------------+------------+
+| Write protection | yes |
++---------------------+------------+
+| Dual BIOS feature | no |
++---------------------+------------+
+| Internal flashing | yes |
++---------------------+------------+
+```
+
+### Internal programming
+
+The main SPI flash can be accessed using [flashrom], if the
+AmdSpiRomProtect modules have been deleted in the factory image previously.
+
+## Integrated graphics
+
+### Retrieve the VGA optionrom from the vendor EFI binary by running:
+
+ # dd if=/dev/mem of=vgabios.bin bs=1k count=64 skip=768
+
+This version is usable for all the GPUs.
+1002,9901 Trinity (Radeon HD 7660D)
+1002,9904 Trinity (Radeon HD 7560D)
+1002,990c Richland (Radeon HD 8670D)
+1002,990e Richland (Radeon HD 8570D)
+1002,9991 Trinity (Radeon HD 7540D)
+1002,9993 Trinity (Radeon HD 7480D)
+1002,9996 Richland (Radeon HD 8470D)
+1002,9998 Richland (Radeon HD 8370D)
+1002,999d Richland (Radeon HD 8550D)
+1002,130f Kaveri (Radeon R7)
+
+## Known issues
+
+- AHCI hot-plug
+- Integrated ethernet
+- S3 resume
+- XHCI
+
+### XHCI ports can broke after using any of the blobs, restarting the
+board with factory image makes it work again as fallback.
+Tested even with/without the Bolton and Hudson blobs.
+
+## Untested
+
+- audio over HDMI
+- IOMMU
+- PS/2 mouse
+
+## TODOs
+
+- one ATOMBIOS module for all the integrated GPUs
+- manage to work with Kaveri/Godavary (missing PSP firmware?)
+
+## Working
+
+- ACPI
+- CPU frequency scaling
+- flashrom under coreboot
+- Hardware monitoring
+- Integrated graphics
+- Keyboard
+- KVM virtualization
+- Onboard audio
+- PCI
+- PCIe
+- PS/2 keyboard (during payload, bootloader)
+- SATA
+- Serial port
+- SuperIO based fan control
+- USB (disabling XHCI controller makes to work as fallback USB2.0 ports)
+
+## Extra resources
+
+- [Board manual]
+
+[ASUS A88XM-E]: https://www.asus.com/Motherboards/A88XME/
+[Board manual]: https://dlcdnets.asus.com/pub/ASUS/mb/SocketFM2/A88XM-E/E9125_A88XM-E.pdf
+[flashrom]: https://flashrom.org/Flashrom
+[GD25Q64]: http://www.elm-tech.com/ja/products/spi-flash-memory/gd25q64/gd25q64.pdf
+[Piledriver]: https://en.wikipedia.org/wiki/Piledriver_%28microarchitecture%29#APU_lines
+[Sea Islands]: https://en.wikipedia.org/wiki/Graphics_Core_Next#GCN_2nd_generation
+[Steamroller]: https://en.wikipedia.org/wiki/Steamroller_(microarchitecture)
+[TeraScale 3]: https://en.wikipedia.org/wiki/TeraScale_%28microarchitecture%29#TeraScale_3
diff --git a/src/mainboard/asus/a88xm-e/BiosCallOuts.c b/src/mainboard/asus/a88xm-e/BiosCallOuts.c
new file mode 100644
index 0000000..56c1753
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/BiosCallOuts.c
@@ -0,0 +1,98 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <AGESA.h>
+#include <northbridge/amd/agesa/BiosCallOuts.h>
+#include <northbridge/amd/agesa/state_machine.h>
+
+#include <vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h>
+#include <stdlib.h>
+
+const BIOS_CALLOUT_STRUCT BiosCallouts[] =
+{
+ {AGESA_DO_RESET, agesa_Reset },
+ {AGESA_READ_SPD, agesa_ReadSpd },
+ {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported },
+ {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp },
+ {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData },
+ {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess },
+ {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
+ {AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage }
+};
+const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
+
+/**
+ * ASUS A88XM-E board ALC887-VD Verb Table
+ *
+ * Copied from `/sys/class/sound/hwC1D0/init_pin_configs` when running
+ * the vendor BIOS.
+ */
+#if !IS_ENABLED(CONFIG_BOARD_ASUS_A88XM_E)
+const CODEC_ENTRY a88xm_e_alc887_VerbTbl[] = {
+ {0x11, 0x90460130},
+ {0x12, 0x40330000},
+ {0x14, 0x01014010},
+ {0x15, 0x411111f0},
+ {0x16, 0x411111f0},
+ {0x17, 0x411111f0},
+ {0x18, 0x01a19040},
+ {0x19, 0x02a19050},
+ {0x1a, 0x0181304f},
+ {0x1b, 0x02214020},
+ {0x1c, 0x411111f0},
+ {0x1d, 0x4044c601},
+ {0x1e, 0x411111f0},
+ {0x1f, 0x411111f0}
+ };
+#else
+const CODEC_ENTRY a88xm_e_alc887_VerbTbl[] = {
+ {0x11, 0x90460130},
+ {0x12, 0x40330000},
+ {0x14, 0x01014010},
+ {0x15, 0x411111f0},
+ {0x16, 0x411111f0},
+ {0x17, 0x411111f0},
+ {0x18, 0x01a19040},
+ {0x19, 0x02a19050},
+ {0x1a, 0x0181304f},
+ {0x1b, 0x02214020},
+ {0x1c, 0x411111f0},
+ {0x1d, 0x4044c601},
+ {0x1e, 0x411111f0},
+ {0x1f, 0x411111f0}
+};
+#endif
+
+static const CODEC_TBL_LIST CodecTableList[] =
+{
+ {0x10ec0887, (CODEC_ENTRY*)&a88xm_e_alc887_VerbTbl[0]},
+ {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL}
+};
+
+void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset)
+{
+ FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE);
+}
+
+void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env)
+{
+ /* Azalia Controller OEM Codec Table Pointer */
+ FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&CodecTableList[0]);
+
+ /* Fan Control */
+ FchParams_env->Imc.ImcEnable = FALSE;
+ FchParams_env->Hwm.HwMonitorEnable = FALSE;
+ FchParams_env->Hwm.HwmFchtsiAutoPoll = FALSE;/* 1 enable, 0 disable TSI Auto Polling */
+}
diff --git a/src/mainboard/asus/a88xm-e/Kconfig b/src/mainboard/asus/a88xm-e/Kconfig
new file mode 100644
index 0000000..70be2f1
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/Kconfig
@@ -0,0 +1,117 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+# Copyright (C) 2012 Rudolf Marek <r.marek(a)assembler.cz>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+if BOARD_ASUS_A88XM_E
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select CPU_AMD_AGESA_FAMILY15_TN
+ select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN
+ select SOUTHBRIDGE_AMD_AGESA_HUDSON
+ select HAVE_OPTION_TABLE
+ select HAVE_PIRQ_TABLE
+ select HAVE_MP_TABLE
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select SUPERIO_ITE_IT8728F
+ select BOARD_ROMSIZE_KB_8192
+ select GFXUMA
+
+choice
+ prompt "DDR3 memory voltage"
+ default BOARD_ASUS_A88XM_E_DDR3_VOLT_150
+
+config BOARD_ASUS_A88XM_E_DDR3_VOLT_135
+ bool "1.35V"
+ help
+ Set DRR3 memory voltage to 1.35V
+config BOARD_ASUS_A88XM_E_DDR3_VOLT_150
+ bool "1.50V"
+ help
+ Set DRR3 memory voltage to 1.50V
+config BOARD_ASUS_A88XM_E_DDR3_VOLT_165
+ bool "1.65V"
+ help
+ Set DRR3 memory voltage to 1.65V
+endchoice
+
+config BOARD_ASUS_A88XM_E_DDR3_VOLT_VAL
+ hex
+ default 0x9e if BOARD_ASUS_A88XM_E_DDR3_VOLT_135
+ default 0x0 if BOARD_ASUS_A88XM_E_DDR3_VOLT_150
+ default 0x1e if BOARD_ASUS_A88XM_E_DDR3_VOLT_165
+
+config MAINBOARD_DIR
+ string
+ default asus/a88xm-e
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "A88XM-E" if BOARD_ASUS_A88XM_E
+
+config HW_MEM_HOLE_SIZEK
+ hex
+ default 0x200000
+
+config MAX_CPUS
+ int
+ default 4
+
+config HUDSON_XHCI_FWM
+ bool
+ default n
+
+config HUDSON_IMC_FWM
+ bool
+ default n
+
+config IRQ_SLOT_COUNT
+ int
+ default 11
+
+config ONBOARD_VGA_IS_PRIMARY
+ bool
+ default y
+
+config VGA_BIOS_ID
+ string
+ default "1002,990e"
+
+config CONFIG_DRIVERS_PS2_KEYBOARD
+ bool
+ default y
+
+config CONFIG_HUDSON_XHCI_ENABLE
+ bool
+ default n
+
+config HUDSON_LEGACY_FREE
+ bool
+ default n
+
+config POST_IO
+ bool
+ default n
+
+config CONFIG_POST_DEVICE_PCI_PCIE
+ bool
+ default y
+
+config DEVICETREE
+ string
+ default "devicetree_a88xm-e.cb"
+
+endif # BOARD_ASUS_A88XM_E
diff --git a/src/mainboard/asus/a88xm-e/Kconfig.name b/src/mainboard/asus/a88xm-e/Kconfig.name
new file mode 100644
index 0000000..492d610
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_ASUS_A88XM_E
+ bool "A88XM-E"
diff --git a/src/mainboard/asus/a88xm-e/Makefile.inc b/src/mainboard/asus/a88xm-e/Makefile.inc
new file mode 100644
index 0000000..f8895fa
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/Makefile.inc
@@ -0,0 +1,22 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+romstage-y += buildOpts.c
+romstage-y += BiosCallOuts.c
+romstage-y += OemCustomize.c
+
+ramstage-y += buildOpts.c
+ramstage-y += BiosCallOuts.c
+ramstage-y += OemCustomize.c
diff --git a/src/mainboard/asus/a88xm-e/OemCustomize.c b/src/mainboard/asus/a88xm-e/OemCustomize.c
new file mode 100644
index 0000000..4c4c5bf
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/OemCustomize.c
@@ -0,0 +1,177 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <Porting.h>
+#include <AGESA.h>
+
+#include <northbridge/amd/agesa/state_machine.h>
+#include <PlatformMemoryConfiguration.h>
+
+/*
+ * Lane ID Mapping (from Fam15h BKDG: Table 45: Lane Id Mapping)
+ *
+ * Lane Id
+ * 0 P_UMI_[T,R]X[P,N]0 - southbridge link, connect via dev 8
+ * 1 P_UMI_[T,R]X[P,N]1 - southbridge link, connect via dev 8
+ * 2 P_UMI_[T,R]X[P,N]2 - southbridge link, connect via dev 8
+ * 3 P_UMI_[T,R]X[P,N]3 - southbridge link, connect via dev 8
+ * 4 P_GPP_[T,R]X[P,N]0 - may connect to PCI dev 4 - 7
+ * 5 P_GPP_[T,R]X[P,N]1 - may connect to PCI dev 4 - 7
+ * 6 P_GPP_[T,R]X[P,N]2 - may connect to PCI dev 4 - 7
+ * 7 P_GPP_[T,R]X[P,N]3 - may connect to PCI dev 4 - 7
+ * 8 P_GFX_[T,R]X[P,N]0 - may be used to form GFX slot or DDI
+ * 9 P_GFX_[T,R]X[P,N]1 - may be used to form GFX slot or DDI
+ * 10 P_GFX_[T,R]X[P,N]2 - may be used to form GFX slot or DDI
+ * 11 P_GFX_[T,R]X[P,N]3 - may be used to form GFX slot or DDI
+ * 12 P_GFX_[T,R]X[P,N]4 - may be used to form GFX slot or DDI
+ * 13 P_GFX_[T,R]X[P,N]5 - may be used to form GFX slot or DDI
+ * 14 P_GFX_[T,R]X[P,N]6 - may be used to form GFX slot or DDI
+ * 15 P_GFX_[T,R]X[P,N]7 - may be used to form GFX slot or DDI
+ * 16 P_GFX_[T,R]X[P,N]8 - may be used to form GFX slot or DDI
+ * 17 P_GFX_[T,R]X[P,N]9 - may be used to form GFX slot or DDI
+ * 18 P_GFX_[T,R]X[P,N]10 - may be used to form GFX slot or DDI
+ * 19 P_GFX_[T,R]X[P,N]11 - may be used to form GFX slot or DDI
+ * 20 P_GFX_[T,R]X[P,N]12 - may be used to form GFX slot or DDI
+ * 21 P_GFX_[T,R]X[P,N]13 - may be used to form GFX slot or DDI
+ * 22 P_GFX_[T,R]X[P,N]14 - may be used to form GFX slot or DDI
+ * 23 P_GFX_[T,R]X[P,N]15 - may be used to form GFX slot or DDI
+ * 24 DP0_TX[P,N]0 - rest is just for DDI (graphics outputs)
+ * 25 DP0_TX[P,N]1
+ * 26 DP0_TX[P,N]2
+ * 27 DP0_TX[P,N]3
+ * 28 DP1_TX[P,N]0
+ * 29 DP1_TX[P,N]1
+ * 30 DP1_TX[P,N]2
+ * 31 DP1_TX[P,N]3
+ * 32 DP2_TX[P,N]0
+ * 33 DP2_TX[P,N]1
+ * 34 DP2_TX[P,N]2
+ * 35 DP2_TX[P,N]3
+ * 36 DP2_TX[P,N]4
+ * 37 DP2_TX[P,N]5
+ * 38 DP2_TX[P,N]6
+ */
+
+static const PCIe_PORT_DESCRIPTOR PortList[] = {
+ /* PCIe port, Lanes 8:23, PCI Device Number 2, blue x16 slot */
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 23),
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 1)
+ },
+ /* PCIe port, Lanes 4:7, PCI Device Number 4, black x16 slot (in fact x4) */
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7),
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 1)
+ },
+ /* PCIe port, Lanes 0:3, UMI link to SB, PCI Device Number 8 */
+ {
+ DESCRIPTOR_TERMINATE_LIST,
+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
+ HotplugDisabled,
+ PcieGenMaxSupported,
+ PcieGenMaxSupported,
+ AspmDisabled, 0)
+ },
+};
+
+/*
+ * It is not known, if the setup is complete.
+ *
+ * Tested and works: VGA/DVI
+ * Untested: HDMI
+ */
+static const PCIe_DDI_DESCRIPTOR DdiList[] = {
+ // DP0 to HDMI0/DP
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 24, 27),
+ PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux1, Hdp1)
+ },
+ // DP1 to FCH
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 28, 31),
+ PCIE_DDI_DATA_INITIALIZER(ConnectorTypeNutmegDpToVga, Aux2, Hdp2)
+ },
+ // DP2 to HDMI1/DP
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 32, 35),
+ PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux3, Hdp3)
+ },
+};
+
+static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
+ .Flags = DESCRIPTOR_TERMINATE_LIST,
+ .SocketId = 0,
+ .PciePortList = PortList,
+ .DdiLinkList = DdiList,
+};
+
+void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
+{
+ FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface;
+ FchReset->Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
+ FchReset->Xhci1Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
+}
+
+void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
+{
+ InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
+ InitEarly->GnbConfig.PsppPolicy = 0;
+}
+
+/*----------------------------------------------------------------------------------------
+ * CUSTOMER OVERIDES MEMORY TABLE
+ *----------------------------------------------------------------------------------------
+ */
+
+/*
+ * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
+ * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
+ * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
+ * use its default conservative settings.
+ */
+
+static CONST PSO_ENTRY ROMDATA MemoryTable_XM_E[] = {
+
+ NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1),
+ NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2),
+
+ PSO_END
+};
+
+void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
+{
+ if (IS_ENABLED(CONFIG_BOARD_ASUS_A88XM_E))
+ InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *) MemoryTable_XM_E;
+}
+
+void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid)
+{
+ /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
+ InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
+}
diff --git a/src/mainboard/asus/a88xm-e/OptionsIds.h b/src/mainboard/asus/a88xm-e/OptionsIds.h
new file mode 100644
index 0000000..b45f5a8
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/OptionsIds.h
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/**
+ * @file
+ *
+ * IDS Option File
+ *
+ * This file is used to switch on/off IDS features.
+ *
+ */
+#ifndef _OPTION_IDS_H_
+#define _OPTION_IDS_H_
+
+/**
+ *
+ * This file generates the defaults tables for the Integrated Debug Support
+ * Module. The documented build options are imported from a user controlled
+ * file for processing. The build options for the Integrated Debug Support
+ * Module are listed below:
+ *
+ * IDSOPT_IDS_ENABLED
+ * IDSOPT_ERROR_TRAP_ENABLED
+ * IDSOPT_CONTROL_ENABLED
+ * IDSOPT_TRACING_ENABLED
+ * IDSOPT_PERF_ANALYSIS
+ * IDSOPT_ASSERT_ENABLED
+ * IDS_DEBUG_PORT
+ * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
+ *
+ **/
+
+//#define IDSOPT_IDS_ENABLED TRUE
+//#define IDSOPT_CONTROL_ENABLED TRUE
+#define IDSOPT_TRACING_ENABLED TRUE
+#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE
+//#define IDSOPT_PERF_ANALYSIS TRUE
+#define IDSOPT_ASSERT_ENABLED TRUE
+//#undef IDSOPT_DEBUG_ENABLED
+//#define IDSOPT_DEBUG_ENABLED FALSE
+//#undef IDSOPT_HOST_SIMNOW
+//#define IDSOPT_HOST_SIMNOW FALSE
+//#undef IDSOPT_HOST_HDT
+//#define IDSOPT_HOST_HDT FALSE
+//#define IDS_DEBUG_PORT 0x80
+
+#endif
diff --git a/src/mainboard/asus/a88xm-e/acpi/cpstate.asl b/src/mainboard/asus/a88xm-e/acpi/cpstate.asl
new file mode 100644
index 0000000..69de2d8
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/cpstate.asl
@@ -0,0 +1,112 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* This file defines the processor and performance state capability
+ * for each core in the system. It is included into the DSDT for each
+ * core. It assumes that each core of the system has the same performance
+ * characteristics.
+*/
+/*
+#include <arch/acpi.h>
+DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001)
+ {
+ Scope (\_PR) {
+ Processor(CPU0,0,0x808,0x06) {
+ #include "cpstate.asl"
+ }
+ Processor(CPU1,1,0x0,0x0) {
+ #include "cpstate.asl"
+ }
+ Processor(CPU2,2,0x0,0x0) {
+ #include "cpstate.asl"
+ }
+ Processor(CPU3,3,0x0,0x0) {
+ #include "cpstate.asl"
+ }
+ }
+*/
+ /* P-state support: The maximum number of P-states supported by the */
+ /* CPUs we'll use is 6. */
+ /* Get from AMI BIOS. */
+ Name(_PSS, Package(){
+ Package()
+ {
+ 0x00000D48,
+ 0x00011170,
+ 0x00000004,
+ 0x00000004,
+ 0x00000000,
+ 0x00000000
+ },
+
+ Package()
+ {
+ 0x00000AF0,
+ 0x0000C544,
+ 0x00000004,
+ 0x00000004,
+ 0x00000001,
+ 0x00000001
+ },
+
+ Package()
+ {
+ 0x000009C4,
+ 0x0000B3B0,
+ 0x00000004,
+ 0x00000004,
+ 0x00000002,
+ 0x00000002
+ },
+
+ Package()
+ {
+ 0x00000898,
+ 0x0000ABE0,
+ 0x00000004,
+ 0x00000004,
+ 0x00000003,
+ 0x00000003
+ },
+
+ Package()
+ {
+ 0x00000708,
+ 0x0000A410,
+ 0x00000004,
+ 0x00000004,
+ 0x00000004,
+ 0x00000004
+ },
+
+ Package()
+ {
+ 0x00000578,
+ 0x00006F54,
+ 0x00000004,
+ 0x00000004,
+ 0x00000005,
+ 0x00000005
+ }
+ })
+
+ Name(_PCT, Package(){
+ ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
+ ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}
+ })
+
+ Method(_PPC, 0){
+ Return(0)
+ }
diff --git a/src/mainboard/asus/a88xm-e/acpi/gpe.asl b/src/mainboard/asus/a88xm-e/acpi/gpe.asl
new file mode 100644
index 0000000..297db37
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/gpe.asl
@@ -0,0 +1,72 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Scope(\_GPE) { /* Start Scope GPE */
+
+ /* General event 3 */
+ Method(_L03) {
+ /* DBGO("\\_GPE\\_L00\n") */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* Legacy PM event */
+ Method(_L08) {
+ /* DBGO("\\_GPE\\_L08\n") */
+ }
+
+ /* Temp warning (TWarn) event */
+ Method(_L09) {
+ /* DBGO("\\_GPE\\_L09\n") */
+ /* Notify (\_TZ.TZ00, 0x80) */
+ }
+
+ /* USB controller PME# */
+ Method(_L0B) {
+ /* DBGO("\\_GPE\\_L0B\n") */
+ Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* ExtEvent0 SCI event */
+ Method(_L10) {
+ /* DBGO("\\_GPE\\_L10\n") */
+ }
+
+
+ /* ExtEvent1 SCI event */
+ Method(_L11) {
+ /* DBGO("\\_GPE\\_L11\n") */
+ }
+
+ /* GPIO0 or GEvent8 event */
+ Method(_L18) {
+ /* DBGO("\\_GPE\\_L18\n") */
+ Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* Azalia SCI event */
+ Method(_L1B) {
+ /* DBGO("\\_GPE\\_L1B\n") */
+ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+} /* End Scope GPE */
diff --git a/src/mainboard/asus/a88xm-e/acpi/mainboard.asl b/src/mainboard/asus/a88xm-e/acpi/mainboard.asl
new file mode 100644
index 0000000..8398c88
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/mainboard.asl
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+ /* Data to be patched by the BIOS during POST */
+ /* FIXME the patching is not done yet! */
+ /* Memory related values */
+ Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
+ Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
+ Name(PBLN, 0x0) /* Length of BIOS area */
+
+ Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
+ Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
+ Name(HPBA, 0xFED00000) /* Base address of HPET table */
+
+ /* Some global data */
+ Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
+ Name(OSV, Ones) /* Assume nothing */
+ Name(PMOD, One) /* Assume APIC */
diff --git a/src/mainboard/asus/a88xm-e/acpi/routing.asl b/src/mainboard/asus/a88xm-e/acpi/routing.asl
new file mode 100644
index 0000000..0af6b42
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/routing.asl
@@ -0,0 +1,258 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+ /* Routing is in System Bus scope */
+ Name(PR0, Package(){
+ /* NB devices */
+ /* Bus 0, Dev 0 - F15 Host Controller */
+ Package(){0x0000FFFF, 0, INTA, 0 },
+ Package(){0x0000FFFF, 1, INTB, 0 },
+ Package(){0x0000FFFF, 2, INTC, 0 },
+ Package(){0x0000FFFF, 3, INTD, 0 },
+
+ /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
+ Package(){0x0001FFFF, 0, INTB, 0 },
+ Package(){0x0001FFFF, 1, INTC, 0 },
+
+ /* Bus 0, Dev 2 - PCIe Bridge for x16 slot */
+ Package(){0x0002FFFF, 0, INTC, 0 },
+ Package(){0x0002FFFF, 1, INTD, 0 },
+ Package(){0x0002FFFF, 2, INTA, 0 },
+ Package(){0x0002FFFF, 3, INTB, 0 },
+
+ /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
+
+ /* Bus 0, Dev 4 - PCIe Bridge for 4x slot */
+ Package(){0x0004FFFF, 0, INTA, 0 },
+ Package(){0x0004FFFF, 1, INTB, 0 },
+ Package(){0x0004FFFF, 2, INTC, 0 },
+ Package(){0x0004FFFF, 3, INTD, 0 },
+
+ /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
+ /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
+ /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
+ /* Bus 0, Dev 8 - Southbridge port (normally hidden) */
+
+ /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
+ Package(){0x0014FFFF, 0, INTA, 0 },
+ Package(){0x0014FFFF, 1, INTB, 0 },
+ Package(){0x0014FFFF, 2, INTC, 0 },
+ Package(){0x0014FFFF, 3, INTD, 0 },
+
+ /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0
+ * EHCI @ func 2 */
+ Package(){0x0012FFFF, 0, INTC, 0 },
+ Package(){0x0012FFFF, 1, INTB, 0 },
+
+ Package(){0x0013FFFF, 0, INTC, 0 },
+ Package(){0x0013FFFF, 1, INTB, 0 },
+
+ Package(){0x0016FFFF, 0, INTC, 0 },
+ Package(){0x0016FFFF, 1, INTB, 0 },
+
+ /* SB devices */
+ /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */
+ Package(){0x0010FFFF, 0, INTC, 0 },
+ Package(){0x0010FFFF, 1, INTB, 0 },
+
+ /* Bus 0, Dev 17 - SATA controller */
+ Package(){0x0011FFFF, 0, INTD, 0 },
+
+ /* Bus 0, Dev 21 Pcie Bridge */
+ Package(){0x0015FFFF, 0, INTA, 0 },
+ Package(){0x0015FFFF, 1, INTB, 0 },
+ Package(){0x0015FFFF, 2, INTC, 0 },
+ Package(){0x0015FFFF, 3, INTD, 0 },
+ })
+
+ Name(APR0, Package(){
+ /* NB devices in APIC mode */
+ /* Bus 0, Dev 0 - F15 Host Controller */
+ Package(){0x0000FFFF, 0, 0, 16 },
+ Package(){0x0000FFFF, 1, 0, 17 },
+ Package(){0x0000FFFF, 2, 0, 18 },
+ Package(){0x0000FFFF, 3, 0, 19 },
+
+ /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
+ Package(){0x0001FFFF, 0, 0, 17 },
+ Package(){0x0001FFFF, 1, 0, 18 },
+
+ /* Bus 0, Dev 2 - PCIe Bridge for x16 PCIe Slot */
+ Package(){0x0002FFFF, 0, 0, 18 },
+ Package(){0x0002FFFF, 1, 0, 19 },
+ Package(){0x0002FFFF, 2, 0, 16 },
+ Package(){0x0002FFFF, 3, 0, 17 },
+
+ /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
+
+ /* Bus 0, Dev 4 - PCIe Bridge for x4 PCIe Slot black */
+ Package(){0x0004FFFF, 0, 0, 16 },
+ Package(){0x0004FFFF, 1, 0, 17 },
+ Package(){0x0004FFFF, 2, 0, 18 },
+ Package(){0x0004FFFF, 3, 0, 19 },
+
+ /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
+ /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
+ /* Bus 0, Dev 7 - PCIe Bridge for network card */
+ /* Bus 0, Dev 8 - Southbridge port (normally hidden) */
+
+ /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
+ Package(){0x0014FFFF, 0, 0, 16 },
+ Package(){0x0014FFFF, 1, 0, 17 },
+ Package(){0x0014FFFF, 2, 0, 18 },
+ Package(){0x0014FFFF, 3, 0, 19 },
+
+ /* SB devices in APIC mode */
+ /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0
+ * EHCI @ func 2 */
+ Package(){0x0012FFFF, 0, 0, 18 },
+ Package(){0x0012FFFF, 1, 0, 17 },
+
+ Package(){0x0013FFFF, 0, 0, 18 },
+ Package(){0x0013FFFF, 1, 0, 17 },
+
+ Package(){0x0016FFFF, 0, 0, 18 },
+ Package(){0x0016FFFF, 1, 0, 17 },
+
+ /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */
+ Package(){0x0010FFFF, 0, 0, 0x12},
+ Package(){0x0010FFFF, 1, 0, 0x11},
+
+ /* Bus 0, Dev 17 - SATA controller */
+ Package(){0x0011FFFF, 0, 0, 19 },
+
+ /* Bus 0, Dev 21 PCIE Bridge */
+ Package(){0x0015FFFF, 0, 0, 17 },
+ Package(){0x0015FFFF, 1, 0, 18 },
+ Package(){0x0015FFFF, 2, 0, 19 },
+ Package(){0x0015FFFF, 3, 0, 16 },
+ })
+
+ Name(PS2, Package(){
+ /* The external GFX - Hooked to PCIe slot 2 */
+ Package(){0x0000FFFF, 0, INTD, 0 },
+ Package(){0x0000FFFF, 1, INTA, 0 },
+ Package(){0x0000FFFF, 2, INTB, 0 },
+ Package(){0x0000FFFF, 3, INTC, 0 },
+ })
+ Name(APS2, Package(){
+ /* The external GFX - Hooked to PCIe slot 2 */
+ Package(){0x0000FFFF, 0, 0, 18 },
+ Package(){0x0000FFFF, 1, 0, 19 },
+ Package(){0x0000FFFF, 2, 0, 16 },
+ Package(){0x0000FFFF, 3, 0, 17 },
+ })
+
+ /* black slot */
+ Name(PS4, Package(){
+ /* PCIe slot - Hooked to PCIe slot 4 */
+ Package(){0x0000FFFF, 0, INTA, 0 },
+ Package(){0x0000FFFF, 1, INTB, 0 },
+ Package(){0x0000FFFF, 2, INTC, 0 },
+ Package(){0x0000FFFF, 3, INTD, 0 },
+ })
+ Name(APS4, Package(){
+ /* PCIe slot - Hooked to PCIe slot 4 */
+ Package(){0x0000FFFF, 0, 0, 16 },
+ Package(){0x0000FFFF, 1, 0, 17 },
+ Package(){0x0000FFFF, 2, 0, 18 },
+ Package(){0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name(PS5, Package(){
+ /* PCIe slot - Hooked to PCIe slot 5 */
+ Package(){0x0000FFFF, 0, INTB, 0 },
+ Package(){0x0000FFFF, 1, INTC, 0 },
+ Package(){0x0000FFFF, 2, INTD, 0 },
+ Package(){0x0000FFFF, 3, INTA, 0 },
+ })
+ Name(APS5, Package(){
+ /* PCIe slot - Hooked to PCIe slot 5 */
+ Package(){0x0000FFFF, 0, 0, 17 },
+ Package(){0x0000FFFF, 1, 0, 18 },
+ Package(){0x0000FFFF, 2, 0, 19 },
+ Package(){0x0000FFFF, 3, 0, 16 },
+ })
+
+ Name(PS6, Package(){
+ /* PCIe slot - Hooked to PCIe slot 6 */
+ Package(){0x0000FFFF, 0, INTC, 0 },
+ Package(){0x0000FFFF, 1, INTD, 0 },
+ Package(){0x0000FFFF, 2, INTA, 0 },
+ Package(){0x0000FFFF, 3, INTB, 0 },
+ })
+ Name(APS6, Package(){
+ /* PCIe slot - Hooked to PCIe slot 6 */
+ Package(){0x0000FFFF, 0, 0, 18 },
+ Package(){0x0000FFFF, 1, 0, 19 },
+ Package(){0x0000FFFF, 2, 0, 16 },
+ Package(){0x0000FFFF, 3, 0, 17 },
+ })
+
+ Name(PS7, Package(){
+ /* The onboard Ethernet chip - Hooked to PCIe slot 7 */
+ Package(){0x0000FFFF, 0, INTD, 0 },
+ Package(){0x0000FFFF, 1, INTA, 0 },
+ Package(){0x0000FFFF, 2, INTB, 0 },
+ Package(){0x0000FFFF, 3, INTC, 0 },
+ })
+
+ Name(APS7, Package(){
+ /* The onboard Ethernet chip - Hooked to PCIe slot 7 */
+ Package(){0x0000FFFF, 0, 0, 19 },
+ Package(){0x0000FFFF, 1, 0, 16 },
+ Package(){0x0000FFFF, 2, 0, 17 },
+ Package(){0x0000FFFF, 3, 0, 18 },
+ })
+
+ Name(PBR0, Package(){
+ /* PCIx1 on SB */
+ Package(){0x0000FFFF, 0, INTA, 0 },
+ Package(){0x0000FFFF, 1, INTB, 0 },
+ Package(){0x0000FFFF, 2, INTC, 0 },
+ Package(){0x0000FFFF, 3, INTD, 0 },
+ })
+ Name(ABR0, Package(){
+ /* PCIx1 on SB */
+ Package(){0x0000FFFF, 0, 0, 0x10 },
+ Package(){0x0000FFFF, 1, 0, 0x11 },
+ Package(){0x0000FFFF, 2, 0, 0x12 },
+ Package(){0x0000FFFF, 3, 0, 0x13 },
+ })
+
+ Name(PBR1, Package(){
+ /* Onboard network */
+ Package(){0x0000FFFF, 0, INTB, 0 },
+ Package(){0x0000FFFF, 1, INTC, 0 },
+ Package(){0x0000FFFF, 2, INTD, 0 },
+ Package(){0x0000FFFF, 3, INTA, 0 },
+ })
+ Name(ABR1, Package(){
+ /* Onboard network */
+ Package(){0x0000FFFF, 0, 0, 0x11 },
+ Package(){0x0000FFFF, 1, 0, 0x12 },
+ Package(){0x0000FFFF, 2, 0, 0x13 },
+ Package(){0x0000FFFF, 3, 0, 0x10 },
+ })
+
+ /* SB PCI Bridge */
+ Name(PCIB, Package(){
+ /* PCI slots: slot 0 behind Dev14, Fun4. */
+ Package(){0x0005FFFF, 0, 0, 0x14 },
+ Package(){0x0005FFFF, 1, 0, 0x15 },
+ Package(){0x0005FFFF, 2, 0, 0x16 },
+ Package(){0x0005FFFF, 3, 0, 0x17 },
+ })
diff --git a/src/mainboard/asus/a88xm-e/acpi/sata.asl b/src/mainboard/asus/a88xm-e/acpi/sata.asl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/sata.asl
diff --git a/src/mainboard/asus/a88xm-e/acpi/si.asl b/src/mainboard/asus/a88xm-e/acpi/si.asl
new file mode 100644
index 0000000..ff0c3cf
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/si.asl
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+ Scope(\_SI) {
+ Method(_SST, 1) {
+ /* DBGO("\\_SI\\_SST\n") */
+ /* DBGO(" New Indicator state: ") */
+ /* DBGO(Arg0) */
+ /* DBGO("\n") */
+ }
+ } /* End Scope SI */
diff --git a/src/mainboard/asus/a88xm-e/acpi/sleep.asl b/src/mainboard/asus/a88xm-e/acpi/sleep.asl
new file mode 100644
index 0000000..08b7de4
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/sleep.asl
@@ -0,0 +1,96 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* Wake status package */
+Name(WKST,Package(){Zero, Zero})
+
+/*
+* \_PTS - Prepare to Sleep method
+*
+* Entry:
+* Arg0=The value of the sleeping state S1=1, S2=2, etc
+*
+* Exit:
+* -none-
+*
+* The _PTS control method is executed at the beginning of the sleep process
+* for S1-S5. The sleeping value is passed to the _PTS control method. This
+* control method may be executed a relatively long time before entering the
+* sleep state and the OS may abort the operation without notification to
+* the ACPI driver. This method cannot modify the configuration or power
+* state of any device in the system.
+*/
+Method(\_PTS, 1) {
+ /* DBGO("\\_PTS\n") */
+ /* DBGO("From S0 to S") */
+ /* DBGO(Arg0) */
+ /* DBGO("\n") */
+
+ /* Clear sleep SMI status flag and enable sleep SMI trap. */
+ /*Store(One, CSSM)
+ Store(One, SSEN)*/
+
+ /* On older chips, clear PciExpWakeDisEn */
+ /*if (LLessEqual(\_SB.SBRI, 0x13)) {
+ * Store(0,\_SB.PWDE)
+ *}
+ */
+
+ /* Clear wake status structure. */
+ Store(0, Index(WKST,0))
+ Store(0, Index(WKST,1))
+
+ Store (0x07, UPWS)
+} /* End Method(\_PTS) */
+
+/*
+* \_BFS OEM Back From Sleep method
+*
+* Entry:
+* Arg0=The value of the sleeping state S1=1, S2=2
+*
+* Exit:
+* -none-
+*/
+Method(\_BFS, 1) {
+ /* DBGO("\\_BFS\n") */
+ /* DBGO("From S") */
+ /* DBGO(Arg0) */
+ /* DBGO(" to S0\n") */
+}
+
+/*
+* \_WAK System Wake method
+*
+* Entry:
+* Arg0=The value of the sleeping state S1=1, S2=2
+*
+* Exit:
+* Return package of 2 DWords
+* Dword 1 - Status
+* 0x00000000 wake succeeded
+* 0x00000001 Wake was signaled but failed due to lack of power
+* 0x00000002 Wake was signaled but failed due to thermal condition
+* Dword 2 - Power Supply state
+* if non-zero the effective S-state the power supply entered
+*/
+Method(\_WAK, 1) {
+ /* DBGO("\\_WAK\n") */
+ /* DBGO("From S") */
+ /* DBGO(Arg0) */
+ /* DBGO(" to S0\n") */
+
+ Return(WKST)
+} /* End Method(\_WAK) */
diff --git a/src/mainboard/asus/a88xm-e/acpi/superio.asl b/src/mainboard/asus/a88xm-e/acpi/superio.asl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/superio.asl
diff --git a/src/mainboard/asus/a88xm-e/acpi/thermal.asl b/src/mainboard/asus/a88xm-e/acpi/thermal.asl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/thermal.asl
diff --git a/src/mainboard/asus/a88xm-e/acpi/usb_oc.asl b/src/mainboard/asus/a88xm-e/acpi/usb_oc.asl
new file mode 100644
index 0000000..f5d6980
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/usb_oc.asl
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* USB overcurrent mapping pins. */
+Name(UOM0, 0)
+Name(UOM1, 2)
+Name(UOM2, 0)
+Name(UOM3, 7)
+Name(UOM4, 2)
+Name(UOM5, 2)
+Name(UOM6, 6)
+Name(UOM7, 2)
+Name(UOM8, 6)
+Name(UOM9, 6)
diff --git a/src/mainboard/asus/a88xm-e/acpi_tables.c b/src/mainboard/asus/a88xm-e/acpi_tables.c
new file mode 100644
index 0000000..f94fde0
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi_tables.c
@@ -0,0 +1,46 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
+#include <arch/ioapic.h>
+#include <device/pci.h>
+#include <string.h>
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+ /* create all subtables for processors */
+ current = acpi_create_madt_lapics(current);
+
+ /* Write Hudson IOAPIC, only one */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS,
+ IO_APIC_ADDR, 0);
+
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 0, 2, 0);
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 9, 9, 0xF);
+ /* 0: mean bus 0--->ISA */
+ /* 0: PIC 0 */
+ /* 2: APIC 2 */
+ /* 5 mean: 0101 --> Edge-triggered, Active high */
+
+ /* create all subtables for processors */
+ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1);
+ /* 1: LINT1 connect to NMI */
+
+ return current;
+}
diff --git a/src/mainboard/asus/a88xm-e/board_info.txt b/src/mainboard/asus/a88xm-e/board_info.txt
new file mode 100644
index 0000000..bc090ff
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/board_info.txt
@@ -0,0 +1,7 @@
+Category: desktop
+Board URL: https://www.asus.com/Motherboards/A88XME/
+ROM package: DIP8
+ROM protocol: [http://www.winbond.com/hq/product/code-storage-flash-memory/serial-nor-fl... SPI]
+ROM socketed: y
+Flashrom support: y (without AmdSpiRomProtect modules)
+Release year: 2014
diff --git a/src/mainboard/asus/a88xm-e/buildOpts.c b/src/mainboard/asus/a88xm-e/buildOpts.c
new file mode 100644
index 0000000..c324532
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/buildOpts.c
@@ -0,0 +1,346 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/**
+ * @file
+ *
+ * AMD User options selection for a Brazos platform solution system
+ *
+ * This file is placed in the user's platform directory and contains the
+ * build option selections desired for that platform.
+ *
+ * For Information about this file, see @ref platforminstall.
+ *
+ */
+
+#include <stdlib.h>
+
+#include <vendorcode/amd/agesa/f15tn/AGESA.h>
+
+/* Include the files that instantiate the configuration definitions. */
+#include <vendorcode/amd/agesa/f15tn/Include/AdvancedApi.h>
+#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h>
+#include <vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.h>
+#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h>
+/* the next two headers depend on heapManager.h */
+#include <vendorcode/amd/agesa/f15tn/Proc/Common/CreateStruct.h>
+#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEarlyInit.h>
+/* These tables are optional and may be used to adjust memory timing settings */
+#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mm.h>
+#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h>
+
+
+/* Select the CPU family. */
+#define INSTALL_FAMILY_10_SUPPORT FALSE
+#define INSTALL_FAMILY_12_SUPPORT FALSE
+#define INSTALL_FAMILY_14_SUPPORT FALSE
+#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE
+
+/* Select the CPU socket type. */
+#define INSTALL_G34_SOCKET_SUPPORT FALSE
+#define INSTALL_C32_SOCKET_SUPPORT FALSE
+#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
+#define INSTALL_S1G4_SOCKET_SUPPORT FALSE
+#define INSTALL_ASB2_SOCKET_SUPPORT FALSE
+#define INSTALL_FS1_SOCKET_SUPPORT FALSE
+#define INSTALL_FM1_SOCKET_SUPPORT FALSE
+#define INSTALL_FP2_SOCKET_SUPPORT FALSE
+#define INSTALL_FT1_SOCKET_SUPPORT FALSE
+#define INSTALL_AM3_SOCKET_SUPPORT FALSE
+
+#define INSTALL_FM2_SOCKET_SUPPORT TRUE
+
+//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE
+#define BLDOPT_REMOVE_SODIMMS_SUPPORT TRUE
+#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE
+#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE
+#define BLDOPT_REMOVE_ECC_SUPPORT TRUE
+//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE
+//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE
+#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE
+#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE
+#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE
+//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE
+#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE
+//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE
+#define BLDOPT_REMOVE_SRAT FALSE //TRUE
+#define BLDOPT_REMOVE_SLIT FALSE //TRUE
+#define BLDOPT_REMOVE_WHEA FALSE //TRUE
+#define BLDOPT_REMOVE_CRAT TRUE
+#define BLDOPT_REMOVE_DMI TRUE
+//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE
+
+//This element selects whether P-States should be forced to be independent,
+// as reported by the ACPI _PSD object. For single-link processors,
+// setting TRUE for OS to support this feature.
+
+//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE
+
+#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS
+#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER
+/* Build configuration values here.
+ */
+#define BLDCFG_VRM_CURRENT_LIMIT 90000
+#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0
+#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 0
+#define BLDCFG_PLAT_NUM_IO_APICS 3
+#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
+#define BLDCFG_MEM_INIT_PSTATE 0
+
+#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
+
+#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY
+#define BLDCFG_MEMORY_MODE_UNGANGED TRUE
+#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE
+#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
+#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE
+#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE
+#define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE
+#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE
+#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE
+#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE
+#define BLDCFG_MEMORY_POWER_DOWN TRUE
+#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT
+#define BLDCFG_ONLINE_SPARE FALSE
+#define BLDCFG_BANK_SWIZZLE TRUE
+#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
+#define BLDCFG_MEMORY_CLOCK_SELECT DDR1600_FREQUENCY
+#define BLDCFG_DQS_TRAINING_CONTROL TRUE
+#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE
+#define BLDCFG_USE_BURST_MODE FALSE
+#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE
+#define BLDCFG_ENABLE_ECC_FEATURE FALSE
+#define BLDCFG_ECC_REDIRECTION FALSE
+#define BLDCFG_SCRUB_DRAM_RATE 0
+#define BLDCFG_SCRUB_L2_RATE 0
+#define BLDCFG_SCRUB_L3_RATE 0
+#define BLDCFG_SCRUB_IC_RATE 0
+#define BLDCFG_SCRUB_DC_RATE 0
+#define BLDCFG_ECC_SYMBOL_SIZE 4
+#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000
+#define BLDCFG_ECC_SYNC_FLOOD FALSE
+#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE
+#define BLDCFG_1GB_ALIGN FALSE
+#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE
+#define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 // PCIE Spread Spectrum default value 0.36%
+#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770
+
+#define BLDOPT_REMOVE_ALIB FALSE
+#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto
+#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P'
+#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0'
+#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6
+
+#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 200
+#define BLDCFG_CFG_ABM_SUPPORT 0
+
+//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770
+
+// Specify the default values for the VRM controlling the VDDNB plane.
+// If not specified, the values used for the core VRM will be applied
+//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 // Not currently used on Trinity
+//#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L
+//#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in calculating the VSRampSlamTime
+//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 // Not currently used on Trinity
+//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE 0 // Not currently used on Trinity
+//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 // Not currently used on Trinity
+
+#define BLDCFG_VRM_NB_CURRENT_LIMIT 60000
+
+#define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3
+#define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3
+
+#if IS_ENABLED(CONFIG_GFXUMA)
+#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED
+#define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED
+//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/
+#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M
+#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE
+#endif
+
+#define BLDCFG_IOMMU_SUPPORT TRUE
+
+#define BLDCFG_CFG_GNB_HD_AUDIO TRUE
+//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID
+//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID
+//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID
+
+/* Process the options...
+ * This file include MUST occur AFTER the user option selection settings
+ */
+/*
+ * Customized OEM build configurations for FCH component
+ */
+// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00
+// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20
+// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00
+// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400
+// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404
+// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408
+// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410
+// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420
+// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000
+// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000
+// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000
+// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0
+// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00
+// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000
+// #define BLDCFG_AZALIA_SSID 0x780D1022
+// #define BLDCFG_SMBUS_SSID 0x780B1022
+// #define BLDCFG_IDE_SSID 0x780C1022
+// #define BLDCFG_SATA_AHCI_SSID 0x78011022
+// #define BLDCFG_SATA_IDE_SSID 0x78001022
+// #define BLDCFG_SATA_RAID5_SSID 0x78031022
+// #define BLDCFG_SATA_RAID_SSID 0x78021022
+// #define BLDCFG_EHCI_SSID 0x78081022
+// #define BLDCFG_OHCI_SSID 0x78071022
+// #define BLDCFG_LPC_SSID 0x780E1022
+// #define BLDCFG_SD_SSID 0x78061022
+// #define BLDCFG_XHCI_SSID 0x78121022
+// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE
+// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE
+// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4
+// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE
+// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE
+// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE
+// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE
+// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE
+// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE
+// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE
+// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE
+
+CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
+{
+ { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E },
+ { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E },
+ { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 },
+ { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 },
+ { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 },
+ { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 },
+ { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 },
+ { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 },
+ { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 },
+ { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 },
+ { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 },
+ { CPU_LIST_TERMINAL }
+};
+
+#define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList
+
+ // This is the delivery package title, "BrazosPI"
+ // This string MUST be exactly 8 characters long
+#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'}
+
+ // This is the release version number of the AGESA component
+ // This string MUST be exactly 12 characters long
+#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '}
+
+/* MEMORY_BUS_SPEED */
+#define DDR400_FREQUENCY 200 ///< DDR 400
+#define DDR533_FREQUENCY 266 ///< DDR 533
+#define DDR667_FREQUENCY 333 ///< DDR 667
+#define DDR800_FREQUENCY 400 ///< DDR 800
+#define DDR1066_FREQUENCY 533 ///< DDR 1066
+#define DDR1333_FREQUENCY 667 ///< DDR 1333
+#define DDR1600_FREQUENCY 800 ///< DDR 1600
+#define DDR1866_FREQUENCY 933 ///< DDR 1866
+#define DDR2100_FREQUENCY 1050 ///< DDR 2100
+#define DDR2133_FREQUENCY 1066 ///< DDR 2133
+#define DDR2400_FREQUENCY 1200 ///< DDR 2400
+#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency
+
+/* QUANDRANK_TYPE*/
+#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
+#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
+
+/* USER_MEMORY_TIMING_MODE */
+#define TIMING_MODE_AUTO 0 ///< Use best rate possible
+#define TIMING_MODE_LIMITED 1 ///< Set user top limit
+#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
+
+/* POWER_DOWN_MODE */
+#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
+#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
+
+/*
+ * Agesa optional capabilities selection.
+ * Uncomment and mark FALSE those features you wish to include in the build.
+ * Comment out or mark TRUE those features you want to REMOVE from the build.
+ */
+
+#define DFLT_SMBUS0_BASE_ADDRESS 0xB00
+#define DFLT_SMBUS1_BASE_ADDRESS 0xB20
+/* The AGESA likes to enable 512 bytes region on this base for LPC bus */
+#define DFLT_SIO_PME_BASE_ADDRESS 0xE00
+#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800
+#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804
+#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808
+#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810
+#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820
+#define DFLT_SPI_BASE_ADDRESS 0xFEC10000
+#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0
+#define DFLT_HPET_BASE_ADDRESS 0xFED00000
+#define DFLT_SMI_CMD_PORT 0xB0
+#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00
+#define DFLT_GEC_BASE_ADDRESS 0xFED61000
+#define DFLT_AZALIA_SSID 0x780D1022
+#define DFLT_SMBUS_SSID 0x780B1022
+#define DFLT_IDE_SSID 0x780C1022
+#define DFLT_SATA_AHCI_SSID 0x78011022
+#define DFLT_SATA_IDE_SSID 0x78001022
+#define DFLT_SATA_RAID5_SSID 0x78031022
+#define DFLT_SATA_RAID_SSID 0x78021022
+#define DFLT_EHCI_SSID 0x78081022
+#define DFLT_OHCI_SSID 0x78071022
+#define DFLT_LPC_SSID 0x780E1022
+#define DFLT_SD_SSID 0x78061022
+#define DFLT_XHCI_SSID 0x78121022
+#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE
+#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE
+#define DFLT_FCH_GPP_LINK_CONFIG PortA1B1C1D1
+#define DFLT_FCH_GPP_PORT0_PRESENT TRUE
+#define DFLT_FCH_GPP_PORT1_PRESENT TRUE
+#define DFLT_FCH_GPP_PORT2_PRESENT FALSE
+#define DFLT_FCH_GPP_PORT3_PRESENT FALSE
+#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE
+#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE
+#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE
+#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE
+//#define BLDCFG_IR_PIN_CONTROL 0x33
+//#define FCH_NO_XHCI_SUPPORT FALSE
+GPIO_CONTROL a88xm_e_gpio[] = {
+// {183, Function1, PullUpB},
+ {-1}
+};
+#define BLDCFG_FCH_GPIO_CONTROL_LIST (&a88xm_e_gpio[0])
+
+// The following definitions specify the default values for various parameters in which there are
+// no clearly defined defaults to be used in the common file. The values below are based on product
+// and BKDG content, please consult the AGESA Memory team for consultation.
+#define DFLT_SCRUB_DRAM_RATE (0)
+#define DFLT_SCRUB_L2_RATE (0)
+#define DFLT_SCRUB_L3_RATE (0)
+#define DFLT_SCRUB_IC_RATE (0)
+#define DFLT_SCRUB_DC_RATE (0)
+#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
+#define DFLT_VRM_SLEW_RATE (5000)
+
+/* Moving this include up will break AGESA. */
+#include <PlatformInstall.h>
diff --git a/src/mainboard/asus/a88xm-e/cmos.layout b/src/mainboard/asus/a88xm-e/cmos.layout
new file mode 100644
index 0000000..e1dbd9a
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/cmos.layout
@@ -0,0 +1,66 @@
+#*****************************************************************************
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#*****************************************************************************
+
+entries
+
+0 384 r 0 reserved_memory
+384 1 e 4 boot_option
+388 4 h 0 reboot_counter
+#392 3 r 0 unused
+395 1 e 1 hw_scrubber
+396 1 e 1 interleave_chip_selects
+397 2 e 8 max_mem_clock
+399 1 e 2 multi_core
+400 1 e 1 power_on_after_fail
+412 4 e 6 debug_level
+440 4 e 9 slow_cpu
+444 1 e 1 nmi
+445 1 e 1 iommu
+456 1 e 1 ECC_memory
+728 256 h 0 user_data
+984 16 h 0 check_sum
+# Reserve the extended AMD configuration registers
+1000 24 r 0 amd_reserved
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+6 5 Notice
+6 6 Info
+6 7 Debug
+6 8 Spew
+8 0 400Mhz
+8 1 333Mhz
+8 2 266Mhz
+8 3 200Mhz
+9 0 off
+9 1 87.5%
+9 2 75.0%
+9 3 62.5%
+9 4 50.0%
+9 5 37.5%
+9 6 25.0%
+9 7 12.5%
+
+checksums
+
+checksum 392 983 984
diff --git a/src/mainboard/asus/a88xm-e/devicetree_a88xm-e.cb b/src/mainboard/asus/a88xm-e/devicetree_a88xm-e.cb
new file mode 100644
index 0000000..e2b0eea
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/devicetree_a88xm-e.cb
@@ -0,0 +1,143 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+chip northbridge/amd/agesa/family15tn/root_complex
+
+ device cpu_cluster 0 on
+ chip cpu/amd/agesa/family15tn
+ device lapic 10 on end
+ end
+ end
+
+ device domain 0 on
+ subsystemid 0x1022 0x1410 inherit
+ chip northbridge/amd/agesa/family15tn # CPU side of HT root complex
+
+ chip northbridge/amd/agesa/family15tn # PCI side of HT root complex
+ device pci 0.0 on end # Root Complex
+ device pci 0.2 on end # IOMMU
+ device pci 1.0 on end # Internal Graphics
+ device pci 1.1 on end # Internal Audio (iGPU)
+ device pci 2.0 on end # PCIE x4/x16 yellow (?)
+ device pci 3.0 on end # unused?
+ device pci 4.0 on end # PCIE x4/x16 yellow (?)
+ device pci 5.0 off end # unused
+ device pci 6.0 off end # unused?
+ device pci 7.0 off end # LAN
+ device pci 8.0 off end # NB/SB Link P2P bridge
+ end #chip northbridge/amd/agesa/family15tn # PCI side of HT root complex
+
+ chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus
+ device pci 10.0 on end # XHCI HC0
+ device pci 10.1 on end # XHCI HC1
+ device pci 11.0 on end # SATA
+ device pci 12.0 on end # USB
+ device pci 12.2 on end # USB
+ device pci 13.0 on end # USB
+ device pci 13.2 on end # USB
+ device pci 14.0 on # SMBUS
+ chip drivers/generic/generic #dimm 0
+ device i2c 50 on end # 7-bit SPD address
+ end
+ chip drivers/generic/generic #dimm 1
+ device i2c 51 on end # 7-bit SPD address
+ end
+ end # SM
+ device pci 14.1 off end # IDE 0x439c
+ device pci 14.2 on end # HDA 0x4383
+ device pci 14.3 on # LPC 0x439d
+ chip superio/ite/it8728f
+ register "TMPIN1.mode" = "THERMAL_RESISTOR"
+ register "TMPIN2.mode" = "THERMAL_RESISTOR"
+ register "TMPIN3.mode" = "THERMAL_RESISTOR"
+
+ register "FAN1.mode" = "FAN_SMART_AUTOMATIC"
+ register "FAN1.smart.tmpin" = "1"
+ register "FAN1.smart.tmp_off" = "0x80" # never
+ register "FAN1.smart.tmp_start" = "20"
+ register "FAN1.smart.tmp_full" = "70"
+ register "FAN1.smart.tmp_delta" = "0"
+ register "FAN1.smart.smoothing" = "1"
+ register "FAN1.smart.pwm_start" = "20"
+ register "FAN1.smart.slope" = "32"
+
+ # Enable tacho reading for chassis fan.
+ register "FAN2.mode" = "FAN_MODE_OFF"
+
+ device pnp 2e.0 off # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.2 off # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.3 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.4 on # Env Controller
+ io 0x60 = 0x290
+ io 0x62 = 0x220
+ irq 0x70 = 0
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ end
+ device pnp 2e.6 off # Mouse
+ irq 0x70 = 12
+ end
+ device pnp 2e.7 on # GPIO
+ io 0x60 = 0x228 #SMI
+ io 0x62 = 0x300 #Simple I/O
+ io 0x64 = 0x238 #Phony resource IT8603E does not have it
+ irq 0x70 = 0
+ end
+ device pnp 2e.a off end # CIR
+ end #superio/ite/it8728f
+ end #
+ device pci 14.3 off end # LPC
+ device pci 14.4 on end # PCI 0x4384
+ device pci 14.5 off end # USB 2
+ device pci 14.6 off end # Gec
+ device pci 14.7 off end # SD
+ device pci 15.0 on end # PCIe 0 - onboard PCIe 1x
+ device pci 15.1 off end # unused
+ device pci 15.2 on end # PCI bridge
+ device pci 15.3 off end # unused
+ end #chip southbridge/amd/agesa/hudson
+
+ device pci 18.0 on end
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ device pci 18.4 on end
+ device pci 18.5 on end
+
+ register "spdAddrLookup" = "
+ {
+ { {0xA0, 0x00}, {0xA2, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
+ { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
+ }"
+
+ end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex
+ end #domain
+end #chip northbridge/amd/agesa/family15tn/root_complex
diff --git a/src/mainboard/asus/a88xm-e/dsdt.asl b/src/mainboard/asus/a88xm-e/dsdt.asl
new file mode 100644
index 0000000..45a2606
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/dsdt.asl
@@ -0,0 +1,110 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* DefinitionBlock Statement */
+#include <arch/acpi.h>
+DefinitionBlock (
+ "DSDT.AML", /* Output filename */
+ "DSDT", /* Signature */
+ 0x02, /* DSDT Revision, needs to be 2 for 64bit */
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x00010001 /* OEM Revision */
+ )
+{ /* Start of ASL file */
+ /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */
+
+ /* Globals for the platform */
+ #include "acpi/mainboard.asl"
+
+ /* Describe the USB Overcurrent pins */
+ #include "acpi/usb_oc.asl"
+
+ /* PCI IRQ mapping for the Southbridge */
+ #include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
+
+ /* Describe the processor tree (\_PR) */
+ #include <cpu/amd/agesa/family15tn/acpi/cpu.asl>
+
+ /* Describe the supported Sleep States for this Southbridge */
+ #include <southbridge/amd/common/acpi/sleepstates.asl>
+
+ /* Describe the Sleep Methods (WAK, PTS, GTS, etc.) for this platform */
+ #include "acpi/sleep.asl"
+
+ Scope(\_SB) {
+ /* global utility methods expected within the \_SB scope */
+ #include <arch/x86/acpi/globutil.asl>
+
+ /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
+ #include "acpi/routing.asl"
+
+ Device(PWRB) {
+ Name(_HID, EISAID("PNP0C0C"))
+ Name(_UID, 0xAA)
+ Name(_PRW, Package () {3, 0x04})
+ Name(_STA, 0x0B)
+ }
+
+ Device(PCI0) {
+ /* Describe the AMD Northbridge */
+ #include <northbridge/amd/agesa/family15tn/acpi/northbridge.asl>
+
+ /* Describe the AMD Fusion Controller Hub Southbridge */
+ #include <southbridge/amd/agesa/hudson/acpi/fch.asl>
+
+ /**
+ * TODO: The devices listed here (SBR0 and SBR1) do not appear to
+ * be referenced anywhere and could possibly be removed.
+ */
+ Device(SBR0) { /* PCIe 1x SB */
+ Name(_ADR, 0x00150000)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(ABR0) } /* APIC mode */
+ Return (PBR0) /* PIC mode */
+ }
+ }
+
+ Device(SBR1) { /* Onboard network */
+ Name(_ADR, 0x00150001)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT, 0) {
+ If(PMOD){ Return(ABR1) } /* APIC mode */
+ Return (PBR1) /* PIC mode */
+ }
+ }
+ }
+
+ /* Describe PCI INT[A-H] for the Southbridge */
+ #include <southbridge/amd/agesa/hudson/acpi/pci_int.asl>
+
+ } /* End Scope(_SB) */
+
+ /* Describe SMBUS for the Southbridge */
+ #include <southbridge/amd/agesa/hudson/acpi/smbus.asl>
+
+ /* Define the General Purpose Events for the platform */
+ #include "acpi/gpe.asl"
+
+ /* Define the Thermal zones and methods for the platform */
+ #include "acpi/thermal.asl"
+
+ /* Define the System Indicators for the platform */
+ #include "acpi/si.asl"
+
+}
+/* End of ASL file */
diff --git a/src/mainboard/asus/a88xm-e/irq_tables.c b/src/mainboard/asus/a88xm-e/irq_tables.c
new file mode 100644
index 0000000..88d2160
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/irq_tables.c
@@ -0,0 +1,101 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/pirq_routing.h>
+#include <console/console.h>
+#include <device/pci_def.h>
+#include <stdint.h>
+#include <string.h>
+
+static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
+ u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
+ u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
+ u8 slot, u8 rfu)
+{
+ pirq_info->bus = bus;
+ pirq_info->devfn = devfn;
+ pirq_info->irq[0].link = link0;
+ pirq_info->irq[0].bitmap = bitmap0;
+ pirq_info->irq[1].link = link1;
+ pirq_info->irq[1].bitmap = bitmap1;
+ pirq_info->irq[2].link = link2;
+ pirq_info->irq[2].bitmap = bitmap2;
+ pirq_info->irq[3].link = link3;
+ pirq_info->irq[3].bitmap = bitmap3;
+ pirq_info->slot = slot;
+ pirq_info->rfu = rfu;
+}
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+ struct irq_routing_table *pirq;
+ struct irq_info *pirq_info;
+ u32 slot_num;
+ u8 *v;
+
+ u8 sum = 0;
+ int i;
+
+ /* Align the table to be 16 byte aligned. */
+ addr += 15;
+ addr &= ~15;
+
+ /* This table must be between 0xf0000 & 0x100000 */
+ printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
+
+ pirq = (void *)(addr);
+ v = (u8 *) (addr);
+
+ pirq->signature = PIRQ_SIGNATURE;
+ pirq->version = PIRQ_VERSION;
+
+ pirq->rtr_bus = 0;
+ pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
+
+ pirq->exclusive_irqs = 0;
+
+ pirq->rtr_vendor = 0x1002;
+ pirq->rtr_device = 0x4384;
+
+ pirq->miniport_data = 0;
+
+ memset(pirq->rfu, 0, sizeof(pirq->rfu));
+
+ pirq_info = (void *)(&pirq->checksum + 1);
+ slot_num = 0;
+
+ /* pci bridge */
+ write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4),
+ 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
+ 0);
+ pirq_info++;
+
+ slot_num++;
+
+ pirq->size = 32 + 16 * slot_num;
+
+ for (i = 0; i < pirq->size; i++)
+ sum += v[i];
+
+ sum = pirq->checksum - sum;
+
+ if (sum != pirq->checksum) {
+ pirq->checksum = sum;
+ }
+
+ printk(BIOS_INFO, "write_pirq_routing_table done.\n");
+
+ return (unsigned long)pirq_info;
+}
diff --git a/src/mainboard/asus/a88xm-e/mainboard.c b/src/mainboard/asus/a88xm-e/mainboard.c
new file mode 100644
index 0000000..2a0e618
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/mainboard.c
@@ -0,0 +1,46 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/msr.h>
+#include <device/device.h>
+
+/*************************************************
+ * enable the dedicated function in thatcher board.
+ *************************************************/
+static void mainboard_enable(struct device *dev)
+{
+ msr_t msr;
+
+ printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
+
+ msr = rdmsr(LS_CFG_MSR);
+ msr.lo &= ~(1 << 28);
+ wrmsr(LS_CFG_MSR, msr);
+
+ msr = rdmsr(DC_CFG_MSR);
+ msr.lo &= ~(1 << 4);
+ msr.lo &= ~(1 << 13);
+ wrmsr(DC_CFG_MSR, msr);
+
+ msr = rdmsr(BU_CFG_MSR);
+ msr.lo &= ~(1 << 23);
+ wrmsr(BU_CFG_MSR, msr);
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/asus/a88xm-e/mptable.c b/src/mainboard/asus/a88xm-e/mptable.c
new file mode 100644
index 0000000..d97663d
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/mptable.c
@@ -0,0 +1,181 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <arch/ioapic.h>
+#include <arch/smp/mpspec.h>
+#include <cpu/x86/lapic.h>
+#include <device/pci.h>
+#include <stdint.h>
+#include <string.h>
+#include <southbridge/amd/agesa/hudson/hudson.h>
+
+u8 picr_data[] = {
+ 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
+ 0x09,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x1F,0x1F,0x1F,0x1F
+};
+u8 intr_data[0x54] = {
+ 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
+ 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x10,0x11,0x12,0x13
+};
+
+static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length)
+{
+ mc->mpc_length += length;
+ mc->mpc_entry_count++;
+}
+
+static void my_smp_write_bus(struct mp_config_table *mc,
+ unsigned char id, const char *bustype)
+{
+ struct mpc_config_bus *mpc;
+ mpc = smp_next_mpc_entry(mc);
+ memset(mpc, '\0', sizeof(*mpc));
+ mpc->mpc_type = MP_BUS;
+ mpc->mpc_busid = id;
+ memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
+ smp_add_mpc_entry(mc, sizeof(*mpc));
+}
+
+static void *smp_write_config_table(void *v)
+{
+ struct mp_config_table *mc;
+ int bus_isa;
+ u8 byte;
+
+ /*
+ * By the time this function gets called, the IOAPIC registers
+ * have been written so they can be read to get the correct
+ * APIC ID and Version
+ */
+ u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
+
+ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+
+ mptable_init(mc, LOCAL_APIC_ADDR);
+ memcpy(mc->mpc_oem, "AMD ", 8);
+
+ smp_write_processors(mc);
+
+ //mptable_write_buses(mc, NULL, &bus_isa);
+ my_smp_write_bus(mc, 0, "PCI ");
+ my_smp_write_bus(mc, 1, "PCI ");
+ bus_isa = 0x02;
+ my_smp_write_bus(mc, bus_isa, "ISA ");
+
+ /* I/O APICs: APIC ID Version State Address */
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
+
+ /* PIC IRQ routine */
+ for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
+ outb(byte, 0xC00);
+ outb(picr_data[byte], 0xC01);
+ }
+
+ /* APIC IRQ routine */
+ for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
+ outb(byte | 0x80, 0xC00);
+ outb(intr_data[byte], 0xC01);
+ }
+
+ /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
+#define IO_LOCAL_INT(type, intr, apicid, pin) \
+ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
+ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
+
+ /* PCI interrupts are level triggered, and are
+ * associated with a specific bus/device/function tuple.
+ */
+#define PCI_INT(bus, dev, int_sign, pin) \
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
+
+ /* IOMMU */
+ PCI_INT(0x0, 0x0, 0x0, 0x10);
+ PCI_INT(0x0, 0x0, 0x1, 0x11);
+ PCI_INT(0x0, 0x0, 0x2, 0x12);
+ PCI_INT(0x0, 0x0, 0x3, 0x13);
+
+ /* Internal VGA */
+ PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
+ PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
+
+ /* SMBUS */
+ PCI_INT(0x0, 0x14, 0x0, 0x10);
+
+ /* HD Audio */
+ PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]);
+
+ /* USB */
+ PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]);
+ PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
+ PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
+ PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
+ PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
+ PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
+ PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]);
+
+ /* sata */
+ PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]);
+ PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
+
+ /* on board NIC & Slot PCIE. */
+
+ /* PCI slots */
+ struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+ }
+
+ /* PCIe Lan*/
+ PCI_INT(0x0, 0x06, 0x0, 0x13);
+
+ /* FCH PCIe PortA */
+ PCI_INT(0x0, 0x15, 0x0, 0x10);
+ /* FCH PCIe PortB */
+ PCI_INT(0x0, 0x15, 0x1, 0x11);
+ /* FCH PCIe PortC */
+ PCI_INT(0x0, 0x15, 0x2, 0x12);
+ /* FCH PCIe PortD */
+ PCI_INT(0x0, 0x15, 0x3, 0x13);
+
+ /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
+ IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
+ IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
+ /* There is no extension information... */
+
+ /* Compute the checksums */
+ return mptable_finalize(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+ void *v;
+ v = smp_write_floating_table(addr, 0);
+ return (unsigned long)smp_write_config_table(v);
+}
diff --git a/src/mainboard/asus/a88xm-e/romstage.c b/src/mainboard/asus/a88xm-e/romstage.c
new file mode 100644
index 0000000..0a85c27
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/romstage.c
@@ -0,0 +1,102 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2012 Rudolf Marek <r.marek(a)assembler.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+
+#include <northbridge/amd/agesa/state_machine.h>
+#include <southbridge/amd/common/amd_defs.h>
+#include <southbridge/amd/agesa/hudson/hudson.h>
+#include <southbridge/amd/agesa/hudson/smbus.h>
+#include <stdint.h>
+#include <string.h>
+
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8728f/it8728f.h>
+
+#define MMIO_NON_POSTED_START 0xfed00000
+#define MMIO_NON_POSTED_END 0xfedfffff
+#define SB_MMIO_MISC32(x) *(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR + 0xE00 + (x))
+
+static void sbxxx_enable_48mhzout(void)
+{
+ /* most likely programming to 48MHz out signal */
+ u32 reg32;
+ reg32 = SB_MMIO_MISC32(0x28);
+ reg32 &= 0xffc7ffff;
+ reg32 |= 0x00100000;
+ SB_MMIO_MISC32(0x28) = reg32;
+
+ reg32 = SB_MMIO_MISC32(0x40);
+ reg32 &= ~0x80u;
+ SB_MMIO_MISC32(0x40) = reg32;
+}
+
+static void superio_init_e(void)
+{
+ pnp_devfn_t uart = PNP_DEV(0x2e, IT8728F_SP1);
+ pnp_devfn_t gpio = PNP_DEV(0x2e, IT8728F_GPIO);
+
+ ite_kill_watchdog(gpio);
+ ite_enable_serial(uart, CONFIG_TTYS0_BASE);
+ ite_enable_3vsbsw(gpio);
+}
+
+void board_BeforeAgesa(struct sysinfo *cb)
+{
+ u8 byte;
+ pci_devfn_t dev;
+
+ if (IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE))
+ hudson_pci_port80();
+ else if (IS_ENABLED(CONFIG_POST_DEVICE_LPC))
+ hudson_lpc_port80();
+
+ /* enable SIO LPC decode */
+ dev = PCI_DEV(0, 0x14, 3);
+ byte = pci_read_config8(dev, 0x48);
+ byte |= 3; /* 2e, 2f */
+ pci_write_config8(dev, 0x48, byte);
+
+ /* enable serial decode */
+ byte = pci_read_config8(dev, 0x44);
+ byte |= (1 << 6); /* 0x3f8 */
+ pci_write_config8(dev, 0x44, byte);
+
+ post_code(0x30);
+
+ /* enable SB MMIO space */
+ outb(0x24, 0xcd6);
+ outb(0x1, 0xcd7);
+
+ /* enable SIO clock */
+ sbxxx_enable_48mhzout();
+
+ if (IS_ENABLED(CONFIG_BOARD_ASUS_A88XM_E))
+ superio_init_e();
+
+ /* turn on secondary smbus at b20 */
+ outb(0x28, 0xcd6);
+ byte = inb(0xcd7);
+ byte |= 1;
+ outb(byte, 0xcd7);
+
+ /* set DDR3 voltage */
+ byte = CONFIG_BOARD_ASUS_A88XM_E_DDR3_VOLT_VAL;
+
+ /* default is byte = 0x0, so no need to set it in this case */
+ if (byte)
+ do_smbus_write_byte(0xb20, 0x15, 0x3, byte);
+}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I60fa0636ba41f5f1a6a3faa2764bf2f0a968cf90
Gerrit-Change-Number: 30987
Gerrit-PatchSet: 1
Gerrit-Owner: Balázs Vinarz <vinibali1(a)gmail.com>
Gerrit-MessageType: newchange
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