Change in ...coreboot[master]: mb/*/romstage: Drop defines already set by raminit code
by Patrick Rudolph (Code Review)
Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32070
Change subject: mb/*/romstage: Drop defines already set by raminit code
......................................................................
mb/*/romstage: Drop defines already set by raminit code
Drop defines that are set by raminit code.
Change-Id: Ica844a70b50486b4db3744cb123b3e4b8d5bedb0
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/mainboard/asrock/h81m-hds/romstage.c
M src/mainboard/google/beltino/romstage.c
M src/mainboard/google/butterfly/romstage.c
M src/mainboard/google/link/romstage.c
M src/mainboard/google/parrot/romstage.c
M src/mainboard/google/slippy/variants/falco/romstage.c
M src/mainboard/google/slippy/variants/leon/romstage.c
M src/mainboard/google/slippy/variants/peppy/romstage.c
M src/mainboard/google/slippy/variants/wolf/romstage.c
M src/mainboard/google/stout/romstage.c
M src/mainboard/intel/dcp847ske/romstage.c
M src/mainboard/intel/emeraldlake2/romstage.c
M src/mainboard/kontron/ktqm77/romstage.c
M src/mainboard/lenovo/x220/romstage.c
M src/mainboard/roda/rv11/variants/rv11/romstage.c
M src/mainboard/roda/rv11/variants/rw11/romstage.c
M src/mainboard/samsung/lumpy/romstage.c
M src/mainboard/samsung/stumpy/romstage.c
M src/mainboard/supermicro/x10slm-f/romstage.c
19 files changed, 0 insertions(+), 265 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/32070/1
diff --git a/src/mainboard/asrock/h81m-hds/romstage.c b/src/mainboard/asrock/h81m-hds/romstage.c
index a917722..68ed658 100644
--- a/src/mainboard/asrock/h81m-hds/romstage.c
+++ b/src/mainboard/asrock/h81m-hds/romstage.c
@@ -74,20 +74,6 @@
{
struct pei_data pei_data = {
.pei_version = PEI_VERSION,
- .mchbar = (uintptr_t)DEFAULT_MCHBAR,
- .dmibar = (uintptr_t)DEFAULT_DMIBAR,
- .epbar = DEFAULT_EPBAR,
- .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
- .wdbbar = 0x4000000,
- .wdbsize = 0x1000,
- .hpet_address = HPET_ADDR,
- .rcba = (uintptr_t)DEFAULT_RCBA,
- .pmbase = DEFAULT_PMBASE,
- .gpiobase = DEFAULT_GPIOBASE,
- .temp_mmio_base = 0xfed08000,
- .system_type = 1, /* desktop/server */
- .tseg_size = CONFIG_SMM_TSEG_SIZE,
.spd_addresses = { 0xa0, 0x00, 0xa4, 0x00 },
.ec_present = 0,
.dimm_channel0_disabled = 2, /* Disable DIMM 1 on channel 0. */
diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c
index 70a8c19..6417f0d 100644
--- a/src/mainboard/google/beltino/romstage.c
+++ b/src/mainboard/google/beltino/romstage.c
@@ -71,20 +71,6 @@
{
struct pei_data pei_data = {
.pei_version = PEI_VERSION,
- .mchbar = (uintptr_t)DEFAULT_MCHBAR,
- .dmibar = (uintptr_t)DEFAULT_DMIBAR,
- .epbar = DEFAULT_EPBAR,
- .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
- .wdbbar = 0x4000000,
- .wdbsize = 0x1000,
- .hpet_address = HPET_ADDR,
- .rcba = (uintptr_t)DEFAULT_RCBA,
- .pmbase = DEFAULT_PMBASE,
- .gpiobase = DEFAULT_GPIOBASE,
- .temp_mmio_base = 0xfed08000,
- .system_type = 5, /* ULT */
- .tseg_size = CONFIG_SMM_TSEG_SIZE,
.spd_addresses = { 0xa0, 0x00, 0xa4, 0x00 },
.ec_present = 0,
// 0 = leave channel enabled
diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c
index d34b1e4..cbd9f3d 100644
--- a/src/mainboard/google/butterfly/romstage.c
+++ b/src/mainboard/google/butterfly/romstage.c
@@ -132,20 +132,6 @@
{
struct pei_data pei_data_template = {
.pei_version = PEI_VERSION,
- .mchbar = (uintptr_t)DEFAULT_MCHBAR,
- .dmibar = (uintptr_t)DEFAULT_DMIBAR,
- .epbar = DEFAULT_EPBAR,
- .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
- .wdbbar = 0x4000000,
- .wdbsize = 0x1000,
- .hpet_address = CONFIG_HPET_ADDRESS,
- .rcba = (uintptr_t)DEFAULT_RCBABASE,
- .pmbase = DEFAULT_PMBASE,
- .gpiobase = DEFAULT_GPIOBASE,
- .thermalbase = 0xfed08000,
- .system_type = 0, // 0 Mobile, 1 Desktop/Server
- .tseg_size = CONFIG_SMM_TSEG_SIZE,
.spd_addresses = { 0xA0, 0x00,0xA4,0x00 },
.ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
.ec_present = 1,
diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c
index 66a503d0..6617dc4 100644
--- a/src/mainboard/google/link/romstage.c
+++ b/src/mainboard/google/link/romstage.c
@@ -127,20 +127,6 @@
{
struct pei_data pei_data_template = {
.pei_version = PEI_VERSION,
- .mchbar = (uintptr_t)DEFAULT_MCHBAR,
- .dmibar = (uintptr_t)DEFAULT_DMIBAR,
- .epbar = DEFAULT_EPBAR,
- .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
- .wdbbar = 0x4000000,
- .wdbsize = 0x1000,
- .hpet_address = CONFIG_HPET_ADDRESS,
- .rcba = (uintptr_t)DEFAULT_RCBABASE,
- .pmbase = DEFAULT_PMBASE,
- .gpiobase = DEFAULT_GPIOBASE,
- .thermalbase = 0xfed08000,
- .system_type = 0, // 0 Mobile, 1 Desktop/Server
- .tseg_size = CONFIG_SMM_TSEG_SIZE,
.ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
.ec_present = 1,
.ddr3lv_support = 1,
diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c
index 76a4b4b..d76d814 100644
--- a/src/mainboard/google/parrot/romstage.c
+++ b/src/mainboard/google/parrot/romstage.c
@@ -101,20 +101,6 @@
{
struct pei_data pei_data_template = {
.pei_version = PEI_VERSION,
- .mchbar = (uintptr_t)DEFAULT_MCHBAR,
- .dmibar = (uintptr_t)DEFAULT_DMIBAR,
- .epbar = DEFAULT_EPBAR,
- .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
- .wdbbar = 0x4000000,
- .wdbsize = 0x1000,
- .hpet_address = CONFIG_HPET_ADDRESS,
- .rcba = (uintptr_t)DEFAULT_RCBABASE,
- .pmbase = DEFAULT_PMBASE,
- .gpiobase = DEFAULT_GPIOBASE,
- .thermalbase = 0xfed08000,
- .system_type = 0, // 0 Mobile, 1 Desktop/Server
- .tseg_size = CONFIG_SMM_TSEG_SIZE,
.spd_addresses = { 0xA0, 0x00,0xA4,0x00 },
.ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
.ec_present = 1,
diff --git a/src/mainboard/google/slippy/variants/falco/romstage.c b/src/mainboard/google/slippy/variants/falco/romstage.c
index 25f8d27..2244119 100644
--- a/src/mainboard/google/slippy/variants/falco/romstage.c
+++ b/src/mainboard/google/slippy/variants/falco/romstage.c
@@ -109,20 +109,6 @@
{
struct pei_data pei_data = {
.pei_version = PEI_VERSION,
- .mchbar = (uintptr_t)DEFAULT_MCHBAR,
- .dmibar = (uintptr_t)DEFAULT_DMIBAR,
- .epbar = DEFAULT_EPBAR,
- .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
- .wdbbar = 0x4000000,
- .wdbsize = 0x1000,
- .hpet_address = HPET_ADDR,
- .rcba = (uintptr_t)DEFAULT_RCBA,
- .pmbase = DEFAULT_PMBASE,
- .gpiobase = DEFAULT_GPIOBASE,
- .temp_mmio_base = 0xfed08000,
- .system_type = 5, /* ULT */
- .tseg_size = CONFIG_SMM_TSEG_SIZE,
.spd_addresses = { 0xff, 0x00, 0xff, 0x00 },
.ec_present = 1,
// 0 = leave channel enabled
diff --git a/src/mainboard/google/slippy/variants/leon/romstage.c b/src/mainboard/google/slippy/variants/leon/romstage.c
index b95c6e1..35345d0 100644
--- a/src/mainboard/google/slippy/variants/leon/romstage.c
+++ b/src/mainboard/google/slippy/variants/leon/romstage.c
@@ -106,20 +106,6 @@
{
struct pei_data pei_data = {
.pei_version = PEI_VERSION,
- .mchbar = (uintptr_t)DEFAULT_MCHBAR,
- .dmibar = (uintptr_t)DEFAULT_DMIBAR,
- .epbar = DEFAULT_EPBAR,
- .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
- .wdbbar = 0x4000000,
- .wdbsize = 0x1000,
- .hpet_address = HPET_ADDR,
- .rcba = (uintptr_t)DEFAULT_RCBA,
- .pmbase = DEFAULT_PMBASE,
- .gpiobase = DEFAULT_GPIOBASE,
- .temp_mmio_base = 0xfed08000,
- .system_type = 5, /* ULT */
- .tseg_size = CONFIG_SMM_TSEG_SIZE,
.spd_addresses = { 0xff, 0x00, 0xff, 0x00 },
.ec_present = 1,
// 0 = leave channel enabled
diff --git a/src/mainboard/google/slippy/variants/peppy/romstage.c b/src/mainboard/google/slippy/variants/peppy/romstage.c
index e47edc7..a5de6c0 100644
--- a/src/mainboard/google/slippy/variants/peppy/romstage.c
+++ b/src/mainboard/google/slippy/variants/peppy/romstage.c
@@ -124,20 +124,6 @@
{
struct pei_data pei_data = {
.pei_version = PEI_VERSION,
- .mchbar = (uintptr_t)DEFAULT_MCHBAR,
- .dmibar = (uintptr_t)DEFAULT_DMIBAR,
- .epbar = DEFAULT_EPBAR,
- .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
- .wdbbar = 0x4000000,
- .wdbsize = 0x1000,
- .hpet_address = HPET_ADDR,
- .rcba = (uintptr_t)DEFAULT_RCBA,
- .pmbase = DEFAULT_PMBASE,
- .gpiobase = DEFAULT_GPIOBASE,
- .temp_mmio_base = 0xfed08000,
- .system_type = 5, /* ULT */
- .tseg_size = CONFIG_SMM_TSEG_SIZE,
.spd_addresses = { 0xff, 0x00, 0xff, 0x00 },
.ec_present = 1,
// 0 = leave channel enabled
diff --git a/src/mainboard/google/slippy/variants/wolf/romstage.c b/src/mainboard/google/slippy/variants/wolf/romstage.c
index 3125efe..5a8c972 100644
--- a/src/mainboard/google/slippy/variants/wolf/romstage.c
+++ b/src/mainboard/google/slippy/variants/wolf/romstage.c
@@ -111,20 +111,7 @@
{
struct pei_data pei_data = {
.pei_version = PEI_VERSION,
- .mchbar = (uintptr_t)DEFAULT_MCHBAR,
- .dmibar = (uintptr_t)DEFAULT_DMIBAR,
- .epbar = DEFAULT_EPBAR,
- .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
- .wdbbar = 0x4000000,
- .wdbsize = 0x1000,
- .hpet_address = HPET_ADDR,
- .rcba = (uintptr_t)DEFAULT_RCBA,
- .pmbase = DEFAULT_PMBASE,
- .gpiobase = DEFAULT_GPIOBASE,
- .temp_mmio_base = 0xfed08000,
.system_type = 5, /* ULT */
- .tseg_size = CONFIG_SMM_TSEG_SIZE,
.spd_addresses = { 0xff, 0x00, 0xff, 0x00 },
.ec_present = 1,
// 0 = leave channel enabled
diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c
index 7539dd7..6e32145 100644
--- a/src/mainboard/google/stout/romstage.c
+++ b/src/mainboard/google/stout/romstage.c
@@ -137,20 +137,6 @@
{
struct pei_data pei_data_template = {
.pei_version = PEI_VERSION,
- .mchbar = (uintptr_t)DEFAULT_MCHBAR,
- .dmibar = (uintptr_t)DEFAULT_DMIBAR,
- .epbar = DEFAULT_EPBAR,
- .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
- .wdbbar = 0x4000000,
- .wdbsize = 0x1000,
- .hpet_address = CONFIG_HPET_ADDRESS,
- .rcba = (uintptr_t)DEFAULT_RCBABASE,
- .pmbase = DEFAULT_PMBASE,
- .gpiobase = DEFAULT_GPIOBASE,
- .thermalbase = 0xfed08000,
- .system_type = 0, // 0 Mobile, 1 Desktop/Server
- .tseg_size = CONFIG_SMM_TSEG_SIZE,
.spd_addresses = { 0xA0, 0x00,0xA4,0x00 },
.ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
.ec_present = 1,
diff --git a/src/mainboard/intel/dcp847ske/romstage.c b/src/mainboard/intel/dcp847ske/romstage.c
index 24ec912..2043cf6 100644
--- a/src/mainboard/intel/dcp847ske/romstage.c
+++ b/src/mainboard/intel/dcp847ske/romstage.c
@@ -29,20 +29,6 @@
{
struct pei_data pei_data_template = {
.pei_version = PEI_VERSION,
- .mchbar = (uintptr_t)DEFAULT_MCHBAR,
- .dmibar = (uintptr_t)DEFAULT_DMIBAR,
- .epbar = DEFAULT_EPBAR,
- .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
- .wdbbar = 0x4000000,
- .wdbsize = 0x1000,
- .hpet_address = CONFIG_HPET_ADDRESS,
- .rcba = (uintptr_t)DEFAULT_RCBABASE,
- .pmbase = DEFAULT_PMBASE,
- .gpiobase = DEFAULT_GPIOBASE,
- .thermalbase = 0xfed08000,
- .system_type = 0, // 0 Mobile, 1 Desktop/Server
- .tseg_size = CONFIG_SMM_TSEG_SIZE,
.spd_addresses = { 0xa0, 0x00, 0xa2, 0x00 },
.ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
.ec_present = 0,
diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c
index 9a9fc24..8cd7ec2 100644
--- a/src/mainboard/intel/emeraldlake2/romstage.c
+++ b/src/mainboard/intel/emeraldlake2/romstage.c
@@ -94,20 +94,6 @@
{
struct pei_data pei_data_template = {
.pei_version = PEI_VERSION,
- .mchbar = (uintptr_t)DEFAULT_MCHBAR,
- .dmibar = (uintptr_t)DEFAULT_DMIBAR,
- .epbar = DEFAULT_EPBAR,
- .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
- .wdbbar = 0x4000000,
- .wdbsize = 0x1000,
- .hpet_address = CONFIG_HPET_ADDRESS,
- .rcba = (uintptr_t)DEFAULT_RCBABASE,
- .pmbase = DEFAULT_PMBASE,
- .gpiobase = DEFAULT_GPIOBASE,
- .thermalbase = 0xfed08000,
- .system_type = 0, // 0 Mobile, 1 Desktop/Server
- .tseg_size = CONFIG_SMM_TSEG_SIZE,
.spd_addresses = { 0xa0, 0x00, 0xa4, 0x00 },
.ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
.ec_present = 0,
diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c
index f778f96..e0f8954 100644
--- a/src/mainboard/kontron/ktqm77/romstage.c
+++ b/src/mainboard/kontron/ktqm77/romstage.c
@@ -80,20 +80,6 @@
{
struct pei_data pei_data_template = {
.pei_version = PEI_VERSION,
- .mchbar = (uintptr_t)DEFAULT_MCHBAR,
- .dmibar = (uintptr_t)DEFAULT_DMIBAR,
- .epbar = DEFAULT_EPBAR,
- .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
- .wdbbar = 0x4000000,
- .wdbsize = 0x1000,
- .hpet_address = CONFIG_HPET_ADDRESS,
- .rcba = (uintptr_t)DEFAULT_RCBABASE,
- .pmbase = DEFAULT_PMBASE,
- .gpiobase = DEFAULT_GPIOBASE,
- .thermalbase = 0xfed08000,
- .system_type = 0, /* 0 Mobile, 1 Desktop/Server */
- .tseg_size = CONFIG_SMM_TSEG_SIZE,
.spd_addresses = { 0xA0, 0x00,0xA4,0x00 },
.ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
.ec_present = 1,
diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c
index a5b0c81..d398d81 100644
--- a/src/mainboard/lenovo/x220/romstage.c
+++ b/src/mainboard/lenovo/x220/romstage.c
@@ -50,20 +50,6 @@
{
struct pei_data pei_data_template = {
.pei_version = PEI_VERSION,
- .mchbar = (uintptr_t)DEFAULT_MCHBAR,
- .dmibar = (uintptr_t)DEFAULT_DMIBAR,
- .epbar = DEFAULT_EPBAR,
- .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
- .wdbbar = 0x4000000,
- .wdbsize = 0x1000,
- .hpet_address = CONFIG_HPET_ADDRESS,
- .rcba = (uintptr_t)DEFAULT_RCBABASE,
- .pmbase = DEFAULT_PMBASE,
- .gpiobase = DEFAULT_GPIOBASE,
- .thermalbase = 0xfed08000,
- .system_type = 0, // 0 Mobile, 1 Desktop/Server
- .tseg_size = CONFIG_SMM_TSEG_SIZE,
.spd_addresses = { 0xa0, 0x00,0xa2,0x00 },
.ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
.ec_present = 1,
diff --git a/src/mainboard/roda/rv11/variants/rv11/romstage.c b/src/mainboard/roda/rv11/variants/rv11/romstage.c
index 685e942..df679f1 100644
--- a/src/mainboard/roda/rv11/variants/rv11/romstage.c
+++ b/src/mainboard/roda/rv11/variants/rv11/romstage.c
@@ -37,20 +37,6 @@
{
const struct pei_data pei_data_template = {
.pei_version = PEI_VERSION,
- .mchbar = (uintptr_t)DEFAULT_MCHBAR,
- .dmibar = (uintptr_t)DEFAULT_DMIBAR,
- .epbar = DEFAULT_EPBAR,
- .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
- .wdbbar = 0x4000000,
- .wdbsize = 0x1000,
- .hpet_address = CONFIG_HPET_ADDRESS,
- .rcba = (uintptr_t)DEFAULT_RCBABASE,
- .pmbase = DEFAULT_PMBASE,
- .gpiobase = DEFAULT_GPIOBASE,
- .thermalbase = 0xfed08000,
- .system_type = 0, // 0 Mobile, 1 Desktop/Server
- .tseg_size = CONFIG_SMM_TSEG_SIZE,
.spd_addresses = { 0xA0, 0x00, 0xA4, 0x00 },
.ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
.ec_present = 1,
diff --git a/src/mainboard/roda/rv11/variants/rw11/romstage.c b/src/mainboard/roda/rv11/variants/rw11/romstage.c
index 97d9d2b..56ac32c 100644
--- a/src/mainboard/roda/rv11/variants/rw11/romstage.c
+++ b/src/mainboard/roda/rv11/variants/rw11/romstage.c
@@ -66,20 +66,6 @@
{
const struct pei_data pei_data_template = {
.pei_version = PEI_VERSION,
- .mchbar = (uintptr_t)DEFAULT_MCHBAR,
- .dmibar = (uintptr_t)DEFAULT_DMIBAR,
- .epbar = DEFAULT_EPBAR,
- .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
- .wdbbar = 0x4000000,
- .wdbsize = 0x1000,
- .hpet_address = CONFIG_HPET_ADDRESS,
- .rcba = (uintptr_t)DEFAULT_RCBABASE,
- .pmbase = DEFAULT_PMBASE,
- .gpiobase = DEFAULT_GPIOBASE,
- .thermalbase = 0xfed08000,
- .system_type = 0, // 0 Mobile, 1 Desktop/Server
- .tseg_size = CONFIG_SMM_TSEG_SIZE,
.spd_addresses = { 0xA0, 0xA2, 0xA4, 0xA6 },
.ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
.ec_present = 1,
diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c
index 1080689..29fe08b 100644
--- a/src/mainboard/samsung/lumpy/romstage.c
+++ b/src/mainboard/samsung/lumpy/romstage.c
@@ -156,20 +156,6 @@
{
struct pei_data pei_data_template = {
.pei_version = PEI_VERSION,
- .mchbar = (uintptr_t)DEFAULT_MCHBAR,
- .dmibar = (uintptr_t)DEFAULT_DMIBAR,
- .epbar = DEFAULT_EPBAR,
- .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
- .wdbbar = 0x4000000,
- .wdbsize = 0x1000,
- .hpet_address = CONFIG_HPET_ADDRESS,
- .rcba = (uintptr_t)DEFAULT_RCBABASE,
- .pmbase = DEFAULT_PMBASE,
- .gpiobase = DEFAULT_GPIOBASE,
- .thermalbase = 0xfed08000,
- .system_type = 0, // 0 Mobile, 1 Desktop/Server
- .tseg_size = CONFIG_SMM_TSEG_SIZE,
.spd_addresses = { 0xa0, 0x00,0x00,0x00 },
.ts_addresses = { 0x30, 0x00, 0x00, 0x00 },
.ec_present = 1,
diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c
index a8e28d6..510efbe 100644
--- a/src/mainboard/samsung/stumpy/romstage.c
+++ b/src/mainboard/samsung/stumpy/romstage.c
@@ -144,20 +144,6 @@
{
struct pei_data pei_data_template = {
.pei_version = PEI_VERSION,
- .mchbar = (uintptr_t)DEFAULT_MCHBAR,
- .dmibar = (uintptr_t)DEFAULT_DMIBAR,
- .epbar = DEFAULT_EPBAR,
- .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
- .wdbbar = 0x4000000,
- .wdbsize = 0x1000,
- .hpet_address = CONFIG_HPET_ADDRESS,
- .rcba = (uintptr_t)DEFAULT_RCBABASE,
- .pmbase = DEFAULT_PMBASE,
- .gpiobase = DEFAULT_GPIOBASE,
- .thermalbase = 0xfed08000,
- .system_type = 0, // 0 Mobile, 1 Desktop/Server
- .tseg_size = CONFIG_SMM_TSEG_SIZE,
.spd_addresses = { 0xa0, 0x00,0xa4,0x00 },
.ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
.ec_present = 0,
diff --git a/src/mainboard/supermicro/x10slm-f/romstage.c b/src/mainboard/supermicro/x10slm-f/romstage.c
index 84ad047..702e8bb 100644
--- a/src/mainboard/supermicro/x10slm-f/romstage.c
+++ b/src/mainboard/supermicro/x10slm-f/romstage.c
@@ -66,20 +66,6 @@
{
struct pei_data pei_data = {
.pei_version = PEI_VERSION,
- .mchbar = (uintptr_t)DEFAULT_MCHBAR,
- .dmibar = (uintptr_t)DEFAULT_DMIBAR,
- .epbar = DEFAULT_EPBAR,
- .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
- .wdbbar = 0x4000000,
- .wdbsize = 0x1000,
- .hpet_address = HPET_ADDR,
- .rcba = (uintptr_t)DEFAULT_RCBA,
- .pmbase = DEFAULT_PMBASE,
- .gpiobase = DEFAULT_GPIOBASE,
- .temp_mmio_base = 0xfed08000,
- .system_type = 1, /* desktop/server */
- .tseg_size = CONFIG_SMM_TSEG_SIZE,
.spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 },
.ec_present = 0,
.ddr_refresh_2x = 1,
--
To view, visit https://review.coreboot.org/c/coreboot/+/32070
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ica844a70b50486b4db3744cb123b3e4b8d5bedb0
Gerrit-Change-Number: 32070
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Gerrit-MessageType: newchange
3 days, 1 hour
- 3
- 12
Change in ...coreboot[master]: configs: Build test experimental x86_64 code
by Patrick Rudolph (Code Review)
Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31472
Change subject: configs: Build test experimental x86_64 code
......................................................................
configs: Build test experimental x86_64 code
Add additional build config to test qemu-i440fx x86_64 code.
Change-Id: I63f7a6e1602728e4d5ff67f9bd702efebe315c16
Signed-off-by: Patrick Rudolph <siro(a)das-labor.org>
---
A configs/config.emulation_qemu_x86_i440fx_x86_64
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/31472/1
diff --git a/configs/config.emulation_qemu_x86_i440fx_x86_64 b/configs/config.emulation_qemu_x86_i440fx_x86_64
new file mode 100644
index 0000000..0ddb3f1
--- /dev/null
+++ b/configs/config.emulation_qemu_x86_i440fx_x86_64
@@ -0,0 +1 @@
+CONFIG_CPU_QEMU_X86_64=y
--
To view, visit https://review.coreboot.org/c/coreboot/+/31472
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I63f7a6e1602728e4d5ff67f9bd702efebe315c16
Gerrit-Change-Number: 31472
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-MessageType: newchange
1 week, 1 day
- 3
- 5
Change in ...coreboot[master]: util/inteltool: Refactoring #2
by Felix Singer (Code Review)
Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31634
Change subject: util/inteltool: Refactoring #2
......................................................................
util/inteltool: Refactoring #2
Change-Id: Ie92a5af141a907251fc847d53c767984949d9312
Signed-off-by: Felix Singer <migy(a)darmstadt.ccc.de>
---
M util/inteltool/Makefile
M util/inteltool/gpio.h
A util/inteltool/gpio_test.c
A util/inteltool/gpio_test.h
4 files changed, 447 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/31634/1
diff --git a/util/inteltool/Makefile b/util/inteltool/Makefile
index d88063b..0097831 100644
--- a/util/inteltool/Makefile
+++ b/util/inteltool/Makefile
@@ -28,7 +28,7 @@
CPPFLAGS += -I$(top)/src/commonlib/include
OBJS = inteltool.o pcr.o cpu.o gpio.o gpio_groups.o rootcmplx.o powermgt.o \
- memory.o pcie.o amb.o ivy_memory.o spi.o gfx.o ahci.o \
+ memory.o pcie.o amb.o ivy_memory.o spi.o gfx.o ahci.o gpio_test.o \
OS_ARCH = $(shell uname)
ifeq ($(OS_ARCH), Darwin)
diff --git a/util/inteltool/gpio.h b/util/inteltool/gpio.h
index c89f393..161e9bb 100644
--- a/util/inteltool/gpio.h
+++ b/util/inteltool/gpio.h
@@ -17,6 +17,36 @@
#ifndef GPIO_H
#define GPIO_H
+
+// Describes a native function
+struct native_mode {
+ uint8_t mode;
+ char *name;
+};
+
+/*
+ * Describes a GPIO pad, which optionally can
+ * have one or more native functions and a default
+ * mode. If no default mode is set,
+ * default_mode to -1, else set it to the
+ * function number.
+ */
+struct gpio_pad {
+ const char *name;
+ uint8_t default_mode;
+ const struct native_mode *modes;
+ uint64_t default_config;
+ uint64_t config;
+};
+
+/*
+struct gpio_pad {
+ const char *name;
+ size_t defaultMode;
+ const char **functions;
+};
+*/
+
struct gpio_group {
const char *display;
size_t pad_count;
diff --git a/util/inteltool/gpio_test.c b/util/inteltool/gpio_test.c
new file mode 100644
index 0000000..9052623
--- /dev/null
+++ b/util/inteltool/gpio_test.c
@@ -0,0 +1,66 @@
+/*
+ * inteltool - dump all registers on an Intel CPU + chipset based system.
+ *
+ * Copyright (C) 2017 secunet Security Networks AG
+ * Copyright (C) 2019 Felix Singer <migy(a)darmstadt.ccc.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <stddef.h>
+#include <stdint.h>
+#include <assert.h>
+#include <inttypes.h>
+#include "inteltool.h"
+#include "pcr.h"
+#include "gpio.h"
+#include "gpio_test.h"
+
+#define SBBAR_SIZE (16 * MiB)
+#define PCR_PORT_SIZE (64 * KiB)
+
+void select_gpio_community(struct pci_dev *const sb)
+{
+ size_t community_count;
+ const struct gpio_community *const *communities;
+
+ switch (sb->device_id) {
+ case PCI_DEVICE_ID_INTEL_B150:
+ case PCI_DEVICE_ID_INTEL_CM236:
+// community_count = ARRAY_SIZE(sunrise_communities);
+// communities = sunrise_communities;
+// pcr_init(sb);
+ break;
+ case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE:
+ case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM:
+ case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM:
+ case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE:
+ case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM:
+ case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM:
+// community_count = ARRAY_SIZE(sunrise_lp_communities);
+// communities = sunrise_lp_communities;
+// pcr_init(sb);
+ break;
+ case PCI_DEVICE_ID_INTEL_DNV_LPC:
+// community_count = ARRAY_SIZE(denverton_communities);
+// communities = denverton_communities;
+// pcr_init(sb);
+ break;
+ default:
+ return;
+ }
+
+ printf("\n============= GPIOS =============\n\n");
+
+// for (; community_count; --community_count)
+// print_gpio_community(*communities++);
+}
diff --git a/util/inteltool/gpio_test.h b/util/inteltool/gpio_test.h
new file mode 100644
index 0000000..9edc4fe
--- /dev/null
+++ b/util/inteltool/gpio_test.h
@@ -0,0 +1,350 @@
+/*
+ * inteltool - dump all registers on an Intel CPU + chipset based system.
+ *
+ * Copyright (C) 2017 secunet Security Networks AG
+ * Copyright (C) 2019 Felix Singer <migy(a)darmstadt.ccc.de>
+ * Copyright (C) 2019 by 9elements Agency GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "gpio.h"
+
+#ifndef GPIO_TEST_H
+#define GPIO_TEST_H
+
+/*
+const struct gpio_pad test[] = {
+ { "gpio1", 2, (const char *[]) { "function1", "function2", NULL, } },
+};
+*/
+
+const struct gpio_pad test[] = {
+ { "GPP_A0", -1, (const struct native_mode[]) { {1, "RCIN#" }, }, },
+ { "GPP_A1", -1, (const struct native_mode[]) { {1, "LAD0" }, {3, "ESPI_IO0" }, }, },
+ { "GPP_A2", -1, (const struct native_mode[]) { {1, "LAD1" }, {3, "ESPI_IO1" }, }, },
+ { "GPP_A3", -1, (const struct native_mode[]) { {1, "LAD2" }, {3, "ESPI_IO2" }, }, },
+ { "GPP_A4", -1, (const struct native_mode[]) { {1, "LAD3" }, {3, "ESPI_IO3" }, }, },
+ { "GPP_A5", -1, (const struct native_mode[]) { {1, "LFRAME#" }, {3, "ESPI_CS#" }, }, },
+ { "GPP_A6", -1, (const struct native_mode[]) { {1, "SERIRQ#" }, }, },
+ { "GPP_A7", -1, (const struct native_mode[]) { {1, "PIRQA#" }, }, },
+ { "GPP_A8", -1, (const struct native_mode[]) { {1, "CLKRUN#" }, }, },
+ { "GPP_A9", -1, (const struct native_mode[]) { {1, "CLKOUT_LPC0" }, {3, "ESPI_CLK" }, }, },
+ { "GPP_A10", -1, (const struct native_mode[]) { {1, "CLKOUT_LPC1" }, }, },
+ { "GPP_A11", -1, (const struct native_mode[]) { {1, "PME#" }, }, },
+ { "GPP_A12", -1, (const struct native_mode[]) { {1, "BM_BUSY#" }, {2, "ISH_GP6" }, {3, "SX_EXIT_HOLDOFF#" }, }, },
+ { "GPP_A13", -1, (const struct native_mode[]) { {1, "SUSWARN#/SUSPWRDNACK" }, }, },
+ { "GPP_A14", -1, (const struct native_mode[]) { {1, "SUS_STAT#" }, {3, "ESPI_RESET#" }, }, },
+ { "GPP_A15", -1, (const struct native_mode[]) { {1, "SUS_ACK#" }, }, },
+ { "GPP_A16", -1, (const struct native_mode[]) { {1, "SD_1P8_SEL" }, }, },
+ { "GPP_A17", -1, (const struct native_mode[]) { {1, "SD_PWR_EN#" }, {2, "ISH_GP7" }, }, },
+ { "GPP_A18", -1, (const struct native_mode[]) { {1, "ISH_GP0" }, }, },
+ { "GPP_A19", -1, (const struct native_mode[]) { {1, "ISH_GP1" }, }, },
+ { "GPP_A20", -1, (const struct native_mode[]) { {1, "ISH_GP2" }, }, },
+ { "GPP_A21", -1, (const struct native_mode[]) { {1, "ISH_GP3" }, }, },
+ { "GPP_A22", -1, (const struct native_mode[]) { {1, "ISH_GP4" }, }, },
+ { "GPP_A23", -1, (const struct native_mode[]) { {1, "ISH_GP5" }, }, },
+};
+
+/*
+const char *const sunrise_lp_group_a_names[] = {
+ "GPP_A0", "RCIN#", "n/a", "n/a",
+ "GPP_A1", "LAD0", "n/a", "ESPI_IO0",
+ "GPP_A2", "LAD1", "n/a", "ESPI_IO1",
+ "GPP_A3", "LAD2", "n/a", "ESPI_IO2",
+ "GPP_A4", "LAD3", "n/a", "ESPI_IO3",
+ "GPP_A5", "LFRAME#", "n/a", "ESPI_CS#",
+ "GPP_A6", "SERIRQ", "n/a", "n/a",
+ "GPP_A7", "PIRQA#", "n/a", "n/a",
+ "GPP_A8", "CLKRUN#", "n/a", "n/a",
+ "GPP_A9", "CLKOUT_LPC0", "n/a", "ESPI_CLK",
+ "GPP_A10", "CLKOUT_LPC1", "n/a", "n/a",
+ "GPP_A11", "PME#", "n/a", "n/a",
+ "GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#",
+ "GPP_A13", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a",
+ "GPP_A14", "SUS_STAT#", "n/a", "ESPI_RESET#",
+ "GPP_A15", "SUS_ACK#", "n/a", "n/a",
+ "GPP_A16", "SD_1P8_SEL", "n/a", "n/a",
+ "GPP_A17", "SD_PWR_EN#", "ISH_GP7", "n/a",
+ "GPP_A18", "ISH_GP0", "n/a", "n/a",
+ "GPP_A19", "ISH_GP1", "n/a", "n/a",
+ "GPP_A20", "ISH_GP2", "n/a", "n/a",
+ "GPP_A21", "ISH_GP3", "n/a", "n/a",
+ "GPP_A22", "ISH_GP4", "n/a", "n/a",
+ "GPP_A23", "ISH_GP5", "n/a", "n/a",
+};
+
+const struct gpio_group sunrise_lp_group_a = {
+ .display = "------- GPIO group GPP_A -------",
+ .pad_count = ARRAY_SIZE(sunrise_lp_group_a_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_lp_group_a_names,
+};
+
+const char *const sunrise_lp_group_b_names[] = {
+ "GPP_B0", "CORE_VID0", "n/a", "n/a",
+ "GPP_B1", "CORE_VID1", "n/a", "n/a",
+ "GPP_B2", "VRALERT#", "n/a", "n/a",
+ "GPP_B3", "CPU_GP2", "n/a", "n/a",
+ "GPP_B4", "CPU_GP3", "n/a", "n/a",
+ "GPP_B5", "SRCCLKREQ0#", "n/a", "n/a",
+ "GPP_B6", "SRCCLKREQ1#", "n/a", "n/a",
+ "GPP_B7", "SRCCLKREQ2#", "n/a", "n/a",
+ "GPP_B8", "SRCCLKREQ3#", "n/a", "n/a",
+ "GPP_B9", "SRCCLKREQ4#", "n/a", "n/a",
+ "GPP_B10", "SRCCLKREQ5#", "n/a", "n/a",
+ "GPP_B11", "EXT_PWR_GATE#", "n/a", "n/a",
+ "GPP_B12", "SLP_S0#", "n/a", "n/a",
+ "GPP_B13", "PLTRST#", "n/a", "n/a",
+ "GPP_B14", "SPKR", "n/a", "n/a",
+ "GPP_B15", "GSPI0_CS#", "n/a", "n/a",
+ "GPP_B16", "GSPI0_CLK", "n/a", "n/a",
+ "GPP_B17", "GSPI0_MISO", "n/a", "n/a",
+ "GPP_B18", "GSPI0_MOSI", "n/a", "n/a",
+ "GPP_B19", "GSPI1_CS#", "n/a", "n/a",
+ "GPP_B20", "GSPI1_CLK", "n/a", "n/a",
+ "GPP_B21", "GSPI1_MISO", "n/a", "n/a",
+ "GPP_B22", "GSPI1_MOSI", "n/a", "n/a",
+ "GPP_B23", "SML1ALERT#", "PCHHOT#", "n/a",
+};
+
+const struct gpio_group sunrise_lp_group_b = {
+ .display = "------- GPIO Group GPP_B -------",
+ .pad_count = ARRAY_SIZE(sunrise_lp_group_b_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_lp_group_b_names,
+};
+
+const struct gpio_group *const sunrise_lp_community_ab_groups[] = {
+ &sunrise_lp_group_a, &sunrise_lp_group_b,
+};
+
+const struct gpio_community sunrise_lp_community_ab = {
+ .name = "------- GPIO Community 0 -------",
+ .pcr_port_id = 0xaf,
+ .group_count = ARRAY_SIZE(sunrise_lp_community_ab_groups),
+ .groups = sunrise_lp_community_ab_groups,
+};
+
+const char *const sunrise_group_c_names[] = {
+ "GPP_C0", "SMBCLK", "n/a", "n/a",
+ "GPP_C1", "SMBDATA", "n/a", "n/a",
+ "GPP_C2", "SMBALERT#", "n/a", "n/a",
+ "GPP_C3", "SML0CLK", "n/a", "n/a",
+ "GPP_C4", "SML0DATA", "n/a", "n/a",
+ "GPP_C5", "SML0ALERT#", "n/a", "n/a",
+ "GPP_C6", "SML1CLK", "n/a", "n/a",
+ "GPP_C7", "SML1DATA", "n/a", "n/a",
+ "GPP_C8", "UART0_RXD", "n/a", "n/a",
+ "GPP_C9", "UART0_TXD", "n/a", "n/a",
+ "GPP_C10", "UART0_RTS#", "n/a", "n/a",
+ "GPP_C11", "UART0_CTS#", "n/a", "n/a",
+ "GPP_C12", "UART1_RXD", "ISH_UART1_RXD", "n/a",
+ "GPP_C13", "UART1_TXD", "ISH_UART1_TXD", "n/a",
+ "GPP_C14", "UART1_RTS#", "ISH_UART1_RTS#", "n/a",
+ "GPP_C15", "UART1_CTS#", "ISH_UART1_CTS#", "n/a",
+ "GPP_C16", "I2C0_SDA", "n/a", "n/a",
+ "GPP_C17", "I2C0_SCL", "n/a", "n/a",
+ "GPP_C18", "I2C1_SDA", "n/a", "n/a",
+ "GPP_C19", "I2C1_SCL", "n/a", "n/a",
+ "GPP_C20", "UART2_RXD", "n/a", "n/a",
+ "GPP_C21", "UART2_TXD", "n/a", "n/a",
+ "GPP_C22", "UART2_RTS#", "n/a", "n/a",
+ "GPP_C23", "UART2_CTS#", "n/a", "n/a",
+};
+
+const struct gpio_group sunrise_group_c = {
+ .display = "------- GPIO Group GPP_C -------",
+ .pad_count = ARRAY_SIZE(sunrise_group_c_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_group_c_names,
+};
+
+const char *const sunrise_lp_group_d_names[] = {
+ "GPP_D0", "SPI1_CS#", "n/a", "n/a",
+ "GPP_D1", "SPI1_CLK", "n/a", "n/a",
+ "GPP_D2", "SPI1_MISO", "n/a", "n/a",
+ "GPP_D3", "SPI1_MOSI", "n/a", "n/a",
+ "GPP_D4", "FLASHTRIG", "n/a", "n/a",
+ "GPP_D5", "ISH_I2C0_SDA", "n/a", "n/a",
+ "GPP_D6", "ISH_I2C0_SCL", "n/a", "n/a",
+ "GPP_D7", "ISH_I2C1_SDA", "n/a", "n/a",
+ "GPP_D8", "ISH_I2C1_SCL", "n/a", "n/a",
+ "GPP_D9", "n/a", "n/a", "n/a",
+ "GPP_D10", "n/a", "n/a", "n/a",
+ "GPP_D11", "n/a", "n/a", "n/a",
+ "GPP_D12", "n/a", "n/a", "n/a",
+ "GPP_D13", "ISH_UART0_RXD", "n/a", "n/a",
+ "GPP_D14", "ISH_UART0_TXD", "n/a", "n/a",
+ "GPP_D15", "ISH_UART0_RTS#", "n/a", "n/a",
+ "GPP_D16", "ISH_UART0_CTS#", "n/a", "n/a",
+ "GPP_D17", "DMIC_CLK1", "n/a", "n/a",
+ "GPP_D18", "DMIC_DATA1", "n/a", "n/a",
+ "GPP_D19", "DMIC_CLK0", "n/a", "n/a",
+ "GPP_D20", "DMIC_DATA0", "n/a", "n/a",
+ "GPP_D21", "SPI1_IO2", "n/a", "n/a",
+ "GPP_D22", "SPI1_IO3", "n/a", "n/a",
+ "GPP_D23", "I2S_MCLK", "n/a", "n/a",
+};
+
+const struct gpio_group sunrise_lp_group_d = {
+ .display = "------- GPIO Group GPP_D -------",
+ .pad_count = ARRAY_SIZE(sunrise_lp_group_d_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_lp_group_d_names,
+};
+
+const char *const sunrise_lp_group_e_names[] = {
+ "GPP_E0", "SATAXPCIE0", "SATAGP0", "n/a",
+ "GPP_E1", "SATAXPCIE1", "SATAGP1", "n/a",
+ "GPP_E2", "SATAXPCIE2", "SATAGP2", "n/a",
+ "GPP_E3", "CPU_GP0", "n/a", "n/a",
+ "GPP_E4", "SATA_DEVSLP0", "n/a", "n/a",
+ "GPP_E5", "SATA_DEVSLP1", "n/a", "n/a",
+ "GPP_E6", "SATA_DEVSLP2", "n/a", "n/a",
+ "GPP_E7", "CPU_GP1", "n/a", "n/a",
+ "GPP_E8", "SATALED#", "n/a", "n/a",
+ "GPP_E9", "USB2_OC0#", "n/a", "n/a",
+ "GPP_E10", "USB2_OC1#", "n/a", "n/a",
+ "GPP_E11", "USB2_OC2#", "n/a", "n/a",
+ "GPP_E12", "USB2_OC3#", "n/a", "n/a",
+ "GPP_E13", "DDPB_HPD0", "n/a", "n/a",
+ "GPP_E14", "DDPC_HPD1", "n/a", "n/a",
+ "GPP_E15", "DDPD_HPD2", "n/a", "n/a",
+ "GPP_E16", "DDPE_HPD3", "n/a", "n/a",
+ "GPP_E17", "EDP_HPD", "n/a", "n/a",
+ "GPP_E18", "DDPB_CTRLCLK", "n/a", "n/a",
+ "GPP_E19", "DDPB_CTRLDATA", "n/a", "n/a",
+ "GPP_E20", "DDPC_CTRLCLK", "n/a", "n/a",
+ "GPP_E21", "DDPC_CTRLDATA", "n/a", "n/a",
+ "GPP_E22", "n/a", "n/a", "n/a",
+ "GPP_E23", "n/a", "n/a", "n/a",
+};
+
+const struct gpio_group sunrise_lp_group_e = {
+ .display = "------- GPIO Group GPP_E -------",
+ .pad_count = ARRAY_SIZE(sunrise_lp_group_e_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_lp_group_e_names,
+};
+
+const char *const sunrise_lp_group_f_names[] = {
+ "GPP_F0", "I2S2_SCLK", "n/a", "n/a",
+ "GPP_F1", "I2S2_SFRM", "n/a", "n/a",
+ "GPP_F2", "I2S2_TXD", "n/a", "n/a",
+ "GPP_F3", "I2S2_RXD", "n/a", "n/a",
+ "GPP_F4", "I2C2_SDA", "n/a", "n/a",
+ "GPP_F5", "I2C2_SCL", "n/a", "n/a",
+ "GPP_F6", "I2C3_SDA", "n/a", "n/a",
+ "GPP_F7", "I2C3_SCL", "n/a", "n/a",
+ "GPP_F8", "I2C4_SDA", "n/a", "n/a",
+ "GPP_F9", "I2C4_SCL", "n/a", "n/a",
+ "GPP_F10", "I2C5_SDA", "ISH_I2C2_SDA", "n/a",
+ "GPP_F11", "I2C5_SCL", "ISH_I2C2_SCL", "n/a",
+ "GPP_F12", "EMMC_CMD", "n/a", "n/a",
+ "GPP_F13", "EMMC_DATA0", "n/a", "n/a",
+ "GPP_F14", "EMMC_DATA1", "n/a", "n/a",
+ "GPP_F15", "EMMC_DATA2", "n/a", "n/a",
+ "GPP_F16", "EMMC_DATA3", "n/a", "n/a",
+ "GPP_F17", "EMMC_DATA4", "n/a", "n/a",
+ "GPP_F18", "EMMC_DATA5", "n/a", "n/a",
+ "GPP_F19", "EMMC_DATA6", "n/a", "n/a",
+ "GPP_F20", "EMMC_DATA7", "n/a", "n/a",
+ "GPP_F21", "EMMC_RCLK", "n/a", "n/a",
+ "GPP_F22", "EMMC_CLK", "n/a", "n/a",
+ "GPP_F23", "n/a", "n/a", "n/a",
+};
+
+const struct gpio_group sunrise_lp_group_f = {
+ .display = "------- GPIO Group GPP_F -------",
+ .pad_count = ARRAY_SIZE(sunrise_lp_group_f_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_lp_group_f_names,
+};
+
+const char *const sunrise_lp_group_g_names[] = {
+ "GPP_G0", "SD_CMD", "n/a", "n/a",
+ "GPP_G1", "SD_DATA0", "n/a", "n/a",
+ "GPP_G2", "SD_DATA1", "n/a", "n/a",
+ "GPP_G3", "SD_DATA2", "n/a", "n/a",
+ "GPP_G4", "SD_DATA3", "n/a", "n/a",
+ "GPP_G5", "SD_CD#", "n/a", "n/a",
+ "GPP_G6", "SD_CLK", "n/a", "n/a",
+ "GPP_G7", "SD_WP", "n/a", "n/a",
+};
+
+const struct gpio_group sunrise_lp_group_g = {
+ .display = "------- GPIO Group GPP_G -------",
+ .pad_count = ARRAY_SIZE(sunrise_lp_group_g_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_lp_group_g_names,
+};
+
+const struct gpio_group *const sunrise_lp_community_cde_groups[] = {
+ &sunrise_group_c, &sunrise_lp_group_d, &sunrise_lp_group_e,
+};
+
+const struct gpio_community sunrise_lp_community_cde = {
+ .name = "------- GPIO Community 1 -------",
+ .pcr_port_id = 0xae,
+ .group_count = ARRAY_SIZE(sunrise_lp_community_cde_groups),
+ .groups = sunrise_lp_community_cde_groups,
+};
+
+const char *const sunrise_group_gpd_names[] = {
+ "GPD0", "BATLOW#", "n/a", "n/a",
+ "GPD1", "ACPRESENT", "n/a", "n/a",
+ "GPD2", "LAN_WAKE#", "n/a", "n/a",
+ "GPD3", "PWRBTN#", "n/a", "n/a",
+ "GPD4", "SLP_S3#", "n/a", "n/a",
+ "GPD5", "SLP_S4#", "n/a", "n/a",
+ "GPD6", "SLP_A#", "n/a", "n/a",
+ "GPD7", "RESERVED", "n/a", "n/a",
+ "GPD8", "SUSCLK", "n/a", "n/a",
+ "GPD9", "SLP_WLAN#", "n/a", "n/a",
+ "GPD10", "SLP_S5#", "n/a", "n/a",
+ "GPD11", "LANPHYPC", "n/a", "n/a",
+};
+
+const struct gpio_group sunrise_group_gpd = {
+ .display = "-------- GPIO Group GPD --------",
+ .pad_count = ARRAY_SIZE(sunrise_group_gpd_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_group_gpd_names,
+};
+
+const struct gpio_group *const sunrise_community_gpd_groups[] = {
+ &sunrise_group_gpd,
+};
+
+const struct gpio_community sunrise_community_gpd = {
+ .name = "------- GPIO Community 2 -------",
+ .pcr_port_id = 0xad,
+ .group_count = ARRAY_SIZE(sunrise_community_gpd_groups),
+ .groups = sunrise_community_gpd_groups,
+};
+
+const struct gpio_group *const sunrise_lp_community_fg_groups[] = {
+ &sunrise_lp_group_f, &sunrise_lp_group_g,
+};
+
+const struct gpio_community sunrise_lp_community_fg = {
+ .name = "------- GPIO Community 3 -------",
+ .pcr_port_id = 0xac,
+ .group_count = ARRAY_SIZE(sunrise_lp_community_fg_groups),
+ .groups = sunrise_lp_community_fg_groups,
+};
+
+const struct gpio_community *const sunrise_lp_communities[] = {
+ &sunrise_lp_community_ab, &sunrise_lp_community_cde,
+ &sunrise_community_gpd, &sunrise_lp_community_fg,
+};
+*/
+#endif
--
To view, visit https://review.coreboot.org/c/coreboot/+/31634
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ie92a5af141a907251fc847d53c767984949d9312
Gerrit-Change-Number: 31634
Gerrit-PatchSet: 1
Gerrit-Owner: Felix Singer <migy(a)darmstadt.ccc.de>
Gerrit-MessageType: newchange
1 week, 3 days
- 3
- 10
Change in ...coreboot[master]: util/inteltool: Refactor code of GPIO groups
by Felix Singer (Code Review)
Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31504
Change subject: util/inteltool: Refactor code of GPIO groups
......................................................................
util/inteltool: Refactor code of GPIO groups
Change-Id: Ic61871f5cf95ac3da93892fa2f7721e682176c8d
Signed-off-by: Felix Singer <migy(a)darmstadt.ccc.de>
---
A util/inteltool/gpio.h
A util/inteltool/gpio_denverton.h
M util/inteltool/gpio_groups.c
A util/inteltool/gpio_sunrise.h
4 files changed, 865 insertions(+), 816 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/31504/1
diff --git a/util/inteltool/gpio.h b/util/inteltool/gpio.h
new file mode 100644
index 0000000..64f62f8
--- /dev/null
+++ b/util/inteltool/gpio.h
@@ -0,0 +1,29 @@
+/*
+ * inteltool - dump all registers on an Intel CPU + chipset based system.
+ *
+ * Copyright (C) 2017 secunet Security Networks AG
+ * Copyright (C) 2019 Felix Singer <migy(a)darmstadt.ccc.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+struct gpio_group {
+ const char *display;
+ size_t pad_count;
+ size_t func_count;
+ const char *const *pad_names; /* indexed by 'pad * func_count + func' */
+};
+
+struct gpio_community {
+ const char *name;
+ uint8_t pcr_port_id;
+ size_t group_count;
+ const struct gpio_group *const *groups;
+};
diff --git a/util/inteltool/gpio_denverton.h b/util/inteltool/gpio_denverton.h
new file mode 100644
index 0000000..e745b44
--- /dev/null
+++ b/util/inteltool/gpio_denverton.h
@@ -0,0 +1,237 @@
+/*
+ * inteltool - dump all registers on an Intel CPU + chipset based system.
+ *
+ * Copyright (C) 2017 secunet Security Networks AG
+ * Copyright (C) 2019 Felix Singer <migy(a)darmstadt.ccc.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+static const char *const denverton_group_north_all_names[] = {
+ "NORTH_ALL_GBE0_SDP0",
+ "NORTH_ALL_GBE1_SDP0",
+ "NORTH_ALL_GBE0_SDP1",
+ "NORTH_ALL_GBE1_SDP1",
+ "NORTH_ALL_GBE0_SDP2",
+ "NORTH_ALL_GBE1_SDP2",
+ "NORTH_ALL_GBE0_SDP3",
+ "NORTH_ALL_GBE1_SDP3",
+ "NORTH_ALL_GBE2_LED0",
+ "NORTH_ALL_GBE2_LED1",
+ "NORTH_ALL_GBE0_I2C_CLK",
+ "NORTH_ALL_GBE0_I2C_DATA",
+ "NORTH_ALL_GBE1_I2C_CLK",
+ "NORTH_ALL_GBE1_I2C_DATA",
+ "NORTH_ALL_NCSI_RXD0",
+ "NORTH_ALL_NCSI_CLK_IN",
+ "NORTH_ALL_NCSI_RXD1",
+ "NORTH_ALL_NCSI_CRS_DV",
+ "NORTH_ALL_NCSI_ARB_IN",
+ "NORTH_ALL_NCSI_TX_EN",
+ "NORTH_ALL_NCSI_TXD0",
+ "NORTH_ALL_NCSI_TXD1",
+ "NORTH_ALL_NCSI_ARB_OUT",
+ "NORTH_ALL_GBE0_LED0",
+ "NORTH_ALL_GBE0_LED1",
+ "NORTH_ALL_GBE1_LED0",
+ "NORTH_ALL_GBE1_LED1",
+ "NORTH_ALL_GPIO_0",
+ "NORTH_ALL_PCIE_CLKREQ0_N",
+ "NORTH_ALL_PCIE_CLKREQ1_N",
+ "NORTH_ALL_PCIE_CLKREQ2_N",
+ "NORTH_ALL_PCIE_CLKREQ3_N",
+ "NORTH_ALL_PCIE_CLKREQ4_N",
+ "NORTH_ALL_GPIO_1",
+ "NORTH_ALL_GPIO_2",
+ "NORTH_ALL_SVID_ALERT_N",
+ "NORTH_ALL_SVID_DATA",
+ "NORTH_ALL_SVID_CLK",
+ "NORTH_ALL_THERMTRIP_N",
+ "NORTH_ALL_PROCHOT_N",
+ "NORTH_ALL_MEMHOT_N",
+};
+
+static const struct gpio_group denverton_group_north_all = {
+ .display = "------- GPIO Group North All -------",
+ .pad_count = ARRAY_SIZE(denverton_group_north_all_names) / 1,
+ .func_count = 1,
+ .pad_names = denverton_group_north_all_names,
+};
+
+static const struct gpio_group *const denverton_community_north_groups[] = {
+ &denverton_group_north_all,
+};
+
+static const struct gpio_community denverton_community_north = {
+ .name = "------- GPIO Community 0 -------",
+ .pcr_port_id = 0xc2,
+ .group_count = ARRAY_SIZE(denverton_community_north_groups),
+ .groups = denverton_community_north_groups,
+};
+
+static const char *const denverton_group_south_dfx_names[] = {
+ "SOUTH_DFX_DFX_PORT_CLK0",
+ "SOUTH_DFX_DFX_PORT_CLK1",
+ "SOUTH_DFX_DFX_PORT0",
+ "SOUTH_DFX_DFX_PORT1",
+ "SOUTH_DFX_DFX_PORT2",
+ "SOUTH_DFX_DFX_PORT3",
+ "SOUTH_DFX_DFX_PORT4",
+ "SOUTH_DFX_DFX_PORT5",
+ "SOUTH_DFX_DFX_PORT6",
+ "SOUTH_DFX_DFX_PORT7",
+ "SOUTH_DFX_DFX_PORT8",
+ "SOUTH_DFX_DFX_PORT9",
+ "SOUTH_DFX_DFX_PORT10",
+ "SOUTH_DFX_DFX_PORT11",
+ "SOUTH_DFX_DFX_PORT12",
+ "SOUTH_DFX_DFX_PORT13",
+ "SOUTH_DFX_DFX_PORT14",
+ "SOUTH_DFX_DFX_PORT15",
+};
+
+static const struct gpio_group denverton_group_south_dfx = {
+ .display = "------- GPIO Group South DFX -------",
+ .pad_count = ARRAY_SIZE(denverton_group_south_dfx_names) / 1,
+ .func_count = 1,
+ .pad_names = denverton_group_south_dfx_names,
+};
+
+static const char *const denverton_group_south_group0_names[] = {
+ "SOUTH_GROUP0_GPIO_12",
+ "SOUTH_GROUP0_SMB5_GBE_ALRT_N",
+ "SOUTH_GROUP0_PCIE_CLKREQ5_N",
+ "SOUTH_GROUP0_PCIE_CLKREQ6_N",
+ "SOUTH_GROUP0_PCIE_CLKREQ7_N",
+ "SOUTH_GROUP0_UART0_RXD",
+ "SOUTH_GROUP0_UART0_TXD",
+ "SOUTH_GROUP0_SMB5_GBE_CLK",
+ "SOUTH_GROUP0_SMB5_GBE_DATA",
+ "SOUTH_GROUP0_ERROR2_N",
+ "SOUTH_GROUP0_ERROR1_N",
+ "SOUTH_GROUP0_ERROR0_N",
+ "SOUTH_GROUP0_IERR_N",
+ "SOUTH_GROUP0_MCERR_N",
+ "SOUTH_GROUP0_SMB0_LEG_CLK",
+ "SOUTH_GROUP0_SMB0_LEG_DATA",
+ "SOUTH_GROUP0_SMB0_LEG_ALRT_N",
+ "SOUTH_GROUP0_SMB1_HOST_DATA",
+ "SOUTH_GROUP0_SMB1_HOST_CLK",
+ "SOUTH_GROUP0_SMB2_PECI_DATA",
+ "SOUTH_GROUP0_SMB2_PECI_CLK",
+ "SOUTH_GROUP0_SMB4_CSME0_DATA",
+ "SOUTH_GROUP0_SMB4_CSME0_CLK",
+ "SOUTH_GROUP0_SMB4_CSME0_ALRT_N",
+ "SOUTH_GROUP0_USB_OC0_N",
+ "SOUTH_GROUP0_FLEX_CLK_SE0",
+ "SOUTH_GROUP0_FLEX_CLK_SE1",
+ "SOUTH_GROUP0_GPIO_4",
+ "SOUTH_GROUP0_GPIO_5",
+ "SOUTH_GROUP0_GPIO_6",
+ "SOUTH_GROUP0_GPIO_7",
+ "SOUTH_GROUP0_SATA0_LED_N",
+ "SOUTH_GROUP0_SATA1_LED_N",
+ "SOUTH_GROUP0_SATA_PDETECT0",
+ "SOUTH_GROUP0_SATA_PDETECT1",
+ "SOUTH_GROUP0_SATA0_SDOUT",
+ "SOUTH_GROUP0_SATA1_SDOUT",
+ "SOUTH_GROUP0_UART1_RXD",
+ "SOUTH_GROUP0_UART1_TXD",
+ "SOUTH_GROUP0_GPIO_8",
+ "SOUTH_GROUP0_GPIO_9",
+ "SOUTH_GROUP0_TCK",
+ "SOUTH_GROUP0_TRST_N",
+ "SOUTH_GROUP0_TMS",
+ "SOUTH_GROUP0_TDI",
+ "SOUTH_GROUP0_TDO",
+ "SOUTH_GROUP0_CX_PRDY_N",
+ "SOUTH_GROUP0_CX_PREQ_N",
+ "SOUTH_GROUP0_CTBTRIGINOUT",
+ "SOUTH_GROUP0_CTBTRIGOUT",
+ "SOUTH_GROUP0_DFX_SPARE2",
+ "SOUTH_GROUP0_DFX_SPARE3",
+ "SOUTH_GROUP0_DFX_SPARE4",
+};
+
+static const struct gpio_group denverton_group_south_group0 = {
+ .display = "------- GPIO Group South Group0 -------",
+ .pad_count = ARRAY_SIZE(denverton_group_south_group0_names) / 1,
+ .func_count = 1,
+ .pad_names = denverton_group_south_group0_names,
+};
+
+static const char *const denverton_group_south_group1_names[] = {
+ "SOUTH_GROUP1_SUSPWRDNACK",
+ "SOUTH_GROUP1_PMU_SUSCLK",
+ "SOUTH_GROUP1_ADR_TRIGGER",
+ "SOUTH_GROUP1_PMU_SLP_S45_N",
+ "SOUTH_GROUP1_PMU_SLP_S3_N",
+ "SOUTH_GROUP1_PMU_WAKE_N",
+ "SOUTH_GROUP1_PMU_PWRBTN_N",
+ "SOUTH_GROUP1_PMU_RESETBUTTON_N",
+ "SOUTH_GROUP1_PMU_PLTRST_N",
+ "SOUTH_GROUP1_SUS_STAT_N",
+ "SOUTH_GROUP1_SLP_S0IX_N",
+ "SOUTH_GROUP1_SPI_CS0_N",
+ "SOUTH_GROUP1_SPI_CS1_N",
+ "SOUTH_GROUP1_SPI_MOSI_IO0",
+ "SOUTH_GROUP1_SPI_MISO_IO1",
+ "SOUTH_GROUP1_SPI_IO2",
+ "SOUTH_GROUP1_SPI_IO3",
+ "SOUTH_GROUP1_SPI_CLK",
+ "SOUTH_GROUP1_SPI_CLK_LOOPBK",
+ "SOUTH_GROUP1_ESPI_IO0",
+ "SOUTH_GROUP1_ESPI_IO1",
+ "SOUTH_GROUP1_ESPI_IO2",
+ "SOUTH_GROUP1_ESPI_IO3",
+ "SOUTH_GROUP1_ESPI_CS0_N",
+ "SOUTH_GROUP1_ESPI_CLK",
+ "SOUTH_GROUP1_ESPI_RST_N",
+ "SOUTH_GROUP1_ESPI_ALRT0_N",
+ "SOUTH_GROUP1_GPIO_10",
+ "SOUTH_GROUP1_GPIO_11",
+ "SOUTH_GROUP1_ESPI_CLK_LOOPBK",
+ "SOUTH_GROUP1_EMMC_CMD",
+ "SOUTH_GROUP1_EMMC_STROBE",
+ "SOUTH_GROUP1_EMMC_CLK",
+ "SOUTH_GROUP1_EMMC_D0",
+ "SOUTH_GROUP1_EMMC_D1",
+ "SOUTH_GROUP1_EMMC_D2",
+ "SOUTH_GROUP1_EMMC_D3",
+ "SOUTH_GROUP1_EMMC_D4",
+ "SOUTH_GROUP1_EMMC_D5",
+ "SOUTH_GROUP1_EMMC_D6",
+ "SOUTH_GROUP1_EMMC_D7",
+ "SOUTH_GROUP1_GPIO_3",
+};
+
+static const struct gpio_group denverton_group_south_group1 = {
+ .display = "------- GPIO Group South Group1 -------",
+ .pad_count = ARRAY_SIZE(denverton_group_south_group1_names) / 1,
+ .func_count = 1,
+ .pad_names = denverton_group_south_group1_names,
+};
+
+static const struct gpio_group *const denverton_community_south_groups[] = {
+ &denverton_group_south_dfx,
+ &denverton_group_south_group0,
+ &denverton_group_south_group1,
+};
+
+static const struct gpio_community denverton_community_south = {
+ .name = "------- GPIO Community 1 -------",
+ .pcr_port_id = 0xc5,
+ .group_count = ARRAY_SIZE(denverton_community_south_groups),
+ .groups = denverton_community_south_groups,
+};
+
+static const struct gpio_community *const denverton_communities[] = {
+ &denverton_community_north, &denverton_community_south,
+};
diff --git a/util/inteltool/gpio_groups.c b/util/inteltool/gpio_groups.c
index 53a8eb9..c7ab186 100644
--- a/util/inteltool/gpio_groups.c
+++ b/util/inteltool/gpio_groups.c
@@ -2,6 +2,7 @@
* inteltool - dump all registers on an Intel CPU + chipset based system.
*
* Copyright (C) 2017 secunet Security Networks AG
+ * Copyright (C) 2019 Felix Singer <migy(a)darmstadt.ccc.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -21,826 +22,13 @@
#include <inttypes.h>
#include "inteltool.h"
#include "pcr.h"
+#include "gpio.h"
+#include "gpio_denverton.h"
+#include "gpio_sunrise.h"
#define SBBAR_SIZE (16 * MiB)
#define PCR_PORT_SIZE (64 * KiB)
-struct gpio_group {
- const char *display;
- size_t pad_count;
- size_t func_count;
- const char *const *pad_names; /* indexed by 'pad * func_count + func' */
-};
-
-struct gpio_community {
- const char *name;
- uint8_t pcr_port_id;
- size_t group_count;
- const struct gpio_group *const *groups;
-};
-
-static const char *const sunrise_group_a_names[] = {
- "GPP_A0", "RCIN#", "n/a", "ESPI_ALERT1#",
- "GPP_A1", "LAD0", "n/a", "ESPI_IO0",
- "GPP_A2", "LAD1", "n/a", "ESPI_IO1",
- "GPP_A3", "LAD2", "n/a", "ESPI_IO2",
- "GPP_A4", "LAD3", "n/a", "ESPI_IO3",
- "GPP_A5", "LFRAME#", "n/a", "ESPI_CS#",
- "GPP_A6", "SERIRQ", "n/a", "ESPI_CS1#",
- "GPP_A7", "PIRQA#", "n/a", "ESPI_ALERT0#",
- "GPP_A8", "CLKRUN#", "n/a", "n/a",
- "GPP_A9", "CLKOUT_LPC0", "n/a", "ESPI_CLK",
- "GPP_A10", "CLKOUT_LPC1", "n/a", "n/a",
- "GPP_A11", "PME#", "n/a", "n/a",
- "GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#",
- "GPP_A13", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a",
- "GPP_A14", "SUS_STAT#", "n/a", "ESPI_RESET#",
- "GPP_A15", "SUS_ACK#", "n/a", "n/a",
- "GPP_A16", "CLKOUT_48", "n/a", "n/a",
- "GPP_A17", "ISH_GP7", "n/a", "n/a",
- "GPP_A18", "ISH_GP0", "n/a", "n/a",
- "GPP_A19", "ISH_GP1", "n/a", "n/a",
- "GPP_A20", "ISH_GP2", "n/a", "n/a",
- "GPP_A21", "ISH_GP3", "n/a", "n/a",
- "GPP_A22", "ISH_GP4", "n/a", "n/a",
- "GPP_A23", "ISH_GP5", "n/a", "n/a",
-};
-
-static const struct gpio_group sunrise_group_a = {
- .display = "------- GPIO Group GPP_A -------",
- .pad_count = ARRAY_SIZE(sunrise_group_a_names) / 4,
- .func_count = 4,
- .pad_names = sunrise_group_a_names,
-};
-
-static const char *const sunrise_lp_group_a_names[] = {
- "GPP_A0", "RCIN#", "n/a", "n/a",
- "GPP_A1", "LAD0", "n/a", "ESPI_IO0",
- "GPP_A2", "LAD1", "n/a", "ESPI_IO1",
- "GPP_A3", "LAD2", "n/a", "ESPI_IO2",
- "GPP_A4", "LAD3", "n/a", "ESPI_IO3",
- "GPP_A5", "LFRAME#", "n/a", "ESPI_CS#",
- "GPP_A6", "SERIRQ", "n/a", "n/a",
- "GPP_A7", "PIRQA#", "n/a", "n/a",
- "GPP_A8", "CLKRUN#", "n/a", "n/a",
- "GPP_A9", "CLKOUT_LPC0", "n/a", "ESPI_CLK",
- "GPP_A10", "CLKOUT_LPC1", "n/a", "n/a",
- "GPP_A11", "PME#", "n/a", "n/a",
- "GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#",
- "GPP_A13", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a",
- "GPP_A14", "SUS_STAT#", "n/a", "ESPI_RESET#",
- "GPP_A15", "SUS_ACK#", "n/a", "n/a",
- "GPP_A16", "SD_1P8_SEL", "n/a", "n/a",
- "GPP_A17", "SD_PWR_EN#", "ISH_GP7", "n/a",
- "GPP_A18", "ISH_GP0", "n/a", "n/a",
- "GPP_A19", "ISH_GP1", "n/a", "n/a",
- "GPP_A20", "ISH_GP2", "n/a", "n/a",
- "GPP_A21", "ISH_GP3", "n/a", "n/a",
- "GPP_A22", "ISH_GP4", "n/a", "n/a",
- "GPP_A23", "ISH_GP5", "n/a", "n/a",
-};
-
-static const struct gpio_group sunrise_lp_group_a = {
- .display = "------- GPIO group GPP_A -------",
- .pad_count = ARRAY_SIZE(sunrise_lp_group_a_names) / 4,
- .func_count = 4,
- .pad_names = sunrise_lp_group_a_names,
-};
-
-static const char *const sunrise_group_b_names[] = {
- "GPP_B0", "n/a", "n/a", "n/a",
- "GPP_B1", "n/a", "n/a", "n/a",
- "GPP_B2", "VRALERT#", "n/a", "n/a",
- "GPP_B3", "CPU_GP2", "n/a", "n/a",
- "GPP_B4", "CPU_GP3", "n/a", "n/a",
- "GPP_B5", "SRCCLKREQ0#", "n/a", "n/a",
- "GPP_B6", "SRCCLKREQ1#", "n/a", "n/a",
- "GPP_B7", "SRCCLKREQ2#", "n/a", "n/a",
- "GPP_B8", "SRCCLKREQ3#", "n/a", "n/a",
- "GPP_B9", "SRCCLKREQ4#", "n/a", "n/a",
- "GPP_B10", "SRCCLKREQ5#", "n/a", "n/a",
- "GPP_B11", "n/a", "n/a", "n/a",
- "GPP_B12", "SLP_S0#", "n/a", "n/a",
- "GPP_B13", "PLTRST#", "n/a", "n/a",
- "GPP_B14", "SPKR", "n/a", "n/a",
- "GPP_B15", "GSPIO_CS#", "n/a", "n/a",
- "GPP_B16", "GSPIO_CLK", "n/a", "n/a",
- "GPP_B17", "GSPIO_MISO", "n/a", "n/a",
- "GPP_B18", "GSPIO_MOSI", "n/a", "n/a",
- "GPP_B19", "GSPI1_CS#", "n/a", "n/a",
- "GPP_B20", "GSPI1_CLK", "n/a", "n/a",
- "GPP_B21", "GSPI1_MISO", "n/a", "n/a",
- "GPP_B22", "GSPI1_MOSI", "n/a", "n/a",
- "GPP_B23", "SML1ALERT#", "PCHHOT#", "n/a",
-};
-
-static const struct gpio_group sunrise_group_b = {
- .display = "------- GPIO Group GPP_B -------",
- .pad_count = ARRAY_SIZE(sunrise_group_b_names) / 4,
- .func_count = 4,
- .pad_names = sunrise_group_b_names,
-};
-
-static const char *const sunrise_lp_group_b_names[] = {
- "GPP_B0", "CORE_VID0", "n/a", "n/a",
- "GPP_B1", "CORE_VID1", "n/a", "n/a",
- "GPP_B2", "VRALERT#", "n/a", "n/a",
- "GPP_B3", "CPU_GP2", "n/a", "n/a",
- "GPP_B4", "CPU_GP3", "n/a", "n/a",
- "GPP_B5", "SRCCLKREQ0#", "n/a", "n/a",
- "GPP_B6", "SRCCLKREQ1#", "n/a", "n/a",
- "GPP_B7", "SRCCLKREQ2#", "n/a", "n/a",
- "GPP_B8", "SRCCLKREQ3#", "n/a", "n/a",
- "GPP_B9", "SRCCLKREQ4#", "n/a", "n/a",
- "GPP_B10", "SRCCLKREQ5#", "n/a", "n/a",
- "GPP_B11", "EXT_PWR_GATE#", "n/a", "n/a",
- "GPP_B12", "SLP_S0#", "n/a", "n/a",
- "GPP_B13", "PLTRST#", "n/a", "n/a",
- "GPP_B14", "SPKR", "n/a", "n/a",
- "GPP_B15", "GSPI0_CS#", "n/a", "n/a",
- "GPP_B16", "GSPI0_CLK", "n/a", "n/a",
- "GPP_B17", "GSPI0_MISO", "n/a", "n/a",
- "GPP_B18", "GSPI0_MOSI", "n/a", "n/a",
- "GPP_B19", "GSPI1_CS#", "n/a", "n/a",
- "GPP_B20", "GSPI1_CLK", "n/a", "n/a",
- "GPP_B21", "GSPI1_MISO", "n/a", "n/a",
- "GPP_B22", "GSPI1_MOSI", "n/a", "n/a",
- "GPP_B23", "SML1ALERT#", "PCHHOT#", "n/a",
-};
-
-static const struct gpio_group sunrise_lp_group_b = {
- .display = "------- GPIO Group GPP_B -------",
- .pad_count = ARRAY_SIZE(sunrise_lp_group_b_names) / 4,
- .func_count = 4,
- .pad_names = sunrise_lp_group_b_names,
-};
-
-static const struct gpio_group *const sunrise_community_ab_groups[] = {
- &sunrise_group_a, &sunrise_group_b,
-};
-
-static const struct gpio_group *const sunrise_lp_community_ab_groups[] = {
- &sunrise_lp_group_a, &sunrise_lp_group_b,
-};
-
-static const struct gpio_community sunrise_community_ab = {
- .name = "------- GPIO Community 0 -------",
- .pcr_port_id = 0xaf,
- .group_count = ARRAY_SIZE(sunrise_community_ab_groups),
- .groups = sunrise_community_ab_groups,
-};
-
-static const struct gpio_community sunrise_lp_community_ab = {
- .name = "------- GPIO Community 0 -------",
- .pcr_port_id = 0xaf,
- .group_count = ARRAY_SIZE(sunrise_lp_community_ab_groups),
- .groups = sunrise_lp_community_ab_groups,
-};
-
-static const char *const sunrise_group_c_names[] = {
- "GPP_C0", "SMBCLK", "n/a", "n/a",
- "GPP_C1", "SMBDATA", "n/a", "n/a",
- "GPP_C2", "SMBALERT#", "n/a", "n/a",
- "GPP_C3", "SML0CLK", "n/a", "n/a",
- "GPP_C4", "SML0DATA", "n/a", "n/a",
- "GPP_C5", "SML0ALERT#", "n/a", "n/a",
- "GPP_C6", "SML1CLK", "n/a", "n/a",
- "GPP_C7", "SML1DATA", "n/a", "n/a",
- "GPP_C8", "UART0_RXD", "n/a", "n/a",
- "GPP_C9", "UART0_TXD", "n/a", "n/a",
- "GPP_C10", "UART0_RTS#", "n/a", "n/a",
- "GPP_C11", "UART0_CTS#", "n/a", "n/a",
- "GPP_C12", "UART1_RXD", "ISH_UART1_RXD", "n/a",
- "GPP_C13", "UART1_TXD", "ISH_UART1_TXD", "n/a",
- "GPP_C14", "UART1_RTS#", "ISH_UART1_RTS#", "n/a",
- "GPP_C15", "UART1_CTS#", "ISH_UART1_CTS#", "n/a",
- "GPP_C16", "I2C0_SDA", "n/a", "n/a",
- "GPP_C17", "I2C0_SCL", "n/a", "n/a",
- "GPP_C18", "I2C1_SDA", "n/a", "n/a",
- "GPP_C19", "I2C1_SCL", "n/a", "n/a",
- "GPP_C20", "UART2_RXD", "n/a", "n/a",
- "GPP_C21", "UART2_TXD", "n/a", "n/a",
- "GPP_C22", "UART2_RTS#", "n/a", "n/a",
- "GPP_C23", "UART2_CTS#", "n/a", "n/a",
-};
-
-static const struct gpio_group sunrise_group_c = {
- .display = "------- GPIO Group GPP_C -------",
- .pad_count = ARRAY_SIZE(sunrise_group_c_names) / 4,
- .func_count = 4,
- .pad_names = sunrise_group_c_names,
-};
-
-static const char *const sunrise_group_d_names[] = {
- "GPP_D0", "n/a", "n/a", "n/a",
- "GPP_D1", "n/a", "n/a", "n/a",
- "GPP_D2", "n/a", "n/a", "n/a",
- "GPP_D3", "n/a", "n/a", "n/a",
- "GPP_D4", "ISH_I2C2_SDA", "I2C3_SDA", "n/a",
- "GPP_D5", "I2S_SFRM", "n/a", "n/a",
- "GPP_D6", "I2S_TXD", "n/a", "n/a",
- "GPP_D7", "I2S_RXD", "n/a", "n/a",
- "GPP_D8", "I2S_SCLK", "n/a", "n/a",
- "GPP_D9", "n/a", "n/a", "n/a",
- "GPP_D10", "n/a", "n/a", "n/a",
- "GPP_D11", "n/a", "n/a", "n/a",
- "GPP_D12", "n/a", "n/a", "n/a",
- "GPP_D13", "ISH_UART0_RXD", "n/a", "I2C2_SDA",
- "GPP_D14", "ISH_UART0_TXD", "n/a", "I2C2_SCL",
- "GPP_D15", "ISH_UART0_RTS#", "n/a", "n/a",
- "GPP_D16", "ISH_UART0_CTS#", "n/a", "n/a",
- "GPP_D17", "DMIC_CLK1", "n/a", "n/a",
- "GPP_D18", "DMIC_DATA1", "n/a", "n/a",
- "GPP_D19", "DMIC_CLK0", "n/a", "n/a",
- "GPP_D20", "DMIC_DATA0", "n/a", "n/a",
- "GPP_D21", "n/a", "n/a", "n/a",
- "GPP_D22", "n/a", "n/a", "n/a",
- "GPP_D23", "ISH_I2C2_SCL", "I2C3_SCL", "n/a",
-};
-
-static const struct gpio_group sunrise_group_d = {
- .display = "------- GPIO Group GPP_D -------",
- .pad_count = ARRAY_SIZE(sunrise_group_d_names) / 4,
- .func_count = 4,
- .pad_names = sunrise_group_d_names,
-};
-
-static const char *const sunrise_lp_group_d_names[] = {
- "GPP_D0", "SPI1_CS#", "n/a", "n/a",
- "GPP_D1", "SPI1_CLK", "n/a", "n/a",
- "GPP_D2", "SPI1_MISO", "n/a", "n/a",
- "GPP_D3", "SPI1_MOSI", "n/a", "n/a",
- "GPP_D4", "FLASHTRIG", "n/a", "n/a",
- "GPP_D5", "ISH_I2C0_SDA", "n/a", "n/a",
- "GPP_D6", "ISH_I2C0_SCL", "n/a", "n/a",
- "GPP_D7", "ISH_I2C1_SDA", "n/a", "n/a",
- "GPP_D8", "ISH_I2C1_SCL", "n/a", "n/a",
- "GPP_D9", "n/a", "n/a", "n/a",
- "GPP_D10", "n/a", "n/a", "n/a",
- "GPP_D11", "n/a", "n/a", "n/a",
- "GPP_D12", "n/a", "n/a", "n/a",
- "GPP_D13", "ISH_UART0_RXD", "n/a", "n/a",
- "GPP_D14", "ISH_UART0_TXD", "n/a", "n/a",
- "GPP_D15", "ISH_UART0_RTS#", "n/a", "n/a",
- "GPP_D16", "ISH_UART0_CTS#", "n/a", "n/a",
- "GPP_D17", "DMIC_CLK1", "n/a", "n/a",
- "GPP_D18", "DMIC_DATA1", "n/a", "n/a",
- "GPP_D19", "DMIC_CLK0", "n/a", "n/a",
- "GPP_D20", "DMIC_DATA0", "n/a", "n/a",
- "GPP_D21", "SPI1_IO2", "n/a", "n/a",
- "GPP_D22", "SPI1_IO3", "n/a", "n/a",
- "GPP_D23", "I2S_MCLK", "n/a", "n/a",
-};
-
-static const struct gpio_group sunrise_lp_group_d = {
- .display = "------- GPIO Group GPP_D -------",
- .pad_count = ARRAY_SIZE(sunrise_lp_group_d_names) / 4,
- .func_count = 4,
- .pad_names = sunrise_lp_group_d_names,
-};
-
-static const char *const sunrise_group_e_names[] = {
- "GPP_E0", "SATAXPCIE0", "SATAGP0", "n/a",
- "GPP_E1", "SATAXPCIE1", "SATAGP1", "n/a",
- "GPP_E2", "SATAXPCIE2", "SATAGP2", "n/a",
- "GPP_E3", "CPU_GP0", "n/a", "n/a",
- "GPP_E4", "SATA_DEVSLP0", "n/a", "n/a",
- "GPP_E5", "SATA_DEVSLP1", "n/a", "n/a",
- "GPP_E6", "SATA_DEVSLP2", "n/a", "n/a",
- "GPP_E7", "CPU_GP1", "n/a", "n/a",
- "GPP_E8", "SATA_LED#", "n/a", "n/a",
- "GPP_E9", "USB_OC0#", "n/a", "n/a",
- "GPP_E10", "USB_OC1#", "n/a", "n/a",
- "GPP_E11", "USB_OC2#", "n/a", "n/a",
- "GPP_E12", "USB_OC3#", "n/a", "n/a",
-};
-
-static const struct gpio_group sunrise_group_e = {
- .display = "------- GPIO Group GPP_E -------",
- .pad_count = ARRAY_SIZE(sunrise_group_e_names) / 4,
- .func_count = 4,
- .pad_names = sunrise_group_e_names,
-};
-
-static const char *const sunrise_lp_group_e_names[] = {
- "GPP_E0", "SATAXPCIE0", "SATAGP0", "n/a",
- "GPP_E1", "SATAXPCIE1", "SATAGP1", "n/a",
- "GPP_E2", "SATAXPCIE2", "SATAGP2", "n/a",
- "GPP_E3", "CPU_GP0", "n/a", "n/a",
- "GPP_E4", "SATA_DEVSLP0", "n/a", "n/a",
- "GPP_E5", "SATA_DEVSLP1", "n/a", "n/a",
- "GPP_E6", "SATA_DEVSLP2", "n/a", "n/a",
- "GPP_E7", "CPU_GP1", "n/a", "n/a",
- "GPP_E8", "SATALED#", "n/a", "n/a",
- "GPP_E9", "USB2_OC0#", "n/a", "n/a",
- "GPP_E10", "USB2_OC1#", "n/a", "n/a",
- "GPP_E11", "USB2_OC2#", "n/a", "n/a",
- "GPP_E12", "USB2_OC3#", "n/a", "n/a",
- "GPP_E13", "DDPB_HPD0", "n/a", "n/a",
- "GPP_E14", "DDPC_HPD1", "n/a", "n/a",
- "GPP_E15", "DDPD_HPD2", "n/a", "n/a",
- "GPP_E16", "DDPE_HPD3", "n/a", "n/a",
- "GPP_E17", "EDP_HPD", "n/a", "n/a",
- "GPP_E18", "DDPB_CTRLCLK", "n/a", "n/a",
- "GPP_E19", "DDPB_CTRLDATA", "n/a", "n/a",
- "GPP_E20", "DDPC_CTRLCLK", "n/a", "n/a",
- "GPP_E21", "DDPC_CTRLDATA", "n/a", "n/a",
- "GPP_E22", "n/a", "n/a", "n/a",
- "GPP_E23", "n/a", "n/a", "n/a",
-};
-
-static const struct gpio_group sunrise_lp_group_e = {
- .display = "------- GPIO Group GPP_E -------",
- .pad_count = ARRAY_SIZE(sunrise_lp_group_e_names) / 4,
- .func_count = 4,
- .pad_names = sunrise_lp_group_e_names,
-};
-
-static const char *const sunrise_group_f_names[] = {
- "GPP_F0", "SATAXPCIE3", "SATAGP3", "n/a",
- "GPP_F1", "SATAXPCIE4", "SATAGP4", "n/a",
- "GPP_F2", "SATAXPCIE5", "SATAGP5", "n/a",
- "GPP_F3", "SATAXPCIE6", "SATAGP6", "n/a",
- "GPP_F4", "SATAXPCIE7", "SATAGP7", "n/a",
- "GPP_F5", "SATA_DEVSLP3", "n/a", "n/a",
- "GPP_F6", "SATA_DEVSLP4", "n/a", "n/a",
- "GPP_F7", "SATA_DEVSLP5", "n/a", "n/a",
- "GPP_F8", "SATA_DEVSLP6", "n/a", "n/a",
- "GPP_F9", "SATA_DEVSLP7", "n/a", "n/a",
- "GPP_F10", "SATA_SCLOCK", "n/a", "n/a",
- "GPP_F11", "SATA_SLOAD", "n/a", "n/a",
- "GPP_F12", "SATA_SDATAOUT1", "n/a", "n/a",
- "GPP_F13", "SATA_SDATAOUT2", "n/a", "n/a",
- "GPP_F14", "n/a", "n/a", "n/a",
- "GPP_F15", "USB_OC4#", "n/a", "n/a",
- "GPP_F16", "USB_OC5#", "n/a", "n/a",
- "GPP_F17", "USB_OC6#", "n/a", "n/a",
- "GPP_F18", "USB_OC7#", "n/a", "n/a",
- "GPP_F19", "eDP_VDDEN", "n/a", "n/a",
- "GPP_F20", "eDP_BKLTEN", "n/a", "n/a",
- "GPP_F21", "eDP_BKLTCTL", "n/a", "n/a",
- "GPP_F22", "n/a", "n/a", "n/a",
- "GPP_F23", "n/a", "n/a", "n/a",
-};
-
-static const struct gpio_group sunrise_group_f = {
- .display = "------- GPIO Group GPP_F -------",
- .pad_count = ARRAY_SIZE(sunrise_group_f_names) / 4,
- .func_count = 4,
- .pad_names = sunrise_group_f_names,
-};
-
-static const char *const sunrise_lp_group_f_names[] = {
- "GPP_F0", "I2S2_SCLK", "n/a", "n/a",
- "GPP_F1", "I2S2_SFRM", "n/a", "n/a",
- "GPP_F2", "I2S2_TXD", "n/a", "n/a",
- "GPP_F3", "I2S2_RXD", "n/a", "n/a",
- "GPP_F4", "I2C2_SDA", "n/a", "n/a",
- "GPP_F5", "I2C2_SCL", "n/a", "n/a",
- "GPP_F6", "I2C3_SDA", "n/a", "n/a",
- "GPP_F7", "I2C3_SCL", "n/a", "n/a",
- "GPP_F8", "I2C4_SDA", "n/a", "n/a",
- "GPP_F9", "I2C4_SCL", "n/a", "n/a",
- "GPP_F10", "I2C5_SDA", "ISH_I2C2_SDA", "n/a",
- "GPP_F11", "I2C5_SCL", "ISH_I2C2_SCL", "n/a",
- "GPP_F12", "EMMC_CMD", "n/a", "n/a",
- "GPP_F13", "EMMC_DATA0", "n/a", "n/a",
- "GPP_F14", "EMMC_DATA1", "n/a", "n/a",
- "GPP_F15", "EMMC_DATA2", "n/a", "n/a",
- "GPP_F16", "EMMC_DATA3", "n/a", "n/a",
- "GPP_F17", "EMMC_DATA4", "n/a", "n/a",
- "GPP_F18", "EMMC_DATA5", "n/a", "n/a",
- "GPP_F19", "EMMC_DATA6", "n/a", "n/a",
- "GPP_F20", "EMMC_DATA7", "n/a", "n/a",
- "GPP_F21", "EMMC_RCLK", "n/a", "n/a",
- "GPP_F22", "EMMC_CLK", "n/a", "n/a",
- "GPP_F23", "n/a", "n/a", "n/a",
-};
-
-static const struct gpio_group sunrise_lp_group_f = {
- .display = "------- GPIO Group GPP_F -------",
- .pad_count = ARRAY_SIZE(sunrise_lp_group_f_names) / 4,
- .func_count = 4,
- .pad_names = sunrise_lp_group_f_names,
-};
-
-static const char *const sunrise_group_g_names[] = {
- "GPP_G0", "FAN_TACH_0", "n/a", "n/a",
- "GPP_G1", "FAN_TACH_1", "n/a", "n/a",
- "GPP_G2", "FAN_TACH_2", "n/a", "n/a",
- "GPP_G3", "FAN_TACH_3", "n/a", "n/a",
- "GPP_G4", "FAN_TACH_4", "n/a", "n/a",
- "GPP_G5", "FAN_TACH_5", "n/a", "n/a",
- "GPP_G6", "FAN_TACH_6", "n/a", "n/a",
- "GPP_G7", "FAN_TACH_7", "n/a", "n/a",
- "GPP_G8", "FAN_PWM_0", "n/a", "n/a",
- "GPP_G9", "FAN_PWM_1", "n/a", "n/a",
- "GPP_G10", "FAN_PWM_2", "n/a", "n/a",
- "GPP_G11", "FAN_PWM_3", "n/a", "n/a",
- "GPP_G12", "GSXDOUT", "n/a", "n/a",
- "GPP_G13", "GSXSLOAD", "n/a", "n/a",
- "GPP_G14", "GSXDIN", "n/a", "n/a",
- "GPP_G15", "GSXRESET#", "n/a", "n/a",
- "GPP_G16", "GSXCLK", "n/a", "n/a",
- "GPP_G17", "ADR_COMPLETE", "n/a", "n/a",
- "GPP_G18", "NMI#", "n/a", "n/a",
- "GPP_G19", "SMI#", "n/a", "n/a",
- "GPP_G20", "n/a", "n/a", "n/a",
- "GPP_G21", "n/a", "n/a", "n/a",
- "GPP_G22", "n/a", "n/a", "n/a",
- "GPP_G23", "n/a", "n/a", "n/a",
-};
-
-static const struct gpio_group sunrise_group_g = {
- .display = "------- GPIO Group GPP_G -------",
- .pad_count = ARRAY_SIZE(sunrise_group_g_names) / 4,
- .func_count = 4,
- .pad_names = sunrise_group_g_names,
-};
-
-static const char *const sunrise_lp_group_g_names[] = {
- "GPP_G0", "SD_CMD", "n/a", "n/a",
- "GPP_G1", "SD_DATA0", "n/a", "n/a",
- "GPP_G2", "SD_DATA1", "n/a", "n/a",
- "GPP_G3", "SD_DATA2", "n/a", "n/a",
- "GPP_G4", "SD_DATA3", "n/a", "n/a",
- "GPP_G5", "SD_CD#", "n/a", "n/a",
- "GPP_G6", "SD_CLK", "n/a", "n/a",
- "GPP_G7", "SD_WP", "n/a", "n/a",
-};
-
-static const struct gpio_group sunrise_lp_group_g = {
- .display = "------- GPIO Group GPP_G -------",
- .pad_count = ARRAY_SIZE(sunrise_lp_group_g_names) / 4,
- .func_count = 4,
- .pad_names = sunrise_lp_group_g_names,
-};
-
-static const char *const sunrise_group_h_names[] = {
- "GPP_H0", "SRCCLKREQ6#", "n/a", "n/a",
- "GPP_H1", "SRCCLKREQ7#", "n/a", "n/a",
- "GPP_H2", "SRCCLKREQ8#", "n/a", "n/a",
- "GPP_H3", "SRCCLKREQ9#", "n/a", "n/a",
- "GPP_H4", "SRCCLKREQ10#", "n/a", "n/a",
- "GPP_H5", "SRCCLKREQ11#", "n/a", "n/a",
- "GPP_H6", "SRCCLKREQ12#", "n/a", "n/a",
- "GPP_H7", "SRCCLKREQ13#", "n/a", "n/a",
- "GPP_H8", "SRCCLKREQ14#", "n/a", "n/a",
- "GPP_H9", "SRCCLKREQ15#", "n/a", "n/a",
- "GPP_H10", "SML2CLK", "n/a", "n/a",
- "GPP_H11", "SML2DATA", "n/a", "n/a",
- "GPP_H12", "SML2ALERT#", "n/a", "n/a",
- "GPP_H13", "SML3CLK", "n/a", "n/a",
- "GPP_H14", "SML3DATA", "n/a", "n/a",
- "GPP_H15", "SML3ALERT#", "n/a", "n/a",
- "GPP_H16", "SML4CLK", "n/a", "n/a",
- "GPP_H17", "SML4DATA", "n/a", "n/a",
- "GPP_H18", "SML4ALERT#", "n/a", "n/a",
- "GPP_H19", "ISH_I2C0_SDA", "n/a", "n/a",
- "GPP_H20", "ISH_I2C0_SCL", "n/a", "n/a",
- "GPP_H21", "ISH_I2C1_SDA", "n/a", "n/a",
- "GPP_H22", "ISH_I2C1_SCL", "n/a", "n/a",
- "GPP_H23", "n/a", "n/a", "n/a",
-};
-
-static const struct gpio_group sunrise_group_h = {
- .display = "------- GPIO Group GPP_H -------",
- .pad_count = ARRAY_SIZE(sunrise_group_h_names) / 4,
- .func_count = 4,
- .pad_names = sunrise_group_h_names,
-};
-
-static const struct gpio_group *const sunrise_community_cdefgh_groups[] = {
- &sunrise_group_c, &sunrise_group_d, &sunrise_group_e,
- &sunrise_group_f, &sunrise_group_g, &sunrise_group_h,
-};
-
-static const struct gpio_group *const sunrise_lp_community_cde_groups[] = {
- &sunrise_group_c, &sunrise_lp_group_d, &sunrise_lp_group_e,
-};
-
-static const struct gpio_community sunrise_community_cdefgh = {
- .name = "------- GPIO Community 1 -------",
- .pcr_port_id = 0xae,
- .group_count = ARRAY_SIZE(sunrise_community_cdefgh_groups),
- .groups = sunrise_community_cdefgh_groups,
-};
-
-static const struct gpio_community sunrise_lp_community_cde = {
- .name = "------- GPIO Community 1 -------",
- .pcr_port_id = 0xae,
- .group_count = ARRAY_SIZE(sunrise_lp_community_cde_groups),
- .groups = sunrise_lp_community_cde_groups,
-};
-
-static const char *const sunrise_group_gpd_names[] = {
- "GPD0", "BATLOW#", "n/a", "n/a",
- "GPD1", "ACPRESENT", "n/a", "n/a",
- "GPD2", "LAN_WAKE#", "n/a", "n/a",
- "GPD3", "PWRBTN#", "n/a", "n/a",
- "GPD4", "SLP_S3#", "n/a", "n/a",
- "GPD5", "SLP_S4#", "n/a", "n/a",
- "GPD6", "SLP_A#", "n/a", "n/a",
- "GPD7", "RESERVED", "n/a", "n/a",
- "GPD8", "SUSCLK", "n/a", "n/a",
- "GPD9", "SLP_WLAN#", "n/a", "n/a",
- "GPD10", "SLP_S5#", "n/a", "n/a",
- "GPD11", "LANPHYPC", "n/a", "n/a",
-};
-
-static const struct gpio_group sunrise_group_gpd = {
- .display = "-------- GPIO Group GPD --------",
- .pad_count = ARRAY_SIZE(sunrise_group_gpd_names) / 4,
- .func_count = 4,
- .pad_names = sunrise_group_gpd_names,
-};
-
-static const struct gpio_group *const sunrise_community_gpd_groups[] = {
- &sunrise_group_gpd,
-};
-
-static const struct gpio_community sunrise_community_gpd = {
- .name = "------- GPIO Community 2 -------",
- .pcr_port_id = 0xad,
- .group_count = ARRAY_SIZE(sunrise_community_gpd_groups),
- .groups = sunrise_community_gpd_groups,
-};
-
-static const char *const sunrise_group_i_names[] = {
- "GPP_I0", "DDPB_HPD0", "n/a", "n/a",
- "GPP_I1", "DDPC_HPD1", "n/a", "n/a",
- "GPP_I2", "DDPD_HPD2", "n/a", "n/a",
- "GPP_I3", "DDPE_HPD3", "n/a", "n/a",
- "GPP_I4", "EDP_HPD", "n/a", "n/a",
- "GPP_I5", "DDPB_CTRLCLK", "n/a", "n/a",
- "GPP_I6", "DDPB_CTRLDATA", "n/a", "n/a",
- "GPP_I7", "DDPC_CTRLCLK", "n/a", "n/a",
- "GPP_I8", "DDPC_CTRLDATA", "n/a", "n/a",
- "GPP_I9", "DDPD_CTRLCLK", "n/a", "n/a",
- "GPP_I10", "DDPD_CTRLDATA", "n/a", "n/a",
-};
-
-static const struct gpio_group sunrise_group_i = {
- .display = "------- GPIO Group GPP_I -------",
- .pad_count = ARRAY_SIZE(sunrise_group_i_names) / 4,
- .func_count = 4,
- .pad_names = sunrise_group_i_names,
-};
-
-static const struct gpio_group *const sunrise_community_i_groups[] = {
- &sunrise_group_i,
-};
-
-static const struct gpio_group *const sunrise_lp_community_fg_groups[] = {
- &sunrise_lp_group_f, &sunrise_lp_group_g,
-};
-
-static const struct gpio_community sunrise_community_i = {
- .name = "------- GPIO Community 3 -------",
- .pcr_port_id = 0xac,
- .group_count = ARRAY_SIZE(sunrise_community_i_groups),
- .groups = sunrise_community_i_groups,
-};
-
-static const struct gpio_community sunrise_lp_community_fg = {
- .name = "------- GPIO Community 3 -------",
- .pcr_port_id = 0xac,
- .group_count = ARRAY_SIZE(sunrise_lp_community_fg_groups),
- .groups = sunrise_lp_community_fg_groups,
-};
-
-static const struct gpio_community *const sunrise_communities[] = {
- &sunrise_community_ab, &sunrise_community_cdefgh,
- &sunrise_community_gpd, &sunrise_community_i,
-};
-
-static const struct gpio_community *const sunrise_lp_communities[] = {
- &sunrise_lp_community_ab, &sunrise_lp_community_cde,
- &sunrise_community_gpd, &sunrise_lp_community_fg,
-};
-
-static const char *const denverton_group_north_all_names[] = {
- "NORTH_ALL_GBE0_SDP0",
- "NORTH_ALL_GBE1_SDP0",
- "NORTH_ALL_GBE0_SDP1",
- "NORTH_ALL_GBE1_SDP1",
- "NORTH_ALL_GBE0_SDP2",
- "NORTH_ALL_GBE1_SDP2",
- "NORTH_ALL_GBE0_SDP3",
- "NORTH_ALL_GBE1_SDP3",
- "NORTH_ALL_GBE2_LED0",
- "NORTH_ALL_GBE2_LED1",
- "NORTH_ALL_GBE0_I2C_CLK",
- "NORTH_ALL_GBE0_I2C_DATA",
- "NORTH_ALL_GBE1_I2C_CLK",
- "NORTH_ALL_GBE1_I2C_DATA",
- "NORTH_ALL_NCSI_RXD0",
- "NORTH_ALL_NCSI_CLK_IN",
- "NORTH_ALL_NCSI_RXD1",
- "NORTH_ALL_NCSI_CRS_DV",
- "NORTH_ALL_NCSI_ARB_IN",
- "NORTH_ALL_NCSI_TX_EN",
- "NORTH_ALL_NCSI_TXD0",
- "NORTH_ALL_NCSI_TXD1",
- "NORTH_ALL_NCSI_ARB_OUT",
- "NORTH_ALL_GBE0_LED0",
- "NORTH_ALL_GBE0_LED1",
- "NORTH_ALL_GBE1_LED0",
- "NORTH_ALL_GBE1_LED1",
- "NORTH_ALL_GPIO_0",
- "NORTH_ALL_PCIE_CLKREQ0_N",
- "NORTH_ALL_PCIE_CLKREQ1_N",
- "NORTH_ALL_PCIE_CLKREQ2_N",
- "NORTH_ALL_PCIE_CLKREQ3_N",
- "NORTH_ALL_PCIE_CLKREQ4_N",
- "NORTH_ALL_GPIO_1",
- "NORTH_ALL_GPIO_2",
- "NORTH_ALL_SVID_ALERT_N",
- "NORTH_ALL_SVID_DATA",
- "NORTH_ALL_SVID_CLK",
- "NORTH_ALL_THERMTRIP_N",
- "NORTH_ALL_PROCHOT_N",
- "NORTH_ALL_MEMHOT_N",
-};
-
-static const struct gpio_group denverton_group_north_all = {
- .display = "------- GPIO Group North All -------",
- .pad_count = ARRAY_SIZE(denverton_group_north_all_names) / 1,
- .func_count = 1,
- .pad_names = denverton_group_north_all_names,
-};
-
-static const struct gpio_group *const denverton_community_north_groups[] = {
- &denverton_group_north_all,
-};
-
-static const struct gpio_community denverton_community_north = {
- .name = "------- GPIO Community 0 -------",
- .pcr_port_id = 0xc2,
- .group_count = ARRAY_SIZE(denverton_community_north_groups),
- .groups = denverton_community_north_groups,
-};
-
-static const char *const denverton_group_south_dfx_names[] = {
- "SOUTH_DFX_DFX_PORT_CLK0",
- "SOUTH_DFX_DFX_PORT_CLK1",
- "SOUTH_DFX_DFX_PORT0",
- "SOUTH_DFX_DFX_PORT1",
- "SOUTH_DFX_DFX_PORT2",
- "SOUTH_DFX_DFX_PORT3",
- "SOUTH_DFX_DFX_PORT4",
- "SOUTH_DFX_DFX_PORT5",
- "SOUTH_DFX_DFX_PORT6",
- "SOUTH_DFX_DFX_PORT7",
- "SOUTH_DFX_DFX_PORT8",
- "SOUTH_DFX_DFX_PORT9",
- "SOUTH_DFX_DFX_PORT10",
- "SOUTH_DFX_DFX_PORT11",
- "SOUTH_DFX_DFX_PORT12",
- "SOUTH_DFX_DFX_PORT13",
- "SOUTH_DFX_DFX_PORT14",
- "SOUTH_DFX_DFX_PORT15",
-};
-
-static const struct gpio_group denverton_group_south_dfx = {
- .display = "------- GPIO Group South DFX -------",
- .pad_count = ARRAY_SIZE(denverton_group_south_dfx_names) / 1,
- .func_count = 1,
- .pad_names = denverton_group_south_dfx_names,
-};
-
-static const char *const denverton_group_south_group0_names[] = {
- "SOUTH_GROUP0_GPIO_12",
- "SOUTH_GROUP0_SMB5_GBE_ALRT_N",
- "SOUTH_GROUP0_PCIE_CLKREQ5_N",
- "SOUTH_GROUP0_PCIE_CLKREQ6_N",
- "SOUTH_GROUP0_PCIE_CLKREQ7_N",
- "SOUTH_GROUP0_UART0_RXD",
- "SOUTH_GROUP0_UART0_TXD",
- "SOUTH_GROUP0_SMB5_GBE_CLK",
- "SOUTH_GROUP0_SMB5_GBE_DATA",
- "SOUTH_GROUP0_ERROR2_N",
- "SOUTH_GROUP0_ERROR1_N",
- "SOUTH_GROUP0_ERROR0_N",
- "SOUTH_GROUP0_IERR_N",
- "SOUTH_GROUP0_MCERR_N",
- "SOUTH_GROUP0_SMB0_LEG_CLK",
- "SOUTH_GROUP0_SMB0_LEG_DATA",
- "SOUTH_GROUP0_SMB0_LEG_ALRT_N",
- "SOUTH_GROUP0_SMB1_HOST_DATA",
- "SOUTH_GROUP0_SMB1_HOST_CLK",
- "SOUTH_GROUP0_SMB2_PECI_DATA",
- "SOUTH_GROUP0_SMB2_PECI_CLK",
- "SOUTH_GROUP0_SMB4_CSME0_DATA",
- "SOUTH_GROUP0_SMB4_CSME0_CLK",
- "SOUTH_GROUP0_SMB4_CSME0_ALRT_N",
- "SOUTH_GROUP0_USB_OC0_N",
- "SOUTH_GROUP0_FLEX_CLK_SE0",
- "SOUTH_GROUP0_FLEX_CLK_SE1",
- "SOUTH_GROUP0_GPIO_4",
- "SOUTH_GROUP0_GPIO_5",
- "SOUTH_GROUP0_GPIO_6",
- "SOUTH_GROUP0_GPIO_7",
- "SOUTH_GROUP0_SATA0_LED_N",
- "SOUTH_GROUP0_SATA1_LED_N",
- "SOUTH_GROUP0_SATA_PDETECT0",
- "SOUTH_GROUP0_SATA_PDETECT1",
- "SOUTH_GROUP0_SATA0_SDOUT",
- "SOUTH_GROUP0_SATA1_SDOUT",
- "SOUTH_GROUP0_UART1_RXD",
- "SOUTH_GROUP0_UART1_TXD",
- "SOUTH_GROUP0_GPIO_8",
- "SOUTH_GROUP0_GPIO_9",
- "SOUTH_GROUP0_TCK",
- "SOUTH_GROUP0_TRST_N",
- "SOUTH_GROUP0_TMS",
- "SOUTH_GROUP0_TDI",
- "SOUTH_GROUP0_TDO",
- "SOUTH_GROUP0_CX_PRDY_N",
- "SOUTH_GROUP0_CX_PREQ_N",
- "SOUTH_GROUP0_CTBTRIGINOUT",
- "SOUTH_GROUP0_CTBTRIGOUT",
- "SOUTH_GROUP0_DFX_SPARE2",
- "SOUTH_GROUP0_DFX_SPARE3",
- "SOUTH_GROUP0_DFX_SPARE4",
-};
-
-static const struct gpio_group denverton_group_south_group0 = {
- .display = "------- GPIO Group South Group0 -------",
- .pad_count = ARRAY_SIZE(denverton_group_south_group0_names) / 1,
- .func_count = 1,
- .pad_names = denverton_group_south_group0_names,
-};
-
-static const char *const denverton_group_south_group1_names[] = {
- "SOUTH_GROUP1_SUSPWRDNACK",
- "SOUTH_GROUP1_PMU_SUSCLK",
- "SOUTH_GROUP1_ADR_TRIGGER",
- "SOUTH_GROUP1_PMU_SLP_S45_N",
- "SOUTH_GROUP1_PMU_SLP_S3_N",
- "SOUTH_GROUP1_PMU_WAKE_N",
- "SOUTH_GROUP1_PMU_PWRBTN_N",
- "SOUTH_GROUP1_PMU_RESETBUTTON_N",
- "SOUTH_GROUP1_PMU_PLTRST_N",
- "SOUTH_GROUP1_SUS_STAT_N",
- "SOUTH_GROUP1_SLP_S0IX_N",
- "SOUTH_GROUP1_SPI_CS0_N",
- "SOUTH_GROUP1_SPI_CS1_N",
- "SOUTH_GROUP1_SPI_MOSI_IO0",
- "SOUTH_GROUP1_SPI_MISO_IO1",
- "SOUTH_GROUP1_SPI_IO2",
- "SOUTH_GROUP1_SPI_IO3",
- "SOUTH_GROUP1_SPI_CLK",
- "SOUTH_GROUP1_SPI_CLK_LOOPBK",
- "SOUTH_GROUP1_ESPI_IO0",
- "SOUTH_GROUP1_ESPI_IO1",
- "SOUTH_GROUP1_ESPI_IO2",
- "SOUTH_GROUP1_ESPI_IO3",
- "SOUTH_GROUP1_ESPI_CS0_N",
- "SOUTH_GROUP1_ESPI_CLK",
- "SOUTH_GROUP1_ESPI_RST_N",
- "SOUTH_GROUP1_ESPI_ALRT0_N",
- "SOUTH_GROUP1_GPIO_10",
- "SOUTH_GROUP1_GPIO_11",
- "SOUTH_GROUP1_ESPI_CLK_LOOPBK",
- "SOUTH_GROUP1_EMMC_CMD",
- "SOUTH_GROUP1_EMMC_STROBE",
- "SOUTH_GROUP1_EMMC_CLK",
- "SOUTH_GROUP1_EMMC_D0",
- "SOUTH_GROUP1_EMMC_D1",
- "SOUTH_GROUP1_EMMC_D2",
- "SOUTH_GROUP1_EMMC_D3",
- "SOUTH_GROUP1_EMMC_D4",
- "SOUTH_GROUP1_EMMC_D5",
- "SOUTH_GROUP1_EMMC_D6",
- "SOUTH_GROUP1_EMMC_D7",
- "SOUTH_GROUP1_GPIO_3",
-};
-
-static const struct gpio_group denverton_group_south_group1 = {
- .display = "------- GPIO Group South Group1 -------",
- .pad_count = ARRAY_SIZE(denverton_group_south_group1_names) / 1,
- .func_count = 1,
- .pad_names = denverton_group_south_group1_names,
-};
-
-static const struct gpio_group *const denverton_community_south_groups[] = {
- &denverton_group_south_dfx,
- &denverton_group_south_group0,
- &denverton_group_south_group1,
-};
-
-static const struct gpio_community denverton_community_south = {
- .name = "------- GPIO Community 1 -------",
- .pcr_port_id = 0xc5,
- .group_count = ARRAY_SIZE(denverton_community_south_groups),
- .groups = denverton_community_south_groups,
-};
-
-static const struct gpio_community *const denverton_communities[] = {
- &denverton_community_north, &denverton_community_south,
-};
-
static const char *decode_pad_mode(const struct gpio_group *const group,
const size_t pad, const uint32_t dw0)
{
diff --git a/util/inteltool/gpio_sunrise.h b/util/inteltool/gpio_sunrise.h
new file mode 100644
index 0000000..5553b7d
--- /dev/null
+++ b/util/inteltool/gpio_sunrise.h
@@ -0,0 +1,595 @@
+/*
+ * inteltool - dump all registers on an Intel CPU + chipset based system.
+ *
+ * Copyright (C) 2017 secunet Security Networks AG
+ * Copyright (C) 2019 Felix Singer <migy(a)darmstadt.ccc.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+static const char *const sunrise_group_a_names[] = {
+ "GPP_A0", "RCIN#", "n/a", "ESPI_ALERT1#",
+ "GPP_A1", "LAD0", "n/a", "ESPI_IO0",
+ "GPP_A2", "LAD1", "n/a", "ESPI_IO1",
+ "GPP_A3", "LAD2", "n/a", "ESPI_IO2",
+ "GPP_A4", "LAD3", "n/a", "ESPI_IO3",
+ "GPP_A5", "LFRAME#", "n/a", "ESPI_CS#",
+ "GPP_A6", "SERIRQ", "n/a", "ESPI_CS1#",
+ "GPP_A7", "PIRQA#", "n/a", "ESPI_ALERT0#",
+ "GPP_A8", "CLKRUN#", "n/a", "n/a",
+ "GPP_A9", "CLKOUT_LPC0", "n/a", "ESPI_CLK",
+ "GPP_A10", "CLKOUT_LPC1", "n/a", "n/a",
+ "GPP_A11", "PME#", "n/a", "n/a",
+ "GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#",
+ "GPP_A13", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a",
+ "GPP_A14", "SUS_STAT#", "n/a", "ESPI_RESET#",
+ "GPP_A15", "SUS_ACK#", "n/a", "n/a",
+ "GPP_A16", "CLKOUT_48", "n/a", "n/a",
+ "GPP_A17", "ISH_GP7", "n/a", "n/a",
+ "GPP_A18", "ISH_GP0", "n/a", "n/a",
+ "GPP_A19", "ISH_GP1", "n/a", "n/a",
+ "GPP_A20", "ISH_GP2", "n/a", "n/a",
+ "GPP_A21", "ISH_GP3", "n/a", "n/a",
+ "GPP_A22", "ISH_GP4", "n/a", "n/a",
+ "GPP_A23", "ISH_GP5", "n/a", "n/a",
+};
+
+static const struct gpio_group sunrise_group_a = {
+ .display = "------- GPIO Group GPP_A -------",
+ .pad_count = ARRAY_SIZE(sunrise_group_a_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_group_a_names,
+};
+
+static const char *const sunrise_lp_group_a_names[] = {
+ "GPP_A0", "RCIN#", "n/a", "n/a",
+ "GPP_A1", "LAD0", "n/a", "ESPI_IO0",
+ "GPP_A2", "LAD1", "n/a", "ESPI_IO1",
+ "GPP_A3", "LAD2", "n/a", "ESPI_IO2",
+ "GPP_A4", "LAD3", "n/a", "ESPI_IO3",
+ "GPP_A5", "LFRAME#", "n/a", "ESPI_CS#",
+ "GPP_A6", "SERIRQ", "n/a", "n/a",
+ "GPP_A7", "PIRQA#", "n/a", "n/a",
+ "GPP_A8", "CLKRUN#", "n/a", "n/a",
+ "GPP_A9", "CLKOUT_LPC0", "n/a", "ESPI_CLK",
+ "GPP_A10", "CLKOUT_LPC1", "n/a", "n/a",
+ "GPP_A11", "PME#", "n/a", "n/a",
+ "GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#",
+ "GPP_A13", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a",
+ "GPP_A14", "SUS_STAT#", "n/a", "ESPI_RESET#",
+ "GPP_A15", "SUS_ACK#", "n/a", "n/a",
+ "GPP_A16", "SD_1P8_SEL", "n/a", "n/a",
+ "GPP_A17", "SD_PWR_EN#", "ISH_GP7", "n/a",
+ "GPP_A18", "ISH_GP0", "n/a", "n/a",
+ "GPP_A19", "ISH_GP1", "n/a", "n/a",
+ "GPP_A20", "ISH_GP2", "n/a", "n/a",
+ "GPP_A21", "ISH_GP3", "n/a", "n/a",
+ "GPP_A22", "ISH_GP4", "n/a", "n/a",
+ "GPP_A23", "ISH_GP5", "n/a", "n/a",
+};
+
+static const struct gpio_group sunrise_lp_group_a = {
+ .display = "------- GPIO group GPP_A -------",
+ .pad_count = ARRAY_SIZE(sunrise_lp_group_a_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_lp_group_a_names,
+};
+
+static const char *const sunrise_group_b_names[] = {
+ "GPP_B0", "n/a", "n/a", "n/a",
+ "GPP_B1", "n/a", "n/a", "n/a",
+ "GPP_B2", "VRALERT#", "n/a", "n/a",
+ "GPP_B3", "CPU_GP2", "n/a", "n/a",
+ "GPP_B4", "CPU_GP3", "n/a", "n/a",
+ "GPP_B5", "SRCCLKREQ0#", "n/a", "n/a",
+ "GPP_B6", "SRCCLKREQ1#", "n/a", "n/a",
+ "GPP_B7", "SRCCLKREQ2#", "n/a", "n/a",
+ "GPP_B8", "SRCCLKREQ3#", "n/a", "n/a",
+ "GPP_B9", "SRCCLKREQ4#", "n/a", "n/a",
+ "GPP_B10", "SRCCLKREQ5#", "n/a", "n/a",
+ "GPP_B11", "n/a", "n/a", "n/a",
+ "GPP_B12", "SLP_S0#", "n/a", "n/a",
+ "GPP_B13", "PLTRST#", "n/a", "n/a",
+ "GPP_B14", "SPKR", "n/a", "n/a",
+ "GPP_B15", "GSPIO_CS#", "n/a", "n/a",
+ "GPP_B16", "GSPIO_CLK", "n/a", "n/a",
+ "GPP_B17", "GSPIO_MISO", "n/a", "n/a",
+ "GPP_B18", "GSPIO_MOSI", "n/a", "n/a",
+ "GPP_B19", "GSPI1_CS#", "n/a", "n/a",
+ "GPP_B20", "GSPI1_CLK", "n/a", "n/a",
+ "GPP_B21", "GSPI1_MISO", "n/a", "n/a",
+ "GPP_B22", "GSPI1_MOSI", "n/a", "n/a",
+ "GPP_B23", "SML1ALERT#", "PCHHOT#", "n/a",
+};
+
+static const struct gpio_group sunrise_group_b = {
+ .display = "------- GPIO Group GPP_B -------",
+ .pad_count = ARRAY_SIZE(sunrise_group_b_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_group_b_names,
+};
+
+static const char *const sunrise_lp_group_b_names[] = {
+ "GPP_B0", "CORE_VID0", "n/a", "n/a",
+ "GPP_B1", "CORE_VID1", "n/a", "n/a",
+ "GPP_B2", "VRALERT#", "n/a", "n/a",
+ "GPP_B3", "CPU_GP2", "n/a", "n/a",
+ "GPP_B4", "CPU_GP3", "n/a", "n/a",
+ "GPP_B5", "SRCCLKREQ0#", "n/a", "n/a",
+ "GPP_B6", "SRCCLKREQ1#", "n/a", "n/a",
+ "GPP_B7", "SRCCLKREQ2#", "n/a", "n/a",
+ "GPP_B8", "SRCCLKREQ3#", "n/a", "n/a",
+ "GPP_B9", "SRCCLKREQ4#", "n/a", "n/a",
+ "GPP_B10", "SRCCLKREQ5#", "n/a", "n/a",
+ "GPP_B11", "EXT_PWR_GATE#", "n/a", "n/a",
+ "GPP_B12", "SLP_S0#", "n/a", "n/a",
+ "GPP_B13", "PLTRST#", "n/a", "n/a",
+ "GPP_B14", "SPKR", "n/a", "n/a",
+ "GPP_B15", "GSPI0_CS#", "n/a", "n/a",
+ "GPP_B16", "GSPI0_CLK", "n/a", "n/a",
+ "GPP_B17", "GSPI0_MISO", "n/a", "n/a",
+ "GPP_B18", "GSPI0_MOSI", "n/a", "n/a",
+ "GPP_B19", "GSPI1_CS#", "n/a", "n/a",
+ "GPP_B20", "GSPI1_CLK", "n/a", "n/a",
+ "GPP_B21", "GSPI1_MISO", "n/a", "n/a",
+ "GPP_B22", "GSPI1_MOSI", "n/a", "n/a",
+ "GPP_B23", "SML1ALERT#", "PCHHOT#", "n/a",
+};
+
+static const struct gpio_group sunrise_lp_group_b = {
+ .display = "------- GPIO Group GPP_B -------",
+ .pad_count = ARRAY_SIZE(sunrise_lp_group_b_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_lp_group_b_names,
+};
+
+static const struct gpio_group *const sunrise_community_ab_groups[] = {
+ &sunrise_group_a, &sunrise_group_b,
+};
+
+static const struct gpio_group *const sunrise_lp_community_ab_groups[] = {
+ &sunrise_lp_group_a, &sunrise_lp_group_b,
+};
+
+static const struct gpio_community sunrise_community_ab = {
+ .name = "------- GPIO Community 0 -------",
+ .pcr_port_id = 0xaf,
+ .group_count = ARRAY_SIZE(sunrise_community_ab_groups),
+ .groups = sunrise_community_ab_groups,
+};
+
+static const struct gpio_community sunrise_lp_community_ab = {
+ .name = "------- GPIO Community 0 -------",
+ .pcr_port_id = 0xaf,
+ .group_count = ARRAY_SIZE(sunrise_lp_community_ab_groups),
+ .groups = sunrise_lp_community_ab_groups,
+};
+
+static const char *const sunrise_group_c_names[] = {
+ "GPP_C0", "SMBCLK", "n/a", "n/a",
+ "GPP_C1", "SMBDATA", "n/a", "n/a",
+ "GPP_C2", "SMBALERT#", "n/a", "n/a",
+ "GPP_C3", "SML0CLK", "n/a", "n/a",
+ "GPP_C4", "SML0DATA", "n/a", "n/a",
+ "GPP_C5", "SML0ALERT#", "n/a", "n/a",
+ "GPP_C6", "SML1CLK", "n/a", "n/a",
+ "GPP_C7", "SML1DATA", "n/a", "n/a",
+ "GPP_C8", "UART0_RXD", "n/a", "n/a",
+ "GPP_C9", "UART0_TXD", "n/a", "n/a",
+ "GPP_C10", "UART0_RTS#", "n/a", "n/a",
+ "GPP_C11", "UART0_CTS#", "n/a", "n/a",
+ "GPP_C12", "UART1_RXD", "ISH_UART1_RXD", "n/a",
+ "GPP_C13", "UART1_TXD", "ISH_UART1_TXD", "n/a",
+ "GPP_C14", "UART1_RTS#", "ISH_UART1_RTS#", "n/a",
+ "GPP_C15", "UART1_CTS#", "ISH_UART1_CTS#", "n/a",
+ "GPP_C16", "I2C0_SDA", "n/a", "n/a",
+ "GPP_C17", "I2C0_SCL", "n/a", "n/a",
+ "GPP_C18", "I2C1_SDA", "n/a", "n/a",
+ "GPP_C19", "I2C1_SCL", "n/a", "n/a",
+ "GPP_C20", "UART2_RXD", "n/a", "n/a",
+ "GPP_C21", "UART2_TXD", "n/a", "n/a",
+ "GPP_C22", "UART2_RTS#", "n/a", "n/a",
+ "GPP_C23", "UART2_CTS#", "n/a", "n/a",
+};
+
+static const struct gpio_group sunrise_group_c = {
+ .display = "------- GPIO Group GPP_C -------",
+ .pad_count = ARRAY_SIZE(sunrise_group_c_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_group_c_names,
+};
+
+static const char *const sunrise_group_d_names[] = {
+ "GPP_D0", "n/a", "n/a", "n/a",
+ "GPP_D1", "n/a", "n/a", "n/a",
+ "GPP_D2", "n/a", "n/a", "n/a",
+ "GPP_D3", "n/a", "n/a", "n/a",
+ "GPP_D4", "ISH_I2C2_SDA", "I2C3_SDA", "n/a",
+ "GPP_D5", "I2S_SFRM", "n/a", "n/a",
+ "GPP_D6", "I2S_TXD", "n/a", "n/a",
+ "GPP_D7", "I2S_RXD", "n/a", "n/a",
+ "GPP_D8", "I2S_SCLK", "n/a", "n/a",
+ "GPP_D9", "n/a", "n/a", "n/a",
+ "GPP_D10", "n/a", "n/a", "n/a",
+ "GPP_D11", "n/a", "n/a", "n/a",
+ "GPP_D12", "n/a", "n/a", "n/a",
+ "GPP_D13", "ISH_UART0_RXD", "n/a", "I2C2_SDA",
+ "GPP_D14", "ISH_UART0_TXD", "n/a", "I2C2_SCL",
+ "GPP_D15", "ISH_UART0_RTS#", "n/a", "n/a",
+ "GPP_D16", "ISH_UART0_CTS#", "n/a", "n/a",
+ "GPP_D17", "DMIC_CLK1", "n/a", "n/a",
+ "GPP_D18", "DMIC_DATA1", "n/a", "n/a",
+ "GPP_D19", "DMIC_CLK0", "n/a", "n/a",
+ "GPP_D20", "DMIC_DATA0", "n/a", "n/a",
+ "GPP_D21", "n/a", "n/a", "n/a",
+ "GPP_D22", "n/a", "n/a", "n/a",
+ "GPP_D23", "ISH_I2C2_SCL", "I2C3_SCL", "n/a",
+};
+
+static const struct gpio_group sunrise_group_d = {
+ .display = "------- GPIO Group GPP_D -------",
+ .pad_count = ARRAY_SIZE(sunrise_group_d_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_group_d_names,
+};
+
+static const char *const sunrise_lp_group_d_names[] = {
+ "GPP_D0", "SPI1_CS#", "n/a", "n/a",
+ "GPP_D1", "SPI1_CLK", "n/a", "n/a",
+ "GPP_D2", "SPI1_MISO", "n/a", "n/a",
+ "GPP_D3", "SPI1_MOSI", "n/a", "n/a",
+ "GPP_D4", "FLASHTRIG", "n/a", "n/a",
+ "GPP_D5", "ISH_I2C0_SDA", "n/a", "n/a",
+ "GPP_D6", "ISH_I2C0_SCL", "n/a", "n/a",
+ "GPP_D7", "ISH_I2C1_SDA", "n/a", "n/a",
+ "GPP_D8", "ISH_I2C1_SCL", "n/a", "n/a",
+ "GPP_D9", "n/a", "n/a", "n/a",
+ "GPP_D10", "n/a", "n/a", "n/a",
+ "GPP_D11", "n/a", "n/a", "n/a",
+ "GPP_D12", "n/a", "n/a", "n/a",
+ "GPP_D13", "ISH_UART0_RXD", "n/a", "n/a",
+ "GPP_D14", "ISH_UART0_TXD", "n/a", "n/a",
+ "GPP_D15", "ISH_UART0_RTS#", "n/a", "n/a",
+ "GPP_D16", "ISH_UART0_CTS#", "n/a", "n/a",
+ "GPP_D17", "DMIC_CLK1", "n/a", "n/a",
+ "GPP_D18", "DMIC_DATA1", "n/a", "n/a",
+ "GPP_D19", "DMIC_CLK0", "n/a", "n/a",
+ "GPP_D20", "DMIC_DATA0", "n/a", "n/a",
+ "GPP_D21", "SPI1_IO2", "n/a", "n/a",
+ "GPP_D22", "SPI1_IO3", "n/a", "n/a",
+ "GPP_D23", "I2S_MCLK", "n/a", "n/a",
+};
+
+static const struct gpio_group sunrise_lp_group_d = {
+ .display = "------- GPIO Group GPP_D -------",
+ .pad_count = ARRAY_SIZE(sunrise_lp_group_d_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_lp_group_d_names,
+};
+
+static const char *const sunrise_group_e_names[] = {
+ "GPP_E0", "SATAXPCIE0", "SATAGP0", "n/a",
+ "GPP_E1", "SATAXPCIE1", "SATAGP1", "n/a",
+ "GPP_E2", "SATAXPCIE2", "SATAGP2", "n/a",
+ "GPP_E3", "CPU_GP0", "n/a", "n/a",
+ "GPP_E4", "SATA_DEVSLP0", "n/a", "n/a",
+ "GPP_E5", "SATA_DEVSLP1", "n/a", "n/a",
+ "GPP_E6", "SATA_DEVSLP2", "n/a", "n/a",
+ "GPP_E7", "CPU_GP1", "n/a", "n/a",
+ "GPP_E8", "SATA_LED#", "n/a", "n/a",
+ "GPP_E9", "USB_OC0#", "n/a", "n/a",
+ "GPP_E10", "USB_OC1#", "n/a", "n/a",
+ "GPP_E11", "USB_OC2#", "n/a", "n/a",
+ "GPP_E12", "USB_OC3#", "n/a", "n/a",
+};
+
+static const struct gpio_group sunrise_group_e = {
+ .display = "------- GPIO Group GPP_E -------",
+ .pad_count = ARRAY_SIZE(sunrise_group_e_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_group_e_names,
+};
+
+static const char *const sunrise_lp_group_e_names[] = {
+ "GPP_E0", "SATAXPCIE0", "SATAGP0", "n/a",
+ "GPP_E1", "SATAXPCIE1", "SATAGP1", "n/a",
+ "GPP_E2", "SATAXPCIE2", "SATAGP2", "n/a",
+ "GPP_E3", "CPU_GP0", "n/a", "n/a",
+ "GPP_E4", "SATA_DEVSLP0", "n/a", "n/a",
+ "GPP_E5", "SATA_DEVSLP1", "n/a", "n/a",
+ "GPP_E6", "SATA_DEVSLP2", "n/a", "n/a",
+ "GPP_E7", "CPU_GP1", "n/a", "n/a",
+ "GPP_E8", "SATALED#", "n/a", "n/a",
+ "GPP_E9", "USB2_OC0#", "n/a", "n/a",
+ "GPP_E10", "USB2_OC1#", "n/a", "n/a",
+ "GPP_E11", "USB2_OC2#", "n/a", "n/a",
+ "GPP_E12", "USB2_OC3#", "n/a", "n/a",
+ "GPP_E13", "DDPB_HPD0", "n/a", "n/a",
+ "GPP_E14", "DDPC_HPD1", "n/a", "n/a",
+ "GPP_E15", "DDPD_HPD2", "n/a", "n/a",
+ "GPP_E16", "DDPE_HPD3", "n/a", "n/a",
+ "GPP_E17", "EDP_HPD", "n/a", "n/a",
+ "GPP_E18", "DDPB_CTRLCLK", "n/a", "n/a",
+ "GPP_E19", "DDPB_CTRLDATA", "n/a", "n/a",
+ "GPP_E20", "DDPC_CTRLCLK", "n/a", "n/a",
+ "GPP_E21", "DDPC_CTRLDATA", "n/a", "n/a",
+ "GPP_E22", "n/a", "n/a", "n/a",
+ "GPP_E23", "n/a", "n/a", "n/a",
+};
+
+static const struct gpio_group sunrise_lp_group_e = {
+ .display = "------- GPIO Group GPP_E -------",
+ .pad_count = ARRAY_SIZE(sunrise_lp_group_e_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_lp_group_e_names,
+};
+
+static const char *const sunrise_group_f_names[] = {
+ "GPP_F0", "SATAXPCIE3", "SATAGP3", "n/a",
+ "GPP_F1", "SATAXPCIE4", "SATAGP4", "n/a",
+ "GPP_F2", "SATAXPCIE5", "SATAGP5", "n/a",
+ "GPP_F3", "SATAXPCIE6", "SATAGP6", "n/a",
+ "GPP_F4", "SATAXPCIE7", "SATAGP7", "n/a",
+ "GPP_F5", "SATA_DEVSLP3", "n/a", "n/a",
+ "GPP_F6", "SATA_DEVSLP4", "n/a", "n/a",
+ "GPP_F7", "SATA_DEVSLP5", "n/a", "n/a",
+ "GPP_F8", "SATA_DEVSLP6", "n/a", "n/a",
+ "GPP_F9", "SATA_DEVSLP7", "n/a", "n/a",
+ "GPP_F10", "SATA_SCLOCK", "n/a", "n/a",
+ "GPP_F11", "SATA_SLOAD", "n/a", "n/a",
+ "GPP_F12", "SATA_SDATAOUT1", "n/a", "n/a",
+ "GPP_F13", "SATA_SDATAOUT2", "n/a", "n/a",
+ "GPP_F14", "n/a", "n/a", "n/a",
+ "GPP_F15", "USB_OC4#", "n/a", "n/a",
+ "GPP_F16", "USB_OC5#", "n/a", "n/a",
+ "GPP_F17", "USB_OC6#", "n/a", "n/a",
+ "GPP_F18", "USB_OC7#", "n/a", "n/a",
+ "GPP_F19", "eDP_VDDEN", "n/a", "n/a",
+ "GPP_F20", "eDP_BKLTEN", "n/a", "n/a",
+ "GPP_F21", "eDP_BKLTCTL", "n/a", "n/a",
+ "GPP_F22", "n/a", "n/a", "n/a",
+ "GPP_F23", "n/a", "n/a", "n/a",
+};
+
+static const struct gpio_group sunrise_group_f = {
+ .display = "------- GPIO Group GPP_F -------",
+ .pad_count = ARRAY_SIZE(sunrise_group_f_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_group_f_names,
+};
+
+static const char *const sunrise_lp_group_f_names[] = {
+ "GPP_F0", "I2S2_SCLK", "n/a", "n/a",
+ "GPP_F1", "I2S2_SFRM", "n/a", "n/a",
+ "GPP_F2", "I2S2_TXD", "n/a", "n/a",
+ "GPP_F3", "I2S2_RXD", "n/a", "n/a",
+ "GPP_F4", "I2C2_SDA", "n/a", "n/a",
+ "GPP_F5", "I2C2_SCL", "n/a", "n/a",
+ "GPP_F6", "I2C3_SDA", "n/a", "n/a",
+ "GPP_F7", "I2C3_SCL", "n/a", "n/a",
+ "GPP_F8", "I2C4_SDA", "n/a", "n/a",
+ "GPP_F9", "I2C4_SCL", "n/a", "n/a",
+ "GPP_F10", "I2C5_SDA", "ISH_I2C2_SDA", "n/a",
+ "GPP_F11", "I2C5_SCL", "ISH_I2C2_SCL", "n/a",
+ "GPP_F12", "EMMC_CMD", "n/a", "n/a",
+ "GPP_F13", "EMMC_DATA0", "n/a", "n/a",
+ "GPP_F14", "EMMC_DATA1", "n/a", "n/a",
+ "GPP_F15", "EMMC_DATA2", "n/a", "n/a",
+ "GPP_F16", "EMMC_DATA3", "n/a", "n/a",
+ "GPP_F17", "EMMC_DATA4", "n/a", "n/a",
+ "GPP_F18", "EMMC_DATA5", "n/a", "n/a",
+ "GPP_F19", "EMMC_DATA6", "n/a", "n/a",
+ "GPP_F20", "EMMC_DATA7", "n/a", "n/a",
+ "GPP_F21", "EMMC_RCLK", "n/a", "n/a",
+ "GPP_F22", "EMMC_CLK", "n/a", "n/a",
+ "GPP_F23", "n/a", "n/a", "n/a",
+};
+
+static const struct gpio_group sunrise_lp_group_f = {
+ .display = "------- GPIO Group GPP_F -------",
+ .pad_count = ARRAY_SIZE(sunrise_lp_group_f_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_lp_group_f_names,
+};
+
+static const char *const sunrise_group_g_names[] = {
+ "GPP_G0", "FAN_TACH_0", "n/a", "n/a",
+ "GPP_G1", "FAN_TACH_1", "n/a", "n/a",
+ "GPP_G2", "FAN_TACH_2", "n/a", "n/a",
+ "GPP_G3", "FAN_TACH_3", "n/a", "n/a",
+ "GPP_G4", "FAN_TACH_4", "n/a", "n/a",
+ "GPP_G5", "FAN_TACH_5", "n/a", "n/a",
+ "GPP_G6", "FAN_TACH_6", "n/a", "n/a",
+ "GPP_G7", "FAN_TACH_7", "n/a", "n/a",
+ "GPP_G8", "FAN_PWM_0", "n/a", "n/a",
+ "GPP_G9", "FAN_PWM_1", "n/a", "n/a",
+ "GPP_G10", "FAN_PWM_2", "n/a", "n/a",
+ "GPP_G11", "FAN_PWM_3", "n/a", "n/a",
+ "GPP_G12", "GSXDOUT", "n/a", "n/a",
+ "GPP_G13", "GSXSLOAD", "n/a", "n/a",
+ "GPP_G14", "GSXDIN", "n/a", "n/a",
+ "GPP_G15", "GSXRESET#", "n/a", "n/a",
+ "GPP_G16", "GSXCLK", "n/a", "n/a",
+ "GPP_G17", "ADR_COMPLETE", "n/a", "n/a",
+ "GPP_G18", "NMI#", "n/a", "n/a",
+ "GPP_G19", "SMI#", "n/a", "n/a",
+ "GPP_G20", "n/a", "n/a", "n/a",
+ "GPP_G21", "n/a", "n/a", "n/a",
+ "GPP_G22", "n/a", "n/a", "n/a",
+ "GPP_G23", "n/a", "n/a", "n/a",
+};
+
+static const struct gpio_group sunrise_group_g = {
+ .display = "------- GPIO Group GPP_G -------",
+ .pad_count = ARRAY_SIZE(sunrise_group_g_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_group_g_names,
+};
+
+static const char *const sunrise_lp_group_g_names[] = {
+ "GPP_G0", "SD_CMD", "n/a", "n/a",
+ "GPP_G1", "SD_DATA0", "n/a", "n/a",
+ "GPP_G2", "SD_DATA1", "n/a", "n/a",
+ "GPP_G3", "SD_DATA2", "n/a", "n/a",
+ "GPP_G4", "SD_DATA3", "n/a", "n/a",
+ "GPP_G5", "SD_CD#", "n/a", "n/a",
+ "GPP_G6", "SD_CLK", "n/a", "n/a",
+ "GPP_G7", "SD_WP", "n/a", "n/a",
+};
+
+static const struct gpio_group sunrise_lp_group_g = {
+ .display = "------- GPIO Group GPP_G -------",
+ .pad_count = ARRAY_SIZE(sunrise_lp_group_g_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_lp_group_g_names,
+};
+
+static const char *const sunrise_group_h_names[] = {
+ "GPP_H0", "SRCCLKREQ6#", "n/a", "n/a",
+ "GPP_H1", "SRCCLKREQ7#", "n/a", "n/a",
+ "GPP_H2", "SRCCLKREQ8#", "n/a", "n/a",
+ "GPP_H3", "SRCCLKREQ9#", "n/a", "n/a",
+ "GPP_H4", "SRCCLKREQ10#", "n/a", "n/a",
+ "GPP_H5", "SRCCLKREQ11#", "n/a", "n/a",
+ "GPP_H6", "SRCCLKREQ12#", "n/a", "n/a",
+ "GPP_H7", "SRCCLKREQ13#", "n/a", "n/a",
+ "GPP_H8", "SRCCLKREQ14#", "n/a", "n/a",
+ "GPP_H9", "SRCCLKREQ15#", "n/a", "n/a",
+ "GPP_H10", "SML2CLK", "n/a", "n/a",
+ "GPP_H11", "SML2DATA", "n/a", "n/a",
+ "GPP_H12", "SML2ALERT#", "n/a", "n/a",
+ "GPP_H13", "SML3CLK", "n/a", "n/a",
+ "GPP_H14", "SML3DATA", "n/a", "n/a",
+ "GPP_H15", "SML3ALERT#", "n/a", "n/a",
+ "GPP_H16", "SML4CLK", "n/a", "n/a",
+ "GPP_H17", "SML4DATA", "n/a", "n/a",
+ "GPP_H18", "SML4ALERT#", "n/a", "n/a",
+ "GPP_H19", "ISH_I2C0_SDA", "n/a", "n/a",
+ "GPP_H20", "ISH_I2C0_SCL", "n/a", "n/a",
+ "GPP_H21", "ISH_I2C1_SDA", "n/a", "n/a",
+ "GPP_H22", "ISH_I2C1_SCL", "n/a", "n/a",
+ "GPP_H23", "n/a", "n/a", "n/a",
+};
+
+static const struct gpio_group sunrise_group_h = {
+ .display = "------- GPIO Group GPP_H -------",
+ .pad_count = ARRAY_SIZE(sunrise_group_h_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_group_h_names,
+};
+
+static const struct gpio_group *const sunrise_community_cdefgh_groups[] = {
+ &sunrise_group_c, &sunrise_group_d, &sunrise_group_e,
+ &sunrise_group_f, &sunrise_group_g, &sunrise_group_h,
+};
+
+static const struct gpio_group *const sunrise_lp_community_cde_groups[] = {
+ &sunrise_group_c, &sunrise_lp_group_d, &sunrise_lp_group_e,
+};
+
+static const struct gpio_community sunrise_community_cdefgh = {
+ .name = "------- GPIO Community 1 -------",
+ .pcr_port_id = 0xae,
+ .group_count = ARRAY_SIZE(sunrise_community_cdefgh_groups),
+ .groups = sunrise_community_cdefgh_groups,
+};
+
+static const struct gpio_community sunrise_lp_community_cde = {
+ .name = "------- GPIO Community 1 -------",
+ .pcr_port_id = 0xae,
+ .group_count = ARRAY_SIZE(sunrise_lp_community_cde_groups),
+ .groups = sunrise_lp_community_cde_groups,
+};
+
+static const char *const sunrise_group_gpd_names[] = {
+ "GPD0", "BATLOW#", "n/a", "n/a",
+ "GPD1", "ACPRESENT", "n/a", "n/a",
+ "GPD2", "LAN_WAKE#", "n/a", "n/a",
+ "GPD3", "PWRBTN#", "n/a", "n/a",
+ "GPD4", "SLP_S3#", "n/a", "n/a",
+ "GPD5", "SLP_S4#", "n/a", "n/a",
+ "GPD6", "SLP_A#", "n/a", "n/a",
+ "GPD7", "RESERVED", "n/a", "n/a",
+ "GPD8", "SUSCLK", "n/a", "n/a",
+ "GPD9", "SLP_WLAN#", "n/a", "n/a",
+ "GPD10", "SLP_S5#", "n/a", "n/a",
+ "GPD11", "LANPHYPC", "n/a", "n/a",
+};
+
+static const struct gpio_group sunrise_group_gpd = {
+ .display = "-------- GPIO Group GPD --------",
+ .pad_count = ARRAY_SIZE(sunrise_group_gpd_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_group_gpd_names,
+};
+
+static const struct gpio_group *const sunrise_community_gpd_groups[] = {
+ &sunrise_group_gpd,
+};
+
+static const struct gpio_community sunrise_community_gpd = {
+ .name = "------- GPIO Community 2 -------",
+ .pcr_port_id = 0xad,
+ .group_count = ARRAY_SIZE(sunrise_community_gpd_groups),
+ .groups = sunrise_community_gpd_groups,
+};
+
+static const char *const sunrise_group_i_names[] = {
+ "GPP_I0", "DDPB_HPD0", "n/a", "n/a",
+ "GPP_I1", "DDPC_HPD1", "n/a", "n/a",
+ "GPP_I2", "DDPD_HPD2", "n/a", "n/a",
+ "GPP_I3", "DDPE_HPD3", "n/a", "n/a",
+ "GPP_I4", "EDP_HPD", "n/a", "n/a",
+ "GPP_I5", "DDPB_CTRLCLK", "n/a", "n/a",
+ "GPP_I6", "DDPB_CTRLDATA", "n/a", "n/a",
+ "GPP_I7", "DDPC_CTRLCLK", "n/a", "n/a",
+ "GPP_I8", "DDPC_CTRLDATA", "n/a", "n/a",
+ "GPP_I9", "DDPD_CTRLCLK", "n/a", "n/a",
+ "GPP_I10", "DDPD_CTRLDATA", "n/a", "n/a",
+};
+
+static const struct gpio_group sunrise_group_i = {
+ .display = "------- GPIO Group GPP_I -------",
+ .pad_count = ARRAY_SIZE(sunrise_group_i_names) / 4,
+ .func_count = 4,
+ .pad_names = sunrise_group_i_names,
+};
+
+static const struct gpio_group *const sunrise_community_i_groups[] = {
+ &sunrise_group_i,
+};
+
+static const struct gpio_group *const sunrise_lp_community_fg_groups[] = {
+ &sunrise_lp_group_f, &sunrise_lp_group_g,
+};
+
+static const struct gpio_community sunrise_community_i = {
+ .name = "------- GPIO Community 3 -------",
+ .pcr_port_id = 0xac,
+ .group_count = ARRAY_SIZE(sunrise_community_i_groups),
+ .groups = sunrise_community_i_groups,
+};
+
+static const struct gpio_community sunrise_lp_community_fg = {
+ .name = "------- GPIO Community 3 -------",
+ .pcr_port_id = 0xac,
+ .group_count = ARRAY_SIZE(sunrise_lp_community_fg_groups),
+ .groups = sunrise_lp_community_fg_groups,
+};
+
+static const struct gpio_community *const sunrise_communities[] = {
+ &sunrise_community_ab, &sunrise_community_cdefgh,
+ &sunrise_community_gpd, &sunrise_community_i,
+};
+
+static const struct gpio_community *const sunrise_lp_communities[] = {
+ &sunrise_lp_community_ab, &sunrise_lp_community_cde,
+ &sunrise_community_gpd, &sunrise_lp_community_fg,
+};
--
To view, visit https://review.coreboot.org/c/coreboot/+/31504
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ic61871f5cf95ac3da93892fa2f7721e682176c8d
Gerrit-Change-Number: 31504
Gerrit-PatchSet: 1
Gerrit-Owner: Felix Singer <migy(a)darmstadt.ccc.de>
Gerrit-MessageType: newchange
1 week, 3 days
- 7
- 34
Change in ...coreboot[master]: drivers/intel/mipi_camera: add functionality
by Matt Delco (Code Review)
Matt Delco has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31163
Change subject: drivers/intel/mipi_camera: add functionality
......................................................................
drivers/intel/mipi_camera: add functionality
Some boards & variants are using raw asl files to define the ACPI devices
(and related properties) required by Linux MIPI camera drivers. These asl
files lack the SSDB property that's required by Windows MIPI camera
drivers. The mipi_camera driver can provide a SSDB property, but it's
missing some properties needed for Linux (and my scan of the source code
didn't find any current users of it).
This change updates the mipi_camera driver so it can provide a combined
superset of what's required by Linux and Windows. I've also expanded
the support so it has support for the IMGU and CIO2 devices.
BUG=none
BRANCH=none
TEST=Verified that the ACPI state generated by the driver (with
appropriate devicetree changes) is extremely comparible to what's
generated by the asl files. Verified that the camera still works in
CrOS on Atlas.
Change-Id: Ie9d84519eae1333eeb67107281a2deafc24e8a08
Signed-off-by: Matt Delco <delco(a)chromium.org>
---
M src/drivers/intel/mipi_camera/camera.c
M src/drivers/intel/mipi_camera/chip.h
M src/mainboard/google/poppy/dsdt.asl
3 files changed, 624 insertions(+), 40 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/31163/1
diff --git a/src/drivers/intel/mipi_camera/camera.c b/src/drivers/intel/mipi_camera/camera.c
index 0cea0ba..8844206 100644
--- a/src/drivers/intel/mipi_camera/camera.c
+++ b/src/drivers/intel/mipi_camera/camera.c
@@ -15,69 +15,599 @@
#include <arch/acpi.h>
#include <arch/acpi_device.h>
+#include <arch/acpi_pld.h>
#include <arch/acpigen.h>
#include <console/console.h>
#include <device/i2c_simple.h>
#include <device/device.h>
#include <device/path.h>
+#include <device/pci_def.h>
#include <string.h>
#include "chip.h"
+#define CIO2_PCI_DEV 0x14
+#define CIO2_PCI_FN 0x3
+
+/*
+ * This implementation assumes there is only 1 endpoint at each end of every
+ * data port. It also assumes there are no clock lanes. It also assumes
+ * that any VCM or NVM for a CAM is on the same I2C bus as the CAM.
+ */
+
+/*
+ * Adds settings for a CIO2 device (typically at "\_SB.PCI0.CIO2"). A _DSD is
+ * added that specifies a child table for each port (e.g., PRT0 for "port0"
+ * and PRT1 for "port1"). Each PRTx table specifies a table for each endpoint
+ * (though only 1 endpoint is supported by this implementation so the table
+ * only has an "endpoint0" that points to a EPx0 table). The EPx0 table
+ * primarily describes the # of lanes in "data-lines" and specifies the name
+ * of the other side in "remote-endpoint" (the name is usually of the form
+ * "\_SB.PCI0.I2Cx.CAM0" for the first port/cam and "\_SB.PCI0.I2Cx.CAM1"
+ * if there's a second port/cam).
+ */
+static void camera_fill_cio2(struct device *dev)
+{
+ struct drivers_intel_mipi_camera_config *config = dev->chip_info;
+ struct acpi_dp *dsd = acpi_dp_new_table("_DSD");
+ char *ep_table_name[MAX_PORT_ENTRIES] = {NULL};
+ char *port_table_name[MAX_PORT_ENTRIES] = {NULL};
+ char *port_name[MAX_PORT_ENTRIES] = {NULL};
+ uint32_t i = 0;
+ char name[BUS_PATH_MAX];
+
+ if (!dsd)
+ return;
+
+ for (i = 0; i < config->cio2_num_ports; ++i) {
+ struct acpi_dp *ep_table = NULL;
+ struct acpi_dp *port_table = NULL;
+ snprintf(name, sizeof(name), "EP%u0", i);
+ ep_table_name[i] = strdup(name);
+ if (!ep_table_name[i])
+ break;
+ ep_table = acpi_dp_new_table(ep_table_name[i]);
+ if (!ep_table)
+ break;
+ acpi_dp_add_integer(ep_table, "endpoint", 0);
+ acpi_dp_add_integer(ep_table, "clock-lanes", 0);
+ if (config->cio2_lanes_used[i] > 0) {
+ struct acpi_dp *lanes = acpi_dp_new_table("data-lanes");
+ if (lanes) {
+ uint32_t j;
+ for (j = 1; j <= config->cio2_lanes_used[i];
+ ++j) {
+ acpi_dp_add_integer(lanes, NULL, j);
+ }
+ acpi_dp_add_array(ep_table, lanes);
+ }
+ }
+ if (config->cio2_lane_endpoint[i]) {
+ struct acpi_dp *remote =
+ acpi_dp_new_table("remote-endpoint");
+ if (remote) {
+ acpi_dp_add_reference(remote, NULL,
+ config->cio2_lane_endpoint[i]);
+ acpi_dp_add_integer(remote, NULL, 0);
+ acpi_dp_add_integer(remote, NULL, 0);
+ acpi_dp_add_array(ep_table, remote);
+ }
+ }
+ snprintf(name, sizeof(name), "PRT%u", i);
+ port_table_name[i] = strdup(name);
+ if (!port_table_name[i]) {
+ // acpi_dp_free(ep_table);
+ break;
+ }
+ port_table = acpi_dp_new_table(port_table_name[i]);
+ if (!port_table) {
+ // acpi_dp_free(ep_table);
+ break;
+ }
+ acpi_dp_add_integer(port_table, "port", i);
+ acpi_dp_add_child(port_table, "endpoint0", ep_table);
+
+ snprintf(name, sizeof(name), "port%u", i);
+ port_name[i] = strdup(name);
+ if (!port_name[i]) {
+ // acpi_dp_free(port_table);
+ break;
+ }
+ acpi_dp_add_child(dsd, port_name[i], port_table);
+ }
+ acpi_dp_write(dsd);
+
+ for (i = 0; i < config->cio2_num_ports; ++i) {
+ free(ep_table_name[i]);
+ free(port_table_name[i]);
+ free(port_name[i]);
+ }
+}
+
+/*
+ * Adds settings for a camera sensor device (typically at
+ * "\_SB.PCI0.I2Cx.CAMy"). The drivers for Linux tends to expect the camera
+ * sensor device and any related nvram / vcm devices to be separate ACPI
+ * devices, while the drivers for Windows want all of these to be grouped
+ * together in the camera sensor ACPI device. This implementation tries to
+ * satisfy both, though the unfortunate tradeoff is that the same I2C address
+ * for nvram and vcm is advertised by multiple devices in ACPI (via "_CRS").
+ * The Windows driver can use the "_DSM" method to disambiguate the I2C
+ * resources in the camera sensor ACPI device. Drivers for Windows typically
+ * query "SSDB" for configuration information (represented as a binary blob
+ * dump of struct), while Linux drivers typically consult individual parameters
+ * in "_DSD".
+ *
+ * The tree of tables in "_DSD" is analogous to what's used for the "CIO2"
+ * device. The _DSD specifies a child table for the sensor's port (e.g., PRT0
+ * for "port0"--this implementation assumes a camera only has 1 port). The
+ * PRT0 table specifies a table for each endpoint (though only 1 endpoint is
+ * supported by this implementation so the table only has an "endpoint0" that
+ * points to a EP00 table). The EP00 table primarily describes the # of lanes
+ * in "data-lines", a list of frequencies in "list-frequencies", and specifies
+ * the name of the other side in "remote-endpoint" (typically "\_SB.PCI0.CIO2").
+ */
+static void camera_fill_sensor(struct device *dev)
+{
+ struct drivers_intel_mipi_camera_config *config = dev->chip_info;
+ struct acpi_dp *ep00 = NULL;
+ struct acpi_dp *prt0 = NULL;
+ struct acpi_dp *dsd = NULL;
+ uint16_t i2c_bus = dev->bus ? dev->bus->secondary : 0xFFFF;
+ uint16_t i2c_addr = dev->path.i2c.device;
+
+ if (config->use_pld && !config->disable_pld_defaults) {
+ if (!config->pld.ignore_color)
+ config->pld.ignore_color = 1;
+ if (!config->pld.visible)
+ config->pld.visible = 1;
+ if (!config->pld.vertical_offset)
+ config->pld.vertical_offset = 0xffff;
+ if (!config->pld.horizontal_offset)
+ config->pld.horizontal_offset = 0xffff;
+ /*
+ * PLD_PANEL_TOP has a value of zero, so the following
+ * will change any instance of PLD_PANEL_TOP to
+ * PLD_PANEL_FRONT unless disable_pld_defaults is set.
+ */
+ if (!config->pld.panel)
+ config->pld.panel = PLD_PANEL_FRONT;
+ /*
+ * PLD_HORIZONTAL_POSITION_LEFT has a value of zero, so
+ * the following will change any instance of that value
+ * to PLD_HORIZONTAL_POSITION_CENTER unless
+ * disable_pld_defaults is set.
+ */
+ if (!config->pld.horizontal_position) {
+ config->pld.horizontal_position =
+ PLD_HORIZONTAL_POSITION_CENTER;
+ }
+ /*
+ * The desired default for |vertical_position| is
+ * PLD_VERTICAL_POSITION_UPPER, which has a value of
+ * zero so no work is needed to set a default. The
+ * same applies for setting |shape| to PLD_SHAPE_ROUND.
+ */
+ }
+ if (config->use_pld)
+ acpigen_write_pld(&config->pld);
+
+ if (!config->disable_ssdb_defaults) {
+ if (!config->ssdb.bdf_value) {
+ config->ssdb.bdf_value = (CIO2_PCI_DEV << 3) |
+ CIO2_PCI_FN;
+ }
+ if (!config->ssdb.platform)
+ config->ssdb.platform = 9;
+ if (!config->ssdb.flash_support)
+ config->ssdb.flash_support = 2;
+ if (!config->ssdb.privacy_led)
+ config->ssdb.privacy_led = 1;
+ if (!config->ssdb.mipi_define)
+ config->ssdb.mipi_define = 1;
+ if (!config->ssdb.mclk_speed)
+ config->ssdb.mclk_speed = 19200000;
+ if (!config->ssdb.lanes_used) {
+ struct device *cio2 = pcidev_on_root(CIO2_PCI_DEV,
+ CIO2_PCI_FN);
+ struct drivers_intel_mipi_camera_config *cio2_config;
+ cio2_config = cio2 ? cio2->chip_info : NULL;
+ if (!cio2_config) {
+ printk(BIOS_ERR, "Failed to get CIO2 config\n");
+ } else if (cio2_config->device_type !=
+ INTEL_ACPI_CAMERA_CIO2) {
+ printk(BIOS_ERR, "Device type isn't CIO2: %u\n",
+ (u32)cio2_config->device_type);
+ } else if (config->ssdb.link_used >=
+ cio2_config->cio2_num_ports) {
+ printk(BIOS_ERR, "%u exceeds CIO2's %u links\n",
+ (u32)config->ssdb.link_used,
+ (u32)cio2_config->cio2_num_ports);
+ } else {
+ config->ssdb.lanes_used =
+ cio2_config->cio2_lanes_used[
+ config->ssdb.link_used];
+ }
+ }
+ }
+
+ /* Method (_DSM, 4, NotSerialized) */
+ acpigen_write_method("_DSM", 0x4);
+
+ /* ToBuffer (Arg0, Local0) */
+ acpigen_write_to_buffer(ARG0_OP, LOCAL0_OP);
+
+ /* If (LEqual (Local0, ToUUID(uuid))) */
+ acpigen_write_if();
+ acpigen_emit_byte(LEQUAL_OP);
+ acpigen_emit_byte(LOCAL0_OP);
+ acpigen_write_uuid("822ace8f-2814-4174-a56b-5f029fe079ee");
+ acpigen_write_return_string(config->sensor_name ?
+ config->sensor_name : "UNKNOWN");
+ acpigen_pop_len(); /* If */
+
+ /* If (LEqual (Local0, ToUUID(uuid))) */
+ acpigen_write_if();
+ acpigen_emit_byte(LEQUAL_OP);
+ acpigen_emit_byte(LOCAL0_OP);
+ acpigen_write_uuid("26257549-9271-4ca4-bb43-c4899d5a4881");
+ /* ToInteger (Arg2, Local1) */
+ acpigen_write_to_integer(ARG2_OP, LOCAL1_OP);
+
+ /* If (LEqual (Local1, 1)) */
+ acpigen_write_if_lequal_op_int(LOCAL1_OP, 1);
+ acpigen_write_return_integer((config->ssdb.vcm_type ? 1 : 0) +
+ (config->ssdb.rom_type ? 1 : 0) + 1);
+ acpigen_pop_len(); /* If Arg2=1 */
+
+ /* If (LEqual (Local1, 2)) */
+ acpigen_write_if_lequal_op_int(LOCAL1_OP, 2);
+ acpigen_write_return_integer(((uint32_t)i2c_bus) << 24 |
+ ((uint32_t)i2c_addr) << 8 |
+ 0x0); /* type 0 for sensor */
+ acpigen_pop_len(); /* If Arg2=2 */
+
+ if (config->ssdb.vcm_type) {
+ /* If (LEqual (Local1, 3)) */
+ acpigen_write_if_lequal_op_int(LOCAL1_OP, 3);
+ acpigen_write_return_integer(((uint32_t)i2c_bus) << 24 |
+ ((uint32_t)config->vcm_address)
+ << 8 |
+ 0x01); /* type 1 for vcm */
+ acpigen_pop_len(); /* If Arg2=3 */
+ }
+ if (config->ssdb.rom_type) {
+ /* If (LEqual (Local1, 3 or 4)) */
+ acpigen_write_if_lequal_op_int(LOCAL1_OP, 3 +
+ (config->ssdb.vcm_type ? 1 : 0));
+ acpigen_write_return_integer(((uint32_t)i2c_bus) << 24 |
+ ((uint32_t)config->rom_address)
+ << 8 |
+ 0x02); /* type 2 for rom */
+ acpigen_pop_len(); /* If Arg2=3 or 4 */
+ }
+
+ acpigen_pop_len(); /* If uuid */
+
+ /* Return (Buffer (One) { 0x0 }) */
+ acpigen_write_return_singleton_buffer(0x0);
+
+ acpigen_pop_len(); /* Method _DSM */
+
+ /* end of _dsm */
+
+ ep00 = acpi_dp_new_table("EP00");
+ if (ep00) {
+ struct acpi_dp *remote = NULL;
+ acpi_dp_add_integer(ep00, "endpoint", 0);
+ acpi_dp_add_integer(ep00, "clock-lanes", 0);
+ if (config->ssdb.lanes_used > 0) {
+ struct acpi_dp *lanes = acpi_dp_new_table("data-lanes");
+ if (lanes) {
+ uint32_t i;
+ for (i = 1; i <= config->ssdb.lanes_used; ++i)
+ acpi_dp_add_integer(lanes, NULL, i);
+ acpi_dp_add_array(ep00, lanes);
+ }
+ }
+ if (config->num_freq_entries > 0) {
+ struct acpi_dp *freq =
+ acpi_dp_new_table("link-frequencies");
+ if (freq) {
+ uint32_t i;
+ for (i = 0; i < config->num_freq_entries &&
+ i < MAX_LINK_FREQ_ENTRIES; ++i) {
+ acpi_dp_add_integer(freq, NULL,
+ config->link_freq[i]);
+ }
+ acpi_dp_add_array(ep00, freq);
+ }
+ }
+ remote = acpi_dp_new_table("remote-endpoint");
+ if (remote) {
+ const char *remote_name = NULL;
+ struct device *cio2 = NULL;
+ if (config->remote_name) {
+ remote_name = config->remote_name;
+ } else {
+ cio2 = pcidev_on_root(CIO2_PCI_DEV,
+ CIO2_PCI_FN);
+ if (cio2)
+ remote_name = acpi_device_path(cio2);
+ else
+ remote_name = "\\_SB.PCI0.CIO2";
+ }
+ acpi_dp_add_reference(remote, NULL, remote_name);
+ acpi_dp_add_integer(remote, NULL,
+ config->ssdb.link_used);
+ acpi_dp_add_integer(remote, NULL, 0); /* endpoint? */
+ acpi_dp_add_array(ep00, remote);
+ }
+ prt0 = acpi_dp_new_table("PRT0");
+ }
+ if (!prt0) {
+ // acpi_dp_free(ep00);
+ } else {
+ acpi_dp_add_integer(prt0, "port", 0);
+ acpi_dp_add_child(prt0, "endpoint0", ep00);
+ dsd = acpi_dp_new_table("_DSD");
+ }
+ if (!dsd) {
+ // acpi_dp_free(prt0);
+ } else {
+ const char *vcm_name = NULL;
+ acpi_dp_add_integer(dsd, "clock-frequency",
+ config->ssdb.mclk_speed);
+ if (config->ssdb.degree)
+ acpi_dp_add_integer(dsd, "rotation", 180);
+ if (config->ssdb.vcm_type) {
+ if (config->vcm_name) {
+ vcm_name = config->vcm_name;
+ } else {
+ const struct device_path path = {
+ .type = DEVICE_PATH_I2C,
+ .i2c.device = config->vcm_address,
+ };
+ struct device *vcm_dev = find_dev_path(dev->bus,
+ &path);
+ struct drivers_intel_mipi_camera_config *
+ vcm_config;
+ vcm_config = vcm_dev ? vcm_dev->chip_info :
+ NULL;
+ if (!vcm_config) {
+ printk(BIOS_ERR, "Failed to get VCM\n");
+ } else if (vcm_config->device_type !=
+ INTEL_ACPI_CAMERA_VCM) {
+ printk(BIOS_ERR, "Device isn't VCM\n");
+ } else {
+ vcm_name = acpi_device_path(vcm_dev);
+ }
+ }
+ }
+ if (vcm_name)
+ acpi_dp_add_reference(dsd, "lens-focus", vcm_name);
+ acpi_dp_add_child(dsd, "port0", prt0);
+ acpi_dp_write(dsd);
+ }
+
+ acpigen_write_method_serialized("SSDB", 0);
+ acpigen_write_return_byte_buffer((uint8_t *)&config->ssdb,
+ sizeof(config->ssdb));
+ acpigen_pop_len(); /* Method */
+
+ /* Fill Power Sequencing Data */
+ if (config->num_pwdb_entries > 0) {
+ acpigen_write_method_serialized("PWDB", 0);
+ acpigen_write_return_byte_buffer((uint8_t *)&config->pwdb,
+ sizeof(struct intel_pwdb) *
+ config->num_pwdb_entries);
+ acpigen_pop_len(); /* Method */
+ }
+}
+
+static void camera_fill_nvm(struct device *dev)
+{
+ struct drivers_intel_mipi_camera_config *config = dev->chip_info;
+ struct acpi_dp *dsd = acpi_dp_new_table("_DSD");
+ if (!dsd)
+ return;
+
+ /* It might be possible to default size or width based on type. */
+ if (!config->disable_nvm_defaults && !config->nvm_pagesize)
+ config->nvm_pagesize = 1;
+ if (!config->disable_nvm_defaults && !config->nvm_readonly)
+ config->nvm_readonly = 1;
+
+ if (config->nvm_size)
+ acpi_dp_add_integer(dsd, "size", config->nvm_size);
+ if (config->nvm_pagesize)
+ acpi_dp_add_integer(dsd, "pagesize", config->nvm_pagesize);
+ if (config->nvm_readonly)
+ acpi_dp_add_integer(dsd, "read-only", config->nvm_readonly);
+ if (config->nvm_width)
+ acpi_dp_add_integer(dsd, "address-width", config->nvm_width);
+ acpi_dp_write(dsd);
+}
+
+static void camera_fill_vcm(struct device *dev)
+{
+ struct drivers_intel_mipi_camera_config *config = dev->chip_info;
+ struct acpi_dp *dsd;
+
+ if (!config->vcm_compat)
+ return;
+
+ dsd = acpi_dp_new_table("_DSD");
+ if (!dsd)
+ return;
+ acpi_dp_add_string(dsd, "compatible", config->vcm_compat);
+ acpi_dp_write(dsd);
+}
+
static void camera_fill_ssdt(struct device *dev)
{
struct drivers_intel_mipi_camera_config *config = dev->chip_info;
const char *scope = acpi_device_scope(dev);
- struct acpi_i2c i2c = {
- .address = dev->path.i2c.device,
- .mode_10bit = dev->path.i2c.mode_10bit,
- .speed = I2C_SPEED_FAST,
- .resource = scope,
- };
if (!dev->enabled || !scope)
return;
/* Device */
- acpigen_write_scope(scope);
- acpigen_write_device(acpi_device_name(dev));
- acpigen_write_name_string("_HID", config->acpi_hid);
- acpigen_write_name_integer("_UID", config->acpi_uid);
- acpigen_write_name_string("_DDN", config->chip_name);
- acpigen_write_STA(acpi_device_status(dev));
+ if (config->device_type == INTEL_ACPI_CAMERA_CIO2 ||
+ config->device_type == INTEL_ACPI_CAMERA_IMGU) {
+ u32 address;
- /* Resources */
- acpigen_write_name("_CRS");
- acpigen_write_resourcetemplate_header();
- acpi_device_write_i2c(&i2c);
- acpigen_write_resourcetemplate_footer();
+ if (dev->path.type != DEVICE_PATH_PCI) {
+ printk(BIOS_ERR, "CIO2/IMGU devices require PCI\n");
+ return;
+ }
+ acpigen_write_scope(scope);
+ acpigen_write_device(acpi_device_name(dev));
+ address = PCI_SLOT(dev->path.pci.devfn) & 0xffff;
+ address <<= 16;
+ address |= PCI_FUNC(dev->path.pci.devfn) & 0xffff;
+ acpigen_write_name_dword("_ADR", address);
+ acpigen_write_name_string("_DDN",
+ config->device_type == INTEL_ACPI_CAMERA_CIO2 ?
+ "Camera and Imaging Subsystem" : "Imaging Unit");
+ } else {
+ struct acpi_i2c i2c = {
+ .address = dev->path.i2c.device,
+ .mode_10bit = dev->path.i2c.mode_10bit,
+ .speed = I2C_SPEED_FAST,
+ .resource = scope,
+ };
- /* Mark it as Camera related device */
- acpigen_write_name_integer("CAMD", config->device_type);
+ if (dev->path.type != DEVICE_PATH_I2C) {
+ printk(BIOS_ERR, "Non-CIO2/IMGU devices require I2C\n");
+ return;
+ }
- /* Create Device specific data */
- if (config->device_type == INTEL_ACPI_CAMERA_SENSOR) {
- acpigen_write_method_serialized("SSDB", 0);
- acpigen_write_return_byte_buffer((uint8_t *)&config->ssdb,
- sizeof(config->ssdb));
- acpigen_pop_len(); /* Method */
+ acpigen_write_scope(scope);
+ acpigen_write_device(acpi_device_name(dev));
+ if (config->device_type == INTEL_ACPI_CAMERA_SENSOR)
+ acpigen_write_name_integer("_ADR", 0);
+ if (config->acpi_hid)
+ acpigen_write_name_string("_HID", config->acpi_hid);
+ else if (config->device_type == INTEL_ACPI_CAMERA_VCM)
+ acpigen_write_name_string("_HID",
+ ACPI_DT_NAMESPACE_HID);
+ else if (config->device_type == INTEL_ACPI_CAMERA_NVM)
+ acpigen_write_name_string("_HID", "INT3499");
+ acpigen_write_name_integer("_UID", config->acpi_uid);
+ acpigen_write_name_string("_DDN", config->chip_name);
+ acpigen_write_STA(acpi_device_status(dev));
+
+ /* Resources */
+ acpigen_write_name("_CRS");
+ acpigen_write_resourcetemplate_header();
+ acpi_device_write_i2c(&i2c);
+ /*
+ * The optional vcm/nvram devices are presumed to be on the
+ * same I2C bus as the camera sensor.
+ */
+ if (config->device_type == INTEL_ACPI_CAMERA_SENSOR &&
+ config->ssdb.vcm_type) {
+ struct acpi_i2c i2c_vcm = i2c;
+ i2c_vcm.address = config->vcm_address;
+ acpi_device_write_i2c(&i2c_vcm);
+ }
+ if (config->device_type == INTEL_ACPI_CAMERA_SENSOR &&
+ config->ssdb.rom_type) {
+ struct acpi_i2c i2c_rom = i2c;
+ i2c_rom.address = config->rom_address;
+ acpi_device_write_i2c(&i2c_rom);
+ }
+ acpigen_write_resourcetemplate_footer();
}
- /* Fill Power Sequencing Data */
- acpigen_write_method_serialized("PWDB", 0);
- acpigen_write_return_byte_buffer((uint8_t *)&config->pwdb,
- (sizeof(struct intel_pwdb) * config->num_pwdb_entries));
- acpigen_pop_len(); /* Method */
+ /* Mark it as Camera related device */
+ if (config->device_type == INTEL_ACPI_CAMERA_CIO2 ||
+ config->device_type == INTEL_ACPI_CAMERA_IMGU ||
+ config->device_type == INTEL_ACPI_CAMERA_SENSOR ||
+ config->device_type == INTEL_ACPI_CAMERA_VCM) {
+ acpigen_write_name_integer("CAMD", config->device_type);
+ }
+
+ if (config->dep) {
+ acpigen_write_name("_DEP");
+ acpigen_write_package(1);
+ acpigen_emit_namestring(config->dep);
+ acpigen_pop_len();
+ }
+ if (config->pr0) {
+ acpigen_write_name("_PR0");
+ acpigen_write_package(1);
+ acpigen_emit_namestring(config->pr0);
+ acpigen_pop_len();
+ }
+ /* It's very unlikely you need _PR3 for any camera device */
+ if (config->pr3) {
+ acpigen_write_name("_PR3");
+ acpigen_write_package(1);
+ acpigen_emit_namestring(config->pr3);
+ acpigen_pop_len();
+ }
+
+ if (config->device_type == INTEL_ACPI_CAMERA_CIO2)
+ camera_fill_cio2(dev);
+ else if (config->device_type == INTEL_ACPI_CAMERA_SENSOR)
+ camera_fill_sensor(dev);
+ else if (config->device_type == INTEL_ACPI_CAMERA_NVM)
+ camera_fill_nvm(dev);
+ else if (config->device_type == INTEL_ACPI_CAMERA_VCM)
+ camera_fill_vcm(dev);
acpigen_pop_len(); /* Device */
acpigen_pop_len(); /* Scope */
- printk(BIOS_INFO, "%s: %s address 0%xh\n", acpi_device_path(dev),
- dev->chip_ops->name, dev->path.i2c.device);
+ if (dev->path.type == DEVICE_PATH_PCI) {
+ printk(BIOS_INFO, "%s: %s PCI address 0%x\n",
+ acpi_device_path(dev),
+ dev->chip_ops->name, dev->path.pci.devfn);
+ } else {
+ printk(BIOS_INFO, "%s: %s I2C address 0%xh\n",
+ acpi_device_path(dev),
+ dev->chip_ops->name, dev->path.i2c.device);
+ }
}
static const char *camera_acpi_name(const struct device *dev)
{
+ const char *prefix = NULL;
+ static char name[BUS_PATH_MAX];
struct drivers_intel_mipi_camera_config *config = dev->chip_info;
- return config->acpi_name;
+ if (config->acpi_name)
+ return config->acpi_name;
+ if (config->device_type == INTEL_ACPI_CAMERA_CIO2)
+ return "CIO2";
+ else if (config->device_type == INTEL_ACPI_CAMERA_IMGU)
+ return "IMGU";
+ else if (config->device_type == INTEL_ACPI_CAMERA_PMIC)
+ return "PMIC";
+
+ switch (config->device_type) {
+ case INTEL_ACPI_CAMERA_SENSOR:
+ prefix = "CAM";
+ break;
+ case INTEL_ACPI_CAMERA_VCM:
+ prefix = "VCM";
+ break;
+ case INTEL_ACPI_CAMERA_NVM:
+ prefix = "NVM";
+ break;
+ default:
+ prefix = "ERR"; /* Error */
+ break;
+ }
+ /*
+ * The cameras know which link # they use, so that's used
+ * as the basis for the instance #. The VCM and NVM don't
+ * have this information, so the best we can go on is the
+ * _UID.
+ */
+ snprintf(name, sizeof(name), "%s%u", prefix,
+ config->device_type == INTEL_ACPI_CAMERA_SENSOR ?
+ config->ssdb.link_used : config->acpi_uid);
+ return name;
}
static struct device_operations camera_ops = {
diff --git a/src/drivers/intel/mipi_camera/chip.h b/src/drivers/intel/mipi_camera/chip.h
index 741ae8e..50b757c 100644
--- a/src/drivers/intel/mipi_camera/chip.h
+++ b/src/drivers/intel/mipi_camera/chip.h
@@ -17,14 +17,19 @@
#define __INTEL_MIPI_CAMERA_CHIP_H__
#include <stdint.h>
+#include <arch/acpi_pld.h>
#define MAX_PWDB_ENTRIES 12
+#define MAX_PORT_ENTRIES 4
+#define MAX_LINK_FREQ_ENTRIES 4
enum intel_camera_device_type {
INTEL_ACPI_CAMERA_CIO2,
INTEL_ACPI_CAMERA_IMGU,
INTEL_ACPI_CAMERA_SENSOR,
INTEL_ACPI_CAMERA_VCM,
+ /* Value for NVM might might not be appropriate for CAMD */
+ INTEL_ACPI_CAMERA_NVM,
INTEL_ACPI_CAMERA_PMIC = 100,
};
@@ -77,12 +82,14 @@
uint8_t degree; /* Camera Orientation */
uint8_t mipi_define; /* MIPI info defined in ACPI or
sensor driver */
- uint32_t mclk; /* Clock info for sensor */
+ uint32_t mclk_speed; /* Clock info for sensor */
uint8_t control_logic_id; /* PMIC device node used for
the camera sensor */
uint8_t mipi_data_format; /* MIPI data format */
uint8_t silicon_version; /* Silicon version */
uint8_t customer_id; /* Customer ID */
+ uint8_t mclk_port;
+ uint8_t reserved[13];
} __packed;
struct intel_pwdb {
@@ -95,14 +102,59 @@
} __packed;
struct drivers_intel_mipi_camera_config {
+ /* Generic settings */
+ enum intel_camera_device_type device_type;
+
+ /* Settings that should not need to be set since defaults sane. */
+ const char *acpi_name; /* defaults: CIO2,IMGU,PMIC,CAMx,VCMx,NVMx */
+
+ /*
+ * General settings that can be used for any type (but doesn't
+ * necessarily need to be used/specified for each device.
+ */
+ const char *chip_name;
+ const char *acpi_hid; /* vcm and nvm have defaults */
+ unsigned int acpi_uid;
+ const char *dep;
+ const char *pr0;
+ const char *pr3; /* _PR3 shouldn't be needed */
+
+ /* Settings specific to CIO2 device */
+ uint32_t cio2_num_ports;
+ uint32_t cio2_lanes_used[MAX_PORT_ENTRIES];
+ const char *cio2_lane_endpoint[MAX_PORT_ENTRIES];
+
+ /* Settings specific to camera sensor */
+ bool disable_ssdb_defaults;
struct intel_ssdb ssdb;
struct intel_pwdb pwdb[MAX_PWDB_ENTRIES];
- enum intel_camera_device_type device_type;
uint8_t num_pwdb_entries;
- const char *acpi_hid;
- const char *acpi_name;
- const char *chip_name;
- unsigned int acpi_uid;
+ uint8_t num_freq_entries; /* # of elements in link_freq */
+ uint32_t link_freq[MAX_LINK_FREQ_ENTRIES];
+ const char *sensor_name; /* default "UNKNOWN" */
+ const char *remote_name; /* default "\_SB.PCI0.CIO2" */
+ const char *vcm_name; /* defaults to |vcm_address| device */
+ bool use_pld;
+ bool disable_pld_defaults;
+ struct acpi_pld pld;
+ uint16_t rom_address; /* I2C to use if ssdb.rom_type != 0 */
+ uint16_t vcm_address; /* I2C to use if ssdb.vcm_type != 0 */
+
+ /*
+ * Settings specific to nvram. Many values, if left as zero,
+ * will be assigned a default. Set disable_nvm_defaults to
+ * non-zero if you want to disable the defaulting behavior so
+ * you can use zero for a value.
+ */
+
+ bool disable_nvm_defaults;
+ uint32_t nvm_size;
+ uint32_t nvm_pagesize;
+ uint32_t nvm_readonly;
+ uint32_t nvm_width;
+
+ /* Settings specific to vcm */
+ const char *vcm_compat;
};
#endif
diff --git a/src/mainboard/google/poppy/dsdt.asl b/src/mainboard/google/poppy/dsdt.asl
index 0001867..d923ba5 100644
--- a/src/mainboard/google/poppy/dsdt.asl
+++ b/src/mainboard/google/poppy/dsdt.asl
@@ -39,8 +39,10 @@
{
Device (PCI0)
{
- /* Image processing unit */
+#if !IS_ENABLED(CONFIG_DRIVERS_INTEL_MIPI_CAMERA)
+ /* Image processing unit, if not using MIPI driver */
#include <soc/intel/skylake/acpi/ipu.asl>
+#endif
#include <soc/intel/skylake/acpi/systemagent.asl>
#include <soc/intel/skylake/acpi/pch.asl>
}
--
To view, visit https://review.coreboot.org/c/coreboot/+/31163
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ie9d84519eae1333eeb67107281a2deafc24e8a08
Gerrit-Change-Number: 31163
Gerrit-PatchSet: 1
Gerrit-Owner: Matt Delco <delco(a)chromium.org>
Gerrit-Reviewer: Matt Delco <delco(a)chromium.org>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-MessageType: newchange
2 weeks, 4 days
- 3
- 4
Change in ...coreboot[master]: soc/intel/denverton_ns: Rewrite pmutil using pmclib
by Patrick Georgi (Code Review)
Hello Julien Viard de Galbert,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/31072
to review the following change.
Change subject: soc/intel/denverton_ns: Rewrite pmutil using pmclib
......................................................................
soc/intel/denverton_ns: Rewrite pmutil using pmclib
Change-Id: I13ab94e7440886f77e3091b16e50e48b17151751
Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net>
---
M src/soc/intel/denverton_ns/include/soc/pm.h
M src/soc/intel/denverton_ns/pmutil.c
M src/soc/intel/denverton_ns/smihandler.c
M src/soc/intel/denverton_ns/smm.c
4 files changed, 33 insertions(+), 184 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/31072/1
diff --git a/src/soc/intel/denverton_ns/include/soc/pm.h b/src/soc/intel/denverton_ns/include/soc/pm.h
index 09ce158..0aab0e2 100644
--- a/src/soc/intel/denverton_ns/include/soc/pm.h
+++ b/src/soc/intel/denverton_ns/include/soc/pm.h
@@ -47,18 +47,6 @@
struct chipset_power_state *fill_power_state(void);
/* Power Management Utility Functions. */
-uint32_t clear_smi_status(void);
-uint16_t clear_pm1_status(void);
-uint32_t clear_tco_status(void);
-uint32_t clear_gpe_status(void);
void clear_pmc_status(void);
-void enable_smi(uint32_t mask);
-void disable_smi(uint32_t mask);
-void enable_pm1(uint16_t events);
-void enable_pm1_control(uint32_t mask);
-void disable_pm1_control(uint32_t mask);
-void enable_gpe(uint32_t mask);
-void disable_gpe(uint32_t mask);
-void disable_all_gpe(void);
#endif /* _DENVERTON_NS_PM_H_ */
diff --git a/src/soc/intel/denverton_ns/pmutil.c b/src/soc/intel/denverton_ns/pmutil.c
index ccf0d95..344f8b9 100644
--- a/src/soc/intel/denverton_ns/pmutil.c
+++ b/src/soc/intel/denverton_ns/pmutil.c
@@ -19,29 +19,12 @@
#include <arch/io.h>
#include <console/console.h>
+#include <intelblocks/pmclib.h>
#include <soc/iomap.h>
#include <soc/soc_util.h>
#include <soc/pm.h>
-static void print_num_status_bits(int num_bits, uint32_t status,
- const char *const bit_names[])
-{
- int i;
-
- if (!status)
- return;
-
- for (i = num_bits - 1; i >= 0; i--) {
- if (status & (1 << i)) {
- if (bit_names[i])
- printk(BIOS_DEBUG, "%s ", bit_names[i]);
- else
- printk(BIOS_DEBUG, "BIT%d ", i);
- }
- }
-}
-
-static uint32_t print_smi_status(uint32_t smi_sts)
+const char *const *soc_smi_sts_array(size_t *a)
{
static const char *const smi_sts_bits[] = {
[2] = "BIOS",
@@ -67,93 +50,11 @@
[31] = "LEGACY_USB3",
};
- if (!smi_sts)
- return 0;
-
- printk(BIOS_DEBUG, "SMI_STS: ");
- print_num_status_bits(ARRAY_SIZE(smi_sts_bits), smi_sts, smi_sts_bits);
- printk(BIOS_DEBUG, "\n");
-
- return smi_sts;
+ *a = ARRAY_SIZE(smi_sts_bits);
+ return smi_sts_bits;
}
-static uint32_t reset_smi_status(void)
-{
- uint16_t pmbase = get_pmbase();
- uint32_t smi_sts = inl((uint16_t)(pmbase + SMI_STS));
- outl(smi_sts, (uint16_t)(pmbase + SMI_STS));
- return smi_sts;
-}
-
-uint32_t clear_smi_status(void) { return print_smi_status(reset_smi_status()); }
-
-void enable_smi(uint32_t mask)
-{
- uint16_t pmbase = get_pmbase();
- uint32_t smi_en = inl((uint16_t)(pmbase + SMI_EN));
- smi_en |= mask;
- outl(smi_en, (uint16_t)(pmbase + SMI_EN));
-}
-
-void disable_smi(uint32_t mask)
-{
- uint16_t pmbase = get_pmbase();
- uint32_t smi_en = inl((uint16_t)(pmbase + SMI_EN));
- smi_en &= ~mask;
- outl(smi_en, (uint16_t)(pmbase + SMI_EN));
-}
-
-void enable_pm1_control(uint32_t mask)
-{
- uint16_t pmbase = get_pmbase();
- uint32_t pm1_cnt = inl((uint16_t)(pmbase + PM1_CNT));
- pm1_cnt |= mask;
- outl(pm1_cnt, (uint16_t)(pmbase + PM1_CNT));
-}
-
-void disable_pm1_control(uint32_t mask)
-{
- uint16_t pmbase = get_pmbase();
- uint32_t pm1_cnt = inl((uint16_t)(pmbase + PM1_CNT));
- pm1_cnt &= ~mask;
- outl(pm1_cnt, (uint16_t)(pmbase + PM1_CNT));
-}
-
-static uint16_t reset_pm1_status(void)
-{
- uint16_t pmbase = get_pmbase();
- uint16_t pm1_sts = inw((uint16_t)(pmbase + PM1_STS));
- outw(pm1_sts, (uint16_t)(pmbase + PM1_STS));
- return pm1_sts;
-}
-
-static uint16_t print_pm1_status(uint16_t pm1_sts)
-{
- static const char *const pm1_sts_bits[] = {
- [0] = "TMROF", [4] = "BM", [5] = "GBL",
- [8] = "PWRBTN", [10] = "RTC", [11] = "PRBTNOR",
- [15] = "WAK",
- };
-
- if (!pm1_sts)
- return 0;
-
- printk(BIOS_SPEW, "PM1_STS: ");
- print_num_status_bits(ARRAY_SIZE(pm1_sts_bits), pm1_sts, pm1_sts_bits);
- printk(BIOS_SPEW, "\n");
-
- return pm1_sts;
-}
-
-uint16_t clear_pm1_status(void) { return print_pm1_status(reset_pm1_status()); }
-
-void enable_pm1(uint16_t events)
-{
- uint16_t pmbase = get_pmbase();
- outw(events, (uint16_t)(pmbase + PM1_EN));
-}
-
-static uint32_t print_tco_status(uint32_t tco_sts)
+const char *const *soc_tco_sts_array(size_t *a)
{
static const char *const tco_sts_bits[] = {
[0] = "NMI2SMI", [1] = "OS_TCO_SMI",
@@ -164,17 +65,11 @@
[17] = "SECOND_TO", [20] = "SMLINK_SLV_SMI",
};
- if (!tco_sts)
- return 0;
-
- printk(BIOS_DEBUG, "TCO_STS: ");
- print_num_status_bits(ARRAY_SIZE(tco_sts_bits), tco_sts, tco_sts_bits);
- printk(BIOS_DEBUG, "\n");
-
- return tco_sts;
+ *a = ARRAY_SIZE(tco_sts_bits);
+ return tco_sts_bits;
}
-static uint32_t reset_tco_status(void)
+uint32_t soc_reset_tco_status(void)
{
uint16_t tcobase = get_tcobase();
uint32_t tco_sts = inl((uint16_t)(tcobase + TCO1_STS));
@@ -184,35 +79,7 @@
return tco_sts & tco_en;
}
-uint32_t clear_tco_status(void) { return print_tco_status(reset_tco_status()); }
-
-void enable_gpe(uint32_t mask)
-{
- uint16_t pmbase = get_pmbase();
- uint32_t gpe0_en = inl((uint16_t)(pmbase + GPE0_EN(GPE_STD)));
- gpe0_en |= mask;
- outl(gpe0_en, (uint16_t)(pmbase + GPE0_EN(GPE_STD)));
-}
-
-void disable_gpe(uint32_t mask)
-{
- uint16_t pmbase = get_pmbase();
- uint32_t gpe0_en = inl((uint16_t)(pmbase + GPE0_EN(GPE_STD)));
- gpe0_en &= ~mask;
- outl(gpe0_en, (uint16_t)(pmbase + GPE0_EN(GPE_STD)));
-}
-
-void disable_all_gpe(void) { disable_gpe(~0); }
-
-static uint32_t reset_gpe_status(void)
-{
- uint16_t pmbase = get_pmbase();
- uint32_t gpe_sts = inl((uint16_t)(pmbase + GPE0_STS(GPE_STD)));
- outl(gpe_sts, (uint16_t)(pmbase + GPE0_STS(GPE_STD)));
- return gpe_sts;
-}
-
-static uint32_t print_gpe_sts(uint32_t gpe_sts)
+const char *const *soc_std_gpe_sts_array(size_t *a)
{
static const char *const gpe_sts_bits[] = {
[0] = "GPIO_0", [1] = "GPIO_1",
@@ -233,16 +100,8 @@
[30] = "GPIO_30", [31] = "GPIO_31",
};
- if (!gpe_sts)
- return gpe_sts;
-
- printk(BIOS_DEBUG, "GPE0a_STS: ");
- print_num_status_bits(ARRAY_SIZE(gpe_sts_bits), gpe_sts, gpe_sts_bits);
- printk(BIOS_DEBUG, "\n");
-
- return gpe_sts;
+ *a = ARRAY_SIZE(gpe_sts_bits);
+ return gpe_sts_bits;
}
-uint32_t clear_gpe_status(void) { return print_gpe_sts(reset_gpe_status()); }
-
void clear_pmc_status(void) { /* TODO */ }
diff --git a/src/soc/intel/denverton_ns/smihandler.c b/src/soc/intel/denverton_ns/smihandler.c
index 85f99d7..e1e7bc4 100644
--- a/src/soc/intel/denverton_ns/smihandler.c
+++ b/src/soc/intel/denverton_ns/smihandler.c
@@ -25,6 +25,7 @@
#include <device/pci_def.h>
#include <elog.h>
#include <intelblocks/fast_spi.h>
+#include <intelblocks/pmclib.h>
#include <spi-generic.h>
#include <soc/iomap.h>
#include <soc/soc_util.h>
@@ -52,7 +53,7 @@
return 0;
}
-void southbridge_smi_set_eos(void) { enable_smi(EOS); }
+void southbridge_smi_set_eos(void) { pmc_enable_smi(EOS); }
global_nvs_t *smm_get_gnvs(void) { return gnvs; }
@@ -98,7 +99,7 @@
uint16_t pmbase = get_pmbase();
/* First, disable further SMIs */
- disable_smi(SLP_SMI_EN);
+ pmc_disable_smi(SLP_SMI_EN);
/* Figure out SLP_TYP */
reg32 = inl((uint16_t)(pmbase + PM1_CNT));
@@ -131,7 +132,7 @@
printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n");
/* Disable all GPE */
- disable_all_gpe();
+ pmc_disable_all_gpe();
/* also iterates over all bridges on bus 0 */
busmaster_disable_on_bus(0);
@@ -145,7 +146,7 @@
* event again. We need to set BIT13 (SLP_EN) though to make the
* sleep happen.
*/
- enable_pm1_control(SLP_EN);
+ pmc_enable_pm1_control(SLP_EN);
/* Make sure to stop executing code here for S3/S4/S5 */
if (slp_typ > 1)
@@ -158,7 +159,7 @@
reg32 = inl((uint16_t)(pmbase + PM1_CNT));
if (reg32 & SCI_EN) {
/* The OS is not an ACPI OS, so we set the state to S0 */
- disable_pm1_control(SLP_EN | SLP_TYP);
+ pmc_disable_pm1_control(SLP_EN | SLP_TYP);
}
}
@@ -237,11 +238,11 @@
printk(BIOS_DEBUG, "P-state control\n");
break;
case APM_CNT_ACPI_DISABLE:
- disable_pm1_control(SCI_EN);
+ pmc_disable_pm1_control(SCI_EN);
printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n");
break;
case APM_CNT_ACPI_ENABLE:
- enable_pm1_control(SCI_EN);
+ pmc_enable_pm1_control(SCI_EN);
printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n");
break;
case APM_CNT_FINALIZE:
@@ -268,23 +269,23 @@
static void southbridge_smi_pm1(void)
{
- uint16_t pm1_sts = clear_pm1_status();
+ uint16_t pm1_sts = pmc_clear_pm1_status();
/* While OSPM is not active, poweroff immediately
* on a power button event.
*/
if (pm1_sts & PWRBTN_STS) {
// power button pressed
- disable_pm1_control(-1UL);
- enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT));
+ pmc_disable_pm1_control(-1UL);
+ pmc_enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT));
}
}
-static void southbridge_smi_gpe0(void) { clear_gpe_status(); }
+static void southbridge_smi_gpe0(void) { pmc_clear_all_gpe_status(); }
static void southbridge_smi_tco(void)
{
- uint32_t tco_sts = clear_tco_status();
+ uint32_t tco_sts = pmc_clear_tco_status();
/* Any TCO event? */
if (!tco_sts)
@@ -354,7 +355,7 @@
/* We need to clear the SMI status registers, or we won't see what's
* happening in the following calls.
*/
- smi_sts = clear_smi_status();
+ smi_sts = pmc_clear_smi_status();
/* Call SMI sub handler for each of the status bits */
for (i = 0; i < ARRAY_SIZE(southbridge_smi); i++) {
diff --git a/src/soc/intel/denverton_ns/smm.c b/src/soc/intel/denverton_ns/smm.c
index 9d3fa75..65d2499 100644
--- a/src/soc/intel/denverton_ns/smm.c
+++ b/src/soc/intel/denverton_ns/smm.c
@@ -23,6 +23,7 @@
#include <cpu/x86/smm.h>
#include <string.h>
+#include <intelblocks/pmclib.h>
#include <soc/iomap.h>
#include <soc/soc_util.h>
#include <soc/pm.h>
@@ -48,10 +49,10 @@
}
/* Dump and clear status registers */
- clear_smi_status();
- clear_pm1_status();
- clear_tco_status();
- clear_gpe_status();
+ pmc_clear_smi_status();
+ pmc_clear_pm1_status();
+ pmc_clear_tco_status();
+ pmc_clear_all_gpe_status();
clear_pmc_status();
}
@@ -60,8 +61,8 @@
printk(BIOS_DEBUG, "Enabling SMIs.\n");
/* Configure events Disable pcie wake. */
- enable_pm1(PWRBTN_EN | GBL_EN | PCIEXPWAK_DIS);
- disable_gpe(PME_B0_EN);
+ pmc_enable_pm1(PWRBTN_EN | GBL_EN | PCIEXPWAK_DIS);
+ pmc_disable_std_gpe(PME_B0_EN);
/* Enable SMI generation:
* - on APMC writes (io 0xb2)
@@ -71,7 +72,7 @@
* - on TCO events
* - on microcontroller writes (io 0x62/0x66)
*/
- enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS);
+ pmc_enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS);
}
void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
--
To view, visit https://review.coreboot.org/c/coreboot/+/31072
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I13ab94e7440886f77e3091b16e50e48b17151751
Gerrit-Change-Number: 31072
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name>
Gerrit-MessageType: newchange
3 weeks, 1 day
- 2
- 3
Change in ...coreboot[master]: _WIP_ mb/amd/mandolin: Add Picasso CRB
by Marshall Dawson (Code Review)
Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33772
Change subject: _WIP_ mb/amd/mandolin: Add Picasso CRB
......................................................................
_WIP_ mb/amd/mandolin: Add Picasso CRB
We can get into ramstage with the state of Mandolin. Still no
AGESA running, and therefore we hang when trying to scan the PCI bus.
Change-Id: I2b4a78e1eef9f998e1986da1506201eb505822eb
Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com>
---
A src/mainboard/amd/mandolin/Kconfig
A src/mainboard/amd/mandolin/Kconfig.name
A src/mainboard/amd/mandolin/Makefile.inc
A src/mainboard/amd/mandolin/acpi/gpe.asl
A src/mainboard/amd/mandolin/acpi/mainboard.asl
A src/mainboard/amd/mandolin/acpi/routing.asl
A src/mainboard/amd/mandolin/acpi/sleep.asl
A src/mainboard/amd/mandolin/acpi/usb_oc.asl
A src/mainboard/amd/mandolin/acpi_tables.c
A src/mainboard/amd/mandolin/board_info.txt
A src/mainboard/amd/mandolin/devicetree.cb
A src/mainboard/amd/mandolin/dsdt.asl
A src/mainboard/amd/mandolin/gpio.c
A src/mainboard/amd/mandolin/gpio.h
A src/mainboard/amd/mandolin/irq_tables.c
A src/mainboard/amd/mandolin/mainboard.c
A src/mainboard/amd/mandolin/mptable.c
A src/mainboard/amd/mandolin/romstage.c
18 files changed, 1,242 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/33772/1
diff --git a/src/mainboard/amd/mandolin/Kconfig b/src/mainboard/amd/mandolin/Kconfig
new file mode 100644
index 0000000..5d1c287
--- /dev/null
+++ b/src/mainboard/amd/mandolin/Kconfig
@@ -0,0 +1,98 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2019 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+if BOARD_AMD_MANDOLIN
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select SOC_AMD_PICASSO
+ select HAVE_PIRQ_TABLE
+ select HAVE_MP_TABLE
+ select HAVE_ACPI_TABLES
+ select BOARD_ROMSIZE_KB_8192
+ select GFXUMA
+
+config AMD_LPC_DEBUG_CARD
+ bool "Enable LPC-Serial debug card on the debug header"
+ default n
+ select SUPERIO_SMSC_SIO1036
+ help
+ AMD's debug card contains an SMSC SIO1036 device which provides
+ an I/O-based UART in the system. This feature is not compatible with
+ CONFIG_HUDSON_UART enabling the memory-mapped UART in the chipset.
+ Note that Kconfig does not currently enforce this restriction.
+
+config CBFS_SIZE
+ default 0x400000
+ help
+ TODO: Adjust this! Right now it's simply making a lot of room for
+ amdfw.rom and EC firmware.
+
+config MAINBOARD_DIR
+ string
+ default amd/mandolin
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "MANDOLIN"
+
+config MAX_CPUS
+ int
+ default 8
+
+config IRQ_SLOT_COUNT
+ int
+ default 11
+
+config ONBOARD_VGA_IS_PRIMARY
+ bool
+ default y
+
+config PICASSO_LEGACY_FREE
+ bool
+ default y
+
+config MANDOLIN_HAVE_APCB_BLOB
+ bool "Have AGESA PSP Customization Block file?"
+ default n
+ help
+ The PSP requires the APCB file to know how to configure memory, as
+ well as other settings it will initialize. To build an image that
+ will get to POST, select 'y' and provide the file path/name. The
+ default of 'n' allows the board to build successfully but it avoids
+ redistributing the APCB blob extracted from UEFI.
+ TODO: Add the ability to construct APCB on the fly for any mainboard.
+
+config PSP_APCB_FILE
+ string "APCB file"
+ depends on MANDOLIN_HAVE_APCB_BLOB
+ default "3rdparty/blobs/mainboard/amd/mandolin/apcb.bin"
+ help
+ The name of the AGESA Parameter Customization Block. TODO: will we
+ be able to generate this at build-time? Build it offline for
+ inclusion?
+
+config MANDOLIN_HAVE_MCHP_FW
+ bool "Have Microchip EC firmware?"
+ default n
+ select AMDFW_OUTSIDE_CBFS
+ # todo: fix build the "inside" build.
+
+config MANDOLIN_MCHP_FW_FILE
+ string
+ depends on MANDOLIN_HAVE_MCHP_FW
+ default "3rdparty/blobs/mainboard/amd/mandolin/mchp.bin"
+
+endif # BOARD_AMD_MANDOLIN
diff --git a/src/mainboard/amd/mandolin/Kconfig.name b/src/mainboard/amd/mandolin/Kconfig.name
new file mode 100644
index 0000000..7dbfc3f
--- /dev/null
+++ b/src/mainboard/amd/mandolin/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_AMD_MANDOLIN
+ bool "Mandolin"
diff --git a/src/mainboard/amd/mandolin/Makefile.inc b/src/mainboard/amd/mandolin/Makefile.inc
new file mode 100644
index 0000000..fe17e8e
--- /dev/null
+++ b/src/mainboard/amd/mandolin/Makefile.inc
@@ -0,0 +1,41 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2019 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+romstage-y += gpio.c
+ramstage-y += gpio.c
+
+PHONY+=add_mchp_fw
+INTERMEDIATE+=add_mchp_fw
+
+ifeq ($(CONFIG_MANDOLIN_HAVE_MCHP_FW),y)
+
+MANDOLIN_MICROCHIP_FW_OFFSET=0
+add_mchp_fw:
+ printf " DD Adding Microchip firmware at ROM offset 0x%x\n" \
+ "$(MANDOLIN_MICROCHIP_FW_OFFSET)"
+ dd if=$(CONFIG_MANDOLIN_MCHP_FW_FILE) \
+ of=$(obj)/coreboot.pre conv=notrunc bs=1 \
+ seek=$(MANDOLIN_MICROCHIP_FW_OFFSET) >/dev/null 2>&1
+
+else
+files_added:: warn_no_mchp
+endif # CONFIG_MANDOLIN_HAVE_MCHP_FW
+
+PHONY+=warn_no_mchp
+warn_no_mchp:
+ printf "\n\t** WARNING **\n"
+ printf "coreboot has been built without an the Microchip EC.\n"
+ printf "Do not flash this image. Your Mandolin's power button\n"
+ printf "will not respond when you press it.\n\n"
diff --git a/src/mainboard/amd/mandolin/acpi/gpe.asl b/src/mainboard/amd/mandolin/acpi/gpe.asl
new file mode 100644
index 0000000..d3c89fd
--- /dev/null
+++ b/src/mainboard/amd/mandolin/acpi/gpe.asl
@@ -0,0 +1,76 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+//
+//
+//
+// todo: check file for accuracy
+//
+//
+//
+
+Scope(\_GPE) { /* Start Scope GPE */
+
+ /* General event 3 */
+ Method(_L03) {
+ /* DBGO("\\_GPE\\_L00\n") */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* Legacy PM event */
+ Method(_L08) {
+ /* DBGO("\\_GPE\\_L08\n") */
+ }
+
+ /* Temp warning (TWarn) event */
+ Method(_L09) {
+ /* DBGO("\\_GPE\\_L09\n") */
+ /* Notify (\_TZ.TZ00, 0x80) */
+ }
+
+ /* USB controller PME# */
+ Method(_L0B) {
+ /* DBGO("\\_GPE\\_L0B\n") */
+ Notify(\_SB.PCI0.EHC0, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* ExtEvent0 SCI event */
+ Method(_L10) {
+ /* DBGO("\\_GPE\\_L10\n") */
+ }
+
+ /* ExtEvent1 SCI event */
+ Method(_L11) {
+ /* DBGO("\\_GPE\\_L11\n") */
+ }
+
+ /* GPIO0 or GEvent8 event */
+ Method(_L18) {
+ /* DBGO("\\_GPE\\_L18\n") */
+ Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* Azalia SCI event */
+ Method(_L1B) {
+ /* DBGO("\\_GPE\\_L1B\n") */
+ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+} /* End Scope GPE */
diff --git a/src/mainboard/amd/mandolin/acpi/mainboard.asl b/src/mainboard/amd/mandolin/acpi/mainboard.asl
new file mode 100644
index 0000000..d73fbea
--- /dev/null
+++ b/src/mainboard/amd/mandolin/acpi/mainboard.asl
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+//
+//
+//
+// todo: check file for accuracy
+//
+//
+//
+
+/* Memory related values */
+Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
+Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
+Name(PBLN, 0x0) /* Length of BIOS area */
+
+Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
+Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
+Name(HPBA, 0xFED00000) /* Base address of HPET table */
+
+/* Some global data */
+Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
+Name(OSV, Ones) /* Assume nothing */
+Name(PMOD, One) /* Assume APIC */
diff --git a/src/mainboard/amd/mandolin/acpi/routing.asl b/src/mainboard/amd/mandolin/acpi/routing.asl
new file mode 100644
index 0000000..969def7
--- /dev/null
+++ b/src/mainboard/amd/mandolin/acpi/routing.asl
@@ -0,0 +1,173 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015, 2016 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+//
+//
+//
+// todo: check file for accuracy
+//
+//
+//
+
+/*
+#include <arch/acpi.h>
+DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001
+ )
+ {
+ #include "routing.asl"
+ }
+*/
+
+/* Routing is in System Bus scope */
+Name(PR0, Package(){
+ /* NB devices */
+ /* Bus 0, Dev 0 - F15 Host Controller */
+
+ /* Bus 0, Dev 1, Func 0 - PCI Bridge for Internal Graphics(IGP) */
+ /* Bus 0, Dev 1, Func 1 - HDMI Audio Controller */
+ Package(){0x0001FFFF, 0, INTB, 0 },
+ Package(){0x0001FFFF, 1, INTC, 0 },
+
+
+ /* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */
+ Package(){0x0002FFFF, 0, INTC, 0 },
+ Package(){0x0002FFFF, 1, INTD, 0 },
+ Package(){0x0002FFFF, 2, INTA, 0 },
+ Package(){0x0002FFFF, 3, INTB, 0 },
+
+ /* FCH devices */
+ /* Bus 0, Dev 20 - F0:SMBus/ACPI;F3:LPC;F7:SD */
+ Package(){0x0014FFFF, 0, INTA, 0 },
+ Package(){0x0014FFFF, 1, INTB, 0 },
+ Package(){0x0014FFFF, 2, INTC, 0 },
+ Package(){0x0014FFFF, 3, INTD, 0 },
+
+ /* Bus 0, Dev 18 Func 0 - USB: EHCI */
+ Package(){0x0012FFFF, 0, INTC, 0 },
+ Package(){0x0012FFFF, 1, INTB, 0 },
+
+ /* Bus 0, Dev 10 Func 0 - USB: xHCI */
+ Package(){0x0010FFFF, 0, INTC, 0 },
+ Package(){0x0010FFFF, 1, INTB, 0 },
+
+ /* Bus 0, Dev 17 - SATA controller */
+ Package(){0x0011FFFF, 0, INTD, 0 },
+
+})
+
+Name(APR0, Package(){
+ /* NB devices in APIC mode */
+ /* Bus 0, Dev 0 - F15 Host Controller */
+
+ /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
+ Package(){0x0001FFFF, 0, 0, 43 },
+ Package(){0x0001FFFF, 1, 0, 40 },
+
+ /* Bus 0, Dev 2 - PCIe Bridges */
+ Package(){0x0002FFFF, 0, 0, 44 },
+ Package(){0x0002FFFF, 1, 0, 45 },
+ Package(){0x0002FFFF, 2, 0, 46 },
+ Package(){0x0002FFFF, 3, 0, 47 },
+
+ /* SB devices in APIC mode */
+ /* Bus 0, Dev 20 - F0:SMBus/ACPI;F3:LPC;F7:SD */
+ Package(){0x0014FFFF, 0, 0, 16 },
+ Package(){0x0014FFFF, 1, 0, 17 },
+ Package(){0x0014FFFF, 2, 0, 18 },
+ Package(){0x0014FFFF, 3, 0, 19 },
+
+ /* Bus 0, Dev 18 Func 0 - USB: EHCI */
+ Package(){0x0012FFFF, 0, 0, 18 },
+ Package(){0x0012FFFF, 1, 0, 17 },
+
+ /* Bus 0, Dev 10 Func 0 - USB: xHCI */
+ Package(){0x0010FFFF, 0, 0, 18},
+ Package(){0x0010FFFF, 1, 0, 17},
+
+ /* Bus 0, Dev 17 - SATA controller */
+ Package(){0x0011FFFF, 0, 0, 19 },
+})
+
+
+/* GPP 0 */
+Name(PS4, Package(){
+ Package(){0x0000FFFF, 0, INTA, 0 },
+ Package(){0x0000FFFF, 1, INTB, 0 },
+ Package(){0x0000FFFF, 2, INTC, 0 },
+ Package(){0x0000FFFF, 3, INTD, 0 },
+})
+Name(APS4, Package(){
+ /* PCIe slot - Hooked to PCIe slot 4 */
+ Package(){0x0000FFFF, 0, 0, 24 },
+ Package(){0x0000FFFF, 1, 0, 25 },
+ Package(){0x0000FFFF, 2, 0, 26 },
+ Package(){0x0000FFFF, 3, 0, 27 },
+})
+
+/* GPP 1 */
+Name(PS5, Package(){
+ Package(){0x0000FFFF, 0, INTB, 0 },
+ Package(){0x0000FFFF, 1, INTC, 0 },
+ Package(){0x0000FFFF, 2, INTD, 0 },
+ Package(){0x0000FFFF, 3, INTA, 0 },
+})
+Name(APS5, Package(){
+ Package(){0x0000FFFF, 0, 0, 28 },
+ Package(){0x0000FFFF, 1, 0, 29 },
+ Package(){0x0000FFFF, 2, 0, 30 },
+ Package(){0x0000FFFF, 3, 0, 31 },
+})
+
+/* GPP 2 */
+Name(PS6, Package(){
+ Package(){0x0000FFFF, 0, INTC, 0 },
+ Package(){0x0000FFFF, 1, INTD, 0 },
+ Package(){0x0000FFFF, 2, INTA, 0 },
+ Package(){0x0000FFFF, 3, INTB, 0 },
+})
+Name(APS6, Package(){
+ Package(){0x0000FFFF, 0, 0, 32 },
+ Package(){0x0000FFFF, 1, 0, 33 },
+ Package(){0x0000FFFF, 2, 0, 34 },
+ Package(){0x0000FFFF, 3, 0, 35 },
+})
+
+/* GPP 3 */
+Name(PS7, Package(){
+ Package(){0x0000FFFF, 0, INTD, 0 },
+ Package(){0x0000FFFF, 1, INTA, 0 },
+ Package(){0x0000FFFF, 2, INTB, 0 },
+ Package(){0x0000FFFF, 3, INTC, 0 },
+})
+Name(APS7, Package(){
+ Package(){0x0000FFFF, 0, 0, 36 },
+ Package(){0x0000FFFF, 1, 0, 37 },
+ Package(){0x0000FFFF, 2, 0, 38 },
+ Package(){0x0000FFFF, 3, 0, 39 },
+})
+
+/* GPP 4 */
+Name(PS8, Package(){
+ Package(){0x0000FFFF, 0, INTA, 0 },
+ Package(){0x0000FFFF, 1, INTB, 0 },
+ Package(){0x0000FFFF, 2, INTC, 0 },
+ Package(){0x0000FFFF, 3, INTD, 0 },
+})
+Name(APS8, Package(){
+ Package(){0x0000FFFF, 0, 0, 40 },
+ Package(){0x0000FFFF, 1, 0, 41 },
+ Package(){0x0000FFFF, 2, 0, 42 },
+ Package(){0x0000FFFF, 3, 0, 43 },
+})
diff --git a/src/mainboard/amd/mandolin/acpi/sleep.asl b/src/mainboard/amd/mandolin/acpi/sleep.asl
new file mode 100644
index 0000000..baf3ca5
--- /dev/null
+++ b/src/mainboard/amd/mandolin/acpi/sleep.asl
@@ -0,0 +1,93 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+//
+//
+//
+// todo: check file for accuracy
+//
+//
+//
+
+/* Wake status package */
+Name(WKST,Package(){Zero, Zero})
+
+/*
+* \_PTS - Prepare to Sleep method
+*
+* Entry:
+* Arg0=The value of the sleeping state S1=1, S2=2, etc
+*
+* Exit:
+* -none-
+*
+* The _PTS control method is executed at the beginning of the sleep process
+* for S1-S5. The sleeping value is passed to the _PTS control method. This
+* control method may be executed a relatively long time before entering the
+* sleep state and the OS may abort the operation without notification to
+* the ACPI driver. This method cannot modify the configuration or power
+* state of any device in the system.
+*/
+Method(_PTS, 1) {
+ /* DBGO("\\_PTS\n") */
+ /* DBGO("From S0 to S") */
+ /* DBGO(Arg0) */
+ /* DBGO("\n") */
+
+ /* Clear wake status structure. */
+ Store(0, PEWD)
+ Store(0, Index(WKST,0))
+ Store(0, Index(WKST,1))
+ Store(7, UPWS)
+} /* End Method(\_PTS) */
+
+/*
+* \_BFS OEM Back From Sleep method
+*
+* Entry:
+* Arg0=The value of the sleeping state S1=1, S2=2
+*
+* Exit:
+* -none-
+*/
+Method(\_BFS, 1) {
+ /* DBGO("\\_BFS\n") */
+ /* DBGO("From S") */
+ /* DBGO(Arg0) */
+ /* DBGO(" to S0\n") */
+}
+
+/*
+* \_WAK System Wake method
+*
+* Entry:
+* Arg0=The value of the sleeping state S1=1, S2=2
+*
+* Exit:
+* Return package of 2 DWords
+* Dword 1 - Status
+* 0x00000000 wake succeeded
+* 0x00000001 Wake was signaled but failed due to lack of power
+* 0x00000002 Wake was signaled but failed due to thermal condition
+* Dword 2 - Power Supply state
+* if non-zero the effective S-state the power supply entered
+*/
+Method(\_WAK, 1) {
+ /* DBGO("\\_WAK\n") */
+ /* DBGO("From S") */
+ /* DBGO(Arg0) */
+ /* DBGO(" to S0\n") */
+
+ Return(WKST)
+} /* End Method(\_WAK) */
diff --git a/src/mainboard/amd/mandolin/acpi/usb_oc.asl b/src/mainboard/amd/mandolin/acpi/usb_oc.asl
new file mode 100644
index 0000000..ea7bd27
--- /dev/null
+++ b/src/mainboard/amd/mandolin/acpi/usb_oc.asl
@@ -0,0 +1,47 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+//
+//
+//
+// todo: check file for accuracy
+// - file had a todo to update for Gardenia
+//
+//
+//
+
+/* simple name description */
+/*
+#include <arch/acpi.h>
+DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001
+ )
+ {
+ #include "usb.asl"
+ }
+*/
+
+/* USB overcurrent mapping pins. */
+Name(UOM0, 0)
+Name(UOM1, 2)
+Name(UOM2, 0)
+Name(UOM3, 7)
+Name(UOM4, 2)
+Name(UOM5, 2)
+Name(UOM6, 6)
+Name(UOM7, 2)
+Name(UOM8, 6)
+Name(UOM9, 6)
+
+/* USB Overcurrent GPEs */
diff --git a/src/mainboard/amd/mandolin/acpi_tables.c b/src/mainboard/amd/mandolin/acpi_tables.c
new file mode 100644
index 0000000..8d4d1cf
--- /dev/null
+++ b/src/mainboard/amd/mandolin/acpi_tables.c
@@ -0,0 +1,14 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * Blank file required by build system assumptions of this file being present.
+ */
diff --git a/src/mainboard/amd/mandolin/board_info.txt b/src/mainboard/amd/mandolin/board_info.txt
new file mode 100644
index 0000000..b351b8e
--- /dev/null
+++ b/src/mainboard/amd/mandolin/board_info.txt
@@ -0,0 +1 @@
+Category: eval
diff --git a/src/mainboard/amd/mandolin/devicetree.cb b/src/mainboard/amd/mandolin/devicetree.cb
new file mode 100644
index 0000000..8cb7da9
--- /dev/null
+++ b/src/mainboard/amd/mandolin/devicetree.cb
@@ -0,0 +1,60 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2015-2019 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+chip soc/amd/picasso
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+ device domain 0 on
+ subsystemid 0x1022 0x1510 inherit
+ device pci 0.0 on end # Root Complex
+ device pci 0.2 on end # IOMMU
+ device pci 1.0 on end # Dummy Host Bridge
+ device pci 1.2 on end # Bridge
+ device pci 1.3 on end # Bridge
+ device pci 8.0 on end # Dummy Host Bridge
+ device pci 8.1 on end # Bridge
+ device pci 8.2 on end # Bridge
+ device pci 14.0 on # SM
+ chip drivers/generic/generic # dimm 0-0-0
+ device i2c 50 on end
+ device i2c 51 on end
+ end
+ chip superio/smsc/sio1036 # optional debug card
+ end
+ end # SM
+ device pci 14.3 on end # LPC
+ device pci 14.6 on end #
+ device pci 18.0 on end
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ device pci 18.4 on end
+ device pci 18.5 on end
+ device pci 18.6 on end
+ device pci 18.7 on end
+ end # domain
+ # todo: on a separate bus now:
+ # 2:0.0 15D8 display controller
+ # 2:0.1 15DE HD Audio
+ # 2:0.2 15DF Crypto Coprocessor
+ # 2:0.3 15E0 serial
+ # 2:0.4 15E1 serial
+ # 2:0.5 15E2 Audio Processor
+ # 2:0.6 15E3 Audio Processor - HD Audio Controller
+ # 2:0.7 15E6 Non-Sensor Fusion hub device
+ # 3:0.0 7901 SATA
+ # 3:0.1 1458 10GbE (per HDT)
+ # 3:0.2 1458 10GbE (per HDT)
+end # chip soc/amd/picasso
diff --git a/src/mainboard/amd/mandolin/dsdt.asl b/src/mainboard/amd/mandolin/dsdt.asl
new file mode 100644
index 0000000..25c0e78
--- /dev/null
+++ b/src/mainboard/amd/mandolin/dsdt.asl
@@ -0,0 +1,83 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015-2017 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+//
+//
+//
+// todo: check file for accuracy
+//
+//
+//
+
+#define MAINBOARD_HAS_SPEAKER 1
+
+/* DefinitionBlock Statement */
+#include <arch/acpi.h>
+DefinitionBlock (
+ "DSDT.AML", /* Output filename */
+ "DSDT", /* Signature */
+ 0x02, /* DSDT Revision, needs to be 2 for 64bit */
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x00010001 /* OEM Revision */
+ )
+{ /* Start of ASL file */
+ /* #include <arch/x86/acpi/debug.asl> */ /* as needed */
+
+ /* global NVS and variables */
+ #include <globalnvs.asl>
+
+ /* Globals for the platform */
+ #include "acpi/mainboard.asl"
+
+ /* Describe the USB Overcurrent pins */
+ #include "acpi/usb_oc.asl"
+
+ /* PCI IRQ mapping for the Southbridge */
+ #include <pcie.asl>
+
+ /* Describe the processor tree (\_PR) */
+ #include <cpu.asl>
+
+ /* Contains the supported sleep states for this chipset */
+ #include <sleepstates.asl>
+
+ /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
+ #include "acpi/sleep.asl"
+
+ /* System Bus */
+ Scope(\_SB) { /* Start \_SB scope */
+ /* global utility methods expected within the \_SB scope */
+ #include <arch/x86/acpi/globutil.asl>
+
+ /* IRQ Routing mapping for this platform (in \_SB scope) */
+ #include "acpi/routing.asl"
+
+ Device(PWRB) {
+ Name(_HID, EISAID("PNP0C0C"))
+ Name(_UID, 0xAA)
+ Name(_PRW, Package () {3, 0x04})
+ Name(_STA, 0x0B)
+ }
+
+ /* Describe the SOC */
+ #include <soc.asl>
+
+ } /* End \_SB scope */
+
+ /* Define the General Purpose Events for the platform */
+ #include "acpi/gpe.asl"
+}
+/* End of ASL file */
diff --git a/src/mainboard/amd/mandolin/gpio.c b/src/mainboard/amd/mandolin/gpio.c
new file mode 100644
index 0000000..aa16826
--- /dev/null
+++ b/src/mainboard/amd/mandolin/gpio.c
@@ -0,0 +1,83 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015-2019 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/southbridge.h>
+#include <stdlib.h>
+#include <soc/gpio.h>
+
+#include "gpio.h"
+
+/*
+ * As a rule of thumb, GPIO pins used by coreboot should be initialized at
+ * bootblock while GPIO pins used only by the OS should be initialized at
+ * ramstage.
+ */
+static const struct soc_amd_gpio gpio_set_stage_reset[] = {
+ /* not LLB */
+ PAD_GPI(GPIO_12, PULL_UP),
+ /* not USB_OC5_L */
+ PAD_GPI(GPIO_13, PULL_UP),
+ /* not USB_OC4_L */
+ PAD_GPI(GPIO_14, PULL_UP),
+ /* not USB_OC1_L */
+ PAD_GPI(GPIO_17, PULL_UP),
+ /* not USB_OC2_L */
+ PAD_GPI(GPIO_18, PULL_UP),
+ /* SDIO eMMC power control */
+ PAD_NF(GPIO_22, EMMC_PRW_CTRL, PULL_NONE),
+ /* PCIe SSD power enable */
+ PAD_GPO(GPIO_23, HIGH),
+ /* PCIe Reset to DP0, DP1, J2105, TP, FP */
+ PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE),
+ /* eSPI CS# */
+ PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE),
+ /* FANOUT0 */
+ PAD_NF(GPIO_85, FANOUT0, PULL_NONE),
+ /* PC beep to codec */
+ PAD_NF(GPIO_91, SPKR, PULL_NONE),
+};
+
+static const struct soc_amd_gpio gpio_set_stage_ram[] = {
+ /* SSD DEVSLP */
+ PAD_NF(GPIO_5, DEVSLP0_S5, PULL_NONE),
+ /* SATA Express DEVSLP */
+ PAD_NF(GPIO_6, DEVSLP1_S5, PULL_NONE),
+ /* I2S SDIN */
+ PAD_NF(GPIO_7, ACP_I2S_SDIN, PULL_NONE),
+ /* I2S LRCLK */
+ PAD_NF(GPIO_8, ACP_I2S_LRCLK, PULL_NONE),
+ /* Blink */
+ PAD_NF(GPIO_11, BLINK, PULL_NONE),
+ /* APU_ALS_INT# */
+ PAD_SCI(GPIO_24, PULL_UP, EDGE_LOW),
+ /* Finger print CS# */
+ PAD_GPO(GPIO_31, HIGH),
+ /* NFC IRQ */
+ PAD_INT(GPIO_69, PULL_UP, EDGE_LOW, STATUS),
+ /* Rear camera power enable */
+ PAD_GPO(GPIO_89, HIGH),
+};
+
+const struct soc_amd_gpio *early_gpio_table(size_t *size)
+{
+ *size = ARRAY_SIZE(gpio_set_stage_reset);
+ return gpio_set_stage_reset;
+}
+
+const struct soc_amd_gpio *gpio_table(size_t *size)
+{
+ *size = ARRAY_SIZE(gpio_set_stage_ram);
+ return gpio_set_stage_ram;
+}
diff --git a/src/mainboard/amd/mandolin/gpio.h b/src/mainboard/amd/mandolin/gpio.h
new file mode 100644
index 0000000..1d3a8a2
--- /dev/null
+++ b/src/mainboard/amd/mandolin/gpio.h
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+const struct soc_amd_gpio *early_gpio_table(size_t *size);
+const struct soc_amd_gpio *gpio_table(size_t *size);
+
+#endif /* MAINBOARD_GPIO_H */
diff --git a/src/mainboard/amd/mandolin/irq_tables.c b/src/mainboard/amd/mandolin/irq_tables.c
new file mode 100644
index 0000000..bf1daec
--- /dev/null
+++ b/src/mainboard/amd/mandolin/irq_tables.c
@@ -0,0 +1,100 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <device/pci.h>
+#include <string.h>
+#include <stdint.h>
+#include <arch/pirq_routing.h>
+
+static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
+ u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
+ u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
+ u8 slot, u8 rfu)
+{
+ pirq_info->bus = bus;
+ pirq_info->devfn = devfn;
+ pirq_info->irq[0].link = link0;
+ pirq_info->irq[0].bitmap = bitmap0;
+ pirq_info->irq[1].link = link1;
+ pirq_info->irq[1].bitmap = bitmap1;
+ pirq_info->irq[2].link = link2;
+ pirq_info->irq[2].bitmap = bitmap2;
+ pirq_info->irq[3].link = link3;
+ pirq_info->irq[3].bitmap = bitmap3;
+ pirq_info->slot = slot;
+ pirq_info->rfu = rfu;
+}
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+ struct irq_routing_table *pirq;
+ struct irq_info *pirq_info;
+ u32 slot_num;
+ u8 *v;
+
+ u8 sum = 0;
+ int i;
+
+ /* Align the table to be 16 byte aligned. */
+ addr += 15;
+ addr &= ~15;
+
+ /* This table must be between 0xf0000 & 0x100000 */
+ printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
+
+ pirq = (void *)(addr);
+ v = (u8 *) (addr);
+
+ pirq->signature = PIRQ_SIGNATURE;
+ pirq->version = PIRQ_VERSION;
+
+ pirq->rtr_bus = 0;
+ pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
+
+ pirq->exclusive_irqs = 0;
+
+ pirq->rtr_vendor = 0x1002;
+ pirq->rtr_device = 0x4384;
+
+ pirq->miniport_data = 0;
+
+ memset(pirq->rfu, 0, sizeof(pirq->rfu));
+
+ pirq_info = (void *)(&pirq->checksum + 1);
+ slot_num = 0;
+
+ /* pci bridge */
+ write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4),
+ 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
+ 0);
+ pirq_info++;
+
+ slot_num++;
+
+ pirq->size = 32 + 16 * slot_num;
+
+ for (i = 0; i < pirq->size; i++)
+ sum += v[i];
+
+ sum = pirq->checksum - sum;
+
+ if (sum != pirq->checksum)
+ pirq->checksum = sum;
+
+ printk(BIOS_INFO, "write_pirq_routing_table done.\n");
+
+ return (unsigned long)pirq_info;
+}
diff --git a/src/mainboard/amd/mandolin/mainboard.c b/src/mainboard/amd/mandolin/mainboard.c
new file mode 100644
index 0000000..6f2d1d9
--- /dev/null
+++ b/src/mainboard/amd/mandolin/mainboard.c
@@ -0,0 +1,110 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <arch/acpi.h>
+#include <amdblocks/amd_pci_util.h>
+#include <soc/southbridge.h>
+
+#include "gpio.h"
+//
+//
+//
+// todo: check file for accuracy
+//
+//
+//
+
+/***********************************************************
+ * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
+ * This table is responsible for physically routing the PIC and
+ * IOAPIC IRQs to the different PCI devices on the system. It
+ * is read and written via registers 0xC00/0xC01 as an
+ * Index/Data pair. These values are chipset and mainboard
+ * dependent and should be updated accordingly.
+ *
+ * These values are used by the PCI configuration space,
+ * MP Tables. TODO: Make ACPI use these values too.
+ */
+const u8 mainboard_picr_data[] = {
+ [0x00] = 0x03, 0x04, 0x05, 0x07, 0x0B, 0x0A, 0x1F, 0x1F,
+ [0x08] = 0xFA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
+ [0x10] = 0x1F, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, 0x1F,
+ [0x18] = 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00,
+ [0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ [0x30] = 0x05, 0x04, 0x05, 0x04, 0x04, 0x05, 0x04, 0x05,
+ [0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ [0x40] = 0x04, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ [0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ [0x50] = 0x03, 0x04, 0x05, 0x07, 0x1F, 0x1F, 0x1F, 0x1F,
+ [0x58] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+ [0x60] = 0x1F, 0x1F, 0x07, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+ [0x68] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+ [0x70] = 0x03, 0x0F, 0x06, 0x0E, 0x0A, 0x0B, 0x1F, 0x1F,
+ [0x78] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+};
+
+const u8 mainboard_intr_data[] = {
+ [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
+ [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
+ [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x1F, 0x1F, 0x10,
+ [0x18] = 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00,
+ [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00,
+ [0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ [0x30] = 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00,
+ [0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ [0x40] = 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ [0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ [0x50] = 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00,
+ [0x58] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ [0x60] = 0x1F, 0x1F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00,
+ [0x68] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ [0x70] = 0x03, 0x0F, 0x06, 0x0E, 0x0A, 0x0B, 0x1F, 0x1F,
+ [0x78] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+};
+
+/* PIRQ Setup */
+static void pirq_setup(void)
+{
+ intr_data_ptr = mainboard_intr_data;
+ picr_data_ptr = mainboard_picr_data;
+}
+
+static void mainboard_init(void *chip_info)
+{
+ size_t num_gpios;
+ const struct soc_amd_gpio *gpios;
+ gpios = gpio_table(&num_gpios);
+ program_gpios(gpios, num_gpios);
+}
+
+/*************************************************
+ * enable the dedicated function in mandolin board.
+ *************************************************/
+static void mandolin_enable(struct device *dev)
+{
+ printk(BIOS_INFO, "Mainboard "
+ CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
+
+ /* Initialize the PIRQ data structures for consumption */
+ pirq_setup();
+}
+
+struct chip_operations mainboard_ops = {
+ .init = mainboard_init,
+ .enable_dev = mandolin_enable,
+};
diff --git a/src/mainboard/amd/mandolin/mptable.c b/src/mainboard/amd/mandolin/mptable.c
new file mode 100644
index 0000000..4e80ce1
--- /dev/null
+++ b/src/mainboard/amd/mandolin/mptable.c
@@ -0,0 +1,171 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+//
+//
+//
+// todo: check file for accuracy
+//
+//
+//
+
+#include <arch/smp/mpspec.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <arch/ioapic.h>
+#include <string.h>
+#include <stdint.h>
+#include <cpu/x86/lapic.h>
+#include <soc/southbridge.h>
+#include <amdblocks/amd_pci_util.h>
+
+static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
+{
+ mc->mpc_length += length;
+ mc->mpc_entry_count++;
+}
+
+static void my_smp_write_bus(struct mp_config_table *mc,
+ unsigned char id, const char *bustype)
+{
+ struct mpc_config_bus *mpc;
+ mpc = smp_next_mpc_entry(mc);
+ memset(mpc, '\0', sizeof(*mpc));
+ mpc->mpc_type = MP_BUS;
+ mpc->mpc_busid = id;
+ memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
+ smp_add_mpc_entry(mc, sizeof(*mpc));
+}
+
+static void *smp_write_config_table(void *v)
+{
+ struct mp_config_table *mc;
+ int bus_isa;
+
+ /*
+ * By the time this function gets called, the IOAPIC registers
+ * have been written so they can be read to get the correct
+ * APIC ID and Version
+ */
+ u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
+
+ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+
+ mptable_init(mc, LOCAL_APIC_ADDR);
+ memcpy(mc->mpc_oem, "AMD ", 8);
+
+ smp_write_processors(mc);
+
+ //mptable_write_buses(mc, NULL, &bus_isa);
+ my_smp_write_bus(mc, 0, "PCI ");
+ my_smp_write_bus(mc, 1, "PCI ");
+ bus_isa = 0x02;
+ my_smp_write_bus(mc, bus_isa, "ISA ");
+
+ /* I/O APICs: APIC ID Version State Address */
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
+
+ smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
+
+ /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
+#define IO_LOCAL_INT(type, intr, apicid, pin) \
+ smp_write_lintsrc(mc, (type), \
+ MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, \
+ (intr), (apicid), (pin))
+ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
+
+ /* PCI interrupts are level triggered, and are
+ * associated with a specific bus/device/function tuple.
+ */
+#define PCI_INT(bus, dev, int_sign, pin) \
+ smp_write_intsrc(mc, mp_INT, \
+ MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), \
+ (((dev)<<2)|(int_sign)), ioapic_id, (pin))
+
+ /* Internal VGA */
+ PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
+ PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
+
+ /* SMBUS */
+ PCI_INT(0x0, 0x14, 0x0, 0x10);
+
+ /* HD Audio */
+ PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
+
+ /* USB */
+ PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
+ PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
+ PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
+ PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
+ PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
+ PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
+ PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
+
+ /* sata */
+ PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
+ PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
+
+ /* on board NIC & Slot PCIE. */
+
+ /* PCI slots */
+ struct device *dev = pcidev_on_root(0x14, 4);
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+
+ /* PCI_SLOT 1. */
+ PCI_INT(bus_pci, 0x6, 0x0, 0x15);
+ PCI_INT(bus_pci, 0x6, 0x1, 0x16);
+ PCI_INT(bus_pci, 0x6, 0x2, 0x17);
+ PCI_INT(bus_pci, 0x6, 0x3, 0x14);
+
+ /* PCI_SLOT 2. */
+ PCI_INT(bus_pci, 0x7, 0x0, 0x16);
+ PCI_INT(bus_pci, 0x7, 0x1, 0x17);
+ PCI_INT(bus_pci, 0x7, 0x2, 0x14);
+ PCI_INT(bus_pci, 0x7, 0x3, 0x15);
+ }
+
+ /* PCIe Lan*/
+ PCI_INT(0x0, 0x06, 0x0, 0x13);
+
+ /* FCH PCIe PortA */
+ PCI_INT(0x0, 0x15, 0x0, 0x10);
+ /* FCH PCIe PortB */
+ PCI_INT(0x0, 0x15, 0x1, 0x11);
+ /* FCH PCIe PortC */
+ PCI_INT(0x0, 0x15, 0x2, 0x12);
+ /* FCH PCIe PortD */
+ PCI_INT(0x0, 0x15, 0x3, 0x13);
+
+ /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
+ IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
+ IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
+ /* There is no extension information... */
+
+ /* Compute the checksums */
+ return mptable_finalize(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+ void *v;
+ v = smp_write_floating_table(addr, 0);
+ return (unsigned long)smp_write_config_table(v);
+}
diff --git a/src/mainboard/amd/mandolin/romstage.c b/src/mainboard/amd/mandolin/romstage.c
new file mode 100644
index 0000000..1741a39
--- /dev/null
+++ b/src/mainboard/amd/mandolin/romstage.c
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stddef.h>
+#include <soc/romstage.h>
+#include <superio/smsc/sio1036/sio1036.h>
+#include <soc/gpio.h>
+#include "gpio.h"
+
+#define SERIAL_DEV PNP_DEV(0x4e, SIO1036_SP1)
+
+void romstage_mainboard_early_init(void)
+{
+ size_t num_gpios;
+ const struct soc_amd_gpio *gpios;
+ gpios = early_gpio_table(&num_gpios);
+ program_gpios(gpios, num_gpios);
+
+ if (CONFIG(SUPERIO_SMSC_SIO1036))
+ sio1036_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+}
--
To view, visit https://review.coreboot.org/c/coreboot/+/33772
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I2b4a78e1eef9f998e1986da1506201eb505822eb
Gerrit-Change-Number: 33772
Gerrit-PatchSet: 1
Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Gerrit-MessageType: newchange
3 weeks, 2 days
- 6
- 65
Change in ...coreboot[master]: google_chromeec_command: makes the error status consistent
by YH Lin (Code Review)
YH Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31626
Change subject: google_chromeec_command: makes the error status consistent
......................................................................
google_chromeec_command: makes the error status consistent
Currently various google_chromeec_command() implementation the error
can be returned differently (LPC: -1 for v3, 1 for v1, SPI: -1/1,
I2C: 1). This patch attempts to make it consistent across all
implementations by using only negative number as error.
All direct/indirect callers of google_chromeec_command() have also
been modified accordingly as well.
BRANCH=None
BUG=chromium:935038
Signed-off-by: YH Lin <yueherngl(a)google.com>
Change-Id: I39f12502bc6982670dd200dcef0724e7eed2ed29
---
M src/ec/google/chromeec/crosec_proto.c
M src/ec/google/chromeec/ec.c
M src/ec/google/chromeec/ec.h
M src/ec/google/chromeec/ec_i2c.c
M src/ec/google/chromeec/ec_lpc.c
M src/ec/google/chromeec/smihandler.c
M src/ec/google/chromeec/vboot_storage.c
M src/ec/google/chromeec/vstore.c
M src/mainboard/google/gru/mainboard.c
M src/security/vboot/vboot_logic.c
10 files changed, 35 insertions(+), 31 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/31626/1
diff --git a/src/ec/google/chromeec/crosec_proto.c b/src/ec/google/chromeec/crosec_proto.c
index 2043347..603f1df 100644
--- a/src/ec/google/chromeec/crosec_proto.c
+++ b/src/ec/google/chromeec/crosec_proto.c
@@ -246,7 +246,7 @@
int rv = send_command_proto3(cec_command, crosec_io, context);
if (rv < 0) {
cec_command->cmd_code = rv;
- return 1;
+ return -1;
}
return 0;
}
diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c
index 09357b0..897dceb 100644
--- a/src/ec/google/chromeec/ec.c
+++ b/src/ec/google/chromeec/ec.c
@@ -363,7 +363,7 @@
cmd.cmd_size_out = sizeof(rsp);
cmd.cmd_dev_index = 0;
- if (google_chromeec_command(&cmd) == 0)
+ if (google_chromeec_command(&cmd) >= 0)
return rsp.event_mask;
return 0;
}
@@ -404,7 +404,7 @@
cmd.cmd_size_out = sizeof(rsp);
cmd.cmd_dev_index = 0;
- if (google_chromeec_command(&cmd) == 0)
+ if (google_chromeec_command(&cmd) >= 0)
return rsp.event_mask;
return 0;
}
@@ -507,7 +507,7 @@
cmd.cmd_size_out = sizeof(r);
cmd.cmd_dev_index = 0;
- if (google_chromeec_command(&cmd) != 0)
+ if (google_chromeec_command(&cmd) < 0)
return -1;
if (feature >= 8 * sizeof(r.flags))
@@ -531,7 +531,7 @@
cmd.cmd_size_out = 0;
cmd.cmd_dev_index = 0;
- if (google_chromeec_command(&cmd) != 0)
+ if (google_chromeec_command(&cmd) < 0)
return -1;
return 0;
@@ -550,7 +550,7 @@
cmd.cmd_size_out = sizeof(r);
cmd.cmd_dev_index = 0;
- if (google_chromeec_command(&cmd) != 0)
+ if (google_chromeec_command(&cmd) < 0)
return -1;
return rtc_to_tm(r.time, time);
@@ -658,7 +658,7 @@
cmd.cmd_data_out = &board_v;
cmd.cmd_dev_index = 0;
- if (google_chromeec_command(&cmd))
+ if (google_chromeec_command(&cmd) < 0)
return -1;
*version = board_v.board_version;
@@ -677,7 +677,7 @@
cmd.cmd_data_out = &sku_v;
cmd.cmd_dev_index = 0;
- if (google_chromeec_command(&cmd) != 0)
+ if (google_chromeec_command(&cmd) < 0)
return 0;
return sku_v.sku_id;
@@ -708,7 +708,7 @@
if (!is_read)
memcpy(&cmd_vbnvcontext.block, data, EC_VBNV_BLOCK_SIZE);
- if (google_chromeec_command(&cec_cmd)) {
+ if (google_chromeec_command(&cec_cmd) < 0) {
printk(BIOS_ERR, "ERROR: failed to %s vbnv_ec context: %d\n",
is_read ? "read" : "write", (int)cec_cmd.cmd_code);
mdelay(10); /* just in case */
@@ -792,7 +792,7 @@
cmd.cmd_size_out = sizeof(*r) + read_len;
cmd.cmd_dev_index = 0;
rv = google_chromeec_command(&cmd);
- if (rv != 0)
+ if (rv < 0)
return rv;
/* Parse response */
@@ -875,7 +875,7 @@
};
struct usb_chg_measures m;
int rv = google_chromeec_command(&cmd);
- if (rv != 0)
+ if (rv < 0)
return rv;
/* values are given in milliAmps and milliVolts */
*type = rsp.type;
diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h
index 7a38336..51124f6 100644
--- a/src/ec/google/chromeec/ec.h
+++ b/src/ec/google/chromeec/ec.h
@@ -108,7 +108,7 @@
*
* @param type charger type
* @param max_watts charger max wattage
- * @return non-zero for error, otherwise 0.
+ * @return 0 on success or negative integer for errors.
*/
int google_chromeec_get_usb_pd_power_info(enum usb_chg_type *type,
u32 *max_watts);
@@ -118,7 +118,7 @@
*
* @param current_lim Max current in mA
* @param voltage_lim Max voltage in mV
- * @return non-zero for error, otherwise 0.
+ * @return 0 on success or negative integer for errors.
*/
int google_chromeec_override_dedicated_charger_limit(u16 current_lim,
u16 voltage_lim);
@@ -150,6 +150,8 @@
* The lower level transport works on the buffers handed out to the
* upper level. Therefore, only the size of the request and response
* are required.
+ *
+ * @return 0 on success or negative integer for errors.
*/
typedef int (*crosec_io_t)(size_t req_size, size_t resp_size, void *context);
int crosec_command_proto(struct chromeec_command *cec_command,
@@ -159,7 +161,7 @@
* Send a command to a CrOS EC
*
* @param cec_command: CrOS EC command to send
- * @return 0 for success. Non-zero for error.
+ * @return 0 on success or negative integer for errors.
*/
int google_chromeec_command(struct chromeec_command *cec_command);
diff --git a/src/ec/google/chromeec/ec_i2c.c b/src/ec/google/chromeec/ec_i2c.c
index 22b491a..7f2ead5 100644
--- a/src/ec/google/chromeec/ec_i2c.c
+++ b/src/ec/google/chromeec/ec_i2c.c
@@ -205,7 +205,7 @@
__func__, cec_command->cmd_size_in,
cec_command->cmd_size_out);
cec_command->cmd_code = EC_RES_INVALID_PARAM;
- return 1;
+ return -1;
}
/* Construct command. */
@@ -221,13 +221,13 @@
printk(BIOS_ERR, "%s: Cannot complete write to i2c-%d:%#x\n",
__func__, bus, chip);
cec_command->cmd_code = EC_RES_ERROR;
- return 1;
+ return -1;
}
if (i2c_read_raw(bus, chip, (uint8_t *)&resp, size_i2c_resp) != 0) {
printk(BIOS_ERR, "%s: Cannot complete read from i2c-%d:%#x\n",
__func__, bus, chip);
cec_command->cmd_code = EC_RES_ERROR;
- return 1;
+ return -1;
}
/* Verify and return response */
@@ -235,17 +235,17 @@
if (resp.response != EC_RES_SUCCESS) {
printk(BIOS_DEBUG, "%s: Received bad result code %d\n",
__func__, (int)resp.response);
- return 1;
+ return -1;
}
if (resp.length > cec_command->cmd_size_out) {
printk(BIOS_ERR, "%s: Received len %#02x too large\n",
__func__, (int)resp.length);
cec_command->cmd_code = EC_RES_INVALID_RESPONSE;
- return 1;
+ return -1;
}
if (!ec_verify_checksum(&resp)) {
cec_command->cmd_code = EC_RES_INVALID_CHECKSUM;
- return 1;
+ return -1;
}
cec_command->cmd_size_out = resp.length;
memcpy(cec_command->cmd_data_out, resp.data, resp.length);
diff --git a/src/ec/google/chromeec/ec_lpc.c b/src/ec/google/chromeec/ec_lpc.c
index 61005d3..097b1b4 100644
--- a/src/ec/google/chromeec/ec_lpc.c
+++ b/src/ec/google/chromeec/ec_lpc.c
@@ -330,13 +330,13 @@
if (google_chromeec_wait_ready(EC_LPC_ADDR_HOST_CMD)) {
printk(BIOS_ERR, "Timeout waiting for EC process command %d!\n",
cec_command->cmd_code);
- return 1;
+ return -1;
}
/* Check result */
cec_command->cmd_code = read_byte(EC_LPC_ADDR_HOST_DATA);
if (cec_command->cmd_code)
- return 1;
+ return -1;
/* Read back args */
read_bytes(EC_LPC_ADDR_HOST_ARGS, sizeof(args), (u8*)&args, NULL);
@@ -348,12 +348,12 @@
*/
if (!(args.flags & EC_HOST_ARGS_FLAG_TO_HOST)) {
printk(BIOS_ERR, "EC protocol mismatch\n");
- return 1;
+ return -1;
}
if (args.data_size > cec_command->cmd_size_out) {
printk(BIOS_ERR, "EC returned too much data\n");
- return 1;
+ return -1;
}
cec_command->cmd_size_out = args.data_size;
@@ -369,7 +369,7 @@
/* Verify checksum */
if (args.checksum != csum) {
printk(BIOS_ERR, "EC response has invalid checksum\n");
- return 1;
+ return -1;
}
return 0;
diff --git a/src/ec/google/chromeec/smihandler.c b/src/ec/google/chromeec/smihandler.c
index cab7192..3f703f9 100644
--- a/src/ec/google/chromeec/smihandler.c
+++ b/src/ec/google/chromeec/smihandler.c
@@ -54,7 +54,7 @@
;
printk(BIOS_DEBUG,"Clearing pending EC events. Error code 1 is expected.\n");
- while (google_chromeec_get_mkbp_event(&mkbp_event) == 0)
+ while (google_chromeec_get_mkbp_event(&mkbp_event) >= 0)
;
}
diff --git a/src/ec/google/chromeec/vboot_storage.c b/src/ec/google/chromeec/vboot_storage.c
index f47c2f1..08af2f6 100644
--- a/src/ec/google/chromeec/vboot_storage.c
+++ b/src/ec/google/chromeec/vboot_storage.c
@@ -30,7 +30,7 @@
/* Ensure the digests being saved match the EC's slot size. */
assert(digest_size == EC_VSTORE_SLOT_SIZE);
- if (google_chromeec_vstore_write(slot, digest, digest_size))
+ if (google_chromeec_vstore_write(slot, digest, digest_size) < 0)
return -1;
/* Assert the slot is locked on successful write. */
diff --git a/src/ec/google/chromeec/vstore.c b/src/ec/google/chromeec/vstore.c
index 28c2603..39e59f8 100644
--- a/src/ec/google/chromeec/vstore.c
+++ b/src/ec/google/chromeec/vstore.c
@@ -42,7 +42,7 @@
.cmd_data_out = &info,
};
- if (google_chromeec_command(&cmd) != 0)
+ if (google_chromeec_command(&cmd) < 0)
return 0;
if (locked)
diff --git a/src/mainboard/google/gru/mainboard.c b/src/mainboard/google/gru/mainboard.c
index 41307c7..245a70e 100644
--- a/src/mainboard/google/gru/mainboard.c
+++ b/src/mainboard/google/gru/mainboard.c
@@ -257,12 +257,14 @@
static void usb_power_cycle(int port)
{
- if (google_chromeec_set_usb_pd_role(port, USB_PD_CTRL_ROLE_FORCE_SINK))
+ if (google_chromeec_set_usb_pd_role(port, USB_PD_CTRL_ROLE_FORCE_SINK)
+ < 0)
printk(BIOS_ERR, "ERROR: Cannot force USB%d PD sink\n", port);
mdelay(10); /* Make sure USB stick is fully depowered. */
- if (google_chromeec_set_usb_pd_role(port, USB_PD_CTRL_ROLE_TOGGLE_ON))
+ if (google_chromeec_set_usb_pd_role(port, USB_PD_CTRL_ROLE_TOGGLE_ON)
+ < 0)
printk(BIOS_ERR, "ERROR: Cannot restore USB%d PD mode\n", port);
}
diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c
index 00bbae6..c379463 100644
--- a/src/security/vboot/vboot_logic.c
+++ b/src/security/vboot/vboot_logic.c
@@ -141,7 +141,7 @@
printk(BIOS_DEBUG, "Platform is resuming.\n");
- if (vboot_retrieve_hash(saved_hash, saved_hash_sz)) {
+ if (vboot_retrieve_hash(saved_hash, saved_hash_sz) < 0) {
printk(BIOS_ERR, "Couldn't retrieve saved hash.\n");
return -1;
}
--
To view, visit https://review.coreboot.org/c/coreboot/+/31626
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I39f12502bc6982670dd200dcef0724e7eed2ed29
Gerrit-Change-Number: 31626
Gerrit-PatchSet: 1
Gerrit-Owner: YH Lin <yueherngl(a)google.com>
Gerrit-MessageType: newchange
3 weeks, 3 days
- 3
- 7
Change in ...coreboot[master]: SeaBIOS - unofficial patches: advanced_bootmenu and multiple_floppies
by mikeb mikeb (Code Review)
Hello Mike Banon,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/32351
to review the following change.
Change subject: SeaBIOS - unofficial patches: advanced_bootmenu and multiple_floppies
......................................................................
SeaBIOS - unofficial patches: advanced_bootmenu and multiple_floppies
If you'd like to add the useful floppies to your coreboot (read about them at
http://dangerousprototypes.com/docs/Lenovo_G505S_hacking#Useful_floppies ), or
to use your USB numpad for choosing a SeaBIOS boot entry, then this change is
for you! It contains two valuable patches together with a Makefile mod needed to
automatically apply these patches to a cloned SeaBIOS before its' compilation.
advanced_bootmenu: up to 35 entries (2 pages if >18), numpad support (console)
https://mail.coreboot.org/hyperkitty/list/seabios@seabios.org/thread/CKWLNT…
[PATCH v2] ramdisk: search for all available floppy images instead of one
https://mail.coreboot.org/pipermail/seabios/2018-December/012670.html
Patch descriptions are available at these links, and just in case here's a copy:
advanced_bootmenu: up to 35 entries (2 pages if >18), numpad support (console)
Add support for up to 35 boot menu entries (2 pages if >18). To solve the
">10" problem currently experienced by SeaBIOS users (there are no 11, 12, etc.
keys on a keyboard - so impossible to choose the last menu entries if you got
>10 entries because of multiple hard drives / secondary payloads / floppies)
- the boot menu has been extended to the letter keys. NOTE: TPM menu has been
moved from T to M letter: it is at the end of keyboard's 3rd row of letters and
"Trusted" is adjective while "Module" is a noun; alternatively could press '-'.
Also, add support for a numpad. Small USB numpad could be really convenient for
choosing the boot entries at coreboot boards used as (maybe headless) servers.
'/' char on numpad could be used to open the boot menu or to exit it. If there
are >10 boot menu entries - the numpad console interface will be enabled: press
one or two digit keys and then ENTER to confirm your choice, or remove a digit
by pressing the '.Del' key. Also you could call TPM with '-' key at any moment,
or boot with a single key press of your fullsize keyboard.
[PATCH v2] ramdisk: search for all available floppy images instead of one
All the floppy images available at CBFS will be found and listed in a boot menu,
instead of the first found. Could be highly valuable if you are participating in
a hobby OS development - would like to test multiple versions of your floppy at
the same coreboot image, to reduce the amount of re-flashes and accelerate the
development at bare metal - or simply you would like to access multiple floppies
as a coreboot user. For example: KolibriOS (nice assembly OS with GUI and apps),
FreeDOS, MichalOS, Snowdrop and memtest (coreboot's memtest version is buggy,
e.g. external USB keyboard isn't working at some laptops; floppy is much better)
Signed-off-by: Mike Banon <mikebdp2(a)gmail.com>
Change-Id: Idf4efba31091a8678b51c2f6541d440c5cc6d37d
---
M payloads/external/SeaBIOS/Makefile
A payloads/external/SeaBIOS/advanced_bootmenu.patch
A payloads/external/SeaBIOS/multiple_floppies.patch
3 files changed, 551 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/32351/1
diff --git a/payloads/external/SeaBIOS/Makefile b/payloads/external/SeaBIOS/Makefile
index e505c8c..ae58c8c 100644
--- a/payloads/external/SeaBIOS/Makefile
+++ b/payloads/external/SeaBIOS/Makefile
@@ -76,7 +76,18 @@
# echo "# CONFIG_SMBIOS is not set" >> seabios/.config
$(MAKE) -C seabios olddefconfig OUT=out/
-build: config
+patch:
+ if [ -d seabios ]; then \
+ cd seabios; \
+ if [ ! -f .patched ]; then \
+ echo " PATCH SeaBIOS $(TAG-y)"; \
+ patch -p1 < ./../advanced_bootmenu.patch; \
+ patch -p1 < ./../multiple_floppies.patch; \
+ touch .patched; \
+ fi; \
+ fi
+
+build: config patch
echo " MAKE SeaBIOS $(TAG-y)"
$(MAKE) -C seabios OUT=out/
diff --git a/payloads/external/SeaBIOS/advanced_bootmenu.patch b/payloads/external/SeaBIOS/advanced_bootmenu.patch
new file mode 100644
index 0000000..c914588
--- /dev/null
+++ b/payloads/external/SeaBIOS/advanced_bootmenu.patch
@@ -0,0 +1,332 @@
+diff --git a/src/boot.c b/src/boot.c
+index 9f82f3c..f94dd27 100644
+--- a/src/boot.c
++++ b/src/boot.c
+@@ -463,6 +463,7 @@ get_keystroke(int msec)
+ * Boot menu and BCV execution
+ ****************************************************************/
+
++#define BOOTMENU_PAGE_SIZE 18
+ #define DEFAULT_BOOTMENU_WAIT 2500
+
+ // Show IPL option menu.
+@@ -478,59 +479,282 @@ interactive_bootmenu(void)
+ ;
+
+ char *bootmsg = romfile_loadfile("etc/boot-menu-message", NULL);
+- int menukey = romfile_loadint("etc/boot-menu-key", 1);
+- printf("%s", bootmsg ?: "\nPress ESC for boot menu.\n\n");
++ int menukey = romfile_loadint("etc/boot-menu-key", 1); // custom menukey
++ printf("%s", bootmsg ?: "\nPress ESC or \\ / slash for boot menu.\n\n");
+ free(bootmsg);
+
+ u32 menutime = romfile_loadint("etc/boot-menu-wait", DEFAULT_BOOTMENU_WAIT);
+ enable_bootsplash();
+ int scan_code = get_keystroke(menutime);
+ disable_bootsplash();
+- if (scan_code != menukey)
++ if (scan_code != menukey && // custom menukey
++ scan_code != 1 && // ESC
++ scan_code != 43 && // '\' char on keyboard
++ scan_code != 53 && // '/' char on keyboard
++ scan_code != 98) { // '/' char on numpad
++ if (scan_code == -1)
++ printf("No key pressed.\n");
++ else
++ printf("Not a menukey pressed.\n");
+ return;
++ }
+
+ while (get_keystroke(0) >= 0)
+ ;
+
+- printf("Select boot device:\n\n");
+ wait_threads();
+
+- // Show menu items
++ char keyboard_keys[35] = {'1','2','3','4','5','6','7','8','9','0',
++ 'q','w','e','r','t','y','u','i','o','p',
++ 'a','s','d','f','g','h','j','k','l',
++ 'z','x','c','v','b','n'}; /* m = TPM */
++ int numpad_scancodes[10] = { 82, 79, 80, 81, 75, 76, 77, 71, 72, 73 };
++ int numpi = 0; // Key index: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9.
++ int digits = 0; // Numerical length of a current choice number.
++ int decode = 0; // Decode the current choice number into a letter?
++ int entry_id = 0;
++ char desc[77];
++
++ printf("Select boot device");
++
++ // Show menu items after counting them and determining a number of pages.
++ // Only 35 boot menu items (36 if to count a TPM) are supported currently.
++
+ int maxmenu = 0;
+ struct bootentry_s *pos;
+- hlist_for_each_entry(pos, &BootList, node) {
+- char desc[77];
++ hlist_for_each_entry(pos, &BootList, node)
+ maxmenu++;
+- printf("%d. %s\n", maxmenu
++
++ if (maxmenu > 10) {
++ if (maxmenu > 35)
++ maxmenu = 35;
++ if (maxmenu > BOOTMENU_PAGE_SIZE)
++ printf(" - page 1 :");
++ else
++ printf(": ");
++ printf(" // press ENTER after your numpad input");
++ if (maxmenu > BOOTMENU_PAGE_SIZE)
++ printf(" - if any -\n "
++ " // - or to switch between the pages...\n");
++ else
++ printf(" (if any)\n\n");
++ } else {
++ printf(":\n\n");
++ }
++
++ hlist_for_each_entry(pos, &BootList, node) {
++ if (entry_id == BOOTMENU_PAGE_SIZE) // Show only the first page.
++ break;
++ printf("%c. %s\n", keyboard_keys[entry_id]
+ , strtcpy(desc, pos->description, ARRAY_SIZE(desc)));
++ entry_id++;
+ }
++ int tpm_cshm = 0;
+ if (tpm_can_show_menu()) {
+- printf("\nt. TPM Configuration\n");
++ tpm_cshm = 1;
++ printf("\nm-. TPM Configuration");
+ }
+-
+- // Get key press. If the menu key is ESC, do not restart boot unless
+- // 1.5 seconds have passed. Otherwise users (trained by years of
+- // repeatedly hitting keys to enter the BIOS) will end up hitting ESC
+- // multiple times and immediately booting the primary boot device.
+- int esc_accepted_time = irqtimer_calc(menukey == 1 ? 1500 : 0);
++ printf("\n> ");
++
++ // Do not restart boot on menukey press, unless DEFAULT_BOOTMENU_WAIT msecs
++ // have passed. Otherwise users (trained by years of repeatedly hitting keys
++ // to enter the BIOS) will end up hitting menukey multiple times and
++ // immediately booting the primary boot device.
++ int esc_accepted_time = irqtimer_calc(DEFAULT_BOOTMENU_WAIT);
++ int choice = 0, kb_choice = 0;
++ int page_num = 1;
++ int enter = 0;
++ int backspace = 0;
++ int tpm_show_menu = 0;
+ for (;;) {
+ scan_code = get_keystroke(1000);
+- if (scan_code == 1 && !irqtimer_check(esc_accepted_time))
+- continue;
+- if (tpm_can_show_menu() && scan_code == 20 /* t */) {
++ if (scan_code == menukey || // custom menukey
++ scan_code == 1 || // ESC
++ scan_code == 43 || // '\' char on keyboard
++ scan_code == 53 || // '/' char on keyboard
++ scan_code == 98) { // '/' char on numpad
++ if (!irqtimer_check(esc_accepted_time))
++ continue;
++ if (digits == 2) // Remove the decoded "(*)"
++ printf(" \b\b\b");
++ /* Remove the existing input before printing a message. */
++ for (; digits > 0; digits--)
++ printf("\b \b");
++ printf("Menukey pressed.\n");
++ return;
++ }
++ kb_choice = 0;
++ /* 4 rows of keyboard_keys: 1 row with numbers, 3 rows with letters.
++ Use any of them to select a boot device (except the TPM 'm-' keys) */
++ // 1st range: 1-9 and 0 (10) keys <==> 2-11 scan codes <==> 1-10 choice
++ if (scan_code >= 2 && scan_code <= 11) kb_choice = scan_code - 1;
++ // 2nd range: Q-P row of letters <==> 16-25 scan codes <==> 11-20 choice
++ if (scan_code >= 16 && scan_code <= 25) kb_choice = scan_code - 5;
++ // 3rd range: A-L row of letters <==> 30-38 scan codes <==> 21-29 choice
++ if (scan_code >= 30 && scan_code <= 38) kb_choice = scan_code - 9;
++ // 4th range: Z-N row of letters <==> 44-49 scan codes <==> 30-35 choice
++ if (scan_code >= 44 && scan_code <= 49) kb_choice = scan_code - 14;
++ // ENTER: (28) on keyboard, (96) on numpad.
++ if (scan_code == 28 || scan_code == 96)
++ enter = 1;
++ // BCKSPC: '<-'(14) and 'Delete'(111) on keyboard, '.Del'(83) on numpad.
++ if (scan_code == 14 || scan_code == 111 || scan_code == 83)
++ backspace = 1;
++ // TPM keys: 'm'(50) and '-'(12) chars on keyboard, '-'(74) on numpad.
++ if ((scan_code == 50 || scan_code == 12 || scan_code == 74) && tpm_cshm)
++ tpm_show_menu = 1;
++
++ if (kb_choice != 0 || tpm_show_menu) {
++ if (kb_choice > maxmenu) {
++ if (!tpm_show_menu)
++ continue;
++ } else {
++ choice = kb_choice;
++ }
++ if (digits == 2) // Remove the decoded "(*)"
++ printf(" \b\b\b");
++ /* Remove the existing input before printing a choice. */
++ for (; digits > 0; digits--)
++ printf("\b \b");
++ if (!tpm_show_menu) {
++ // Choice is any of the detected boot devices ==> lets boot!
++ break;
++ }
++ } else {
++ // Internal/USB Numpad console interface.
++ if (digits < 9) {
++ for (numpi = 0; numpi < 10; numpi++) {
++ if (scan_code == numpad_scancodes[numpi]) {
++ if (maxmenu <= 10) { // Console interface is not needed.
++ if ((numpi != 0 && numpi <= maxmenu) ||
++ (numpi == 0 && 10 <= maxmenu)) { // 10(0)
++ choice = numpi;
++ enter = 1; // Fake ENTER to boot this entry now.
++ } else { // If no such an entry, don't try to boot.
++ break;
++ }
++ } else {
++ if (digits == 2) {
++ printf(" \b\b\b"); // Remove the decoded "(*)"
++ if (choice == 0) {
++ printf("\b\b \b\b"); // Remove "10".
++ digits = 0;
++ }
++ }
++ choice = 10 * choice + numpi;
++ }
++ if (choice > 0) {
++ printf("%d", numpi); // Print the entered digit.
++ digits++;
++ } else {
++ if (10 <= maxmenu)
++ printf("10(0)\b\b\b");
++ else
++ printf("10(?)\b\b\b");
++ digits = 2;
++ }
++ if (choice > 9 && digits == 2) // Decode into a letter.
++ decode = 1;
++ break;
++ }
++ }
++ }
++ if (backspace && digits > 0) {
++ backspace = 0;
++ choice = choice / 10;
++ if (digits == 2) {
++ printf(" \b\b\b"); // Remove the decoded "(*)"
++ // 0 turned into 10: one more Backspace is needed to remove.
++ if (choice == 0) {
++ printf("\b \b");
++ digits--;
++ }
++ }
++ printf("\b \b"); // Remove the last entered digit.
++ digits--;
++ if (choice > 9 && digits == 2) // Decode into a letter.
++ decode = 1;
++ }
++ if (decode) { // Decode the current choice number into a letter.
++ decode = 0;
++ if (choice <= maxmenu) {
++ printf("(%c)", keyboard_keys[choice-1]);
++ } else {
++ if (tpm_cshm && choice == 36)
++ printf("(m)"); // For TPM.
++ else
++ printf("(?)"); // No matching letter found.
++ }
++ printf("\b\b\b"); // Move a cursor before the "(*)"
++ }
++ }
++
++ if (enter) {
++ enter = 0;
++ if (choice == 0) {
++ if (digits == 2) { // for 0 that turned into 10
++ if (10 <= maxmenu)
++ break;
++ else
++ continue;
++ }
++ // If there are two pages - switch between them.
++ if (maxmenu > BOOTMENU_PAGE_SIZE) {
++ entry_id = 0;
++ page_num = 3 - page_num; // 3 - 1 = 2; 3 - 2 = 1.
++ printf("\n\nSelect boot device - page %d :"
++ " // press ENTER after your numpad input"
++ " - if any -\n "
++ " // - or to switch between the pages...\n",
++ page_num);
++ hlist_for_each_entry(pos, &BootList, node) {
++ if ((page_num == 1 && entry_id == BOOTMENU_PAGE_SIZE) ||
++ (page_num == 2 && entry_id == 35))
++ break;
++ if (page_num == 1 || entry_id >= BOOTMENU_PAGE_SIZE)
++ printf("%c. %s\n", keyboard_keys[entry_id],
++ strtcpy(desc, pos->description, ARRAY_SIZE(desc)));
++ entry_id++;
++ }
++ if (tpm_cshm)
++ printf("\nm-. TPM Configuration");
++ printf("\n> ");
++ }
++ } else {
++ if (choice > maxmenu) {
++ if (tpm_cshm && choice == 36)
++ tpm_show_menu = 1;
++ } else {
++ // Choice is any of the detected boot devices ==> lets boot!
++ break;
++ }
++ }
++ }
++
++ if (tpm_show_menu) {
++ tpm_show_menu = 0;
++ choice = 0;
++ if (digits == 0)
++ printf("TPM key pressed.");
++ else
++ digits = 0;
+ printf("\n");
+ tpm_menu();
++ printf("> ");
+ }
+- if (scan_code >= 1 && scan_code <= maxmenu+1)
+- break;
++ }
++
++ if (choice == 0) // 10(0)
++ choice = 10;
++
++ if (digits == 0 && choice < 36) {
++ printf("%c", keyboard_keys[choice-1]);
++ if (choice > 9) // Decode into a number.
++ printf("(%d)", choice);
+ }
+ printf("\n");
+- if (scan_code == 0x01)
+- // ESC
+- return;
+
+ // Find entry and make top priority.
+- int choice = scan_code - 1;
+ hlist_for_each_entry(pos, &BootList, node) {
+ if (! --choice)
+ break;
+diff --git a/src/config.h b/src/config.h
+index 93c8dbc..f85cc14 100644
+--- a/src/config.h
++++ b/src/config.h
+@@ -19,7 +19,7 @@
+ // Space to reserve in high-memory for tables
+ #define BUILD_MAX_HIGHTABLE (256*1024)
+ // Largest supported externaly facing drive id
+-#define BUILD_MAX_EXTDRIVE 16
++#define BUILD_MAX_EXTDRIVE 36
+ // Number of bytes the smbios may be and still live in the f-segment
+ #define BUILD_MAX_SMBIOS_FSEG 600
+ // Maximum number of bytes the mptable may be and still be copied to f-segment
diff --git a/payloads/external/SeaBIOS/multiple_floppies.patch b/payloads/external/SeaBIOS/multiple_floppies.patch
new file mode 100644
index 0000000..5249394
--- /dev/null
+++ b/payloads/external/SeaBIOS/multiple_floppies.patch
@@ -0,0 +1,207 @@
+diff --git a/src/block.h b/src/block.h
+index f64e880..aaa236f 100644
+--- a/src/block.h
++++ b/src/block.h
+@@ -2,7 +2,7 @@
+ #define __BLOCK_H
+
+ #include "types.h" // u32
+-
++#include "romfile.h" // struct romfile_s
+
+ /****************************************************************
+ * Disk command request
+@@ -48,6 +48,7 @@ struct drive_s {
+ struct drive_s {
+ u8 type; // Driver type (DTYPE_*)
+ u8 floppy_type; // Type of floppy (only for floppy drives).
++ struct romfile_s *floppy_file; // Floppy file (only for virtual floppies).
+ struct chs_s lchs; // Logical CHS
+ u64 sectors; // Total sectors count
+ u32 cntl_id; // Unique id for a given driver type.
+diff --git a/src/boot.c b/src/boot.c
+index 9f82f3c..79f1e7d 100644
+--- a/src/boot.c
++++ b/src/boot.c
+@@ -584,7 +584,7 @@ bcv_prepboot(void)
+ break;
+ case IPL_TYPE_FLOPPY:
+ map_floppy_drive(pos->drive);
+- add_bev(IPL_TYPE_FLOPPY, 0);
++ add_bev(IPL_TYPE_FLOPPY, (u32)pos->drive);
+ break;
+ case IPL_TYPE_HARDDISK:
+ map_hd_drive(pos->drive);
+@@ -733,6 +733,12 @@ do_boot(int seq_nr)
+ static void
+ do_boot(int seq_nr)
+ {
++
++ int ret;
++ void *pos;
++ struct romfile_s *file;
++ struct drive_s *drive;
++
+ if (! CONFIG_BOOT)
+ panic("Boot support not compiled in.\n");
+
+@@ -744,6 +750,16 @@ do_boot(int seq_nr)
+ switch (ie->type) {
+ case IPL_TYPE_FLOPPY:
+ printf("Booting from Floppy...\n");
++ drive = (struct drive_s *)ie->vector;
++ file = drive->floppy_file;
++ // File is NULL if a floppy is physical.
++ if (file) {
++ // Copy virtual floppy image into ram.
++ pos = (void *)drive->cntl_id;
++ ret = file->copy(file, pos, file->size);
++ if (ret < 0)
++ break;
++ }
+ boot_disk(0x00, CheckFloppySig);
+ break;
+ case IPL_TYPE_HARDDISK:
+diff --git a/src/hw/floppy.c b/src/hw/floppy.c
+index 9e6647d..5b37c6c 100644
+--- a/src/hw/floppy.c
++++ b/src/hw/floppy.c
+@@ -107,7 +107,7 @@ struct floppyinfo_s FloppyInfo[] VARFSEG = {
+ };
+
+ struct drive_s *
+-init_floppy(int floppyid, int ftype)
++init_floppy(int floppyid, int ftype, struct romfile_s *ffile)
+ {
+ if (ftype <= 0 || ftype >= ARRAY_SIZE(FloppyInfo)) {
+ dprintf(1, "Bad floppy type %d\n", ftype);
+@@ -124,6 +124,7 @@ init_floppy(int floppyid, int ftype)
+ drive->type = DTYPE_FLOPPY;
+ drive->blksize = DISK_SECTOR_SIZE;
+ drive->floppy_type = ftype;
++ drive->floppy_file = ffile;
+ drive->sectors = (u64)-1;
+
+ memcpy(&drive->lchs, &FloppyInfo[ftype].chs
+@@ -134,7 +135,7 @@ addFloppy(int floppyid, int ftype)
+ static void
+ addFloppy(int floppyid, int ftype)
+ {
+- struct drive_s *drive = init_floppy(floppyid, ftype);
++ struct drive_s *drive = init_floppy(floppyid, ftype, 0);
+ if (!drive)
+ return;
+ char *desc = znprintf(MAXDESCSIZE, "Floppy [drive %c]", 'A' + floppyid);
+diff --git a/src/hw/ramdisk.c b/src/hw/ramdisk.c
+index b9e9baa..a679385 100644
+--- a/src/hw/ramdisk.c
++++ b/src/hw/ramdisk.c
+@@ -23,40 +23,69 @@ ramdisk_setup(void)
+ if (!CONFIG_FLASH_FLOPPY)
+ return;
+
+- // Find image.
+- struct romfile_s *file = romfile_findprefix("floppyimg/", NULL);
+- if (!file)
+- return;
+- const char *filename = file->name;
+- u32 size = file->size;
+- dprintf(3, "Found floppy file %s of size %d\n", filename, size);
+- int ftype = find_floppy_type(size);
+- if (ftype < 0) {
+- dprintf(3, "No floppy type found for ramdisk size\n");
++ struct romfile_s *file = NULL;
++ char *filename, *desc;
++ u32 size, max_size = 0;
++ int ftype;
++ void *pos;
++ struct drive_s *drive;
++
++ // Find the max floppy size
++ for (;;) {
++ // Find the next image.
++ file = romfile_findprefix("floppyimg/", file);
++ if (!file)
++ break;
++ filename = file->name;
++ size = file->size;
++ dprintf(3, "Found floppy file %s of size %d\n", filename, size);
++ // Check if this size is valid.
++ ftype = find_floppy_type(size);
++ if (ftype < 0) {
++ dprintf(3, "No floppy type found for ramdisk size\n");
++ } else {
++ if (size > max_size)
++ max_size = size;
++ }
++ }
++ if (max_size == 0) {
++ dprintf(3, "No floppies found\n");
+ return;
+ }
+
+ // Allocate ram for image.
+- void *pos = memalign_tmphigh(PAGE_SIZE, size);
++ pos = memalign_tmphigh(PAGE_SIZE, max_size);
+ if (!pos) {
+ warn_noalloc();
+ return;
+ }
+- e820_add((u32)pos, size, E820_RESERVED);
++ e820_add((u32)pos, max_size, E820_RESERVED);
++ dprintf(3, "Allocate %u bytes for a floppy\n", max_size);
+
+- // Copy image into ram.
+- int ret = file->copy(file, pos, size);
+- if (ret < 0)
+- return;
+-
+- // Setup driver.
+- struct drive_s *drive = init_floppy((u32)pos, ftype);
+- if (!drive)
+- return;
+- drive->type = DTYPE_RAMDISK;
+- dprintf(1, "Mapping floppy %s to addr %p\n", filename, pos);
+- char *desc = znprintf(MAXDESCSIZE, "Ramdisk [%s]", &filename[10]);
+- boot_add_floppy(drive, desc, bootprio_find_named_rom(filename, 0));
++ // Setup the floppy drivers.
++ file = NULL;
++ for (;;) {
++ // Find the next image.
++ file = romfile_findprefix("floppyimg/", file);
++ if (!file)
++ return;
++ filename = file->name;
++ size = file->size;
++ dprintf(3, "Found floppy file %s of size %d\n", filename, size);
++ ftype = find_floppy_type(size);
++ if (ftype < 0) {
++ dprintf(3, "No floppy type found for ramdisk size\n");
++ } else {
++ // Setup driver.
++ drive = init_floppy((u32)pos, ftype, file);
++ if (!drive)
++ return;
++ drive->type = DTYPE_RAMDISK;
++ dprintf(1, "Mapping floppy %s to addr %p\n", filename, pos);
++ desc = znprintf(MAXDESCSIZE, "Ramdisk [%s]", &filename[10]);
++ boot_add_floppy(drive, desc, bootprio_find_named_rom(filename, 0));
++ }
++ }
+ }
+
+ static int
+diff --git a/src/util.h b/src/util.h
+index 9c06850..ce3a26d 100644
+--- a/src/util.h
++++ b/src/util.h
+@@ -147,7 +147,8 @@ void dma_setup(void);
+ // hw/floppy.c
+ extern struct floppy_ext_dbt_s diskette_param_table2;
+ void floppy_setup(void);
+-struct drive_s *init_floppy(int floppyid, int ftype);
++extern struct romfile_s *ffile;
++struct drive_s *init_floppy(int floppyid, int ftype, struct romfile_s *ffile);
+ int find_floppy_type(u32 size);
+ int floppy_process_op(struct disk_op_s *op);
+ void floppy_tick(void);
--
To view, visit https://review.coreboot.org/c/coreboot/+/32351
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Idf4efba31091a8678b51c2f6541d440c5cc6d37d
Gerrit-Change-Number: 32351
Gerrit-PatchSet: 1
Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com>
Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com>
Gerrit-MessageType: newchange
3 weeks, 6 days
- 3
- 12
Change in ...coreboot[master]: autoport: Add support for Haswell-LynxPoint platform
by Iru Cai (vimacs) (Code Review)
Hello Iru Cai,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/30890
to review the following change.
Change subject: autoport: Add support for Haswell-LynxPoint platform
......................................................................
autoport: Add support for Haswell-LynxPoint platform
It can now generate a buildable source for Clevo W650SZ.
TODO:
- Support Lynx Point LP (GPIO registers differ from non-LP)
- Use PCH HD-Audio in azilia instead of the CPU/Northbridge HD-Audio
Change-Id: I4f6e8c97b5122101de2f36bba8ba9f8ddd5b813a
Signed-off-by: Iru Cai <mytbk920423(a)gmail.com>
---
M util/autoport/azalia.go
A util/autoport/haswell.go
A util/autoport/lynxpoint.go
M util/autoport/main.go
4 files changed, 625 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/30890/1
diff --git a/util/autoport/azalia.go b/util/autoport/azalia.go
index c525189..3090dd0 100644
--- a/util/autoport/azalia.go
+++ b/util/autoport/azalia.go
@@ -62,4 +62,9 @@
RegisterPCI(0x8086, 0x1c20, azalia{})
/* C216/ivybridge */
RegisterPCI(0x8086, 0x1e20, azalia{})
+ /* Haswell */
+ RegisterPCI(0x8086, 0x0c0c, azalia{})
+ /* Lynx Point */
+ RegisterPCI(0x8086, 0x8c20, azalia{})
+ RegisterPCI(0x8086, 0x9c20, azalia{})
}
diff --git a/util/autoport/haswell.go b/util/autoport/haswell.go
new file mode 100644
index 0000000..d3c9d9f
--- /dev/null
+++ b/util/autoport/haswell.go
@@ -0,0 +1,119 @@
+package main
+
+type haswellmc struct {
+ variant string
+}
+
+func (i haswellmc) Scan(ctx Context, addr PCIDevData) {
+ inteltool := ctx.InfoSource.GetInteltool()
+
+ /* FIXME:XX Move this somewhere else. */
+ MainboardIncludes = append(MainboardIncludes, "drivers/intel/gma/int15.h")
+ MainboardEnable += (` /* FIXME: fix those values*/
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+`)
+
+ DevTree = DevTreeNode{
+ Chip: "northbridge/intel/haswell",
+ MissingParent: "northbridge",
+ Comment: "FIXME: check gfx.ndid and gfx.did",
+ Registers: map[string]string{
+ "gpu_dp_b_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 2) & 7),
+ "gpu_dp_c_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 10) & 7),
+ "gpu_dp_d_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 18) & 7),
+ "gpu_panel_port_select": FormatInt32((inteltool.IGD[0xc7208] >> 30) & 3),
+ "gpu_panel_power_up_delay": FormatInt32((inteltool.IGD[0xc7208] >> 16) & 0x1fff),
+ "gpu_panel_power_backlight_on_delay": FormatInt32(inteltool.IGD[0xc7208] & 0x1fff),
+ "gpu_panel_power_down_delay": FormatInt32((inteltool.IGD[0xc720c] >> 16) & 0x1fff),
+ "gpu_panel_power_backlight_off_delay": FormatInt32(inteltool.IGD[0xc720c] & 0x1fff),
+ "gpu_panel_power_cycle_delay": FormatInt32(inteltool.IGD[0xc7210] & 0xff),
+ "gpu_cpu_backlight": FormatHex32(inteltool.IGD[0x48254]),
+ "gpu_pch_backlight": FormatHex32((inteltool.IGD[0xc8254] >> 16) * 0x10001),
+ "gpu_ddi_e_connected": FormatBool(((inteltool.IGD[0x64000] >> 4) & 1) == 0),
+ /* FIXME:XX hardcoded. */
+ "gfx.ndid": "3",
+ "gfx.did": "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }",
+ },
+ Children: []DevTreeNode{
+ {
+ Chip: "cpu_cluster",
+ Dev: 0,
+ Children: []DevTreeNode{
+ {
+ Chip: "cpu/intel/haswell",
+ Children: []DevTreeNode{
+ {
+ Chip: "lapic",
+ Dev: 0,
+ },
+ {
+ Chip: "lapic",
+ Dev: 0xacac,
+ Disabled: true,
+ },
+ },
+ Registers: map[string]string{
+ /* FIXME:XX hardcoded. */
+ "c1_acpower": "1",
+ "c2_acpower": "3",
+ "c3_acpower": "5",
+ "c1_battery": "1",
+ "c2_battery": "3",
+ "c3_battery": "5",
+ },
+ },
+ },
+ },
+
+ {
+ Chip: "domain",
+ Dev: 0,
+ PCIController: true,
+ ChildPCIBus: 0,
+ PCISlots: []PCISlot{
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x0, Func: 0}, writeEmpty: true, additionalComment: "Host bridge"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1, Func: 0}, writeEmpty: true, additionalComment: "PCIe Bridge for discrete graphics"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x2, Func: 0}, writeEmpty: true, additionalComment: "Internal graphics"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x3, Func: 0}, writeEmpty: true, additionalComment: "Mini-HD audio"},
+ },
+ },
+ },
+ }
+
+ PutPCIDev(addr, "Host bridge")
+
+ /* FIXME:XX some configs are unsupported. */
+
+ KconfigBool["CPU_INTEL_HASWELL"] = true
+ KconfigBool["NORTHBRIDGE_INTEL_HASWELL"] = true
+ KconfigBool["INTEL_INT15"] = true
+ KconfigBool["HAVE_ACPI_TABLES"] = true
+ KconfigBool["HAVE_ACPI_RESUME"] = true
+
+ KconfigInt["MAX_CPUS"] = 8
+
+ DSDTIncludes = append(DSDTIncludes, DSDTInclude{
+ File: "cpu/intel/common/acpi/cpu.asl",
+ })
+
+ DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{
+ File: "northbridge/intel/haswell/acpi/haswell.asl",
+ }, DSDTInclude{
+ File: "drivers/intel/gma/acpi/default_brightness_levels.asl",
+ })
+}
+
+func init() {
+ RegisterPCI(0x8086, 0x0c00, haswellmc{variant: "Desktop"})
+ RegisterPCI(0x8086, 0x0c04, haswellmc{variant: "Mobile"})
+ RegisterPCI(0x8086, 0x0a04, haswellmc{variant: "ULT"})
+ RegisterPCI(0x8086, 0x0c08, haswellmc{variant: "Server"})
+ for _, id := range []uint16{
+ 0x0402, 0x0412, 0x0422,
+ 0x0406, 0x0416, 0x0426,
+ 0x0d16, 0x0d26, 0x0d36,
+ 0x0a06, 0x0a16, 0x0a26,
+ } {
+ RegisterPCI(0x8086, id, GenericVGA{GenericPCI{Comment: "VGA controller"}})
+ }
+}
diff --git a/util/autoport/lynxpoint.go b/util/autoport/lynxpoint.go
new file mode 100644
index 0000000..df20c3f
--- /dev/null
+++ b/util/autoport/lynxpoint.go
@@ -0,0 +1,495 @@
+package main
+
+import (
+ "fmt"
+ "os"
+)
+
+type lynxpoint struct {
+ variant string
+ node *DevTreeNode
+}
+
+func (b lynxpoint) writeGPIOSet(ctx Context, sb *os.File,
+ val uint32, set uint, partno int, constraint uint32) {
+
+ max := uint(32)
+ if set == 3 {
+ max = 12
+ }
+
+ bits := [6][2]string{
+ {"GPIO_MODE_NATIVE", "GPIO_MODE_GPIO"},
+ {"GPIO_DIR_OUTPUT", "GPIO_DIR_INPUT"},
+ {"GPIO_LEVEL_LOW", "GPIO_LEVEL_HIGH"},
+ {"GPIO_RESET_PWROK", "GPIO_RESET_RSMRST"},
+ {"GPIO_NO_INVERT", "GPIO_INVERT"},
+ {"GPIO_NO_BLINK", "GPIO_BLINK"},
+ }
+
+ for i := uint(0); i < max; i++ {
+ if ((constraint>>i)&1 == 1) {
+ fmt.Fprintf(sb, " .gpio%d = %s,\n",
+ (set-1)*32+i,
+ bits[partno][(val>>i)&1])
+ }
+ }
+}
+
+func (b lynxpoint) GPIO(ctx Context, inteltool InteltoolData) {
+ var constraint uint32
+ gpio := Create(ctx, "gpio.c")
+ defer gpio.Close()
+
+ AddROMStageFile("gpio.c", "")
+
+ Add_gpl(gpio)
+ gpio.WriteString("#include <southbridge/intel/common/gpio.h>\n\n")
+
+ /* TODO: different in LP PCH */
+ addresses := [3][6]int{
+ {0x00, 0x04, 0x0c, 0x60, 0x2c, 0x18},
+ {0x30, 0x34, 0x38, 0x64, -1, -1},
+ {0x40, 0x44, 0x48, 0x68, -1, -1},
+ }
+
+ for set := 1; set <= 3; set++ {
+ for partno, part := range []string{"mode", "direction", "level", "reset", "invert", "blink"} {
+ addr := addresses[set-1][partno]
+ if addr < 0 {
+ continue
+ }
+ fmt.Fprintf(gpio, "static const struct pch_gpio_set%d pch_gpio_set%d_%s = {\n",
+ set, set, part)
+
+ constraint = 0xffffffff
+ switch part {
+ case "direction":
+ /* Ignored on native mode */
+ constraint = inteltool.GPIO[uint16(addresses[set-1][0])]
+ case "level":
+ /* Level doesn't matter for input */
+ constraint = inteltool.GPIO[uint16(addresses[set-1][0])]
+ constraint &^= inteltool.GPIO[uint16(addresses[set-1][1])]
+ case "reset":
+ /* Only show reset */
+ constraint = inteltool.GPIO[uint16(addresses[set-1][3])]
+ case "invert":
+ /* Only on input and only show inverted GPIO */
+ constraint = inteltool.GPIO[uint16(addresses[set-1][0])]
+ constraint &= inteltool.GPIO[uint16(addresses[set-1][1])]
+ constraint &= inteltool.GPIO[uint16(addresses[set-1][4])]
+ case "blink":
+ /* Only on output and only show blinking GPIO */
+ constraint = inteltool.GPIO[uint16(addresses[set-1][0])]
+ constraint &^= inteltool.GPIO[uint16(addresses[set-1][1])]
+ constraint &= inteltool.GPIO[uint16(addresses[set-1][5])]
+ }
+ b.writeGPIOSet(ctx, gpio, inteltool.GPIO[uint16(addr)], uint(set), partno, constraint)
+ gpio.WriteString("};\n\n")
+ }
+ }
+
+ gpio.WriteString(`const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
+`)
+}
+
+func (b lynxpoint) IsPCIeHotplug(ctx Context, port int) bool {
+ portDev, ok := PCIMap[PCIAddr{Bus: 0, Dev: 0x1c, Func: port}]
+ if !ok {
+ return false
+ }
+ return (portDev.ConfigDump[0xdb] & (1 << 6)) != 0
+}
+
+func (b lynxpoint) GetGPIOHeader() string {
+ return "southbridge/intel/lynxpoint/pch.h"
+}
+
+func (b lynxpoint) EnableGPE(in int) {
+ b.node.Registers[fmt.Sprintf("gpi%d_routing", in)] = "2"
+}
+
+func (b lynxpoint) EncodeGPE(in int) int {
+ return in + 0x10
+}
+
+func (b lynxpoint) DecodeGPE(in int) int {
+ return in - 0x10
+}
+
+func (b lynxpoint) NeedRouteGPIOManually() {
+ b.node.Comment += ", FIXME: set gpiX_routing for EC support"
+}
+
+func (b lynxpoint) Scan(ctx Context, addr PCIDevData) {
+
+ SouthBridge = &b
+
+ inteltool := ctx.InfoSource.GetInteltool()
+ b.GPIO(ctx, inteltool)
+
+ KconfigBool["SOUTHBRIDGE_INTEL_LYNXPOINT"] = true
+ if b.variant == "Lynx Point LP" {
+ KconfigBool["INTEL_LYNXPOINT_LP"] = true
+ }
+ KconfigBool["SERIRQ_CONTINUOUS_MODE"] = true
+ KconfigInt["USBDEBUG_HCD_INDEX"] = 2
+ KconfigComment["USBDEBUG_HCD_INDEX"] = "FIXME: check this"
+ dmi := ctx.InfoSource.GetDMI()
+ if dmi.Vendor == "LENOVO" {
+ KconfigInt["DRAM_RESET_GATE_GPIO"] = 10
+ } else {
+ KconfigInt["DRAM_RESET_GATE_GPIO"] = 60
+ }
+ KconfigComment["DRAM_RESET_GATE_GPIO"] = "FIXME: check this"
+
+ /* Not strictly speaking correct. These subsys/subvendor referer to PCI devices.
+ But most systems don't have any of those. But the config needs to be set
+ nevertheless. So set it to southbridge subsys/subvendor. */
+ KconfigHex["MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID"] = uint32(GetLE16(addr.ConfigDump[0x2c:0x2e]))
+ KconfigHex["MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID"] = uint32(GetLE16(addr.ConfigDump[0x2e:0x30]))
+
+ ich9GetFlashSize(ctx)
+
+ DSDTDefines = append(DSDTDefines,
+ DSDTDefine{
+ Key: "BRIGHTNESS_UP",
+ Value: "\\_SB.PCI0.GFX0.INCB",
+ },
+ DSDTDefine{
+ Key: "BRIGHTNESS_DOWN",
+ Value: "\\_SB.PCI0.GFX0.DECB",
+ },
+ DSDTDefine{
+ Key: "ACPI_VIDEO_DEVICE",
+ Value: "\\_SB.PCI0.GFX0",
+ })
+
+ /* SPI init */
+ MainboardIncludes = append(MainboardIncludes, "southbridge/intel/lynxpoint/pch.h")
+
+ cur := DevTreeNode{
+ Chip: "southbridge/intel/lynxpoint",
+ Comment: "Intel Series 8 Lynx Point PCH",
+
+ Registers: map[string]string{
+ "pirqa_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x60]),
+ "pirqb_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x61]),
+ "pirqc_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x62]),
+ "pirqd_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x63]),
+ "pirqe_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x68]),
+ "pirqf_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x69]),
+ "pirqg_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x6a]),
+ "pirqh_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x6b]),
+ "sata_ahci": "1",
+ "gen1_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x84:0x88]),
+ "gen2_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x88:0x8c]),
+ "gen3_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x8c:0x90]),
+ "gen4_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x90:0x94]),
+ "sata_port_map": fmt.Sprintf("0x%x", PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 2}].ConfigDump[0x92]&0x3f),
+ },
+ PCISlots: []PCISlot{
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x14, Func: 0}, writeEmpty: false, additionalComment: "USB 3.0 Controller"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 0}, writeEmpty: true, additionalComment: "Management Engine Interface 1"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 1}, writeEmpty: true, additionalComment: "Management Engine Interface 2"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 2}, writeEmpty: true, additionalComment: "Management Engine IDE-R"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 3}, writeEmpty: true, additionalComment: "Management Engine KT"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x19, Func: 0}, writeEmpty: true, additionalComment: "Intel Gigabit Ethernet"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1a, Func: 0}, writeEmpty: true, additionalComment: "USB2 EHCI #2"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1b, Func: 0}, writeEmpty: true, additionalComment: "High Definition Audio"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 0}, writeEmpty: true, additionalComment: "PCIe Port #1"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 1}, writeEmpty: true, additionalComment: "PCIe Port #2"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 2}, writeEmpty: true, additionalComment: "PCIe Port #3"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 3}, writeEmpty: true, additionalComment: "PCIe Port #4"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 4}, writeEmpty: true, additionalComment: "PCIe Port #5"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 5}, writeEmpty: true, additionalComment: "PCIe Port #6"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 6}, writeEmpty: true, additionalComment: "PCIe Port #7"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 7}, writeEmpty: true, additionalComment: "PCIe Port #8"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1d, Func: 0}, writeEmpty: true, additionalComment: "USB2 EHCI #1"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1e, Func: 0}, writeEmpty: true, additionalComment: "PCI bridge"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 0}, writeEmpty: true, additionalComment: "LPC bridge"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 2}, writeEmpty: true, additionalComment: "SATA Controller 1"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 3}, writeEmpty: true, additionalComment: "SMBus"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 5}, writeEmpty: true, additionalComment: "SATA Controller 2"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 6}, writeEmpty: true, additionalComment: "Thermal"},
+ },
+ }
+
+ b.node = &cur
+
+ PutPCIChip(addr, cur)
+ PutPCIDevParent(addr, "PCI-LPC bridge", "lpc")
+
+ DSDTIncludes = append(DSDTIncludes, DSDTInclude{
+ File: "southbridge/intel/lynxpoint/acpi/platform.asl",
+ })
+ DSDTIncludes = append(DSDTIncludes, DSDTInclude{
+ File: "southbridge/intel/lynxpoint/acpi/globalnvs.asl",
+ Comment: "global NVS and variables",
+ })
+ DSDTIncludes = append(DSDTIncludes, DSDTInclude{
+ File: "southbridge/intel/lynxpoint/acpi/sleepstates.asl",
+ })
+ DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{
+ File: "southbridge/intel/lynxpoint/acpi/pch.asl",
+ })
+
+ sb := Create(ctx, "romstage.c")
+ defer sb.Close()
+ Add_gpl(sb)
+ sb.WriteString(`#include <stdint.h>
+#include <cpu/intel/romstage.h>
+#include <cpu/intel/haswell/haswell.h>
+#include <northbridge/intel/haswell/haswell.h>
+#include <northbridge/intel/haswell/pei_data.h>
+#include <southbridge/intel/common/gpio.h>
+#include <southbridge/intel/lynxpoint/pch.h>
+
+static const struct rcba_config_instruction rcba_config[] = {
+`)
+ RestoreDIRRoute(sb, "D31IR", uint16(inteltool.RCBA[0x3140]))
+ RestoreDIRRoute(sb, "D29IR", uint16(inteltool.RCBA[0x3144]))
+ RestoreDIRRoute(sb, "D28IR", uint16(inteltool.RCBA[0x3146]))
+ RestoreDIRRoute(sb, "D27IR", uint16(inteltool.RCBA[0x3148]))
+ RestoreDIRRoute(sb, "D26IR", uint16(inteltool.RCBA[0x314c]))
+ RestoreDIRRoute(sb, "D25IR", uint16(inteltool.RCBA[0x3150]))
+ RestoreDIRRoute(sb, "D22IR", uint16(inteltool.RCBA[0x315c]))
+ RestoreDIRRoute(sb, "D20IR", uint16(inteltool.RCBA[0x3160]))
+
+ sb.WriteString(`
+ RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS),
+
+ RCBA_END_CONFIG,
+};`)
+
+ sb.WriteString(`
+
+void mainboard_config_superio(void)
+{
+}
+
+void mainboard_romstage_entry(unsigned long bist)
+{
+ struct pei_data pei_data = {
+ .pei_version = PEI_VERSION,
+ .mchbar = (uintptr_t)DEFAULT_MCHBAR,
+ .dmibar = (uintptr_t)DEFAULT_DMIBAR,
+ .epbar = DEFAULT_EPBAR,
+ .pciexbar = DEFAULT_PCIEXBAR,
+ .smbusbar = SMBUS_IO_BASE,
+ .wdbbar = 0x4000000,
+ .wdbsize = 0x1000,
+ .hpet_address = HPET_ADDR,
+ .rcba = (uintptr_t)DEFAULT_RCBA,
+ .pmbase = DEFAULT_PMBASE,
+ .gpiobase = DEFAULT_GPIOBASE,
+ .temp_mmio_base = 0xfed08000,
+ .system_type = 1, /* desktop/server, FIXME: check this */
+ .tseg_size = CONFIG_SMM_TSEG_SIZE,
+ .spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 }, /* FIXME: check this */
+ .ec_present = 0,
+ .dimm_channel0_disabled = 0, /* FIXME: leave channel 0 enabled */
+ .dimm_channel1_disabled = 0, /* FIXME: leave channel 1 enabled */
+ .max_ddr3_freq = 1600,
+ .usb2_ports = {
+ /* Length, Enable, OCn#, Location */
+`)
+
+ pdo1 := PCIMap[PCIAddr{Bus: 0, Dev: 0x1d, Func: 0}].ConfigDump[0x64]
+ ocmap1 := PCIMap[PCIAddr{Bus: 0, Dev: 0x1d, Func: 0}].ConfigDump[0x74:0x78]
+ pdo2 := PCIMap[PCIAddr{Bus: 0, Dev: 0x1a, Func: 0}].ConfigDump[0x64]
+ ocmap2 := PCIMap[PCIAddr{Bus: 0, Dev: 0x1a, Func: 0}].ConfigDump[0x74:0x78]
+
+ for port := uint(0); port < 14; port++ {
+ var port_oc int = -1
+ var port_pos string
+ var port_disable uint8
+
+ if port < 8 {
+ port_disable = (pdo1 >> port) & 1
+ for oc := 0; oc < 4; oc++ {
+ if ((ocmap1[oc] & (1 << port)) != 0) {
+ port_oc = oc
+ break
+ }
+ }
+ } else {
+ port_disable = (pdo2 >> (port - 8)) & 1
+ for oc := 0; oc < 4; oc++ {
+ if ((ocmap2[oc] & (1 << (port - 8))) != 0) {
+ port_oc = oc + 4
+ break
+ }
+ }
+ }
+ if port_disable == 1 {
+ port_pos = "USB_PORT_SKIP"
+ } else {
+ port_pos = "USB_PORT_BACK_PANEL"
+ }
+ if port_oc == -1 {
+ fmt.Fprintf(sb, " { 0x0040, %d, USB_OC_PIN_SKIP, %s },\n",
+ (port_disable ^ 1), port_pos)
+ } else {
+ fmt.Fprintf(sb, " { 0x0040, %d, %d, %s },\n",
+ (port_disable ^ 1), port_oc, port_pos)
+ }
+ }
+
+ sb.WriteString(` },
+ .usb3_ports = {
+`)
+
+ xpdo := PCIMap[PCIAddr{Bus: 0, Dev: 0x14, Func: 0}].ConfigDump[0xe8]
+ u3ocm := PCIMap[PCIAddr{Bus: 0, Dev: 0x14, Func: 0}].ConfigDump[0xc8:0xd0]
+
+ for port := uint(0); port < 6; port++ {
+ var port_oc int = -1
+ port_disable := (xpdo >> port) & 1
+ for oc := 0; oc < 8; oc++ {
+ if (u3ocm[oc] & (1 << port)) != 0 {
+ port_oc = oc
+ break
+ }
+ }
+ if port_oc == -1 {
+ fmt.Fprintf(sb, " { %d, USB_OC_PIN_SKIP },\n",
+ (port_disable ^ 1))
+ } else {
+ fmt.Fprintf(sb, " { %d, %d },\n",
+ (port_disable ^ 1), port_oc)
+ }
+ }
+
+ sb.WriteString(` },
+ };
+
+ struct romstage_params romstage_params = {
+ .pei_data = &pei_data,
+ .gpio_map = &mainboard_gpio_map,
+ .rcba_config = &rcba_config[0],
+ .bist = bist,
+ };
+
+ romstage_common(&romstage_params);
+}`)
+
+ gnvs := Create(ctx, "acpi_tables.c")
+ defer gnvs.Close()
+
+ Add_gpl(gnvs)
+ gnvs.WriteString(`#include <southbridge/intel/lynxpoint/nvs.h>
+
+/* FIXME: check this function. */
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+ /* Disable USB ports in S3 by default */
+ gnvs->s3u0 = 0;
+ gnvs->s3u1 = 0;
+
+ /* Disable USB ports in S5 by default */
+ gnvs->s5u0 = 0;
+ gnvs->s5u1 = 0;
+
+ // the lid is open by default.
+ gnvs->lids = 1;
+
+ gnvs->tcrt = 100;
+ gnvs->tpsv = 90;
+}
+`)
+
+}
+
+func init() {
+ for _, id := range []uint16 {
+ 0x8c41, 0x8c49, 0x8c4b, 0x8c4f,
+ } {
+ RegisterPCI(0x8086, uint16(id), lynxpoint{variant: "Lynx Point Mobile"})
+ }
+
+ for _, id := range []uint16 {
+ 0x8c42, 0x8c44, 0x8c46, 0x8c4a,
+ 0x8c4c, 0x8c4e, 0x8c50, 0x8c5c,
+ } {
+ RegisterPCI(0x8086, uint16(id), lynxpoint{variant: "Lynx Point Desktop"})
+ }
+
+ for _, id := range []uint16 {
+ 0x8c52, 0x8c54, 0x8c56,
+ } {
+ RegisterPCI(0x8086, uint16(id), lynxpoint{variant: "Lynx Point Server"})
+ }
+
+ for _, id := range []uint16 {
+ 0x9c41, 0x9c43, 0x9c45,
+ } {
+ RegisterPCI(0x8086, uint16(id), lynxpoint{variant: "Lynx Point LP"})
+ }
+
+ /* PCIe bridge */
+ for _, id := range []uint16{
+ 0x8c10, 0x8c12, 0x8c14, 0x8c16, 0x8c18, 0x8c1a, 0x8c1c, 0x8c1e,
+ 0x9c10, 0x9c12, 0x9c14, 0x9c16, 0x9c18, 0x9c1a,
+ } {
+ RegisterPCI(0x8086, id, GenericPCI{})
+ }
+
+ /* SMBus controller */
+ RegisterPCI(0x8086, 0x1c22, GenericPCI{MissingParent: "smbus"})
+ RegisterPCI(0x8086, 0x1e22, GenericPCI{MissingParent: "smbus"})
+ RegisterPCI(0x8086, 0x8c22, GenericPCI{MissingParent: "smbus"})
+ RegisterPCI(0x8086, 0x9c22, GenericPCI{MissingParent: "smbus"})
+
+ /* SATA */
+ for _, id := range []uint16{
+ 0x8c00, 0x8c02, 0x8c04, 0x8c06, 0x8c08, 0x8c0e,
+ 0x8c01, 0x8c03, 0x8c05, 0x8c07, 0x8c09, 0x8c0f,
+ 0x9c03, 0x9c05, 0x9c07, 0x9c0f,
+ } {
+ RegisterPCI(0x8086, id, GenericPCI{})
+ }
+
+ /* EHCI */
+ for _, id := range []uint16{
+ 0x9c26, 0x8c26, 0x8c2d,
+ } {
+ RegisterPCI(0x8086, id, GenericPCI{})
+ }
+
+ /* XHCI */
+ RegisterPCI(0x8086, 0x8c31, GenericPCI{})
+ RegisterPCI(0x8086, 0x9c31, GenericPCI{})
+
+ /* ME and children */
+ for _, id := range []uint16{
+ 0x8c3a, 0x8c3b,
+ } {
+ RegisterPCI(0x8086, id, GenericPCI{})
+ }
+
+ /* Ethernet */
+ RegisterPCI(0x8086, 0x8c33, GenericPCI{})
+}
diff --git a/util/autoport/main.go b/util/autoport/main.go
index 05a829b..c1920a7 100644
--- a/util/autoport/main.go
+++ b/util/autoport/main.go
@@ -236,6 +236,12 @@
pcidev.ConfigDump[addr])
}
+func RestoreDIRRoute(f *os.File, regname string, val uint16) {
+ fmt.Fprintf(f, " RCBA_SET_REG_16(%s, DIR_ROUTE(PIRQ%c, PIRQ%c, PIRQ%c, PIRQ%c)),\n",
+ regname, 'A' + (val & 7), 'A' + ((val >> 4) & 7),
+ 'A' + ((val >> 8) & 7), 'A' + ((val >> 12) & 7))
+}
+
func RestorePCI32Simple(f *os.File, pcidev PCIDevData, addr uint16) {
fmt.Fprintf(f, " pci_write_config32(PCI_DEV(%d, 0x%02x, %d), 0x%02x, 0x%02x%02x%02x%02x);\n",
pcidev.Bus, pcidev.Dev, pcidev.Func, addr,
--
To view, visit https://review.coreboot.org/c/coreboot/+/30890
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I4f6e8c97b5122101de2f36bba8ba9f8ddd5b813a
Gerrit-Change-Number: 30890
Gerrit-PatchSet: 1
Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com>
Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com>
Gerrit-MessageType: newchange
1 month, 1 week
- 6
- 31