Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/29968
to look at the new patch set (#26).
Change subject: qcs405: Enable SPI-NOR
......................................................................
qcs405: Enable SPI-NOR
Enable support for Gigadevice spi-nor flash.
Change-Id: I340eb3bf77b25fe3502d4b29ef4bf7c06b282c02
Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org>
---
M src/mainboard/google/mistral/Kconfig
1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/29968/26
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Gerrit-Change-Id: I340eb3bf77b25fe3502d4b29ef4bf7c06b282c02
Gerrit-Change-Number: 29968
Gerrit-PatchSet: 26
Gerrit-Owner: Nitheesh Sekar <nsekar(a)codeaurora.org>
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Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/29957
to look at the new patch set (#25).
Change subject: libpayload: Add UART for qcs405
......................................................................
libpayload: Add UART for qcs405
TEST=build
Change-Id: I43164cf9eacc844af1d048f7b6ebbda96fc9d202
Signed-off-by: Prudhvi Yarlagadda <pyarlaga(a)codeaurora.org>
Signed-off-by: Sricharan R <sricharan(a)codeaurora.org>
Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org>
---
M payloads/libpayload/Kconfig
M payloads/libpayload/configs/config.mistral
M payloads/libpayload/drivers/Makefile.inc
A payloads/libpayload/drivers/serial/qcs405.c
4 files changed, 563 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/29957/25
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Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33136 )
Change subject: mb/up/squared: Remove unnecessary code
......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/#/c/33136/4/src/mainboard/up/squared/ramstage.c
File src/mainboard/up/squared/ramstage.c:
https://review.coreboot.org/#/c/33136/4/src/mainboard/up/squared/ramstage.c…
PS4, Line 57: silconfig->WriteProtectionEnable[0] = 0x1; // 0x0
I think we don't need WriteProtectionEnable/ReadProtectionEnable here and can do it in coreboot
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Gerrit-Change-Id: If7dae4f24a9fcb01d2d47063dd3a0f4ce6c120d2
Gerrit-Change-Number: 33136
Gerrit-PatchSet: 4
Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net>
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Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32935 )
Change subject: doc/mb/upsquared: Add documentation
......................................................................
Patch Set 7: Code-Review+1
(2 comments)
https://review.coreboot.org/#/c/32935/7/Documentation/soc/intel/apollolake/…
File Documentation/soc/intel/apollolake/index.md:
https://review.coreboot.org/#/c/32935/7/Documentation/soc/intel/apollolake/…
PS7, Line 3: ![][apl_flash_layout]
missing topic:
## SPI flash layout
https://review.coreboot.org/#/c/32935/7/Documentation/soc/intel/apollolake/…
PS7, Line 7: Usually on x86 platforms the bootblock is stored at the end of the bios region and the Intel ME / TXE has its own IFD region. On Apollolake both have been moved into the IFWI region, which is a subregion of "BIOS", since it allows to store multiple firmware components.
80 char limit per line
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