Hello Julius Werner, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/29970
to look at the new patch set (#27).
Change subject: QCS405: Added RPM support
......................................................................
QCS405: Added RPM support
This patch adds support to read RPM image from
3rdparty/blobs and load it. It takes RPM out of reset.
Note that, clock_reset_rpm function to touch the
GCC registers actually should reside in clock.c,
but for now keeping it here till clock patches
are posted.
Change-Id: I17f491f0a4bd0dce7522b7e80e1bac97ec18b945
Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org>
Signed-off-by: Sricharan R <sricharan(a)codeaurora.org>
---
M src/soc/qualcomm/qcs405/Makefile.inc
M src/soc/qualcomm/qcs405/include/soc/memlayout.ld
A src/soc/qualcomm/qcs405/include/soc/rpm.h
M src/soc/qualcomm/qcs405/include/soc/symbols.h
M src/soc/qualcomm/qcs405/mmu.c
A src/soc/qualcomm/qcs405/rpm_load_reset.c
M src/soc/qualcomm/qcs405/soc.c
7 files changed, 106 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/29970/27
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I17f491f0a4bd0dce7522b7e80e1bac97ec18b945
Gerrit-Change-Number: 29970
Gerrit-PatchSet: 27
Gerrit-Owner: Nitheesh Sekar <nsekar(a)codeaurora.org>
Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Nitheesh Sekar <nsekar(a)codeaurora.org>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-CC: Sricharan Ramabadhran <srichara(a)qualcomm.corp-partner.google.com>
Gerrit-MessageType: newpatchset
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/29958
to look at the new patch set (#26).
Change subject: qcs405: Combine BB with QC-Sec for ROM boot
......................................................................
qcs405: Combine BB with QC-Sec for ROM boot
TEST=build & run
Change-Id: I2428fd067c0216d9cf6a63e218d1792788317db0
Signed-off-by: Sricharan R <sricharan(a)codeaurora.org>
Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org>
---
M src/soc/qualcomm/qcs405/Makefile.inc
1 file changed, 25 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/29958/26
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Gerrit-Branch: master
Gerrit-Change-Id: I2428fd067c0216d9cf6a63e218d1792788317db0
Gerrit-Change-Number: 29958
Gerrit-PatchSet: 26
Gerrit-Owner: Nitheesh Sekar <nsekar(a)codeaurora.org>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Nitheesh Sekar <nsekar(a)codeaurora.org>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-MessageType: newpatchset
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33136 )
Change subject: mb/up/squared: Remove unnecessary code
......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/#/c/33136/4/src/mainboard/up/squared/ramstage.c
File src/mainboard/up/squared/ramstage.c:
https://review.coreboot.org/#/c/33136/4/src/mainboard/up/squared/ramstage.c…
PS4, Line 57: silconfig->WriteProtectionEnable[0] = 0x1; // 0x0
I think we don't need WriteProtectionEnable/ReadProtectionEnable here and can do it in coreboot
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Gerrit-Branch: master
Gerrit-Change-Id: If7dae4f24a9fcb01d2d47063dd3a0f4ce6c120d2
Gerrit-Change-Number: 33136
Gerrit-PatchSet: 4
Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net>
Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net>
Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Comment-Date: Sat, 01 Jun 2019 07:46:24 +0000
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Gerrit-MessageType: comment
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32935 )
Change subject: doc/mb/upsquared: Add documentation
......................................................................
Patch Set 7: Code-Review+1
(2 comments)
https://review.coreboot.org/#/c/32935/7/Documentation/soc/intel/apollolake/…
File Documentation/soc/intel/apollolake/index.md:
https://review.coreboot.org/#/c/32935/7/Documentation/soc/intel/apollolake/…
PS7, Line 3: ![][apl_flash_layout]
missing topic:
## SPI flash layout
https://review.coreboot.org/#/c/32935/7/Documentation/soc/intel/apollolake/…
PS7, Line 7: Usually on x86 platforms the bootblock is stored at the end of the bios region and the Intel ME / TXE has its own IFD region. On Apollolake both have been moved into the IFWI region, which is a subregion of "BIOS", since it allows to store multiple firmware components.
80 char limit per line
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Gerrit-Change-Id: Ic708ddbd2616eee4e5ec2740b3eac18b408bde38
Gerrit-Change-Number: 32935
Gerrit-PatchSet: 7
Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net>
Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net>
Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>
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Gerrit-Comment-Date: Sat, 01 Jun 2019 07:38:04 +0000
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