June 2019 - coreboot-gerrit - mail.coreboot.org

Change in ...coreboot[master]: qcs405: util/qualcomm: Add T32 debug scripts
by Patrick Georgi (Code Review) June 3, 2019

June 3, 2019

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29951 ) Change subject: qcs405: util/qualcomm: Add T32 debug scripts ...................................................................... qcs405: util/qualcomm: Add T32 debug scripts Add T32 scripts that allow debug of any coreboot stage on qcs405. Change-Id: I4e792a2806e5ebd3b4075c7bb69c43587920deae Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29951 Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- A util/qualcomm/scripts/cmm/clear_bss.cmm A util/qualcomm/scripts/cmm/debug_cb_405.cmm M util/qualcomm/scripts/cmm/debug_cb_common.cmm A util/qualcomm/scripts/cmm/pbl32_to_bootblock64_jump.cmm 4 files changed, 211 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved diff --git a/util/qualcomm/scripts/cmm/clear_bss.cmm b/util/qualcomm/scripts/cmm/clear_bss.cmm new file mode 100755 index 0000000..16eaac7 --- /dev/null +++ b/util/qualcomm/scripts/cmm/clear_bss.cmm @@ -0,0 +1,16 @@ +d.a 0x80000000 mov x0,#0x8c +d.a 0x80000004 lsl x0, x0, #0x14 +d.a 0x80000008 mov x1,#0x18 +d.a 0x8000000c lsl x1,x1, #0x10 +d.a 0x80000010 mov x2,#0x0 +d.a 0x80000014 mov x3,#0x80 +d.a 0x80000018 lsl x3, x3, #0x18 +d.a 0x8000001c add x3, x3, #0x14 +d.a 0x80000020 str x2,[x0] +d.a 0x80000024 sub x1, x1, #0x8 +d.a 0x80000028 add x0, x0, #0x8 +d.a 0x8000002c cmp x1,0x0 +d.a 0x80000030 b.ne 0x20 +d.a 0x80000034 b 0x34 +r.s pc 0x80000000 +go diff --git a/util/qualcomm/scripts/cmm/debug_cb_405.cmm b/util/qualcomm/scripts/cmm/debug_cb_405.cmm new file mode 100644 index 0000000..166d2aa --- /dev/null +++ b/util/qualcomm/scripts/cmm/debug_cb_405.cmm @@ -0,0 +1,165 @@ +;============================================================================ +;## +;## This file is part of the coreboot project. +;## +;## Copyright (C) 2018, The Linux Foundation. All rights reserved. +;## +;## This program is free software; you can redistribute it and/or modify +;## it under the terms of the GNU General Public License version 2 and +;## only version 2 as published by the Free Software Foundation. +;## +;## This program is distributed in the hope that it will be useful, +;## but WITHOUT ANY WARRANTY; without even the implied warranty of +;## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;## GNU General Public License for more details. +;## +;============================================================================ +; Name: +; debug_cb_405.cmm +; +; Description: +; Debug coreboot 405 front-end +;============================================================================ + +;============================================================================ +; CMM script variables +;============================================================================ + +LOCAL &TargetPkg + +GLOBAL &BBEntryAddr // Bootblock Entry +GLOBAL &BBExitAddr // Bootblock Exit to Xbl-Sec +GLOBAL &VEREntryAddr // Verstage Entry +GLOBAL &ROMEntryAddr // Romstage Entry +GLOBAL &QCLEntryAddr // QCLstage Entry +GLOBAL &RAMEntryAddr // Ramstage Entry +GLOBAL &BL31EntryAddr // BL31 Entry +GLOBAL &DCEntryAddr // Depthcharge Entry +GLOBAL &KernelEntryAddr // Kernel Entry + +GLOBAL &PreRamConsoleAddr +GLOBAL &RamConsoleAddr +GLOBAL &PreRamCbfsCache +GLOBAL &VBoot2Work +GLOBAL &Stack +GLOBAL &Ttb +GLOBAL &Timestamp +GLOBAL &CbmemTop +GLOBAL &PostRamCbfsCache + +GLOBAL &CBTablePtr + +GLOBAL &debug + +;============================================================================ + +;--------------------------------------------------- +; Entry point +;--------------------------------------------------- +ENTRY &ImageName + + // Later these can be parameterized + &TargetPkg="Qcs405Pkg" + + // These settings come from .../src/soc/qualcomm/qcs405/include/soc/memlayout.ld + &BBEntryAddr=0x8c2f000 + &VEREntryAddr=0x8C00000 + &ROMEntryAddr=0x8C00000 + &QCLEntryAddr=0x1485AC00 + &RAMEntryAddr=0x9F860000 + &BL31EntryAddr=0x06820000 + &DCEntryAddr=0xf1104800 + &KernelEntryAddr=0x90080000 + + &PreRamConsoleAddr=0x8C4F400 + &VBoot2Work=0x8C47000 + &Stack=0x8C4B000 + &Ttb=0x8C39000 + &Timestamp=0x8C4F000 + &PreRamCbfsCache=0x8C57400 + &CbmemTop=0x280000000 + &PostRamCbfsCache=0x9F800000 + // End of memlayout.ld settings + + // Common commands irrespective of &Mode + PATH + &CwDir=os.pwd() + PATH + &CwDir + + // position at top of coreboot tree + // find depth count for source loading + cd ..\..\..\.. + &srcpath=os.pwd() + + b.sel PROGRAM onchip + ;sys.u + + b.d /all + + ;go &BBEntryAddr + ;wait !run() + +;--------------------------------------------------- +; Setup area and log +;--------------------------------------------------- + area.clear + area.reset + area.create CB_Logs 1000. 8192. + area.select CB_Logs + + ;winclear + ;b.d /all + + if FILE.EXIST("C:\TEMP\WIN.CMM") + do C:\TEMP\WIN.CMM + + area.view CB_Logs + + PRINT %String "Source Path: &srcpath" + + symbol.sourcepath.setbasedir &srcpath\src + + PRINT "pbl32_to_bootblock64 jump" + do pbl32_to_bootblock64_jump.cmm + do clear_bss.cmm + WAIT 5s + b + + // Make parsing simple, upper-case parameters + &Imagename=STRING.UPR("&Imagename") + IF (STR.CP("&ImageName","DEBUG,*")) + ( + &debug="DEBUG" + ) + ELSE + ( + &debug="" + ) + &Imagename=STR.CUT("&ImageName",6) + IF "&debug"=="" + ( + PRINT "SPI_RAM LOAD" + &ImageName=STRING.UPR("&ImageName") + IF "&ImageName"=="" + ( + &ImageName="RAM,BB" //for RAM load Bootblock only and jump till DC + ) + PRINT "&ImageName" + ) + ELSE + ( + if (STR.CP("&debug","DEBUG")) + ( + PRINT "DEBUG" + &ImageName=STRING.UPR("&ImageName") + IF "&ImageName"=="" + ( + &ImageName="RAM,ALL" //for RAM loading all the images + ) + PRINT "&ImageName" + ) + ) + + DO debug_cb_common.cmm &TargetPkg &srcpath &xblsrcpath &ImageName + + enddo diff --git a/util/qualcomm/scripts/cmm/debug_cb_common.cmm b/util/qualcomm/scripts/cmm/debug_cb_common.cmm index bdb0097..5959ee1 100644 --- a/util/qualcomm/scripts/cmm/debug_cb_common.cmm +++ b/util/qualcomm/scripts/cmm/debug_cb_common.cmm @@ -104,6 +104,10 @@ if &BBStage ( + IF "&debug"=="" + ( + d.load.binary build/coreboot.rom 0xA0000000 + ) &imgpath="build\cbfs\fallback\bootblock.elf" if (&RAMLoad) d.load.elf &imgpath /strippart "coreboot" /sourcepath &srcpath @@ -114,9 +118,17 @@ ;b.s run_romstage /o ;d.set &PreRamConsoleAddr++0x8000 0 d.dump &PreRamConsoleAddr /spotlight - print %String "Now the control is in BootBlock, press enter after debugging to go to next stage" - print %String "Press enter to go to next stage" - enter + IF (STR.CP("&debug","DEBUG")) + ( + print %String "Now the control is in BootBlock, press enter after debugging to go to next stage" + print %String "Press enter to go to next stage" + enter + ) + ELSE + ( + go + enddo + ) ) go &VEREntryAddr diff --git a/util/qualcomm/scripts/cmm/pbl32_to_bootblock64_jump.cmm b/util/qualcomm/scripts/cmm/pbl32_to_bootblock64_jump.cmm new file mode 100644 index 0000000..bebf85d --- /dev/null +++ b/util/qualcomm/scripts/cmm/pbl32_to_bootblock64_jump.cmm @@ -0,0 +1,15 @@ +PER.Set.simple SPR:0x36100 %Long 00c5183C +D.S AZSD:0x8600034 %LE %Long 0x8600000 +D.S AZSD:0x8600000 %LE %Long 0x1400000 +d.a 0x8600004 ldr r0,0x8600034 +d.a 0x8600008 mcr p15,0x0,r0,c12,c0,1 +d.a 0x860000c dsb +d.a 0x8600010 isb +d.a 0x8600014 mrc p15,0x0,r1,c12,c0,2 +d.a 0x8600018 orr r1,r1,0x3 +d.a 0x860001c mcr p15,0x0,r1,c12,c0,2 +d.a 0x8600020 isb +d.a 0x8600024 wfi +r.s pc 0x8600004 +go +b -- To view, visit https://review.coreboot.org/c/coreboot/+/29951 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e792a2806e5ebd3b4075c7bb69c43587920deae Gerrit-Change-Number: 29951 Gerrit-PatchSet: 26 Gerrit-Owner: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Sricharan Ramabadhran <srichara(a)qualcomm.corp-partner.google.com> Gerrit-MessageType: merged

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Change in ...coreboot[master]: drivers/intel/fsp1_1: Exit cleanly if FSP not found
by Jacob Garber (Code Review) June 3, 2019

June 3, 2019

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33049 Change subject: drivers/intel/fsp1_1: Exit cleanly if FSP not found ...................................................................... drivers/intel/fsp1_1: Exit cleanly if FSP not found Instead of dereferencing a null pointer, print a nice message and exit cleanly if the FSP isn't found in the CBFS. Change-Id: I761e7febc7cec5bd2ef3af214bc51777ee5c313d Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> Found-by: Coverity CID 1401467 --- M src/drivers/intel/fsp1_1/car.c 1 file changed, 6 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/33049/1 diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c index 34b2518..194406b 100644 --- a/src/drivers/intel/fsp1_1/car.c +++ b/src/drivers/intel/fsp1_1/car.c @@ -159,19 +159,16 @@ { /* Need to locate the current FSP_INFO_HEADER. The cache-as-ram * is still enabled. We can directly access work buffer here. */ - FSP_INFO_HEADER *fih; struct prog fsp = PROG_INIT(PROG_REFCODE, "fsp.bin"); console_init(); - if (prog_locate(&fsp)) { - fih = NULL; - printk(BIOS_ERR, "Unable to locate %s\n", prog_name(&fsp)); - } else { - /* This leaks a mapping which this code assumes is benign as - * the flash is memory mapped CPU's address space. */ - fih = find_fsp((uintptr_t)rdev_mmap_full(prog_rdev(&fsp))); - } + if (prog_locate(&fsp)) + die_with_post_code(POST_INVALID_CBFS, "Unable to locate fsp.bin"); + + /* This leaks a mapping which this code assumes is benign as + * the flash is memory mapped CPU's address space. */ + FSP_INFO_HEADER *fih = find_fsp((uintptr_t)rdev_mmap_full(prog_rdev(&fsp))); cache_as_ram_stage_main(fih); -- To view, visit https://review.coreboot.org/c/coreboot/+/33049 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I761e7febc7cec5bd2ef3af214bc51777ee5c313d Gerrit-Change-Number: 33049 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/sifive/hifive-unleashed: Check for errors in fixup_fdt
by Jacob Garber (Code Review) June 3, 2019

June 3, 2019

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33134 Change subject: mb/sifive/hifive-unleashed: Check for errors in fixup_fdt ...................................................................... mb/sifive/hifive-unleashed: Check for errors in fixup_fdt It is possible that cbfs_boot_map_with_leak() and malloc() could fail, so detect those conditions and print error messages if they do. Change-Id: I34951da0b73028c4c89446cb1779a72422997325 Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> Found-by: Coverity CID 1399147 --- M src/mainboard/sifive/hifive-unleashed/fixup_fdt.c 1 file changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/33134/1 diff --git a/src/mainboard/sifive/hifive-unleashed/fixup_fdt.c b/src/mainboard/sifive/hifive-unleashed/fixup_fdt.c index ea58e02..6c42fc8 100644 --- a/src/mainboard/sifive/hifive-unleashed/fixup_fdt.c +++ b/src/mainboard/sifive/hifive-unleashed/fixup_fdt.c @@ -86,6 +86,11 @@ /* load flat dt from cbfs */ fdt_rom = cbfs_boot_map_with_leak("fallback/DTB", CBFS_TYPE_RAW, NULL); + if (fdt_rom == NULL) { + printk(BIOS_ERR, "Unable to load fallback/DTB from CBFS\n"); + return; + } + /* Expand DT into a tree */ tree = fdt_unflatten(fdt_rom); @@ -95,6 +100,12 @@ /* convert the tree to a flat dt */ void *dt = malloc(dt_flat_size(tree)); + + if (dt == NULL) { + printk(BIOS_ERR, "Unable to allocate memory for flat device tree\n"); + return; + } + dt_flatten(tree, dt); /* update HLS */ -- To view, visit https://review.coreboot.org/c/coreboot/+/33134 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34951da0b73028c4c89446cb1779a72422997325 Gerrit-Change-Number: 33134 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

4 5

Change in ...coreboot[master]: mb/google/poppy/variants/nami: Add fallthrough comment
by Jacob Garber (Code Review) June 3, 2019

June 3, 2019

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33156 Change subject: mb/google/poppy/variants/nami: Add fallthrough comment ...................................................................... mb/google/poppy/variants/nami: Add fallthrough comment This fallthrough is intentional (see commit 2257a35862 - Perform PL2 setting for syndra), so add a comment to make that explicit. Change-Id: I57fe1e08f59aed12544cd2a71f1e0464f432f03b Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> Found-by: Coverity CID 1397063 --- M src/mainboard/google/poppy/variants/nami/mainboard.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/33156/1 diff --git a/src/mainboard/google/poppy/variants/nami/mainboard.c b/src/mainboard/google/poppy/variants/nami/mainboard.c index cc87136..2387017 100644 --- a/src/mainboard/google/poppy/variants/nami/mainboard.c +++ b/src/mainboard/google/poppy/variants/nami/mainboard.c @@ -252,6 +252,7 @@ case SKU_6_SYNDRA: case SKU_7_SYNDRA: pl2_id = PL2_ID_SONA_SYNDRA; + /* fallthrough */ case SKU_0_VAYNE: case SKU_1_VAYNE: case SKU_2_VAYNE: -- To view, visit https://review.coreboot.org/c/coreboot/+/33156 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I57fe1e08f59aed12544cd2a71f1e0464f432f03b Gerrit-Change-Number: 33156 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

3 2

Change in ...coreboot[master]: mb/lenovo/*: Remove useless smihandler code
by Arthur Heymans (Code Review) June 3, 2019

June 3, 2019

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33138 Change subject: mb/lenovo/*: Remove useless smihandler code ...................................................................... mb/lenovo/*: Remove useless smihandler code This code to handle the brightness from SMM is copied from the Lenovo Thinkpad X60 code, but does not work on later generation. The PCI device it tries to address does not even exist on those devices. Change-Id: Ia959eb5b747846048396e66d4c926c96c27f3878 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/t420s/smihandler.c M src/mainboard/lenovo/t430s/smihandler.c M src/mainboard/lenovo/t520/smihandler.c M src/mainboard/lenovo/t530/smihandler.c M src/mainboard/lenovo/x220/smihandler.c 5 files changed, 0 insertions(+), 150 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/33138/1 diff --git a/src/mainboard/lenovo/t420s/smihandler.c b/src/mainboard/lenovo/t420s/smihandler.c index be4228d..2713725 100644 --- a/src/mainboard/lenovo/t420s/smihandler.c +++ b/src/mainboard/lenovo/t420s/smihandler.c @@ -27,23 +27,6 @@ #define GPE_EC_SCI 1 #define GPE_EC_WAKE 13 -static void mainboard_smi_brightness_up(void) -{ - u8 value; - - if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) < 0xf0) - pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, (value + 0x10) | 0xf); -} - -static void mainboard_smi_brightness_down(void) -{ - u8 value; - - if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) > 0x10) - pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, - (value - 0x10) & 0xf0); -} - static void mainboard_smi_handle_ec_sci(void) { u8 status = inb(EC_SC); @@ -54,19 +37,6 @@ event = ec_query(); printk(BIOS_DEBUG, "EC event %02x\n", event); - - switch (event) { - case 0x14: - /* brightness up */ - mainboard_smi_brightness_up(); - break; - case 0x15: - /* brightness down */ - mainboard_smi_brightness_down(); - break; - default: - break; - } } void mainboard_smi_gpi(u32 gpi_sts) diff --git a/src/mainboard/lenovo/t430s/smihandler.c b/src/mainboard/lenovo/t430s/smihandler.c index 876d81c..2810e5a 100644 --- a/src/mainboard/lenovo/t430s/smihandler.c +++ b/src/mainboard/lenovo/t430s/smihandler.c @@ -27,23 +27,6 @@ #define GPE_EC_SCI 1 #define GPE_EC_WAKE 13 -static void mainboard_smi_brightness_up(void) -{ - u8 value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4); - - if (value < 0xf0) - pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, (value + 0x10) | 0xf); -} - -static void mainboard_smi_brightness_down(void) -{ - u8 value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4); - - if (value > 0x10) - pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, - (value - 0x10) & 0xf0); -} - static void mainboard_smi_handle_ec_sci(void) { u8 status = inb(EC_SC); @@ -54,19 +37,6 @@ event = ec_query(); printk(BIOS_DEBUG, "EC event %02x\n", event); - - switch (event) { - case 0x14: - /* brightness up */ - mainboard_smi_brightness_up(); - break; - case 0x15: - /* brightness down */ - mainboard_smi_brightness_down(); - break; - default: - break; - } } void mainboard_smi_gpi(u32 gpi_sts) diff --git a/src/mainboard/lenovo/t520/smihandler.c b/src/mainboard/lenovo/t520/smihandler.c index 88ce504..46ad664 100644 --- a/src/mainboard/lenovo/t520/smihandler.c +++ b/src/mainboard/lenovo/t520/smihandler.c @@ -27,23 +27,6 @@ #define GPE_EC_SCI 1 #define GPE_EC_WAKE 13 -static void mainboard_smi_brightness_up(void) -{ - u8 value; - - if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) < 0xf0) - pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, (value + 0x10) | 0xf); -} - -static void mainboard_smi_brightness_down(void) -{ - u8 value; - - if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) > 0x10) - pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, - (value - 0x10) & 0xf0); -} - static void mainboard_smi_handle_ec_sci(void) { u8 status = inb(EC_SC); @@ -54,19 +37,6 @@ event = ec_query(); printk(BIOS_DEBUG, "EC event %02x\n", event); - - switch (event) { - case 0x14: - /* brightness up */ - mainboard_smi_brightness_up(); - break; - case 0x15: - /* brightness down */ - mainboard_smi_brightness_down(); - break; - default: - break; - } } void mainboard_smi_gpi(u32 gpi_sts) diff --git a/src/mainboard/lenovo/t530/smihandler.c b/src/mainboard/lenovo/t530/smihandler.c index bf0f81f..46ad664 100644 --- a/src/mainboard/lenovo/t530/smihandler.c +++ b/src/mainboard/lenovo/t530/smihandler.c @@ -27,23 +27,6 @@ #define GPE_EC_SCI 1 #define GPE_EC_WAKE 13 -static void mainboard_smi_brightness_up(void) -{ - u8 value; - - if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) < 0xf0) - pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, (value + 0x10) | 0xf); -} - -static void mainboard_smi_brightness_down(void) -{ - u8 value; - - if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) > 0x10) - pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, - (value - 0x10) & 0xf0); -} - static void mainboard_smi_handle_ec_sci(void) { u8 status = inb(EC_SC); @@ -54,19 +37,6 @@ event = ec_query(); printk(BIOS_DEBUG, "EC event %02x\n", event); - - switch (event) { - case 0x14: - /* brightness up */ - mainboard_smi_brightness_up(); - break; - case 0x15: - /* brightness down */ - mainboard_smi_brightness_down(); - break; - default: - break; - } } void mainboard_smi_gpi(u32 gpi_sts) diff --git a/src/mainboard/lenovo/x220/smihandler.c b/src/mainboard/lenovo/x220/smihandler.c index bf0f81f..46ad664 100644 --- a/src/mainboard/lenovo/x220/smihandler.c +++ b/src/mainboard/lenovo/x220/smihandler.c @@ -27,23 +27,6 @@ #define GPE_EC_SCI 1 #define GPE_EC_WAKE 13 -static void mainboard_smi_brightness_up(void) -{ - u8 value; - - if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) < 0xf0) - pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, (value + 0x10) | 0xf); -} - -static void mainboard_smi_brightness_down(void) -{ - u8 value; - - if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) > 0x10) - pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, - (value - 0x10) & 0xf0); -} - static void mainboard_smi_handle_ec_sci(void) { u8 status = inb(EC_SC); @@ -54,19 +37,6 @@ event = ec_query(); printk(BIOS_DEBUG, "EC event %02x\n", event); - - switch (event) { - case 0x14: - /* brightness up */ - mainboard_smi_brightness_up(); - break; - case 0x15: - /* brightness down */ - mainboard_smi_brightness_down(); - break; - default: - break; - } } void mainboard_smi_gpi(u32 gpi_sts) -- To view, visit https://review.coreboot.org/c/coreboot/+/33138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia959eb5b747846048396e66d4c926c96c27f3878 Gerrit-Change-Number: 33138 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: ec/lenovo/h8: Fix method name in ACPI code
by Evgeny Zinoviev (Code Review) June 3, 2019

June 3, 2019

Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33100 Change subject: ec/lenovo/h8: Fix method name in ACPI code ...................................................................... ec/lenovo/h8: Fix method name in ACPI code Fix a typo. Change-Id: I2ab624eccd9bad36908df7fd739828e9ed8a4f62 Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- M src/ec/lenovo/h8/acpi/lid.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/33100/1 diff --git a/src/ec/lenovo/h8/acpi/lid.asl b/src/ec/lenovo/h8/acpi/lid.asl index a8e17cb..c9142f5 100644 --- a/src/ec/lenovo/h8/acpi/lid.asl +++ b/src/ec/lenovo/h8/acpi/lid.asl @@ -28,7 +28,7 @@ { Name(_HID, "PNP0C0D") - Method(_LId, 0, NotSerialized) + Method(_LID, 0, NotSerialized) { return (LIDS) } -- To view, visit https://review.coreboot.org/c/coreboot/+/33100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ab624eccd9bad36908df7fd739828e9ed8a4f62 Gerrit-Change-Number: 33100 Gerrit-PatchSet: 1 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-MessageType: newchange

3 2

Change in ...coreboot[master]: mb/google/link: Remove Link's own native graphics init
by Nico Huber (Code Review) June 3, 2019

June 3, 2019

Hello Julius Werner, Angel Pons, Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/33128 to review the following change. Change subject: mb/google/link: Remove Link's own native graphics init ...................................................................... mb/google/link: Remove Link's own native graphics init The code was already orphaned since its hook-up was removed with a6be58fece (nb/intel/sandybridge: Remove the C native graphic init). Change-Id: Ia554c457e2f3a2dc42965ac5cded0be8e82311fb Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/mainboard/google/link/Kconfig M src/mainboard/google/link/Makefile.inc D src/mainboard/google/link/i915.c D src/mainboard/google/link/i915io.c D src/mainboard/google/link/i915io.h D src/mainboard/google/link/intel_dp.c 6 files changed, 0 insertions(+), 982 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/33128/1 diff --git a/src/mainboard/google/link/Kconfig b/src/mainboard/google/link/Kconfig index 3628f1d..6d62f64 100644 --- a/src/mainboard/google/link/Kconfig +++ b/src/mainboard/google/link/Kconfig @@ -14,8 +14,6 @@ select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 select SERIRQ_CONTINUOUS_MODE - select MAINBOARD_HAS_NATIVE_VGA_INIT - select HAVE_LINEAR_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT select MAINBOARD_HAS_LIBGFXINIT select HAVE_IFD_BIN select HAVE_ME_BIN diff --git a/src/mainboard/google/link/Makefile.inc b/src/mainboard/google/link/Makefile.inc index 281ce32..89bb365 100644 --- a/src/mainboard/google/link/Makefile.inc +++ b/src/mainboard/google/link/Makefile.inc @@ -17,9 +17,6 @@ romstage-y += chromeos.c ramstage-y += chromeos.c -ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += i915.c -ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += i915io.c -ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += intel_dp.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c diff --git a/src/mainboard/google/link/i915.c b/src/mainboard/google/link/i915.c deleted file mode 100644 index 12d424c..0000000 --- a/src/mainboard/google/link/i915.c +++ /dev/null @@ -1,374 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <types.h> -#include <string.h> -#include <stdlib.h> -#include <device/device.h> -#include <device/pci_def.h> -#include <device/pci_ops.h> -#include <console/console.h> -#include <delay.h> -#include <arch/acpi.h> -#include <arch/io.h> -#include <arch/interrupt.h> -#include <boot/coreboot_tables.h> -#include <southbridge/intel/bd82x6x/pch.h> -#include <northbridge/intel/sandybridge/gma.h> -#include <device/pci.h> -#include <ec/google/chromeec/ec.h> -#include <cpu/x86/tsc.h> -#include <cpu/x86/cache.h> -#include <cpu/x86/mtrr.h> -#include <cpu/x86/msr.h> -#include <edid.h> - -#include "ec.h" -#include "onboard.h" -#include "i915io.h" - -enum { - vmsg = 1, vio = 2, vspin = 4, -}; - -static int verbose = 0; - -static unsigned int *mmio; -static unsigned int graphics; -static unsigned short addrport; -static unsigned short dataport; -static unsigned int physbase; -static u32 htotal, hblank, hsync, vtotal, vblank, vsync; - -const u32 link_edid_data[] = { - 0xffffff00, 0x00ffffff, 0x0379e430, 0x00000000, - 0x04011500, 0x96121ba5, 0xa2d54f02, 0x26935259, - 0x00545017, 0x01010000, 0x01010101, 0x01010101, - 0x01010101, 0x6f6d0101, 0xa4a0a000, 0x20306031, - 0xb510003a, 0x19000010, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x4c00fe00, - 0x69442047, 0x616c7073, 0x20200a79, 0xfe000000, - 0x31504c00, 0x45513932, 0x50532d31, 0x24003141, -}; - -#define READ32(addr) io_i915_READ32(addr) -#define WRITE32(val, addr) io_i915_WRITE32(val, addr) - -static char *regname(unsigned long addr) -{ - static char name[16]; - snprintf(name, sizeof(name), "0x%lx", addr); - return name; -} - -unsigned long io_i915_READ32(unsigned long addr) -{ - unsigned long val; - outl(addr, addrport); - val = inl(dataport); - if (verbose & vio) - printk(BIOS_SPEW, "%s: Got %08lx\n", regname(addr), val); - return val; -} - -void io_i915_WRITE32(unsigned long val, unsigned long addr) -{ - if (verbose & vio) - printk(BIOS_SPEW, "%s: outl %08lx\n", regname(addr), val); - outl(addr, addrport); - outl(val, dataport); -} - - -/* - 2560 - 4 words per - 4 *p - 10240 - 4k bytes per page - 4096/p - 2.50 - 1700 lines - 1700 * p - 4250.00 - PTEs -*/ -static void -setgtt(int start, int end, unsigned long base, int inc) -{ - int i; - - for(i = start; i < end; i++){ - u32 word = base + i*inc; - WRITE32(word|1,(i*4)|1); - } -} - -static unsigned long tickspermicrosecond = 1795; -static unsigned long long globalstart; - -static unsigned long -microseconds(unsigned long long start, unsigned long long end) -{ - unsigned long ret; - ret = ((end - start)/tickspermicrosecond); - return ret; -} - -static unsigned long globalmicroseconds(void) -{ - return microseconds(globalstart, rdtscll()); -} - -extern struct iodef iodefs[]; -extern int niodefs; - -static int i915_init_done = 0; - -/* fill the palette. This runs when the P opcode is hit. */ -/* and, yes, it's needed for even 32 bits per pixel */ -static void palette(void) -{ - int i; - unsigned long color = 0; - - for(i = 0; i < 256; i++, color += 0x010101){ - io_i915_WRITE32(color, _LGC_PALETTE_A + (i << 2)); - } -} - -static unsigned long times[4096]; - -static int run(int index) -{ - int i, prev = 0; - struct iodef *id, *lastidread = NULL; - unsigned long u, t; - if (index >= niodefs) - return index; - /* state machine! */ - for(i = index, id = &iodefs[i]; id->op; i++, id++){ - switch (id->op) { - case M: - if (verbose & vmsg) printk(BIOS_SPEW, "%ld: %s\n", - globalmicroseconds(), id->msg); - break; - case P: - palette(); - break; - case R: - u = READ32(id->addr); - if (verbose & vio) - printk(BIOS_SPEW, "\texpect %08lx\n", id->data); - /* we're looking for something. */ - if (lastidread->addr == id->addr){ - /* they're going to be polling. - * just do it 1000 times - */ - for (t = 0; t < 1000 && id->data != u; t++){ - u = READ32(id->addr); - } - if (verbose & vspin) printk(BIOS_SPEW, - "%s: # loops %ld got %08lx want %08lx\n", - regname(id->addr), - t, u, id->data); - } - lastidread = id; - break; - case W: - WRITE32(id->data, id->addr); - if (id->addr == PCH_PP_CONTROL){ - if (verbose & vio) - printk(BIOS_SPEW, "PCH_PP_CONTROL\n"); - switch (id->data & 0xf) { - case 8: break; - case 7: break; - default: udelay(100000); - if (verbose & vio) - printk(BIOS_SPEW, "U %d\n", 100000); - } - } - break; - case V: - if (id->count < 8){ - prev = verbose; - verbose = id->count; - } else { - verbose = prev; - } - printk(BIOS_SPEW, "Change verbosity to %d\n", verbose); - break; - case I: - printk(BIOS_SPEW, "run: return %d\n", i+1); - return i+1; - break; - default: - printk(BIOS_SPEW, "BAD TABLE, opcode %d @ %d\n", id->op, i); - return -1; - } - if (id->udelay) - udelay(id->udelay); - if (i < ARRAY_SIZE(times)) - times[i] = globalmicroseconds(); - } - printk(BIOS_SPEW, "run: return %d\n", i); - return i+1; -} - -int i915lightup_sandy(const struct i915_gpu_controller_info *info, - u32 pphysbase, u16 piobase, u8 *pmmio, u32 pgfx) -{ - static struct edid edid; - const struct edid_mode *mode; - int edid_ok; - - int index; - u32 auxin[16], auxout[16]; - mmio = (void *)pmmio; - addrport = piobase; - dataport = addrport + 4; - physbase = pphysbase; - graphics = pgfx; - printk(BIOS_SPEW, "i915lightup: graphics %p mmio %p" - "addrport %04x physbase %08x\n", - (void *)graphics, mmio, addrport, physbase); - globalstart = rdtscll(); - - - edid_ok = decode_edid((unsigned char *)&link_edid_data, - sizeof(link_edid_data), &edid); - mode = &edid.mode; - printk(BIOS_SPEW, "decode edid returns %d\n", edid_ok); - edid.framebuffer_bits_per_pixel = 32; - - htotal = (mode->ha - 1) | ((mode->ha + mode->hbl - 1) << 16); - printk(BIOS_SPEW, "I915_WRITE(HTOTAL(pipe), %08x)\n", htotal); - - hblank = (mode->ha - 1) | ((mode->ha + mode->hbl - 1) << 16); - printk(BIOS_SPEW, "I915_WRITE(HBLANK(pipe),0x%08x)\n", hblank); - - hsync = (mode->ha + mode->hso - 1) | - ((mode->ha + mode->hso + mode->hspw - 1) << 16); - printk(BIOS_SPEW, "I915_WRITE(HSYNC(pipe),0x%08x)\n", hsync); - - vtotal = (mode->va - 1) | ((mode->va + mode->vbl - 1) << 16); - printk(BIOS_SPEW, "I915_WRITE(VTOTAL(pipe), %08x)\n", vtotal); - - vblank = (mode->va - 1) | ((mode->va + mode->vbl - 1) << 16); - printk(BIOS_SPEW, "I915_WRITE(VBLANK(pipe),0x%08x)\n", vblank); - - vsync = (mode->va + mode->vso - 1) | - ((mode->va + mode->vso + mode->vspw - 1) << 16); - printk(BIOS_SPEW, "I915_WRITE(VSYNC(pipe),0x%08x)\n", vsync); - - printk(BIOS_SPEW, "Table has %d elements\n", niodefs); - - index = run(0); - printk(BIOS_SPEW, "Run returns %d\n", index); - auxout[0] = 1 << 31 /* dp */|0x1 << 28/*R*/|DP_DPCD_REV << 8|0xe; - intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 4, auxin, 14); - auxout[0] = 0 << 31 /* i2c */|1 << 30|0x0 << 28/*W*/|0x0 << 8|0x0; - intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 3, auxin, 0); - index = run(index); - printk(BIOS_SPEW, "Run returns %d\n", index); - auxout[0] = 0 << 31 /* i2c */|0 << 30|0x0 << 28/*W*/|0x0 << 8|0x0; - intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 3, auxin, 0); - index = run(index); - printk(BIOS_SPEW, "Run returns %d\n", index); - auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_SET_POWER << 8|0x0; - auxout[1] = 0x01000000; - /* DP_SET_POWER_D0 | DP_PSR_SINK_INACTIVE */ - intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 5, auxin, 0); - index = run(index); - auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_LINK_BW_SET << 8|0x8; - auxout[1] = 0x0a840000; - /*(DP_LINK_BW_2_7 &0xa)|0x0000840a*/ - auxout[2] = 0x00000000; - auxout[3] = 0x01000000; - intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 13, auxin, 0); - index = run(index); - auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_TRAINING_PATTERN_SET << 8|0x0; - auxout[1] = 0x21000000; - /* DP_TRAINING_PATTERN_1 | DP_LINK_SCRAMBLING_DISABLE | - * DP_SYMBOL_ERROR_COUNT_BOTH |0x00000021*/ - intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 5, auxin, 0); - index = run(index); - auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_TRAINING_LANE0_SET << 8|0x3; - auxout[1] = 0x00000000; - /* DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0 |0x00000000*/ - intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 8, auxin, 0); - index = run(index); - auxout[0] = 1 << 31 /* dp */|0x1 << 28/*R*/|DP_LANE0_1_STATUS << 8|0x5; - intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 4, auxin, 5); - index = run(index); - auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_TRAINING_PATTERN_SET << 8|0x0; - auxout[1] = 0x22000000; - /* DP_TRAINING_PATTERN_2 | DP_LINK_SCRAMBLING_DISABLE | - * DP_SYMBOL_ERROR_COUNT_BOTH |0x00000022*/ - intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 5, auxin, 0); - index = run(index); - auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_TRAINING_LANE0_SET << 8|0x3; - auxout[1] = 0x00000000; - /* DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0 |0x00000000*/ - intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 8, auxin, 0); - index = run(index); - auxout[0] = 1 << 31 /* dp */|0x1 << 28/*R*/|DP_LANE0_1_STATUS << 8|0x5; - intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 4, auxin, 5); - index = run(index); - auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_TRAINING_PATTERN_SET << 8|0x0; - auxout[1] = 0x00000000; - /* DP_TRAINING_PATTERN_DISABLE | DP_LINK_QUAL_PATTERN_DISABLE | - * DP_SYMBOL_ERROR_COUNT_BOTH |0x00000000*/ - intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 5, auxin, 0); - index = run(index); - - if (index != niodefs) - printk(BIOS_ERR, "Left over IO work in i915_lightup" - " -- this is likely a table error. " - "Only %d of %d were done.\n", index, niodefs); - printk(BIOS_SPEW, "DONE startup\n"); - verbose = 0; - /* GTT is the Global Translation Table for the graphics pipeline. - * It is used to translate graphics addresses to physical - * memory addresses. As in the CPU, GTTs map 4K pages. - * There are 32 bits per pixel, or 4 bytes, - * which means 1024 pixels per page. - * There are 4250 GTTs on Link: - * 2650 (X) * 1700 (Y) pixels / 1024 pixels per page. - * The setgtt function adds a further bit of flexibility: - * it allows you to set a range (the first two parameters) to point - * to a physical address (third parameter);the physical address is - * incremented by a count (fourth parameter) for each GTT in the - * range. - * Why do it this way? For ultrafast startup, - * we can point all the GTT entries to point to one page, - * and set that page to 0s: - * memset(physbase, 0, 4096); - * setgtt(0, 4250, physbase, 0); - * this takes about 2 ms, and is a win because zeroing - * the page takes a up to 200 ms. We will be exploiting this - * trick in a later rev of this code. - * This call sets the GTT to point to a linear range of pages - * starting at physbase. - */ - setgtt(0, FRAME_BUFFER_PAGES, physbase, 4096); - printk(BIOS_SPEW, "memset %p to 0 for %d bytes\n", - (void *)graphics, FRAME_BUFFER_BYTES); - memset((void *)graphics, 0, FRAME_BUFFER_BYTES); - printk(BIOS_SPEW, "%ld microseconds\n", globalmicroseconds()); - set_vbe_mode_info_valid(&edid, (uintptr_t)graphics); - i915_init_done = 1; - return i915_init_done; -} diff --git a/src/mainboard/google/link/i915io.c b/src/mainboard/google/link/i915io.c deleted file mode 100644 index 5ebb42d..0000000 --- a/src/mainboard/google/link/i915io.c +++ /dev/null @@ -1,355 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <stdlib.h> -#include "i915io.h" - -struct iodef iodefs[] = { - {V, 0}, - {W, 1, "", PCH_GMBUS0, 0x00000000, 0}, - {R, 1, "", PP_ON_DELAYS, ( /* T2 */ 0x0 << 16) | ( /* T5 */ 0x0 << 0) | 0x00000000, 0}, - {R, 1, "", PP_OFF_DELAYS, ( /* T3 */ 0x0 << 16) | ( /* Tx */ 0x0 << 0) | 0x00000000, 0}, - {W, 1, "", PP_ON_DELAYS, ( /* T2 */ 0x190 << 16) | ( /* T5 */ 0x7d0 << 0) | 0x019007d0, 0}, - {W, 1, "", PP_OFF_DELAYS, ( /* T3 */ 0x15e << 16) | ( /* Tx */ 0x7d0 << 0) | 0x015e07d0, 0}, - {M, 1, "[drm:intel_detect_pch], Found PatherPoint PCH", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:i915_load_modeset_init], failed to find VBIOS tables", 0x0, 0xcf8e64, 0}, - {R, 50, "", FORCEWAKE_MT_ACK, 0x00000001, 10}, - {W, 1, "", FORCEWAKE_MT, 0x00010001, 0}, - {R, 1, "", FORCEWAKE_MT, 0x00010001, 0}, - {R, 1, "", FORCEWAKE_MT_ACK, 0x00000001, 0}, - {R, 1, "", 0x13805c, 0x40000000, 0}, - {R, 1, "", 0xa180, 0x84100020, 0}, - {W, 1, "", FORCEWAKE_MT, 0x00010000, 0}, - {R, 1, "", 0x120000, 0x00000000, 0}, - {M, 1, "[drm:intel_init_display], Using MT version of forcewake", 0x0, 0xcf8e64, 0}, - {R, 1, "", 0x145d10, 0x2010040c, 0}, - {M, 1, "[drm:intel_modeset_init], 3 display pipes available.", 0x0, 0xcf8e64, 0}, - {R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0}, - {W, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0}, - {R, 1, "", _PIPEBCONF, 0x00000000, 0}, - {W, 1, "", _PIPEBCONF, 0x00000000, 0}, - {R, 1, "", 0x72008, 0x00000000, 0}, - {W, 1, "", 0x72008, 0x00000000, 0}, - {R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0}, - {W, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0}, - {R, 1, "", _PIPEBCONF, 0x00000000, 0}, - {W, 1, "", _PIPEBCONF, 0x00000000, 0}, - {R, 1, "", 0x72008, 0x00000000, 0}, - {W, 1, "", 0x72008, 0x00000000, 0}, - {R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0}, - {W, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0}, - {R, 1, "", _PIPEBCONF, 0x00000000, 0}, - {W, 1, "", _PIPEBCONF, 0x00000000, 0}, - {R, 1, "", 0x72008, 0x00000000, 0}, - {W, 1, "", 0x72008, 0x00000000, 300}, - {W, 1, "", CPU_VGACNTRL, 0x80000000, 0}, - {R, 1, "", CPU_VGACNTRL, 0x80000000, 0}, - {R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000001c, 0}, - {R, 1, "", PCH_PP_ON_DELAYS, PANEL_PORT_SELECT_DPA | ( /* PANEL_POWER_UP_DELAY */ 0x7d0 << 16) | ( /* PANEL_LIGHT_ON_DELAY */ 0x7d0 << 0) | 0x47d007d0, 0}, - {R, 1, "", PCH_PP_OFF_DELAYS, ( /* PANEL_POWER_DOWN_DELAY */ 0x1f4 << 16) | ( /* PANEL_LIGHT_OFF_DELAY */ 0x7d0 << 0) | 0x01f407d0, 0}, - {R, 1, "", PCH_PP_DIVISOR, 0x00186906, 0}, - {M, 1, "[drm:intel_dp_init], cur t1_t3 2000 t8 2000 t9 2000 t10 500t11_t12 6000", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:intel_dp_init], vbt t1_t3 0 t8 0 t9 0 t10 0 t11_t12 0", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:intel_dp_init], panel power up delay 200,power down" "delay 50, power cycle delay 600", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:intel_dp_init], backlight on delay 200, off delay 200", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on", 0x0, 0xcf8e64, 0}, - {R, 1, "", PCH_PP_CONTROL, 0x00000000, 0}, - {R, 1, "", PCH_PP_STATUS, 0x00000000, 0}, - {M, 1, "[drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:ironlake_wait_panel_status], R PCH_PP_CONTROL:00000000", 0x0, 0xcf8e64, 0}, - {R, 2, "", PCH_PP_STATUS, 0x00000000, 0}, - {R, 1, "", PCH_PP_CONTROL, 0x00000000, 0}, - {W, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0}, - {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0}, - {M, 1, "[drm:ironlake_edp_panel_vdd_on], R PCH_PP_CONTROL:abcd0008", 0x0, 0xcf8e64, 0}, - {R, 2, "", PCH_PP_STATUS, 0x00000000, 0}, - {M, 1, "[drm:ironlake_edp_panel_vdd_on], eDP was not running", 0x0, 0xcf8e64, 0}, - {R, 1, "", PCH_PP_STATUS, 0x00000000, 0}, - {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0}, - {R, 1, "", PCH_PP_STATUS, 0x00000000, 0}, - {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0}, - {M, 1, "[drm:intel_dp_i2c_init], i2c_init DPDDC-A", 0x0, 0x00000000, 0}, - {R, 1, "", PCH_PP_STATUS, 0x00000000, 0}, - {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0}, - {R, 1, "", PCH_PP_STATUS, 0x00000000, 0}, - {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0}, - {R, 1, "", PCH_PP_STATUS, 0x00000000, 0}, - {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0}, - {R, 1, "", PCH_PP_STATUS, 0x00000000, 0}, - {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0}, - {I,}, - {M, 1, "[drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1", 0x0, 0x00000000, 0}, - {R, 1, "", BLC_PWM_CPU_CTL, 0x000010ce, 0}, - {M, 1, "[drm:intel_panel_get_backlight], get backlight PWM = 4302", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5145003f", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:intel_dp_i2c_aux_ch], aux_ch failed -110", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:ironlake_init_pch_refclk], has_panel 1 has_lvds 0 " "has_pch_edp 0has_cpu_edp 1 has_ck505 0", 0x0, 0xcf8e64, 0}, - {R, 1, "", PCH_DREF_CONTROL, 0x00000000, 0}, - {M, 1, "[drm:ironlake_init_pch_refclk], Using SSC on panel", 0x0, 0xcf8e64, 0}, - {W, 1, "", PCH_DREF_CONTROL, DREF_SSC_SOURCE_ENABLE | DREF_NONSPREAD_SOURCE_ENABLE | DREF_SSC1_ENABLE | 0x00001402, 0}, - {R, 1, "", PCH_DREF_CONTROL, DREF_SSC_SOURCE_ENABLE | DREF_NONSPREAD_SOURCE_ENABLE | DREF_SSC1_ENABLE | 0x00001402, 200}, - {M, 1, "[drm:ironlake_init_pch_refclk], Using SSC on eDP", 0x0, 0xcf8e64, 0}, - {W, 1, "", PCH_DREF_CONTROL, DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD | DREF_SSC_SOURCE_ENABLE | DREF_NONSPREAD_SOURCE_ENABLE | DREF_SSC1_ENABLE | 0x00005402, 0}, - {R, 1, "", PCH_DREF_CONTROL, DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD | DREF_SSC_SOURCE_ENABLE | DREF_NONSPREAD_SOURCE_ENABLE | DREF_SSC1_ENABLE | 0x00005402, 200}, - {W, 1, "", ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE | 0x10000000, 0}, - {W, 1, "", WM3_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0}, - {W, 1, "", WM2_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0}, - {W, 1, "", WM1_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0}, - {W, 1, "", 0x9404, 0x00002000, 0}, - {W, 1, "", ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE | 0x10000000, 0}, - {W, 1, "", IVB_CHICKEN3, 0x00000024, 0}, - {W, 1, "", GEN7_COMMON_SLICE_CHICKEN1, 0x04000400, 0}, - {W, 1, "", 0xb01c, 0x3c4fff8c, 0}, - {W, 1, "", GEN7_L3_CHICKEN_MODE_REGISTER, 0x20000000, 0}, - {R, 1, "", GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 0x00000000, 0}, - {W, 1, "", GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 0x00000800, 0}, - {R, 1, "", _DSPACNTR, ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | 0x00000000, 0}, - {W, 1, "", _DSPACNTR, ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0x00004000, 0}, - {R, 1, "", _DSPAADDR, 0x00000000, 0}, - {W, 1, "", _DSPAADDR, 0x00000000, 0}, - {R, 1, "", _DSPASIZE + 0xc, 0x00000000, 0}, - {W, 1, "", _DSPASIZE + 0xc, 0x00000000, 0}, - {R, 1, "", _DSPBCNTR, 0x00000000, 0}, - {W, 1, "", _DSPBCNTR, 0x00004000, 0}, - {R, 1, "", _DSPBADDR, 0x00000000, 0}, - {W, 1, "", _DSPBADDR, 0x00000000, 0}, - {R, 1, "", _DSPBSURF, 0x00000000, 0}, - {W, 1, "", _DSPBSURF, 0x00000000, 0}, - {R, 1, "", _DVSACNTR, 0x00000000, 0}, - {W, 1, "", _DVSACNTR, DVS_TRICKLE_FEED_DISABLE | 0x00004000, 0}, - {R, 1, "", _DVSALINOFF, 0x00000000, 0}, - {W, 1, "", _DVSALINOFF, 0x00000000, 0}, - {R, 1, "", _DVSASURF, 0x00000000, 0}, - {W, 1, "", _DVSASURF, 0x00000000, 0}, - {W, 1, "", SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE | 0x20000000, 0}, - {R, 1, "", SOUTH_CHICKEN2, 0x00000000, 0}, - {W, 1, "", SOUTH_CHICKEN2, DPLS_EDP_PPS_FIX_DIS | 0x00000001, 0}, - {W, 1, "", _TRANSA_CHICKEN2, 0x80000000, 0}, - {W, 1, "", _TRANSB_CHICKEN2, TRANS_CHICKEN2_TIMING_OVERRIDE | 0x80000000, 0}, - {M, 1, "[drm:drm_edid_to_eld], ELD:no CEA Extension found", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:drm_helper_probe_single_connector_modes], " "[CONNECTOR:6:eDP-1]probed modes :", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:drm_mode_debug_printmodeline],Modeline 0:\"2560x1700\" " "60 285250 2560 2608 2640 2720 1700 1703 1713 17490x48 0xa", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:drm_setup_crtcs], ", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:drm_enable_connectors], connector 6 enabled? yes", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:drm_setup_crtcs], picking CRTCs for 8192x8192 config", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:drm_setup_crtcs], desired mode 2560x1700 set on crtc 3", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:6:eDP-1]", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:intel_dp_detect], DPCD:110a8441000001c0", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:intel_dp_detect], DPCD:110a8441000001c0", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:drm_enable_connectors], connector 6 enabled? yes", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:intel_get_load_detect_pipe], [CONNECTOR:6:eDP-1],[ENCODER:7:TMDS-7]", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:intel_dp_mode_fixup], Display port link bw 0a lane count 4clock 270000", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:drm_crtc_helper_set_mode], [CRTC:3]", 0x0, 0xcf8e64, 0}, - {R, 1, "", PCH_PP_STATUS, 0x00000000, 0}, - {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0}, - {R, 1, "", PCH_PP_STATUS, 0x00000000, 0}, - {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0}, - {I,}, - {R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000001c, 0}, - {M, 1, "[drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1", 0x0, 0xcf8e64, 0}, - {R, 2, "", PCH_DP_D, 0x00000004, 0}, - {R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0}, - {W, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_TYPE_SP | 0x00000040, 0}, - {R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_TYPE_SP | 0x00000040, 0}, - {M, 1, "[drm:ironlake_crtc_mode_set], Mode for pipe 0:", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:drm_mode_debug_printmodeline],Modeline 0:\"2560x1700\" " "60 285250 2560 2608 2640 2720 1700 1703 1713 1749 0x48 0xa", 0x0, 0xcf8e64, 0}, - {W, 1, "", _TRANSA_DATA_M1, 0x00000000, 0}, - {W, 1, "", _TRANSA_DATA_N1, 0x00000000, 0}, - {W, 1, "", _TRANSA_DP_LINK_M1, 0x00000000, 0}, - {W, 1, "", _TRANSA_DP_LINK_N1, 0x00000000, 0}, - {W, 1, "", _PCH_FPA1, 0x00020e08, 0}, - {W, 1, "", _VSYNCSHIFT_A, 0x00000000, 0}, - {W, 1, "", _HTOTAL_A, 0x0a9f09ff, 0}, - {W, 1, "", _HBLANK_A, 0x0a9f09ff, 0}, - {W, 1, "", _HSYNC_A, 0x0a4f0a2f, 0}, - {W, 1, "", _VTOTAL_A, 0x06d406a3, 0}, - {W, 1, "", _VBLANK_A, 0x06d406a3, 0}, - {W, 1, "", _VSYNC_A, 0x06b006a6, 0}, - {W, 1, "", _PIPEASRC, 0x09ff06a3, 0}, - {W, 1, "", _PIPEA_DATA_M1, 0x7e4e58a4, 0}, - {W, 1, "", _PIPEA_DATA_N1, 0x0083d600, 0}, - {W, 1, "", _PIPEA_LINK_M1, 0x00045a42, 0}, - {W, 1, "", _PIPEA_LINK_N1, 0x00041eb0, 0}, - {M, 1, "[drm:ironlake_set_pll_edp], eDP PLL enable for clock 270000", 0x0, 0xcf8e64, 0}, - {R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000001c, 0}, - {W, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000001c, 0}, - {R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000001c, 500}, - {W, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP | 0x00000050, 0}, - {R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP | 0x00000050, 0}, - {R, 1, "", _PIPEASTAT, 0x00000000, 0}, - {W, 1, "", _PIPEASTAT, PIPE_VBLANK_INTERRUPT_STATUS | 0x00000002, 0}, - {R, 4562, "", _PIPEASTAT, 0x00000000, 0}, - {M, 1, "[drm:intel_wait_for_vblank], vblank wait timed out", 0x0, 0xcf8e64, 0}, - {W, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | 0x40000000, 0}, - {R, 2, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | 0x40000000, 0}, - {W, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | (DISPPLANE_BGRX888 & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0x58004000, 0}, - {M, 1, "[drm:ironlake_update_plane], Writing base 00000000 00000000 0 0 10240", 0x0, 0xcf8e64, 0}, - {W, 1, "", _DSPASTRIDE, 0x00002800, 0}, - {W, 1, "", _DSPASIZE + 0xc, 0x00000000, 0}, - {W, 1, "", _DSPACNTR + 0x24, 0x00000000, 0}, - {W, 1, "", _DSPAADDR, 0x00000000, 0}, - {R, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | (DISPPLANE_BGRX888 & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0x58004000, 0}, - {R, 1, "", 0x145d10, 0x2010040c, 0}, - {R, 1, "", WM0_PIPEA_ILK, 0x00783818, 0}, - {W, 1, "", WM0_PIPEA_ILK, 0x00183806, 0}, - {M, 1, "[drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 24,cursor:6", 0x0, 0xcf8e64, 0}, - {W, 1, "", WM3_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0}, - {W, 1, "", WM2_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0}, - {W, 1, "", WM1_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0}, - {R, 1, "", 0x145d10, 0x2010040c, 0}, - {M, 1, "[drm:ironlake_check_srwm], watermark 1:display plane 38, fbc lines 3,cursor 6", 0x0, 0xcf8e64, 0}, - {R, 1, "", 0x145d10, 0x2010040c, 0}, - {W, 1, "", WM1_LP_ILK, WMx_LP_SR_EN | ( /* WMx_LP_LATENCY */ 0x4 << 24) | ( /* WMx_LP_FBC */ 0x3 << 20) | ( /* WMx_LP_SR */ 0x26 << 8) | ( /* WMx_LP_CURSOR */ 0x6 << 0) | 0x84302606, 0}, - {R, 1, "", 0x145d10, 0x2010040c, 0}, - {M, 1, "[drm:ironlake_check_srwm], watermark 2:display plane 145, " "fbc lines 3,cursor 6", 0x0, 0xcf8e64, 0}, - {R, 1, "", 0x145d10, 0x2010040c, 0}, - {W, 1, "", WM2_LP_ILK, WMx_LP_SR_EN | ( /* WMx_LP_LATENCY */ 0x10 << 24) | ( /* WMx_LP_FBC */ 0x3 << 20) | ( /* WMx_LP_SR */ 0x91 << 8) | ( /* WMx_LP_CURSOR */ 0x6 << 0) | 0x90309106, 0}, - {R, 1, "", 0x145d10, 0x2010040c, 0}, - {M, 1, "[drm:ironlake_check_srwm], watermark 3:display plane " "288, fbc lines 4,cursor 10", 0x0, 0xcf8e64, 0}, - {R, 1, "", 0x145d10, 0x2010040c, 0}, - {W, 1, "", WM3_LP_ILK, WMx_LP_SR_EN | ( /* WMx_LP_LATENCY */ 0x20 << 24) | ( /* WMx_LP_FBC */ 0x4 << 20) | ( /* WMx_LP_SR */ 0x120 << 8) | ( /* WMx_LP_CURSOR */ 0xa << 0) | 0xa041200a, 0}, - {M, 1, "[drm:drm_crtc_helper_set_mode], [ENCODER:7:TMDS-7]set [MODE:0:2560x1700]", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:ironlake_edp_pll_on], ", 0x0, 0xcf8e64, 0}, - {R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000001c, 0}, - {W, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000401c, 0}, - {R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000401c, 200}, - {R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000401c, 0}, - {R, 1, "", 0x145d10, 0x2010040c, 0}, - {R, 1, "", WM0_PIPEA_ILK, 0x00183806, 0}, - {W, 1, "", WM0_PIPEA_ILK, 0x00183806, 0}, - {M, 1, "[drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 24,cursor:6", 0x0, 0xcf8e64, 0}, - {W, 1, "", WM3_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0}, - {W, 1, "", WM2_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0}, - {W, 1, "", WM1_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0}, - {R, 1, "", 0x145d10, 0x2010040c, 0}, - {M, 1, "[drm:ironlake_check_srwm], watermark 1:display plane 38, fbc lines 3,cursor 6", 0x0, 0xcf8e64, 0}, - {R, 1, "", 0x145d10, 0x2010040c, 0}, - {W, 1, "", WM1_LP_ILK, WMx_LP_SR_EN | ( /* WMx_LP_LATENCY */ 0x4 << 24) | ( /* WMx_LP_FBC */ 0x3 << 20) |( /* WMx_LP_SR */ 0x26 << 8) | ( /* WMx_LP_CURSOR */ 0x6 << 0) | 0x84302606, 0}, - {R, 1, "", 0x145d10, 0x2010040c, 0}, - {M, 1, "[drm:ironlake_check_srwm], watermark 2:display plane 145, " "fbc lines 3,cursor 6", 0x0, 0xcf8e64, 0}, - {R, 1, "", 0x145d10, 0x2010040c, 0}, - {W, 1, "", WM2_LP_ILK, WMx_LP_SR_EN | ( /* WMx_LP_LATENCY */ 0x10 << 24) | ( /* WMx_LP_FBC */ 0x3 << 20) |( /* WMx_LP_SR */ 0x91 << 8) | ( /* WMx_LP_CURSOR */ 0x6 << 0) | 0x90309106, 0}, - {R, 1, "", 0x145d10, 0x2010040c, 0}, - {M, 1, "[drm:ironlake_check_srwm], watermark 3:display plane 288, " "fbc lines 4,cursor 10", 0x0, 0xcf8e64, 0}, - {R, 1, "", 0x145d10, 0x2010040c, 0}, - {W, 1, "", WM3_LP_ILK, WMx_LP_SR_EN | ( /* WMx_LP_LATENCY */ 0x20 << 24) | ( /* WMx_LP_FBC */ 0x4 << 20) |( /* WMx_LP_SR */ 0x120 << 8) | ( /* WMx_LP_CURSOR */ 0xa << 0) | 0xa041200a, 0}, - {R, 1, "", _FDI_TXA_CTL, 0x00040000, 0}, - {W, 1, "", _FDI_TXA_CTL, 0x00040000, 0}, - {R, 1, "", _FDI_TXA_CTL, 0x00040000, 0}, - {R, 1, "", _FDI_RXA_CTL, 0x00000040, 0}, - {R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP | 0x00000050, 0}, - {W, 1, "", _FDI_RXA_CTL, 0x00020040, 0}, - {R, 1, "", _FDI_RXA_CTL, 0x00020040, 100}, - {R, 1, "", SOUTH_CHICKEN1, 0x00000000, 0}, - {W, 2, "", SOUTH_CHICKEN1, 0x00000000, 0}, - {R, 1, "", SOUTH_CHICKEN1, 0x00000000, 0}, - {R, 1, "", _FDI_TXA_CTL, 0x00040000, 0}, - {W, 1, "", _FDI_TXA_CTL, 0x00040000, 0}, - {R, 1, "", _FDI_RXA_CTL, 0x00020040, 0}, - {R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP | 0x00000050, 0}, - {W, 1, "", _FDI_RXA_CTL, 0x00020040, 0}, - {R, 1, "", _FDI_RXA_CTL, 0x00020040, 100}, - {P, 1, "Set Palette"}, - {R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP | 0x00000050, 0}, - {W, 1, "", _PIPEACONF, PIPECONF_ENABLE | ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP | 0x80000050, 0}, - {R, 1, "", _PIPEASTAT, 0x00000000, 0}, - {W, 1, "", _PIPEASTAT, PIPE_VBLANK_INTERRUPT_STATUS | 0x00000002, 0}, - {R, 4533, "", _PIPEASTAT, 0x00000000, 0}, - {M, 1, "[drm:intel_wait_for_vblank], vblank wait timed out", 0x0, 0xcf8e64, 0}, - {R, 1, "", _PIPEACONF, PIPECONF_ENABLE | PIPECONF_DOUBLE_WIDE | ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP |0xc0000050, 0}, - {R, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | (DISPPLANE_BGRX888 & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0x58004000, 0}, - {W, 1, "", _DSPACNTR, DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE | (DISPPLANE_BGRX888 & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0xd8004000, 0}, - {R, 1, "", _DSPAADDR, 0x00000000, 0}, - {W, 1, "", _DSPAADDR, 0x00000000, 0}, - {R, 1, "", _DSPASIZE + 0xc, 0x00000000, 0}, - {W, 1, "", _DSPASIZE + 0xc, 0x00000000, 0}, - {R, 1, "", _PIPEASTAT, 0x00000000, 0}, - {W, 1, "", _PIPEASTAT, PIPE_VBLANK_INTERRUPT_STATUS | 0x00000002, 0}, - {R, 4392, "", _PIPEASTAT, 0x00000000, 0}, - {M, 1, "[drm:intel_wait_for_vblank], vblank wait timed out", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on", 0x0, 0xcf8e64, 0}, - {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0}, - {M, 1, "[drm:ironlake_edp_panel_on], Turn eDP power on", 0x0, 0xcf8e64, 0}, - {R, 1, "", PCH_PP_STATUS, 0x00000000, 0}, - {M, 1, "[drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:ironlake_wait_panel_status], R PCH_PP_CONTROL:abcd0008", 0x0, 0xcf8e64, 0}, - {R, 2, "", PCH_PP_STATUS, 0x00000000, 0}, - {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0}, - {W, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd000b, 0}, - {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd000b, 0}, - {M, 1, "[drm:ironlake_wait_panel_on], Wait for panel power on", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:ironlake_wait_panel_status], R PCH_PP_CONTROL:abcd000b", 0x0, 0xcf8e64, 0}, - {R, 4, "", PCH_PP_STATUS, /*undocbit3 | undocbit1 | */ 0x0000000a, 0}, - {R, 16983, "", PCH_PP_STATUS, PP_ON | PP_SEQUENCE_POWER_UP | /*undocbit3 | undocbit1 | */ 0x9000000a, 0}, - {R, 17839, "", PCH_PP_STATUS, PP_ON | PP_SEQUENCE_POWER_UP | /*undocbit3 | undocbit0 | */ 0x90000009, 0}, - {R, 1, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0}, - {M, 1, "[drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1", 0x0, 0xcf8e64, 0}, - {R, 2, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd000b, 0}, - {W, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd0003, 0}, - {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd0003, 0}, - {M, 1, "[drm:ironlake_panel_vdd_off_sync], R PCH_PP_CONTROL:abcd0003", 0x0, 0xcf8e64, 0}, - {R, 1, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0}, - {W, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_2_CPT | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x8e1c4104, 0}, - {R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_2_CPT | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x8e1c4104, 0}, - {R, 2, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0}, - {R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_2_CPT | (DP_PRE_EMPHASIS_9_5 & 0xc00000) | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x8cdc4104, 0}, - {M, 1, "[drm:intel_dp_link_down], ", 0x0, 0xcf8e64, 0}, - {W, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_DETECTED | 0x8e1c0004, 0}, - {R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_DETECTED | 0x8e1c0004, 100}, - {W, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_IDLE_CPT | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_DETECTED | 0x8e1c0204, 0}, - {R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_IDLE_CPT | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_DETECTED | 0x8e1c0204, 0}, - {W, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | (DP_LINK_TRAIN_OFF_CPT & 0x300) | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_DETECTED | 0x0e1c0304, 0}, - {R, 2, "", DP_A, DP_LINK_TRAIN_PAT_1 | (DP_LINK_TRAIN_OFF_CPT & 0x300) | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_DETECTED | 0x0e1c0304, 0}, - {R, 2, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0}, - {I,}, - {W, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x891c4004, 0}, - {R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x891c4004, 0}, - {R, 2, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0}, - {I,}, - {R, 2, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0}, - {I,}, - {R, 2, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0}, - {I,}, - {M, 1, "[drm:intel_dp_start_link_train], clock recovery OK", 0x0, 0x00000000, 0}, - {W, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_2_CPT | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x891c4104, 0}, - {R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_2_CPT | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x891c4104, 0}, - {R, 2, "", PCH_PP_STATUS, PP_ON | /* undocbit3 | */ 0x80000008, 0}, - {I,}, - {R, 2, "", PCH_PP_STATUS, PP_ON | /* undocbit3 | */ 0x80000008, 0}, - {I,}, - {R, 2, "", PCH_PP_STATUS, PP_ON | /* undocbit3 | */ 0x80000008, 0}, - {I,}, - {W, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | (DP_LINK_TRAIN_OFF_CPT & 0x300) | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x891c4304, 0}, - {R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | (DP_LINK_TRAIN_OFF_CPT & 0x300) | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x891c4304, 0}, - {R, 2, "", PCH_PP_STATUS, PP_ON | /* undocbit3 | */ 0x80000008, 0}, - {I,}, - {M, 1, "[drm:ironlake_edp_backlight_on], ", 0x0, 0x00000000, 0}, - {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd0003, 0}, - {W, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_BLC_ENABLE | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd0007, 0}, - {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_BLC_ENABLE | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd0007, 0}, - {R, 1, "", _PIPEADSL, 0x00000633, 500}, - {R, 1, "", _PIPEADSL, 0x00000652, 0}, - {R, 1, "", _PIPEASTAT, 0x00000000, 0}, - {W, 1, "", _PIPEASTAT, PIPE_VBLANK_INTERRUPT_STATUS | 0x00000002, 0}, - {R, 5085, "", _PIPEASTAT, 0x00000000, 0}, - {M, 1, "[drm:intel_wait_for_vblank], vblank wait timed out", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:intel_dp_mode_fixup], Display port link bw 0a lane count 4clock 270000", 0x0, 0xcf8e64, 0}, - {M, 1, "[drm:drm_crtc_helper_set_mode], [CRTC:3]", 0x0, 0xcf8e64, 0}, - {I,}, -}; - -int niodefs = ARRAY_SIZE(iodefs); diff --git a/src/mainboard/google/link/i915io.h b/src/mainboard/google/link/i915io.h deleted file mode 100644 index c7663d4..0000000 --- a/src/mainboard/google/link/i915io.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <drivers/intel/gma/i915_reg.h> -#include <drivers/intel/gma/drm_dp_helper.h> - -/* things that are, strangely, not defined anywhere? */ -#define PCH_PP_UNLOCK 0xabcd0000 -#define WMx_LP_SR_EN (1 << 31) - -/* Google Link-specific defines */ -/* how many 4096-byte pages do we need for the framebuffer? - * There are 32 bits per pixel, or 4 bytes, - * which means 1024 pixels per page. - * HencetThere are 4250 GTTs on Link: - * 2650 (X) * 1700 (Y) pixels / 1024 pixels per page. - */ -#define FRAME_BUFFER_PAGES ((2560*1700)/1024) -#define FRAME_BUFFER_BYTES (FRAME_BUFFER_PAGES*4096) - -/* One-letter commands for code not meant to be ready for humans. - * The code was generated by a set of programs/scripts. - * M print out a kernel message - * R read a register. We do these mainly to ensure that if hardware wanted - * the register read, it was read; also, in debug, we can see what was expected - * and what was found. This has proven *very* useful to get this debugged. - * The udelay, if non-zero, will make sure there is a - * udelay() call with the value. - * The count is from the kernel and tells us how many times this read was done. - * Also useful for debugging and the state - * machine uses the info to drive a poll. - * W Write a register - * V set verbosity. It's a bit mask. - * 0 -> nothing - * 1 -> print kernel messages - * 2 -> print IO ops - * 4 -> print the number of times we spin on a register in a poll - * 8 -> restore whatever the previous verbosity level was - * (only one deep stack) - * - * Again, this is not really meant for human consumption. There is not a poll - * operator as such because, sometimes, there is a read/write/read where the - * second read is a poll, and this chipset is so touchy I'm reluctant to move - * things around and/or delete too many reads. - */ -#define M 1 -#define R 2 -#define W 4 -#define V 8 -#define I 16 -#define P 32 - -struct iodef { - unsigned char op; - unsigned int count; - const char *msg; - unsigned long addr; - unsigned long data; - unsigned long udelay; -}; - -/* i915.c */ -unsigned long io_i915_READ32(unsigned long addr); -void io_i915_WRITE32(unsigned long val, unsigned long addr); - -/* intel_dp.c */ -u32 pack_aux(u32 *src, int src_bytes); -void unpack_aux(u32 src, u32 *dst, int dst_bytes); -int intel_dp_aux_ch(u32 ch_ctl, u32 ch_data, u32 *send, int send_bytes, - u32 *recv, int recv_size); diff --git a/src/mainboard/google/link/intel_dp.c b/src/mainboard/google/link/intel_dp.c deleted file mode 100644 index f74743a..0000000 --- a/src/mainboard/google/link/intel_dp.c +++ /dev/null @@ -1,166 +0,0 @@ -/* - * Copyright 2013 Google Inc. - * Copyright © 2008 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - * - * Authors: - * Keith Packard <keithp(a)keithp.com> - * - */ - -#include <console/console.h> -#include <stdint.h> -#include <delay.h> -#include "i915io.h" - -u32 -pack_aux(u32 *src32, int src_bytes) -{ - u8 *src = (u8 *)src32; - int i; - u32 v = 0; - - if (src_bytes > 4) - src_bytes = 4; - for (i = 0; i < src_bytes; i++) - v |= ((u32) src[i]) << ((3-i) * 8); - return v; -} - -void -unpack_aux(u32 src, u32 *dst32, int dst_bytes) -{ - u8 *dst = (u8 *)dst32; - - int i; - if (dst_bytes > 4) - dst_bytes = 4; - for (i = 0; i < dst_bytes; i++) - dst[i] = src >> ((3-i) * 8); -} - -int -intel_dp_aux_ch(u32 ch_ctl, u32 ch_data, u32 *send, int send_bytes, - u32 *recv, int recv_size) -{ - int i; - int recv_bytes; - u32 status; - u32 aux_clock_divider; - int try, precharge = 5; - - /* The clock divider is based off the hrawclk, - * and would like to run at 2MHz. So, take the - * hrawclk value and divide by 2 and use that - * - * Note that PCH attached eDP panels should use a 125MHz input - * clock divider. - */ - /* 200 on link */ - aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */ - - /* Try to wait for any previous AUX channel activity */ - for (try = 0; try < 3; try++) { - status = io_i915_READ32(ch_ctl); - if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) - break; - udelay(1000); - } - - if (try == 3) { - printk(BIOS_SPEW, "[000000.0] [drm:%s], ", __func__); - printk(BIOS_SPEW, "dp_aux_ch not started status 0x%08lx\n", - io_i915_READ32(ch_ctl)); - return -1; - } - - /* Must try at least 3 times according to DP spec */ - for (try = 0; try < 5; try++) { - /* Load the send data into the aux channel data registers */ - for (i = 0; i < send_bytes; i += 4) - io_i915_WRITE32(send[i], ch_data + i); - - /* Send the command and wait for it to complete */ - io_i915_WRITE32( - DP_AUX_CH_CTL_SEND_BUSY | - DP_AUX_CH_CTL_TIME_OUT_400us | - (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | - (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | - (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) | - DP_AUX_CH_CTL_DONE | - DP_AUX_CH_CTL_TIME_OUT_ERROR | - DP_AUX_CH_CTL_RECEIVE_ERROR, ch_ctl); - for (;;) { - status = io_i915_READ32(ch_ctl); - if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) - break; - udelay(100); - } - - /* Clear done status and any errors */ - io_i915_WRITE32( - status | - DP_AUX_CH_CTL_DONE | - DP_AUX_CH_CTL_TIME_OUT_ERROR | - DP_AUX_CH_CTL_RECEIVE_ERROR, ch_ctl); - - if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR | - DP_AUX_CH_CTL_RECEIVE_ERROR)) - continue; - if (status & DP_AUX_CH_CTL_DONE) - break; - } - - if ((status & DP_AUX_CH_CTL_DONE) == 0) { - printk(BIOS_SPEW, "[000000.0] [drm:%s], ", __func__); - printk(BIOS_SPEW, "dp_aux_ch not done status 0x%08x\n", status); - return -1; - } - - /* Check for timeout or receive error. - * Timeouts occur when the sink is not connected - */ - if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { - printk(BIOS_SPEW, "[000000.0] [drm:%s], ", __func__); - printk(BIOS_SPEW, "dp_aux_ch receive error status 0x%08x\n", status); - return -1; - } - - /* Timeouts occur when the device isn't connected, so they're - * "normal" -- don't fill the kernel log with these */ - if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { - printk(BIOS_SPEW, "[000000.0] [drm:%s], ", __func__); - printk(BIOS_SPEW, "dp_aux_ch timeout status 0x%08x\n", status); - return -1; - } - - /* Unload any bytes sent back from the other side */ - recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> - DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); - if (recv_bytes > recv_size) - recv_bytes = recv_size; - - for (i = 0; i < recv_bytes; i += 4) - unpack_aux(io_i915_READ32(ch_data + i), - recv + i, recv_bytes - i); - - return recv_bytes; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/33128 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia554c457e2f3a2dc42965ac5cded0be8e82311fb Gerrit-Change-Number: 33128 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: nb/intel/haswell/gma: Drop NGI remnant
by Nico Huber (Code Review) June 3, 2019

June 3, 2019

Hello Julius Werner, Angel Pons, Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/33127 to review the following change. Change subject: nb/intel/haswell/gma: Drop NGI remnant ...................................................................... nb/intel/haswell/gma: Drop NGI remnant The native graphics init option was replaced with libgfxinit. Change-Id: I62569b70186b7b068effdadc4b39b3c09ddb7188 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/northbridge/intel/haswell/gma.c 1 file changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/33127/1 diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 607fab7..ca446e2 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -236,14 +236,6 @@ { gtt_write(HSW_PWR_WELL_CTL1, HSW_PWR_WELL_ENABLE); gtt_poll(HSW_PWR_WELL_CTL1, HSW_PWR_WELL_STATE, HSW_PWR_WELL_STATE); - - /* In the native graphics case, we've got about 20 ms. - * after we power up the AUX channel until we can talk to it. - * So get that going right now. We can't turn on the panel, yet, just VDD. - */ - if (CONFIG(MAINBOARD_DO_NATIVE_VGA_INIT)) { - gtt_write(PCH_PP_CONTROL, PCH_PP_UNLOCK| EDP_FORCE_VDD | PANEL_POWER_RESET); - } } static void gma_pm_init_pre_vbios(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/33127 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62569b70186b7b068effdadc4b39b3c09ddb7188 Gerrit-Change-Number: 33127 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: nb/intel/snb: Don't run VGA oprom when libgfxinit is enabled
by Nico Huber (Code Review) June 3, 2019

June 3, 2019

Hello Julius Werner, Angel Pons, Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/33126 to review the following change. Change subject: nb/intel/snb: Don't run VGA oprom when libgfxinit is enabled ...................................................................... nb/intel/snb: Don't run VGA oprom when libgfxinit is enabled This was likely an oversight when libgfxinit got its own Kconfig symbols. Change-Id: I647551719b332b5b734720ae4ee0619bbfcbed8c Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/northbridge/intel/sandybridge/gma.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/33126/1 diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index 1005288..19df8d4 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -626,7 +626,7 @@ /* Init graphics power management */ gma_pm_init_pre_vbios(dev); - if (!CONFIG(MAINBOARD_DO_NATIVE_VGA_INIT)) + if (!CONFIG(MAINBOARD_USE_LIBGFXINIT)) /* PCI Init, will run VBIOS */ pci_dev_init(dev); -- To view, visit https://review.coreboot.org/c/coreboot/+/33126 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I647551719b332b5b734720ae4ee0619bbfcbed8c Gerrit-Change-Number: 33126 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/common/mmc: Replace IS_ENABLED() with CONFIG()
by Nico Huber (Code Review) June 3, 2019

June 3, 2019

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33111 Change subject: soc/intel/common/mmc: Replace IS_ENABLED() with CONFIG() ...................................................................... soc/intel/common/mmc: Replace IS_ENABLED() with CONFIG() Change-Id: I99d51176f6d7d6a98a3a3c82aa8e8eee73344496 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/soc/intel/common/block/include/intelblocks/early_mmc.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/33111/1 diff --git a/src/soc/intel/common/block/include/intelblocks/early_mmc.h b/src/soc/intel/common/block/include/intelblocks/early_mmc.h index 69be40c..39aaf58 100644 --- a/src/soc/intel/common/block/include/intelblocks/early_mmc.h +++ b/src/soc/intel/common/block/include/intelblocks/early_mmc.h @@ -61,7 +61,7 @@ */ int soc_get_mmc_dll(struct mmc_dll_params *params); -#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_EARLY_MMC_WAKE) +#if CONFIG(SOC_INTEL_COMMON_EARLY_MMC_WAKE) /* * Initializes sdhci / mmc controller and sends CMD0, CMD1 to emmc card. * In case of success: It returns 0 and adds cbmem entry CBMEM_ID_MMC_STATUS -- To view, visit https://review.coreboot.org/c/coreboot/+/33111 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I99d51176f6d7d6a98a3a3c82aa8e8eee73344496 Gerrit-Change-Number: 33111 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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